1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1216 fprintf (dump_file
, "insn_cost %d: %d\n",
1217 INSN_UID (insn
), INSN_COST (insn
));
1221 nonzero_sign_valid
= 1;
1223 /* Now scan all the insns in forward order. */
1224 label_tick
= label_tick_ebb_start
= 1;
1226 setup_incoming_promotions (first
);
1227 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1228 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1230 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1232 rtx_insn
*last_combined_insn
= NULL
;
1233 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1238 if (!single_pred_p (this_basic_block
)
1239 || single_pred (this_basic_block
) != last_bb
)
1240 label_tick_ebb_start
= label_tick
;
1241 last_bb
= this_basic_block
;
1243 rtl_profile_for_bb (this_basic_block
);
1244 for (insn
= BB_HEAD (this_basic_block
);
1245 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1246 insn
= next
? next
: NEXT_INSN (insn
))
1249 if (!NONDEBUG_INSN_P (insn
))
1252 while (last_combined_insn
1253 && last_combined_insn
->deleted ())
1254 last_combined_insn
= PREV_INSN (last_combined_insn
);
1255 if (last_combined_insn
== NULL_RTX
1256 || BARRIER_P (last_combined_insn
)
1257 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1258 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1259 last_combined_insn
= insn
;
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1263 check_promoted_subreg (insn
, PATTERN (insn
));
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1268 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1270 /* Try this insn with each insn it links back to. */
1272 FOR_EACH_LOG_LINK (links
, insn
)
1273 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1274 NULL
, &new_direct_jump_p
,
1275 last_combined_insn
)) != 0)
1277 statistics_counter_event (cfun
, "two-insn combine", 1);
1281 /* Try each sequence of three linked insns ending with this one. */
1283 if (max_combine
>= 3)
1284 FOR_EACH_LOG_LINK (links
, insn
)
1286 rtx_insn
*link
= links
->insn
;
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 FOR_EACH_LOG_LINK (nextlinks
, link
)
1294 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1295 NULL
, &new_direct_jump_p
,
1296 last_combined_insn
)) != 0)
1298 statistics_counter_event (cfun
, "three-insn combine", 1);
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1312 && (prev
= prev_nonnote_insn (insn
)) != 0
1313 && NONJUMP_INSN_P (prev
)
1314 && sets_cc0_p (PATTERN (prev
)))
1316 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1318 last_combined_insn
)) != 0)
1321 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1322 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1323 NULL
, &new_direct_jump_p
,
1324 last_combined_insn
)) != 0)
1328 /* Do the same for an insn that explicitly references CC0. */
1329 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1330 && (prev
= prev_nonnote_insn (insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && GET_CODE (PATTERN (insn
)) == SET
1334 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1336 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1338 last_combined_insn
)) != 0)
1341 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1342 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1343 NULL
, &new_direct_jump_p
,
1344 last_combined_insn
)) != 0)
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1353 FOR_EACH_LOG_LINK (links
, insn
)
1354 if (NONJUMP_INSN_P (links
->insn
)
1355 && GET_CODE (PATTERN (links
->insn
)) == SET
1356 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1357 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1358 && NONJUMP_INSN_P (prev
)
1359 && sets_cc0_p (PATTERN (prev
))
1360 && (next
= try_combine (insn
, links
->insn
,
1361 prev
, NULL
, &new_direct_jump_p
,
1362 last_combined_insn
)) != 0)
1366 /* Try combining an insn with two different insns whose results it
1368 if (max_combine
>= 3)
1369 FOR_EACH_LOG_LINK (links
, insn
)
1370 for (nextlinks
= links
->next
; nextlinks
;
1371 nextlinks
= nextlinks
->next
)
1372 if ((next
= try_combine (insn
, links
->insn
,
1373 nextlinks
->insn
, NULL
,
1375 last_combined_insn
)) != 0)
1378 statistics_counter_event (cfun
, "three-insn combine", 1);
1382 /* Try four-instruction combinations. */
1383 if (max_combine
>= 4)
1384 FOR_EACH_LOG_LINK (links
, insn
)
1386 struct insn_link
*next1
;
1387 rtx_insn
*link
= links
->insn
;
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1394 FOR_EACH_LOG_LINK (next1
, link
)
1396 rtx_insn
*link1
= next1
->insn
;
1399 /* I0 -> I1 -> I2 -> I3. */
1400 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1401 if ((next
= try_combine (insn
, link
, link1
,
1404 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "four-insn combine", 1);
1409 /* I0, I1 -> I2, I2 -> I3. */
1410 for (nextlinks
= next1
->next
; nextlinks
;
1411 nextlinks
= nextlinks
->next
)
1412 if ((next
= try_combine (insn
, link
, link1
,
1415 last_combined_insn
)) != 0)
1417 statistics_counter_event (cfun
, "four-insn combine", 1);
1422 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I2; I1, I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0 -> I1; I1, I2 -> I3. */
1438 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1439 if ((next
= try_combine (insn
, link
, link1
,
1442 last_combined_insn
)) != 0)
1444 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1451 FOR_EACH_LOG_LINK (links
, insn
)
1454 rtx_insn
*temp
= links
->insn
;
1455 if ((set
= single_set (temp
)) != 0
1456 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1457 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1460 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1461 && (GET_MODE (note
) == VOIDmode
1462 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1463 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1464 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1465 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1466 == GET_MODE (note
))))))
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1471 rtx orig_src
= SET_SRC (set
);
1472 rtx orig_dest
= SET_DEST (set
);
1473 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1474 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1475 SET_SRC (set
) = note
;
1477 i2mod_old_rhs
= copy_rtx (orig_src
);
1478 i2mod_new_rhs
= copy_rtx (note
);
1479 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1481 last_combined_insn
);
1485 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1488 SET_SRC (set
) = orig_src
;
1489 SET_DEST (set
) = orig_dest
;
1494 record_dead_and_set_regs (insn
);
1501 default_rtl_profile ();
1503 new_direct_jump_p
|= purge_all_dead_edges ();
1504 delete_noop_moves ();
1507 obstack_free (&insn_link_obstack
, NULL
);
1508 free (uid_log_links
);
1509 free (uid_insn_cost
);
1510 reg_stat
.release ();
1513 struct undo
*undo
, *next
;
1514 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1522 total_attempts
+= combine_attempts
;
1523 total_merges
+= combine_merges
;
1524 total_extras
+= combine_extras
;
1525 total_successes
+= combine_successes
;
1527 nonzero_sign_valid
= 0;
1528 rtl_hooks
= general_rtl_hooks
;
1530 /* Make recognizer allow volatile MEMs again. */
1533 return new_direct_jump_p
;
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1539 init_reg_last (void)
1544 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1545 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1548 /* Set up any promoted values for incoming argument registers. */
1551 setup_incoming_promotions (rtx_insn
*first
)
1554 bool strictly_local
= false;
1556 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1557 arg
= DECL_CHAIN (arg
))
1559 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1561 machine_mode mode1
, mode2
, mode3
, mode4
;
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1571 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1575 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1576 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1580 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1581 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1585 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1586 TREE_TYPE (cfun
->decl
), 0);
1588 /* The mode of the register in which the argument is being passed. */
1589 mode4
= GET_MODE (reg
);
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1606 else if (!strictly_local
)
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1620 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1621 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1622 record_value_for_reg (reg
, first
, x
);
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1635 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1637 if (GET_MODE_PRECISION (mode
) < prec
1638 && CONST_INT_P (src
)
1640 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1641 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1650 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1653 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1654 unsigned HOST_WIDE_INT bits
= 0;
1655 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1656 unsigned int num
= 0;
1659 reg_equal
= XEXP (reg_equal_note
, 0);
1661 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1663 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1665 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1671 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1672 if (reg_equal
&& bits
)
1673 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1674 rsp
->nonzero_bits
|= bits
;
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1678 if (rsp
->sign_bit_copies
!= 1)
1680 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1681 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1683 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1684 if (num
== 0 || numeq
> num
)
1687 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1688 rsp
->sign_bit_copies
= num
;
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1704 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1706 rtx_insn
*insn
= (rtx_insn
*) data
;
1709 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1713 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1714 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1716 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1718 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1720 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1721 rsp
->sign_bit_copies
= 1;
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1739 && reg_referenced_p (x
, PATTERN (insn
))
1740 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1743 struct insn_link
*link
;
1745 FOR_EACH_LOG_LINK (link
, insn
)
1746 if (dead_or_set_p (link
->insn
, x
))
1750 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1751 rsp
->sign_bit_copies
= 1;
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1758 set
= expand_field_assignment (set
);
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1763 if (SET_DEST (set
) == x
1764 || (paradoxical_subreg_p (SET_DEST (set
))
1765 && SUBREG_REG (SET_DEST (set
)) == x
))
1766 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1769 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1770 rsp
->sign_bit_copies
= 1;
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1787 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1788 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1789 rtx
*pdest
, rtx
*psrc
)
1796 bool all_adjacent
= true;
1797 int (*is_volatile_p
) (const_rtx
);
1803 if (next_active_insn (succ2
) != i3
)
1804 all_adjacent
= false;
1805 if (next_active_insn (succ
) != succ2
)
1806 all_adjacent
= false;
1808 else if (next_active_insn (succ
) != i3
)
1809 all_adjacent
= false;
1810 if (next_active_insn (insn
) != succ
)
1811 all_adjacent
= false;
1813 else if (next_active_insn (insn
) != i3
)
1814 all_adjacent
= false;
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1828 Get the source and destination of INSN. If more than one, can't
1831 if (GET_CODE (PATTERN (insn
)) == SET
)
1832 set
= PATTERN (insn
);
1833 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1834 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1836 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1838 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1840 switch (GET_CODE (elt
))
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1858 if (REG_P (XEXP (elt
, 0))
1859 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1861 rtx i3pat
= PATTERN (i3
);
1862 int i
= XVECLEN (i3pat
, 0) - 1;
1863 unsigned int regno
= REGNO (XEXP (elt
, 0));
1867 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1869 if (GET_CODE (i3elt
) == USE
1870 && REG_P (XEXP (i3elt
, 0))
1871 && (REGNO (XEXP (i3elt
, 0)) == regno
1872 ? reg_set_between_p (XEXP (elt
, 0),
1873 PREV_INSN (insn
), i3
)
1874 : regno
>= FIRST_PSEUDO_REGISTER
))
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1888 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1889 && insn_nothrow_p (insn
)
1890 && !side_effects_p (elt
))
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1910 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1921 subst_low_luid
= DF_INSN_LUID (insn
);
1923 set
= expand_field_assignment (set
);
1924 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1931 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1932 && extract_asm_operands (PATTERN (i3
)))
1935 /* Don't eliminate a store in the stack pointer. */
1936 if (dest
== stack_pointer_rtx
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1939 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1940 /* Can't merge an ASM_OPERANDS. */
1941 || GET_CODE (src
) == ASM_OPERANDS
1942 /* Can't merge a function call. */
1943 || GET_CODE (src
) == CALL
1944 /* Don't eliminate a function call argument. */
1946 && (find_reg_fusage (i3
, USE
, dest
)
1948 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1949 && global_regs
[REGNO (dest
)])))
1950 /* Don't substitute into an incremented register. */
1951 || FIND_REG_INC_NOTE (i3
, dest
)
1952 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1953 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1955 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1959 && (reg_used_between_p (dest
, succ2
, i3
)
1960 || reg_used_between_p (dest
, succ
, succ2
)))
1961 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1973 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1974 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1975 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1976 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1982 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1985 /* DEST must either be a REG or CC0. */
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1998 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1999 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2007 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2008 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2011 else if (GET_CODE (dest
) != CC0
)
2015 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2016 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2017 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2019 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2029 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2030 || !fixed_regs
[REGNO (reg
)])
2031 if (reg_overlap_mentioned_p (reg
, src
))
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2038 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2041 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2043 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2045 /* We'll check insns between INSN and I3 below. */
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2051 if (GET_CODE (src
) == ASM_OPERANDS
2052 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2060 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2064 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2065 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2075 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2076 if (REG_NOTE_KIND (link
) == REG_INC
2078 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2079 || (pred
!= NULL_RTX
2080 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2081 || (pred2
!= NULL_RTX
2082 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2083 || (succ
!= NULL_RTX
2084 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2085 || (succ2
!= NULL_RTX
2086 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2087 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2101 p
= prev_nonnote_insn (insn
);
2102 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2107 /* If we get here, we have passed all the tests and the combination is
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2155 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2156 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2160 if (GET_CODE (x
) == SET
)
2163 rtx dest
= SET_DEST (set
);
2164 rtx src
= SET_SRC (set
);
2165 rtx inner_dest
= dest
;
2168 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2169 || GET_CODE (inner_dest
) == SUBREG
2170 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2171 inner_dest
= XEXP (inner_dest
, 0);
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2177 if ((inner_dest
!= dest
&&
2178 (!MEM_P (inner_dest
)
2179 || rtx_equal_p (i2dest
, inner_dest
)
2180 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2181 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2182 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2183 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2184 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2196 || (REG_P (inner_dest
)
2197 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2198 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2199 GET_MODE (inner_dest
))))
2200 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2201 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2212 if (GET_CODE (subdest
) == SUBREG
2213 && (GET_MODE_SIZE (GET_MODE (subdest
))
2214 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2215 subdest
= SUBREG_REG (subdest
);
2218 && reg_referenced_p (subdest
, PATTERN (i3
))
2219 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2221 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2222 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2223 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2224 || ! fixed_regs
[REGNO (subdest
)]))
2225 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2227 if (*pi3dest_killed
)
2230 *pi3dest_killed
= subdest
;
2234 else if (GET_CODE (x
) == PARALLEL
)
2238 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2239 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2240 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2251 contains_muldiv (rtx x
)
2253 switch (GET_CODE (x
))
2255 case MOD
: case DIV
: case UMOD
: case UDIV
:
2259 return ! (CONST_INT_P (XEXP (x
, 1))
2260 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2263 return contains_muldiv (XEXP (x
, 0))
2264 || contains_muldiv (XEXP (x
, 1));
2267 return contains_muldiv (XEXP (x
, 0));
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2278 cant_combine_insn_p (rtx_insn
*insn
)
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2286 if (!NONDEBUG_INSN_P (insn
))
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2296 set
= single_set (insn
);
2299 src
= SET_SRC (set
);
2300 dest
= SET_DEST (set
);
2301 if (GET_CODE (src
) == SUBREG
)
2302 src
= SUBREG_REG (src
);
2303 if (GET_CODE (dest
) == SUBREG
)
2304 dest
= SUBREG_REG (dest
);
2305 if (REG_P (src
) && REG_P (dest
)
2306 && ((HARD_REGISTER_P (src
)
2307 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2308 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2309 || (HARD_REGISTER_P (dest
)
2310 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2311 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2317 struct likely_spilled_retval_info
2319 unsigned regno
, nregs
;
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2326 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2328 struct likely_spilled_retval_info
*const info
=
2329 (struct likely_spilled_retval_info
*) data
;
2330 unsigned regno
, nregs
;
2333 if (!REG_P (XEXP (set
, 0)))
2336 if (regno
>= info
->regno
+ info
->nregs
)
2338 nregs
= REG_NREGS (x
);
2339 if (regno
+ nregs
<= info
->regno
)
2341 new_mask
= (2U << (nregs
- 1)) - 1;
2342 if (regno
< info
->regno
)
2343 new_mask
>>= info
->regno
- regno
;
2345 new_mask
<<= regno
- info
->regno
;
2346 info
->mask
&= ~new_mask
;
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2355 likely_spilled_retval_p (rtx_insn
*insn
)
2357 rtx_insn
*use
= BB_END (this_basic_block
);
2360 unsigned regno
, nregs
;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2365 struct likely_spilled_retval_info info
;
2367 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2369 reg
= XEXP (PATTERN (use
), 0);
2370 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2372 regno
= REGNO (reg
);
2373 nregs
= REG_NREGS (reg
);
2376 mask
= (2U << (nregs
- 1)) - 1;
2378 /* Disregard parts of the return value that are set later. */
2382 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2384 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2387 /* Check if any of the (probably) live return value registers is
2392 if ((mask
& 1 << nregs
)
2393 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2405 adjust_for_new_dest (rtx_insn
*insn
)
2407 /* For notes, be conservative and simply remove them. */
2408 remove_reg_equal_equiv_notes (insn
);
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2414 rtx set
= single_set (insn
);
2417 rtx reg
= SET_DEST (set
);
2419 while (GET_CODE (reg
) == ZERO_EXTRACT
2420 || GET_CODE (reg
) == STRICT_LOW_PART
2421 || GET_CODE (reg
) == SUBREG
)
2422 reg
= XEXP (reg
, 0);
2423 gcc_assert (REG_P (reg
));
2425 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2427 df_insn_rescan (insn
);
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2433 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2443 if (regno
< FIRST_PSEUDO_REGISTER
)
2444 return (HARD_REGNO_MODE_OK (regno
, mode
)
2445 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2447 /* Or a pseudo that is only used once. */
2448 return (regno
< reg_n_sets_max
2449 && REG_N_SETS (regno
) == 1
2451 && !REG_USERVAR_P (x
));
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2459 reg_subword_p (rtx x
, rtx reg
)
2461 /* Check that reg is an integer mode register. */
2462 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2465 if (GET_CODE (x
) == STRICT_LOW_PART
2466 || GET_CODE (x
) == ZERO_EXTRACT
)
2469 return GET_CODE (x
) == SUBREG
2470 && SUBREG_REG (x
) == reg
2471 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2480 update_cfg_for_uncondjump (rtx_insn
*insn
)
2482 basic_block bb
= BLOCK_FOR_INSN (insn
);
2483 gcc_assert (BB_END (bb
) == insn
);
2485 purge_dead_edges (bb
);
2488 if (EDGE_COUNT (bb
->succs
) == 1)
2492 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2494 /* Remove barriers from the footer if there are any. */
2495 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2496 if (BARRIER_P (insn
))
2498 if (PREV_INSN (insn
))
2499 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2501 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2502 if (NEXT_INSN (insn
))
2503 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2505 else if (LABEL_P (insn
))
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2513 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2515 if (GET_CODE (pat
) != PARALLEL
)
2518 int len
= XVECLEN (pat
, 0);
2523 for (i
= 0; i
< n
; i
++)
2524 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2525 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2527 for ( ; i
< len
; i
++)
2528 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2529 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2539 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2541 if (!insn_nothrow_p (insn
))
2544 rtx pat
= PATTERN (insn
);
2547 for (i
= 0; i
< n
; i
++)
2549 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2552 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2554 for (j
= i
+ 1; j
< n
; j
++)
2555 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2562 /* Set up a set of registers used in an insn. Called through note_uses,
2563 arguments as described for that function. */
2566 record_used_regs (rtx
*xptr
, void *data
)
2568 bitmap set
= (bitmap
)data
;
2574 /* repeat is used to turn tail-recursion into iteration since GCC
2575 can't do it when there's no return value. */
2580 code
= GET_CODE (x
);
2583 unsigned regno
= REGNO (x
);
2584 unsigned end_regno
= END_REGNO (x
);
2585 while (regno
< end_regno
)
2586 bitmap_set_bit (set
, regno
++);
2590 /* Recursively scan the operands of this expression. */
2592 for (i
= GET_RTX_LENGTH (code
) - 1, fmt
= GET_RTX_FORMAT (code
); i
>= 0; i
--)
2596 /* If we are about to do the last recursive call
2597 needed at this level, change it into iteration.
2598 This function is called enough to be worth it. */
2605 record_used_regs (&XEXP (x
, i
), data
);
2607 else if (fmt
[i
] == 'E')
2608 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2609 record_used_regs (&XVECEXP (x
, i
, j
), data
);
2613 /* Try to combine the insns I0, I1 and I2 into I3.
2614 Here I0, I1 and I2 appear earlier than I3.
2615 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2618 If we are combining more than two insns and the resulting insn is not
2619 recognized, try splitting it into two insns. If that happens, I2 and I3
2620 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2621 Otherwise, I0, I1 and I2 are pseudo-deleted.
2623 Return 0 if the combination does not work. Then nothing is changed.
2624 If we did the combination, return the insn at which combine should
2627 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2628 new direct jump instruction.
2630 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2631 been I3 passed to an earlier try_combine within the same basic
2635 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2636 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2638 /* New patterns for I3 and I2, respectively. */
2639 rtx newpat
, newi2pat
= 0;
2640 rtvec newpat_vec_with_clobbers
= 0;
2641 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2642 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2644 int added_sets_0
, added_sets_1
, added_sets_2
;
2645 /* Total number of SETs to put into I3. */
2647 /* Nonzero if I2's or I1's body now appears in I3. */
2648 int i2_is_used
= 0, i1_is_used
= 0;
2649 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2650 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2651 /* Contains I3 if the destination of I3 is used in its source, which means
2652 that the old life of I3 is being killed. If that usage is placed into
2653 I2 and not in I3, a REG_DEAD note must be made. */
2654 rtx i3dest_killed
= 0;
2655 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2656 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2657 /* Copy of SET_SRC of I1 and I0, if needed. */
2658 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2659 /* Set if I2DEST was reused as a scratch register. */
2660 bool i2scratch
= false;
2661 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2662 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2663 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2664 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2665 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2666 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2667 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2668 /* Notes that must be added to REG_NOTES in I3 and I2. */
2669 rtx new_i3_notes
, new_i2_notes
;
2670 /* Notes that we substituted I3 into I2 instead of the normal case. */
2671 int i3_subst_into_i2
= 0;
2672 /* Notes that I1, I2 or I3 is a MULT operation. */
2675 int changed_i3_dest
= 0;
2678 rtx_insn
*temp_insn
;
2680 struct insn_link
*link
;
2682 rtx new_other_notes
;
2685 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2687 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2690 /* Only try four-insn combinations when there's high likelihood of
2691 success. Look for simple insns, such as loads of constants or
2692 binary operations involving a constant. */
2700 if (!flag_expensive_optimizations
)
2703 for (i
= 0; i
< 4; i
++)
2705 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2706 rtx set
= single_set (insn
);
2710 src
= SET_SRC (set
);
2711 if (CONSTANT_P (src
))
2716 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2718 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2719 || GET_CODE (src
) == LSHIFTRT
)
2723 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2724 are likely manipulating its value. Ideally we'll be able to combine
2725 all four insns into a bitfield insertion of some kind.
2727 Note the source in I0 might be inside a sign/zero extension and the
2728 memory modes in I0 and I3 might be different. So extract the address
2729 from the destination of I3 and search for it in the source of I0.
2731 In the event that there's a match but the source/dest do not actually
2732 refer to the same memory, the worst that happens is we try some
2733 combinations that we wouldn't have otherwise. */
2734 if ((set0
= single_set (i0
))
2735 /* Ensure the source of SET0 is a MEM, possibly buried inside
2737 && (GET_CODE (SET_SRC (set0
)) == MEM
2738 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2739 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2740 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2741 && (set3
= single_set (i3
))
2742 /* Ensure the destination of SET3 is a MEM. */
2743 && GET_CODE (SET_DEST (set3
)) == MEM
2744 /* Would it be better to extract the base address for the MEM
2745 in SET3 and look for that? I don't have cases where it matters
2746 but I could envision such cases. */
2747 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2750 if (ngood
< 2 && nshift
< 2)
2754 /* Exit early if one of the insns involved can't be used for
2757 || (i1
&& CALL_P (i1
))
2758 || (i0
&& CALL_P (i0
))
2759 || cant_combine_insn_p (i3
)
2760 || cant_combine_insn_p (i2
)
2761 || (i1
&& cant_combine_insn_p (i1
))
2762 || (i0
&& cant_combine_insn_p (i0
))
2763 || likely_spilled_retval_p (i3
))
2767 undobuf
.other_insn
= 0;
2769 /* Reset the hard register usage information. */
2770 CLEAR_HARD_REG_SET (newpat_used_regs
);
2772 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2775 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2776 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2778 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2779 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2781 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2782 INSN_UID (i2
), INSN_UID (i3
));
2785 /* If multiple insns feed into one of I2 or I3, they can be in any
2786 order. To simplify the code below, reorder them in sequence. */
2787 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2789 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2791 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2794 added_links_insn
= 0;
2796 /* For combinations that may result in two insns, we have to gather
2797 some extra information about registers used, so that we can
2798 update all relevant LOG_LINKS later. */
2799 auto_bitmap i2_regset
, i3_regset
, links_regset
;
2802 note_uses (&PATTERN (i2
), record_used_regs
, (bitmap
)i2_regset
);
2803 note_uses (&PATTERN (i3
), record_used_regs
, (bitmap
)i3_regset
);
2805 FOR_EACH_LOG_LINK (ll
, i3
)
2806 bitmap_set_bit (links_regset
, ll
->regno
);
2807 FOR_EACH_LOG_LINK (ll
, i2
)
2808 bitmap_set_bit (links_regset
, ll
->regno
);
2809 FOR_EACH_LOG_LINK (ll
, i1
)
2810 bitmap_set_bit (links_regset
, ll
->regno
);
2812 FOR_EACH_LOG_LINK (ll
, i0
)
2813 bitmap_set_bit (links_regset
, ll
->regno
);
2816 /* First check for one important special case that the code below will
2817 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2818 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2819 we may be able to replace that destination with the destination of I3.
2820 This occurs in the common code where we compute both a quotient and
2821 remainder into a structure, in which case we want to do the computation
2822 directly into the structure to avoid register-register copies.
2824 Note that this case handles both multiple sets in I2 and also cases
2825 where I2 has a number of CLOBBERs inside the PARALLEL.
2827 We make very conservative checks below and only try to handle the
2828 most common cases of this. For example, we only handle the case
2829 where I2 and I3 are adjacent to avoid making difficult register
2832 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2833 && REG_P (SET_SRC (PATTERN (i3
)))
2834 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2835 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2836 && GET_CODE (PATTERN (i2
)) == PARALLEL
2837 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2838 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2839 below would need to check what is inside (and reg_overlap_mentioned_p
2840 doesn't support those codes anyway). Don't allow those destinations;
2841 the resulting insn isn't likely to be recognized anyway. */
2842 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2843 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2844 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2845 SET_DEST (PATTERN (i3
)))
2846 && next_active_insn (i2
) == i3
)
2848 rtx p2
= PATTERN (i2
);
2850 /* Make sure that the destination of I3,
2851 which we are going to substitute into one output of I2,
2852 is not used within another output of I2. We must avoid making this:
2853 (parallel [(set (mem (reg 69)) ...)
2854 (set (reg 69) ...)])
2855 which is not well-defined as to order of actions.
2856 (Besides, reload can't handle output reloads for this.)
2858 The problem can also happen if the dest of I3 is a memory ref,
2859 if another dest in I2 is an indirect memory ref.
2861 Neither can this PARALLEL be an asm. We do not allow combining
2862 that usually (see can_combine_p), so do not here either. */
2864 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2866 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2867 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2868 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2869 SET_DEST (XVECEXP (p2
, 0, i
))))
2871 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2872 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2877 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2878 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2879 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2884 subst_low_luid
= DF_INSN_LUID (i2
);
2886 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2887 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2888 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2889 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2891 /* Replace the dest in I2 with our dest and make the resulting
2892 insn the new pattern for I3. Then skip to where we validate
2893 the pattern. Everything was set up above. */
2894 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2896 i3_subst_into_i2
= 1;
2897 goto validate_replacement
;
2901 /* If I2 is setting a pseudo to a constant and I3 is setting some
2902 sub-part of it to another constant, merge them by making a new
2905 && (temp_expr
= single_set (i2
)) != 0
2906 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2907 && GET_CODE (PATTERN (i3
)) == SET
2908 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2909 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2911 rtx dest
= SET_DEST (PATTERN (i3
));
2915 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2917 if (CONST_INT_P (XEXP (dest
, 1))
2918 && CONST_INT_P (XEXP (dest
, 2)))
2920 width
= INTVAL (XEXP (dest
, 1));
2921 offset
= INTVAL (XEXP (dest
, 2));
2922 dest
= XEXP (dest
, 0);
2923 if (BITS_BIG_ENDIAN
)
2924 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2929 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2930 dest
= XEXP (dest
, 0);
2931 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2937 /* If this is the low part, we're done. */
2938 if (subreg_lowpart_p (dest
))
2940 /* Handle the case where inner is twice the size of outer. */
2941 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2942 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2943 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2944 /* Otherwise give up for now. */
2951 rtx inner
= SET_SRC (PATTERN (i3
));
2952 rtx outer
= SET_SRC (temp_expr
);
2955 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2956 rtx_mode_t (inner
, GET_MODE (dest
)),
2961 subst_low_luid
= DF_INSN_LUID (i2
);
2962 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2963 i2dest
= SET_DEST (temp_expr
);
2964 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2966 /* Replace the source in I2 with the new constant and make the
2967 resulting insn the new pattern for I3. Then skip to where we
2968 validate the pattern. Everything was set up above. */
2969 SUBST (SET_SRC (temp_expr
),
2970 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2972 newpat
= PATTERN (i2
);
2974 /* The dest of I3 has been replaced with the dest of I2. */
2975 changed_i3_dest
= 1;
2976 goto validate_replacement
;
2980 /* If we have no I1 and I2 looks like:
2981 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2983 make up a dummy I1 that is
2986 (set (reg:CC X) (compare:CC Y (const_int 0)))
2988 (We can ignore any trailing CLOBBERs.)
2990 This undoes a previous combination and allows us to match a branch-and-
2993 if (!HAVE_cc0
&& i1
== 0
2994 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2995 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2997 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2998 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2999 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
3000 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
3001 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3002 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3004 /* We make I1 with the same INSN_UID as I2. This gives it
3005 the same DF_INSN_LUID for value tracking. Our fake I1 will
3006 never appear in the insn stream so giving it the same INSN_UID
3007 as I2 will not cause a problem. */
3009 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3010 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
3012 INSN_UID (i1
) = INSN_UID (i2
);
3014 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
3015 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
3016 SET_DEST (PATTERN (i1
)));
3017 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
3018 SUBST_LINK (LOG_LINKS (i2
),
3019 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
3022 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3023 make those two SETs separate I1 and I2 insns, and make an I0 that is
3025 if (!HAVE_cc0
&& i0
== 0
3026 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
3027 && can_split_parallel_of_n_reg_sets (i2
, 2)
3028 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
3029 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
3031 /* If there is no I1, there is no I0 either. */
3034 /* We make I1 with the same INSN_UID as I2. This gives it
3035 the same DF_INSN_LUID for value tracking. Our fake I1 will
3036 never appear in the insn stream so giving it the same INSN_UID
3037 as I2 will not cause a problem. */
3039 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
3040 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
3042 INSN_UID (i1
) = INSN_UID (i2
);
3044 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3047 /* Verify that I2 and I1 are valid for combining. */
3048 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
3049 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
3051 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3058 /* Record whether I2DEST is used in I2SRC and similarly for the other
3059 cases. Knowing this will help in register status updating below. */
3060 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3061 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3062 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3063 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3064 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3065 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3066 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3067 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3068 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3070 /* For the earlier insns, determine which of the subsequent ones they
3072 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3073 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3074 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3075 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3076 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3078 /* Ensure that I3's pattern can be the destination of combines. */
3079 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3080 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3081 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3082 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3089 /* See if any of the insns is a MULT operation. Unless one is, we will
3090 reject a combination that is, since it must be slower. Be conservative
3092 if (GET_CODE (i2src
) == MULT
3093 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3094 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3095 || (GET_CODE (PATTERN (i3
)) == SET
3096 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3099 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3100 We used to do this EXCEPT in one case: I3 has a post-inc in an
3101 output operand. However, that exception can give rise to insns like
3103 which is a famous insn on the PDP-11 where the value of r3 used as the
3104 source was model-dependent. Avoid this sort of thing. */
3107 if (!(GET_CODE (PATTERN (i3
)) == SET
3108 && REG_P (SET_SRC (PATTERN (i3
)))
3109 && MEM_P (SET_DEST (PATTERN (i3
)))
3110 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3111 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3112 /* It's not the exception. */
3117 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3118 if (REG_NOTE_KIND (link
) == REG_INC
3119 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3121 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3128 /* See if the SETs in I1 or I2 need to be kept around in the merged
3129 instruction: whenever the value set there is still needed past I3.
3130 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3132 For the SET in I1, we have two cases: if I1 and I2 independently feed
3133 into I3, the set in I1 needs to be kept around unless I1DEST dies
3134 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3135 in I1 needs to be kept around unless I1DEST dies or is set in either
3136 I2 or I3. The same considerations apply to I0. */
3138 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3141 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3142 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3147 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3148 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3149 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3150 && dead_or_set_p (i2
, i0dest
)));
3154 /* We are about to copy insns for the case where they need to be kept
3155 around. Check that they can be copied in the merged instruction. */
3157 if (targetm
.cannot_copy_insn_p
3158 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3159 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3160 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3166 /* If the set in I2 needs to be kept around, we must make a copy of
3167 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3168 PATTERN (I2), we are only substituting for the original I1DEST, not into
3169 an already-substituted copy. This also prevents making self-referential
3170 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3175 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3176 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3178 i2pat
= copy_rtx (PATTERN (i2
));
3183 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3184 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3186 i1pat
= copy_rtx (PATTERN (i1
));
3191 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3192 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3194 i0pat
= copy_rtx (PATTERN (i0
));
3199 /* Substitute in the latest insn for the regs set by the earlier ones. */
3201 maxreg
= max_reg_num ();
3205 /* Many machines that don't use CC0 have insns that can both perform an
3206 arithmetic operation and set the condition code. These operations will
3207 be represented as a PARALLEL with the first element of the vector
3208 being a COMPARE of an arithmetic operation with the constant zero.
3209 The second element of the vector will set some pseudo to the result
3210 of the same arithmetic operation. If we simplify the COMPARE, we won't
3211 match such a pattern and so will generate an extra insn. Here we test
3212 for this case, where both the comparison and the operation result are
3213 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3214 I2SRC. Later we will make the PARALLEL that contains I2. */
3216 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3217 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3218 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3219 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3222 rtx
*cc_use_loc
= NULL
;
3223 rtx_insn
*cc_use_insn
= NULL
;
3224 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3225 machine_mode compare_mode
, orig_compare_mode
;
3226 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3228 newpat
= PATTERN (i3
);
3229 newpat_dest
= SET_DEST (newpat
);
3230 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3232 if (undobuf
.other_insn
== 0
3233 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3236 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3237 compare_code
= simplify_compare_const (compare_code
,
3238 GET_MODE (i2dest
), op0
, &op1
);
3239 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3242 /* Do the rest only if op1 is const0_rtx, which may be the
3243 result of simplification. */
3244 if (op1
== const0_rtx
)
3246 /* If a single use of the CC is found, prepare to modify it
3247 when SELECT_CC_MODE returns a new CC-class mode, or when
3248 the above simplify_compare_const() returned a new comparison
3249 operator. undobuf.other_insn is assigned the CC use insn
3250 when modifying it. */
3253 #ifdef SELECT_CC_MODE
3254 machine_mode new_mode
3255 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3256 if (new_mode
!= orig_compare_mode
3257 && can_change_dest_mode (SET_DEST (newpat
),
3258 added_sets_2
, new_mode
))
3260 unsigned int regno
= REGNO (newpat_dest
);
3261 compare_mode
= new_mode
;
3262 if (regno
< FIRST_PSEUDO_REGISTER
)
3263 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3266 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3267 newpat_dest
= regno_reg_rtx
[regno
];
3271 /* Cases for modifying the CC-using comparison. */
3272 if (compare_code
!= orig_compare_code
3273 /* ??? Do we need to verify the zero rtx? */
3274 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3276 /* Replace cc_use_loc with entire new RTX. */
3278 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3279 newpat_dest
, const0_rtx
));
3280 undobuf
.other_insn
= cc_use_insn
;
3282 else if (compare_mode
!= orig_compare_mode
)
3284 /* Just replace the CC reg with a new mode. */
3285 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3286 undobuf
.other_insn
= cc_use_insn
;
3290 /* Now we modify the current newpat:
3291 First, SET_DEST(newpat) is updated if the CC mode has been
3292 altered. For targets without SELECT_CC_MODE, this should be
3294 if (compare_mode
!= orig_compare_mode
)
3295 SUBST (SET_DEST (newpat
), newpat_dest
);
3296 /* This is always done to propagate i2src into newpat. */
3297 SUBST (SET_SRC (newpat
),
3298 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3299 /* Create new version of i2pat if needed; the below PARALLEL
3300 creation needs this to work correctly. */
3301 if (! rtx_equal_p (i2src
, op0
))
3302 i2pat
= gen_rtx_SET (i2dest
, op0
);
3307 if (i2_is_used
== 0)
3309 /* It is possible that the source of I2 or I1 may be performing
3310 an unneeded operation, such as a ZERO_EXTEND of something
3311 that is known to have the high part zero. Handle that case
3312 by letting subst look at the inner insns.
3314 Another way to do this would be to have a function that tries
3315 to simplify a single insn instead of merging two or more
3316 insns. We don't do this because of the potential of infinite
3317 loops and because of the potential extra memory required.
3318 However, doing it the way we are is a bit of a kludge and
3319 doesn't catch all cases.
3321 But only do this if -fexpensive-optimizations since it slows
3322 things down and doesn't usually win.
3324 This is not done in the COMPARE case above because the
3325 unmodified I2PAT is used in the PARALLEL and so a pattern
3326 with a modified I2SRC would not match. */
3328 if (flag_expensive_optimizations
)
3330 /* Pass pc_rtx so no substitutions are done, just
3334 subst_low_luid
= DF_INSN_LUID (i1
);
3335 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3338 subst_low_luid
= DF_INSN_LUID (i2
);
3339 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3342 n_occurrences
= 0; /* `subst' counts here */
3343 subst_low_luid
= DF_INSN_LUID (i2
);
3345 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3346 copy of I2SRC each time we substitute it, in order to avoid creating
3347 self-referential RTL when we will be substituting I1SRC for I1DEST
3348 later. Likewise if I0 feeds into I2, either directly or indirectly
3349 through I1, and I0DEST is in I0SRC. */
3350 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3351 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3352 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3353 && i0dest_in_i0src
));
3356 /* Record whether I2's body now appears within I3's body. */
3357 i2_is_used
= n_occurrences
;
3360 /* If we already got a failure, don't try to do more. Otherwise, try to
3361 substitute I1 if we have it. */
3363 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3365 /* Check that an autoincrement side-effect on I1 has not been lost.
3366 This happens if I1DEST is mentioned in I2 and dies there, and
3367 has disappeared from the new pattern. */
3368 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3370 && dead_or_set_p (i2
, i1dest
)
3371 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3372 /* Before we can do this substitution, we must redo the test done
3373 above (see detailed comments there) that ensures I1DEST isn't
3374 mentioned in any SETs in NEWPAT that are field assignments. */
3375 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3383 subst_low_luid
= DF_INSN_LUID (i1
);
3385 /* If the following substitution will modify I1SRC, make a copy of it
3386 for the case where it is substituted for I1DEST in I2PAT later. */
3387 if (added_sets_2
&& i1_feeds_i2_n
)
3388 i1src_copy
= copy_rtx (i1src
);
3390 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3391 copy of I1SRC each time we substitute it, in order to avoid creating
3392 self-referential RTL when we will be substituting I0SRC for I0DEST
3394 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3395 i0_feeds_i1_n
&& i0dest_in_i0src
);
3398 /* Record whether I1's body now appears within I3's body. */
3399 i1_is_used
= n_occurrences
;
3402 /* Likewise for I0 if we have it. */
3404 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3406 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3407 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3408 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3409 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3410 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3417 /* If the following substitution will modify I0SRC, make a copy of it
3418 for the case where it is substituted for I0DEST in I1PAT later. */
3419 if (added_sets_1
&& i0_feeds_i1_n
)
3420 i0src_copy
= copy_rtx (i0src
);
3421 /* And a copy for I0DEST in I2PAT substitution. */
3422 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3423 || (i0_feeds_i2_n
)))
3424 i0src_copy2
= copy_rtx (i0src
);
3427 subst_low_luid
= DF_INSN_LUID (i0
);
3428 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3432 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3433 to count all the ways that I2SRC and I1SRC can be used. */
3434 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3435 && i2_is_used
+ added_sets_2
> 1)
3436 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3437 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3439 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3440 && (n_occurrences
+ added_sets_0
3441 + (added_sets_1
&& i0_feeds_i1_n
)
3442 + (added_sets_2
&& i0_feeds_i2_n
)
3444 /* Fail if we tried to make a new register. */
3445 || max_reg_num () != maxreg
3446 /* Fail if we couldn't do something and have a CLOBBER. */
3447 || GET_CODE (newpat
) == CLOBBER
3448 /* Fail if this new pattern is a MULT and we didn't have one before
3449 at the outer level. */
3450 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3457 /* If the actions of the earlier insns must be kept
3458 in addition to substituting them into the latest one,
3459 we must make a new PARALLEL for the latest insn
3460 to hold additional the SETs. */
3462 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3464 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3467 if (GET_CODE (newpat
) == PARALLEL
)
3469 rtvec old
= XVEC (newpat
, 0);
3470 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3471 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3472 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3473 sizeof (old
->elem
[0]) * old
->num_elem
);
3478 total_sets
= 1 + extra_sets
;
3479 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3480 XVECEXP (newpat
, 0, 0) = old
;
3484 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3490 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3492 XVECEXP (newpat
, 0, --total_sets
) = t
;
3498 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3499 i0_feeds_i1_n
&& i0dest_in_i0src
);
3500 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3501 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3503 XVECEXP (newpat
, 0, --total_sets
) = t
;
3507 validate_replacement
:
3509 /* Note which hard regs this insn has as inputs. */
3510 mark_used_regs_combine (newpat
);
3512 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3513 consider splitting this pattern, we might need these clobbers. */
3514 if (i1
&& GET_CODE (newpat
) == PARALLEL
3515 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3517 int len
= XVECLEN (newpat
, 0);
3519 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3520 for (i
= 0; i
< len
; i
++)
3521 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3524 /* We have recognized nothing yet. */
3525 insn_code_number
= -1;
3527 /* See if this is a PARALLEL of two SETs where one SET's destination is
3528 a register that is unused and this isn't marked as an instruction that
3529 might trap in an EH region. In that case, we just need the other SET.
3530 We prefer this over the PARALLEL.
3532 This can occur when simplifying a divmod insn. We *must* test for this
3533 case here because the code below that splits two independent SETs doesn't
3534 handle this case correctly when it updates the register status.
3536 It's pointless doing this if we originally had two sets, one from
3537 i3, and one from i2. Combining then splitting the parallel results
3538 in the original i2 again plus an invalid insn (which we delete).
3539 The net effect is only to move instructions around, which makes
3540 debug info less accurate. */
3542 if (!(added_sets_2
&& i1
== 0)
3543 && is_parallel_of_n_reg_sets (newpat
, 2)
3544 && asm_noperands (newpat
) < 0)
3546 rtx set0
= XVECEXP (newpat
, 0, 0);
3547 rtx set1
= XVECEXP (newpat
, 0, 1);
3548 rtx oldpat
= newpat
;
3550 if (((REG_P (SET_DEST (set1
))
3551 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3552 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3553 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3554 && insn_nothrow_p (i3
)
3555 && !side_effects_p (SET_SRC (set1
)))
3558 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3561 else if (((REG_P (SET_DEST (set0
))
3562 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3563 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3564 && find_reg_note (i3
, REG_UNUSED
,
3565 SUBREG_REG (SET_DEST (set0
)))))
3566 && insn_nothrow_p (i3
)
3567 && !side_effects_p (SET_SRC (set0
)))
3570 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3572 if (insn_code_number
>= 0)
3573 changed_i3_dest
= 1;
3576 if (insn_code_number
< 0)
3580 /* Is the result of combination a valid instruction? */
3581 if (insn_code_number
< 0)
3582 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3584 /* If we were combining three insns and the result is a simple SET
3585 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3586 insns. There are two ways to do this. It can be split using a
3587 machine-specific method (like when you have an addition of a large
3588 constant) or by combine in the function find_split_point. */
3590 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3591 && asm_noperands (newpat
) < 0)
3593 rtx parallel
, *split
;
3594 rtx_insn
*m_split_insn
;
3596 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3597 use I2DEST as a scratch register will help. In the latter case,
3598 convert I2DEST to the mode of the source of NEWPAT if we can. */
3600 m_split_insn
= combine_split_insns (newpat
, i3
);
3602 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3603 inputs of NEWPAT. */
3605 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3606 possible to try that as a scratch reg. This would require adding
3607 more code to make it work though. */
3609 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3611 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3613 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3614 (temporarily, until we are committed to this instruction
3615 combination) does not work: for example, any call to nonzero_bits
3616 on the register (from a splitter in the MD file, for example)
3617 will get the old information, which is invalid.
3619 Since nowadays we can create registers during combine just fine,
3620 we should just create a new one here, not reuse i2dest. */
3622 /* First try to split using the original register as a
3623 scratch register. */
3624 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3625 gen_rtvec (2, newpat
,
3626 gen_rtx_CLOBBER (VOIDmode
,
3628 m_split_insn
= combine_split_insns (parallel
, i3
);
3630 /* If that didn't work, try changing the mode of I2DEST if
3632 if (m_split_insn
== 0
3633 && new_mode
!= GET_MODE (i2dest
)
3634 && new_mode
!= VOIDmode
3635 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3637 machine_mode old_mode
= GET_MODE (i2dest
);
3640 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3641 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3644 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3645 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3648 parallel
= (gen_rtx_PARALLEL
3650 gen_rtvec (2, newpat
,
3651 gen_rtx_CLOBBER (VOIDmode
,
3653 m_split_insn
= combine_split_insns (parallel
, i3
);
3655 if (m_split_insn
== 0
3656 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3660 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3661 buf
= undobuf
.undos
;
3662 undobuf
.undos
= buf
->next
;
3663 buf
->next
= undobuf
.frees
;
3664 undobuf
.frees
= buf
;
3668 i2scratch
= m_split_insn
!= 0;
3671 /* If recog_for_combine has discarded clobbers, try to use them
3672 again for the split. */
3673 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3675 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3676 m_split_insn
= combine_split_insns (parallel
, i3
);
3679 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3681 rtx m_split_pat
= PATTERN (m_split_insn
);
3682 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3683 if (insn_code_number
>= 0)
3684 newpat
= m_split_pat
;
3686 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3687 && (next_nonnote_nondebug_insn (i2
) == i3
3688 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3691 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3692 newi2pat
= PATTERN (m_split_insn
);
3694 i3set
= single_set (NEXT_INSN (m_split_insn
));
3695 i2set
= single_set (m_split_insn
);
3697 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3699 /* If I2 or I3 has multiple SETs, we won't know how to track
3700 register status, so don't use these insns. If I2's destination
3701 is used between I2 and I3, we also can't use these insns. */
3703 if (i2_code_number
>= 0 && i2set
&& i3set
3704 && (next_nonnote_nondebug_insn (i2
) == i3
3705 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3706 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3708 if (insn_code_number
>= 0)
3711 /* It is possible that both insns now set the destination of I3.
3712 If so, we must show an extra use of it. */
3714 if (insn_code_number
>= 0)
3716 rtx new_i3_dest
= SET_DEST (i3set
);
3717 rtx new_i2_dest
= SET_DEST (i2set
);
3719 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3720 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3721 || GET_CODE (new_i3_dest
) == SUBREG
)
3722 new_i3_dest
= XEXP (new_i3_dest
, 0);
3724 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3725 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3726 || GET_CODE (new_i2_dest
) == SUBREG
)
3727 new_i2_dest
= XEXP (new_i2_dest
, 0);
3729 if (REG_P (new_i3_dest
)
3730 && REG_P (new_i2_dest
)
3731 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3732 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3733 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3737 /* If we can split it and use I2DEST, go ahead and see if that
3738 helps things be recognized. Verify that none of the registers
3739 are set between I2 and I3. */
3740 if (insn_code_number
< 0
3741 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3742 && (!HAVE_cc0
|| REG_P (i2dest
))
3743 /* We need I2DEST in the proper mode. If it is a hard register
3744 or the only use of a pseudo, we can change its mode.
3745 Make sure we don't change a hard register to have a mode that
3746 isn't valid for it, or change the number of registers. */
3747 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3748 || GET_MODE (*split
) == VOIDmode
3749 || can_change_dest_mode (i2dest
, added_sets_2
,
3751 && (next_nonnote_nondebug_insn (i2
) == i3
3752 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3753 /* We can't overwrite I2DEST if its value is still used by
3755 && ! reg_referenced_p (i2dest
, newpat
))
3757 rtx newdest
= i2dest
;
3758 enum rtx_code split_code
= GET_CODE (*split
);
3759 machine_mode split_mode
= GET_MODE (*split
);
3760 bool subst_done
= false;
3761 newi2pat
= NULL_RTX
;
3765 /* *SPLIT may be part of I2SRC, so make sure we have the
3766 original expression around for later debug processing.
3767 We should not need I2SRC any more in other cases. */
3768 if (MAY_HAVE_DEBUG_INSNS
)
3769 i2src
= copy_rtx (i2src
);
3773 /* Get NEWDEST as a register in the proper mode. We have already
3774 validated that we can do this. */
3775 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3777 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3778 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3781 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3782 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3786 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3787 an ASHIFT. This can occur if it was inside a PLUS and hence
3788 appeared to be a memory address. This is a kludge. */
3789 if (split_code
== MULT
3790 && CONST_INT_P (XEXP (*split
, 1))
3791 && INTVAL (XEXP (*split
, 1)) > 0
3792 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3794 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3795 XEXP (*split
, 0), GEN_INT (i
)));
3796 /* Update split_code because we may not have a multiply
3798 split_code
= GET_CODE (*split
);
3801 /* Similarly for (plus (mult FOO (const_int pow2))). */
3802 if (split_code
== PLUS
3803 && GET_CODE (XEXP (*split
, 0)) == MULT
3804 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3805 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3806 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3808 rtx nsplit
= XEXP (*split
, 0);
3809 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3810 XEXP (nsplit
, 0), GEN_INT (i
)));
3811 /* Update split_code because we may not have a multiply
3813 split_code
= GET_CODE (*split
);
3816 #ifdef INSN_SCHEDULING
3817 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3818 be written as a ZERO_EXTEND. */
3819 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3821 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3822 what it really is. */
3823 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3825 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3826 SUBREG_REG (*split
)));
3828 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3829 SUBREG_REG (*split
)));
3833 /* Attempt to split binary operators using arithmetic identities. */
3834 if (BINARY_P (SET_SRC (newpat
))
3835 && split_mode
== GET_MODE (SET_SRC (newpat
))
3836 && ! side_effects_p (SET_SRC (newpat
)))
3838 rtx setsrc
= SET_SRC (newpat
);
3839 machine_mode mode
= GET_MODE (setsrc
);
3840 enum rtx_code code
= GET_CODE (setsrc
);
3841 rtx src_op0
= XEXP (setsrc
, 0);
3842 rtx src_op1
= XEXP (setsrc
, 1);
3844 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3845 if (rtx_equal_p (src_op0
, src_op1
))
3847 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3848 SUBST (XEXP (setsrc
, 0), newdest
);
3849 SUBST (XEXP (setsrc
, 1), newdest
);
3852 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3853 else if ((code
== PLUS
|| code
== MULT
)
3854 && GET_CODE (src_op0
) == code
3855 && GET_CODE (XEXP (src_op0
, 0)) == code
3856 && (INTEGRAL_MODE_P (mode
)
3857 || (FLOAT_MODE_P (mode
)
3858 && flag_unsafe_math_optimizations
)))
3860 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3861 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3862 rtx r
= XEXP (src_op0
, 1);
3865 /* Split both "((X op Y) op X) op Y" and
3866 "((X op Y) op Y) op X" as "T op T" where T is
3868 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3869 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3871 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3872 SUBST (XEXP (setsrc
, 0), newdest
);
3873 SUBST (XEXP (setsrc
, 1), newdest
);
3876 /* Split "((X op X) op Y) op Y)" as "T op T" where
3878 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3880 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3881 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3882 SUBST (XEXP (setsrc
, 0), newdest
);
3883 SUBST (XEXP (setsrc
, 1), newdest
);
3891 newi2pat
= gen_rtx_SET (newdest
, *split
);
3892 SUBST (*split
, newdest
);
3895 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3897 /* recog_for_combine might have added CLOBBERs to newi2pat.
3898 Make sure NEWPAT does not depend on the clobbered regs. */
3899 if (GET_CODE (newi2pat
) == PARALLEL
)
3900 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3901 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3903 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3904 if (reg_overlap_mentioned_p (reg
, newpat
))
3911 /* If the split point was a MULT and we didn't have one before,
3912 don't use one now. */
3913 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3914 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3918 /* Check for a case where we loaded from memory in a narrow mode and
3919 then sign extended it, but we need both registers. In that case,
3920 we have a PARALLEL with both loads from the same memory location.
3921 We can split this into a load from memory followed by a register-register
3922 copy. This saves at least one insn, more if register allocation can
3925 We cannot do this if the destination of the first assignment is a
3926 condition code register or cc0. We eliminate this case by making sure
3927 the SET_DEST and SET_SRC have the same mode.
3929 We cannot do this if the destination of the second assignment is
3930 a register that we have already assumed is zero-extended. Similarly
3931 for a SUBREG of such a register. */
3933 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3934 && GET_CODE (newpat
) == PARALLEL
3935 && XVECLEN (newpat
, 0) == 2
3936 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3937 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3938 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3939 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3940 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3941 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3942 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3943 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3945 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3946 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3947 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3949 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3950 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3951 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3952 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3953 != GET_MODE_MASK (word_mode
))))
3954 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3955 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3957 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3958 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3959 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3960 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3961 != GET_MODE_MASK (word_mode
)))))
3962 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3963 SET_SRC (XVECEXP (newpat
, 0, 1)))
3964 && ! find_reg_note (i3
, REG_UNUSED
,
3965 SET_DEST (XVECEXP (newpat
, 0, 0))))
3969 newi2pat
= XVECEXP (newpat
, 0, 0);
3970 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3971 newpat
= XVECEXP (newpat
, 0, 1);
3972 SUBST (SET_SRC (newpat
),
3973 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3974 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3976 if (i2_code_number
>= 0)
3977 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3979 if (insn_code_number
>= 0)
3983 /* Similarly, check for a case where we have a PARALLEL of two independent
3984 SETs but we started with three insns. In this case, we can do the sets
3985 as two separate insns. This case occurs when some SET allows two
3986 other insns to combine, but the destination of that SET is still live.
3988 Also do this if we started with two insns and (at least) one of the
3989 resulting sets is a noop; this noop will be deleted later. */
3991 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3992 && GET_CODE (newpat
) == PARALLEL
3993 && XVECLEN (newpat
, 0) == 2
3994 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3995 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3996 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3997 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3998 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3999 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
4000 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
4001 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
4002 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
4003 XVECEXP (newpat
, 0, 0))
4004 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
4005 XVECEXP (newpat
, 0, 1))
4006 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
4007 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
4009 rtx set0
= XVECEXP (newpat
, 0, 0);
4010 rtx set1
= XVECEXP (newpat
, 0, 1);
4012 /* Normally, it doesn't matter which of the two is done first,
4013 but the one that references cc0 can't be the second, and
4014 one which uses any regs/memory set in between i2 and i3 can't
4015 be first. The PARALLEL might also have been pre-existing in i3,
4016 so we need to make sure that we won't wrongly hoist a SET to i2
4017 that would conflict with a death note present in there. */
4018 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
4019 && !(REG_P (SET_DEST (set1
))
4020 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4021 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4022 && find_reg_note (i2
, REG_DEAD
,
4023 SUBREG_REG (SET_DEST (set1
))))
4024 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
4025 /* If I3 is a jump, ensure that set0 is a jump so that
4026 we do not create invalid RTL. */
4027 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4033 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
4034 && !(REG_P (SET_DEST (set0
))
4035 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4036 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4037 && find_reg_note (i2
, REG_DEAD
,
4038 SUBREG_REG (SET_DEST (set0
))))
4039 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
4040 /* If I3 is a jump, ensure that set1 is a jump so that
4041 we do not create invalid RTL. */
4042 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4054 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4056 if (i2_code_number
>= 0)
4058 /* recog_for_combine might have added CLOBBERs to newi2pat.
4059 Make sure NEWPAT does not depend on the clobbered regs. */
4060 if (GET_CODE (newi2pat
) == PARALLEL
)
4062 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4063 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4065 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4066 if (reg_overlap_mentioned_p (reg
, newpat
))
4074 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4078 /* If it still isn't recognized, fail and change things back the way they
4080 if ((insn_code_number
< 0
4081 /* Is the result a reasonable ASM_OPERANDS? */
4082 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4088 /* If we had to change another insn, make sure it is valid also. */
4089 if (undobuf
.other_insn
)
4091 CLEAR_HARD_REG_SET (newpat_used_regs
);
4093 other_pat
= PATTERN (undobuf
.other_insn
);
4094 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4097 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4104 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4105 they are adjacent to each other or not. */
4108 rtx_insn
*p
= prev_nonnote_insn (i3
);
4109 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4110 && sets_cc0_p (newi2pat
))
4117 /* Only allow this combination if insn_rtx_costs reports that the
4118 replacement instructions are cheaper than the originals. */
4119 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4125 auto_bitmap new_regs_in_i2
;
4128 /* We need to discover situations where we introduce a use of a
4129 register into I2, where none of the existing LOG_LINKS contain
4130 a reference to it. This can happen if previously I3 referenced
4131 the reg, and there is an additional use between I2 and I3. We
4132 must remove the LOG_LINKS entry from that additional use and
4133 distribute it along with our own ones. */
4134 note_uses (&newi2pat
, record_used_regs
, (bitmap
)new_regs_in_i2
);
4135 bitmap_and_compl_into (new_regs_in_i2
, i2_regset
);
4136 bitmap_and_compl_into (new_regs_in_i2
, links_regset
);
4138 /* Here, we first look for situations where a hard register use
4139 moved, and just give up. This should happen approximately
4140 never, and it's not worth it to deal with possibilities like
4141 multi-word registers. Later, when fixing up LOG_LINKS, we
4142 deal with the case where a pseudo use moved. */
4143 if (!bitmap_empty_p (new_regs_in_i2
)
4144 && prev_nonnote_nondebug_insn (i3
) != i2
4145 && bitmap_first_set_bit (new_regs_in_i2
) < FIRST_PSEUDO_REGISTER
)
4152 if (MAY_HAVE_DEBUG_INSNS
)
4156 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4157 if (undo
->kind
== UNDO_MODE
)
4159 rtx reg
= *undo
->where
.r
;
4160 machine_mode new_mode
= GET_MODE (reg
);
4161 machine_mode old_mode
= undo
->old_contents
.m
;
4163 /* Temporarily revert mode back. */
4164 adjust_reg_mode (reg
, old_mode
);
4166 if (reg
== i2dest
&& i2scratch
)
4168 /* If we used i2dest as a scratch register with a
4169 different mode, substitute it for the original
4170 i2src while its original mode is temporarily
4171 restored, and then clear i2scratch so that we don't
4172 do it again later. */
4173 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4176 /* Put back the new mode. */
4177 adjust_reg_mode (reg
, new_mode
);
4181 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4182 rtx_insn
*first
, *last
;
4187 last
= last_combined_insn
;
4192 last
= undobuf
.other_insn
;
4194 if (DF_INSN_LUID (last
)
4195 < DF_INSN_LUID (last_combined_insn
))
4196 last
= last_combined_insn
;
4199 /* We're dealing with a reg that changed mode but not
4200 meaning, so we want to turn it into a subreg for
4201 the new mode. However, because of REG sharing and
4202 because its mode had already changed, we have to do
4203 it in two steps. First, replace any debug uses of
4204 reg, with its original mode temporarily restored,
4205 with this copy we have created; then, replace the
4206 copy with the SUBREG of the original shared reg,
4207 once again changed to the new mode. */
4208 propagate_for_debug (first
, last
, reg
, tempreg
,
4210 adjust_reg_mode (reg
, new_mode
);
4211 propagate_for_debug (first
, last
, tempreg
,
4212 lowpart_subreg (old_mode
, reg
, new_mode
),
4218 /* If we will be able to accept this, we have made a
4219 change to the destination of I3. This requires us to
4220 do a few adjustments. */
4222 if (changed_i3_dest
)
4224 PATTERN (i3
) = newpat
;
4225 adjust_for_new_dest (i3
);
4228 /* We now know that we can do this combination. Merge the insns and
4229 update the status of registers and LOG_LINKS. */
4231 if (undobuf
.other_insn
)
4235 PATTERN (undobuf
.other_insn
) = other_pat
;
4237 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4238 ensure that they are still valid. Then add any non-duplicate
4239 notes added by recog_for_combine. */
4240 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4242 next
= XEXP (note
, 1);
4244 if ((REG_NOTE_KIND (note
) == REG_DEAD
4245 && !reg_referenced_p (XEXP (note
, 0),
4246 PATTERN (undobuf
.other_insn
)))
4247 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4248 && !reg_set_p (XEXP (note
, 0),
4249 PATTERN (undobuf
.other_insn
)))
4250 /* Simply drop equal note since it may be no longer valid
4251 for other_insn. It may be possible to record that CC
4252 register is changed and only discard those notes, but
4253 in practice it's unnecessary complication and doesn't
4254 give any meaningful improvement.
4257 || REG_NOTE_KIND (note
) == REG_EQUAL
4258 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4259 remove_note (undobuf
.other_insn
, note
);
4262 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4263 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4270 struct insn_link
*link
;
4273 /* I3 now uses what used to be its destination and which is now
4274 I2's destination. This requires us to do a few adjustments. */
4275 PATTERN (i3
) = newpat
;
4276 adjust_for_new_dest (i3
);
4278 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4281 However, some later insn might be using I2's dest and have
4282 a LOG_LINK pointing at I3. We must remove this link.
4283 The simplest way to remove the link is to point it at I1,
4284 which we know will be a NOTE. */
4286 /* newi2pat is usually a SET here; however, recog_for_combine might
4287 have added some clobbers. */
4288 if (GET_CODE (newi2pat
) == PARALLEL
)
4289 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4291 ni2dest
= SET_DEST (newi2pat
);
4293 for (insn
= NEXT_INSN (i3
);
4294 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4295 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4296 insn
= NEXT_INSN (insn
))
4298 if (NONDEBUG_INSN_P (insn
)
4299 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4301 FOR_EACH_LOG_LINK (link
, insn
)
4302 if (link
->insn
== i3
)
4311 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4312 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4315 /* Compute which registers we expect to eliminate. newi2pat may be setting
4316 either i3dest or i2dest, so we must check it. */
4317 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4318 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4321 /* For i1, we need to compute both local elimination and global
4322 elimination information with respect to newi2pat because i1dest
4323 may be the same as i3dest, in which case newi2pat may be setting
4324 i1dest. Global information is used when distributing REG_DEAD
4325 note for i2 and i3, in which case it does matter if newi2pat sets
4328 Local information is used when distributing REG_DEAD note for i1,
4329 in which case it doesn't matter if newi2pat sets i1dest or not.
4330 See PR62151, if we have four insns combination:
4332 i1: r1 <- i1src (using r0)
4334 i2: r0 <- i2src (using r1)
4335 i3: r3 <- i3src (using r0)
4337 From i1's point of view, r0 is eliminated, no matter if it is set
4338 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4339 should be discarded.
4341 Note local information only affects cases in forms like "I1->I2->I3",
4342 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4343 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4345 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4348 rtx elim_i1
= (local_elim_i1
== 0
4349 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4351 /* Same case as i1. */
4352 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4354 rtx elim_i0
= (local_elim_i0
== 0
4355 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4358 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4360 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4361 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4363 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4365 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4367 /* Ensure that we do not have something that should not be shared but
4368 occurs multiple times in the new insns. Check this by first
4369 resetting all the `used' flags and then copying anything is shared. */
4371 reset_used_flags (i3notes
);
4372 reset_used_flags (i2notes
);
4373 reset_used_flags (i1notes
);
4374 reset_used_flags (i0notes
);
4375 reset_used_flags (newpat
);
4376 reset_used_flags (newi2pat
);
4377 if (undobuf
.other_insn
)
4378 reset_used_flags (PATTERN (undobuf
.other_insn
));
4380 i3notes
= copy_rtx_if_shared (i3notes
);
4381 i2notes
= copy_rtx_if_shared (i2notes
);
4382 i1notes
= copy_rtx_if_shared (i1notes
);
4383 i0notes
= copy_rtx_if_shared (i0notes
);
4384 newpat
= copy_rtx_if_shared (newpat
);
4385 newi2pat
= copy_rtx_if_shared (newi2pat
);
4386 if (undobuf
.other_insn
)
4387 reset_used_flags (PATTERN (undobuf
.other_insn
));
4389 INSN_CODE (i3
) = insn_code_number
;
4390 PATTERN (i3
) = newpat
;
4392 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4394 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4395 link
= XEXP (link
, 1))
4399 /* I2SRC must still be meaningful at this point. Some
4400 splitting operations can invalidate I2SRC, but those
4401 operations do not apply to calls. */
4403 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4407 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4410 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4415 if (undobuf
.other_insn
)
4416 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4418 /* We had one special case above where I2 had more than one set and
4419 we replaced a destination of one of those sets with the destination
4420 of I3. In that case, we have to update LOG_LINKS of insns later
4421 in this basic block. Note that this (expensive) case is rare.
4423 Also, in this case, we must pretend that all REG_NOTEs for I2
4424 actually came from I3, so that REG_UNUSED notes from I2 will be
4425 properly handled. */
4427 if (i3_subst_into_i2
)
4429 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4430 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4431 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4432 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4433 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4434 && ! find_reg_note (i2
, REG_UNUSED
,
4435 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4436 for (temp_insn
= NEXT_INSN (i2
);
4438 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4439 || BB_HEAD (this_basic_block
) != temp_insn
);
4440 temp_insn
= NEXT_INSN (temp_insn
))
4441 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4442 FOR_EACH_LOG_LINK (link
, temp_insn
)
4443 if (link
->insn
== i2
)
4449 while (XEXP (link
, 1))
4450 link
= XEXP (link
, 1);
4451 XEXP (link
, 1) = i2notes
;
4458 LOG_LINKS (i3
) = NULL
;
4460 LOG_LINKS (i2
) = NULL
;
4465 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4466 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4468 INSN_CODE (i2
) = i2_code_number
;
4469 PATTERN (i2
) = newi2pat
;
4473 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4474 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4476 SET_INSN_DELETED (i2
);
4481 LOG_LINKS (i1
) = NULL
;
4483 if (MAY_HAVE_DEBUG_INSNS
)
4484 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4486 SET_INSN_DELETED (i1
);
4491 LOG_LINKS (i0
) = NULL
;
4493 if (MAY_HAVE_DEBUG_INSNS
)
4494 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4496 SET_INSN_DELETED (i0
);
4499 /* Get death notes for everything that is now used in either I3 or
4500 I2 and used to die in a previous insn. If we built two new
4501 patterns, move from I1 to I2 then I2 to I3 so that we get the
4502 proper movement on registers that I2 modifies. */
4505 from_luid
= DF_INSN_LUID (i0
);
4507 from_luid
= DF_INSN_LUID (i1
);
4509 from_luid
= DF_INSN_LUID (i2
);
4511 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4512 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4514 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4516 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4517 elim_i2
, elim_i1
, elim_i0
);
4519 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4520 elim_i2
, elim_i1
, elim_i0
);
4522 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4523 elim_i2
, local_elim_i1
, local_elim_i0
);
4525 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4526 elim_i2
, elim_i1
, local_elim_i0
);
4528 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4529 elim_i2
, elim_i1
, elim_i0
);
4531 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4532 know these are REG_UNUSED and want them to go to the desired insn,
4533 so we always pass it as i3. */
4535 if (newi2pat
&& new_i2_notes
)
4536 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4540 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4543 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4544 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4545 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4546 in that case, it might delete I2. Similarly for I2 and I1.
4547 Show an additional death due to the REG_DEAD note we make here. If
4548 we discard it in distribute_notes, we will decrement it again. */
4552 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4553 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4554 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4557 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4558 elim_i2
, elim_i1
, elim_i0
);
4561 if (i2dest_in_i2src
)
4563 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4564 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4565 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4566 NULL_RTX
, NULL_RTX
);
4568 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4569 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4572 if (i1dest_in_i1src
)
4574 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4575 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4576 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4577 NULL_RTX
, NULL_RTX
);
4579 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4580 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4583 if (i0dest_in_i0src
)
4585 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4586 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4587 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4588 NULL_RTX
, NULL_RTX
);
4590 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4591 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4596 bitmap_iterator iter
;
4599 /* See comments above where we calculate the bitmap. */
4600 EXECUTE_IF_SET_IN_BITMAP ((bitmap
)new_regs_in_i2
,
4601 LAST_VIRTUAL_REGISTER
, i
, iter
)
4603 rtx reg
= regno_reg_rtx
[i
];
4605 for (other
= NEXT_INSN (i2
); other
!= i3
; other
= NEXT_INSN (other
))
4606 if (NONDEBUG_INSN_P (other
)
4607 && (reg_overlap_mentioned_p (reg
, PATTERN (other
))
4608 || (CALL_P (other
) && find_reg_fusage (other
, USE
, reg
))))
4612 "found extra use of reg %d at insn %d\n", i
,
4615 for (plink
= &LOG_LINKS (other
);
4617 plink
= &(*plink
)->next
)
4619 insn_link
*link
= *plink
;
4620 if (link
->regno
== i
)
4622 *plink
= link
->next
;
4623 link
->next
= i3links
;
4633 distribute_links (i3links
);
4634 distribute_links (i2links
);
4635 distribute_links (i1links
);
4636 distribute_links (i0links
);
4640 struct insn_link
*link
;
4641 rtx_insn
*i2_insn
= 0;
4642 rtx i2_val
= 0, set
;
4644 /* The insn that used to set this register doesn't exist, and
4645 this life of the register may not exist either. See if one of
4646 I3's links points to an insn that sets I2DEST. If it does,
4647 that is now the last known value for I2DEST. If we don't update
4648 this and I2 set the register to a value that depended on its old
4649 contents, we will get confused. If this insn is used, thing
4650 will be set correctly in combine_instructions. */
4651 FOR_EACH_LOG_LINK (link
, i3
)
4652 if ((set
= single_set (link
->insn
)) != 0
4653 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4654 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4656 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4658 /* If the reg formerly set in I2 died only once and that was in I3,
4659 zero its use count so it won't make `reload' do any work. */
4661 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4662 && ! i2dest_in_i2src
4663 && REGNO (i2dest
) < reg_n_sets_max
)
4664 INC_REG_N_SETS (REGNO (i2dest
), -1);
4667 if (i1
&& REG_P (i1dest
))
4669 struct insn_link
*link
;
4670 rtx_insn
*i1_insn
= 0;
4671 rtx i1_val
= 0, set
;
4673 FOR_EACH_LOG_LINK (link
, i3
)
4674 if ((set
= single_set (link
->insn
)) != 0
4675 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4676 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4678 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4681 && ! i1dest_in_i1src
4682 && REGNO (i1dest
) < reg_n_sets_max
)
4683 INC_REG_N_SETS (REGNO (i1dest
), -1);
4686 if (i0
&& REG_P (i0dest
))
4688 struct insn_link
*link
;
4689 rtx_insn
*i0_insn
= 0;
4690 rtx i0_val
= 0, set
;
4692 FOR_EACH_LOG_LINK (link
, i3
)
4693 if ((set
= single_set (link
->insn
)) != 0
4694 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4695 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4697 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4700 && ! i0dest_in_i0src
4701 && REGNO (i0dest
) < reg_n_sets_max
)
4702 INC_REG_N_SETS (REGNO (i0dest
), -1);
4705 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4706 been made to this insn. The order is important, because newi2pat
4707 can affect nonzero_bits of newpat. */
4709 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4710 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4713 if (undobuf
.other_insn
!= NULL_RTX
)
4717 fprintf (dump_file
, "modifying other_insn ");
4718 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4720 df_insn_rescan (undobuf
.other_insn
);
4723 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4727 fprintf (dump_file
, "modifying insn i0 ");
4728 dump_insn_slim (dump_file
, i0
);
4730 df_insn_rescan (i0
);
4733 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4737 fprintf (dump_file
, "modifying insn i1 ");
4738 dump_insn_slim (dump_file
, i1
);
4740 df_insn_rescan (i1
);
4743 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4747 fprintf (dump_file
, "modifying insn i2 ");
4748 dump_insn_slim (dump_file
, i2
);
4750 df_insn_rescan (i2
);
4753 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4757 fprintf (dump_file
, "modifying insn i3 ");
4758 dump_insn_slim (dump_file
, i3
);
4760 df_insn_rescan (i3
);
4763 /* Set new_direct_jump_p if a new return or simple jump instruction
4764 has been created. Adjust the CFG accordingly. */
4765 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4767 *new_direct_jump_p
= 1;
4768 mark_jump_label (PATTERN (i3
), i3
, 0);
4769 update_cfg_for_uncondjump (i3
);
4772 if (undobuf
.other_insn
!= NULL_RTX
4773 && (returnjump_p (undobuf
.other_insn
)
4774 || any_uncondjump_p (undobuf
.other_insn
)))
4776 *new_direct_jump_p
= 1;
4777 update_cfg_for_uncondjump (undobuf
.other_insn
);
4780 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4781 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4783 basic_block bb
= BLOCK_FOR_INSN (i3
);
4785 remove_edge (split_block (bb
, i3
));
4786 emit_barrier_after_bb (bb
);
4787 *new_direct_jump_p
= 1;
4790 if (undobuf
.other_insn
4791 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4792 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4794 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4796 remove_edge (split_block (bb
, undobuf
.other_insn
));
4797 emit_barrier_after_bb (bb
);
4798 *new_direct_jump_p
= 1;
4801 /* A noop might also need cleaning up of CFG, if it comes from the
4802 simplification of a jump. */
4804 && GET_CODE (newpat
) == SET
4805 && SET_SRC (newpat
) == pc_rtx
4806 && SET_DEST (newpat
) == pc_rtx
)
4808 *new_direct_jump_p
= 1;
4809 update_cfg_for_uncondjump (i3
);
4812 if (undobuf
.other_insn
!= NULL_RTX
4813 && JUMP_P (undobuf
.other_insn
)
4814 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4815 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4816 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4818 *new_direct_jump_p
= 1;
4819 update_cfg_for_uncondjump (undobuf
.other_insn
);
4822 combine_successes
++;
4825 if (added_links_insn
4826 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4827 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4828 return added_links_insn
;
4830 return newi2pat
? i2
: i3
;
4833 /* Get a marker for undoing to the current state. */
4836 get_undo_marker (void)
4838 return undobuf
.undos
;
4841 /* Undo the modifications up to the marker. */
4844 undo_to_marker (void *marker
)
4846 struct undo
*undo
, *next
;
4848 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4856 *undo
->where
.r
= undo
->old_contents
.r
;
4859 *undo
->where
.i
= undo
->old_contents
.i
;
4862 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4865 *undo
->where
.l
= undo
->old_contents
.l
;
4871 undo
->next
= undobuf
.frees
;
4872 undobuf
.frees
= undo
;
4875 undobuf
.undos
= (struct undo
*) marker
;
4878 /* Undo all the modifications recorded in undobuf. */
4886 /* We've committed to accepting the changes we made. Move all
4887 of the undos to the free list. */
4892 struct undo
*undo
, *next
;
4894 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4897 undo
->next
= undobuf
.frees
;
4898 undobuf
.frees
= undo
;
4903 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4904 where we have an arithmetic expression and return that point. LOC will
4907 try_combine will call this function to see if an insn can be split into
4911 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4914 enum rtx_code code
= GET_CODE (x
);
4916 unsigned HOST_WIDE_INT len
= 0;
4917 HOST_WIDE_INT pos
= 0;
4919 rtx inner
= NULL_RTX
;
4921 /* First special-case some codes. */
4925 #ifdef INSN_SCHEDULING
4926 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4928 if (MEM_P (SUBREG_REG (x
)))
4931 return find_split_point (&SUBREG_REG (x
), insn
, false);
4934 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4935 using LO_SUM and HIGH. */
4936 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4937 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4939 machine_mode address_mode
= get_address_mode (x
);
4942 gen_rtx_LO_SUM (address_mode
,
4943 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4945 return &XEXP (XEXP (x
, 0), 0);
4948 /* If we have a PLUS whose second operand is a constant and the
4949 address is not valid, perhaps will can split it up using
4950 the machine-specific way to split large constants. We use
4951 the first pseudo-reg (one of the virtual regs) as a placeholder;
4952 it will not remain in the result. */
4953 if (GET_CODE (XEXP (x
, 0)) == PLUS
4954 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4955 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4956 MEM_ADDR_SPACE (x
)))
4958 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4959 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4962 /* This should have produced two insns, each of which sets our
4963 placeholder. If the source of the second is a valid address,
4964 we can make put both sources together and make a split point
4968 && NEXT_INSN (seq
) != NULL_RTX
4969 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4970 && NONJUMP_INSN_P (seq
)
4971 && GET_CODE (PATTERN (seq
)) == SET
4972 && SET_DEST (PATTERN (seq
)) == reg
4973 && ! reg_mentioned_p (reg
,
4974 SET_SRC (PATTERN (seq
)))
4975 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4976 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4977 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4978 && memory_address_addr_space_p
4979 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4980 MEM_ADDR_SPACE (x
)))
4982 rtx src1
= SET_SRC (PATTERN (seq
));
4983 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4985 /* Replace the placeholder in SRC2 with SRC1. If we can
4986 find where in SRC2 it was placed, that can become our
4987 split point and we can replace this address with SRC2.
4988 Just try two obvious places. */
4990 src2
= replace_rtx (src2
, reg
, src1
);
4992 if (XEXP (src2
, 0) == src1
)
4993 split
= &XEXP (src2
, 0);
4994 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4995 && XEXP (XEXP (src2
, 0), 0) == src1
)
4996 split
= &XEXP (XEXP (src2
, 0), 0);
5000 SUBST (XEXP (x
, 0), src2
);
5005 /* If that didn't work, perhaps the first operand is complex and
5006 needs to be computed separately, so make a split point there.
5007 This will occur on machines that just support REG + CONST
5008 and have a constant moved through some previous computation. */
5010 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
5011 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5012 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5013 return &XEXP (XEXP (x
, 0), 0);
5016 /* If we have a PLUS whose first operand is complex, try computing it
5017 separately by making a split there. */
5018 if (GET_CODE (XEXP (x
, 0)) == PLUS
5019 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5021 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
5022 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5023 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5024 return &XEXP (XEXP (x
, 0), 0);
5028 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5029 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5030 we need to put the operand into a register. So split at that
5033 if (SET_DEST (x
) == cc0_rtx
5034 && GET_CODE (SET_SRC (x
)) != COMPARE
5035 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
5036 && !OBJECT_P (SET_SRC (x
))
5037 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
5038 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
5039 return &SET_SRC (x
);
5041 /* See if we can split SET_SRC as it stands. */
5042 split
= find_split_point (&SET_SRC (x
), insn
, true);
5043 if (split
&& split
!= &SET_SRC (x
))
5046 /* See if we can split SET_DEST as it stands. */
5047 split
= find_split_point (&SET_DEST (x
), insn
, false);
5048 if (split
&& split
!= &SET_DEST (x
))
5051 /* See if this is a bitfield assignment with everything constant. If
5052 so, this is an IOR of an AND, so split it into that. */
5053 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5054 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
5055 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5056 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5057 && CONST_INT_P (SET_SRC (x
))
5058 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5059 + INTVAL (XEXP (SET_DEST (x
), 2)))
5060 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
5061 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5063 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5064 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5065 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
5066 rtx dest
= XEXP (SET_DEST (x
), 0);
5067 machine_mode mode
= GET_MODE (dest
);
5068 unsigned HOST_WIDE_INT mask
5069 = (HOST_WIDE_INT_1U
<< len
) - 1;
5072 if (BITS_BIG_ENDIAN
)
5073 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
5075 or_mask
= gen_int_mode (src
<< pos
, mode
);
5078 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
5081 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
5083 simplify_gen_binary (IOR
, mode
,
5084 simplify_gen_binary (AND
, mode
,
5089 SUBST (SET_DEST (x
), dest
);
5091 split
= find_split_point (&SET_SRC (x
), insn
, true);
5092 if (split
&& split
!= &SET_SRC (x
))
5096 /* Otherwise, see if this is an operation that we can split into two.
5097 If so, try to split that. */
5098 code
= GET_CODE (SET_SRC (x
));
5103 /* If we are AND'ing with a large constant that is only a single
5104 bit and the result is only being used in a context where we
5105 need to know if it is zero or nonzero, replace it with a bit
5106 extraction. This will avoid the large constant, which might
5107 have taken more than one insn to make. If the constant were
5108 not a valid argument to the AND but took only one insn to make,
5109 this is no worse, but if it took more than one insn, it will
5112 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5113 && REG_P (XEXP (SET_SRC (x
), 0))
5114 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5115 && REG_P (SET_DEST (x
))
5116 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5117 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5118 && XEXP (*split
, 0) == SET_DEST (x
)
5119 && XEXP (*split
, 1) == const0_rtx
)
5121 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5122 XEXP (SET_SRC (x
), 0),
5123 pos
, NULL_RTX
, 1, 1, 0, 0);
5124 if (extraction
!= 0)
5126 SUBST (SET_SRC (x
), extraction
);
5127 return find_split_point (loc
, insn
, false);
5133 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5134 is known to be on, this can be converted into a NEG of a shift. */
5135 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5136 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5137 && 1 <= (pos
= exact_log2
5138 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5139 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5141 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5145 gen_rtx_LSHIFTRT (mode
,
5146 XEXP (SET_SRC (x
), 0),
5149 split
= find_split_point (&SET_SRC (x
), insn
, true);
5150 if (split
&& split
!= &SET_SRC (x
))
5156 inner
= XEXP (SET_SRC (x
), 0);
5158 /* We can't optimize if either mode is a partial integer
5159 mode as we don't know how many bits are significant
5161 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5162 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5166 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5172 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5173 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5175 inner
= XEXP (SET_SRC (x
), 0);
5176 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5177 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5179 if (BITS_BIG_ENDIAN
)
5180 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5181 unsignedp
= (code
== ZERO_EXTRACT
);
5190 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5192 machine_mode mode
= GET_MODE (SET_SRC (x
));
5194 /* For unsigned, we have a choice of a shift followed by an
5195 AND or two shifts. Use two shifts for field sizes where the
5196 constant might be too large. We assume here that we can
5197 always at least get 8-bit constants in an AND insn, which is
5198 true for every current RISC. */
5200 if (unsignedp
&& len
<= 8)
5202 unsigned HOST_WIDE_INT mask
5203 = (HOST_WIDE_INT_1U
<< len
) - 1;
5207 (mode
, gen_lowpart (mode
, inner
),
5209 gen_int_mode (mask
, mode
)));
5211 split
= find_split_point (&SET_SRC (x
), insn
, true);
5212 if (split
&& split
!= &SET_SRC (x
))
5219 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5220 gen_rtx_ASHIFT (mode
,
5221 gen_lowpart (mode
, inner
),
5222 GEN_INT (GET_MODE_PRECISION (mode
)
5224 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5226 split
= find_split_point (&SET_SRC (x
), insn
, true);
5227 if (split
&& split
!= &SET_SRC (x
))
5232 /* See if this is a simple operation with a constant as the second
5233 operand. It might be that this constant is out of range and hence
5234 could be used as a split point. */
5235 if (BINARY_P (SET_SRC (x
))
5236 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5237 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5238 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5239 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5240 return &XEXP (SET_SRC (x
), 1);
5242 /* Finally, see if this is a simple operation with its first operand
5243 not in a register. The operation might require this operand in a
5244 register, so return it as a split point. We can always do this
5245 because if the first operand were another operation, we would have
5246 already found it as a split point. */
5247 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5248 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5249 return &XEXP (SET_SRC (x
), 0);
5255 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5256 it is better to write this as (not (ior A B)) so we can split it.
5257 Similarly for IOR. */
5258 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5261 gen_rtx_NOT (GET_MODE (x
),
5262 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5264 XEXP (XEXP (x
, 0), 0),
5265 XEXP (XEXP (x
, 1), 0))));
5266 return find_split_point (loc
, insn
, set_src
);
5269 /* Many RISC machines have a large set of logical insns. If the
5270 second operand is a NOT, put it first so we will try to split the
5271 other operand first. */
5272 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5274 rtx tem
= XEXP (x
, 0);
5275 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5276 SUBST (XEXP (x
, 1), tem
);
5282 /* Canonicalization can produce (minus A (mult B C)), where C is a
5283 constant. It may be better to try splitting (plus (mult B -C) A)
5284 instead if this isn't a multiply by a power of two. */
5285 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5286 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5287 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5289 machine_mode mode
= GET_MODE (x
);
5290 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5291 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5292 SUBST (*loc
, gen_rtx_PLUS (mode
,
5294 XEXP (XEXP (x
, 1), 0),
5295 gen_int_mode (other_int
,
5298 return find_split_point (loc
, insn
, set_src
);
5301 /* Split at a multiply-accumulate instruction. However if this is
5302 the SET_SRC, we likely do not have such an instruction and it's
5303 worthless to try this split. */
5305 && (GET_CODE (XEXP (x
, 0)) == MULT
5306 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5307 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5314 /* Otherwise, select our actions depending on our rtx class. */
5315 switch (GET_RTX_CLASS (code
))
5317 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5319 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5324 case RTX_COMM_ARITH
:
5326 case RTX_COMM_COMPARE
:
5327 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5332 /* Some machines have (and (shift ...) ...) insns. If X is not
5333 an AND, but XEXP (X, 0) is, use it as our split point. */
5334 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5335 return &XEXP (x
, 0);
5337 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5343 /* Otherwise, we don't have a split point. */
5348 /* Throughout X, replace FROM with TO, and return the result.
5349 The result is TO if X is FROM;
5350 otherwise the result is X, but its contents may have been modified.
5351 If they were modified, a record was made in undobuf so that
5352 undo_all will (among other things) return X to its original state.
5354 If the number of changes necessary is too much to record to undo,
5355 the excess changes are not made, so the result is invalid.
5356 The changes already made can still be undone.
5357 undobuf.num_undo is incremented for such changes, so by testing that
5358 the caller can tell whether the result is valid.
5360 `n_occurrences' is incremented each time FROM is replaced.
5362 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5364 IN_COND is nonzero if we are at the top level of a condition.
5366 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5367 by copying if `n_occurrences' is nonzero. */
5370 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5372 enum rtx_code code
= GET_CODE (x
);
5373 machine_mode op0_mode
= VOIDmode
;
5378 /* Two expressions are equal if they are identical copies of a shared
5379 RTX or if they are both registers with the same register number
5382 #define COMBINE_RTX_EQUAL_P(X,Y) \
5384 || (REG_P (X) && REG_P (Y) \
5385 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5387 /* Do not substitute into clobbers of regs -- this will never result in
5389 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5392 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5395 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5398 /* If X and FROM are the same register but different modes, they
5399 will not have been seen as equal above. However, the log links code
5400 will make a LOG_LINKS entry for that case. If we do nothing, we
5401 will try to rerecognize our original insn and, when it succeeds,
5402 we will delete the feeding insn, which is incorrect.
5404 So force this insn not to match in this (rare) case. */
5405 if (! in_dest
&& code
== REG
&& REG_P (from
)
5406 && reg_overlap_mentioned_p (x
, from
))
5407 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5409 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5410 of which may contain things that can be combined. */
5411 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5414 /* It is possible to have a subexpression appear twice in the insn.
5415 Suppose that FROM is a register that appears within TO.
5416 Then, after that subexpression has been scanned once by `subst',
5417 the second time it is scanned, TO may be found. If we were
5418 to scan TO here, we would find FROM within it and create a
5419 self-referent rtl structure which is completely wrong. */
5420 if (COMBINE_RTX_EQUAL_P (x
, to
))
5423 /* Parallel asm_operands need special attention because all of the
5424 inputs are shared across the arms. Furthermore, unsharing the
5425 rtl results in recognition failures. Failure to handle this case
5426 specially can result in circular rtl.
5428 Solve this by doing a normal pass across the first entry of the
5429 parallel, and only processing the SET_DESTs of the subsequent
5432 if (code
== PARALLEL
5433 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5434 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5436 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5438 /* If this substitution failed, this whole thing fails. */
5439 if (GET_CODE (new_rtx
) == CLOBBER
5440 && XEXP (new_rtx
, 0) == const0_rtx
)
5443 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5445 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5447 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5450 && GET_CODE (dest
) != CC0
5451 && GET_CODE (dest
) != PC
)
5453 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5455 /* If this substitution failed, this whole thing fails. */
5456 if (GET_CODE (new_rtx
) == CLOBBER
5457 && XEXP (new_rtx
, 0) == const0_rtx
)
5460 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5466 len
= GET_RTX_LENGTH (code
);
5467 fmt
= GET_RTX_FORMAT (code
);
5469 /* We don't need to process a SET_DEST that is a register, CC0,
5470 or PC, so set up to skip this common case. All other cases
5471 where we want to suppress replacing something inside a
5472 SET_SRC are handled via the IN_DEST operand. */
5474 && (REG_P (SET_DEST (x
))
5475 || GET_CODE (SET_DEST (x
)) == CC0
5476 || GET_CODE (SET_DEST (x
)) == PC
))
5479 /* Trying to simplify the operands of a widening MULT is not likely
5480 to create RTL matching a machine insn. */
5482 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5483 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5484 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5485 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5486 && REG_P (XEXP (XEXP (x
, 0), 0))
5487 && REG_P (XEXP (XEXP (x
, 1), 0))
5492 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5495 op0_mode
= GET_MODE (XEXP (x
, 0));
5497 for (i
= 0; i
< len
; i
++)
5502 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5504 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5506 new_rtx
= (unique_copy
&& n_occurrences
5507 ? copy_rtx (to
) : to
);
5512 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5515 /* If this substitution failed, this whole thing
5517 if (GET_CODE (new_rtx
) == CLOBBER
5518 && XEXP (new_rtx
, 0) == const0_rtx
)
5522 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5525 else if (fmt
[i
] == 'e')
5527 /* If this is a register being set, ignore it. */
5528 new_rtx
= XEXP (x
, i
);
5531 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5533 || code
== STRICT_LOW_PART
))
5536 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5538 /* In general, don't install a subreg involving two
5539 modes not tieable. It can worsen register
5540 allocation, and can even make invalid reload
5541 insns, since the reg inside may need to be copied
5542 from in the outside mode, and that may be invalid
5543 if it is an fp reg copied in integer mode.
5545 We allow two exceptions to this: It is valid if
5546 it is inside another SUBREG and the mode of that
5547 SUBREG and the mode of the inside of TO is
5548 tieable and it is valid if X is a SET that copies
5551 if (GET_CODE (to
) == SUBREG
5552 && ! MODES_TIEABLE_P (GET_MODE (to
),
5553 GET_MODE (SUBREG_REG (to
)))
5554 && ! (code
== SUBREG
5555 && MODES_TIEABLE_P (GET_MODE (x
),
5556 GET_MODE (SUBREG_REG (to
))))
5560 && XEXP (x
, 0) == cc0_rtx
))))
5561 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5565 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5566 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5569 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5571 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5575 /* If we are in a SET_DEST, suppress most cases unless we
5576 have gone inside a MEM, in which case we want to
5577 simplify the address. We assume here that things that
5578 are actually part of the destination have their inner
5579 parts in the first expression. This is true for SUBREG,
5580 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5581 things aside from REG and MEM that should appear in a
5583 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5585 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5586 || code
== ZERO_EXTRACT
))
5589 code
== IF_THEN_ELSE
&& i
== 0,
5592 /* If we found that we will have to reject this combination,
5593 indicate that by returning the CLOBBER ourselves, rather than
5594 an expression containing it. This will speed things up as
5595 well as prevent accidents where two CLOBBERs are considered
5596 to be equal, thus producing an incorrect simplification. */
5598 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5601 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5603 machine_mode mode
= GET_MODE (x
);
5605 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5606 GET_MODE (SUBREG_REG (x
)),
5609 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5611 else if (CONST_SCALAR_INT_P (new_rtx
)
5612 && GET_CODE (x
) == ZERO_EXTEND
)
5614 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5615 new_rtx
, GET_MODE (XEXP (x
, 0)));
5619 SUBST (XEXP (x
, i
), new_rtx
);
5624 /* Check if we are loading something from the constant pool via float
5625 extension; in this case we would undo compress_float_constant
5626 optimization and degenerate constant load to an immediate value. */
5627 if (GET_CODE (x
) == FLOAT_EXTEND
5628 && MEM_P (XEXP (x
, 0))
5629 && MEM_READONLY_P (XEXP (x
, 0)))
5631 rtx tmp
= avoid_constant_pool_reference (x
);
5636 /* Try to simplify X. If the simplification changed the code, it is likely
5637 that further simplification will help, so loop, but limit the number
5638 of repetitions that will be performed. */
5640 for (i
= 0; i
< 4; i
++)
5642 /* If X is sufficiently simple, don't bother trying to do anything
5644 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5645 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5647 if (GET_CODE (x
) == code
)
5650 code
= GET_CODE (x
);
5652 /* We no longer know the original mode of operand 0 since we
5653 have changed the form of X) */
5654 op0_mode
= VOIDmode
;
5660 /* If X is a commutative operation whose operands are not in the canonical
5661 order, use substitutions to swap them. */
5664 maybe_swap_commutative_operands (rtx x
)
5666 if (COMMUTATIVE_ARITH_P (x
)
5667 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5669 rtx temp
= XEXP (x
, 0);
5670 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5671 SUBST (XEXP (x
, 1), temp
);
5675 /* Simplify X, a piece of RTL. We just operate on the expression at the
5676 outer level; call `subst' to simplify recursively. Return the new
5679 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5680 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5684 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5687 enum rtx_code code
= GET_CODE (x
);
5688 machine_mode mode
= GET_MODE (x
);
5692 /* If this is a commutative operation, put a constant last and a complex
5693 expression first. We don't need to do this for comparisons here. */
5694 maybe_swap_commutative_operands (x
);
5696 /* Try to fold this expression in case we have constants that weren't
5699 switch (GET_RTX_CLASS (code
))
5702 if (op0_mode
== VOIDmode
)
5703 op0_mode
= GET_MODE (XEXP (x
, 0));
5704 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5707 case RTX_COMM_COMPARE
:
5709 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5710 if (cmp_mode
== VOIDmode
)
5712 cmp_mode
= GET_MODE (XEXP (x
, 1));
5713 if (cmp_mode
== VOIDmode
)
5714 cmp_mode
= op0_mode
;
5716 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5717 XEXP (x
, 0), XEXP (x
, 1));
5720 case RTX_COMM_ARITH
:
5722 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5724 case RTX_BITFIELD_OPS
:
5726 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5727 XEXP (x
, 1), XEXP (x
, 2));
5736 code
= GET_CODE (temp
);
5737 op0_mode
= VOIDmode
;
5738 mode
= GET_MODE (temp
);
5741 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5742 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5743 things. Check for cases where both arms are testing the same
5746 Don't do anything if all operands are very simple. */
5749 && ((!OBJECT_P (XEXP (x
, 0))
5750 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5751 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5752 || (!OBJECT_P (XEXP (x
, 1))
5753 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5754 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5756 && (!OBJECT_P (XEXP (x
, 0))
5757 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5758 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5760 rtx cond
, true_rtx
, false_rtx
;
5762 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5764 /* If everything is a comparison, what we have is highly unlikely
5765 to be simpler, so don't use it. */
5766 && ! (COMPARISON_P (x
)
5767 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5769 rtx cop1
= const0_rtx
;
5770 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5772 if (cond_code
== NE
&& COMPARISON_P (cond
))
5775 /* Simplify the alternative arms; this may collapse the true and
5776 false arms to store-flag values. Be careful to use copy_rtx
5777 here since true_rtx or false_rtx might share RTL with x as a
5778 result of the if_then_else_cond call above. */
5779 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5780 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5782 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5783 is unlikely to be simpler. */
5784 if (general_operand (true_rtx
, VOIDmode
)
5785 && general_operand (false_rtx
, VOIDmode
))
5787 enum rtx_code reversed
;
5789 /* Restarting if we generate a store-flag expression will cause
5790 us to loop. Just drop through in this case. */
5792 /* If the result values are STORE_FLAG_VALUE and zero, we can
5793 just make the comparison operation. */
5794 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5795 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5797 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5798 && ((reversed
= reversed_comparison_code_parts
5799 (cond_code
, cond
, cop1
, NULL
))
5801 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5804 /* Likewise, we can make the negate of a comparison operation
5805 if the result values are - STORE_FLAG_VALUE and zero. */
5806 else if (CONST_INT_P (true_rtx
)
5807 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5808 && false_rtx
== const0_rtx
)
5809 x
= simplify_gen_unary (NEG
, mode
,
5810 simplify_gen_relational (cond_code
,
5814 else if (CONST_INT_P (false_rtx
)
5815 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5816 && true_rtx
== const0_rtx
5817 && ((reversed
= reversed_comparison_code_parts
5818 (cond_code
, cond
, cop1
, NULL
))
5820 x
= simplify_gen_unary (NEG
, mode
,
5821 simplify_gen_relational (reversed
,
5826 return gen_rtx_IF_THEN_ELSE (mode
,
5827 simplify_gen_relational (cond_code
,
5832 true_rtx
, false_rtx
);
5834 code
= GET_CODE (x
);
5835 op0_mode
= VOIDmode
;
5840 /* First see if we can apply the inverse distributive law. */
5841 if (code
== PLUS
|| code
== MINUS
5842 || code
== AND
|| code
== IOR
|| code
== XOR
)
5844 x
= apply_distributive_law (x
);
5845 code
= GET_CODE (x
);
5846 op0_mode
= VOIDmode
;
5849 /* If CODE is an associative operation not otherwise handled, see if we
5850 can associate some operands. This can win if they are constants or
5851 if they are logically related (i.e. (a & b) & a). */
5852 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5853 || code
== AND
|| code
== IOR
|| code
== XOR
5854 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5855 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5856 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5858 if (GET_CODE (XEXP (x
, 0)) == code
)
5860 rtx other
= XEXP (XEXP (x
, 0), 0);
5861 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5862 rtx inner_op1
= XEXP (x
, 1);
5865 /* Make sure we pass the constant operand if any as the second
5866 one if this is a commutative operation. */
5867 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5868 std::swap (inner_op0
, inner_op1
);
5869 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5870 : code
== DIV
? MULT
5872 mode
, inner_op0
, inner_op1
);
5874 /* For commutative operations, try the other pair if that one
5876 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5878 other
= XEXP (XEXP (x
, 0), 1);
5879 inner
= simplify_binary_operation (code
, mode
,
5880 XEXP (XEXP (x
, 0), 0),
5885 return simplify_gen_binary (code
, mode
, other
, inner
);
5889 /* A little bit of algebraic simplification here. */
5893 /* Ensure that our address has any ASHIFTs converted to MULT in case
5894 address-recognizing predicates are called later. */
5895 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5896 SUBST (XEXP (x
, 0), temp
);
5900 if (op0_mode
== VOIDmode
)
5901 op0_mode
= GET_MODE (SUBREG_REG (x
));
5903 /* See if this can be moved to simplify_subreg. */
5904 if (CONSTANT_P (SUBREG_REG (x
))
5905 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5906 /* Don't call gen_lowpart if the inner mode
5907 is VOIDmode and we cannot simplify it, as SUBREG without
5908 inner mode is invalid. */
5909 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5910 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5911 return gen_lowpart (mode
, SUBREG_REG (x
));
5913 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5917 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5922 /* If op is known to have all lower bits zero, the result is zero. */
5924 && SCALAR_INT_MODE_P (mode
)
5925 && SCALAR_INT_MODE_P (op0_mode
)
5926 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5927 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5928 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5929 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5930 & GET_MODE_MASK (mode
)) == 0)
5931 return CONST0_RTX (mode
);
5934 /* Don't change the mode of the MEM if that would change the meaning
5936 if (MEM_P (SUBREG_REG (x
))
5937 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5938 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5939 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5940 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5942 /* Note that we cannot do any narrowing for non-constants since
5943 we might have been counting on using the fact that some bits were
5944 zero. We now do this in the SET. */
5949 temp
= expand_compound_operation (XEXP (x
, 0));
5951 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5952 replaced by (lshiftrt X C). This will convert
5953 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5955 if (GET_CODE (temp
) == ASHIFTRT
5956 && CONST_INT_P (XEXP (temp
, 1))
5957 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5958 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5959 INTVAL (XEXP (temp
, 1)));
5961 /* If X has only a single bit that might be nonzero, say, bit I, convert
5962 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5963 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5964 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5965 or a SUBREG of one since we'd be making the expression more
5966 complex if it was just a register. */
5969 && ! (GET_CODE (temp
) == SUBREG
5970 && REG_P (SUBREG_REG (temp
)))
5971 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5973 rtx temp1
= simplify_shift_const
5974 (NULL_RTX
, ASHIFTRT
, mode
,
5975 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5976 GET_MODE_PRECISION (mode
) - 1 - i
),
5977 GET_MODE_PRECISION (mode
) - 1 - i
);
5979 /* If all we did was surround TEMP with the two shifts, we
5980 haven't improved anything, so don't use it. Otherwise,
5981 we are better off with TEMP1. */
5982 if (GET_CODE (temp1
) != ASHIFTRT
5983 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5984 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5990 /* We can't handle truncation to a partial integer mode here
5991 because we don't know the real bitsize of the partial
5993 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5996 if (HWI_COMPUTABLE_MODE_P (mode
))
5998 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5999 GET_MODE_MASK (mode
), 0));
6001 /* We can truncate a constant value and return it. */
6002 if (CONST_INT_P (XEXP (x
, 0)))
6003 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
6005 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6006 whose value is a comparison can be replaced with a subreg if
6007 STORE_FLAG_VALUE permits. */
6008 if (HWI_COMPUTABLE_MODE_P (mode
)
6009 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
6010 && (temp
= get_last_value (XEXP (x
, 0)))
6011 && COMPARISON_P (temp
))
6012 return gen_lowpart (mode
, XEXP (x
, 0));
6016 /* (const (const X)) can become (const X). Do it this way rather than
6017 returning the inner CONST since CONST can be shared with a
6019 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6020 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6024 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6025 can add in an offset. find_split_point will split this address up
6026 again if it doesn't match. */
6027 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6028 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6033 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6034 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6035 bit-field and can be replaced by either a sign_extend or a
6036 sign_extract. The `and' may be a zero_extend and the two
6037 <c>, -<c> constants may be reversed. */
6038 if (GET_CODE (XEXP (x
, 0)) == XOR
6039 && CONST_INT_P (XEXP (x
, 1))
6040 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6041 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6042 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6043 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6044 && HWI_COMPUTABLE_MODE_P (mode
)
6045 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6046 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6047 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6048 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6049 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6050 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
6051 == (unsigned int) i
+ 1))))
6052 return simplify_shift_const
6053 (NULL_RTX
, ASHIFTRT
, mode
,
6054 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6055 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6056 GET_MODE_PRECISION (mode
) - (i
+ 1)),
6057 GET_MODE_PRECISION (mode
) - (i
+ 1));
6059 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6060 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6061 the bitsize of the mode - 1. This allows simplification of
6062 "a = (b & 8) == 0;" */
6063 if (XEXP (x
, 1) == constm1_rtx
6064 && !REG_P (XEXP (x
, 0))
6065 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6066 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6067 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
6068 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
6069 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6070 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
6071 GET_MODE_PRECISION (mode
) - 1),
6072 GET_MODE_PRECISION (mode
) - 1);
6074 /* If we are adding two things that have no bits in common, convert
6075 the addition into an IOR. This will often be further simplified,
6076 for example in cases like ((a & 1) + (a & 2)), which can
6079 if (HWI_COMPUTABLE_MODE_P (mode
)
6080 && (nonzero_bits (XEXP (x
, 0), mode
)
6081 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6083 /* Try to simplify the expression further. */
6084 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6085 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
6087 /* If we could, great. If not, do not go ahead with the IOR
6088 replacement, since PLUS appears in many special purpose
6089 address arithmetic instructions. */
6090 if (GET_CODE (temp
) != CLOBBER
6091 && (GET_CODE (temp
) != IOR
6092 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6093 || XEXP (temp
, 1) != XEXP (x
, 1))
6094 && (XEXP (temp
, 0) != XEXP (x
, 1)
6095 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6099 /* Canonicalize x + x into x << 1. */
6100 if (GET_MODE_CLASS (mode
) == MODE_INT
6101 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6102 && !side_effects_p (XEXP (x
, 0)))
6103 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6108 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6109 (and <foo> (const_int pow2-1)) */
6110 if (GET_CODE (XEXP (x
, 1)) == AND
6111 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6112 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6113 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6114 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
6115 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6119 /* If we have (mult (plus A B) C), apply the distributive law and then
6120 the inverse distributive law to see if things simplify. This
6121 occurs mostly in addresses, often when unrolling loops. */
6123 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6125 rtx result
= distribute_and_simplify_rtx (x
, 0);
6130 /* Try simplify a*(b/c) as (a*b)/c. */
6131 if (FLOAT_MODE_P (mode
) && flag_associative_math
6132 && GET_CODE (XEXP (x
, 0)) == DIV
)
6134 rtx tem
= simplify_binary_operation (MULT
, mode
,
6135 XEXP (XEXP (x
, 0), 0),
6138 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6143 /* If this is a divide by a power of two, treat it as a shift if
6144 its first operand is a shift. */
6145 if (CONST_INT_P (XEXP (x
, 1))
6146 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6147 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6148 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6149 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6150 || GET_CODE (XEXP (x
, 0)) == ROTATE
6151 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6152 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
6156 case GT
: case GTU
: case GE
: case GEU
:
6157 case LT
: case LTU
: case LE
: case LEU
:
6158 case UNEQ
: case LTGT
:
6159 case UNGT
: case UNGE
:
6160 case UNLT
: case UNLE
:
6161 case UNORDERED
: case ORDERED
:
6162 /* If the first operand is a condition code, we can't do anything
6164 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6165 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6166 && ! CC0_P (XEXP (x
, 0))))
6168 rtx op0
= XEXP (x
, 0);
6169 rtx op1
= XEXP (x
, 1);
6170 enum rtx_code new_code
;
6172 if (GET_CODE (op0
) == COMPARE
)
6173 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6175 /* Simplify our comparison, if possible. */
6176 new_code
= simplify_comparison (code
, &op0
, &op1
);
6178 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6179 if only the low-order bit is possibly nonzero in X (such as when
6180 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6181 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6182 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6185 Remove any ZERO_EXTRACT we made when thinking this was a
6186 comparison. It may now be simpler to use, e.g., an AND. If a
6187 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6188 the call to make_compound_operation in the SET case.
6190 Don't apply these optimizations if the caller would
6191 prefer a comparison rather than a value.
6192 E.g., for the condition in an IF_THEN_ELSE most targets need
6193 an explicit comparison. */
6198 else if (STORE_FLAG_VALUE
== 1
6199 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6200 && op1
== const0_rtx
6201 && mode
== GET_MODE (op0
)
6202 && nonzero_bits (op0
, mode
) == 1)
6203 return gen_lowpart (mode
,
6204 expand_compound_operation (op0
));
6206 else if (STORE_FLAG_VALUE
== 1
6207 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6208 && op1
== const0_rtx
6209 && mode
== GET_MODE (op0
)
6210 && (num_sign_bit_copies (op0
, mode
)
6211 == GET_MODE_PRECISION (mode
)))
6213 op0
= expand_compound_operation (op0
);
6214 return simplify_gen_unary (NEG
, mode
,
6215 gen_lowpart (mode
, op0
),
6219 else if (STORE_FLAG_VALUE
== 1
6220 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6221 && op1
== const0_rtx
6222 && mode
== GET_MODE (op0
)
6223 && nonzero_bits (op0
, mode
) == 1)
6225 op0
= expand_compound_operation (op0
);
6226 return simplify_gen_binary (XOR
, mode
,
6227 gen_lowpart (mode
, op0
),
6231 else if (STORE_FLAG_VALUE
== 1
6232 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6233 && op1
== const0_rtx
6234 && mode
== GET_MODE (op0
)
6235 && (num_sign_bit_copies (op0
, mode
)
6236 == GET_MODE_PRECISION (mode
)))
6238 op0
= expand_compound_operation (op0
);
6239 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6242 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6247 else if (STORE_FLAG_VALUE
== -1
6248 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6249 && op1
== const0_rtx
6250 && mode
== GET_MODE (op0
)
6251 && (num_sign_bit_copies (op0
, mode
)
6252 == GET_MODE_PRECISION (mode
)))
6253 return gen_lowpart (mode
,
6254 expand_compound_operation (op0
));
6256 else if (STORE_FLAG_VALUE
== -1
6257 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6258 && op1
== const0_rtx
6259 && mode
== GET_MODE (op0
)
6260 && nonzero_bits (op0
, mode
) == 1)
6262 op0
= expand_compound_operation (op0
);
6263 return simplify_gen_unary (NEG
, mode
,
6264 gen_lowpart (mode
, op0
),
6268 else if (STORE_FLAG_VALUE
== -1
6269 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6270 && op1
== const0_rtx
6271 && mode
== GET_MODE (op0
)
6272 && (num_sign_bit_copies (op0
, mode
)
6273 == GET_MODE_PRECISION (mode
)))
6275 op0
= expand_compound_operation (op0
);
6276 return simplify_gen_unary (NOT
, mode
,
6277 gen_lowpart (mode
, op0
),
6281 /* If X is 0/1, (eq X 0) is X-1. */
6282 else if (STORE_FLAG_VALUE
== -1
6283 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6284 && op1
== const0_rtx
6285 && mode
== GET_MODE (op0
)
6286 && nonzero_bits (op0
, mode
) == 1)
6288 op0
= expand_compound_operation (op0
);
6289 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6292 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6293 one bit that might be nonzero, we can convert (ne x 0) to
6294 (ashift x c) where C puts the bit in the sign bit. Remove any
6295 AND with STORE_FLAG_VALUE when we are done, since we are only
6296 going to test the sign bit. */
6297 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6298 && HWI_COMPUTABLE_MODE_P (mode
)
6299 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6300 && op1
== const0_rtx
6301 && mode
== GET_MODE (op0
)
6302 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6304 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6305 expand_compound_operation (op0
),
6306 GET_MODE_PRECISION (mode
) - 1 - i
);
6307 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6313 /* If the code changed, return a whole new comparison.
6314 We also need to avoid using SUBST in cases where
6315 simplify_comparison has widened a comparison with a CONST_INT,
6316 since in that case the wider CONST_INT may fail the sanity
6317 checks in do_SUBST. */
6318 if (new_code
!= code
6319 || (CONST_INT_P (op1
)
6320 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6321 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6322 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6324 /* Otherwise, keep this operation, but maybe change its operands.
6325 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6326 SUBST (XEXP (x
, 0), op0
);
6327 SUBST (XEXP (x
, 1), op1
);
6332 return simplify_if_then_else (x
);
6338 /* If we are processing SET_DEST, we are done. */
6342 return expand_compound_operation (x
);
6345 return simplify_set (x
);
6349 return simplify_logical (x
);
6356 /* If this is a shift by a constant amount, simplify it. */
6357 if (CONST_INT_P (XEXP (x
, 1)))
6358 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6359 INTVAL (XEXP (x
, 1)));
6361 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6363 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6365 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6377 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6380 simplify_if_then_else (rtx x
)
6382 machine_mode mode
= GET_MODE (x
);
6383 rtx cond
= XEXP (x
, 0);
6384 rtx true_rtx
= XEXP (x
, 1);
6385 rtx false_rtx
= XEXP (x
, 2);
6386 enum rtx_code true_code
= GET_CODE (cond
);
6387 int comparison_p
= COMPARISON_P (cond
);
6390 enum rtx_code false_code
;
6393 /* Simplify storing of the truth value. */
6394 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6395 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6396 XEXP (cond
, 0), XEXP (cond
, 1));
6398 /* Also when the truth value has to be reversed. */
6400 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6401 && (reversed
= reversed_comparison (cond
, mode
)))
6404 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6405 in it is being compared against certain values. Get the true and false
6406 comparisons and see if that says anything about the value of each arm. */
6409 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6411 && REG_P (XEXP (cond
, 0)))
6414 rtx from
= XEXP (cond
, 0);
6415 rtx true_val
= XEXP (cond
, 1);
6416 rtx false_val
= true_val
;
6419 /* If FALSE_CODE is EQ, swap the codes and arms. */
6421 if (false_code
== EQ
)
6423 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6424 std::swap (true_rtx
, false_rtx
);
6427 /* If we are comparing against zero and the expression being tested has
6428 only a single bit that might be nonzero, that is its value when it is
6429 not equal to zero. Similarly if it is known to be -1 or 0. */
6431 if (true_code
== EQ
&& true_val
== const0_rtx
6432 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6435 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6437 else if (true_code
== EQ
&& true_val
== const0_rtx
6438 && (num_sign_bit_copies (from
, GET_MODE (from
))
6439 == GET_MODE_PRECISION (GET_MODE (from
))))
6442 false_val
= constm1_rtx
;
6445 /* Now simplify an arm if we know the value of the register in the
6446 branch and it is used in the arm. Be careful due to the potential
6447 of locally-shared RTL. */
6449 if (reg_mentioned_p (from
, true_rtx
))
6450 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6452 pc_rtx
, pc_rtx
, 0, 0, 0);
6453 if (reg_mentioned_p (from
, false_rtx
))
6454 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6456 pc_rtx
, pc_rtx
, 0, 0, 0);
6458 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6459 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6461 true_rtx
= XEXP (x
, 1);
6462 false_rtx
= XEXP (x
, 2);
6463 true_code
= GET_CODE (cond
);
6466 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6467 reversed, do so to avoid needing two sets of patterns for
6468 subtract-and-branch insns. Similarly if we have a constant in the true
6469 arm, the false arm is the same as the first operand of the comparison, or
6470 the false arm is more complicated than the true arm. */
6473 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6474 && (true_rtx
== pc_rtx
6475 || (CONSTANT_P (true_rtx
)
6476 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6477 || true_rtx
== const0_rtx
6478 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6479 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6480 && !OBJECT_P (false_rtx
))
6481 || reg_mentioned_p (true_rtx
, false_rtx
)
6482 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6484 true_code
= reversed_comparison_code (cond
, NULL
);
6485 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6486 SUBST (XEXP (x
, 1), false_rtx
);
6487 SUBST (XEXP (x
, 2), true_rtx
);
6489 std::swap (true_rtx
, false_rtx
);
6492 /* It is possible that the conditional has been simplified out. */
6493 true_code
= GET_CODE (cond
);
6494 comparison_p
= COMPARISON_P (cond
);
6497 /* If the two arms are identical, we don't need the comparison. */
6499 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6502 /* Convert a == b ? b : a to "a". */
6503 if (true_code
== EQ
&& ! side_effects_p (cond
)
6504 && !HONOR_NANS (mode
)
6505 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6506 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6508 else if (true_code
== NE
&& ! side_effects_p (cond
)
6509 && !HONOR_NANS (mode
)
6510 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6511 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6514 /* Look for cases where we have (abs x) or (neg (abs X)). */
6516 if (GET_MODE_CLASS (mode
) == MODE_INT
6518 && XEXP (cond
, 1) == const0_rtx
6519 && GET_CODE (false_rtx
) == NEG
6520 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6521 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6522 && ! side_effects_p (true_rtx
))
6527 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6531 simplify_gen_unary (NEG
, mode
,
6532 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6538 /* Look for MIN or MAX. */
6540 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6542 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6543 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6544 && ! side_effects_p (cond
))
6549 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6552 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6555 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6558 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6563 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6564 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6565 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6566 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6567 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6568 neither 1 or -1, but it isn't worth checking for. */
6570 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6572 && GET_MODE_CLASS (mode
) == MODE_INT
6573 && ! side_effects_p (x
))
6575 rtx t
= make_compound_operation (true_rtx
, SET
);
6576 rtx f
= make_compound_operation (false_rtx
, SET
);
6577 rtx cond_op0
= XEXP (cond
, 0);
6578 rtx cond_op1
= XEXP (cond
, 1);
6579 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6580 machine_mode m
= mode
;
6581 rtx z
= 0, c1
= NULL_RTX
;
6583 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6584 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6585 || GET_CODE (t
) == ASHIFT
6586 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6587 && rtx_equal_p (XEXP (t
, 0), f
))
6588 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6590 /* If an identity-zero op is commutative, check whether there
6591 would be a match if we swapped the operands. */
6592 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6593 || GET_CODE (t
) == XOR
)
6594 && rtx_equal_p (XEXP (t
, 1), f
))
6595 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6596 else if (GET_CODE (t
) == SIGN_EXTEND
6597 && (GET_CODE (XEXP (t
, 0)) == PLUS
6598 || GET_CODE (XEXP (t
, 0)) == MINUS
6599 || GET_CODE (XEXP (t
, 0)) == IOR
6600 || GET_CODE (XEXP (t
, 0)) == XOR
6601 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6602 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6603 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6604 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6605 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6606 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6607 && (num_sign_bit_copies (f
, GET_MODE (f
))
6609 (GET_MODE_PRECISION (mode
)
6610 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6612 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6613 extend_op
= SIGN_EXTEND
;
6614 m
= GET_MODE (XEXP (t
, 0));
6616 else if (GET_CODE (t
) == SIGN_EXTEND
6617 && (GET_CODE (XEXP (t
, 0)) == PLUS
6618 || GET_CODE (XEXP (t
, 0)) == IOR
6619 || GET_CODE (XEXP (t
, 0)) == XOR
)
6620 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6621 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6622 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6623 && (num_sign_bit_copies (f
, GET_MODE (f
))
6625 (GET_MODE_PRECISION (mode
)
6626 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6628 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6629 extend_op
= SIGN_EXTEND
;
6630 m
= GET_MODE (XEXP (t
, 0));
6632 else if (GET_CODE (t
) == ZERO_EXTEND
6633 && (GET_CODE (XEXP (t
, 0)) == PLUS
6634 || GET_CODE (XEXP (t
, 0)) == MINUS
6635 || GET_CODE (XEXP (t
, 0)) == IOR
6636 || GET_CODE (XEXP (t
, 0)) == XOR
6637 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6638 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6639 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6640 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6641 && HWI_COMPUTABLE_MODE_P (mode
)
6642 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6643 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6644 && ((nonzero_bits (f
, GET_MODE (f
))
6645 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6648 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6649 extend_op
= ZERO_EXTEND
;
6650 m
= GET_MODE (XEXP (t
, 0));
6652 else if (GET_CODE (t
) == ZERO_EXTEND
6653 && (GET_CODE (XEXP (t
, 0)) == PLUS
6654 || GET_CODE (XEXP (t
, 0)) == IOR
6655 || GET_CODE (XEXP (t
, 0)) == XOR
)
6656 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6657 && HWI_COMPUTABLE_MODE_P (mode
)
6658 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6659 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6660 && ((nonzero_bits (f
, GET_MODE (f
))
6661 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6664 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6665 extend_op
= ZERO_EXTEND
;
6666 m
= GET_MODE (XEXP (t
, 0));
6671 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6672 cond_op0
, cond_op1
),
6673 pc_rtx
, pc_rtx
, 0, 0, 0);
6674 temp
= simplify_gen_binary (MULT
, m
, temp
,
6675 simplify_gen_binary (MULT
, m
, c1
,
6677 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6678 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6680 if (extend_op
!= UNKNOWN
)
6681 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6687 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6688 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6689 negation of a single bit, we can convert this operation to a shift. We
6690 can actually do this more generally, but it doesn't seem worth it. */
6692 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6693 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6694 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6695 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6696 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6697 == GET_MODE_PRECISION (mode
))
6698 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6700 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6701 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6703 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6704 non-zero bit in A is C1. */
6705 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6706 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6707 && INTEGRAL_MODE_P (GET_MODE (XEXP (cond
, 0)))
6708 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6709 == nonzero_bits (XEXP (cond
, 0), GET_MODE (XEXP (cond
, 0)))
6710 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6712 rtx val
= XEXP (cond
, 0);
6713 enum machine_mode val_mode
= GET_MODE (val
);
6714 if (val_mode
== mode
)
6716 else if (GET_MODE_PRECISION (val_mode
) < GET_MODE_PRECISION (mode
))
6717 return simplify_gen_unary (ZERO_EXTEND
, mode
, val
, val_mode
);
6723 /* Simplify X, a SET expression. Return the new expression. */
6726 simplify_set (rtx x
)
6728 rtx src
= SET_SRC (x
);
6729 rtx dest
= SET_DEST (x
);
6731 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6732 rtx_insn
*other_insn
;
6735 /* (set (pc) (return)) gets written as (return). */
6736 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6739 /* Now that we know for sure which bits of SRC we are using, see if we can
6740 simplify the expression for the object knowing that we only need the
6743 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6745 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6746 SUBST (SET_SRC (x
), src
);
6749 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6750 the comparison result and try to simplify it unless we already have used
6751 undobuf.other_insn. */
6752 if ((GET_MODE_CLASS (mode
) == MODE_CC
6753 || GET_CODE (src
) == COMPARE
6755 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6756 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6757 && COMPARISON_P (*cc_use
)
6758 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6760 enum rtx_code old_code
= GET_CODE (*cc_use
);
6761 enum rtx_code new_code
;
6763 int other_changed
= 0;
6764 rtx inner_compare
= NULL_RTX
;
6765 machine_mode compare_mode
= GET_MODE (dest
);
6767 if (GET_CODE (src
) == COMPARE
)
6769 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6770 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6772 inner_compare
= op0
;
6773 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6777 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6779 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6782 new_code
= old_code
;
6783 else if (!CONSTANT_P (tmp
))
6785 new_code
= GET_CODE (tmp
);
6786 op0
= XEXP (tmp
, 0);
6787 op1
= XEXP (tmp
, 1);
6791 rtx pat
= PATTERN (other_insn
);
6792 undobuf
.other_insn
= other_insn
;
6793 SUBST (*cc_use
, tmp
);
6795 /* Attempt to simplify CC user. */
6796 if (GET_CODE (pat
) == SET
)
6798 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6799 if (new_rtx
!= NULL_RTX
)
6800 SUBST (SET_SRC (pat
), new_rtx
);
6803 /* Convert X into a no-op move. */
6804 SUBST (SET_DEST (x
), pc_rtx
);
6805 SUBST (SET_SRC (x
), pc_rtx
);
6809 /* Simplify our comparison, if possible. */
6810 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6812 #ifdef SELECT_CC_MODE
6813 /* If this machine has CC modes other than CCmode, check to see if we
6814 need to use a different CC mode here. */
6815 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6816 compare_mode
= GET_MODE (op0
);
6817 else if (inner_compare
6818 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6819 && new_code
== old_code
6820 && op0
== XEXP (inner_compare
, 0)
6821 && op1
== XEXP (inner_compare
, 1))
6822 compare_mode
= GET_MODE (inner_compare
);
6824 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6826 /* If the mode changed, we have to change SET_DEST, the mode in the
6827 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6828 a hard register, just build new versions with the proper mode. If it
6829 is a pseudo, we lose unless it is only time we set the pseudo, in
6830 which case we can safely change its mode. */
6831 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6833 if (can_change_dest_mode (dest
, 0, compare_mode
))
6835 unsigned int regno
= REGNO (dest
);
6838 if (regno
< FIRST_PSEUDO_REGISTER
)
6839 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6842 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6843 new_dest
= regno_reg_rtx
[regno
];
6846 SUBST (SET_DEST (x
), new_dest
);
6847 SUBST (XEXP (*cc_use
, 0), new_dest
);
6853 #endif /* SELECT_CC_MODE */
6855 /* If the code changed, we have to build a new comparison in
6856 undobuf.other_insn. */
6857 if (new_code
!= old_code
)
6859 int other_changed_previously
= other_changed
;
6860 unsigned HOST_WIDE_INT mask
;
6861 rtx old_cc_use
= *cc_use
;
6863 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6867 /* If the only change we made was to change an EQ into an NE or
6868 vice versa, OP0 has only one bit that might be nonzero, and OP1
6869 is zero, check if changing the user of the condition code will
6870 produce a valid insn. If it won't, we can keep the original code
6871 in that insn by surrounding our operation with an XOR. */
6873 if (((old_code
== NE
&& new_code
== EQ
)
6874 || (old_code
== EQ
&& new_code
== NE
))
6875 && ! other_changed_previously
&& op1
== const0_rtx
6876 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6877 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6879 rtx pat
= PATTERN (other_insn
), note
= 0;
6881 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6882 && ! check_asm_operands (pat
)))
6884 *cc_use
= old_cc_use
;
6887 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6895 undobuf
.other_insn
= other_insn
;
6897 /* Don't generate a compare of a CC with 0, just use that CC. */
6898 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6900 SUBST (SET_SRC (x
), op0
);
6903 /* Otherwise, if we didn't previously have the same COMPARE we
6904 want, create it from scratch. */
6905 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6906 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6908 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6914 /* Get SET_SRC in a form where we have placed back any
6915 compound expressions. Then do the checks below. */
6916 src
= make_compound_operation (src
, SET
);
6917 SUBST (SET_SRC (x
), src
);
6920 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6921 and X being a REG or (subreg (reg)), we may be able to convert this to
6922 (set (subreg:m2 x) (op)).
6924 We can always do this if M1 is narrower than M2 because that means that
6925 we only care about the low bits of the result.
6927 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6928 perform a narrower operation than requested since the high-order bits will
6929 be undefined. On machine where it is defined, this transformation is safe
6930 as long as M1 and M2 have the same number of words. */
6932 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6933 && !OBJECT_P (SUBREG_REG (src
))
6934 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6936 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6937 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6938 && (WORD_REGISTER_OPERATIONS
6939 || (GET_MODE_SIZE (GET_MODE (src
))
6940 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6941 #ifdef CANNOT_CHANGE_MODE_CLASS
6942 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6943 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6944 GET_MODE (SUBREG_REG (src
)),
6948 || (GET_CODE (dest
) == SUBREG
6949 && REG_P (SUBREG_REG (dest
)))))
6951 SUBST (SET_DEST (x
),
6952 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6954 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6956 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6959 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6962 && GET_CODE (src
) == SUBREG
6963 && subreg_lowpart_p (src
)
6964 && (GET_MODE_PRECISION (GET_MODE (src
))
6965 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6967 rtx inner
= SUBREG_REG (src
);
6968 machine_mode inner_mode
= GET_MODE (inner
);
6970 /* Here we make sure that we don't have a sign bit on. */
6971 if (val_signbit_known_clear_p (GET_MODE (src
),
6972 nonzero_bits (inner
, inner_mode
)))
6974 SUBST (SET_SRC (x
), inner
);
6979 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6980 would require a paradoxical subreg. Replace the subreg with a
6981 zero_extend to avoid the reload that would otherwise be required. */
6983 enum rtx_code extend_op
;
6984 if (paradoxical_subreg_p (src
)
6985 && MEM_P (SUBREG_REG (src
))
6986 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6989 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6994 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6995 are comparing an item known to be 0 or -1 against 0, use a logical
6996 operation instead. Check for one of the arms being an IOR of the other
6997 arm with some value. We compute three terms to be IOR'ed together. In
6998 practice, at most two will be nonzero. Then we do the IOR's. */
7000 if (GET_CODE (dest
) != PC
7001 && GET_CODE (src
) == IF_THEN_ELSE
7002 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
7003 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7004 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7005 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
7006 && (!HAVE_conditional_move
7007 || ! can_conditionally_move_p (GET_MODE (src
)))
7008 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
7009 GET_MODE (XEXP (XEXP (src
, 0), 0)))
7010 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
7011 && ! side_effects_p (src
))
7013 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7014 ? XEXP (src
, 1) : XEXP (src
, 2));
7015 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7016 ? XEXP (src
, 2) : XEXP (src
, 1));
7017 rtx term1
= const0_rtx
, term2
, term3
;
7019 if (GET_CODE (true_rtx
) == IOR
7020 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7021 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7022 else if (GET_CODE (true_rtx
) == IOR
7023 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7024 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7025 else if (GET_CODE (false_rtx
) == IOR
7026 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7027 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7028 else if (GET_CODE (false_rtx
) == IOR
7029 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7030 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7032 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
7033 XEXP (XEXP (src
, 0), 0), true_rtx
);
7034 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
7035 simplify_gen_unary (NOT
, GET_MODE (src
),
7036 XEXP (XEXP (src
, 0), 0),
7041 simplify_gen_binary (IOR
, GET_MODE (src
),
7042 simplify_gen_binary (IOR
, GET_MODE (src
),
7049 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7050 whole thing fail. */
7051 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7053 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7056 /* Convert this into a field assignment operation, if possible. */
7057 return make_field_assignment (x
);
7060 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7064 simplify_logical (rtx x
)
7066 machine_mode mode
= GET_MODE (x
);
7067 rtx op0
= XEXP (x
, 0);
7068 rtx op1
= XEXP (x
, 1);
7070 switch (GET_CODE (x
))
7073 /* We can call simplify_and_const_int only if we don't lose
7074 any (sign) bits when converting INTVAL (op1) to
7075 "unsigned HOST_WIDE_INT". */
7076 if (CONST_INT_P (op1
)
7077 && (HWI_COMPUTABLE_MODE_P (mode
)
7078 || INTVAL (op1
) > 0))
7080 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7081 if (GET_CODE (x
) != AND
)
7088 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7089 apply the distributive law and then the inverse distributive
7090 law to see if things simplify. */
7091 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7093 rtx result
= distribute_and_simplify_rtx (x
, 0);
7097 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7099 rtx result
= distribute_and_simplify_rtx (x
, 1);
7106 /* If we have (ior (and A B) C), apply the distributive law and then
7107 the inverse distributive law to see if things simplify. */
7109 if (GET_CODE (op0
) == AND
)
7111 rtx result
= distribute_and_simplify_rtx (x
, 0);
7116 if (GET_CODE (op1
) == AND
)
7118 rtx result
= distribute_and_simplify_rtx (x
, 1);
7131 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7132 operations" because they can be replaced with two more basic operations.
7133 ZERO_EXTEND is also considered "compound" because it can be replaced with
7134 an AND operation, which is simpler, though only one operation.
7136 The function expand_compound_operation is called with an rtx expression
7137 and will convert it to the appropriate shifts and AND operations,
7138 simplifying at each stage.
7140 The function make_compound_operation is called to convert an expression
7141 consisting of shifts and ANDs into the equivalent compound expression.
7142 It is the inverse of this function, loosely speaking. */
7145 expand_compound_operation (rtx x
)
7147 unsigned HOST_WIDE_INT pos
= 0, len
;
7149 unsigned int modewidth
;
7152 switch (GET_CODE (x
))
7158 /* We can't necessarily use a const_int for a multiword mode;
7159 it depends on implicitly extending the value.
7160 Since we don't know the right way to extend it,
7161 we can't tell whether the implicit way is right.
7163 Even for a mode that is no wider than a const_int,
7164 we can't win, because we need to sign extend one of its bits through
7165 the rest of it, and we don't know which bit. */
7166 if (CONST_INT_P (XEXP (x
, 0)))
7169 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7170 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7171 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7172 reloaded. If not for that, MEM's would very rarely be safe.
7174 Reject MODEs bigger than a word, because we might not be able
7175 to reference a two-register group starting with an arbitrary register
7176 (and currently gen_lowpart might crash for a SUBREG). */
7178 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7181 /* Reject MODEs that aren't scalar integers because turning vector
7182 or complex modes into shifts causes problems. */
7184 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7187 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7188 /* If the inner object has VOIDmode (the only way this can happen
7189 is if it is an ASM_OPERANDS), we can't do anything since we don't
7190 know how much masking to do. */
7202 /* If the operand is a CLOBBER, just return it. */
7203 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7206 if (!CONST_INT_P (XEXP (x
, 1))
7207 || !CONST_INT_P (XEXP (x
, 2))
7208 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7211 /* Reject MODEs that aren't scalar integers because turning vector
7212 or complex modes into shifts causes problems. */
7214 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7217 len
= INTVAL (XEXP (x
, 1));
7218 pos
= INTVAL (XEXP (x
, 2));
7220 /* This should stay within the object being extracted, fail otherwise. */
7221 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7224 if (BITS_BIG_ENDIAN
)
7225 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7232 /* Convert sign extension to zero extension, if we know that the high
7233 bit is not set, as this is easier to optimize. It will be converted
7234 back to cheaper alternative in make_extraction. */
7235 if (GET_CODE (x
) == SIGN_EXTEND
7236 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7237 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7238 & ~(((unsigned HOST_WIDE_INT
)
7239 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7243 machine_mode mode
= GET_MODE (x
);
7244 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7245 rtx temp2
= expand_compound_operation (temp
);
7247 /* Make sure this is a profitable operation. */
7248 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7249 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7251 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7252 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7258 /* We can optimize some special cases of ZERO_EXTEND. */
7259 if (GET_CODE (x
) == ZERO_EXTEND
)
7261 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7262 know that the last value didn't have any inappropriate bits
7264 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7265 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7266 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7267 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7268 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7269 return XEXP (XEXP (x
, 0), 0);
7271 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7272 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7273 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7274 && subreg_lowpart_p (XEXP (x
, 0))
7275 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7276 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7277 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7278 return SUBREG_REG (XEXP (x
, 0));
7280 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7281 is a comparison and STORE_FLAG_VALUE permits. This is like
7282 the first case, but it works even when GET_MODE (x) is larger
7283 than HOST_WIDE_INT. */
7284 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7285 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7286 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7287 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7288 <= HOST_BITS_PER_WIDE_INT
)
7289 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7290 return XEXP (XEXP (x
, 0), 0);
7292 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7293 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7294 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7295 && subreg_lowpart_p (XEXP (x
, 0))
7296 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7297 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7298 <= HOST_BITS_PER_WIDE_INT
)
7299 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7300 return SUBREG_REG (XEXP (x
, 0));
7304 /* If we reach here, we want to return a pair of shifts. The inner
7305 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7306 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7307 logical depending on the value of UNSIGNEDP.
7309 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7310 converted into an AND of a shift.
7312 We must check for the case where the left shift would have a negative
7313 count. This can happen in a case like (x >> 31) & 255 on machines
7314 that can't shift by a constant. On those machines, we would first
7315 combine the shift with the AND to produce a variable-position
7316 extraction. Then the constant of 31 would be substituted in
7317 to produce such a position. */
7319 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7320 if (modewidth
>= pos
+ len
)
7322 machine_mode mode
= GET_MODE (x
);
7323 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7324 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7326 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7327 tem
, modewidth
- pos
- len
);
7328 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7329 mode
, tem
, modewidth
- len
);
7331 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7332 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7333 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7336 (HOST_WIDE_INT_1U
<< len
) - 1);
7338 /* Any other cases we can't handle. */
7341 /* If we couldn't do this for some reason, return the original
7343 if (GET_CODE (tem
) == CLOBBER
)
7349 /* X is a SET which contains an assignment of one object into
7350 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7351 or certain SUBREGS). If possible, convert it into a series of
7354 We half-heartedly support variable positions, but do not at all
7355 support variable lengths. */
7358 expand_field_assignment (const_rtx x
)
7361 rtx pos
; /* Always counts from low bit. */
7363 rtx mask
, cleared
, masked
;
7364 machine_mode compute_mode
;
7366 /* Loop until we find something we can't simplify. */
7369 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7370 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7372 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7373 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7374 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7376 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7377 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7379 inner
= XEXP (SET_DEST (x
), 0);
7380 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7381 pos
= XEXP (SET_DEST (x
), 2);
7383 /* A constant position should stay within the width of INNER. */
7384 if (CONST_INT_P (pos
)
7385 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7388 if (BITS_BIG_ENDIAN
)
7390 if (CONST_INT_P (pos
))
7391 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7393 else if (GET_CODE (pos
) == MINUS
7394 && CONST_INT_P (XEXP (pos
, 1))
7395 && (INTVAL (XEXP (pos
, 1))
7396 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7397 /* If position is ADJUST - X, new position is X. */
7398 pos
= XEXP (pos
, 0);
7401 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7402 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7403 gen_int_mode (prec
- len
,
7410 /* A SUBREG between two modes that occupy the same numbers of words
7411 can be done by moving the SUBREG to the source. */
7412 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7413 /* We need SUBREGs to compute nonzero_bits properly. */
7414 && nonzero_sign_valid
7415 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7416 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7417 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7418 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7420 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7422 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7429 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7430 inner
= SUBREG_REG (inner
);
7432 compute_mode
= GET_MODE (inner
);
7434 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7435 if (! SCALAR_INT_MODE_P (compute_mode
))
7439 /* Don't do anything for vector or complex integral types. */
7440 if (! FLOAT_MODE_P (compute_mode
))
7443 /* Try to find an integral mode to pun with. */
7444 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7445 if (imode
== BLKmode
)
7448 compute_mode
= imode
;
7449 inner
= gen_lowpart (imode
, inner
);
7452 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7453 if (len
>= HOST_BITS_PER_WIDE_INT
)
7456 /* Don't try to compute in too wide unsupported modes. */
7457 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7460 /* Now compute the equivalent expression. Make a copy of INNER
7461 for the SET_DEST in case it is a MEM into which we will substitute;
7462 we don't want shared RTL in that case. */
7463 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7465 cleared
= simplify_gen_binary (AND
, compute_mode
,
7466 simplify_gen_unary (NOT
, compute_mode
,
7467 simplify_gen_binary (ASHIFT
,
7472 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7473 simplify_gen_binary (
7475 gen_lowpart (compute_mode
, SET_SRC (x
)),
7479 x
= gen_rtx_SET (copy_rtx (inner
),
7480 simplify_gen_binary (IOR
, compute_mode
,
7487 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7488 it is an RTX that represents the (variable) starting position; otherwise,
7489 POS is the (constant) starting bit position. Both are counted from the LSB.
7491 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7493 IN_DEST is nonzero if this is a reference in the destination of a SET.
7494 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7495 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7498 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7499 ZERO_EXTRACT should be built even for bits starting at bit 0.
7501 MODE is the desired mode of the result (if IN_DEST == 0).
7503 The result is an RTX for the extraction or NULL_RTX if the target
7507 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7508 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7509 int in_dest
, int in_compare
)
7511 /* This mode describes the size of the storage area
7512 to fetch the overall value from. Within that, we
7513 ignore the POS lowest bits, etc. */
7514 machine_mode is_mode
= GET_MODE (inner
);
7515 machine_mode inner_mode
;
7516 machine_mode wanted_inner_mode
;
7517 machine_mode wanted_inner_reg_mode
= word_mode
;
7518 machine_mode pos_mode
= word_mode
;
7519 machine_mode extraction_mode
= word_mode
;
7520 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7522 rtx orig_pos_rtx
= pos_rtx
;
7523 HOST_WIDE_INT orig_pos
;
7525 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7526 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7528 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7530 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7531 consider just the QI as the memory to extract from.
7532 The subreg adds or removes high bits; its mode is
7533 irrelevant to the meaning of this extraction,
7534 since POS and LEN count from the lsb. */
7535 if (MEM_P (SUBREG_REG (inner
)))
7536 is_mode
= GET_MODE (SUBREG_REG (inner
));
7537 inner
= SUBREG_REG (inner
);
7539 else if (GET_CODE (inner
) == ASHIFT
7540 && CONST_INT_P (XEXP (inner
, 1))
7541 && pos_rtx
== 0 && pos
== 0
7542 && len
> UINTVAL (XEXP (inner
, 1)))
7544 /* We're extracting the least significant bits of an rtx
7545 (ashift X (const_int C)), where LEN > C. Extract the
7546 least significant (LEN - C) bits of X, giving an rtx
7547 whose mode is MODE, then shift it left C times. */
7548 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7549 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7550 unsignedp
, in_dest
, in_compare
);
7552 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7554 else if (GET_CODE (inner
) == TRUNCATE
)
7555 inner
= XEXP (inner
, 0);
7557 inner_mode
= GET_MODE (inner
);
7559 /* See if this can be done without an extraction. We never can if the
7560 width of the field is not the same as that of some integer mode. For
7561 registers, we can only avoid the extraction if the position is at the
7562 low-order bit and this is either not in the destination or we have the
7563 appropriate STRICT_LOW_PART operation available.
7565 For MEM, we can avoid an extract if the field starts on an appropriate
7566 boundary and we can change the mode of the memory reference. */
7568 if (tmode
!= BLKmode
7569 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7571 && (pos
== 0 || REG_P (inner
))
7572 && (inner_mode
== tmode
7574 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7575 || reg_truncated_to_mode (tmode
, inner
))
7578 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7579 || (MEM_P (inner
) && pos_rtx
== 0
7581 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7582 : BITS_PER_UNIT
)) == 0
7583 /* We can't do this if we are widening INNER_MODE (it
7584 may not be aligned, for one thing). */
7585 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7586 && (inner_mode
== tmode
7587 || (! mode_dependent_address_p (XEXP (inner
, 0),
7588 MEM_ADDR_SPACE (inner
))
7589 && ! MEM_VOLATILE_P (inner
))))))
7591 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7592 field. If the original and current mode are the same, we need not
7593 adjust the offset. Otherwise, we do if bytes big endian.
7595 If INNER is not a MEM, get a piece consisting of just the field
7596 of interest (in this case POS % BITS_PER_WORD must be 0). */
7600 HOST_WIDE_INT offset
;
7602 /* POS counts from lsb, but make OFFSET count in memory order. */
7603 if (BYTES_BIG_ENDIAN
)
7604 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7606 offset
= pos
/ BITS_PER_UNIT
;
7608 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7610 else if (REG_P (inner
))
7612 if (tmode
!= inner_mode
)
7614 /* We can't call gen_lowpart in a DEST since we
7615 always want a SUBREG (see below) and it would sometimes
7616 return a new hard register. */
7619 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7621 if (WORDS_BIG_ENDIAN
7622 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7623 final_word
= ((GET_MODE_SIZE (inner_mode
)
7624 - GET_MODE_SIZE (tmode
))
7625 / UNITS_PER_WORD
) - final_word
;
7627 final_word
*= UNITS_PER_WORD
;
7628 if (BYTES_BIG_ENDIAN
&&
7629 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7630 final_word
+= (GET_MODE_SIZE (inner_mode
)
7631 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7633 /* Avoid creating invalid subregs, for example when
7634 simplifying (x>>32)&255. */
7635 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7638 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7641 new_rtx
= gen_lowpart (tmode
, inner
);
7647 new_rtx
= force_to_mode (inner
, tmode
,
7648 len
>= HOST_BITS_PER_WIDE_INT
7650 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7652 /* If this extraction is going into the destination of a SET,
7653 make a STRICT_LOW_PART unless we made a MEM. */
7656 return (MEM_P (new_rtx
) ? new_rtx
7657 : (GET_CODE (new_rtx
) != SUBREG
7658 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7659 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7664 if (CONST_SCALAR_INT_P (new_rtx
))
7665 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7666 mode
, new_rtx
, tmode
);
7668 /* If we know that no extraneous bits are set, and that the high
7669 bit is not set, convert the extraction to the cheaper of
7670 sign and zero extension, that are equivalent in these cases. */
7671 if (flag_expensive_optimizations
7672 && (HWI_COMPUTABLE_MODE_P (tmode
)
7673 && ((nonzero_bits (new_rtx
, tmode
)
7674 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7677 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7678 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7680 /* Prefer ZERO_EXTENSION, since it gives more information to
7682 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7683 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7688 /* Otherwise, sign- or zero-extend unless we already are in the
7691 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7695 /* Unless this is a COMPARE or we have a funny memory reference,
7696 don't do anything with zero-extending field extracts starting at
7697 the low-order bit since they are simple AND operations. */
7698 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7699 && ! in_compare
&& unsignedp
)
7702 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7703 if the position is not a constant and the length is not 1. In all
7704 other cases, we would only be going outside our object in cases when
7705 an original shift would have been undefined. */
7707 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7708 || (pos_rtx
!= 0 && len
!= 1)))
7711 enum extraction_pattern pattern
= (in_dest
? EP_insv
7712 : unsignedp
? EP_extzv
: EP_extv
);
7714 /* If INNER is not from memory, we want it to have the mode of a register
7715 extraction pattern's structure operand, or word_mode if there is no
7716 such pattern. The same applies to extraction_mode and pos_mode
7717 and their respective operands.
7719 For memory, assume that the desired extraction_mode and pos_mode
7720 are the same as for a register operation, since at present we don't
7721 have named patterns for aligned memory structures. */
7722 struct extraction_insn insn
;
7723 if (get_best_reg_extraction_insn (&insn
, pattern
,
7724 GET_MODE_BITSIZE (inner_mode
), mode
))
7726 wanted_inner_reg_mode
= insn
.struct_mode
;
7727 pos_mode
= insn
.pos_mode
;
7728 extraction_mode
= insn
.field_mode
;
7731 /* Never narrow an object, since that might not be safe. */
7733 if (mode
!= VOIDmode
7734 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7735 extraction_mode
= mode
;
7738 wanted_inner_mode
= wanted_inner_reg_mode
;
7741 /* Be careful not to go beyond the extracted object and maintain the
7742 natural alignment of the memory. */
7743 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7744 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7745 > GET_MODE_BITSIZE (wanted_inner_mode
))
7747 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7748 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7754 if (BITS_BIG_ENDIAN
)
7756 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7757 BITS_BIG_ENDIAN style. If position is constant, compute new
7758 position. Otherwise, build subtraction.
7759 Note that POS is relative to the mode of the original argument.
7760 If it's a MEM we need to recompute POS relative to that.
7761 However, if we're extracting from (or inserting into) a register,
7762 we want to recompute POS relative to wanted_inner_mode. */
7763 int width
= (MEM_P (inner
)
7764 ? GET_MODE_BITSIZE (is_mode
)
7765 : GET_MODE_BITSIZE (wanted_inner_mode
));
7768 pos
= width
- len
- pos
;
7771 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7772 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7774 /* POS may be less than 0 now, but we check for that below.
7775 Note that it can only be less than 0 if !MEM_P (inner). */
7778 /* If INNER has a wider mode, and this is a constant extraction, try to
7779 make it smaller and adjust the byte to point to the byte containing
7781 if (wanted_inner_mode
!= VOIDmode
7782 && inner_mode
!= wanted_inner_mode
7784 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7786 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7787 && ! MEM_VOLATILE_P (inner
))
7791 /* The computations below will be correct if the machine is big
7792 endian in both bits and bytes or little endian in bits and bytes.
7793 If it is mixed, we must adjust. */
7795 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7796 adjust OFFSET to compensate. */
7797 if (BYTES_BIG_ENDIAN
7798 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7799 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7801 /* We can now move to the desired byte. */
7802 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7803 * GET_MODE_SIZE (wanted_inner_mode
);
7804 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7806 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7807 && is_mode
!= wanted_inner_mode
)
7808 offset
= (GET_MODE_SIZE (is_mode
)
7809 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7811 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7814 /* If INNER is not memory, get it into the proper mode. If we are changing
7815 its mode, POS must be a constant and smaller than the size of the new
7817 else if (!MEM_P (inner
))
7819 /* On the LHS, don't create paradoxical subregs implicitely truncating
7820 the register unless TRULY_NOOP_TRUNCATION. */
7822 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7826 if (GET_MODE (inner
) != wanted_inner_mode
7828 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7834 inner
= force_to_mode (inner
, wanted_inner_mode
,
7836 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7838 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7843 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7844 have to zero extend. Otherwise, we can just use a SUBREG. */
7846 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7848 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7849 GET_MODE (pos_rtx
));
7851 /* If we know that no extraneous bits are set, and that the high
7852 bit is not set, convert extraction to cheaper one - either
7853 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7855 if (flag_expensive_optimizations
7856 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7857 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7858 & ~(((unsigned HOST_WIDE_INT
)
7859 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7863 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7864 GET_MODE (pos_rtx
));
7866 /* Prefer ZERO_EXTENSION, since it gives more information to
7868 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7869 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7875 /* Make POS_RTX unless we already have it and it is correct. If we don't
7876 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7878 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7879 pos_rtx
= orig_pos_rtx
;
7881 else if (pos_rtx
== 0)
7882 pos_rtx
= GEN_INT (pos
);
7884 /* Make the required operation. See if we can use existing rtx. */
7885 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7886 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7888 new_rtx
= gen_lowpart (mode
, new_rtx
);
7893 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7894 with any other operations in X. Return X without that shift if so. */
7897 extract_left_shift (rtx x
, int count
)
7899 enum rtx_code code
= GET_CODE (x
);
7900 machine_mode mode
= GET_MODE (x
);
7906 /* This is the shift itself. If it is wide enough, we will return
7907 either the value being shifted if the shift count is equal to
7908 COUNT or a shift for the difference. */
7909 if (CONST_INT_P (XEXP (x
, 1))
7910 && INTVAL (XEXP (x
, 1)) >= count
)
7911 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7912 INTVAL (XEXP (x
, 1)) - count
);
7916 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7917 return simplify_gen_unary (code
, mode
, tem
, mode
);
7921 case PLUS
: case IOR
: case XOR
: case AND
:
7922 /* If we can safely shift this constant and we find the inner shift,
7923 make a new operation. */
7924 if (CONST_INT_P (XEXP (x
, 1))
7925 && (UINTVAL (XEXP (x
, 1))
7926 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7927 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7929 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7930 return simplify_gen_binary (code
, mode
, tem
,
7931 gen_int_mode (val
, mode
));
7942 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7943 level of the expression and MODE is its mode. IN_CODE is as for
7944 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7945 that should be used when recursing on operands of *X_PTR.
7947 There are two possible actions:
7949 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7950 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7952 - Return a new rtx, which the caller returns directly. */
7955 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7956 enum rtx_code in_code
,
7957 enum rtx_code
*next_code_ptr
)
7960 enum rtx_code next_code
= *next_code_ptr
;
7961 enum rtx_code code
= GET_CODE (x
);
7962 int mode_width
= GET_MODE_PRECISION (mode
);
7967 bool equality_comparison
= false;
7971 equality_comparison
= true;
7975 /* Process depending on the code of this operation. If NEW is set
7976 nonzero, it will be returned. */
7981 /* Convert shifts by constants into multiplications if inside
7983 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7984 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7985 && INTVAL (XEXP (x
, 1)) >= 0)
7987 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7988 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7990 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7991 if (GET_CODE (new_rtx
) == NEG
)
7993 new_rtx
= XEXP (new_rtx
, 0);
7996 multval
= trunc_int_for_mode (multval
, mode
);
7997 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8004 lhs
= make_compound_operation (lhs
, next_code
);
8005 rhs
= make_compound_operation (rhs
, next_code
);
8006 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8008 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8010 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8012 else if (GET_CODE (lhs
) == MULT
8013 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8015 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8016 simplify_gen_unary (NEG
, mode
,
8019 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8023 SUBST (XEXP (x
, 0), lhs
);
8024 SUBST (XEXP (x
, 1), rhs
);
8026 maybe_swap_commutative_operands (x
);
8032 lhs
= make_compound_operation (lhs
, next_code
);
8033 rhs
= make_compound_operation (rhs
, next_code
);
8034 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8036 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8038 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8040 else if (GET_CODE (rhs
) == MULT
8041 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8043 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8044 simplify_gen_unary (NEG
, mode
,
8047 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8051 SUBST (XEXP (x
, 0), lhs
);
8052 SUBST (XEXP (x
, 1), rhs
);
8057 /* If the second operand is not a constant, we can't do anything
8059 if (!CONST_INT_P (XEXP (x
, 1)))
8062 /* If the constant is a power of two minus one and the first operand
8063 is a logical right shift, make an extraction. */
8064 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8065 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8067 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8068 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
8069 0, in_code
== COMPARE
);
8072 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8073 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8074 && subreg_lowpart_p (XEXP (x
, 0))
8075 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8076 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8078 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8079 machine_mode inner_mode
= GET_MODE (inner_x0
);
8080 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8081 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8083 i
, 1, 0, in_code
== COMPARE
);
8087 /* If we narrowed the mode when dropping the subreg, then
8088 we must zero-extend to keep the semantics of the AND. */
8089 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
8091 else if (SCALAR_INT_MODE_P (inner_mode
))
8092 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
8093 new_rtx
, inner_mode
);
8098 /* If that didn't give anything, see if the AND simplifies on
8100 if (!new_rtx
&& i
>= 0)
8102 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8103 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
8104 0, in_code
== COMPARE
);
8107 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8108 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8109 || GET_CODE (XEXP (x
, 0)) == IOR
)
8110 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8111 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8112 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8114 /* Apply the distributive law, and then try to make extractions. */
8115 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8116 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8118 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8120 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8123 /* If we are have (and (rotate X C) M) and C is larger than the number
8124 of bits in M, this is an extraction. */
8126 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8127 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8128 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8129 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8131 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8132 new_rtx
= make_extraction (mode
, new_rtx
,
8133 (GET_MODE_PRECISION (mode
)
8134 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8135 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8138 /* On machines without logical shifts, if the operand of the AND is
8139 a logical shift and our mask turns off all the propagated sign
8140 bits, we can replace the logical shift with an arithmetic shift. */
8141 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8142 && !have_insn_for (LSHIFTRT
, mode
)
8143 && have_insn_for (ASHIFTRT
, mode
)
8144 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8145 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8146 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8147 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8149 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8151 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8152 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8154 gen_rtx_ASHIFTRT (mode
,
8155 make_compound_operation
8156 (XEXP (XEXP (x
, 0), 0), next_code
),
8157 XEXP (XEXP (x
, 0), 1)));
8160 /* If the constant is one less than a power of two, this might be
8161 representable by an extraction even if no shift is present.
8162 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8163 we are in a COMPARE. */
8164 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8165 new_rtx
= make_extraction (mode
,
8166 make_compound_operation (XEXP (x
, 0),
8168 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8170 /* If we are in a comparison and this is an AND with a power of two,
8171 convert this into the appropriate bit extract. */
8172 else if (in_code
== COMPARE
8173 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8174 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8175 new_rtx
= make_extraction (mode
,
8176 make_compound_operation (XEXP (x
, 0),
8178 i
, NULL_RTX
, 1, 1, 0, 1);
8180 /* If the one operand is a paradoxical subreg of a register or memory and
8181 the constant (limited to the smaller mode) has only zero bits where
8182 the sub expression has known zero bits, this can be expressed as
8184 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8188 sub
= XEXP (XEXP (x
, 0), 0);
8189 machine_mode sub_mode
= GET_MODE (sub
);
8190 if ((REG_P (sub
) || MEM_P (sub
))
8191 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8193 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8194 unsigned HOST_WIDE_INT mask
;
8196 /* original AND constant with all the known zero bits set */
8197 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8198 if ((mask
& mode_mask
) == mode_mask
)
8200 new_rtx
= make_compound_operation (sub
, next_code
);
8201 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8202 GET_MODE_PRECISION (sub_mode
),
8203 1, 0, in_code
== COMPARE
);
8211 /* If the sign bit is known to be zero, replace this with an
8212 arithmetic shift. */
8213 if (have_insn_for (ASHIFTRT
, mode
)
8214 && ! have_insn_for (LSHIFTRT
, mode
)
8215 && mode_width
<= HOST_BITS_PER_WIDE_INT
8216 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8218 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8219 make_compound_operation (XEXP (x
, 0),
8231 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8232 this is a SIGN_EXTRACT. */
8233 if (CONST_INT_P (rhs
)
8234 && GET_CODE (lhs
) == ASHIFT
8235 && CONST_INT_P (XEXP (lhs
, 1))
8236 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8237 && INTVAL (XEXP (lhs
, 1)) >= 0
8238 && INTVAL (rhs
) < mode_width
)
8240 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8241 new_rtx
= make_extraction (mode
, new_rtx
,
8242 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8243 NULL_RTX
, mode_width
- INTVAL (rhs
),
8244 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8248 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8249 If so, try to merge the shifts into a SIGN_EXTEND. We could
8250 also do this for some cases of SIGN_EXTRACT, but it doesn't
8251 seem worth the effort; the case checked for occurs on Alpha. */
8254 && ! (GET_CODE (lhs
) == SUBREG
8255 && (OBJECT_P (SUBREG_REG (lhs
))))
8256 && CONST_INT_P (rhs
)
8257 && INTVAL (rhs
) >= 0
8258 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8259 && INTVAL (rhs
) < mode_width
8260 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8261 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8262 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8263 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8268 /* Call ourselves recursively on the inner expression. If we are
8269 narrowing the object and it has a different RTL code from
8270 what it originally did, do this SUBREG as a force_to_mode. */
8272 rtx inner
= SUBREG_REG (x
), simplified
;
8273 enum rtx_code subreg_code
= in_code
;
8275 /* If the SUBREG is masking of a logical right shift,
8276 make an extraction. */
8277 if (GET_CODE (inner
) == LSHIFTRT
8278 && CONST_INT_P (XEXP (inner
, 1))
8279 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8280 && (UINTVAL (XEXP (inner
, 1))
8281 < GET_MODE_PRECISION (GET_MODE (inner
)))
8282 && subreg_lowpart_p (x
))
8284 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8285 int width
= GET_MODE_PRECISION (GET_MODE (inner
))
8286 - INTVAL (XEXP (inner
, 1));
8287 if (width
> mode_width
)
8289 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8290 width
, 1, 0, in_code
== COMPARE
);
8294 /* If in_code is COMPARE, it isn't always safe to pass it through
8295 to the recursive make_compound_operation call. */
8296 if (subreg_code
== COMPARE
8297 && (!subreg_lowpart_p (x
)
8298 || GET_CODE (inner
) == SUBREG
8299 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8300 is (const_int 0), rather than
8301 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8302 || (GET_CODE (inner
) == AND
8303 && CONST_INT_P (XEXP (inner
, 1))
8304 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8305 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8306 >= GET_MODE_BITSIZE (mode
))))
8309 tem
= make_compound_operation (inner
, subreg_code
);
8312 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8316 if (GET_CODE (tem
) != GET_CODE (inner
)
8317 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8318 && subreg_lowpart_p (x
))
8321 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8323 /* If we have something other than a SUBREG, we might have
8324 done an expansion, so rerun ourselves. */
8325 if (GET_CODE (newer
) != SUBREG
)
8326 newer
= make_compound_operation (newer
, in_code
);
8328 /* force_to_mode can expand compounds. If it just re-expanded the
8329 compound, use gen_lowpart to convert to the desired mode. */
8330 if (rtx_equal_p (newer
, x
)
8331 /* Likewise if it re-expanded the compound only partially.
8332 This happens for SUBREG of ZERO_EXTRACT if they extract
8333 the same number of bits. */
8334 || (GET_CODE (newer
) == SUBREG
8335 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8336 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8337 && GET_CODE (inner
) == AND
8338 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8339 return gen_lowpart (GET_MODE (x
), tem
);
8354 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8355 *next_code_ptr
= next_code
;
8359 /* Look at the expression rooted at X. Look for expressions
8360 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8361 Form these expressions.
8363 Return the new rtx, usually just X.
8365 Also, for machines like the VAX that don't have logical shift insns,
8366 try to convert logical to arithmetic shift operations in cases where
8367 they are equivalent. This undoes the canonicalizations to logical
8368 shifts done elsewhere.
8370 We try, as much as possible, to re-use rtl expressions to save memory.
8372 IN_CODE says what kind of expression we are processing. Normally, it is
8373 SET. In a memory address it is MEM. When processing the arguments of
8374 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8375 precisely it is an equality comparison against zero. */
8378 make_compound_operation (rtx x
, enum rtx_code in_code
)
8380 enum rtx_code code
= GET_CODE (x
);
8383 enum rtx_code next_code
;
8386 /* Select the code to be used in recursive calls. Once we are inside an
8387 address, we stay there. If we have a comparison, set to COMPARE,
8388 but once inside, go back to our default of SET. */
8390 next_code
= (code
== MEM
? MEM
8391 : ((code
== COMPARE
|| COMPARISON_P (x
))
8392 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8393 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8395 if (SCALAR_INT_MODE_P (GET_MODE (x
)))
8397 rtx new_rtx
= make_compound_operation_int (GET_MODE (x
), &x
,
8398 in_code
, &next_code
);
8401 code
= GET_CODE (x
);
8404 /* Now recursively process each operand of this operation. We need to
8405 handle ZERO_EXTEND specially so that we don't lose track of the
8407 if (code
== ZERO_EXTEND
)
8409 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8410 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8411 new_rtx
, GET_MODE (XEXP (x
, 0)));
8414 SUBST (XEXP (x
, 0), new_rtx
);
8418 fmt
= GET_RTX_FORMAT (code
);
8419 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8422 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8423 SUBST (XEXP (x
, i
), new_rtx
);
8425 else if (fmt
[i
] == 'E')
8426 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8428 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8429 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8432 maybe_swap_commutative_operands (x
);
8436 /* Given M see if it is a value that would select a field of bits
8437 within an item, but not the entire word. Return -1 if not.
8438 Otherwise, return the starting position of the field, where 0 is the
8441 *PLEN is set to the length of the field. */
8444 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8446 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8447 int pos
= m
? ctz_hwi (m
) : -1;
8451 /* Now shift off the low-order zero bits and see if we have a
8452 power of two minus 1. */
8453 len
= exact_log2 ((m
>> pos
) + 1);
8462 /* If X refers to a register that equals REG in value, replace these
8463 references with REG. */
8465 canon_reg_for_combine (rtx x
, rtx reg
)
8472 enum rtx_code code
= GET_CODE (x
);
8473 switch (GET_RTX_CLASS (code
))
8476 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8477 if (op0
!= XEXP (x
, 0))
8478 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8483 case RTX_COMM_ARITH
:
8484 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8485 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8486 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8487 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8491 case RTX_COMM_COMPARE
:
8492 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8493 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8494 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8495 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8496 GET_MODE (op0
), op0
, op1
);
8500 case RTX_BITFIELD_OPS
:
8501 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8502 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8503 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8504 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8505 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8506 GET_MODE (op0
), op0
, op1
, op2
);
8512 if (rtx_equal_p (get_last_value (reg
), x
)
8513 || rtx_equal_p (reg
, get_last_value (x
)))
8522 fmt
= GET_RTX_FORMAT (code
);
8524 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8527 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8528 if (op
!= XEXP (x
, i
))
8538 else if (fmt
[i
] == 'E')
8541 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8543 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8544 if (op
!= XVECEXP (x
, i
, j
))
8551 XVECEXP (x
, i
, j
) = op
;
8562 /* Return X converted to MODE. If the value is already truncated to
8563 MODE we can just return a subreg even though in the general case we
8564 would need an explicit truncation. */
8567 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8569 if (!CONST_INT_P (x
)
8570 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8571 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8572 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8574 /* Bit-cast X into an integer mode. */
8575 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8576 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8577 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8581 return gen_lowpart (mode
, x
);
8584 /* See if X can be simplified knowing that we will only refer to it in
8585 MODE and will only refer to those bits that are nonzero in MASK.
8586 If other bits are being computed or if masking operations are done
8587 that select a superset of the bits in MASK, they can sometimes be
8590 Return a possibly simplified expression, but always convert X to
8591 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8593 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8594 are all off in X. This is used when X will be complemented, by either
8595 NOT, NEG, or XOR. */
8598 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8601 enum rtx_code code
= GET_CODE (x
);
8602 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8603 machine_mode op_mode
;
8604 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8607 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8608 code below will do the wrong thing since the mode of such an
8609 expression is VOIDmode.
8611 Also do nothing if X is a CLOBBER; this can happen if X was
8612 the return value from a call to gen_lowpart. */
8613 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8616 /* We want to perform the operation in its present mode unless we know
8617 that the operation is valid in MODE, in which case we do the operation
8619 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8620 && have_insn_for (code
, mode
))
8621 ? mode
: GET_MODE (x
));
8623 /* It is not valid to do a right-shift in a narrower mode
8624 than the one it came in with. */
8625 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8626 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8627 op_mode
= GET_MODE (x
);
8629 /* Truncate MASK to fit OP_MODE. */
8631 mask
&= GET_MODE_MASK (op_mode
);
8633 /* When we have an arithmetic operation, or a shift whose count we
8634 do not know, we need to assume that all bits up to the highest-order
8635 bit in MASK will be needed. This is how we form such a mask. */
8636 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8637 fuller_mask
= HOST_WIDE_INT_M1U
;
8639 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8642 /* Determine what bits of X are guaranteed to be (non)zero. */
8643 nonzero
= nonzero_bits (x
, mode
);
8645 /* If none of the bits in X are needed, return a zero. */
8646 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8649 /* If X is a CONST_INT, return a new one. Do this here since the
8650 test below will fail. */
8651 if (CONST_INT_P (x
))
8653 if (SCALAR_INT_MODE_P (mode
))
8654 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8657 x
= GEN_INT (INTVAL (x
) & mask
);
8658 return gen_lowpart_common (mode
, x
);
8662 /* If X is narrower than MODE and we want all the bits in X's mode, just
8663 get X in the proper mode. */
8664 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8665 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8666 return gen_lowpart (mode
, x
);
8668 /* We can ignore the effect of a SUBREG if it narrows the mode or
8669 if the constant masks to zero all the bits the mode doesn't have. */
8670 if (GET_CODE (x
) == SUBREG
8671 && subreg_lowpart_p (x
)
8672 && ((GET_MODE_SIZE (GET_MODE (x
))
8673 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8675 & GET_MODE_MASK (GET_MODE (x
))
8676 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8677 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8679 /* The arithmetic simplifications here only work for scalar integer modes. */
8680 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8681 return gen_lowpart_or_truncate (mode
, x
);
8686 /* If X is a (clobber (const_int)), return it since we know we are
8687 generating something that won't match. */
8694 x
= expand_compound_operation (x
);
8695 if (GET_CODE (x
) != code
)
8696 return force_to_mode (x
, mode
, mask
, next_select
);
8700 /* Similarly for a truncate. */
8701 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8704 /* If this is an AND with a constant, convert it into an AND
8705 whose constant is the AND of that constant with MASK. If it
8706 remains an AND of MASK, delete it since it is redundant. */
8708 if (CONST_INT_P (XEXP (x
, 1)))
8710 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8711 mask
& INTVAL (XEXP (x
, 1)));
8713 /* If X is still an AND, see if it is an AND with a mask that
8714 is just some low-order bits. If so, and it is MASK, we don't
8717 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8718 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8722 /* If it remains an AND, try making another AND with the bits
8723 in the mode mask that aren't in MASK turned on. If the
8724 constant in the AND is wide enough, this might make a
8725 cheaper constant. */
8727 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8728 && GET_MODE_MASK (GET_MODE (x
)) != mask
8729 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8731 unsigned HOST_WIDE_INT cval
8732 = UINTVAL (XEXP (x
, 1))
8733 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8736 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8737 gen_int_mode (cval
, GET_MODE (x
)));
8738 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8739 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8749 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8750 low-order bits (as in an alignment operation) and FOO is already
8751 aligned to that boundary, mask C1 to that boundary as well.
8752 This may eliminate that PLUS and, later, the AND. */
8755 unsigned int width
= GET_MODE_PRECISION (mode
);
8756 unsigned HOST_WIDE_INT smask
= mask
;
8758 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8759 number, sign extend it. */
8761 if (width
< HOST_BITS_PER_WIDE_INT
8762 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8763 smask
|= HOST_WIDE_INT_M1U
<< width
;
8765 if (CONST_INT_P (XEXP (x
, 1))
8766 && pow2p_hwi (- smask
)
8767 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8768 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8769 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8770 (INTVAL (XEXP (x
, 1)) & smask
)),
8771 mode
, smask
, next_select
);
8777 /* Substituting into the operands of a widening MULT is not likely to
8778 create RTL matching a machine insn. */
8780 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8781 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8782 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8783 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8784 && REG_P (XEXP (XEXP (x
, 0), 0))
8785 && REG_P (XEXP (XEXP (x
, 1), 0)))
8786 return gen_lowpart_or_truncate (mode
, x
);
8788 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8789 most significant bit in MASK since carries from those bits will
8790 affect the bits we are interested in. */
8795 /* If X is (minus C Y) where C's least set bit is larger than any bit
8796 in the mask, then we may replace with (neg Y). */
8797 if (CONST_INT_P (XEXP (x
, 0))
8798 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8800 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8802 return force_to_mode (x
, mode
, mask
, next_select
);
8805 /* Similarly, if C contains every bit in the fuller_mask, then we may
8806 replace with (not Y). */
8807 if (CONST_INT_P (XEXP (x
, 0))
8808 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8810 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8811 XEXP (x
, 1), GET_MODE (x
));
8812 return force_to_mode (x
, mode
, mask
, next_select
);
8820 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8821 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8822 operation which may be a bitfield extraction. Ensure that the
8823 constant we form is not wider than the mode of X. */
8825 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8826 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8827 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8828 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8829 && CONST_INT_P (XEXP (x
, 1))
8830 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8831 + floor_log2 (INTVAL (XEXP (x
, 1))))
8832 < GET_MODE_PRECISION (GET_MODE (x
)))
8833 && (UINTVAL (XEXP (x
, 1))
8834 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8836 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8837 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8839 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8840 XEXP (XEXP (x
, 0), 0), temp
);
8841 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8842 XEXP (XEXP (x
, 0), 1));
8843 return force_to_mode (x
, mode
, mask
, next_select
);
8847 /* For most binary operations, just propagate into the operation and
8848 change the mode if we have an operation of that mode. */
8850 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8851 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8853 /* If we ended up truncating both operands, truncate the result of the
8854 operation instead. */
8855 if (GET_CODE (op0
) == TRUNCATE
8856 && GET_CODE (op1
) == TRUNCATE
)
8858 op0
= XEXP (op0
, 0);
8859 op1
= XEXP (op1
, 0);
8862 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8863 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8865 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8866 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8870 /* For left shifts, do the same, but just for the first operand.
8871 However, we cannot do anything with shifts where we cannot
8872 guarantee that the counts are smaller than the size of the mode
8873 because such a count will have a different meaning in a
8876 if (! (CONST_INT_P (XEXP (x
, 1))
8877 && INTVAL (XEXP (x
, 1)) >= 0
8878 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8879 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8880 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8881 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8884 /* If the shift count is a constant and we can do arithmetic in
8885 the mode of the shift, refine which bits we need. Otherwise, use the
8886 conservative form of the mask. */
8887 if (CONST_INT_P (XEXP (x
, 1))
8888 && INTVAL (XEXP (x
, 1)) >= 0
8889 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8890 && HWI_COMPUTABLE_MODE_P (op_mode
))
8891 mask
>>= INTVAL (XEXP (x
, 1));
8895 op0
= gen_lowpart_or_truncate (op_mode
,
8896 force_to_mode (XEXP (x
, 0), op_mode
,
8897 mask
, next_select
));
8899 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8900 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8904 /* Here we can only do something if the shift count is a constant,
8905 this shift constant is valid for the host, and we can do arithmetic
8908 if (CONST_INT_P (XEXP (x
, 1))
8909 && INTVAL (XEXP (x
, 1)) >= 0
8910 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8911 && HWI_COMPUTABLE_MODE_P (op_mode
))
8913 rtx inner
= XEXP (x
, 0);
8914 unsigned HOST_WIDE_INT inner_mask
;
8916 /* Select the mask of the bits we need for the shift operand. */
8917 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8919 /* We can only change the mode of the shift if we can do arithmetic
8920 in the mode of the shift and INNER_MASK is no wider than the
8921 width of X's mode. */
8922 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8923 op_mode
= GET_MODE (x
);
8925 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8927 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8928 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8931 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8932 shift and AND produces only copies of the sign bit (C2 is one less
8933 than a power of two), we can do this with just a shift. */
8935 if (GET_CODE (x
) == LSHIFTRT
8936 && CONST_INT_P (XEXP (x
, 1))
8937 /* The shift puts one of the sign bit copies in the least significant
8939 && ((INTVAL (XEXP (x
, 1))
8940 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8941 >= GET_MODE_PRECISION (GET_MODE (x
)))
8942 && pow2p_hwi (mask
+ 1)
8943 /* Number of bits left after the shift must be more than the mask
8945 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8946 <= GET_MODE_PRECISION (GET_MODE (x
)))
8947 /* Must be more sign bit copies than the mask needs. */
8948 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8949 >= exact_log2 (mask
+ 1)))
8950 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8951 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8952 - exact_log2 (mask
+ 1)));
8957 /* If we are just looking for the sign bit, we don't need this shift at
8958 all, even if it has a variable count. */
8959 if (val_signbit_p (GET_MODE (x
), mask
))
8960 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8962 /* If this is a shift by a constant, get a mask that contains those bits
8963 that are not copies of the sign bit. We then have two cases: If
8964 MASK only includes those bits, this can be a logical shift, which may
8965 allow simplifications. If MASK is a single-bit field not within
8966 those bits, we are requesting a copy of the sign bit and hence can
8967 shift the sign bit to the appropriate location. */
8969 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8970 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8974 /* If the considered data is wider than HOST_WIDE_INT, we can't
8975 represent a mask for all its bits in a single scalar.
8976 But we only care about the lower bits, so calculate these. */
8978 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8980 nonzero
= HOST_WIDE_INT_M1U
;
8982 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8983 is the number of bits a full-width mask would have set.
8984 We need only shift if these are fewer than nonzero can
8985 hold. If not, we must keep all bits set in nonzero. */
8987 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8988 < HOST_BITS_PER_WIDE_INT
)
8989 nonzero
>>= INTVAL (XEXP (x
, 1))
8990 + HOST_BITS_PER_WIDE_INT
8991 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8995 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8996 nonzero
>>= INTVAL (XEXP (x
, 1));
8999 if ((mask
& ~nonzero
) == 0)
9001 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
9002 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9003 if (GET_CODE (x
) != ASHIFTRT
)
9004 return force_to_mode (x
, mode
, mask
, next_select
);
9007 else if ((i
= exact_log2 (mask
)) >= 0)
9009 x
= simplify_shift_const
9010 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
9011 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
9013 if (GET_CODE (x
) != ASHIFTRT
)
9014 return force_to_mode (x
, mode
, mask
, next_select
);
9018 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9019 even if the shift count isn't a constant. */
9021 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
9022 XEXP (x
, 0), XEXP (x
, 1));
9026 /* If this is a zero- or sign-extension operation that just affects bits
9027 we don't care about, remove it. Be sure the call above returned
9028 something that is still a shift. */
9030 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9031 && CONST_INT_P (XEXP (x
, 1))
9032 && INTVAL (XEXP (x
, 1)) >= 0
9033 && (INTVAL (XEXP (x
, 1))
9034 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
9035 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9036 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9037 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
9044 /* If the shift count is constant and we can do computations
9045 in the mode of X, compute where the bits we care about are.
9046 Otherwise, we can't do anything. Don't change the mode of
9047 the shift or propagate MODE into the shift, though. */
9048 if (CONST_INT_P (XEXP (x
, 1))
9049 && INTVAL (XEXP (x
, 1)) >= 0)
9051 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9053 gen_int_mode (mask
, GET_MODE (x
)),
9055 if (temp
&& CONST_INT_P (temp
))
9056 x
= simplify_gen_binary (code
, GET_MODE (x
),
9057 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
9058 INTVAL (temp
), next_select
),
9064 /* If we just want the low-order bit, the NEG isn't needed since it
9065 won't change the low-order bit. */
9067 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9069 /* We need any bits less significant than the most significant bit in
9070 MASK since carries from those bits will affect the bits we are
9076 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9077 same as the XOR case above. Ensure that the constant we form is not
9078 wider than the mode of X. */
9080 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9081 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9082 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9083 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9084 < GET_MODE_PRECISION (GET_MODE (x
)))
9085 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9087 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
9089 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
9090 XEXP (XEXP (x
, 0), 0), temp
);
9091 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
9092 temp
, XEXP (XEXP (x
, 0), 1));
9094 return force_to_mode (x
, mode
, mask
, next_select
);
9097 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9098 use the full mask inside the NOT. */
9102 op0
= gen_lowpart_or_truncate (op_mode
,
9103 force_to_mode (XEXP (x
, 0), mode
, mask
,
9105 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
9106 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9110 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9111 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9112 which is equal to STORE_FLAG_VALUE. */
9113 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9114 && XEXP (x
, 1) == const0_rtx
9115 && GET_MODE (XEXP (x
, 0)) == mode
9116 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9117 && (nonzero_bits (XEXP (x
, 0), mode
)
9118 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9119 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9124 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9125 written in a narrower mode. We play it safe and do not do so. */
9127 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
9128 force_to_mode (XEXP (x
, 1), mode
,
9129 mask
, next_select
));
9130 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
9131 force_to_mode (XEXP (x
, 2), mode
,
9132 mask
, next_select
));
9133 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9134 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
9135 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9143 /* Ensure we return a value of the proper mode. */
9144 return gen_lowpart_or_truncate (mode
, x
);
9147 /* Return nonzero if X is an expression that has one of two values depending on
9148 whether some other value is zero or nonzero. In that case, we return the
9149 value that is being tested, *PTRUE is set to the value if the rtx being
9150 returned has a nonzero value, and *PFALSE is set to the other alternative.
9152 If we return zero, we set *PTRUE and *PFALSE to X. */
9155 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9157 machine_mode mode
= GET_MODE (x
);
9158 enum rtx_code code
= GET_CODE (x
);
9159 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9160 unsigned HOST_WIDE_INT nz
;
9162 /* If we are comparing a value against zero, we are done. */
9163 if ((code
== NE
|| code
== EQ
)
9164 && XEXP (x
, 1) == const0_rtx
)
9166 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9167 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9171 /* If this is a unary operation whose operand has one of two values, apply
9172 our opcode to compute those values. */
9173 else if (UNARY_P (x
)
9174 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9176 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9177 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9178 GET_MODE (XEXP (x
, 0)));
9182 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9183 make can't possibly match and would suppress other optimizations. */
9184 else if (code
== COMPARE
)
9187 /* If this is a binary operation, see if either side has only one of two
9188 values. If either one does or if both do and they are conditional on
9189 the same value, compute the new true and false values. */
9190 else if (BINARY_P (x
))
9192 rtx op0
= XEXP (x
, 0);
9193 rtx op1
= XEXP (x
, 1);
9194 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9195 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9197 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9198 && (REG_P (op0
) || REG_P (op1
)))
9200 /* Try to enable a simplification by undoing work done by
9201 if_then_else_cond if it converted a REG into something more
9206 true0
= false0
= op0
;
9211 true1
= false1
= op1
;
9215 if ((cond0
!= 0 || cond1
!= 0)
9216 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9218 /* If if_then_else_cond returned zero, then true/false are the
9219 same rtl. We must copy one of them to prevent invalid rtl
9222 true0
= copy_rtx (true0
);
9223 else if (cond1
== 0)
9224 true1
= copy_rtx (true1
);
9226 if (COMPARISON_P (x
))
9228 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9230 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9235 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9236 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9239 return cond0
? cond0
: cond1
;
9242 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9243 operands is zero when the other is nonzero, and vice-versa,
9244 and STORE_FLAG_VALUE is 1 or -1. */
9246 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9247 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9249 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9251 rtx op0
= XEXP (XEXP (x
, 0), 1);
9252 rtx op1
= XEXP (XEXP (x
, 1), 1);
9254 cond0
= XEXP (XEXP (x
, 0), 0);
9255 cond1
= XEXP (XEXP (x
, 1), 0);
9257 if (COMPARISON_P (cond0
)
9258 && COMPARISON_P (cond1
)
9259 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9260 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9261 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9262 || ((swap_condition (GET_CODE (cond0
))
9263 == reversed_comparison_code (cond1
, NULL
))
9264 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9265 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9266 && ! side_effects_p (x
))
9268 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9269 *pfalse
= simplify_gen_binary (MULT
, mode
,
9271 ? simplify_gen_unary (NEG
, mode
,
9279 /* Similarly for MULT, AND and UMIN, except that for these the result
9281 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9282 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9283 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9285 cond0
= XEXP (XEXP (x
, 0), 0);
9286 cond1
= XEXP (XEXP (x
, 1), 0);
9288 if (COMPARISON_P (cond0
)
9289 && COMPARISON_P (cond1
)
9290 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9291 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9292 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9293 || ((swap_condition (GET_CODE (cond0
))
9294 == reversed_comparison_code (cond1
, NULL
))
9295 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9296 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9297 && ! side_effects_p (x
))
9299 *ptrue
= *pfalse
= const0_rtx
;
9305 else if (code
== IF_THEN_ELSE
)
9307 /* If we have IF_THEN_ELSE already, extract the condition and
9308 canonicalize it if it is NE or EQ. */
9309 cond0
= XEXP (x
, 0);
9310 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9311 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9312 return XEXP (cond0
, 0);
9313 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9315 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9316 return XEXP (cond0
, 0);
9322 /* If X is a SUBREG, we can narrow both the true and false values
9323 if the inner expression, if there is a condition. */
9324 else if (code
== SUBREG
9325 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9328 true0
= simplify_gen_subreg (mode
, true0
,
9329 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9330 false0
= simplify_gen_subreg (mode
, false0
,
9331 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9332 if (true0
&& false0
)
9340 /* If X is a constant, this isn't special and will cause confusions
9341 if we treat it as such. Likewise if it is equivalent to a constant. */
9342 else if (CONSTANT_P (x
)
9343 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9346 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9347 will be least confusing to the rest of the compiler. */
9348 else if (mode
== BImode
)
9350 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9354 /* If X is known to be either 0 or -1, those are the true and
9355 false values when testing X. */
9356 else if (x
== constm1_rtx
|| x
== const0_rtx
9357 || (mode
!= VOIDmode
&& mode
!= BLKmode
9358 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9360 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9364 /* Likewise for 0 or a single bit. */
9365 else if (HWI_COMPUTABLE_MODE_P (mode
)
9366 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9368 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9372 /* Otherwise fail; show no condition with true and false values the same. */
9373 *ptrue
= *pfalse
= x
;
9377 /* Return the value of expression X given the fact that condition COND
9378 is known to be true when applied to REG as its first operand and VAL
9379 as its second. X is known to not be shared and so can be modified in
9382 We only handle the simplest cases, and specifically those cases that
9383 arise with IF_THEN_ELSE expressions. */
9386 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9388 enum rtx_code code
= GET_CODE (x
);
9392 if (side_effects_p (x
))
9395 /* If either operand of the condition is a floating point value,
9396 then we have to avoid collapsing an EQ comparison. */
9398 && rtx_equal_p (x
, reg
)
9399 && ! FLOAT_MODE_P (GET_MODE (x
))
9400 && ! FLOAT_MODE_P (GET_MODE (val
)))
9403 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9406 /* If X is (abs REG) and we know something about REG's relationship
9407 with zero, we may be able to simplify this. */
9409 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9412 case GE
: case GT
: case EQ
:
9415 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9417 GET_MODE (XEXP (x
, 0)));
9422 /* The only other cases we handle are MIN, MAX, and comparisons if the
9423 operands are the same as REG and VAL. */
9425 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9427 if (rtx_equal_p (XEXP (x
, 0), val
))
9429 std::swap (val
, reg
);
9430 cond
= swap_condition (cond
);
9433 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9435 if (COMPARISON_P (x
))
9437 if (comparison_dominates_p (cond
, code
))
9438 return const_true_rtx
;
9440 code
= reversed_comparison_code (x
, NULL
);
9442 && comparison_dominates_p (cond
, code
))
9447 else if (code
== SMAX
|| code
== SMIN
9448 || code
== UMIN
|| code
== UMAX
)
9450 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9452 /* Do not reverse the condition when it is NE or EQ.
9453 This is because we cannot conclude anything about
9454 the value of 'SMAX (x, y)' when x is not equal to y,
9455 but we can when x equals y. */
9456 if ((code
== SMAX
|| code
== UMAX
)
9457 && ! (cond
== EQ
|| cond
== NE
))
9458 cond
= reverse_condition (cond
);
9463 return unsignedp
? x
: XEXP (x
, 1);
9465 return unsignedp
? x
: XEXP (x
, 0);
9467 return unsignedp
? XEXP (x
, 1) : x
;
9469 return unsignedp
? XEXP (x
, 0) : x
;
9476 else if (code
== SUBREG
)
9478 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9479 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9481 if (SUBREG_REG (x
) != r
)
9483 /* We must simplify subreg here, before we lose track of the
9484 original inner_mode. */
9485 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9486 inner_mode
, SUBREG_BYTE (x
));
9490 SUBST (SUBREG_REG (x
), r
);
9495 /* We don't have to handle SIGN_EXTEND here, because even in the
9496 case of replacing something with a modeless CONST_INT, a
9497 CONST_INT is already (supposed to be) a valid sign extension for
9498 its narrower mode, which implies it's already properly
9499 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9500 story is different. */
9501 else if (code
== ZERO_EXTEND
)
9503 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9504 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9506 if (XEXP (x
, 0) != r
)
9508 /* We must simplify the zero_extend here, before we lose
9509 track of the original inner_mode. */
9510 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9515 SUBST (XEXP (x
, 0), r
);
9521 fmt
= GET_RTX_FORMAT (code
);
9522 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9525 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9526 else if (fmt
[i
] == 'E')
9527 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9528 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9535 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9536 assignment as a field assignment. */
9539 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9541 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9543 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9545 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9547 /* For big endian, adjust the memory offset. */
9548 if (BYTES_BIG_ENDIAN
)
9549 x
= adjust_address_nv (x
, GET_MODE (y
),
9550 -subreg_lowpart_offset (GET_MODE (x
),
9553 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9556 if (x
== y
|| rtx_equal_p (x
, y
))
9559 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9562 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9563 Note that all SUBREGs of MEM are paradoxical; otherwise they
9564 would have been rewritten. */
9565 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9566 && MEM_P (SUBREG_REG (y
))
9567 && rtx_equal_p (SUBREG_REG (y
),
9568 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9571 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9572 && MEM_P (SUBREG_REG (x
))
9573 && rtx_equal_p (SUBREG_REG (x
),
9574 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9577 /* We used to see if get_last_value of X and Y were the same but that's
9578 not correct. In one direction, we'll cause the assignment to have
9579 the wrong destination and in the case, we'll import a register into this
9580 insn that might have already have been dead. So fail if none of the
9581 above cases are true. */
9585 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9586 Return that assignment if so.
9588 We only handle the most common cases. */
9591 make_field_assignment (rtx x
)
9593 rtx dest
= SET_DEST (x
);
9594 rtx src
= SET_SRC (x
);
9599 unsigned HOST_WIDE_INT len
;
9603 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9604 a clear of a one-bit field. We will have changed it to
9605 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9608 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9609 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9610 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9611 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9613 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9616 return gen_rtx_SET (assign
, const0_rtx
);
9620 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9621 && subreg_lowpart_p (XEXP (src
, 0))
9622 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9623 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9624 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9625 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9626 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9627 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9629 assign
= make_extraction (VOIDmode
, dest
, 0,
9630 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9633 return gen_rtx_SET (assign
, const0_rtx
);
9637 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9639 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9640 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9641 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9643 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9646 return gen_rtx_SET (assign
, const1_rtx
);
9650 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9651 SRC is an AND with all bits of that field set, then we can discard
9653 if (GET_CODE (dest
) == ZERO_EXTRACT
9654 && CONST_INT_P (XEXP (dest
, 1))
9655 && GET_CODE (src
) == AND
9656 && CONST_INT_P (XEXP (src
, 1)))
9658 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9659 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9660 unsigned HOST_WIDE_INT ze_mask
;
9662 if (width
>= HOST_BITS_PER_WIDE_INT
)
9665 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9667 /* Complete overlap. We can remove the source AND. */
9668 if ((and_mask
& ze_mask
) == ze_mask
)
9669 return gen_rtx_SET (dest
, XEXP (src
, 0));
9671 /* Partial overlap. We can reduce the source AND. */
9672 if ((and_mask
& ze_mask
) != and_mask
)
9674 mode
= GET_MODE (src
);
9675 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9676 gen_int_mode (and_mask
& ze_mask
, mode
));
9677 return gen_rtx_SET (dest
, src
);
9681 /* The other case we handle is assignments into a constant-position
9682 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9683 a mask that has all one bits except for a group of zero bits and
9684 OTHER is known to have zeros where C1 has ones, this is such an
9685 assignment. Compute the position and length from C1. Shift OTHER
9686 to the appropriate position, force it to the required mode, and
9687 make the extraction. Check for the AND in both operands. */
9689 /* One or more SUBREGs might obscure the constant-position field
9690 assignment. The first one we are likely to encounter is an outer
9691 narrowing SUBREG, which we can just strip for the purposes of
9692 identifying the constant-field assignment. */
9693 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9694 src
= SUBREG_REG (src
);
9696 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9699 rhs
= expand_compound_operation (XEXP (src
, 0));
9700 lhs
= expand_compound_operation (XEXP (src
, 1));
9702 if (GET_CODE (rhs
) == AND
9703 && CONST_INT_P (XEXP (rhs
, 1))
9704 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9705 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9706 /* The second SUBREG that might get in the way is a paradoxical
9707 SUBREG around the first operand of the AND. We want to
9708 pretend the operand is as wide as the destination here. We
9709 do this by adjusting the MEM to wider mode for the sole
9710 purpose of the call to rtx_equal_for_field_assignment_p. Also
9711 note this trick only works for MEMs. */
9712 else if (GET_CODE (rhs
) == AND
9713 && paradoxical_subreg_p (XEXP (rhs
, 0))
9714 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9715 && CONST_INT_P (XEXP (rhs
, 1))
9716 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9718 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9719 else if (GET_CODE (lhs
) == AND
9720 && CONST_INT_P (XEXP (lhs
, 1))
9721 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9722 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9723 /* The second SUBREG that might get in the way is a paradoxical
9724 SUBREG around the first operand of the AND. We want to
9725 pretend the operand is as wide as the destination here. We
9726 do this by adjusting the MEM to wider mode for the sole
9727 purpose of the call to rtx_equal_for_field_assignment_p. Also
9728 note this trick only works for MEMs. */
9729 else if (GET_CODE (lhs
) == AND
9730 && paradoxical_subreg_p (XEXP (lhs
, 0))
9731 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9732 && CONST_INT_P (XEXP (lhs
, 1))
9733 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9735 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9739 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9740 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9741 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9742 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9745 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9749 /* The mode to use for the source is the mode of the assignment, or of
9750 what is inside a possible STRICT_LOW_PART. */
9751 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9752 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9754 /* Shift OTHER right POS places and make it the source, restricting it
9755 to the proper length and mode. */
9757 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9761 src
= force_to_mode (src
, mode
,
9762 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9764 : (HOST_WIDE_INT_1U
<< len
) - 1,
9767 /* If SRC is masked by an AND that does not make a difference in
9768 the value being stored, strip it. */
9769 if (GET_CODE (assign
) == ZERO_EXTRACT
9770 && CONST_INT_P (XEXP (assign
, 1))
9771 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9772 && GET_CODE (src
) == AND
9773 && CONST_INT_P (XEXP (src
, 1))
9774 && UINTVAL (XEXP (src
, 1))
9775 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9776 src
= XEXP (src
, 0);
9778 return gen_rtx_SET (assign
, src
);
9781 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9785 apply_distributive_law (rtx x
)
9787 enum rtx_code code
= GET_CODE (x
);
9788 enum rtx_code inner_code
;
9789 rtx lhs
, rhs
, other
;
9792 /* Distributivity is not true for floating point as it can change the
9793 value. So we don't do it unless -funsafe-math-optimizations. */
9794 if (FLOAT_MODE_P (GET_MODE (x
))
9795 && ! flag_unsafe_math_optimizations
)
9798 /* The outer operation can only be one of the following: */
9799 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9800 && code
!= PLUS
&& code
!= MINUS
)
9806 /* If either operand is a primitive we can't do anything, so get out
9808 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9811 lhs
= expand_compound_operation (lhs
);
9812 rhs
= expand_compound_operation (rhs
);
9813 inner_code
= GET_CODE (lhs
);
9814 if (inner_code
!= GET_CODE (rhs
))
9817 /* See if the inner and outer operations distribute. */
9824 /* These all distribute except over PLUS. */
9825 if (code
== PLUS
|| code
== MINUS
)
9830 if (code
!= PLUS
&& code
!= MINUS
)
9835 /* This is also a multiply, so it distributes over everything. */
9838 /* This used to handle SUBREG, but this turned out to be counter-
9839 productive, since (subreg (op ...)) usually is not handled by
9840 insn patterns, and this "optimization" therefore transformed
9841 recognizable patterns into unrecognizable ones. Therefore the
9842 SUBREG case was removed from here.
9844 It is possible that distributing SUBREG over arithmetic operations
9845 leads to an intermediate result than can then be optimized further,
9846 e.g. by moving the outer SUBREG to the other side of a SET as done
9847 in simplify_set. This seems to have been the original intent of
9848 handling SUBREGs here.
9850 However, with current GCC this does not appear to actually happen,
9851 at least on major platforms. If some case is found where removing
9852 the SUBREG case here prevents follow-on optimizations, distributing
9853 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9859 /* Set LHS and RHS to the inner operands (A and B in the example
9860 above) and set OTHER to the common operand (C in the example).
9861 There is only one way to do this unless the inner operation is
9863 if (COMMUTATIVE_ARITH_P (lhs
)
9864 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9865 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9866 else if (COMMUTATIVE_ARITH_P (lhs
)
9867 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9868 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9869 else if (COMMUTATIVE_ARITH_P (lhs
)
9870 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9871 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9872 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9873 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9877 /* Form the new inner operation, seeing if it simplifies first. */
9878 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9880 /* There is one exception to the general way of distributing:
9881 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9882 if (code
== XOR
&& inner_code
== IOR
)
9885 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9888 /* We may be able to continuing distributing the result, so call
9889 ourselves recursively on the inner operation before forming the
9890 outer operation, which we return. */
9891 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9892 apply_distributive_law (tem
), other
);
9895 /* See if X is of the form (* (+ A B) C), and if so convert to
9896 (+ (* A C) (* B C)) and try to simplify.
9898 Most of the time, this results in no change. However, if some of
9899 the operands are the same or inverses of each other, simplifications
9902 For example, (and (ior A B) (not B)) can occur as the result of
9903 expanding a bit field assignment. When we apply the distributive
9904 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9905 which then simplifies to (and (A (not B))).
9907 Note that no checks happen on the validity of applying the inverse
9908 distributive law. This is pointless since we can do it in the
9909 few places where this routine is called.
9911 N is the index of the term that is decomposed (the arithmetic operation,
9912 i.e. (+ A B) in the first example above). !N is the index of the term that
9913 is distributed, i.e. of C in the first example above. */
9915 distribute_and_simplify_rtx (rtx x
, int n
)
9918 enum rtx_code outer_code
, inner_code
;
9919 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9921 /* Distributivity is not true for floating point as it can change the
9922 value. So we don't do it unless -funsafe-math-optimizations. */
9923 if (FLOAT_MODE_P (GET_MODE (x
))
9924 && ! flag_unsafe_math_optimizations
)
9927 decomposed
= XEXP (x
, n
);
9928 if (!ARITHMETIC_P (decomposed
))
9931 mode
= GET_MODE (x
);
9932 outer_code
= GET_CODE (x
);
9933 distributed
= XEXP (x
, !n
);
9935 inner_code
= GET_CODE (decomposed
);
9936 inner_op0
= XEXP (decomposed
, 0);
9937 inner_op1
= XEXP (decomposed
, 1);
9939 /* Special case (and (xor B C) (not A)), which is equivalent to
9940 (xor (ior A B) (ior A C)) */
9941 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9943 distributed
= XEXP (distributed
, 0);
9949 /* Distribute the second term. */
9950 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9951 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9955 /* Distribute the first term. */
9956 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9957 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9960 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9962 if (GET_CODE (tmp
) != outer_code
9963 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9964 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9970 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9971 in MODE. Return an equivalent form, if different from (and VAROP
9972 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9975 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9976 unsigned HOST_WIDE_INT constop
)
9978 unsigned HOST_WIDE_INT nonzero
;
9979 unsigned HOST_WIDE_INT orig_constop
;
9984 orig_constop
= constop
;
9985 if (GET_CODE (varop
) == CLOBBER
)
9988 /* Simplify VAROP knowing that we will be only looking at some of the
9991 Note by passing in CONSTOP, we guarantee that the bits not set in
9992 CONSTOP are not significant and will never be examined. We must
9993 ensure that is the case by explicitly masking out those bits
9994 before returning. */
9995 varop
= force_to_mode (varop
, mode
, constop
, 0);
9997 /* If VAROP is a CLOBBER, we will fail so return it. */
9998 if (GET_CODE (varop
) == CLOBBER
)
10001 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10002 to VAROP and return the new constant. */
10003 if (CONST_INT_P (varop
))
10004 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10006 /* See what bits may be nonzero in VAROP. Unlike the general case of
10007 a call to nonzero_bits, here we don't care about bits outside
10010 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
10012 /* Turn off all bits in the constant that are known to already be zero.
10013 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10014 which is tested below. */
10016 constop
&= nonzero
;
10018 /* If we don't have any bits left, return zero. */
10022 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10023 a power of two, we can replace this with an ASHIFT. */
10024 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
10025 && (i
= exact_log2 (constop
)) >= 0)
10026 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10028 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10029 or XOR, then try to apply the distributive law. This may eliminate
10030 operations if either branch can be simplified because of the AND.
10031 It may also make some cases more complex, but those cases probably
10032 won't match a pattern either with or without this. */
10034 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10038 apply_distributive_law
10039 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
10040 simplify_and_const_int (NULL_RTX
,
10044 simplify_and_const_int (NULL_RTX
,
10049 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10050 the AND and see if one of the operands simplifies to zero. If so, we
10051 may eliminate it. */
10053 if (GET_CODE (varop
) == PLUS
10054 && pow2p_hwi (constop
+ 1))
10058 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10059 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10060 if (o0
== const0_rtx
)
10062 if (o1
== const0_rtx
)
10066 /* Make a SUBREG if necessary. If we can't make it, fail. */
10067 varop
= gen_lowpart (mode
, varop
);
10068 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10071 /* If we are only masking insignificant bits, return VAROP. */
10072 if (constop
== nonzero
)
10075 if (varop
== orig_varop
&& constop
== orig_constop
)
10078 /* Otherwise, return an AND. */
10079 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10083 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10086 Return an equivalent form, if different from X. Otherwise, return X. If
10087 X is zero, we are to always construct the equivalent form. */
10090 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
10091 unsigned HOST_WIDE_INT constop
)
10093 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10098 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10099 gen_int_mode (constop
, mode
));
10100 if (GET_MODE (x
) != mode
)
10101 x
= gen_lowpart (mode
, x
);
10105 /* Given a REG, X, compute which bits in X can be nonzero.
10106 We don't care about bits outside of those defined in MODE.
10108 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10109 a shift, AND, or zero_extract, we can do better. */
10112 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
10113 const_rtx known_x ATTRIBUTE_UNUSED
,
10114 machine_mode known_mode ATTRIBUTE_UNUSED
,
10115 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
10116 unsigned HOST_WIDE_INT
*nonzero
)
10119 reg_stat_type
*rsp
;
10121 /* If X is a register whose nonzero bits value is current, use it.
10122 Otherwise, if X is a register whose value we can find, use that
10123 value. Otherwise, use the previously-computed global nonzero bits
10124 for this register. */
10126 rsp
= ®_stat
[REGNO (x
)];
10127 if (rsp
->last_set_value
!= 0
10128 && (rsp
->last_set_mode
== mode
10129 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10130 && GET_MODE_CLASS (mode
) == MODE_INT
))
10131 && ((rsp
->last_set_label
>= label_tick_ebb_start
10132 && rsp
->last_set_label
< label_tick
)
10133 || (rsp
->last_set_label
== label_tick
10134 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10135 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10136 && REGNO (x
) < reg_n_sets_max
10137 && REG_N_SETS (REGNO (x
)) == 1
10138 && !REGNO_REG_SET_P
10139 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10142 /* Note that, even if the precision of last_set_mode is lower than that
10143 of mode, record_value_for_reg invoked nonzero_bits on the register
10144 with nonzero_bits_mode (because last_set_mode is necessarily integral
10145 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10146 are all valid, hence in mode too since nonzero_bits_mode is defined
10147 to the largest HWI_COMPUTABLE_MODE_P mode. */
10148 *nonzero
&= rsp
->last_set_nonzero_bits
;
10152 tem
= get_last_value (x
);
10155 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10156 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
10157 GET_MODE_PRECISION (mode
));
10162 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10164 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10166 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10167 /* We don't know anything about the upper bits. */
10168 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10176 /* Return the number of bits at the high-order end of X that are known to
10177 be equal to the sign bit. X will be used in mode MODE; if MODE is
10178 VOIDmode, X will be used in its own mode. The returned value will always
10179 be between 1 and the number of bits in MODE. */
10182 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10183 const_rtx known_x ATTRIBUTE_UNUSED
,
10184 machine_mode known_mode
10186 unsigned int known_ret ATTRIBUTE_UNUSED
,
10187 unsigned int *result
)
10190 reg_stat_type
*rsp
;
10192 rsp
= ®_stat
[REGNO (x
)];
10193 if (rsp
->last_set_value
!= 0
10194 && rsp
->last_set_mode
== mode
10195 && ((rsp
->last_set_label
>= label_tick_ebb_start
10196 && rsp
->last_set_label
< label_tick
)
10197 || (rsp
->last_set_label
== label_tick
10198 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10199 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10200 && REGNO (x
) < reg_n_sets_max
10201 && REG_N_SETS (REGNO (x
)) == 1
10202 && !REGNO_REG_SET_P
10203 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10206 *result
= rsp
->last_set_sign_bit_copies
;
10210 tem
= get_last_value (x
);
10214 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10215 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10216 *result
= rsp
->sign_bit_copies
;
10221 /* Return the number of "extended" bits there are in X, when interpreted
10222 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10223 unsigned quantities, this is the number of high-order zero bits.
10224 For signed quantities, this is the number of copies of the sign bit
10225 minus 1. In both case, this function returns the number of "spare"
10226 bits. For example, if two quantities for which this function returns
10227 at least 1 are added, the addition is known not to overflow.
10229 This function will always return 0 unless called during combine, which
10230 implies that it must be called from a define_split. */
10233 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10235 if (nonzero_sign_valid
== 0)
10239 ? (HWI_COMPUTABLE_MODE_P (mode
)
10240 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
10241 - floor_log2 (nonzero_bits (x
, mode
)))
10243 : num_sign_bit_copies (x
, mode
) - 1);
10246 /* This function is called from `simplify_shift_const' to merge two
10247 outer operations. Specifically, we have already found that we need
10248 to perform operation *POP0 with constant *PCONST0 at the outermost
10249 position. We would now like to also perform OP1 with constant CONST1
10250 (with *POP0 being done last).
10252 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10253 the resulting operation. *PCOMP_P is set to 1 if we would need to
10254 complement the innermost operand, otherwise it is unchanged.
10256 MODE is the mode in which the operation will be done. No bits outside
10257 the width of this mode matter. It is assumed that the width of this mode
10258 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10260 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10261 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10262 result is simply *PCONST0.
10264 If the resulting operation cannot be expressed as one operation, we
10265 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10268 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10270 enum rtx_code op0
= *pop0
;
10271 HOST_WIDE_INT const0
= *pconst0
;
10273 const0
&= GET_MODE_MASK (mode
);
10274 const1
&= GET_MODE_MASK (mode
);
10276 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10280 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10283 if (op1
== UNKNOWN
|| op0
== SET
)
10286 else if (op0
== UNKNOWN
)
10287 op0
= op1
, const0
= const1
;
10289 else if (op0
== op1
)
10313 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10314 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10317 /* If the two constants aren't the same, we can't do anything. The
10318 remaining six cases can all be done. */
10319 else if (const0
!= const1
)
10327 /* (a & b) | b == b */
10329 else /* op1 == XOR */
10330 /* (a ^ b) | b == a | b */
10336 /* (a & b) ^ b == (~a) & b */
10337 op0
= AND
, *pcomp_p
= 1;
10338 else /* op1 == IOR */
10339 /* (a | b) ^ b == a & ~b */
10340 op0
= AND
, const0
= ~const0
;
10345 /* (a | b) & b == b */
10347 else /* op1 == XOR */
10348 /* (a ^ b) & b) == (~a) & b */
10355 /* Check for NO-OP cases. */
10356 const0
&= GET_MODE_MASK (mode
);
10358 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10360 else if (const0
== 0 && op0
== AND
)
10362 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10368 /* ??? Slightly redundant with the above mask, but not entirely.
10369 Moving this above means we'd have to sign-extend the mode mask
10370 for the final test. */
10371 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10372 *pconst0
= trunc_int_for_mode (const0
, mode
);
10377 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10378 the shift in. The original shift operation CODE is performed on OP in
10379 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10380 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10381 result of the shift is subject to operation OUTER_CODE with operand
10384 static machine_mode
10385 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10386 machine_mode orig_mode
, machine_mode mode
,
10387 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10389 if (orig_mode
== mode
)
10391 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10393 /* In general we can't perform in wider mode for right shift and rotate. */
10397 /* We can still widen if the bits brought in from the left are identical
10398 to the sign bit of ORIG_MODE. */
10399 if (num_sign_bit_copies (op
, mode
)
10400 > (unsigned) (GET_MODE_PRECISION (mode
)
10401 - GET_MODE_PRECISION (orig_mode
)))
10406 /* Similarly here but with zero bits. */
10407 if (HWI_COMPUTABLE_MODE_P (mode
)
10408 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10411 /* We can also widen if the bits brought in will be masked off. This
10412 operation is performed in ORIG_MODE. */
10413 if (outer_code
== AND
)
10415 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10418 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10427 gcc_unreachable ();
10434 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10435 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10436 if we cannot simplify it. Otherwise, return a simplified value.
10438 The shift is normally computed in the widest mode we find in VAROP, as
10439 long as it isn't a different number of words than RESULT_MODE. Exceptions
10440 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10443 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10444 rtx varop
, int orig_count
)
10446 enum rtx_code orig_code
= code
;
10447 rtx orig_varop
= varop
;
10449 machine_mode mode
= result_mode
;
10450 machine_mode shift_mode
, tmode
;
10451 unsigned int mode_words
10452 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10453 /* We form (outer_op (code varop count) (outer_const)). */
10454 enum rtx_code outer_op
= UNKNOWN
;
10455 HOST_WIDE_INT outer_const
= 0;
10456 int complement_p
= 0;
10459 /* Make sure and truncate the "natural" shift on the way in. We don't
10460 want to do this inside the loop as it makes it more difficult to
10462 if (SHIFT_COUNT_TRUNCATED
)
10463 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10465 /* If we were given an invalid count, don't do anything except exactly
10466 what was requested. */
10468 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10471 count
= orig_count
;
10473 /* Unless one of the branches of the `if' in this loop does a `continue',
10474 we will `break' the loop after the `if'. */
10478 /* If we have an operand of (clobber (const_int 0)), fail. */
10479 if (GET_CODE (varop
) == CLOBBER
)
10482 /* Convert ROTATERT to ROTATE. */
10483 if (code
== ROTATERT
)
10485 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10487 count
= bitsize
- count
;
10490 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10491 mode
, outer_op
, outer_const
);
10492 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10494 /* Handle cases where the count is greater than the size of the mode
10495 minus 1. For ASHIFT, use the size minus one as the count (this can
10496 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10497 take the count modulo the size. For other shifts, the result is
10500 Since these shifts are being produced by the compiler by combining
10501 multiple operations, each of which are defined, we know what the
10502 result is supposed to be. */
10504 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10506 if (code
== ASHIFTRT
)
10507 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10508 else if (code
== ROTATE
|| code
== ROTATERT
)
10509 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10512 /* We can't simply return zero because there may be an
10514 varop
= const0_rtx
;
10520 /* If we discovered we had to complement VAROP, leave. Making a NOT
10521 here would cause an infinite loop. */
10525 if (shift_mode
== shift_unit_mode
)
10527 /* An arithmetic right shift of a quantity known to be -1 or 0
10529 if (code
== ASHIFTRT
10530 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10531 == GET_MODE_PRECISION (shift_unit_mode
)))
10537 /* If we are doing an arithmetic right shift and discarding all but
10538 the sign bit copies, this is equivalent to doing a shift by the
10539 bitsize minus one. Convert it into that shift because it will
10540 often allow other simplifications. */
10542 if (code
== ASHIFTRT
10543 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10544 >= GET_MODE_PRECISION (shift_unit_mode
)))
10545 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10547 /* We simplify the tests below and elsewhere by converting
10548 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10549 `make_compound_operation' will convert it to an ASHIFTRT for
10550 those machines (such as VAX) that don't have an LSHIFTRT. */
10551 if (code
== ASHIFTRT
10552 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10553 && val_signbit_known_clear_p (shift_unit_mode
,
10554 nonzero_bits (varop
,
10558 if (((code
== LSHIFTRT
10559 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10560 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10562 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10563 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10564 & GET_MODE_MASK (shift_unit_mode
))))
10565 && !side_effects_p (varop
))
10566 varop
= const0_rtx
;
10569 switch (GET_CODE (varop
))
10575 new_rtx
= expand_compound_operation (varop
);
10576 if (new_rtx
!= varop
)
10584 /* The following rules apply only to scalars. */
10585 if (shift_mode
!= shift_unit_mode
)
10588 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10589 minus the width of a smaller mode, we can do this with a
10590 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10591 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10592 && ! mode_dependent_address_p (XEXP (varop
, 0),
10593 MEM_ADDR_SPACE (varop
))
10594 && ! MEM_VOLATILE_P (varop
)
10595 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10596 MODE_INT
, 1)) != BLKmode
)
10598 new_rtx
= adjust_address_nv (varop
, tmode
,
10599 BYTES_BIG_ENDIAN
? 0
10600 : count
/ BITS_PER_UNIT
);
10602 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10603 : ZERO_EXTEND
, mode
, new_rtx
);
10610 /* The following rules apply only to scalars. */
10611 if (shift_mode
!= shift_unit_mode
)
10614 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10615 the same number of words as what we've seen so far. Then store
10616 the widest mode in MODE. */
10617 if (subreg_lowpart_p (varop
)
10618 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10619 > GET_MODE_SIZE (GET_MODE (varop
)))
10620 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10621 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10623 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10624 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10626 varop
= SUBREG_REG (varop
);
10627 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10628 mode
= GET_MODE (varop
);
10634 /* Some machines use MULT instead of ASHIFT because MULT
10635 is cheaper. But it is still better on those machines to
10636 merge two shifts into one. */
10637 if (CONST_INT_P (XEXP (varop
, 1))
10638 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10641 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10643 GEN_INT (exact_log2 (
10644 UINTVAL (XEXP (varop
, 1)))));
10650 /* Similar, for when divides are cheaper. */
10651 if (CONST_INT_P (XEXP (varop
, 1))
10652 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10655 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10657 GEN_INT (exact_log2 (
10658 UINTVAL (XEXP (varop
, 1)))));
10664 /* If we are extracting just the sign bit of an arithmetic
10665 right shift, that shift is not needed. However, the sign
10666 bit of a wider mode may be different from what would be
10667 interpreted as the sign bit in a narrower mode, so, if
10668 the result is narrower, don't discard the shift. */
10669 if (code
== LSHIFTRT
10670 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10671 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10672 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10674 varop
= XEXP (varop
, 0);
10683 /* The following rules apply only to scalars. */
10684 if (shift_mode
!= shift_unit_mode
)
10687 /* Here we have two nested shifts. The result is usually the
10688 AND of a new shift with a mask. We compute the result below. */
10689 if (CONST_INT_P (XEXP (varop
, 1))
10690 && INTVAL (XEXP (varop
, 1)) >= 0
10691 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10692 && HWI_COMPUTABLE_MODE_P (result_mode
)
10693 && HWI_COMPUTABLE_MODE_P (mode
))
10695 enum rtx_code first_code
= GET_CODE (varop
);
10696 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10697 unsigned HOST_WIDE_INT mask
;
10700 /* We have one common special case. We can't do any merging if
10701 the inner code is an ASHIFTRT of a smaller mode. However, if
10702 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10703 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10704 we can convert it to
10705 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10706 This simplifies certain SIGN_EXTEND operations. */
10707 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10708 && count
== (GET_MODE_PRECISION (result_mode
)
10709 - GET_MODE_PRECISION (GET_MODE (varop
))))
10711 /* C3 has the low-order C1 bits zero. */
10713 mask
= GET_MODE_MASK (mode
)
10714 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10716 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10717 XEXP (varop
, 0), mask
);
10718 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10720 count
= first_count
;
10725 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10726 than C1 high-order bits equal to the sign bit, we can convert
10727 this to either an ASHIFT or an ASHIFTRT depending on the
10730 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10732 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10733 && GET_MODE (varop
) == shift_mode
10734 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10737 varop
= XEXP (varop
, 0);
10738 count
-= first_count
;
10748 /* There are some cases we can't do. If CODE is ASHIFTRT,
10749 we can only do this if FIRST_CODE is also ASHIFTRT.
10751 We can't do the case when CODE is ROTATE and FIRST_CODE is
10754 If the mode of this shift is not the mode of the outer shift,
10755 we can't do this if either shift is a right shift or ROTATE.
10757 Finally, we can't do any of these if the mode is too wide
10758 unless the codes are the same.
10760 Handle the case where the shift codes are the same
10763 if (code
== first_code
)
10765 if (GET_MODE (varop
) != result_mode
10766 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10767 || code
== ROTATE
))
10770 count
+= first_count
;
10771 varop
= XEXP (varop
, 0);
10775 if (code
== ASHIFTRT
10776 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10777 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10778 || (GET_MODE (varop
) != result_mode
10779 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10780 || first_code
== ROTATE
10781 || code
== ROTATE
)))
10784 /* To compute the mask to apply after the shift, shift the
10785 nonzero bits of the inner shift the same way the
10786 outer shift will. */
10788 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10792 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10795 /* Give up if we can't compute an outer operation to use. */
10797 || !CONST_INT_P (mask_rtx
)
10798 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10800 result_mode
, &complement_p
))
10803 /* If the shifts are in the same direction, we add the
10804 counts. Otherwise, we subtract them. */
10805 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10806 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10807 count
+= first_count
;
10809 count
-= first_count
;
10811 /* If COUNT is positive, the new shift is usually CODE,
10812 except for the two exceptions below, in which case it is
10813 FIRST_CODE. If the count is negative, FIRST_CODE should
10816 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10817 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10819 else if (count
< 0)
10820 code
= first_code
, count
= -count
;
10822 varop
= XEXP (varop
, 0);
10826 /* If we have (A << B << C) for any shift, we can convert this to
10827 (A << C << B). This wins if A is a constant. Only try this if
10828 B is not a constant. */
10830 else if (GET_CODE (varop
) == code
10831 && CONST_INT_P (XEXP (varop
, 0))
10832 && !CONST_INT_P (XEXP (varop
, 1)))
10834 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10835 sure the result will be masked. See PR70222. */
10836 if (code
== LSHIFTRT
10837 && mode
!= result_mode
10838 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10839 GET_MODE_MASK (result_mode
)
10840 >> orig_count
, result_mode
,
10843 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10844 up outer sign extension (often left and right shift) is
10845 hardly more efficient than the original. See PR70429. */
10846 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10849 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10852 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10859 /* The following rules apply only to scalars. */
10860 if (shift_mode
!= shift_unit_mode
)
10863 /* Make this fit the case below. */
10864 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10870 /* The following rules apply only to scalars. */
10871 if (shift_mode
!= shift_unit_mode
)
10874 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10875 with C the size of VAROP - 1 and the shift is logical if
10876 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10877 we have an (le X 0) operation. If we have an arithmetic shift
10878 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10879 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10881 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10882 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10883 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10884 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10885 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10886 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10889 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10892 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10893 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10898 /* If we have (shift (logical)), move the logical to the outside
10899 to allow it to possibly combine with another logical and the
10900 shift to combine with another shift. This also canonicalizes to
10901 what a ZERO_EXTRACT looks like. Also, some machines have
10902 (and (shift)) insns. */
10904 if (CONST_INT_P (XEXP (varop
, 1))
10905 /* We can't do this if we have (ashiftrt (xor)) and the
10906 constant has its sign bit set in shift_mode with shift_mode
10907 wider than result_mode. */
10908 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10909 && result_mode
!= shift_mode
10910 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10912 && (new_rtx
= simplify_const_binary_operation
10913 (code
, result_mode
,
10914 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10915 GEN_INT (count
))) != 0
10916 && CONST_INT_P (new_rtx
)
10917 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10918 INTVAL (new_rtx
), result_mode
, &complement_p
))
10920 varop
= XEXP (varop
, 0);
10924 /* If we can't do that, try to simplify the shift in each arm of the
10925 logical expression, make a new logical expression, and apply
10926 the inverse distributive law. This also can't be done for
10927 (ashiftrt (xor)) where we've widened the shift and the constant
10928 changes the sign bit. */
10929 if (CONST_INT_P (XEXP (varop
, 1))
10930 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10931 && result_mode
!= shift_mode
10932 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10935 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10936 XEXP (varop
, 0), count
);
10937 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10938 XEXP (varop
, 1), count
);
10940 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10942 varop
= apply_distributive_law (varop
);
10950 /* The following rules apply only to scalars. */
10951 if (shift_mode
!= shift_unit_mode
)
10954 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10955 says that the sign bit can be tested, FOO has mode MODE, C is
10956 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10957 that may be nonzero. */
10958 if (code
== LSHIFTRT
10959 && XEXP (varop
, 1) == const0_rtx
10960 && GET_MODE (XEXP (varop
, 0)) == result_mode
10961 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10962 && HWI_COMPUTABLE_MODE_P (result_mode
)
10963 && STORE_FLAG_VALUE
== -1
10964 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10965 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10968 varop
= XEXP (varop
, 0);
10975 /* The following rules apply only to scalars. */
10976 if (shift_mode
!= shift_unit_mode
)
10979 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10980 than the number of bits in the mode is equivalent to A. */
10981 if (code
== LSHIFTRT
10982 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10983 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10985 varop
= XEXP (varop
, 0);
10990 /* NEG commutes with ASHIFT since it is multiplication. Move the
10991 NEG outside to allow shifts to combine. */
10993 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10996 varop
= XEXP (varop
, 0);
11002 /* The following rules apply only to scalars. */
11003 if (shift_mode
!= shift_unit_mode
)
11006 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11007 is one less than the number of bits in the mode is
11008 equivalent to (xor A 1). */
11009 if (code
== LSHIFTRT
11010 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
11011 && XEXP (varop
, 1) == constm1_rtx
11012 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
11013 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
11017 varop
= XEXP (varop
, 0);
11021 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11022 that might be nonzero in BAR are those being shifted out and those
11023 bits are known zero in FOO, we can replace the PLUS with FOO.
11024 Similarly in the other operand order. This code occurs when
11025 we are computing the size of a variable-size array. */
11027 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11028 && count
< HOST_BITS_PER_WIDE_INT
11029 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
11030 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
11031 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
11033 varop
= XEXP (varop
, 0);
11036 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11037 && count
< HOST_BITS_PER_WIDE_INT
11038 && HWI_COMPUTABLE_MODE_P (result_mode
)
11039 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
11041 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
11042 & nonzero_bits (XEXP (varop
, 1),
11045 varop
= XEXP (varop
, 1);
11049 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11051 && CONST_INT_P (XEXP (varop
, 1))
11052 && (new_rtx
= simplify_const_binary_operation
11053 (ASHIFT
, result_mode
,
11054 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
11055 GEN_INT (count
))) != 0
11056 && CONST_INT_P (new_rtx
)
11057 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11058 INTVAL (new_rtx
), result_mode
, &complement_p
))
11060 varop
= XEXP (varop
, 0);
11064 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11065 signbit', and attempt to change the PLUS to an XOR and move it to
11066 the outer operation as is done above in the AND/IOR/XOR case
11067 leg for shift(logical). See details in logical handling above
11068 for reasoning in doing so. */
11069 if (code
== LSHIFTRT
11070 && CONST_INT_P (XEXP (varop
, 1))
11071 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
11072 && (new_rtx
= simplify_const_binary_operation
11073 (code
, result_mode
,
11074 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
11075 GEN_INT (count
))) != 0
11076 && CONST_INT_P (new_rtx
)
11077 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11078 INTVAL (new_rtx
), result_mode
, &complement_p
))
11080 varop
= XEXP (varop
, 0);
11087 /* The following rules apply only to scalars. */
11088 if (shift_mode
!= shift_unit_mode
)
11091 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11092 with C the size of VAROP - 1 and the shift is logical if
11093 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11094 we have a (gt X 0) operation. If the shift is arithmetic with
11095 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11096 we have a (neg (gt X 0)) operation. */
11098 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11099 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11100 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
11101 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11102 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11103 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11104 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11107 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
11110 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11111 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
11118 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11119 if the truncate does not affect the value. */
11120 if (code
== LSHIFTRT
11121 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11122 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11123 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11124 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11125 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11127 rtx varop_inner
= XEXP (varop
, 0);
11130 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11131 XEXP (varop_inner
, 0),
11133 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11134 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11147 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
11148 outer_op
, outer_const
);
11150 /* We have now finished analyzing the shift. The result should be
11151 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11152 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11153 to the result of the shift. OUTER_CONST is the relevant constant,
11154 but we must turn off all bits turned off in the shift. */
11156 if (outer_op
== UNKNOWN
11157 && orig_code
== code
&& orig_count
== count
11158 && varop
== orig_varop
11159 && shift_mode
== GET_MODE (varop
))
11162 /* Make a SUBREG if necessary. If we can't make it, fail. */
11163 varop
= gen_lowpart (shift_mode
, varop
);
11164 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11167 /* If we have an outer operation and we just made a shift, it is
11168 possible that we could have simplified the shift were it not
11169 for the outer operation. So try to do the simplification
11172 if (outer_op
!= UNKNOWN
)
11173 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11178 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11180 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11181 turn off all the bits that the shift would have turned off. */
11182 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11183 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11184 GET_MODE_MASK (result_mode
) >> orig_count
);
11186 /* Do the remainder of the processing in RESULT_MODE. */
11187 x
= gen_lowpart_or_truncate (result_mode
, x
);
11189 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11192 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11194 if (outer_op
!= UNKNOWN
)
11196 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11197 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11198 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11200 if (outer_op
== AND
)
11201 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11202 else if (outer_op
== SET
)
11204 /* This means that we have determined that the result is
11205 equivalent to a constant. This should be rare. */
11206 if (!side_effects_p (x
))
11207 x
= GEN_INT (outer_const
);
11209 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11210 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11212 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11213 GEN_INT (outer_const
));
11219 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11220 The result of the shift is RESULT_MODE. If we cannot simplify it,
11221 return X or, if it is NULL, synthesize the expression with
11222 simplify_gen_binary. Otherwise, return a simplified value.
11224 The shift is normally computed in the widest mode we find in VAROP, as
11225 long as it isn't a different number of words than RESULT_MODE. Exceptions
11226 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11229 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11230 rtx varop
, int count
)
11232 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11237 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11238 if (GET_MODE (x
) != result_mode
)
11239 x
= gen_lowpart (result_mode
, x
);
11244 /* A subroutine of recog_for_combine. See there for arguments and
11248 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11250 rtx pat
= *pnewpat
;
11251 rtx pat_without_clobbers
;
11252 int insn_code_number
;
11253 int num_clobbers_to_add
= 0;
11255 rtx notes
= NULL_RTX
;
11256 rtx old_notes
, old_pat
;
11259 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11260 we use to indicate that something didn't match. If we find such a
11261 thing, force rejection. */
11262 if (GET_CODE (pat
) == PARALLEL
)
11263 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11264 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11265 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11268 old_pat
= PATTERN (insn
);
11269 old_notes
= REG_NOTES (insn
);
11270 PATTERN (insn
) = pat
;
11271 REG_NOTES (insn
) = NULL_RTX
;
11273 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11274 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11276 if (insn_code_number
< 0)
11277 fputs ("Failed to match this instruction:\n", dump_file
);
11279 fputs ("Successfully matched this instruction:\n", dump_file
);
11280 print_rtl_single (dump_file
, pat
);
11283 /* If it isn't, there is the possibility that we previously had an insn
11284 that clobbered some register as a side effect, but the combined
11285 insn doesn't need to do that. So try once more without the clobbers
11286 unless this represents an ASM insn. */
11288 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11289 && GET_CODE (pat
) == PARALLEL
)
11293 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11294 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11297 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11301 SUBST_INT (XVECLEN (pat
, 0), pos
);
11304 pat
= XVECEXP (pat
, 0, 0);
11306 PATTERN (insn
) = pat
;
11307 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11308 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11310 if (insn_code_number
< 0)
11311 fputs ("Failed to match this instruction:\n", dump_file
);
11313 fputs ("Successfully matched this instruction:\n", dump_file
);
11314 print_rtl_single (dump_file
, pat
);
11318 pat_without_clobbers
= pat
;
11320 PATTERN (insn
) = old_pat
;
11321 REG_NOTES (insn
) = old_notes
;
11323 /* Recognize all noop sets, these will be killed by followup pass. */
11324 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11325 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11327 /* If we had any clobbers to add, make a new pattern than contains
11328 them. Then check to make sure that all of them are dead. */
11329 if (num_clobbers_to_add
)
11331 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11332 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11333 ? (XVECLEN (pat
, 0)
11334 + num_clobbers_to_add
)
11335 : num_clobbers_to_add
+ 1));
11337 if (GET_CODE (pat
) == PARALLEL
)
11338 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11339 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11341 XVECEXP (newpat
, 0, 0) = pat
;
11343 add_clobbers (newpat
, insn_code_number
);
11345 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11346 i
< XVECLEN (newpat
, 0); i
++)
11348 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11349 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11351 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11353 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11354 notes
= alloc_reg_note (REG_UNUSED
,
11355 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11361 if (insn_code_number
>= 0
11362 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11364 old_pat
= PATTERN (insn
);
11365 old_notes
= REG_NOTES (insn
);
11366 old_icode
= INSN_CODE (insn
);
11367 PATTERN (insn
) = pat
;
11368 REG_NOTES (insn
) = notes
;
11369 INSN_CODE (insn
) = insn_code_number
;
11371 /* Allow targets to reject combined insn. */
11372 if (!targetm
.legitimate_combined_insn (insn
))
11374 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11375 fputs ("Instruction not appropriate for target.",
11378 /* Callers expect recog_for_combine to strip
11379 clobbers from the pattern on failure. */
11380 pat
= pat_without_clobbers
;
11383 insn_code_number
= -1;
11386 PATTERN (insn
) = old_pat
;
11387 REG_NOTES (insn
) = old_notes
;
11388 INSN_CODE (insn
) = old_icode
;
11394 return insn_code_number
;
11397 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11398 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11399 Return whether anything was so changed. */
11402 change_zero_ext (rtx pat
)
11404 bool changed
= false;
11405 rtx
*src
= &SET_SRC (pat
);
11407 subrtx_ptr_iterator::array_type array
;
11408 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11411 machine_mode mode
= GET_MODE (x
);
11414 if (GET_CODE (x
) == ZERO_EXTRACT
11415 && CONST_INT_P (XEXP (x
, 1))
11416 && CONST_INT_P (XEXP (x
, 2))
11417 && GET_MODE (XEXP (x
, 0)) != VOIDmode
11418 && GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
11419 <= GET_MODE_PRECISION (mode
))
11421 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
11423 size
= INTVAL (XEXP (x
, 1));
11425 int start
= INTVAL (XEXP (x
, 2));
11426 if (BITS_BIG_ENDIAN
)
11427 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11430 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11433 if (mode
!= inner_mode
)
11434 x
= gen_lowpart_SUBREG (mode
, x
);
11436 else if (GET_CODE (x
) == ZERO_EXTEND
11437 && SCALAR_INT_MODE_P (mode
)
11438 && GET_CODE (XEXP (x
, 0)) == SUBREG
11439 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11440 && !paradoxical_subreg_p (XEXP (x
, 0))
11441 && subreg_lowpart_p (XEXP (x
, 0)))
11443 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11444 x
= SUBREG_REG (XEXP (x
, 0));
11445 if (GET_MODE (x
) != mode
)
11446 x
= gen_lowpart_SUBREG (mode
, x
);
11448 else if (GET_CODE (x
) == ZERO_EXTEND
11449 && SCALAR_INT_MODE_P (mode
)
11450 && REG_P (XEXP (x
, 0))
11451 && HARD_REGISTER_P (XEXP (x
, 0))
11452 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11454 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11455 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11460 if (!(GET_CODE (x
) == LSHIFTRT
11461 && CONST_INT_P (XEXP (x
, 1))
11462 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11464 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11465 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11473 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11474 maybe_swap_commutative_operands (**iter
);
11476 rtx
*dst
= &SET_DEST (pat
);
11477 if (GET_CODE (*dst
) == ZERO_EXTRACT
11478 && REG_P (XEXP (*dst
, 0))
11479 && CONST_INT_P (XEXP (*dst
, 1))
11480 && CONST_INT_P (XEXP (*dst
, 2)))
11482 rtx reg
= XEXP (*dst
, 0);
11483 int width
= INTVAL (XEXP (*dst
, 1));
11484 int offset
= INTVAL (XEXP (*dst
, 2));
11485 machine_mode mode
= GET_MODE (reg
);
11486 int reg_width
= GET_MODE_PRECISION (mode
);
11487 if (BITS_BIG_ENDIAN
)
11488 offset
= reg_width
- width
- offset
;
11491 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11492 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11493 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11495 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11498 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11499 w
= gen_rtx_IOR (mode
, x
, z
);
11500 SUBST (SET_DEST (pat
), reg
);
11501 SUBST (SET_SRC (pat
), w
);
11509 /* Like recog, but we receive the address of a pointer to a new pattern.
11510 We try to match the rtx that the pointer points to.
11511 If that fails, we may try to modify or replace the pattern,
11512 storing the replacement into the same pointer object.
11514 Modifications include deletion or addition of CLOBBERs. If the
11515 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11516 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11517 (and undo if that fails).
11519 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11520 the CLOBBERs are placed.
11522 The value is the final insn code from the pattern ultimately matched,
11526 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11528 rtx pat
= *pnewpat
;
11529 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11530 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11531 return insn_code_number
;
11533 void *marker
= get_undo_marker ();
11534 bool changed
= false;
11536 if (GET_CODE (pat
) == SET
)
11537 changed
= change_zero_ext (pat
);
11538 else if (GET_CODE (pat
) == PARALLEL
)
11541 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11543 rtx set
= XVECEXP (pat
, 0, i
);
11544 if (GET_CODE (set
) == SET
)
11545 changed
|= change_zero_ext (set
);
11551 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11553 if (insn_code_number
< 0)
11554 undo_to_marker (marker
);
11557 return insn_code_number
;
11560 /* Like gen_lowpart_general but for use by combine. In combine it
11561 is not possible to create any new pseudoregs. However, it is
11562 safe to create invalid memory addresses, because combine will
11563 try to recognize them and all they will do is make the combine
11566 If for some reason this cannot do its job, an rtx
11567 (clobber (const_int 0)) is returned.
11568 An insn containing that will not be recognized. */
11571 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11573 machine_mode imode
= GET_MODE (x
);
11574 unsigned int osize
= GET_MODE_SIZE (omode
);
11575 unsigned int isize
= GET_MODE_SIZE (imode
);
11578 if (omode
== imode
)
11581 /* We can only support MODE being wider than a word if X is a
11582 constant integer or has a mode the same size. */
11583 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11584 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11587 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11588 won't know what to do. So we will strip off the SUBREG here and
11589 process normally. */
11590 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11592 x
= SUBREG_REG (x
);
11594 /* For use in case we fall down into the address adjustments
11595 further below, we need to adjust the known mode and size of
11596 x; imode and isize, since we just adjusted x. */
11597 imode
= GET_MODE (x
);
11599 if (imode
== omode
)
11602 isize
= GET_MODE_SIZE (imode
);
11605 result
= gen_lowpart_common (omode
, x
);
11614 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11616 if (MEM_VOLATILE_P (x
)
11617 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11620 /* If we want to refer to something bigger than the original memref,
11621 generate a paradoxical subreg instead. That will force a reload
11622 of the original memref X. */
11624 return gen_rtx_SUBREG (omode
, x
, 0);
11626 if (WORDS_BIG_ENDIAN
)
11627 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11629 /* Adjust the address so that the address-after-the-data is
11631 if (BYTES_BIG_ENDIAN
)
11632 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11634 return adjust_address_nv (x
, omode
, offset
);
11637 /* If X is a comparison operator, rewrite it in a new mode. This
11638 probably won't match, but may allow further simplifications. */
11639 else if (COMPARISON_P (x
))
11640 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11642 /* If we couldn't simplify X any other way, just enclose it in a
11643 SUBREG. Normally, this SUBREG won't match, but some patterns may
11644 include an explicit SUBREG or we may simplify it further in combine. */
11649 if (imode
== VOIDmode
)
11651 imode
= int_mode_for_mode (omode
);
11652 x
= gen_lowpart_common (imode
, x
);
11656 res
= lowpart_subreg (omode
, x
, imode
);
11662 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11665 /* Try to simplify a comparison between OP0 and a constant OP1,
11666 where CODE is the comparison code that will be tested, into a
11667 (CODE OP0 const0_rtx) form.
11669 The result is a possibly different comparison code to use.
11670 *POP1 may be updated. */
11672 static enum rtx_code
11673 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11674 rtx op0
, rtx
*pop1
)
11676 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11677 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11679 /* Get the constant we are comparing against and turn off all bits
11680 not on in our mode. */
11681 if (mode
!= VOIDmode
)
11682 const_op
= trunc_int_for_mode (const_op
, mode
);
11684 /* If we are comparing against a constant power of two and the value
11685 being compared can only have that single bit nonzero (e.g., it was
11686 `and'ed with that bit), we can replace this with a comparison
11689 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11690 || code
== LT
|| code
== LTU
)
11691 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11692 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11693 && (nonzero_bits (op0
, mode
)
11694 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11696 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11700 /* Similarly, if we are comparing a value known to be either -1 or
11701 0 with -1, change it to the opposite comparison against zero. */
11703 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11704 || code
== GEU
|| code
== LTU
)
11705 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11707 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11711 /* Do some canonicalizations based on the comparison code. We prefer
11712 comparisons against zero and then prefer equality comparisons.
11713 If we can reduce the size of a constant, we will do that too. */
11717 /* < C is equivalent to <= (C - 1) */
11722 /* ... fall through to LE case below. */
11723 gcc_fallthrough ();
11729 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11736 /* If we are doing a <= 0 comparison on a value known to have
11737 a zero sign bit, we can replace this with == 0. */
11738 else if (const_op
== 0
11739 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11740 && (nonzero_bits (op0
, mode
)
11741 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11747 /* >= C is equivalent to > (C - 1). */
11752 /* ... fall through to GT below. */
11753 gcc_fallthrough ();
11759 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11766 /* If we are doing a > 0 comparison on a value known to have
11767 a zero sign bit, we can replace this with != 0. */
11768 else if (const_op
== 0
11769 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11770 && (nonzero_bits (op0
, mode
)
11771 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11777 /* < C is equivalent to <= (C - 1). */
11782 /* ... fall through ... */
11784 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11785 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11786 && (unsigned HOST_WIDE_INT
) const_op
11787 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11797 /* unsigned <= 0 is equivalent to == 0 */
11800 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11801 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11802 && (unsigned HOST_WIDE_INT
) const_op
11803 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11811 /* >= C is equivalent to > (C - 1). */
11816 /* ... fall through ... */
11819 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11820 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11821 && (unsigned HOST_WIDE_INT
) const_op
11822 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11832 /* unsigned > 0 is equivalent to != 0 */
11835 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11836 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11837 && (unsigned HOST_WIDE_INT
) const_op
11838 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11849 *pop1
= GEN_INT (const_op
);
11853 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11854 comparison code that will be tested.
11856 The result is a possibly different comparison code to use. *POP0 and
11857 *POP1 may be updated.
11859 It is possible that we might detect that a comparison is either always
11860 true or always false. However, we do not perform general constant
11861 folding in combine, so this knowledge isn't useful. Such tautologies
11862 should have been detected earlier. Hence we ignore all such cases. */
11864 static enum rtx_code
11865 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11871 machine_mode mode
, tmode
;
11873 /* Try a few ways of applying the same transformation to both operands. */
11876 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11877 so check specially. */
11878 if (!WORD_REGISTER_OPERATIONS
11879 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11880 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11881 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11882 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11883 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11884 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11885 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11886 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11887 && CONST_INT_P (XEXP (op0
, 1))
11888 && XEXP (op0
, 1) == XEXP (op1
, 1)
11889 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11890 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11891 && (INTVAL (XEXP (op0
, 1))
11892 == (GET_MODE_PRECISION (GET_MODE (op0
))
11893 - (GET_MODE_PRECISION
11894 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11896 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11897 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11900 /* If both operands are the same constant shift, see if we can ignore the
11901 shift. We can if the shift is a rotate or if the bits shifted out of
11902 this shift are known to be zero for both inputs and if the type of
11903 comparison is compatible with the shift. */
11904 if (GET_CODE (op0
) == GET_CODE (op1
)
11905 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11906 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11907 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11908 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11909 || (GET_CODE (op0
) == ASHIFTRT
11910 && (code
!= GTU
&& code
!= LTU
11911 && code
!= GEU
&& code
!= LEU
)))
11912 && CONST_INT_P (XEXP (op0
, 1))
11913 && INTVAL (XEXP (op0
, 1)) >= 0
11914 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11915 && XEXP (op0
, 1) == XEXP (op1
, 1))
11917 machine_mode mode
= GET_MODE (op0
);
11918 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11919 int shift_count
= INTVAL (XEXP (op0
, 1));
11921 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11922 mask
&= (mask
>> shift_count
) << shift_count
;
11923 else if (GET_CODE (op0
) == ASHIFT
)
11924 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11926 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11927 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11928 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11933 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11934 SUBREGs are of the same mode, and, in both cases, the AND would
11935 be redundant if the comparison was done in the narrower mode,
11936 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11937 and the operand's possibly nonzero bits are 0xffffff01; in that case
11938 if we only care about QImode, we don't need the AND). This case
11939 occurs if the output mode of an scc insn is not SImode and
11940 STORE_FLAG_VALUE == 1 (e.g., the 386).
11942 Similarly, check for a case where the AND's are ZERO_EXTEND
11943 operations from some narrower mode even though a SUBREG is not
11946 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11947 && CONST_INT_P (XEXP (op0
, 1))
11948 && CONST_INT_P (XEXP (op1
, 1)))
11950 rtx inner_op0
= XEXP (op0
, 0);
11951 rtx inner_op1
= XEXP (op1
, 0);
11952 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11953 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11956 if (paradoxical_subreg_p (inner_op0
)
11957 && GET_CODE (inner_op1
) == SUBREG
11958 && (GET_MODE (SUBREG_REG (inner_op0
))
11959 == GET_MODE (SUBREG_REG (inner_op1
)))
11960 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11961 <= HOST_BITS_PER_WIDE_INT
)
11962 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11963 GET_MODE (SUBREG_REG (inner_op0
)))))
11964 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11965 GET_MODE (SUBREG_REG (inner_op1
))))))
11967 op0
= SUBREG_REG (inner_op0
);
11968 op1
= SUBREG_REG (inner_op1
);
11970 /* The resulting comparison is always unsigned since we masked
11971 off the original sign bit. */
11972 code
= unsigned_condition (code
);
11978 for (tmode
= GET_CLASS_NARROWEST_MODE
11979 (GET_MODE_CLASS (GET_MODE (op0
)));
11980 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11981 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11983 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11984 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11985 code
= unsigned_condition (code
);
11994 /* If both operands are NOT, we can strip off the outer operation
11995 and adjust the comparison code for swapped operands; similarly for
11996 NEG, except that this must be an equality comparison. */
11997 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11998 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11999 && (code
== EQ
|| code
== NE
)))
12000 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12006 /* If the first operand is a constant, swap the operands and adjust the
12007 comparison code appropriately, but don't do this if the second operand
12008 is already a constant integer. */
12009 if (swap_commutative_operands_p (op0
, op1
))
12011 std::swap (op0
, op1
);
12012 code
= swap_condition (code
);
12015 /* We now enter a loop during which we will try to simplify the comparison.
12016 For the most part, we only are concerned with comparisons with zero,
12017 but some things may really be comparisons with zero but not start
12018 out looking that way. */
12020 while (CONST_INT_P (op1
))
12022 machine_mode mode
= GET_MODE (op0
);
12023 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12024 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12025 int equality_comparison_p
;
12026 int sign_bit_comparison_p
;
12027 int unsigned_comparison_p
;
12028 HOST_WIDE_INT const_op
;
12030 /* We only want to handle integral modes. This catches VOIDmode,
12031 CCmode, and the floating-point modes. An exception is that we
12032 can handle VOIDmode if OP0 is a COMPARE or a comparison
12035 if (GET_MODE_CLASS (mode
) != MODE_INT
12036 && ! (mode
== VOIDmode
12037 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12040 /* Try to simplify the compare to constant, possibly changing the
12041 comparison op, and/or changing op1 to zero. */
12042 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
12043 const_op
= INTVAL (op1
);
12045 /* Compute some predicates to simplify code below. */
12047 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12048 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12049 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12052 /* If this is a sign bit comparison and we can do arithmetic in
12053 MODE, say that we will only be needing the sign bit of OP0. */
12054 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
12055 op0
= force_to_mode (op0
, mode
,
12057 << (GET_MODE_PRECISION (mode
) - 1),
12060 /* Now try cases based on the opcode of OP0. If none of the cases
12061 does a "continue", we exit this loop immediately after the
12064 switch (GET_CODE (op0
))
12067 /* If we are extracting a single bit from a variable position in
12068 a constant that has only a single bit set and are comparing it
12069 with zero, we can convert this into an equality comparison
12070 between the position and the location of the single bit. */
12071 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12072 have already reduced the shift count modulo the word size. */
12073 if (!SHIFT_COUNT_TRUNCATED
12074 && CONST_INT_P (XEXP (op0
, 0))
12075 && XEXP (op0
, 1) == const1_rtx
12076 && equality_comparison_p
&& const_op
== 0
12077 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12079 if (BITS_BIG_ENDIAN
)
12080 i
= BITS_PER_WORD
- 1 - i
;
12082 op0
= XEXP (op0
, 2);
12086 /* Result is nonzero iff shift count is equal to I. */
12087 code
= reverse_condition (code
);
12094 tem
= expand_compound_operation (op0
);
12103 /* If testing for equality, we can take the NOT of the constant. */
12104 if (equality_comparison_p
12105 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12107 op0
= XEXP (op0
, 0);
12112 /* If just looking at the sign bit, reverse the sense of the
12114 if (sign_bit_comparison_p
)
12116 op0
= XEXP (op0
, 0);
12117 code
= (code
== GE
? LT
: GE
);
12123 /* If testing for equality, we can take the NEG of the constant. */
12124 if (equality_comparison_p
12125 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12127 op0
= XEXP (op0
, 0);
12132 /* The remaining cases only apply to comparisons with zero. */
12136 /* When X is ABS or is known positive,
12137 (neg X) is < 0 if and only if X != 0. */
12139 if (sign_bit_comparison_p
12140 && (GET_CODE (XEXP (op0
, 0)) == ABS
12141 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12142 && (nonzero_bits (XEXP (op0
, 0), mode
)
12143 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12146 op0
= XEXP (op0
, 0);
12147 code
= (code
== LT
? NE
: EQ
);
12151 /* If we have NEG of something whose two high-order bits are the
12152 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12153 if (num_sign_bit_copies (op0
, mode
) >= 2)
12155 op0
= XEXP (op0
, 0);
12156 code
= swap_condition (code
);
12162 /* If we are testing equality and our count is a constant, we
12163 can perform the inverse operation on our RHS. */
12164 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12165 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12166 op1
, XEXP (op0
, 1))) != 0)
12168 op0
= XEXP (op0
, 0);
12173 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12174 a particular bit. Convert it to an AND of a constant of that
12175 bit. This will be converted into a ZERO_EXTRACT. */
12176 if (const_op
== 0 && sign_bit_comparison_p
12177 && CONST_INT_P (XEXP (op0
, 1))
12178 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12180 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12183 - INTVAL (XEXP (op0
, 1)))));
12184 code
= (code
== LT
? NE
: EQ
);
12188 /* Fall through. */
12191 /* ABS is ignorable inside an equality comparison with zero. */
12192 if (const_op
== 0 && equality_comparison_p
)
12194 op0
= XEXP (op0
, 0);
12200 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12201 (compare FOO CONST) if CONST fits in FOO's mode and we
12202 are either testing inequality or have an unsigned
12203 comparison with ZERO_EXTEND or a signed comparison with
12204 SIGN_EXTEND. But don't do it if we don't have a compare
12205 insn of the given mode, since we'd have to revert it
12206 later on, and then we wouldn't know whether to sign- or
12208 mode
= GET_MODE (XEXP (op0
, 0));
12209 if (GET_MODE_CLASS (mode
) == MODE_INT
12210 && ! unsigned_comparison_p
12211 && HWI_COMPUTABLE_MODE_P (mode
)
12212 && trunc_int_for_mode (const_op
, mode
) == const_op
12213 && have_insn_for (COMPARE
, mode
))
12215 op0
= XEXP (op0
, 0);
12221 /* Check for the case where we are comparing A - C1 with C2, that is
12223 (subreg:MODE (plus (A) (-C1))) op (C2)
12225 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12226 comparison in the wider mode. One of the following two conditions
12227 must be true in order for this to be valid:
12229 1. The mode extension results in the same bit pattern being added
12230 on both sides and the comparison is equality or unsigned. As
12231 C2 has been truncated to fit in MODE, the pattern can only be
12234 2. The mode extension results in the sign bit being copied on
12237 The difficulty here is that we have predicates for A but not for
12238 (A - C1) so we need to check that C1 is within proper bounds so
12239 as to perturbate A as little as possible. */
12241 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12242 && subreg_lowpart_p (op0
)
12243 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12244 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12245 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12247 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12248 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12249 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12252 && (unsigned HOST_WIDE_INT
) c1
12253 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12254 && (equality_comparison_p
|| unsigned_comparison_p
)
12255 /* (A - C1) zero-extends if it is positive and sign-extends
12256 if it is negative, C2 both zero- and sign-extends. */
12257 && ((0 == (nonzero_bits (a
, inner_mode
)
12258 & ~GET_MODE_MASK (mode
))
12260 /* (A - C1) sign-extends if it is positive and 1-extends
12261 if it is negative, C2 both sign- and 1-extends. */
12262 || (num_sign_bit_copies (a
, inner_mode
)
12263 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12266 || ((unsigned HOST_WIDE_INT
) c1
12267 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12268 /* (A - C1) always sign-extends, like C2. */
12269 && num_sign_bit_copies (a
, inner_mode
)
12270 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12271 - (mode_width
- 1))))
12273 op0
= SUBREG_REG (op0
);
12278 /* If the inner mode is narrower and we are extracting the low part,
12279 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12280 if (subreg_lowpart_p (op0
)
12281 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
12283 else if (subreg_lowpart_p (op0
)
12284 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12285 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12286 && (code
== NE
|| code
== EQ
)
12287 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12288 <= HOST_BITS_PER_WIDE_INT
)
12289 && !paradoxical_subreg_p (op0
)
12290 && (nonzero_bits (SUBREG_REG (op0
),
12291 GET_MODE (SUBREG_REG (op0
)))
12292 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12294 /* Remove outer subregs that don't do anything. */
12295 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12297 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12298 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12300 op0
= SUBREG_REG (op0
);
12312 mode
= GET_MODE (XEXP (op0
, 0));
12313 if (GET_MODE_CLASS (mode
) == MODE_INT
12314 && (unsigned_comparison_p
|| equality_comparison_p
)
12315 && HWI_COMPUTABLE_MODE_P (mode
)
12316 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12318 && have_insn_for (COMPARE
, mode
))
12320 op0
= XEXP (op0
, 0);
12326 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12327 this for equality comparisons due to pathological cases involving
12329 if (equality_comparison_p
12330 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12331 op1
, XEXP (op0
, 1))))
12333 op0
= XEXP (op0
, 0);
12338 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12339 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12340 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12342 op0
= XEXP (XEXP (op0
, 0), 0);
12343 code
= (code
== LT
? EQ
: NE
);
12349 /* We used to optimize signed comparisons against zero, but that
12350 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12351 arrive here as equality comparisons, or (GEU, LTU) are
12352 optimized away. No need to special-case them. */
12354 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12355 (eq B (minus A C)), whichever simplifies. We can only do
12356 this for equality comparisons due to pathological cases involving
12358 if (equality_comparison_p
12359 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12360 XEXP (op0
, 1), op1
)))
12362 op0
= XEXP (op0
, 0);
12367 if (equality_comparison_p
12368 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12369 XEXP (op0
, 0), op1
)))
12371 op0
= XEXP (op0
, 1);
12376 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12377 of bits in X minus 1, is one iff X > 0. */
12378 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12379 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12380 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12381 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12383 op0
= XEXP (op0
, 1);
12384 code
= (code
== GE
? LE
: GT
);
12390 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12391 if C is zero or B is a constant. */
12392 if (equality_comparison_p
12393 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12394 XEXP (op0
, 1), op1
)))
12396 op0
= XEXP (op0
, 0);
12403 case UNEQ
: case LTGT
:
12404 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12405 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12406 case UNORDERED
: case ORDERED
:
12407 /* We can't do anything if OP0 is a condition code value, rather
12408 than an actual data value. */
12410 || CC0_P (XEXP (op0
, 0))
12411 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12414 /* Get the two operands being compared. */
12415 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12416 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12418 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12420 /* Check for the cases where we simply want the result of the
12421 earlier test or the opposite of that result. */
12422 if (code
== NE
|| code
== EQ
12423 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12424 && (code
== LT
|| code
== GE
)))
12426 enum rtx_code new_code
;
12427 if (code
== LT
|| code
== NE
)
12428 new_code
= GET_CODE (op0
);
12430 new_code
= reversed_comparison_code (op0
, NULL
);
12432 if (new_code
!= UNKNOWN
)
12443 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12445 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12446 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12447 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12449 op0
= XEXP (op0
, 1);
12450 code
= (code
== GE
? GT
: LE
);
12456 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12457 will be converted to a ZERO_EXTRACT later. */
12458 if (const_op
== 0 && equality_comparison_p
12459 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12460 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12462 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12463 XEXP (XEXP (op0
, 0), 1));
12464 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12468 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12469 zero and X is a comparison and C1 and C2 describe only bits set
12470 in STORE_FLAG_VALUE, we can compare with X. */
12471 if (const_op
== 0 && equality_comparison_p
12472 && mode_width
<= HOST_BITS_PER_WIDE_INT
12473 && CONST_INT_P (XEXP (op0
, 1))
12474 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12475 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12476 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12477 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12479 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12480 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12481 if ((~STORE_FLAG_VALUE
& mask
) == 0
12482 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12483 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12484 && COMPARISON_P (tem
))))
12486 op0
= XEXP (XEXP (op0
, 0), 0);
12491 /* If we are doing an equality comparison of an AND of a bit equal
12492 to the sign bit, replace this with a LT or GE comparison of
12493 the underlying value. */
12494 if (equality_comparison_p
12496 && CONST_INT_P (XEXP (op0
, 1))
12497 && mode_width
<= HOST_BITS_PER_WIDE_INT
12498 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12499 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12501 op0
= XEXP (op0
, 0);
12502 code
= (code
== EQ
? GE
: LT
);
12506 /* If this AND operation is really a ZERO_EXTEND from a narrower
12507 mode, the constant fits within that mode, and this is either an
12508 equality or unsigned comparison, try to do this comparison in
12513 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12514 -> (ne:DI (reg:SI 4) (const_int 0))
12516 unless TRULY_NOOP_TRUNCATION allows it or the register is
12517 known to hold a value of the required mode the
12518 transformation is invalid. */
12519 if ((equality_comparison_p
|| unsigned_comparison_p
)
12520 && CONST_INT_P (XEXP (op0
, 1))
12521 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12522 & GET_MODE_MASK (mode
))
12524 && const_op
>> i
== 0
12525 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12527 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12531 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12532 fits in both M1 and M2 and the SUBREG is either paradoxical
12533 or represents the low part, permute the SUBREG and the AND
12535 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12536 && CONST_INT_P (XEXP (op0
, 1)))
12538 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12539 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12540 /* Require an integral mode, to avoid creating something like
12542 if (SCALAR_INT_MODE_P (tmode
)
12543 /* It is unsafe to commute the AND into the SUBREG if the
12544 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12545 not defined. As originally written the upper bits
12546 have a defined value due to the AND operation.
12547 However, if we commute the AND inside the SUBREG then
12548 they no longer have defined values and the meaning of
12549 the code has been changed.
12550 Also C1 should not change value in the smaller mode,
12551 see PR67028 (a positive C1 can become negative in the
12552 smaller mode, so that the AND does no longer mask the
12554 && ((WORD_REGISTER_OPERATIONS
12555 && mode_width
> GET_MODE_PRECISION (tmode
)
12556 && mode_width
<= BITS_PER_WORD
12557 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12558 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12559 && subreg_lowpart_p (XEXP (op0
, 0))))
12560 && mode_width
<= HOST_BITS_PER_WIDE_INT
12561 && HWI_COMPUTABLE_MODE_P (tmode
)
12562 && (c1
& ~mask
) == 0
12563 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12565 && c1
!= GET_MODE_MASK (tmode
))
12567 op0
= simplify_gen_binary (AND
, tmode
,
12568 SUBREG_REG (XEXP (op0
, 0)),
12569 gen_int_mode (c1
, tmode
));
12570 op0
= gen_lowpart (mode
, op0
);
12575 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12576 if (const_op
== 0 && equality_comparison_p
12577 && XEXP (op0
, 1) == const1_rtx
12578 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12580 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12581 XEXP (XEXP (op0
, 0), 0), 1);
12582 code
= (code
== NE
? EQ
: NE
);
12586 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12587 (eq (and (lshiftrt X) 1) 0).
12588 Also handle the case where (not X) is expressed using xor. */
12589 if (const_op
== 0 && equality_comparison_p
12590 && XEXP (op0
, 1) == const1_rtx
12591 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12593 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12594 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12596 if (GET_CODE (shift_op
) == NOT
12597 || (GET_CODE (shift_op
) == XOR
12598 && CONST_INT_P (XEXP (shift_op
, 1))
12599 && CONST_INT_P (shift_count
)
12600 && HWI_COMPUTABLE_MODE_P (mode
)
12601 && (UINTVAL (XEXP (shift_op
, 1))
12602 == HOST_WIDE_INT_1U
12603 << INTVAL (shift_count
))))
12606 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12607 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12608 code
= (code
== NE
? EQ
: NE
);
12615 /* If we have (compare (ashift FOO N) (const_int C)) and
12616 the high order N bits of FOO (N+1 if an inequality comparison)
12617 are known to be zero, we can do this by comparing FOO with C
12618 shifted right N bits so long as the low-order N bits of C are
12620 if (CONST_INT_P (XEXP (op0
, 1))
12621 && INTVAL (XEXP (op0
, 1)) >= 0
12622 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12623 < HOST_BITS_PER_WIDE_INT
)
12624 && (((unsigned HOST_WIDE_INT
) const_op
12625 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12627 && mode_width
<= HOST_BITS_PER_WIDE_INT
12628 && (nonzero_bits (XEXP (op0
, 0), mode
)
12629 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12630 + ! equality_comparison_p
))) == 0)
12632 /* We must perform a logical shift, not an arithmetic one,
12633 as we want the top N bits of C to be zero. */
12634 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12636 temp
>>= INTVAL (XEXP (op0
, 1));
12637 op1
= gen_int_mode (temp
, mode
);
12638 op0
= XEXP (op0
, 0);
12642 /* If we are doing a sign bit comparison, it means we are testing
12643 a particular bit. Convert it to the appropriate AND. */
12644 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12645 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12647 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12650 - INTVAL (XEXP (op0
, 1)))));
12651 code
= (code
== LT
? NE
: EQ
);
12655 /* If this an equality comparison with zero and we are shifting
12656 the low bit to the sign bit, we can convert this to an AND of the
12658 if (const_op
== 0 && equality_comparison_p
12659 && CONST_INT_P (XEXP (op0
, 1))
12660 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12662 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12668 /* If this is an equality comparison with zero, we can do this
12669 as a logical shift, which might be much simpler. */
12670 if (equality_comparison_p
&& const_op
== 0
12671 && CONST_INT_P (XEXP (op0
, 1)))
12673 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12675 INTVAL (XEXP (op0
, 1)));
12679 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12680 do the comparison in a narrower mode. */
12681 if (! unsigned_comparison_p
12682 && CONST_INT_P (XEXP (op0
, 1))
12683 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12684 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12685 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12686 MODE_INT
, 1)) != BLKmode
12687 && (((unsigned HOST_WIDE_INT
) const_op
12688 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12689 <= GET_MODE_MASK (tmode
)))
12691 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12695 /* Likewise if OP0 is a PLUS of a sign extension with a
12696 constant, which is usually represented with the PLUS
12697 between the shifts. */
12698 if (! unsigned_comparison_p
12699 && CONST_INT_P (XEXP (op0
, 1))
12700 && GET_CODE (XEXP (op0
, 0)) == PLUS
12701 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12702 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12703 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12704 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12705 MODE_INT
, 1)) != BLKmode
12706 && (((unsigned HOST_WIDE_INT
) const_op
12707 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12708 <= GET_MODE_MASK (tmode
)))
12710 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12711 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12712 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12713 add_const
, XEXP (op0
, 1));
12715 op0
= simplify_gen_binary (PLUS
, tmode
,
12716 gen_lowpart (tmode
, inner
),
12723 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12724 the low order N bits of FOO are known to be zero, we can do this
12725 by comparing FOO with C shifted left N bits so long as no
12726 overflow occurs. Even if the low order N bits of FOO aren't known
12727 to be zero, if the comparison is >= or < we can use the same
12728 optimization and for > or <= by setting all the low
12729 order N bits in the comparison constant. */
12730 if (CONST_INT_P (XEXP (op0
, 1))
12731 && INTVAL (XEXP (op0
, 1)) > 0
12732 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12733 && mode_width
<= HOST_BITS_PER_WIDE_INT
12734 && (((unsigned HOST_WIDE_INT
) const_op
12735 + (GET_CODE (op0
) != LSHIFTRT
12736 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12739 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12741 unsigned HOST_WIDE_INT low_bits
12742 = (nonzero_bits (XEXP (op0
, 0), mode
)
12743 & ((HOST_WIDE_INT_1U
12744 << INTVAL (XEXP (op0
, 1))) - 1));
12745 if (low_bits
== 0 || !equality_comparison_p
)
12747 /* If the shift was logical, then we must make the condition
12749 if (GET_CODE (op0
) == LSHIFTRT
)
12750 code
= unsigned_condition (code
);
12752 const_op
= (unsigned HOST_WIDE_INT
) const_op
12753 << INTVAL (XEXP (op0
, 1));
12755 && (code
== GT
|| code
== GTU
12756 || code
== LE
|| code
== LEU
))
12758 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12759 op1
= GEN_INT (const_op
);
12760 op0
= XEXP (op0
, 0);
12765 /* If we are using this shift to extract just the sign bit, we
12766 can replace this with an LT or GE comparison. */
12768 && (equality_comparison_p
|| sign_bit_comparison_p
)
12769 && CONST_INT_P (XEXP (op0
, 1))
12770 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12772 op0
= XEXP (op0
, 0);
12773 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12785 /* Now make any compound operations involved in this comparison. Then,
12786 check for an outmost SUBREG on OP0 that is not doing anything or is
12787 paradoxical. The latter transformation must only be performed when
12788 it is known that the "extra" bits will be the same in op0 and op1 or
12789 that they don't matter. There are three cases to consider:
12791 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12792 care bits and we can assume they have any convenient value. So
12793 making the transformation is safe.
12795 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12796 In this case the upper bits of op0 are undefined. We should not make
12797 the simplification in that case as we do not know the contents of
12800 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12801 In that case we know those bits are zeros or ones. We must also be
12802 sure that they are the same as the upper bits of op1.
12804 We can never remove a SUBREG for a non-equality comparison because
12805 the sign bit is in a different place in the underlying object. */
12807 rtx_code op0_mco_code
= SET
;
12808 if (op1
== const0_rtx
)
12809 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12811 op0
= make_compound_operation (op0
, op0_mco_code
);
12812 op1
= make_compound_operation (op1
, SET
);
12814 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12815 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12816 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12817 && (code
== NE
|| code
== EQ
))
12819 if (paradoxical_subreg_p (op0
))
12821 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12823 if (REG_P (SUBREG_REG (op0
)))
12825 op0
= SUBREG_REG (op0
);
12826 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12829 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12830 <= HOST_BITS_PER_WIDE_INT
)
12831 && (nonzero_bits (SUBREG_REG (op0
),
12832 GET_MODE (SUBREG_REG (op0
)))
12833 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12835 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12837 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12838 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12839 op0
= SUBREG_REG (op0
), op1
= tem
;
12843 /* We now do the opposite procedure: Some machines don't have compare
12844 insns in all modes. If OP0's mode is an integer mode smaller than a
12845 word and we can't do a compare in that mode, see if there is a larger
12846 mode for which we can do the compare. There are a number of cases in
12847 which we can use the wider mode. */
12849 mode
= GET_MODE (op0
);
12850 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12851 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12852 && ! have_insn_for (COMPARE
, mode
))
12853 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12854 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12855 tmode
= GET_MODE_WIDER_MODE (tmode
))
12856 if (have_insn_for (COMPARE
, tmode
))
12860 /* If this is a test for negative, we can make an explicit
12861 test of the sign bit. Test this first so we can use
12862 a paradoxical subreg to extend OP0. */
12864 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12865 && HWI_COMPUTABLE_MODE_P (mode
))
12867 unsigned HOST_WIDE_INT sign
12868 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12869 op0
= simplify_gen_binary (AND
, tmode
,
12870 gen_lowpart (tmode
, op0
),
12871 gen_int_mode (sign
, tmode
));
12872 code
= (code
== LT
) ? NE
: EQ
;
12876 /* If the only nonzero bits in OP0 and OP1 are those in the
12877 narrower mode and this is an equality or unsigned comparison,
12878 we can use the wider mode. Similarly for sign-extended
12879 values, in which case it is true for all comparisons. */
12880 zero_extended
= ((code
== EQ
|| code
== NE
12881 || code
== GEU
|| code
== GTU
12882 || code
== LEU
|| code
== LTU
)
12883 && (nonzero_bits (op0
, tmode
)
12884 & ~GET_MODE_MASK (mode
)) == 0
12885 && ((CONST_INT_P (op1
)
12886 || (nonzero_bits (op1
, tmode
)
12887 & ~GET_MODE_MASK (mode
)) == 0)));
12890 || ((num_sign_bit_copies (op0
, tmode
)
12891 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12892 - GET_MODE_PRECISION (mode
)))
12893 && (num_sign_bit_copies (op1
, tmode
)
12894 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12895 - GET_MODE_PRECISION (mode
)))))
12897 /* If OP0 is an AND and we don't have an AND in MODE either,
12898 make a new AND in the proper mode. */
12899 if (GET_CODE (op0
) == AND
12900 && !have_insn_for (AND
, mode
))
12901 op0
= simplify_gen_binary (AND
, tmode
,
12902 gen_lowpart (tmode
,
12904 gen_lowpart (tmode
,
12910 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12911 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12915 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12916 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12923 /* We may have changed the comparison operands. Re-canonicalize. */
12924 if (swap_commutative_operands_p (op0
, op1
))
12926 std::swap (op0
, op1
);
12927 code
= swap_condition (code
);
12930 /* If this machine only supports a subset of valid comparisons, see if we
12931 can convert an unsupported one into a supported one. */
12932 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12940 /* Utility function for record_value_for_reg. Count number of
12945 enum rtx_code code
= GET_CODE (x
);
12949 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12950 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12952 rtx x0
= XEXP (x
, 0);
12953 rtx x1
= XEXP (x
, 1);
12956 return 1 + 2 * count_rtxs (x0
);
12958 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12959 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12960 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12961 return 2 + 2 * count_rtxs (x0
)
12962 + count_rtxs (x
== XEXP (x1
, 0)
12963 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12965 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12966 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12967 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12968 return 2 + 2 * count_rtxs (x1
)
12969 + count_rtxs (x
== XEXP (x0
, 0)
12970 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12973 fmt
= GET_RTX_FORMAT (code
);
12974 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12976 ret
+= count_rtxs (XEXP (x
, i
));
12977 else if (fmt
[i
] == 'E')
12978 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12979 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12984 /* Utility function for following routine. Called when X is part of a value
12985 being stored into last_set_value. Sets last_set_table_tick
12986 for each register mentioned. Similar to mention_regs in cse.c */
12989 update_table_tick (rtx x
)
12991 enum rtx_code code
= GET_CODE (x
);
12992 const char *fmt
= GET_RTX_FORMAT (code
);
12997 unsigned int regno
= REGNO (x
);
12998 unsigned int endregno
= END_REGNO (x
);
13001 for (r
= regno
; r
< endregno
; r
++)
13003 reg_stat_type
*rsp
= ®_stat
[r
];
13004 rsp
->last_set_table_tick
= label_tick
;
13010 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13013 /* Check for identical subexpressions. If x contains
13014 identical subexpression we only have to traverse one of
13016 if (i
== 0 && ARITHMETIC_P (x
))
13018 /* Note that at this point x1 has already been
13020 rtx x0
= XEXP (x
, 0);
13021 rtx x1
= XEXP (x
, 1);
13023 /* If x0 and x1 are identical then there is no need to
13028 /* If x0 is identical to a subexpression of x1 then while
13029 processing x1, x0 has already been processed. Thus we
13030 are done with x. */
13031 if (ARITHMETIC_P (x1
)
13032 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13035 /* If x1 is identical to a subexpression of x0 then we
13036 still have to process the rest of x0. */
13037 if (ARITHMETIC_P (x0
)
13038 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13040 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13045 update_table_tick (XEXP (x
, i
));
13047 else if (fmt
[i
] == 'E')
13048 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13049 update_table_tick (XVECEXP (x
, i
, j
));
13052 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13053 are saying that the register is clobbered and we no longer know its
13054 value. If INSN is zero, don't update reg_stat[].last_set; this is
13055 only permitted with VALUE also zero and is used to invalidate the
13059 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13061 unsigned int regno
= REGNO (reg
);
13062 unsigned int endregno
= END_REGNO (reg
);
13064 reg_stat_type
*rsp
;
13066 /* If VALUE contains REG and we have a previous value for REG, substitute
13067 the previous value. */
13068 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13072 /* Set things up so get_last_value is allowed to see anything set up to
13074 subst_low_luid
= DF_INSN_LUID (insn
);
13075 tem
= get_last_value (reg
);
13077 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13078 it isn't going to be useful and will take a lot of time to process,
13079 so just use the CLOBBER. */
13083 if (ARITHMETIC_P (tem
)
13084 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13085 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13086 tem
= XEXP (tem
, 0);
13087 else if (count_occurrences (value
, reg
, 1) >= 2)
13089 /* If there are two or more occurrences of REG in VALUE,
13090 prevent the value from growing too much. */
13091 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
13092 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13095 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13099 /* For each register modified, show we don't know its value, that
13100 we don't know about its bitwise content, that its value has been
13101 updated, and that we don't know the location of the death of the
13103 for (i
= regno
; i
< endregno
; i
++)
13105 rsp
= ®_stat
[i
];
13108 rsp
->last_set
= insn
;
13110 rsp
->last_set_value
= 0;
13111 rsp
->last_set_mode
= VOIDmode
;
13112 rsp
->last_set_nonzero_bits
= 0;
13113 rsp
->last_set_sign_bit_copies
= 0;
13114 rsp
->last_death
= 0;
13115 rsp
->truncated_to_mode
= VOIDmode
;
13118 /* Mark registers that are being referenced in this value. */
13120 update_table_tick (value
);
13122 /* Now update the status of each register being set.
13123 If someone is using this register in this block, set this register
13124 to invalid since we will get confused between the two lives in this
13125 basic block. This makes using this register always invalid. In cse, we
13126 scan the table to invalidate all entries using this register, but this
13127 is too much work for us. */
13129 for (i
= regno
; i
< endregno
; i
++)
13131 rsp
= ®_stat
[i
];
13132 rsp
->last_set_label
= label_tick
;
13134 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13135 rsp
->last_set_invalid
= 1;
13137 rsp
->last_set_invalid
= 0;
13140 /* The value being assigned might refer to X (like in "x++;"). In that
13141 case, we must replace it with (clobber (const_int 0)) to prevent
13143 rsp
= ®_stat
[regno
];
13144 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13146 value
= copy_rtx (value
);
13147 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13151 /* For the main register being modified, update the value, the mode, the
13152 nonzero bits, and the number of sign bit copies. */
13154 rsp
->last_set_value
= value
;
13158 machine_mode mode
= GET_MODE (reg
);
13159 subst_low_luid
= DF_INSN_LUID (insn
);
13160 rsp
->last_set_mode
= mode
;
13161 if (GET_MODE_CLASS (mode
) == MODE_INT
13162 && HWI_COMPUTABLE_MODE_P (mode
))
13163 mode
= nonzero_bits_mode
;
13164 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13165 rsp
->last_set_sign_bit_copies
13166 = num_sign_bit_copies (value
, GET_MODE (reg
));
13170 /* Called via note_stores from record_dead_and_set_regs to handle one
13171 SET or CLOBBER in an insn. DATA is the instruction in which the
13172 set is occurring. */
13175 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13177 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13179 if (GET_CODE (dest
) == SUBREG
)
13180 dest
= SUBREG_REG (dest
);
13182 if (!record_dead_insn
)
13185 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13191 /* If we are setting the whole register, we know its value. Otherwise
13192 show that we don't know the value. We can handle SUBREG in
13194 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13195 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13196 else if (GET_CODE (setter
) == SET
13197 && GET_CODE (SET_DEST (setter
)) == SUBREG
13198 && SUBREG_REG (SET_DEST (setter
)) == dest
13199 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13200 && subreg_lowpart_p (SET_DEST (setter
)))
13201 record_value_for_reg (dest
, record_dead_insn
,
13202 gen_lowpart (GET_MODE (dest
),
13203 SET_SRC (setter
)));
13205 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13207 else if (MEM_P (dest
)
13208 /* Ignore pushes, they clobber nothing. */
13209 && ! push_operand (dest
, GET_MODE (dest
)))
13210 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13213 /* Update the records of when each REG was most recently set or killed
13214 for the things done by INSN. This is the last thing done in processing
13215 INSN in the combiner loop.
13217 We update reg_stat[], in particular fields last_set, last_set_value,
13218 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13219 last_death, and also the similar information mem_last_set (which insn
13220 most recently modified memory) and last_call_luid (which insn was the
13221 most recent subroutine call). */
13224 record_dead_and_set_regs (rtx_insn
*insn
)
13229 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13231 if (REG_NOTE_KIND (link
) == REG_DEAD
13232 && REG_P (XEXP (link
, 0)))
13234 unsigned int regno
= REGNO (XEXP (link
, 0));
13235 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13237 for (i
= regno
; i
< endregno
; i
++)
13239 reg_stat_type
*rsp
;
13241 rsp
= ®_stat
[i
];
13242 rsp
->last_death
= insn
;
13245 else if (REG_NOTE_KIND (link
) == REG_INC
)
13246 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13251 hard_reg_set_iterator hrsi
;
13252 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13254 reg_stat_type
*rsp
;
13256 rsp
= ®_stat
[i
];
13257 rsp
->last_set_invalid
= 1;
13258 rsp
->last_set
= insn
;
13259 rsp
->last_set_value
= 0;
13260 rsp
->last_set_mode
= VOIDmode
;
13261 rsp
->last_set_nonzero_bits
= 0;
13262 rsp
->last_set_sign_bit_copies
= 0;
13263 rsp
->last_death
= 0;
13264 rsp
->truncated_to_mode
= VOIDmode
;
13267 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13269 /* We can't combine into a call pattern. Remember, though, that
13270 the return value register is set at this LUID. We could
13271 still replace a register with the return value from the
13272 wrong subroutine call! */
13273 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13276 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13279 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13280 register present in the SUBREG, so for each such SUBREG go back and
13281 adjust nonzero and sign bit information of the registers that are
13282 known to have some zero/sign bits set.
13284 This is needed because when combine blows the SUBREGs away, the
13285 information on zero/sign bits is lost and further combines can be
13286 missed because of that. */
13289 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13291 struct insn_link
*links
;
13293 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13294 machine_mode mode
= GET_MODE (subreg
);
13296 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13299 for (links
= LOG_LINKS (insn
); links
;)
13301 reg_stat_type
*rsp
;
13303 insn
= links
->insn
;
13304 set
= single_set (insn
);
13306 if (! set
|| !REG_P (SET_DEST (set
))
13307 || REGNO (SET_DEST (set
)) != regno
13308 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13310 links
= links
->next
;
13314 rsp
= ®_stat
[regno
];
13315 if (rsp
->last_set
== insn
)
13317 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13318 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13321 if (REG_P (SET_SRC (set
)))
13323 regno
= REGNO (SET_SRC (set
));
13324 links
= LOG_LINKS (insn
);
13331 /* Check if X, a register, is known to contain a value already
13332 truncated to MODE. In this case we can use a subreg to refer to
13333 the truncated value even though in the generic case we would need
13334 an explicit truncation. */
13337 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13339 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13340 machine_mode truncated
= rsp
->truncated_to_mode
;
13343 || rsp
->truncation_label
< label_tick_ebb_start
)
13345 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13347 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13352 /* If X is a hard reg or a subreg record the mode that the register is
13353 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13354 to turn a truncate into a subreg using this information. Return true
13355 if traversing X is complete. */
13358 record_truncated_value (rtx x
)
13360 machine_mode truncated_mode
;
13361 reg_stat_type
*rsp
;
13363 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13365 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13366 truncated_mode
= GET_MODE (x
);
13368 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13371 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13374 x
= SUBREG_REG (x
);
13376 /* ??? For hard-regs we now record everything. We might be able to
13377 optimize this using last_set_mode. */
13378 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13379 truncated_mode
= GET_MODE (x
);
13383 rsp
= ®_stat
[REGNO (x
)];
13384 if (rsp
->truncated_to_mode
== 0
13385 || rsp
->truncation_label
< label_tick_ebb_start
13386 || (GET_MODE_SIZE (truncated_mode
)
13387 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13389 rsp
->truncated_to_mode
= truncated_mode
;
13390 rsp
->truncation_label
= label_tick
;
13396 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13397 the modes they are used in. This can help truning TRUNCATEs into
13401 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13403 subrtx_var_iterator::array_type array
;
13404 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13405 if (record_truncated_value (*iter
))
13406 iter
.skip_subrtxes ();
13409 /* Scan X for promoted SUBREGs. For each one found,
13410 note what it implies to the registers used in it. */
13413 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13415 if (GET_CODE (x
) == SUBREG
13416 && SUBREG_PROMOTED_VAR_P (x
)
13417 && REG_P (SUBREG_REG (x
)))
13418 record_promoted_value (insn
, x
);
13421 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13424 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13428 check_promoted_subreg (insn
, XEXP (x
, i
));
13432 if (XVEC (x
, i
) != 0)
13433 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13434 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13440 /* Verify that all the registers and memory references mentioned in *LOC are
13441 still valid. *LOC was part of a value set in INSN when label_tick was
13442 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13443 the invalid references with (clobber (const_int 0)) and return 1. This
13444 replacement is useful because we often can get useful information about
13445 the form of a value (e.g., if it was produced by a shift that always
13446 produces -1 or 0) even though we don't know exactly what registers it
13447 was produced from. */
13450 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13453 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13454 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13459 unsigned int regno
= REGNO (x
);
13460 unsigned int endregno
= END_REGNO (x
);
13463 for (j
= regno
; j
< endregno
; j
++)
13465 reg_stat_type
*rsp
= ®_stat
[j
];
13466 if (rsp
->last_set_invalid
13467 /* If this is a pseudo-register that was only set once and not
13468 live at the beginning of the function, it is always valid. */
13469 || (! (regno
>= FIRST_PSEUDO_REGISTER
13470 && regno
< reg_n_sets_max
13471 && REG_N_SETS (regno
) == 1
13472 && (!REGNO_REG_SET_P
13473 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13475 && rsp
->last_set_label
> tick
))
13478 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13485 /* If this is a memory reference, make sure that there were no stores after
13486 it that might have clobbered the value. We don't have alias info, so we
13487 assume any store invalidates it. Moreover, we only have local UIDs, so
13488 we also assume that there were stores in the intervening basic blocks. */
13489 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13490 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13493 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13497 for (i
= 0; i
< len
; i
++)
13501 /* Check for identical subexpressions. If x contains
13502 identical subexpression we only have to traverse one of
13504 if (i
== 1 && ARITHMETIC_P (x
))
13506 /* Note that at this point x0 has already been checked
13507 and found valid. */
13508 rtx x0
= XEXP (x
, 0);
13509 rtx x1
= XEXP (x
, 1);
13511 /* If x0 and x1 are identical then x is also valid. */
13515 /* If x1 is identical to a subexpression of x0 then
13516 while checking x0, x1 has already been checked. Thus
13517 it is valid and so as x. */
13518 if (ARITHMETIC_P (x0
)
13519 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13522 /* If x0 is identical to a subexpression of x1 then x is
13523 valid iff the rest of x1 is valid. */
13524 if (ARITHMETIC_P (x1
)
13525 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13527 get_last_value_validate (&XEXP (x1
,
13528 x0
== XEXP (x1
, 0) ? 1 : 0),
13529 insn
, tick
, replace
);
13532 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13536 else if (fmt
[i
] == 'E')
13537 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13538 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13539 insn
, tick
, replace
) == 0)
13543 /* If we haven't found a reason for it to be invalid, it is valid. */
13547 /* Get the last value assigned to X, if known. Some registers
13548 in the value may be replaced with (clobber (const_int 0)) if their value
13549 is known longer known reliably. */
13552 get_last_value (const_rtx x
)
13554 unsigned int regno
;
13556 reg_stat_type
*rsp
;
13558 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13559 then convert it to the desired mode. If this is a paradoxical SUBREG,
13560 we cannot predict what values the "extra" bits might have. */
13561 if (GET_CODE (x
) == SUBREG
13562 && subreg_lowpart_p (x
)
13563 && !paradoxical_subreg_p (x
)
13564 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13565 return gen_lowpart (GET_MODE (x
), value
);
13571 rsp
= ®_stat
[regno
];
13572 value
= rsp
->last_set_value
;
13574 /* If we don't have a value, or if it isn't for this basic block and
13575 it's either a hard register, set more than once, or it's a live
13576 at the beginning of the function, return 0.
13578 Because if it's not live at the beginning of the function then the reg
13579 is always set before being used (is never used without being set).
13580 And, if it's set only once, and it's always set before use, then all
13581 uses must have the same last value, even if it's not from this basic
13585 || (rsp
->last_set_label
< label_tick_ebb_start
13586 && (regno
< FIRST_PSEUDO_REGISTER
13587 || regno
>= reg_n_sets_max
13588 || REG_N_SETS (regno
) != 1
13590 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13593 /* If the value was set in a later insn than the ones we are processing,
13594 we can't use it even if the register was only set once. */
13595 if (rsp
->last_set_label
== label_tick
13596 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13599 /* If fewer bits were set than what we are asked for now, we cannot use
13601 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13602 < GET_MODE_PRECISION (GET_MODE (x
)))
13605 /* If the value has all its registers valid, return it. */
13606 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13609 /* Otherwise, make a copy and replace any invalid register with
13610 (clobber (const_int 0)). If that fails for some reason, return 0. */
13612 value
= copy_rtx (value
);
13613 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13619 /* Return nonzero if expression X refers to a REG or to memory
13620 that is set in an instruction more recent than FROM_LUID. */
13623 use_crosses_set_p (const_rtx x
, int from_luid
)
13627 enum rtx_code code
= GET_CODE (x
);
13631 unsigned int regno
= REGNO (x
);
13632 unsigned endreg
= END_REGNO (x
);
13634 #ifdef PUSH_ROUNDING
13635 /* Don't allow uses of the stack pointer to be moved,
13636 because we don't know whether the move crosses a push insn. */
13637 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13640 for (; regno
< endreg
; regno
++)
13642 reg_stat_type
*rsp
= ®_stat
[regno
];
13644 && rsp
->last_set_label
== label_tick
13645 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13651 if (code
== MEM
&& mem_last_set
> from_luid
)
13654 fmt
= GET_RTX_FORMAT (code
);
13656 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13661 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13662 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13665 else if (fmt
[i
] == 'e'
13666 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13672 /* Define three variables used for communication between the following
13675 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13676 static int reg_dead_flag
;
13678 /* Function called via note_stores from reg_dead_at_p.
13680 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13681 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13684 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13686 unsigned int regno
, endregno
;
13691 regno
= REGNO (dest
);
13692 endregno
= END_REGNO (dest
);
13693 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13694 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13697 /* Return nonzero if REG is known to be dead at INSN.
13699 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13700 referencing REG, it is dead. If we hit a SET referencing REG, it is
13701 live. Otherwise, see if it is live or dead at the start of the basic
13702 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13703 must be assumed to be always live. */
13706 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13711 /* Set variables for reg_dead_at_p_1. */
13712 reg_dead_regno
= REGNO (reg
);
13713 reg_dead_endregno
= END_REGNO (reg
);
13717 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13718 we allow the machine description to decide whether use-and-clobber
13719 patterns are OK. */
13720 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13722 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13723 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13727 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13728 beginning of basic block. */
13729 block
= BLOCK_FOR_INSN (insn
);
13734 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13737 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13739 return reg_dead_flag
== 1 ? 1 : 0;
13741 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13745 if (insn
== BB_HEAD (block
))
13748 insn
= PREV_INSN (insn
);
13751 /* Look at live-in sets for the basic block that we were in. */
13752 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13753 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13759 /* Note hard registers in X that are used. */
13762 mark_used_regs_combine (rtx x
)
13764 RTX_CODE code
= GET_CODE (x
);
13765 unsigned int regno
;
13776 case ADDR_DIFF_VEC
:
13778 /* CC0 must die in the insn after it is set, so we don't need to take
13779 special note of it here. */
13784 /* If we are clobbering a MEM, mark any hard registers inside the
13785 address as used. */
13786 if (MEM_P (XEXP (x
, 0)))
13787 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13792 /* A hard reg in a wide mode may really be multiple registers.
13793 If so, mark all of them just like the first. */
13794 if (regno
< FIRST_PSEUDO_REGISTER
)
13796 /* None of this applies to the stack, frame or arg pointers. */
13797 if (regno
== STACK_POINTER_REGNUM
13798 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13799 && regno
== HARD_FRAME_POINTER_REGNUM
)
13800 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13801 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13802 || regno
== FRAME_POINTER_REGNUM
)
13805 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13811 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13813 rtx testreg
= SET_DEST (x
);
13815 while (GET_CODE (testreg
) == SUBREG
13816 || GET_CODE (testreg
) == ZERO_EXTRACT
13817 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13818 testreg
= XEXP (testreg
, 0);
13820 if (MEM_P (testreg
))
13821 mark_used_regs_combine (XEXP (testreg
, 0));
13823 mark_used_regs_combine (SET_SRC (x
));
13831 /* Recursively scan the operands of this expression. */
13834 const char *fmt
= GET_RTX_FORMAT (code
);
13836 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13839 mark_used_regs_combine (XEXP (x
, i
));
13840 else if (fmt
[i
] == 'E')
13844 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13845 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13851 /* Remove register number REGNO from the dead registers list of INSN.
13853 Return the note used to record the death, if there was one. */
13856 remove_death (unsigned int regno
, rtx_insn
*insn
)
13858 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13861 remove_note (insn
, note
);
13866 /* For each register (hardware or pseudo) used within expression X, if its
13867 death is in an instruction with luid between FROM_LUID (inclusive) and
13868 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13869 list headed by PNOTES.
13871 That said, don't move registers killed by maybe_kill_insn.
13873 This is done when X is being merged by combination into TO_INSN. These
13874 notes will then be distributed as needed. */
13877 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13882 enum rtx_code code
= GET_CODE (x
);
13886 unsigned int regno
= REGNO (x
);
13887 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13889 /* Don't move the register if it gets killed in between from and to. */
13890 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13891 && ! reg_referenced_p (x
, maybe_kill_insn
))
13895 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13896 && DF_INSN_LUID (where_dead
) >= from_luid
13897 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13899 rtx note
= remove_death (regno
, where_dead
);
13901 /* It is possible for the call above to return 0. This can occur
13902 when last_death points to I2 or I1 that we combined with.
13903 In that case make a new note.
13905 We must also check for the case where X is a hard register
13906 and NOTE is a death note for a range of hard registers
13907 including X. In that case, we must put REG_DEAD notes for
13908 the remaining registers in place of NOTE. */
13910 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13911 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13912 > GET_MODE_SIZE (GET_MODE (x
))))
13914 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13915 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13916 unsigned int ourend
= END_REGNO (x
);
13919 for (i
= deadregno
; i
< deadend
; i
++)
13920 if (i
< regno
|| i
>= ourend
)
13921 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13924 /* If we didn't find any note, or if we found a REG_DEAD note that
13925 covers only part of the given reg, and we have a multi-reg hard
13926 register, then to be safe we must check for REG_DEAD notes
13927 for each register other than the first. They could have
13928 their own REG_DEAD notes lying around. */
13929 else if ((note
== 0
13931 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13932 < GET_MODE_SIZE (GET_MODE (x
)))))
13933 && regno
< FIRST_PSEUDO_REGISTER
13934 && REG_NREGS (x
) > 1)
13936 unsigned int ourend
= END_REGNO (x
);
13937 unsigned int i
, offset
;
13941 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13945 for (i
= regno
+ offset
; i
< ourend
; i
++)
13946 move_deaths (regno_reg_rtx
[i
],
13947 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13950 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13952 XEXP (note
, 1) = *pnotes
;
13956 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13962 else if (GET_CODE (x
) == SET
)
13964 rtx dest
= SET_DEST (x
);
13966 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13968 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13969 that accesses one word of a multi-word item, some
13970 piece of everything register in the expression is used by
13971 this insn, so remove any old death. */
13972 /* ??? So why do we test for equality of the sizes? */
13974 if (GET_CODE (dest
) == ZERO_EXTRACT
13975 || GET_CODE (dest
) == STRICT_LOW_PART
13976 || (GET_CODE (dest
) == SUBREG
13977 && (((GET_MODE_SIZE (GET_MODE (dest
))
13978 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13979 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13980 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13982 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13986 /* If this is some other SUBREG, we know it replaces the entire
13987 value, so use that as the destination. */
13988 if (GET_CODE (dest
) == SUBREG
)
13989 dest
= SUBREG_REG (dest
);
13991 /* If this is a MEM, adjust deaths of anything used in the address.
13992 For a REG (the only other possibility), the entire value is
13993 being replaced so the old value is not used in this insn. */
13996 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14001 else if (GET_CODE (x
) == CLOBBER
)
14004 len
= GET_RTX_LENGTH (code
);
14005 fmt
= GET_RTX_FORMAT (code
);
14007 for (i
= 0; i
< len
; i
++)
14012 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14013 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14016 else if (fmt
[i
] == 'e')
14017 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14021 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14022 pattern of an insn. X must be a REG. */
14025 reg_bitfield_target_p (rtx x
, rtx body
)
14029 if (GET_CODE (body
) == SET
)
14031 rtx dest
= SET_DEST (body
);
14033 unsigned int regno
, tregno
, endregno
, endtregno
;
14035 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14036 target
= XEXP (dest
, 0);
14037 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14038 target
= SUBREG_REG (XEXP (dest
, 0));
14042 if (GET_CODE (target
) == SUBREG
)
14043 target
= SUBREG_REG (target
);
14045 if (!REG_P (target
))
14048 tregno
= REGNO (target
), regno
= REGNO (x
);
14049 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14050 return target
== x
;
14052 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14053 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14055 return endregno
> tregno
&& regno
< endtregno
;
14058 else if (GET_CODE (body
) == PARALLEL
)
14059 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14060 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14066 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14067 as appropriate. I3 and I2 are the insns resulting from the combination
14068 insns including FROM (I2 may be zero).
14070 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14071 not need REG_DEAD notes because they are being substituted for. This
14072 saves searching in the most common cases.
14074 Each note in the list is either ignored or placed on some insns, depending
14075 on the type of note. */
14078 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14079 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14081 rtx note
, next_note
;
14083 rtx_insn
*tem_insn
;
14085 for (note
= notes
; note
; note
= next_note
)
14087 rtx_insn
*place
= 0, *place2
= 0;
14089 next_note
= XEXP (note
, 1);
14090 switch (REG_NOTE_KIND (note
))
14094 /* Doesn't matter much where we put this, as long as it's somewhere.
14095 It is preferable to keep these notes on branches, which is most
14096 likely to be i3. */
14100 case REG_NON_LOCAL_GOTO
:
14105 gcc_assert (i2
&& JUMP_P (i2
));
14110 case REG_EH_REGION
:
14111 /* These notes must remain with the call or trapping instruction. */
14114 else if (i2
&& CALL_P (i2
))
14118 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14119 if (may_trap_p (i3
))
14121 else if (i2
&& may_trap_p (i2
))
14123 /* ??? Otherwise assume we've combined things such that we
14124 can now prove that the instructions can't trap. Drop the
14125 note in this case. */
14129 case REG_ARGS_SIZE
:
14130 /* ??? How to distribute between i3-i1. Assume i3 contains the
14131 entire adjustment. Assert i3 contains at least some adjust. */
14132 if (!noop_move_p (i3
))
14134 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14135 /* fixup_args_size_notes looks at REG_NORETURN note,
14136 so ensure the note is placed there first. */
14140 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14141 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14145 XEXP (n
, 1) = REG_NOTES (i3
);
14146 REG_NOTES (i3
) = n
;
14150 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14151 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14152 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14153 gcc_assert (old_size
!= args_size
14155 && !ACCUMULATE_OUTGOING_ARGS
14156 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14163 case REG_CALL_DECL
:
14164 /* These notes must remain with the call. It should not be
14165 possible for both I2 and I3 to be a call. */
14170 gcc_assert (i2
&& CALL_P (i2
));
14176 /* Any clobbers for i3 may still exist, and so we must process
14177 REG_UNUSED notes from that insn.
14179 Any clobbers from i2 or i1 can only exist if they were added by
14180 recog_for_combine. In that case, recog_for_combine created the
14181 necessary REG_UNUSED notes. Trying to keep any original
14182 REG_UNUSED notes from these insns can cause incorrect output
14183 if it is for the same register as the original i3 dest.
14184 In that case, we will notice that the register is set in i3,
14185 and then add a REG_UNUSED note for the destination of i3, which
14186 is wrong. However, it is possible to have REG_UNUSED notes from
14187 i2 or i1 for register which were both used and clobbered, so
14188 we keep notes from i2 or i1 if they will turn into REG_DEAD
14191 /* If this register is set or clobbered in I3, put the note there
14192 unless there is one already. */
14193 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14195 if (from_insn
!= i3
)
14198 if (! (REG_P (XEXP (note
, 0))
14199 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14200 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14203 /* Otherwise, if this register is used by I3, then this register
14204 now dies here, so we must put a REG_DEAD note here unless there
14206 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14207 && ! (REG_P (XEXP (note
, 0))
14208 ? find_regno_note (i3
, REG_DEAD
,
14209 REGNO (XEXP (note
, 0)))
14210 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14212 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14220 /* These notes say something about results of an insn. We can
14221 only support them if they used to be on I3 in which case they
14222 remain on I3. Otherwise they are ignored.
14224 If the note refers to an expression that is not a constant, we
14225 must also ignore the note since we cannot tell whether the
14226 equivalence is still true. It might be possible to do
14227 slightly better than this (we only have a problem if I2DEST
14228 or I1DEST is present in the expression), but it doesn't
14229 seem worth the trouble. */
14231 if (from_insn
== i3
14232 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14237 /* These notes say something about how a register is used. They must
14238 be present on any use of the register in I2 or I3. */
14239 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14242 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14251 case REG_LABEL_TARGET
:
14252 case REG_LABEL_OPERAND
:
14253 /* This can show up in several ways -- either directly in the
14254 pattern, or hidden off in the constant pool with (or without?)
14255 a REG_EQUAL note. */
14256 /* ??? Ignore the without-reg_equal-note problem for now. */
14257 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14258 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14259 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14260 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14264 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14265 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14266 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14267 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14275 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14276 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14278 if (place
&& JUMP_P (place
)
14279 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14280 && (JUMP_LABEL (place
) == NULL
14281 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14283 rtx label
= JUMP_LABEL (place
);
14286 JUMP_LABEL (place
) = XEXP (note
, 0);
14287 else if (LABEL_P (label
))
14288 LABEL_NUSES (label
)--;
14291 if (place2
&& JUMP_P (place2
)
14292 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14293 && (JUMP_LABEL (place2
) == NULL
14294 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14296 rtx label
= JUMP_LABEL (place2
);
14299 JUMP_LABEL (place2
) = XEXP (note
, 0);
14300 else if (LABEL_P (label
))
14301 LABEL_NUSES (label
)--;
14307 /* This note says something about the value of a register prior
14308 to the execution of an insn. It is too much trouble to see
14309 if the note is still correct in all situations. It is better
14310 to simply delete it. */
14314 /* If we replaced the right hand side of FROM_INSN with a
14315 REG_EQUAL note, the original use of the dying register
14316 will not have been combined into I3 and I2. In such cases,
14317 FROM_INSN is guaranteed to be the first of the combined
14318 instructions, so we simply need to search back before
14319 FROM_INSN for the previous use or set of this register,
14320 then alter the notes there appropriately.
14322 If the register is used as an input in I3, it dies there.
14323 Similarly for I2, if it is nonzero and adjacent to I3.
14325 If the register is not used as an input in either I3 or I2
14326 and it is not one of the registers we were supposed to eliminate,
14327 there are two possibilities. We might have a non-adjacent I2
14328 or we might have somehow eliminated an additional register
14329 from a computation. For example, we might have had A & B where
14330 we discover that B will always be zero. In this case we will
14331 eliminate the reference to A.
14333 In both cases, we must search to see if we can find a previous
14334 use of A and put the death note there. */
14337 && from_insn
== i2mod
14338 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14339 tem_insn
= from_insn
;
14343 && CALL_P (from_insn
)
14344 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14346 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14348 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14349 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14351 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14353 && reg_overlap_mentioned_p (XEXP (note
, 0),
14355 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14356 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14359 /* If the new I2 sets the same register that is marked dead
14360 in the note, we do not know where to put the note.
14362 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14368 basic_block bb
= this_basic_block
;
14370 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14372 if (!NONDEBUG_INSN_P (tem_insn
))
14374 if (tem_insn
== BB_HEAD (bb
))
14379 /* If the register is being set at TEM_INSN, see if that is all
14380 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14381 into a REG_UNUSED note instead. Don't delete sets to
14382 global register vars. */
14383 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14384 || !global_regs
[REGNO (XEXP (note
, 0))])
14385 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14387 rtx set
= single_set (tem_insn
);
14388 rtx inner_dest
= 0;
14389 rtx_insn
*cc0_setter
= NULL
;
14392 for (inner_dest
= SET_DEST (set
);
14393 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14394 || GET_CODE (inner_dest
) == SUBREG
14395 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14396 inner_dest
= XEXP (inner_dest
, 0))
14399 /* Verify that it was the set, and not a clobber that
14400 modified the register.
14402 CC0 targets must be careful to maintain setter/user
14403 pairs. If we cannot delete the setter due to side
14404 effects, mark the user with an UNUSED note instead
14407 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14408 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14410 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14411 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14412 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14414 /* Move the notes and links of TEM_INSN elsewhere.
14415 This might delete other dead insns recursively.
14416 First set the pattern to something that won't use
14418 rtx old_notes
= REG_NOTES (tem_insn
);
14420 PATTERN (tem_insn
) = pc_rtx
;
14421 REG_NOTES (tem_insn
) = NULL
;
14423 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14424 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14425 distribute_links (LOG_LINKS (tem_insn
));
14427 unsigned int regno
= REGNO (XEXP (note
, 0));
14428 reg_stat_type
*rsp
= ®_stat
[regno
];
14429 if (rsp
->last_set
== tem_insn
)
14430 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14432 SET_INSN_DELETED (tem_insn
);
14433 if (tem_insn
== i2
)
14436 /* Delete the setter too. */
14439 PATTERN (cc0_setter
) = pc_rtx
;
14440 old_notes
= REG_NOTES (cc0_setter
);
14441 REG_NOTES (cc0_setter
) = NULL
;
14443 distribute_notes (old_notes
, cc0_setter
,
14445 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14446 distribute_links (LOG_LINKS (cc0_setter
));
14448 SET_INSN_DELETED (cc0_setter
);
14449 if (cc0_setter
== i2
)
14455 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14457 /* If there isn't already a REG_UNUSED note, put one
14458 here. Do not place a REG_DEAD note, even if
14459 the register is also used here; that would not
14460 match the algorithm used in lifetime analysis
14461 and can cause the consistency check in the
14462 scheduler to fail. */
14463 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14464 REGNO (XEXP (note
, 0))))
14469 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14470 || (CALL_P (tem_insn
)
14471 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14475 /* If we are doing a 3->2 combination, and we have a
14476 register which formerly died in i3 and was not used
14477 by i2, which now no longer dies in i3 and is used in
14478 i2 but does not die in i2, and place is between i2
14479 and i3, then we may need to move a link from place to
14481 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14483 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14484 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14486 struct insn_link
*links
= LOG_LINKS (place
);
14487 LOG_LINKS (place
) = NULL
;
14488 distribute_links (links
);
14493 if (tem_insn
== BB_HEAD (bb
))
14499 /* If the register is set or already dead at PLACE, we needn't do
14500 anything with this note if it is still a REG_DEAD note.
14501 We check here if it is set at all, not if is it totally replaced,
14502 which is what `dead_or_set_p' checks, so also check for it being
14505 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14507 unsigned int regno
= REGNO (XEXP (note
, 0));
14508 reg_stat_type
*rsp
= ®_stat
[regno
];
14510 if (dead_or_set_p (place
, XEXP (note
, 0))
14511 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14513 /* Unless the register previously died in PLACE, clear
14514 last_death. [I no longer understand why this is
14516 if (rsp
->last_death
!= place
)
14517 rsp
->last_death
= 0;
14521 rsp
->last_death
= place
;
14523 /* If this is a death note for a hard reg that is occupying
14524 multiple registers, ensure that we are still using all
14525 parts of the object. If we find a piece of the object
14526 that is unused, we must arrange for an appropriate REG_DEAD
14527 note to be added for it. However, we can't just emit a USE
14528 and tag the note to it, since the register might actually
14529 be dead; so we recourse, and the recursive call then finds
14530 the previous insn that used this register. */
14532 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14534 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14535 bool all_used
= true;
14538 for (i
= regno
; i
< endregno
; i
++)
14539 if ((! refers_to_regno_p (i
, PATTERN (place
))
14540 && ! find_regno_fusage (place
, USE
, i
))
14541 || dead_or_set_regno_p (place
, i
))
14549 /* Put only REG_DEAD notes for pieces that are
14550 not already dead or set. */
14552 for (i
= regno
; i
< endregno
;
14553 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14555 rtx piece
= regno_reg_rtx
[i
];
14556 basic_block bb
= this_basic_block
;
14558 if (! dead_or_set_p (place
, piece
)
14559 && ! reg_bitfield_target_p (piece
,
14562 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14565 distribute_notes (new_note
, place
, place
,
14566 NULL
, NULL_RTX
, NULL_RTX
,
14569 else if (! refers_to_regno_p (i
, PATTERN (place
))
14570 && ! find_regno_fusage (place
, USE
, i
))
14571 for (tem_insn
= PREV_INSN (place
); ;
14572 tem_insn
= PREV_INSN (tem_insn
))
14574 if (!NONDEBUG_INSN_P (tem_insn
))
14576 if (tem_insn
== BB_HEAD (bb
))
14580 if (dead_or_set_p (tem_insn
, piece
)
14581 || reg_bitfield_target_p (piece
,
14582 PATTERN (tem_insn
)))
14584 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14597 /* Any other notes should not be present at this point in the
14599 gcc_unreachable ();
14604 XEXP (note
, 1) = REG_NOTES (place
);
14605 REG_NOTES (place
) = note
;
14609 add_shallow_copy_of_reg_note (place2
, note
);
14613 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14614 I3, I2, and I1 to new locations. This is also called to add a link
14615 pointing at I3 when I3's destination is changed. */
14618 distribute_links (struct insn_link
*links
)
14620 struct insn_link
*link
, *next_link
;
14622 for (link
= links
; link
; link
= next_link
)
14624 rtx_insn
*place
= 0;
14628 next_link
= link
->next
;
14630 /* If the insn that this link points to is a NOTE, ignore it. */
14631 if (NOTE_P (link
->insn
))
14635 rtx pat
= PATTERN (link
->insn
);
14636 if (GET_CODE (pat
) == SET
)
14638 else if (GET_CODE (pat
) == PARALLEL
)
14641 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14643 set
= XVECEXP (pat
, 0, i
);
14644 if (GET_CODE (set
) != SET
)
14647 reg
= SET_DEST (set
);
14648 while (GET_CODE (reg
) == ZERO_EXTRACT
14649 || GET_CODE (reg
) == STRICT_LOW_PART
14650 || GET_CODE (reg
) == SUBREG
)
14651 reg
= XEXP (reg
, 0);
14656 if (REGNO (reg
) == link
->regno
)
14659 if (i
== XVECLEN (pat
, 0))
14665 reg
= SET_DEST (set
);
14667 while (GET_CODE (reg
) == ZERO_EXTRACT
14668 || GET_CODE (reg
) == STRICT_LOW_PART
14669 || GET_CODE (reg
) == SUBREG
)
14670 reg
= XEXP (reg
, 0);
14672 /* A LOG_LINK is defined as being placed on the first insn that uses
14673 a register and points to the insn that sets the register. Start
14674 searching at the next insn after the target of the link and stop
14675 when we reach a set of the register or the end of the basic block.
14677 Note that this correctly handles the link that used to point from
14678 I3 to I2. Also note that not much searching is typically done here
14679 since most links don't point very far away. */
14681 for (insn
= NEXT_INSN (link
->insn
);
14682 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14683 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14684 insn
= NEXT_INSN (insn
))
14685 if (DEBUG_INSN_P (insn
))
14687 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14689 if (reg_referenced_p (reg
, PATTERN (insn
)))
14693 else if (CALL_P (insn
)
14694 && find_reg_fusage (insn
, USE
, reg
))
14699 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14702 /* If we found a place to put the link, place it there unless there
14703 is already a link to the same insn as LINK at that point. */
14707 struct insn_link
*link2
;
14709 FOR_EACH_LOG_LINK (link2
, place
)
14710 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14715 link
->next
= LOG_LINKS (place
);
14716 LOG_LINKS (place
) = link
;
14718 /* Set added_links_insn to the earliest insn we added a
14720 if (added_links_insn
== 0
14721 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14722 added_links_insn
= place
;
14728 /* Check for any register or memory mentioned in EQUIV that is not
14729 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14730 of EXPR where some registers may have been replaced by constants. */
14733 unmentioned_reg_p (rtx equiv
, rtx expr
)
14735 subrtx_iterator::array_type array
;
14736 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14738 const_rtx x
= *iter
;
14739 if ((REG_P (x
) || MEM_P (x
))
14740 && !reg_mentioned_p (x
, expr
))
14746 DEBUG_FUNCTION
void
14747 dump_combine_stats (FILE *file
)
14751 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14752 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14756 dump_combine_total_stats (FILE *file
)
14760 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14761 total_attempts
, total_merges
, total_extras
, total_successes
);
14764 /* Try combining insns through substitution. */
14765 static unsigned int
14766 rest_of_handle_combine (void)
14768 int rebuild_jump_labels_after_combine
;
14770 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14771 df_note_add_problem ();
14774 regstat_init_n_sets_and_refs ();
14775 reg_n_sets_max
= max_reg_num ();
14777 rebuild_jump_labels_after_combine
14778 = combine_instructions (get_insns (), max_reg_num ());
14780 /* Combining insns may have turned an indirect jump into a
14781 direct jump. Rebuild the JUMP_LABEL fields of jumping
14783 if (rebuild_jump_labels_after_combine
)
14785 if (dom_info_available_p (CDI_DOMINATORS
))
14786 free_dominance_info (CDI_DOMINATORS
);
14787 timevar_push (TV_JUMP
);
14788 rebuild_jump_labels (get_insns ());
14790 timevar_pop (TV_JUMP
);
14793 regstat_free_n_sets_and_refs ();
14799 const pass_data pass_data_combine
=
14801 RTL_PASS
, /* type */
14802 "combine", /* name */
14803 OPTGROUP_NONE
, /* optinfo_flags */
14804 TV_COMBINE
, /* tv_id */
14805 PROP_cfglayout
, /* properties_required */
14806 0, /* properties_provided */
14807 0, /* properties_destroyed */
14808 0, /* todo_flags_start */
14809 TODO_df_finish
, /* todo_flags_finish */
14812 class pass_combine
: public rtl_opt_pass
14815 pass_combine (gcc::context
*ctxt
)
14816 : rtl_opt_pass (pass_data_combine
, ctxt
)
14819 /* opt_pass methods: */
14820 virtual bool gate (function
*) { return (optimize
> 0); }
14821 virtual unsigned int execute (function
*)
14823 return rest_of_handle_combine ();
14826 }; // class pass_combine
14828 } // anon namespace
14831 make_pass_combine (gcc::context
*ctxt
)
14833 return new pass_combine (ctxt
);