| blob | 463737f9773eab8f851ddb71198757f35071c950 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 machine_mode,
422 machine_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1218 }
1219 }
1223 /* Now scan all the insns in forward order. */
1231 {
1237 label_tick++;
1247 {
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1267 into SUBREGs. */
1270 /* Try this insn with each insn it links back to. */
1276 {
1279 }
1281 /* Try each sequence of three linked insns ending with this one. */
1285 {
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1297 {
1300 }
1301 }
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1315 {
1326 }
1328 /* Do the same for an insn that explicitly references CC0. */
1335 {
1346 }
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1352 {
1364 }
1366 /* Try combining an insn with two different insns whose results it
1367 uses. */
1377 {
1380 }
1382 /* Try four-instruction combinations. */
1385 {
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1395 {
1399 /* I0 -> I1 -> I2 -> I3. */
1405 {
1408 }
1409 /* I0, I1 -> I2, I2 -> I3. */
1416 {
1419 }
1420 }
1423 {
1427 /* I0 -> I2; I1, I2 -> I3. */
1433 {
1436 }
1437 /* I0 -> I1; I1, I2 -> I3. */
1443 {
1446 }
1447 }
1448 }
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1452 {
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1467 {
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1481 last_combined_insn);
1484 {
1487 }
1490 }
1491 }
1496 retry:
1497 ;
1498 }
1499 }
1506 /* Clean up. */
1512 {
1515 {
1518 }
1520 }
1530 /* Make recognizer allow volatile MEMs again. */
1534 }
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1538 static void
1540 {
1546 }
1547 \f
1548 /* Set up any promoted values for incoming argument registers. */
1550 static void
1552 {
1553 tree arg;
1558 {
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1588 /* The mode of the register in which the argument is being passed. */
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1601 ;
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1623 }
1624 }
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1632 kludge. */
1634 static rtx
1636 {
1644 }
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1647 and SET. */
1649 static void
1651 rtx x)
1652 {
1662 {
1666 }
1668 /* Don't call nonzero_bits if it cannot change anything. */
1670 {
1675 }
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1679 {
1682 {
1686 }
1689 }
1690 }
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1697 be happening.
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1701 by any set of X. */
1703 static void
1705 {
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1715 {
1719 {
1723 }
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1742 {
1749 {
1753 }
1754 }
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1767 else
1768 {
1771 }
1772 }
1773 }
1774 \f
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1784 will return 1. */
1786 static int
1790 {
1795 rtx link;
1800 {
1802 {
1807 }
1812 }
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1826 note.
1828 Get the source and destination of INSN. If more than one, can't
1829 combine. */
1835 {
1837 {
1841 {
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1850 I3 and INSN.
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1860 {
1865 do
1866 {
1876 }
1878 }
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1904 }
1905 }
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1912 }
1913 else
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1935 /* Don't eliminate a store in the stack pointer. */
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1940 /* Can't merge an ASM_OPERANDS. */
1942 /* Can't merge a function call. */
1944 /* Don't eliminate a function call argument. */
1950 /* Don't substitute into an incremented register. */
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1957 || (!all_adjacent
1958 && ((succ2
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1971 || (! all_adjacent
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1985 /* DEST must either be a REG or CC0. */
1987 {
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1995 register. */
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2003 is going on).
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2006 inputs. */
2010 }
2018 {
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2033 }
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2039 {
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2045 /* We'll check insns between INSN and I3 below. */
2046 }
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2061 ? volatile_refs_p
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2100 {
2105 }
2107 /* If we get here, we have passed all the tests and the combination is
2108 to be allowed. */
2114 }
2115 \f
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2123 Consider:
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2154 static int
2157 {
2161 {
2166 rtx subdest;
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2189 INNER_DEST.
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2226 {
2231 }
2232 }
2235 {
2242 }
2245 }
2246 \f
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2250 static int
2252 {
2254 {
2270 }
2271 }
2272 \f
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2277 static int
2279 {
2280 rtx set;
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2315 }
2317 struct likely_spilled_retval_info
2318 {
2321 };
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2325 static void
2327 {
2344 else
2347 }
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2354 static int
2356 {
2358 rtx reg;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2378 /* Disregard parts of the return value that are set later. */
2387 /* Check if any of the (probably) live return value registers is
2388 likely spilled. */
2389 nregs --;
2390 do
2391 {
2397 }
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2404 static void
2406 {
2407 /* For notes, be conservative and simply remove them. */
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2428 }
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2432 static bool
2434 {
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2447 /* Or a pseudo that is only used once. */
2450 && !added_sets
2452 }
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2458 static bool
2460 {
2461 /* Check that reg is an integer mode register. */
2472 }
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2479 static void
2481 {
2489 {
2494 /* Remove barriers from the footer if there are any. */
2497 {
2500 else
2504 }
2507 }
2508 }
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2512 static bool
2514 {
2533 }
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2538 static bool
2540 {
2548 {
2557 }
2560 }
2562 /* Set up a set of registers used in an insn. Called through note_uses,
2563 arguments as described for that function. */
2565 static void
2567 {
2574 /* repeat is used to turn tail-recursion into iteration since GCC
2575 can't do it when there's no return value. */
2576 repeat:
2582 {
2588 }
2590 /* Recursively scan the operands of this expression. */
2593 {
2595 {
2596 /* If we are about to do the last recursive call
2597 needed at this level, change it into iteration.
2598 This function is called enough to be worth it. */
2600 {
2603 }
2606 }
2610 }
2611 }
2613 /* Try to combine the insns I0, I1 and I2 into I3.
2614 Here I0, I1 and I2 appear earlier than I3.
2615 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2616 I3.
2618 If we are combining more than two insns and the resulting insn is not
2619 recognized, try splitting it into two insns. If that happens, I2 and I3
2620 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2621 Otherwise, I0, I1 and I2 are pseudo-deleted.
2623 Return 0 if the combination does not work. Then nothing is changed.
2624 If we did the combination, return the insn at which combine should
2625 resume scanning.
2627 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2628 new direct jump instruction.
2630 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2631 been I3 passed to an earlier try_combine within the same basic
2632 block. */
2637 {
2638 /* New patterns for I3 and I2, respectively. */
2642 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2643 dead. */
2645 /* Total number of SETs to put into I3. */
2647 /* Nonzero if I2's or I1's body now appears in I3. */
2649 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2651 /* Contains I3 if the destination of I3 is used in its source, which means
2652 that the old life of I3 is being killed. If that usage is placed into
2653 I2 and not in I3, a REG_DEAD note must be made. */
2655 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2657 /* Copy of SET_SRC of I1 and I0, if needed. */
2659 /* Set if I2DEST was reused as a scratch register. */
2661 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2663 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2668 /* Notes that must be added to REG_NOTES in I3 and I2. */
2670 /* Notes that we substituted I3 into I2 instead of the normal case. */
2672 /* Notes that I1, I2 or I3 is a MULT operation. */
2679 rtx temp_expr;
2682 rtx new_other_notes;
2685 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2686 never be). */
2690 /* Only try four-insn combinations when there's high likelihood of
2691 success. Look for simple insns, such as loads of constants or
2692 binary operations involving a constant. */
2694 {
2704 {
2707 rtx src;
2712 {
2715 }
2717 ngood++;
2720 nshift++;
2721 }
2723 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2724 are likely manipulating its value. Ideally we'll be able to combine
2725 all four insns into a bitfield insertion of some kind.
2727 Note the source in I0 might be inside a sign/zero extension and the
2728 memory modes in I0 and I3 might be different. So extract the address
2729 from the destination of I3 and search for it in the source of I0.
2731 In the event that there's a match but the source/dest do not actually
2732 refer to the same memory, the worst that happens is we try some
2733 combinations that we wouldn't have otherwise. */
2735 /* Ensure the source of SET0 is a MEM, possibly buried inside
2736 an extension. */
2742 /* Ensure the destination of SET3 is a MEM. */
2744 /* Would it be better to extract the base address for the MEM
2745 in SET3 and look for that? I don't have cases where it matters
2746 but I could envision such cases. */
2752 }
2754 /* Exit early if one of the insns involved can't be used for
2755 combinations. */
2766 combine_attempts++;
2769 /* Reset the hard register usage information. */
2773 {
2780 else
2783 }
2785 /* If multiple insns feed into one of I2 or I3, they can be in any
2786 order. To simplify the code below, reorder them in sequence. */
2796 /* For combinations that may result in two insns, we have to gather
2797 some extra information about registers used, so that we can
2798 update all relevant LOG_LINKS later. */
2801 {
2814 }
2816 /* First check for one important special case that the code below will
2817 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2818 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2819 we may be able to replace that destination with the destination of I3.
2820 This occurs in the common code where we compute both a quotient and
2821 remainder into a structure, in which case we want to do the computation
2822 directly into the structure to avoid register-register copies.
2824 Note that this case handles both multiple sets in I2 and also cases
2825 where I2 has a number of CLOBBERs inside the PARALLEL.
2827 We make very conservative checks below and only try to handle the
2828 most common cases of this. For example, we only handle the case
2829 where I2 and I3 are adjacent to avoid making difficult register
2830 usage tests. */
2838 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2839 below would need to check what is inside (and reg_overlap_mentioned_p
2840 doesn't support those codes anyway). Don't allow those destinations;
2841 the resulting insn isn't likely to be recognized anyway. */
2847 {
2850 /* Make sure that the destination of I3,
2851 which we are going to substitute into one output of I2,
2852 is not used within another output of I2. We must avoid making this:
2853 (parallel [(set (mem (reg 69)) ...)
2854 (set (reg 69) ...)])
2855 which is not well-defined as to order of actions.
2856 (Besides, reload can't handle output reloads for this.)
2858 The problem can also happen if the dest of I3 is a memory ref,
2859 if another dest in I2 is an indirect memory ref.
2861 Neither can this PARALLEL be an asm. We do not allow combining
2862 that usually (see can_combine_p), so do not here either. */
2865 {
2874 }
2880 {
2881 combine_merges++;
2891 /* Replace the dest in I2 with our dest and make the resulting
2892 insn the new pattern for I3. Then skip to where we validate
2893 the pattern. Everything was set up above. */
2898 }
2899 }
2901 /* If I2 is setting a pseudo to a constant and I3 is setting some
2902 sub-part of it to another constant, merge them by making a new
2903 constant. */
2910 {
2916 {
2919 {
2925 }
2926 }
2927 else
2928 {
2933 }
2936 {
2937 /* If this is the low part, we're done. */
2939 ;
2940 /* Handle the case where inner is twice the size of outer. */
2944 /* Otherwise give up for now. */
2945 else
2947 }
2950 {
2954 wide_int o
2959 combine_merges++;
2966 /* Replace the source in I2 with the new constant and make the
2967 resulting insn the new pattern for I3. Then skip to where we
2968 validate the pattern. Everything was set up above. */
2974 /* The dest of I3 has been replaced with the dest of I2. */
2977 }
2978 }
2980 /* If we have no I1 and I2 looks like:
2981 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2982 (set Y OP)])
2983 make up a dummy I1 that is
2984 (set Y OP)
2985 and change I2 to be
2986 (set (reg:CC X) (compare:CC Y (const_int 0)))
2988 (We can ignore any trailing CLOBBERs.)
2990 This undoes a previous combination and allows us to match a branch-and-
2991 decrement insn. */
3003 {
3004 /* We make I1 with the same INSN_UID as I2. This gives it
3005 the same DF_INSN_LUID for value tracking. Our fake I1 will
3006 never appear in the insn stream so giving it the same INSN_UID
3007 as I2 will not cause a problem. */
3020 }
3022 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3023 make those two SETs separate I1 and I2 insns, and make an I0 that is
3024 the original I1. */
3030 {
3031 /* If there is no I1, there is no I0 either. */
3034 /* We make I1 with the same INSN_UID as I2. This gives it
3035 the same DF_INSN_LUID for value tracking. Our fake I1 will
3036 never appear in the insn stream so giving it the same INSN_UID
3037 as I2 will not cause a problem. */
3045 }
3047 /* Verify that I2 and I1 are valid for combining. */
3053 {
3056 }
3058 /* Record whether I2DEST is used in I2SRC and similarly for the other
3059 cases. Knowing this will help in register status updating below. */
3070 /* For the earlier insns, determine which of the subsequent ones they
3071 feed. */
3078 /* Ensure that I3's pattern can be the destination of combines. */
3084 {
3087 }
3089 /* See if any of the insns is a MULT operation. Unless one is, we will
3090 reject a combination that is, since it must be slower. Be conservative
3091 here. */
3099 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3100 We used to do this EXCEPT in one case: I3 has a post-inc in an
3101 output operand. However, that exception can give rise to insns like
3102 mov r3,(r3)+
3103 which is a famous insn on the PDP-11 where the value of r3 used as the
3104 source was model-dependent. Avoid this sort of thing. */
3106 #if 0
3112 /* It's not the exception. */
3113 #endif
3115 {
3116 rtx link;
3122 {
3125 }
3126 }
3128 /* See if the SETs in I1 or I2 need to be kept around in the merged
3129 instruction: whenever the value set there is still needed past I3.
3130 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3132 For the SET in I1, we have two cases: if I1 and I2 independently feed
3133 into I3, the set in I1 needs to be kept around unless I1DEST dies
3134 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3135 in I1 needs to be kept around unless I1DEST dies or is set in either
3136 I2 or I3. The same considerations apply to I0. */
3143 else
3151 else
3154 /* We are about to copy insns for the case where they need to be kept
3155 around. Check that they can be copied in the merged instruction. */
3161 {
3164 }
3166 /* If the set in I2 needs to be kept around, we must make a copy of
3167 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3168 PATTERN (I2), we are only substituting for the original I1DEST, not into
3169 an already-substituted copy. This also prevents making self-referential
3170 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3171 I2DEST. */
3174 {
3177 else
3179 }
3182 {
3185 else
3187 }
3190 {
3193 else
3195 }
3197 combine_merges++;
3199 /* Substitute in the latest insn for the regs set by the earlier ones. */
3205 /* Many machines that don't use CC0 have insns that can both perform an
3206 arithmetic operation and set the condition code. These operations will
3207 be represented as a PARALLEL with the first element of the vector
3208 being a COMPARE of an arithmetic operation with the constant zero.
3209 The second element of the vector will set some pseudo to the result
3210 of the same arithmetic operation. If we simplify the COMPARE, we won't
3211 match such a pattern and so will generate an extra insn. Here we test
3212 for this case, where both the comparison and the operation result are
3213 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3214 I2SRC. Later we will make the PARALLEL that contains I2. */
3220 {
3221 rtx newpat_dest;
3235 {
3240 }
3242 /* Do the rest only if op1 is const0_rtx, which may be the
3243 result of simplification. */
3245 {
3246 /* If a single use of the CC is found, prepare to modify it
3247 when SELECT_CC_MODE returns a new CC-class mode, or when
3248 the above simplify_compare_const() returned a new comparison
3249 operator. undobuf.other_insn is assigned the CC use insn
3250 when modifying it. */
3252 {
3253 #ifdef SELECT_CC_MODE
3254 machine_mode new_mode
3259 {
3264 else
3265 {
3268 }
3269 }
3270 #endif
3271 /* Cases for modifying the CC-using comparison. */
3273 /* ??? Do we need to verify the zero rtx? */
3275 {
3276 /* Replace cc_use_loc with entire new RTX. */
3281 }
3283 {
3284 /* Just replace the CC reg with a new mode. */
3287 }
3288 }
3290 /* Now we modify the current newpat:
3291 First, SET_DEST(newpat) is updated if the CC mode has been
3292 altered. For targets without SELECT_CC_MODE, this should be
3293 optimized away. */
3296 /* This is always done to propagate i2src into newpat. */
3299 /* Create new version of i2pat if needed; the below PARALLEL
3300 creation needs this to work correctly. */
3304 }
3305 }
3308 {
3309 /* It is possible that the source of I2 or I1 may be performing
3310 an unneeded operation, such as a ZERO_EXTEND of something
3311 that is known to have the high part zero. Handle that case
3312 by letting subst look at the inner insns.
3314 Another way to do this would be to have a function that tries
3315 to simplify a single insn instead of merging two or more
3316 insns. We don't do this because of the potential of infinite
3317 loops and because of the potential extra memory required.
3318 However, doing it the way we are is a bit of a kludge and
3319 doesn't catch all cases.
3321 But only do this if -fexpensive-optimizations since it slows
3322 things down and doesn't usually win.
3324 This is not done in the COMPARE case above because the
3325 unmodified I2PAT is used in the PARALLEL and so a pattern
3326 with a modified I2SRC would not match. */
3329 {
3330 /* Pass pc_rtx so no substitutions are done, just
3331 simplifications. */
3333 {
3336 }
3340 }
3345 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3346 copy of I2SRC each time we substitute it, in order to avoid creating
3347 self-referential RTL when we will be substituting I1SRC for I1DEST
3348 later. Likewise if I0 feeds into I2, either directly or indirectly
3349 through I1, and I0DEST is in I0SRC. */
3356 /* Record whether I2's body now appears within I3's body. */
3358 }
3360 /* If we already got a failure, don't try to do more. Otherwise, try to
3361 substitute I1 if we have it. */
3364 {
3365 /* Check that an autoincrement side-effect on I1 has not been lost.
3366 This happens if I1DEST is mentioned in I2 and dies there, and
3367 has disappeared from the new pattern. */
3369 && i1_feeds_i2_n
3372 /* Before we can do this substitution, we must redo the test done
3373 above (see detailed comments there) that ensures I1DEST isn't
3374 mentioned in any SETs in NEWPAT that are field assignments. */
3377 {
3380 }
3385 /* If the following substitution will modify I1SRC, make a copy of it
3386 for the case where it is substituted for I1DEST in I2PAT later. */
3390 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3391 copy of I1SRC each time we substitute it, in order to avoid creating
3392 self-referential RTL when we will be substituting I0SRC for I0DEST
3393 later. */
3398 /* Record whether I1's body now appears within I3's body. */
3400 }
3402 /* Likewise for I0 if we have it. */
3405 {
3412 {
3415 }
3417 /* If the following substitution will modify I0SRC, make a copy of it
3418 for the case where it is substituted for I0DEST in I1PAT later. */
3421 /* And a copy for I0DEST in I2PAT substitution. */
3430 }
3432 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3433 to count all the ways that I2SRC and I1SRC can be used. */
3444 /* Fail if we tried to make a new register. */
3446 /* Fail if we couldn't do something and have a CLOBBER. */
3448 /* Fail if this new pattern is a MULT and we didn't have one before
3449 at the outer level. */
3452 {
3455 }
3457 /* If the actions of the earlier insns must be kept
3458 in addition to substituting them into the latest one,
3459 we must make a new PARALLEL for the latest insn
3460 to hold additional the SETs. */
3463 {
3465 combine_extras++;
3468 {
3474 }
3475 else
3476 {
3481 }
3487 {
3493 }
3495 {
3504 }
3505 }
3507 validate_replacement:
3509 /* Note which hard regs this insn has as inputs. */
3512 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3513 consider splitting this pattern, we might need these clobbers. */
3516 {
3522 }
3524 /* We have recognized nothing yet. */
3527 /* See if this is a PARALLEL of two SETs where one SET's destination is
3528 a register that is unused and this isn't marked as an instruction that
3529 might trap in an EH region. In that case, we just need the other SET.
3530 We prefer this over the PARALLEL.
3532 This can occur when simplifying a divmod insn. We *must* test for this
3533 case here because the code below that splits two independent SETs doesn't
3534 handle this case correctly when it updates the register status.
3536 It's pointless doing this if we originally had two sets, one from
3537 i3, and one from i2. Combining then splitting the parallel results
3538 in the original i2 again plus an invalid insn (which we delete).
3539 The net effect is only to move instructions around, which makes
3540 debug info less accurate. */
3545 {
3556 {
3559 }
3568 {
3574 }
3578 }
3580 /* Is the result of combination a valid instruction? */
3584 /* If we were combining three insns and the result is a simple SET
3585 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3586 insns. There are two ways to do this. It can be split using a
3587 machine-specific method (like when you have an addition of a large
3588 constant) or by combine in the function find_split_point. */
3592 {
3596 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3597 use I2DEST as a scratch register will help. In the latter case,
3598 convert I2DEST to the mode of the source of NEWPAT if we can. */
3602 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3603 inputs of NEWPAT. */
3605 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3606 possible to try that as a scratch reg. This would require adding
3607 more code to make it work though. */
3610 {
3613 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3614 (temporarily, until we are committed to this instruction
3615 combination) does not work: for example, any call to nonzero_bits
3616 on the register (from a splitter in the MD file, for example)
3617 will get the old information, which is invalid.
3619 Since nowadays we can create registers during combine just fine,
3620 we should just create a new one here, not reuse i2dest. */
3622 /* First try to split using the original register as a
3623 scratch register. */
3627 i2dest)));
3630 /* If that didn't work, try changing the mode of I2DEST if
3631 we can. */
3636 {
3638 rtx ni2dest;
3642 else
3643 {
3646 }
3648 parallel = (gen_rtx_PARALLEL
3652 ni2dest))));
3657 {
3665 }
3666 }
3669 }
3671 /* If recog_for_combine has discarded clobbers, try to use them
3672 again for the split. */
3674 {
3677 }
3680 {
3685 }
3689 {
3699 /* If I2 or I3 has multiple SETs, we won't know how to track
3700 register status, so don't use these insns. If I2's destination
3701 is used between I2 and I3, we also can't use these insns. */
3711 /* It is possible that both insns now set the destination of I3.
3712 If so, we must show an extra use of it. */
3715 {
3734 }
3735 }
3737 /* If we can split it and use I2DEST, go ahead and see if that
3738 helps things be recognized. Verify that none of the registers
3739 are set between I2 and I3. */
3743 /* We need I2DEST in the proper mode. If it is a hard register
3744 or the only use of a pseudo, we can change its mode.
3745 Make sure we don't change a hard register to have a mode that
3746 isn't valid for it, or change the number of registers. */
3753 /* We can't overwrite I2DEST if its value is still used by
3754 NEWPAT. */
3756 {
3765 /* *SPLIT may be part of I2SRC, so make sure we have the
3766 original expression around for later debug processing.
3767 We should not need I2SRC any more in other cases. */
3770 else
3773 /* Get NEWDEST as a register in the proper mode. We have already
3774 validated that we can do this. */
3776 {
3779 else
3780 {
3783 }
3784 }
3786 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3787 an ASHIFT. This can occur if it was inside a PLUS and hence
3788 appeared to be a memory address. This is a kludge. */
3793 {
3796 /* Update split_code because we may not have a multiply
3797 anymore. */
3799 }
3801 /* Similarly for (plus (mult FOO (const_int pow2))). */
3807 {
3811 /* Update split_code because we may not have a multiply
3812 anymore. */
3814 }
3816 #ifdef INSN_SCHEDULING
3817 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3818 be written as a ZERO_EXTEND. */
3820 {
3821 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3822 what it really is. */
3827 else
3830 }
3831 #endif
3833 /* Attempt to split binary operators using arithmetic identities. */
3837 {
3844 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3846 {
3851 }
3852 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3859 {
3865 /* Split both "((X op Y) op X) op Y" and
3866 "((X op Y) op Y) op X" as "T op T" where T is
3867 "X op Y". */
3870 {
3875 }
3876 /* Split "((X op X) op Y) op Y)" as "T op T" where
3877 T is "X op Y". */
3879 {
3885 }
3886 }
3887 }
3890 {
3893 }
3897 /* recog_for_combine might have added CLOBBERs to newi2pat.
3898 Make sure NEWPAT does not depend on the clobbered regs. */
3902 {
3905 {
3908 }
3909 }
3911 /* If the split point was a MULT and we didn't have one before,
3912 don't use one now. */
3915 }
3916 }
3918 /* Check for a case where we loaded from memory in a narrow mode and
3919 then sign extended it, but we need both registers. In that case,
3920 we have a PARALLEL with both loads from the same memory location.
3921 We can split this into a load from memory followed by a register-register
3922 copy. This saves at least one insn, more if register allocation can
3923 eliminate the copy.
3925 We cannot do this if the destination of the first assignment is a
3926 condition code register or cc0. We eliminate this case by making sure
3927 the SET_DEST and SET_SRC have the same mode.
3929 We cannot do this if the destination of the second assignment is
3930 a register that we have already assumed is zero-extended. Similarly
3931 for a SUBREG of such a register. */
3966 {
3967 rtx ni2dest;
3981 }
3983 /* Similarly, check for a case where we have a PARALLEL of two independent
3984 SETs but we started with three insns. In this case, we can do the sets
3985 as two separate insns. This case occurs when some SET allows two
3986 other insns to combine, but the destination of that SET is still live.
3988 Also do this if we started with two insns and (at least) one of the
3989 resulting sets is a noop; this noop will be deleted later. */
4008 {
4012 /* Normally, it doesn't matter which of the two is done first,
4013 but the one that references cc0 can't be the second, and
4014 one which uses any regs/memory set in between i2 and i3 can't
4015 be first. The PARALLEL might also have been pre-existing in i3,
4016 so we need to make sure that we won't wrongly hoist a SET to i2
4017 that would conflict with a death note present in there. */
4025 /* If I3 is a jump, ensure that set0 is a jump so that
4026 we do not create invalid RTL. */
4028 )
4029 {
4032 }
4040 /* If I3 is a jump, ensure that set1 is a jump so that
4041 we do not create invalid RTL. */
4043 )
4044 {
4047 }
4048 else
4049 {
4052 }
4057 {
4058 /* recog_for_combine might have added CLOBBERs to newi2pat.
4059 Make sure NEWPAT does not depend on the clobbered regs. */
4061 {
4064 {
4067 {
4070 }
4071 }
4072 }
4075 }
4076 }
4078 /* If it still isn't recognized, fail and change things back the way they
4079 were. */
4081 /* Is the result a reasonable ASM_OPERANDS? */
4083 {
4086 }
4088 /* If we had to change another insn, make sure it is valid also. */
4090 {
4098 {
4101 }
4102 }
4104 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4105 they are adjacent to each other or not. */
4107 {
4111 {
4114 }
4115 }
4117 /* Only allow this combination if insn_rtx_costs reports that the
4118 replacement instructions are cheaper than the originals. */
4120 {
4123 }
4125 auto_bitmap new_regs_in_i2;
4127 {
4128 /* We need to discover situations where we introduce a use of a
4129 register into I2, where none of the existing LOG_LINKS contain
4130 a reference to it. This can happen if previously I3 referenced
4131 the reg, and there is an additional use between I2 and I3. We
4132 must remove the LOG_LINKS entry from that additional use and
4133 distribute it along with our own ones. */
4138 /* Here, we first look for situations where a hard register use
4139 moved, and just give up. This should happen approximately
4140 never, and it's not worth it to deal with possibilities like
4141 multi-word registers. Later, when fixing up LOG_LINKS, we
4142 deal with the case where a pseudo use moved. */
4146 {
4149 }
4150 }
4153 {
4158 {
4163 /* Temporarily revert mode back. */
4167 {
4168 /* If we used i2dest as a scratch register with a
4169 different mode, substitute it for the original
4170 i2src while its original mode is temporarily
4171 restored, and then clear i2scratch so that we don't
4172 do it again later. */
4174 this_basic_block);
4176 /* Put back the new mode. */
4178 }
4179 else
4180 {
4185 {
4188 }
4189 else
4190 {
4197 }
4199 /* We're dealing with a reg that changed mode but not
4200 meaning, so we want to turn it into a subreg for
4201 the new mode. However, because of REG sharing and
4202 because its mode had already changed, we have to do
4203 it in two steps. First, replace any debug uses of
4204 reg, with its original mode temporarily restored,
4205 with this copy we have created; then, replace the
4206 copy with the SUBREG of the original shared reg,
4207 once again changed to the new mode. */
4209 this_basic_block);
4213 this_basic_block);
4214 }
4215 }
4216 }
4218 /* If we will be able to accept this, we have made a
4219 change to the destination of I3. This requires us to
4220 do a few adjustments. */
4223 {
4226 }
4228 /* We now know that we can do this combination. Merge the insns and
4229 update the status of registers and LOG_LINKS. */
4232 {
4237 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4238 ensure that they are still valid. Then add any non-duplicate
4239 notes added by recog_for_combine. */
4241 {
4250 /* Simply drop equal note since it may be no longer valid
4251 for other_insn. It may be possible to record that CC
4252 register is changed and only discard those notes, but
4253 in practice it's unnecessary complication and doesn't
4254 give any meaningful improvement.
4256 See PR78559. */
4260 }
4264 NULL_RTX);
4265 }
4268 {
4271 rtx ni2dest;
4273 /* I3 now uses what used to be its destination and which is now
4274 I2's destination. This requires us to do a few adjustments. */
4278 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4279 so we still will.
4281 However, some later insn might be using I2's dest and have
4282 a LOG_LINK pointing at I3. We must remove this link.
4283 The simplest way to remove the link is to point it at I1,
4284 which we know will be a NOTE. */
4286 /* newi2pat is usually a SET here; however, recog_for_combine might
4287 have added some clobbers. */
4290 else
4297 {
4300 {
4306 }
4307 }
4308 }
4310 {
4315 /* Compute which registers we expect to eliminate. newi2pat may be setting
4316 either i3dest or i2dest, so we must check it. */
4319 || !i2dest_killed
4321 /* For i1, we need to compute both local elimination and global
4322 elimination information with respect to newi2pat because i1dest
4323 may be the same as i3dest, in which case newi2pat may be setting
4324 i1dest. Global information is used when distributing REG_DEAD
4325 note for i2 and i3, in which case it does matter if newi2pat sets
4326 i1dest or not.
4328 Local information is used when distributing REG_DEAD note for i1,
4329 in which case it doesn't matter if newi2pat sets i1dest or not.
4330 See PR62151, if we have four insns combination:
4331 i0: r0 <- i0src
4332 i1: r1 <- i1src (using r0)
4333 REG_DEAD (r0)
4334 i2: r0 <- i2src (using r1)
4335 i3: r3 <- i3src (using r0)
4336 ix: using r0
4337 From i1's point of view, r0 is eliminated, no matter if it is set
4338 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4339 should be discarded.
4341 Note local information only affects cases in forms like "I1->I2->I3",
4342 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4343 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4344 i0dest anyway. */
4346 || !i1dest_killed
4351 /* Same case as i1. */
4358 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4359 clear them. */
4367 /* Ensure that we do not have something that should not be shared but
4368 occurs multiple times in the new insns. Check this by first
4369 resetting all the `used' flags and then copying anything is shared. */
4393 {
4396 {
4398 {
4399 /* I2SRC must still be meaningful at this point. Some
4400 splitting operations can invalidate I2SRC, but those
4401 operations do not apply to calls. */
4405 }
4412 }
4413 }
4418 /* We had one special case above where I2 had more than one set and
4419 we replaced a destination of one of those sets with the destination
4420 of I3. In that case, we have to update LOG_LINKS of insns later
4421 in this basic block. Note that this (expensive) case is rare.
4423 Also, in this case, we must pretend that all REG_NOTEs for I2
4424 actually came from I3, so that REG_UNUSED notes from I2 will be
4425 properly handled. */
4428 {
4437 temp_insn
4447 {
4452 }
4453 else
4456 }
4464 {
4467 this_basic_block);
4470 }
4471 else
4472 {
4475 this_basic_block);
4477 }
4480 {
4485 this_basic_block);
4487 }
4490 {
4495 this_basic_block);
4497 }
4499 /* Get death notes for everything that is now used in either I3 or
4500 I2 and used to die in a previous insn. If we built two new
4501 patterns, move from I1 to I2 then I2 to I3 so that we get the
4502 proper movement on registers that I2 modifies. */
4508 else
4514 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4531 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4532 know these are REG_UNUSED and want them to go to the desired insn,
4533 so we always pass it as i3. */
4537 NULL_RTX);
4541 NULL_RTX);
4543 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4544 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4545 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4546 in that case, it might delete I2. Similarly for I2 and I1.
4547 Show an additional death due to the REG_DEAD note we make here. If
4548 we discard it in distribute_notes, we will decrement it again. */
4551 {
4556 else
4559 }
4562 {
4567 else
4570 }
4573 {
4578 else
4581 }
4584 {
4589 else
4592 }
4595 {
4596 bitmap_iterator iter;
4599 /* See comments above where we calculate the bitmap. */
4602 {
4609 {
4618 {
4621 {
4626 }
4627 }
4629 }
4630 }
4631 }
4639 {
4644 /* The insn that used to set this register doesn't exist, and
4645 this life of the register may not exist either. See if one of
4646 I3's links points to an insn that sets I2DEST. If it does,
4647 that is now the last known value for I2DEST. If we don't update
4648 this and I2 set the register to a value that depended on its old
4649 contents, we will get confused. If this insn is used, thing
4650 will be set correctly in combine_instructions. */
4658 /* If the reg formerly set in I2 died only once and that was in I3,
4659 zero its use count so it won't make `reload' do any work. */
4662 && ! i2dest_in_i2src
4665 }
4668 {
4681 && ! i1dest_in_i1src
4684 }
4687 {
4700 && ! i0dest_in_i0src
4703 }
4705 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4706 been made to this insn. The order is important, because newi2pat
4707 can affect nonzero_bits of newpat. */
4711 }
4714 {
4716 {
4719 }
4721 }
4724 {
4726 {
4729 }
4731 }
4734 {
4736 {
4739 }
4741 }
4744 {
4746 {
4749 }
4751 }
4754 {
4756 {
4759 }
4761 }
4763 /* Set new_direct_jump_p if a new return or simple jump instruction
4764 has been created. Adjust the CFG accordingly. */
4766 {
4770 }
4775 {
4778 }
4782 {
4788 }
4793 {
4799 }
4801 /* A noop might also need cleaning up of CFG, if it comes from the
4802 simplification of a jump. */
4807 {
4810 }
4817 {
4820 }
4822 combine_successes++;
4829 else
4831 }
4832 \f
4833 /* Get a marker for undoing to the current state. */
4837 {
4839 }
4841 /* Undo the modifications up to the marker. */
4843 static void
4845 {
4849 {
4854 {
4869 }
4873 }
4876 }
4878 /* Undo all the modifications recorded in undobuf. */
4880 static void
4882 {
4884 }
4886 /* We've committed to accepting the changes we made. Move all
4887 of the undos to the free list. */
4889 static void
4891 {
4895 {
4899 }
4901 }
4902 \f
4903 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4904 where we have an arithmetic expression and return that point. LOC will
4905 be inside INSN.
4907 try_combine will call this function to see if an insn can be split into
4908 two insns. */
4912 {
4921 /* First special-case some codes. */
4923 {
4925 #ifdef INSN_SCHEDULING
4926 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4927 point. */
4930 #endif
4934 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4935 using LO_SUM and HIGH. */
4938 {
4946 }
4948 /* If we have a PLUS whose second operand is a constant and the
4949 address is not valid, perhaps will can split it up using
4950 the machine-specific way to split large constants. We use
4951 the first pseudo-reg (one of the virtual regs) as a placeholder;
4952 it will not remain in the result. */
4957 {
4960 subst_insn);
4962 /* This should have produced two insns, each of which sets our
4963 placeholder. If the source of the second is a valid address,
4964 we can make put both sources together and make a split point
4965 in the middle. */
4978 && memory_address_addr_space_p
4981 {
4985 /* Replace the placeholder in SRC2 with SRC1. If we can
4986 find where in SRC2 it was placed, that can become our
4987 split point and we can replace this address with SRC2.
4988 Just try two obvious places. */
4999 {
5002 }
5003 }
5005 /* If that didn't work, perhaps the first operand is complex and
5006 needs to be computed separately, so make a split point there.
5007 This will occur on machines that just support REG + CONST
5008 and have a constant moved through some previous computation. */
5014 }
5016 /* If we have a PLUS whose first operand is complex, try computing it
5017 separately by making a split there. */
5028 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5029 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5030 we need to put the operand into a register. So split at that
5031 point. */
5041 /* See if we can split SET_SRC as it stands. */
5046 /* See if we can split SET_DEST as it stands. */
5051 /* See if this is a bitfield assignment with everything constant. If
5052 so, this is an IOR of an AND, so split it into that. */
5062 {
5068 unsigned HOST_WIDE_INT mask
5070 rtx or_mask;
5079 else
5080 {
5086 or_mask));
5087 }
5094 }
5096 /* Otherwise, see if this is an operation that we can split into two.
5097 If so, try to split that. */
5101 {
5103 /* If we are AND'ing with a large constant that is only a single
5104 bit and the result is only being used in a context where we
5105 need to know if it is zero or nonzero, replace it with a bit
5106 extraction. This will avoid the large constant, which might
5107 have taken more than one insn to make. If the constant were
5108 not a valid argument to the AND but took only one insn to make,
5109 this is no worse, but if it took more than one insn, it will
5110 be better. */
5120 {
5125 {
5128 }
5129 }
5133 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5134 is known to be on, this can be converted into a NEG of a shift. */
5140 {
5152 }
5158 /* We can't optimize if either mode is a partial integer
5159 mode as we don't know how many bits are significant
5160 in those modes. */
5174 {
5182 }
5187 }
5191 {
5194 /* For unsigned, we have a choice of a shift followed by an
5195 AND or two shifts. Use two shifts for field sizes where the
5196 constant might be too large. We assume here that we can
5197 always at least get 8-bit constants in an AND insn, which is
5198 true for every current RISC. */
5201 {
5202 unsigned HOST_WIDE_INT mask
5206 gen_rtx_LSHIFTRT
5214 }
5215 else
5216 {
5218 gen_rtx_fmt_ee
5229 }
5230 }
5232 /* See if this is a simple operation with a constant as the second
5233 operand. It might be that this constant is out of range and hence
5234 could be used as a split point. */
5242 /* Finally, see if this is a simple operation with its first operand
5243 not in a register. The operation might require this operand in a
5244 register, so return it as a split point. We can always do this
5245 because if the first operand were another operation, we would have
5246 already found it as a split point. */
5255 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5256 it is better to write this as (not (ior A B)) so we can split it.
5257 Similarly for IOR. */
5259 {
5267 }
5269 /* Many RISC machines have a large set of logical insns. If the
5270 second operand is a NOT, put it first so we will try to split the
5271 other operand first. */
5273 {
5277 }
5282 /* Canonicalization can produce (minus A (mult B C)), where C is a
5283 constant. It may be better to try splitting (plus (mult B -C) A)
5284 instead if this isn't a multiply by a power of two. */
5288 {
5296 mode)),
5299 }
5301 /* Split at a multiply-accumulate instruction. However if this is
5302 the SET_SRC, we likely do not have such an instruction and it's
5303 worthless to try this split. */
5312 }
5314 /* Otherwise, select our actions depending on our rtx class. */
5316 {
5322 /* fall through */
5330 /* fall through */
5332 /* Some machines have (and (shift ...) ...) insns. If X is not
5333 an AND, but XEXP (X, 0) is, use it as our split point. */
5343 /* Otherwise, we don't have a split point. */
5345 }
5346 }
5347 \f
5348 /* Throughout X, replace FROM with TO, and return the result.
5349 The result is TO if X is FROM;
5350 otherwise the result is X, but its contents may have been modified.
5351 If they were modified, a record was made in undobuf so that
5352 undo_all will (among other things) return X to its original state.
5354 If the number of changes necessary is too much to record to undo,
5355 the excess changes are not made, so the result is invalid.
5356 The changes already made can still be undone.
5357 undobuf.num_undo is incremented for such changes, so by testing that
5358 the caller can tell whether the result is valid.
5360 `n_occurrences' is incremented each time FROM is replaced.
5362 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5364 IN_COND is nonzero if we are at the top level of a condition.
5366 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5367 by copying if `n_occurrences' is nonzero. */
5369 static rtx
5371 {
5376 rtx new_rtx;
5378 /* Two expressions are equal if they are identical copies of a shared
5379 RTX or if they are both registers with the same register number
5380 and mode. */
5382 #define COMBINE_RTX_EQUAL_P(X,Y) \
5383 ((X) == (Y) \
5384 || (REG_P (X) && REG_P (Y) \
5385 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5387 /* Do not substitute into clobbers of regs -- this will never result in
5388 valid RTL. */
5393 {
5394 n_occurrences++;
5396 }
5398 /* If X and FROM are the same register but different modes, they
5399 will not have been seen as equal above. However, the log links code
5400 will make a LOG_LINKS entry for that case. If we do nothing, we
5401 will try to rerecognize our original insn and, when it succeeds,
5402 we will delete the feeding insn, which is incorrect.
5404 So force this insn not to match in this (rare) case. */
5409 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5410 of which may contain things that can be combined. */
5414 /* It is possible to have a subexpression appear twice in the insn.
5415 Suppose that FROM is a register that appears within TO.
5416 Then, after that subexpression has been scanned once by `subst',
5417 the second time it is scanned, TO may be found. If we were
5418 to scan TO here, we would find FROM within it and create a
5419 self-referent rtl structure which is completely wrong. */
5423 /* Parallel asm_operands need special attention because all of the
5424 inputs are shared across the arms. Furthermore, unsharing the
5425 rtl results in recognition failures. Failure to handle this case
5426 specially can result in circular rtl.
5428 Solve this by doing a normal pass across the first entry of the
5429 parallel, and only processing the SET_DESTs of the subsequent
5430 entries. Ug. */
5435 {
5438 /* If this substitution failed, this whole thing fails. */
5446 {
5452 {
5455 /* If this substitution failed, this whole thing fails. */
5461 }
5462 }
5463 }
5464 else
5465 {
5469 /* We don't need to process a SET_DEST that is a register, CC0,
5470 or PC, so set up to skip this common case. All other cases
5471 where we want to suppress replacing something inside a
5472 SET_SRC are handled via the IN_DEST operand. */
5479 /* Trying to simplify the operands of a widening MULT is not likely
5480 to create RTL matching a machine insn. */
5492 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5493 constant. */
5498 {
5500 {
5503 {
5505 {
5508 n_occurrences++;
5509 }
5510 else
5511 {
5513 unique_copy);
5515 /* If this substitution failed, this whole thing
5516 fails. */
5520 }
5523 }
5524 }
5526 {
5527 /* If this is a register being set, ignore it. */
5534 ;
5537 {
5538 /* In general, don't install a subreg involving two
5539 modes not tieable. It can worsen register
5540 allocation, and can even make invalid reload
5541 insns, since the reg inside may need to be copied
5542 from in the outside mode, and that may be invalid
5543 if it is an fp reg copied in integer mode.
5545 We allow two exceptions to this: It is valid if
5546 it is inside another SUBREG and the mode of that
5547 SUBREG and the mode of the inside of TO is
5548 tieable and it is valid if X is a SET that copies
5549 FROM to CC0. */
5557 && (!HAVE_cc0
5572 n_occurrences++;
5573 }
5574 else
5575 /* If we are in a SET_DEST, suppress most cases unless we
5576 have gone inside a MEM, in which case we want to
5577 simplify the address. We assume here that things that
5578 are actually part of the destination have their inner
5579 parts in the first expression. This is true for SUBREG,
5580 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5581 things aside from REG and MEM that should appear in a
5582 SET_DEST. */
5584 (((in_dest
5590 unique_copy);
5592 /* If we found that we will have to reject this combination,
5593 indicate that by returning the CLOBBER ourselves, rather than
5594 an expression containing it. This will speed things up as
5595 well as prevent accidents where two CLOBBERs are considered
5596 to be equal, thus producing an incorrect simplification. */
5602 {
5610 }
5613 {
5617 }
5618 else
5620 }
5621 }
5622 }
5624 /* Check if we are loading something from the constant pool via float
5625 extension; in this case we would undo compress_float_constant
5626 optimization and degenerate constant load to an immediate value. */
5630 {
5634 }
5636 /* Try to simplify X. If the simplification changed the code, it is likely
5637 that further simplification will help, so loop, but limit the number
5638 of repetitions that will be performed. */
5641 {
5642 /* If X is sufficiently simple, don't bother trying to do anything
5643 with it. */
5652 /* We no longer know the original mode of operand 0 since we
5653 have changed the form of X) */
5655 }
5658 }
5659 \f
5660 /* If X is a commutative operation whose operands are not in the canonical
5661 order, use substitutions to swap them. */
5663 static void
5665 {
5668 {
5672 }
5673 }
5675 /* Simplify X, a piece of RTL. We just operate on the expression at the
5676 outer level; call `subst' to simplify recursively. Return the new
5677 expression.
5679 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5680 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5681 of a condition. */
5683 static rtx
5686 {
5689 rtx temp;
5692 /* If this is a commutative operation, put a constant last and a complex
5693 expression first. We don't need to do this for comparisons here. */
5696 /* Try to fold this expression in case we have constants that weren't
5697 present before. */
5700 {
5708 {
5711 {
5715 }
5718 }
5731 }
5734 {
5739 }
5741 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5742 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5743 things. Check for cases where both arms are testing the same
5744 condition.
5746 Don't do anything if all operands are very simple. */
5759 {
5764 /* If everything is a comparison, what we have is highly unlikely
5765 to be simpler, so don't use it. */
5768 {
5775 /* Simplify the alternative arms; this may collapse the true and
5776 false arms to store-flag values. Be careful to use copy_rtx
5777 here since true_rtx or false_rtx might share RTL with x as a
5778 result of the if_then_else_cond call above. */
5782 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5783 is unlikely to be simpler. */
5786 {
5789 /* Restarting if we generate a store-flag expression will cause
5790 us to loop. Just drop through in this case. */
5792 /* If the result values are STORE_FLAG_VALUE and zero, we can
5793 just make the comparison operation. */
5804 /* Likewise, we can make the negate of a comparison operation
5805 if the result values are - STORE_FLAG_VALUE and zero. */
5813 mode);
5824 mode);
5825 else
5828 mode,
5829 VOIDmode,
5830 cond,
5831 cop1),
5836 }
5837 }
5838 }
5840 /* First see if we can apply the inverse distributive law. */
5843 {
5847 }
5849 /* If CODE is an associative operation not otherwise handled, see if we
5850 can associate some operands. This can win if they are constants or
5851 if they are logically related (i.e. (a & b) & a). */
5857 {
5859 {
5863 rtx inner;
5865 /* Make sure we pass the constant operand if any as the second
5866 one if this is a commutative operation. */
5874 /* For commutative operations, try the other pair if that one
5875 didn't simplify. */
5877 {
5882 }
5886 }
5887 }
5889 /* A little bit of algebraic simplification here. */
5891 {
5893 /* Ensure that our address has any ASHIFTs converted to MULT in case
5894 address-recognizing predicates are called later. */
5903 /* See if this can be moved to simplify_subreg. */
5906 /* Don't call gen_lowpart if the inner mode
5907 is VOIDmode and we cannot simplify it, as SUBREG without
5908 inner mode is invalid. */
5915 {
5916 rtx temp;
5922 /* If op is known to have all lower bits zero, the result is zero. */
5932 }
5934 /* Don't change the mode of the MEM if that would change the meaning
5935 of the address. */
5942 /* Note that we cannot do any narrowing for non-constants since
5943 we might have been counting on using the fact that some bits were
5944 zero. We now do this in the SET. */
5951 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5952 replaced by (lshiftrt X C). This will convert
5953 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5961 /* If X has only a single bit that might be nonzero, say, bit I, convert
5962 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5963 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5964 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5965 or a SUBREG of one since we'd be making the expression more
5966 complex if it was just a register. */
5972 {
5973 rtx temp1 = simplify_shift_const
5979 /* If all we did was surround TEMP with the two shifts, we
5980 haven't improved anything, so don't use it. Otherwise,
5981 we are better off with TEMP1. */
5986 }
5990 /* We can't handle truncation to a partial integer mode here
5991 because we don't know the real bitsize of the partial
5992 integer mode. */
6001 /* We can truncate a constant value and return it. */
6005 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6006 whose value is a comparison can be replaced with a subreg if
6007 STORE_FLAG_VALUE permits. */
6016 /* (const (const X)) can become (const X). Do it this way rather than
6017 returning the inner CONST since CONST can be shared with a
6018 REG_EQUAL note. */
6024 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6025 can add in an offset. find_split_point will split this address up
6026 again if it doesn't match. */
6033 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6034 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6035 bit-field and can be replaced by either a sign_extend or a
6036 sign_extract. The `and' may be a zero_extend and the two
6037 <c>, -<c> constants may be reversed. */
6052 return simplify_shift_const
6059 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6060 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6061 the bitsize of the mode - 1. This allows simplification of
6062 "a = (b & 8) == 0;" */
6074 /* If we are adding two things that have no bits in common, convert
6075 the addition into an IOR. This will often be further simplified,
6076 for example in cases like ((a & 1) + (a & 2)), which can
6077 become a & 3. */
6082 {
6083 /* Try to simplify the expression further. */
6087 /* If we could, great. If not, do not go ahead with the IOR
6088 replacement, since PLUS appears in many special purpose
6089 address arithmetic instructions. */
6097 }
6099 /* Canonicalize x + x into x << 1. */
6108 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6109 (and <foo> (const_int pow2-1)) */
6119 /* If we have (mult (plus A B) C), apply the distributive law and then
6120 the inverse distributive law to see if things simplify. This
6121 occurs mostly in addresses, often when unrolling loops. */
6124 {
6128 }
6130 /* Try simplify a*(b/c) as (a*b)/c. */
6133 {
6139 }
6143 /* If this is a divide by a power of two, treat it as a shift if
6144 its first operand is a shift. */
6162 /* If the first operand is a condition code, we can't do anything
6163 with it. */
6167 {
6175 /* Simplify our comparison, if possible. */
6178 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6179 if only the low-order bit is possibly nonzero in X (such as when
6180 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6181 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6182 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6183 (plus X 1).
6185 Remove any ZERO_EXTRACT we made when thinking this was a
6186 comparison. It may now be simpler to use, e.g., an AND. If a
6187 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6188 the call to make_compound_operation in the SET case.
6190 Don't apply these optimizations if the caller would
6191 prefer a comparison rather than a value.
6192 E.g., for the condition in an IF_THEN_ELSE most targets need
6193 an explicit comparison. */
6196 ;
6212 {
6216 mode);
6217 }
6224 {
6228 const1_rtx);
6229 }
6237 {
6240 }
6242 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6243 those above. */
6245 ;
6261 {
6265 mode);
6266 }
6274 {
6278 mode);
6279 }
6281 /* If X is 0/1, (eq X 0) is X-1. */
6287 {
6290 }
6292 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6293 one bit that might be nonzero, we can convert (ne x 0) to
6294 (ashift x c) where C puts the bit in the sign bit. Remove any
6295 AND with STORE_FLAG_VALUE when we are done, since we are only
6296 going to test the sign bit. */
6303 {
6309 else
6311 }
6313 /* If the code changed, return a whole new comparison.
6314 We also need to avoid using SUBST in cases where
6315 simplify_comparison has widened a comparison with a CONST_INT,
6316 since in that case the wider CONST_INT may fail the sanity
6317 checks in do_SUBST. */
6324 /* Otherwise, keep this operation, but maybe change its operands.
6325 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6328 }
6338 /* If we are processing SET_DEST, we are done. */
6356 /* If this is a shift by a constant amount, simplify it. */
6364 (HOST_WIDE_INT_1U
6372 }
6375 }
6376 \f
6377 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6379 static rtx
6381 {
6388 rtx temp;
6391 rtx reversed;
6393 /* Simplify storing of the truth value. */
6398 /* Also when the truth value has to be reversed. */
6404 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6405 in it is being compared against certain values. Get the true and false
6406 comparisons and see if that says anything about the value of each arm. */
6412 {
6413 HOST_WIDE_INT nzb;
6419 /* If FALSE_CODE is EQ, swap the codes and arms. */
6422 {
6425 }
6427 /* If we are comparing against zero and the expression being tested has
6428 only a single bit that might be nonzero, that is its value when it is
6429 not equal to zero. Similarly if it is known to be -1 or 0. */
6433 {
6436 }
6440 {
6443 }
6445 /* Now simplify an arm if we know the value of the register in the
6446 branch and it is used in the arm. Be careful due to the potential
6447 of locally-shared RTL. */
6464 }
6466 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6467 reversed, do so to avoid needing two sets of patterns for
6468 subtract-and-branch insns. Similarly if we have a constant in the true
6469 arm, the false arm is the same as the first operand of the comparison, or
6470 the false arm is more complicated than the true arm. */
6483 {
6492 /* It is possible that the conditional has been simplified out. */
6495 }
6497 /* If the two arms are identical, we don't need the comparison. */
6502 /* Convert a == b ? b : a to "a". */
6514 /* Look for cases where we have (abs x) or (neg (abs X)). */
6517 && comparison_p
6524 {
6530 return
6533 mode);
6536 }
6538 /* Look for MIN or MAX. */
6541 && comparison_p
6546 {
6561 }
6563 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6564 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6565 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6566 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6567 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6568 neither 1 or -1, but it isn't worth checking for. */
6571 && comparison_p
6574 {
6590 /* If an identity-zero op is commutative, check whether there
6591 would be a match if we swapped the operands. */
6611 {
6615 }
6627 {
6631 }
6647 {
6651 }
6663 {
6667 }
6670 {
6676 const_true_rtx));
6684 }
6685 }
6687 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6688 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6689 negation of a single bit, we can convert this operation to a shift. We
6690 can actually do this more generally, but it doesn't seem worth it. */
6699 return
6703 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6704 non-zero bit in A is C1. */
6711 {
6718 }
6721 }
6722 \f
6723 /* Simplify X, a SET expression. Return the new expression. */
6725 static rtx
6727 {
6730 machine_mode mode
6735 /* (set (pc) (return)) gets written as (return). */
6739 /* Now that we know for sure which bits of SRC we are using, see if we can
6740 simplify the expression for the object knowing that we only need the
6741 low-order bits. */
6744 {
6747 }
6749 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6750 the comparison result and try to simplify it unless we already have used
6751 undobuf.other_insn. */
6759 {
6768 {
6771 {
6774 }
6775 }
6776 else
6784 {
6788 }
6789 else
6790 {
6795 /* Attempt to simplify CC user. */
6797 {
6801 }
6803 /* Convert X into a no-op move. */
6807 }
6809 /* Simplify our comparison, if possible. */
6812 #ifdef SELECT_CC_MODE
6813 /* If this machine has CC modes other than CCmode, check to see if we
6814 need to use a different CC mode here. */
6823 else
6826 /* If the mode changed, we have to change SET_DEST, the mode in the
6827 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6828 a hard register, just build new versions with the proper mode. If it
6829 is a pseudo, we lose unless it is only time we set the pseudo, in
6830 which case we can safely change its mode. */
6832 {
6834 {
6836 rtx new_dest;
6840 else
6841 {
6844 }
6851 }
6852 }
6855 /* If the code changed, we have to build a new comparison in
6856 undobuf.other_insn. */
6858 {
6867 /* If the only change we made was to change an EQ into an NE or
6868 vice versa, OP0 has only one bit that might be nonzero, and OP1
6869 is zero, check if changing the user of the condition code will
6870 produce a valid insn. If it won't, we can keep the original code
6871 in that insn by surrounding our operation with an XOR. */
6878 {
6883 {
6890 }
6891 }
6892 }
6897 /* Don't generate a compare of a CC with 0, just use that CC. */
6899 {
6902 }
6903 /* Otherwise, if we didn't previously have the same COMPARE we
6904 want, create it from scratch. */
6907 {
6910 }
6911 }
6912 else
6913 {
6914 /* Get SET_SRC in a form where we have placed back any
6915 compound expressions. Then do the checks below. */
6918 }
6920 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6921 and X being a REG or (subreg (reg)), we may be able to convert this to
6922 (set (subreg:m2 x) (op)).
6924 We can always do this if M1 is narrower than M2 because that means that
6925 we only care about the low bits of the result.
6927 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6928 perform a narrower operation than requested since the high-order bits will
6929 be undefined. On machine where it is defined, this transformation is safe
6930 as long as M1 and M2 have the same number of words. */
6938 && (WORD_REGISTER_OPERATIONS
6941 #ifdef CANNOT_CHANGE_MODE_CLASS
6946 #endif
6950 {
6953 dest));
6957 }
6959 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6960 in SRC. */
6966 {
6970 /* Here we make sure that we don't have a sign bit on. */
6973 {
6976 }
6977 }
6979 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6980 would require a paradoxical subreg. Replace the subreg with a
6981 zero_extend to avoid the reload that would otherwise be required. */
6987 {
6992 }
6994 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6995 are comparing an item known to be 0 or -1 against 0, use a logical
6996 operation instead. Check for one of the arms being an IOR of the other
6997 arm with some value. We compute three terms to be IOR'ed together. In
6998 practice, at most two will be nonzero. Then we do the IOR's. */
7006 && (!HAVE_conditional_move
7012 {
7038 false_rtx);
7044 term3));
7047 }
7049 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7050 whole thing fail. */
7055 else
7056 /* Convert this into a field assignment operation, if possible. */
7058 }
7059 \f
7060 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7061 result. */
7063 static rtx
7065 {
7071 {
7073 /* We can call simplify_and_const_int only if we don't lose
7074 any (sign) bits when converting INTVAL (op1) to
7075 "unsigned HOST_WIDE_INT". */
7079 {
7086 }
7088 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7089 apply the distributive law and then the inverse distributive
7090 law to see if things simplify. */
7092 {
7096 }
7098 {
7102 }
7106 /* If we have (ior (and A B) C), apply the distributive law and then
7107 the inverse distributive law to see if things simplify. */
7110 {
7114 }
7117 {
7121 }
7126 }
7129 }
7130 \f
7131 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7132 operations" because they can be replaced with two more basic operations.
7133 ZERO_EXTEND is also considered "compound" because it can be replaced with
7134 an AND operation, which is simpler, though only one operation.
7136 The function expand_compound_operation is called with an rtx expression
7137 and will convert it to the appropriate shifts and AND operations,
7138 simplifying at each stage.
7140 The function make_compound_operation is called to convert an expression
7141 consisting of shifts and ANDs into the equivalent compound expression.
7142 It is the inverse of this function, loosely speaking. */
7144 static rtx
7146 {
7150 rtx tem;
7153 {
7156 /* FALLTHRU */
7158 /* We can't necessarily use a const_int for a multiword mode;
7159 it depends on implicitly extending the value.
7160 Since we don't know the right way to extend it,
7161 we can't tell whether the implicit way is right.
7163 Even for a mode that is no wider than a const_int,
7164 we can't win, because we need to sign extend one of its bits through
7165 the rest of it, and we don't know which bit. */
7169 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7170 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7171 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7172 reloaded. If not for that, MEM's would very rarely be safe.
7174 Reject MODEs bigger than a word, because we might not be able
7175 to reference a two-register group starting with an arbitrary register
7176 (and currently gen_lowpart might crash for a SUBREG). */
7181 /* Reject MODEs that aren't scalar integers because turning vector
7182 or complex modes into shifts causes problems. */
7188 /* If the inner object has VOIDmode (the only way this can happen
7189 is if it is an ASM_OPERANDS), we can't do anything since we don't
7190 know how much masking to do. */
7199 /* fall through */
7202 /* If the operand is a CLOBBER, just return it. */
7211 /* Reject MODEs that aren't scalar integers because turning vector
7212 or complex modes into shifts causes problems. */
7220 /* This should stay within the object being extracted, fail otherwise. */
7231 }
7232 /* Convert sign extension to zero extension, if we know that the high
7233 bit is not set, as this is easier to optimize. It will be converted
7234 back to cheaper alternative in make_extraction. */
7242 {
7247 /* Make sure this is a profitable operation. */
7254 else
7256 }
7258 /* We can optimize some special cases of ZERO_EXTEND. */
7260 {
7261 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7262 know that the last value didn't have any inappropriate bits
7263 set. */
7271 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7280 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7281 is a comparison and STORE_FLAG_VALUE permits. This is like
7282 the first case, but it works even when GET_MODE (x) is larger
7283 than HOST_WIDE_INT. */
7292 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7302 }
7304 /* If we reach here, we want to return a pair of shifts. The inner
7305 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7306 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7307 logical depending on the value of UNSIGNEDP.
7309 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7310 converted into an AND of a shift.
7312 We must check for the case where the left shift would have a negative
7313 count. This can happen in a case like (x >> 31) & 255 on machines
7314 that can't shift by a constant. On those machines, we would first
7315 combine the shift with the AND to produce a variable-position
7316 extraction. Then the constant of 31 would be substituted in
7317 to produce such a position. */
7321 {
7330 }
7337 else
7338 /* Any other cases we can't handle. */
7341 /* If we couldn't do this for some reason, return the original
7342 expression. */
7347 }
7348 \f
7349 /* X is a SET which contains an assignment of one object into
7350 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7351 or certain SUBREGS). If possible, convert it into a series of
7352 logical operations.
7354 We half-heartedly support variable positions, but do not at all
7355 support variable lengths. */
7357 static const_rtx
7359 {
7360 rtx inner;
7364 machine_mode compute_mode;
7366 /* Loop until we find something we can't simplify. */
7368 {
7371 {
7375 }
7378 {
7383 /* A constant position should stay within the width of INNER. */
7389 {
7397 /* If position is ADJUST - X, new position is X. */
7399 else
7400 {
7405 pos);
7406 }
7407 }
7408 }
7410 /* A SUBREG between two modes that occupy the same numbers of words
7411 can be done by moving the SUBREG to the source. */
7413 /* We need SUBREGs to compute nonzero_bits properly. */
7414 && nonzero_sign_valid
7419 {
7421 gen_lowpart
7425 }
7426 else
7434 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7436 {
7437 machine_mode imode;
7439 /* Don't do anything for vector or complex integral types. */
7443 /* Try to find an integral mode to pun with. */
7450 }
7452 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7456 /* Don't try to compute in too wide unsupported modes. */
7460 /* Now compute the equivalent expression. Make a copy of INNER
7461 for the SET_DEST in case it is a MEM into which we will substitute;
7462 we don't want shared RTL in that case. */
7464 compute_mode);
7468 compute_mode,
7470 compute_mode),
7471 inner);
7476 mask),
7477 pos);
7482 }
7485 }
7486 \f
7487 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7488 it is an RTX that represents the (variable) starting position; otherwise,
7489 POS is the (constant) starting bit position. Both are counted from the LSB.
7491 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7493 IN_DEST is nonzero if this is a reference in the destination of a SET.
7494 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7495 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7496 be used.
7498 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7499 ZERO_EXTRACT should be built even for bits starting at bit 0.
7501 MODE is the desired mode of the result (if IN_DEST == 0).
7503 The result is an RTX for the extraction or NULL_RTX if the target
7504 can't handle it. */
7506 static rtx
7510 {
7511 /* This mode describes the size of the storage area
7512 to fetch the overall value from. Within that, we
7513 ignore the POS lowest bits, etc. */
7515 machine_mode inner_mode;
7516 machine_mode wanted_inner_mode;
7523 HOST_WIDE_INT orig_pos;
7529 {
7530 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7531 consider just the QI as the memory to extract from.
7532 The subreg adds or removes high bits; its mode is
7533 irrelevant to the meaning of this extraction,
7534 since POS and LEN count from the lsb. */
7538 }
7543 {
7544 /* We're extracting the least significant bits of an rtx
7545 (ashift X (const_int C)), where LEN > C. Extract the
7546 least significant (LEN - C) bits of X, giving an rtx
7547 whose mode is MODE, then shift it left C times. */
7553 }
7559 /* See if this can be done without an extraction. We never can if the
7560 width of the field is not the same as that of some integer mode. For
7561 registers, we can only avoid the extraction if the position is at the
7562 low-order bit and this is either not in the destination or we have the
7563 appropriate STRICT_LOW_PART operation available.
7565 For MEM, we can avoid an extract if the field starts on an appropriate
7566 boundary and we can change the mode of the memory reference. */
7576 && (! in_dest
7580 && (pos
7583 /* We can't do this if we are widening INNER_MODE (it
7584 may not be aligned, for one thing). */
7590 {
7591 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7592 field. If the original and current mode are the same, we need not
7593 adjust the offset. Otherwise, we do if bytes big endian.
7595 If INNER is not a MEM, get a piece consisting of just the field
7596 of interest (in this case POS % BITS_PER_WORD must be 0). */
7599 {
7600 HOST_WIDE_INT offset;
7602 /* POS counts from lsb, but make OFFSET count in memory order. */
7605 else
7609 }
7611 {
7613 {
7614 /* We can't call gen_lowpart in a DEST since we
7615 always want a SUBREG (see below) and it would sometimes
7616 return a new hard register. */
7618 {
7633 /* Avoid creating invalid subregs, for example when
7634 simplifying (x>>32)&255. */
7639 }
7640 else
7642 }
7643 else
7645 }
7646 else
7648 len >= HOST_BITS_PER_WIDE_INT
7649 ? HOST_WIDE_INT_M1U
7652 /* If this extraction is going into the destination of a SET,
7653 make a STRICT_LOW_PART unless we made a MEM. */
7668 /* If we know that no extraneous bits are set, and that the high
7669 bit is not set, convert the extraction to the cheaper of
7670 sign and zero extension, that are equivalent in these cases. */
7676 {
7680 /* Prefer ZERO_EXTENSION, since it gives more information to
7681 backends. */
7686 }
7688 /* Otherwise, sign- or zero-extend unless we already are in the
7689 proper mode. */
7693 }
7695 /* Unless this is a COMPARE or we have a funny memory reference,
7696 don't do anything with zero-extending field extracts starting at
7697 the low-order bit since they are simple AND operations. */
7702 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7703 if the position is not a constant and the length is not 1. In all
7704 other cases, we would only be going outside our object in cases when
7705 an original shift would have been undefined. */
7714 /* If INNER is not from memory, we want it to have the mode of a register
7715 extraction pattern's structure operand, or word_mode if there is no
7716 such pattern. The same applies to extraction_mode and pos_mode
7717 and their respective operands.
7719 For memory, assume that the desired extraction_mode and pos_mode
7720 are the same as for a register operation, since at present we don't
7721 have named patterns for aligned memory structures. */
7725 {
7729 }
7731 /* Never narrow an object, since that might not be safe. */
7739 else
7740 {
7741 /* Be careful not to go beyond the extracted object and maintain the
7742 natural alignment of the memory. */
7746 {
7749 }
7750 }
7755 {
7756 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7757 BITS_BIG_ENDIAN style. If position is constant, compute new
7758 position. Otherwise, build subtraction.
7759 Note that POS is relative to the mode of the original argument.
7760 If it's a MEM we need to recompute POS relative to that.
7761 However, if we're extracting from (or inserting into) a register,
7762 we want to recompute POS relative to wanted_inner_mode. */
7769 else
7770 pos_rtx
7773 pos_rtx);
7774 /* POS may be less than 0 now, but we check for that below.
7775 Note that it can only be less than 0 if !MEM_P (inner). */
7776 }
7778 /* If INNER has a wider mode, and this is a constant extraction, try to
7779 make it smaller and adjust the byte to point to the byte containing
7780 the value. */
7783 && ! pos_rtx
7788 {
7791 /* The computations below will be correct if the machine is big
7792 endian in both bits and bytes or little endian in bits and bytes.
7793 If it is mixed, we must adjust. */
7795 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7796 adjust OFFSET to compensate. */
7801 /* We can now move to the desired byte. */
7812 }
7814 /* If INNER is not memory, get it into the proper mode. If we are changing
7815 its mode, POS must be a constant and smaller than the size of the new
7816 mode. */
7818 {
7819 /* On the LHS, don't create paradoxical subregs implicitely truncating
7820 the register unless TRULY_NOOP_TRUNCATION. */
7823 wanted_inner_mode))
7835 pos_rtx
7837 ? HOST_WIDE_INT_M1U
7841 }
7843 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7844 have to zero extend. Otherwise, we can just use a SUBREG. */
7847 {
7851 /* If we know that no extraneous bits are set, and that the high
7852 bit is not set, convert extraction to cheaper one - either
7853 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7854 cases. */
7862 {
7866 /* Prefer ZERO_EXTENSION, since it gives more information to
7867 backends. */
7871 }
7873 }
7875 /* Make POS_RTX unless we already have it and it is correct. If we don't
7876 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7877 be a CONST_INT. */
7884 /* Make the required operation. See if we can use existing rtx. */
7891 }
7892 \f
7893 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7894 with any other operations in X. Return X without that shift if so. */
7896 static rtx
7898 {
7901 rtx tem;
7904 {
7906 /* This is the shift itself. If it is wide enough, we will return
7907 either the value being shifted if the shift count is equal to
7908 COUNT or a shift for the difference. */
7922 /* If we can safely shift this constant and we find the inner shift,
7923 make a new operation. */
7928 {
7932 }
7937 }
7940 }
7941 \f
7942 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7943 level of the expression and MODE is its mode. IN_CODE is as for
7944 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7945 that should be used when recursing on operands of *X_PTR.
7947 There are two possible actions:
7949 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7950 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7952 - Return a new rtx, which the caller returns directly. */
7954 static rtx
7958 {
7966 rtx tem;
7970 {
7973 }
7975 /* Process depending on the code of this operation. If NEW is set
7976 nonzero, it will be returned. */
7979 {
7981 /* Convert shifts by constants into multiplications if inside
7982 an address. */
7986 {
7992 {
7995 }
7998 }
8007 {
8011 }
8014 {
8018 mode));
8020 }
8021 else
8022 {
8025 }
8035 {
8039 }
8042 {
8046 mode));
8048 }
8049 else
8050 {
8054 }
8057 /* If the second operand is not a constant, we can't do anything
8058 with it. */
8062 /* If the constant is a power of two minus one and the first operand
8063 is a logical right shift, make an extraction. */
8066 {
8070 }
8072 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8077 {
8086 {
8087 /* If we narrowed the mode when dropping the subreg, then
8088 we must zero-extend to keep the semantics of the AND. */
8090 ;
8094 else
8096 }
8098 /* If that didn't give anything, see if the AND simplifies on
8099 its own. */
8101 {
8105 }
8106 }
8107 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8113 {
8114 /* Apply the distributive law, and then try to make extractions. */
8121 }
8123 /* If we are have (and (rotate X C) M) and C is larger than the number
8124 of bits in M, this is an extraction. */
8130 {
8136 }
8138 /* On machines without logical shifts, if the operand of the AND is
8139 a logical shift and our mask turns off all the propagated sign
8140 bits, we can replace the logical shift with an arithmetic shift. */
8148 {
8155 make_compound_operation
8158 }
8160 /* If the constant is one less than a power of two, this might be
8161 representable by an extraction even if no shift is present.
8162 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8163 we are in a COMPARE. */
8167 next_code),
8170 /* If we are in a comparison and this is an AND with a power of two,
8171 convert this into the appropriate bit extract. */
8177 next_code),
8180 /* If the one operand is a paradoxical subreg of a register or memory and
8181 the constant (limited to the smaller mode) has only zero bits where
8182 the sub expression has known zero bits, this can be expressed as
8183 a zero_extend. */
8185 {
8186 rtx sub;
8192 {
8196 /* original AND constant with all the known zero bits set */
8199 {
8204 }
8205 }
8206 }
8211 /* If the sign bit is known to be zero, replace this with an
8212 arithmetic shift. */
8217 {
8220 next_code),
8223 }
8225 /* fall through */
8231 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8232 this is a SIGN_EXTRACT. */
8239 {
8246 }
8248 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8249 If so, try to merge the shifts into a SIGN_EXTEND. We could
8250 also do this for some cases of SIGN_EXTRACT, but it doesn't
8251 seem worth the effort; the case checked for occurs on Alpha. */
8268 /* Call ourselves recursively on the inner expression. If we are
8269 narrowing the object and it has a different RTL code from
8270 what it originally did, do this SUBREG as a force_to_mode. */
8271 {
8275 /* If the SUBREG is masking of a logical right shift,
8276 make an extraction. */
8283 {
8292 }
8294 /* If in_code is COMPARE, it isn't always safe to pass it through
8295 to the recursive make_compound_operation call. */
8299 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8300 is (const_int 0), rather than
8301 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8311 simplified
8319 {
8320 rtx newer
8323 /* If we have something other than a SUBREG, we might have
8324 done an expansion, so rerun ourselves. */
8328 /* force_to_mode can expand compounds. If it just re-expanded the
8329 compound, use gen_lowpart to convert to the desired mode. */
8331 /* Likewise if it re-expanded the compound only partially.
8332 This happens for SUBREG of ZERO_EXTRACT if they extract
8333 the same number of bits. */
8342 }
8346 }
8351 }
8357 }
8359 /* Look at the expression rooted at X. Look for expressions
8360 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8361 Form these expressions.
8363 Return the new rtx, usually just X.
8365 Also, for machines like the VAX that don't have logical shift insns,
8366 try to convert logical to arithmetic shift operations in cases where
8367 they are equivalent. This undoes the canonicalizations to logical
8368 shifts done elsewhere.
8370 We try, as much as possible, to re-use rtl expressions to save memory.
8372 IN_CODE says what kind of expression we are processing. Normally, it is
8373 SET. In a memory address it is MEM. When processing the arguments of
8374 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8375 precisely it is an equality comparison against zero. */
8377 rtx
8379 {
8386 /* Select the code to be used in recursive calls. Once we are inside an
8387 address, we stay there. If we have a comparison, set to COMPARE,
8388 but once inside, go back to our default of SET. */
8396 {
8402 }
8404 /* Now recursively process each operand of this operation. We need to
8405 handle ZERO_EXTEND specially so that we don't lose track of the
8406 inner mode. */
8408 {
8416 }
8421 {
8424 }
8427 {
8430 }
8434 }
8435 \f
8436 /* Given M see if it is a value that would select a field of bits
8437 within an item, but not the entire word. Return -1 if not.
8438 Otherwise, return the starting position of the field, where 0 is the
8439 low-order bit.
8441 *PLEN is set to the length of the field. */
8443 static int
8445 {
8446 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8451 /* Now shift off the low-order zero bits and see if we have a
8452 power of two minus 1. */
8460 }
8461 \f
8462 /* If X refers to a register that equals REG in value, replace these
8463 references with REG. */
8464 static rtx
8466 {
8474 {
8507 /* FALLTHRU */
8511 {
8515 else
8517 }
8519 /* fall through */
8526 {
8529 {
8531 {
8534 }
8536 }
8537 }
8539 {
8542 {
8545 {
8547 {
8550 }
8552 }
8553 }
8554 }
8557 }
8560 }
8562 /* Return X converted to MODE. If the value is already truncated to
8563 MODE we can just return a subreg even though in the general case we
8564 would need an explicit truncation. */
8566 static rtx
8568 {
8573 {
8574 /* Bit-cast X into an integer mode. */
8579 }
8582 }
8584 /* See if X can be simplified knowing that we will only refer to it in
8585 MODE and will only refer to those bits that are nonzero in MASK.
8586 If other bits are being computed or if masking operations are done
8587 that select a superset of the bits in MASK, they can sometimes be
8588 ignored.
8590 Return a possibly simplified expression, but always convert X to
8591 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8593 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8594 are all off in X. This is used when X will be complemented, by either
8595 NOT, NEG, or XOR. */
8597 static rtx
8600 {
8603 machine_mode op_mode;
8607 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8608 code below will do the wrong thing since the mode of such an
8609 expression is VOIDmode.
8611 Also do nothing if X is a CLOBBER; this can happen if X was
8612 the return value from a call to gen_lowpart. */
8616 /* We want to perform the operation in its present mode unless we know
8617 that the operation is valid in MODE, in which case we do the operation
8618 in MODE. */
8623 /* It is not valid to do a right-shift in a narrower mode
8624 than the one it came in with. */
8629 /* Truncate MASK to fit OP_MODE. */
8633 /* When we have an arithmetic operation, or a shift whose count we
8634 do not know, we need to assume that all bits up to the highest-order
8635 bit in MASK will be needed. This is how we form such a mask. */
8638 else
8642 /* Determine what bits of X are guaranteed to be (non)zero. */
8645 /* If none of the bits in X are needed, return a zero. */
8649 /* If X is a CONST_INT, return a new one. Do this here since the
8650 test below will fail. */
8652 {
8655 else
8656 {
8659 }
8660 }
8662 /* If X is narrower than MODE and we want all the bits in X's mode, just
8663 get X in the proper mode. */
8668 /* We can ignore the effect of a SUBREG if it narrows the mode or
8669 if the constant masks to zero all the bits the mode doesn't have. */
8679 /* The arithmetic simplifications here only work for scalar integer modes. */
8684 {
8686 /* If X is a (clobber (const_int)), return it since we know we are
8687 generating something that won't match. */
8700 /* Similarly for a truncate. */
8704 /* If this is an AND with a constant, convert it into an AND
8705 whose constant is the AND of that constant with MASK. If it
8706 remains an AND of MASK, delete it since it is redundant. */
8709 {
8713 /* If X is still an AND, see if it is an AND with a mask that
8714 is just some low-order bits. If so, and it is MASK, we don't
8715 need it. */
8722 /* If it remains an AND, try making another AND with the bits
8723 in the mode mask that aren't in MASK turned on. If the
8724 constant in the AND is wide enough, this might make a
8725 cheaper constant. */
8730 {
8731 unsigned HOST_WIDE_INT cval
8734 rtx y;
8741 }
8744 }
8749 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8750 low-order bits (as in an alignment operation) and FOO is already
8751 aligned to that boundary, mask C1 to that boundary as well.
8752 This may eliminate that PLUS and, later, the AND. */
8754 {
8758 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8759 number, sign extend it. */
8772 }
8774 /* fall through */
8777 /* Substituting into the operands of a widening MULT is not likely to
8778 create RTL matching a machine insn. */
8788 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8789 most significant bit in MASK since carries from those bits will
8790 affect the bits we are interested in. */
8795 /* If X is (minus C Y) where C's least set bit is larger than any bit
8796 in the mask, then we may replace with (neg Y). */
8799 {
8803 }
8805 /* Similarly, if C contains every bit in the fuller_mask, then we may
8806 replace with (not Y). */
8809 {
8813 }
8820 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8821 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8822 operation which may be a bitfield extraction. Ensure that the
8823 constant we form is not wider than the mode of X. */
8835 {
8844 }
8846 binop:
8847 /* For most binary operations, just propagate into the operation and
8848 change the mode if we have an operation of that mode. */
8853 /* If we ended up truncating both operands, truncate the result of the
8854 operation instead. */
8857 {
8860 }
8870 /* For left shifts, do the same, but just for the first operand.
8871 However, we cannot do anything with shifts where we cannot
8872 guarantee that the counts are smaller than the size of the mode
8873 because such a count will have a different meaning in a
8874 wider mode. */
8884 /* If the shift count is a constant and we can do arithmetic in
8885 the mode of the shift, refine which bits we need. Otherwise, use the
8886 conservative form of the mask. */
8892 else
8904 /* Here we can only do something if the shift count is a constant,
8905 this shift constant is valid for the host, and we can do arithmetic
8906 in OP_MODE. */
8912 {
8916 /* Select the mask of the bits we need for the shift operand. */
8919 /* We can only change the mode of the shift if we can do arithmetic
8920 in the mode of the shift and INNER_MASK is no wider than the
8921 width of X's mode. */
8929 }
8931 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8932 shift and AND produces only copies of the sign bit (C2 is one less
8933 than a power of two), we can do this with just a shift. */
8937 /* The shift puts one of the sign bit copies in the least significant
8938 bit. */
8943 /* Number of bits left after the shift must be more than the mask
8944 needs. */
8947 /* Must be more sign bit copies than the mask needs. */
8957 /* If we are just looking for the sign bit, we don't need this shift at
8958 all, even if it has a variable count. */
8962 /* If this is a shift by a constant, get a mask that contains those bits
8963 that are not copies of the sign bit. We then have two cases: If
8964 MASK only includes those bits, this can be a logical shift, which may
8965 allow simplifications. If MASK is a single-bit field not within
8966 those bits, we are requesting a copy of the sign bit and hence can
8967 shift the sign bit to the appropriate location. */
8971 {
8974 /* If the considered data is wider than HOST_WIDE_INT, we can't
8975 represent a mask for all its bits in a single scalar.
8976 But we only care about the lower bits, so calculate these. */
8979 {
8982 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8983 is the number of bits a full-width mask would have set.
8984 We need only shift if these are fewer than nonzero can
8985 hold. If not, we must keep all bits set in nonzero. */
8990 + HOST_BITS_PER_WIDE_INT
8992 }
8993 else
8994 {
8997 }
9000 {
9005 }
9008 {
9009 x = simplify_shift_const
9015 }
9016 }
9018 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9019 even if the shift count isn't a constant. */
9024 shiftrt:
9026 /* If this is a zero- or sign-extension operation that just affects bits
9027 we don't care about, remove it. Be sure the call above returned
9028 something that is still a shift. */
9038 next_select);
9044 /* If the shift count is constant and we can do computations
9045 in the mode of X, compute where the bits we care about are.
9046 Otherwise, we can't do anything. Don't change the mode of
9047 the shift or propagate MODE into the shift, though. */
9050 {
9060 }
9064 /* If we just want the low-order bit, the NEG isn't needed since it
9065 won't change the low-order bit. */
9069 /* We need any bits less significant than the most significant bit in
9070 MASK since carries from those bits will affect the bits we are
9071 interested in. */
9076 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9077 same as the XOR case above. Ensure that the constant we form is not
9078 wider than the mode of X. */
9086 {
9095 }
9097 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9098 use the full mask inside the NOT. */
9101 unop:
9104 next_select));
9110 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9111 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9112 which is equal to STORE_FLAG_VALUE. */
9124 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9125 written in a narrower mode. We play it safe and do not do so. */
9141 }
9143 /* Ensure we return a value of the proper mode. */
9145 }
9146 \f
9147 /* Return nonzero if X is an expression that has one of two values depending on
9148 whether some other value is zero or nonzero. In that case, we return the
9149 value that is being tested, *PTRUE is set to the value if the rtx being
9150 returned has a nonzero value, and *PFALSE is set to the other alternative.
9152 If we return zero, we set *PTRUE and *PFALSE to X. */
9154 static rtx
9156 {
9162 /* If we are comparing a value against zero, we are done. */
9165 {
9169 }
9171 /* If this is a unary operation whose operand has one of two values, apply
9172 our opcode to compute those values. */
9175 {
9180 }
9182 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9183 make can't possibly match and would suppress other optimizations. */
9185 ;
9187 /* If this is a binary operation, see if either side has only one of two
9188 values. If either one does or if both do and they are conditional on
9189 the same value, compute the new true and false values. */
9191 {
9199 {
9200 /* Try to enable a simplification by undoing work done by
9201 if_then_else_cond if it converted a REG into something more
9202 complex. */
9204 {
9207 }
9208 else
9209 {
9212 }
9213 }
9217 {
9218 /* If if_then_else_cond returned zero, then true/false are the
9219 same rtl. We must copy one of them to prevent invalid rtl
9220 sharing. */
9227 {
9232 }
9233 else
9234 {
9237 }
9240 }
9242 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9243 operands is zero when the other is nonzero, and vice-versa,
9244 and STORE_FLAG_VALUE is 1 or -1. */
9250 {
9267 {
9274 const_true_rtx);
9276 }
9277 }
9279 /* Similarly for MULT, AND and UMIN, except that for these the result
9280 is always zero. */
9284 {
9298 {
9301 }
9302 }
9303 }
9306 {
9307 /* If we have IF_THEN_ELSE already, extract the condition and
9308 canonicalize it if it is NE or EQ. */
9314 {
9317 }
9318 else
9320 }
9322 /* If X is a SUBREG, we can narrow both the true and false values
9323 if the inner expression, if there is a condition. */
9327 {
9333 {
9337 }
9338 }
9340 /* If X is a constant, this isn't special and will cause confusions
9341 if we treat it as such. Likewise if it is equivalent to a constant. */
9344 ;
9346 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9347 will be least confusing to the rest of the compiler. */
9349 {
9352 }
9354 /* If X is known to be either 0 or -1, those are the true and
9355 false values when testing X. */
9359 {
9362 }
9364 /* Likewise for 0 or a single bit. */
9367 {
9370 }
9372 /* Otherwise fail; show no condition with true and false values the same. */
9375 }
9376 \f
9377 /* Return the value of expression X given the fact that condition COND
9378 is known to be true when applied to REG as its first operand and VAL
9379 as its second. X is known to not be shared and so can be modified in
9380 place.
9382 We only handle the simplest cases, and specifically those cases that
9383 arise with IF_THEN_ELSE expressions. */
9385 static rtx
9387 {
9395 /* If either operand of the condition is a floating point value,
9396 then we have to avoid collapsing an EQ comparison. */
9406 /* If X is (abs REG) and we know something about REG's relationship
9407 with zero, we may be able to simplify this. */
9411 {
9420 }
9422 /* The only other cases we handle are MIN, MAX, and comparisons if the
9423 operands are the same as REG and VAL. */
9426 {
9428 {
9431 }
9434 {
9436 {
9444 else
9446 }
9449 {
9452 /* Do not reverse the condition when it is NE or EQ.
9453 This is because we cannot conclude anything about
9454 the value of 'SMAX (x, y)' when x is not equal to y,
9455 but we can when x equals y. */
9461 {
9472 }
9473 }
9474 }
9475 }
9477 {
9482 {
9483 /* We must simplify subreg here, before we lose track of the
9484 original inner_mode. */
9489 else
9491 }
9494 }
9495 /* We don't have to handle SIGN_EXTEND here, because even in the
9496 case of replacing something with a modeless CONST_INT, a
9497 CONST_INT is already (supposed to be) a valid sign extension for
9498 its narrower mode, which implies it's already properly
9499 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9500 story is different. */
9502 {
9507 {
9508 /* We must simplify the zero_extend here, before we lose
9509 track of the original inner_mode. */
9514 else
9516 }
9519 }
9523 {
9530 }
9533 }
9534 \f
9535 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9536 assignment as a field assignment. */
9538 static int
9540 {
9542 {
9547 /* For big endian, adjust the memory offset. */
9552 else
9554 }
9562 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9563 Note that all SUBREGs of MEM are paradoxical; otherwise they
9564 would have been rewritten. */
9577 /* We used to see if get_last_value of X and Y were the same but that's
9578 not correct. In one direction, we'll cause the assignment to have
9579 the wrong destination and in the case, we'll import a register into this
9580 insn that might have already have been dead. So fail if none of the
9581 above cases are true. */
9583 }
9584 \f
9585 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9586 Return that assignment if so.
9588 We only handle the most common cases. */
9590 static rtx
9592 {
9595 rtx assign;
9597 HOST_WIDE_INT c1;
9598 HOST_WIDE_INT pos;
9600 rtx other;
9601 machine_mode mode;
9603 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9604 a clear of a one-bit field. We will have changed it to
9605 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9606 for a SUBREG. */
9612 {
9618 }
9628 {
9635 }
9637 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9638 one-bit field. */
9642 {
9648 }
9650 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9651 SRC is an AND with all bits of that field set, then we can discard
9652 the AND. */
9657 {
9664 else
9667 /* Complete overlap. We can remove the source AND. */
9671 /* Partial overlap. We can reduce the source AND. */
9673 {
9678 }
9679 }
9681 /* The other case we handle is assignments into a constant-position
9682 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9683 a mask that has all one bits except for a group of zero bits and
9684 OTHER is known to have zeros where C1 has ones, this is such an
9685 assignment. Compute the position and length from C1. Shift OTHER
9686 to the appropriate position, force it to the required mode, and
9687 make the extraction. Check for the AND in both operands. */
9689 /* One or more SUBREGs might obscure the constant-position field
9690 assignment. The first one we are likely to encounter is an outer
9691 narrowing SUBREG, which we can just strip for the purposes of
9692 identifying the constant-field assignment. */
9706 /* The second SUBREG that might get in the way is a paradoxical
9707 SUBREG around the first operand of the AND. We want to
9708 pretend the operand is as wide as the destination here. We
9709 do this by adjusting the MEM to wider mode for the sole
9710 purpose of the call to rtx_equal_for_field_assignment_p. Also
9711 note this trick only works for MEMs. */
9723 /* The second SUBREG that might get in the way is a paradoxical
9724 SUBREG around the first operand of the AND. We want to
9725 pretend the operand is as wide as the destination here. We
9726 do this by adjusting the MEM to wider mode for the sole
9727 purpose of the call to rtx_equal_for_field_assignment_p. Also
9728 note this trick only works for MEMs. */
9736 else
9749 /* The mode to use for the source is the mode of the assignment, or of
9750 what is inside a possible STRICT_LOW_PART. */
9754 /* Shift OTHER right POS places and make it the source, restricting it
9755 to the proper length and mode. */
9760 dest);
9763 ? HOST_WIDE_INT_M1U
9767 /* If SRC is masked by an AND that does not make a difference in
9768 the value being stored, strip it. */
9779 }
9780 \f
9781 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9782 if so. */
9784 static rtx
9786 {
9790 rtx tem;
9792 /* Distributivity is not true for floating point as it can change the
9793 value. So we don't do it unless -funsafe-math-optimizations. */
9798 /* The outer operation can only be one of the following: */
9806 /* If either operand is a primitive we can't do anything, so get out
9807 fast. */
9817 /* See if the inner and outer operations distribute. */
9819 {
9824 /* These all distribute except over PLUS. */
9835 /* This is also a multiply, so it distributes over everything. */
9838 /* This used to handle SUBREG, but this turned out to be counter-
9839 productive, since (subreg (op ...)) usually is not handled by
9840 insn patterns, and this "optimization" therefore transformed
9841 recognizable patterns into unrecognizable ones. Therefore the
9842 SUBREG case was removed from here.
9844 It is possible that distributing SUBREG over arithmetic operations
9845 leads to an intermediate result than can then be optimized further,
9846 e.g. by moving the outer SUBREG to the other side of a SET as done
9847 in simplify_set. This seems to have been the original intent of
9848 handling SUBREGs here.
9850 However, with current GCC this does not appear to actually happen,
9851 at least on major platforms. If some case is found where removing
9852 the SUBREG case here prevents follow-on optimizations, distributing
9853 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9857 }
9859 /* Set LHS and RHS to the inner operands (A and B in the example
9860 above) and set OTHER to the common operand (C in the example).
9861 There is only one way to do this unless the inner operation is
9862 commutative. */
9874 else
9877 /* Form the new inner operation, seeing if it simplifies first. */
9880 /* There is one exception to the general way of distributing:
9881 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9883 {
9886 }
9888 /* We may be able to continuing distributing the result, so call
9889 ourselves recursively on the inner operation before forming the
9890 outer operation, which we return. */
9893 }
9895 /* See if X is of the form (* (+ A B) C), and if so convert to
9896 (+ (* A C) (* B C)) and try to simplify.
9898 Most of the time, this results in no change. However, if some of
9899 the operands are the same or inverses of each other, simplifications
9900 will result.
9902 For example, (and (ior A B) (not B)) can occur as the result of
9903 expanding a bit field assignment. When we apply the distributive
9904 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9905 which then simplifies to (and (A (not B))).
9907 Note that no checks happen on the validity of applying the inverse
9908 distributive law. This is pointless since we can do it in the
9909 few places where this routine is called.
9911 N is the index of the term that is decomposed (the arithmetic operation,
9912 i.e. (+ A B) in the first example above). !N is the index of the term that
9913 is distributed, i.e. of C in the first example above. */
9914 static rtx
9916 {
9917 machine_mode mode;
9921 /* Distributivity is not true for floating point as it can change the
9922 value. So we don't do it unless -funsafe-math-optimizations. */
9939 /* Special case (and (xor B C) (not A)), which is equivalent to
9940 (xor (ior A B) (ior A C)) */
9942 {
9945 }
9948 {
9949 /* Distribute the second term. */
9952 }
9953 else
9954 {
9955 /* Distribute the first term. */
9958 }
9968 }
9969 \f
9970 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9971 in MODE. Return an equivalent form, if different from (and VAROP
9972 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9974 static rtx
9977 {
9980 rtx orig_varop;
9988 /* Simplify VAROP knowing that we will be only looking at some of the
9989 bits in it.
9991 Note by passing in CONSTOP, we guarantee that the bits not set in
9992 CONSTOP are not significant and will never be examined. We must
9993 ensure that is the case by explicitly masking out those bits
9994 before returning. */
9997 /* If VAROP is a CLOBBER, we will fail so return it. */
10001 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10002 to VAROP and return the new constant. */
10006 /* See what bits may be nonzero in VAROP. Unlike the general case of
10007 a call to nonzero_bits, here we don't care about bits outside
10008 MODE. */
10012 /* Turn off all bits in the constant that are known to already be zero.
10013 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10014 which is tested below. */
10018 /* If we don't have any bits left, return zero. */
10022 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10023 a power of two, we can replace this with an ASHIFT. */
10028 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10029 or XOR, then try to apply the distributive law. This may eliminate
10030 operations if either branch can be simplified because of the AND.
10031 It may also make some cases more complex, but those cases probably
10032 won't match a pattern either with or without this. */
10035 return
10036 gen_lowpart
10038 apply_distributive_law
10043 constop),
10047 constop))));
10049 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10050 the AND and see if one of the operands simplifies to zero. If so, we
10051 may eliminate it. */
10055 {
10064 }
10066 /* Make a SUBREG if necessary. If we can't make it, fail. */
10071 /* If we are only masking insignificant bits, return VAROP. */
10078 /* Otherwise, return an AND. */
10080 }
10083 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10084 in MODE.
10086 Return an equivalent form, if different from X. Otherwise, return X. If
10087 X is zero, we are to always construct the equivalent form. */
10089 static rtx
10092 {
10103 }
10104 \f
10105 /* Given a REG, X, compute which bits in X can be nonzero.
10106 We don't care about bits outside of those defined in MODE.
10108 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10109 a shift, AND, or zero_extract, we can do better. */
10111 static rtx
10113 const_rtx known_x ATTRIBUTE_UNUSED,
10114 machine_mode known_mode ATTRIBUTE_UNUSED,
10117 {
10118 rtx tem;
10121 /* If X is a register whose nonzero bits value is current, use it.
10122 Otherwise, if X is a register whose value we can find, use that
10123 value. Otherwise, use the previously-computed global nonzero bits
10124 for this register. */
10138 && !REGNO_REG_SET_P
10141 {
10142 /* Note that, even if the precision of last_set_mode is lower than that
10143 of mode, record_value_for_reg invoked nonzero_bits on the register
10144 with nonzero_bits_mode (because last_set_mode is necessarily integral
10145 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10146 are all valid, hence in mode too since nonzero_bits_mode is defined
10147 to the largest HWI_COMPUTABLE_MODE_P mode. */
10150 }
10154 {
10160 }
10163 {
10167 /* We don't know anything about the upper bits. */
10171 }
10174 }
10176 /* Return the number of bits at the high-order end of X that are known to
10177 be equal to the sign bit. X will be used in mode MODE; if MODE is
10178 VOIDmode, X will be used in its own mode. The returned value will always
10179 be between 1 and the number of bits in MODE. */
10181 static rtx
10183 const_rtx known_x ATTRIBUTE_UNUSED,
10184 machine_mode known_mode
10185 ATTRIBUTE_UNUSED,
10188 {
10189 rtx tem;
10202 && !REGNO_REG_SET_P
10205 {
10208 }
10219 }
10220 \f
10221 /* Return the number of "extended" bits there are in X, when interpreted
10222 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10223 unsigned quantities, this is the number of high-order zero bits.
10224 For signed quantities, this is the number of copies of the sign bit
10225 minus 1. In both case, this function returns the number of "spare"
10226 bits. For example, if two quantities for which this function returns
10227 at least 1 are added, the addition is known not to overflow.
10229 This function will always return 0 unless called during combine, which
10230 implies that it must be called from a define_split. */
10232 unsigned int
10234 {
10244 }
10246 /* This function is called from `simplify_shift_const' to merge two
10247 outer operations. Specifically, we have already found that we need
10248 to perform operation *POP0 with constant *PCONST0 at the outermost
10249 position. We would now like to also perform OP1 with constant CONST1
10250 (with *POP0 being done last).
10252 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10253 the resulting operation. *PCOMP_P is set to 1 if we would need to
10254 complement the innermost operand, otherwise it is unchanged.
10256 MODE is the mode in which the operation will be done. No bits outside
10257 the width of this mode matter. It is assumed that the width of this mode
10258 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10260 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10261 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10262 result is simply *PCONST0.
10264 If the resulting operation cannot be expressed as one operation, we
10265 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10267 static int
10268 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10269 {
10276 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10280 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10281 if OP0 is SET. */
10290 {
10292 {
10310 }
10311 }
10313 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10317 /* If the two constants aren't the same, we can't do anything. The
10318 remaining six cases can all be done. */
10322 else
10324 {
10327 /* (a & b) | b == b */
10330 /* (a ^ b) | b == a | b */
10331 {;}
10336 /* (a & b) ^ b == (~a) & b */
10339 /* (a | b) ^ b == a & ~b */
10345 /* (a | b) & b == b */
10348 /* (a ^ b) & b) == (~a) & b */
10353 }
10355 /* Check for NO-OP cases. */
10368 /* ??? Slightly redundant with the above mask, but not entirely.
10369 Moving this above means we'd have to sign-extend the mode mask
10370 for the final test. */
10375 }
10376 \f
10377 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10378 the shift in. The original shift operation CODE is performed on OP in
10379 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10380 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10381 result of the shift is subject to operation OUTER_CODE with operand
10382 OUTER_CONST. */
10384 static machine_mode
10388 {
10393 /* In general we can't perform in wider mode for right shift and rotate. */
10395 {
10397 /* We can still widen if the bits brought in from the left are identical
10398 to the sign bit of ORIG_MODE. */
10406 /* Similarly here but with zero bits. */
10411 /* We can also widen if the bits brought in will be masked off. This
10412 operation is performed in ORIG_MODE. */
10414 {
10420 }
10421 /* fall through */
10431 }
10432 }
10434 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10435 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10436 if we cannot simplify it. Otherwise, return a simplified value.
10438 The shift is normally computed in the widest mode we find in VAROP, as
10439 long as it isn't a different number of words than RESULT_MODE. Exceptions
10440 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10442 static rtx
10445 {
10451 unsigned int mode_words
10453 /* We form (outer_op (code varop count) (outer_const)). */
10459 /* Make sure and truncate the "natural" shift on the way in. We don't
10460 want to do this inside the loop as it makes it more difficult to
10461 combine shifts. */
10465 /* If we were given an invalid count, don't do anything except exactly
10466 what was requested. */
10473 /* Unless one of the branches of the `if' in this loop does a `continue',
10474 we will `break' the loop after the `if'. */
10477 {
10478 /* If we have an operand of (clobber (const_int 0)), fail. */
10482 /* Convert ROTATERT to ROTATE. */
10484 {
10488 }
10494 /* Handle cases where the count is greater than the size of the mode
10495 minus 1. For ASHIFT, use the size minus one as the count (this can
10496 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10497 take the count modulo the size. For other shifts, the result is
10498 zero.
10500 Since these shifts are being produced by the compiler by combining
10501 multiple operations, each of which are defined, we know what the
10502 result is supposed to be. */
10505 {
10510 else
10511 {
10512 /* We can't simply return zero because there may be an
10513 outer op. */
10517 }
10518 }
10520 /* If we discovered we had to complement VAROP, leave. Making a NOT
10521 here would cause an infinite loop. */
10526 {
10527 /* An arithmetic right shift of a quantity known to be -1 or 0
10528 is a no-op. */
10532 {
10535 }
10537 /* If we are doing an arithmetic right shift and discarding all but
10538 the sign bit copies, this is equivalent to doing a shift by the
10539 bitsize minus one. Convert it into that shift because it will
10540 often allow other simplifications. */
10547 /* We simplify the tests below and elsewhere by converting
10548 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10549 `make_compound_operation' will convert it to an ASHIFTRT for
10550 those machines (such as VAX) that don't have an LSHIFTRT. */
10555 shift_unit_mode)))
10567 }
10570 {
10577 {
10580 }
10584 /* The following rules apply only to scalars. */
10588 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10589 minus the width of a smaller mode, we can do this with a
10590 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10597 {
10606 }
10610 /* The following rules apply only to scalars. */
10614 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10615 the same number of words as what we've seen so far. Then store
10616 the widest mode in MODE. */
10622 == mode_words
10625 {
10630 }
10634 /* Some machines use MULT instead of ASHIFT because MULT
10635 is cheaper. But it is still better on those machines to
10636 merge two shifts into one. */
10639 {
10640 varop
10646 }
10650 /* Similar, for when divides are cheaper. */
10653 {
10654 varop
10660 }
10664 /* If we are extracting just the sign bit of an arithmetic
10665 right shift, that shift is not needed. However, the sign
10666 bit of a wider mode may be different from what would be
10667 interpreted as the sign bit in a narrower mode, so, if
10668 the result is narrower, don't discard the shift. */
10673 {
10676 }
10678 /* fall through */
10683 /* The following rules apply only to scalars. */
10687 /* Here we have two nested shifts. The result is usually the
10688 AND of a new shift with a mask. We compute the result below. */
10694 {
10698 rtx mask_rtx;
10700 /* We have one common special case. We can't do any merging if
10701 the inner code is an ASHIFTRT of a smaller mode. However, if
10702 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10703 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10704 we can convert it to
10705 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10706 This simplifies certain SIGN_EXTEND operations. */
10710 {
10711 /* C3 has the low-order C1 bits zero. */
10723 }
10725 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10726 than C1 high-order bits equal to the sign bit, we can convert
10727 this to either an ASHIFT or an ASHIFTRT depending on the
10728 two counts.
10730 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10736 {
10740 {
10743 }
10746 }
10748 /* There are some cases we can't do. If CODE is ASHIFTRT,
10749 we can only do this if FIRST_CODE is also ASHIFTRT.
10751 We can't do the case when CODE is ROTATE and FIRST_CODE is
10752 ASHIFTRT.
10754 If the mode of this shift is not the mode of the outer shift,
10755 we can't do this if either shift is a right shift or ROTATE.
10757 Finally, we can't do any of these if the mode is too wide
10758 unless the codes are the same.
10760 Handle the case where the shift codes are the same
10761 first. */
10764 {
10773 }
10784 /* To compute the mask to apply after the shift, shift the
10785 nonzero bits of the inner shift the same way the
10786 outer shift will. */
10789 result_mode);
10791 mask_rtx
10795 /* Give up if we can't compute an outer operation to use. */
10803 /* If the shifts are in the same direction, we add the
10804 counts. Otherwise, we subtract them. */
10808 else
10811 /* If COUNT is positive, the new shift is usually CODE,
10812 except for the two exceptions below, in which case it is
10813 FIRST_CODE. If the count is negative, FIRST_CODE should
10814 always be used */
10824 }
10826 /* If we have (A << B << C) for any shift, we can convert this to
10827 (A << C << B). This wins if A is a constant. Only try this if
10828 B is not a constant. */
10833 {
10834 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10835 sure the result will be masked. See PR70222. */
10843 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10844 up outer sign extension (often left and right shift) is
10845 hardly more efficient than the original. See PR70429. */
10855 }
10859 /* The following rules apply only to scalars. */
10863 /* Make this fit the case below. */
10870 /* The following rules apply only to scalars. */
10874 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10875 with C the size of VAROP - 1 and the shift is logical if
10876 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10877 we have an (le X 0) operation. If we have an arithmetic shift
10878 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10879 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10887 {
10890 const0_rtx);
10896 }
10898 /* If we have (shift (logical)), move the logical to the outside
10899 to allow it to possibly combine with another logical and the
10900 shift to combine with another shift. This also canonicalizes to
10901 what a ZERO_EXTRACT looks like. Also, some machines have
10902 (and (shift)) insns. */
10905 /* We can't do this if we have (ashiftrt (xor)) and the
10906 constant has its sign bit set in shift_mode with shift_mode
10907 wider than result_mode. */
10911 shift_mode))
10919 {
10922 }
10924 /* If we can't do that, try to simplify the shift in each arm of the
10925 logical expression, make a new logical expression, and apply
10926 the inverse distributive law. This also can't be done for
10927 (ashiftrt (xor)) where we've widened the shift and the constant
10928 changes the sign bit. */
10933 shift_mode)))
10934 {
10946 }
10950 /* The following rules apply only to scalars. */
10954 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10955 says that the sign bit can be tested, FOO has mode MODE, C is
10956 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10957 that may be nonzero. */
10967 {
10971 }
10975 /* The following rules apply only to scalars. */
10979 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10980 than the number of bits in the mode is equivalent to A. */
10984 {
10988 }
10990 /* NEG commutes with ASHIFT since it is multiplication. Move the
10991 NEG outside to allow shifts to combine. */
10995 {
10998 }
11002 /* The following rules apply only to scalars. */
11006 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11007 is one less than the number of bits in the mode is
11008 equivalent to (xor A 1). */
11015 {
11019 }
11021 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11022 that might be nonzero in BAR are those being shifted out and those
11023 bits are known zero in FOO, we can replace the PLUS with FOO.
11024 Similarly in the other operand order. This code occurs when
11025 we are computing the size of a variable-size array. */
11032 {
11035 }
11043 result_mode)))
11044 {
11047 }
11049 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11059 {
11062 }
11064 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11065 signbit', and attempt to change the PLUS to an XOR and move it to
11066 the outer operation as is done above in the AND/IOR/XOR case
11067 leg for shift(logical). See details in logical handling above
11068 for reasoning in doing so. */
11079 {
11082 }
11087 /* The following rules apply only to scalars. */
11091 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11092 with C the size of VAROP - 1 and the shift is logical if
11093 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11094 we have a (gt X 0) operation. If the shift is arithmetic with
11095 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11096 we have a (neg (gt X 0)) operation. */
11105 {
11108 const0_rtx);
11114 }
11118 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11119 if the truncate does not affect the value. */
11126 {
11129 varop_inner
11132 GEN_INT
11137 }
11142 }
11145 }
11150 /* We have now finished analyzing the shift. The result should be
11151 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11152 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11153 to the result of the shift. OUTER_CONST is the relevant constant,
11154 but we must turn off all bits turned off in the shift. */
11162 /* Make a SUBREG if necessary. If we can't make it, fail. */
11167 /* If we have an outer operation and we just made a shift, it is
11168 possible that we could have simplified the shift were it not
11169 for the outer operation. So try to do the simplification
11170 recursively. */
11174 else
11180 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11181 turn off all the bits that the shift would have turned off. */
11186 /* Do the remainder of the processing in RESULT_MODE. */
11189 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11190 operation. */
11195 {
11203 {
11204 /* This means that we have determined that the result is
11205 equivalent to a constant. This should be rare. */
11208 }
11211 else
11214 }
11217 }
11219 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11220 The result of the shift is RESULT_MODE. If we cannot simplify it,
11221 return X or, if it is NULL, synthesize the expression with
11222 simplify_gen_binary. Otherwise, return a simplified value.
11224 The shift is normally computed in the widest mode we find in VAROP, as
11225 long as it isn't a different number of words than RESULT_MODE. Exceptions
11226 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11228 static rtx
11231 {
11241 }
11243 \f
11244 /* A subroutine of recog_for_combine. See there for arguments and
11245 return value. */
11247 static int
11249 {
11251 rtx pat_without_clobbers;
11259 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11260 we use to indicate that something didn't match. If we find such a
11261 thing, force rejection. */
11275 {
11278 else
11281 }
11283 /* If it isn't, there is the possibility that we previously had an insn
11284 that clobbered some register as a side effect, but the combined
11285 insn doesn't need to do that. So try once more without the clobbers
11286 unless this represents an ASM insn. */
11290 {
11295 {
11298 pos++;
11299 }
11309 {
11312 else
11315 }
11316 }
11323 /* Recognize all noop sets, these will be killed by followup pass. */
11327 /* If we had any clobbers to add, make a new pattern than contains
11328 them. Then check to make sure that all of them are dead. */
11330 {
11340 else
11347 {
11352 {
11356 }
11357 }
11359 }
11363 {
11371 /* Allow targets to reject combined insn. */
11373 {
11376 dump_file);
11378 /* Callers expect recog_for_combine to strip
11379 clobbers from the pattern on failure. */
11384 }
11389 }
11395 }
11397 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11398 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11399 Return whether anything was so changed. */
11401 static bool
11403 {
11409 {
11420 {
11431 else
11435 }
11442 {
11447 }
11453 {
11456 }
11457 else
11463 {
11466 }
11470 }
11481 {
11496 else
11504 }
11507 }
11509 /* Like recog, but we receive the address of a pointer to a new pattern.
11510 We try to match the rtx that the pointer points to.
11511 If that fails, we may try to modify or replace the pattern,
11512 storing the replacement into the same pointer object.
11514 Modifications include deletion or addition of CLOBBERs. If the
11515 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11516 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11517 (and undo if that fails).
11519 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11520 the CLOBBERs are placed.
11522 The value is the final insn code from the pattern ultimately matched,
11523 or -1. */
11525 static int
11527 {
11539 {
11542 {
11546 }
11547 }
11550 {
11555 }
11558 }
11559 \f
11560 /* Like gen_lowpart_general but for use by combine. In combine it
11561 is not possible to create any new pseudoregs. However, it is
11562 safe to create invalid memory addresses, because combine will
11563 try to recognize them and all they will do is make the combine
11564 attempt fail.
11566 If for some reason this cannot do its job, an rtx
11567 (clobber (const_int 0)) is returned.
11568 An insn containing that will not be recognized. */
11570 static rtx
11572 {
11576 rtx result;
11581 /* We can only support MODE being wider than a word if X is a
11582 constant integer or has a mode the same size. */
11587 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11588 won't know what to do. So we will strip off the SUBREG here and
11589 process normally. */
11591 {
11594 /* For use in case we fall down into the address adjustments
11595 further below, we need to adjust the known mode and size of
11596 x; imode and isize, since we just adjusted x. */
11603 }
11611 {
11614 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11615 address. */
11620 /* If we want to refer to something bigger than the original memref,
11621 generate a paradoxical subreg instead. That will force a reload
11622 of the original memref X. */
11629 /* Adjust the address so that the address-after-the-data is
11630 unchanged. */
11635 }
11637 /* If X is a comparison operator, rewrite it in a new mode. This
11638 probably won't match, but may allow further simplifications. */
11642 /* If we couldn't simplify X any other way, just enclose it in a
11643 SUBREG. Normally, this SUBREG won't match, but some patterns may
11644 include an explicit SUBREG or we may simplify it further in combine. */
11645 else
11646 {
11647 rtx res;
11650 {
11655 }
11659 }
11661 fail:
11663 }
11664 \f
11665 /* Try to simplify a comparison between OP0 and a constant OP1,
11666 where CODE is the comparison code that will be tested, into a
11667 (CODE OP0 const0_rtx) form.
11669 The result is a possibly different comparison code to use.
11670 *POP1 may be updated. */
11672 static enum rtx_code
11675 {
11679 /* Get the constant we are comparing against and turn off all bits
11680 not on in our mode. */
11684 /* If we are comparing against a constant power of two and the value
11685 being compared can only have that single bit nonzero (e.g., it was
11686 `and'ed with that bit), we can replace this with a comparison
11687 with zero. */
11695 {
11698 }
11700 /* Similarly, if we are comparing a value known to be either -1 or
11701 0 with -1, change it to the opposite comparison against zero. */
11706 {
11709 }
11711 /* Do some canonicalizations based on the comparison code. We prefer
11712 comparisons against zero and then prefer equality comparisons.
11713 If we can reduce the size of a constant, we will do that too. */
11715 {
11717 /* < C is equivalent to <= (C - 1) */
11719 {
11722 /* ... fall through to LE case below. */
11724 }
11725 else
11729 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11731 {
11734 }
11736 /* If we are doing a <= 0 comparison on a value known to have
11737 a zero sign bit, we can replace this with == 0. */
11747 /* >= C is equivalent to > (C - 1). */
11749 {
11752 /* ... fall through to GT below. */
11754 }
11755 else
11759 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11761 {
11764 }
11766 /* If we are doing a > 0 comparison on a value known to have
11767 a zero sign bit, we can replace this with != 0. */
11777 /* < C is equivalent to <= (C - 1). */
11779 {
11782 /* ... fall through ... */
11783 }
11784 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11788 {
11792 }
11793 else
11797 /* unsigned <= 0 is equivalent to == 0 */
11800 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11804 {
11807 }
11811 /* >= C is equivalent to > (C - 1). */
11813 {
11816 /* ... fall through ... */
11817 }
11819 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11823 {
11827 }
11828 else
11832 /* unsigned > 0 is equivalent to != 0 */
11835 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11839 {
11842 }
11847 }
11851 }
11852 \f
11853 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11854 comparison code that will be tested.
11856 The result is a possibly different comparison code to use. *POP0 and
11857 *POP1 may be updated.
11859 It is possible that we might detect that a comparison is either always
11860 true or always false. However, we do not perform general constant
11861 folding in combine, so this knowledge isn't useful. Such tautologies
11862 should have been detected earlier. Hence we ignore all such cases. */
11864 static enum rtx_code
11866 {
11873 /* Try a few ways of applying the same transformation to both operands. */
11875 {
11876 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11877 so check specially. */
11893 - (GET_MODE_PRECISION
11895 {
11898 }
11900 /* If both operands are the same constant shift, see if we can ignore the
11901 shift. We can if the shift is a rotate or if the bits shifted out of
11902 this shift are known to be zero for both inputs and if the type of
11903 comparison is compatible with the shift. */
11916 {
11929 else
11931 }
11933 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11934 SUBREGs are of the same mode, and, in both cases, the AND would
11935 be redundant if the comparison was done in the narrower mode,
11936 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11937 and the operand's possibly nonzero bits are 0xffffff01; in that case
11938 if we only care about QImode, we don't need the AND). This case
11939 occurs if the output mode of an scc insn is not SImode and
11940 STORE_FLAG_VALUE == 1 (e.g., the 386).
11942 Similarly, check for a case where the AND's are ZERO_EXTEND
11943 operations from some narrower mode even though a SUBREG is not
11944 present. */
11949 {
11966 {
11970 /* The resulting comparison is always unsigned since we masked
11971 off the original sign bit. */
11975 }
11982 {
11988 }
11992 }
11994 /* If both operands are NOT, we can strip off the outer operation
11995 and adjust the comparison code for swapped operands; similarly for
11996 NEG, except that this must be an equality comparison. */
12002 else
12004 }
12006 /* If the first operand is a constant, swap the operands and adjust the
12007 comparison code appropriately, but don't do this if the second operand
12008 is already a constant integer. */
12010 {
12013 }
12015 /* We now enter a loop during which we will try to simplify the comparison.
12016 For the most part, we only are concerned with comparisons with zero,
12017 but some things may really be comparisons with zero but not start
12018 out looking that way. */
12021 {
12028 HOST_WIDE_INT const_op;
12030 /* We only want to handle integral modes. This catches VOIDmode,
12031 CCmode, and the floating-point modes. An exception is that we
12032 can handle VOIDmode if OP0 is a COMPARE or a comparison
12033 operation. */
12040 /* Try to simplify the compare to constant, possibly changing the
12041 comparison op, and/or changing op1 to zero. */
12045 /* Compute some predicates to simplify code below. */
12052 /* If this is a sign bit comparison and we can do arithmetic in
12053 MODE, say that we will only be needing the sign bit of OP0. */
12056 HOST_WIDE_INT_1U
12060 /* Now try cases based on the opcode of OP0. If none of the cases
12061 does a "continue", we exit this loop immediately after the
12062 switch. */
12065 {
12067 /* If we are extracting a single bit from a variable position in
12068 a constant that has only a single bit set and are comparing it
12069 with zero, we can convert this into an equality comparison
12070 between the position and the location of the single bit. */
12071 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12072 have already reduced the shift count modulo the word size. */
12078 {
12086 /* Result is nonzero iff shift count is equal to I. */
12089 }
12091 /* fall through */
12096 {
12099 }
12103 /* If testing for equality, we can take the NOT of the constant. */
12106 {
12110 }
12112 /* If just looking at the sign bit, reverse the sense of the
12113 comparison. */
12115 {
12119 }
12123 /* If testing for equality, we can take the NEG of the constant. */
12126 {
12130 }
12132 /* The remaining cases only apply to comparisons with zero. */
12136 /* When X is ABS or is known positive,
12137 (neg X) is < 0 if and only if X != 0. */
12145 {
12149 }
12151 /* If we have NEG of something whose two high-order bits are the
12152 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12154 {
12158 }
12162 /* If we are testing equality and our count is a constant, we
12163 can perform the inverse operation on our RHS. */
12167 {
12171 }
12173 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12174 a particular bit. Convert it to an AND of a constant of that
12175 bit. This will be converted into a ZERO_EXTRACT. */
12179 {
12181 (HOST_WIDE_INT_1U
12186 }
12188 /* Fall through. */
12191 /* ABS is ignorable inside an equality comparison with zero. */
12193 {
12196 }
12200 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12201 (compare FOO CONST) if CONST fits in FOO's mode and we
12202 are either testing inequality or have an unsigned
12203 comparison with ZERO_EXTEND or a signed comparison with
12204 SIGN_EXTEND. But don't do it if we don't have a compare
12205 insn of the given mode, since we'd have to revert it
12206 later on, and then we wouldn't know whether to sign- or
12207 zero-extend. */
12210 && ! unsigned_comparison_p
12214 {
12217 }
12221 /* Check for the case where we are comparing A - C1 with C2, that is
12223 (subreg:MODE (plus (A) (-C1))) op (C2)
12225 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12226 comparison in the wider mode. One of the following two conditions
12227 must be true in order for this to be valid:
12229 1. The mode extension results in the same bit pattern being added
12230 on both sides and the comparison is equality or unsigned. As
12231 C2 has been truncated to fit in MODE, the pattern can only be
12232 all 0s or all 1s.
12234 2. The mode extension results in the sign bit being copied on
12235 each side.
12237 The difficulty here is that we have predicates for A but not for
12238 (A - C1) so we need to check that C1 is within proper bounds so
12239 as to perturbate A as little as possible. */
12246 {
12255 /* (A - C1) zero-extends if it is positive and sign-extends
12256 if it is negative, C2 both zero- and sign-extends. */
12260 /* (A - C1) sign-extends if it is positive and 1-extends
12261 if it is negative, C2 both sign- and 1-extends. */
12268 /* (A - C1) always sign-extends, like C2. */
12272 {
12275 }
12276 }
12278 /* If the inner mode is narrower and we are extracting the low part,
12279 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12282 ;
12293 {
12294 /* Remove outer subregs that don't do anything. */
12299 {
12303 }
12305 }
12306 else
12309 /* FALLTHROUGH */
12319 {
12322 }
12326 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12327 this for equality comparisons due to pathological cases involving
12328 overflows. */
12332 {
12336 }
12338 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12341 {
12345 }
12349 /* We used to optimize signed comparisons against zero, but that
12350 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12351 arrive here as equality comparisons, or (GEU, LTU) are
12352 optimized away. No need to special-case them. */
12354 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12355 (eq B (minus A C)), whichever simplifies. We can only do
12356 this for equality comparisons due to pathological cases involving
12357 overflows. */
12361 {
12365 }
12370 {
12374 }
12376 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12377 of bits in X minus 1, is one iff X > 0. */
12382 {
12386 }
12390 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12391 if C is zero or B is a constant. */
12395 {
12399 }
12407 /* We can't do anything if OP0 is a condition code value, rather
12408 than an actual data value. */
12414 /* Get the two operands being compared. */
12417 else
12420 /* Check for the cases where we simply want the result of the
12421 earlier test or the opposite of that result. */
12425 {
12429 else
12433 {
12438 }
12439 }
12443 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12444 iff X <= 0. */
12448 {
12452 }
12456 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12457 will be converted to a ZERO_EXTRACT later. */
12461 {
12466 }
12468 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12469 zero and X is a comparison and C1 and C2 describe only bits set
12470 in STORE_FLAG_VALUE, we can compare with X. */
12478 {
12485 {
12488 }
12489 }
12491 /* If we are doing an equality comparison of an AND of a bit equal
12492 to the sign bit, replace this with a LT or GE comparison of
12493 the underlying value. */
12500 {
12504 }
12506 /* If this AND operation is really a ZERO_EXTEND from a narrower
12507 mode, the constant fits within that mode, and this is either an
12508 equality or unsigned comparison, try to do this comparison in
12509 the narrower mode.
12511 Note that in:
12513 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12514 -> (ne:DI (reg:SI 4) (const_int 0))
12516 unless TRULY_NOOP_TRUNCATION allows it or the register is
12517 known to hold a value of the required mode the
12518 transformation is invalid. */
12526 {
12529 }
12531 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12532 fits in both M1 and M2 and the SUBREG is either paradoxical
12533 or represents the low part, permute the SUBREG and the AND
12534 and try again. */
12537 {
12540 /* Require an integral mode, to avoid creating something like
12541 (AND:SF ...). */
12543 /* It is unsafe to commute the AND into the SUBREG if the
12544 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12545 not defined. As originally written the upper bits
12546 have a defined value due to the AND operation.
12547 However, if we commute the AND inside the SUBREG then
12548 they no longer have defined values and the meaning of
12549 the code has been changed.
12550 Also C1 should not change value in the smaller mode,
12551 see PR67028 (a positive C1 can become negative in the
12552 smaller mode, so that the AND does no longer mask the
12553 upper bits). */
12554 && ((WORD_REGISTER_OPERATIONS
12566 {
12572 }
12573 }
12575 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12579 {
12584 }
12586 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12587 (eq (and (lshiftrt X) 1) 0).
12588 Also handle the case where (not X) is expressed using xor. */
12592 {
12602 == HOST_WIDE_INT_1U
12604 {
12605 op0
12610 }
12611 }
12615 /* If we have (compare (ashift FOO N) (const_int C)) and
12616 the high order N bits of FOO (N+1 if an inequality comparison)
12617 are known to be zero, we can do this by comparing FOO with C
12618 shifted right N bits so long as the low-order N bits of C are
12619 zero. */
12631 {
12632 /* We must perform a logical shift, not an arithmetic one,
12633 as we want the top N bits of C to be zero. */
12640 }
12642 /* If we are doing a sign bit comparison, it means we are testing
12643 a particular bit. Convert it to the appropriate AND. */
12646 {
12648 (HOST_WIDE_INT_1U
12653 }
12655 /* If this an equality comparison with zero and we are shifting
12656 the low bit to the sign bit, we can convert this to an AND of the
12657 low-order bit. */
12661 {
12664 }
12668 /* If this is an equality comparison with zero, we can do this
12669 as a logical shift, which might be much simpler. */
12672 {
12677 }
12679 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12680 do the comparison in a narrower mode. */
12690 {
12693 }
12695 /* Likewise if OP0 is a PLUS of a sign extension with a
12696 constant, which is usually represented with the PLUS
12697 between the shifts. */
12709 {
12717 new_const);
12719 }
12721 /* FALLTHROUGH */
12723 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12724 the low order N bits of FOO are known to be zero, we can do this
12725 by comparing FOO with C shifted left N bits so long as no
12726 overflow occurs. Even if the low order N bits of FOO aren't known
12727 to be zero, if the comparison is >= or < we can use the same
12728 optimization and for > or <= by setting all the low
12729 order N bits in the comparison constant. */
12740 {
12741 unsigned HOST_WIDE_INT low_bits
12743 & ((HOST_WIDE_INT_1U
12746 {
12747 /* If the shift was logical, then we must make the condition
12748 unsigned. */
12757 const_op
12762 }
12763 }
12765 /* If we are using this shift to extract just the sign bit, we
12766 can replace this with an LT or GE comparison. */
12771 {
12775 }
12780 }
12783 }
12785 /* Now make any compound operations involved in this comparison. Then,
12786 check for an outmost SUBREG on OP0 that is not doing anything or is
12787 paradoxical. The latter transformation must only be performed when
12788 it is known that the "extra" bits will be the same in op0 and op1 or
12789 that they don't matter. There are three cases to consider:
12791 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12792 care bits and we can assume they have any convenient value. So
12793 making the transformation is safe.
12795 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12796 In this case the upper bits of op0 are undefined. We should not make
12797 the simplification in that case as we do not know the contents of
12798 those bits.
12800 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12801 In that case we know those bits are zeros or ones. We must also be
12802 sure that they are the same as the upper bits of op1.
12804 We can never remove a SUBREG for a non-equality comparison because
12805 the sign bit is in a different place in the underlying object. */
12818 {
12820 {
12821 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12822 implemented. */
12824 {
12827 }
12828 }
12834 {
12840 }
12841 }
12843 /* We now do the opposite procedure: Some machines don't have compare
12844 insns in all modes. If OP0's mode is an integer mode smaller than a
12845 word and we can't do a compare in that mode, see if there is a larger
12846 mode for which we can do the compare. There are a number of cases in
12847 which we can use the wider mode. */
12857 {
12860 /* If this is a test for negative, we can make an explicit
12861 test of the sign bit. Test this first so we can use
12862 a paradoxical subreg to extend OP0. */
12866 {
12867 unsigned HOST_WIDE_INT sign
12874 }
12876 /* If the only nonzero bits in OP0 and OP1 are those in the
12877 narrower mode and this is an equality or unsigned comparison,
12878 we can use the wider mode. Similarly for sign-extended
12879 values, in which case it is true for all comparisons. */
12896 {
12897 /* If OP0 is an AND and we don't have an AND in MODE either,
12898 make a new AND in the proper mode. */
12906 else
12907 {
12909 {
12912 }
12913 else
12914 {
12917 }
12919 }
12920 }
12921 }
12923 /* We may have changed the comparison operands. Re-canonicalize. */
12925 {
12928 }
12930 /* If this machine only supports a subset of valid comparisons, see if we
12931 can convert an unsupported one into a supported one. */
12938 }
12939 \f
12940 /* Utility function for record_value_for_reg. Count number of
12941 rtxs in X. */
12942 static int
12944 {
12951 {
12971 }
12982 }
12983 \f
12984 /* Utility function for following routine. Called when X is part of a value
12985 being stored into last_set_value. Sets last_set_table_tick
12986 for each register mentioned. Similar to mention_regs in cse.c */
12988 static void
12990 {
12996 {
13002 {
13005 }
13008 }
13012 {
13013 /* Check for identical subexpressions. If x contains
13014 identical subexpression we only have to traverse one of
13015 them. */
13017 {
13018 /* Note that at this point x1 has already been
13019 processed. */
13023 /* If x0 and x1 are identical then there is no need to
13024 process x0. */
13028 /* If x0 is identical to a subexpression of x1 then while
13029 processing x1, x0 has already been processed. Thus we
13030 are done with x. */
13035 /* If x1 is identical to a subexpression of x0 then we
13036 still have to process the rest of x0. */
13039 {
13042 }
13043 }
13046 }
13050 }
13052 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13053 are saying that the register is clobbered and we no longer know its
13054 value. If INSN is zero, don't update reg_stat[].last_set; this is
13055 only permitted with VALUE also zero and is used to invalidate the
13056 register. */
13058 static void
13060 {
13066 /* If VALUE contains REG and we have a previous value for REG, substitute
13067 the previous value. */
13069 {
13070 rtx tem;
13072 /* Set things up so get_last_value is allowed to see anything set up to
13073 our insn. */
13077 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13078 it isn't going to be useful and will take a lot of time to process,
13079 so just use the CLOBBER. */
13082 {
13088 {
13089 /* If there are two or more occurrences of REG in VALUE,
13090 prevent the value from growing too much. */
13093 }
13096 }
13097 }
13099 /* For each register modified, show we don't know its value, that
13100 we don't know about its bitwise content, that its value has been
13101 updated, and that we don't know the location of the death of the
13102 register. */
13104 {
13116 }
13118 /* Mark registers that are being referenced in this value. */
13122 /* Now update the status of each register being set.
13123 If someone is using this register in this block, set this register
13124 to invalid since we will get confused between the two lives in this
13125 basic block. This makes using this register always invalid. In cse, we
13126 scan the table to invalidate all entries using this register, but this
13127 is too much work for us. */
13130 {
13136 else
13138 }
13140 /* The value being assigned might refer to X (like in "x++;"). In that
13141 case, we must replace it with (clobber (const_int 0)) to prevent
13142 infinite loops. */
13145 {
13149 }
13151 /* For the main register being modified, update the value, the mode, the
13152 nonzero bits, and the number of sign bit copies. */
13157 {
13165 rsp->last_set_sign_bit_copies
13167 }
13168 }
13170 /* Called via note_stores from record_dead_and_set_regs to handle one
13171 SET or CLOBBER in an insn. DATA is the instruction in which the
13172 set is occurring. */
13174 static void
13176 {
13183 {
13187 }
13190 {
13191 /* If we are setting the whole register, we know its value. Otherwise
13192 show that we don't know the value. We can handle SUBREG in
13193 some cases. */
13204 else
13206 }
13208 /* Ignore pushes, they clobber nothing. */
13211 }
13213 /* Update the records of when each REG was most recently set or killed
13214 for the things done by INSN. This is the last thing done in processing
13215 INSN in the combiner loop.
13217 We update reg_stat[], in particular fields last_set, last_set_value,
13218 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13219 last_death, and also the similar information mem_last_set (which insn
13220 most recently modified memory) and last_call_luid (which insn was the
13221 most recent subroutine call). */
13223 static void
13225 {
13226 rtx link;
13230 {
13233 {
13238 {
13243 }
13244 }
13247 }
13250 {
13251 hard_reg_set_iterator hrsi;
13253 {
13265 }
13269 /* We can't combine into a call pattern. Remember, though, that
13270 the return value register is set at this LUID. We could
13271 still replace a register with the return value from the
13272 wrong subroutine call! */
13274 }
13275 else
13277 }
13279 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13280 register present in the SUBREG, so for each such SUBREG go back and
13281 adjust nonzero and sign bit information of the registers that are
13282 known to have some zero/sign bits set.
13284 This is needed because when combine blows the SUBREGs away, the
13285 information on zero/sign bits is lost and further combines can be
13286 missed because of that. */
13288 static void
13290 {
13292 rtx set;
13300 {
13309 {
13312 }
13316 {
13319 }
13322 {
13325 }
13326 else
13328 }
13329 }
13331 /* Check if X, a register, is known to contain a value already
13332 truncated to MODE. In this case we can use a subreg to refer to
13333 the truncated value even though in the generic case we would need
13334 an explicit truncation. */
13336 static bool
13338 {
13350 }
13352 /* If X is a hard reg or a subreg record the mode that the register is
13353 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13354 to turn a truncate into a subreg using this information. Return true
13355 if traversing X is complete. */
13357 static bool
13359 {
13360 machine_mode truncated_mode;
13364 {
13375 }
13376 /* ??? For hard-regs we now record everything. We might be able to
13377 optimize this using last_set_mode. */
13380 else
13388 {
13391 }
13394 }
13396 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13397 the modes they are used in. This can help truning TRUNCATEs into
13398 SUBREGs. */
13400 static void
13402 {
13407 }
13409 /* Scan X for promoted SUBREGs. For each one found,
13410 note what it implies to the registers used in it. */
13412 static void
13414 {
13419 else
13420 {
13426 {
13436 }
13437 }
13438 }
13439 \f
13440 /* Verify that all the registers and memory references mentioned in *LOC are
13441 still valid. *LOC was part of a value set in INSN when label_tick was
13442 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13443 the invalid references with (clobber (const_int 0)) and return 1. This
13444 replacement is useful because we often can get useful information about
13445 the form of a value (e.g., if it was produced by a shift that always
13446 produces -1 or 0) even though we don't know exactly what registers it
13447 was produced from. */
13449 static int
13451 {
13458 {
13464 {
13467 /* If this is a pseudo-register that was only set once and not
13468 live at the beginning of the function, it is always valid. */
13472 && (!REGNO_REG_SET_P
13474 regno)))
13476 {
13480 }
13481 }
13484 }
13485 /* If this is a memory reference, make sure that there were no stores after
13486 it that might have clobbered the value. We don't have alias info, so we
13487 assume any store invalidates it. Moreover, we only have local UIDs, so
13488 we also assume that there were stores in the intervening basic blocks. */
13491 {
13495 }
13498 {
13500 {
13501 /* Check for identical subexpressions. If x contains
13502 identical subexpression we only have to traverse one of
13503 them. */
13505 {
13506 /* Note that at this point x0 has already been checked
13507 and found valid. */
13511 /* If x0 and x1 are identical then x is also valid. */
13515 /* If x1 is identical to a subexpression of x0 then
13516 while checking x0, x1 has already been checked. Thus
13517 it is valid and so as x. */
13522 /* If x0 is identical to a subexpression of x1 then x is
13523 valid iff the rest of x1 is valid. */
13526 return
13530 }
13535 }
13541 }
13543 /* If we haven't found a reason for it to be invalid, it is valid. */
13545 }
13547 /* Get the last value assigned to X, if known. Some registers
13548 in the value may be replaced with (clobber (const_int 0)) if their value
13549 is known longer known reliably. */
13551 static rtx
13553 {
13555 rtx value;
13558 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13559 then convert it to the desired mode. If this is a paradoxical SUBREG,
13560 we cannot predict what values the "extra" bits might have. */
13574 /* If we don't have a value, or if it isn't for this basic block and
13575 it's either a hard register, set more than once, or it's a live
13576 at the beginning of the function, return 0.
13578 Because if it's not live at the beginning of the function then the reg
13579 is always set before being used (is never used without being set).
13580 And, if it's set only once, and it's always set before use, then all
13581 uses must have the same last value, even if it's not from this basic
13582 block. */
13589 || REGNO_REG_SET_P
13593 /* If the value was set in a later insn than the ones we are processing,
13594 we can't use it even if the register was only set once. */
13599 /* If fewer bits were set than what we are asked for now, we cannot use
13600 the value. */
13605 /* If the value has all its registers valid, return it. */
13609 /* Otherwise, make a copy and replace any invalid register with
13610 (clobber (const_int 0)). If that fails for some reason, return 0. */
13617 }
13618 \f
13619 /* Return nonzero if expression X refers to a REG or to memory
13620 that is set in an instruction more recent than FROM_LUID. */
13622 static int
13624 {
13630 {
13634 #ifdef PUSH_ROUNDING
13635 /* Don't allow uses of the stack pointer to be moved,
13636 because we don't know whether the move crosses a push insn. */
13639 #endif
13641 {
13647 }
13649 }
13657 {
13659 {
13664 }
13668 }
13670 }
13671 \f
13672 /* Define three variables used for communication between the following
13673 routines. */
13678 /* Function called via note_stores from reg_dead_at_p.
13680 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13681 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13683 static void
13685 {
13695 }
13697 /* Return nonzero if REG is known to be dead at INSN.
13699 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13700 referencing REG, it is dead. If we hit a SET referencing REG, it is
13701 live. Otherwise, see if it is live or dead at the start of the basic
13702 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13703 must be assumed to be always live. */
13705 static int
13707 {
13708 basic_block block;
13711 /* Set variables for reg_dead_at_p_1. */
13717 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13718 we allow the machine description to decide whether use-and-clobber
13719 patterns are OK. */
13721 {
13725 }
13727 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13728 beginning of basic block. */
13731 {
13733 {
13743 }
13749 }
13751 /* Look at live-in sets for the basic block that we were in. */
13757 }
13758 \f
13759 /* Note hard registers in X that are used. */
13761 static void
13763 {
13769 {
13773 CASE_CONST_ANY:
13778 /* CC0 must die in the insn after it is set, so we don't need to take
13779 special note of it here. */
13784 /* If we are clobbering a MEM, mark any hard registers inside the
13785 address as used. */
13792 /* A hard reg in a wide mode may really be multiple registers.
13793 If so, mark all of them just like the first. */
13795 {
13796 /* None of this applies to the stack, frame or arg pointers. */
13798 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13806 }
13810 {
13811 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13812 the address. */
13824 }
13829 }
13831 /* Recursively scan the operands of this expression. */
13833 {
13837 {
13841 {
13846 }
13847 }
13848 }
13849 }
13850 \f
13851 /* Remove register number REGNO from the dead registers list of INSN.
13853 Return the note used to record the death, if there was one. */
13855 rtx
13857 {
13864 }
13866 /* For each register (hardware or pseudo) used within expression X, if its
13867 death is in an instruction with luid between FROM_LUID (inclusive) and
13868 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13869 list headed by PNOTES.
13871 That said, don't move registers killed by maybe_kill_insn.
13873 This is done when X is being merged by combination into TO_INSN. These
13874 notes will then be distributed as needed. */
13876 static void
13879 {
13885 {
13889 /* Don't move the register if it gets killed in between from and to. */
13898 {
13901 /* It is possible for the call above to return 0. This can occur
13902 when last_death points to I2 or I1 that we combined with.
13903 In that case make a new note.
13905 We must also check for the case where X is a hard register
13906 and NOTE is a death note for a range of hard registers
13907 including X. In that case, we must put REG_DEAD notes for
13908 the remaining registers in place of NOTE. */
13913 {
13922 }
13924 /* If we didn't find any note, or if we found a REG_DEAD note that
13925 covers only part of the given reg, and we have a multi-reg hard
13926 register, then to be safe we must check for REG_DEAD notes
13927 for each register other than the first. They could have
13928 their own REG_DEAD notes lying around. */
13935 {
13942 else
13948 }
13951 {
13954 }
13955 else
13957 }
13960 }
13963 {
13968 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13969 that accesses one word of a multi-word item, some
13970 piece of everything register in the expression is used by
13971 this insn, so remove any old death. */
13972 /* ??? So why do we test for equality of the sizes? */
13981 {
13984 }
13986 /* If this is some other SUBREG, we know it replaces the entire
13987 value, so use that as the destination. */
13991 /* If this is a MEM, adjust deaths of anything used in the address.
13992 For a REG (the only other possibility), the entire value is
13993 being replaced so the old value is not used in this insn. */
13999 }
14008 {
14010 {
14015 }
14018 }
14019 }
14020 \f
14021 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14022 pattern of an insn. X must be a REG. */
14024 static int
14026 {
14030 {
14032 rtx target;
14039 else
14056 }
14064 }
14065 \f
14066 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14067 as appropriate. I3 and I2 are the insns resulting from the combination
14068 insns including FROM (I2 may be zero).
14070 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14071 not need REG_DEAD notes because they are being substituted for. This
14072 saves searching in the most common cases.
14074 Each note in the list is either ignored or placed on some insns, depending
14075 on the type of note. */
14077 static void
14080 {
14082 rtx tem_note;
14086 {
14091 {
14094 /* Doesn't matter much where we put this, as long as it's somewhere.
14095 It is preferable to keep these notes on branches, which is most
14096 likely to be i3. */
14103 else
14104 {
14107 }
14111 /* These notes must remain with the call or trapping instruction. */
14116 else
14117 {
14123 /* ??? Otherwise assume we've combined things such that we
14124 can now prove that the instructions can't trap. Drop the
14125 note in this case. */
14126 }
14130 /* ??? How to distribute between i3-i1. Assume i3 contains the
14131 entire adjustment. Assert i3 contains at least some adjust. */
14133 {
14135 /* fixup_args_size_notes looks at REG_NORETURN note,
14136 so ensure the note is placed there first. */
14138 {
14142 {
14148 }
14149 }
14151 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14152 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14155 && !ACCUMULATE_OUTGOING_ARGS
14157 }
14164 /* These notes must remain with the call. It should not be
14165 possible for both I2 and I3 to be a call. */
14168 else
14169 {
14172 }
14176 /* Any clobbers for i3 may still exist, and so we must process
14177 REG_UNUSED notes from that insn.
14179 Any clobbers from i2 or i1 can only exist if they were added by
14180 recog_for_combine. In that case, recog_for_combine created the
14181 necessary REG_UNUSED notes. Trying to keep any original
14182 REG_UNUSED notes from these insns can cause incorrect output
14183 if it is for the same register as the original i3 dest.
14184 In that case, we will notice that the register is set in i3,
14185 and then add a REG_UNUSED note for the destination of i3, which
14186 is wrong. However, it is possible to have REG_UNUSED notes from
14187 i2 or i1 for register which were both used and clobbered, so
14188 we keep notes from i2 or i1 if they will turn into REG_DEAD
14189 notes. */
14191 /* If this register is set or clobbered in I3, put the note there
14192 unless there is one already. */
14194 {
14202 }
14203 /* Otherwise, if this register is used by I3, then this register
14204 now dies here, so we must put a REG_DEAD note here unless there
14205 is one already. */
14211 {
14214 }
14220 /* These notes say something about results of an insn. We can
14221 only support them if they used to be on I3 in which case they
14222 remain on I3. Otherwise they are ignored.
14224 If the note refers to an expression that is not a constant, we
14225 must also ignore the note since we cannot tell whether the
14226 equivalence is still true. It might be possible to do
14227 slightly better than this (we only have a problem if I2DEST
14228 or I1DEST is present in the expression), but it doesn't
14229 seem worth the trouble. */
14237 /* These notes say something about how a register is used. They must
14238 be present on any use of the register in I2 or I3. */
14243 {
14246 else
14248 }
14253 /* This can show up in several ways -- either directly in the
14254 pattern, or hidden off in the constant pool with (or without?)
14255 a REG_EQUAL note. */
14256 /* ??? Ignore the without-reg_equal-note problem for now. */
14268 {
14271 else
14273 }
14275 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14276 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14277 there. */
14282 {
14289 }
14295 {
14303 }
14307 /* This note says something about the value of a register prior
14308 to the execution of an insn. It is too much trouble to see
14309 if the note is still correct in all situations. It is better
14310 to simply delete it. */
14314 /* If we replaced the right hand side of FROM_INSN with a
14315 REG_EQUAL note, the original use of the dying register
14316 will not have been combined into I3 and I2. In such cases,
14317 FROM_INSN is guaranteed to be the first of the combined
14318 instructions, so we simply need to search back before
14319 FROM_INSN for the previous use or set of this register,
14320 then alter the notes there appropriately.
14322 If the register is used as an input in I3, it dies there.
14323 Similarly for I2, if it is nonzero and adjacent to I3.
14325 If the register is not used as an input in either I3 or I2
14326 and it is not one of the registers we were supposed to eliminate,
14327 there are two possibilities. We might have a non-adjacent I2
14328 or we might have somehow eliminated an additional register
14329 from a computation. For example, we might have had A & B where
14330 we discover that B will always be zero. In this case we will
14331 eliminate the reference to A.
14333 In both cases, we must search to see if we can find a previous
14334 use of A and put the death note there. */
14340 else
14341 {
14352 && !(i2mod
14354 i2mod_old_rhs)))
14359 /* If the new I2 sets the same register that is marked dead
14360 in the note, we do not know where to put the note.
14361 Give up. */
14364 }
14367 {
14371 {
14373 {
14377 }
14379 /* If the register is being set at TEM_INSN, see if that is all
14380 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14381 into a REG_UNUSED note instead. Don't delete sets to
14382 global register vars. */
14386 {
14397 ;
14399 /* Verify that it was the set, and not a clobber that
14400 modified the register.
14402 CC0 targets must be careful to maintain setter/user
14403 pairs. If we cannot delete the setter due to side
14404 effects, mark the user with an UNUSED note instead
14405 of deleting it. */
14409 && (!HAVE_cc0
14413 {
14414 /* Move the notes and links of TEM_INSN elsewhere.
14415 This might delete other dead insns recursively.
14416 First set the pattern to something that won't use
14417 any register. */
14436 /* Delete the setter too. */
14438 {
14451 }
14452 }
14453 else
14454 {
14457 /* If there isn't already a REG_UNUSED note, put one
14458 here. Do not place a REG_DEAD note, even if
14459 the register is also used here; that would not
14460 match the algorithm used in lifetime analysis
14461 and can cause the consistency check in the
14462 scheduler to fail. */
14467 }
14468 }
14472 {
14475 /* If we are doing a 3->2 combination, and we have a
14476 register which formerly died in i3 and was not used
14477 by i2, which now no longer dies in i3 and is used in
14478 i2 but does not die in i2, and place is between i2
14479 and i3, then we may need to move a link from place to
14480 i2. */
14482 && from_insn
14485 {
14489 }
14491 }
14495 }
14497 }
14499 /* If the register is set or already dead at PLACE, we needn't do
14500 anything with this note if it is still a REG_DEAD note.
14501 We check here if it is set at all, not if is it totally replaced,
14502 which is what `dead_or_set_p' checks, so also check for it being
14503 set partially. */
14506 {
14512 {
14513 /* Unless the register previously died in PLACE, clear
14514 last_death. [I no longer understand why this is
14515 being done.] */
14519 }
14520 else
14523 /* If this is a death note for a hard reg that is occupying
14524 multiple registers, ensure that we are still using all
14525 parts of the object. If we find a piece of the object
14526 that is unused, we must arrange for an appropriate REG_DEAD
14527 note to be added for it. However, we can't just emit a USE
14528 and tag the note to it, since the register might actually
14529 be dead; so we recourse, and the recursive call then finds
14530 the previous insn that used this register. */
14533 {
14542 {
14545 }
14548 {
14549 /* Put only REG_DEAD notes for pieces that are
14550 not already dead or set. */
14554 {
14561 {
14563 NULL_RTX);
14567 NULL_RTX);
14568 }
14573 {
14575 {
14579 }
14583 {
14586 }
14587 }
14588 }
14591 }
14592 }
14593 }
14597 /* Any other notes should not be present at this point in the
14598 compilation. */
14600 }
14603 {
14606 }
14610 }
14611 }
14612 \f
14613 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14614 I3, I2, and I1 to new locations. This is also called to add a link
14615 pointing at I3 when I3's destination is changed. */
14617 static void
14619 {
14623 {
14630 /* If the insn that this link points to is a NOTE, ignore it. */
14639 {
14642 {
14658 }
14661 }
14662 else
14672 /* A LOG_LINK is defined as being placed on the first insn that uses
14673 a register and points to the insn that sets the register. Start
14674 searching at the next insn after the target of the link and stop
14675 when we reach a set of the register or the end of the basic block.
14677 Note that this correctly handles the link that used to point from
14678 I3 to I2. Also note that not much searching is typically done here
14679 since most links don't point very far away. */
14688 {
14692 }
14695 {
14698 }
14702 /* If we found a place to put the link, place it there unless there
14703 is already a link to the same insn as LINK at that point. */
14706 {
14714 {
14718 /* Set added_links_insn to the earliest insn we added a
14719 link to. */
14723 }
14724 }
14725 }
14726 }
14727 \f
14728 /* Check for any register or memory mentioned in EQUIV that is not
14729 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14730 of EXPR where some registers may have been replaced by constants. */
14732 static bool
14734 {
14737 {
14742 }
14744 }
14745 \f
14746 DEBUG_FUNCTION void
14748 {
14749 fprintf
14751 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14753 }
14755 void
14757 {
14758 fprintf
14760 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14762 }
14763 \f
14764 /* Try combining insns through substitution. */
14765 static unsigned int
14767 {
14777 rebuild_jump_labels_after_combine
14780 /* Combining insns may have turned an indirect jump into a
14781 direct jump. Rebuild the JUMP_LABEL fields of jumping
14782 instructions. */
14784 {
14791 }
14795 }
14800 {
14810 };
14813 {
14817 {}
14819 /* opt_pass methods: */
14822 {
14824 }
14830 rtl_opt_pass *
14832 {
14834 }