1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern tree lookup_name
PARAMS ((tree
));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
90 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
91 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
93 int coprocessor_operand
PARAMS ((rtx
,
95 int coprocessor2_operand
PARAMS ((rtx
,
97 static int m16_check_op
PARAMS ((rtx
, int, int, int));
98 static void block_move_loop
PARAMS ((rtx
, rtx
,
102 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
103 static void mips_arg_info
PARAMS ((const CUMULATIVE_ARGS
*,
106 struct mips_arg_info
*));
107 static rtx mips_add_large_offset_to_sp
PARAMS ((HOST_WIDE_INT
,
109 static void mips_annotate_frame_insn
PARAMS ((rtx
, rtx
));
110 static rtx mips_frame_set
PARAMS ((enum machine_mode
,
112 static void mips_emit_frame_related_store
PARAMS ((rtx
, rtx
,
114 static void save_restore_insns
PARAMS ((int, rtx
,
116 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
117 static void mips16_fp_args
PARAMS ((FILE *, int, int));
118 static void build_mips16_function_stub
PARAMS ((FILE *));
119 static void mips16_optimize_gp
PARAMS ((rtx
));
120 static rtx add_constant
PARAMS ((struct constant
**,
123 static void dump_constants
PARAMS ((struct constant
*,
125 static rtx mips_find_symbol
PARAMS ((rtx
));
126 static void abort_with_insn
PARAMS ((rtx
, const char *))
128 static int symbolic_expression_p
PARAMS ((rtx
));
129 static void mips_add_gc_roots
PARAMS ((void));
130 static bool mips_assemble_integer
PARAMS ((rtx
, unsigned int, int));
131 static void mips_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
132 static void mips_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
133 static enum processor_type mips_parse_cpu
PARAMS ((const char *));
134 static void copy_file_data
PARAMS ((FILE *, FILE *));
136 static void iris6_asm_named_section_1
PARAMS ((const char *,
139 static void iris6_asm_named_section
PARAMS ((const char *,
141 static int iris_section_align_entry_eq
PARAMS ((const PTR
, const PTR
));
142 static hashval_t iris_section_align_entry_hash
PARAMS ((const PTR
));
143 static int iris6_section_align_1
PARAMS ((void **, void *));
145 static int mips_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
146 static int mips_issue_rate
PARAMS ((void));
148 static void mips_init_machine_status
PARAMS ((struct function
*));
149 static void mips_free_machine_status
PARAMS ((struct function
*));
150 static void mips_mark_machine_status
PARAMS ((struct function
*));
152 struct machine_function
{
153 /* Pseudo-reg holding the address of the current function when
154 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
155 used by mips_finalize_pic if it was created. */
156 rtx embedded_pic_fnaddr_rtx
;
158 /* Pseudo-reg holding the value of $28 in a mips16 function which
159 refers to GP relative global variables. */
160 rtx mips16_gp_pseudo_rtx
;
163 /* Information about a single argument. */
166 /* True if the argument is a record or union type. */
169 /* True if the argument is passed in a floating-point register, or
170 would have been if we hadn't run out of registers. */
173 /* The argument's size, in bytes. */
174 unsigned int num_bytes
;
176 /* The number of words passed in registers, rounded up. */
177 unsigned int reg_words
;
179 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
180 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
182 unsigned int reg_offset
;
184 /* The number of words that must be passed on the stack, rounded up. */
185 unsigned int stack_words
;
187 /* The offset from the start of the stack overflow area of the argument's
188 first stack word. Only meaningful when STACK_WORDS is non-zero. */
189 unsigned int stack_offset
;
192 /* Global variables for machine-dependent things. */
194 /* Threshold for data being put into the small data/bss area, instead
195 of the normal data area (references to the small data/bss area take
196 1 instruction, and use the global pointer, references to the normal
197 data area takes 2 instructions). */
198 int mips_section_threshold
= -1;
200 /* Count the number of .file directives, so that .loc is up to date. */
201 int num_source_filenames
= 0;
203 /* Count the number of sdb related labels are generated (to find block
204 start and end boundaries). */
205 int sdb_label_count
= 0;
207 /* Next label # for each statement for Silicon Graphics IRIS systems. */
210 /* Non-zero if inside of a function, because the stupid MIPS asm can't
211 handle .files inside of functions. */
212 int inside_function
= 0;
214 /* Files to separate the text and the data output, so that all of the data
215 can be emitted before the text, which will mean that the assembler will
216 generate smaller code, based on the global pointer. */
217 FILE *asm_out_data_file
;
218 FILE *asm_out_text_file
;
220 /* Linked list of all externals that are to be emitted when optimizing
221 for the global pointer if they haven't been declared by the end of
222 the program with an appropriate .comm or initialization. */
226 struct extern_list
*next
; /* next external */
227 const char *name
; /* name of the external */
228 int size
; /* size in bytes */
231 /* Name of the file containing the current function. */
232 const char *current_function_file
= "";
234 /* Warning given that Mips ECOFF can't support changing files
235 within a function. */
236 int file_in_function_warning
= FALSE
;
238 /* Whether to suppress issuing .loc's because the user attempted
239 to change the filename within a function. */
240 int ignore_line_number
= FALSE
;
242 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
248 /* The next branch instruction is a branch likely, not branch normal. */
249 int mips_branch_likely
;
251 /* Count of delay slots and how many are filled. */
252 int dslots_load_total
;
253 int dslots_load_filled
;
254 int dslots_jump_total
;
255 int dslots_jump_filled
;
257 /* # of nops needed by previous insn */
258 int dslots_number_nops
;
260 /* Number of 1/2/3 word references to data items (ie, not jal's). */
263 /* registers to check for load delay */
264 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
266 /* Cached operands, and operator to compare for use in set/branch/trap
267 on condition codes. */
270 /* what type of branch to use */
271 enum cmp_type branch_type
;
273 /* Number of previously seen half-pic pointers and references. */
274 static int prev_half_pic_ptrs
= 0;
275 static int prev_half_pic_refs
= 0;
277 /* The target cpu for code generation. */
278 enum processor_type mips_arch
;
280 /* The target cpu for optimization and scheduling. */
281 enum processor_type mips_tune
;
283 /* which instruction set architecture to use. */
286 /* which abi to use. */
289 /* Strings to hold which cpu and instruction set architecture to use. */
290 const char *mips_cpu_string
; /* for -mcpu=<xxx> */
291 const char *mips_arch_string
; /* for -march=<xxx> */
292 const char *mips_tune_string
; /* for -mtune=<xxx> */
293 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
294 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
296 /* Whether we are generating mips16 code. This is a synonym for
297 TARGET_MIPS16, and exists for use as an attribute. */
300 /* This variable is set by -mno-mips16. We only care whether
301 -mno-mips16 appears or not, and using a string in this fashion is
302 just a way to avoid using up another bit in target_flags. */
303 const char *mips_no_mips16_string
;
305 /* This is only used to determine if an type size setting option was
306 explicitly specified (-mlong64, -mint64, -mlong32). The specs
307 set this option if such an option is used. */
308 const char *mips_explicit_type_size_string
;
310 /* Whether we are generating mips16 hard float code. In mips16 mode
311 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
312 -msoft-float was not specified by the user, which means that we
313 should arrange to call mips32 hard floating point code. */
314 int mips16_hard_float
;
316 /* This variable is set by -mentry. We only care whether -mentry
317 appears or not, and using a string in this fashion is just a way to
318 avoid using up another bit in target_flags. */
319 const char *mips_entry_string
;
321 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
323 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
326 /* If TRUE, we split addresses into their high and low parts in the RTL. */
327 int mips_split_addresses
;
329 /* Generating calls to position independent functions? */
330 enum mips_abicalls_type mips_abicalls
;
332 /* High and low marks for floating point values which we will accept
333 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
334 initialized in override_options. */
335 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
337 /* Mode used for saving/restoring general purpose registers. */
338 static enum machine_mode gpr_mode
;
340 /* Array giving truth value on whether or not a given hard register
341 can support a given mode. */
342 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
344 /* Current frame information calculated by compute_frame_size. */
345 struct mips_frame_info current_frame_info
;
347 /* Zero structure to initialize current_frame_info. */
348 struct mips_frame_info zero_frame_info
;
350 /* The length of all strings seen when compiling for the mips16. This
351 is used to tell how many strings are in the constant pool, so that
352 we can see if we may have an overflow. This is reset each time the
353 constant pool is output. */
354 int mips_string_length
;
356 /* In mips16 mode, we build a list of all the string constants we see
357 in a particular function. */
359 struct string_constant
361 struct string_constant
*next
;
365 static struct string_constant
*string_constants
;
367 /* List of all MIPS punctuation characters used by print_operand. */
368 char mips_print_operand_punct
[256];
370 /* Map GCC register number to debugger register number. */
371 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
373 /* Buffer to use to enclose a load/store operation with %{ %} to
374 turn on .set volatile. */
375 static char volatile_buffer
[60];
377 /* Hardware names for the registers. If -mrnames is used, this
378 will be overwritten with mips_sw_reg_names. */
380 char mips_reg_names
[][8] =
382 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
383 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
384 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
385 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
386 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
387 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
388 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
389 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
390 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
391 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
392 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
393 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
394 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
395 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
396 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
397 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
398 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
399 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
400 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
401 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
402 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
403 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
406 /* Mips software names for the registers, used to overwrite the
407 mips_reg_names array. */
409 char mips_sw_reg_names
[][8] =
411 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
412 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
413 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
414 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
415 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
416 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
417 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
418 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
419 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
420 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
421 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
422 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
423 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
424 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
425 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
426 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
427 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
428 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
429 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
430 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
431 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
432 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
435 /* Map hard register number to register class */
436 const enum reg_class mips_regno_to_class
[] =
438 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
439 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
440 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
441 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
442 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
443 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
444 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
445 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
446 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
447 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
448 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
449 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
450 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
451 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
452 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
453 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
454 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
455 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
456 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
,
457 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
458 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
459 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
460 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
461 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
462 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
463 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
464 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
465 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
466 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
467 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
468 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
469 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
470 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
471 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
472 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
473 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
474 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
475 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
476 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
477 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
478 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
479 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
480 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
481 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
484 /* Map register constraint character to register class. */
485 enum reg_class mips_char_to_class
[256] =
487 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
488 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
489 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
490 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
491 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
492 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
493 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
494 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
495 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
496 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
497 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
498 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
499 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
500 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
501 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
502 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
503 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
504 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
505 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
506 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
507 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
508 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
509 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
510 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
511 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
512 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
513 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
514 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
515 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
516 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
517 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
518 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
519 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
520 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
521 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
522 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
523 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
524 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
525 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
526 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
527 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
528 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
529 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
530 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
531 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
532 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
533 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
534 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
535 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
536 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
537 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
538 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
539 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
540 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
541 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
542 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
543 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
544 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
545 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
546 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
547 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
548 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
549 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
550 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
553 /* Initialize the GCC target structure. */
554 #undef TARGET_ASM_ALIGNED_HI_OP
555 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
556 #undef TARGET_ASM_ALIGNED_SI_OP
557 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
558 #undef TARGET_ASM_INTEGER
559 #define TARGET_ASM_INTEGER mips_assemble_integer
561 #if TARGET_IRIX5 && !TARGET_IRIX6
562 #undef TARGET_ASM_UNALIGNED_HI_OP
563 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
564 #undef TARGET_ASM_UNALIGNED_SI_OP
565 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
568 #undef TARGET_ASM_FUNCTION_PROLOGUE
569 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
570 #undef TARGET_ASM_FUNCTION_EPILOGUE
571 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
573 #undef TARGET_SCHED_ADJUST_COST
574 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
576 #undef TARGET_SCHED_ISSUE_RATE
577 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
579 struct gcc_target targetm
= TARGET_INITIALIZER
;
581 /* Return truth value of whether OP can be used as an operands
582 where a register or 16 bit unsigned integer is needed. */
585 uns_arith_operand (op
, mode
)
587 enum machine_mode mode
;
589 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
592 return register_operand (op
, mode
);
595 /* Return truth value of whether OP can be used as an operands
596 where a 16 bit integer is needed */
599 arith_operand (op
, mode
)
601 enum machine_mode mode
;
603 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
606 /* On the mips16, a GP relative value is a signed 16 bit offset. */
607 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
610 return register_operand (op
, mode
);
613 /* Return truth value of whether OP can be used as an operand in a two
614 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
617 arith32_operand (op
, mode
)
619 enum machine_mode mode
;
621 if (GET_CODE (op
) == CONST_INT
)
624 return register_operand (op
, mode
);
627 /* Return truth value of whether OP is an integer which fits in 16 bits. */
632 enum machine_mode mode ATTRIBUTE_UNUSED
;
634 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
637 /* Return truth value of whether OP is a 32 bit integer which is too big to
638 be loaded with one instruction. */
643 enum machine_mode mode ATTRIBUTE_UNUSED
;
647 if (GET_CODE (op
) != CONST_INT
)
652 /* ior reg,$r0,value */
653 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
656 /* subu reg,$r0,value */
657 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
660 /* lui reg,value>>16 */
661 if ((value
& 0x0000ffff) == 0)
667 /* Return truth value of whether OP is a register or the constant 0.
668 In mips16 mode, we only accept a register, since the mips16 does
672 reg_or_0_operand (op
, mode
)
674 enum machine_mode mode
;
676 switch (GET_CODE (op
))
681 return INTVAL (op
) == 0;
686 return op
== CONST0_RTX (mode
);
690 return register_operand (op
, mode
);
699 /* Return truth value of whether OP is a register or the constant 0,
700 even in mips16 mode. */
703 true_reg_or_0_operand (op
, mode
)
705 enum machine_mode mode
;
707 switch (GET_CODE (op
))
710 return INTVAL (op
) == 0;
713 return op
== CONST0_RTX (mode
);
717 return register_operand (op
, mode
);
726 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
729 mips_const_double_ok (op
, mode
)
731 enum machine_mode mode
;
735 if (GET_CODE (op
) != CONST_DOUBLE
)
738 if (mode
== VOIDmode
)
741 if (mode
!= SFmode
&& mode
!= DFmode
)
744 if (op
== CONST0_RTX (mode
))
747 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
748 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
751 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
753 if (REAL_VALUE_ISNAN (d
))
756 if (REAL_VALUE_NEGATIVE (d
))
757 d
= REAL_VALUE_NEGATE (d
);
761 if (REAL_VALUES_LESS (d
, dfhigh
)
762 && REAL_VALUES_LESS (dflow
, d
))
767 if (REAL_VALUES_LESS (d
, sfhigh
)
768 && REAL_VALUES_LESS (sflow
, d
))
775 /* Accept the floating point constant 1 in the appropriate mode. */
778 const_float_1_operand (op
, mode
)
780 enum machine_mode mode
;
783 static REAL_VALUE_TYPE onedf
;
784 static REAL_VALUE_TYPE onesf
;
785 static int one_initialized
;
787 if (GET_CODE (op
) != CONST_DOUBLE
788 || mode
!= GET_MODE (op
)
789 || (mode
!= DFmode
&& mode
!= SFmode
))
792 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
794 /* We only initialize these values if we need them, since we will
795 never get called unless mips_isa >= 4. */
796 if (! one_initialized
)
798 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
799 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
804 return REAL_VALUES_EQUAL (d
, onedf
);
806 return REAL_VALUES_EQUAL (d
, onesf
);
809 /* Return true if a memory load or store of REG plus OFFSET in MODE
810 can be represented in a single word on the mips16. */
813 mips16_simple_memory_operand (reg
, offset
, mode
)
816 enum machine_mode mode
;
823 /* We can't tell, because we don't know how the value will
824 eventually be accessed. Returning 0 here does no great
825 harm; it just prevents some possible instruction scheduling. */
829 size
= GET_MODE_SIZE (mode
);
831 if (INTVAL (offset
) % size
!= 0)
833 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
837 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < (HOST_WIDE_INT
)(off
* size
))
842 /* Return truth value if a memory operand fits in a single instruction
843 (ie, register + small offset). */
846 simple_memory_operand (op
, mode
)
848 enum machine_mode mode
;
850 rtx addr
, plus0
, plus1
;
852 /* Eliminate non-memory operations */
853 if (GET_CODE (op
) != MEM
)
856 /* dword operations really put out 2 instructions, so eliminate them. */
857 /* ??? This isn't strictly correct. It is OK to accept multiword modes
858 here, since the length attributes are being set correctly, but only
859 if the address is offsettable. LO_SUM is not offsettable. */
860 if (GET_MODE_SIZE (GET_MODE (op
)) > (unsigned) UNITS_PER_WORD
)
863 /* Decode the address now. */
865 switch (GET_CODE (addr
))
874 return SMALL_INT (addr
);
877 plus0
= XEXP (addr
, 0);
878 plus1
= XEXP (addr
, 1);
879 if (GET_CODE (plus0
) == REG
880 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
882 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
885 else if (GET_CODE (plus1
) == REG
886 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
888 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
895 /* We used to allow small symbol refs here (ie, stuff in .sdata
896 or .sbss), but this causes some bugs in G++. Also, it won't
897 interfere if the MIPS linker rewrites the store instruction
898 because the function is PIC. */
900 case LABEL_REF
: /* never gp relative */
904 /* If -G 0, we can never have a GP relative memory operation.
905 Also, save some time if not optimizing. */
910 rtx offset
= const0_rtx
;
911 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
912 if (GET_CODE (op
) != SYMBOL_REF
)
915 /* let's be paranoid.... */
916 if (! SMALL_INT (offset
))
923 return SYMBOL_REF_FLAG (addr
);
926 /* This SYMBOL_REF case is for the mips16. If the above case is
927 reenabled, this one should be merged in. */
929 /* References to the constant pool on the mips16 use a small
930 offset if the function is small. The only time we care about
931 getting this right is during delayed branch scheduling, so
932 don't need to check until then. The machine_dependent_reorg
933 function will set the total length of the instructions used
934 in the function in current_frame_info. If that is small
935 enough, we know for sure that this is a small offset. It
936 would be better if we could take into account the location of
937 the instruction within the function, but we can't, because we
938 don't know where we are. */
940 && CONSTANT_POOL_ADDRESS_P (addr
)
941 && current_frame_info
.insns_len
> 0)
945 size
= current_frame_info
.insns_len
+ get_pool_size ();
946 if (GET_MODE_SIZE (mode
) == 4)
947 return size
< 4 * 0x100;
948 else if (GET_MODE_SIZE (mode
) == 8)
949 return size
< 8 * 0x20;
963 /* Return nonzero for a memory address that can be used to load or store
967 double_memory_operand (op
, mode
)
969 enum machine_mode mode
;
971 if (GET_CODE (op
) != MEM
972 || ! memory_operand (op
, mode
))
974 /* During reload, we accept a pseudo register if it has an
975 appropriate memory address. If we don't do this, we will
976 wind up reloading into a register, and then reloading that
977 register from memory, when we could just reload directly from
979 if (reload_in_progress
980 && GET_CODE (op
) == REG
981 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
982 && reg_renumber
[REGNO (op
)] < 0
983 && reg_equiv_mem
[REGNO (op
)] != 0
984 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
987 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
988 the same test performed for 'm' in find_reloads. */
990 if (reload_in_progress
992 && (GET_CODE (op
) == MEM
993 || (GET_CODE (op
) == REG
994 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
995 && reg_renumber
[REGNO (op
)] < 0)))
998 if (reload_in_progress
1000 && GET_CODE (op
) == MEM
)
1004 addr
= XEXP (op
, 0);
1006 /* During reload on the mips16, we accept a large offset
1007 from the frame pointer or the stack pointer. This large
1008 address will get reloaded anyhow. */
1009 if (GET_CODE (addr
) == PLUS
1010 && GET_CODE (XEXP (addr
, 0)) == REG
1011 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1012 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1013 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1014 && ! SMALL_INT (XEXP (addr
, 1)))
1015 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1016 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1019 /* Similarly, we accept a case where the memory address is
1020 itself on the stack, and will be reloaded. */
1021 if (GET_CODE (addr
) == MEM
)
1025 maddr
= XEXP (addr
, 0);
1026 if (GET_CODE (maddr
) == PLUS
1027 && GET_CODE (XEXP (maddr
, 0)) == REG
1028 && (REGNO (XEXP (maddr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1029 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
1030 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
1031 && ! SMALL_INT (XEXP (maddr
, 1)))
1032 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
1033 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
1037 /* We also accept the same case when we have a 16 bit signed
1038 offset mixed in as well. The large address will get
1039 reloaded, and the 16 bit offset will be OK. */
1040 if (GET_CODE (addr
) == PLUS
1041 && GET_CODE (XEXP (addr
, 0)) == MEM
1042 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
1043 && SMALL_INT (XEXP (addr
, 1)))
1045 addr
= XEXP (XEXP (addr
, 0), 0);
1046 if (GET_CODE (addr
) == PLUS
1047 && GET_CODE (XEXP (addr
, 0)) == REG
1048 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1049 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1050 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1051 && ! SMALL_INT (XEXP (addr
, 1)))
1052 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1053 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1063 /* In this case we can use an instruction like sd. */
1067 /* Make sure that 4 added to the address is a valid memory address.
1068 This essentially just checks for overflow in an added constant. */
1070 if (CONSTANT_ADDRESS_P (XEXP (op
, 0)))
1073 op
= adjust_address_nv (op
, GET_MODE_CLASS (mode
) == MODE_INT
1074 ? SImode
: SFmode
, 4);
1075 return memory_address_p (GET_MODE (op
), XEXP (op
, 0));
1078 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1081 equality_op (op
, mode
)
1083 enum machine_mode mode
;
1085 if (mode
!= GET_MODE (op
))
1088 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
1091 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1096 enum machine_mode mode
;
1098 if (mode
!= GET_MODE (op
))
1101 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
1104 /* Return nonzero if the code is a relational operation suitable for a
1105 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1106 We need this in the insn that expands `trap_if' in order to prevent
1107 combine from erroneously altering the condition. */
1110 trap_cmp_op (op
, mode
)
1112 enum machine_mode mode
;
1114 if (mode
!= GET_MODE (op
))
1117 switch (GET_CODE (op
))
1132 /* Return nonzero if the operand is either the PC or a label_ref. */
1135 pc_or_label_operand (op
, mode
)
1137 enum machine_mode mode ATTRIBUTE_UNUSED
;
1142 if (GET_CODE (op
) == LABEL_REF
)
1148 /* Test for a valid operand for a call instruction.
1149 Don't allow the arg pointer register or virtual regs
1150 since they may change into reg + const, which the patterns
1151 can't handle yet. */
1154 call_insn_operand (op
, mode
)
1156 enum machine_mode mode ATTRIBUTE_UNUSED
;
1158 return (CONSTANT_ADDRESS_P (op
)
1159 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
1160 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1161 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
1164 /* Return nonzero if OPERAND is valid as a source operand for a move
1168 move_operand (op
, mode
)
1170 enum machine_mode mode
;
1172 /* Accept any general operand after reload has started; doing so
1173 avoids losing if reload does an in-place replacement of a register
1174 with a SYMBOL_REF or CONST. */
1175 return (general_operand (op
, mode
)
1176 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1177 || reload_in_progress
|| reload_completed
)
1179 && GET_CODE (op
) == SYMBOL_REF
1180 && ! mips16_constant (op
, mode
, 1, 0)));
1183 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1184 This accepts not only general_operand, but also sign extended
1185 constants and registers. We need to accept sign extended constants
1186 in case a sign extended register which is used in an expression,
1187 and is equivalent to a constant, is spilled. */
1190 movdi_operand (op
, mode
)
1192 enum machine_mode mode
;
1196 && GET_CODE (op
) == SIGN_EXTEND
1197 && GET_MODE (op
) == DImode
1198 && (GET_MODE (XEXP (op
, 0)) == SImode
1199 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
1200 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
1201 && (register_operand (XEXP (op
, 0), SImode
)
1202 || immediate_operand (XEXP (op
, 0), SImode
)))
1205 return (general_operand (op
, mode
)
1207 && GET_CODE (op
) == SYMBOL_REF
1208 && ! mips16_constant (op
, mode
, 1, 0)));
1211 /* Like register_operand, but when in 64 bit mode also accept a sign
1212 extend of a 32 bit register, since the value is known to be already
1216 se_register_operand (op
, mode
)
1218 enum machine_mode mode
;
1222 && GET_CODE (op
) == SIGN_EXTEND
1223 && GET_MODE (op
) == DImode
1224 && GET_MODE (XEXP (op
, 0)) == SImode
1225 && register_operand (XEXP (op
, 0), SImode
))
1228 return register_operand (op
, mode
);
1231 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1232 extend of a 32 bit register, since the value is known to be already
1236 se_reg_or_0_operand (op
, mode
)
1238 enum machine_mode mode
;
1242 && GET_CODE (op
) == SIGN_EXTEND
1243 && GET_MODE (op
) == DImode
1244 && GET_MODE (XEXP (op
, 0)) == SImode
1245 && register_operand (XEXP (op
, 0), SImode
))
1248 return reg_or_0_operand (op
, mode
);
1251 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1252 extend of a 32 bit register, since the value is known to be already
1256 se_uns_arith_operand (op
, mode
)
1258 enum machine_mode mode
;
1262 && GET_CODE (op
) == SIGN_EXTEND
1263 && GET_MODE (op
) == DImode
1264 && GET_MODE (XEXP (op
, 0)) == SImode
1265 && register_operand (XEXP (op
, 0), SImode
))
1268 return uns_arith_operand (op
, mode
);
1271 /* Like arith_operand, but when in 64 bit mode also accept a sign
1272 extend of a 32 bit register, since the value is known to be already
1276 se_arith_operand (op
, mode
)
1278 enum machine_mode mode
;
1282 && GET_CODE (op
) == SIGN_EXTEND
1283 && GET_MODE (op
) == DImode
1284 && GET_MODE (XEXP (op
, 0)) == SImode
1285 && register_operand (XEXP (op
, 0), SImode
))
1288 return arith_operand (op
, mode
);
1291 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1292 extend of a 32 bit register, since the value is known to be already
1296 se_nonmemory_operand (op
, mode
)
1298 enum machine_mode mode
;
1302 && GET_CODE (op
) == SIGN_EXTEND
1303 && GET_MODE (op
) == DImode
1304 && GET_MODE (XEXP (op
, 0)) == SImode
1305 && register_operand (XEXP (op
, 0), SImode
))
1308 return nonmemory_operand (op
, mode
);
1311 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1312 sign extend of a 32 bit register, since the value is known to be
1313 already sign extended. */
1316 se_nonimmediate_operand (op
, mode
)
1318 enum machine_mode mode
;
1322 && GET_CODE (op
) == SIGN_EXTEND
1323 && GET_MODE (op
) == DImode
1324 && GET_MODE (XEXP (op
, 0)) == SImode
1325 && register_operand (XEXP (op
, 0), SImode
))
1328 return nonimmediate_operand (op
, mode
);
1331 /* Accept any operand that can appear in a mips16 constant table
1332 instruction. We can't use any of the standard operand functions
1333 because for these instructions we accept values that are not
1334 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1337 consttable_operand (op
, mode
)
1339 enum machine_mode mode ATTRIBUTE_UNUSED
;
1341 return CONSTANT_P (op
);
1344 /* Coprocessor operand; return true if rtx is a REG and refers to a
1348 coprocessor_operand (op
, mode
)
1350 enum machine_mode mode ATTRIBUTE_UNUSED
;
1352 return (GET_CODE (op
) == REG
1353 && COP0_REG_FIRST
<= REGNO (op
)
1354 && REGNO (op
) <= COP3_REG_LAST
);
1358 coprocessor2_operand (op
, mode
)
1360 enum machine_mode mode ATTRIBUTE_UNUSED
;
1362 return (GET_CODE (op
) == REG
1363 && COP2_REG_FIRST
<= REGNO (op
)
1364 && REGNO (op
) <= COP2_REG_LAST
);
1367 /* Return nonzero if we split the address into high and low parts. */
1369 /* ??? We should also handle reg+array somewhere. We get four
1370 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1371 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1372 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1373 out of the address, then we have 4 instructions to combine. Perhaps
1374 add a 3->2 define_split for combine. */
1376 /* ??? We could also split a CONST_INT here if it is a large_int().
1377 However, it doesn't seem to be very useful to have %hi(constant).
1378 We would be better off by doing the masking ourselves and then putting
1379 the explicit high part of the constant in the RTL. This will give better
1380 optimization. Also, %hi(constant) needs assembler changes to work.
1381 There is already a define_split that does this. */
1384 mips_check_split (address
, mode
)
1386 enum machine_mode mode
;
1388 /* ??? This is the same check used in simple_memory_operand.
1389 We use it here because LO_SUM is not offsettable. */
1390 if (GET_MODE_SIZE (mode
) > (unsigned) UNITS_PER_WORD
)
1393 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1394 || (GET_CODE (address
) == CONST
1395 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1396 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1397 || GET_CODE (address
) == LABEL_REF
)
1403 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1406 mips_reg_mode_ok_for_base_p (reg
, mode
, strict
)
1408 enum machine_mode mode
;
1412 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg
), mode
)
1413 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg
), mode
));
1416 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1417 returns a nonzero value if XINSN is a legitimate address for a
1418 memory operand of the indicated MODE. STRICT is non-zero if this
1419 function is called during reload. */
1422 mips_legitimate_address_p (mode
, xinsn
, strict
)
1423 enum machine_mode mode
;
1427 if (TARGET_DEBUG_B_MODE
)
1429 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1430 strict
? "" : "not ");
1431 GO_DEBUG_RTX (xinsn
);
1434 /* Check for constant before stripping off SUBREG, so that we don't
1435 accept (subreg (const_int)) which will fail to reload. */
1436 if (CONSTANT_ADDRESS_P (xinsn
)
1437 && ! (mips_split_addresses
&& mips_check_split (xinsn
, mode
))
1438 && (! TARGET_MIPS16
|| mips16_constant (xinsn
, mode
, 1, 0)))
1441 while (GET_CODE (xinsn
) == SUBREG
)
1442 xinsn
= SUBREG_REG (xinsn
);
1444 /* The mips16 can only use the stack pointer as a base register when
1445 loading SImode or DImode values. */
1446 if (GET_CODE (xinsn
) == REG
1447 && mips_reg_mode_ok_for_base_p (xinsn
, mode
, strict
))
1450 if (GET_CODE (xinsn
) == LO_SUM
&& mips_split_addresses
)
1452 register rtx xlow0
= XEXP (xinsn
, 0);
1453 register rtx xlow1
= XEXP (xinsn
, 1);
1455 while (GET_CODE (xlow0
) == SUBREG
)
1456 xlow0
= SUBREG_REG (xlow0
);
1457 if (GET_CODE (xlow0
) == REG
1458 && mips_reg_mode_ok_for_base_p (xlow0
, mode
, strict
)
1459 && mips_check_split (xlow1
, mode
))
1463 if (GET_CODE (xinsn
) == PLUS
)
1465 register rtx xplus0
= XEXP (xinsn
, 0);
1466 register rtx xplus1
= XEXP (xinsn
, 1);
1467 register enum rtx_code code0
;
1468 register enum rtx_code code1
;
1470 while (GET_CODE (xplus0
) == SUBREG
)
1471 xplus0
= SUBREG_REG (xplus0
);
1472 code0
= GET_CODE (xplus0
);
1474 while (GET_CODE (xplus1
) == SUBREG
)
1475 xplus1
= SUBREG_REG (xplus1
);
1476 code1
= GET_CODE (xplus1
);
1478 /* The mips16 can only use the stack pointer as a base register
1479 when loading SImode or DImode values. */
1481 && mips_reg_mode_ok_for_base_p (xplus0
, mode
, strict
))
1483 if (code1
== CONST_INT
&& SMALL_INT (xplus1
))
1486 /* On the mips16, we represent GP relative offsets in RTL.
1487 These are 16 bit signed values, and can serve as register
1490 && mips16_gp_offset_p (xplus1
))
1493 /* For some code sequences, you actually get better code by
1494 pretending that the MIPS supports an address mode of a
1495 constant address + a register, even though the real
1496 machine doesn't support it. This is because the
1497 assembler can use $r1 to load just the high 16 bits, add
1498 in the register, and fold the low 16 bits into the memory
1499 reference, whereas the compiler generates a 4 instruction
1500 sequence. On the other hand, CSE is not as effective.
1501 It would be a win to generate the lui directly, but the
1502 MIPS assembler does not have syntax to generate the
1503 appropriate relocation. */
1505 /* Also accept CONST_INT addresses here, so no else. */
1506 /* Reject combining an embedded PIC text segment reference
1507 with a register. That requires an additional
1509 /* ??? Reject combining an address with a register for the MIPS
1510 64 bit ABI, because the SGI assembler can not handle this. */
1511 if (!TARGET_DEBUG_A_MODE
1512 && (mips_abi
== ABI_32
1513 || mips_abi
== ABI_O64
1514 || mips_abi
== ABI_EABI
)
1515 && CONSTANT_ADDRESS_P (xplus1
)
1516 && ! mips_split_addresses
1517 && (!TARGET_EMBEDDED_PIC
1519 || GET_CODE (XEXP (xplus1
, 0)) != MINUS
)
1520 /* When assembling for machines with 64 bit registers,
1521 the assembler will sign-extend the constant "foo"
1522 in "la x, foo(x)" yielding the wrong result for:
1523 (set (blah:DI) (plus x y)). */
1525 || (code1
== CONST_INT
1526 && trunc_int_for_mode (INTVAL (xplus1
),
1527 SImode
) == INTVAL (xplus1
)))
1533 if (TARGET_DEBUG_B_MODE
)
1534 GO_PRINTF ("Not a legitimate address\n");
1536 /* The address was not legitimate. */
1541 /* We need a lot of little routines to check constant values on the
1542 mips16. These are used to figure out how long the instruction will
1543 be. It would be much better to do this using constraints, but
1544 there aren't nearly enough letters available. */
1547 m16_check_op (op
, low
, high
, mask
)
1553 return (GET_CODE (op
) == CONST_INT
1554 && INTVAL (op
) >= low
1555 && INTVAL (op
) <= high
1556 && (INTVAL (op
) & mask
) == 0);
1560 m16_uimm3_b (op
, mode
)
1562 enum machine_mode mode ATTRIBUTE_UNUSED
;
1564 return m16_check_op (op
, 0x1, 0x8, 0);
1568 m16_simm4_1 (op
, mode
)
1570 enum machine_mode mode ATTRIBUTE_UNUSED
;
1572 return m16_check_op (op
, - 0x8, 0x7, 0);
1576 m16_nsimm4_1 (op
, mode
)
1578 enum machine_mode mode ATTRIBUTE_UNUSED
;
1580 return m16_check_op (op
, - 0x7, 0x8, 0);
1584 m16_simm5_1 (op
, mode
)
1586 enum machine_mode mode ATTRIBUTE_UNUSED
;
1588 return m16_check_op (op
, - 0x10, 0xf, 0);
1592 m16_nsimm5_1 (op
, mode
)
1594 enum machine_mode mode ATTRIBUTE_UNUSED
;
1596 return m16_check_op (op
, - 0xf, 0x10, 0);
1600 m16_uimm5_4 (op
, mode
)
1602 enum machine_mode mode ATTRIBUTE_UNUSED
;
1604 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1608 m16_nuimm5_4 (op
, mode
)
1610 enum machine_mode mode ATTRIBUTE_UNUSED
;
1612 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1616 m16_simm8_1 (op
, mode
)
1618 enum machine_mode mode ATTRIBUTE_UNUSED
;
1620 return m16_check_op (op
, - 0x80, 0x7f, 0);
1624 m16_nsimm8_1 (op
, mode
)
1626 enum machine_mode mode ATTRIBUTE_UNUSED
;
1628 return m16_check_op (op
, - 0x7f, 0x80, 0);
1632 m16_uimm8_1 (op
, mode
)
1634 enum machine_mode mode ATTRIBUTE_UNUSED
;
1636 return m16_check_op (op
, 0x0, 0xff, 0);
1640 m16_nuimm8_1 (op
, mode
)
1642 enum machine_mode mode ATTRIBUTE_UNUSED
;
1644 return m16_check_op (op
, - 0xff, 0x0, 0);
1648 m16_uimm8_m1_1 (op
, mode
)
1650 enum machine_mode mode ATTRIBUTE_UNUSED
;
1652 return m16_check_op (op
, - 0x1, 0xfe, 0);
1656 m16_uimm8_4 (op
, mode
)
1658 enum machine_mode mode ATTRIBUTE_UNUSED
;
1660 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1664 m16_nuimm8_4 (op
, mode
)
1666 enum machine_mode mode ATTRIBUTE_UNUSED
;
1668 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1672 m16_simm8_8 (op
, mode
)
1674 enum machine_mode mode ATTRIBUTE_UNUSED
;
1676 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1680 m16_nsimm8_8 (op
, mode
)
1682 enum machine_mode mode ATTRIBUTE_UNUSED
;
1684 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1687 /* References to the string table on the mips16 only use a small
1688 offset if the function is small. See the comment in the SYMBOL_REF
1689 case in simple_memory_operand. We can't check for LABEL_REF here,
1690 because the offset is always large if the label is before the
1691 referencing instruction. */
1694 m16_usym8_4 (op
, mode
)
1696 enum machine_mode mode ATTRIBUTE_UNUSED
;
1698 if (GET_CODE (op
) == SYMBOL_REF
1699 && SYMBOL_REF_FLAG (op
)
1700 && current_frame_info
.insns_len
> 0
1701 && XSTR (op
, 0)[0] == '*'
1702 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1703 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1704 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1707 struct string_constant
*l
;
1709 /* Make sure this symbol is on thelist of string constants to be
1710 output for this function. It is possible that it has already
1711 been output, in which case this requires a large offset. */
1712 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1713 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1721 m16_usym5_4 (op
, mode
)
1723 enum machine_mode mode ATTRIBUTE_UNUSED
;
1725 if (GET_CODE (op
) == SYMBOL_REF
1726 && SYMBOL_REF_FLAG (op
)
1727 && current_frame_info
.insns_len
> 0
1728 && XSTR (op
, 0)[0] == '*'
1729 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1730 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1731 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1734 struct string_constant
*l
;
1736 /* Make sure this symbol is on thelist of string constants to be
1737 output for this function. It is possible that it has already
1738 been output, in which case this requires a large offset. */
1739 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1740 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1747 /* Returns an operand string for the given instruction's delay slot,
1748 after updating filled delay slot statistics.
1750 We assume that operands[0] is the target register that is set.
1752 In order to check the next insn, most of this functionality is moved
1753 to FINAL_PRESCAN_INSN, and we just set the global variables that
1756 /* ??? This function no longer does anything useful, because final_prescan_insn
1757 now will never emit a nop. */
1760 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1761 const char *ret
; /* normal string to return */
1762 enum delay_type type
; /* type of delay */
1763 rtx operands
[]; /* operands to use */
1764 rtx cur_insn
; /* current insn */
1766 register rtx set_reg
;
1767 register enum machine_mode mode
;
1768 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1769 register int num_nops
;
1771 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1774 else if (type
== DELAY_HILO
)
1780 /* Make sure that we don't put nop's after labels. */
1781 next_insn
= NEXT_INSN (cur_insn
);
1782 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1783 next_insn
= NEXT_INSN (next_insn
);
1785 dslots_load_total
+= num_nops
;
1786 if (TARGET_DEBUG_F_MODE
1788 || type
== DELAY_NONE
1792 || GET_CODE (next_insn
) == CODE_LABEL
1793 || (set_reg
= operands
[0]) == 0)
1795 dslots_number_nops
= 0;
1803 set_reg
= operands
[0];
1807 while (GET_CODE (set_reg
) == SUBREG
)
1808 set_reg
= SUBREG_REG (set_reg
);
1810 mode
= GET_MODE (set_reg
);
1811 dslots_number_nops
= num_nops
;
1812 mips_load_reg
= set_reg
;
1813 if (GET_MODE_SIZE (mode
)
1814 > (unsigned) (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1815 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1819 if (type
== DELAY_HILO
)
1821 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1822 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1834 /* Determine whether a memory reference takes one (based off of the GP
1835 pointer), two (normal), or three (label + reg) instructions, and bump the
1836 appropriate counter for -mstats. */
1839 mips_count_memory_refs (op
, num
)
1845 rtx addr
, plus0
, plus1
;
1846 enum rtx_code code0
, code1
;
1849 if (TARGET_DEBUG_B_MODE
)
1851 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1855 /* Skip MEM if passed, otherwise handle movsi of address. */
1856 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1858 /* Loop, going through the address RTL. */
1862 switch (GET_CODE (addr
))
1870 plus0
= XEXP (addr
, 0);
1871 plus1
= XEXP (addr
, 1);
1872 code0
= GET_CODE (plus0
);
1873 code1
= GET_CODE (plus1
);
1883 if (code0
== CONST_INT
)
1898 if (code1
== CONST_INT
)
1905 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1912 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1922 n_words
= 2; /* always 2 words */
1926 addr
= XEXP (addr
, 0);
1931 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1943 n_words
+= additional
;
1947 num_refs
[n_words
-1] += num
;
1951 /* Return a pseudo that points to the address of the current function.
1952 The first time it is called for a function, an initializer for the
1953 pseudo is emitted in the beginning of the function. */
1956 embedded_pic_fnaddr_reg ()
1958 if (cfun
->machine
->embedded_pic_fnaddr_rtx
== NULL
)
1962 cfun
->machine
->embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1964 /* Output code at function start to initialize the pseudo-reg. */
1965 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1966 inline functions, because it is called after RTL for the function
1967 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1968 does not get copied, and ends up not matching the rest of the RTL.
1969 This solution works, but means that we get unnecessary code to
1970 initialize this value every time a function is inlined into another
1973 emit_insn (gen_get_fnaddr (cfun
->machine
->embedded_pic_fnaddr_rtx
,
1974 XEXP (DECL_RTL (current_function_decl
), 0)));
1975 seq
= gen_sequence ();
1977 push_topmost_sequence ();
1978 emit_insn_after (seq
, get_insns ());
1979 pop_topmost_sequence ();
1982 return cfun
->machine
->embedded_pic_fnaddr_rtx
;
1985 /* Return RTL for the offset from the current function to the argument.
1986 X is the symbol whose offset from the current function we want. */
1989 embedded_pic_offset (x
)
1992 /* Make sure it is emitted. */
1993 embedded_pic_fnaddr_reg ();
1996 gen_rtx_CONST (Pmode
,
1997 gen_rtx_MINUS (Pmode
, x
,
1998 XEXP (DECL_RTL (current_function_decl
), 0)));
2001 /* Return the appropriate instructions to move one operand to another. */
2004 mips_move_1word (operands
, insn
, unsignedp
)
2009 const char *ret
= 0;
2010 rtx op0
= operands
[0];
2011 rtx op1
= operands
[1];
2012 enum rtx_code code0
= GET_CODE (op0
);
2013 enum rtx_code code1
= GET_CODE (op1
);
2014 enum machine_mode mode
= GET_MODE (op0
);
2015 int subreg_offset0
= 0;
2016 int subreg_offset1
= 0;
2017 enum delay_type delay
= DELAY_NONE
;
2019 while (code0
== SUBREG
)
2021 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2022 GET_MODE (SUBREG_REG (op0
)),
2025 op0
= SUBREG_REG (op0
);
2026 code0
= GET_CODE (op0
);
2029 while (code1
== SUBREG
)
2031 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2032 GET_MODE (SUBREG_REG (op1
)),
2035 op1
= SUBREG_REG (op1
);
2036 code1
= GET_CODE (op1
);
2039 /* For our purposes, a condition code mode is the same as SImode. */
2045 int regno0
= REGNO (op0
) + subreg_offset0
;
2049 int regno1
= REGNO (op1
) + subreg_offset1
;
2051 /* Just in case, don't do anything for assigning a register
2052 to itself, unless we are filling a delay slot. */
2053 if (regno0
== regno1
&& set_nomacro
== 0)
2056 else if (GP_REG_P (regno0
))
2058 if (GP_REG_P (regno1
))
2059 ret
= "move\t%0,%1";
2061 else if (MD_REG_P (regno1
))
2064 if (regno1
!= HILO_REGNUM
)
2070 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
2071 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
2076 if (FP_REG_P (regno1
))
2077 ret
= "mfc1\t%0,%1";
2078 else if (ALL_COP_REG_P (regno1
))
2080 static char retval
[] = "mfc_\t%0,%1";
2082 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2085 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2086 ret
= "cfc1\t%0,$31";
2090 else if (FP_REG_P (regno0
))
2092 if (GP_REG_P (regno1
))
2095 ret
= "mtc1\t%1,%0";
2098 if (FP_REG_P (regno1
))
2099 ret
= "mov.s\t%0,%1";
2102 else if (MD_REG_P (regno0
))
2104 if (GP_REG_P (regno1
))
2107 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
2112 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2114 if (GP_REG_P (regno1
))
2117 ret
= "ctc1\t%0,$31";
2120 else if (ALL_COP_REG_P (regno0
))
2122 if (GP_REG_P (regno1
))
2124 static char retval
[] = "mtc_\t%1,%0";
2125 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2128 abort_with_insn (insn
,
2129 "mtc0 not supported; it disturbs virtual address translation");
2137 else if (code1
== MEM
)
2142 mips_count_memory_refs (op1
, 1);
2144 if (GP_REG_P (regno0
))
2146 /* For loads, use the mode of the memory item, instead of the
2147 target, so zero/sign extend can use this code as well. */
2148 switch (GET_MODE (op1
))
2157 ret
= ((unsignedp
&& TARGET_64BIT
)
2162 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
2165 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
2170 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
2173 else if (ALL_COP_REG_P (regno0
))
2175 static char retval
[] = "lwc_\t%0,%1";
2176 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2179 abort_with_insn (insn
,
2180 "loads from memory to COP0 are illegal");
2186 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
2188 size_t i
= strlen (ret
);
2189 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2192 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2193 ret
= volatile_buffer
;
2197 else if (code1
== CONST_INT
2198 || (code1
== CONST_DOUBLE
2199 && GET_MODE (op1
) == VOIDmode
))
2201 if (code1
== CONST_DOUBLE
)
2203 /* This can happen when storing constants into long long
2204 bitfields. Just store the least significant word of
2206 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2209 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2211 if (GP_REG_P (regno0
))
2212 ret
= "move\t%0,%z1";
2214 else if (FP_REG_P (regno0
))
2217 ret
= "mtc1\t%z1,%0";
2220 else if (MD_REG_P (regno0
))
2227 else if (GP_REG_P (regno0
))
2229 /* Don't use X format, because that will give out of
2230 range numbers for 64 bit host and 32 bit target. */
2231 if (! TARGET_MIPS16
)
2232 ret
= "li\t%0,%1\t\t\t# %X1";
2235 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2237 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2238 ret
= "li\t%0,%n1\n\tneg\t%0";
2243 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
2245 if (op1
== CONST0_RTX (SFmode
))
2247 if (GP_REG_P (regno0
))
2248 ret
= "move\t%0,%.";
2250 else if (FP_REG_P (regno0
))
2253 ret
= "mtc1\t%.,%0";
2260 ret
= "li.s\t%0,%1";
2264 else if (code1
== LABEL_REF
)
2267 mips_count_memory_refs (op1
, 1);
2272 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2274 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
2276 rtx offset
= const0_rtx
;
2278 if (GET_CODE (op1
) == CONST
)
2279 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
2281 if (GET_CODE (op1
) == SYMBOL_REF
)
2283 operands
[2] = HALF_PIC_PTR (op1
);
2286 mips_count_memory_refs (operands
[2], 1);
2288 if (INTVAL (offset
) == 0)
2291 ret
= (unsignedp
&& TARGET_64BIT
2297 dslots_load_total
++;
2298 operands
[3] = offset
;
2299 if (unsignedp
&& TARGET_64BIT
)
2300 ret
= (SMALL_INT (offset
)
2301 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2302 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2304 ret
= (SMALL_INT (offset
)
2305 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2306 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2310 else if (TARGET_MIPS16
2312 && GET_CODE (XEXP (op1
, 0)) == REG
2313 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2315 /* This case arises on the mips16; see
2316 mips16_gp_pseudo_reg. */
2317 ret
= "move\t%0,%+";
2319 else if (TARGET_MIPS16
2320 && code1
== SYMBOL_REF
2321 && SYMBOL_REF_FLAG (op1
)
2322 && (XSTR (op1
, 0)[0] != '*'
2323 || strncmp (XSTR (op1
, 0) + 1,
2325 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2327 /* This can occur when reloading the address of a GP
2328 relative symbol on the mips16. */
2329 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2334 mips_count_memory_refs (op1
, 1);
2340 else if (code1
== PLUS
)
2342 rtx add_op0
= XEXP (op1
, 0);
2343 rtx add_op1
= XEXP (op1
, 1);
2345 if (GET_CODE (XEXP (op1
, 1)) == REG
2346 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
2347 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
2349 operands
[2] = add_op0
;
2350 operands
[3] = add_op1
;
2351 ret
= "add%:\t%0,%2,%3";
2354 else if (code1
== HIGH
)
2356 operands
[1] = XEXP (op1
, 0);
2357 ret
= "lui\t%0,%%hi(%1)";
2361 else if (code0
== MEM
)
2364 mips_count_memory_refs (op0
, 1);
2368 int regno1
= REGNO (op1
) + subreg_offset1
;
2370 if (GP_REG_P (regno1
))
2374 case SFmode
: ret
= "sw\t%1,%0"; break;
2375 case SImode
: ret
= "sw\t%1,%0"; break;
2376 case HImode
: ret
= "sh\t%1,%0"; break;
2377 case QImode
: ret
= "sb\t%1,%0"; break;
2382 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2384 else if (ALL_COP_REG_P (regno1
))
2386 static char retval
[] = "swc_\t%1,%0";
2388 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2393 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2397 case SFmode
: ret
= "sw\t%z1,%0"; break;
2398 case SImode
: ret
= "sw\t%z1,%0"; break;
2399 case HImode
: ret
= "sh\t%z1,%0"; break;
2400 case QImode
: ret
= "sb\t%z1,%0"; break;
2405 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2409 case SFmode
: ret
= "sw\t%.,%0"; break;
2410 case SImode
: ret
= "sw\t%.,%0"; break;
2411 case HImode
: ret
= "sh\t%.,%0"; break;
2412 case QImode
: ret
= "sb\t%.,%0"; break;
2417 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2419 size_t i
= strlen (ret
);
2421 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2424 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2425 ret
= volatile_buffer
;
2431 abort_with_insn (insn
, "bad move");
2435 if (delay
!= DELAY_NONE
)
2436 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2442 /* Return the appropriate instructions to move 2 words */
2445 mips_move_2words (operands
, insn
)
2449 const char *ret
= 0;
2450 rtx op0
= operands
[0];
2451 rtx op1
= operands
[1];
2452 enum rtx_code code0
= GET_CODE (operands
[0]);
2453 enum rtx_code code1
= GET_CODE (operands
[1]);
2454 int subreg_offset0
= 0;
2455 int subreg_offset1
= 0;
2456 enum delay_type delay
= DELAY_NONE
;
2458 while (code0
== SUBREG
)
2460 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2461 GET_MODE (SUBREG_REG (op0
)),
2464 op0
= SUBREG_REG (op0
);
2465 code0
= GET_CODE (op0
);
2468 if (code1
== SIGN_EXTEND
)
2470 op1
= XEXP (op1
, 0);
2471 code1
= GET_CODE (op1
);
2474 while (code1
== SUBREG
)
2476 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2477 GET_MODE (SUBREG_REG (op1
)),
2480 op1
= SUBREG_REG (op1
);
2481 code1
= GET_CODE (op1
);
2485 if (GET_CODE (operands
[1]) == SIGN_EXTEND
2487 && code1
!= CONST_INT
2488 /* The following three can happen as the result of a questionable
2490 && code1
!= LABEL_REF
2491 && code1
!= SYMBOL_REF
2497 int regno0
= REGNO (op0
) + subreg_offset0
;
2501 int regno1
= REGNO (op1
) + subreg_offset1
;
2503 /* Just in case, don't do anything for assigning a register
2504 to itself, unless we are filling a delay slot. */
2505 if (regno0
== regno1
&& set_nomacro
== 0)
2508 else if (FP_REG_P (regno0
))
2510 if (FP_REG_P (regno1
))
2511 ret
= "mov.d\t%0,%1";
2519 abort_with_insn (insn
, "bad move");
2521 #ifdef TARGET_FP_CALL_32
2522 if (FP_CALL_GP_REG_P (regno1
))
2523 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2526 ret
= "dmtc1\t%1,%0";
2529 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2533 else if (FP_REG_P (regno1
))
2539 abort_with_insn (insn
, "bad move");
2541 #ifdef TARGET_FP_CALL_32
2542 if (FP_CALL_GP_REG_P (regno0
))
2543 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2546 ret
= "dmfc1\t%0,%1";
2549 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2552 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2557 if (regno0
!= HILO_REGNUM
)
2559 else if (regno1
== 0)
2560 ret
= "mtlo\t%.\n\tmthi\t%.";
2563 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2566 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2571 if (regno1
!= HILO_REGNUM
)
2575 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2577 else if (GP_REG_P (regno0
) && ALL_COP_REG_P (regno1
)
2580 static char retval
[] = "dmfc_\t%0,%1";
2583 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2586 else if (ALL_COP_REG_P (regno0
) && GP_REG_P (regno1
)
2589 static char retval
[] = "dmtc_\t%1,%0";
2590 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2593 abort_with_insn (insn
,
2594 "dmtc0 not supported; it disturbs virtual address translation");
2599 else if (TARGET_64BIT
)
2600 ret
= "move\t%0,%1";
2602 else if (regno0
!= (regno1
+1))
2603 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2606 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2609 else if (code1
== CONST_DOUBLE
)
2611 /* Move zero from $0 unless !TARGET_64BIT and recipient
2612 is 64-bit fp reg, in which case generate a constant. */
2613 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2614 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2616 if (GET_MODE (op1
) == DFmode
)
2620 #ifdef TARGET_FP_CALL_32
2621 if (FP_CALL_GP_REG_P (regno0
))
2623 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2625 split_double (op1
, operands
+ 2, operands
+ 3);
2626 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2629 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2633 /* GNU as emits 64-bit code for li.d if the ISA is 3
2634 or higher. For !TARGET_64BIT && gp registers we
2635 need to avoid this by using two li instructions
2637 if (ISA_HAS_64BIT_REGS
2639 && ! FP_REG_P (regno0
))
2641 split_double (op1
, operands
+ 2, operands
+ 3);
2642 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2645 ret
= "li.d\t%0,%1";
2648 else if (TARGET_64BIT
)
2650 if (! TARGET_MIPS16
)
2656 split_double (op1
, operands
+ 2, operands
+ 3);
2657 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2663 if (GP_REG_P (regno0
))
2665 #ifdef TARGET_FP_CALL_32
2666 && ! FP_CALL_GP_REG_P (regno0
)
2669 : "move\t%0,%.\n\tmove\t%D0,%.");
2671 else if (FP_REG_P (regno0
))
2676 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2681 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2683 if (GP_REG_P (regno0
))
2686 : "move\t%0,%.\n\tmove\t%D0,%.");
2688 else if (FP_REG_P (regno0
))
2695 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2697 else if (MD_REG_P (regno0
))
2700 ret
= (regno0
== HILO_REGNUM
2701 ? "mtlo\t%.\n\tmthi\t%."
2706 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2707 && GP_REG_P (regno0
))
2713 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2715 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2716 ret
= "li\t%0,%n1\n\tneg\t%0";
2718 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2719 ret
= "li\t%0,%1\t\t# %X1";
2720 else if (HOST_BITS_PER_WIDE_INT
< 64)
2721 /* We can't use 'X' for negative numbers, because then we won't
2722 get the right value for the upper 32 bits. */
2723 ret
= (INTVAL (op1
) < 0
2724 ? "dli\t%0,%1\t\t\t# %X1"
2725 : "dli\t%0,%X1\t\t# %1");
2727 /* We must use 'X', because otherwise LONG_MIN will print as
2728 a number that the assembler won't accept. */
2729 ret
= "dli\t%0,%X1\t\t# %1";
2731 else if (HOST_BITS_PER_WIDE_INT
< 64)
2733 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2736 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2737 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2738 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2740 operands
[2] = GEN_INT (1);
2741 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2745 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2749 /* We use multiple shifts here, to avoid warnings about out
2750 of range shifts on 32 bit hosts. */
2751 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2753 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2756 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2757 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2758 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2760 operands
[2] = GEN_INT (1);
2761 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2765 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2769 else if (code1
== MEM
)
2774 mips_count_memory_refs (op1
, 2);
2776 if (FP_REG_P (regno0
))
2779 else if (ALL_COP_REG_P (regno0
) && TARGET_64BIT
)
2781 static char retval
[] = "ldc_\t%0,%1";
2782 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2785 abort_with_insn (insn
,
2786 "loads from memory to COP0 are illegal");
2792 else if (TARGET_64BIT
)
2795 #ifdef TARGET_FP_CALL_32
2796 if (FP_CALL_GP_REG_P (regno0
))
2797 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2798 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2799 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2805 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2806 ret
= (reg_mentioned_p (op0
, op1
)
2807 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2808 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2810 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2812 size_t i
= strlen (ret
);
2814 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2817 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2818 ret
= volatile_buffer
;
2822 else if (code1
== LABEL_REF
)
2825 mips_count_memory_refs (op1
, 2);
2827 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2828 /* We deliberately remove the 'a' from '%1', so that we don't
2829 have to add SIGN_EXTEND support to print_operand_address.
2830 print_operand will just call print_operand_address in this
2831 case, so there is no problem. */
2834 ret
= "dla\t%0,%a1";
2836 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2840 && GET_CODE (XEXP (op1
, 0)) == REG
2841 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2843 /* This case arises on the mips16; see
2844 mips16_gp_pseudo_reg. */
2845 ret
= "move\t%0,%+";
2847 else if (TARGET_MIPS16
2848 && code1
== SYMBOL_REF
2849 && SYMBOL_REF_FLAG (op1
)
2850 && (XSTR (op1
, 0)[0] != '*'
2851 || strncmp (XSTR (op1
, 0) + 1,
2853 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2855 /* This can occur when reloading the address of a GP
2856 relative symbol on the mips16. */
2857 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2862 mips_count_memory_refs (op1
, 2);
2864 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2865 /* We deliberately remove the 'a' from '%1', so that we don't
2866 have to add SIGN_EXTEND support to print_operand_address.
2867 print_operand will just call print_operand_address in this
2868 case, so there is no problem. */
2871 ret
= "dla\t%0,%a1";
2876 else if (code0
== MEM
)
2880 int regno1
= REGNO (op1
) + subreg_offset1
;
2882 if (FP_REG_P (regno1
))
2885 else if (ALL_COP_REG_P (regno1
) && TARGET_64BIT
)
2887 static char retval
[] = "sdc_\t%1,%0";
2889 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2892 else if (TARGET_64BIT
)
2895 #ifdef TARGET_FP_CALL_32
2896 if (FP_CALL_GP_REG_P (regno1
))
2897 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2903 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2904 ret
= "sw\t%1,%0\n\tsw\t%D1,%D0";
2907 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2908 || (code1
== CONST_DOUBLE
2909 && op1
== CONST0_RTX (GET_MODE (op1
))))
2911 || double_memory_operand (op0
, GET_MODE (op0
))))
2916 ret
= "sw\t%.,%0\n\tsw\t%.,%D0";
2920 mips_count_memory_refs (op0
, 2);
2922 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2924 size_t i
= strlen (ret
);
2926 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2929 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2930 ret
= volatile_buffer
;
2936 abort_with_insn (insn
, "bad move");
2940 if (delay
!= DELAY_NONE
)
2941 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2946 /* Provide the costs of an addressing mode that contains ADDR.
2947 If ADDR is not a valid address, its cost is irrelevant. */
2950 mips_address_cost (addr
)
2953 switch (GET_CODE (addr
))
2963 rtx offset
= const0_rtx
;
2964 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
2965 if (GET_CODE (addr
) == LABEL_REF
)
2968 if (GET_CODE (addr
) != SYMBOL_REF
)
2971 if (! SMALL_INT (offset
))
2975 /* ... fall through ... */
2978 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
2982 register rtx plus0
= XEXP (addr
, 0);
2983 register rtx plus1
= XEXP (addr
, 1);
2985 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
2986 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
2988 if (GET_CODE (plus0
) != REG
)
2991 switch (GET_CODE (plus1
))
2994 return SMALL_INT (plus1
) ? 1 : 2;
3001 return mips_address_cost (plus1
) + 1;
3015 /* Return nonzero if X is an address which needs a temporary register when
3016 reloaded while generating PIC code. */
3019 pic_address_needs_scratch (x
)
3022 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3023 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3024 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3025 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3026 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3032 /* Make normal rtx_code into something we can index from an array */
3034 static enum internal_test
3035 map_test_to_internal_test (test_code
)
3036 enum rtx_code test_code
;
3038 enum internal_test test
= ITEST_MAX
;
3042 case EQ
: test
= ITEST_EQ
; break;
3043 case NE
: test
= ITEST_NE
; break;
3044 case GT
: test
= ITEST_GT
; break;
3045 case GE
: test
= ITEST_GE
; break;
3046 case LT
: test
= ITEST_LT
; break;
3047 case LE
: test
= ITEST_LE
; break;
3048 case GTU
: test
= ITEST_GTU
; break;
3049 case GEU
: test
= ITEST_GEU
; break;
3050 case LTU
: test
= ITEST_LTU
; break;
3051 case LEU
: test
= ITEST_LEU
; break;
3059 /* Generate the code to compare two integer values. The return value is:
3060 (reg:SI xx) The pseudo register the comparison is in
3061 0 No register, generate a simple branch.
3063 ??? This is called with result nonzero by the Scond patterns in
3064 mips.md. These patterns are called with a target in the mode of
3065 the Scond instruction pattern. Since this must be a constant, we
3066 must use SImode. This means that if RESULT is non-zero, it will
3067 always be an SImode register, even if TARGET_64BIT is true. We
3068 cope with this by calling convert_move rather than emit_move_insn.
3069 This will sometimes lead to an unnecessary extension of the result;
3081 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
3082 enum rtx_code test_code
; /* relational test (EQ, etc) */
3083 rtx result
; /* result to store comp. or 0 if branch */
3084 rtx cmp0
; /* first operand to compare */
3085 rtx cmp1
; /* second operand to compare */
3086 int *p_invert
; /* NULL or ptr to hold whether branch needs */
3087 /* to reverse its test */
3091 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
3092 int const_low
; /* low bound of constant we can accept */
3093 int const_high
; /* high bound of constant we can accept */
3094 int const_add
; /* constant to add (convert LE -> LT) */
3095 int reverse_regs
; /* reverse registers in test */
3096 int invert_const
; /* != 0 if invert value if cmp1 is constant */
3097 int invert_reg
; /* != 0 if invert value if cmp1 is register */
3098 int unsignedp
; /* != 0 for unsigned comparisons. */
3101 static const struct cmp_info info
[ (int)ITEST_MAX
] = {
3103 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3104 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3105 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3106 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3107 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3108 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3109 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3110 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3111 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3112 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3115 enum internal_test test
;
3116 enum machine_mode mode
;
3117 const struct cmp_info
*p_info
;
3124 test
= map_test_to_internal_test (test_code
);
3125 if (test
== ITEST_MAX
)
3128 p_info
= &info
[(int) test
];
3129 eqne_p
= (p_info
->test_code
== XOR
);
3131 mode
= GET_MODE (cmp0
);
3132 if (mode
== VOIDmode
)
3133 mode
= GET_MODE (cmp1
);
3135 /* Eliminate simple branches */
3136 branch_p
= (result
== 0);
3139 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
3141 /* Comparisons against zero are simple branches */
3142 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
3143 && (! TARGET_MIPS16
|| eqne_p
))
3146 /* Test for beq/bne. */
3147 if (eqne_p
&& ! TARGET_MIPS16
)
3151 /* allocate a pseudo to calculate the value in. */
3152 result
= gen_reg_rtx (mode
);
3155 /* Make sure we can handle any constants given to us. */
3156 if (GET_CODE (cmp0
) == CONST_INT
)
3157 cmp0
= force_reg (mode
, cmp0
);
3159 if (GET_CODE (cmp1
) == CONST_INT
)
3161 HOST_WIDE_INT value
= INTVAL (cmp1
);
3163 if (value
< p_info
->const_low
3164 || value
> p_info
->const_high
3165 /* ??? Why? And why wasn't the similar code below modified too? */
3167 && HOST_BITS_PER_WIDE_INT
< 64
3168 && p_info
->const_add
!= 0
3169 && ((p_info
->unsignedp
3170 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
3171 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
3172 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
3173 != (p_info
->const_add
> 0))))
3174 cmp1
= force_reg (mode
, cmp1
);
3177 /* See if we need to invert the result. */
3178 invert
= (GET_CODE (cmp1
) == CONST_INT
3179 ? p_info
->invert_const
: p_info
->invert_reg
);
3181 if (p_invert
!= (int *)0)
3187 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3188 Comparison between two registers, may involve switching operands. */
3189 if (GET_CODE (cmp1
) == CONST_INT
)
3191 if (p_info
->const_add
!= 0)
3193 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
3195 /* If modification of cmp1 caused overflow,
3196 we would get the wrong answer if we follow the usual path;
3197 thus, x > 0xffffffffU would turn into x > 0U. */
3198 if ((p_info
->unsignedp
3199 ? (unsigned HOST_WIDE_INT
) new >
3200 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
3201 : new > INTVAL (cmp1
))
3202 != (p_info
->const_add
> 0))
3204 /* This test is always true, but if INVERT is true then
3205 the result of the test needs to be inverted so 0 should
3206 be returned instead. */
3207 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
3211 cmp1
= GEN_INT (new);
3215 else if (p_info
->reverse_regs
)
3222 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
3226 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
3227 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
3230 if (test
== ITEST_NE
)
3232 if (! TARGET_MIPS16
)
3234 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
3235 if (p_invert
!= NULL
)
3241 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3242 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
3247 else if (test
== ITEST_EQ
)
3249 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3250 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
3258 if (! TARGET_MIPS16
)
3262 /* The value is in $24. Copy it to another register, so
3263 that reload doesn't think it needs to store the $24 and
3264 the input to the XOR in the same location. */
3265 reg2
= gen_reg_rtx (mode
);
3266 emit_move_insn (reg2
, reg
);
3268 one
= force_reg (mode
, const1_rtx
);
3270 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
3276 /* Emit the common code for doing conditional branches.
3277 operand[0] is the label to jump to.
3278 The comparison operands are saved away by cmp{si,di,sf,df}. */
3281 gen_conditional_branch (operands
, test_code
)
3283 enum rtx_code test_code
;
3285 enum cmp_type type
= branch_type
;
3286 rtx cmp0
= branch_cmp
[0];
3287 rtx cmp1
= branch_cmp
[1];
3288 enum machine_mode mode
;
3297 mode
= type
== CMP_SI
? SImode
: DImode
;
3299 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
3307 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
3308 /* We don't want to build a comparison against a non-zero
3310 cmp1
= force_reg (mode
, cmp1
);
3317 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
3319 reg
= gen_reg_rtx (CCmode
);
3321 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3322 0 in the instruction built below. The MIPS FPU handles
3323 inequality testing by testing for equality and looking for a
3325 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3326 gen_rtx (test_code
== NE
? EQ
: test_code
,
3327 CCmode
, cmp0
, cmp1
)));
3329 test_code
= test_code
== NE
? EQ
: NE
;
3337 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
3340 /* Generate the branch. */
3342 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
3351 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3352 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3353 gen_rtx (test_code
, mode
,
3358 /* Emit the common code for conditional moves. OPERANDS is the array
3359 of operands passed to the conditional move defined_expand. */
3362 gen_conditional_move (operands
)
3365 rtx op0
= branch_cmp
[0];
3366 rtx op1
= branch_cmp
[1];
3367 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3368 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
3369 enum rtx_code move_code
= NE
;
3370 enum machine_mode op_mode
= GET_MODE (operands
[0]);
3371 enum machine_mode cmp_mode
;
3374 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3393 op0
= force_reg (mode
, branch_cmp
[1]);
3394 op1
= branch_cmp
[0];
3398 op0
= force_reg (mode
, branch_cmp
[1]);
3399 op1
= branch_cmp
[0];
3410 op0
= force_reg (mode
, branch_cmp
[1]);
3411 op1
= branch_cmp
[0];
3415 op0
= force_reg (mode
, branch_cmp
[1]);
3416 op1
= branch_cmp
[0];
3423 else if (cmp_code
== NE
)
3424 cmp_code
= EQ
, move_code
= EQ
;
3426 if (mode
== SImode
|| mode
== DImode
)
3428 else if (mode
== SFmode
|| mode
== DFmode
)
3433 cmp_reg
= gen_reg_rtx (cmp_mode
);
3434 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
3435 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
3437 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
3438 gen_rtx_IF_THEN_ELSE (op_mode
,
3439 gen_rtx (move_code
, VOIDmode
,
3441 CONST0_RTX (SImode
)),
3442 operands
[2], operands
[3])));
3445 /* Emit the common code for conditional moves. OPERANDS is the array
3446 of operands passed to the conditional move defined_expand. */
3449 mips_gen_conditional_trap (operands
)
3453 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3454 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3456 /* MIPS conditional trap machine instructions don't have GT or LE
3457 flavors, so we must invert the comparison and convert to LT and
3458 GE, respectively. */
3461 case GT
: cmp_code
= LT
; break;
3462 case LE
: cmp_code
= GE
; break;
3463 case GTU
: cmp_code
= LTU
; break;
3464 case LEU
: cmp_code
= GEU
; break;
3467 if (cmp_code
== GET_CODE (operands
[0]))
3469 op0
= force_reg (mode
, branch_cmp
[0]);
3470 op1
= branch_cmp
[1];
3474 op0
= force_reg (mode
, branch_cmp
[1]);
3475 op1
= branch_cmp
[0];
3477 if (GET_CODE (op1
) == CONST_INT
&& ! SMALL_INT (op1
))
3478 op1
= force_reg (mode
, op1
);
3480 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3481 gen_rtx (cmp_code
, GET_MODE (operands
[0]), op0
, op1
),
3485 /* Write a loop to move a constant number of bytes.
3486 Generate load/stores as follows:
3492 temp<last> = src[MAX_MOVE_REGS-1];
3496 dest[MAX_MOVE_REGS-1] = temp<last>;
3497 src += MAX_MOVE_REGS;
3498 dest += MAX_MOVE_REGS;
3499 } while (src != final);
3501 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3502 registers are needed.
3504 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3505 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3506 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3508 #define MAX_MOVE_REGS 4
3509 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3512 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3513 rtx dest_reg
; /* register holding destination address */
3514 rtx src_reg
; /* register holding source address */
3515 unsigned int bytes
; /* # bytes to move */
3516 int align
; /* alignment */
3517 rtx orig_dest
; /* original dest */
3518 rtx orig_src
; /* original source for making a reg note */
3520 rtx dest_mem
= replace_equiv_address (orig_dest
, dest_reg
);
3521 rtx src_mem
= replace_equiv_address (orig_src
, src_reg
);
3522 rtx align_rtx
= GEN_INT (align
);
3528 if (bytes
< (unsigned)2 * MAX_MOVE_BYTES
)
3531 leftover
= bytes
% MAX_MOVE_BYTES
;
3534 label
= gen_label_rtx ();
3535 final_src
= gen_reg_rtx (Pmode
);
3536 bytes_rtx
= GEN_INT (bytes
);
3540 if (Pmode
== DImode
)
3542 emit_insn (gen_movdi (final_src
, bytes_rtx
));
3543 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
3547 emit_insn (gen_movsi (final_src
, bytes_rtx
));
3548 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
3553 if (Pmode
== DImode
)
3554 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
3556 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
3561 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
3562 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
3564 if (Pmode
== DImode
)
3566 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
3567 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
3568 emit_insn (gen_cmpdi (src_reg
, final_src
));
3572 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
3573 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
3574 emit_insn (gen_cmpsi (src_reg
, final_src
));
3577 emit_jump_insn (gen_bne (label
));
3580 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
3584 /* Use a library function to move some bytes. */
3587 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
3592 /* We want to pass the size as Pmode, which will normally be SImode
3593 but will be DImode if we are using 64 bit longs and pointers. */
3594 if (GET_MODE (bytes_rtx
) != VOIDmode
3595 && GET_MODE (bytes_rtx
) != (unsigned) Pmode
)
3596 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
3598 #ifdef TARGET_MEM_FUNCTIONS
3599 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
3600 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
3601 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
3602 TREE_UNSIGNED (sizetype
)),
3603 TYPE_MODE (sizetype
));
3605 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
3606 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
3607 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
3608 TREE_UNSIGNED (integer_type_node
)),
3609 TYPE_MODE (integer_type_node
));
3613 /* Expand string/block move operations.
3615 operands[0] is the pointer to the destination.
3616 operands[1] is the pointer to the source.
3617 operands[2] is the number of bytes to move.
3618 operands[3] is the alignment. */
3621 expand_block_move (operands
)
3624 rtx bytes_rtx
= operands
[2];
3625 rtx align_rtx
= operands
[3];
3626 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
3627 unsigned HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
3628 unsigned int align
= INTVAL (align_rtx
);
3629 rtx orig_src
= operands
[1];
3630 rtx orig_dest
= operands
[0];
3634 if (constp
&& bytes
== 0)
3637 if (align
> (unsigned) UNITS_PER_WORD
)
3638 align
= UNITS_PER_WORD
;
3640 /* Move the address into scratch registers. */
3641 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
3642 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
3645 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3647 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
3648 && align
== (unsigned) UNITS_PER_WORD
)
3649 move_by_pieces (orig_dest
, orig_src
, bytes
, align
* BITS_PER_WORD
);
3651 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
)
3652 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3654 replace_equiv_address (orig_src
,
3656 bytes_rtx
, align_rtx
));
3658 else if (constp
&& align
>= (unsigned) UNITS_PER_WORD
&& optimize
)
3659 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
3661 else if (constp
&& optimize
)
3663 /* If the alignment is not word aligned, generate a test at
3664 runtime, to see whether things wound up aligned, and we
3665 can use the faster lw/sw instead ulw/usw. */
3667 rtx temp
= gen_reg_rtx (Pmode
);
3668 rtx aligned_label
= gen_label_rtx ();
3669 rtx join_label
= gen_label_rtx ();
3670 int leftover
= bytes
% MAX_MOVE_BYTES
;
3674 if (Pmode
== DImode
)
3676 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
3677 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3678 emit_insn (gen_cmpdi (temp
, const0_rtx
));
3682 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
3683 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3684 emit_insn (gen_cmpsi (temp
, const0_rtx
));
3687 emit_jump_insn (gen_beq (aligned_label
));
3689 /* Unaligned loop. */
3690 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
3691 emit_jump_insn (gen_jump (join_label
));
3695 emit_label (aligned_label
);
3696 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
3698 emit_label (join_label
);
3700 /* Bytes at the end of the loop. */
3702 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3704 replace_equiv_address (orig_src
,
3711 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3714 /* Emit load/stores for a small constant block_move.
3716 operands[0] is the memory address of the destination.
3717 operands[1] is the memory address of the source.
3718 operands[2] is the number of bytes to move.
3719 operands[3] is the alignment.
3720 operands[4] is a temp register.
3721 operands[5] is a temp register.
3723 operands[3+num_regs] is the last temp register.
3725 The block move type can be one of the following:
3726 BLOCK_MOVE_NORMAL Do all of the block move.
3727 BLOCK_MOVE_NOT_LAST Do all but the last store.
3728 BLOCK_MOVE_LAST Do just the last store. */
3731 output_block_move (insn
, operands
, num_regs
, move_type
)
3735 enum block_move_type move_type
;
3737 rtx dest_reg
= XEXP (operands
[0], 0);
3738 rtx src_reg
= XEXP (operands
[1], 0);
3739 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
3740 int align
= INTVAL (operands
[3]);
3743 int use_lwl_lwr
= 0;
3744 int last_operand
= num_regs
+ 4;
3750 const char *load
; /* load insn without nop */
3751 const char *load_nop
; /* load insn with trailing nop */
3752 const char *store
; /* store insn */
3753 const char *final
; /* if last_store used: NULL or swr */
3754 const char *last_store
; /* last store instruction */
3755 int offset
; /* current offset */
3756 enum machine_mode mode
; /* mode to use on (MEM) */
3759 /* ??? Detect a bug in GCC, where it can give us a register
3760 the same as one of the addressing registers and reduce
3761 the number of registers available. */
3762 for (i
= 4; i
< last_operand
&& safe_regs
< (int) ARRAY_SIZE (xoperands
); i
++)
3763 if (! reg_mentioned_p (operands
[i
], operands
[0])
3764 && ! reg_mentioned_p (operands
[i
], operands
[1]))
3765 xoperands
[safe_regs
++] = operands
[i
];
3767 if (safe_regs
< last_operand
)
3769 xoperands
[0] = operands
[0];
3770 xoperands
[1] = operands
[1];
3771 xoperands
[2] = operands
[2];
3772 xoperands
[3] = operands
[3];
3773 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
3776 /* If we are given global or static addresses, and we would be
3777 emitting a few instructions, try to save time by using a
3778 temporary register for the pointer. */
3779 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3780 an ldl/ldr instruction pair. We play it safe, and always move
3781 constant addresses into registers when generating N32/N64 code, just
3782 in case we might emit an unaligned load instruction. */
3783 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
3784 || mips_abi
== ABI_MEABI
3785 || mips_abi
== ABI_N32
3786 || mips_abi
== ABI_64
))
3788 if (CONSTANT_P (src_reg
))
3791 mips_count_memory_refs (operands
[1], 1);
3793 src_reg
= operands
[3 + num_regs
--];
3794 if (move_type
!= BLOCK_MOVE_LAST
)
3796 xoperands
[1] = operands
[1];
3797 xoperands
[0] = src_reg
;
3798 if (Pmode
== DImode
)
3799 output_asm_insn ("dla\t%0,%1", xoperands
);
3801 output_asm_insn ("la\t%0,%1", xoperands
);
3805 if (CONSTANT_P (dest_reg
))
3808 mips_count_memory_refs (operands
[0], 1);
3810 dest_reg
= operands
[3 + num_regs
--];
3811 if (move_type
!= BLOCK_MOVE_LAST
)
3813 xoperands
[1] = operands
[0];
3814 xoperands
[0] = dest_reg
;
3815 if (Pmode
== DImode
)
3816 output_asm_insn ("dla\t%0,%1", xoperands
);
3818 output_asm_insn ("la\t%0,%1", xoperands
);
3823 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3824 are not offsettable, however, offsettable_address_p says they are
3825 offsettable. I think this is a bug in offsettable_address_p.
3826 For expediency, we fix this by just loading the address into a register
3827 if we happen to get one. */
3829 if (GET_CODE (src_reg
) == LO_SUM
)
3831 src_reg
= operands
[3 + num_regs
--];
3832 if (move_type
!= BLOCK_MOVE_LAST
)
3834 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
3835 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3836 xoperands
[0] = src_reg
;
3837 if (Pmode
== DImode
)
3838 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3840 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3844 if (GET_CODE (dest_reg
) == LO_SUM
)
3846 dest_reg
= operands
[3 + num_regs
--];
3847 if (move_type
!= BLOCK_MOVE_LAST
)
3849 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
3850 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
3851 xoperands
[0] = dest_reg
;
3852 if (Pmode
== DImode
)
3853 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3855 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3859 if (num_regs
> (int) ARRAY_SIZE (load_store
))
3860 num_regs
= ARRAY_SIZE (load_store
);
3862 else if (num_regs
< 1)
3863 abort_with_insn (insn
,
3864 "cannot do block move, not enough scratch registers");
3868 load_store
[num
].offset
= offset
;
3870 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
3872 load_store
[num
].load
= "ld\t%0,%1";
3873 load_store
[num
].load_nop
= "ld\t%0,%1%#";
3874 load_store
[num
].store
= "sd\t%0,%1";
3875 load_store
[num
].last_store
= "sd\t%0,%1";
3876 load_store
[num
].final
= 0;
3877 load_store
[num
].mode
= DImode
;
3882 /* ??? Fails because of a MIPS assembler bug? */
3883 else if (TARGET_64BIT
&& bytes
>= 8 && ! TARGET_MIPS16
)
3885 if (BYTES_BIG_ENDIAN
)
3887 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
3888 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
3889 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
3890 load_store
[num
].last_store
= "sdr\t%0,%2";
3891 load_store
[num
].final
= "sdl\t%0,%1";
3895 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
3896 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
3897 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
3898 load_store
[num
].last_store
= "sdr\t%0,%1";
3899 load_store
[num
].final
= "sdl\t%0,%2";
3902 load_store
[num
].mode
= DImode
;
3908 else if (bytes
>= 4 && align
>= 4)
3910 load_store
[num
].load
= "lw\t%0,%1";
3911 load_store
[num
].load_nop
= "lw\t%0,%1%#";
3912 load_store
[num
].store
= "sw\t%0,%1";
3913 load_store
[num
].last_store
= "sw\t%0,%1";
3914 load_store
[num
].final
= 0;
3915 load_store
[num
].mode
= SImode
;
3920 else if (bytes
>= 4 && ! TARGET_MIPS16
)
3922 if (BYTES_BIG_ENDIAN
)
3924 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
3925 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3926 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
3927 load_store
[num
].last_store
= "swr\t%0,%2";
3928 load_store
[num
].final
= "swl\t%0,%1";
3932 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
3933 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3934 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
3935 load_store
[num
].last_store
= "swr\t%0,%1";
3936 load_store
[num
].final
= "swl\t%0,%2";
3939 load_store
[num
].mode
= SImode
;
3945 else if (bytes
>= 2 && align
>= 2)
3947 load_store
[num
].load
= "lh\t%0,%1";
3948 load_store
[num
].load_nop
= "lh\t%0,%1%#";
3949 load_store
[num
].store
= "sh\t%0,%1";
3950 load_store
[num
].last_store
= "sh\t%0,%1";
3951 load_store
[num
].final
= 0;
3952 load_store
[num
].mode
= HImode
;
3958 load_store
[num
].load
= "lb\t%0,%1";
3959 load_store
[num
].load_nop
= "lb\t%0,%1%#";
3960 load_store
[num
].store
= "sb\t%0,%1";
3961 load_store
[num
].last_store
= "sb\t%0,%1";
3962 load_store
[num
].final
= 0;
3963 load_store
[num
].mode
= QImode
;
3968 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3970 dslots_load_total
++;
3971 dslots_load_filled
++;
3973 if (CONSTANT_P (src_reg
))
3974 mips_count_memory_refs (src_reg
, 1);
3976 if (CONSTANT_P (dest_reg
))
3977 mips_count_memory_refs (dest_reg
, 1);
3980 /* Emit load/stores now if we have run out of registers or are
3981 at the end of the move. */
3983 if (++num
== num_regs
|| bytes
== 0)
3985 /* If only load/store, we need a NOP after the load. */
3988 load_store
[0].load
= load_store
[0].load_nop
;
3989 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3990 dslots_load_filled
--;
3993 if (move_type
!= BLOCK_MOVE_LAST
)
3995 for (i
= 0; i
< num
; i
++)
3999 if (!operands
[i
+ 4])
4002 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
4003 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
4004 REGNO (operands
[i
+ 4]));
4006 offset
= load_store
[i
].offset
;
4007 xoperands
[0] = operands
[i
+ 4];
4008 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4009 plus_constant (src_reg
, offset
));
4014 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4016 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4017 plus_constant (src_reg
,
4022 output_asm_insn (load_store
[i
].load
, xoperands
);
4026 for (i
= 0; i
< num
; i
++)
4028 int last_p
= (i
== num
-1 && bytes
== 0);
4029 int offset
= load_store
[i
].offset
;
4031 xoperands
[0] = operands
[i
+ 4];
4032 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4033 plus_constant (dest_reg
, offset
));
4038 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4039 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4040 plus_constant (dest_reg
,
4045 if (move_type
== BLOCK_MOVE_NORMAL
)
4046 output_asm_insn (load_store
[i
].store
, xoperands
);
4048 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
4051 output_asm_insn (load_store
[i
].store
, xoperands
);
4053 else if (load_store
[i
].final
!= 0)
4054 output_asm_insn (load_store
[i
].final
, xoperands
);
4058 output_asm_insn (load_store
[i
].last_store
, xoperands
);
4061 num
= 0; /* reset load_store */
4069 /* Argument support functions. */
4071 /* Initialize CUMULATIVE_ARGS for a function. */
4074 init_cumulative_args (cum
, fntype
, libname
)
4075 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
4076 tree fntype
; /* tree ptr for function decl */
4077 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
4079 static CUMULATIVE_ARGS zero_cum
;
4080 tree param
, next_param
;
4082 if (TARGET_DEBUG_E_MODE
)
4085 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
4088 fputc ('\n', stderr
);
4092 tree ret_type
= TREE_TYPE (fntype
);
4093 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
4094 tree_code_name
[(int)TREE_CODE (fntype
)],
4095 tree_code_name
[(int)TREE_CODE (ret_type
)]);
4100 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4102 /* Determine if this function has variable arguments. This is
4103 indicated by the last argument being 'void_type_mode' if there
4104 are no variable arguments. The standard MIPS calling sequence
4105 passes all arguments in the general purpose registers in this case. */
4107 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
4108 param
!= 0; param
= next_param
)
4110 next_param
= TREE_CHAIN (param
);
4111 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
4112 cum
->gp_reg_found
= 1;
4117 mips_arg_info (cum
, mode
, type
, named
, info
)
4118 const CUMULATIVE_ARGS
*cum
;
4119 enum machine_mode mode
;
4122 struct mips_arg_info
*info
;
4125 unsigned int num_words
, max_regs
;
4127 info
->struct_p
= (type
!= 0
4128 && (TREE_CODE (type
) == RECORD_TYPE
4129 || TREE_CODE (type
) == UNION_TYPE
4130 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
4132 /* Decide whether this argument should go in a floating-point register,
4133 assuming one is free. Later code checks for availablity. */
4135 info
->fpr_p
= false;
4136 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4137 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
4143 info
->fpr_p
= (!cum
->gp_reg_found
&& cum
->arg_number
< 2);
4151 /* The MIPS eabi says only structures containing doubles get
4152 passed in a fp register, so force a structure containing
4153 a float to be passed in the integer registers. */
4154 info
->fpr_p
= (named
&& !(mode
== SFmode
&& info
->struct_p
));
4158 info
->fpr_p
= named
;
4163 /* Now decide whether the argument must go in an even-numbered register. */
4168 /* Under the O64 ABI, the second float argument goes in $f13 if it
4169 is a double, but $f14 if it is a single. Otherwise, on a
4170 32-bit double-float machine, each FP argument must start in a
4171 new register pair. */
4172 even_reg_p
= ((mips_abi
== ABI_O64
&& mode
== SFmode
) || FP_INC
> 1);
4174 else if (!TARGET_64BIT
)
4176 if (GET_MODE_CLASS (mode
) == MODE_INT
4177 || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4178 even_reg_p
= (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
);
4180 else if (type
!= NULL_TREE
&& TYPE_ALIGN (type
) > BITS_PER_WORD
)
4184 /* Set REG_OFFSET to the register count we're interested in.
4185 The EABI allocates the floating-point registers separately,
4186 but the other ABIs allocate them like integer registers. */
4187 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4192 info
->reg_offset
+= info
->reg_offset
& 1;
4194 /* The alignment applied to registers is also applied to stack arguments. */
4195 info
->stack_offset
= cum
->stack_words
;
4197 info
->stack_offset
+= info
->stack_offset
& 1;
4199 if (mode
== BLKmode
)
4200 info
->num_bytes
= int_size_in_bytes (type
);
4202 info
->num_bytes
= GET_MODE_SIZE (mode
);
4204 num_words
= (info
->num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4205 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4207 /* Partition the argument between registers and stack. */
4208 info
->reg_words
= MIN (num_words
, max_regs
);
4209 info
->stack_words
= num_words
- info
->reg_words
;
4213 /* Advance the argument to the next argument position. */
4216 function_arg_advance (cum
, mode
, type
, named
)
4217 CUMULATIVE_ARGS
*cum
; /* current arg information */
4218 enum machine_mode mode
; /* current arg mode */
4219 tree type
; /* type of the argument or 0 if lib support */
4220 int named
; /* whether or not the argument was named */
4222 struct mips_arg_info info
;
4224 mips_arg_info (cum
, mode
, type
, named
, &info
);
4226 /* The following is a hack in order to pass 1 byte structures
4227 the same way that the MIPS compiler does (namely by passing
4228 the structure in the high byte or half word of the register).
4229 This also makes varargs work. If we have such a structure,
4230 we save the adjustment RTL, and the call define expands will
4231 emit them. For the VOIDmode argument (argument after the
4232 last real argument), pass back a parallel vector holding each
4233 of the adjustments. */
4235 /* ??? This scheme requires everything smaller than the word size to
4236 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4237 that would mean every int needs to be shifted left, which is very
4238 inefficient. Let's not carry this compatibility to the 64 bit
4239 calling convention for now. */
4242 && info
.reg_words
== 1
4243 && info
.num_bytes
< UNITS_PER_WORD
4245 && mips_abi
!= ABI_EABI
4246 && mips_abi
!= ABI_MEABI
)
4248 rtx amount
= GEN_INT (BITS_PER_WORD
- info
.num_bytes
* BITS_PER_UNIT
);
4249 rtx reg
= gen_rtx_REG (word_mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4252 cum
->adjust
[cum
->num_adjusts
++] = gen_ashldi3 (reg
, reg
, amount
);
4254 cum
->adjust
[cum
->num_adjusts
++] = gen_ashlsi3 (reg
, reg
, amount
);
4258 cum
->gp_reg_found
= true;
4260 /* See the comment above the cumulative args structure in mips.h
4261 for an explanation of what this code does. It assumes the O32
4262 ABI, which passes at most 2 arguments in float registers. */
4263 if (cum
->arg_number
< 2 && info
.fpr_p
)
4264 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
4266 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4267 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4268 else if (info
.reg_words
> 0)
4269 cum
->num_fprs
+= FP_INC
;
4271 if (info
.stack_words
> 0)
4272 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4277 /* Return an RTL expression containing the register for the given mode,
4278 or 0 if the argument is to be passed on the stack. */
4281 function_arg (cum
, mode
, type
, named
)
4282 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4283 enum machine_mode mode
; /* current arg mode */
4284 tree type
; /* type of the argument or 0 if lib support */
4285 int named
; /* != 0 for normal args, == 0 for ... args */
4287 struct mips_arg_info info
;
4289 /* We will be called with a mode of VOIDmode after the last argument
4290 has been seen. Whatever we return will be passed to the call
4291 insn. If we need any shifts for small structures, return them in
4292 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4293 mode. Otherwise, if we need a mips16 fp_code, return a REG
4294 with the code stored as the mode. */
4295 if (mode
== VOIDmode
)
4297 if (cum
->num_adjusts
> 0)
4298 return gen_rtx_PARALLEL ((enum machine_mode
) cum
->fp_code
,
4299 gen_rtvec_v (cum
->num_adjusts
,
4300 (rtx
*) cum
->adjust
));
4302 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4303 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4309 mips_arg_info (cum
, mode
, type
, named
, &info
);
4311 /* Return straight away if the whole argument is passed on the stack. */
4312 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4316 && TREE_CODE (type
) == RECORD_TYPE
4317 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4318 && TYPE_SIZE_UNIT (type
)
4319 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
4323 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4324 structure contains a double in its entirety, then that 64 bit
4325 chunk is passed in a floating point register. */
4328 /* First check to see if there is any such field. */
4329 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4330 if (TREE_CODE (field
) == FIELD_DECL
4331 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4332 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4333 && host_integerp (bit_position (field
), 0)
4334 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4339 /* Now handle the special case by returning a PARALLEL
4340 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4341 chunks are passed in registers. */
4343 HOST_WIDE_INT bitpos
;
4346 /* assign_parms checks the mode of ENTRY_PARM, so we must
4347 use the actual mode here. */
4348 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4351 field
= TYPE_FIELDS (type
);
4352 for (i
= 0; i
< info
.reg_words
; i
++)
4356 for (; field
; field
= TREE_CHAIN (field
))
4357 if (TREE_CODE (field
) == FIELD_DECL
4358 && int_bit_position (field
) >= bitpos
)
4362 && int_bit_position (field
) == bitpos
4363 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4364 && !TARGET_SOFT_FLOAT
4365 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4366 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4368 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4371 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4372 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4374 bitpos
+= BITS_PER_WORD
;
4380 if (mips_abi
== ABI_MEABI
&& info
.fpr_p
&& !cum
->prototype
)
4382 /* To make K&R varargs work we need to pass floating
4383 point arguments in both integer and FP registers. */
4384 return gen_rtx_PARALLEL
4387 gen_rtx_EXPR_LIST (VOIDmode
,
4392 gen_rtx_EXPR_LIST (VOIDmode
,
4400 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
4402 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4406 function_arg_partial_nregs (cum
, mode
, type
, named
)
4407 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4408 enum machine_mode mode
; /* current arg mode */
4409 tree type
; /* type of the argument or 0 if lib support */
4410 int named
; /* != 0 for normal args, == 0 for ... args */
4412 struct mips_arg_info info
;
4414 mips_arg_info (cum
, mode
, type
, named
, &info
);
4415 return info
.stack_words
> 0 ? info
.reg_words
: 0;
4419 mips_setup_incoming_varargs (cum
, mode
, type
, no_rtl
)
4420 const CUMULATIVE_ARGS
*cum
;
4421 enum machine_mode mode
;
4425 CUMULATIVE_ARGS local_cum
;
4426 int gp_saved
, fp_saved
;
4428 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4431 /* The caller has advanced CUM up to, but not beyond, the last named
4432 argument. Advance a local copy of CUM past the last "real" named
4433 argument, to find out how many registers are left over.
4435 For K&R varargs, the last named argument is a dummy word-sized one,
4436 so CUM already contains the information we need. For stdarg, it is
4437 a real argument (such as the format in printf()) and we need to
4440 if (!current_function_varargs
)
4441 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4443 /* Found out how many registers we need to save. */
4444 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4445 fp_saved
= (EABI_FLOAT_VARARGS_P
4446 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4455 ptr
= virtual_incoming_args_rtx
;
4456 if (mips_abi
== ABI_EABI
)
4457 ptr
= plus_constant (ptr
, -gp_saved
* UNITS_PER_WORD
);
4458 mem
= gen_rtx_MEM (BLKmode
, ptr
);
4460 /* va_arg is an array access in this case, which causes
4461 it to get MEM_IN_STRUCT_P set. We must set it here
4462 so that the insn scheduler won't assume that these
4463 stores can't possibly overlap with the va_arg loads. */
4464 if (mips_abi
!= ABI_EABI
&& BYTES_BIG_ENDIAN
)
4465 MEM_SET_IN_STRUCT_P (mem
, 1);
4467 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
, mem
,
4468 gp_saved
, gp_saved
* UNITS_PER_WORD
);
4472 /* We can't use move_block_from_reg, because it will use
4474 enum machine_mode mode
;
4477 /* Set OFF to the offset from virtual_incoming_args_rtx of
4478 the first float register. The FP save area lies below
4479 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4480 off
= -gp_saved
* UNITS_PER_WORD
;
4481 off
&= ~(UNITS_PER_FPVALUE
- 1);
4482 off
-= fp_saved
* UNITS_PER_FPREG
;
4484 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4486 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
4488 rtx ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4489 emit_move_insn (gen_rtx_MEM (mode
, ptr
),
4490 gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4491 off
+= UNITS_PER_FPVALUE
;
4495 return (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_FPREG
);
4498 /* Create the va_list data type.
4499 We keep 3 pointers, and two offsets.
4500 Two pointers are to the overflow area, which starts at the CFA.
4501 One of these is constant, for addressing into the GPR save area below it.
4502 The other is advanced up the stack through the overflow region.
4503 The third pointer is to the GPR save area. Since the FPR save area
4504 is just below it, we can address FPR slots off this pointer.
4505 We also keep two one-byte offsets, which are to be subtracted from the
4506 constant pointers to yield addresses in the GPR and FPR save areas.
4507 These are downcounted as float or non-float arguments are used,
4508 and when they get to zero, the argument must be obtained from the
4510 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4511 pointer is enough. It's started at the GPR save area, and is
4513 Note that the GPR save area is not constant size, due to optimization
4514 in the prologue. Hence, we can't use a design with two pointers
4515 and two offsets, although we could have designed this with two pointers
4516 and three offsets. */
4520 mips_build_va_list ()
4522 if (EABI_FLOAT_VARARGS_P
)
4524 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, record
;
4526 record
= make_node (RECORD_TYPE
);
4528 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4530 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4532 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4534 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4535 unsigned_char_type_node
);
4536 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4537 unsigned_char_type_node
);
4540 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4541 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4542 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4543 DECL_FIELD_CONTEXT (f_goff
) = record
;
4544 DECL_FIELD_CONTEXT (f_foff
) = record
;
4546 TYPE_FIELDS (record
) = f_ovfl
;
4547 TREE_CHAIN (f_ovfl
) = f_gtop
;
4548 TREE_CHAIN (f_gtop
) = f_ftop
;
4549 TREE_CHAIN (f_ftop
) = f_goff
;
4550 TREE_CHAIN (f_goff
) = f_foff
;
4552 layout_type (record
);
4556 return ptr_type_node
;
4559 /* Implement va_start. stdarg_p is 0 if implementing
4560 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4561 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4562 (It doesn't have "...", so it inherits the pointers of its caller.) */
4565 mips_va_start (stdarg_p
, valist
, nextarg
)
4570 const CUMULATIVE_ARGS
*cum
= ¤t_function_args_info
;
4572 if (mips_abi
== ABI_EABI
)
4574 int gpr_save_area_size
;
4577 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4579 if (EABI_FLOAT_VARARGS_P
)
4581 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4582 tree ovfl
, gtop
, ftop
, goff
, foff
;
4585 int fpr_save_area_size
;
4587 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4588 f_gtop
= TREE_CHAIN (f_ovfl
);
4589 f_ftop
= TREE_CHAIN (f_gtop
);
4590 f_goff
= TREE_CHAIN (f_ftop
);
4591 f_foff
= TREE_CHAIN (f_goff
);
4593 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4594 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4595 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4596 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4597 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4599 /* Emit code to initialize OVFL, which points to the next varargs
4600 stack argument. CUM->STACK_WORDS gives the number of stack
4601 words used by named arguments. */
4602 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4603 if (cum
->stack_words
> 0)
4604 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4605 build_int_2 (cum
->stack_words
* UNITS_PER_WORD
, 0));
4606 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4607 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4609 /* Emit code to initialize GTOP, the top of the GPR save area. */
4610 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4611 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
4612 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4614 /* Emit code to initialize FTOP, the top of the FPR save area.
4615 This address is gpr_save_area_bytes below GTOP, rounded
4616 down to the next fp-aligned boundary. */
4617 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4618 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4619 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4621 t
= build (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4622 build_int_2 (-fpr_offset
, -1));
4623 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
4624 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4626 /* Emit code to initialize GOFF, the offset from GTOP of the
4627 next GPR argument. */
4628 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
4629 build_int_2 (gpr_save_area_size
, 0));
4630 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4632 /* Likewise emit code to initialize FOFF, the offset from FTOP
4633 of the next FPR argument. */
4635 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4636 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
4637 build_int_2 (fpr_save_area_size
, 0));
4638 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4642 /* Everything is in the GPR save area, or in the overflow
4643 area which is contiguous with it. */
4645 int offset
= -gpr_save_area_size
;
4646 if (gpr_save_area_size
== 0)
4647 offset
= (stdarg_p
? 0 : -UNITS_PER_WORD
);
4648 nextarg
= plus_constant (nextarg
, offset
);
4649 std_expand_builtin_va_start (1, valist
, nextarg
);
4661 /* ??? This had been conditional on
4662 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4663 and both iris5.h and iris6.h define _MIPS_SIM. */
4664 if (mips_abi
== ABI_N32
4665 || mips_abi
== ABI_64
4666 || mips_abi
== ABI_MEABI
)
4667 ofs
= (cum
->num_gprs
< MAX_ARGS_IN_REGISTERS
4671 ofs
= -UNITS_PER_WORD
;
4674 nextarg
= plus_constant (nextarg
, ofs
);
4675 std_expand_builtin_va_start (1, valist
, nextarg
);
4679 /* Implement va_arg. */
4682 mips_va_arg (valist
, type
)
4685 HOST_WIDE_INT size
, rsize
;
4689 size
= int_size_in_bytes (type
);
4690 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4692 if (mips_abi
== ABI_EABI
)
4698 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4702 size
= POINTER_SIZE
/ BITS_PER_UNIT
;
4703 rsize
= UNITS_PER_WORD
;
4706 addr_rtx
= gen_reg_rtx (Pmode
);
4708 if (!EABI_FLOAT_VARARGS_P
)
4710 /* Case of all args in a merged stack. No need to check bounds,
4711 just advance valist along the stack. */
4716 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
4718 /* Align the pointer using: ap = (ap + align - 1) & -align,
4719 where align is 2 * UNITS_PER_WORD. */
4720 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
4721 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
4722 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4723 build_int_2 (-2 * UNITS_PER_WORD
, -1));
4724 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
4725 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4728 /* Emit code to set addr_rtx to the valist, and postincrement
4729 the valist by the size of the argument, rounded up to the
4731 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
,
4733 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4735 emit_move_insn (addr_rtx
, r
);
4737 /* Flush the POSTINCREMENT. */
4742 /* Not a simple merged stack. */
4744 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4745 tree ovfl
, top
, off
;
4746 rtx lab_over
= NULL_RTX
, lab_false
;
4747 HOST_WIDE_INT osize
;
4749 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4750 f_gtop
= TREE_CHAIN (f_ovfl
);
4751 f_ftop
= TREE_CHAIN (f_gtop
);
4752 f_goff
= TREE_CHAIN (f_ftop
);
4753 f_foff
= TREE_CHAIN (f_goff
);
4755 /* We maintain separate pointers and offsets for floating-point
4756 and integer arguments, but we need similar code in both cases.
4759 TOP be the top of the register save area;
4760 OFF be the offset from TOP of the next register;
4761 ADDR_RTX be the address of the argument; and
4762 RSIZE be the number of bytes used to store the argument
4763 when it's in the register save area
4764 OSIZE be the number of bytes used to store it when it's
4765 in the stack overflow area
4766 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4768 The code we want is:
4770 1: off &= -rsize; // round down
4773 4: addr_rtx = top - off;
4778 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4779 10: addr_rtx = ovfl + PADDING;
4783 [1] and [9] can sometimes be optimized away. */
4785 lab_false
= gen_label_rtx ();
4786 lab_over
= gen_label_rtx ();
4788 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4790 if (TREE_CODE (type
) == REAL_TYPE
)
4792 top
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4793 off
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4795 /* When floating-point registers are saved to the stack,
4796 each one will take up UNITS_PER_FPVALUE bytes, regardless
4797 of the float's precision. */
4798 rsize
= UNITS_PER_FPVALUE
;
4802 top
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4803 off
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4804 if (rsize
> UNITS_PER_WORD
)
4806 /* [1] Emit code for: off &= -rsize. */
4807 t
= build (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4808 build_int_2 (-rsize
, -1));
4809 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4810 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4813 /* Every overflow argument must take up at least UNITS_PER_WORD
4814 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4815 than that, such as in the combination -mgp64 -msingle-float
4816 -fshort-double. Doubles passed in registers will then take
4817 up UNITS_PER_FPVALUE bytes, but those passed on the stack
4818 take up UNITS_PER_WORD bytes. */
4819 osize
= MAX (rsize
, UNITS_PER_WORD
);
4821 /* [2] Emit code to branch if off == 0. */
4822 r
= expand_expr (off
, NULL_RTX
, TYPE_MODE (TREE_TYPE (off
)),
4824 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
4827 /* [4] Emit code for: addr_rtx = top - off. */
4828 t
= build (MINUS_EXPR
, TREE_TYPE (top
), top
, off
);
4829 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4831 emit_move_insn (addr_rtx
, r
);
4833 /* [5] Emit code for: off -= rsize. */
4834 t
= build (MINUS_EXPR
, TREE_TYPE (off
), off
, build_int_2 (rsize
, 0));
4835 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4836 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4838 /* [7] Emit code to jump over the else clause, then the label
4841 emit_jump (lab_over
);
4843 emit_label (lab_false
);
4845 if (osize
> UNITS_PER_WORD
)
4847 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4848 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4849 build_int_2 (osize
- 1, 0));
4850 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
,
4851 build_int_2 (-osize
, -1));
4852 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4853 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4856 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4857 post-increment ovfl by osize. On big-endian machines,
4858 the argument has OSIZE - RSIZE bytes of leading padding. */
4859 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4861 if (BYTES_BIG_ENDIAN
&& osize
> rsize
)
4862 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
,
4863 build_int_2 (osize
- rsize
, 0));
4864 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4866 emit_move_insn (addr_rtx
, r
);
4869 emit_label (lab_over
);
4873 addr_rtx
= force_reg (Pmode
, addr_rtx
);
4874 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4875 set_mem_alias_set (r
, get_varargs_alias_set ());
4876 emit_move_insn (addr_rtx
, r
);
4880 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4881 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4890 /* ??? The original va-mips.h did always align, despite the fact
4891 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4892 increment mechanism. */
4896 else if (TYPE_ALIGN (type
) > 32)
4901 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4902 build_int_2 (align
- 1, 0));
4903 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
4904 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4905 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4907 /* Everything past the alignment is standard. */
4908 return std_expand_builtin_va_arg (valist
, type
);
4912 /* Abort after printing out a specific insn. */
4915 abort_with_insn (insn
, reason
)
4924 /* Set up the threshold for data to go into the small data area, instead
4925 of the normal data area, and detect any conflicts in the switches. */
4930 register int i
, start
;
4932 register enum machine_mode mode
;
4933 register enum processor_type mips_cpu
;
4935 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4937 if (mips_section_threshold
<= 0)
4938 target_flags
&= ~MASK_GPOPT
;
4940 target_flags
|= MASK_GPOPT
;
4942 /* If both single-float and soft-float are set, then clear the one that
4943 was set by TARGET_DEFAULT, leaving the one that was set by the
4944 user. We assume here that the specs prevent both being set by the
4946 #ifdef TARGET_DEFAULT
4947 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
4948 target_flags
&= ~((TARGET_DEFAULT
) & (MASK_SOFT_FLOAT
| MASK_SINGLE_FLOAT
));
4951 /* Get the architectural level. */
4952 if (mips_isa_string
== 0)
4953 mips_isa
= MIPS_ISA_DEFAULT
;
4955 else if (mips_isa_string
!= 0
4956 && mips_arch_string
!= 0)
4957 warning ("The -march option is incompatible to -mipsN and therefore ignored.");
4959 else if (ISDIGIT (*mips_isa_string
))
4961 mips_isa
= atoi (mips_isa_string
);
4964 /* -mno-mips16 overrides -mips16. */
4965 if (mips_no_mips16_string
== NULL
)
4967 target_flags
|= MASK_MIPS16
;
4971 mips_isa
= MIPS_ISA_DEFAULT
;
4975 mips_isa
= MIPS_ISA_DEFAULT
;
4978 else if (mips_isa
< 1
4983 error ("-mips%d not supported", mips_isa
);
4990 error ("bad value (%s) for -mips switch", mips_isa_string
);
4994 #ifdef MIPS_ABI_DEFAULT
4995 /* Get the ABI to use. */
4996 if (mips_abi_string
== (char *) 0)
4997 mips_abi
= MIPS_ABI_DEFAULT
;
4998 else if (! strcmp (mips_abi_string
, "32"))
5000 else if (! strcmp (mips_abi_string
, "o64"))
5002 else if (! strcmp (mips_abi_string
, "n32"))
5004 else if (! strcmp (mips_abi_string
, "64"))
5006 else if (! strcmp (mips_abi_string
, "eabi"))
5007 mips_abi
= ABI_EABI
;
5008 else if (! strcmp (mips_abi_string
, "meabi"))
5009 mips_abi
= ABI_MEABI
;
5011 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
5013 /* A specified ISA defaults the ABI if it was not specified. */
5014 if (mips_abi_string
== 0 && mips_isa_string
5015 && mips_abi
!= ABI_EABI
5016 && mips_abi
!= ABI_O64
5017 && mips_abi
!= ABI_MEABI
)
5023 if (! ISA_HAS_64BIT_REGS
)
5025 else if (mips_abi
!= ABI_N32
)
5030 #ifdef MIPS_CPU_STRING_DEFAULT
5031 /* A specified ABI defaults the ISA if it was not specified. */
5032 else if (mips_isa_string
== 0 && mips_abi_string
5033 && mips_abi
!= ABI_EABI
&& mips_abi
!= ABI_O64
)
5035 if (mips_abi
== ABI_32
)
5037 else if (mips_abi
== ABI_N32
)
5044 /* If both ABI and ISA were specified, check for conflicts. */
5045 else if (mips_isa_string
&& mips_abi_string
)
5047 if (! ISA_HAS_64BIT_REGS
&& (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
5048 || mips_abi
== ABI_O64
))
5049 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
5052 /* Override TARGET_DEFAULT if necessary. */
5053 if (mips_abi
== ABI_32
)
5054 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
5056 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
5057 then set the type sizes. In the EABI in 64 bit mode, longs and
5058 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
5059 if (mips_explicit_type_size_string
== NULL
5060 && ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
5061 || mips_abi
== ABI_64
))
5062 target_flags
|= MASK_LONG64
;
5065 if (mips_abi_string
)
5066 error ("this target does not support the -mabi switch");
5069 #ifdef MIPS_CPU_STRING_DEFAULT
5070 /* ??? There is a minor inconsistency here. If the user specifies an ISA
5071 greater than that supported by the default processor, then the user gets
5072 an error. Normally, the compiler will just default to the base level cpu
5073 for the indicated isa. */
5074 if (mips_arch_string
== 0)
5075 mips_arch_string
= MIPS_CPU_STRING_DEFAULT
;
5076 if (mips_tune_string
== 0)
5077 mips_tune_string
= MIPS_CPU_STRING_DEFAULT
;
5080 /* Identify the processor type. */
5082 if (mips_cpu_string
!= 0)
5084 mips_cpu
= mips_parse_cpu (mips_cpu_string
);
5085 if (mips_cpu
== PROCESSOR_DEFAULT
)
5087 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
5088 mips_cpu_string
= "default";
5090 mips_arch
= mips_cpu
;
5091 mips_tune
= mips_cpu
;
5094 if (mips_arch_string
== 0
5095 || ! strcmp (mips_arch_string
, "default")
5096 || ! strcmp (mips_arch_string
, "DEFAULT"))
5101 mips_arch_string
= "3000";
5102 mips_arch
= PROCESSOR_R3000
;
5105 mips_arch_string
= "6000";
5106 mips_arch
= PROCESSOR_R6000
;
5109 mips_arch_string
= "4000";
5110 mips_arch
= PROCESSOR_R4000
;
5113 mips_arch_string
= "8000";
5114 mips_arch
= PROCESSOR_R8000
;
5117 mips_arch_string
= "4kc";
5118 mips_arch
= PROCESSOR_R4KC
;
5121 mips_arch_string
= "5kc";
5122 mips_arch
= PROCESSOR_R5KC
;
5128 mips_arch
= mips_parse_cpu (mips_arch_string
);
5129 if (mips_arch
== PROCESSOR_DEFAULT
)
5131 error ("bad value (%s) for -march= switch", mips_arch_string
);
5132 mips_arch_string
= "default";
5135 if (mips_tune_string
== 0
5136 || ! strcmp (mips_tune_string
, "default")
5137 || ! strcmp (mips_tune_string
, "DEFAULT"))
5139 if (mips_arch
!= PROCESSOR_DEFAULT
)
5140 mips_tune
= mips_arch
;
5145 mips_tune_string
= "3000";
5146 mips_tune
= PROCESSOR_R3000
;
5149 mips_tune_string
= "6000";
5150 mips_tune
= PROCESSOR_R6000
;
5153 mips_tune_string
= "4000";
5154 mips_tune
= PROCESSOR_R4000
;
5157 mips_tune_string
= "8000";
5158 mips_tune
= PROCESSOR_R8000
;
5161 mips_tune_string
= "4kc";
5162 mips_tune
= PROCESSOR_R4KC
;
5165 mips_tune_string
= "5kc";
5166 mips_tune
= PROCESSOR_R5KC
;
5173 mips_tune
= mips_parse_cpu (mips_tune_string
);
5174 if (mips_tune
== PROCESSOR_DEFAULT
)
5176 error ("bad value (%s) for -mtune= switch", mips_tune_string
);
5177 mips_tune_string
= "default";
5181 /* make sure sizes of ints/longs/etc. are ok */
5182 if (! ISA_HAS_64BIT_REGS
)
5186 error ("-mips%d does not support 64 bit fp registers", mips_isa
);
5187 target_flags
&= ~ MASK_FLOAT64
;
5190 else if (TARGET_64BIT
)
5192 error ("-mips%d does not support 64 bit gp registers", mips_isa
);
5193 target_flags
&= ~MASK_64BIT
;
5197 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5198 flag_pcc_struct_return
= 0;
5200 /* Tell halfpic.c that we have half-pic code if we do. */
5201 if (TARGET_HALF_PIC
)
5204 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5205 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5206 /* ??? -non_shared turns off pic code generation, but this is not
5208 if (TARGET_ABICALLS
)
5210 mips_abicalls
= MIPS_ABICALLS_YES
;
5212 if (mips_section_threshold
> 0)
5213 warning ("-G is incompatible with PIC code which is the default");
5216 mips_abicalls
= MIPS_ABICALLS_NO
;
5218 /* -membedded-pic is a form of PIC code suitable for embedded
5219 systems. All calls are made using PC relative addressing, and
5220 all data is addressed using the $gp register. This requires gas,
5221 which does most of the work, and GNU ld, which automatically
5222 expands PC relative calls which are out of range into a longer
5223 instruction sequence. All gcc really does differently is
5224 generate a different sequence for a switch. */
5225 if (TARGET_EMBEDDED_PIC
)
5228 if (TARGET_ABICALLS
)
5229 warning ("-membedded-pic and -mabicalls are incompatible");
5232 warning ("-G and -membedded-pic are incompatible");
5234 /* Setting mips_section_threshold is not required, because gas
5235 will force everything to be GP addressable anyhow, but
5236 setting it will cause gcc to make better estimates of the
5237 number of instructions required to access a particular data
5239 mips_section_threshold
= 0x7fffffff;
5242 /* This optimization requires a linker that can support a R_MIPS_LO16
5243 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5244 GNU ld has this support, but not all other MIPS linkers do, so we enable
5245 this optimization only if the user requests it, or if GNU ld is the
5246 standard linker for this configuration. */
5247 /* ??? This does not work when target addresses are DImode.
5248 This is because we are missing DImode high/lo_sum patterns. */
5249 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
5251 mips_split_addresses
= 1;
5253 mips_split_addresses
= 0;
5255 /* -mrnames says to use the MIPS software convention for register
5256 names instead of the hardware names (ie, $a0 instead of $4).
5257 We do this by switching the names in mips_reg_names, which the
5258 reg_names points into via the REGISTER_NAMES macro. */
5260 if (TARGET_NAME_REGS
)
5261 memcpy (mips_reg_names
, mips_sw_reg_names
, sizeof (mips_reg_names
));
5263 /* When compiling for the mips16, we can not use floating point. We
5264 record the original hard float value in mips16_hard_float. */
5267 if (TARGET_SOFT_FLOAT
)
5268 mips16_hard_float
= 0;
5270 mips16_hard_float
= 1;
5271 target_flags
|= MASK_SOFT_FLOAT
;
5273 /* Don't run the scheduler before reload, since it tends to
5274 increase register pressure. */
5275 flag_schedule_insns
= 0;
5278 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5279 to avoid using up another bit in target_flags. */
5280 if (mips_entry_string
!= NULL
)
5282 if (*mips_entry_string
!= '\0')
5283 error ("invalid option `entry%s'", mips_entry_string
);
5285 if (! TARGET_MIPS16
)
5286 warning ("-mentry is only meaningful with -mips-16");
5291 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5292 attributes can access it. */
5298 /* Initialize the high and low values for legitimate floating point
5299 constants. Rather than trying to get the accuracy down to the
5300 last bit, just use approximate ranges. */
5301 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
5302 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
5303 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
5304 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
5306 mips_print_operand_punct
['?'] = 1;
5307 mips_print_operand_punct
['#'] = 1;
5308 mips_print_operand_punct
['&'] = 1;
5309 mips_print_operand_punct
['!'] = 1;
5310 mips_print_operand_punct
['*'] = 1;
5311 mips_print_operand_punct
['@'] = 1;
5312 mips_print_operand_punct
['.'] = 1;
5313 mips_print_operand_punct
['('] = 1;
5314 mips_print_operand_punct
[')'] = 1;
5315 mips_print_operand_punct
['['] = 1;
5316 mips_print_operand_punct
[']'] = 1;
5317 mips_print_operand_punct
['<'] = 1;
5318 mips_print_operand_punct
['>'] = 1;
5319 mips_print_operand_punct
['{'] = 1;
5320 mips_print_operand_punct
['}'] = 1;
5321 mips_print_operand_punct
['^'] = 1;
5322 mips_print_operand_punct
['$'] = 1;
5323 mips_print_operand_punct
['+'] = 1;
5324 mips_print_operand_punct
['~'] = 1;
5326 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
5327 mips_char_to_class
['e'] = M16_NA_REGS
;
5328 mips_char_to_class
['t'] = T_REG
;
5329 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
5330 mips_char_to_class
['h'] = HI_REG
;
5331 mips_char_to_class
['l'] = LO_REG
;
5332 mips_char_to_class
['a'] = HILO_REG
;
5333 mips_char_to_class
['x'] = MD_REGS
;
5334 mips_char_to_class
['b'] = ALL_REGS
;
5335 mips_char_to_class
['y'] = GR_REGS
;
5336 mips_char_to_class
['z'] = ST_REGS
;
5337 mips_char_to_class
['B'] = COP0_REGS
;
5338 mips_char_to_class
['C'] = COP2_REGS
;
5339 mips_char_to_class
['D'] = COP3_REGS
;
5341 /* Set up array to map GCC register number to debug register number.
5342 Ignore the special purpose register numbers. */
5344 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5345 mips_dbx_regno
[i
] = -1;
5347 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
5348 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
5349 mips_dbx_regno
[i
] = i
+ start
;
5351 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
5352 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
5353 mips_dbx_regno
[i
] = i
+ start
;
5355 /* Set up array giving whether a given register can hold a given mode.
5356 At present, restrict ints from being in FP registers, because reload
5357 is a little enthusiastic about storing extra values in FP registers,
5358 and this is not good for things like OS kernels. Also, due to the
5359 mandatory delay, it is as fast to load from cached memory as to move
5360 from the FP register. */
5362 for (mode
= VOIDmode
;
5363 mode
!= MAX_MACHINE_MODE
;
5364 mode
= (enum machine_mode
) ((int)mode
+ 1))
5366 register int size
= GET_MODE_SIZE (mode
);
5367 register enum mode_class
class = GET_MODE_CLASS (mode
);
5369 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5376 temp
= (regno
== FPSW_REGNUM
);
5378 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5379 || FP_REG_P (regno
));
5382 else if (GP_REG_P (regno
))
5383 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5385 else if (FP_REG_P (regno
))
5386 temp
= (((regno
% FP_INC
) == 0
5387 /* I think this change is OK regardless of abi, but
5388 I'm being cautions untill I can test this more.
5389 HARD_REGNO_MODE_OK is about whether or not you
5390 can move to and from a register without changing
5391 the value, not about whether math works on the
5393 || (mips_abi
== ABI_MEABI
&& size
<= 4))
5394 && (class == MODE_FLOAT
5395 || class == MODE_COMPLEX_FLOAT
5396 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
5397 && size
<= UNITS_PER_FPVALUE
);
5399 else if (MD_REG_P (regno
))
5400 temp
= (class == MODE_INT
5401 && (size
<= UNITS_PER_WORD
5402 || (regno
== MD_REG_FIRST
5403 && size
== 2 * UNITS_PER_WORD
)));
5405 else if (ALL_COP_REG_P (regno
))
5406 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
5410 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5414 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5415 initialized yet, so we can't use that here. */
5416 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5418 /* Provide default values for align_* for 64-bit targets. */
5419 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5421 if (align_loops
== 0)
5423 if (align_jumps
== 0)
5425 if (align_functions
== 0)
5426 align_functions
= 8;
5429 /* Register global variables with the garbage collector. */
5430 mips_add_gc_roots ();
5432 /* Functions to allocate, mark and deallocate machine-dependent
5434 init_machine_status
= &mips_init_machine_status
;
5435 free_machine_status
= &mips_free_machine_status
;
5436 mark_machine_status
= &mips_mark_machine_status
;
5439 /* Allocate a chunk of memory for per-function machine-dependent data. */
5441 mips_init_machine_status (fn
)
5442 struct function
*fn
;
5444 fn
->machine
= ((struct machine_function
*)
5445 xcalloc (1, sizeof (struct machine_function
)));
5448 /* Release the chunk of memory for per-function machine-dependent data. */
5450 mips_free_machine_status (fn
)
5451 struct function
*fn
;
5457 /* Mark per-function machine-dependent data. */
5459 mips_mark_machine_status (fn
)
5460 struct function
*fn
;
5464 ggc_mark_rtx (fn
->machine
->embedded_pic_fnaddr_rtx
);
5465 ggc_mark_rtx (fn
->machine
->mips16_gp_pseudo_rtx
);
5469 /* On the mips16, we want to allocate $24 (T_REG) before other
5470 registers for instructions for which it is possible. This helps
5471 avoid shuffling registers around in order to set up for an xor,
5472 encouraging the compiler to use a cmp instead. */
5475 mips_order_regs_for_local_alloc ()
5479 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5480 reg_alloc_order
[i
] = i
;
5484 /* It really doesn't matter where we put register 0, since it is
5485 a fixed register anyhow. */
5486 reg_alloc_order
[0] = 24;
5487 reg_alloc_order
[24] = 0;
5492 /* The MIPS debug format wants all automatic variables and arguments
5493 to be in terms of the virtual frame pointer (stack pointer before
5494 any adjustment in the function), while the MIPS 3.0 linker wants
5495 the frame pointer to be the stack pointer after the initial
5496 adjustment. So, we do the adjustment here. The arg pointer (which
5497 is eliminated) points to the virtual frame pointer, while the frame
5498 pointer (which may be eliminated) points to the stack pointer after
5499 the initial adjustments. */
5502 mips_debugger_offset (addr
, offset
)
5504 HOST_WIDE_INT offset
;
5506 rtx offset2
= const0_rtx
;
5507 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5510 offset
= INTVAL (offset2
);
5512 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5513 || reg
== hard_frame_pointer_rtx
)
5515 HOST_WIDE_INT frame_size
= (!current_frame_info
.initialized
)
5516 ? compute_frame_size (get_frame_size ())
5517 : current_frame_info
.total_size
;
5519 /* MIPS16 frame is smaller */
5520 if (frame_pointer_needed
&& TARGET_MIPS16
)
5521 frame_size
-= current_function_outgoing_args_size
;
5523 offset
= offset
- frame_size
;
5526 /* sdbout_parms does not want this to crash for unrecognized cases. */
5528 else if (reg
!= arg_pointer_rtx
)
5529 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer");
5535 /* A C compound statement to output to stdio stream STREAM the
5536 assembler syntax for an instruction operand X. X is an RTL
5539 CODE is a value that can be used to specify one of several ways
5540 of printing the operand. It is used when identical operands
5541 must be printed differently depending on the context. CODE
5542 comes from the `%' specification that was used to request
5543 printing of the operand. If the specification was just `%DIGIT'
5544 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5545 is the ASCII code for LTR.
5547 If X is a register, this macro should print the register's name.
5548 The names can be found in an array `reg_names' whose type is
5549 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5551 When the machine description has a specification `%PUNCT' (a `%'
5552 followed by a punctuation character), this macro is called with
5553 a null pointer for X and the punctuation character for CODE.
5555 The MIPS specific codes are:
5557 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5558 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5559 'd' output integer constant in decimal,
5560 'z' if the operand is 0, use $0 instead of normal operand.
5561 'D' print second part of double-word register or memory operand.
5562 'L' print low-order register of double-word register operand.
5563 'M' print high-order register of double-word register operand.
5564 'C' print part of opcode for a branch condition.
5565 'F' print part of opcode for a floating-point branch condition.
5566 'N' print part of opcode for a branch condition, inverted.
5567 'W' print part of opcode for a floating-point branch condition, inverted.
5568 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5569 'B' print 'z' for EQ, 'n' for NE
5570 'b' print 'n' for EQ, 'z' for NE
5571 'T' print 'f' for EQ, 't' for NE
5572 't' print 't' for EQ, 'f' for NE
5573 'Z' print register and a comma, but print nothing for $fcc0
5574 '(' Turn on .set noreorder
5575 ')' Turn on .set reorder
5576 '[' Turn on .set noat
5578 '<' Turn on .set nomacro
5579 '>' Turn on .set macro
5580 '{' Turn on .set volatile (not GAS)
5581 '}' Turn on .set novolatile (not GAS)
5582 '&' Turn on .set noreorder if filling delay slots
5583 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5584 '!' Turn on .set nomacro if filling delay slots
5585 '#' Print nop if in a .set noreorder section.
5586 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5587 '@' Print the name of the assembler temporary register (at or $1).
5588 '.' Print the name of the register with a hard-wired zero (zero or $0).
5589 '^' Print the name of the pic call-through register (t9 or $25).
5590 '$' Print the name of the stack pointer register (sp or $29).
5591 '+' Print the name of the gp register (gp or $28).
5592 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5595 print_operand (file
, op
, letter
)
5596 FILE *file
; /* file to write to */
5597 rtx op
; /* operand to print */
5598 int letter
; /* %<letter> or 0 */
5600 register enum rtx_code code
;
5602 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5607 if (mips_branch_likely
)
5612 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5616 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5620 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5624 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5628 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
5632 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5633 fputs (".set\tnoreorder\n\t", file
);
5637 if (final_sequence
!= 0)
5639 if (set_noreorder
++ == 0)
5640 fputs (".set\tnoreorder\n\t", file
);
5642 if (set_nomacro
++ == 0)
5643 fputs (".set\tnomacro\n\t", file
);
5648 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5649 fputs ("\n\t.set\tnomacro", file
);
5653 if (set_noreorder
!= 0)
5654 fputs ("\n\tnop", file
);
5655 else if (TARGET_STATS
)
5656 fputs ("\n\t#nop", file
);
5661 if (set_noreorder
++ == 0)
5662 fputs (".set\tnoreorder\n\t", file
);
5666 if (set_noreorder
== 0)
5667 error ("internal error: %%) found without a %%( in assembler pattern");
5669 else if (--set_noreorder
== 0)
5670 fputs ("\n\t.set\treorder", file
);
5675 if (set_noat
++ == 0)
5676 fputs (".set\tnoat\n\t", file
);
5681 error ("internal error: %%] found without a %%[ in assembler pattern");
5682 else if (--set_noat
== 0)
5683 fputs ("\n\t.set\tat", file
);
5688 if (set_nomacro
++ == 0)
5689 fputs (".set\tnomacro\n\t", file
);
5693 if (set_nomacro
== 0)
5694 error ("internal error: %%> found without a %%< in assembler pattern");
5695 else if (--set_nomacro
== 0)
5696 fputs ("\n\t.set\tmacro", file
);
5701 if (set_volatile
++ == 0)
5702 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
5706 if (set_volatile
== 0)
5707 error ("internal error: %%} found without a %%{ in assembler pattern");
5708 else if (--set_volatile
== 0)
5709 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
5715 if (align_labels_log
> 0)
5716 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5721 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5730 error ("PRINT_OPERAND null pointer");
5734 code
= GET_CODE (op
);
5736 if (code
== SIGN_EXTEND
)
5737 op
= XEXP (op
, 0), code
= GET_CODE (op
);
5742 case EQ
: fputs ("eq", file
); break;
5743 case NE
: fputs ("ne", file
); break;
5744 case GT
: fputs ("gt", file
); break;
5745 case GE
: fputs ("ge", file
); break;
5746 case LT
: fputs ("lt", file
); break;
5747 case LE
: fputs ("le", file
); break;
5748 case GTU
: fputs ("gtu", file
); break;
5749 case GEU
: fputs ("geu", file
); break;
5750 case LTU
: fputs ("ltu", file
); break;
5751 case LEU
: fputs ("leu", file
); break;
5753 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
5756 else if (letter
== 'N')
5759 case EQ
: fputs ("ne", file
); break;
5760 case NE
: fputs ("eq", file
); break;
5761 case GT
: fputs ("le", file
); break;
5762 case GE
: fputs ("lt", file
); break;
5763 case LT
: fputs ("ge", file
); break;
5764 case LE
: fputs ("gt", file
); break;
5765 case GTU
: fputs ("leu", file
); break;
5766 case GEU
: fputs ("ltu", file
); break;
5767 case LTU
: fputs ("geu", file
); break;
5768 case LEU
: fputs ("gtu", file
); break;
5770 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
5773 else if (letter
== 'F')
5776 case EQ
: fputs ("c1f", file
); break;
5777 case NE
: fputs ("c1t", file
); break;
5779 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
5782 else if (letter
== 'W')
5785 case EQ
: fputs ("c1t", file
); break;
5786 case NE
: fputs ("c1f", file
); break;
5788 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
5791 else if (letter
== 'S')
5795 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
5796 assemble_name (file
, buffer
);
5799 else if (letter
== 'Z')
5801 register int regnum
;
5806 regnum
= REGNO (op
);
5807 if (! ST_REG_P (regnum
))
5810 if (regnum
!= ST_REG_FIRST
)
5811 fprintf (file
, "%s,", reg_names
[regnum
]);
5814 else if (code
== REG
|| code
== SUBREG
)
5816 register int regnum
;
5819 regnum
= REGNO (op
);
5821 regnum
= true_regnum (op
);
5823 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5824 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5828 fprintf (file
, "%s", reg_names
[regnum
]);
5831 else if (code
== MEM
)
5834 output_address (plus_constant (XEXP (op
, 0), 4));
5836 output_address (XEXP (op
, 0));
5839 else if (code
== CONST_DOUBLE
5840 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
5845 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
5846 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
5850 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5851 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5853 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5854 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5856 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5857 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5859 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
5860 fputs (reg_names
[GP_REG_FIRST
], file
);
5862 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5863 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5865 else if (letter
== 'B')
5866 fputs (code
== EQ
? "z" : "n", file
);
5867 else if (letter
== 'b')
5868 fputs (code
== EQ
? "n" : "z", file
);
5869 else if (letter
== 'T')
5870 fputs (code
== EQ
? "f" : "t", file
);
5871 else if (letter
== 't')
5872 fputs (code
== EQ
? "t" : "f", file
);
5874 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
5876 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5877 print_operand (file
, XEXP (op
, 0), letter
);
5880 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
5882 fputs ("%gprel(", file
);
5883 mips16_output_gp_offset (file
, op
);
5888 output_addr_const (file
, op
);
5891 /* A C compound statement to output to stdio stream STREAM the
5892 assembler syntax for an instruction operand that is a memory
5893 reference whose address is ADDR. ADDR is an RTL expression.
5895 On some machines, the syntax for a symbolic address depends on
5896 the section that the address refers to. On these machines,
5897 define the macro `ENCODE_SECTION_INFO' to store the information
5898 into the `symbol_ref', and then check for it here. */
5901 print_operand_address (file
, addr
)
5906 error ("PRINT_OPERAND_ADDRESS, null pointer");
5909 switch (GET_CODE (addr
))
5912 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
5913 abort_with_insn (addr
, "arg pointer not eliminated");
5915 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
5920 register rtx arg0
= XEXP (addr
, 0);
5921 register rtx arg1
= XEXP (addr
, 1);
5923 if (! mips_split_addresses
)
5924 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5926 if (GET_CODE (arg0
) != REG
)
5927 abort_with_insn (addr
,
5928 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5930 fprintf (file
, "%%lo(");
5931 print_operand_address (file
, arg1
);
5932 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
5938 register rtx reg
= 0;
5939 register rtx offset
= 0;
5940 register rtx arg0
= XEXP (addr
, 0);
5941 register rtx arg1
= XEXP (addr
, 1);
5943 if (GET_CODE (arg0
) == REG
)
5947 if (GET_CODE (offset
) == REG
)
5948 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
5951 else if (GET_CODE (arg1
) == REG
)
5952 reg
= arg1
, offset
= arg0
;
5953 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
5955 output_addr_const (file
, addr
);
5959 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
5961 if (! CONSTANT_P (offset
))
5962 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5964 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
5965 abort_with_insn (addr
, "arg pointer not eliminated");
5968 && GET_CODE (offset
) == CONST
5969 && mips16_gp_offset_p (offset
))
5971 fputs ("%gprel(", file
);
5972 mips16_output_gp_offset (file
, offset
);
5976 output_addr_const (file
, offset
);
5977 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
5985 output_addr_const (file
, addr
);
5989 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5994 /* Target hook for assembling integer objects. It appears that the Irix
5995 6 assembler can't handle 64-bit decimal integers, so avoid printing
5996 such an integer here. */
5999 mips_assemble_integer (x
, size
, aligned_p
)
6004 if ((TARGET_64BIT
|| TARGET_GAS
) && size
== 8 && aligned_p
)
6006 fputs ("\t.dword\t", asm_out_file
);
6007 if (HOST_BITS_PER_WIDE_INT
< 64 || GET_CODE (x
) != CONST_INT
)
6008 output_addr_const (asm_out_file
, x
);
6010 print_operand (asm_out_file
, x
, 'X');
6011 fputc ('\n', asm_out_file
);
6014 return default_assemble_integer (x
, size
, aligned_p
);
6017 /* If optimizing for the global pointer, keep track of all of the externs, so
6018 that at the end of the file, we can emit the appropriate .extern
6019 declaration for them, before writing out the text section. We assume all
6020 names passed to us are in the permanent obstack, so they will be valid at
6021 the end of the compilation.
6023 If we have -G 0, or the extern size is unknown, or the object is in a user
6024 specified section that is not .sbss/.sdata, don't bother emitting the
6025 .externs. In the case of user specified sections this behaviour is
6026 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6029 mips_output_external (file
, decl
, name
)
6030 FILE *file ATTRIBUTE_UNUSED
;
6034 register struct extern_list
*p
;
6039 && TREE_CODE (decl
) != FUNCTION_DECL
6040 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
6041 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
6042 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
6043 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
6045 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6046 p
->next
= extern_head
;
6052 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6053 if (TREE_CODE (decl
) == FUNCTION_DECL
6054 /* ??? Don't include alloca, since gcc will always expand it
6055 inline. If we don't do this, the C++ library fails to build. */
6056 && strcmp (name
, "alloca")
6057 /* ??? Don't include __builtin_next_arg, because then gcc will not
6058 bootstrap under Irix 5.1. */
6059 && strcmp (name
, "__builtin_next_arg"))
6061 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6062 p
->next
= extern_head
;
6072 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6074 mips_output_external_libcall (file
, name
)
6075 FILE *file ATTRIBUTE_UNUSED
;
6078 register struct extern_list
*p
;
6080 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
6081 p
->next
= extern_head
;
6090 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6091 for .file's that start within a function. If we are smuggling stabs, try to
6092 put out a MIPS ECOFF file and a stab. */
6095 mips_output_filename (stream
, name
)
6099 static int first_time
= 1;
6100 char ltext_label_name
[100];
6106 current_function_file
= name
;
6107 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6108 /* This tells mips-tfile that stabs will follow. */
6109 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
6110 fprintf (stream
, "\t#@stabs\n");
6113 else if (write_symbols
== DBX_DEBUG
)
6115 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
6116 fprintf (stream
, "%s", ASM_STABS_OP
);
6117 output_quoted_string (stream
, name
);
6118 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
6121 else if (name
!= current_function_file
6122 && strcmp (name
, current_function_file
) != 0)
6124 if (inside_function
&& !TARGET_GAS
)
6126 if (!file_in_function_warning
)
6128 file_in_function_warning
= 1;
6129 ignore_line_number
= 1;
6130 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6136 current_function_file
= name
;
6137 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6142 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6143 as well as a .loc, since it is possible that MIPS ECOFF might not be
6144 able to represent the location for inlines that come from a different
6148 mips_output_lineno (stream
, line
)
6152 if (write_symbols
== DBX_DEBUG
)
6155 fprintf (stream
, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6156 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
6157 LOCAL_LABEL_PREFIX
, sym_lineno
);
6161 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
6162 (ignore_line_number
) ? "#" : "",
6163 num_source_filenames
, line
);
6165 LABEL_AFTER_LOC (stream
);
6169 /* Output an ASCII string, in a space-saving way. */
6172 mips_output_ascii (stream
, string_param
, len
)
6174 const char *string_param
;
6179 register const unsigned char *string
=
6180 (const unsigned char *)string_param
;
6182 fprintf (stream
, "\t.ascii\t\"");
6183 for (i
= 0; i
< len
; i
++)
6185 register int c
= string
[i
];
6191 putc ('\\', stream
);
6196 case TARGET_NEWLINE
:
6197 fputs ("\\n", stream
);
6199 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
6200 || c
== TARGET_TAB
))
6201 cur_pos
= 32767; /* break right here */
6207 fputs ("\\t", stream
);
6212 fputs ("\\f", stream
);
6217 fputs ("\\b", stream
);
6222 fputs ("\\r", stream
);
6227 if (c
>= ' ' && c
< 0177)
6234 fprintf (stream
, "\\%03o", c
);
6239 if (cur_pos
> 72 && i
+1 < len
)
6242 fprintf (stream
, "\"\n\t.ascii\t\"");
6245 fprintf (stream
, "\"\n");
6248 /* If defined, a C statement to be executed just prior to the output of
6249 assembler code for INSN, to modify the extracted operands so they will be
6252 Here the argument OPVEC is the vector containing the operands extracted
6253 from INSN, and NOPERANDS is the number of elements of the vector which
6254 contain meaningful data for this insn. The contents of this vector are
6255 what will be used to convert the insn template into assembler code, so you
6256 can change the assembler output by changing the contents of the vector.
6258 We use it to check if the current insn needs a nop in front of it because
6259 of load delays, and also to update the delay slot statistics. */
6261 /* ??? There is no real need for this function, because it never actually
6262 emits a NOP anymore. */
6265 final_prescan_insn (insn
, opvec
, noperands
)
6267 rtx opvec
[] ATTRIBUTE_UNUSED
;
6268 int noperands ATTRIBUTE_UNUSED
;
6270 if (dslots_number_nops
> 0)
6272 rtx pattern
= PATTERN (insn
);
6273 int length
= get_attr_length (insn
);
6275 /* Do we need to emit a NOP? */
6277 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
6278 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
6279 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
6280 || (mips_load_reg4
!= 0
6281 && reg_mentioned_p (mips_load_reg4
, pattern
)))
6282 fputs ("\t#nop\n", asm_out_file
);
6285 dslots_load_filled
++;
6287 while (--dslots_number_nops
> 0)
6288 fputs ("\t#nop\n", asm_out_file
);
6297 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
6298 dslots_jump_total
++;
6301 /* Output at beginning of assembler file.
6303 If we are optimizing to use the global pointer, create a temporary file to
6304 hold all of the text stuff, and write it out to the end. This is needed
6305 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6306 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6307 processed, it generates a two instruction sequence. */
6310 mips_asm_file_start (stream
)
6313 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
6315 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6316 inside of a .set noreorder section jumps to a label outside of the .set
6317 noreorder section. Revision 2.20 just set nobopt silently rather than
6320 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
6321 fprintf (stream
, "\t.set\tnobopt\n");
6325 #if defined(OBJECT_FORMAT_ELF)
6326 /* Generate a special section to describe the ABI switches used to
6327 produce the resultant binary. This used to be done by the assembler
6328 setting bits in the ELF header's flags field, but we have run out of
6329 bits. GDB needs this information in order to be able to correctly
6330 debug these binaries. See the function mips_gdbarch_init() in
6332 const char * abi_string
= NULL
;
6336 case ABI_32
: abi_string
= "abi32"; break;
6337 case ABI_N32
: abi_string
= "abiN32"; break;
6338 case ABI_64
: abi_string
= "abi64"; break;
6339 case ABI_O64
: abi_string
= "abiO64"; break;
6340 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
6341 case ABI_MEABI
:abi_string
= TARGET_64BIT
? "meabi64" : "meabi32"; break;
6345 /* Note - we use fprintf directly rather than called named_section()
6346 because in this way we can avoid creating an allocated section. We
6347 do not want this section to take up any space in the running
6349 fprintf (stream
, "\t.section .mdebug.%s\n", abi_string
);
6351 /* Restore the default section. */
6352 fprintf (stream
, "\t.previous\n");
6358 /* Generate the pseudo ops that System V.4 wants. */
6359 #ifndef ABICALLS_ASM_OP
6360 #define ABICALLS_ASM_OP "\t.abicalls"
6362 if (TARGET_ABICALLS
)
6363 /* ??? but do not want this (or want pic0) if -non-shared? */
6364 fprintf (stream
, "%s\n", ABICALLS_ASM_OP
);
6367 fprintf (stream
, "\t.set\tmips16\n");
6369 /* This code exists so that we can put all externs before all symbol
6370 references. This is necessary for the MIPS assembler's global pointer
6371 optimizations to work. */
6372 if (TARGET_FILE_SWITCHING
)
6374 asm_out_data_file
= stream
;
6375 asm_out_text_file
= tmpfile ();
6378 asm_out_data_file
= asm_out_text_file
= stream
;
6380 if (flag_verbose_asm
)
6381 fprintf (stream
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6383 mips_section_threshold
, mips_arch_string
, mips_isa
);
6386 /* If we are optimizing the global pointer, emit the text section now and any
6387 small externs which did not have .comm, etc that are needed. Also, give a
6388 warning if the data area is more than 32K and -pic because 3 instructions
6389 are needed to reference the data pointers. */
6392 mips_asm_file_end (file
)
6396 struct extern_list
*p
;
6400 HALF_PIC_FINISH (file
);
6407 for (p
= extern_head
; p
!= 0; p
= p
->next
)
6409 name_tree
= get_identifier (p
->name
);
6411 /* Positively ensure only one .extern for any given symbol. */
6412 if (! TREE_ASM_WRITTEN (name_tree
))
6414 TREE_ASM_WRITTEN (name_tree
) = 1;
6415 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6417 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
6421 fputs ("\t.extern\t", file
);
6422 assemble_name (file
, p
->name
);
6423 fprintf (file
, ", %d\n", p
->size
);
6429 if (TARGET_FILE_SWITCHING
)
6431 fprintf (file
, "\n\t.text\n");
6432 copy_file_data (file
, asm_out_text_file
);
6437 copy_file_data (to
, from
)
6444 fatal_io_error ("can't rewind temp file");
6446 while ((len
= fread (buffer
, 1, sizeof (buffer
), from
)) > 0)
6447 if (fwrite (buffer
, 1, len
, to
) != len
)
6448 fatal_io_error ("can't write to output file");
6451 fatal_io_error ("can't read from temp file");
6454 fatal_io_error ("can't close temp file");
6457 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6458 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6461 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
6464 const char *init_string
;
6465 const char *final_string
;
6468 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
6469 assemble_name (stream
, name
);
6470 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
6474 tree name_tree
= get_identifier (name
);
6475 TREE_ASM_WRITTEN (name_tree
) = 1;
6479 /* Return the bytes needed to compute the frame pointer from the current
6482 Mips stack frames look like:
6484 Before call After call
6485 +-----------------------+ +-----------------------+
6488 | caller's temps. | | caller's temps. |
6490 +-----------------------+ +-----------------------+
6492 | arguments on stack. | | arguments on stack. |
6494 +-----------------------+ +-----------------------+
6495 | 4 words to save | | 4 words to save |
6496 | arguments passed | | arguments passed |
6497 | in registers, even | | in registers, even |
6498 SP->| if not passed. | VFP->| if not passed. |
6499 +-----------------------+ +-----------------------+
6501 | fp register save |
6503 +-----------------------+
6505 | gp register save |
6507 +-----------------------+
6511 +-----------------------+
6513 | alloca allocations |
6515 +-----------------------+
6517 | GP save for V.4 abi |
6519 +-----------------------+
6521 | arguments on stack |
6523 +-----------------------+
6525 | arguments passed |
6526 | in registers, even |
6527 low SP->| if not passed. |
6528 memory +-----------------------+
6533 compute_frame_size (size
)
6534 HOST_WIDE_INT size
; /* # of var. bytes allocated */
6537 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6538 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6539 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6540 HOST_WIDE_INT extra_size
; /* # extra bytes */
6541 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6542 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6543 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6544 long mask
; /* mask of saved gp registers */
6545 long fmask
; /* mask of saved fp registers */
6552 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
6553 var_size
= MIPS_STACK_ALIGN (size
);
6554 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
6556 /* The MIPS 3.0 linker does not like functions that dynamically
6557 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6558 looks like we are trying to create a second frame pointer to the
6559 function, so allocate some stack space to make it happy. */
6561 if (args_size
== 0 && current_function_calls_alloca
)
6562 args_size
= 4 * UNITS_PER_WORD
;
6564 total_size
= var_size
+ args_size
+ extra_size
;
6565 return_type
= DECL_RESULT (current_function_decl
);
6567 /* Calculate space needed for gp registers. */
6568 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6570 /* $18 is a special case on the mips16. It may be used to call
6571 a function which returns a floating point value, but it is
6572 marked in call_used_regs. $31 is also a special case. When
6573 not using -mentry, it will be used to copy a return value
6574 into the floating point registers if the return value is
6576 if (MUST_SAVE_REGISTER (regno
)
6578 && regno
== GP_REG_FIRST
+ 18
6579 && regs_ever_live
[regno
])
6581 && regno
== GP_REG_FIRST
+ 31
6582 && mips16_hard_float
6584 && ! aggregate_value_p (return_type
)
6585 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6586 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
))
6588 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6589 mask
|= 1L << (regno
- GP_REG_FIRST
);
6591 /* The entry and exit pseudo instructions can not save $17
6592 without also saving $16. */
6594 && regno
== GP_REG_FIRST
+ 17
6595 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
6597 gp_reg_size
+= UNITS_PER_WORD
;
6603 /* We need to restore these for the handler. */
6604 if (current_function_calls_eh_return
)
6609 regno
= EH_RETURN_DATA_REGNO (i
);
6610 if (regno
== INVALID_REGNUM
)
6612 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6613 mask
|= 1L << (regno
- GP_REG_FIRST
);
6617 /* This loop must iterate over the same space as its companion in
6618 save_restore_insns. */
6619 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6620 regno
>= FP_REG_FIRST
;
6623 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6625 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
6626 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
6630 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6631 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6633 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6634 for leaf routines (total_size == extra_size) to save the gp reg.
6635 The gp reg is callee saved in the 64 bit ABI, so all routines must
6636 save the gp reg. This is not a leaf routine if -p, because of the
6638 if (total_size
== extra_size
6639 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
6640 && ! current_function_profile
)
6641 total_size
= extra_size
= 0;
6642 else if (TARGET_ABICALLS
)
6644 /* Add the context-pointer to the saved registers. */
6645 gp_reg_size
+= UNITS_PER_WORD
;
6646 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
6647 total_size
-= gp_reg_rounded
;
6648 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6649 total_size
+= gp_reg_rounded
;
6652 /* Add in space reserved on the stack by the callee for storing arguments
6653 passed in registers. */
6654 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6655 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
6657 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6658 if (mips_entry
&& total_size
> 0 && total_size
< 32)
6661 /* Save other computed information. */
6662 current_frame_info
.total_size
= total_size
;
6663 current_frame_info
.var_size
= var_size
;
6664 current_frame_info
.args_size
= args_size
;
6665 current_frame_info
.extra_size
= extra_size
;
6666 current_frame_info
.gp_reg_size
= gp_reg_size
;
6667 current_frame_info
.fp_reg_size
= fp_reg_size
;
6668 current_frame_info
.mask
= mask
;
6669 current_frame_info
.fmask
= fmask
;
6670 current_frame_info
.initialized
= reload_completed
;
6671 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6672 current_frame_info
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
6676 unsigned long offset
;
6678 /* When using mips_entry, the registers are always saved at the
6679 top of the stack. */
6681 offset
= (args_size
+ extra_size
+ var_size
6682 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6684 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
6686 current_frame_info
.gp_sp_offset
= offset
;
6687 current_frame_info
.gp_save_offset
= offset
- total_size
;
6691 current_frame_info
.gp_sp_offset
= 0;
6692 current_frame_info
.gp_save_offset
= 0;
6697 unsigned long offset
= (args_size
+ extra_size
+ var_size
6698 + gp_reg_rounded
+ fp_reg_size
6699 - FP_INC
* UNITS_PER_FPREG
);
6700 current_frame_info
.fp_sp_offset
= offset
;
6701 current_frame_info
.fp_save_offset
= offset
- total_size
;
6705 current_frame_info
.fp_sp_offset
= 0;
6706 current_frame_info
.fp_save_offset
= 0;
6709 /* Ok, we're done. */
6713 /* Common code to emit the insns (or to write the instructions to a file)
6714 to save/restore registers.
6716 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6717 is not modified within save_restore_insns. */
6719 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6721 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6722 and return an rtl expression for the register. Write the assembly
6723 instructions directly to FILE if it is not null, otherwise emit them as
6726 This function is a subroutine of save_restore_insns. It is used when
6727 OFFSET is too large to add in a single instruction. */
6730 mips_add_large_offset_to_sp (offset
, file
)
6731 HOST_WIDE_INT offset
;
6734 rtx reg
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6737 rtx offset_rtx
= GEN_INT (offset
);
6739 emit_move_insn (reg
, offset_rtx
);
6740 if (Pmode
== DImode
)
6741 emit_insn (gen_adddi3 (reg
, reg
, stack_pointer_rtx
));
6743 emit_insn (gen_addsi3 (reg
, reg
, stack_pointer_rtx
));
6747 fprintf (file
, "\tli\t%s,0x%.08lx\t# ",
6748 reg_names
[MIPS_TEMP2_REGNUM
], (long) offset
);
6749 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6750 fprintf (file
, "\n\t%s\t%s,%s,%s\n",
6751 Pmode
== DImode
? "daddu" : "addu",
6752 reg_names
[MIPS_TEMP2_REGNUM
],
6753 reg_names
[MIPS_TEMP2_REGNUM
],
6754 reg_names
[STACK_POINTER_REGNUM
]);
6759 /* Make INSN frame related and note that it performs the frame-related
6760 operation DWARF_PATTERN. */
6763 mips_annotate_frame_insn (insn
, dwarf_pattern
)
6764 rtx insn
, dwarf_pattern
;
6766 RTX_FRAME_RELATED_P (insn
) = 1;
6767 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6772 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6773 The expression should only be used to store single registers. */
6776 mips_frame_set (mode
, regno
, offset
)
6777 enum machine_mode mode
;
6781 rtx address
= plus_constant (stack_pointer_rtx
, offset
);
6782 rtx set
= gen_rtx_SET (mode
,
6783 gen_rtx_MEM (mode
, address
),
6784 gen_rtx_REG (mode
, regno
));
6785 RTX_FRAME_RELATED_P (set
) = 1;
6790 /* Emit a move instruction that stores REG in MEM. Make the instruction
6791 frame related and note that it stores REG at (SP + OFFSET). This
6792 function may be asked to store an FPR pair. */
6795 mips_emit_frame_related_store (mem
, reg
, offset
)
6798 HOST_WIDE_INT offset
;
6802 if (GET_MODE (reg
) == DFmode
&& ! TARGET_FLOAT64
)
6804 /* Two registers are being stored, so the frame-related expression
6805 must be a PARALLEL rtx with one SET for each register. The
6806 higher numbered register is stored in the lower address on
6807 big-endian targets. */
6808 int regno1
= TARGET_BIG_ENDIAN
? REGNO (reg
) + 1 : REGNO (reg
);
6809 int regno2
= TARGET_BIG_ENDIAN
? REGNO (reg
) : REGNO (reg
) + 1;
6810 rtx set1
= mips_frame_set (SFmode
, regno1
, offset
);
6811 rtx set2
= mips_frame_set (SFmode
, regno2
, offset
+ UNITS_PER_FPREG
);
6812 dwarf_expr
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set1
, set2
));
6815 dwarf_expr
= mips_frame_set (GET_MODE (reg
), REGNO (reg
), offset
);
6817 mips_annotate_frame_insn (emit_move_insn (mem
, reg
), dwarf_expr
);
6821 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
6822 int store_p
; /* true if this is prologue */
6823 rtx large_reg
; /* register holding large offset constant or NULL */
6824 long large_offset
; /* large constant offset value */
6825 FILE *file
; /* file to write instructions instead of making RTL */
6827 long mask
= current_frame_info
.mask
;
6828 long fmask
= current_frame_info
.fmask
;
6829 long real_mask
= mask
;
6832 HOST_WIDE_INT base_offset
;
6833 HOST_WIDE_INT gp_offset
;
6834 HOST_WIDE_INT fp_offset
;
6835 HOST_WIDE_INT end_offset
;
6838 if (frame_pointer_needed
6839 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
6842 /* Do not restore GP under certain conditions. */
6845 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
6846 mask
&= ~(1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
));
6848 if (mask
== 0 && fmask
== 0)
6851 /* Save registers starting from high to low. The debuggers prefer at least
6852 the return register be stored at func+4, and also it allows us not to
6853 need a nop in the epilog if at least one register is reloaded in
6854 addition to return address. */
6856 /* Save GP registers if needed. */
6859 /* Pick which pointer to use as a base register. For small frames, just
6860 use the stack pointer. Otherwise, use a temporary register. Save 2
6861 cycles if the save area is near the end of a large frame, by reusing
6862 the constant created in the prologue/epilogue to adjust the stack
6865 gp_offset
= current_frame_info
.gp_sp_offset
;
6867 = gp_offset
- (current_frame_info
.gp_reg_size
6868 - GET_MODE_SIZE (gpr_mode
));
6870 if (gp_offset
< 0 || end_offset
< 0)
6872 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6873 (long) gp_offset
, (long) end_offset
);
6875 /* If we see a large frame in mips16 mode, we save the registers
6876 before adjusting the stack pointer, and load them afterward. */
6877 else if (TARGET_MIPS16
&& large_offset
> 32767)
6878 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
6880 else if (gp_offset
< 32768)
6881 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6883 else if (large_reg
!= 0
6884 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
6885 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6887 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6888 base_offset
= large_offset
;
6891 if (Pmode
== DImode
)
6892 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6893 stack_pointer_rtx
));
6895 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6896 stack_pointer_rtx
));
6899 fprintf (file
, "\t%s\t%s,%s,%s\n",
6900 Pmode
== DImode
? "daddu" : "addu",
6901 reg_names
[MIPS_TEMP2_REGNUM
],
6902 reg_names
[REGNO (large_reg
)],
6903 reg_names
[STACK_POINTER_REGNUM
]);
6907 base_offset
= gp_offset
;
6908 base_reg_rtx
= mips_add_large_offset_to_sp (base_offset
, file
);
6911 /* When we restore the registers in MIPS16 mode, then if we are
6912 using a frame pointer, and this is not a large frame, the
6913 current stack pointer will be offset by
6914 current_function_outgoing_args_size. Doing it this way lets
6915 us avoid offsetting the frame pointer before copying it into
6916 the stack pointer; there is no instruction to set the stack
6917 pointer to the sum of a register and a constant. */
6920 && frame_pointer_needed
6921 && large_offset
<= 32767)
6922 base_offset
+= current_function_outgoing_args_size
;
6924 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6925 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
6931 = gen_rtx (MEM
, gpr_mode
,
6932 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6933 GEN_INT (gp_offset
- base_offset
)));
6935 if (! current_function_calls_eh_return
)
6936 RTX_UNCHANGING_P (mem_rtx
) = 1;
6938 /* The mips16 does not have an instruction to load
6939 $31, so we load $7 instead, and work things out
6940 in mips_expand_epilogue. */
6941 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
6942 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
6943 /* The mips16 sometimes needs to save $18. */
6944 else if (TARGET_MIPS16
6945 && regno
!= GP_REG_FIRST
+ 31
6946 && ! M16_REG_P (regno
))
6949 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
6952 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
6953 emit_move_insn (reg_rtx
,
6954 gen_rtx (REG
, gpr_mode
, regno
));
6958 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
6961 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, gp_offset
);
6964 emit_move_insn (reg_rtx
, mem_rtx
);
6966 && regno
!= GP_REG_FIRST
+ 31
6967 && ! M16_REG_P (regno
))
6968 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
6976 /* The mips16 does not have an instruction to
6977 load $31, so we load $7 instead, and work
6978 things out in the caller. */
6979 if (TARGET_MIPS16
&& ! store_p
&& r
== GP_REG_FIRST
+ 31)
6980 r
= GP_REG_FIRST
+ 7;
6981 /* The mips16 sometimes needs to save $18. */
6983 && regno
!= GP_REG_FIRST
+ 31
6984 && ! M16_REG_P (regno
))
6987 r
= GP_REG_FIRST
+ 6;
6990 r
= GP_REG_FIRST
+ 3;
6991 fprintf (file
, "\tmove\t%s,%s\n",
6992 reg_names
[r
], reg_names
[regno
]);
6995 fprintf (file
, "\t%s\t%s,",
6997 ? (store_p
) ? "sd" : "ld"
6998 : (store_p
) ? "sw" : "lw"),
7000 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7001 gp_offset
- base_offset
);
7002 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
7005 && regno
!= GP_REG_FIRST
+ 31
7006 && ! M16_REG_P (regno
))
7007 fprintf (file
, "\tmove\t%s,%s\n",
7008 reg_names
[regno
], reg_names
[r
]);
7010 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
7012 /* If the restore is being supressed, still take into account
7013 the offset at which it is stored. */
7014 else if (BITSET_P (real_mask
, regno
- GP_REG_FIRST
))
7016 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
7020 base_reg_rtx
= 0, base_offset
= 0;
7022 /* Save floating point registers if needed. */
7025 /* Pick which pointer to use as a base register. */
7026 fp_offset
= current_frame_info
.fp_sp_offset
;
7027 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
7028 - UNITS_PER_FPVALUE
);
7030 if (fp_offset
< 0 || end_offset
< 0)
7032 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
7033 (long) fp_offset
, (long) end_offset
);
7035 else if (fp_offset
< 32768)
7036 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
7038 else if (base_reg_rtx
!= 0
7039 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
7040 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
7041 ; /* already set up for gp registers above */
7043 else if (large_reg
!= 0
7044 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
7045 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
7047 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
7048 base_offset
= large_offset
;
7051 if (Pmode
== DImode
)
7052 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
7053 stack_pointer_rtx
));
7055 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
7056 stack_pointer_rtx
));
7060 fprintf (file
, "\t%s\t%s,%s,%s\n",
7061 Pmode
== DImode
? "daddu" : "addu",
7062 reg_names
[MIPS_TEMP2_REGNUM
],
7063 reg_names
[REGNO (large_reg
)],
7064 reg_names
[STACK_POINTER_REGNUM
]);
7068 base_offset
= fp_offset
;
7069 base_reg_rtx
= mips_add_large_offset_to_sp (fp_offset
, file
);
7072 /* This loop must iterate over the same space as its companion in
7073 compute_frame_size. */
7074 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
7075 regno
>= FP_REG_FIRST
;
7077 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
7081 enum machine_mode sz
7082 = TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
7083 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
7084 rtx mem_rtx
= gen_rtx (MEM
, sz
,
7085 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
7088 if (! current_function_calls_eh_return
)
7089 RTX_UNCHANGING_P (mem_rtx
) = 1;
7092 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, fp_offset
);
7094 emit_move_insn (reg_rtx
, mem_rtx
);
7098 fprintf (file
, "\t%s\t%s,",
7099 (TARGET_SINGLE_FLOAT
7100 ? (store_p
? "s.s" : "l.s")
7101 : (store_p
? "s.d" : "l.d")),
7103 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7104 fp_offset
- base_offset
);
7105 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
7108 fp_offset
-= UNITS_PER_FPVALUE
;
7113 /* Set up the stack and frame (if desired) for the function. */
7116 mips_output_function_prologue (file
, size
)
7118 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7120 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7123 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7125 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
7127 #ifdef SDB_DEBUGGING_INFO
7128 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
7129 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
7132 /* In mips16 mode, we may need to generate a 32 bit to handle
7133 floating point arguments. The linker will arrange for any 32 bit
7134 functions to call this stub, which will then jump to the 16 bit
7136 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
7137 && current_function_args_info
.fp_code
!= 0)
7138 build_mips16_function_stub (file
);
7140 inside_function
= 1;
7142 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7143 /* Get the function name the same way that toplev.c does before calling
7144 assemble_start_function. This is needed so that the name used here
7145 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7146 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7148 if (!flag_inhibit_size_directive
)
7150 fputs ("\t.ent\t", file
);
7151 assemble_name (file
, fnname
);
7155 assemble_name (file
, fnname
);
7156 fputs (":\n", file
);
7159 if (!flag_inhibit_size_directive
)
7161 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7163 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7164 (reg_names
[(frame_pointer_needed
)
7165 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
7166 ((frame_pointer_needed
&& TARGET_MIPS16
)
7167 ? ((long) tsize
- current_function_outgoing_args_size
)
7169 reg_names
[GP_REG_FIRST
+ 31],
7170 current_frame_info
.var_size
,
7171 current_frame_info
.num_gp
,
7172 current_frame_info
.num_fp
,
7173 current_function_outgoing_args_size
,
7174 current_frame_info
.extra_size
);
7176 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7177 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7178 current_frame_info
.mask
,
7179 current_frame_info
.gp_save_offset
,
7180 current_frame_info
.fmask
,
7181 current_frame_info
.fp_save_offset
);
7184 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7185 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7188 if (mips_entry
&& ! mips_can_use_return_insn ())
7190 int save16
= BITSET_P (current_frame_info
.mask
, 16);
7191 int save17
= BITSET_P (current_frame_info
.mask
, 17);
7192 int save31
= BITSET_P (current_frame_info
.mask
, 31);
7196 /* Look through the initial insns to see if any of them store
7197 the function parameters into the incoming parameter storage
7198 area. If they do, we delete the insn, and save the register
7199 using the entry pseudo-instruction instead. We don't try to
7200 look past a label, jump, or call. */
7201 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
7203 rtx note
, set
, src
, dest
, base
, offset
;
7206 if (GET_CODE (insn
) == CODE_LABEL
7207 || GET_CODE (insn
) == JUMP_INSN
7208 || GET_CODE (insn
) == CALL_INSN
)
7210 if (GET_CODE (insn
) != INSN
)
7212 set
= PATTERN (insn
);
7213 if (GET_CODE (set
) != SET
)
7216 /* An insn storing a function parameter will still have a
7217 REG_EQUIV note on it mentioning the argument pointer. */
7218 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
7219 if (note
== NULL_RTX
)
7221 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
7224 src
= SET_SRC (set
);
7225 if (GET_CODE (src
) != REG
7226 || REGNO (src
) < GP_REG_FIRST
+ 4
7227 || REGNO (src
) > GP_REG_FIRST
+ 7)
7230 dest
= SET_DEST (set
);
7231 if (GET_CODE (dest
) != MEM
)
7233 if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned) UNITS_PER_WORD
)
7235 else if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned)2 * UNITS_PER_WORD
7236 && REGNO (src
) < GP_REG_FIRST
+ 7)
7240 offset
= const0_rtx
;
7241 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
7242 if (GET_CODE (base
) != REG
7243 || GET_CODE (offset
) != CONST_INT
)
7245 if (REGNO (base
) == (unsigned) STACK_POINTER_REGNUM
7246 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
7248 else if (REGNO (base
) == (unsigned) HARD_FRAME_POINTER_REGNUM
7251 + (REGNO (src
) - 4) * UNITS_PER_WORD
7252 - current_function_outgoing_args_size
)))
7257 /* This insn stores a parameter onto the stack, in the same
7258 location where the entry pseudo-instruction will put it.
7259 Delete the insn, and arrange to tell the entry
7260 instruction to save the register. */
7261 PUT_CODE (insn
, NOTE
);
7262 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7263 NOTE_SOURCE_FILE (insn
) = 0;
7265 hireg
= (REGNO (src
)
7266 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
7268 if (hireg
> savearg
)
7272 /* If this is a varargs function, we need to save all the
7273 registers onto the stack anyhow. */
7274 if (current_function_stdarg
|| current_function_varargs
)
7275 savearg
= GP_REG_FIRST
+ 7;
7277 fprintf (file
, "\tentry\t");
7280 if (savearg
== GP_REG_FIRST
+ 4)
7281 fprintf (file
, "%s", reg_names
[savearg
]);
7283 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
7284 reg_names
[savearg
]);
7286 if (save16
|| save17
)
7289 fprintf (file
, ",");
7290 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
7292 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
7296 if (savearg
> 0 || save16
|| save17
)
7297 fprintf (file
, ",");
7298 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
7300 fprintf (file
, "\n");
7303 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7305 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7307 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7308 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
7311 fprintf (file
, "\t%s\t%s,%s,%ld\n",
7312 (Pmode
== DImode
? "dsubu" : "subu"),
7313 sp_str
, sp_str
, (long) tsize
);
7314 fprintf (file
, "\t.cprestore %ld\n", current_frame_info
.args_size
);
7317 if (dwarf2out_do_frame ())
7318 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
7322 /* Expand the prologue into a bunch of separate insns. */
7325 mips_expand_prologue ()
7328 HOST_WIDE_INT tsize
;
7330 int last_arg_is_vararg_marker
= 0;
7331 tree fndecl
= current_function_decl
;
7332 tree fntype
= TREE_TYPE (fndecl
);
7333 tree fnargs
= DECL_ARGUMENTS (fndecl
);
7338 CUMULATIVE_ARGS args_so_far
;
7339 rtx reg_18_save
= NULL_RTX
;
7340 int store_args_on_stack
= (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
7341 && (! mips_entry
|| mips_can_use_return_insn ());
7343 /* If struct value address is treated as the first argument, make it so. */
7344 if (aggregate_value_p (DECL_RESULT (fndecl
))
7345 && ! current_function_returns_pcc_struct
7346 && struct_value_incoming_rtx
== 0)
7348 tree type
= build_pointer_type (fntype
);
7349 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
7351 DECL_ARG_TYPE (function_result_decl
) = type
;
7352 TREE_CHAIN (function_result_decl
) = fnargs
;
7353 fnargs
= function_result_decl
;
7356 /* For arguments passed in registers, find the register number
7357 of the first argument in the variable part of the argument list,
7358 otherwise GP_ARG_LAST+1. Note also if the last argument is
7359 the varargs special argument, and treat it as part of the
7362 This is only needed if store_args_on_stack is true. */
7364 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
7365 regno
= GP_ARG_FIRST
;
7367 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
7369 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
7370 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
7373 if (TREE_ADDRESSABLE (passed_type
))
7375 passed_type
= build_pointer_type (passed_type
);
7376 passed_mode
= Pmode
;
7379 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
7381 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
7382 next_arg
= TREE_CHAIN (cur_arg
);
7384 if (entry_parm
&& store_args_on_stack
)
7387 && DECL_NAME (cur_arg
)
7388 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7389 "__builtin_va_alist"))
7390 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7393 last_arg_is_vararg_marker
= 1;
7394 if (GET_CODE (entry_parm
) == REG
)
7395 regno
= REGNO (entry_parm
);
7397 regno
= GP_ARG_LAST
+ 1;
7404 if (GET_CODE (entry_parm
) != REG
)
7407 /* passed in a register, so will get homed automatically */
7408 if (GET_MODE (entry_parm
) == BLKmode
)
7409 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
7411 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
7413 regno
= REGNO (entry_parm
) + words
- 1;
7418 regno
= GP_ARG_LAST
+1;
7423 /* In order to pass small structures by value in registers compatibly with
7424 the MIPS compiler, we need to shift the value into the high part of the
7425 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7426 adjustments to be made as the next_arg_reg variable, so we split up the
7427 insns, and emit them separately. */
7429 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
7430 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
7432 rtvec adjust
= XVEC (next_arg_reg
, 0);
7433 int num
= GET_NUM_ELEM (adjust
);
7435 for (i
= 0; i
< num
; i
++)
7439 pattern
= RTVEC_ELT (adjust
, i
);
7440 if (GET_CODE (pattern
) != SET
7441 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
7442 abort_with_insn (pattern
, "insn is not a shift");
7443 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
7445 insn
= emit_insn (pattern
);
7447 /* Global life information isn't valid at this point, so we
7448 can't check whether these shifts are actually used. Mark
7449 them MAYBE_DEAD so that flow2 will remove them, and not
7450 complain about dead code in the prologue. */
7451 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, NULL_RTX
,
7456 tsize
= compute_frame_size (get_frame_size ());
7458 /* If this function is a varargs function, store any registers that
7459 would normally hold arguments ($4 - $7) on the stack. */
7460 if (store_args_on_stack
7461 && ((TYPE_ARG_TYPES (fntype
) != 0
7462 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
7464 || last_arg_is_vararg_marker
))
7466 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
7467 rtx ptr
= stack_pointer_rtx
;
7469 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7470 if (TARGET_ABICALLS
)
7473 for (; regno
<= GP_ARG_LAST
; regno
++)
7476 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
7477 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
7478 gen_rtx (REG
, gpr_mode
, regno
));
7480 offset
+= GET_MODE_SIZE (gpr_mode
);
7484 /* If we are using the entry pseudo instruction, it will
7485 automatically subtract 32 from the stack pointer, so we don't
7486 need to. The entry pseudo instruction is emitted by
7487 function_prologue. */
7488 if (mips_entry
&& ! mips_can_use_return_insn ())
7490 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
7494 /* If we are using a frame pointer with a small stack frame,
7495 we need to initialize it here since it won't be done
7497 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7499 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7500 if (Pmode
== DImode
)
7501 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7505 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7509 else if (Pmode
== DImode
)
7510 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7511 stack_pointer_rtx
));
7513 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7514 stack_pointer_rtx
));
7516 RTX_FRAME_RELATED_P (insn
) = 1;
7519 /* We may need to save $18, if it is used to call a function
7520 which may return a floating point value. Set up a sequence
7521 of instructions to do so. Later on we emit them at the right
7523 if (TARGET_MIPS16
&& BITSET_P (current_frame_info
.mask
, 18))
7525 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
7526 long gp_offset
, base_offset
;
7528 gp_offset
= current_frame_info
.gp_sp_offset
;
7529 if (BITSET_P (current_frame_info
.mask
, 16))
7530 gp_offset
-= UNITS_PER_WORD
;
7531 if (BITSET_P (current_frame_info
.mask
, 17))
7532 gp_offset
-= UNITS_PER_WORD
;
7533 if (BITSET_P (current_frame_info
.mask
, 31))
7534 gp_offset
-= UNITS_PER_WORD
;
7536 base_offset
= tsize
;
7540 emit_move_insn (reg_rtx
,
7541 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
7542 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
7543 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
7547 reg_18_save
= gen_sequence ();
7556 if (reg_18_save
!= NULL_RTX
)
7557 emit_insn (reg_18_save
);
7563 rtx tsize_rtx
= GEN_INT (tsize
);
7565 /* If we are doing svr4-abi, sp move is done by
7566 function_prologue. In mips16 mode with a large frame, we
7567 save the registers before adjusting the stack. */
7568 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7569 && (!TARGET_MIPS16
|| tsize
<= 32767))
7571 rtx adjustment_rtx
, insn
, dwarf_pattern
;
7575 adjustment_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
7576 emit_move_insn (adjustment_rtx
, tsize_rtx
);
7579 adjustment_rtx
= tsize_rtx
;
7581 if (Pmode
== DImode
)
7582 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7585 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7588 dwarf_pattern
= gen_rtx_SET (Pmode
, stack_pointer_rtx
,
7589 plus_constant (stack_pointer_rtx
,
7592 mips_annotate_frame_insn (insn
, dwarf_pattern
);
7596 save_restore_insns (1, tmp_rtx
, tsize
, (FILE *)0);
7597 else if (reg_18_save
!= NULL_RTX
)
7598 emit_insn (reg_18_save
);
7600 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7606 if (!frame_pointer_needed
)
7609 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
7610 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7611 emit_move_insn (reg_rtx
, tsize_rtx
);
7612 if (Pmode
== DImode
)
7613 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
7614 hard_frame_pointer_rtx
,
7617 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
7618 hard_frame_pointer_rtx
,
7620 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
7623 if (frame_pointer_needed
)
7627 /* On the mips16, we encourage the use of unextended
7628 instructions when using the frame pointer by pointing the
7629 frame pointer ahead of the argument space allocated on
7631 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7635 /* In this case, we have already copied the stack
7636 pointer into the frame pointer, above. We need only
7637 adjust for the outgoing argument size. */
7638 if (current_function_outgoing_args_size
!= 0)
7640 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7641 if (Pmode
== DImode
)
7642 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7643 hard_frame_pointer_rtx
,
7646 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7647 hard_frame_pointer_rtx
,
7651 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7653 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7654 if (Pmode
== DImode
)
7655 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7659 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7663 else if (Pmode
== DImode
)
7664 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7665 stack_pointer_rtx
));
7667 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7668 stack_pointer_rtx
));
7671 RTX_FRAME_RELATED_P (insn
) = 1;
7674 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7675 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
7676 gen_rtx_REG (DImode
, 25)));
7679 /* If we are profiling, make sure no instructions are scheduled before
7680 the call to mcount. */
7682 if (current_function_profile
)
7683 emit_insn (gen_blockage ());
7686 /* Do any necessary cleanup after a function to restore stack, frame,
7689 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7690 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7693 mips_output_function_epilogue (file
, size
)
7694 FILE *file ATTRIBUTE_UNUSED
;
7695 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7697 const char *fnname
= ""; /* FIXME: Correct initialisation? */
7699 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7700 /* Get the function name the same way that toplev.c does before calling
7701 assemble_start_function. This is needed so that the name used here
7702 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7703 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7705 if (!flag_inhibit_size_directive
)
7707 fputs ("\t.end\t", file
);
7708 assemble_name (file
, fnname
);
7715 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
7716 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
7717 int num_regs
= num_gp_regs
+ num_fp_regs
;
7718 const char *name
= fnname
;
7723 dslots_load_total
+= num_regs
;
7726 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7727 name
, frame_pointer_needed
? 'y' : 'n',
7728 (current_frame_info
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
7729 current_function_calls_alloca
? 'y' : 'n',
7730 current_function_calls_setjmp
? 'y' : 'n',
7731 current_frame_info
.total_size
,
7732 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
7733 dslots_load_total
, dslots_load_filled
,
7734 dslots_jump_total
, dslots_jump_filled
,
7735 num_refs
[0], num_refs
[1], num_refs
[2]);
7737 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
7740 " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
7741 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
7744 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
7747 " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
7748 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
7751 fputc ('\n', stderr
);
7754 /* Reset state info for each function. */
7755 inside_function
= 0;
7756 ignore_line_number
= 0;
7757 dslots_load_total
= 0;
7758 dslots_jump_total
= 0;
7759 dslots_load_filled
= 0;
7760 dslots_jump_filled
= 0;
7766 current_frame_info
= zero_frame_info
;
7768 while (string_constants
!= NULL
)
7770 struct string_constant
*next
;
7772 next
= string_constants
->next
;
7773 free (string_constants
);
7774 string_constants
= next
;
7777 /* Restore the output file if optimizing the GP (optimizing the GP causes
7778 the text to be diverted to a tempfile, so that data decls come before
7779 references to the data). */
7780 if (TARGET_FILE_SWITCHING
)
7782 asm_out_file
= asm_out_data_file
;
7787 /* Expand the epilogue into a bunch of separate insns. */
7790 mips_expand_epilogue ()
7792 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7793 rtx tsize_rtx
= GEN_INT (tsize
);
7794 rtx tmp_rtx
= (rtx
)0;
7796 if (mips_can_use_return_insn ())
7798 emit_insn (gen_return ());
7802 if (mips_entry
&& ! mips_can_use_return_insn ())
7805 if (tsize
> 32767 && ! TARGET_MIPS16
)
7807 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
7808 emit_move_insn (tmp_rtx
, tsize_rtx
);
7809 tsize_rtx
= tmp_rtx
;
7814 long orig_tsize
= tsize
;
7816 if (frame_pointer_needed
)
7818 emit_insn (gen_blockage ());
7820 /* On the mips16, the frame pointer is offset from the stack
7821 pointer by current_function_outgoing_args_size. We
7822 account for that by changing tsize. Note that this can
7823 actually make tsize negative. */
7826 tsize
-= current_function_outgoing_args_size
;
7828 /* If we have a large frame, it's easier to add to $6
7829 than to $sp, since the mips16 has no instruction to
7830 add a register to $sp. */
7831 if (orig_tsize
> 32767)
7833 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7835 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
7836 if (Pmode
== DImode
)
7837 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7838 hard_frame_pointer_rtx
,
7841 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7842 hard_frame_pointer_rtx
,
7847 if (tsize
&& tsize
!= orig_tsize
)
7848 tsize_rtx
= GEN_INT (tsize
);
7851 if (Pmode
== DImode
)
7852 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7854 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7857 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7858 are going to restore it, then we must emit a blockage insn to
7859 prevent the scheduler from moving the restore out of the epilogue. */
7860 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
7861 && (current_frame_info
.mask
7862 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
7863 emit_insn (gen_blockage ());
7865 save_restore_insns (0, tmp_rtx
, orig_tsize
, (FILE *)0);
7867 /* In mips16 mode with a large frame, we adjust the stack
7868 pointer before restoring the registers. In this case, we
7869 should always be using a frame pointer, so everything should
7870 have been handled above. */
7871 if (tsize
> 32767 && TARGET_MIPS16
)
7874 if (current_function_calls_eh_return
)
7876 rtx eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7877 if (Pmode
== DImode
)
7878 emit_insn (gen_adddi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7880 emit_insn (gen_addsi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7884 emit_insn (gen_blockage ());
7886 if (tsize
!= 0 || current_function_calls_eh_return
)
7890 if (Pmode
== DImode
)
7891 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7894 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7899 /* We need to work around not being able to add a register
7900 to the stack pointer directly. Use register $6 as an
7901 intermediate step. */
7903 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7905 if (Pmode
== DImode
)
7907 emit_insn (gen_movdi (g6_rtx
, stack_pointer_rtx
));
7908 emit_insn (gen_adddi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7909 emit_insn (gen_movdi (stack_pointer_rtx
, g6_rtx
));
7913 emit_insn (gen_movsi (g6_rtx
, stack_pointer_rtx
));
7914 emit_insn (gen_addsi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7915 emit_insn (gen_movsi (stack_pointer_rtx
, g6_rtx
));
7922 /* The mips16 loads the return address into $7, not $31. */
7923 if (TARGET_MIPS16
&& (current_frame_info
.mask
& RA_MASK
) != 0)
7924 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7925 GP_REG_FIRST
+ 7)));
7927 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7928 GP_REG_FIRST
+ 31)));
7931 /* Return nonzero if this function is known to have a null epilogue.
7932 This allows the optimizer to omit jumps to jumps if no stack
7936 mips_can_use_return_insn ()
7940 if (! reload_completed
)
7943 if (regs_ever_live
[31] || current_function_profile
)
7946 return_type
= DECL_RESULT (current_function_decl
);
7948 /* In mips16 mode, a function which returns a floating point value
7949 needs to arrange to copy the return value into the floating point
7952 && mips16_hard_float
7953 && ! aggregate_value_p (return_type
)
7954 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
7955 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
7958 if (current_frame_info
.initialized
)
7959 return current_frame_info
.total_size
== 0;
7961 return compute_frame_size (get_frame_size ()) == 0;
7964 /* Returns non-zero if X contains a SYMBOL_REF. */
7967 symbolic_expression_p (x
)
7970 if (GET_CODE (x
) == SYMBOL_REF
)
7973 if (GET_CODE (x
) == CONST
)
7974 return symbolic_expression_p (XEXP (x
, 0));
7976 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
7977 return symbolic_expression_p (XEXP (x
, 0));
7979 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
7980 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
7981 return (symbolic_expression_p (XEXP (x
, 0))
7982 || symbolic_expression_p (XEXP (x
, 1)));
7987 /* Choose the section to use for the constant rtx expression X that has
7991 mips_select_rtx_section (mode
, x
)
7992 enum machine_mode mode
;
7993 rtx x ATTRIBUTE_UNUSED
;
7997 /* In mips16 mode, the constant table always goes in the same section
7998 as the function, so that constants can be loaded using PC relative
8000 function_section (current_function_decl
);
8002 else if (TARGET_EMBEDDED_DATA
)
8004 /* For embedded applications, always put constants in read-only data,
8005 in order to reduce RAM usage. */
8006 READONLY_DATA_SECTION ();
8010 /* For hosted applications, always put constants in small data if
8011 possible, as this gives the best performance. */
8013 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
8014 && mips_section_threshold
> 0)
8015 SMALL_DATA_SECTION ();
8016 else if (flag_pic
&& symbolic_expression_p (x
))
8017 /* Any expression involving a SYMBOL_REF might need a run-time
8018 relocation. (The symbol might be defined in a shared
8019 library loaded at an unexpected base address.) So, we must
8020 put such expressions in the data segment (which is
8021 writable), rather than the text segment (which is
8025 READONLY_DATA_SECTION ();
8029 /* Choose the section to use for DECL. RELOC is true if its value contains
8030 any relocatable expression.
8032 Some of the logic used here needs to be replicated in
8033 ENCODE_SECTION_INFO in mips.h so that references to these symbols
8034 are done correctly. Specifically, at least all symbols assigned
8035 here to rom (.text and/or .rodata) must not be referenced via
8036 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
8038 If you need to make a change here, you probably should check
8039 ENCODE_SECTION_INFO to see if it needs a similar change. */
8042 mips_select_section (decl
, reloc
)
8046 int size
= int_size_in_bytes (TREE_TYPE (decl
));
8048 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
8049 && TREE_CODE (decl
) == STRING_CST
8050 && !flag_writable_strings
)
8051 /* For embedded position independent code, put constant strings in the
8052 text section, because the data section is limited to 64K in size.
8053 For mips16 code, put strings in the text section so that a PC
8054 relative load instruction can be used to get their address. */
8056 else if (TARGET_EMBEDDED_DATA
)
8058 /* For embedded applications, always put an object in read-only data
8059 if possible, in order to reduce RAM usage. */
8061 if (((TREE_CODE (decl
) == VAR_DECL
8062 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8063 && DECL_INITIAL (decl
)
8064 && (DECL_INITIAL (decl
) == error_mark_node
8065 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8066 /* Deal with calls from output_constant_def_contents. */
8067 || (TREE_CODE (decl
) != VAR_DECL
8068 && (TREE_CODE (decl
) != STRING_CST
8069 || !flag_writable_strings
)))
8070 && ! (flag_pic
&& reloc
))
8071 READONLY_DATA_SECTION ();
8072 else if (size
> 0 && size
<= mips_section_threshold
)
8073 SMALL_DATA_SECTION ();
8079 /* For hosted applications, always put an object in small data if
8080 possible, as this gives the best performance. */
8082 if (size
> 0 && size
<= mips_section_threshold
)
8083 SMALL_DATA_SECTION ();
8084 else if (((TREE_CODE (decl
) == VAR_DECL
8085 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8086 && DECL_INITIAL (decl
)
8087 && (DECL_INITIAL (decl
) == error_mark_node
8088 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8089 /* Deal with calls from output_constant_def_contents. */
8090 || (TREE_CODE (decl
) != VAR_DECL
8091 && (TREE_CODE (decl
) != STRING_CST
8092 || !flag_writable_strings
)))
8093 && ! (flag_pic
&& reloc
))
8094 READONLY_DATA_SECTION ();
8100 /* Return register to use for a function return value with VALTYPE for
8101 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8104 mips_function_value (valtype
, func
, mode
)
8106 tree func ATTRIBUTE_UNUSED
;
8107 enum machine_mode mode
;
8109 int reg
= GP_RETURN
;
8110 enum mode_class mclass
;
8115 mode
= TYPE_MODE (valtype
);
8116 unsignedp
= TREE_UNSIGNED (valtype
);
8118 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8119 the mode just as PROMOTE_MODE does. */
8120 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
8122 mclass
= GET_MODE_CLASS (mode
);
8124 if (mclass
== MODE_FLOAT
&& GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
8127 else if (mclass
== MODE_COMPLEX_FLOAT
8128 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
* 2)
8130 enum machine_mode cmode
= GET_MODE_INNER (mode
);
8132 return gen_rtx_PARALLEL
8135 gen_rtx_EXPR_LIST (VOIDmode
,
8136 gen_rtx_REG (cmode
, FP_RETURN
),
8138 gen_rtx_EXPR_LIST (VOIDmode
,
8139 gen_rtx_REG (cmode
, FP_RETURN
+ FP_INC
),
8140 GEN_INT (GET_MODE_SIZE (cmode
)))));
8143 else if (valtype
&& TREE_CODE (valtype
) == RECORD_TYPE
8144 && mips_abi
!= ABI_32
8145 && mips_abi
!= ABI_O64
8146 && mips_abi
!= ABI_EABI
)
8148 /* A struct with only one or two floating point fields is returned in
8149 the floating point registers. */
8150 tree field
, fields
[2];
8153 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
8154 field
= TREE_CHAIN (field
))
8156 if (TREE_CODE (field
) != FIELD_DECL
)
8159 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
8162 fields
[i
++] = field
;
8165 /* Must check i, so that we reject structures with no elements. */
8170 /* The structure has DImode, but we don't allow DImode values
8171 in FP registers, so we use a PARALLEL even though it isn't
8172 strictly necessary. */
8173 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
8175 return gen_rtx_PARALLEL
8178 gen_rtx_EXPR_LIST (VOIDmode
,
8179 gen_rtx_REG (field_mode
,
8186 enum machine_mode first_mode
8187 = TYPE_MODE (TREE_TYPE (fields
[0]));
8188 enum machine_mode second_mode
8189 = TYPE_MODE (TREE_TYPE (fields
[1]));
8190 HOST_WIDE_INT first_offset
= int_byte_position (fields
[0]);
8191 HOST_WIDE_INT second_offset
= int_byte_position (fields
[1]);
8193 return gen_rtx_PARALLEL
8196 gen_rtx_EXPR_LIST (VOIDmode
,
8197 gen_rtx_REG (first_mode
,
8199 GEN_INT (first_offset
)),
8200 gen_rtx_EXPR_LIST (VOIDmode
,
8201 gen_rtx_REG (second_mode
,
8203 GEN_INT (second_offset
))));
8208 return gen_rtx_REG (mode
, reg
);
8211 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8212 nonzero when an argument must be passed by reference. */
8215 function_arg_pass_by_reference (cum
, mode
, type
, named
)
8216 const CUMULATIVE_ARGS
*cum
;
8217 enum machine_mode mode
;
8219 int named ATTRIBUTE_UNUSED
;
8223 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
8226 /* We must pass by reference if we would be both passing in registers
8227 and the stack. This is because any subsequent partial arg would be
8228 handled incorrectly in this case.
8230 ??? This is really a kludge. We should either fix GCC so that such
8231 a situation causes an abort and then do something in the MIPS port
8232 to prevent it, or add code to function.c to properly handle the case. */
8233 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8234 here hopefully is not relevant to mips_va_arg. */
8235 if (cum
&& MUST_PASS_IN_STACK (mode
, type
)
8236 && mips_abi
!= ABI_MEABI
8237 && FUNCTION_ARG (*cum
, mode
, type
, named
) != 0)
8240 /* Otherwise, we only do this if EABI is selected. */
8241 if (mips_abi
!= ABI_EABI
)
8244 /* ??? How should SCmode be handled? */
8245 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
8248 size
= int_size_in_bytes (type
);
8249 return size
== -1 || size
> UNITS_PER_WORD
;
8252 /* This function returns the register class required for a secondary
8253 register when copying between one of the registers in CLASS, and X,
8254 using MODE. If IN_P is nonzero, the copy is going from X to the
8255 register, otherwise the register is the source. A return value of
8256 NO_REGS means that no secondary register is required. */
8259 mips_secondary_reload_class (class, mode
, x
, in_p
)
8260 enum reg_class
class;
8261 enum machine_mode mode
;
8265 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
8269 if (GET_CODE (x
) == SIGN_EXTEND
)
8275 /* We may be called with reg_renumber NULL from regclass.
8276 ??? This is probably a bug. */
8278 regno
= true_regnum (x
);
8281 while (GET_CODE (x
) == SUBREG
)
8283 off
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
8284 GET_MODE (SUBREG_REG (x
)),
8290 if (GET_CODE (x
) == REG
)
8291 regno
= REGNO (x
) + off
;
8295 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
8296 regno
= true_regnum (x
);
8298 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
8300 /* We always require a general register when copying anything to
8301 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8302 to a general register, or when copying from register 0. */
8303 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
8306 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8307 ? NO_REGS
: gr_regs
);
8308 else if (regno
== HILO_REGNUM
)
8311 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8312 ? NO_REGS
: gr_regs
);
8314 /* Copying from HI or LO to anywhere other than a general register
8315 requires a general register. */
8316 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
8318 if (TARGET_MIPS16
&& in_p
)
8320 /* We can't really copy to HI or LO at all in mips16 mode. */
8323 return gp_reg_p
? NO_REGS
: gr_regs
;
8325 if (MD_REG_P (regno
))
8327 if (TARGET_MIPS16
&& ! in_p
)
8329 /* We can't really copy to HI or LO at all in mips16 mode. */
8332 return class == gr_regs
? NO_REGS
: gr_regs
;
8335 /* We can only copy a value to a condition code register from a
8336 floating point register, and even then we require a scratch
8337 floating point register. We can only copy a value out of a
8338 condition code register into a general register. */
8339 if (class == ST_REGS
)
8343 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8345 if (ST_REG_P (regno
))
8349 return class == GR_REGS
? NO_REGS
: GR_REGS
;
8352 /* In mips16 mode, going between memory and anything but M16_REGS
8353 requires an M16_REG. */
8356 if (class != M16_REGS
&& class != M16_NA_REGS
)
8364 /* The stack pointer isn't a valid operand to an add instruction,
8365 so we need to load it into M16_REGS first. This can happen as
8366 a result of register elimination and form_sum converting
8367 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8368 need an extra register if the dest is the same as the other
8369 register. In that case, we can't fix the problem by loading SP
8370 into the dest first. */
8371 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
8372 && GET_CODE (XEXP (x
, 1)) == REG
8373 && (XEXP (x
, 0) == stack_pointer_rtx
8374 || XEXP (x
, 1) == stack_pointer_rtx
))
8375 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
8377 if (class == M16_REGS
|| class == M16_NA_REGS
)
8386 /* This function returns the maximum number of consecutive registers
8387 needed to represent mode MODE in registers of class CLASS. */
8390 mips_class_max_nregs (class, mode
)
8391 enum reg_class
class;
8392 enum machine_mode mode
;
8394 if (class == FP_REGS
)
8397 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8400 /* For each mips16 function which refers to GP relative symbols, we
8401 use a pseudo register, initialized at the start of the function, to
8402 hold the $gp value. */
8405 mips16_gp_pseudo_reg ()
8407 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
8412 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
8413 RTX_UNCHANGING_P (cfun
->machine
->mips16_gp_pseudo_rtx
) = 1;
8415 /* We want to initialize this to a value which gcc will believe
8417 const_gp
= gen_rtx (CONST
, Pmode
,
8418 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
8421 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
8423 insn
= gen_sequence ();
8426 push_topmost_sequence ();
8427 /* We need to emit the initialization after the FUNCTION_BEG
8428 note, so that it will be integrated. */
8429 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
8430 if (GET_CODE (scan
) == NOTE
8431 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
8433 if (scan
== NULL_RTX
)
8434 scan
= get_insns ();
8435 insn
= emit_insn_after (insn
, scan
);
8436 pop_topmost_sequence ();
8439 return cfun
->machine
->mips16_gp_pseudo_rtx
;
8442 /* Return an RTX which represents the signed 16 bit offset from the
8443 $gp register for the given symbol. This is only used on the
8447 mips16_gp_offset (sym
)
8452 if (GET_CODE (sym
) != SYMBOL_REF
8453 || ! SYMBOL_REF_FLAG (sym
))
8456 /* We use a special identifier to represent the value of the gp
8458 gp
= get_identifier ("__mips16_gp_value");
8460 return gen_rtx (CONST
, Pmode
,
8461 gen_rtx (MINUS
, Pmode
, sym
,
8462 gen_rtx (SYMBOL_REF
, Pmode
,
8463 IDENTIFIER_POINTER (gp
))));
8466 /* Return nonzero if the given RTX represents a signed 16 bit offset
8467 from the $gp register. */
8470 mips16_gp_offset_p (x
)
8473 if (GET_CODE (x
) == CONST
)
8476 /* It's OK to add a small integer value to a gp offset. */
8477 if (GET_CODE (x
) == PLUS
)
8479 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8480 && SMALL_INT (XEXP (x
, 1)))
8481 return mips16_gp_offset_p (XEXP (x
, 0));
8482 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
8483 && SMALL_INT (XEXP (x
, 0)))
8484 return mips16_gp_offset_p (XEXP (x
, 1));
8488 /* Make sure it is in the form SYM - __mips16_gp_value. */
8489 return (GET_CODE (x
) == MINUS
8490 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
8491 && SYMBOL_REF_FLAG (XEXP (x
, 0))
8492 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8493 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
8496 /* Output a GP offset. We don't want to print the subtraction of
8497 __mips16_gp_value; it is implicitly represented by the %gprel which
8498 should have been printed by the caller. */
8501 mips16_output_gp_offset (file
, x
)
8505 if (GET_CODE (x
) == CONST
)
8508 if (GET_CODE (x
) == PLUS
)
8510 mips16_output_gp_offset (file
, XEXP (x
, 0));
8512 mips16_output_gp_offset (file
, XEXP (x
, 1));
8516 if (GET_CODE (x
) == MINUS
8517 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8518 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
8520 mips16_output_gp_offset (file
, XEXP (x
, 0));
8524 output_addr_const (file
, x
);
8527 /* Return nonzero if a constant should not be output until after the
8528 function. This is true of most string constants, so that we can
8529 use a more efficient PC relative reference. However, a static
8530 inline function may never call assemble_function_end to write out
8531 the constant pool, so don't try to postpone the constant in that
8534 ??? It's really a bug that a static inline function can put stuff
8535 in the constant pool even if the function itself is not output.
8537 We record which string constants we've seen, so that we know which
8538 ones might use the more efficient reference. */
8541 mips16_constant_after_function_p (x
)
8544 if (TREE_CODE (x
) == STRING_CST
8545 && ! flag_writable_strings
8546 && current_function_decl
!= 0
8547 && ! DECL_DEFER_OUTPUT (current_function_decl
)
8548 && ! (DECL_INLINE (current_function_decl
)
8549 && ((! TREE_PUBLIC (current_function_decl
)
8550 && ! TREE_ADDRESSABLE (current_function_decl
)
8551 && ! flag_keep_inline_functions
)
8552 || DECL_EXTERNAL (current_function_decl
))))
8554 struct string_constant
*n
;
8556 n
= (struct string_constant
*) xmalloc (sizeof *n
);
8557 n
->label
= XSTR (XEXP (TREE_CST_RTL (x
), 0), 0);
8558 n
->next
= string_constants
;
8559 string_constants
= n
;
8567 /* Validate a constant for the mips16. This rejects general symbolic
8568 addresses, which must be loaded from memory. If ADDR is nonzero,
8569 this should reject anything which is not a legal address. If
8570 ADDEND is nonzero, this is being added to something else. */
8573 mips16_constant (x
, mode
, addr
, addend
)
8575 enum machine_mode mode
;
8579 while (GET_CODE (x
) == CONST
)
8582 switch (GET_CODE (x
))
8588 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
8589 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
8592 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8594 if (CONSTANT_POOL_ADDRESS_P (x
))
8597 /* If we aren't looking for a memory address, we can accept a GP
8598 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8599 knows how to handle this. We can always accept a string
8600 constant, which is the other case in which SYMBOL_REF_FLAG
8604 && SYMBOL_REF_FLAG (x
)
8605 && mode
== (enum machine_mode
) Pmode
)
8608 /* We can accept a string constant, which will have
8609 SYMBOL_REF_FLAG set but must be recognized by name to
8610 distinguish from a GP accessible symbol. The name of a
8611 string constant will have been generated by
8612 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8613 if (SYMBOL_REF_FLAG (x
))
8615 const char *name
= XSTR (x
, 0);
8617 return (name
[0] == '*'
8618 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
8619 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
8625 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8630 if (addr
&& ! addend
)
8632 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
8635 /* We need to treat $gp as a legitimate constant, because
8636 mips16_gp_pseudo_reg assumes that. */
8637 return REGNO (x
) == GP_REG_FIRST
+ 28;
8641 /* Write out code to move floating point arguments in or out of
8642 general registers. Output the instructions to FILE. FP_CODE is
8643 the code describing which arguments are present (see the comment at
8644 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8645 we are copying from the floating point registers. */
8648 mips16_fp_args (file
, fp_code
, from_fp_p
)
8657 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8658 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8665 gparg
= GP_ARG_FIRST
;
8666 fparg
= FP_ARG_FIRST
;
8667 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8671 if ((fparg
& 1) != 0)
8673 fprintf (file
, "\t%s\t%s,%s\n", s
,
8674 reg_names
[gparg
], reg_names
[fparg
]);
8676 else if ((f
& 3) == 2)
8679 fprintf (file
, "\td%s\t%s,%s\n", s
,
8680 reg_names
[gparg
], reg_names
[fparg
]);
8683 if ((fparg
& 1) != 0)
8685 if (TARGET_BIG_ENDIAN
)
8686 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8687 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
8688 reg_names
[gparg
+ 1], reg_names
[fparg
]);
8690 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8691 reg_names
[gparg
], reg_names
[fparg
], s
,
8692 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
8705 /* Build a mips16 function stub. This is used for functions which
8706 take aruments in the floating point registers. It is 32 bit code
8707 that moves the floating point args into the general registers, and
8708 then jumps to the 16 bit code. */
8711 build_mips16_function_stub (file
)
8715 char *secname
, *stubname
;
8716 tree stubid
, stubdecl
;
8720 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8721 secname
= (char *) alloca (strlen (fnname
) + 20);
8722 sprintf (secname
, ".mips16.fn.%s", fnname
);
8723 stubname
= (char *) alloca (strlen (fnname
) + 20);
8724 sprintf (stubname
, "__fn_stub_%s", fnname
);
8725 stubid
= get_identifier (stubname
);
8726 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8727 build_function_type (void_type_node
, NULL_TREE
));
8728 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8730 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
8732 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
8734 fprintf (file
, "%s%s",
8735 need_comma
? ", " : "",
8736 (f
& 3) == 1 ? "float" : "double");
8739 fprintf (file
, ")\n");
8741 fprintf (file
, "\t.set\tnomips16\n");
8742 function_section (stubdecl
);
8743 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
8745 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8746 within a .ent, and we can not emit another .ent. */
8747 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8748 fputs ("\t.ent\t", file
);
8749 assemble_name (file
, stubname
);
8753 assemble_name (file
, stubname
);
8754 fputs (":\n", file
);
8756 /* We don't want the assembler to insert any nops here. */
8757 fprintf (file
, "\t.set\tnoreorder\n");
8759 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
8761 fprintf (asm_out_file
, "\t.set\tnoat\n");
8762 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
8763 assemble_name (file
, fnname
);
8764 fprintf (file
, "\n");
8765 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8766 fprintf (asm_out_file
, "\t.set\tat\n");
8768 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8769 with one of the mfc1 instructions, because the result is not
8770 available for one instruction, so if the very first instruction
8771 in the function refers to the register, it will see the wrong
8773 fprintf (file
, "\tnop\n");
8775 fprintf (file
, "\t.set\treorder\n");
8777 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8778 fputs ("\t.end\t", file
);
8779 assemble_name (file
, stubname
);
8783 fprintf (file
, "\t.set\tmips16\n");
8785 function_section (current_function_decl
);
8788 /* We keep a list of functions for which we have already built stubs
8789 in build_mips16_call_stub. */
8793 struct mips16_stub
*next
;
8798 static struct mips16_stub
*mips16_stubs
;
8800 /* Build a call stub for a mips16 call. A stub is needed if we are
8801 passing any floating point values which should go into the floating
8802 point registers. If we are, and the call turns out to be to a 32
8803 bit function, the stub will be used to move the values into the
8804 floating point registers before calling the 32 bit function. The
8805 linker will magically adjust the function call to either the 16 bit
8806 function or the 32 bit stub, depending upon where the function call
8807 is actually defined.
8809 Similarly, we need a stub if the return value might come back in a
8810 floating point register.
8812 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8813 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8814 is the code built by function_arg. This function returns a nonzero
8815 value if it builds the call instruction itself. */
8818 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
8827 char *secname
, *stubname
;
8828 struct mips16_stub
*l
;
8829 tree stubid
, stubdecl
;
8833 /* We don't need to do anything if we aren't in mips16 mode, or if
8834 we were invoked with the -msoft-float option. */
8835 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8838 /* Figure out whether the value might come back in a floating point
8840 fpret
= (retval
!= 0
8841 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8842 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
8844 /* We don't need to do anything if there were no floating point
8845 arguments and the value will not be returned in a floating point
8847 if (fp_code
== 0 && ! fpret
)
8850 if (GET_CODE (fnmem
) != MEM
)
8852 fn
= XEXP (fnmem
, 0);
8854 /* We don't need to do anything if this is a call to a special
8855 mips16 support function. */
8856 if (GET_CODE (fn
) == SYMBOL_REF
8857 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8860 /* This code will only work for o32 and o64 abis. The other ABI's
8861 require more sophisticated support. */
8862 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8865 /* We can only handle SFmode and DFmode floating point return
8867 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
8870 /* If we're calling via a function pointer, then we must always call
8871 via a stub. There are magic stubs provided in libgcc.a for each
8872 of the required cases. Each of them expects the function address
8873 to arrive in register $2. */
8875 if (GET_CODE (fn
) != SYMBOL_REF
)
8879 rtx stub_fn
, stub_mem
, insn
;
8881 /* ??? If this code is modified to support other ABI's, we need
8882 to handle PARALLEL return values here. */
8884 sprintf (buf
, "__mips16_call_stub_%s%d",
8886 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
8889 id
= get_identifier (buf
);
8890 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
8891 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
8893 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
8895 if (retval
== NULL_RTX
)
8896 insn
= gen_call_internal0 (stub_mem
, arg_size
,
8897 gen_rtx (REG
, SImode
,
8898 GP_REG_FIRST
+ 31));
8900 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
8901 gen_rtx (REG
, SImode
,
8902 GP_REG_FIRST
+ 31));
8903 insn
= emit_call_insn (insn
);
8905 /* Put the register usage information on the CALL. */
8906 if (GET_CODE (insn
) != CALL_INSN
)
8908 CALL_INSN_FUNCTION_USAGE (insn
) =
8909 gen_rtx (EXPR_LIST
, VOIDmode
,
8910 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
8911 CALL_INSN_FUNCTION_USAGE (insn
));
8913 /* If we are handling a floating point return value, we need to
8914 save $18 in the function prologue. Putting a note on the
8915 call will mean that regs_ever_live[$18] will be true if the
8916 call is not eliminated, and we can check that in the prologue
8919 CALL_INSN_FUNCTION_USAGE (insn
) =
8920 gen_rtx (EXPR_LIST
, VOIDmode
,
8921 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8922 CALL_INSN_FUNCTION_USAGE (insn
));
8924 /* Return 1 to tell the caller that we've generated the call
8929 /* We know the function we are going to call. If we have already
8930 built a stub, we don't need to do anything further. */
8932 fnname
= XSTR (fn
, 0);
8933 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8934 if (strcmp (l
->name
, fnname
) == 0)
8939 /* Build a special purpose stub. When the linker sees a
8940 function call in mips16 code, it will check where the target
8941 is defined. If the target is a 32 bit call, the linker will
8942 search for the section defined here. It can tell which
8943 symbol this section is associated with by looking at the
8944 relocation information (the name is unreliable, since this
8945 might be a static function). If such a section is found, the
8946 linker will redirect the call to the start of the magic
8949 If the function does not return a floating point value, the
8950 special stub section is named
8953 If the function does return a floating point value, the stub
8955 .mips16.call.fp.FNNAME
8958 secname
= (char *) alloca (strlen (fnname
) + 40);
8959 sprintf (secname
, ".mips16.call.%s%s",
8962 stubname
= (char *) alloca (strlen (fnname
) + 20);
8963 sprintf (stubname
, "__call_stub_%s%s",
8966 stubid
= get_identifier (stubname
);
8967 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8968 build_function_type (void_type_node
, NULL_TREE
));
8969 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8971 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8973 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8977 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8979 fprintf (asm_out_file
, "%s%s",
8980 need_comma
? ", " : "",
8981 (f
& 3) == 1 ? "float" : "double");
8984 fprintf (asm_out_file
, ")\n");
8986 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8987 assemble_start_function (stubdecl
, stubname
);
8989 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8990 fputs ("\t.ent\t", asm_out_file
);
8991 assemble_name (asm_out_file
, stubname
);
8992 fputs ("\n", asm_out_file
);
8994 assemble_name (asm_out_file
, stubname
);
8995 fputs (":\n", asm_out_file
);
8998 /* We build the stub code by hand. That's the only way we can
8999 do it, since we can't generate 32 bit code during a 16 bit
9002 /* We don't want the assembler to insert any nops here. */
9003 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
9005 mips16_fp_args (asm_out_file
, fp_code
, 0);
9009 fprintf (asm_out_file
, "\t.set\tnoat\n");
9010 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
9012 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
9013 fprintf (asm_out_file
, "\t.set\tat\n");
9014 /* Unfortunately, we can't fill the jump delay slot. We
9015 can't fill with one of the mtc1 instructions, because the
9016 result is not available for one instruction, so if the
9017 very first instruction in the function refers to the
9018 register, it will see the wrong value. */
9019 fprintf (asm_out_file
, "\tnop\n");
9023 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
9024 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
9025 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
9026 /* As above, we can't fill the delay slot. */
9027 fprintf (asm_out_file
, "\tnop\n");
9028 if (GET_MODE (retval
) == SFmode
)
9029 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9030 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
9033 if (TARGET_BIG_ENDIAN
)
9035 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9036 reg_names
[GP_REG_FIRST
+ 2],
9037 reg_names
[FP_REG_FIRST
+ 1]);
9038 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9039 reg_names
[GP_REG_FIRST
+ 3],
9040 reg_names
[FP_REG_FIRST
+ 0]);
9044 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9045 reg_names
[GP_REG_FIRST
+ 2],
9046 reg_names
[FP_REG_FIRST
+ 0]);
9047 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9048 reg_names
[GP_REG_FIRST
+ 3],
9049 reg_names
[FP_REG_FIRST
+ 1]);
9052 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
9053 /* As above, we can't fill the delay slot. */
9054 fprintf (asm_out_file
, "\tnop\n");
9057 fprintf (asm_out_file
, "\t.set\treorder\n");
9059 #ifdef ASM_DECLARE_FUNCTION_SIZE
9060 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
9063 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9064 fputs ("\t.end\t", asm_out_file
);
9065 assemble_name (asm_out_file
, stubname
);
9066 fputs ("\n", asm_out_file
);
9069 fprintf (asm_out_file
, "\t.set\tmips16\n");
9071 /* Record this stub. */
9072 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
9073 l
->name
= xstrdup (fnname
);
9075 l
->next
= mips16_stubs
;
9079 /* If we expect a floating point return value, but we've built a
9080 stub which does not expect one, then we're in trouble. We can't
9081 use the existing stub, because it won't handle the floating point
9082 value. We can't build a new stub, because the linker won't know
9083 which stub to use for the various calls in this object file.
9084 Fortunately, this case is illegal, since it means that a function
9085 was declared in two different ways in a single compilation. */
9086 if (fpret
&& ! l
->fpret
)
9087 error ("can not handle inconsistent calls to `%s'", fnname
);
9089 /* If we are calling a stub which handles a floating point return
9090 value, we need to arrange to save $18 in the prologue. We do
9091 this by marking the function call as using the register. The
9092 prologue will later see that it is used, and emit code to save
9099 if (retval
== NULL_RTX
)
9100 insn
= gen_call_internal0 (fnmem
, arg_size
,
9101 gen_rtx (REG
, SImode
,
9102 GP_REG_FIRST
+ 31));
9104 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
9105 gen_rtx (REG
, SImode
,
9106 GP_REG_FIRST
+ 31));
9107 insn
= emit_call_insn (insn
);
9109 if (GET_CODE (insn
) != CALL_INSN
)
9112 CALL_INSN_FUNCTION_USAGE (insn
) =
9113 gen_rtx (EXPR_LIST
, VOIDmode
,
9114 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9115 CALL_INSN_FUNCTION_USAGE (insn
));
9117 /* Return 1 to tell the caller that we've generated the call
9122 /* Return 0 to let the caller generate the call insn. */
9126 /* This function looks through the code for a function, and tries to
9127 optimize the usage of the $gp register. We arrange to copy $gp
9128 into a pseudo-register, and then let gcc's normal reload handling
9129 deal with the pseudo-register. Unfortunately, if reload choose to
9130 put the pseudo-register into a call-clobbered register, it will
9131 emit saves and restores for that register around any function
9132 calls. We don't need the saves, and it's faster to copy $gp than
9133 to do an actual restore. ??? This still means that we waste a
9136 This is an optimization, and the code which gcc has actually
9137 generated is correct, so we do not need to catch all cases. */
9140 mips16_optimize_gp (first
)
9143 rtx gpcopy
, slot
, insn
;
9145 /* Look through the instructions. Set GPCOPY to the register which
9146 holds a copy of $gp. Set SLOT to the stack slot where it is
9147 saved. If we find an instruction which sets GPCOPY to anything
9148 other than $gp or SLOT, then we can't use it. If we find an
9149 instruction which sets SLOT to anything other than GPCOPY, we
9154 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9158 if (! INSN_P (insn
))
9161 set
= PATTERN (insn
);
9163 /* We know that all references to memory will be inside a SET,
9164 because there is no other way to access memory on the mips16.
9165 We don't have to worry about a PARALLEL here, because the
9166 mips.md file will never generate them for memory references. */
9167 if (GET_CODE (set
) != SET
)
9170 if (gpcopy
== NULL_RTX
9171 && GET_CODE (SET_SRC (set
)) == CONST
9172 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
9173 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
9174 && GET_CODE (SET_DEST (set
)) == REG
9175 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9176 gpcopy
= SET_DEST (set
);
9177 else if (slot
== NULL_RTX
9178 && gpcopy
!= NULL_RTX
9179 && GET_CODE (SET_DEST (set
)) == MEM
9180 && GET_CODE (SET_SRC (set
)) == REG
9181 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
9182 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9186 offset
= const0_rtx
;
9187 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9188 if (GET_CODE (base
) == REG
9189 && (REGNO (base
) == STACK_POINTER_REGNUM
9190 || REGNO (base
) == FRAME_POINTER_REGNUM
))
9191 slot
= SET_DEST (set
);
9193 else if (gpcopy
!= NULL_RTX
9194 && (GET_CODE (SET_DEST (set
)) == REG
9195 || GET_CODE (SET_DEST (set
)) == SUBREG
)
9196 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
9197 && (GET_CODE (SET_DEST (set
)) != REG
9198 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
9199 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
9200 || ((GET_CODE (SET_SRC (set
)) != CONST
9201 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
9202 || (REGNO (XEXP (SET_SRC (set
), 0))
9203 != GP_REG_FIRST
+ 28))
9204 && ! rtx_equal_p (SET_SRC (set
), slot
))))
9206 else if (slot
!= NULL_RTX
9207 && GET_CODE (SET_DEST (set
)) == MEM
9208 && rtx_equal_p (SET_DEST (set
), slot
)
9209 && (GET_CODE (SET_SRC (set
)) != REG
9210 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
9214 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9215 different optimization. Any time we find a copy of $28 into a
9216 register, followed by an add of a symbol_ref to that register, we
9217 convert it to load the value from the constant table instead.
9218 The copy and add will take six bytes, just as the load and
9219 constant table entry will take six bytes. However, it is
9220 possible that the constant table entry will be shared.
9222 This could be a peephole optimization, but I don't know if the
9223 peephole code can call force_const_mem.
9225 Using the same register for the copy of $28 and the add of the
9226 symbol_ref is actually pretty likely, since the add instruction
9227 requires the destination and the first addend to be the same
9230 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
9234 /* This optimization is only reasonable if the constant table
9235 entries are only 4 bytes. */
9236 if (Pmode
!= SImode
)
9239 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
9246 next
= NEXT_INSN (next
);
9248 while (next
!= NULL_RTX
9249 && (GET_CODE (next
) == NOTE
9250 || (GET_CODE (next
) == INSN
9251 && (GET_CODE (PATTERN (next
)) == USE
9252 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
9254 if (next
== NULL_RTX
)
9257 if (! INSN_P (insn
))
9260 if (! INSN_P (next
))
9263 set1
= PATTERN (insn
);
9264 if (GET_CODE (set1
) != SET
)
9266 set2
= PATTERN (next
);
9267 if (GET_CODE (set2
) != SET
)
9270 if (GET_CODE (SET_DEST (set1
)) == REG
9271 && GET_CODE (SET_SRC (set1
)) == CONST
9272 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
9273 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
9274 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
9275 && GET_CODE (SET_SRC (set2
)) == PLUS
9276 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
9277 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
9278 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
9282 /* We've found a case we can change to load from the
9285 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
9286 if (GET_CODE (sym
) != SYMBOL_REF
)
9288 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
9289 force_const_mem (Pmode
, sym
)),
9292 PUT_CODE (insn
, NOTE
);
9293 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9294 NOTE_SOURCE_FILE (insn
) = 0;
9296 PUT_CODE (next
, NOTE
);
9297 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
9298 NOTE_SOURCE_FILE (next
) = 0;
9305 /* We can safely remove all assignments to SLOT from GPCOPY, and
9306 replace all assignments from SLOT to GPCOPY with assignments from
9309 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9313 if (! INSN_P (insn
))
9316 set
= PATTERN (insn
);
9317 if (GET_CODE (set
) != SET
9318 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
)
9321 if (GET_CODE (SET_DEST (set
)) == MEM
9322 && rtx_equal_p (SET_DEST (set
), slot
)
9323 && GET_CODE (SET_SRC (set
)) == REG
9324 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
9326 PUT_CODE (insn
, NOTE
);
9327 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9328 NOTE_SOURCE_FILE (insn
) = 0;
9330 else if (GET_CODE (SET_DEST (set
)) == REG
9331 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
9332 && GET_CODE (SET_SRC (set
)) == MEM
9333 && rtx_equal_p (SET_SRC (set
), slot
))
9335 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
9336 gen_rtx (CONST
, Pmode
,
9337 gen_rtx (REG
, Pmode
,
9338 GP_REG_FIRST
+ 28))),
9340 PUT_CODE (insn
, NOTE
);
9341 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9342 NOTE_SOURCE_FILE (insn
) = 0;
9347 /* We keep a list of constants we which we have to add to internal
9348 constant tables in the middle of large functions. */
9352 struct constant
*next
;
9355 enum machine_mode mode
;
9358 /* Add a constant to the list in *PCONSTANTS. */
9361 add_constant (pconstants
, val
, mode
)
9362 struct constant
**pconstants
;
9364 enum machine_mode mode
;
9368 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
9369 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
9372 c
= (struct constant
*) xmalloc (sizeof *c
);
9375 c
->label
= gen_label_rtx ();
9376 c
->next
= *pconstants
;
9381 /* Dump out the constants in CONSTANTS after INSN. */
9384 dump_constants (constants
, insn
)
9385 struct constant
*constants
;
9396 struct constant
*next
;
9398 switch (GET_MODE_SIZE (c
->mode
))
9405 insn
= emit_insn_after (gen_align_2 (), insn
);
9410 insn
= emit_insn_after (gen_align_4 (), insn
);
9415 insn
= emit_insn_after (gen_align_8 (), insn
);
9420 insn
= emit_label_after (c
->label
, insn
);
9425 r
= gen_consttable_qi (c
->value
);
9428 r
= gen_consttable_hi (c
->value
);
9431 r
= gen_consttable_si (c
->value
);
9434 r
= gen_consttable_sf (c
->value
);
9437 r
= gen_consttable_di (c
->value
);
9440 r
= gen_consttable_df (c
->value
);
9446 insn
= emit_insn_after (r
, insn
);
9453 emit_barrier_after (insn
);
9456 /* Find the symbol in an address expression. */
9459 mips_find_symbol (addr
)
9462 if (GET_CODE (addr
) == MEM
)
9463 addr
= XEXP (addr
, 0);
9464 while (GET_CODE (addr
) == CONST
)
9465 addr
= XEXP (addr
, 0);
9466 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
9468 if (GET_CODE (addr
) == PLUS
)
9472 l1
= mips_find_symbol (XEXP (addr
, 0));
9473 l2
= mips_find_symbol (XEXP (addr
, 1));
9474 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
9476 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
9482 /* Exported to toplev.c.
9484 Do a final pass over the function, just before delayed branch
9488 machine_dependent_reorg (first
)
9491 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
9493 struct constant
*constants
;
9495 if (! TARGET_MIPS16
)
9498 /* If $gp is used, try to remove stores, and replace loads with
9501 mips16_optimize_gp (first
);
9503 /* Scan the function looking for PC relative loads which may be out
9504 of range. All such loads will either be from the constant table,
9505 or be getting the address of a constant string. If the size of
9506 the function plus the size of the constant table is less than
9507 0x8000, then all loads are in range. */
9510 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9512 insns_len
+= get_attr_length (insn
);
9514 /* ??? We put switch tables in .text, but we don't define
9515 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9516 compute their lengths correctly. */
9517 if (GET_CODE (insn
) == JUMP_INSN
)
9521 body
= PATTERN (insn
);
9522 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9523 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9524 * GET_MODE_SIZE (GET_MODE (body
)));
9525 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9529 /* Store the original value of insns_len in current_frame_info, so
9530 that simple_memory_operand can look at it. */
9531 current_frame_info
.insns_len
= insns_len
;
9533 pool_size
= get_pool_size ();
9534 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
9537 /* Loop over the insns and figure out what the maximum internal pool
9539 max_internal_pool_size
= 0;
9540 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9542 if (GET_CODE (insn
) == INSN
9543 && GET_CODE (PATTERN (insn
)) == SET
)
9547 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9548 if (src
== NULL_RTX
)
9550 if (CONSTANT_POOL_ADDRESS_P (src
))
9551 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
9552 else if (SYMBOL_REF_FLAG (src
))
9553 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
9559 first_constant_ref
= -1;
9561 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9563 if (GET_CODE (insn
) == INSN
9564 && GET_CODE (PATTERN (insn
)) == SET
)
9567 enum machine_mode mode
= VOIDmode
;
9570 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9571 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
9573 /* ??? This is very conservative, which means that we
9574 will generate too many copies of the constant table.
9575 The only solution would seem to be some form of
9577 if (((insns_len
- addr
)
9578 + max_internal_pool_size
9579 + get_pool_offset (src
))
9582 val
= get_pool_constant (src
);
9583 mode
= get_pool_mode (src
);
9585 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
9587 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
9589 /* Including all of mips_string_length is conservative,
9590 and so is including all of max_internal_pool_size. */
9591 if (((insns_len
- addr
)
9592 + max_internal_pool_size
9594 + mips_string_length
)
9600 max_internal_pool_size
-= Pmode
;
9603 if (val
!= NULL_RTX
)
9607 /* This PC relative load is out of range. ??? In the
9608 case of a string constant, we are only guessing that
9609 it is range, since we don't know the offset of a
9610 particular string constant. */
9612 lab
= add_constant (&constants
, val
, mode
);
9613 newsrc
= gen_rtx (MEM
, mode
,
9614 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
9615 RTX_UNCHANGING_P (newsrc
) = 1;
9616 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
9617 SET_DEST (PATTERN (insn
)),
9619 INSN_CODE (insn
) = -1;
9621 if (first_constant_ref
< 0)
9622 first_constant_ref
= addr
;
9626 addr
+= get_attr_length (insn
);
9628 /* ??? We put switch tables in .text, but we don't define
9629 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9630 compute their lengths correctly. */
9631 if (GET_CODE (insn
) == JUMP_INSN
)
9635 body
= PATTERN (insn
);
9636 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9637 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9638 * GET_MODE_SIZE (GET_MODE (body
)));
9639 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9642 if (GET_CODE (insn
) == BARRIER
)
9644 /* Output any constants we have accumulated. Note that we
9645 don't need to change ADDR, since its only use is
9646 subtraction from INSNS_LEN, and both would be changed by
9648 ??? If the instructions up to the next barrier reuse a
9649 constant, it would often be better to continue
9651 if (constants
!= NULL
)
9652 dump_constants (constants
, insn
);
9654 first_constant_ref
= -1;
9657 if (constants
!= NULL
9658 && (NEXT_INSN (insn
) == NULL
9659 || (first_constant_ref
>= 0
9660 && (((addr
- first_constant_ref
)
9661 + 2 /* for alignment */
9662 + 2 /* for a short jump insn */
9666 /* If we haven't had a barrier within 0x8000 bytes of a
9667 constant reference or we are at the end of the function,
9668 emit a barrier now. */
9670 rtx label
, jump
, barrier
;
9672 label
= gen_label_rtx ();
9673 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
9674 JUMP_LABEL (jump
) = label
;
9675 LABEL_NUSES (label
) = 1;
9676 barrier
= emit_barrier_after (jump
);
9677 emit_label_after (label
, barrier
);
9678 first_constant_ref
= -1;
9682 /* ??? If we output all references to a constant in internal
9683 constants table, we don't need to output the constant in the real
9684 constant table, but we have no way to prevent that. */
9687 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9689 extend_operator (x
, mode
)
9691 enum machine_mode mode ATTRIBUTE_UNUSED
;
9693 enum rtx_code code
= GET_CODE (x
);
9694 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
9697 /* Accept any operator that can be used to shift the high half of the
9698 input value to the lower half, suitable for truncation. The
9699 remainder (the lower half of the input, and the upper half of the
9700 output) will be discarded. */
9702 highpart_shift_operator (x
, mode
)
9704 enum machine_mode mode ATTRIBUTE_UNUSED
;
9706 enum rtx_code code
= GET_CODE (x
);
9707 return (code
== LSHIFTRT
9713 /* Return a number assessing the cost of moving a register in class
9714 FROM to class TO. The classes are expressed using the enumeration
9715 values such as `GENERAL_REGS'. A value of 2 is the default; other
9716 values are interpreted relative to that.
9718 It is not required that the cost always equal 2 when FROM is the
9719 same as TO; on some machines it is expensive to move between
9720 registers if they are not general registers.
9722 If reload sees an insn consisting of a single `set' between two
9723 hard registers, and if `REGISTER_MOVE_COST' applied to their
9724 classes returns a value of 2, reload does not check to ensure that
9725 the constraints of the insn are met. Setting a cost of other than
9726 2 will allow reload to verify that the constraints are met. You
9727 should do this if the `movM' pattern's constraints do not allow
9730 ??? We make make the cost of moving from HI/LO/HILO/MD into general
9731 registers the same as for one of moving general registers to
9732 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
9733 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
9734 isn't clear if it is wise. And it might not work in all cases. We
9735 could solve the DImode LO reg problem by using a multiply, just
9736 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9737 problem by using divide instructions. divu puts the remainder in
9738 the HI reg, so doing a divide by -1 will move the value in the HI
9739 reg for all values except -1. We could handle that case by using a
9740 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9741 a compare/branch to test the input value to see which instruction
9742 we need to use. This gets pretty messy, but it is feasible. */
9745 mips_register_move_cost (mode
, to
, from
)
9746 enum machine_mode mode
;
9747 enum reg_class to
, from
;
9749 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
9751 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
9753 else if (GR_REG_CLASS_P (from
))
9757 else if (to
== M16_NA_REGS
)
9759 else if (GR_REG_CLASS_P (to
))
9766 else if (to
== FP_REGS
)
9768 else if (to
== HI_REG
|| to
== LO_REG
|| to
== MD_REGS
9776 else if (COP_REG_CLASS_P (to
))
9780 } /* GR_REG_CLASS_P (from) */
9781 else if (from
== FP_REGS
)
9783 if (GR_REG_CLASS_P (to
))
9785 else if (to
== FP_REGS
)
9787 else if (to
== ST_REGS
)
9789 } /* from == FP_REGS */
9790 else if (from
== HI_REG
|| from
== LO_REG
|| from
== MD_REGS
9791 || from
== HILO_REG
)
9793 if (GR_REG_CLASS_P (to
))
9800 } /* from == HI_REG, etc. */
9801 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
9803 else if (COP_REG_CLASS_P (from
))
9806 } /* COP_REG_CLASS_P (from) */
9813 /* Return the length of INSN. LENGTH is the initial length computed by
9814 attributes in the machine-description file. */
9817 mips_adjust_insn_length (insn
, length
)
9821 /* A unconditional jump has an unfilled delay slot if it is not part
9822 of a sequence. A conditional jump normally has a delay slot, but
9823 does not on MIPS16. */
9824 if (simplejump_p (insn
)
9825 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
9826 || GET_CODE (insn
) == CALL_INSN
)))
9829 /* All MIPS16 instructions are a measly two bytes. */
9836 /* Output assembly instructions to peform a conditional branch.
9838 INSN is the branch instruction. OPERANDS[0] is the condition.
9839 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9840 of the first operand to the condition. If TWO_OPERANDS_P is
9841 non-zero the comparison takes two operands; OPERANDS[3] will be the
9844 If INVERTED_P is non-zero we are to branch if the condition does
9845 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9847 LENGTH is the length (in bytes) of the sequence we are to generate.
9848 That tells us whether to generate a simple conditional branch, or a
9849 reversed conditional branch around a `jr' instruction. */
9851 mips_output_conditional_branch (insn
,
9864 static char buffer
[200];
9865 /* The kind of comparison we are doing. */
9866 enum rtx_code code
= GET_CODE (operands
[0]);
9867 /* Non-zero if the opcode for the comparison needs a `z' indicating
9868 that it is a comparision against zero. */
9870 /* A string to use in the assembly output to represent the first
9872 const char *op1
= "%z2";
9873 /* A string to use in the assembly output to represent the second
9874 operand. Use the hard-wired zero register if there's no second
9876 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
9877 /* The operand-printing string for the comparison. */
9878 const char *const comp
= (float_p
? "%F0" : "%C0");
9879 /* The operand-printing string for the inverted comparison. */
9880 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
9882 /* The MIPS processors (for levels of the ISA at least two), have
9883 "likely" variants of each branch instruction. These instructions
9884 annul the instruction in the delay slot if the branch is not
9886 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9888 if (!two_operands_p
)
9890 /* To compute whether than A > B, for example, we normally
9891 subtract B from A and then look at the sign bit. But, if we
9892 are doing an unsigned comparison, and B is zero, we don't
9893 have to do the subtraction. Instead, we can just check to
9894 see if A is non-zero. Thus, we change the CODE here to
9895 reflect the simpler comparison operation. */
9907 /* A condition which will always be true. */
9913 /* A condition which will always be false. */
9919 /* Not a special case. */
9924 /* Relative comparisons are always done against zero. But
9925 equality comparisons are done between two operands, and therefore
9926 do not require a `z' in the assembly language output. */
9927 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
9928 /* For comparisons against zero, the zero is not provided
9933 /* Begin by terminating the buffer. That way we can always use
9934 strcat to add to it. */
9941 /* Just a simple conditional branch. */
9943 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
9944 inverted_p
? inverted_comp
: comp
);
9946 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
9947 inverted_p
? inverted_comp
: comp
,
9948 need_z_p
? "z" : "",
9956 /* Generate a reversed conditional branch around ` j'
9971 rtx target
= gen_label_rtx ();
9973 output_asm_insn ("%(%<", 0);
9974 orig_target
= operands
[1];
9975 operands
[1] = target
;
9976 /* Generate the reversed comparison. This takes four
9979 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
9980 inverted_p
? comp
: inverted_comp
);
9982 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
9983 inverted_p
? comp
: inverted_comp
,
9984 need_z_p
? "z" : "",
9987 output_asm_insn (buffer
, operands
);
9988 operands
[1] = orig_target
;
9990 output_asm_insn ("nop\n\tj\t%1", operands
);
9993 output_asm_insn ("nop", 0);
9996 /* Output delay slot instruction. */
9997 rtx insn
= final_sequence
;
9998 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
10000 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
10002 output_asm_insn ("%>%)", 0);
10003 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
10004 CODE_LABEL_NUMBER (target
));
10008 /* We do not currently use this code. It handles jumps to
10009 arbitrary locations, using `jr', even across a 256MB boundary.
10010 We could add a -mhuge switch, and then use this code instead of
10011 the `j' alternative above when -mhuge was used. */
10016 /* Generate a reversed conditional branch around a `jr'
10030 Not pretty, but allows a conditional branch anywhere in the
10031 32-bit address space. If the original branch is annulled,
10032 then the instruction in the delay slot should be executed
10033 only if the branch is taken. The la instruction is really
10034 a macro which will usually take eight bytes, but sometimes
10035 takes only four, if the instruction to which we're jumping
10036 gets its own entry in the global pointer table, which will
10037 happen if its a case label. The assembler will then
10038 generate only a four-byte sequence, rather than eight, and
10039 there seems to be no way to tell it not to. Thus, we can't
10040 just use a `.+x' addressing form; we don't know what value
10043 So, we resort to using the explicit relocation syntax
10044 available in the assembler and do:
10046 lw $at,%got_page(target)($gp)
10047 daddiu $at,$at,%got_ofst(target)
10049 That way, this always takes up eight bytes, and we can use
10050 the `.+x' form. Of course, these explicit machinations
10051 with relocation will not work with old assemblers. Then
10052 again, neither do out-of-range branches, so we haven't lost
10055 /* The target of the reversed branch. */
10056 const char *const target
10057 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
10058 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
10059 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
10062 strcpy (buffer
, "%(%<%[");
10063 c
= strchr (buffer
, '\0');
10064 /* Generate the reversed comparision. This takes four
10067 sprintf (c
, "%%*b%s\t%%Z2%s",
10068 inverted_p
? comp
: inverted_comp
,
10071 sprintf (c
, "%%*b%s%s\t%s%s,%s",
10072 inverted_p
? comp
: inverted_comp
,
10073 need_z_p
? "z" : "",
10077 c
= strchr (buffer
, '\0');
10078 /* Generate the load-address, and jump. This takes twelve
10079 bytes, for a total of 16. */
10081 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10088 /* The delay slot was unfilled. Since we're inside
10089 .noreorder, the assembler will not fill in the NOP for
10090 us, so we must do it ourselves. */
10091 strcat (buffer
, "\n\tnop");
10092 strcat (buffer
, "%]%>%)");
10105 /* Called to register all of our global variables with the garbage
10109 mips_add_gc_roots ()
10111 ggc_add_rtx_root (&mips_load_reg
, 1);
10112 ggc_add_rtx_root (&mips_load_reg2
, 1);
10113 ggc_add_rtx_root (&mips_load_reg3
, 1);
10114 ggc_add_rtx_root (&mips_load_reg4
, 1);
10115 ggc_add_rtx_root (branch_cmp
, ARRAY_SIZE (branch_cmp
));
10118 static enum processor_type
10119 mips_parse_cpu (cpu_string
)
10120 const char *cpu_string
;
10122 const char *p
= cpu_string
;
10124 enum processor_type cpu
;
10125 int warn_upper_case
= 0;
10127 /* We need to cope with the various "vr" prefixes for the NEC 4300
10128 and 4100 processors. */
10129 if (*p
== 'v' || *p
== 'V')
10132 warn_upper_case
= 1;
10136 if (*p
== 'r' || *p
== 'R')
10139 warn_upper_case
= 1;
10143 if (warn_upper_case
)
10144 warning ("the cpu name must be lower case");
10146 /* Since there is no difference between a R2000 and R3000 in
10147 terms of the scheduler, we collapse them into just an R3000. */
10149 cpu
= PROCESSOR_DEFAULT
;
10153 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
10154 cpu
= PROCESSOR_R3000
;
10155 else if (!strcmp (p
, "20kc") || !strcmp (p
, "20Kc") )
10156 cpu
= PROCESSOR_R20KC
;
10160 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
10161 cpu
= PROCESSOR_R3000
;
10162 else if (!strcmp (p
, "3900"))
10163 cpu
= PROCESSOR_R3900
;
10167 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
10168 cpu
= PROCESSOR_R4000
;
10169 /* The vr4100 is a non-FP ISA III processor with some extra
10171 else if (!strcmp (p
, "4100"))
10172 cpu
= PROCESSOR_R4100
;
10173 /* The vr4300 is a standard ISA III processor, but with a different
10175 else if (!strcmp (p
, "4300"))
10176 cpu
= PROCESSOR_R4300
;
10177 /* The r4400 is exactly the same as the r4000 from the compiler's
10179 else if (!strcmp (p
, "4400"))
10180 cpu
= PROCESSOR_R4000
;
10181 else if (!strcmp (p
, "4600"))
10182 cpu
= PROCESSOR_R4600
;
10183 else if (!strcmp (p
, "4650"))
10184 cpu
= PROCESSOR_R4650
;
10185 /* The 4kc and 4kp processor cores are the same for
10186 scheduling purposes; they both implement the MIPS32
10187 ISA and only differ in their memory management
10189 else if (!strcmp (p
, "4kc") || !strcmp (p
, "4Kc")
10190 || !strcmp (p
, "4kp") || !strcmp (p
, "4Kp") )
10191 cpu
= PROCESSOR_R4KC
;
10195 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
10196 cpu
= PROCESSOR_R5000
;
10197 else if (!strcmp (p
, "5kc") || !strcmp (p
, "5Kc") )
10198 cpu
= PROCESSOR_R5KC
;
10202 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
10203 cpu
= PROCESSOR_R6000
;
10207 if (!strcmp (p
, "8000"))
10208 cpu
= PROCESSOR_R8000
;
10212 if (!strcmp (p
, "orion"))
10213 cpu
= PROCESSOR_R4600
;
10218 && cpu
!= PROCESSOR_R4300
10219 && cpu
!= PROCESSOR_R4100
10220 && cpu
!= PROCESSOR_R5000
)
10221 cpu
= PROCESSOR_DEFAULT
;
10226 /* Adjust the cost of INSN based on the relationship between INSN that
10227 is dependent on DEP_INSN through the dependence LINK. The default
10228 is to make no adjustment to COST.
10230 On the MIPS, ignore the cost of anti- and output-dependencies. */
10232 mips_adjust_cost (insn
, link
, dep
, cost
)
10233 rtx insn ATTRIBUTE_UNUSED
;
10235 rtx dep ATTRIBUTE_UNUSED
;
10238 if (REG_NOTE_KIND (link
) != 0)
10239 return 0; /* Anti or output dependence. */
10243 /* Cover function for UNIQUE_SECTION. */
10246 mips_unique_section (decl
, reloc
)
10250 int len
, size
, sec
;
10251 const char *name
, *prefix
;
10253 static const char *const prefixes
[4][2] = {
10254 { ".text.", ".gnu.linkonce.t." },
10255 { ".rodata.", ".gnu.linkonce.r." },
10256 { ".data.", ".gnu.linkonce.d." },
10257 { ".sdata.", ".gnu.linkonce.s." }
10260 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10261 size
= int_size_in_bytes (TREE_TYPE (decl
));
10262 STRIP_NAME_ENCODING (name
, name
);
10264 /* Determine the base section we are interested in:
10265 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10266 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10268 else if (DECL_INITIAL (decl
) == 0
10269 || DECL_INITIAL (decl
) == error_mark_node
)
10271 else if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
10272 && TREE_CODE (decl
) == STRING_CST
10273 && !flag_writable_strings
)
10275 /* For embedded position independent code, put constant
10276 strings in the text section, because the data section
10277 is limited to 64K in size. For mips16 code, put
10278 strings in the text section so that a PC relative load
10279 instruction can be used to get their address. */
10282 else if (TARGET_EMBEDDED_DATA
)
10284 /* For embedded applications, always put an object in
10285 read-only data if possible, in order to reduce RAM
10288 if (DECL_READONLY_SECTION (decl
, reloc
))
10290 else if (size
> 0 && size
<= mips_section_threshold
)
10297 /* For hosted applications, always put an object in
10298 small data if possible, as this gives the best
10301 if (size
> 0 && size
<= mips_section_threshold
)
10303 else if (DECL_READONLY_SECTION (decl
, reloc
))
10309 prefix
= prefixes
[sec
][DECL_ONE_ONLY (decl
)];
10310 len
= strlen (name
) + strlen (prefix
);
10311 string
= alloca (len
+ 1);
10312 sprintf (string
, "%s%s", prefix
, name
);
10314 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
10318 mips_hard_regno_nregs (regno
, mode
)
10320 enum machine_mode mode
;
10322 if (! FP_REG_P (regno
))
10323 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
10325 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
10329 mips_return_in_memory (type
)
10332 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10333 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10334 structures are returned in a register. Objects with varying size
10335 must still be returned in memory, of course. */
10337 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
10338 return (TYPE_MODE (type
) == BLKmode
);
10340 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
10341 || (int_size_in_bytes (type
) == -1));
10351 case PROCESSOR_R3000
:
10364 #ifdef TARGET_IRIX6
10365 /* Output assembly to switch to section NAME with attribute FLAGS. */
10368 iris6_asm_named_section_1 (name
, flags
, align
)
10370 unsigned int flags
;
10371 unsigned int align
;
10373 unsigned int sh_type
, sh_flags
, sh_entsize
;
10376 if (!(flags
& SECTION_DEBUG
))
10377 sh_flags
|= 2; /* SHF_ALLOC */
10378 if (flags
& SECTION_WRITE
)
10379 sh_flags
|= 1; /* SHF_WRITE */
10380 if (flags
& SECTION_CODE
)
10381 sh_flags
|= 4; /* SHF_EXECINSTR */
10382 if (flags
& SECTION_SMALL
)
10383 sh_flags
|= 0x10000000; /* SHF_MIPS_GPREL */
10384 if (strcmp (name
, ".debug_frame") == 0)
10385 sh_flags
|= 0x08000000; /* SHF_MIPS_NOSTRIP */
10386 if (flags
& SECTION_DEBUG
)
10387 sh_type
= 0x7000001e; /* SHT_MIPS_DWARF */
10388 else if (flags
& SECTION_BSS
)
10389 sh_type
= 8; /* SHT_NOBITS */
10391 sh_type
= 1; /* SHT_PROGBITS */
10393 if (flags
& SECTION_CODE
)
10398 fprintf (asm_out_file
, "\t.section %s,%#x,%#x,%u,%u\n",
10399 name
, sh_type
, sh_flags
, sh_entsize
, align
);
10403 iris6_asm_named_section (name
, flags
)
10405 unsigned int flags
;
10407 if (TARGET_FILE_SWITCHING
&& (flags
& SECTION_CODE
))
10408 asm_out_file
= asm_out_text_file
;
10409 iris6_asm_named_section_1 (name
, flags
, 0);
10412 /* In addition to emitting a .align directive, record the maximum
10413 alignment requested for the current section. */
10415 struct iris_section_align_entry
10419 unsigned int flags
;
10422 static htab_t iris_section_align_htab
;
10423 static FILE *iris_orig_asm_out_file
;
10426 iris_section_align_entry_eq (p1
, p2
)
10430 const struct iris_section_align_entry
*old
= p1
;
10431 const char *new = p2
;
10433 return strcmp (old
->name
, new) == 0;
10437 iris_section_align_entry_hash (p
)
10440 const struct iris_section_align_entry
*old
= p
;
10441 return htab_hash_string (old
->name
);
10445 iris6_asm_output_align (file
, log
)
10449 const char *section
= current_section_name ();
10450 struct iris_section_align_entry
**slot
, *entry
;
10455 slot
= (struct iris_section_align_entry
**)
10456 htab_find_slot_with_hash (iris_section_align_htab
, section
,
10457 htab_hash_string (section
), INSERT
);
10461 entry
= (struct iris_section_align_entry
*)
10462 xmalloc (sizeof (struct iris_section_align_entry
));
10464 entry
->name
= section
;
10466 entry
->flags
= current_section_flags ();
10468 else if (entry
->log
< log
)
10471 fprintf (file
, "\t.align\t%u\n", log
);
10474 /* The Iris assembler does not record alignment from .align directives,
10475 but takes it from the first .section directive seen. Play yet more
10476 file switching games so that we can emit a .section directive at the
10477 beginning of the file with the proper alignment attached. */
10480 iris6_asm_file_start (stream
)
10483 mips_asm_file_start (stream
);
10485 iris_orig_asm_out_file
= asm_out_file
;
10486 stream
= tmpfile ();
10487 asm_out_file
= stream
;
10488 asm_out_data_file
= stream
;
10489 if (! TARGET_FILE_SWITCHING
)
10490 asm_out_text_file
= stream
;
10492 iris_section_align_htab
= htab_create (31, iris_section_align_entry_hash
,
10493 iris_section_align_entry_eq
, NULL
);
10497 iris6_section_align_1 (slot
, data
)
10499 void *data ATTRIBUTE_UNUSED
;
10501 const struct iris_section_align_entry
*entry
10502 = *(const struct iris_section_align_entry
**) slot
;
10504 iris6_asm_named_section_1 (entry
->name
, entry
->flags
, 1 << entry
->log
);
10509 iris6_asm_file_end (stream
)
10512 /* Emit section directives with the proper alignment at the top of the
10513 real output file. */
10514 asm_out_file
= iris_orig_asm_out_file
;
10515 htab_traverse (iris_section_align_htab
, iris6_section_align_1
, NULL
);
10517 /* Copy the data emitted to the temp file to the real output file. */
10518 copy_file_data (asm_out_file
, stream
);
10520 mips_asm_file_end (stream
);
10522 #endif /* TARGET_IRIX6 */