1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94 #include "insn-attr.h"
96 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
104 #include "valtrack.h"
107 #include "statistics.h"
109 #include "rtl-iter.h"
111 /* Number of attempts to combine instructions in this function. */
113 static int combine_attempts
;
115 /* Number of attempts that got as far as substitution in this function. */
117 static int combine_merges
;
119 /* Number of instructions combined with added SETs in this function. */
121 static int combine_extras
;
123 /* Number of instructions combined in this function. */
125 static int combine_successes
;
127 /* Totals over entire compilation. */
129 static int total_attempts
, total_merges
, total_extras
, total_successes
;
131 /* combine_instructions may try to replace the right hand side of the
132 second instruction with the value of an associated REG_EQUAL note
133 before throwing it at try_combine. That is problematic when there
134 is a REG_DEAD note for a register used in the old right hand side
135 and can cause distribute_notes to do wrong things. This is the
136 second instruction if it has been so modified, null otherwise. */
138 static rtx_insn
*i2mod
;
140 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 static rtx i2mod_old_rhs
;
144 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 static rtx i2mod_new_rhs
;
148 typedef struct reg_stat_struct
{
149 /* Record last point of death of (hard or pseudo) register n. */
150 rtx_insn
*last_death
;
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick
;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
218 char last_set_sign_bit_copies
;
219 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid
;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies
;
241 unsigned HOST_WIDE_INT nonzero_bits
;
243 /* Record the value of the label_tick when the last truncation
244 happened. The field truncated_to_mode is only valid if
245 truncation_label == label_tick. */
247 int truncation_label
;
249 /* Record the last truncation seen for this register. If truncation
250 is not a nop to this mode we might be able to save an explicit
251 truncation if we know that value already contains a truncated
254 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
258 static vec
<reg_stat_type
> reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx_insn
*subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx_insn
*added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link
*next
;
320 static struct insn_link
**uid_log_links
;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack
;
332 /* Allocate a link. */
334 static inline struct insn_link
*
335 alloc_insn_link (rtx_insn
*insn
, struct insn_link
*next
)
338 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
339 sizeof (struct insn_link
));
345 /* Incremented for each basic block. */
347 static int label_tick
;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start
;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode
;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid
;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
376 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
377 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
390 rtx_insn
*other_insn
;
393 static struct undobuf undobuf
;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences
;
400 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned HOST_WIDE_INT
,
403 unsigned HOST_WIDE_INT
*);
404 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx
*, rtx
);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx_insn
*);
411 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
412 static int cant_combine_insn_p (rtx_insn
*);
413 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
414 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
415 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
416 static int contains_muldiv (rtx
);
417 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
419 static void undo_all (void);
420 static void undo_commit (void);
421 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
422 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
423 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
424 static rtx
simplify_if_then_else (rtx
);
425 static rtx
simplify_set (rtx
);
426 static rtx
simplify_logical (rtx
);
427 static rtx
expand_compound_operation (rtx
);
428 static const_rtx
expand_field_assignment (const_rtx
);
429 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
430 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
431 static rtx
extract_left_shift (rtx
, int);
432 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
433 unsigned HOST_WIDE_INT
*);
434 static rtx
canon_reg_for_combine (rtx
, rtx
);
435 static rtx
force_to_mode (rtx
, enum machine_mode
,
436 unsigned HOST_WIDE_INT
, int);
437 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
438 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
439 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
440 static rtx
make_field_assignment (rtx
);
441 static rtx
apply_distributive_law (rtx
);
442 static rtx
distribute_and_simplify_rtx (rtx
, int);
443 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
444 unsigned HOST_WIDE_INT
);
445 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
446 unsigned HOST_WIDE_INT
);
447 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
448 HOST_WIDE_INT
, enum machine_mode
, int *);
449 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
450 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
452 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
453 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
454 static enum rtx_code
simplify_compare_const (enum rtx_code
, enum machine_mode
,
456 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
457 static void update_table_tick (rtx
);
458 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
459 static void check_promoted_subreg (rtx_insn
*, rtx
);
460 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
461 static void record_dead_and_set_regs (rtx_insn
*);
462 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
463 static rtx
get_last_value (const_rtx
);
464 static int use_crosses_set_p (const_rtx
, int);
465 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
466 static int reg_dead_at_p (rtx
, rtx_insn
*);
467 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
468 static int reg_bitfield_target_p (rtx
, rtx
);
469 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
470 static void distribute_links (struct insn_link
*);
471 static void mark_used_regs_combine (rtx
);
472 static void record_promoted_value (rtx_insn
*, rtx
);
473 static bool unmentioned_reg_p (rtx
, rtx
);
474 static void record_truncated_values (rtx
*, void *);
475 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
476 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
500 /* Convenience wrapper for the canonicalize_comparison target hook.
501 Target hooks cannot use enum rtx_code. */
503 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
504 bool op0_preserve_value
)
506 int code_int
= (int)*code
;
507 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
508 *code
= (enum rtx_code
)code_int
;
511 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
512 PATTERN can not be split. Otherwise, it returns an insn sequence.
513 This is a wrapper around split_insns which ensures that the
514 reg_stat vector is made larger if the splitter creates a new
518 combine_split_insns (rtx pattern
, rtx insn
)
523 ret
= split_insns (pattern
, insn
);
524 nregs
= max_reg_num ();
525 if (nregs
> reg_stat
.length ())
526 reg_stat
.safe_grow_cleared (nregs
);
530 /* This is used by find_single_use to locate an rtx in LOC that
531 contains exactly one use of DEST, which is typically either a REG
532 or CC0. It returns a pointer to the innermost rtx expression
533 containing DEST. Appearances of DEST that are being used to
534 totally replace it are not counted. */
537 find_single_use_1 (rtx dest
, rtx
*loc
)
540 enum rtx_code code
= GET_CODE (x
);
556 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
557 of a REG that occupies all of the REG, the insn uses DEST if
558 it is mentioned in the destination or the source. Otherwise, we
559 need just check the source. */
560 if (GET_CODE (SET_DEST (x
)) != CC0
561 && GET_CODE (SET_DEST (x
)) != PC
562 && !REG_P (SET_DEST (x
))
563 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
564 && REG_P (SUBREG_REG (SET_DEST (x
)))
565 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
566 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
567 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
568 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
571 return find_single_use_1 (dest
, &SET_SRC (x
));
575 return find_single_use_1 (dest
, &XEXP (x
, 0));
581 /* If it wasn't one of the common cases above, check each expression and
582 vector of this code. Look for a unique usage of DEST. */
584 fmt
= GET_RTX_FORMAT (code
);
585 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
589 if (dest
== XEXP (x
, i
)
590 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
591 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
594 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
597 result
= this_result
;
598 else if (this_result
)
599 /* Duplicate usage. */
602 else if (fmt
[i
] == 'E')
606 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
608 if (XVECEXP (x
, i
, j
) == dest
610 && REG_P (XVECEXP (x
, i
, j
))
611 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
614 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
617 result
= this_result
;
618 else if (this_result
)
628 /* See if DEST, produced in INSN, is used only a single time in the
629 sequel. If so, return a pointer to the innermost rtx expression in which
632 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
634 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
635 care about REG_DEAD notes or LOG_LINKS.
637 Otherwise, we find the single use by finding an insn that has a
638 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
639 only referenced once in that insn, we know that it must be the first
640 and last insn referencing DEST. */
643 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
648 struct insn_link
*link
;
653 next
= NEXT_INSN (insn
);
655 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
658 result
= find_single_use_1 (dest
, &PATTERN (next
));
668 bb
= BLOCK_FOR_INSN (insn
);
669 for (next
= NEXT_INSN (insn
);
670 next
&& BLOCK_FOR_INSN (next
) == bb
;
671 next
= NEXT_INSN (next
))
672 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
674 FOR_EACH_LOG_LINK (link
, next
)
675 if (link
->insn
== insn
)
680 result
= find_single_use_1 (dest
, &PATTERN (next
));
690 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
691 insn. The substitution can be undone by undo_all. If INTO is already
692 set to NEWVAL, do not record this change. Because computing NEWVAL might
693 also call SUBST, we have to compute it before we put anything into
697 do_SUBST (rtx
*into
, rtx newval
)
702 if (oldval
== newval
)
705 /* We'd like to catch as many invalid transformations here as
706 possible. Unfortunately, there are way too many mode changes
707 that are perfectly valid, so we'd waste too much effort for
708 little gain doing the checks here. Focus on catching invalid
709 transformations involving integer constants. */
710 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
711 && CONST_INT_P (newval
))
713 /* Sanity check that we're replacing oldval with a CONST_INT
714 that is a valid sign-extension for the original mode. */
715 gcc_assert (INTVAL (newval
)
716 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
718 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
719 CONST_INT is not valid, because after the replacement, the
720 original mode would be gone. Unfortunately, we can't tell
721 when do_SUBST is called to replace the operand thereof, so we
722 perform this test on oldval instead, checking whether an
723 invalid replacement took place before we got here. */
724 gcc_assert (!(GET_CODE (oldval
) == SUBREG
725 && CONST_INT_P (SUBREG_REG (oldval
))));
726 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
727 && CONST_INT_P (XEXP (oldval
, 0))));
731 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
733 buf
= XNEW (struct undo
);
735 buf
->kind
= UNDO_RTX
;
737 buf
->old_contents
.r
= oldval
;
740 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
743 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
745 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
746 for the value of a HOST_WIDE_INT value (including CONST_INT) is
750 do_SUBST_INT (int *into
, int newval
)
755 if (oldval
== newval
)
759 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
761 buf
= XNEW (struct undo
);
763 buf
->kind
= UNDO_INT
;
765 buf
->old_contents
.i
= oldval
;
768 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
771 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
773 /* Similar to SUBST, but just substitute the mode. This is used when
774 changing the mode of a pseudo-register, so that any other
775 references to the entry in the regno_reg_rtx array will change as
779 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
782 enum machine_mode oldval
= GET_MODE (*into
);
784 if (oldval
== newval
)
788 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
790 buf
= XNEW (struct undo
);
792 buf
->kind
= UNDO_MODE
;
794 buf
->old_contents
.m
= oldval
;
795 adjust_reg_mode (*into
, newval
);
797 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
800 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
803 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
806 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
809 struct insn_link
* oldval
= *into
;
811 if (oldval
== newval
)
815 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
817 buf
= XNEW (struct undo
);
819 buf
->kind
= UNDO_LINKS
;
821 buf
->old_contents
.l
= oldval
;
824 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
827 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
830 /* Subroutine of try_combine. Determine whether the replacement patterns
831 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
832 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
833 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
834 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
835 of all the instructions can be estimated and the replacements are more
836 expensive than the original sequence. */
839 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
840 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
842 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
843 int new_i2_cost
, new_i3_cost
;
844 int old_cost
, new_cost
;
846 /* Lookup the original insn_rtx_costs. */
847 i2_cost
= INSN_COST (i2
);
848 i3_cost
= INSN_COST (i3
);
852 i1_cost
= INSN_COST (i1
);
855 i0_cost
= INSN_COST (i0
);
856 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
857 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
861 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
862 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
868 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
869 i1_cost
= i0_cost
= 0;
872 /* Calculate the replacement insn_rtx_costs. */
873 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
876 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
877 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
878 ? new_i2_cost
+ new_i3_cost
: 0;
882 new_cost
= new_i3_cost
;
886 if (undobuf
.other_insn
)
888 int old_other_cost
, new_other_cost
;
890 old_other_cost
= INSN_COST (undobuf
.other_insn
);
891 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
892 if (old_other_cost
> 0 && new_other_cost
> 0)
894 old_cost
+= old_other_cost
;
895 new_cost
+= new_other_cost
;
901 /* Disallow this combination if both new_cost and old_cost are greater than
902 zero, and new_cost is greater than old cost. */
903 if (old_cost
> 0 && new_cost
> old_cost
)
910 "rejecting combination of insns %d, %d, %d and %d\n",
911 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
913 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
914 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
919 "rejecting combination of insns %d, %d and %d\n",
920 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
921 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
922 i1_cost
, i2_cost
, i3_cost
, old_cost
);
927 "rejecting combination of insns %d and %d\n",
928 INSN_UID (i2
), INSN_UID (i3
));
929 fprintf (dump_file
, "original costs %d + %d = %d\n",
930 i2_cost
, i3_cost
, old_cost
);
935 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
936 new_i2_cost
, new_i3_cost
, new_cost
);
939 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
945 /* Update the uid_insn_cost array with the replacement costs. */
946 INSN_COST (i2
) = new_i2_cost
;
947 INSN_COST (i3
) = new_i3_cost
;
959 /* Delete any insns that copy a register to itself. */
962 delete_noop_moves (void)
964 rtx_insn
*insn
, *next
;
967 FOR_EACH_BB_FN (bb
, cfun
)
969 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
971 next
= NEXT_INSN (insn
);
972 if (INSN_P (insn
) && noop_move_p (insn
))
975 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
977 delete_insn_and_edges (insn
);
984 /* Fill in log links field for all insns. */
987 create_log_links (void)
994 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
996 /* Pass through each block from the end, recording the uses of each
997 register and establishing log links when def is encountered.
998 Note that we do not clear next_use array in order to save time,
999 so we have to test whether the use is in the same basic block as def.
1001 There are a few cases below when we do not consider the definition or
1002 usage -- these are taken from original flow.c did. Don't ask me why it is
1003 done this way; I don't know and if it works, I don't want to know. */
1005 FOR_EACH_BB_FN (bb
, cfun
)
1007 FOR_BB_INSNS_REVERSE (bb
, insn
)
1009 if (!NONDEBUG_INSN_P (insn
))
1012 /* Log links are created only once. */
1013 gcc_assert (!LOG_LINKS (insn
));
1015 FOR_EACH_INSN_DEF (def
, insn
)
1017 int regno
= DF_REF_REGNO (def
);
1020 if (!next_use
[regno
])
1023 /* Do not consider if it is pre/post modification in MEM. */
1024 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1027 /* Do not make the log link for frame pointer. */
1028 if ((regno
== FRAME_POINTER_REGNUM
1029 && (! reload_completed
|| frame_pointer_needed
))
1030 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1031 || (regno
== HARD_FRAME_POINTER_REGNUM
1032 && (! reload_completed
|| frame_pointer_needed
))
1034 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1035 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1040 use_insn
= next_use
[regno
];
1041 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1045 We don't build a LOG_LINK for hard registers contained
1046 in ASM_OPERANDs. If these registers get replaced,
1047 we might wind up changing the semantics of the insn,
1048 even if reload can make what appear to be valid
1049 assignments later. */
1050 if (regno
>= FIRST_PSEUDO_REGISTER
1051 || asm_noperands (PATTERN (use_insn
)) < 0)
1053 /* Don't add duplicate links between instructions. */
1054 struct insn_link
*links
;
1055 FOR_EACH_LOG_LINK (links
, use_insn
)
1056 if (insn
== links
->insn
)
1060 LOG_LINKS (use_insn
)
1061 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1064 next_use
[regno
] = NULL
;
1067 FOR_EACH_INSN_USE (use
, insn
)
1069 int regno
= DF_REF_REGNO (use
);
1071 /* Do not consider the usage of the stack pointer
1072 by function call. */
1073 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1076 next_use
[regno
] = insn
;
1084 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1085 true if we found a LOG_LINK that proves that A feeds B. This only works
1086 if there are no instructions between A and B which could have a link
1087 depending on A, since in that case we would not record a link for B.
1088 We also check the implicit dependency created by a cc0 setter/user
1092 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1094 struct insn_link
*links
;
1095 FOR_EACH_LOG_LINK (links
, b
)
1096 if (links
->insn
== a
)
1105 /* Main entry point for combiner. F is the first insn of the function.
1106 NREGS is the first unused pseudo-reg number.
1108 Return nonzero if the combiner has turned an indirect jump
1109 instruction into a direct jump. */
1111 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1113 rtx_insn
*insn
, *next
;
1117 struct insn_link
*links
, *nextlinks
;
1119 basic_block last_bb
;
1121 int new_direct_jump_p
= 0;
1123 for (first
= f
; first
&& !INSN_P (first
); )
1124 first
= NEXT_INSN (first
);
1128 combine_attempts
= 0;
1131 combine_successes
= 0;
1133 rtl_hooks
= combine_rtl_hooks
;
1135 reg_stat
.safe_grow_cleared (nregs
);
1137 init_recog_no_volatile ();
1139 /* Allocate array for insn info. */
1140 max_uid_known
= get_max_uid ();
1141 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1142 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1143 gcc_obstack_init (&insn_link_obstack
);
1145 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1147 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1148 problems when, for example, we have j <<= 1 in a loop. */
1150 nonzero_sign_valid
= 0;
1151 label_tick
= label_tick_ebb_start
= 1;
1153 /* Scan all SETs and see if we can deduce anything about what
1154 bits are known to be zero for some registers and how many copies
1155 of the sign bit are known to exist for those registers.
1157 Also set any known values so that we can use it while searching
1158 for what bits are known to be set. */
1160 setup_incoming_promotions (first
);
1161 /* Allow the entry block and the first block to fall into the same EBB.
1162 Conceptually the incoming promotions are assigned to the entry block. */
1163 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1165 create_log_links ();
1166 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1168 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1173 if (!single_pred_p (this_basic_block
)
1174 || single_pred (this_basic_block
) != last_bb
)
1175 label_tick_ebb_start
= label_tick
;
1176 last_bb
= this_basic_block
;
1178 FOR_BB_INSNS (this_basic_block
, insn
)
1179 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1185 subst_low_luid
= DF_INSN_LUID (insn
);
1188 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1190 record_dead_and_set_regs (insn
);
1193 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1194 if (REG_NOTE_KIND (links
) == REG_INC
)
1195 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1199 /* Record the current insn_rtx_cost of this instruction. */
1200 if (NONJUMP_INSN_P (insn
))
1201 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1202 optimize_this_for_speed_p
);
1204 fprintf (dump_file
, "insn_cost %d: %d\n",
1205 INSN_UID (insn
), INSN_COST (insn
));
1209 nonzero_sign_valid
= 1;
1211 /* Now scan all the insns in forward order. */
1212 label_tick
= label_tick_ebb_start
= 1;
1214 setup_incoming_promotions (first
);
1215 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1216 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1218 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1220 rtx_insn
*last_combined_insn
= NULL
;
1221 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1226 if (!single_pred_p (this_basic_block
)
1227 || single_pred (this_basic_block
) != last_bb
)
1228 label_tick_ebb_start
= label_tick
;
1229 last_bb
= this_basic_block
;
1231 rtl_profile_for_bb (this_basic_block
);
1232 for (insn
= BB_HEAD (this_basic_block
);
1233 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1234 insn
= next
? next
: NEXT_INSN (insn
))
1237 if (!NONDEBUG_INSN_P (insn
))
1240 while (last_combined_insn
1241 && INSN_DELETED_P (last_combined_insn
))
1242 last_combined_insn
= PREV_INSN (last_combined_insn
);
1243 if (last_combined_insn
== NULL_RTX
1244 || BARRIER_P (last_combined_insn
)
1245 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1246 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1247 last_combined_insn
= insn
;
1249 /* See if we know about function return values before this
1250 insn based upon SUBREG flags. */
1251 check_promoted_subreg (insn
, PATTERN (insn
));
1253 /* See if we can find hardregs and subreg of pseudos in
1254 narrower modes. This could help turning TRUNCATEs
1256 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1258 /* Try this insn with each insn it links back to. */
1260 FOR_EACH_LOG_LINK (links
, insn
)
1261 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1262 NULL
, &new_direct_jump_p
,
1263 last_combined_insn
)) != 0)
1265 statistics_counter_event (cfun
, "two-insn combine", 1);
1269 /* Try each sequence of three linked insns ending with this one. */
1271 if (max_combine
>= 3)
1272 FOR_EACH_LOG_LINK (links
, insn
)
1274 rtx_insn
*link
= links
->insn
;
1276 /* If the linked insn has been replaced by a note, then there
1277 is no point in pursuing this chain any further. */
1281 FOR_EACH_LOG_LINK (nextlinks
, link
)
1282 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1283 NULL
, &new_direct_jump_p
,
1284 last_combined_insn
)) != 0)
1286 statistics_counter_event (cfun
, "three-insn combine", 1);
1292 /* Try to combine a jump insn that uses CC0
1293 with a preceding insn that sets CC0, and maybe with its
1294 logical predecessor as well.
1295 This is how we make decrement-and-branch insns.
1296 We need this special code because data flow connections
1297 via CC0 do not get entered in LOG_LINKS. */
1300 && (prev
= prev_nonnote_insn (insn
)) != 0
1301 && NONJUMP_INSN_P (prev
)
1302 && sets_cc0_p (PATTERN (prev
)))
1304 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1306 last_combined_insn
)) != 0)
1309 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1310 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1311 NULL
, &new_direct_jump_p
,
1312 last_combined_insn
)) != 0)
1316 /* Do the same for an insn that explicitly references CC0. */
1317 if (NONJUMP_INSN_P (insn
)
1318 && (prev
= prev_nonnote_insn (insn
)) != 0
1319 && NONJUMP_INSN_P (prev
)
1320 && sets_cc0_p (PATTERN (prev
))
1321 && GET_CODE (PATTERN (insn
)) == SET
1322 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1324 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1326 last_combined_insn
)) != 0)
1329 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1330 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1331 NULL
, &new_direct_jump_p
,
1332 last_combined_insn
)) != 0)
1336 /* Finally, see if any of the insns that this insn links to
1337 explicitly references CC0. If so, try this insn, that insn,
1338 and its predecessor if it sets CC0. */
1339 FOR_EACH_LOG_LINK (links
, insn
)
1340 if (NONJUMP_INSN_P (links
->insn
)
1341 && GET_CODE (PATTERN (links
->insn
)) == SET
1342 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1343 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1344 && NONJUMP_INSN_P (prev
)
1345 && sets_cc0_p (PATTERN (prev
))
1346 && (next
= try_combine (insn
, links
->insn
,
1347 prev
, NULL
, &new_direct_jump_p
,
1348 last_combined_insn
)) != 0)
1352 /* Try combining an insn with two different insns whose results it
1354 if (max_combine
>= 3)
1355 FOR_EACH_LOG_LINK (links
, insn
)
1356 for (nextlinks
= links
->next
; nextlinks
;
1357 nextlinks
= nextlinks
->next
)
1358 if ((next
= try_combine (insn
, links
->insn
,
1359 nextlinks
->insn
, NULL
,
1361 last_combined_insn
)) != 0)
1364 statistics_counter_event (cfun
, "three-insn combine", 1);
1368 /* Try four-instruction combinations. */
1369 if (max_combine
>= 4)
1370 FOR_EACH_LOG_LINK (links
, insn
)
1372 struct insn_link
*next1
;
1373 rtx_insn
*link
= links
->insn
;
1375 /* If the linked insn has been replaced by a note, then there
1376 is no point in pursuing this chain any further. */
1380 FOR_EACH_LOG_LINK (next1
, link
)
1382 rtx_insn
*link1
= next1
->insn
;
1385 /* I0 -> I1 -> I2 -> I3. */
1386 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1387 if ((next
= try_combine (insn
, link
, link1
,
1390 last_combined_insn
)) != 0)
1392 statistics_counter_event (cfun
, "four-insn combine", 1);
1395 /* I0, I1 -> I2, I2 -> I3. */
1396 for (nextlinks
= next1
->next
; nextlinks
;
1397 nextlinks
= nextlinks
->next
)
1398 if ((next
= try_combine (insn
, link
, link1
,
1401 last_combined_insn
)) != 0)
1403 statistics_counter_event (cfun
, "four-insn combine", 1);
1408 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1410 rtx_insn
*link1
= next1
->insn
;
1413 /* I0 -> I2; I1, I2 -> I3. */
1414 FOR_EACH_LOG_LINK (nextlinks
, link
)
1415 if ((next
= try_combine (insn
, link
, link1
,
1418 last_combined_insn
)) != 0)
1420 statistics_counter_event (cfun
, "four-insn combine", 1);
1423 /* I0 -> I1; I1, I2 -> I3. */
1424 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1425 if ((next
= try_combine (insn
, link
, link1
,
1428 last_combined_insn
)) != 0)
1430 statistics_counter_event (cfun
, "four-insn combine", 1);
1436 /* Try this insn with each REG_EQUAL note it links back to. */
1437 FOR_EACH_LOG_LINK (links
, insn
)
1440 rtx_insn
*temp
= links
->insn
;
1441 if ((set
= single_set (temp
)) != 0
1442 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1443 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1444 /* Avoid using a register that may already been marked
1445 dead by an earlier instruction. */
1446 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1447 && (GET_MODE (note
) == VOIDmode
1448 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1449 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1451 /* Temporarily replace the set's source with the
1452 contents of the REG_EQUAL note. The insn will
1453 be deleted or recognized by try_combine. */
1454 rtx orig
= SET_SRC (set
);
1455 SET_SRC (set
) = note
;
1457 i2mod_old_rhs
= copy_rtx (orig
);
1458 i2mod_new_rhs
= copy_rtx (note
);
1459 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1461 last_combined_insn
);
1465 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1468 SET_SRC (set
) = orig
;
1473 record_dead_and_set_regs (insn
);
1480 default_rtl_profile ();
1482 new_direct_jump_p
|= purge_all_dead_edges ();
1483 delete_noop_moves ();
1486 obstack_free (&insn_link_obstack
, NULL
);
1487 free (uid_log_links
);
1488 free (uid_insn_cost
);
1489 reg_stat
.release ();
1492 struct undo
*undo
, *next
;
1493 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1501 total_attempts
+= combine_attempts
;
1502 total_merges
+= combine_merges
;
1503 total_extras
+= combine_extras
;
1504 total_successes
+= combine_successes
;
1506 nonzero_sign_valid
= 0;
1507 rtl_hooks
= general_rtl_hooks
;
1509 /* Make recognizer allow volatile MEMs again. */
1512 return new_direct_jump_p
;
1515 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1518 init_reg_last (void)
1523 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1524 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1527 /* Set up any promoted values for incoming argument registers. */
1530 setup_incoming_promotions (rtx_insn
*first
)
1533 bool strictly_local
= false;
1535 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1536 arg
= DECL_CHAIN (arg
))
1538 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1540 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1542 /* Only continue if the incoming argument is in a register. */
1546 /* Determine, if possible, whether all call sites of the current
1547 function lie within the current compilation unit. (This does
1548 take into account the exporting of a function via taking its
1549 address, and so forth.) */
1550 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1552 /* The mode and signedness of the argument before any promotions happen
1553 (equal to the mode of the pseudo holding it at that stage). */
1554 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1555 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1557 /* The mode and signedness of the argument after any source language and
1558 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1559 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1560 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1562 /* The mode and signedness of the argument as it is actually passed,
1563 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1564 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1565 TREE_TYPE (cfun
->decl
), 0);
1567 /* The mode of the register in which the argument is being passed. */
1568 mode4
= GET_MODE (reg
);
1570 /* Eliminate sign extensions in the callee when:
1571 (a) A mode promotion has occurred; */
1574 /* (b) The mode of the register is the same as the mode of
1575 the argument as it is passed; */
1578 /* (c) There's no language level extension; */
1581 /* (c.1) All callers are from the current compilation unit. If that's
1582 the case we don't have to rely on an ABI, we only have to know
1583 what we're generating right now, and we know that we will do the
1584 mode1 to mode2 promotion with the given sign. */
1585 else if (!strictly_local
)
1587 /* (c.2) The combination of the two promotions is useful. This is
1588 true when the signs match, or if the first promotion is unsigned.
1589 In the later case, (sign_extend (zero_extend x)) is the same as
1590 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1596 /* Record that the value was promoted from mode1 to mode3,
1597 so that any sign extension at the head of the current
1598 function may be eliminated. */
1599 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1600 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1601 record_value_for_reg (reg
, first
, x
);
1605 /* Called via note_stores. If X is a pseudo that is narrower than
1606 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1608 If we are setting only a portion of X and we can't figure out what
1609 portion, assume all bits will be used since we don't know what will
1612 Similarly, set how many bits of X are known to be copies of the sign bit
1613 at all locations in the function. This is the smallest number implied
1617 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1619 rtx_insn
*insn
= (rtx_insn
*) data
;
1623 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1624 /* If this register is undefined at the start of the file, we can't
1625 say what its contents were. */
1626 && ! REGNO_REG_SET_P
1627 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1628 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1630 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1632 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1634 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1635 rsp
->sign_bit_copies
= 1;
1639 /* If this register is being initialized using itself, and the
1640 register is uninitialized in this basic block, and there are
1641 no LOG_LINKS which set the register, then part of the
1642 register is uninitialized. In that case we can't assume
1643 anything about the number of nonzero bits.
1645 ??? We could do better if we checked this in
1646 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1647 could avoid making assumptions about the insn which initially
1648 sets the register, while still using the information in other
1649 insns. We would have to be careful to check every insn
1650 involved in the combination. */
1653 && reg_referenced_p (x
, PATTERN (insn
))
1654 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1657 struct insn_link
*link
;
1659 FOR_EACH_LOG_LINK (link
, insn
)
1660 if (dead_or_set_p (link
->insn
, x
))
1664 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1665 rsp
->sign_bit_copies
= 1;
1670 /* If this is a complex assignment, see if we can convert it into a
1671 simple assignment. */
1672 set
= expand_field_assignment (set
);
1674 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1675 set what we know about X. */
1677 if (SET_DEST (set
) == x
1678 || (paradoxical_subreg_p (SET_DEST (set
))
1679 && SUBREG_REG (SET_DEST (set
)) == x
))
1681 rtx src
= SET_SRC (set
);
1683 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1684 /* If X is narrower than a word and SRC is a non-negative
1685 constant that would appear negative in the mode of X,
1686 sign-extend it for use in reg_stat[].nonzero_bits because some
1687 machines (maybe most) will actually do the sign-extension
1688 and this is the conservative approach.
1690 ??? For 2.5, try to tighten up the MD files in this regard
1691 instead of this kludge. */
1693 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1694 && CONST_INT_P (src
)
1696 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1697 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1700 /* Don't call nonzero_bits if it cannot change anything. */
1701 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1702 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1703 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1704 if (rsp
->sign_bit_copies
== 0
1705 || rsp
->sign_bit_copies
> num
)
1706 rsp
->sign_bit_copies
= num
;
1710 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1711 rsp
->sign_bit_copies
= 1;
1716 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1717 optionally insns that were previously combined into I3 or that will be
1718 combined into the merger of INSN and I3. The order is PRED, PRED2,
1719 INSN, SUCC, SUCC2, I3.
1721 Return 0 if the combination is not allowed for any reason.
1723 If the combination is allowed, *PDEST will be set to the single
1724 destination of INSN and *PSRC to the single source, and this function
1728 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1729 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1730 rtx
*pdest
, rtx
*psrc
)
1739 bool all_adjacent
= true;
1740 int (*is_volatile_p
) (const_rtx
);
1746 if (next_active_insn (succ2
) != i3
)
1747 all_adjacent
= false;
1748 if (next_active_insn (succ
) != succ2
)
1749 all_adjacent
= false;
1751 else if (next_active_insn (succ
) != i3
)
1752 all_adjacent
= false;
1753 if (next_active_insn (insn
) != succ
)
1754 all_adjacent
= false;
1756 else if (next_active_insn (insn
) != i3
)
1757 all_adjacent
= false;
1759 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1760 or a PARALLEL consisting of such a SET and CLOBBERs.
1762 If INSN has CLOBBER parallel parts, ignore them for our processing.
1763 By definition, these happen during the execution of the insn. When it
1764 is merged with another insn, all bets are off. If they are, in fact,
1765 needed and aren't also supplied in I3, they may be added by
1766 recog_for_combine. Otherwise, it won't match.
1768 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1771 Get the source and destination of INSN. If more than one, can't
1774 if (GET_CODE (PATTERN (insn
)) == SET
)
1775 set
= PATTERN (insn
);
1776 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1777 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1779 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1781 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1783 switch (GET_CODE (elt
))
1785 /* This is important to combine floating point insns
1786 for the SH4 port. */
1788 /* Combining an isolated USE doesn't make sense.
1789 We depend here on combinable_i3pat to reject them. */
1790 /* The code below this loop only verifies that the inputs of
1791 the SET in INSN do not change. We call reg_set_between_p
1792 to verify that the REG in the USE does not change between
1794 If the USE in INSN was for a pseudo register, the matching
1795 insn pattern will likely match any register; combining this
1796 with any other USE would only be safe if we knew that the
1797 used registers have identical values, or if there was
1798 something to tell them apart, e.g. different modes. For
1799 now, we forgo such complicated tests and simply disallow
1800 combining of USES of pseudo registers with any other USE. */
1801 if (REG_P (XEXP (elt
, 0))
1802 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1804 rtx i3pat
= PATTERN (i3
);
1805 int i
= XVECLEN (i3pat
, 0) - 1;
1806 unsigned int regno
= REGNO (XEXP (elt
, 0));
1810 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1812 if (GET_CODE (i3elt
) == USE
1813 && REG_P (XEXP (i3elt
, 0))
1814 && (REGNO (XEXP (i3elt
, 0)) == regno
1815 ? reg_set_between_p (XEXP (elt
, 0),
1816 PREV_INSN (insn
), i3
)
1817 : regno
>= FIRST_PSEUDO_REGISTER
))
1824 /* We can ignore CLOBBERs. */
1829 /* Ignore SETs whose result isn't used but not those that
1830 have side-effects. */
1831 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1832 && insn_nothrow_p (insn
)
1833 && !side_effects_p (elt
))
1836 /* If we have already found a SET, this is a second one and
1837 so we cannot combine with this insn. */
1845 /* Anything else means we can't combine. */
1851 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1852 so don't do anything with it. */
1853 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1862 /* The simplification in expand_field_assignment may call back to
1863 get_last_value, so set safe guard here. */
1864 subst_low_luid
= DF_INSN_LUID (insn
);
1866 set
= expand_field_assignment (set
);
1867 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1869 /* Don't eliminate a store in the stack pointer. */
1870 if (dest
== stack_pointer_rtx
1871 /* Don't combine with an insn that sets a register to itself if it has
1872 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1873 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1874 /* Can't merge an ASM_OPERANDS. */
1875 || GET_CODE (src
) == ASM_OPERANDS
1876 /* Can't merge a function call. */
1877 || GET_CODE (src
) == CALL
1878 /* Don't eliminate a function call argument. */
1880 && (find_reg_fusage (i3
, USE
, dest
)
1882 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1883 && global_regs
[REGNO (dest
)])))
1884 /* Don't substitute into an incremented register. */
1885 || FIND_REG_INC_NOTE (i3
, dest
)
1886 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1887 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1888 /* Don't substitute into a non-local goto, this confuses CFG. */
1889 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1890 /* Make sure that DEST is not used after SUCC but before I3. */
1893 && (reg_used_between_p (dest
, succ2
, i3
)
1894 || reg_used_between_p (dest
, succ
, succ2
)))
1895 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1896 /* Make sure that the value that is to be substituted for the register
1897 does not use any registers whose values alter in between. However,
1898 If the insns are adjacent, a use can't cross a set even though we
1899 think it might (this can happen for a sequence of insns each setting
1900 the same destination; last_set of that register might point to
1901 a NOTE). If INSN has a REG_EQUIV note, the register is always
1902 equivalent to the memory so the substitution is valid even if there
1903 are intervening stores. Also, don't move a volatile asm or
1904 UNSPEC_VOLATILE across any other insns. */
1907 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1908 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1909 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1910 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1911 /* Don't combine across a CALL_INSN, because that would possibly
1912 change whether the life span of some REGs crosses calls or not,
1913 and it is a pain to update that information.
1914 Exception: if source is a constant, moving it later can't hurt.
1915 Accept that as a special case. */
1916 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1919 /* DEST must either be a REG or CC0. */
1922 /* If register alignment is being enforced for multi-word items in all
1923 cases except for parameters, it is possible to have a register copy
1924 insn referencing a hard register that is not allowed to contain the
1925 mode being copied and which would not be valid as an operand of most
1926 insns. Eliminate this problem by not combining with such an insn.
1928 Also, on some machines we don't want to extend the life of a hard
1932 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1933 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1934 /* Don't extend the life of a hard register unless it is
1935 user variable (if we have few registers) or it can't
1936 fit into the desired register (meaning something special
1938 Also avoid substituting a return register into I3, because
1939 reload can't handle a conflict with constraints of other
1941 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1942 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1945 else if (GET_CODE (dest
) != CC0
)
1949 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1950 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1951 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1953 /* Don't substitute for a register intended as a clobberable
1955 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1956 if (rtx_equal_p (reg
, dest
))
1959 /* If the clobber represents an earlyclobber operand, we must not
1960 substitute an expression containing the clobbered register.
1961 As we do not analyze the constraint strings here, we have to
1962 make the conservative assumption. However, if the register is
1963 a fixed hard reg, the clobber cannot represent any operand;
1964 we leave it up to the machine description to either accept or
1965 reject use-and-clobber patterns. */
1967 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1968 || !fixed_regs
[REGNO (reg
)])
1969 if (reg_overlap_mentioned_p (reg
, src
))
1973 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1974 or not), reject, unless nothing volatile comes between it and I3 */
1976 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1978 /* Make sure neither succ nor succ2 contains a volatile reference. */
1979 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1981 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1983 /* We'll check insns between INSN and I3 below. */
1986 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1987 to be an explicit register variable, and was chosen for a reason. */
1989 if (GET_CODE (src
) == ASM_OPERANDS
1990 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1993 /* If INSN contains volatile references (specifically volatile MEMs),
1994 we cannot combine across any other volatile references.
1995 Even if INSN doesn't contain volatile references, any intervening
1996 volatile insn might affect machine state. */
1998 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2002 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2003 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2006 /* If INSN contains an autoincrement or autodecrement, make sure that
2007 register is not used between there and I3, and not already used in
2008 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2009 Also insist that I3 not be a jump; if it were one
2010 and the incremented register were spilled, we would lose. */
2013 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2014 if (REG_NOTE_KIND (link
) == REG_INC
2016 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2017 || (pred
!= NULL_RTX
2018 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2019 || (pred2
!= NULL_RTX
2020 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2021 || (succ
!= NULL_RTX
2022 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2023 || (succ2
!= NULL_RTX
2024 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2025 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2030 /* Don't combine an insn that follows a CC0-setting insn.
2031 An insn that uses CC0 must not be separated from the one that sets it.
2032 We do, however, allow I2 to follow a CC0-setting insn if that insn
2033 is passed as I1; in that case it will be deleted also.
2034 We also allow combining in this case if all the insns are adjacent
2035 because that would leave the two CC0 insns adjacent as well.
2036 It would be more logical to test whether CC0 occurs inside I1 or I2,
2037 but that would be much slower, and this ought to be equivalent. */
2039 p
= prev_nonnote_insn (insn
);
2040 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2045 /* If we get here, we have passed all the tests and the combination is
2054 /* LOC is the location within I3 that contains its pattern or the component
2055 of a PARALLEL of the pattern. We validate that it is valid for combining.
2057 One problem is if I3 modifies its output, as opposed to replacing it
2058 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2059 doing so would produce an insn that is not equivalent to the original insns.
2063 (set (reg:DI 101) (reg:DI 100))
2064 (set (subreg:SI (reg:DI 101) 0) <foo>)
2066 This is NOT equivalent to:
2068 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2069 (set (reg:DI 101) (reg:DI 100))])
2071 Not only does this modify 100 (in which case it might still be valid
2072 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2074 We can also run into a problem if I2 sets a register that I1
2075 uses and I1 gets directly substituted into I3 (not via I2). In that
2076 case, we would be getting the wrong value of I2DEST into I3, so we
2077 must reject the combination. This case occurs when I2 and I1 both
2078 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2079 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2080 of a SET must prevent combination from occurring. The same situation
2081 can occur for I0, in which case I0_NOT_IN_SRC is set.
2083 Before doing the above check, we first try to expand a field assignment
2084 into a set of logical operations.
2086 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2087 we place a register that is both set and used within I3. If more than one
2088 such register is detected, we fail.
2090 Return 1 if the combination is valid, zero otherwise. */
2093 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2094 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2098 if (GET_CODE (x
) == SET
)
2101 rtx dest
= SET_DEST (set
);
2102 rtx src
= SET_SRC (set
);
2103 rtx inner_dest
= dest
;
2106 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2107 || GET_CODE (inner_dest
) == SUBREG
2108 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2109 inner_dest
= XEXP (inner_dest
, 0);
2111 /* Check for the case where I3 modifies its output, as discussed
2112 above. We don't want to prevent pseudos from being combined
2113 into the address of a MEM, so only prevent the combination if
2114 i1 or i2 set the same MEM. */
2115 if ((inner_dest
!= dest
&&
2116 (!MEM_P (inner_dest
)
2117 || rtx_equal_p (i2dest
, inner_dest
)
2118 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2119 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2120 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2121 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2122 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2124 /* This is the same test done in can_combine_p except we can't test
2125 all_adjacent; we don't have to, since this instruction will stay
2126 in place, thus we are not considering increasing the lifetime of
2129 Also, if this insn sets a function argument, combining it with
2130 something that might need a spill could clobber a previous
2131 function argument; the all_adjacent test in can_combine_p also
2132 checks this; here, we do a more specific test for this case. */
2134 || (REG_P (inner_dest
)
2135 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2136 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2137 GET_MODE (inner_dest
))))
2138 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2139 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2142 /* If DEST is used in I3, it is being killed in this insn, so
2143 record that for later. We have to consider paradoxical
2144 subregs here, since they kill the whole register, but we
2145 ignore partial subregs, STRICT_LOW_PART, etc.
2146 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2147 STACK_POINTER_REGNUM, since these are always considered to be
2148 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2150 if (GET_CODE (subdest
) == SUBREG
2151 && (GET_MODE_SIZE (GET_MODE (subdest
))
2152 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2153 subdest
= SUBREG_REG (subdest
);
2156 && reg_referenced_p (subdest
, PATTERN (i3
))
2157 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2158 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2159 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2161 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2162 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2163 || ! fixed_regs
[REGNO (subdest
)])
2165 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2167 if (*pi3dest_killed
)
2170 *pi3dest_killed
= subdest
;
2174 else if (GET_CODE (x
) == PARALLEL
)
2178 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2179 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2180 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2187 /* Return 1 if X is an arithmetic expression that contains a multiplication
2188 and division. We don't count multiplications by powers of two here. */
2191 contains_muldiv (rtx x
)
2193 switch (GET_CODE (x
))
2195 case MOD
: case DIV
: case UMOD
: case UDIV
:
2199 return ! (CONST_INT_P (XEXP (x
, 1))
2200 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2203 return contains_muldiv (XEXP (x
, 0))
2204 || contains_muldiv (XEXP (x
, 1));
2207 return contains_muldiv (XEXP (x
, 0));
2213 /* Determine whether INSN can be used in a combination. Return nonzero if
2214 not. This is used in try_combine to detect early some cases where we
2215 can't perform combinations. */
2218 cant_combine_insn_p (rtx_insn
*insn
)
2223 /* If this isn't really an insn, we can't do anything.
2224 This can occur when flow deletes an insn that it has merged into an
2225 auto-increment address. */
2226 if (! INSN_P (insn
))
2229 /* Never combine loads and stores involving hard regs that are likely
2230 to be spilled. The register allocator can usually handle such
2231 reg-reg moves by tying. If we allow the combiner to make
2232 substitutions of likely-spilled regs, reload might die.
2233 As an exception, we allow combinations involving fixed regs; these are
2234 not available to the register allocator so there's no risk involved. */
2236 set
= single_set (insn
);
2239 src
= SET_SRC (set
);
2240 dest
= SET_DEST (set
);
2241 if (GET_CODE (src
) == SUBREG
)
2242 src
= SUBREG_REG (src
);
2243 if (GET_CODE (dest
) == SUBREG
)
2244 dest
= SUBREG_REG (dest
);
2245 if (REG_P (src
) && REG_P (dest
)
2246 && ((HARD_REGISTER_P (src
)
2247 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2248 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2249 || (HARD_REGISTER_P (dest
)
2250 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2251 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2257 struct likely_spilled_retval_info
2259 unsigned regno
, nregs
;
2263 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2264 hard registers that are known to be written to / clobbered in full. */
2266 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2268 struct likely_spilled_retval_info
*const info
=
2269 (struct likely_spilled_retval_info
*) data
;
2270 unsigned regno
, nregs
;
2273 if (!REG_P (XEXP (set
, 0)))
2276 if (regno
>= info
->regno
+ info
->nregs
)
2278 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2279 if (regno
+ nregs
<= info
->regno
)
2281 new_mask
= (2U << (nregs
- 1)) - 1;
2282 if (regno
< info
->regno
)
2283 new_mask
>>= info
->regno
- regno
;
2285 new_mask
<<= regno
- info
->regno
;
2286 info
->mask
&= ~new_mask
;
2289 /* Return nonzero iff part of the return value is live during INSN, and
2290 it is likely spilled. This can happen when more than one insn is needed
2291 to copy the return value, e.g. when we consider to combine into the
2292 second copy insn for a complex value. */
2295 likely_spilled_retval_p (rtx_insn
*insn
)
2297 rtx use
= BB_END (this_basic_block
);
2299 unsigned regno
, nregs
;
2300 /* We assume here that no machine mode needs more than
2301 32 hard registers when the value overlaps with a register
2302 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2304 struct likely_spilled_retval_info info
;
2306 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2308 reg
= XEXP (PATTERN (use
), 0);
2309 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2311 regno
= REGNO (reg
);
2312 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2315 mask
= (2U << (nregs
- 1)) - 1;
2317 /* Disregard parts of the return value that are set later. */
2321 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2323 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2326 /* Check if any of the (probably) live return value registers is
2331 if ((mask
& 1 << nregs
)
2332 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2338 /* Adjust INSN after we made a change to its destination.
2340 Changing the destination can invalidate notes that say something about
2341 the results of the insn and a LOG_LINK pointing to the insn. */
2344 adjust_for_new_dest (rtx_insn
*insn
)
2346 /* For notes, be conservative and simply remove them. */
2347 remove_reg_equal_equiv_notes (insn
);
2349 /* The new insn will have a destination that was previously the destination
2350 of an insn just above it. Call distribute_links to make a LOG_LINK from
2351 the next use of that destination. */
2352 distribute_links (alloc_insn_link (insn
, NULL
));
2354 df_insn_rescan (insn
);
2357 /* Return TRUE if combine can reuse reg X in mode MODE.
2358 ADDED_SETS is nonzero if the original set is still required. */
2360 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2368 /* Allow hard registers if the new mode is legal, and occupies no more
2369 registers than the old mode. */
2370 if (regno
< FIRST_PSEUDO_REGISTER
)
2371 return (HARD_REGNO_MODE_OK (regno
, mode
)
2372 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2373 >= hard_regno_nregs
[regno
][mode
]));
2375 /* Or a pseudo that is only used once. */
2376 return (REG_N_SETS (regno
) == 1 && !added_sets
2377 && !REG_USERVAR_P (x
));
2381 /* Check whether X, the destination of a set, refers to part of
2382 the register specified by REG. */
2385 reg_subword_p (rtx x
, rtx reg
)
2387 /* Check that reg is an integer mode register. */
2388 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2391 if (GET_CODE (x
) == STRICT_LOW_PART
2392 || GET_CODE (x
) == ZERO_EXTRACT
)
2395 return GET_CODE (x
) == SUBREG
2396 && SUBREG_REG (x
) == reg
2397 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2400 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2401 Note that the INSN should be deleted *after* removing dead edges, so
2402 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2403 but not for a (set (pc) (label_ref FOO)). */
2406 update_cfg_for_uncondjump (rtx_insn
*insn
)
2408 basic_block bb
= BLOCK_FOR_INSN (insn
);
2409 gcc_assert (BB_END (bb
) == insn
);
2411 purge_dead_edges (bb
);
2414 if (EDGE_COUNT (bb
->succs
) == 1)
2418 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2420 /* Remove barriers from the footer if there are any. */
2421 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2422 if (BARRIER_P (insn
))
2424 if (PREV_INSN (insn
))
2425 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2427 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2428 if (NEXT_INSN (insn
))
2429 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2431 else if (LABEL_P (insn
))
2436 /* Try to combine the insns I0, I1 and I2 into I3.
2437 Here I0, I1 and I2 appear earlier than I3.
2438 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2441 If we are combining more than two insns and the resulting insn is not
2442 recognized, try splitting it into two insns. If that happens, I2 and I3
2443 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2444 Otherwise, I0, I1 and I2 are pseudo-deleted.
2446 Return 0 if the combination does not work. Then nothing is changed.
2447 If we did the combination, return the insn at which combine should
2450 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2451 new direct jump instruction.
2453 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2454 been I3 passed to an earlier try_combine within the same basic
2458 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2459 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2461 /* New patterns for I3 and I2, respectively. */
2462 rtx newpat
, newi2pat
= 0;
2463 rtvec newpat_vec_with_clobbers
= 0;
2464 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2465 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2467 int added_sets_0
, added_sets_1
, added_sets_2
;
2468 /* Total number of SETs to put into I3. */
2470 /* Nonzero if I2's or I1's body now appears in I3. */
2471 int i2_is_used
= 0, i1_is_used
= 0;
2472 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2473 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2474 /* Contains I3 if the destination of I3 is used in its source, which means
2475 that the old life of I3 is being killed. If that usage is placed into
2476 I2 and not in I3, a REG_DEAD note must be made. */
2477 rtx i3dest_killed
= 0;
2478 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2479 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2480 /* Copy of SET_SRC of I1 and I0, if needed. */
2481 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2482 /* Set if I2DEST was reused as a scratch register. */
2483 bool i2scratch
= false;
2484 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2485 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2486 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2487 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2488 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2489 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2490 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2491 /* Notes that must be added to REG_NOTES in I3 and I2. */
2492 rtx new_i3_notes
, new_i2_notes
;
2493 /* Notes that we substituted I3 into I2 instead of the normal case. */
2494 int i3_subst_into_i2
= 0;
2495 /* Notes that I1, I2 or I3 is a MULT operation. */
2498 int changed_i3_dest
= 0;
2501 rtx_insn
*temp_insn
;
2503 struct insn_link
*link
;
2505 rtx new_other_notes
;
2508 /* Only try four-insn combinations when there's high likelihood of
2509 success. Look for simple insns, such as loads of constants or
2510 binary operations involving a constant. */
2517 if (!flag_expensive_optimizations
)
2520 for (i
= 0; i
< 4; i
++)
2522 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2523 rtx set
= single_set (insn
);
2527 src
= SET_SRC (set
);
2528 if (CONSTANT_P (src
))
2533 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2535 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2536 || GET_CODE (src
) == LSHIFTRT
)
2539 if (ngood
< 2 && nshift
< 2)
2543 /* Exit early if one of the insns involved can't be used for
2545 if (cant_combine_insn_p (i3
)
2546 || cant_combine_insn_p (i2
)
2547 || (i1
&& cant_combine_insn_p (i1
))
2548 || (i0
&& cant_combine_insn_p (i0
))
2549 || likely_spilled_retval_p (i3
))
2553 undobuf
.other_insn
= 0;
2555 /* Reset the hard register usage information. */
2556 CLEAR_HARD_REG_SET (newpat_used_regs
);
2558 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2561 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2562 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2564 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2565 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2567 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2568 INSN_UID (i2
), INSN_UID (i3
));
2571 /* If multiple insns feed into one of I2 or I3, they can be in any
2572 order. To simplify the code below, reorder them in sequence. */
2573 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2574 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2575 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2576 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2577 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2578 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2580 added_links_insn
= 0;
2582 /* First check for one important special case that the code below will
2583 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2584 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2585 we may be able to replace that destination with the destination of I3.
2586 This occurs in the common code where we compute both a quotient and
2587 remainder into a structure, in which case we want to do the computation
2588 directly into the structure to avoid register-register copies.
2590 Note that this case handles both multiple sets in I2 and also cases
2591 where I2 has a number of CLOBBERs inside the PARALLEL.
2593 We make very conservative checks below and only try to handle the
2594 most common cases of this. For example, we only handle the case
2595 where I2 and I3 are adjacent to avoid making difficult register
2598 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2599 && REG_P (SET_SRC (PATTERN (i3
)))
2600 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2601 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2602 && GET_CODE (PATTERN (i2
)) == PARALLEL
2603 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2604 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2605 below would need to check what is inside (and reg_overlap_mentioned_p
2606 doesn't support those codes anyway). Don't allow those destinations;
2607 the resulting insn isn't likely to be recognized anyway. */
2608 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2609 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2610 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2611 SET_DEST (PATTERN (i3
)))
2612 && next_active_insn (i2
) == i3
)
2614 rtx p2
= PATTERN (i2
);
2616 /* Make sure that the destination of I3,
2617 which we are going to substitute into one output of I2,
2618 is not used within another output of I2. We must avoid making this:
2619 (parallel [(set (mem (reg 69)) ...)
2620 (set (reg 69) ...)])
2621 which is not well-defined as to order of actions.
2622 (Besides, reload can't handle output reloads for this.)
2624 The problem can also happen if the dest of I3 is a memory ref,
2625 if another dest in I2 is an indirect memory ref. */
2626 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2627 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2628 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2629 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2630 SET_DEST (XVECEXP (p2
, 0, i
))))
2633 if (i
== XVECLEN (p2
, 0))
2634 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2635 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2636 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2641 subst_low_luid
= DF_INSN_LUID (i2
);
2643 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2644 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2645 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2646 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2648 /* Replace the dest in I2 with our dest and make the resulting
2649 insn the new pattern for I3. Then skip to where we validate
2650 the pattern. Everything was set up above. */
2651 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2653 i3_subst_into_i2
= 1;
2654 goto validate_replacement
;
2658 /* If I2 is setting a pseudo to a constant and I3 is setting some
2659 sub-part of it to another constant, merge them by making a new
2662 && (temp_expr
= single_set (i2
)) != 0
2663 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2664 && GET_CODE (PATTERN (i3
)) == SET
2665 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2666 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2668 rtx dest
= SET_DEST (PATTERN (i3
));
2672 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2674 if (CONST_INT_P (XEXP (dest
, 1))
2675 && CONST_INT_P (XEXP (dest
, 2)))
2677 width
= INTVAL (XEXP (dest
, 1));
2678 offset
= INTVAL (XEXP (dest
, 2));
2679 dest
= XEXP (dest
, 0);
2680 if (BITS_BIG_ENDIAN
)
2681 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2686 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2687 dest
= XEXP (dest
, 0);
2688 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2694 /* If this is the low part, we're done. */
2695 if (subreg_lowpart_p (dest
))
2697 /* Handle the case where inner is twice the size of outer. */
2698 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2699 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2700 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2701 /* Otherwise give up for now. */
2708 rtx inner
= SET_SRC (PATTERN (i3
));
2709 rtx outer
= SET_SRC (temp_expr
);
2712 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2713 std::make_pair (inner
, GET_MODE (dest
)),
2718 subst_low_luid
= DF_INSN_LUID (i2
);
2719 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2720 i2dest
= SET_DEST (temp_expr
);
2721 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2723 /* Replace the source in I2 with the new constant and make the
2724 resulting insn the new pattern for I3. Then skip to where we
2725 validate the pattern. Everything was set up above. */
2726 SUBST (SET_SRC (temp_expr
),
2727 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2729 newpat
= PATTERN (i2
);
2731 /* The dest of I3 has been replaced with the dest of I2. */
2732 changed_i3_dest
= 1;
2733 goto validate_replacement
;
2738 /* If we have no I1 and I2 looks like:
2739 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2741 make up a dummy I1 that is
2744 (set (reg:CC X) (compare:CC Y (const_int 0)))
2746 (We can ignore any trailing CLOBBERs.)
2748 This undoes a previous combination and allows us to match a branch-and-
2751 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2752 && XVECLEN (PATTERN (i2
), 0) >= 2
2753 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2754 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2756 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2757 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2758 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2759 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2760 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2761 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2763 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2764 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2769 /* We make I1 with the same INSN_UID as I2. This gives it
2770 the same DF_INSN_LUID for value tracking. Our fake I1 will
2771 never appear in the insn stream so giving it the same INSN_UID
2772 as I2 will not cause a problem. */
2774 i1
= as_a
<rtx_insn
*> (
2775 gen_rtx_INSN (VOIDmode
, NULL_RTX
, i2
, BLOCK_FOR_INSN (i2
),
2776 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2778 INSN_UID (i1
) = INSN_UID (i2
);
2780 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2781 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2782 SET_DEST (PATTERN (i1
)));
2783 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2788 /* Verify that I2 and I1 are valid for combining. */
2789 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2790 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2792 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2799 /* Record whether I2DEST is used in I2SRC and similarly for the other
2800 cases. Knowing this will help in register status updating below. */
2801 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2802 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2803 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2804 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2805 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2806 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2807 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2808 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2809 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2811 /* For the earlier insns, determine which of the subsequent ones they
2813 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2814 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2815 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2816 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2817 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2819 /* Ensure that I3's pattern can be the destination of combines. */
2820 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2821 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2822 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2823 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2830 /* See if any of the insns is a MULT operation. Unless one is, we will
2831 reject a combination that is, since it must be slower. Be conservative
2833 if (GET_CODE (i2src
) == MULT
2834 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2835 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2836 || (GET_CODE (PATTERN (i3
)) == SET
2837 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2840 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2841 We used to do this EXCEPT in one case: I3 has a post-inc in an
2842 output operand. However, that exception can give rise to insns like
2844 which is a famous insn on the PDP-11 where the value of r3 used as the
2845 source was model-dependent. Avoid this sort of thing. */
2848 if (!(GET_CODE (PATTERN (i3
)) == SET
2849 && REG_P (SET_SRC (PATTERN (i3
)))
2850 && MEM_P (SET_DEST (PATTERN (i3
)))
2851 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2852 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2853 /* It's not the exception. */
2858 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2859 if (REG_NOTE_KIND (link
) == REG_INC
2860 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2862 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2870 /* See if the SETs in I1 or I2 need to be kept around in the merged
2871 instruction: whenever the value set there is still needed past I3.
2872 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2874 For the SET in I1, we have two cases: if I1 and I2 independently feed
2875 into I3, the set in I1 needs to be kept around unless I1DEST dies
2876 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2877 in I1 needs to be kept around unless I1DEST dies or is set in either
2878 I2 or I3. The same considerations apply to I0. */
2880 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2883 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2884 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2889 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2890 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2891 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2892 && dead_or_set_p (i2
, i0dest
)));
2896 /* We are about to copy insns for the case where they need to be kept
2897 around. Check that they can be copied in the merged instruction. */
2899 if (targetm
.cannot_copy_insn_p
2900 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2901 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2902 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2908 /* If the set in I2 needs to be kept around, we must make a copy of
2909 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2910 PATTERN (I2), we are only substituting for the original I1DEST, not into
2911 an already-substituted copy. This also prevents making self-referential
2912 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2917 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2918 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2920 i2pat
= copy_rtx (PATTERN (i2
));
2925 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2926 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2928 i1pat
= copy_rtx (PATTERN (i1
));
2933 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2934 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2936 i0pat
= copy_rtx (PATTERN (i0
));
2941 /* Substitute in the latest insn for the regs set by the earlier ones. */
2943 maxreg
= max_reg_num ();
2948 /* Many machines that don't use CC0 have insns that can both perform an
2949 arithmetic operation and set the condition code. These operations will
2950 be represented as a PARALLEL with the first element of the vector
2951 being a COMPARE of an arithmetic operation with the constant zero.
2952 The second element of the vector will set some pseudo to the result
2953 of the same arithmetic operation. If we simplify the COMPARE, we won't
2954 match such a pattern and so will generate an extra insn. Here we test
2955 for this case, where both the comparison and the operation result are
2956 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2957 I2SRC. Later we will make the PARALLEL that contains I2. */
2959 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2960 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2961 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2962 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2965 rtx
*cc_use_loc
= NULL
;
2966 rtx_insn
*cc_use_insn
= NULL
;
2967 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2968 enum machine_mode compare_mode
, orig_compare_mode
;
2969 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2971 newpat
= PATTERN (i3
);
2972 newpat_dest
= SET_DEST (newpat
);
2973 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2975 if (undobuf
.other_insn
== 0
2976 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2979 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2980 compare_code
= simplify_compare_const (compare_code
,
2981 GET_MODE (i2dest
), op0
, &op1
);
2982 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2985 /* Do the rest only if op1 is const0_rtx, which may be the
2986 result of simplification. */
2987 if (op1
== const0_rtx
)
2989 /* If a single use of the CC is found, prepare to modify it
2990 when SELECT_CC_MODE returns a new CC-class mode, or when
2991 the above simplify_compare_const() returned a new comparison
2992 operator. undobuf.other_insn is assigned the CC use insn
2993 when modifying it. */
2996 #ifdef SELECT_CC_MODE
2997 enum machine_mode new_mode
2998 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2999 if (new_mode
!= orig_compare_mode
3000 && can_change_dest_mode (SET_DEST (newpat
),
3001 added_sets_2
, new_mode
))
3003 unsigned int regno
= REGNO (newpat_dest
);
3004 compare_mode
= new_mode
;
3005 if (regno
< FIRST_PSEUDO_REGISTER
)
3006 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3009 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3010 newpat_dest
= regno_reg_rtx
[regno
];
3014 /* Cases for modifying the CC-using comparison. */
3015 if (compare_code
!= orig_compare_code
3016 /* ??? Do we need to verify the zero rtx? */
3017 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3019 /* Replace cc_use_loc with entire new RTX. */
3021 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3022 newpat_dest
, const0_rtx
));
3023 undobuf
.other_insn
= cc_use_insn
;
3025 else if (compare_mode
!= orig_compare_mode
)
3027 /* Just replace the CC reg with a new mode. */
3028 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3029 undobuf
.other_insn
= cc_use_insn
;
3033 /* Now we modify the current newpat:
3034 First, SET_DEST(newpat) is updated if the CC mode has been
3035 altered. For targets without SELECT_CC_MODE, this should be
3037 if (compare_mode
!= orig_compare_mode
)
3038 SUBST (SET_DEST (newpat
), newpat_dest
);
3039 /* This is always done to propagate i2src into newpat. */
3040 SUBST (SET_SRC (newpat
),
3041 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3042 /* Create new version of i2pat if needed; the below PARALLEL
3043 creation needs this to work correctly. */
3044 if (! rtx_equal_p (i2src
, op0
))
3045 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3051 if (i2_is_used
== 0)
3053 /* It is possible that the source of I2 or I1 may be performing
3054 an unneeded operation, such as a ZERO_EXTEND of something
3055 that is known to have the high part zero. Handle that case
3056 by letting subst look at the inner insns.
3058 Another way to do this would be to have a function that tries
3059 to simplify a single insn instead of merging two or more
3060 insns. We don't do this because of the potential of infinite
3061 loops and because of the potential extra memory required.
3062 However, doing it the way we are is a bit of a kludge and
3063 doesn't catch all cases.
3065 But only do this if -fexpensive-optimizations since it slows
3066 things down and doesn't usually win.
3068 This is not done in the COMPARE case above because the
3069 unmodified I2PAT is used in the PARALLEL and so a pattern
3070 with a modified I2SRC would not match. */
3072 if (flag_expensive_optimizations
)
3074 /* Pass pc_rtx so no substitutions are done, just
3078 subst_low_luid
= DF_INSN_LUID (i1
);
3079 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3082 subst_low_luid
= DF_INSN_LUID (i2
);
3083 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3086 n_occurrences
= 0; /* `subst' counts here */
3087 subst_low_luid
= DF_INSN_LUID (i2
);
3089 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3090 copy of I2SRC each time we substitute it, in order to avoid creating
3091 self-referential RTL when we will be substituting I1SRC for I1DEST
3092 later. Likewise if I0 feeds into I2, either directly or indirectly
3093 through I1, and I0DEST is in I0SRC. */
3094 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3095 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3096 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3097 && i0dest_in_i0src
));
3100 /* Record whether I2's body now appears within I3's body. */
3101 i2_is_used
= n_occurrences
;
3104 /* If we already got a failure, don't try to do more. Otherwise, try to
3105 substitute I1 if we have it. */
3107 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3109 /* Check that an autoincrement side-effect on I1 has not been lost.
3110 This happens if I1DEST is mentioned in I2 and dies there, and
3111 has disappeared from the new pattern. */
3112 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3114 && dead_or_set_p (i2
, i1dest
)
3115 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3116 /* Before we can do this substitution, we must redo the test done
3117 above (see detailed comments there) that ensures I1DEST isn't
3118 mentioned in any SETs in NEWPAT that are field assignments. */
3119 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3127 subst_low_luid
= DF_INSN_LUID (i1
);
3129 /* If the following substitution will modify I1SRC, make a copy of it
3130 for the case where it is substituted for I1DEST in I2PAT later. */
3131 if (added_sets_2
&& i1_feeds_i2_n
)
3132 i1src_copy
= copy_rtx (i1src
);
3134 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3135 copy of I1SRC each time we substitute it, in order to avoid creating
3136 self-referential RTL when we will be substituting I0SRC for I0DEST
3138 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3139 i0_feeds_i1_n
&& i0dest_in_i0src
);
3142 /* Record whether I1's body now appears within I3's body. */
3143 i1_is_used
= n_occurrences
;
3146 /* Likewise for I0 if we have it. */
3148 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3150 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3151 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3152 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3153 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3154 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3161 /* If the following substitution will modify I0SRC, make a copy of it
3162 for the case where it is substituted for I0DEST in I1PAT later. */
3163 if (added_sets_1
&& i0_feeds_i1_n
)
3164 i0src_copy
= copy_rtx (i0src
);
3165 /* And a copy for I0DEST in I2PAT substitution. */
3166 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3167 || (i0_feeds_i2_n
)))
3168 i0src_copy2
= copy_rtx (i0src
);
3171 subst_low_luid
= DF_INSN_LUID (i0
);
3172 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3176 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3177 to count all the ways that I2SRC and I1SRC can be used. */
3178 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3179 && i2_is_used
+ added_sets_2
> 1)
3180 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3181 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3183 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3184 && (n_occurrences
+ added_sets_0
3185 + (added_sets_1
&& i0_feeds_i1_n
)
3186 + (added_sets_2
&& i0_feeds_i2_n
)
3188 /* Fail if we tried to make a new register. */
3189 || max_reg_num () != maxreg
3190 /* Fail if we couldn't do something and have a CLOBBER. */
3191 || GET_CODE (newpat
) == CLOBBER
3192 /* Fail if this new pattern is a MULT and we didn't have one before
3193 at the outer level. */
3194 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3201 /* If the actions of the earlier insns must be kept
3202 in addition to substituting them into the latest one,
3203 we must make a new PARALLEL for the latest insn
3204 to hold additional the SETs. */
3206 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3208 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3211 if (GET_CODE (newpat
) == PARALLEL
)
3213 rtvec old
= XVEC (newpat
, 0);
3214 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3215 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3216 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3217 sizeof (old
->elem
[0]) * old
->num_elem
);
3222 total_sets
= 1 + extra_sets
;
3223 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3224 XVECEXP (newpat
, 0, 0) = old
;
3228 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3234 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3236 XVECEXP (newpat
, 0, --total_sets
) = t
;
3242 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3243 i0_feeds_i1_n
&& i0dest_in_i0src
);
3244 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3245 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3247 XVECEXP (newpat
, 0, --total_sets
) = t
;
3251 validate_replacement
:
3253 /* Note which hard regs this insn has as inputs. */
3254 mark_used_regs_combine (newpat
);
3256 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3257 consider splitting this pattern, we might need these clobbers. */
3258 if (i1
&& GET_CODE (newpat
) == PARALLEL
3259 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3261 int len
= XVECLEN (newpat
, 0);
3263 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3264 for (i
= 0; i
< len
; i
++)
3265 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3268 /* Is the result of combination a valid instruction? */
3269 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3271 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3272 the second SET's destination is a register that is unused and isn't
3273 marked as an instruction that might trap in an EH region. In that case,
3274 we just need the first SET. This can occur when simplifying a divmod
3275 insn. We *must* test for this case here because the code below that
3276 splits two independent SETs doesn't handle this case correctly when it
3277 updates the register status.
3279 It's pointless doing this if we originally had two sets, one from
3280 i3, and one from i2. Combining then splitting the parallel results
3281 in the original i2 again plus an invalid insn (which we delete).
3282 The net effect is only to move instructions around, which makes
3283 debug info less accurate.
3285 Also check the case where the first SET's destination is unused.
3286 That would not cause incorrect code, but does cause an unneeded
3289 if (insn_code_number
< 0
3290 && !(added_sets_2
&& i1
== 0)
3291 && GET_CODE (newpat
) == PARALLEL
3292 && XVECLEN (newpat
, 0) == 2
3293 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3294 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3295 && asm_noperands (newpat
) < 0)
3297 rtx set0
= XVECEXP (newpat
, 0, 0);
3298 rtx set1
= XVECEXP (newpat
, 0, 1);
3300 if (((REG_P (SET_DEST (set1
))
3301 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3302 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3303 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3304 && insn_nothrow_p (i3
)
3305 && !side_effects_p (SET_SRC (set1
)))
3308 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3311 else if (((REG_P (SET_DEST (set0
))
3312 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3313 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3314 && find_reg_note (i3
, REG_UNUSED
,
3315 SUBREG_REG (SET_DEST (set0
)))))
3316 && insn_nothrow_p (i3
)
3317 && !side_effects_p (SET_SRC (set0
)))
3320 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3322 if (insn_code_number
>= 0)
3323 changed_i3_dest
= 1;
3327 /* If we were combining three insns and the result is a simple SET
3328 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3329 insns. There are two ways to do this. It can be split using a
3330 machine-specific method (like when you have an addition of a large
3331 constant) or by combine in the function find_split_point. */
3333 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3334 && asm_noperands (newpat
) < 0)
3336 rtx parallel
, m_split
, *split
;
3338 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3339 use I2DEST as a scratch register will help. In the latter case,
3340 convert I2DEST to the mode of the source of NEWPAT if we can. */
3342 m_split
= combine_split_insns (newpat
, i3
);
3344 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3345 inputs of NEWPAT. */
3347 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3348 possible to try that as a scratch reg. This would require adding
3349 more code to make it work though. */
3351 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3353 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3355 /* First try to split using the original register as a
3356 scratch register. */
3357 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3358 gen_rtvec (2, newpat
,
3359 gen_rtx_CLOBBER (VOIDmode
,
3361 m_split
= combine_split_insns (parallel
, i3
);
3363 /* If that didn't work, try changing the mode of I2DEST if
3366 && new_mode
!= GET_MODE (i2dest
)
3367 && new_mode
!= VOIDmode
3368 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3370 enum machine_mode old_mode
= GET_MODE (i2dest
);
3373 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3374 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3377 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3378 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3381 parallel
= (gen_rtx_PARALLEL
3383 gen_rtvec (2, newpat
,
3384 gen_rtx_CLOBBER (VOIDmode
,
3386 m_split
= combine_split_insns (parallel
, i3
);
3389 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3393 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3394 buf
= undobuf
.undos
;
3395 undobuf
.undos
= buf
->next
;
3396 buf
->next
= undobuf
.frees
;
3397 undobuf
.frees
= buf
;
3401 i2scratch
= m_split
!= 0;
3404 /* If recog_for_combine has discarded clobbers, try to use them
3405 again for the split. */
3406 if (m_split
== 0 && newpat_vec_with_clobbers
)
3408 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3409 m_split
= combine_split_insns (parallel
, i3
);
3412 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3414 m_split
= PATTERN (m_split
);
3415 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3416 if (insn_code_number
>= 0)
3419 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3420 && (next_nonnote_nondebug_insn (i2
) == i3
3421 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3424 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3425 newi2pat
= PATTERN (m_split
);
3427 i3set
= single_set (NEXT_INSN (m_split
));
3428 i2set
= single_set (m_split
);
3430 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3432 /* If I2 or I3 has multiple SETs, we won't know how to track
3433 register status, so don't use these insns. If I2's destination
3434 is used between I2 and I3, we also can't use these insns. */
3436 if (i2_code_number
>= 0 && i2set
&& i3set
3437 && (next_nonnote_nondebug_insn (i2
) == i3
3438 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3439 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3441 if (insn_code_number
>= 0)
3444 /* It is possible that both insns now set the destination of I3.
3445 If so, we must show an extra use of it. */
3447 if (insn_code_number
>= 0)
3449 rtx new_i3_dest
= SET_DEST (i3set
);
3450 rtx new_i2_dest
= SET_DEST (i2set
);
3452 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3453 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3454 || GET_CODE (new_i3_dest
) == SUBREG
)
3455 new_i3_dest
= XEXP (new_i3_dest
, 0);
3457 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3458 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3459 || GET_CODE (new_i2_dest
) == SUBREG
)
3460 new_i2_dest
= XEXP (new_i2_dest
, 0);
3462 if (REG_P (new_i3_dest
)
3463 && REG_P (new_i2_dest
)
3464 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3465 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3469 /* If we can split it and use I2DEST, go ahead and see if that
3470 helps things be recognized. Verify that none of the registers
3471 are set between I2 and I3. */
3472 if (insn_code_number
< 0
3473 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3477 /* We need I2DEST in the proper mode. If it is a hard register
3478 or the only use of a pseudo, we can change its mode.
3479 Make sure we don't change a hard register to have a mode that
3480 isn't valid for it, or change the number of registers. */
3481 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3482 || GET_MODE (*split
) == VOIDmode
3483 || can_change_dest_mode (i2dest
, added_sets_2
,
3485 && (next_nonnote_nondebug_insn (i2
) == i3
3486 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3487 /* We can't overwrite I2DEST if its value is still used by
3489 && ! reg_referenced_p (i2dest
, newpat
))
3491 rtx newdest
= i2dest
;
3492 enum rtx_code split_code
= GET_CODE (*split
);
3493 enum machine_mode split_mode
= GET_MODE (*split
);
3494 bool subst_done
= false;
3495 newi2pat
= NULL_RTX
;
3499 /* *SPLIT may be part of I2SRC, so make sure we have the
3500 original expression around for later debug processing.
3501 We should not need I2SRC any more in other cases. */
3502 if (MAY_HAVE_DEBUG_INSNS
)
3503 i2src
= copy_rtx (i2src
);
3507 /* Get NEWDEST as a register in the proper mode. We have already
3508 validated that we can do this. */
3509 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3511 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3512 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3515 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3516 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3520 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3521 an ASHIFT. This can occur if it was inside a PLUS and hence
3522 appeared to be a memory address. This is a kludge. */
3523 if (split_code
== MULT
3524 && CONST_INT_P (XEXP (*split
, 1))
3525 && INTVAL (XEXP (*split
, 1)) > 0
3526 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3528 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3529 XEXP (*split
, 0), GEN_INT (i
)));
3530 /* Update split_code because we may not have a multiply
3532 split_code
= GET_CODE (*split
);
3535 #ifdef INSN_SCHEDULING
3536 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3537 be written as a ZERO_EXTEND. */
3538 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3540 #ifdef LOAD_EXTEND_OP
3541 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3542 what it really is. */
3543 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3545 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3546 SUBREG_REG (*split
)));
3549 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3550 SUBREG_REG (*split
)));
3554 /* Attempt to split binary operators using arithmetic identities. */
3555 if (BINARY_P (SET_SRC (newpat
))
3556 && split_mode
== GET_MODE (SET_SRC (newpat
))
3557 && ! side_effects_p (SET_SRC (newpat
)))
3559 rtx setsrc
= SET_SRC (newpat
);
3560 enum machine_mode mode
= GET_MODE (setsrc
);
3561 enum rtx_code code
= GET_CODE (setsrc
);
3562 rtx src_op0
= XEXP (setsrc
, 0);
3563 rtx src_op1
= XEXP (setsrc
, 1);
3565 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3566 if (rtx_equal_p (src_op0
, src_op1
))
3568 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3569 SUBST (XEXP (setsrc
, 0), newdest
);
3570 SUBST (XEXP (setsrc
, 1), newdest
);
3573 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3574 else if ((code
== PLUS
|| code
== MULT
)
3575 && GET_CODE (src_op0
) == code
3576 && GET_CODE (XEXP (src_op0
, 0)) == code
3577 && (INTEGRAL_MODE_P (mode
)
3578 || (FLOAT_MODE_P (mode
)
3579 && flag_unsafe_math_optimizations
)))
3581 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3582 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3583 rtx r
= XEXP (src_op0
, 1);
3586 /* Split both "((X op Y) op X) op Y" and
3587 "((X op Y) op Y) op X" as "T op T" where T is
3589 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3590 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3592 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3594 SUBST (XEXP (setsrc
, 0), newdest
);
3595 SUBST (XEXP (setsrc
, 1), newdest
);
3598 /* Split "((X op X) op Y) op Y)" as "T op T" where
3600 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3602 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3603 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3604 SUBST (XEXP (setsrc
, 0), newdest
);
3605 SUBST (XEXP (setsrc
, 1), newdest
);
3613 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3614 SUBST (*split
, newdest
);
3617 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3619 /* recog_for_combine might have added CLOBBERs to newi2pat.
3620 Make sure NEWPAT does not depend on the clobbered regs. */
3621 if (GET_CODE (newi2pat
) == PARALLEL
)
3622 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3623 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3625 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3626 if (reg_overlap_mentioned_p (reg
, newpat
))
3633 /* If the split point was a MULT and we didn't have one before,
3634 don't use one now. */
3635 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3636 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3640 /* Check for a case where we loaded from memory in a narrow mode and
3641 then sign extended it, but we need both registers. In that case,
3642 we have a PARALLEL with both loads from the same memory location.
3643 We can split this into a load from memory followed by a register-register
3644 copy. This saves at least one insn, more if register allocation can
3647 We cannot do this if the destination of the first assignment is a
3648 condition code register or cc0. We eliminate this case by making sure
3649 the SET_DEST and SET_SRC have the same mode.
3651 We cannot do this if the destination of the second assignment is
3652 a register that we have already assumed is zero-extended. Similarly
3653 for a SUBREG of such a register. */
3655 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3656 && GET_CODE (newpat
) == PARALLEL
3657 && XVECLEN (newpat
, 0) == 2
3658 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3659 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3660 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3661 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3662 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3663 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3664 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3665 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3667 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3668 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3669 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3671 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3672 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3673 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3674 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3675 != GET_MODE_MASK (word_mode
))))
3676 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3677 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3679 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3680 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3681 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3682 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3683 != GET_MODE_MASK (word_mode
)))))
3684 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3685 SET_SRC (XVECEXP (newpat
, 0, 1)))
3686 && ! find_reg_note (i3
, REG_UNUSED
,
3687 SET_DEST (XVECEXP (newpat
, 0, 0))))
3691 newi2pat
= XVECEXP (newpat
, 0, 0);
3692 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3693 newpat
= XVECEXP (newpat
, 0, 1);
3694 SUBST (SET_SRC (newpat
),
3695 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3696 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3698 if (i2_code_number
>= 0)
3699 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3701 if (insn_code_number
>= 0)
3705 /* Similarly, check for a case where we have a PARALLEL of two independent
3706 SETs but we started with three insns. In this case, we can do the sets
3707 as two separate insns. This case occurs when some SET allows two
3708 other insns to combine, but the destination of that SET is still live. */
3710 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3711 && GET_CODE (newpat
) == PARALLEL
3712 && XVECLEN (newpat
, 0) == 2
3713 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3714 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3715 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3716 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3717 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3718 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3719 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3720 XVECEXP (newpat
, 0, 0))
3721 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3722 XVECEXP (newpat
, 0, 1))
3723 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3724 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3726 rtx set0
= XVECEXP (newpat
, 0, 0);
3727 rtx set1
= XVECEXP (newpat
, 0, 1);
3729 /* Normally, it doesn't matter which of the two is done first,
3730 but the one that references cc0 can't be the second, and
3731 one which uses any regs/memory set in between i2 and i3 can't
3732 be first. The PARALLEL might also have been pre-existing in i3,
3733 so we need to make sure that we won't wrongly hoist a SET to i2
3734 that would conflict with a death note present in there. */
3735 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3736 && !(REG_P (SET_DEST (set1
))
3737 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3738 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3739 && find_reg_note (i2
, REG_DEAD
,
3740 SUBREG_REG (SET_DEST (set1
))))
3742 && !reg_referenced_p (cc0_rtx
, set0
)
3744 /* If I3 is a jump, ensure that set0 is a jump so that
3745 we do not create invalid RTL. */
3746 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3752 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3753 && !(REG_P (SET_DEST (set0
))
3754 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3755 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3756 && find_reg_note (i2
, REG_DEAD
,
3757 SUBREG_REG (SET_DEST (set0
))))
3759 && !reg_referenced_p (cc0_rtx
, set1
)
3761 /* If I3 is a jump, ensure that set1 is a jump so that
3762 we do not create invalid RTL. */
3763 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3775 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3777 if (i2_code_number
>= 0)
3779 /* recog_for_combine might have added CLOBBERs to newi2pat.
3780 Make sure NEWPAT does not depend on the clobbered regs. */
3781 if (GET_CODE (newi2pat
) == PARALLEL
)
3783 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3784 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3786 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3787 if (reg_overlap_mentioned_p (reg
, newpat
))
3795 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3799 /* If it still isn't recognized, fail and change things back the way they
3801 if ((insn_code_number
< 0
3802 /* Is the result a reasonable ASM_OPERANDS? */
3803 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3809 /* If we had to change another insn, make sure it is valid also. */
3810 if (undobuf
.other_insn
)
3812 CLEAR_HARD_REG_SET (newpat_used_regs
);
3814 other_pat
= PATTERN (undobuf
.other_insn
);
3815 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3818 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3826 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3827 they are adjacent to each other or not. */
3829 rtx_insn
*p
= prev_nonnote_insn (i3
);
3830 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3831 && sets_cc0_p (newi2pat
))
3839 /* Only allow this combination if insn_rtx_costs reports that the
3840 replacement instructions are cheaper than the originals. */
3841 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3847 if (MAY_HAVE_DEBUG_INSNS
)
3851 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3852 if (undo
->kind
== UNDO_MODE
)
3854 rtx reg
= *undo
->where
.r
;
3855 enum machine_mode new_mode
= GET_MODE (reg
);
3856 enum machine_mode old_mode
= undo
->old_contents
.m
;
3858 /* Temporarily revert mode back. */
3859 adjust_reg_mode (reg
, old_mode
);
3861 if (reg
== i2dest
&& i2scratch
)
3863 /* If we used i2dest as a scratch register with a
3864 different mode, substitute it for the original
3865 i2src while its original mode is temporarily
3866 restored, and then clear i2scratch so that we don't
3867 do it again later. */
3868 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3871 /* Put back the new mode. */
3872 adjust_reg_mode (reg
, new_mode
);
3876 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3877 rtx_insn
*first
, *last
;
3882 last
= last_combined_insn
;
3887 last
= undobuf
.other_insn
;
3889 if (DF_INSN_LUID (last
)
3890 < DF_INSN_LUID (last_combined_insn
))
3891 last
= last_combined_insn
;
3894 /* We're dealing with a reg that changed mode but not
3895 meaning, so we want to turn it into a subreg for
3896 the new mode. However, because of REG sharing and
3897 because its mode had already changed, we have to do
3898 it in two steps. First, replace any debug uses of
3899 reg, with its original mode temporarily restored,
3900 with this copy we have created; then, replace the
3901 copy with the SUBREG of the original shared reg,
3902 once again changed to the new mode. */
3903 propagate_for_debug (first
, last
, reg
, tempreg
,
3905 adjust_reg_mode (reg
, new_mode
);
3906 propagate_for_debug (first
, last
, tempreg
,
3907 lowpart_subreg (old_mode
, reg
, new_mode
),
3913 /* If we will be able to accept this, we have made a
3914 change to the destination of I3. This requires us to
3915 do a few adjustments. */
3917 if (changed_i3_dest
)
3919 PATTERN (i3
) = newpat
;
3920 adjust_for_new_dest (i3
);
3923 /* We now know that we can do this combination. Merge the insns and
3924 update the status of registers and LOG_LINKS. */
3926 if (undobuf
.other_insn
)
3930 PATTERN (undobuf
.other_insn
) = other_pat
;
3932 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3933 ensure that they are still valid. Then add any non-duplicate
3934 notes added by recog_for_combine. */
3935 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3937 next
= XEXP (note
, 1);
3939 if ((REG_NOTE_KIND (note
) == REG_DEAD
3940 && !reg_referenced_p (XEXP (note
, 0),
3941 PATTERN (undobuf
.other_insn
)))
3942 ||(REG_NOTE_KIND (note
) == REG_UNUSED
3943 && !reg_set_p (XEXP (note
, 0),
3944 PATTERN (undobuf
.other_insn
))))
3945 remove_note (undobuf
.other_insn
, note
);
3948 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3949 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
3956 struct insn_link
*link
;
3959 /* I3 now uses what used to be its destination and which is now
3960 I2's destination. This requires us to do a few adjustments. */
3961 PATTERN (i3
) = newpat
;
3962 adjust_for_new_dest (i3
);
3964 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3967 However, some later insn might be using I2's dest and have
3968 a LOG_LINK pointing at I3. We must remove this link.
3969 The simplest way to remove the link is to point it at I1,
3970 which we know will be a NOTE. */
3972 /* newi2pat is usually a SET here; however, recog_for_combine might
3973 have added some clobbers. */
3974 if (GET_CODE (newi2pat
) == PARALLEL
)
3975 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3977 ni2dest
= SET_DEST (newi2pat
);
3979 for (insn
= NEXT_INSN (i3
);
3980 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
3981 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3982 insn
= NEXT_INSN (insn
))
3984 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3986 FOR_EACH_LOG_LINK (link
, insn
)
3987 if (link
->insn
== i3
)
3996 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3997 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4000 /* Compute which registers we expect to eliminate. newi2pat may be setting
4001 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4002 same as i3dest, in which case newi2pat may be setting i1dest. */
4003 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4004 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4007 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4008 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4011 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
4012 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4016 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4018 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4019 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4021 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4023 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4025 /* Ensure that we do not have something that should not be shared but
4026 occurs multiple times in the new insns. Check this by first
4027 resetting all the `used' flags and then copying anything is shared. */
4029 reset_used_flags (i3notes
);
4030 reset_used_flags (i2notes
);
4031 reset_used_flags (i1notes
);
4032 reset_used_flags (i0notes
);
4033 reset_used_flags (newpat
);
4034 reset_used_flags (newi2pat
);
4035 if (undobuf
.other_insn
)
4036 reset_used_flags (PATTERN (undobuf
.other_insn
));
4038 i3notes
= copy_rtx_if_shared (i3notes
);
4039 i2notes
= copy_rtx_if_shared (i2notes
);
4040 i1notes
= copy_rtx_if_shared (i1notes
);
4041 i0notes
= copy_rtx_if_shared (i0notes
);
4042 newpat
= copy_rtx_if_shared (newpat
);
4043 newi2pat
= copy_rtx_if_shared (newi2pat
);
4044 if (undobuf
.other_insn
)
4045 reset_used_flags (PATTERN (undobuf
.other_insn
));
4047 INSN_CODE (i3
) = insn_code_number
;
4048 PATTERN (i3
) = newpat
;
4050 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4052 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4054 reset_used_flags (call_usage
);
4055 call_usage
= copy_rtx (call_usage
);
4059 /* I2SRC must still be meaningful at this point. Some splitting
4060 operations can invalidate I2SRC, but those operations do not
4063 replace_rtx (call_usage
, i2dest
, i2src
);
4067 replace_rtx (call_usage
, i1dest
, i1src
);
4069 replace_rtx (call_usage
, i0dest
, i0src
);
4071 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4074 if (undobuf
.other_insn
)
4075 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4077 /* We had one special case above where I2 had more than one set and
4078 we replaced a destination of one of those sets with the destination
4079 of I3. In that case, we have to update LOG_LINKS of insns later
4080 in this basic block. Note that this (expensive) case is rare.
4082 Also, in this case, we must pretend that all REG_NOTEs for I2
4083 actually came from I3, so that REG_UNUSED notes from I2 will be
4084 properly handled. */
4086 if (i3_subst_into_i2
)
4088 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4089 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4090 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4091 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4092 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4093 && ! find_reg_note (i2
, REG_UNUSED
,
4094 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4095 for (temp_insn
= NEXT_INSN (i2
);
4097 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4098 || BB_HEAD (this_basic_block
) != temp_insn
);
4099 temp_insn
= NEXT_INSN (temp_insn
))
4100 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4101 FOR_EACH_LOG_LINK (link
, temp_insn
)
4102 if (link
->insn
== i2
)
4108 while (XEXP (link
, 1))
4109 link
= XEXP (link
, 1);
4110 XEXP (link
, 1) = i2notes
;
4117 LOG_LINKS (i3
) = NULL
;
4119 LOG_LINKS (i2
) = NULL
;
4124 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4125 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4127 INSN_CODE (i2
) = i2_code_number
;
4128 PATTERN (i2
) = newi2pat
;
4132 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4133 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4135 SET_INSN_DELETED (i2
);
4140 LOG_LINKS (i1
) = NULL
;
4142 if (MAY_HAVE_DEBUG_INSNS
)
4143 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4145 SET_INSN_DELETED (i1
);
4150 LOG_LINKS (i0
) = NULL
;
4152 if (MAY_HAVE_DEBUG_INSNS
)
4153 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4155 SET_INSN_DELETED (i0
);
4158 /* Get death notes for everything that is now used in either I3 or
4159 I2 and used to die in a previous insn. If we built two new
4160 patterns, move from I1 to I2 then I2 to I3 so that we get the
4161 proper movement on registers that I2 modifies. */
4164 from_luid
= DF_INSN_LUID (i0
);
4166 from_luid
= DF_INSN_LUID (i1
);
4168 from_luid
= DF_INSN_LUID (i2
);
4170 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4171 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4173 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4175 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4176 elim_i2
, elim_i1
, elim_i0
);
4178 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4179 elim_i2
, elim_i1
, elim_i0
);
4181 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4182 elim_i2
, elim_i1
, elim_i0
);
4184 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4185 elim_i2
, elim_i1
, elim_i0
);
4187 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4188 elim_i2
, elim_i1
, elim_i0
);
4190 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4191 know these are REG_UNUSED and want them to go to the desired insn,
4192 so we always pass it as i3. */
4194 if (newi2pat
&& new_i2_notes
)
4195 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4199 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4202 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4203 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4204 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4205 in that case, it might delete I2. Similarly for I2 and I1.
4206 Show an additional death due to the REG_DEAD note we make here. If
4207 we discard it in distribute_notes, we will decrement it again. */
4211 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4212 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4213 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4216 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4217 elim_i2
, elim_i1
, elim_i0
);
4220 if (i2dest_in_i2src
)
4222 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4223 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4224 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4225 NULL_RTX
, NULL_RTX
);
4227 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4228 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4231 if (i1dest_in_i1src
)
4233 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4234 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4235 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4236 NULL_RTX
, NULL_RTX
);
4238 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4239 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4242 if (i0dest_in_i0src
)
4244 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4245 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4246 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4247 NULL_RTX
, NULL_RTX
);
4249 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4250 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4253 distribute_links (i3links
);
4254 distribute_links (i2links
);
4255 distribute_links (i1links
);
4256 distribute_links (i0links
);
4260 struct insn_link
*link
;
4261 rtx_insn
*i2_insn
= 0;
4262 rtx i2_val
= 0, set
;
4264 /* The insn that used to set this register doesn't exist, and
4265 this life of the register may not exist either. See if one of
4266 I3's links points to an insn that sets I2DEST. If it does,
4267 that is now the last known value for I2DEST. If we don't update
4268 this and I2 set the register to a value that depended on its old
4269 contents, we will get confused. If this insn is used, thing
4270 will be set correctly in combine_instructions. */
4271 FOR_EACH_LOG_LINK (link
, i3
)
4272 if ((set
= single_set (link
->insn
)) != 0
4273 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4274 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4276 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4278 /* If the reg formerly set in I2 died only once and that was in I3,
4279 zero its use count so it won't make `reload' do any work. */
4281 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4282 && ! i2dest_in_i2src
)
4283 INC_REG_N_SETS (REGNO (i2dest
), -1);
4286 if (i1
&& REG_P (i1dest
))
4288 struct insn_link
*link
;
4289 rtx_insn
*i1_insn
= 0;
4290 rtx i1_val
= 0, set
;
4292 FOR_EACH_LOG_LINK (link
, i3
)
4293 if ((set
= single_set (link
->insn
)) != 0
4294 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4295 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4297 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4299 if (! added_sets_1
&& ! i1dest_in_i1src
)
4300 INC_REG_N_SETS (REGNO (i1dest
), -1);
4303 if (i0
&& REG_P (i0dest
))
4305 struct insn_link
*link
;
4306 rtx_insn
*i0_insn
= 0;
4307 rtx i0_val
= 0, set
;
4309 FOR_EACH_LOG_LINK (link
, i3
)
4310 if ((set
= single_set (link
->insn
)) != 0
4311 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4312 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4314 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4316 if (! added_sets_0
&& ! i0dest_in_i0src
)
4317 INC_REG_N_SETS (REGNO (i0dest
), -1);
4320 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4321 been made to this insn. The order is important, because newi2pat
4322 can affect nonzero_bits of newpat. */
4324 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4325 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4328 if (undobuf
.other_insn
!= NULL_RTX
)
4332 fprintf (dump_file
, "modifying other_insn ");
4333 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4335 df_insn_rescan (undobuf
.other_insn
);
4338 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4342 fprintf (dump_file
, "modifying insn i0 ");
4343 dump_insn_slim (dump_file
, i0
);
4345 df_insn_rescan (i0
);
4348 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4352 fprintf (dump_file
, "modifying insn i1 ");
4353 dump_insn_slim (dump_file
, i1
);
4355 df_insn_rescan (i1
);
4358 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4362 fprintf (dump_file
, "modifying insn i2 ");
4363 dump_insn_slim (dump_file
, i2
);
4365 df_insn_rescan (i2
);
4368 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4372 fprintf (dump_file
, "modifying insn i3 ");
4373 dump_insn_slim (dump_file
, i3
);
4375 df_insn_rescan (i3
);
4378 /* Set new_direct_jump_p if a new return or simple jump instruction
4379 has been created. Adjust the CFG accordingly. */
4380 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4382 *new_direct_jump_p
= 1;
4383 mark_jump_label (PATTERN (i3
), i3
, 0);
4384 update_cfg_for_uncondjump (i3
);
4387 if (undobuf
.other_insn
!= NULL_RTX
4388 && (returnjump_p (undobuf
.other_insn
)
4389 || any_uncondjump_p (undobuf
.other_insn
)))
4391 *new_direct_jump_p
= 1;
4392 update_cfg_for_uncondjump (undobuf
.other_insn
);
4395 /* A noop might also need cleaning up of CFG, if it comes from the
4396 simplification of a jump. */
4398 && GET_CODE (newpat
) == SET
4399 && SET_SRC (newpat
) == pc_rtx
4400 && SET_DEST (newpat
) == pc_rtx
)
4402 *new_direct_jump_p
= 1;
4403 update_cfg_for_uncondjump (i3
);
4406 if (undobuf
.other_insn
!= NULL_RTX
4407 && JUMP_P (undobuf
.other_insn
)
4408 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4409 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4410 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4412 *new_direct_jump_p
= 1;
4413 update_cfg_for_uncondjump (undobuf
.other_insn
);
4416 combine_successes
++;
4419 if (added_links_insn
4420 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4421 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4422 return added_links_insn
;
4424 return newi2pat
? i2
: i3
;
4427 /* Undo all the modifications recorded in undobuf. */
4432 struct undo
*undo
, *next
;
4434 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4440 *undo
->where
.r
= undo
->old_contents
.r
;
4443 *undo
->where
.i
= undo
->old_contents
.i
;
4446 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4449 *undo
->where
.l
= undo
->old_contents
.l
;
4455 undo
->next
= undobuf
.frees
;
4456 undobuf
.frees
= undo
;
4462 /* We've committed to accepting the changes we made. Move all
4463 of the undos to the free list. */
4468 struct undo
*undo
, *next
;
4470 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4473 undo
->next
= undobuf
.frees
;
4474 undobuf
.frees
= undo
;
4479 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4480 where we have an arithmetic expression and return that point. LOC will
4483 try_combine will call this function to see if an insn can be split into
4487 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4490 enum rtx_code code
= GET_CODE (x
);
4492 unsigned HOST_WIDE_INT len
= 0;
4493 HOST_WIDE_INT pos
= 0;
4495 rtx inner
= NULL_RTX
;
4497 /* First special-case some codes. */
4501 #ifdef INSN_SCHEDULING
4502 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4504 if (MEM_P (SUBREG_REG (x
)))
4507 return find_split_point (&SUBREG_REG (x
), insn
, false);
4511 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4512 using LO_SUM and HIGH. */
4513 if (GET_CODE (XEXP (x
, 0)) == CONST
4514 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4516 enum machine_mode address_mode
= get_address_mode (x
);
4519 gen_rtx_LO_SUM (address_mode
,
4520 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4522 return &XEXP (XEXP (x
, 0), 0);
4526 /* If we have a PLUS whose second operand is a constant and the
4527 address is not valid, perhaps will can split it up using
4528 the machine-specific way to split large constants. We use
4529 the first pseudo-reg (one of the virtual regs) as a placeholder;
4530 it will not remain in the result. */
4531 if (GET_CODE (XEXP (x
, 0)) == PLUS
4532 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4533 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4534 MEM_ADDR_SPACE (x
)))
4536 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4537 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4541 /* This should have produced two insns, each of which sets our
4542 placeholder. If the source of the second is a valid address,
4543 we can make put both sources together and make a split point
4547 && NEXT_INSN (seq
) != NULL_RTX
4548 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4549 && NONJUMP_INSN_P (seq
)
4550 && GET_CODE (PATTERN (seq
)) == SET
4551 && SET_DEST (PATTERN (seq
)) == reg
4552 && ! reg_mentioned_p (reg
,
4553 SET_SRC (PATTERN (seq
)))
4554 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4555 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4556 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4557 && memory_address_addr_space_p
4558 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4559 MEM_ADDR_SPACE (x
)))
4561 rtx src1
= SET_SRC (PATTERN (seq
));
4562 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4564 /* Replace the placeholder in SRC2 with SRC1. If we can
4565 find where in SRC2 it was placed, that can become our
4566 split point and we can replace this address with SRC2.
4567 Just try two obvious places. */
4569 src2
= replace_rtx (src2
, reg
, src1
);
4571 if (XEXP (src2
, 0) == src1
)
4572 split
= &XEXP (src2
, 0);
4573 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4574 && XEXP (XEXP (src2
, 0), 0) == src1
)
4575 split
= &XEXP (XEXP (src2
, 0), 0);
4579 SUBST (XEXP (x
, 0), src2
);
4584 /* If that didn't work, perhaps the first operand is complex and
4585 needs to be computed separately, so make a split point there.
4586 This will occur on machines that just support REG + CONST
4587 and have a constant moved through some previous computation. */
4589 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4590 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4591 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4592 return &XEXP (XEXP (x
, 0), 0);
4595 /* If we have a PLUS whose first operand is complex, try computing it
4596 separately by making a split there. */
4597 if (GET_CODE (XEXP (x
, 0)) == PLUS
4598 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4600 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4601 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4602 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4603 return &XEXP (XEXP (x
, 0), 0);
4608 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4609 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4610 we need to put the operand into a register. So split at that
4613 if (SET_DEST (x
) == cc0_rtx
4614 && GET_CODE (SET_SRC (x
)) != COMPARE
4615 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4616 && !OBJECT_P (SET_SRC (x
))
4617 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4618 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4619 return &SET_SRC (x
);
4622 /* See if we can split SET_SRC as it stands. */
4623 split
= find_split_point (&SET_SRC (x
), insn
, true);
4624 if (split
&& split
!= &SET_SRC (x
))
4627 /* See if we can split SET_DEST as it stands. */
4628 split
= find_split_point (&SET_DEST (x
), insn
, false);
4629 if (split
&& split
!= &SET_DEST (x
))
4632 /* See if this is a bitfield assignment with everything constant. If
4633 so, this is an IOR of an AND, so split it into that. */
4634 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4635 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4636 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4637 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4638 && CONST_INT_P (SET_SRC (x
))
4639 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4640 + INTVAL (XEXP (SET_DEST (x
), 2)))
4641 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4642 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4644 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4645 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4646 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4647 rtx dest
= XEXP (SET_DEST (x
), 0);
4648 enum machine_mode mode
= GET_MODE (dest
);
4649 unsigned HOST_WIDE_INT mask
4650 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4653 if (BITS_BIG_ENDIAN
)
4654 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4656 or_mask
= gen_int_mode (src
<< pos
, mode
);
4659 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4662 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4664 simplify_gen_binary (IOR
, mode
,
4665 simplify_gen_binary (AND
, mode
,
4670 SUBST (SET_DEST (x
), dest
);
4672 split
= find_split_point (&SET_SRC (x
), insn
, true);
4673 if (split
&& split
!= &SET_SRC (x
))
4677 /* Otherwise, see if this is an operation that we can split into two.
4678 If so, try to split that. */
4679 code
= GET_CODE (SET_SRC (x
));
4684 /* If we are AND'ing with a large constant that is only a single
4685 bit and the result is only being used in a context where we
4686 need to know if it is zero or nonzero, replace it with a bit
4687 extraction. This will avoid the large constant, which might
4688 have taken more than one insn to make. If the constant were
4689 not a valid argument to the AND but took only one insn to make,
4690 this is no worse, but if it took more than one insn, it will
4693 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4694 && REG_P (XEXP (SET_SRC (x
), 0))
4695 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4696 && REG_P (SET_DEST (x
))
4697 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4698 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4699 && XEXP (*split
, 0) == SET_DEST (x
)
4700 && XEXP (*split
, 1) == const0_rtx
)
4702 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4703 XEXP (SET_SRC (x
), 0),
4704 pos
, NULL_RTX
, 1, 1, 0, 0);
4705 if (extraction
!= 0)
4707 SUBST (SET_SRC (x
), extraction
);
4708 return find_split_point (loc
, insn
, false);
4714 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4715 is known to be on, this can be converted into a NEG of a shift. */
4716 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4717 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4718 && 1 <= (pos
= exact_log2
4719 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4720 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4722 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4726 gen_rtx_LSHIFTRT (mode
,
4727 XEXP (SET_SRC (x
), 0),
4730 split
= find_split_point (&SET_SRC (x
), insn
, true);
4731 if (split
&& split
!= &SET_SRC (x
))
4737 inner
= XEXP (SET_SRC (x
), 0);
4739 /* We can't optimize if either mode is a partial integer
4740 mode as we don't know how many bits are significant
4742 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4743 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4747 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4753 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4754 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4756 inner
= XEXP (SET_SRC (x
), 0);
4757 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4758 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4760 if (BITS_BIG_ENDIAN
)
4761 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4762 unsignedp
= (code
== ZERO_EXTRACT
);
4771 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4773 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4775 /* For unsigned, we have a choice of a shift followed by an
4776 AND or two shifts. Use two shifts for field sizes where the
4777 constant might be too large. We assume here that we can
4778 always at least get 8-bit constants in an AND insn, which is
4779 true for every current RISC. */
4781 if (unsignedp
&& len
<= 8)
4783 unsigned HOST_WIDE_INT mask
4784 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4788 (mode
, gen_lowpart (mode
, inner
),
4790 gen_int_mode (mask
, mode
)));
4792 split
= find_split_point (&SET_SRC (x
), insn
, true);
4793 if (split
&& split
!= &SET_SRC (x
))
4800 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4801 gen_rtx_ASHIFT (mode
,
4802 gen_lowpart (mode
, inner
),
4803 GEN_INT (GET_MODE_PRECISION (mode
)
4805 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4807 split
= find_split_point (&SET_SRC (x
), insn
, true);
4808 if (split
&& split
!= &SET_SRC (x
))
4813 /* See if this is a simple operation with a constant as the second
4814 operand. It might be that this constant is out of range and hence
4815 could be used as a split point. */
4816 if (BINARY_P (SET_SRC (x
))
4817 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4818 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4819 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4820 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4821 return &XEXP (SET_SRC (x
), 1);
4823 /* Finally, see if this is a simple operation with its first operand
4824 not in a register. The operation might require this operand in a
4825 register, so return it as a split point. We can always do this
4826 because if the first operand were another operation, we would have
4827 already found it as a split point. */
4828 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4829 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4830 return &XEXP (SET_SRC (x
), 0);
4836 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4837 it is better to write this as (not (ior A B)) so we can split it.
4838 Similarly for IOR. */
4839 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4842 gen_rtx_NOT (GET_MODE (x
),
4843 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4845 XEXP (XEXP (x
, 0), 0),
4846 XEXP (XEXP (x
, 1), 0))));
4847 return find_split_point (loc
, insn
, set_src
);
4850 /* Many RISC machines have a large set of logical insns. If the
4851 second operand is a NOT, put it first so we will try to split the
4852 other operand first. */
4853 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4855 rtx tem
= XEXP (x
, 0);
4856 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4857 SUBST (XEXP (x
, 1), tem
);
4863 /* Canonicalization can produce (minus A (mult B C)), where C is a
4864 constant. It may be better to try splitting (plus (mult B -C) A)
4865 instead if this isn't a multiply by a power of two. */
4866 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4867 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4868 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4870 enum machine_mode mode
= GET_MODE (x
);
4871 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4872 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4873 SUBST (*loc
, gen_rtx_PLUS (mode
,
4875 XEXP (XEXP (x
, 1), 0),
4876 gen_int_mode (other_int
,
4879 return find_split_point (loc
, insn
, set_src
);
4882 /* Split at a multiply-accumulate instruction. However if this is
4883 the SET_SRC, we likely do not have such an instruction and it's
4884 worthless to try this split. */
4885 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4892 /* Otherwise, select our actions depending on our rtx class. */
4893 switch (GET_RTX_CLASS (code
))
4895 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4897 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4900 /* ... fall through ... */
4902 case RTX_COMM_ARITH
:
4904 case RTX_COMM_COMPARE
:
4905 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4908 /* ... fall through ... */
4910 /* Some machines have (and (shift ...) ...) insns. If X is not
4911 an AND, but XEXP (X, 0) is, use it as our split point. */
4912 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4913 return &XEXP (x
, 0);
4915 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4921 /* Otherwise, we don't have a split point. */
4926 /* Throughout X, replace FROM with TO, and return the result.
4927 The result is TO if X is FROM;
4928 otherwise the result is X, but its contents may have been modified.
4929 If they were modified, a record was made in undobuf so that
4930 undo_all will (among other things) return X to its original state.
4932 If the number of changes necessary is too much to record to undo,
4933 the excess changes are not made, so the result is invalid.
4934 The changes already made can still be undone.
4935 undobuf.num_undo is incremented for such changes, so by testing that
4936 the caller can tell whether the result is valid.
4938 `n_occurrences' is incremented each time FROM is replaced.
4940 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4942 IN_COND is nonzero if we are at the top level of a condition.
4944 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4945 by copying if `n_occurrences' is nonzero. */
4948 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4950 enum rtx_code code
= GET_CODE (x
);
4951 enum machine_mode op0_mode
= VOIDmode
;
4956 /* Two expressions are equal if they are identical copies of a shared
4957 RTX or if they are both registers with the same register number
4960 #define COMBINE_RTX_EQUAL_P(X,Y) \
4962 || (REG_P (X) && REG_P (Y) \
4963 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4965 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4968 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4971 /* If X and FROM are the same register but different modes, they
4972 will not have been seen as equal above. However, the log links code
4973 will make a LOG_LINKS entry for that case. If we do nothing, we
4974 will try to rerecognize our original insn and, when it succeeds,
4975 we will delete the feeding insn, which is incorrect.
4977 So force this insn not to match in this (rare) case. */
4978 if (! in_dest
&& code
== REG
&& REG_P (from
)
4979 && reg_overlap_mentioned_p (x
, from
))
4980 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4982 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4983 of which may contain things that can be combined. */
4984 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4987 /* It is possible to have a subexpression appear twice in the insn.
4988 Suppose that FROM is a register that appears within TO.
4989 Then, after that subexpression has been scanned once by `subst',
4990 the second time it is scanned, TO may be found. If we were
4991 to scan TO here, we would find FROM within it and create a
4992 self-referent rtl structure which is completely wrong. */
4993 if (COMBINE_RTX_EQUAL_P (x
, to
))
4996 /* Parallel asm_operands need special attention because all of the
4997 inputs are shared across the arms. Furthermore, unsharing the
4998 rtl results in recognition failures. Failure to handle this case
4999 specially can result in circular rtl.
5001 Solve this by doing a normal pass across the first entry of the
5002 parallel, and only processing the SET_DESTs of the subsequent
5005 if (code
== PARALLEL
5006 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5007 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5009 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5011 /* If this substitution failed, this whole thing fails. */
5012 if (GET_CODE (new_rtx
) == CLOBBER
5013 && XEXP (new_rtx
, 0) == const0_rtx
)
5016 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5018 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5020 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5023 && GET_CODE (dest
) != CC0
5024 && GET_CODE (dest
) != PC
)
5026 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5028 /* If this substitution failed, this whole thing fails. */
5029 if (GET_CODE (new_rtx
) == CLOBBER
5030 && XEXP (new_rtx
, 0) == const0_rtx
)
5033 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5039 len
= GET_RTX_LENGTH (code
);
5040 fmt
= GET_RTX_FORMAT (code
);
5042 /* We don't need to process a SET_DEST that is a register, CC0,
5043 or PC, so set up to skip this common case. All other cases
5044 where we want to suppress replacing something inside a
5045 SET_SRC are handled via the IN_DEST operand. */
5047 && (REG_P (SET_DEST (x
))
5048 || GET_CODE (SET_DEST (x
)) == CC0
5049 || GET_CODE (SET_DEST (x
)) == PC
))
5052 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5055 op0_mode
= GET_MODE (XEXP (x
, 0));
5057 for (i
= 0; i
< len
; i
++)
5062 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5064 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5066 new_rtx
= (unique_copy
&& n_occurrences
5067 ? copy_rtx (to
) : to
);
5072 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5075 /* If this substitution failed, this whole thing
5077 if (GET_CODE (new_rtx
) == CLOBBER
5078 && XEXP (new_rtx
, 0) == const0_rtx
)
5082 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5085 else if (fmt
[i
] == 'e')
5087 /* If this is a register being set, ignore it. */
5088 new_rtx
= XEXP (x
, i
);
5091 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5093 || code
== STRICT_LOW_PART
))
5096 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5098 /* In general, don't install a subreg involving two
5099 modes not tieable. It can worsen register
5100 allocation, and can even make invalid reload
5101 insns, since the reg inside may need to be copied
5102 from in the outside mode, and that may be invalid
5103 if it is an fp reg copied in integer mode.
5105 We allow two exceptions to this: It is valid if
5106 it is inside another SUBREG and the mode of that
5107 SUBREG and the mode of the inside of TO is
5108 tieable and it is valid if X is a SET that copies
5111 if (GET_CODE (to
) == SUBREG
5112 && ! MODES_TIEABLE_P (GET_MODE (to
),
5113 GET_MODE (SUBREG_REG (to
)))
5114 && ! (code
== SUBREG
5115 && MODES_TIEABLE_P (GET_MODE (x
),
5116 GET_MODE (SUBREG_REG (to
))))
5118 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5121 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5123 #ifdef CANNOT_CHANGE_MODE_CLASS
5126 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5127 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5130 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5133 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5137 /* If we are in a SET_DEST, suppress most cases unless we
5138 have gone inside a MEM, in which case we want to
5139 simplify the address. We assume here that things that
5140 are actually part of the destination have their inner
5141 parts in the first expression. This is true for SUBREG,
5142 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5143 things aside from REG and MEM that should appear in a
5145 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5147 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5148 || code
== ZERO_EXTRACT
))
5151 code
== IF_THEN_ELSE
&& i
== 0,
5154 /* If we found that we will have to reject this combination,
5155 indicate that by returning the CLOBBER ourselves, rather than
5156 an expression containing it. This will speed things up as
5157 well as prevent accidents where two CLOBBERs are considered
5158 to be equal, thus producing an incorrect simplification. */
5160 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5163 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5165 enum machine_mode mode
= GET_MODE (x
);
5167 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5168 GET_MODE (SUBREG_REG (x
)),
5171 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5173 else if (CONST_SCALAR_INT_P (new_rtx
)
5174 && GET_CODE (x
) == ZERO_EXTEND
)
5176 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5177 new_rtx
, GET_MODE (XEXP (x
, 0)));
5181 SUBST (XEXP (x
, i
), new_rtx
);
5186 /* Check if we are loading something from the constant pool via float
5187 extension; in this case we would undo compress_float_constant
5188 optimization and degenerate constant load to an immediate value. */
5189 if (GET_CODE (x
) == FLOAT_EXTEND
5190 && MEM_P (XEXP (x
, 0))
5191 && MEM_READONLY_P (XEXP (x
, 0)))
5193 rtx tmp
= avoid_constant_pool_reference (x
);
5198 /* Try to simplify X. If the simplification changed the code, it is likely
5199 that further simplification will help, so loop, but limit the number
5200 of repetitions that will be performed. */
5202 for (i
= 0; i
< 4; i
++)
5204 /* If X is sufficiently simple, don't bother trying to do anything
5206 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5207 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5209 if (GET_CODE (x
) == code
)
5212 code
= GET_CODE (x
);
5214 /* We no longer know the original mode of operand 0 since we
5215 have changed the form of X) */
5216 op0_mode
= VOIDmode
;
5222 /* Simplify X, a piece of RTL. We just operate on the expression at the
5223 outer level; call `subst' to simplify recursively. Return the new
5226 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5227 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5231 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5234 enum rtx_code code
= GET_CODE (x
);
5235 enum machine_mode mode
= GET_MODE (x
);
5239 /* If this is a commutative operation, put a constant last and a complex
5240 expression first. We don't need to do this for comparisons here. */
5241 if (COMMUTATIVE_ARITH_P (x
)
5242 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5245 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5246 SUBST (XEXP (x
, 1), temp
);
5249 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5250 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5251 things. Check for cases where both arms are testing the same
5254 Don't do anything if all operands are very simple. */
5257 && ((!OBJECT_P (XEXP (x
, 0))
5258 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5259 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5260 || (!OBJECT_P (XEXP (x
, 1))
5261 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5262 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5264 && (!OBJECT_P (XEXP (x
, 0))
5265 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5266 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5268 rtx cond
, true_rtx
, false_rtx
;
5270 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5272 /* If everything is a comparison, what we have is highly unlikely
5273 to be simpler, so don't use it. */
5274 && ! (COMPARISON_P (x
)
5275 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5277 rtx cop1
= const0_rtx
;
5278 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5280 if (cond_code
== NE
&& COMPARISON_P (cond
))
5283 /* Simplify the alternative arms; this may collapse the true and
5284 false arms to store-flag values. Be careful to use copy_rtx
5285 here since true_rtx or false_rtx might share RTL with x as a
5286 result of the if_then_else_cond call above. */
5287 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5288 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5290 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5291 is unlikely to be simpler. */
5292 if (general_operand (true_rtx
, VOIDmode
)
5293 && general_operand (false_rtx
, VOIDmode
))
5295 enum rtx_code reversed
;
5297 /* Restarting if we generate a store-flag expression will cause
5298 us to loop. Just drop through in this case. */
5300 /* If the result values are STORE_FLAG_VALUE and zero, we can
5301 just make the comparison operation. */
5302 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5303 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5305 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5306 && ((reversed
= reversed_comparison_code_parts
5307 (cond_code
, cond
, cop1
, NULL
))
5309 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5312 /* Likewise, we can make the negate of a comparison operation
5313 if the result values are - STORE_FLAG_VALUE and zero. */
5314 else if (CONST_INT_P (true_rtx
)
5315 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5316 && false_rtx
== const0_rtx
)
5317 x
= simplify_gen_unary (NEG
, mode
,
5318 simplify_gen_relational (cond_code
,
5322 else if (CONST_INT_P (false_rtx
)
5323 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5324 && true_rtx
== const0_rtx
5325 && ((reversed
= reversed_comparison_code_parts
5326 (cond_code
, cond
, cop1
, NULL
))
5328 x
= simplify_gen_unary (NEG
, mode
,
5329 simplify_gen_relational (reversed
,
5334 return gen_rtx_IF_THEN_ELSE (mode
,
5335 simplify_gen_relational (cond_code
,
5340 true_rtx
, false_rtx
);
5342 code
= GET_CODE (x
);
5343 op0_mode
= VOIDmode
;
5348 /* Try to fold this expression in case we have constants that weren't
5351 switch (GET_RTX_CLASS (code
))
5354 if (op0_mode
== VOIDmode
)
5355 op0_mode
= GET_MODE (XEXP (x
, 0));
5356 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5359 case RTX_COMM_COMPARE
:
5361 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5362 if (cmp_mode
== VOIDmode
)
5364 cmp_mode
= GET_MODE (XEXP (x
, 1));
5365 if (cmp_mode
== VOIDmode
)
5366 cmp_mode
= op0_mode
;
5368 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5369 XEXP (x
, 0), XEXP (x
, 1));
5372 case RTX_COMM_ARITH
:
5374 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5376 case RTX_BITFIELD_OPS
:
5378 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5379 XEXP (x
, 1), XEXP (x
, 2));
5388 code
= GET_CODE (temp
);
5389 op0_mode
= VOIDmode
;
5390 mode
= GET_MODE (temp
);
5393 /* First see if we can apply the inverse distributive law. */
5394 if (code
== PLUS
|| code
== MINUS
5395 || code
== AND
|| code
== IOR
|| code
== XOR
)
5397 x
= apply_distributive_law (x
);
5398 code
= GET_CODE (x
);
5399 op0_mode
= VOIDmode
;
5402 /* If CODE is an associative operation not otherwise handled, see if we
5403 can associate some operands. This can win if they are constants or
5404 if they are logically related (i.e. (a & b) & a). */
5405 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5406 || code
== AND
|| code
== IOR
|| code
== XOR
5407 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5408 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5409 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5411 if (GET_CODE (XEXP (x
, 0)) == code
)
5413 rtx other
= XEXP (XEXP (x
, 0), 0);
5414 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5415 rtx inner_op1
= XEXP (x
, 1);
5418 /* Make sure we pass the constant operand if any as the second
5419 one if this is a commutative operation. */
5420 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5422 rtx tem
= inner_op0
;
5423 inner_op0
= inner_op1
;
5426 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5427 : code
== DIV
? MULT
5429 mode
, inner_op0
, inner_op1
);
5431 /* For commutative operations, try the other pair if that one
5433 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5435 other
= XEXP (XEXP (x
, 0), 1);
5436 inner
= simplify_binary_operation (code
, mode
,
5437 XEXP (XEXP (x
, 0), 0),
5442 return simplify_gen_binary (code
, mode
, other
, inner
);
5446 /* A little bit of algebraic simplification here. */
5450 /* Ensure that our address has any ASHIFTs converted to MULT in case
5451 address-recognizing predicates are called later. */
5452 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5453 SUBST (XEXP (x
, 0), temp
);
5457 if (op0_mode
== VOIDmode
)
5458 op0_mode
= GET_MODE (SUBREG_REG (x
));
5460 /* See if this can be moved to simplify_subreg. */
5461 if (CONSTANT_P (SUBREG_REG (x
))
5462 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5463 /* Don't call gen_lowpart if the inner mode
5464 is VOIDmode and we cannot simplify it, as SUBREG without
5465 inner mode is invalid. */
5466 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5467 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5468 return gen_lowpart (mode
, SUBREG_REG (x
));
5470 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5474 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5479 /* If op is known to have all lower bits zero, the result is zero. */
5481 && SCALAR_INT_MODE_P (mode
)
5482 && SCALAR_INT_MODE_P (op0_mode
)
5483 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5484 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5485 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5486 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5487 & GET_MODE_MASK (mode
)) == 0)
5488 return CONST0_RTX (mode
);
5491 /* Don't change the mode of the MEM if that would change the meaning
5493 if (MEM_P (SUBREG_REG (x
))
5494 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5495 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5496 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5497 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5499 /* Note that we cannot do any narrowing for non-constants since
5500 we might have been counting on using the fact that some bits were
5501 zero. We now do this in the SET. */
5506 temp
= expand_compound_operation (XEXP (x
, 0));
5508 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5509 replaced by (lshiftrt X C). This will convert
5510 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5512 if (GET_CODE (temp
) == ASHIFTRT
5513 && CONST_INT_P (XEXP (temp
, 1))
5514 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5515 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5516 INTVAL (XEXP (temp
, 1)));
5518 /* If X has only a single bit that might be nonzero, say, bit I, convert
5519 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5520 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5521 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5522 or a SUBREG of one since we'd be making the expression more
5523 complex if it was just a register. */
5526 && ! (GET_CODE (temp
) == SUBREG
5527 && REG_P (SUBREG_REG (temp
)))
5528 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5530 rtx temp1
= simplify_shift_const
5531 (NULL_RTX
, ASHIFTRT
, mode
,
5532 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5533 GET_MODE_PRECISION (mode
) - 1 - i
),
5534 GET_MODE_PRECISION (mode
) - 1 - i
);
5536 /* If all we did was surround TEMP with the two shifts, we
5537 haven't improved anything, so don't use it. Otherwise,
5538 we are better off with TEMP1. */
5539 if (GET_CODE (temp1
) != ASHIFTRT
5540 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5541 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5547 /* We can't handle truncation to a partial integer mode here
5548 because we don't know the real bitsize of the partial
5550 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5553 if (HWI_COMPUTABLE_MODE_P (mode
))
5555 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5556 GET_MODE_MASK (mode
), 0));
5558 /* We can truncate a constant value and return it. */
5559 if (CONST_INT_P (XEXP (x
, 0)))
5560 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5562 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5563 whose value is a comparison can be replaced with a subreg if
5564 STORE_FLAG_VALUE permits. */
5565 if (HWI_COMPUTABLE_MODE_P (mode
)
5566 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5567 && (temp
= get_last_value (XEXP (x
, 0)))
5568 && COMPARISON_P (temp
))
5569 return gen_lowpart (mode
, XEXP (x
, 0));
5573 /* (const (const X)) can become (const X). Do it this way rather than
5574 returning the inner CONST since CONST can be shared with a
5576 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5577 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5582 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5583 can add in an offset. find_split_point will split this address up
5584 again if it doesn't match. */
5585 if (GET_CODE (XEXP (x
, 0)) == HIGH
5586 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5592 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5593 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5594 bit-field and can be replaced by either a sign_extend or a
5595 sign_extract. The `and' may be a zero_extend and the two
5596 <c>, -<c> constants may be reversed. */
5597 if (GET_CODE (XEXP (x
, 0)) == XOR
5598 && CONST_INT_P (XEXP (x
, 1))
5599 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5600 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5601 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5602 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5603 && HWI_COMPUTABLE_MODE_P (mode
)
5604 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5605 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5606 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5607 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5608 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5609 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5610 == (unsigned int) i
+ 1))))
5611 return simplify_shift_const
5612 (NULL_RTX
, ASHIFTRT
, mode
,
5613 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5614 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5615 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5616 GET_MODE_PRECISION (mode
) - (i
+ 1));
5618 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5619 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5620 the bitsize of the mode - 1. This allows simplification of
5621 "a = (b & 8) == 0;" */
5622 if (XEXP (x
, 1) == constm1_rtx
5623 && !REG_P (XEXP (x
, 0))
5624 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5625 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5626 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5627 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5628 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5629 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5630 GET_MODE_PRECISION (mode
) - 1),
5631 GET_MODE_PRECISION (mode
) - 1);
5633 /* If we are adding two things that have no bits in common, convert
5634 the addition into an IOR. This will often be further simplified,
5635 for example in cases like ((a & 1) + (a & 2)), which can
5638 if (HWI_COMPUTABLE_MODE_P (mode
)
5639 && (nonzero_bits (XEXP (x
, 0), mode
)
5640 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5642 /* Try to simplify the expression further. */
5643 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5644 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5646 /* If we could, great. If not, do not go ahead with the IOR
5647 replacement, since PLUS appears in many special purpose
5648 address arithmetic instructions. */
5649 if (GET_CODE (temp
) != CLOBBER
5650 && (GET_CODE (temp
) != IOR
5651 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5652 || XEXP (temp
, 1) != XEXP (x
, 1))
5653 && (XEXP (temp
, 0) != XEXP (x
, 1)
5654 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5660 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5661 (and <foo> (const_int pow2-1)) */
5662 if (GET_CODE (XEXP (x
, 1)) == AND
5663 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5664 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5665 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5666 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5667 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5671 /* If we have (mult (plus A B) C), apply the distributive law and then
5672 the inverse distributive law to see if things simplify. This
5673 occurs mostly in addresses, often when unrolling loops. */
5675 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5677 rtx result
= distribute_and_simplify_rtx (x
, 0);
5682 /* Try simplify a*(b/c) as (a*b)/c. */
5683 if (FLOAT_MODE_P (mode
) && flag_associative_math
5684 && GET_CODE (XEXP (x
, 0)) == DIV
)
5686 rtx tem
= simplify_binary_operation (MULT
, mode
,
5687 XEXP (XEXP (x
, 0), 0),
5690 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5695 /* If this is a divide by a power of two, treat it as a shift if
5696 its first operand is a shift. */
5697 if (CONST_INT_P (XEXP (x
, 1))
5698 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5699 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5700 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5701 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5702 || GET_CODE (XEXP (x
, 0)) == ROTATE
5703 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5704 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5708 case GT
: case GTU
: case GE
: case GEU
:
5709 case LT
: case LTU
: case LE
: case LEU
:
5710 case UNEQ
: case LTGT
:
5711 case UNGT
: case UNGE
:
5712 case UNLT
: case UNLE
:
5713 case UNORDERED
: case ORDERED
:
5714 /* If the first operand is a condition code, we can't do anything
5716 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5717 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5718 && ! CC0_P (XEXP (x
, 0))))
5720 rtx op0
= XEXP (x
, 0);
5721 rtx op1
= XEXP (x
, 1);
5722 enum rtx_code new_code
;
5724 if (GET_CODE (op0
) == COMPARE
)
5725 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5727 /* Simplify our comparison, if possible. */
5728 new_code
= simplify_comparison (code
, &op0
, &op1
);
5730 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5731 if only the low-order bit is possibly nonzero in X (such as when
5732 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5733 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5734 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5737 Remove any ZERO_EXTRACT we made when thinking this was a
5738 comparison. It may now be simpler to use, e.g., an AND. If a
5739 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5740 the call to make_compound_operation in the SET case.
5742 Don't apply these optimizations if the caller would
5743 prefer a comparison rather than a value.
5744 E.g., for the condition in an IF_THEN_ELSE most targets need
5745 an explicit comparison. */
5750 else if (STORE_FLAG_VALUE
== 1
5751 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5752 && op1
== const0_rtx
5753 && mode
== GET_MODE (op0
)
5754 && nonzero_bits (op0
, mode
) == 1)
5755 return gen_lowpart (mode
,
5756 expand_compound_operation (op0
));
5758 else if (STORE_FLAG_VALUE
== 1
5759 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5760 && op1
== const0_rtx
5761 && mode
== GET_MODE (op0
)
5762 && (num_sign_bit_copies (op0
, mode
)
5763 == GET_MODE_PRECISION (mode
)))
5765 op0
= expand_compound_operation (op0
);
5766 return simplify_gen_unary (NEG
, mode
,
5767 gen_lowpart (mode
, op0
),
5771 else if (STORE_FLAG_VALUE
== 1
5772 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5773 && op1
== const0_rtx
5774 && mode
== GET_MODE (op0
)
5775 && nonzero_bits (op0
, mode
) == 1)
5777 op0
= expand_compound_operation (op0
);
5778 return simplify_gen_binary (XOR
, mode
,
5779 gen_lowpart (mode
, op0
),
5783 else if (STORE_FLAG_VALUE
== 1
5784 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5785 && op1
== const0_rtx
5786 && mode
== GET_MODE (op0
)
5787 && (num_sign_bit_copies (op0
, mode
)
5788 == GET_MODE_PRECISION (mode
)))
5790 op0
= expand_compound_operation (op0
);
5791 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5794 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5799 else if (STORE_FLAG_VALUE
== -1
5800 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5801 && op1
== const0_rtx
5802 && (num_sign_bit_copies (op0
, mode
)
5803 == GET_MODE_PRECISION (mode
)))
5804 return gen_lowpart (mode
,
5805 expand_compound_operation (op0
));
5807 else if (STORE_FLAG_VALUE
== -1
5808 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5809 && op1
== const0_rtx
5810 && mode
== GET_MODE (op0
)
5811 && nonzero_bits (op0
, mode
) == 1)
5813 op0
= expand_compound_operation (op0
);
5814 return simplify_gen_unary (NEG
, mode
,
5815 gen_lowpart (mode
, op0
),
5819 else if (STORE_FLAG_VALUE
== -1
5820 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5821 && op1
== const0_rtx
5822 && mode
== GET_MODE (op0
)
5823 && (num_sign_bit_copies (op0
, mode
)
5824 == GET_MODE_PRECISION (mode
)))
5826 op0
= expand_compound_operation (op0
);
5827 return simplify_gen_unary (NOT
, mode
,
5828 gen_lowpart (mode
, op0
),
5832 /* If X is 0/1, (eq X 0) is X-1. */
5833 else if (STORE_FLAG_VALUE
== -1
5834 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5835 && op1
== const0_rtx
5836 && mode
== GET_MODE (op0
)
5837 && nonzero_bits (op0
, mode
) == 1)
5839 op0
= expand_compound_operation (op0
);
5840 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5843 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5844 one bit that might be nonzero, we can convert (ne x 0) to
5845 (ashift x c) where C puts the bit in the sign bit. Remove any
5846 AND with STORE_FLAG_VALUE when we are done, since we are only
5847 going to test the sign bit. */
5848 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5849 && HWI_COMPUTABLE_MODE_P (mode
)
5850 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5851 && op1
== const0_rtx
5852 && mode
== GET_MODE (op0
)
5853 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5855 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5856 expand_compound_operation (op0
),
5857 GET_MODE_PRECISION (mode
) - 1 - i
);
5858 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5864 /* If the code changed, return a whole new comparison.
5865 We also need to avoid using SUBST in cases where
5866 simplify_comparison has widened a comparison with a CONST_INT,
5867 since in that case the wider CONST_INT may fail the sanity
5868 checks in do_SUBST. */
5869 if (new_code
!= code
5870 || (CONST_INT_P (op1
)
5871 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5872 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5873 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5875 /* Otherwise, keep this operation, but maybe change its operands.
5876 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5877 SUBST (XEXP (x
, 0), op0
);
5878 SUBST (XEXP (x
, 1), op1
);
5883 return simplify_if_then_else (x
);
5889 /* If we are processing SET_DEST, we are done. */
5893 return expand_compound_operation (x
);
5896 return simplify_set (x
);
5900 return simplify_logical (x
);
5907 /* If this is a shift by a constant amount, simplify it. */
5908 if (CONST_INT_P (XEXP (x
, 1)))
5909 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5910 INTVAL (XEXP (x
, 1)));
5912 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5914 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5915 ((unsigned HOST_WIDE_INT
) 1
5916 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5928 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5931 simplify_if_then_else (rtx x
)
5933 enum machine_mode mode
= GET_MODE (x
);
5934 rtx cond
= XEXP (x
, 0);
5935 rtx true_rtx
= XEXP (x
, 1);
5936 rtx false_rtx
= XEXP (x
, 2);
5937 enum rtx_code true_code
= GET_CODE (cond
);
5938 int comparison_p
= COMPARISON_P (cond
);
5941 enum rtx_code false_code
;
5944 /* Simplify storing of the truth value. */
5945 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5946 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5947 XEXP (cond
, 0), XEXP (cond
, 1));
5949 /* Also when the truth value has to be reversed. */
5951 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5952 && (reversed
= reversed_comparison (cond
, mode
)))
5955 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5956 in it is being compared against certain values. Get the true and false
5957 comparisons and see if that says anything about the value of each arm. */
5960 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5962 && REG_P (XEXP (cond
, 0)))
5965 rtx from
= XEXP (cond
, 0);
5966 rtx true_val
= XEXP (cond
, 1);
5967 rtx false_val
= true_val
;
5970 /* If FALSE_CODE is EQ, swap the codes and arms. */
5972 if (false_code
== EQ
)
5974 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5975 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5978 /* If we are comparing against zero and the expression being tested has
5979 only a single bit that might be nonzero, that is its value when it is
5980 not equal to zero. Similarly if it is known to be -1 or 0. */
5982 if (true_code
== EQ
&& true_val
== const0_rtx
5983 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5986 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5988 else if (true_code
== EQ
&& true_val
== const0_rtx
5989 && (num_sign_bit_copies (from
, GET_MODE (from
))
5990 == GET_MODE_PRECISION (GET_MODE (from
))))
5993 false_val
= constm1_rtx
;
5996 /* Now simplify an arm if we know the value of the register in the
5997 branch and it is used in the arm. Be careful due to the potential
5998 of locally-shared RTL. */
6000 if (reg_mentioned_p (from
, true_rtx
))
6001 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6003 pc_rtx
, pc_rtx
, 0, 0, 0);
6004 if (reg_mentioned_p (from
, false_rtx
))
6005 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6007 pc_rtx
, pc_rtx
, 0, 0, 0);
6009 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6010 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6012 true_rtx
= XEXP (x
, 1);
6013 false_rtx
= XEXP (x
, 2);
6014 true_code
= GET_CODE (cond
);
6017 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6018 reversed, do so to avoid needing two sets of patterns for
6019 subtract-and-branch insns. Similarly if we have a constant in the true
6020 arm, the false arm is the same as the first operand of the comparison, or
6021 the false arm is more complicated than the true arm. */
6024 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6025 && (true_rtx
== pc_rtx
6026 || (CONSTANT_P (true_rtx
)
6027 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6028 || true_rtx
== const0_rtx
6029 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6030 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6031 && !OBJECT_P (false_rtx
))
6032 || reg_mentioned_p (true_rtx
, false_rtx
)
6033 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6035 true_code
= reversed_comparison_code (cond
, NULL
);
6036 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6037 SUBST (XEXP (x
, 1), false_rtx
);
6038 SUBST (XEXP (x
, 2), true_rtx
);
6040 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
6043 /* It is possible that the conditional has been simplified out. */
6044 true_code
= GET_CODE (cond
);
6045 comparison_p
= COMPARISON_P (cond
);
6048 /* If the two arms are identical, we don't need the comparison. */
6050 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6053 /* Convert a == b ? b : a to "a". */
6054 if (true_code
== EQ
&& ! side_effects_p (cond
)
6055 && !HONOR_NANS (mode
)
6056 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6057 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6059 else if (true_code
== NE
&& ! side_effects_p (cond
)
6060 && !HONOR_NANS (mode
)
6061 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6062 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6065 /* Look for cases where we have (abs x) or (neg (abs X)). */
6067 if (GET_MODE_CLASS (mode
) == MODE_INT
6069 && XEXP (cond
, 1) == const0_rtx
6070 && GET_CODE (false_rtx
) == NEG
6071 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6072 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6073 && ! side_effects_p (true_rtx
))
6078 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6082 simplify_gen_unary (NEG
, mode
,
6083 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6089 /* Look for MIN or MAX. */
6091 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6093 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6094 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6095 && ! side_effects_p (cond
))
6100 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6103 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6106 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6109 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6114 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6115 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6116 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6117 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6118 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6119 neither 1 or -1, but it isn't worth checking for. */
6121 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6123 && GET_MODE_CLASS (mode
) == MODE_INT
6124 && ! side_effects_p (x
))
6126 rtx t
= make_compound_operation (true_rtx
, SET
);
6127 rtx f
= make_compound_operation (false_rtx
, SET
);
6128 rtx cond_op0
= XEXP (cond
, 0);
6129 rtx cond_op1
= XEXP (cond
, 1);
6130 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6131 enum machine_mode m
= mode
;
6132 rtx z
= 0, c1
= NULL_RTX
;
6134 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6135 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6136 || GET_CODE (t
) == ASHIFT
6137 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6138 && rtx_equal_p (XEXP (t
, 0), f
))
6139 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6141 /* If an identity-zero op is commutative, check whether there
6142 would be a match if we swapped the operands. */
6143 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6144 || GET_CODE (t
) == XOR
)
6145 && rtx_equal_p (XEXP (t
, 1), f
))
6146 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6147 else if (GET_CODE (t
) == SIGN_EXTEND
6148 && (GET_CODE (XEXP (t
, 0)) == PLUS
6149 || GET_CODE (XEXP (t
, 0)) == MINUS
6150 || GET_CODE (XEXP (t
, 0)) == IOR
6151 || GET_CODE (XEXP (t
, 0)) == XOR
6152 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6153 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6154 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6155 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6156 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6157 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6158 && (num_sign_bit_copies (f
, GET_MODE (f
))
6160 (GET_MODE_PRECISION (mode
)
6161 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6163 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6164 extend_op
= SIGN_EXTEND
;
6165 m
= GET_MODE (XEXP (t
, 0));
6167 else if (GET_CODE (t
) == SIGN_EXTEND
6168 && (GET_CODE (XEXP (t
, 0)) == PLUS
6169 || GET_CODE (XEXP (t
, 0)) == IOR
6170 || GET_CODE (XEXP (t
, 0)) == XOR
)
6171 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6172 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6173 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6174 && (num_sign_bit_copies (f
, GET_MODE (f
))
6176 (GET_MODE_PRECISION (mode
)
6177 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6179 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6180 extend_op
= SIGN_EXTEND
;
6181 m
= GET_MODE (XEXP (t
, 0));
6183 else if (GET_CODE (t
) == ZERO_EXTEND
6184 && (GET_CODE (XEXP (t
, 0)) == PLUS
6185 || GET_CODE (XEXP (t
, 0)) == MINUS
6186 || GET_CODE (XEXP (t
, 0)) == IOR
6187 || GET_CODE (XEXP (t
, 0)) == XOR
6188 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6189 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6190 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6191 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6192 && HWI_COMPUTABLE_MODE_P (mode
)
6193 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6194 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6195 && ((nonzero_bits (f
, GET_MODE (f
))
6196 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6199 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6200 extend_op
= ZERO_EXTEND
;
6201 m
= GET_MODE (XEXP (t
, 0));
6203 else if (GET_CODE (t
) == ZERO_EXTEND
6204 && (GET_CODE (XEXP (t
, 0)) == PLUS
6205 || GET_CODE (XEXP (t
, 0)) == IOR
6206 || GET_CODE (XEXP (t
, 0)) == XOR
)
6207 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6208 && HWI_COMPUTABLE_MODE_P (mode
)
6209 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6210 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6211 && ((nonzero_bits (f
, GET_MODE (f
))
6212 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6215 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6216 extend_op
= ZERO_EXTEND
;
6217 m
= GET_MODE (XEXP (t
, 0));
6222 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6223 cond_op0
, cond_op1
),
6224 pc_rtx
, pc_rtx
, 0, 0, 0);
6225 temp
= simplify_gen_binary (MULT
, m
, temp
,
6226 simplify_gen_binary (MULT
, m
, c1
,
6228 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6229 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6231 if (extend_op
!= UNKNOWN
)
6232 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6238 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6239 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6240 negation of a single bit, we can convert this operation to a shift. We
6241 can actually do this more generally, but it doesn't seem worth it. */
6243 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6244 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6245 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6246 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6247 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6248 == GET_MODE_PRECISION (mode
))
6249 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6251 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6252 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6254 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6255 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6256 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6257 && GET_MODE (XEXP (cond
, 0)) == mode
6258 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6259 == nonzero_bits (XEXP (cond
, 0), mode
)
6260 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6261 return XEXP (cond
, 0);
6266 /* Simplify X, a SET expression. Return the new expression. */
6269 simplify_set (rtx x
)
6271 rtx src
= SET_SRC (x
);
6272 rtx dest
= SET_DEST (x
);
6273 enum machine_mode mode
6274 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6275 rtx_insn
*other_insn
;
6278 /* (set (pc) (return)) gets written as (return). */
6279 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6282 /* Now that we know for sure which bits of SRC we are using, see if we can
6283 simplify the expression for the object knowing that we only need the
6286 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6288 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6289 SUBST (SET_SRC (x
), src
);
6292 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6293 the comparison result and try to simplify it unless we already have used
6294 undobuf.other_insn. */
6295 if ((GET_MODE_CLASS (mode
) == MODE_CC
6296 || GET_CODE (src
) == COMPARE
6298 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6299 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6300 && COMPARISON_P (*cc_use
)
6301 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6303 enum rtx_code old_code
= GET_CODE (*cc_use
);
6304 enum rtx_code new_code
;
6306 int other_changed
= 0;
6307 rtx inner_compare
= NULL_RTX
;
6308 enum machine_mode compare_mode
= GET_MODE (dest
);
6310 if (GET_CODE (src
) == COMPARE
)
6312 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6313 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6315 inner_compare
= op0
;
6316 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6320 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6322 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6325 new_code
= old_code
;
6326 else if (!CONSTANT_P (tmp
))
6328 new_code
= GET_CODE (tmp
);
6329 op0
= XEXP (tmp
, 0);
6330 op1
= XEXP (tmp
, 1);
6334 rtx pat
= PATTERN (other_insn
);
6335 undobuf
.other_insn
= other_insn
;
6336 SUBST (*cc_use
, tmp
);
6338 /* Attempt to simplify CC user. */
6339 if (GET_CODE (pat
) == SET
)
6341 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6342 if (new_rtx
!= NULL_RTX
)
6343 SUBST (SET_SRC (pat
), new_rtx
);
6346 /* Convert X into a no-op move. */
6347 SUBST (SET_DEST (x
), pc_rtx
);
6348 SUBST (SET_SRC (x
), pc_rtx
);
6352 /* Simplify our comparison, if possible. */
6353 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6355 #ifdef SELECT_CC_MODE
6356 /* If this machine has CC modes other than CCmode, check to see if we
6357 need to use a different CC mode here. */
6358 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6359 compare_mode
= GET_MODE (op0
);
6360 else if (inner_compare
6361 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6362 && new_code
== old_code
6363 && op0
== XEXP (inner_compare
, 0)
6364 && op1
== XEXP (inner_compare
, 1))
6365 compare_mode
= GET_MODE (inner_compare
);
6367 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6370 /* If the mode changed, we have to change SET_DEST, the mode in the
6371 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6372 a hard register, just build new versions with the proper mode. If it
6373 is a pseudo, we lose unless it is only time we set the pseudo, in
6374 which case we can safely change its mode. */
6375 if (compare_mode
!= GET_MODE (dest
))
6377 if (can_change_dest_mode (dest
, 0, compare_mode
))
6379 unsigned int regno
= REGNO (dest
);
6382 if (regno
< FIRST_PSEUDO_REGISTER
)
6383 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6386 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6387 new_dest
= regno_reg_rtx
[regno
];
6390 SUBST (SET_DEST (x
), new_dest
);
6391 SUBST (XEXP (*cc_use
, 0), new_dest
);
6398 #endif /* SELECT_CC_MODE */
6400 /* If the code changed, we have to build a new comparison in
6401 undobuf.other_insn. */
6402 if (new_code
!= old_code
)
6404 int other_changed_previously
= other_changed
;
6405 unsigned HOST_WIDE_INT mask
;
6406 rtx old_cc_use
= *cc_use
;
6408 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6412 /* If the only change we made was to change an EQ into an NE or
6413 vice versa, OP0 has only one bit that might be nonzero, and OP1
6414 is zero, check if changing the user of the condition code will
6415 produce a valid insn. If it won't, we can keep the original code
6416 in that insn by surrounding our operation with an XOR. */
6418 if (((old_code
== NE
&& new_code
== EQ
)
6419 || (old_code
== EQ
&& new_code
== NE
))
6420 && ! other_changed_previously
&& op1
== const0_rtx
6421 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6422 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6424 rtx pat
= PATTERN (other_insn
), note
= 0;
6426 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6427 && ! check_asm_operands (pat
)))
6429 *cc_use
= old_cc_use
;
6432 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6440 undobuf
.other_insn
= other_insn
;
6442 /* Otherwise, if we didn't previously have a COMPARE in the
6443 correct mode, we need one. */
6444 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6446 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6449 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6451 SUBST (SET_SRC (x
), op0
);
6454 /* Otherwise, update the COMPARE if needed. */
6455 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6457 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6463 /* Get SET_SRC in a form where we have placed back any
6464 compound expressions. Then do the checks below. */
6465 src
= make_compound_operation (src
, SET
);
6466 SUBST (SET_SRC (x
), src
);
6469 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6470 and X being a REG or (subreg (reg)), we may be able to convert this to
6471 (set (subreg:m2 x) (op)).
6473 We can always do this if M1 is narrower than M2 because that means that
6474 we only care about the low bits of the result.
6476 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6477 perform a narrower operation than requested since the high-order bits will
6478 be undefined. On machine where it is defined, this transformation is safe
6479 as long as M1 and M2 have the same number of words. */
6481 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6482 && !OBJECT_P (SUBREG_REG (src
))
6483 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6485 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6486 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6487 #ifndef WORD_REGISTER_OPERATIONS
6488 && (GET_MODE_SIZE (GET_MODE (src
))
6489 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6491 #ifdef CANNOT_CHANGE_MODE_CLASS
6492 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6493 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6494 GET_MODE (SUBREG_REG (src
)),
6498 || (GET_CODE (dest
) == SUBREG
6499 && REG_P (SUBREG_REG (dest
)))))
6501 SUBST (SET_DEST (x
),
6502 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6504 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6506 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6510 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6513 && GET_CODE (src
) == SUBREG
6514 && subreg_lowpart_p (src
)
6515 && (GET_MODE_PRECISION (GET_MODE (src
))
6516 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6518 rtx inner
= SUBREG_REG (src
);
6519 enum machine_mode inner_mode
= GET_MODE (inner
);
6521 /* Here we make sure that we don't have a sign bit on. */
6522 if (val_signbit_known_clear_p (GET_MODE (src
),
6523 nonzero_bits (inner
, inner_mode
)))
6525 SUBST (SET_SRC (x
), inner
);
6531 #ifdef LOAD_EXTEND_OP
6532 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6533 would require a paradoxical subreg. Replace the subreg with a
6534 zero_extend to avoid the reload that would otherwise be required. */
6536 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6537 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6538 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6539 && SUBREG_BYTE (src
) == 0
6540 && paradoxical_subreg_p (src
)
6541 && MEM_P (SUBREG_REG (src
)))
6544 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6545 GET_MODE (src
), SUBREG_REG (src
)));
6551 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6552 are comparing an item known to be 0 or -1 against 0, use a logical
6553 operation instead. Check for one of the arms being an IOR of the other
6554 arm with some value. We compute three terms to be IOR'ed together. In
6555 practice, at most two will be nonzero. Then we do the IOR's. */
6557 if (GET_CODE (dest
) != PC
6558 && GET_CODE (src
) == IF_THEN_ELSE
6559 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6560 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6561 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6562 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6563 #ifdef HAVE_conditional_move
6564 && ! can_conditionally_move_p (GET_MODE (src
))
6566 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6567 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6568 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6569 && ! side_effects_p (src
))
6571 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6572 ? XEXP (src
, 1) : XEXP (src
, 2));
6573 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6574 ? XEXP (src
, 2) : XEXP (src
, 1));
6575 rtx term1
= const0_rtx
, term2
, term3
;
6577 if (GET_CODE (true_rtx
) == IOR
6578 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6579 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6580 else if (GET_CODE (true_rtx
) == IOR
6581 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6582 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6583 else if (GET_CODE (false_rtx
) == IOR
6584 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6585 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6586 else if (GET_CODE (false_rtx
) == IOR
6587 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6588 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6590 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6591 XEXP (XEXP (src
, 0), 0), true_rtx
);
6592 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6593 simplify_gen_unary (NOT
, GET_MODE (src
),
6594 XEXP (XEXP (src
, 0), 0),
6599 simplify_gen_binary (IOR
, GET_MODE (src
),
6600 simplify_gen_binary (IOR
, GET_MODE (src
),
6607 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6608 whole thing fail. */
6609 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6611 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6614 /* Convert this into a field assignment operation, if possible. */
6615 return make_field_assignment (x
);
6618 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6622 simplify_logical (rtx x
)
6624 enum machine_mode mode
= GET_MODE (x
);
6625 rtx op0
= XEXP (x
, 0);
6626 rtx op1
= XEXP (x
, 1);
6628 switch (GET_CODE (x
))
6631 /* We can call simplify_and_const_int only if we don't lose
6632 any (sign) bits when converting INTVAL (op1) to
6633 "unsigned HOST_WIDE_INT". */
6634 if (CONST_INT_P (op1
)
6635 && (HWI_COMPUTABLE_MODE_P (mode
)
6636 || INTVAL (op1
) > 0))
6638 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6639 if (GET_CODE (x
) != AND
)
6646 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6647 apply the distributive law and then the inverse distributive
6648 law to see if things simplify. */
6649 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6651 rtx result
= distribute_and_simplify_rtx (x
, 0);
6655 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6657 rtx result
= distribute_and_simplify_rtx (x
, 1);
6664 /* If we have (ior (and A B) C), apply the distributive law and then
6665 the inverse distributive law to see if things simplify. */
6667 if (GET_CODE (op0
) == AND
)
6669 rtx result
= distribute_and_simplify_rtx (x
, 0);
6674 if (GET_CODE (op1
) == AND
)
6676 rtx result
= distribute_and_simplify_rtx (x
, 1);
6689 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6690 operations" because they can be replaced with two more basic operations.
6691 ZERO_EXTEND is also considered "compound" because it can be replaced with
6692 an AND operation, which is simpler, though only one operation.
6694 The function expand_compound_operation is called with an rtx expression
6695 and will convert it to the appropriate shifts and AND operations,
6696 simplifying at each stage.
6698 The function make_compound_operation is called to convert an expression
6699 consisting of shifts and ANDs into the equivalent compound expression.
6700 It is the inverse of this function, loosely speaking. */
6703 expand_compound_operation (rtx x
)
6705 unsigned HOST_WIDE_INT pos
= 0, len
;
6707 unsigned int modewidth
;
6710 switch (GET_CODE (x
))
6715 /* We can't necessarily use a const_int for a multiword mode;
6716 it depends on implicitly extending the value.
6717 Since we don't know the right way to extend it,
6718 we can't tell whether the implicit way is right.
6720 Even for a mode that is no wider than a const_int,
6721 we can't win, because we need to sign extend one of its bits through
6722 the rest of it, and we don't know which bit. */
6723 if (CONST_INT_P (XEXP (x
, 0)))
6726 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6727 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6728 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6729 reloaded. If not for that, MEM's would very rarely be safe.
6731 Reject MODEs bigger than a word, because we might not be able
6732 to reference a two-register group starting with an arbitrary register
6733 (and currently gen_lowpart might crash for a SUBREG). */
6735 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6738 /* Reject MODEs that aren't scalar integers because turning vector
6739 or complex modes into shifts causes problems. */
6741 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6744 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6745 /* If the inner object has VOIDmode (the only way this can happen
6746 is if it is an ASM_OPERANDS), we can't do anything since we don't
6747 know how much masking to do. */
6756 /* ... fall through ... */
6759 /* If the operand is a CLOBBER, just return it. */
6760 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6763 if (!CONST_INT_P (XEXP (x
, 1))
6764 || !CONST_INT_P (XEXP (x
, 2))
6765 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6768 /* Reject MODEs that aren't scalar integers because turning vector
6769 or complex modes into shifts causes problems. */
6771 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6774 len
= INTVAL (XEXP (x
, 1));
6775 pos
= INTVAL (XEXP (x
, 2));
6777 /* This should stay within the object being extracted, fail otherwise. */
6778 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6781 if (BITS_BIG_ENDIAN
)
6782 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6789 /* Convert sign extension to zero extension, if we know that the high
6790 bit is not set, as this is easier to optimize. It will be converted
6791 back to cheaper alternative in make_extraction. */
6792 if (GET_CODE (x
) == SIGN_EXTEND
6793 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6794 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6795 & ~(((unsigned HOST_WIDE_INT
)
6796 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6800 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6801 rtx temp2
= expand_compound_operation (temp
);
6803 /* Make sure this is a profitable operation. */
6804 if (set_src_cost (x
, optimize_this_for_speed_p
)
6805 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6807 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6808 > set_src_cost (temp
, optimize_this_for_speed_p
))
6814 /* We can optimize some special cases of ZERO_EXTEND. */
6815 if (GET_CODE (x
) == ZERO_EXTEND
)
6817 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6818 know that the last value didn't have any inappropriate bits
6820 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6821 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6822 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6823 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6824 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6825 return XEXP (XEXP (x
, 0), 0);
6827 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6828 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6829 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6830 && subreg_lowpart_p (XEXP (x
, 0))
6831 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6832 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6833 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6834 return SUBREG_REG (XEXP (x
, 0));
6836 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6837 is a comparison and STORE_FLAG_VALUE permits. This is like
6838 the first case, but it works even when GET_MODE (x) is larger
6839 than HOST_WIDE_INT. */
6840 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6841 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6842 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6843 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6844 <= HOST_BITS_PER_WIDE_INT
)
6845 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6846 return XEXP (XEXP (x
, 0), 0);
6848 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6849 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6850 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6851 && subreg_lowpart_p (XEXP (x
, 0))
6852 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6853 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6854 <= HOST_BITS_PER_WIDE_INT
)
6855 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6856 return SUBREG_REG (XEXP (x
, 0));
6860 /* If we reach here, we want to return a pair of shifts. The inner
6861 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6862 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6863 logical depending on the value of UNSIGNEDP.
6865 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6866 converted into an AND of a shift.
6868 We must check for the case where the left shift would have a negative
6869 count. This can happen in a case like (x >> 31) & 255 on machines
6870 that can't shift by a constant. On those machines, we would first
6871 combine the shift with the AND to produce a variable-position
6872 extraction. Then the constant of 31 would be substituted in
6873 to produce such a position. */
6875 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6876 if (modewidth
>= pos
+ len
)
6878 enum machine_mode mode
= GET_MODE (x
);
6879 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6880 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6882 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6883 tem
, modewidth
- pos
- len
);
6884 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6885 mode
, tem
, modewidth
- len
);
6887 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6888 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6889 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6892 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6894 /* Any other cases we can't handle. */
6897 /* If we couldn't do this for some reason, return the original
6899 if (GET_CODE (tem
) == CLOBBER
)
6905 /* X is a SET which contains an assignment of one object into
6906 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6907 or certain SUBREGS). If possible, convert it into a series of
6910 We half-heartedly support variable positions, but do not at all
6911 support variable lengths. */
6914 expand_field_assignment (const_rtx x
)
6917 rtx pos
; /* Always counts from low bit. */
6919 rtx mask
, cleared
, masked
;
6920 enum machine_mode compute_mode
;
6922 /* Loop until we find something we can't simplify. */
6925 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6926 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6928 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6929 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6930 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6932 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6933 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6935 inner
= XEXP (SET_DEST (x
), 0);
6936 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6937 pos
= XEXP (SET_DEST (x
), 2);
6939 /* A constant position should stay within the width of INNER. */
6940 if (CONST_INT_P (pos
)
6941 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6944 if (BITS_BIG_ENDIAN
)
6946 if (CONST_INT_P (pos
))
6947 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6949 else if (GET_CODE (pos
) == MINUS
6950 && CONST_INT_P (XEXP (pos
, 1))
6951 && (INTVAL (XEXP (pos
, 1))
6952 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6953 /* If position is ADJUST - X, new position is X. */
6954 pos
= XEXP (pos
, 0);
6957 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6958 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6959 gen_int_mode (prec
- len
,
6966 /* A SUBREG between two modes that occupy the same numbers of words
6967 can be done by moving the SUBREG to the source. */
6968 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6969 /* We need SUBREGs to compute nonzero_bits properly. */
6970 && nonzero_sign_valid
6971 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6972 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6973 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6974 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6976 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6978 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6985 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6986 inner
= SUBREG_REG (inner
);
6988 compute_mode
= GET_MODE (inner
);
6990 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6991 if (! SCALAR_INT_MODE_P (compute_mode
))
6993 enum machine_mode imode
;
6995 /* Don't do anything for vector or complex integral types. */
6996 if (! FLOAT_MODE_P (compute_mode
))
6999 /* Try to find an integral mode to pun with. */
7000 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7001 if (imode
== BLKmode
)
7004 compute_mode
= imode
;
7005 inner
= gen_lowpart (imode
, inner
);
7008 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7009 if (len
>= HOST_BITS_PER_WIDE_INT
)
7012 /* Now compute the equivalent expression. Make a copy of INNER
7013 for the SET_DEST in case it is a MEM into which we will substitute;
7014 we don't want shared RTL in that case. */
7015 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7017 cleared
= simplify_gen_binary (AND
, compute_mode
,
7018 simplify_gen_unary (NOT
, compute_mode
,
7019 simplify_gen_binary (ASHIFT
,
7024 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7025 simplify_gen_binary (
7027 gen_lowpart (compute_mode
, SET_SRC (x
)),
7031 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
7032 simplify_gen_binary (IOR
, compute_mode
,
7039 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7040 it is an RTX that represents the (variable) starting position; otherwise,
7041 POS is the (constant) starting bit position. Both are counted from the LSB.
7043 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7045 IN_DEST is nonzero if this is a reference in the destination of a SET.
7046 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7047 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7050 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7051 ZERO_EXTRACT should be built even for bits starting at bit 0.
7053 MODE is the desired mode of the result (if IN_DEST == 0).
7055 The result is an RTX for the extraction or NULL_RTX if the target
7059 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7060 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7061 int in_dest
, int in_compare
)
7063 /* This mode describes the size of the storage area
7064 to fetch the overall value from. Within that, we
7065 ignore the POS lowest bits, etc. */
7066 enum machine_mode is_mode
= GET_MODE (inner
);
7067 enum machine_mode inner_mode
;
7068 enum machine_mode wanted_inner_mode
;
7069 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7070 enum machine_mode pos_mode
= word_mode
;
7071 enum machine_mode extraction_mode
= word_mode
;
7072 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7074 rtx orig_pos_rtx
= pos_rtx
;
7075 HOST_WIDE_INT orig_pos
;
7077 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7078 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7080 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7082 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7083 consider just the QI as the memory to extract from.
7084 The subreg adds or removes high bits; its mode is
7085 irrelevant to the meaning of this extraction,
7086 since POS and LEN count from the lsb. */
7087 if (MEM_P (SUBREG_REG (inner
)))
7088 is_mode
= GET_MODE (SUBREG_REG (inner
));
7089 inner
= SUBREG_REG (inner
);
7091 else if (GET_CODE (inner
) == ASHIFT
7092 && CONST_INT_P (XEXP (inner
, 1))
7093 && pos_rtx
== 0 && pos
== 0
7094 && len
> UINTVAL (XEXP (inner
, 1)))
7096 /* We're extracting the least significant bits of an rtx
7097 (ashift X (const_int C)), where LEN > C. Extract the
7098 least significant (LEN - C) bits of X, giving an rtx
7099 whose mode is MODE, then shift it left C times. */
7100 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7101 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7102 unsignedp
, in_dest
, in_compare
);
7104 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7106 else if (GET_CODE (inner
) == TRUNCATE
)
7107 inner
= XEXP (inner
, 0);
7109 inner_mode
= GET_MODE (inner
);
7111 /* See if this can be done without an extraction. We never can if the
7112 width of the field is not the same as that of some integer mode. For
7113 registers, we can only avoid the extraction if the position is at the
7114 low-order bit and this is either not in the destination or we have the
7115 appropriate STRICT_LOW_PART operation available.
7117 For MEM, we can avoid an extract if the field starts on an appropriate
7118 boundary and we can change the mode of the memory reference. */
7120 if (tmode
!= BLKmode
7121 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7123 && (inner_mode
== tmode
7125 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7126 || reg_truncated_to_mode (tmode
, inner
))
7129 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7130 || (MEM_P (inner
) && pos_rtx
== 0
7132 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7133 : BITS_PER_UNIT
)) == 0
7134 /* We can't do this if we are widening INNER_MODE (it
7135 may not be aligned, for one thing). */
7136 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7137 && (inner_mode
== tmode
7138 || (! mode_dependent_address_p (XEXP (inner
, 0),
7139 MEM_ADDR_SPACE (inner
))
7140 && ! MEM_VOLATILE_P (inner
))))))
7142 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7143 field. If the original and current mode are the same, we need not
7144 adjust the offset. Otherwise, we do if bytes big endian.
7146 If INNER is not a MEM, get a piece consisting of just the field
7147 of interest (in this case POS % BITS_PER_WORD must be 0). */
7151 HOST_WIDE_INT offset
;
7153 /* POS counts from lsb, but make OFFSET count in memory order. */
7154 if (BYTES_BIG_ENDIAN
)
7155 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7157 offset
= pos
/ BITS_PER_UNIT
;
7159 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7161 else if (REG_P (inner
))
7163 if (tmode
!= inner_mode
)
7165 /* We can't call gen_lowpart in a DEST since we
7166 always want a SUBREG (see below) and it would sometimes
7167 return a new hard register. */
7170 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7172 if (WORDS_BIG_ENDIAN
7173 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7174 final_word
= ((GET_MODE_SIZE (inner_mode
)
7175 - GET_MODE_SIZE (tmode
))
7176 / UNITS_PER_WORD
) - final_word
;
7178 final_word
*= UNITS_PER_WORD
;
7179 if (BYTES_BIG_ENDIAN
&&
7180 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7181 final_word
+= (GET_MODE_SIZE (inner_mode
)
7182 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7184 /* Avoid creating invalid subregs, for example when
7185 simplifying (x>>32)&255. */
7186 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7189 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7192 new_rtx
= gen_lowpart (tmode
, inner
);
7198 new_rtx
= force_to_mode (inner
, tmode
,
7199 len
>= HOST_BITS_PER_WIDE_INT
7200 ? ~(unsigned HOST_WIDE_INT
) 0
7201 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7204 /* If this extraction is going into the destination of a SET,
7205 make a STRICT_LOW_PART unless we made a MEM. */
7208 return (MEM_P (new_rtx
) ? new_rtx
7209 : (GET_CODE (new_rtx
) != SUBREG
7210 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7211 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7216 if (CONST_SCALAR_INT_P (new_rtx
))
7217 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7218 mode
, new_rtx
, tmode
);
7220 /* If we know that no extraneous bits are set, and that the high
7221 bit is not set, convert the extraction to the cheaper of
7222 sign and zero extension, that are equivalent in these cases. */
7223 if (flag_expensive_optimizations
7224 && (HWI_COMPUTABLE_MODE_P (tmode
)
7225 && ((nonzero_bits (new_rtx
, tmode
)
7226 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7229 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7230 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7232 /* Prefer ZERO_EXTENSION, since it gives more information to
7234 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7235 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7240 /* Otherwise, sign- or zero-extend unless we already are in the
7243 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7247 /* Unless this is a COMPARE or we have a funny memory reference,
7248 don't do anything with zero-extending field extracts starting at
7249 the low-order bit since they are simple AND operations. */
7250 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7251 && ! in_compare
&& unsignedp
)
7254 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7255 if the position is not a constant and the length is not 1. In all
7256 other cases, we would only be going outside our object in cases when
7257 an original shift would have been undefined. */
7259 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7260 || (pos_rtx
!= 0 && len
!= 1)))
7263 enum extraction_pattern pattern
= (in_dest
? EP_insv
7264 : unsignedp
? EP_extzv
: EP_extv
);
7266 /* If INNER is not from memory, we want it to have the mode of a register
7267 extraction pattern's structure operand, or word_mode if there is no
7268 such pattern. The same applies to extraction_mode and pos_mode
7269 and their respective operands.
7271 For memory, assume that the desired extraction_mode and pos_mode
7272 are the same as for a register operation, since at present we don't
7273 have named patterns for aligned memory structures. */
7274 struct extraction_insn insn
;
7275 if (get_best_reg_extraction_insn (&insn
, pattern
,
7276 GET_MODE_BITSIZE (inner_mode
), mode
))
7278 wanted_inner_reg_mode
= insn
.struct_mode
;
7279 pos_mode
= insn
.pos_mode
;
7280 extraction_mode
= insn
.field_mode
;
7283 /* Never narrow an object, since that might not be safe. */
7285 if (mode
!= VOIDmode
7286 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7287 extraction_mode
= mode
;
7290 wanted_inner_mode
= wanted_inner_reg_mode
;
7293 /* Be careful not to go beyond the extracted object and maintain the
7294 natural alignment of the memory. */
7295 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7296 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7297 > GET_MODE_BITSIZE (wanted_inner_mode
))
7299 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7300 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7306 if (BITS_BIG_ENDIAN
)
7308 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7309 BITS_BIG_ENDIAN style. If position is constant, compute new
7310 position. Otherwise, build subtraction.
7311 Note that POS is relative to the mode of the original argument.
7312 If it's a MEM we need to recompute POS relative to that.
7313 However, if we're extracting from (or inserting into) a register,
7314 we want to recompute POS relative to wanted_inner_mode. */
7315 int width
= (MEM_P (inner
)
7316 ? GET_MODE_BITSIZE (is_mode
)
7317 : GET_MODE_BITSIZE (wanted_inner_mode
));
7320 pos
= width
- len
- pos
;
7323 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7324 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7326 /* POS may be less than 0 now, but we check for that below.
7327 Note that it can only be less than 0 if !MEM_P (inner). */
7330 /* If INNER has a wider mode, and this is a constant extraction, try to
7331 make it smaller and adjust the byte to point to the byte containing
7333 if (wanted_inner_mode
!= VOIDmode
7334 && inner_mode
!= wanted_inner_mode
7336 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7338 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7339 && ! MEM_VOLATILE_P (inner
))
7343 /* The computations below will be correct if the machine is big
7344 endian in both bits and bytes or little endian in bits and bytes.
7345 If it is mixed, we must adjust. */
7347 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7348 adjust OFFSET to compensate. */
7349 if (BYTES_BIG_ENDIAN
7350 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7351 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7353 /* We can now move to the desired byte. */
7354 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7355 * GET_MODE_SIZE (wanted_inner_mode
);
7356 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7358 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7359 && is_mode
!= wanted_inner_mode
)
7360 offset
= (GET_MODE_SIZE (is_mode
)
7361 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7363 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7366 /* If INNER is not memory, get it into the proper mode. If we are changing
7367 its mode, POS must be a constant and smaller than the size of the new
7369 else if (!MEM_P (inner
))
7371 /* On the LHS, don't create paradoxical subregs implicitely truncating
7372 the register unless TRULY_NOOP_TRUNCATION. */
7374 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7378 if (GET_MODE (inner
) != wanted_inner_mode
7380 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7386 inner
= force_to_mode (inner
, wanted_inner_mode
,
7388 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7389 ? ~(unsigned HOST_WIDE_INT
) 0
7390 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7395 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7396 have to zero extend. Otherwise, we can just use a SUBREG. */
7398 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7400 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7401 GET_MODE (pos_rtx
));
7403 /* If we know that no extraneous bits are set, and that the high
7404 bit is not set, convert extraction to cheaper one - either
7405 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7407 if (flag_expensive_optimizations
7408 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7409 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7410 & ~(((unsigned HOST_WIDE_INT
)
7411 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7415 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7416 GET_MODE (pos_rtx
));
7418 /* Prefer ZERO_EXTENSION, since it gives more information to
7420 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7421 < set_src_cost (temp
, optimize_this_for_speed_p
))
7427 /* Make POS_RTX unless we already have it and it is correct. If we don't
7428 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7430 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7431 pos_rtx
= orig_pos_rtx
;
7433 else if (pos_rtx
== 0)
7434 pos_rtx
= GEN_INT (pos
);
7436 /* Make the required operation. See if we can use existing rtx. */
7437 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7438 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7440 new_rtx
= gen_lowpart (mode
, new_rtx
);
7445 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7446 with any other operations in X. Return X without that shift if so. */
7449 extract_left_shift (rtx x
, int count
)
7451 enum rtx_code code
= GET_CODE (x
);
7452 enum machine_mode mode
= GET_MODE (x
);
7458 /* This is the shift itself. If it is wide enough, we will return
7459 either the value being shifted if the shift count is equal to
7460 COUNT or a shift for the difference. */
7461 if (CONST_INT_P (XEXP (x
, 1))
7462 && INTVAL (XEXP (x
, 1)) >= count
)
7463 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7464 INTVAL (XEXP (x
, 1)) - count
);
7468 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7469 return simplify_gen_unary (code
, mode
, tem
, mode
);
7473 case PLUS
: case IOR
: case XOR
: case AND
:
7474 /* If we can safely shift this constant and we find the inner shift,
7475 make a new operation. */
7476 if (CONST_INT_P (XEXP (x
, 1))
7477 && (UINTVAL (XEXP (x
, 1))
7478 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7479 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7481 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7482 return simplify_gen_binary (code
, mode
, tem
,
7483 gen_int_mode (val
, mode
));
7494 /* Look at the expression rooted at X. Look for expressions
7495 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7496 Form these expressions.
7498 Return the new rtx, usually just X.
7500 Also, for machines like the VAX that don't have logical shift insns,
7501 try to convert logical to arithmetic shift operations in cases where
7502 they are equivalent. This undoes the canonicalizations to logical
7503 shifts done elsewhere.
7505 We try, as much as possible, to re-use rtl expressions to save memory.
7507 IN_CODE says what kind of expression we are processing. Normally, it is
7508 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7509 being kludges), it is MEM. When processing the arguments of a comparison
7510 or a COMPARE against zero, it is COMPARE. */
7513 make_compound_operation (rtx x
, enum rtx_code in_code
)
7515 enum rtx_code code
= GET_CODE (x
);
7516 enum machine_mode mode
= GET_MODE (x
);
7517 int mode_width
= GET_MODE_PRECISION (mode
);
7519 enum rtx_code next_code
;
7525 /* Select the code to be used in recursive calls. Once we are inside an
7526 address, we stay there. If we have a comparison, set to COMPARE,
7527 but once inside, go back to our default of SET. */
7529 next_code
= (code
== MEM
? MEM
7530 : ((code
== PLUS
|| code
== MINUS
)
7531 && SCALAR_INT_MODE_P (mode
)) ? MEM
7532 : ((code
== COMPARE
|| COMPARISON_P (x
))
7533 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7534 : in_code
== COMPARE
? SET
: in_code
);
7536 /* Process depending on the code of this operation. If NEW is set
7537 nonzero, it will be returned. */
7542 /* Convert shifts by constants into multiplications if inside
7544 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7545 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7546 && INTVAL (XEXP (x
, 1)) >= 0
7547 && SCALAR_INT_MODE_P (mode
))
7549 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7550 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7552 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7553 if (GET_CODE (new_rtx
) == NEG
)
7555 new_rtx
= XEXP (new_rtx
, 0);
7558 multval
= trunc_int_for_mode (multval
, mode
);
7559 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7566 lhs
= make_compound_operation (lhs
, next_code
);
7567 rhs
= make_compound_operation (rhs
, next_code
);
7568 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7569 && SCALAR_INT_MODE_P (mode
))
7571 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7573 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7575 else if (GET_CODE (lhs
) == MULT
7576 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7578 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7579 simplify_gen_unary (NEG
, mode
,
7582 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7586 SUBST (XEXP (x
, 0), lhs
);
7587 SUBST (XEXP (x
, 1), rhs
);
7590 x
= gen_lowpart (mode
, new_rtx
);
7596 lhs
= make_compound_operation (lhs
, next_code
);
7597 rhs
= make_compound_operation (rhs
, next_code
);
7598 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7599 && SCALAR_INT_MODE_P (mode
))
7601 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7603 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7605 else if (GET_CODE (rhs
) == MULT
7606 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7608 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7609 simplify_gen_unary (NEG
, mode
,
7612 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7616 SUBST (XEXP (x
, 0), lhs
);
7617 SUBST (XEXP (x
, 1), rhs
);
7620 return gen_lowpart (mode
, new_rtx
);
7623 /* If the second operand is not a constant, we can't do anything
7625 if (!CONST_INT_P (XEXP (x
, 1)))
7628 /* If the constant is a power of two minus one and the first operand
7629 is a logical right shift, make an extraction. */
7630 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7631 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7633 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7634 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7635 0, in_code
== COMPARE
);
7638 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7639 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7640 && subreg_lowpart_p (XEXP (x
, 0))
7641 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7642 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7644 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7646 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7647 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7648 0, in_code
== COMPARE
);
7650 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7651 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7652 || GET_CODE (XEXP (x
, 0)) == IOR
)
7653 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7654 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7655 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7657 /* Apply the distributive law, and then try to make extractions. */
7658 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7659 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7661 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7663 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7666 /* If we are have (and (rotate X C) M) and C is larger than the number
7667 of bits in M, this is an extraction. */
7669 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7670 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7671 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7672 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7674 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7675 new_rtx
= make_extraction (mode
, new_rtx
,
7676 (GET_MODE_PRECISION (mode
)
7677 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7678 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7681 /* On machines without logical shifts, if the operand of the AND is
7682 a logical shift and our mask turns off all the propagated sign
7683 bits, we can replace the logical shift with an arithmetic shift. */
7684 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7685 && !have_insn_for (LSHIFTRT
, mode
)
7686 && have_insn_for (ASHIFTRT
, mode
)
7687 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7688 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7689 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7690 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7692 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7694 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7695 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7697 gen_rtx_ASHIFTRT (mode
,
7698 make_compound_operation
7699 (XEXP (XEXP (x
, 0), 0), next_code
),
7700 XEXP (XEXP (x
, 0), 1)));
7703 /* If the constant is one less than a power of two, this might be
7704 representable by an extraction even if no shift is present.
7705 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7706 we are in a COMPARE. */
7707 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7708 new_rtx
= make_extraction (mode
,
7709 make_compound_operation (XEXP (x
, 0),
7711 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7713 /* If we are in a comparison and this is an AND with a power of two,
7714 convert this into the appropriate bit extract. */
7715 else if (in_code
== COMPARE
7716 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7717 new_rtx
= make_extraction (mode
,
7718 make_compound_operation (XEXP (x
, 0),
7720 i
, NULL_RTX
, 1, 1, 0, 1);
7725 /* If the sign bit is known to be zero, replace this with an
7726 arithmetic shift. */
7727 if (have_insn_for (ASHIFTRT
, mode
)
7728 && ! have_insn_for (LSHIFTRT
, mode
)
7729 && mode_width
<= HOST_BITS_PER_WIDE_INT
7730 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7732 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7733 make_compound_operation (XEXP (x
, 0),
7739 /* ... fall through ... */
7745 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7746 this is a SIGN_EXTRACT. */
7747 if (CONST_INT_P (rhs
)
7748 && GET_CODE (lhs
) == ASHIFT
7749 && CONST_INT_P (XEXP (lhs
, 1))
7750 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7751 && INTVAL (XEXP (lhs
, 1)) >= 0
7752 && INTVAL (rhs
) < mode_width
)
7754 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7755 new_rtx
= make_extraction (mode
, new_rtx
,
7756 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7757 NULL_RTX
, mode_width
- INTVAL (rhs
),
7758 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7762 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7763 If so, try to merge the shifts into a SIGN_EXTEND. We could
7764 also do this for some cases of SIGN_EXTRACT, but it doesn't
7765 seem worth the effort; the case checked for occurs on Alpha. */
7768 && ! (GET_CODE (lhs
) == SUBREG
7769 && (OBJECT_P (SUBREG_REG (lhs
))))
7770 && CONST_INT_P (rhs
)
7771 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7772 && INTVAL (rhs
) < mode_width
7773 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7774 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7775 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7776 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7781 /* Call ourselves recursively on the inner expression. If we are
7782 narrowing the object and it has a different RTL code from
7783 what it originally did, do this SUBREG as a force_to_mode. */
7785 rtx inner
= SUBREG_REG (x
), simplified
;
7786 enum rtx_code subreg_code
= in_code
;
7788 /* If in_code is COMPARE, it isn't always safe to pass it through
7789 to the recursive make_compound_operation call. */
7790 if (subreg_code
== COMPARE
7791 && (!subreg_lowpart_p (x
)
7792 || GET_CODE (inner
) == SUBREG
7793 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7794 is (const_int 0), rather than
7795 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7796 || (GET_CODE (inner
) == AND
7797 && CONST_INT_P (XEXP (inner
, 1))
7798 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7799 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7800 >= GET_MODE_BITSIZE (mode
))))
7803 tem
= make_compound_operation (inner
, subreg_code
);
7806 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7810 if (GET_CODE (tem
) != GET_CODE (inner
)
7811 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7812 && subreg_lowpart_p (x
))
7815 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7817 /* If we have something other than a SUBREG, we might have
7818 done an expansion, so rerun ourselves. */
7819 if (GET_CODE (newer
) != SUBREG
)
7820 newer
= make_compound_operation (newer
, in_code
);
7822 /* force_to_mode can expand compounds. If it just re-expanded the
7823 compound, use gen_lowpart to convert to the desired mode. */
7824 if (rtx_equal_p (newer
, x
)
7825 /* Likewise if it re-expanded the compound only partially.
7826 This happens for SUBREG of ZERO_EXTRACT if they extract
7827 the same number of bits. */
7828 || (GET_CODE (newer
) == SUBREG
7829 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7830 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7831 && GET_CODE (inner
) == AND
7832 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7833 return gen_lowpart (GET_MODE (x
), tem
);
7849 x
= gen_lowpart (mode
, new_rtx
);
7850 code
= GET_CODE (x
);
7853 /* Now recursively process each operand of this operation. We need to
7854 handle ZERO_EXTEND specially so that we don't lose track of the
7856 if (GET_CODE (x
) == ZERO_EXTEND
)
7858 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7859 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7860 new_rtx
, GET_MODE (XEXP (x
, 0)));
7863 SUBST (XEXP (x
, 0), new_rtx
);
7867 fmt
= GET_RTX_FORMAT (code
);
7868 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7871 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7872 SUBST (XEXP (x
, i
), new_rtx
);
7874 else if (fmt
[i
] == 'E')
7875 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7877 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7878 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7882 /* If this is a commutative operation, the changes to the operands
7883 may have made it noncanonical. */
7884 if (COMMUTATIVE_ARITH_P (x
)
7885 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7888 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7889 SUBST (XEXP (x
, 1), tem
);
7895 /* Given M see if it is a value that would select a field of bits
7896 within an item, but not the entire word. Return -1 if not.
7897 Otherwise, return the starting position of the field, where 0 is the
7900 *PLEN is set to the length of the field. */
7903 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7905 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7906 int pos
= m
? ctz_hwi (m
) : -1;
7910 /* Now shift off the low-order zero bits and see if we have a
7911 power of two minus 1. */
7912 len
= exact_log2 ((m
>> pos
) + 1);
7921 /* If X refers to a register that equals REG in value, replace these
7922 references with REG. */
7924 canon_reg_for_combine (rtx x
, rtx reg
)
7931 enum rtx_code code
= GET_CODE (x
);
7932 switch (GET_RTX_CLASS (code
))
7935 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7936 if (op0
!= XEXP (x
, 0))
7937 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7942 case RTX_COMM_ARITH
:
7943 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7944 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7945 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7946 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7950 case RTX_COMM_COMPARE
:
7951 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7952 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7953 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7954 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7955 GET_MODE (op0
), op0
, op1
);
7959 case RTX_BITFIELD_OPS
:
7960 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7961 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7962 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7963 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7964 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7965 GET_MODE (op0
), op0
, op1
, op2
);
7970 if (rtx_equal_p (get_last_value (reg
), x
)
7971 || rtx_equal_p (reg
, get_last_value (x
)))
7980 fmt
= GET_RTX_FORMAT (code
);
7982 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7985 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7986 if (op
!= XEXP (x
, i
))
7996 else if (fmt
[i
] == 'E')
7999 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8001 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8002 if (op
!= XVECEXP (x
, i
, j
))
8009 XVECEXP (x
, i
, j
) = op
;
8020 /* Return X converted to MODE. If the value is already truncated to
8021 MODE we can just return a subreg even though in the general case we
8022 would need an explicit truncation. */
8025 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
8027 if (!CONST_INT_P (x
)
8028 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8029 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8030 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8032 /* Bit-cast X into an integer mode. */
8033 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8034 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8035 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8039 return gen_lowpart (mode
, x
);
8042 /* See if X can be simplified knowing that we will only refer to it in
8043 MODE and will only refer to those bits that are nonzero in MASK.
8044 If other bits are being computed or if masking operations are done
8045 that select a superset of the bits in MASK, they can sometimes be
8048 Return a possibly simplified expression, but always convert X to
8049 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8051 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8052 are all off in X. This is used when X will be complemented, by either
8053 NOT, NEG, or XOR. */
8056 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8059 enum rtx_code code
= GET_CODE (x
);
8060 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8061 enum machine_mode op_mode
;
8062 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8065 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8066 code below will do the wrong thing since the mode of such an
8067 expression is VOIDmode.
8069 Also do nothing if X is a CLOBBER; this can happen if X was
8070 the return value from a call to gen_lowpart. */
8071 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8074 /* We want to perform the operation in its present mode unless we know
8075 that the operation is valid in MODE, in which case we do the operation
8077 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8078 && have_insn_for (code
, mode
))
8079 ? mode
: GET_MODE (x
));
8081 /* It is not valid to do a right-shift in a narrower mode
8082 than the one it came in with. */
8083 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8084 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8085 op_mode
= GET_MODE (x
);
8087 /* Truncate MASK to fit OP_MODE. */
8089 mask
&= GET_MODE_MASK (op_mode
);
8091 /* When we have an arithmetic operation, or a shift whose count we
8092 do not know, we need to assume that all bits up to the highest-order
8093 bit in MASK will be needed. This is how we form such a mask. */
8094 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8095 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8097 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8100 /* Determine what bits of X are guaranteed to be (non)zero. */
8101 nonzero
= nonzero_bits (x
, mode
);
8103 /* If none of the bits in X are needed, return a zero. */
8104 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8107 /* If X is a CONST_INT, return a new one. Do this here since the
8108 test below will fail. */
8109 if (CONST_INT_P (x
))
8111 if (SCALAR_INT_MODE_P (mode
))
8112 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8115 x
= GEN_INT (INTVAL (x
) & mask
);
8116 return gen_lowpart_common (mode
, x
);
8120 /* If X is narrower than MODE and we want all the bits in X's mode, just
8121 get X in the proper mode. */
8122 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8123 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8124 return gen_lowpart (mode
, x
);
8126 /* We can ignore the effect of a SUBREG if it narrows the mode or
8127 if the constant masks to zero all the bits the mode doesn't have. */
8128 if (GET_CODE (x
) == SUBREG
8129 && subreg_lowpart_p (x
)
8130 && ((GET_MODE_SIZE (GET_MODE (x
))
8131 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8133 & GET_MODE_MASK (GET_MODE (x
))
8134 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8135 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8137 /* The arithmetic simplifications here only work for scalar integer modes. */
8138 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8139 return gen_lowpart_or_truncate (mode
, x
);
8144 /* If X is a (clobber (const_int)), return it since we know we are
8145 generating something that won't match. */
8152 x
= expand_compound_operation (x
);
8153 if (GET_CODE (x
) != code
)
8154 return force_to_mode (x
, mode
, mask
, next_select
);
8158 /* Similarly for a truncate. */
8159 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8162 /* If this is an AND with a constant, convert it into an AND
8163 whose constant is the AND of that constant with MASK. If it
8164 remains an AND of MASK, delete it since it is redundant. */
8166 if (CONST_INT_P (XEXP (x
, 1)))
8168 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8169 mask
& INTVAL (XEXP (x
, 1)));
8171 /* If X is still an AND, see if it is an AND with a mask that
8172 is just some low-order bits. If so, and it is MASK, we don't
8175 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8176 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8180 /* If it remains an AND, try making another AND with the bits
8181 in the mode mask that aren't in MASK turned on. If the
8182 constant in the AND is wide enough, this might make a
8183 cheaper constant. */
8185 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8186 && GET_MODE_MASK (GET_MODE (x
)) != mask
8187 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8189 unsigned HOST_WIDE_INT cval
8190 = UINTVAL (XEXP (x
, 1))
8191 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8194 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8195 gen_int_mode (cval
, GET_MODE (x
)));
8196 if (set_src_cost (y
, optimize_this_for_speed_p
)
8197 < set_src_cost (x
, optimize_this_for_speed_p
))
8207 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8208 low-order bits (as in an alignment operation) and FOO is already
8209 aligned to that boundary, mask C1 to that boundary as well.
8210 This may eliminate that PLUS and, later, the AND. */
8213 unsigned int width
= GET_MODE_PRECISION (mode
);
8214 unsigned HOST_WIDE_INT smask
= mask
;
8216 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8217 number, sign extend it. */
8219 if (width
< HOST_BITS_PER_WIDE_INT
8220 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8221 smask
|= HOST_WIDE_INT_M1U
<< width
;
8223 if (CONST_INT_P (XEXP (x
, 1))
8224 && exact_log2 (- smask
) >= 0
8225 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8226 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8227 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8228 (INTVAL (XEXP (x
, 1)) & smask
)),
8229 mode
, smask
, next_select
);
8232 /* ... fall through ... */
8235 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8236 most significant bit in MASK since carries from those bits will
8237 affect the bits we are interested in. */
8242 /* If X is (minus C Y) where C's least set bit is larger than any bit
8243 in the mask, then we may replace with (neg Y). */
8244 if (CONST_INT_P (XEXP (x
, 0))
8245 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8247 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8249 return force_to_mode (x
, mode
, mask
, next_select
);
8252 /* Similarly, if C contains every bit in the fuller_mask, then we may
8253 replace with (not Y). */
8254 if (CONST_INT_P (XEXP (x
, 0))
8255 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8257 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8258 XEXP (x
, 1), GET_MODE (x
));
8259 return force_to_mode (x
, mode
, mask
, next_select
);
8267 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8268 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8269 operation which may be a bitfield extraction. Ensure that the
8270 constant we form is not wider than the mode of X. */
8272 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8273 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8274 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8275 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8276 && CONST_INT_P (XEXP (x
, 1))
8277 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8278 + floor_log2 (INTVAL (XEXP (x
, 1))))
8279 < GET_MODE_PRECISION (GET_MODE (x
)))
8280 && (UINTVAL (XEXP (x
, 1))
8281 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8283 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8284 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8286 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8287 XEXP (XEXP (x
, 0), 0), temp
);
8288 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8289 XEXP (XEXP (x
, 0), 1));
8290 return force_to_mode (x
, mode
, mask
, next_select
);
8294 /* For most binary operations, just propagate into the operation and
8295 change the mode if we have an operation of that mode. */
8297 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8298 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8300 /* If we ended up truncating both operands, truncate the result of the
8301 operation instead. */
8302 if (GET_CODE (op0
) == TRUNCATE
8303 && GET_CODE (op1
) == TRUNCATE
)
8305 op0
= XEXP (op0
, 0);
8306 op1
= XEXP (op1
, 0);
8309 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8310 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8312 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8313 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8317 /* For left shifts, do the same, but just for the first operand.
8318 However, we cannot do anything with shifts where we cannot
8319 guarantee that the counts are smaller than the size of the mode
8320 because such a count will have a different meaning in a
8323 if (! (CONST_INT_P (XEXP (x
, 1))
8324 && INTVAL (XEXP (x
, 1)) >= 0
8325 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8326 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8327 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8328 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8331 /* If the shift count is a constant and we can do arithmetic in
8332 the mode of the shift, refine which bits we need. Otherwise, use the
8333 conservative form of the mask. */
8334 if (CONST_INT_P (XEXP (x
, 1))
8335 && INTVAL (XEXP (x
, 1)) >= 0
8336 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8337 && HWI_COMPUTABLE_MODE_P (op_mode
))
8338 mask
>>= INTVAL (XEXP (x
, 1));
8342 op0
= gen_lowpart_or_truncate (op_mode
,
8343 force_to_mode (XEXP (x
, 0), op_mode
,
8344 mask
, next_select
));
8346 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8347 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8351 /* Here we can only do something if the shift count is a constant,
8352 this shift constant is valid for the host, and we can do arithmetic
8355 if (CONST_INT_P (XEXP (x
, 1))
8356 && INTVAL (XEXP (x
, 1)) >= 0
8357 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8358 && HWI_COMPUTABLE_MODE_P (op_mode
))
8360 rtx inner
= XEXP (x
, 0);
8361 unsigned HOST_WIDE_INT inner_mask
;
8363 /* Select the mask of the bits we need for the shift operand. */
8364 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8366 /* We can only change the mode of the shift if we can do arithmetic
8367 in the mode of the shift and INNER_MASK is no wider than the
8368 width of X's mode. */
8369 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8370 op_mode
= GET_MODE (x
);
8372 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8374 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8375 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8378 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8379 shift and AND produces only copies of the sign bit (C2 is one less
8380 than a power of two), we can do this with just a shift. */
8382 if (GET_CODE (x
) == LSHIFTRT
8383 && CONST_INT_P (XEXP (x
, 1))
8384 /* The shift puts one of the sign bit copies in the least significant
8386 && ((INTVAL (XEXP (x
, 1))
8387 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8388 >= GET_MODE_PRECISION (GET_MODE (x
)))
8389 && exact_log2 (mask
+ 1) >= 0
8390 /* Number of bits left after the shift must be more than the mask
8392 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8393 <= GET_MODE_PRECISION (GET_MODE (x
)))
8394 /* Must be more sign bit copies than the mask needs. */
8395 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8396 >= exact_log2 (mask
+ 1)))
8397 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8398 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8399 - exact_log2 (mask
+ 1)));
8404 /* If we are just looking for the sign bit, we don't need this shift at
8405 all, even if it has a variable count. */
8406 if (val_signbit_p (GET_MODE (x
), mask
))
8407 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8409 /* If this is a shift by a constant, get a mask that contains those bits
8410 that are not copies of the sign bit. We then have two cases: If
8411 MASK only includes those bits, this can be a logical shift, which may
8412 allow simplifications. If MASK is a single-bit field not within
8413 those bits, we are requesting a copy of the sign bit and hence can
8414 shift the sign bit to the appropriate location. */
8416 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8417 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8421 /* If the considered data is wider than HOST_WIDE_INT, we can't
8422 represent a mask for all its bits in a single scalar.
8423 But we only care about the lower bits, so calculate these. */
8425 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8427 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8429 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8430 is the number of bits a full-width mask would have set.
8431 We need only shift if these are fewer than nonzero can
8432 hold. If not, we must keep all bits set in nonzero. */
8434 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8435 < HOST_BITS_PER_WIDE_INT
)
8436 nonzero
>>= INTVAL (XEXP (x
, 1))
8437 + HOST_BITS_PER_WIDE_INT
8438 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8442 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8443 nonzero
>>= INTVAL (XEXP (x
, 1));
8446 if ((mask
& ~nonzero
) == 0)
8448 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8449 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8450 if (GET_CODE (x
) != ASHIFTRT
)
8451 return force_to_mode (x
, mode
, mask
, next_select
);
8454 else if ((i
= exact_log2 (mask
)) >= 0)
8456 x
= simplify_shift_const
8457 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8458 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8460 if (GET_CODE (x
) != ASHIFTRT
)
8461 return force_to_mode (x
, mode
, mask
, next_select
);
8465 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8466 even if the shift count isn't a constant. */
8468 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8469 XEXP (x
, 0), XEXP (x
, 1));
8473 /* If this is a zero- or sign-extension operation that just affects bits
8474 we don't care about, remove it. Be sure the call above returned
8475 something that is still a shift. */
8477 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8478 && CONST_INT_P (XEXP (x
, 1))
8479 && INTVAL (XEXP (x
, 1)) >= 0
8480 && (INTVAL (XEXP (x
, 1))
8481 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8482 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8483 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8484 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8491 /* If the shift count is constant and we can do computations
8492 in the mode of X, compute where the bits we care about are.
8493 Otherwise, we can't do anything. Don't change the mode of
8494 the shift or propagate MODE into the shift, though. */
8495 if (CONST_INT_P (XEXP (x
, 1))
8496 && INTVAL (XEXP (x
, 1)) >= 0)
8498 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8500 gen_int_mode (mask
, GET_MODE (x
)),
8502 if (temp
&& CONST_INT_P (temp
))
8503 x
= simplify_gen_binary (code
, GET_MODE (x
),
8504 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8505 INTVAL (temp
), next_select
),
8511 /* If we just want the low-order bit, the NEG isn't needed since it
8512 won't change the low-order bit. */
8514 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8516 /* We need any bits less significant than the most significant bit in
8517 MASK since carries from those bits will affect the bits we are
8523 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8524 same as the XOR case above. Ensure that the constant we form is not
8525 wider than the mode of X. */
8527 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8528 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8529 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8530 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8531 < GET_MODE_PRECISION (GET_MODE (x
)))
8532 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8534 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8536 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8537 XEXP (XEXP (x
, 0), 0), temp
);
8538 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8539 temp
, XEXP (XEXP (x
, 0), 1));
8541 return force_to_mode (x
, mode
, mask
, next_select
);
8544 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8545 use the full mask inside the NOT. */
8549 op0
= gen_lowpart_or_truncate (op_mode
,
8550 force_to_mode (XEXP (x
, 0), mode
, mask
,
8552 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8553 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8557 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8558 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8559 which is equal to STORE_FLAG_VALUE. */
8560 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8561 && XEXP (x
, 1) == const0_rtx
8562 && GET_MODE (XEXP (x
, 0)) == mode
8563 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8564 && (nonzero_bits (XEXP (x
, 0), mode
)
8565 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8566 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8571 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8572 written in a narrower mode. We play it safe and do not do so. */
8574 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8575 force_to_mode (XEXP (x
, 1), mode
,
8576 mask
, next_select
));
8577 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8578 force_to_mode (XEXP (x
, 2), mode
,
8579 mask
, next_select
));
8580 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8581 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8582 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8590 /* Ensure we return a value of the proper mode. */
8591 return gen_lowpart_or_truncate (mode
, x
);
8594 /* Return nonzero if X is an expression that has one of two values depending on
8595 whether some other value is zero or nonzero. In that case, we return the
8596 value that is being tested, *PTRUE is set to the value if the rtx being
8597 returned has a nonzero value, and *PFALSE is set to the other alternative.
8599 If we return zero, we set *PTRUE and *PFALSE to X. */
8602 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8604 enum machine_mode mode
= GET_MODE (x
);
8605 enum rtx_code code
= GET_CODE (x
);
8606 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8607 unsigned HOST_WIDE_INT nz
;
8609 /* If we are comparing a value against zero, we are done. */
8610 if ((code
== NE
|| code
== EQ
)
8611 && XEXP (x
, 1) == const0_rtx
)
8613 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8614 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8618 /* If this is a unary operation whose operand has one of two values, apply
8619 our opcode to compute those values. */
8620 else if (UNARY_P (x
)
8621 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8623 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8624 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8625 GET_MODE (XEXP (x
, 0)));
8629 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8630 make can't possibly match and would suppress other optimizations. */
8631 else if (code
== COMPARE
)
8634 /* If this is a binary operation, see if either side has only one of two
8635 values. If either one does or if both do and they are conditional on
8636 the same value, compute the new true and false values. */
8637 else if (BINARY_P (x
))
8639 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8640 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8642 if ((cond0
!= 0 || cond1
!= 0)
8643 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8645 /* If if_then_else_cond returned zero, then true/false are the
8646 same rtl. We must copy one of them to prevent invalid rtl
8649 true0
= copy_rtx (true0
);
8650 else if (cond1
== 0)
8651 true1
= copy_rtx (true1
);
8653 if (COMPARISON_P (x
))
8655 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8657 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8662 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8663 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8666 return cond0
? cond0
: cond1
;
8669 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8670 operands is zero when the other is nonzero, and vice-versa,
8671 and STORE_FLAG_VALUE is 1 or -1. */
8673 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8674 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8676 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8678 rtx op0
= XEXP (XEXP (x
, 0), 1);
8679 rtx op1
= XEXP (XEXP (x
, 1), 1);
8681 cond0
= XEXP (XEXP (x
, 0), 0);
8682 cond1
= XEXP (XEXP (x
, 1), 0);
8684 if (COMPARISON_P (cond0
)
8685 && COMPARISON_P (cond1
)
8686 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8687 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8688 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8689 || ((swap_condition (GET_CODE (cond0
))
8690 == reversed_comparison_code (cond1
, NULL
))
8691 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8692 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8693 && ! side_effects_p (x
))
8695 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8696 *pfalse
= simplify_gen_binary (MULT
, mode
,
8698 ? simplify_gen_unary (NEG
, mode
,
8706 /* Similarly for MULT, AND and UMIN, except that for these the result
8708 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8709 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8710 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8712 cond0
= XEXP (XEXP (x
, 0), 0);
8713 cond1
= XEXP (XEXP (x
, 1), 0);
8715 if (COMPARISON_P (cond0
)
8716 && COMPARISON_P (cond1
)
8717 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8718 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8719 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8720 || ((swap_condition (GET_CODE (cond0
))
8721 == reversed_comparison_code (cond1
, NULL
))
8722 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8723 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8724 && ! side_effects_p (x
))
8726 *ptrue
= *pfalse
= const0_rtx
;
8732 else if (code
== IF_THEN_ELSE
)
8734 /* If we have IF_THEN_ELSE already, extract the condition and
8735 canonicalize it if it is NE or EQ. */
8736 cond0
= XEXP (x
, 0);
8737 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8738 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8739 return XEXP (cond0
, 0);
8740 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8742 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8743 return XEXP (cond0
, 0);
8749 /* If X is a SUBREG, we can narrow both the true and false values
8750 if the inner expression, if there is a condition. */
8751 else if (code
== SUBREG
8752 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8755 true0
= simplify_gen_subreg (mode
, true0
,
8756 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8757 false0
= simplify_gen_subreg (mode
, false0
,
8758 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8759 if (true0
&& false0
)
8767 /* If X is a constant, this isn't special and will cause confusions
8768 if we treat it as such. Likewise if it is equivalent to a constant. */
8769 else if (CONSTANT_P (x
)
8770 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8773 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8774 will be least confusing to the rest of the compiler. */
8775 else if (mode
== BImode
)
8777 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8781 /* If X is known to be either 0 or -1, those are the true and
8782 false values when testing X. */
8783 else if (x
== constm1_rtx
|| x
== const0_rtx
8784 || (mode
!= VOIDmode
8785 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8787 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8791 /* Likewise for 0 or a single bit. */
8792 else if (HWI_COMPUTABLE_MODE_P (mode
)
8793 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8795 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8799 /* Otherwise fail; show no condition with true and false values the same. */
8800 *ptrue
= *pfalse
= x
;
8804 /* Return the value of expression X given the fact that condition COND
8805 is known to be true when applied to REG as its first operand and VAL
8806 as its second. X is known to not be shared and so can be modified in
8809 We only handle the simplest cases, and specifically those cases that
8810 arise with IF_THEN_ELSE expressions. */
8813 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8815 enum rtx_code code
= GET_CODE (x
);
8820 if (side_effects_p (x
))
8823 /* If either operand of the condition is a floating point value,
8824 then we have to avoid collapsing an EQ comparison. */
8826 && rtx_equal_p (x
, reg
)
8827 && ! FLOAT_MODE_P (GET_MODE (x
))
8828 && ! FLOAT_MODE_P (GET_MODE (val
)))
8831 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8834 /* If X is (abs REG) and we know something about REG's relationship
8835 with zero, we may be able to simplify this. */
8837 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8840 case GE
: case GT
: case EQ
:
8843 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8845 GET_MODE (XEXP (x
, 0)));
8850 /* The only other cases we handle are MIN, MAX, and comparisons if the
8851 operands are the same as REG and VAL. */
8853 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8855 if (rtx_equal_p (XEXP (x
, 0), val
))
8856 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8858 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8860 if (COMPARISON_P (x
))
8862 if (comparison_dominates_p (cond
, code
))
8863 return const_true_rtx
;
8865 code
= reversed_comparison_code (x
, NULL
);
8867 && comparison_dominates_p (cond
, code
))
8872 else if (code
== SMAX
|| code
== SMIN
8873 || code
== UMIN
|| code
== UMAX
)
8875 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8877 /* Do not reverse the condition when it is NE or EQ.
8878 This is because we cannot conclude anything about
8879 the value of 'SMAX (x, y)' when x is not equal to y,
8880 but we can when x equals y. */
8881 if ((code
== SMAX
|| code
== UMAX
)
8882 && ! (cond
== EQ
|| cond
== NE
))
8883 cond
= reverse_condition (cond
);
8888 return unsignedp
? x
: XEXP (x
, 1);
8890 return unsignedp
? x
: XEXP (x
, 0);
8892 return unsignedp
? XEXP (x
, 1) : x
;
8894 return unsignedp
? XEXP (x
, 0) : x
;
8901 else if (code
== SUBREG
)
8903 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8904 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8906 if (SUBREG_REG (x
) != r
)
8908 /* We must simplify subreg here, before we lose track of the
8909 original inner_mode. */
8910 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8911 inner_mode
, SUBREG_BYTE (x
));
8915 SUBST (SUBREG_REG (x
), r
);
8920 /* We don't have to handle SIGN_EXTEND here, because even in the
8921 case of replacing something with a modeless CONST_INT, a
8922 CONST_INT is already (supposed to be) a valid sign extension for
8923 its narrower mode, which implies it's already properly
8924 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8925 story is different. */
8926 else if (code
== ZERO_EXTEND
)
8928 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8929 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8931 if (XEXP (x
, 0) != r
)
8933 /* We must simplify the zero_extend here, before we lose
8934 track of the original inner_mode. */
8935 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8940 SUBST (XEXP (x
, 0), r
);
8946 fmt
= GET_RTX_FORMAT (code
);
8947 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8950 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8951 else if (fmt
[i
] == 'E')
8952 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8953 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8960 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8961 assignment as a field assignment. */
8964 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8966 if (x
== y
|| rtx_equal_p (x
, y
))
8969 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8972 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8973 Note that all SUBREGs of MEM are paradoxical; otherwise they
8974 would have been rewritten. */
8975 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8976 && MEM_P (SUBREG_REG (y
))
8977 && rtx_equal_p (SUBREG_REG (y
),
8978 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8981 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8982 && MEM_P (SUBREG_REG (x
))
8983 && rtx_equal_p (SUBREG_REG (x
),
8984 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8987 /* We used to see if get_last_value of X and Y were the same but that's
8988 not correct. In one direction, we'll cause the assignment to have
8989 the wrong destination and in the case, we'll import a register into this
8990 insn that might have already have been dead. So fail if none of the
8991 above cases are true. */
8995 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8996 Return that assignment if so.
8998 We only handle the most common cases. */
9001 make_field_assignment (rtx x
)
9003 rtx dest
= SET_DEST (x
);
9004 rtx src
= SET_SRC (x
);
9009 unsigned HOST_WIDE_INT len
;
9011 enum machine_mode mode
;
9013 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9014 a clear of a one-bit field. We will have changed it to
9015 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9018 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9019 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9020 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9021 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9023 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9026 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9030 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9031 && subreg_lowpart_p (XEXP (src
, 0))
9032 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9033 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9034 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9035 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9036 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9037 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9039 assign
= make_extraction (VOIDmode
, dest
, 0,
9040 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9043 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
9047 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9049 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9050 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9051 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9053 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9056 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9060 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9061 SRC is an AND with all bits of that field set, then we can discard
9063 if (GET_CODE (dest
) == ZERO_EXTRACT
9064 && CONST_INT_P (XEXP (dest
, 1))
9065 && GET_CODE (src
) == AND
9066 && CONST_INT_P (XEXP (src
, 1)))
9068 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9069 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9070 unsigned HOST_WIDE_INT ze_mask
;
9072 if (width
>= HOST_BITS_PER_WIDE_INT
)
9075 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9077 /* Complete overlap. We can remove the source AND. */
9078 if ((and_mask
& ze_mask
) == ze_mask
)
9079 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9081 /* Partial overlap. We can reduce the source AND. */
9082 if ((and_mask
& ze_mask
) != and_mask
)
9084 mode
= GET_MODE (src
);
9085 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9086 gen_int_mode (and_mask
& ze_mask
, mode
));
9087 return gen_rtx_SET (VOIDmode
, dest
, src
);
9091 /* The other case we handle is assignments into a constant-position
9092 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9093 a mask that has all one bits except for a group of zero bits and
9094 OTHER is known to have zeros where C1 has ones, this is such an
9095 assignment. Compute the position and length from C1. Shift OTHER
9096 to the appropriate position, force it to the required mode, and
9097 make the extraction. Check for the AND in both operands. */
9099 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9102 rhs
= expand_compound_operation (XEXP (src
, 0));
9103 lhs
= expand_compound_operation (XEXP (src
, 1));
9105 if (GET_CODE (rhs
) == AND
9106 && CONST_INT_P (XEXP (rhs
, 1))
9107 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9108 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9109 else if (GET_CODE (lhs
) == AND
9110 && CONST_INT_P (XEXP (lhs
, 1))
9111 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9112 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9116 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9117 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9118 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9119 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9122 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9126 /* The mode to use for the source is the mode of the assignment, or of
9127 what is inside a possible STRICT_LOW_PART. */
9128 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9129 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9131 /* Shift OTHER right POS places and make it the source, restricting it
9132 to the proper length and mode. */
9134 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9138 src
= force_to_mode (src
, mode
,
9139 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9140 ? ~(unsigned HOST_WIDE_INT
) 0
9141 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9144 /* If SRC is masked by an AND that does not make a difference in
9145 the value being stored, strip it. */
9146 if (GET_CODE (assign
) == ZERO_EXTRACT
9147 && CONST_INT_P (XEXP (assign
, 1))
9148 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9149 && GET_CODE (src
) == AND
9150 && CONST_INT_P (XEXP (src
, 1))
9151 && UINTVAL (XEXP (src
, 1))
9152 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9153 src
= XEXP (src
, 0);
9155 return gen_rtx_SET (VOIDmode
, assign
, src
);
9158 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9162 apply_distributive_law (rtx x
)
9164 enum rtx_code code
= GET_CODE (x
);
9165 enum rtx_code inner_code
;
9166 rtx lhs
, rhs
, other
;
9169 /* Distributivity is not true for floating point as it can change the
9170 value. So we don't do it unless -funsafe-math-optimizations. */
9171 if (FLOAT_MODE_P (GET_MODE (x
))
9172 && ! flag_unsafe_math_optimizations
)
9175 /* The outer operation can only be one of the following: */
9176 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9177 && code
!= PLUS
&& code
!= MINUS
)
9183 /* If either operand is a primitive we can't do anything, so get out
9185 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9188 lhs
= expand_compound_operation (lhs
);
9189 rhs
= expand_compound_operation (rhs
);
9190 inner_code
= GET_CODE (lhs
);
9191 if (inner_code
!= GET_CODE (rhs
))
9194 /* See if the inner and outer operations distribute. */
9201 /* These all distribute except over PLUS. */
9202 if (code
== PLUS
|| code
== MINUS
)
9207 if (code
!= PLUS
&& code
!= MINUS
)
9212 /* This is also a multiply, so it distributes over everything. */
9215 /* This used to handle SUBREG, but this turned out to be counter-
9216 productive, since (subreg (op ...)) usually is not handled by
9217 insn patterns, and this "optimization" therefore transformed
9218 recognizable patterns into unrecognizable ones. Therefore the
9219 SUBREG case was removed from here.
9221 It is possible that distributing SUBREG over arithmetic operations
9222 leads to an intermediate result than can then be optimized further,
9223 e.g. by moving the outer SUBREG to the other side of a SET as done
9224 in simplify_set. This seems to have been the original intent of
9225 handling SUBREGs here.
9227 However, with current GCC this does not appear to actually happen,
9228 at least on major platforms. If some case is found where removing
9229 the SUBREG case here prevents follow-on optimizations, distributing
9230 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9236 /* Set LHS and RHS to the inner operands (A and B in the example
9237 above) and set OTHER to the common operand (C in the example).
9238 There is only one way to do this unless the inner operation is
9240 if (COMMUTATIVE_ARITH_P (lhs
)
9241 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9242 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9243 else if (COMMUTATIVE_ARITH_P (lhs
)
9244 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9245 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9246 else if (COMMUTATIVE_ARITH_P (lhs
)
9247 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9248 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9249 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9250 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9254 /* Form the new inner operation, seeing if it simplifies first. */
9255 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9257 /* There is one exception to the general way of distributing:
9258 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9259 if (code
== XOR
&& inner_code
== IOR
)
9262 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9265 /* We may be able to continuing distributing the result, so call
9266 ourselves recursively on the inner operation before forming the
9267 outer operation, which we return. */
9268 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9269 apply_distributive_law (tem
), other
);
9272 /* See if X is of the form (* (+ A B) C), and if so convert to
9273 (+ (* A C) (* B C)) and try to simplify.
9275 Most of the time, this results in no change. However, if some of
9276 the operands are the same or inverses of each other, simplifications
9279 For example, (and (ior A B) (not B)) can occur as the result of
9280 expanding a bit field assignment. When we apply the distributive
9281 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9282 which then simplifies to (and (A (not B))).
9284 Note that no checks happen on the validity of applying the inverse
9285 distributive law. This is pointless since we can do it in the
9286 few places where this routine is called.
9288 N is the index of the term that is decomposed (the arithmetic operation,
9289 i.e. (+ A B) in the first example above). !N is the index of the term that
9290 is distributed, i.e. of C in the first example above. */
9292 distribute_and_simplify_rtx (rtx x
, int n
)
9294 enum machine_mode mode
;
9295 enum rtx_code outer_code
, inner_code
;
9296 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9298 /* Distributivity is not true for floating point as it can change the
9299 value. So we don't do it unless -funsafe-math-optimizations. */
9300 if (FLOAT_MODE_P (GET_MODE (x
))
9301 && ! flag_unsafe_math_optimizations
)
9304 decomposed
= XEXP (x
, n
);
9305 if (!ARITHMETIC_P (decomposed
))
9308 mode
= GET_MODE (x
);
9309 outer_code
= GET_CODE (x
);
9310 distributed
= XEXP (x
, !n
);
9312 inner_code
= GET_CODE (decomposed
);
9313 inner_op0
= XEXP (decomposed
, 0);
9314 inner_op1
= XEXP (decomposed
, 1);
9316 /* Special case (and (xor B C) (not A)), which is equivalent to
9317 (xor (ior A B) (ior A C)) */
9318 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9320 distributed
= XEXP (distributed
, 0);
9326 /* Distribute the second term. */
9327 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9328 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9332 /* Distribute the first term. */
9333 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9334 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9337 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9339 if (GET_CODE (tmp
) != outer_code
9340 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9341 < set_src_cost (x
, optimize_this_for_speed_p
)))
9347 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9348 in MODE. Return an equivalent form, if different from (and VAROP
9349 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9352 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9353 unsigned HOST_WIDE_INT constop
)
9355 unsigned HOST_WIDE_INT nonzero
;
9356 unsigned HOST_WIDE_INT orig_constop
;
9361 orig_constop
= constop
;
9362 if (GET_CODE (varop
) == CLOBBER
)
9365 /* Simplify VAROP knowing that we will be only looking at some of the
9368 Note by passing in CONSTOP, we guarantee that the bits not set in
9369 CONSTOP are not significant and will never be examined. We must
9370 ensure that is the case by explicitly masking out those bits
9371 before returning. */
9372 varop
= force_to_mode (varop
, mode
, constop
, 0);
9374 /* If VAROP is a CLOBBER, we will fail so return it. */
9375 if (GET_CODE (varop
) == CLOBBER
)
9378 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9379 to VAROP and return the new constant. */
9380 if (CONST_INT_P (varop
))
9381 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9383 /* See what bits may be nonzero in VAROP. Unlike the general case of
9384 a call to nonzero_bits, here we don't care about bits outside
9387 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9389 /* Turn off all bits in the constant that are known to already be zero.
9390 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9391 which is tested below. */
9395 /* If we don't have any bits left, return zero. */
9399 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9400 a power of two, we can replace this with an ASHIFT. */
9401 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9402 && (i
= exact_log2 (constop
)) >= 0)
9403 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9405 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9406 or XOR, then try to apply the distributive law. This may eliminate
9407 operations if either branch can be simplified because of the AND.
9408 It may also make some cases more complex, but those cases probably
9409 won't match a pattern either with or without this. */
9411 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9415 apply_distributive_law
9416 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9417 simplify_and_const_int (NULL_RTX
,
9421 simplify_and_const_int (NULL_RTX
,
9426 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9427 the AND and see if one of the operands simplifies to zero. If so, we
9428 may eliminate it. */
9430 if (GET_CODE (varop
) == PLUS
9431 && exact_log2 (constop
+ 1) >= 0)
9435 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9436 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9437 if (o0
== const0_rtx
)
9439 if (o1
== const0_rtx
)
9443 /* Make a SUBREG if necessary. If we can't make it, fail. */
9444 varop
= gen_lowpart (mode
, varop
);
9445 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9448 /* If we are only masking insignificant bits, return VAROP. */
9449 if (constop
== nonzero
)
9452 if (varop
== orig_varop
&& constop
== orig_constop
)
9455 /* Otherwise, return an AND. */
9456 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9460 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9463 Return an equivalent form, if different from X. Otherwise, return X. If
9464 X is zero, we are to always construct the equivalent form. */
9467 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9468 unsigned HOST_WIDE_INT constop
)
9470 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9475 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9476 gen_int_mode (constop
, mode
));
9477 if (GET_MODE (x
) != mode
)
9478 x
= gen_lowpart (mode
, x
);
9482 /* Given a REG, X, compute which bits in X can be nonzero.
9483 We don't care about bits outside of those defined in MODE.
9485 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9486 a shift, AND, or zero_extract, we can do better. */
9489 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9490 const_rtx known_x ATTRIBUTE_UNUSED
,
9491 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9492 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9493 unsigned HOST_WIDE_INT
*nonzero
)
9498 /* If X is a register whose nonzero bits value is current, use it.
9499 Otherwise, if X is a register whose value we can find, use that
9500 value. Otherwise, use the previously-computed global nonzero bits
9501 for this register. */
9503 rsp
= ®_stat
[REGNO (x
)];
9504 if (rsp
->last_set_value
!= 0
9505 && (rsp
->last_set_mode
== mode
9506 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9507 && GET_MODE_CLASS (mode
) == MODE_INT
))
9508 && ((rsp
->last_set_label
>= label_tick_ebb_start
9509 && rsp
->last_set_label
< label_tick
)
9510 || (rsp
->last_set_label
== label_tick
9511 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9512 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9513 && REG_N_SETS (REGNO (x
)) == 1
9515 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9518 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9520 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9521 /* We don't know anything about the upper bits. */
9522 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9528 tem
= get_last_value (x
);
9532 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9533 /* If X is narrower than MODE and TEM is a non-negative
9534 constant that would appear negative in the mode of X,
9535 sign-extend it for use in reg_nonzero_bits because some
9536 machines (maybe most) will actually do the sign-extension
9537 and this is the conservative approach.
9539 ??? For 2.5, try to tighten up the MD files in this regard
9540 instead of this kludge. */
9542 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9543 && CONST_INT_P (tem
)
9545 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9546 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9550 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9552 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9554 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9555 /* We don't know anything about the upper bits. */
9556 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9564 /* Return the number of bits at the high-order end of X that are known to
9565 be equal to the sign bit. X will be used in mode MODE; if MODE is
9566 VOIDmode, X will be used in its own mode. The returned value will always
9567 be between 1 and the number of bits in MODE. */
9570 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9571 const_rtx known_x ATTRIBUTE_UNUSED
,
9572 enum machine_mode known_mode
9574 unsigned int known_ret ATTRIBUTE_UNUSED
,
9575 unsigned int *result
)
9580 rsp
= ®_stat
[REGNO (x
)];
9581 if (rsp
->last_set_value
!= 0
9582 && rsp
->last_set_mode
== mode
9583 && ((rsp
->last_set_label
>= label_tick_ebb_start
9584 && rsp
->last_set_label
< label_tick
)
9585 || (rsp
->last_set_label
== label_tick
9586 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9587 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9588 && REG_N_SETS (REGNO (x
)) == 1
9590 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9593 *result
= rsp
->last_set_sign_bit_copies
;
9597 tem
= get_last_value (x
);
9601 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9602 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9603 *result
= rsp
->sign_bit_copies
;
9608 /* Return the number of "extended" bits there are in X, when interpreted
9609 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9610 unsigned quantities, this is the number of high-order zero bits.
9611 For signed quantities, this is the number of copies of the sign bit
9612 minus 1. In both case, this function returns the number of "spare"
9613 bits. For example, if two quantities for which this function returns
9614 at least 1 are added, the addition is known not to overflow.
9616 This function will always return 0 unless called during combine, which
9617 implies that it must be called from a define_split. */
9620 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9622 if (nonzero_sign_valid
== 0)
9626 ? (HWI_COMPUTABLE_MODE_P (mode
)
9627 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9628 - floor_log2 (nonzero_bits (x
, mode
)))
9630 : num_sign_bit_copies (x
, mode
) - 1);
9633 /* This function is called from `simplify_shift_const' to merge two
9634 outer operations. Specifically, we have already found that we need
9635 to perform operation *POP0 with constant *PCONST0 at the outermost
9636 position. We would now like to also perform OP1 with constant CONST1
9637 (with *POP0 being done last).
9639 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9640 the resulting operation. *PCOMP_P is set to 1 if we would need to
9641 complement the innermost operand, otherwise it is unchanged.
9643 MODE is the mode in which the operation will be done. No bits outside
9644 the width of this mode matter. It is assumed that the width of this mode
9645 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9647 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9648 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9649 result is simply *PCONST0.
9651 If the resulting operation cannot be expressed as one operation, we
9652 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9655 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9657 enum rtx_code op0
= *pop0
;
9658 HOST_WIDE_INT const0
= *pconst0
;
9660 const0
&= GET_MODE_MASK (mode
);
9661 const1
&= GET_MODE_MASK (mode
);
9663 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9667 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9670 if (op1
== UNKNOWN
|| op0
== SET
)
9673 else if (op0
== UNKNOWN
)
9674 op0
= op1
, const0
= const1
;
9676 else if (op0
== op1
)
9700 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9701 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9704 /* If the two constants aren't the same, we can't do anything. The
9705 remaining six cases can all be done. */
9706 else if (const0
!= const1
)
9714 /* (a & b) | b == b */
9716 else /* op1 == XOR */
9717 /* (a ^ b) | b == a | b */
9723 /* (a & b) ^ b == (~a) & b */
9724 op0
= AND
, *pcomp_p
= 1;
9725 else /* op1 == IOR */
9726 /* (a | b) ^ b == a & ~b */
9727 op0
= AND
, const0
= ~const0
;
9732 /* (a | b) & b == b */
9734 else /* op1 == XOR */
9735 /* (a ^ b) & b) == (~a) & b */
9742 /* Check for NO-OP cases. */
9743 const0
&= GET_MODE_MASK (mode
);
9745 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9747 else if (const0
== 0 && op0
== AND
)
9749 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9755 /* ??? Slightly redundant with the above mask, but not entirely.
9756 Moving this above means we'd have to sign-extend the mode mask
9757 for the final test. */
9758 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9759 *pconst0
= trunc_int_for_mode (const0
, mode
);
9764 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9765 the shift in. The original shift operation CODE is performed on OP in
9766 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9767 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9768 result of the shift is subject to operation OUTER_CODE with operand
9771 static enum machine_mode
9772 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9773 enum machine_mode orig_mode
, enum machine_mode mode
,
9774 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9776 if (orig_mode
== mode
)
9778 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9780 /* In general we can't perform in wider mode for right shift and rotate. */
9784 /* We can still widen if the bits brought in from the left are identical
9785 to the sign bit of ORIG_MODE. */
9786 if (num_sign_bit_copies (op
, mode
)
9787 > (unsigned) (GET_MODE_PRECISION (mode
)
9788 - GET_MODE_PRECISION (orig_mode
)))
9793 /* Similarly here but with zero bits. */
9794 if (HWI_COMPUTABLE_MODE_P (mode
)
9795 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9798 /* We can also widen if the bits brought in will be masked off. This
9799 operation is performed in ORIG_MODE. */
9800 if (outer_code
== AND
)
9802 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9805 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9821 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9822 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9823 if we cannot simplify it. Otherwise, return a simplified value.
9825 The shift is normally computed in the widest mode we find in VAROP, as
9826 long as it isn't a different number of words than RESULT_MODE. Exceptions
9827 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9830 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9831 rtx varop
, int orig_count
)
9833 enum rtx_code orig_code
= code
;
9834 rtx orig_varop
= varop
;
9836 enum machine_mode mode
= result_mode
;
9837 enum machine_mode shift_mode
, tmode
;
9838 unsigned int mode_words
9839 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9840 /* We form (outer_op (code varop count) (outer_const)). */
9841 enum rtx_code outer_op
= UNKNOWN
;
9842 HOST_WIDE_INT outer_const
= 0;
9843 int complement_p
= 0;
9846 /* Make sure and truncate the "natural" shift on the way in. We don't
9847 want to do this inside the loop as it makes it more difficult to
9849 if (SHIFT_COUNT_TRUNCATED
)
9850 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9852 /* If we were given an invalid count, don't do anything except exactly
9853 what was requested. */
9855 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9860 /* Unless one of the branches of the `if' in this loop does a `continue',
9861 we will `break' the loop after the `if'. */
9865 /* If we have an operand of (clobber (const_int 0)), fail. */
9866 if (GET_CODE (varop
) == CLOBBER
)
9869 /* Convert ROTATERT to ROTATE. */
9870 if (code
== ROTATERT
)
9872 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9874 if (VECTOR_MODE_P (result_mode
))
9875 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9877 count
= bitsize
- count
;
9880 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9881 mode
, outer_op
, outer_const
);
9883 /* Handle cases where the count is greater than the size of the mode
9884 minus 1. For ASHIFT, use the size minus one as the count (this can
9885 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9886 take the count modulo the size. For other shifts, the result is
9889 Since these shifts are being produced by the compiler by combining
9890 multiple operations, each of which are defined, we know what the
9891 result is supposed to be. */
9893 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9895 if (code
== ASHIFTRT
)
9896 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9897 else if (code
== ROTATE
|| code
== ROTATERT
)
9898 count
%= GET_MODE_PRECISION (shift_mode
);
9901 /* We can't simply return zero because there may be an
9909 /* If we discovered we had to complement VAROP, leave. Making a NOT
9910 here would cause an infinite loop. */
9914 /* An arithmetic right shift of a quantity known to be -1 or 0
9916 if (code
== ASHIFTRT
9917 && (num_sign_bit_copies (varop
, shift_mode
)
9918 == GET_MODE_PRECISION (shift_mode
)))
9924 /* If we are doing an arithmetic right shift and discarding all but
9925 the sign bit copies, this is equivalent to doing a shift by the
9926 bitsize minus one. Convert it into that shift because it will often
9927 allow other simplifications. */
9929 if (code
== ASHIFTRT
9930 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9931 >= GET_MODE_PRECISION (shift_mode
)))
9932 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9934 /* We simplify the tests below and elsewhere by converting
9935 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9936 `make_compound_operation' will convert it to an ASHIFTRT for
9937 those machines (such as VAX) that don't have an LSHIFTRT. */
9938 if (code
== ASHIFTRT
9939 && val_signbit_known_clear_p (shift_mode
,
9940 nonzero_bits (varop
, shift_mode
)))
9943 if (((code
== LSHIFTRT
9944 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9945 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9947 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9948 && !((nonzero_bits (varop
, shift_mode
) << count
)
9949 & GET_MODE_MASK (shift_mode
))))
9950 && !side_effects_p (varop
))
9953 switch (GET_CODE (varop
))
9959 new_rtx
= expand_compound_operation (varop
);
9960 if (new_rtx
!= varop
)
9968 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9969 minus the width of a smaller mode, we can do this with a
9970 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9971 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9972 && ! mode_dependent_address_p (XEXP (varop
, 0),
9973 MEM_ADDR_SPACE (varop
))
9974 && ! MEM_VOLATILE_P (varop
)
9975 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9976 MODE_INT
, 1)) != BLKmode
)
9978 new_rtx
= adjust_address_nv (varop
, tmode
,
9979 BYTES_BIG_ENDIAN
? 0
9980 : count
/ BITS_PER_UNIT
);
9982 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9983 : ZERO_EXTEND
, mode
, new_rtx
);
9990 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9991 the same number of words as what we've seen so far. Then store
9992 the widest mode in MODE. */
9993 if (subreg_lowpart_p (varop
)
9994 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9995 > GET_MODE_SIZE (GET_MODE (varop
)))
9996 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9997 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9999 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10000 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10002 varop
= SUBREG_REG (varop
);
10003 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10004 mode
= GET_MODE (varop
);
10010 /* Some machines use MULT instead of ASHIFT because MULT
10011 is cheaper. But it is still better on those machines to
10012 merge two shifts into one. */
10013 if (CONST_INT_P (XEXP (varop
, 1))
10014 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10017 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10019 GEN_INT (exact_log2 (
10020 UINTVAL (XEXP (varop
, 1)))));
10026 /* Similar, for when divides are cheaper. */
10027 if (CONST_INT_P (XEXP (varop
, 1))
10028 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10031 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10033 GEN_INT (exact_log2 (
10034 UINTVAL (XEXP (varop
, 1)))));
10040 /* If we are extracting just the sign bit of an arithmetic
10041 right shift, that shift is not needed. However, the sign
10042 bit of a wider mode may be different from what would be
10043 interpreted as the sign bit in a narrower mode, so, if
10044 the result is narrower, don't discard the shift. */
10045 if (code
== LSHIFTRT
10046 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10047 && (GET_MODE_BITSIZE (result_mode
)
10048 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10050 varop
= XEXP (varop
, 0);
10054 /* ... fall through ... */
10059 /* Here we have two nested shifts. The result is usually the
10060 AND of a new shift with a mask. We compute the result below. */
10061 if (CONST_INT_P (XEXP (varop
, 1))
10062 && INTVAL (XEXP (varop
, 1)) >= 0
10063 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10064 && HWI_COMPUTABLE_MODE_P (result_mode
)
10065 && HWI_COMPUTABLE_MODE_P (mode
)
10066 && !VECTOR_MODE_P (result_mode
))
10068 enum rtx_code first_code
= GET_CODE (varop
);
10069 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10070 unsigned HOST_WIDE_INT mask
;
10073 /* We have one common special case. We can't do any merging if
10074 the inner code is an ASHIFTRT of a smaller mode. However, if
10075 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10076 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10077 we can convert it to
10078 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10079 This simplifies certain SIGN_EXTEND operations. */
10080 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10081 && count
== (GET_MODE_PRECISION (result_mode
)
10082 - GET_MODE_PRECISION (GET_MODE (varop
))))
10084 /* C3 has the low-order C1 bits zero. */
10086 mask
= GET_MODE_MASK (mode
)
10087 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10089 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10090 XEXP (varop
, 0), mask
);
10091 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10093 count
= first_count
;
10098 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10099 than C1 high-order bits equal to the sign bit, we can convert
10100 this to either an ASHIFT or an ASHIFTRT depending on the
10103 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10105 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10106 && GET_MODE (varop
) == shift_mode
10107 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10110 varop
= XEXP (varop
, 0);
10111 count
-= first_count
;
10121 /* There are some cases we can't do. If CODE is ASHIFTRT,
10122 we can only do this if FIRST_CODE is also ASHIFTRT.
10124 We can't do the case when CODE is ROTATE and FIRST_CODE is
10127 If the mode of this shift is not the mode of the outer shift,
10128 we can't do this if either shift is a right shift or ROTATE.
10130 Finally, we can't do any of these if the mode is too wide
10131 unless the codes are the same.
10133 Handle the case where the shift codes are the same
10136 if (code
== first_code
)
10138 if (GET_MODE (varop
) != result_mode
10139 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10140 || code
== ROTATE
))
10143 count
+= first_count
;
10144 varop
= XEXP (varop
, 0);
10148 if (code
== ASHIFTRT
10149 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10150 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10151 || (GET_MODE (varop
) != result_mode
10152 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10153 || first_code
== ROTATE
10154 || code
== ROTATE
)))
10157 /* To compute the mask to apply after the shift, shift the
10158 nonzero bits of the inner shift the same way the
10159 outer shift will. */
10161 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10165 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10168 /* Give up if we can't compute an outer operation to use. */
10170 || !CONST_INT_P (mask_rtx
)
10171 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10173 result_mode
, &complement_p
))
10176 /* If the shifts are in the same direction, we add the
10177 counts. Otherwise, we subtract them. */
10178 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10179 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10180 count
+= first_count
;
10182 count
-= first_count
;
10184 /* If COUNT is positive, the new shift is usually CODE,
10185 except for the two exceptions below, in which case it is
10186 FIRST_CODE. If the count is negative, FIRST_CODE should
10189 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10190 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10192 else if (count
< 0)
10193 code
= first_code
, count
= -count
;
10195 varop
= XEXP (varop
, 0);
10199 /* If we have (A << B << C) for any shift, we can convert this to
10200 (A << C << B). This wins if A is a constant. Only try this if
10201 B is not a constant. */
10203 else if (GET_CODE (varop
) == code
10204 && CONST_INT_P (XEXP (varop
, 0))
10205 && !CONST_INT_P (XEXP (varop
, 1)))
10207 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10210 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10217 if (VECTOR_MODE_P (mode
))
10220 /* Make this fit the case below. */
10221 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10227 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10228 with C the size of VAROP - 1 and the shift is logical if
10229 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10230 we have an (le X 0) operation. If we have an arithmetic shift
10231 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10232 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10234 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10235 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10236 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10237 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10238 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10239 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10242 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10245 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10246 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10251 /* If we have (shift (logical)), move the logical to the outside
10252 to allow it to possibly combine with another logical and the
10253 shift to combine with another shift. This also canonicalizes to
10254 what a ZERO_EXTRACT looks like. Also, some machines have
10255 (and (shift)) insns. */
10257 if (CONST_INT_P (XEXP (varop
, 1))
10258 /* We can't do this if we have (ashiftrt (xor)) and the
10259 constant has its sign bit set in shift_mode. */
10260 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10261 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10263 && (new_rtx
= simplify_const_binary_operation
10264 (code
, result_mode
,
10265 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10266 GEN_INT (count
))) != 0
10267 && CONST_INT_P (new_rtx
)
10268 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10269 INTVAL (new_rtx
), result_mode
, &complement_p
))
10271 varop
= XEXP (varop
, 0);
10275 /* If we can't do that, try to simplify the shift in each arm of the
10276 logical expression, make a new logical expression, and apply
10277 the inverse distributive law. This also can't be done
10278 for some (ashiftrt (xor)). */
10279 if (CONST_INT_P (XEXP (varop
, 1))
10280 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10281 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10284 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10285 XEXP (varop
, 0), count
);
10286 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10287 XEXP (varop
, 1), count
);
10289 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10291 varop
= apply_distributive_law (varop
);
10299 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10300 says that the sign bit can be tested, FOO has mode MODE, C is
10301 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10302 that may be nonzero. */
10303 if (code
== LSHIFTRT
10304 && XEXP (varop
, 1) == const0_rtx
10305 && GET_MODE (XEXP (varop
, 0)) == result_mode
10306 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10307 && HWI_COMPUTABLE_MODE_P (result_mode
)
10308 && STORE_FLAG_VALUE
== -1
10309 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10310 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10313 varop
= XEXP (varop
, 0);
10320 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10321 than the number of bits in the mode is equivalent to A. */
10322 if (code
== LSHIFTRT
10323 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10324 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10326 varop
= XEXP (varop
, 0);
10331 /* NEG commutes with ASHIFT since it is multiplication. Move the
10332 NEG outside to allow shifts to combine. */
10334 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10337 varop
= XEXP (varop
, 0);
10343 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10344 is one less than the number of bits in the mode is
10345 equivalent to (xor A 1). */
10346 if (code
== LSHIFTRT
10347 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10348 && XEXP (varop
, 1) == constm1_rtx
10349 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10350 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10354 varop
= XEXP (varop
, 0);
10358 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10359 that might be nonzero in BAR are those being shifted out and those
10360 bits are known zero in FOO, we can replace the PLUS with FOO.
10361 Similarly in the other operand order. This code occurs when
10362 we are computing the size of a variable-size array. */
10364 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10365 && count
< HOST_BITS_PER_WIDE_INT
10366 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10367 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10368 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10370 varop
= XEXP (varop
, 0);
10373 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10374 && count
< HOST_BITS_PER_WIDE_INT
10375 && HWI_COMPUTABLE_MODE_P (result_mode
)
10376 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10378 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10379 & nonzero_bits (XEXP (varop
, 1),
10382 varop
= XEXP (varop
, 1);
10386 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10388 && CONST_INT_P (XEXP (varop
, 1))
10389 && (new_rtx
= simplify_const_binary_operation
10390 (ASHIFT
, result_mode
,
10391 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10392 GEN_INT (count
))) != 0
10393 && CONST_INT_P (new_rtx
)
10394 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10395 INTVAL (new_rtx
), result_mode
, &complement_p
))
10397 varop
= XEXP (varop
, 0);
10401 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10402 signbit', and attempt to change the PLUS to an XOR and move it to
10403 the outer operation as is done above in the AND/IOR/XOR case
10404 leg for shift(logical). See details in logical handling above
10405 for reasoning in doing so. */
10406 if (code
== LSHIFTRT
10407 && CONST_INT_P (XEXP (varop
, 1))
10408 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10409 && (new_rtx
= simplify_const_binary_operation
10410 (code
, result_mode
,
10411 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10412 GEN_INT (count
))) != 0
10413 && CONST_INT_P (new_rtx
)
10414 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10415 INTVAL (new_rtx
), result_mode
, &complement_p
))
10417 varop
= XEXP (varop
, 0);
10424 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10425 with C the size of VAROP - 1 and the shift is logical if
10426 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10427 we have a (gt X 0) operation. If the shift is arithmetic with
10428 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10429 we have a (neg (gt X 0)) operation. */
10431 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10432 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10433 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10434 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10435 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10436 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10437 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10440 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10443 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10444 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10451 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10452 if the truncate does not affect the value. */
10453 if (code
== LSHIFTRT
10454 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10455 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10456 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10457 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10458 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10460 rtx varop_inner
= XEXP (varop
, 0);
10463 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10464 XEXP (varop_inner
, 0),
10466 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10467 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10480 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10481 outer_op
, outer_const
);
10483 /* We have now finished analyzing the shift. The result should be
10484 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10485 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10486 to the result of the shift. OUTER_CONST is the relevant constant,
10487 but we must turn off all bits turned off in the shift. */
10489 if (outer_op
== UNKNOWN
10490 && orig_code
== code
&& orig_count
== count
10491 && varop
== orig_varop
10492 && shift_mode
== GET_MODE (varop
))
10495 /* Make a SUBREG if necessary. If we can't make it, fail. */
10496 varop
= gen_lowpart (shift_mode
, varop
);
10497 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10500 /* If we have an outer operation and we just made a shift, it is
10501 possible that we could have simplified the shift were it not
10502 for the outer operation. So try to do the simplification
10505 if (outer_op
!= UNKNOWN
)
10506 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10511 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10513 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10514 turn off all the bits that the shift would have turned off. */
10515 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10516 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10517 GET_MODE_MASK (result_mode
) >> orig_count
);
10519 /* Do the remainder of the processing in RESULT_MODE. */
10520 x
= gen_lowpart_or_truncate (result_mode
, x
);
10522 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10525 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10527 if (outer_op
!= UNKNOWN
)
10529 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10530 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10531 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10533 if (outer_op
== AND
)
10534 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10535 else if (outer_op
== SET
)
10537 /* This means that we have determined that the result is
10538 equivalent to a constant. This should be rare. */
10539 if (!side_effects_p (x
))
10540 x
= GEN_INT (outer_const
);
10542 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10543 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10545 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10546 GEN_INT (outer_const
));
10552 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10553 The result of the shift is RESULT_MODE. If we cannot simplify it,
10554 return X or, if it is NULL, synthesize the expression with
10555 simplify_gen_binary. Otherwise, return a simplified value.
10557 The shift is normally computed in the widest mode we find in VAROP, as
10558 long as it isn't a different number of words than RESULT_MODE. Exceptions
10559 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10562 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10563 rtx varop
, int count
)
10565 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10570 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10571 if (GET_MODE (x
) != result_mode
)
10572 x
= gen_lowpart (result_mode
, x
);
10577 /* Like recog, but we receive the address of a pointer to a new pattern.
10578 We try to match the rtx that the pointer points to.
10579 If that fails, we may try to modify or replace the pattern,
10580 storing the replacement into the same pointer object.
10582 Modifications include deletion or addition of CLOBBERs.
10584 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10585 the CLOBBERs are placed.
10587 The value is the final insn code from the pattern ultimately matched,
10591 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10593 rtx pat
= *pnewpat
;
10594 rtx pat_without_clobbers
;
10595 int insn_code_number
;
10596 int num_clobbers_to_add
= 0;
10598 rtx notes
= NULL_RTX
;
10599 rtx old_notes
, old_pat
;
10602 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10603 we use to indicate that something didn't match. If we find such a
10604 thing, force rejection. */
10605 if (GET_CODE (pat
) == PARALLEL
)
10606 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10607 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10608 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10611 old_pat
= PATTERN (insn
);
10612 old_notes
= REG_NOTES (insn
);
10613 PATTERN (insn
) = pat
;
10614 REG_NOTES (insn
) = NULL_RTX
;
10616 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10617 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10619 if (insn_code_number
< 0)
10620 fputs ("Failed to match this instruction:\n", dump_file
);
10622 fputs ("Successfully matched this instruction:\n", dump_file
);
10623 print_rtl_single (dump_file
, pat
);
10626 /* If it isn't, there is the possibility that we previously had an insn
10627 that clobbered some register as a side effect, but the combined
10628 insn doesn't need to do that. So try once more without the clobbers
10629 unless this represents an ASM insn. */
10631 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10632 && GET_CODE (pat
) == PARALLEL
)
10636 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10637 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10640 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10644 SUBST_INT (XVECLEN (pat
, 0), pos
);
10647 pat
= XVECEXP (pat
, 0, 0);
10649 PATTERN (insn
) = pat
;
10650 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10651 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10653 if (insn_code_number
< 0)
10654 fputs ("Failed to match this instruction:\n", dump_file
);
10656 fputs ("Successfully matched this instruction:\n", dump_file
);
10657 print_rtl_single (dump_file
, pat
);
10661 pat_without_clobbers
= pat
;
10663 PATTERN (insn
) = old_pat
;
10664 REG_NOTES (insn
) = old_notes
;
10666 /* Recognize all noop sets, these will be killed by followup pass. */
10667 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10668 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10670 /* If we had any clobbers to add, make a new pattern than contains
10671 them. Then check to make sure that all of them are dead. */
10672 if (num_clobbers_to_add
)
10674 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10675 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10676 ? (XVECLEN (pat
, 0)
10677 + num_clobbers_to_add
)
10678 : num_clobbers_to_add
+ 1));
10680 if (GET_CODE (pat
) == PARALLEL
)
10681 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10682 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10684 XVECEXP (newpat
, 0, 0) = pat
;
10686 add_clobbers (newpat
, insn_code_number
);
10688 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10689 i
< XVECLEN (newpat
, 0); i
++)
10691 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10692 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10694 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10696 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10697 notes
= alloc_reg_note (REG_UNUSED
,
10698 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10704 if (insn_code_number
>= 0
10705 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10707 old_pat
= PATTERN (insn
);
10708 old_notes
= REG_NOTES (insn
);
10709 old_icode
= INSN_CODE (insn
);
10710 PATTERN (insn
) = pat
;
10711 REG_NOTES (insn
) = notes
;
10713 /* Allow targets to reject combined insn. */
10714 if (!targetm
.legitimate_combined_insn (insn
))
10716 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10717 fputs ("Instruction not appropriate for target.",
10720 /* Callers expect recog_for_combine to strip
10721 clobbers from the pattern on failure. */
10722 pat
= pat_without_clobbers
;
10725 insn_code_number
= -1;
10728 PATTERN (insn
) = old_pat
;
10729 REG_NOTES (insn
) = old_notes
;
10730 INSN_CODE (insn
) = old_icode
;
10736 return insn_code_number
;
10739 /* Like gen_lowpart_general but for use by combine. In combine it
10740 is not possible to create any new pseudoregs. However, it is
10741 safe to create invalid memory addresses, because combine will
10742 try to recognize them and all they will do is make the combine
10745 If for some reason this cannot do its job, an rtx
10746 (clobber (const_int 0)) is returned.
10747 An insn containing that will not be recognized. */
10750 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10752 enum machine_mode imode
= GET_MODE (x
);
10753 unsigned int osize
= GET_MODE_SIZE (omode
);
10754 unsigned int isize
= GET_MODE_SIZE (imode
);
10757 if (omode
== imode
)
10760 /* We can only support MODE being wider than a word if X is a
10761 constant integer or has a mode the same size. */
10762 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10763 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10766 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10767 won't know what to do. So we will strip off the SUBREG here and
10768 process normally. */
10769 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10771 x
= SUBREG_REG (x
);
10773 /* For use in case we fall down into the address adjustments
10774 further below, we need to adjust the known mode and size of
10775 x; imode and isize, since we just adjusted x. */
10776 imode
= GET_MODE (x
);
10778 if (imode
== omode
)
10781 isize
= GET_MODE_SIZE (imode
);
10784 result
= gen_lowpart_common (omode
, x
);
10793 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10795 if (MEM_VOLATILE_P (x
)
10796 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10799 /* If we want to refer to something bigger than the original memref,
10800 generate a paradoxical subreg instead. That will force a reload
10801 of the original memref X. */
10803 return gen_rtx_SUBREG (omode
, x
, 0);
10805 if (WORDS_BIG_ENDIAN
)
10806 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10808 /* Adjust the address so that the address-after-the-data is
10810 if (BYTES_BIG_ENDIAN
)
10811 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10813 return adjust_address_nv (x
, omode
, offset
);
10816 /* If X is a comparison operator, rewrite it in a new mode. This
10817 probably won't match, but may allow further simplifications. */
10818 else if (COMPARISON_P (x
))
10819 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10821 /* If we couldn't simplify X any other way, just enclose it in a
10822 SUBREG. Normally, this SUBREG won't match, but some patterns may
10823 include an explicit SUBREG or we may simplify it further in combine. */
10829 offset
= subreg_lowpart_offset (omode
, imode
);
10830 if (imode
== VOIDmode
)
10832 imode
= int_mode_for_mode (omode
);
10833 x
= gen_lowpart_common (imode
, x
);
10837 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10843 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10846 /* Try to simplify a comparison between OP0 and a constant OP1,
10847 where CODE is the comparison code that will be tested, into a
10848 (CODE OP0 const0_rtx) form.
10850 The result is a possibly different comparison code to use.
10851 *POP1 may be updated. */
10853 static enum rtx_code
10854 simplify_compare_const (enum rtx_code code
, enum machine_mode mode
,
10855 rtx op0
, rtx
*pop1
)
10857 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10858 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10860 /* Get the constant we are comparing against and turn off all bits
10861 not on in our mode. */
10862 if (mode
!= VOIDmode
)
10863 const_op
= trunc_int_for_mode (const_op
, mode
);
10865 /* If we are comparing against a constant power of two and the value
10866 being compared can only have that single bit nonzero (e.g., it was
10867 `and'ed with that bit), we can replace this with a comparison
10870 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10871 || code
== LT
|| code
== LTU
)
10872 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10873 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10874 && (nonzero_bits (op0
, mode
)
10875 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10877 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10881 /* Similarly, if we are comparing a value known to be either -1 or
10882 0 with -1, change it to the opposite comparison against zero. */
10884 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10885 || code
== GEU
|| code
== LTU
)
10886 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10888 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10892 /* Do some canonicalizations based on the comparison code. We prefer
10893 comparisons against zero and then prefer equality comparisons.
10894 If we can reduce the size of a constant, we will do that too. */
10898 /* < C is equivalent to <= (C - 1) */
10903 /* ... fall through to LE case below. */
10909 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10916 /* If we are doing a <= 0 comparison on a value known to have
10917 a zero sign bit, we can replace this with == 0. */
10918 else if (const_op
== 0
10919 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10920 && (nonzero_bits (op0
, mode
)
10921 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10927 /* >= C is equivalent to > (C - 1). */
10932 /* ... fall through to GT below. */
10938 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10945 /* If we are doing a > 0 comparison on a value known to have
10946 a zero sign bit, we can replace this with != 0. */
10947 else if (const_op
== 0
10948 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10949 && (nonzero_bits (op0
, mode
)
10950 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10956 /* < C is equivalent to <= (C - 1). */
10961 /* ... fall through ... */
10963 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10964 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10965 && (unsigned HOST_WIDE_INT
) const_op
10966 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10976 /* unsigned <= 0 is equivalent to == 0 */
10979 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10980 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
10981 && (unsigned HOST_WIDE_INT
) const_op
10982 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10990 /* >= C is equivalent to > (C - 1). */
10995 /* ... fall through ... */
10998 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10999 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11000 && (unsigned HOST_WIDE_INT
) const_op
11001 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11011 /* unsigned > 0 is equivalent to != 0 */
11014 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11015 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11016 && (unsigned HOST_WIDE_INT
) const_op
11017 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11028 *pop1
= GEN_INT (const_op
);
11032 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11033 comparison code that will be tested.
11035 The result is a possibly different comparison code to use. *POP0 and
11036 *POP1 may be updated.
11038 It is possible that we might detect that a comparison is either always
11039 true or always false. However, we do not perform general constant
11040 folding in combine, so this knowledge isn't useful. Such tautologies
11041 should have been detected earlier. Hence we ignore all such cases. */
11043 static enum rtx_code
11044 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11050 enum machine_mode mode
, tmode
;
11052 /* Try a few ways of applying the same transformation to both operands. */
11055 #ifndef WORD_REGISTER_OPERATIONS
11056 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11057 so check specially. */
11058 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11059 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11060 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11061 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11062 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11063 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11064 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11065 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11066 && CONST_INT_P (XEXP (op0
, 1))
11067 && XEXP (op0
, 1) == XEXP (op1
, 1)
11068 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11069 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11070 && (INTVAL (XEXP (op0
, 1))
11071 == (GET_MODE_PRECISION (GET_MODE (op0
))
11072 - (GET_MODE_PRECISION
11073 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11075 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11076 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11080 /* If both operands are the same constant shift, see if we can ignore the
11081 shift. We can if the shift is a rotate or if the bits shifted out of
11082 this shift are known to be zero for both inputs and if the type of
11083 comparison is compatible with the shift. */
11084 if (GET_CODE (op0
) == GET_CODE (op1
)
11085 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11086 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11087 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11088 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11089 || (GET_CODE (op0
) == ASHIFTRT
11090 && (code
!= GTU
&& code
!= LTU
11091 && code
!= GEU
&& code
!= LEU
)))
11092 && CONST_INT_P (XEXP (op0
, 1))
11093 && INTVAL (XEXP (op0
, 1)) >= 0
11094 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11095 && XEXP (op0
, 1) == XEXP (op1
, 1))
11097 enum machine_mode mode
= GET_MODE (op0
);
11098 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11099 int shift_count
= INTVAL (XEXP (op0
, 1));
11101 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11102 mask
&= (mask
>> shift_count
) << shift_count
;
11103 else if (GET_CODE (op0
) == ASHIFT
)
11104 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11106 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11107 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11108 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11113 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11114 SUBREGs are of the same mode, and, in both cases, the AND would
11115 be redundant if the comparison was done in the narrower mode,
11116 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11117 and the operand's possibly nonzero bits are 0xffffff01; in that case
11118 if we only care about QImode, we don't need the AND). This case
11119 occurs if the output mode of an scc insn is not SImode and
11120 STORE_FLAG_VALUE == 1 (e.g., the 386).
11122 Similarly, check for a case where the AND's are ZERO_EXTEND
11123 operations from some narrower mode even though a SUBREG is not
11126 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11127 && CONST_INT_P (XEXP (op0
, 1))
11128 && CONST_INT_P (XEXP (op1
, 1)))
11130 rtx inner_op0
= XEXP (op0
, 0);
11131 rtx inner_op1
= XEXP (op1
, 0);
11132 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11133 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11136 if (paradoxical_subreg_p (inner_op0
)
11137 && GET_CODE (inner_op1
) == SUBREG
11138 && (GET_MODE (SUBREG_REG (inner_op0
))
11139 == GET_MODE (SUBREG_REG (inner_op1
)))
11140 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11141 <= HOST_BITS_PER_WIDE_INT
)
11142 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11143 GET_MODE (SUBREG_REG (inner_op0
)))))
11144 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11145 GET_MODE (SUBREG_REG (inner_op1
))))))
11147 op0
= SUBREG_REG (inner_op0
);
11148 op1
= SUBREG_REG (inner_op1
);
11150 /* The resulting comparison is always unsigned since we masked
11151 off the original sign bit. */
11152 code
= unsigned_condition (code
);
11158 for (tmode
= GET_CLASS_NARROWEST_MODE
11159 (GET_MODE_CLASS (GET_MODE (op0
)));
11160 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11161 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11163 op0
= gen_lowpart (tmode
, inner_op0
);
11164 op1
= gen_lowpart (tmode
, inner_op1
);
11165 code
= unsigned_condition (code
);
11174 /* If both operands are NOT, we can strip off the outer operation
11175 and adjust the comparison code for swapped operands; similarly for
11176 NEG, except that this must be an equality comparison. */
11177 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11178 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11179 && (code
== EQ
|| code
== NE
)))
11180 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11186 /* If the first operand is a constant, swap the operands and adjust the
11187 comparison code appropriately, but don't do this if the second operand
11188 is already a constant integer. */
11189 if (swap_commutative_operands_p (op0
, op1
))
11191 tem
= op0
, op0
= op1
, op1
= tem
;
11192 code
= swap_condition (code
);
11195 /* We now enter a loop during which we will try to simplify the comparison.
11196 For the most part, we only are concerned with comparisons with zero,
11197 but some things may really be comparisons with zero but not start
11198 out looking that way. */
11200 while (CONST_INT_P (op1
))
11202 enum machine_mode mode
= GET_MODE (op0
);
11203 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11204 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11205 int equality_comparison_p
;
11206 int sign_bit_comparison_p
;
11207 int unsigned_comparison_p
;
11208 HOST_WIDE_INT const_op
;
11210 /* We only want to handle integral modes. This catches VOIDmode,
11211 CCmode, and the floating-point modes. An exception is that we
11212 can handle VOIDmode if OP0 is a COMPARE or a comparison
11215 if (GET_MODE_CLASS (mode
) != MODE_INT
11216 && ! (mode
== VOIDmode
11217 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11220 /* Try to simplify the compare to constant, possibly changing the
11221 comparison op, and/or changing op1 to zero. */
11222 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11223 const_op
= INTVAL (op1
);
11225 /* Compute some predicates to simplify code below. */
11227 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11228 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11229 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11232 /* If this is a sign bit comparison and we can do arithmetic in
11233 MODE, say that we will only be needing the sign bit of OP0. */
11234 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11235 op0
= force_to_mode (op0
, mode
,
11236 (unsigned HOST_WIDE_INT
) 1
11237 << (GET_MODE_PRECISION (mode
) - 1),
11240 /* Now try cases based on the opcode of OP0. If none of the cases
11241 does a "continue", we exit this loop immediately after the
11244 switch (GET_CODE (op0
))
11247 /* If we are extracting a single bit from a variable position in
11248 a constant that has only a single bit set and are comparing it
11249 with zero, we can convert this into an equality comparison
11250 between the position and the location of the single bit. */
11251 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11252 have already reduced the shift count modulo the word size. */
11253 if (!SHIFT_COUNT_TRUNCATED
11254 && CONST_INT_P (XEXP (op0
, 0))
11255 && XEXP (op0
, 1) == const1_rtx
11256 && equality_comparison_p
&& const_op
== 0
11257 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11259 if (BITS_BIG_ENDIAN
)
11260 i
= BITS_PER_WORD
- 1 - i
;
11262 op0
= XEXP (op0
, 2);
11266 /* Result is nonzero iff shift count is equal to I. */
11267 code
= reverse_condition (code
);
11271 /* ... fall through ... */
11274 tem
= expand_compound_operation (op0
);
11283 /* If testing for equality, we can take the NOT of the constant. */
11284 if (equality_comparison_p
11285 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11287 op0
= XEXP (op0
, 0);
11292 /* If just looking at the sign bit, reverse the sense of the
11294 if (sign_bit_comparison_p
)
11296 op0
= XEXP (op0
, 0);
11297 code
= (code
== GE
? LT
: GE
);
11303 /* If testing for equality, we can take the NEG of the constant. */
11304 if (equality_comparison_p
11305 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11307 op0
= XEXP (op0
, 0);
11312 /* The remaining cases only apply to comparisons with zero. */
11316 /* When X is ABS or is known positive,
11317 (neg X) is < 0 if and only if X != 0. */
11319 if (sign_bit_comparison_p
11320 && (GET_CODE (XEXP (op0
, 0)) == ABS
11321 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11322 && (nonzero_bits (XEXP (op0
, 0), mode
)
11323 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11326 op0
= XEXP (op0
, 0);
11327 code
= (code
== LT
? NE
: EQ
);
11331 /* If we have NEG of something whose two high-order bits are the
11332 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11333 if (num_sign_bit_copies (op0
, mode
) >= 2)
11335 op0
= XEXP (op0
, 0);
11336 code
= swap_condition (code
);
11342 /* If we are testing equality and our count is a constant, we
11343 can perform the inverse operation on our RHS. */
11344 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11345 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11346 op1
, XEXP (op0
, 1))) != 0)
11348 op0
= XEXP (op0
, 0);
11353 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11354 a particular bit. Convert it to an AND of a constant of that
11355 bit. This will be converted into a ZERO_EXTRACT. */
11356 if (const_op
== 0 && sign_bit_comparison_p
11357 && CONST_INT_P (XEXP (op0
, 1))
11358 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11360 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11361 ((unsigned HOST_WIDE_INT
) 1
11363 - INTVAL (XEXP (op0
, 1)))));
11364 code
= (code
== LT
? NE
: EQ
);
11368 /* Fall through. */
11371 /* ABS is ignorable inside an equality comparison with zero. */
11372 if (const_op
== 0 && equality_comparison_p
)
11374 op0
= XEXP (op0
, 0);
11380 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11381 (compare FOO CONST) if CONST fits in FOO's mode and we
11382 are either testing inequality or have an unsigned
11383 comparison with ZERO_EXTEND or a signed comparison with
11384 SIGN_EXTEND. But don't do it if we don't have a compare
11385 insn of the given mode, since we'd have to revert it
11386 later on, and then we wouldn't know whether to sign- or
11388 mode
= GET_MODE (XEXP (op0
, 0));
11389 if (GET_MODE_CLASS (mode
) == MODE_INT
11390 && ! unsigned_comparison_p
11391 && HWI_COMPUTABLE_MODE_P (mode
)
11392 && trunc_int_for_mode (const_op
, mode
) == const_op
11393 && have_insn_for (COMPARE
, mode
))
11395 op0
= XEXP (op0
, 0);
11401 /* Check for the case where we are comparing A - C1 with C2, that is
11403 (subreg:MODE (plus (A) (-C1))) op (C2)
11405 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11406 comparison in the wider mode. One of the following two conditions
11407 must be true in order for this to be valid:
11409 1. The mode extension results in the same bit pattern being added
11410 on both sides and the comparison is equality or unsigned. As
11411 C2 has been truncated to fit in MODE, the pattern can only be
11414 2. The mode extension results in the sign bit being copied on
11417 The difficulty here is that we have predicates for A but not for
11418 (A - C1) so we need to check that C1 is within proper bounds so
11419 as to perturbate A as little as possible. */
11421 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11422 && subreg_lowpart_p (op0
)
11423 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11424 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11425 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11427 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11428 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11429 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11432 && (unsigned HOST_WIDE_INT
) c1
11433 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11434 && (equality_comparison_p
|| unsigned_comparison_p
)
11435 /* (A - C1) zero-extends if it is positive and sign-extends
11436 if it is negative, C2 both zero- and sign-extends. */
11437 && ((0 == (nonzero_bits (a
, inner_mode
)
11438 & ~GET_MODE_MASK (mode
))
11440 /* (A - C1) sign-extends if it is positive and 1-extends
11441 if it is negative, C2 both sign- and 1-extends. */
11442 || (num_sign_bit_copies (a
, inner_mode
)
11443 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11446 || ((unsigned HOST_WIDE_INT
) c1
11447 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11448 /* (A - C1) always sign-extends, like C2. */
11449 && num_sign_bit_copies (a
, inner_mode
)
11450 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11451 - (mode_width
- 1))))
11453 op0
= SUBREG_REG (op0
);
11458 /* If the inner mode is narrower and we are extracting the low part,
11459 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11460 if (subreg_lowpart_p (op0
)
11461 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11462 /* Fall through */ ;
11466 /* ... fall through ... */
11469 mode
= GET_MODE (XEXP (op0
, 0));
11470 if (GET_MODE_CLASS (mode
) == MODE_INT
11471 && (unsigned_comparison_p
|| equality_comparison_p
)
11472 && HWI_COMPUTABLE_MODE_P (mode
)
11473 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11475 && have_insn_for (COMPARE
, mode
))
11477 op0
= XEXP (op0
, 0);
11483 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11484 this for equality comparisons due to pathological cases involving
11486 if (equality_comparison_p
11487 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11488 op1
, XEXP (op0
, 1))))
11490 op0
= XEXP (op0
, 0);
11495 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11496 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11497 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11499 op0
= XEXP (XEXP (op0
, 0), 0);
11500 code
= (code
== LT
? EQ
: NE
);
11506 /* We used to optimize signed comparisons against zero, but that
11507 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11508 arrive here as equality comparisons, or (GEU, LTU) are
11509 optimized away. No need to special-case them. */
11511 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11512 (eq B (minus A C)), whichever simplifies. We can only do
11513 this for equality comparisons due to pathological cases involving
11515 if (equality_comparison_p
11516 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11517 XEXP (op0
, 1), op1
)))
11519 op0
= XEXP (op0
, 0);
11524 if (equality_comparison_p
11525 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11526 XEXP (op0
, 0), op1
)))
11528 op0
= XEXP (op0
, 1);
11533 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11534 of bits in X minus 1, is one iff X > 0. */
11535 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11536 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11537 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11538 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11540 op0
= XEXP (op0
, 1);
11541 code
= (code
== GE
? LE
: GT
);
11547 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11548 if C is zero or B is a constant. */
11549 if (equality_comparison_p
11550 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11551 XEXP (op0
, 1), op1
)))
11553 op0
= XEXP (op0
, 0);
11560 case UNEQ
: case LTGT
:
11561 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11562 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11563 case UNORDERED
: case ORDERED
:
11564 /* We can't do anything if OP0 is a condition code value, rather
11565 than an actual data value. */
11567 || CC0_P (XEXP (op0
, 0))
11568 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11571 /* Get the two operands being compared. */
11572 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11573 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11575 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11577 /* Check for the cases where we simply want the result of the
11578 earlier test or the opposite of that result. */
11579 if (code
== NE
|| code
== EQ
11580 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11581 && (code
== LT
|| code
== GE
)))
11583 enum rtx_code new_code
;
11584 if (code
== LT
|| code
== NE
)
11585 new_code
= GET_CODE (op0
);
11587 new_code
= reversed_comparison_code (op0
, NULL
);
11589 if (new_code
!= UNKNOWN
)
11600 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11602 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11603 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11604 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11606 op0
= XEXP (op0
, 1);
11607 code
= (code
== GE
? GT
: LE
);
11613 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11614 will be converted to a ZERO_EXTRACT later. */
11615 if (const_op
== 0 && equality_comparison_p
11616 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11617 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11619 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11620 XEXP (XEXP (op0
, 0), 1));
11621 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11625 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11626 zero and X is a comparison and C1 and C2 describe only bits set
11627 in STORE_FLAG_VALUE, we can compare with X. */
11628 if (const_op
== 0 && equality_comparison_p
11629 && mode_width
<= HOST_BITS_PER_WIDE_INT
11630 && CONST_INT_P (XEXP (op0
, 1))
11631 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11632 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11633 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11634 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11636 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11637 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11638 if ((~STORE_FLAG_VALUE
& mask
) == 0
11639 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11640 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11641 && COMPARISON_P (tem
))))
11643 op0
= XEXP (XEXP (op0
, 0), 0);
11648 /* If we are doing an equality comparison of an AND of a bit equal
11649 to the sign bit, replace this with a LT or GE comparison of
11650 the underlying value. */
11651 if (equality_comparison_p
11653 && CONST_INT_P (XEXP (op0
, 1))
11654 && mode_width
<= HOST_BITS_PER_WIDE_INT
11655 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11656 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11658 op0
= XEXP (op0
, 0);
11659 code
= (code
== EQ
? GE
: LT
);
11663 /* If this AND operation is really a ZERO_EXTEND from a narrower
11664 mode, the constant fits within that mode, and this is either an
11665 equality or unsigned comparison, try to do this comparison in
11670 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11671 -> (ne:DI (reg:SI 4) (const_int 0))
11673 unless TRULY_NOOP_TRUNCATION allows it or the register is
11674 known to hold a value of the required mode the
11675 transformation is invalid. */
11676 if ((equality_comparison_p
|| unsigned_comparison_p
)
11677 && CONST_INT_P (XEXP (op0
, 1))
11678 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11679 & GET_MODE_MASK (mode
))
11681 && const_op
>> i
== 0
11682 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11683 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11684 || (REG_P (XEXP (op0
, 0))
11685 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11687 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11691 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11692 fits in both M1 and M2 and the SUBREG is either paradoxical
11693 or represents the low part, permute the SUBREG and the AND
11695 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11697 unsigned HOST_WIDE_INT c1
;
11698 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11699 /* Require an integral mode, to avoid creating something like
11701 if (SCALAR_INT_MODE_P (tmode
)
11702 /* It is unsafe to commute the AND into the SUBREG if the
11703 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11704 not defined. As originally written the upper bits
11705 have a defined value due to the AND operation.
11706 However, if we commute the AND inside the SUBREG then
11707 they no longer have defined values and the meaning of
11708 the code has been changed. */
11710 #ifdef WORD_REGISTER_OPERATIONS
11711 || (mode_width
> GET_MODE_PRECISION (tmode
)
11712 && mode_width
<= BITS_PER_WORD
)
11714 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11715 && subreg_lowpart_p (XEXP (op0
, 0))))
11716 && CONST_INT_P (XEXP (op0
, 1))
11717 && mode_width
<= HOST_BITS_PER_WIDE_INT
11718 && HWI_COMPUTABLE_MODE_P (tmode
)
11719 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11720 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11722 && c1
!= GET_MODE_MASK (tmode
))
11724 op0
= simplify_gen_binary (AND
, tmode
,
11725 SUBREG_REG (XEXP (op0
, 0)),
11726 gen_int_mode (c1
, tmode
));
11727 op0
= gen_lowpart (mode
, op0
);
11732 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11733 if (const_op
== 0 && equality_comparison_p
11734 && XEXP (op0
, 1) == const1_rtx
11735 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11737 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11738 XEXP (XEXP (op0
, 0), 0), 1);
11739 code
= (code
== NE
? EQ
: NE
);
11743 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11744 (eq (and (lshiftrt X) 1) 0).
11745 Also handle the case where (not X) is expressed using xor. */
11746 if (const_op
== 0 && equality_comparison_p
11747 && XEXP (op0
, 1) == const1_rtx
11748 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11750 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11751 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11753 if (GET_CODE (shift_op
) == NOT
11754 || (GET_CODE (shift_op
) == XOR
11755 && CONST_INT_P (XEXP (shift_op
, 1))
11756 && CONST_INT_P (shift_count
)
11757 && HWI_COMPUTABLE_MODE_P (mode
)
11758 && (UINTVAL (XEXP (shift_op
, 1))
11759 == (unsigned HOST_WIDE_INT
) 1
11760 << INTVAL (shift_count
))))
11763 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11764 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11765 code
= (code
== NE
? EQ
: NE
);
11772 /* If we have (compare (ashift FOO N) (const_int C)) and
11773 the high order N bits of FOO (N+1 if an inequality comparison)
11774 are known to be zero, we can do this by comparing FOO with C
11775 shifted right N bits so long as the low-order N bits of C are
11777 if (CONST_INT_P (XEXP (op0
, 1))
11778 && INTVAL (XEXP (op0
, 1)) >= 0
11779 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11780 < HOST_BITS_PER_WIDE_INT
)
11781 && (((unsigned HOST_WIDE_INT
) const_op
11782 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11784 && mode_width
<= HOST_BITS_PER_WIDE_INT
11785 && (nonzero_bits (XEXP (op0
, 0), mode
)
11786 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11787 + ! equality_comparison_p
))) == 0)
11789 /* We must perform a logical shift, not an arithmetic one,
11790 as we want the top N bits of C to be zero. */
11791 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11793 temp
>>= INTVAL (XEXP (op0
, 1));
11794 op1
= gen_int_mode (temp
, mode
);
11795 op0
= XEXP (op0
, 0);
11799 /* If we are doing a sign bit comparison, it means we are testing
11800 a particular bit. Convert it to the appropriate AND. */
11801 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11802 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11804 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11805 ((unsigned HOST_WIDE_INT
) 1
11807 - INTVAL (XEXP (op0
, 1)))));
11808 code
= (code
== LT
? NE
: EQ
);
11812 /* If this an equality comparison with zero and we are shifting
11813 the low bit to the sign bit, we can convert this to an AND of the
11815 if (const_op
== 0 && equality_comparison_p
11816 && CONST_INT_P (XEXP (op0
, 1))
11817 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11819 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11825 /* If this is an equality comparison with zero, we can do this
11826 as a logical shift, which might be much simpler. */
11827 if (equality_comparison_p
&& const_op
== 0
11828 && CONST_INT_P (XEXP (op0
, 1)))
11830 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11832 INTVAL (XEXP (op0
, 1)));
11836 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11837 do the comparison in a narrower mode. */
11838 if (! unsigned_comparison_p
11839 && CONST_INT_P (XEXP (op0
, 1))
11840 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11841 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11842 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11843 MODE_INT
, 1)) != BLKmode
11844 && (((unsigned HOST_WIDE_INT
) const_op
11845 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11846 <= GET_MODE_MASK (tmode
)))
11848 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11852 /* Likewise if OP0 is a PLUS of a sign extension with a
11853 constant, which is usually represented with the PLUS
11854 between the shifts. */
11855 if (! unsigned_comparison_p
11856 && CONST_INT_P (XEXP (op0
, 1))
11857 && GET_CODE (XEXP (op0
, 0)) == PLUS
11858 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11859 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11860 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11861 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11862 MODE_INT
, 1)) != BLKmode
11863 && (((unsigned HOST_WIDE_INT
) const_op
11864 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11865 <= GET_MODE_MASK (tmode
)))
11867 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11868 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11869 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11870 add_const
, XEXP (op0
, 1));
11872 op0
= simplify_gen_binary (PLUS
, tmode
,
11873 gen_lowpart (tmode
, inner
),
11878 /* ... fall through ... */
11880 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11881 the low order N bits of FOO are known to be zero, we can do this
11882 by comparing FOO with C shifted left N bits so long as no
11883 overflow occurs. Even if the low order N bits of FOO aren't known
11884 to be zero, if the comparison is >= or < we can use the same
11885 optimization and for > or <= by setting all the low
11886 order N bits in the comparison constant. */
11887 if (CONST_INT_P (XEXP (op0
, 1))
11888 && INTVAL (XEXP (op0
, 1)) > 0
11889 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11890 && mode_width
<= HOST_BITS_PER_WIDE_INT
11891 && (((unsigned HOST_WIDE_INT
) const_op
11892 + (GET_CODE (op0
) != LSHIFTRT
11893 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11896 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11898 unsigned HOST_WIDE_INT low_bits
11899 = (nonzero_bits (XEXP (op0
, 0), mode
)
11900 & (((unsigned HOST_WIDE_INT
) 1
11901 << INTVAL (XEXP (op0
, 1))) - 1));
11902 if (low_bits
== 0 || !equality_comparison_p
)
11904 /* If the shift was logical, then we must make the condition
11906 if (GET_CODE (op0
) == LSHIFTRT
)
11907 code
= unsigned_condition (code
);
11909 const_op
<<= INTVAL (XEXP (op0
, 1));
11911 && (code
== GT
|| code
== GTU
11912 || code
== LE
|| code
== LEU
))
11914 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11915 op1
= GEN_INT (const_op
);
11916 op0
= XEXP (op0
, 0);
11921 /* If we are using this shift to extract just the sign bit, we
11922 can replace this with an LT or GE comparison. */
11924 && (equality_comparison_p
|| sign_bit_comparison_p
)
11925 && CONST_INT_P (XEXP (op0
, 1))
11926 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11928 op0
= XEXP (op0
, 0);
11929 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11941 /* Now make any compound operations involved in this comparison. Then,
11942 check for an outmost SUBREG on OP0 that is not doing anything or is
11943 paradoxical. The latter transformation must only be performed when
11944 it is known that the "extra" bits will be the same in op0 and op1 or
11945 that they don't matter. There are three cases to consider:
11947 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11948 care bits and we can assume they have any convenient value. So
11949 making the transformation is safe.
11951 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11952 In this case the upper bits of op0 are undefined. We should not make
11953 the simplification in that case as we do not know the contents of
11956 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11957 UNKNOWN. In that case we know those bits are zeros or ones. We must
11958 also be sure that they are the same as the upper bits of op1.
11960 We can never remove a SUBREG for a non-equality comparison because
11961 the sign bit is in a different place in the underlying object. */
11963 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11964 op1
= make_compound_operation (op1
, SET
);
11966 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11967 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11968 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11969 && (code
== NE
|| code
== EQ
))
11971 if (paradoxical_subreg_p (op0
))
11973 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11975 if (REG_P (SUBREG_REG (op0
)))
11977 op0
= SUBREG_REG (op0
);
11978 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11981 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11982 <= HOST_BITS_PER_WIDE_INT
)
11983 && (nonzero_bits (SUBREG_REG (op0
),
11984 GET_MODE (SUBREG_REG (op0
)))
11985 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11987 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11989 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11990 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11991 op0
= SUBREG_REG (op0
), op1
= tem
;
11995 /* We now do the opposite procedure: Some machines don't have compare
11996 insns in all modes. If OP0's mode is an integer mode smaller than a
11997 word and we can't do a compare in that mode, see if there is a larger
11998 mode for which we can do the compare. There are a number of cases in
11999 which we can use the wider mode. */
12001 mode
= GET_MODE (op0
);
12002 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12003 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12004 && ! have_insn_for (COMPARE
, mode
))
12005 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12006 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12007 tmode
= GET_MODE_WIDER_MODE (tmode
))
12008 if (have_insn_for (COMPARE
, tmode
))
12012 /* If this is a test for negative, we can make an explicit
12013 test of the sign bit. Test this first so we can use
12014 a paradoxical subreg to extend OP0. */
12016 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12017 && HWI_COMPUTABLE_MODE_P (mode
))
12019 unsigned HOST_WIDE_INT sign
12020 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12021 op0
= simplify_gen_binary (AND
, tmode
,
12022 gen_lowpart (tmode
, op0
),
12023 gen_int_mode (sign
, tmode
));
12024 code
= (code
== LT
) ? NE
: EQ
;
12028 /* If the only nonzero bits in OP0 and OP1 are those in the
12029 narrower mode and this is an equality or unsigned comparison,
12030 we can use the wider mode. Similarly for sign-extended
12031 values, in which case it is true for all comparisons. */
12032 zero_extended
= ((code
== EQ
|| code
== NE
12033 || code
== GEU
|| code
== GTU
12034 || code
== LEU
|| code
== LTU
)
12035 && (nonzero_bits (op0
, tmode
)
12036 & ~GET_MODE_MASK (mode
)) == 0
12037 && ((CONST_INT_P (op1
)
12038 || (nonzero_bits (op1
, tmode
)
12039 & ~GET_MODE_MASK (mode
)) == 0)));
12042 || ((num_sign_bit_copies (op0
, tmode
)
12043 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12044 - GET_MODE_PRECISION (mode
)))
12045 && (num_sign_bit_copies (op1
, tmode
)
12046 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12047 - GET_MODE_PRECISION (mode
)))))
12049 /* If OP0 is an AND and we don't have an AND in MODE either,
12050 make a new AND in the proper mode. */
12051 if (GET_CODE (op0
) == AND
12052 && !have_insn_for (AND
, mode
))
12053 op0
= simplify_gen_binary (AND
, tmode
,
12054 gen_lowpart (tmode
,
12056 gen_lowpart (tmode
,
12062 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12063 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12067 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12068 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12075 /* We may have changed the comparison operands. Re-canonicalize. */
12076 if (swap_commutative_operands_p (op0
, op1
))
12078 tem
= op0
, op0
= op1
, op1
= tem
;
12079 code
= swap_condition (code
);
12082 /* If this machine only supports a subset of valid comparisons, see if we
12083 can convert an unsupported one into a supported one. */
12084 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12092 /* Utility function for record_value_for_reg. Count number of
12097 enum rtx_code code
= GET_CODE (x
);
12101 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12102 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12104 rtx x0
= XEXP (x
, 0);
12105 rtx x1
= XEXP (x
, 1);
12108 return 1 + 2 * count_rtxs (x0
);
12110 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12111 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12112 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12113 return 2 + 2 * count_rtxs (x0
)
12114 + count_rtxs (x
== XEXP (x1
, 0)
12115 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12117 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12118 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12119 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12120 return 2 + 2 * count_rtxs (x1
)
12121 + count_rtxs (x
== XEXP (x0
, 0)
12122 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12125 fmt
= GET_RTX_FORMAT (code
);
12126 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12128 ret
+= count_rtxs (XEXP (x
, i
));
12129 else if (fmt
[i
] == 'E')
12130 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12131 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12136 /* Utility function for following routine. Called when X is part of a value
12137 being stored into last_set_value. Sets last_set_table_tick
12138 for each register mentioned. Similar to mention_regs in cse.c */
12141 update_table_tick (rtx x
)
12143 enum rtx_code code
= GET_CODE (x
);
12144 const char *fmt
= GET_RTX_FORMAT (code
);
12149 unsigned int regno
= REGNO (x
);
12150 unsigned int endregno
= END_REGNO (x
);
12153 for (r
= regno
; r
< endregno
; r
++)
12155 reg_stat_type
*rsp
= ®_stat
[r
];
12156 rsp
->last_set_table_tick
= label_tick
;
12162 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12165 /* Check for identical subexpressions. If x contains
12166 identical subexpression we only have to traverse one of
12168 if (i
== 0 && ARITHMETIC_P (x
))
12170 /* Note that at this point x1 has already been
12172 rtx x0
= XEXP (x
, 0);
12173 rtx x1
= XEXP (x
, 1);
12175 /* If x0 and x1 are identical then there is no need to
12180 /* If x0 is identical to a subexpression of x1 then while
12181 processing x1, x0 has already been processed. Thus we
12182 are done with x. */
12183 if (ARITHMETIC_P (x1
)
12184 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12187 /* If x1 is identical to a subexpression of x0 then we
12188 still have to process the rest of x0. */
12189 if (ARITHMETIC_P (x0
)
12190 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12192 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12197 update_table_tick (XEXP (x
, i
));
12199 else if (fmt
[i
] == 'E')
12200 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12201 update_table_tick (XVECEXP (x
, i
, j
));
12204 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12205 are saying that the register is clobbered and we no longer know its
12206 value. If INSN is zero, don't update reg_stat[].last_set; this is
12207 only permitted with VALUE also zero and is used to invalidate the
12211 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12213 unsigned int regno
= REGNO (reg
);
12214 unsigned int endregno
= END_REGNO (reg
);
12216 reg_stat_type
*rsp
;
12218 /* If VALUE contains REG and we have a previous value for REG, substitute
12219 the previous value. */
12220 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12224 /* Set things up so get_last_value is allowed to see anything set up to
12226 subst_low_luid
= DF_INSN_LUID (insn
);
12227 tem
= get_last_value (reg
);
12229 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12230 it isn't going to be useful and will take a lot of time to process,
12231 so just use the CLOBBER. */
12235 if (ARITHMETIC_P (tem
)
12236 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12237 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12238 tem
= XEXP (tem
, 0);
12239 else if (count_occurrences (value
, reg
, 1) >= 2)
12241 /* If there are two or more occurrences of REG in VALUE,
12242 prevent the value from growing too much. */
12243 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12244 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12247 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12251 /* For each register modified, show we don't know its value, that
12252 we don't know about its bitwise content, that its value has been
12253 updated, and that we don't know the location of the death of the
12255 for (i
= regno
; i
< endregno
; i
++)
12257 rsp
= ®_stat
[i
];
12260 rsp
->last_set
= insn
;
12262 rsp
->last_set_value
= 0;
12263 rsp
->last_set_mode
= VOIDmode
;
12264 rsp
->last_set_nonzero_bits
= 0;
12265 rsp
->last_set_sign_bit_copies
= 0;
12266 rsp
->last_death
= 0;
12267 rsp
->truncated_to_mode
= VOIDmode
;
12270 /* Mark registers that are being referenced in this value. */
12272 update_table_tick (value
);
12274 /* Now update the status of each register being set.
12275 If someone is using this register in this block, set this register
12276 to invalid since we will get confused between the two lives in this
12277 basic block. This makes using this register always invalid. In cse, we
12278 scan the table to invalidate all entries using this register, but this
12279 is too much work for us. */
12281 for (i
= regno
; i
< endregno
; i
++)
12283 rsp
= ®_stat
[i
];
12284 rsp
->last_set_label
= label_tick
;
12286 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12287 rsp
->last_set_invalid
= 1;
12289 rsp
->last_set_invalid
= 0;
12292 /* The value being assigned might refer to X (like in "x++;"). In that
12293 case, we must replace it with (clobber (const_int 0)) to prevent
12295 rsp
= ®_stat
[regno
];
12296 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12298 value
= copy_rtx (value
);
12299 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12303 /* For the main register being modified, update the value, the mode, the
12304 nonzero bits, and the number of sign bit copies. */
12306 rsp
->last_set_value
= value
;
12310 enum machine_mode mode
= GET_MODE (reg
);
12311 subst_low_luid
= DF_INSN_LUID (insn
);
12312 rsp
->last_set_mode
= mode
;
12313 if (GET_MODE_CLASS (mode
) == MODE_INT
12314 && HWI_COMPUTABLE_MODE_P (mode
))
12315 mode
= nonzero_bits_mode
;
12316 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12317 rsp
->last_set_sign_bit_copies
12318 = num_sign_bit_copies (value
, GET_MODE (reg
));
12322 /* Called via note_stores from record_dead_and_set_regs to handle one
12323 SET or CLOBBER in an insn. DATA is the instruction in which the
12324 set is occurring. */
12327 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12329 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12331 if (GET_CODE (dest
) == SUBREG
)
12332 dest
= SUBREG_REG (dest
);
12334 if (!record_dead_insn
)
12337 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12343 /* If we are setting the whole register, we know its value. Otherwise
12344 show that we don't know the value. We can handle SUBREG in
12346 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12347 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12348 else if (GET_CODE (setter
) == SET
12349 && GET_CODE (SET_DEST (setter
)) == SUBREG
12350 && SUBREG_REG (SET_DEST (setter
)) == dest
12351 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12352 && subreg_lowpart_p (SET_DEST (setter
)))
12353 record_value_for_reg (dest
, record_dead_insn
,
12354 gen_lowpart (GET_MODE (dest
),
12355 SET_SRC (setter
)));
12357 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12359 else if (MEM_P (dest
)
12360 /* Ignore pushes, they clobber nothing. */
12361 && ! push_operand (dest
, GET_MODE (dest
)))
12362 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12365 /* Update the records of when each REG was most recently set or killed
12366 for the things done by INSN. This is the last thing done in processing
12367 INSN in the combiner loop.
12369 We update reg_stat[], in particular fields last_set, last_set_value,
12370 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12371 last_death, and also the similar information mem_last_set (which insn
12372 most recently modified memory) and last_call_luid (which insn was the
12373 most recent subroutine call). */
12376 record_dead_and_set_regs (rtx_insn
*insn
)
12381 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12383 if (REG_NOTE_KIND (link
) == REG_DEAD
12384 && REG_P (XEXP (link
, 0)))
12386 unsigned int regno
= REGNO (XEXP (link
, 0));
12387 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12389 for (i
= regno
; i
< endregno
; i
++)
12391 reg_stat_type
*rsp
;
12393 rsp
= ®_stat
[i
];
12394 rsp
->last_death
= insn
;
12397 else if (REG_NOTE_KIND (link
) == REG_INC
)
12398 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12403 hard_reg_set_iterator hrsi
;
12404 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12406 reg_stat_type
*rsp
;
12408 rsp
= ®_stat
[i
];
12409 rsp
->last_set_invalid
= 1;
12410 rsp
->last_set
= insn
;
12411 rsp
->last_set_value
= 0;
12412 rsp
->last_set_mode
= VOIDmode
;
12413 rsp
->last_set_nonzero_bits
= 0;
12414 rsp
->last_set_sign_bit_copies
= 0;
12415 rsp
->last_death
= 0;
12416 rsp
->truncated_to_mode
= VOIDmode
;
12419 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12421 /* We can't combine into a call pattern. Remember, though, that
12422 the return value register is set at this LUID. We could
12423 still replace a register with the return value from the
12424 wrong subroutine call! */
12425 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12428 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12431 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12432 register present in the SUBREG, so for each such SUBREG go back and
12433 adjust nonzero and sign bit information of the registers that are
12434 known to have some zero/sign bits set.
12436 This is needed because when combine blows the SUBREGs away, the
12437 information on zero/sign bits is lost and further combines can be
12438 missed because of that. */
12441 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12443 struct insn_link
*links
;
12445 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12446 enum machine_mode mode
= GET_MODE (subreg
);
12448 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12451 for (links
= LOG_LINKS (insn
); links
;)
12453 reg_stat_type
*rsp
;
12455 insn
= links
->insn
;
12456 set
= single_set (insn
);
12458 if (! set
|| !REG_P (SET_DEST (set
))
12459 || REGNO (SET_DEST (set
)) != regno
12460 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12462 links
= links
->next
;
12466 rsp
= ®_stat
[regno
];
12467 if (rsp
->last_set
== insn
)
12469 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12470 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12473 if (REG_P (SET_SRC (set
)))
12475 regno
= REGNO (SET_SRC (set
));
12476 links
= LOG_LINKS (insn
);
12483 /* Check if X, a register, is known to contain a value already
12484 truncated to MODE. In this case we can use a subreg to refer to
12485 the truncated value even though in the generic case we would need
12486 an explicit truncation. */
12489 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12491 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12492 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12495 || rsp
->truncation_label
< label_tick_ebb_start
)
12497 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12499 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12504 /* If X is a hard reg or a subreg record the mode that the register is
12505 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12506 to turn a truncate into a subreg using this information. Return true
12507 if traversing X is complete. */
12510 record_truncated_value (rtx x
)
12512 enum machine_mode truncated_mode
;
12513 reg_stat_type
*rsp
;
12515 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12517 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12518 truncated_mode
= GET_MODE (x
);
12520 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12523 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12526 x
= SUBREG_REG (x
);
12528 /* ??? For hard-regs we now record everything. We might be able to
12529 optimize this using last_set_mode. */
12530 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12531 truncated_mode
= GET_MODE (x
);
12535 rsp
= ®_stat
[REGNO (x
)];
12536 if (rsp
->truncated_to_mode
== 0
12537 || rsp
->truncation_label
< label_tick_ebb_start
12538 || (GET_MODE_SIZE (truncated_mode
)
12539 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12541 rsp
->truncated_to_mode
= truncated_mode
;
12542 rsp
->truncation_label
= label_tick
;
12548 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12549 the modes they are used in. This can help truning TRUNCATEs into
12553 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12555 subrtx_var_iterator::array_type array
;
12556 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12557 if (record_truncated_value (*iter
))
12558 iter
.skip_subrtxes ();
12561 /* Scan X for promoted SUBREGs. For each one found,
12562 note what it implies to the registers used in it. */
12565 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12567 if (GET_CODE (x
) == SUBREG
12568 && SUBREG_PROMOTED_VAR_P (x
)
12569 && REG_P (SUBREG_REG (x
)))
12570 record_promoted_value (insn
, x
);
12573 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12576 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12580 check_promoted_subreg (insn
, XEXP (x
, i
));
12584 if (XVEC (x
, i
) != 0)
12585 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12586 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12592 /* Verify that all the registers and memory references mentioned in *LOC are
12593 still valid. *LOC was part of a value set in INSN when label_tick was
12594 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12595 the invalid references with (clobber (const_int 0)) and return 1. This
12596 replacement is useful because we often can get useful information about
12597 the form of a value (e.g., if it was produced by a shift that always
12598 produces -1 or 0) even though we don't know exactly what registers it
12599 was produced from. */
12602 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12605 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12606 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12611 unsigned int regno
= REGNO (x
);
12612 unsigned int endregno
= END_REGNO (x
);
12615 for (j
= regno
; j
< endregno
; j
++)
12617 reg_stat_type
*rsp
= ®_stat
[j
];
12618 if (rsp
->last_set_invalid
12619 /* If this is a pseudo-register that was only set once and not
12620 live at the beginning of the function, it is always valid. */
12621 || (! (regno
>= FIRST_PSEUDO_REGISTER
12622 && REG_N_SETS (regno
) == 1
12623 && (!REGNO_REG_SET_P
12624 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12626 && rsp
->last_set_label
> tick
))
12629 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12636 /* If this is a memory reference, make sure that there were no stores after
12637 it that might have clobbered the value. We don't have alias info, so we
12638 assume any store invalidates it. Moreover, we only have local UIDs, so
12639 we also assume that there were stores in the intervening basic blocks. */
12640 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12641 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12644 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12648 for (i
= 0; i
< len
; i
++)
12652 /* Check for identical subexpressions. If x contains
12653 identical subexpression we only have to traverse one of
12655 if (i
== 1 && ARITHMETIC_P (x
))
12657 /* Note that at this point x0 has already been checked
12658 and found valid. */
12659 rtx x0
= XEXP (x
, 0);
12660 rtx x1
= XEXP (x
, 1);
12662 /* If x0 and x1 are identical then x is also valid. */
12666 /* If x1 is identical to a subexpression of x0 then
12667 while checking x0, x1 has already been checked. Thus
12668 it is valid and so as x. */
12669 if (ARITHMETIC_P (x0
)
12670 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12673 /* If x0 is identical to a subexpression of x1 then x is
12674 valid iff the rest of x1 is valid. */
12675 if (ARITHMETIC_P (x1
)
12676 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12678 get_last_value_validate (&XEXP (x1
,
12679 x0
== XEXP (x1
, 0) ? 1 : 0),
12680 insn
, tick
, replace
);
12683 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12687 else if (fmt
[i
] == 'E')
12688 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12689 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12690 insn
, tick
, replace
) == 0)
12694 /* If we haven't found a reason for it to be invalid, it is valid. */
12698 /* Get the last value assigned to X, if known. Some registers
12699 in the value may be replaced with (clobber (const_int 0)) if their value
12700 is known longer known reliably. */
12703 get_last_value (const_rtx x
)
12705 unsigned int regno
;
12707 reg_stat_type
*rsp
;
12709 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12710 then convert it to the desired mode. If this is a paradoxical SUBREG,
12711 we cannot predict what values the "extra" bits might have. */
12712 if (GET_CODE (x
) == SUBREG
12713 && subreg_lowpart_p (x
)
12714 && !paradoxical_subreg_p (x
)
12715 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12716 return gen_lowpart (GET_MODE (x
), value
);
12722 rsp
= ®_stat
[regno
];
12723 value
= rsp
->last_set_value
;
12725 /* If we don't have a value, or if it isn't for this basic block and
12726 it's either a hard register, set more than once, or it's a live
12727 at the beginning of the function, return 0.
12729 Because if it's not live at the beginning of the function then the reg
12730 is always set before being used (is never used without being set).
12731 And, if it's set only once, and it's always set before use, then all
12732 uses must have the same last value, even if it's not from this basic
12736 || (rsp
->last_set_label
< label_tick_ebb_start
12737 && (regno
< FIRST_PSEUDO_REGISTER
12738 || REG_N_SETS (regno
) != 1
12740 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12743 /* If the value was set in a later insn than the ones we are processing,
12744 we can't use it even if the register was only set once. */
12745 if (rsp
->last_set_label
== label_tick
12746 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12749 /* If the value has all its registers valid, return it. */
12750 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12753 /* Otherwise, make a copy and replace any invalid register with
12754 (clobber (const_int 0)). If that fails for some reason, return 0. */
12756 value
= copy_rtx (value
);
12757 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12763 /* Return nonzero if expression X refers to a REG or to memory
12764 that is set in an instruction more recent than FROM_LUID. */
12767 use_crosses_set_p (const_rtx x
, int from_luid
)
12771 enum rtx_code code
= GET_CODE (x
);
12775 unsigned int regno
= REGNO (x
);
12776 unsigned endreg
= END_REGNO (x
);
12778 #ifdef PUSH_ROUNDING
12779 /* Don't allow uses of the stack pointer to be moved,
12780 because we don't know whether the move crosses a push insn. */
12781 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12784 for (; regno
< endreg
; regno
++)
12786 reg_stat_type
*rsp
= ®_stat
[regno
];
12788 && rsp
->last_set_label
== label_tick
12789 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12795 if (code
== MEM
&& mem_last_set
> from_luid
)
12798 fmt
= GET_RTX_FORMAT (code
);
12800 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12805 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12806 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12809 else if (fmt
[i
] == 'e'
12810 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12816 /* Define three variables used for communication between the following
12819 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12820 static int reg_dead_flag
;
12822 /* Function called via note_stores from reg_dead_at_p.
12824 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12825 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12828 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12830 unsigned int regno
, endregno
;
12835 regno
= REGNO (dest
);
12836 endregno
= END_REGNO (dest
);
12837 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12838 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12841 /* Return nonzero if REG is known to be dead at INSN.
12843 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12844 referencing REG, it is dead. If we hit a SET referencing REG, it is
12845 live. Otherwise, see if it is live or dead at the start of the basic
12846 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12847 must be assumed to be always live. */
12850 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
12855 /* Set variables for reg_dead_at_p_1. */
12856 reg_dead_regno
= REGNO (reg
);
12857 reg_dead_endregno
= END_REGNO (reg
);
12861 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12862 we allow the machine description to decide whether use-and-clobber
12863 patterns are OK. */
12864 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12866 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12867 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12871 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12872 beginning of basic block. */
12873 block
= BLOCK_FOR_INSN (insn
);
12878 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12880 return reg_dead_flag
== 1 ? 1 : 0;
12882 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12886 if (insn
== BB_HEAD (block
))
12889 insn
= PREV_INSN (insn
);
12892 /* Look at live-in sets for the basic block that we were in. */
12893 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12894 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12900 /* Note hard registers in X that are used. */
12903 mark_used_regs_combine (rtx x
)
12905 RTX_CODE code
= GET_CODE (x
);
12906 unsigned int regno
;
12917 case ADDR_DIFF_VEC
:
12920 /* CC0 must die in the insn after it is set, so we don't need to take
12921 special note of it here. */
12927 /* If we are clobbering a MEM, mark any hard registers inside the
12928 address as used. */
12929 if (MEM_P (XEXP (x
, 0)))
12930 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12935 /* A hard reg in a wide mode may really be multiple registers.
12936 If so, mark all of them just like the first. */
12937 if (regno
< FIRST_PSEUDO_REGISTER
)
12939 /* None of this applies to the stack, frame or arg pointers. */
12940 if (regno
== STACK_POINTER_REGNUM
12941 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12942 || regno
== HARD_FRAME_POINTER_REGNUM
12944 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12945 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12947 || regno
== FRAME_POINTER_REGNUM
)
12950 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12956 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12958 rtx testreg
= SET_DEST (x
);
12960 while (GET_CODE (testreg
) == SUBREG
12961 || GET_CODE (testreg
) == ZERO_EXTRACT
12962 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12963 testreg
= XEXP (testreg
, 0);
12965 if (MEM_P (testreg
))
12966 mark_used_regs_combine (XEXP (testreg
, 0));
12968 mark_used_regs_combine (SET_SRC (x
));
12976 /* Recursively scan the operands of this expression. */
12979 const char *fmt
= GET_RTX_FORMAT (code
);
12981 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12984 mark_used_regs_combine (XEXP (x
, i
));
12985 else if (fmt
[i
] == 'E')
12989 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12990 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12996 /* Remove register number REGNO from the dead registers list of INSN.
12998 Return the note used to record the death, if there was one. */
13001 remove_death (unsigned int regno
, rtx_insn
*insn
)
13003 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13006 remove_note (insn
, note
);
13011 /* For each register (hardware or pseudo) used within expression X, if its
13012 death is in an instruction with luid between FROM_LUID (inclusive) and
13013 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13014 list headed by PNOTES.
13016 That said, don't move registers killed by maybe_kill_insn.
13018 This is done when X is being merged by combination into TO_INSN. These
13019 notes will then be distributed as needed. */
13022 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13027 enum rtx_code code
= GET_CODE (x
);
13031 unsigned int regno
= REGNO (x
);
13032 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13034 /* Don't move the register if it gets killed in between from and to. */
13035 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13036 && ! reg_referenced_p (x
, maybe_kill_insn
))
13040 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13041 && DF_INSN_LUID (where_dead
) >= from_luid
13042 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13044 rtx note
= remove_death (regno
, where_dead
);
13046 /* It is possible for the call above to return 0. This can occur
13047 when last_death points to I2 or I1 that we combined with.
13048 In that case make a new note.
13050 We must also check for the case where X is a hard register
13051 and NOTE is a death note for a range of hard registers
13052 including X. In that case, we must put REG_DEAD notes for
13053 the remaining registers in place of NOTE. */
13055 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13056 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13057 > GET_MODE_SIZE (GET_MODE (x
))))
13059 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13060 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13061 unsigned int ourend
= END_HARD_REGNO (x
);
13064 for (i
= deadregno
; i
< deadend
; i
++)
13065 if (i
< regno
|| i
>= ourend
)
13066 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13069 /* If we didn't find any note, or if we found a REG_DEAD note that
13070 covers only part of the given reg, and we have a multi-reg hard
13071 register, then to be safe we must check for REG_DEAD notes
13072 for each register other than the first. They could have
13073 their own REG_DEAD notes lying around. */
13074 else if ((note
== 0
13076 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13077 < GET_MODE_SIZE (GET_MODE (x
)))))
13078 && regno
< FIRST_PSEUDO_REGISTER
13079 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13081 unsigned int ourend
= END_HARD_REGNO (x
);
13082 unsigned int i
, offset
;
13086 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13090 for (i
= regno
+ offset
; i
< ourend
; i
++)
13091 move_deaths (regno_reg_rtx
[i
],
13092 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13095 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13097 XEXP (note
, 1) = *pnotes
;
13101 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13107 else if (GET_CODE (x
) == SET
)
13109 rtx dest
= SET_DEST (x
);
13111 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13113 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13114 that accesses one word of a multi-word item, some
13115 piece of everything register in the expression is used by
13116 this insn, so remove any old death. */
13117 /* ??? So why do we test for equality of the sizes? */
13119 if (GET_CODE (dest
) == ZERO_EXTRACT
13120 || GET_CODE (dest
) == STRICT_LOW_PART
13121 || (GET_CODE (dest
) == SUBREG
13122 && (((GET_MODE_SIZE (GET_MODE (dest
))
13123 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13124 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13125 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13127 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13131 /* If this is some other SUBREG, we know it replaces the entire
13132 value, so use that as the destination. */
13133 if (GET_CODE (dest
) == SUBREG
)
13134 dest
= SUBREG_REG (dest
);
13136 /* If this is a MEM, adjust deaths of anything used in the address.
13137 For a REG (the only other possibility), the entire value is
13138 being replaced so the old value is not used in this insn. */
13141 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13146 else if (GET_CODE (x
) == CLOBBER
)
13149 len
= GET_RTX_LENGTH (code
);
13150 fmt
= GET_RTX_FORMAT (code
);
13152 for (i
= 0; i
< len
; i
++)
13157 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13158 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13161 else if (fmt
[i
] == 'e')
13162 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13166 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13167 pattern of an insn. X must be a REG. */
13170 reg_bitfield_target_p (rtx x
, rtx body
)
13174 if (GET_CODE (body
) == SET
)
13176 rtx dest
= SET_DEST (body
);
13178 unsigned int regno
, tregno
, endregno
, endtregno
;
13180 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13181 target
= XEXP (dest
, 0);
13182 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13183 target
= SUBREG_REG (XEXP (dest
, 0));
13187 if (GET_CODE (target
) == SUBREG
)
13188 target
= SUBREG_REG (target
);
13190 if (!REG_P (target
))
13193 tregno
= REGNO (target
), regno
= REGNO (x
);
13194 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13195 return target
== x
;
13197 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13198 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13200 return endregno
> tregno
&& regno
< endtregno
;
13203 else if (GET_CODE (body
) == PARALLEL
)
13204 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13205 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13211 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13212 as appropriate. I3 and I2 are the insns resulting from the combination
13213 insns including FROM (I2 may be zero).
13215 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13216 not need REG_DEAD notes because they are being substituted for. This
13217 saves searching in the most common cases.
13219 Each note in the list is either ignored or placed on some insns, depending
13220 on the type of note. */
13223 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13224 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13226 rtx note
, next_note
;
13228 rtx_insn
*tem_insn
;
13230 for (note
= notes
; note
; note
= next_note
)
13232 rtx_insn
*place
= 0, *place2
= 0;
13234 next_note
= XEXP (note
, 1);
13235 switch (REG_NOTE_KIND (note
))
13239 /* Doesn't matter much where we put this, as long as it's somewhere.
13240 It is preferable to keep these notes on branches, which is most
13241 likely to be i3. */
13245 case REG_NON_LOCAL_GOTO
:
13250 gcc_assert (i2
&& JUMP_P (i2
));
13255 case REG_EH_REGION
:
13256 /* These notes must remain with the call or trapping instruction. */
13259 else if (i2
&& CALL_P (i2
))
13263 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13264 if (may_trap_p (i3
))
13266 else if (i2
&& may_trap_p (i2
))
13268 /* ??? Otherwise assume we've combined things such that we
13269 can now prove that the instructions can't trap. Drop the
13270 note in this case. */
13274 case REG_ARGS_SIZE
:
13275 /* ??? How to distribute between i3-i1. Assume i3 contains the
13276 entire adjustment. Assert i3 contains at least some adjust. */
13277 if (!noop_move_p (i3
))
13279 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13280 /* fixup_args_size_notes looks at REG_NORETURN note,
13281 so ensure the note is placed there first. */
13285 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13286 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13290 XEXP (n
, 1) = REG_NOTES (i3
);
13291 REG_NOTES (i3
) = n
;
13295 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13296 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13297 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13298 gcc_assert (old_size
!= args_size
13300 && !ACCUMULATE_OUTGOING_ARGS
13301 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13308 case REG_CALL_DECL
:
13309 /* These notes must remain with the call. It should not be
13310 possible for both I2 and I3 to be a call. */
13315 gcc_assert (i2
&& CALL_P (i2
));
13321 /* Any clobbers for i3 may still exist, and so we must process
13322 REG_UNUSED notes from that insn.
13324 Any clobbers from i2 or i1 can only exist if they were added by
13325 recog_for_combine. In that case, recog_for_combine created the
13326 necessary REG_UNUSED notes. Trying to keep any original
13327 REG_UNUSED notes from these insns can cause incorrect output
13328 if it is for the same register as the original i3 dest.
13329 In that case, we will notice that the register is set in i3,
13330 and then add a REG_UNUSED note for the destination of i3, which
13331 is wrong. However, it is possible to have REG_UNUSED notes from
13332 i2 or i1 for register which were both used and clobbered, so
13333 we keep notes from i2 or i1 if they will turn into REG_DEAD
13336 /* If this register is set or clobbered in I3, put the note there
13337 unless there is one already. */
13338 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13340 if (from_insn
!= i3
)
13343 if (! (REG_P (XEXP (note
, 0))
13344 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13345 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13348 /* Otherwise, if this register is used by I3, then this register
13349 now dies here, so we must put a REG_DEAD note here unless there
13351 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13352 && ! (REG_P (XEXP (note
, 0))
13353 ? find_regno_note (i3
, REG_DEAD
,
13354 REGNO (XEXP (note
, 0)))
13355 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13357 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13365 /* These notes say something about results of an insn. We can
13366 only support them if they used to be on I3 in which case they
13367 remain on I3. Otherwise they are ignored.
13369 If the note refers to an expression that is not a constant, we
13370 must also ignore the note since we cannot tell whether the
13371 equivalence is still true. It might be possible to do
13372 slightly better than this (we only have a problem if I2DEST
13373 or I1DEST is present in the expression), but it doesn't
13374 seem worth the trouble. */
13376 if (from_insn
== i3
13377 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13382 /* These notes say something about how a register is used. They must
13383 be present on any use of the register in I2 or I3. */
13384 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13387 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13396 case REG_LABEL_TARGET
:
13397 case REG_LABEL_OPERAND
:
13398 /* This can show up in several ways -- either directly in the
13399 pattern, or hidden off in the constant pool with (or without?)
13400 a REG_EQUAL note. */
13401 /* ??? Ignore the without-reg_equal-note problem for now. */
13402 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13403 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13404 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13405 && XEXP (XEXP (tem_note
, 0), 0) == XEXP (note
, 0)))
13409 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13410 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13411 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13412 && XEXP (XEXP (tem_note
, 0), 0) == XEXP (note
, 0))))
13420 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13421 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13423 if (place
&& JUMP_P (place
)
13424 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13425 && (JUMP_LABEL (place
) == NULL
13426 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13428 rtx label
= JUMP_LABEL (place
);
13431 JUMP_LABEL (place
) = XEXP (note
, 0);
13432 else if (LABEL_P (label
))
13433 LABEL_NUSES (label
)--;
13436 if (place2
&& JUMP_P (place2
)
13437 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13438 && (JUMP_LABEL (place2
) == NULL
13439 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13441 rtx label
= JUMP_LABEL (place2
);
13444 JUMP_LABEL (place2
) = XEXP (note
, 0);
13445 else if (LABEL_P (label
))
13446 LABEL_NUSES (label
)--;
13452 /* This note says something about the value of a register prior
13453 to the execution of an insn. It is too much trouble to see
13454 if the note is still correct in all situations. It is better
13455 to simply delete it. */
13459 /* If we replaced the right hand side of FROM_INSN with a
13460 REG_EQUAL note, the original use of the dying register
13461 will not have been combined into I3 and I2. In such cases,
13462 FROM_INSN is guaranteed to be the first of the combined
13463 instructions, so we simply need to search back before
13464 FROM_INSN for the previous use or set of this register,
13465 then alter the notes there appropriately.
13467 If the register is used as an input in I3, it dies there.
13468 Similarly for I2, if it is nonzero and adjacent to I3.
13470 If the register is not used as an input in either I3 or I2
13471 and it is not one of the registers we were supposed to eliminate,
13472 there are two possibilities. We might have a non-adjacent I2
13473 or we might have somehow eliminated an additional register
13474 from a computation. For example, we might have had A & B where
13475 we discover that B will always be zero. In this case we will
13476 eliminate the reference to A.
13478 In both cases, we must search to see if we can find a previous
13479 use of A and put the death note there. */
13482 && from_insn
== i2mod
13483 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13484 tem_insn
= from_insn
;
13488 && CALL_P (from_insn
)
13489 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13491 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13493 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13494 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13496 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13498 && reg_overlap_mentioned_p (XEXP (note
, 0),
13500 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13501 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13508 basic_block bb
= this_basic_block
;
13510 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13512 if (!NONDEBUG_INSN_P (tem_insn
))
13514 if (tem_insn
== BB_HEAD (bb
))
13519 /* If the register is being set at TEM_INSN, see if that is all
13520 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13521 into a REG_UNUSED note instead. Don't delete sets to
13522 global register vars. */
13523 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13524 || !global_regs
[REGNO (XEXP (note
, 0))])
13525 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13527 rtx set
= single_set (tem_insn
);
13528 rtx inner_dest
= 0;
13530 rtx_insn
*cc0_setter
= NULL
;
13534 for (inner_dest
= SET_DEST (set
);
13535 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13536 || GET_CODE (inner_dest
) == SUBREG
13537 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13538 inner_dest
= XEXP (inner_dest
, 0))
13541 /* Verify that it was the set, and not a clobber that
13542 modified the register.
13544 CC0 targets must be careful to maintain setter/user
13545 pairs. If we cannot delete the setter due to side
13546 effects, mark the user with an UNUSED note instead
13549 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13550 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13552 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13553 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13554 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13558 /* Move the notes and links of TEM_INSN elsewhere.
13559 This might delete other dead insns recursively.
13560 First set the pattern to something that won't use
13562 rtx old_notes
= REG_NOTES (tem_insn
);
13564 PATTERN (tem_insn
) = pc_rtx
;
13565 REG_NOTES (tem_insn
) = NULL
;
13567 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13568 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13569 distribute_links (LOG_LINKS (tem_insn
));
13571 SET_INSN_DELETED (tem_insn
);
13572 if (tem_insn
== i2
)
13576 /* Delete the setter too. */
13579 PATTERN (cc0_setter
) = pc_rtx
;
13580 old_notes
= REG_NOTES (cc0_setter
);
13581 REG_NOTES (cc0_setter
) = NULL
;
13583 distribute_notes (old_notes
, cc0_setter
,
13585 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13586 distribute_links (LOG_LINKS (cc0_setter
));
13588 SET_INSN_DELETED (cc0_setter
);
13589 if (cc0_setter
== i2
)
13596 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13598 /* If there isn't already a REG_UNUSED note, put one
13599 here. Do not place a REG_DEAD note, even if
13600 the register is also used here; that would not
13601 match the algorithm used in lifetime analysis
13602 and can cause the consistency check in the
13603 scheduler to fail. */
13604 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13605 REGNO (XEXP (note
, 0))))
13610 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13611 || (CALL_P (tem_insn
)
13612 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13616 /* If we are doing a 3->2 combination, and we have a
13617 register which formerly died in i3 and was not used
13618 by i2, which now no longer dies in i3 and is used in
13619 i2 but does not die in i2, and place is between i2
13620 and i3, then we may need to move a link from place to
13622 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13624 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13625 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13627 struct insn_link
*links
= LOG_LINKS (place
);
13628 LOG_LINKS (place
) = NULL
;
13629 distribute_links (links
);
13634 if (tem_insn
== BB_HEAD (bb
))
13640 /* If the register is set or already dead at PLACE, we needn't do
13641 anything with this note if it is still a REG_DEAD note.
13642 We check here if it is set at all, not if is it totally replaced,
13643 which is what `dead_or_set_p' checks, so also check for it being
13646 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13648 unsigned int regno
= REGNO (XEXP (note
, 0));
13649 reg_stat_type
*rsp
= ®_stat
[regno
];
13651 if (dead_or_set_p (place
, XEXP (note
, 0))
13652 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13654 /* Unless the register previously died in PLACE, clear
13655 last_death. [I no longer understand why this is
13657 if (rsp
->last_death
!= place
)
13658 rsp
->last_death
= 0;
13662 rsp
->last_death
= place
;
13664 /* If this is a death note for a hard reg that is occupying
13665 multiple registers, ensure that we are still using all
13666 parts of the object. If we find a piece of the object
13667 that is unused, we must arrange for an appropriate REG_DEAD
13668 note to be added for it. However, we can't just emit a USE
13669 and tag the note to it, since the register might actually
13670 be dead; so we recourse, and the recursive call then finds
13671 the previous insn that used this register. */
13673 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13674 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13676 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13677 bool all_used
= true;
13680 for (i
= regno
; i
< endregno
; i
++)
13681 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13682 && ! find_regno_fusage (place
, USE
, i
))
13683 || dead_or_set_regno_p (place
, i
))
13691 /* Put only REG_DEAD notes for pieces that are
13692 not already dead or set. */
13694 for (i
= regno
; i
< endregno
;
13695 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13697 rtx piece
= regno_reg_rtx
[i
];
13698 basic_block bb
= this_basic_block
;
13700 if (! dead_or_set_p (place
, piece
)
13701 && ! reg_bitfield_target_p (piece
,
13704 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13707 distribute_notes (new_note
, place
, place
,
13708 NULL
, NULL_RTX
, NULL_RTX
,
13711 else if (! refers_to_regno_p (i
, i
+ 1,
13712 PATTERN (place
), 0)
13713 && ! find_regno_fusage (place
, USE
, i
))
13714 for (tem_insn
= PREV_INSN (place
); ;
13715 tem_insn
= PREV_INSN (tem_insn
))
13717 if (!NONDEBUG_INSN_P (tem_insn
))
13719 if (tem_insn
== BB_HEAD (bb
))
13723 if (dead_or_set_p (tem_insn
, piece
)
13724 || reg_bitfield_target_p (piece
,
13725 PATTERN (tem_insn
)))
13727 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
13740 /* Any other notes should not be present at this point in the
13742 gcc_unreachable ();
13747 XEXP (note
, 1) = REG_NOTES (place
);
13748 REG_NOTES (place
) = note
;
13752 add_shallow_copy_of_reg_note (place2
, note
);
13756 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13757 I3, I2, and I1 to new locations. This is also called to add a link
13758 pointing at I3 when I3's destination is changed. */
13761 distribute_links (struct insn_link
*links
)
13763 struct insn_link
*link
, *next_link
;
13765 for (link
= links
; link
; link
= next_link
)
13767 rtx_insn
*place
= 0;
13771 next_link
= link
->next
;
13773 /* If the insn that this link points to is a NOTE or isn't a single
13774 set, ignore it. In the latter case, it isn't clear what we
13775 can do other than ignore the link, since we can't tell which
13776 register it was for. Such links wouldn't be used by combine
13779 It is not possible for the destination of the target of the link to
13780 have been changed by combine. The only potential of this is if we
13781 replace I3, I2, and I1 by I3 and I2. But in that case the
13782 destination of I2 also remains unchanged. */
13784 if (NOTE_P (link
->insn
)
13785 || (set
= single_set (link
->insn
)) == 0)
13788 reg
= SET_DEST (set
);
13789 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13790 || GET_CODE (reg
) == STRICT_LOW_PART
)
13791 reg
= XEXP (reg
, 0);
13793 /* A LOG_LINK is defined as being placed on the first insn that uses
13794 a register and points to the insn that sets the register. Start
13795 searching at the next insn after the target of the link and stop
13796 when we reach a set of the register or the end of the basic block.
13798 Note that this correctly handles the link that used to point from
13799 I3 to I2. Also note that not much searching is typically done here
13800 since most links don't point very far away. */
13802 for (insn
= NEXT_INSN (link
->insn
);
13803 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13804 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13805 insn
= NEXT_INSN (insn
))
13806 if (DEBUG_INSN_P (insn
))
13808 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13810 if (reg_referenced_p (reg
, PATTERN (insn
)))
13814 else if (CALL_P (insn
)
13815 && find_reg_fusage (insn
, USE
, reg
))
13820 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13823 /* If we found a place to put the link, place it there unless there
13824 is already a link to the same insn as LINK at that point. */
13828 struct insn_link
*link2
;
13830 FOR_EACH_LOG_LINK (link2
, place
)
13831 if (link2
->insn
== link
->insn
)
13836 link
->next
= LOG_LINKS (place
);
13837 LOG_LINKS (place
) = link
;
13839 /* Set added_links_insn to the earliest insn we added a
13841 if (added_links_insn
== 0
13842 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13843 added_links_insn
= place
;
13849 /* Check for any register or memory mentioned in EQUIV that is not
13850 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13851 of EXPR where some registers may have been replaced by constants. */
13854 unmentioned_reg_p (rtx equiv
, rtx expr
)
13856 subrtx_iterator::array_type array
;
13857 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
13859 const_rtx x
= *iter
;
13860 if ((REG_P (x
) || MEM_P (x
))
13861 && !reg_mentioned_p (x
, expr
))
13867 DEBUG_FUNCTION
void
13868 dump_combine_stats (FILE *file
)
13872 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13873 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13877 dump_combine_total_stats (FILE *file
)
13881 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13882 total_attempts
, total_merges
, total_extras
, total_successes
);
13885 /* Try combining insns through substitution. */
13886 static unsigned int
13887 rest_of_handle_combine (void)
13889 int rebuild_jump_labels_after_combine
;
13891 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13892 df_note_add_problem ();
13895 regstat_init_n_sets_and_refs ();
13897 rebuild_jump_labels_after_combine
13898 = combine_instructions (get_insns (), max_reg_num ());
13900 /* Combining insns may have turned an indirect jump into a
13901 direct jump. Rebuild the JUMP_LABEL fields of jumping
13903 if (rebuild_jump_labels_after_combine
)
13905 timevar_push (TV_JUMP
);
13906 rebuild_jump_labels (get_insns ());
13908 timevar_pop (TV_JUMP
);
13911 regstat_free_n_sets_and_refs ();
13917 const pass_data pass_data_combine
=
13919 RTL_PASS
, /* type */
13920 "combine", /* name */
13921 OPTGROUP_NONE
, /* optinfo_flags */
13922 TV_COMBINE
, /* tv_id */
13923 PROP_cfglayout
, /* properties_required */
13924 0, /* properties_provided */
13925 0, /* properties_destroyed */
13926 0, /* todo_flags_start */
13927 TODO_df_finish
, /* todo_flags_finish */
13930 class pass_combine
: public rtl_opt_pass
13933 pass_combine (gcc::context
*ctxt
)
13934 : rtl_opt_pass (pass_data_combine
, ctxt
)
13937 /* opt_pass methods: */
13938 virtual bool gate (function
*) { return (optimize
> 0); }
13939 virtual unsigned int execute (function
*)
13941 return rest_of_handle_combine ();
13944 }; // class pass_combine
13946 } // anon namespace
13949 make_pass_combine (gcc::context
*ctxt
)
13951 return new pass_combine (ctxt
);