| blob | 4a393c94e119ab2000c868c109a3ea92b479f7b0 |
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
41 /* The maximum number of insns skipped which will be conditionalised if
42 possible. */
46 /* Some function declarations. */
50 HOST_WIDE_INT));
71 /* Define the information needed to generate branch insns. This is
72 stored from the compare operation. */
77 /* What type of floating point are we tuning for? */
80 /* What type of floating point instructions are available? */
83 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
86 /* Set by the -mfp=... option */
89 /* Used to parse -mstructure_size_boundary command line option. */
93 /* Nonzero if this is an "M" variant of the processor. */
96 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
99 /* Nonzero if this chip can benefit from laod scheduling. */
102 /* Nonzero if this chip is a StrongARM. */
105 /* Nonzero if this chip is a an ARM6 or an ARM7. */
108 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
109 must report the mode of the memory reference from PRINT_OPERAND to
110 PRINT_OPERAND_ADDRESS. */
113 /* Nonzero if the prologue must setup `fp'. */
116 /* The register number to be used for the PIC offset register. */
119 /* Location counter of .text segment. */
122 /* Set to one if we think that lr is only saved because of subroutine calls,
123 but all of these can be `put after' return insns */
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
135 /* For an explanation of these variables, see final_prescan_insn below. */
138 rtx arm_target_insn;
141 /* The condition codes of the ARM, and the inverse function. */
143 {
146 };
150 #define streq(string1, string2) (strcmp (string1, string2) == 0)
151 \f
152 /* Initialization code */
163 struct processors
164 {
167 };
169 /* Not all of these give usefully different compilation alternatives,
170 but there is no simple way of generalizing them. */
172 {
173 /* ARM Cores */
184 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */
186 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */
196 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu. */
207 };
210 {
211 /* ARM Architectures */
218 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
219 implementations that support it, so we will leave it out for now. */
222 };
224 /* This is a magic stucture. The 'string' field is magically filled in
225 with a pointer to the value specified by the user on the command line
226 assuming that the user has specified such a value. */
229 {
230 /* string name processors */
234 };
236 /* Fix up any incompatible options that the user has specified.
237 This has now turned into a maze. */
238 void
240 {
245 /* Set up the flags based on the cpu/architecture selected by the user. */
247 {
251 {
256 {
258 {
259 /* We scan the arm_select array in the order:
260 tune -> arch -> cpu
261 So if we have been asked to tune for, say, an ARM8,
262 but we are told that the cpu is only an ARM6, then
263 we have problems. We detect this by seeing if the
264 flags bits accumulated so far can be supported by the
265 cpu/architecture type now being parsed. If they can,
266 then OR in any new bits. If they cannot then report
267 an error. */
271 }
276 }
280 }
281 }
283 /* If the user did not specify a processor, choose one for them. */
285 {
290 {
293 /* Force apcs-32 to be used for Thumb targets. */
295 }
301 {
304 {
307 }
311 }
312 else
313 {
314 /* The user did not specify any command line switches that require
315 a certain kind of CPU. Use TARGET_CPU_DEFAULT instead. */
317 static struct cpu_default
318 {
321 }
322 cpu_defaults[] =
323 {
336 };
339 /* Find the default. */
347 /* Find the default CPU's flags. */
356 }
357 }
359 /* Make sure that the processor choice does not conflict with any of the
360 other command line choices. */
362 {
365 }
367 {
370 }
373 {
376 }
378 /* If interworking is enabled then APCS-32 must be selected as well. */
380 {
384 }
387 {
390 }
404 /* If stack checking is disabled, we can use r10 as the PIC register,
405 which keeps r9 available. */
409 /* Well, I'm about to have a go, but pic is NOT going to be compatible
410 with APCS reentrancy, since that requires too much support in the
411 assembler and linker, and the ARMASM assembler seems to lack some
412 required directives. */
419 /* Initialise booleans used elsewhere in this file, and in arm.md */
425 /* The arm.md file needs to know if theprocessor is an ARM6 or an ARM7 */
428 /* Default value for floating point code... if no co-processor
429 bus, then schedule for emulated floating point. Otherwise,
430 assume the user has an FPA.
431 Note: this does not prevent use of floating point instructions,
432 -msoft-float does that. */
435 else
439 {
444 else
446 target_fp_name);
447 }
448 else
454 /* For arm2/3 there is no need to do any scheduling if there is only
455 a floating point emulator, or we are doing software floating-point. */
462 {
467 else
469 }
471 /* If optimizing for space, don't synthesize constants.
472 For processors with load scheduling, it never costs more than 2 cycles
473 to load a constant, and the load scheduler may well reduce that to 1. */
477 /* If optimizing for size, bump the number of instructions that we
478 are prepared to conditionally execute (even on a StrongARM).
479 Otherwise for the StrongARM, which has early execution of branches,
480 a sequence that is worth skipping is shorter. */
485 }
486 \f
487 /* Return 1 if it is possible to return using a single instruction */
489 int
492 {
496 || current_function_pretend_args_size
497 || current_function_anonymous_args
502 /* Can't be done if interworking with Thumb, and any registers have been
503 stacked. Similarly, on StrongARM, conditional returns are expensive
504 if they aren't taken and registers have been stacked. */
513 /* Can't be done if any of the FPU regs are pushed, since this also
514 requires an insn */
519 /* If a function is naked, don't use the "return" insn. */
524 }
526 /* Return TRUE if int I is a valid immediate ARM constant. */
528 int
530 HOST_WIDE_INT i;
531 {
534 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
535 be all zero, or all one. */
542 /* Fast return for 0 and powers of 2 */
546 do
547 {
550 mask =
556 }
558 /* Return true if I is a valid constant for the operation CODE. */
559 int
561 HOST_WIDE_INT i;
564 {
569 {
583 }
584 }
586 /* Emit a sequence of insns to handle a large constant.
587 CODE is the code of the operation required, it can be any of SET, PLUS,
588 IOR, AND, XOR, MINUS;
589 MODE is the mode in which the operation is being performed;
590 VAL is the integer to operate on;
591 SOURCE is the other operand (a register, or a null-pointer for SET);
592 SUBTARGETS means it is safe to create scratch registers if that will
593 either produce a simpler sequence, or we will want to cse the values.
594 Return value is the number of insns emitted. */
596 int
600 HOST_WIDE_INT val;
601 rtx target;
602 rtx source;
604 {
608 {
609 /* After arm_reorg has been called, we can't fix up expensive
610 constants by pushing them into memory so we must synthesise
611 them in-line, regardless of the cost. This is only likely to
612 be more costly on chips that have load delay slots and we are
613 compiling without running the scheduler (so no splitting
614 occurred before the final instruction emission. */
618 {
620 {
621 /* Currently SET is the only monadic value for CODE, all
622 the rest are diadic. */
625 }
626 else
627 {
631 /* For MINUS, the value is subtracted from, since we never
632 have subtraction of a constant. */
636 else
640 }
641 }
642 }
645 }
647 /* As above, but extra parameter GENERATE which, if clear, suppresses
648 RTL generation. */
649 int
653 HOST_WIDE_INT val;
654 rtx target;
655 rtx source;
658 {
673 /* find out which operations are safe for a given CODE. Also do a quick
674 check for degenerate cases; these can occur when DImode operations
675 are split. */
677 {
691 {
696 }
698 {
704 }
709 {
713 }
715 {
721 }
727 {
733 }
735 {
740 }
742 /* We don't know how to handle this yet below. */
746 /* We treat MINUS as (val - source), since (source - val) is always
747 passed as (source + (-val)). */
749 {
754 }
756 {
760 source)));
762 }
769 }
771 /* If we can do it in one insn get out quickly */
775 {
782 }
785 /* Calculate a few attributes that may be useful for specific
786 optimizations. */
789 {
791 clear_sign_bit_copies++;
792 else
794 }
797 {
799 set_sign_bit_copies++;
800 else
802 }
805 {
807 clear_zero_bit_copies++;
808 else
810 }
813 {
815 set_zero_bit_copies++;
816 else
818 }
821 {
823 /* See if we can do this by sign_extending a constant that is known
824 to be negative. This is a good, way of doing it, since the shift
825 may well merge into a subsequent insn. */
827 {
831 {
833 {
839 }
841 }
842 /* For an inverted constant, we will need to set the low bits,
843 these will be shifted out of harm's way. */
846 {
848 {
854 }
856 }
857 }
859 /* See if we can generate this by setting the bottom (or the top)
860 16 bits, and then shifting these into the other half of the
861 word. We only look for the simplest cases, to do more would cost
862 too much. Be careful, however, not to generate this when the
863 alternative would take fewer insns. */
865 {
869 /* Overlaps outside this range are best done using other methods. */
871 {
874 {
875 rtx new_src = (subtargets
887 source)));
889 }
890 }
892 /* Don't duplicate cases already considered. */
894 {
897 {
898 rtx new_src = (subtargets
905 emit_insn
907 gen_rtx_IOR
911 source)));
913 }
914 }
915 }
920 /* If we have IOR or XOR, and the constant can be loaded in a
921 single instruction, and we can find a temporary to put it in,
922 then this can be done in two instructions instead of 3-4. */
924 /* TARGET can't be NULL if SUBTARGETS is 0 */
926 {
928 {
930 {
936 }
938 }
939 }
946 {
948 {
955 source,
956 shift))));
960 shift))));
961 }
963 }
967 {
969 {
976 source,
977 shift))));
981 shift))));
982 }
984 }
987 {
989 {
1001 }
1003 }
1007 /* See if two shifts will do 2 or more insn's worth of work. */
1009 {
1015 {
1017 {
1022 }
1023 else
1024 {
1028 }
1029 }
1032 {
1038 }
1041 }
1044 {
1048 {
1050 {
1056 }
1057 else
1058 {
1063 }
1064 }
1067 {
1073 }
1076 }
1082 }
1086 num_bits_set++;
1092 else
1093 {
1096 }
1098 /* Now try and find a way of doing the job in either two or three
1099 instructions.
1100 We start by looking for the largest block of zeros that are aligned on
1101 a 2-bit boundary, we then fill up the temps, wrapping around to the
1102 top of the word when we drop off the bottom.
1103 In the worst case this code should produce no more than four insns. */
1104 {
1109 {
1113 {
1115 {
1118 }
1120 {
1123 }
1125 }
1126 }
1128 /* Now start emitting the insns, starting with the one with the highest
1129 bit set: we do this so that the smallest number will be emitted last;
1130 this is more likely to be combinable with addressing insns. */
1132 do
1133 {
1139 {
1148 {
1149 rtx new_src;
1153 new_src = (subtargets
1160 new_src = (subtargets
1164 source)));
1165 else
1167 new_src = (remainder
1168 ? (subtargets
1174 : (can_negate
1175 ? -temp1
1178 }
1181 {
1184 }
1188 insns++;
1190 }
1193 }
1195 }
1197 /* Canonicalize a comparison so that we are more likely to recognize it.
1198 This can be done for a few constant compares, where we can make the
1199 immediate value easier to load. */
1200 enum rtx_code
1204 {
1208 {
1218 {
1221 }
1228 {
1231 }
1238 {
1241 }
1248 {
1251 }
1256 }
1259 }
1261 /* Decide whether a type should be returned in memory (true)
1262 or in a register (false). This is called by the macro
1263 RETURN_IN_MEMORY. */
1264 int
1266 tree type;
1267 {
1269 {
1270 /* All simple types are returned in registers. */
1272 }
1274 {
1275 /* All structures/unions bigger than one word are returned in memory. */
1277 }
1279 {
1280 tree field;
1282 /* For a struct the APCS says that we must return in a register if
1283 every addressable element has an offset of zero. For practical
1284 purposes this means that the structure can have at most one non
1285 bit-field element and that this element must be the first one in
1286 the structure. */
1288 /* Find the first field, ignoring non FIELD_DECL things which will
1289 have been created by C++. */
1298 /* Now check the remaining fields, if any. */
1300 field;
1302 {
1308 }
1311 }
1313 {
1314 tree field;
1316 /* Unions can be returned in registers if every element is
1317 integral, or can be returned in an integer register. */
1319 field;
1321 {
1330 }
1333 }
1335 /* XXX Not sure what should be done for other aggregates, so put them in
1336 memory. */
1338 }
1340 int
1342 rtx x;
1343 {
1352 }
1354 rtx
1356 rtx orig;
1358 rtx reg;
1359 {
1361 {
1363 rtx insn;
1367 {
1370 else
1374 }
1376 #ifdef AOF_ASSEMBLER
1377 /* The AOF assembler can generate relocations for these directly, and
1378 understands that the PIC register has to be added into the offset.
1379 */
1381 #else
1384 else
1391 address));
1394 #endif
1396 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1397 by loop. */
1401 }
1403 {
1411 {
1414 else
1416 }
1419 {
1423 }
1424 else
1428 {
1429 /* The base register doesn't really matter, we only want to
1430 test the index for the appropriate mode. */
1435 else
1438 win:
1441 }
1446 {
1449 }
1452 }
1457 }
1461 int
1463 rtx x;
1464 {
1468 }
1470 void
1472 {
1473 #ifndef AOF_ASSEMBLER
1475 rtx global_offset_table;
1487 /* On the ARM the PC register contains 'dot + 8' at the time of the
1488 addition. */
1502 /* Need to emit this whether or not we obey regdecls,
1503 since setjmp/longjmp can cause life info to screw up. */
1506 }
1508 #define REG_OR_SUBREG_REG(X) \
1509 (GET_CODE (X) == REG \
1510 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1512 #define REG_OR_SUBREG_RTX(X) \
1513 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1515 #define ARM_FRAME_RTX(X) \
1516 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1517 || (X) == arg_pointer_rtx)
1519 int
1521 rtx x;
1523 {
1529 {
1531 /* Memory costs quite a lot for the first word, but subsequent words
1532 load at the equivalent of a single insn each. */
1543 /* Fall through */
1547 /* Fall through */
1598 /* Fall through */
1608 /* Fall through */
1612 /* Normally the frame registers will be spilt into reg+const during
1613 reload, so it is a bad idea to combine them with other instructions,
1614 since then they might not be moved outside of loops. As a compromise
1615 we allow integration with ops that have a constant as their second
1616 operand. */
1655 /* There is no point basing this on the tuning, since it is always the
1656 fast variant if it exists at all */
1668 {
1673 /* Tune as appropriate */
1677 {
1680 }
1683 }
1703 /* Fall through */
1725 /* Fall through */
1728 {
1742 }
1747 }
1748 }
1750 int
1752 rtx insn;
1753 rtx link;
1754 rtx dep;
1756 {
1759 /* XXX This is not strictly true for the FPA. */
1768 {
1769 /* This is a load after a store, there is no conflict if the load reads
1770 from a cached area. Assume that loads from the stack, and from the
1771 constant pool are cached, and that others will miss. This is a
1772 hack. */
1774 /* debug_rtx (insn);
1775 debug_rtx (dep);
1776 debug_rtx (link);
1777 fprintf (stderr, "costs %d\n", cost); */
1784 {
1785 /* fprintf (stderr, "***** Now 1\n"); */
1787 }
1788 }
1791 }
1793 /* This code has been fixed for cross compilation. */
1800 };
1804 static void
1806 {
1808 REAL_VALUE_TYPE r;
1811 {
1814 }
1817 }
1819 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1821 int
1823 rtx x;
1824 {
1825 REAL_VALUE_TYPE r;
1840 }
1842 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1844 int
1846 rtx x;
1847 {
1848 REAL_VALUE_TYPE r;
1864 }
1865 \f
1866 /* Predicates for `match_operand' and `match_operator'. */
1868 /* s_register_operand is the same as register_operand, but it doesn't accept
1869 (SUBREG (MEM)...).
1871 This function exists because at the time it was put in it led to better
1872 code. SUBREG(MEM) always needs a reload in the places where
1873 s_register_operand is used, and this seemed to lead to excessive
1874 reloading. */
1876 int
1880 {
1887 /* We don't consider registers whose class is NO_REGS
1888 to be a register operand. */
1892 }
1894 /* Only accept reg, subreg(reg), const_int. */
1896 int
1900 {
1910 /* We don't consider registers whose class is NO_REGS
1911 to be a register operand. */
1915 }
1917 /* Return 1 if OP is an item in memory, given that we are in reload. */
1919 int
1921 rtx op;
1923 {
1930 }
1932 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
1933 memory access (architecture V4) */
1934 int
1936 rtx op;
1938 {
1944 /* A sum of anything more complex than reg + reg or reg + const is bad */
1951 /* Big constants are also bad */
1957 /* Everything else is good, or can will automatically be made so. */
1959 }
1961 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1963 int
1965 rtx op;
1967 {
1970 }
1972 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1973 */
1975 int
1977 rtx op;
1979 {
1983 }
1985 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1986 constant that is valid when negated. */
1988 int
1990 rtx op;
1992 {
1997 }
1999 int
2001 rtx op;
2003 {
2008 }
2010 /* Return TRUE if the operand is a memory reference which contains an
2011 offsettable address. */
2012 int
2016 {
2024 }
2026 /* Return TRUE if the operand is a memory reference which is, or can be
2027 made word aligned by adjusting the offset. */
2028 int
2032 {
2033 rtx reg;
2052 }
2054 /* Similar to s_register_operand, but does not allow hard integer
2055 registers. */
2056 int
2060 {
2067 /* We don't consider registers whose class is NO_REGS
2068 to be a register operand. */
2072 }
2074 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2076 int
2078 rtx op;
2080 {
2087 }
2089 int
2091 rtx op;
2093 {
2101 }
2103 /* Return nonzero if OP is a constant power of two. */
2105 int
2107 rtx op;
2109 {
2111 {
2114 }
2116 }
2118 /* Return TRUE for a valid operand of a DImode operation.
2119 Either: REG, CONST_DOUBLE or MEM(DImode_address).
2120 Note that this disallows MEM(REG+REG), but allows
2121 MEM(PRE/POST_INC/DEC(REG)). */
2123 int
2125 rtx op;
2127 {
2132 {
2142 }
2143 }
2145 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2146 Either: REG, CONST_DOUBLE or MEM(DImode_address).
2147 Note that this disallows MEM(REG+REG), but allows
2148 MEM(PRE/POST_INC/DEC(REG)). */
2150 int
2152 rtx op;
2154 {
2159 {
2168 }
2169 }
2171 /* Return TRUE for valid index operands. */
2173 int
2175 rtx op;
2177 {
2181 }
2183 /* Return TRUE for valid shifts by a constant. This also accepts any
2184 power of two on the (somewhat overly relaxed) assumption that the
2185 shift operator in this case was a mult. */
2187 int
2189 rtx op;
2191 {
2195 }
2197 /* Return TRUE for arithmetic operators which can be combined with a multiply
2198 (shift). */
2200 int
2202 rtx x;
2204 {
2207 else
2208 {
2213 }
2214 }
2216 /* Return TRUE for shift operators. */
2218 int
2220 rtx x;
2222 {
2225 else
2226 {
2234 }
2235 }
2238 rtx x;
2240 {
2242 }
2244 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2246 int
2248 rtx x;
2250 {
2257 }
2259 /* return TRUE if x is EQ or NE */
2261 /* Return TRUE if this is the condition code register, if we aren't given
2262 a mode, accept any class CCmode register */
2264 int
2266 rtx x;
2268 {
2270 {
2274 }
2280 }
2282 /* Return TRUE if this is the condition code register, if we aren't given
2283 a mode, accept any class CCmode register which indicates a dominance
2284 expression. */
2286 int
2288 rtx x;
2290 {
2292 {
2296 }
2309 }
2311 /* Return TRUE if X references a SYMBOL_REF. */
2312 int
2314 rtx x;
2315 {
2324 {
2326 {
2332 }
2335 }
2338 }
2340 /* Return TRUE if X references a LABEL_REF. */
2341 int
2343 rtx x;
2344 {
2353 {
2355 {
2361 }
2364 }
2367 }
2369 enum rtx_code
2371 rtx x;
2372 {
2385 }
2387 /* Return 1 if memory locations are adjacent */
2389 int
2392 {
2402 {
2404 {
2407 }
2408 else
2411 {
2414 }
2415 else
2418 }
2420 }
2422 /* Return 1 if OP is a load multiple operation. It is known to be
2423 parallel and the first section will be tested. */
2425 int
2427 rtx op;
2429 {
2432 rtx src_addr;
2434 rtx elt;
2440 /* Check to see if this might be a write-back */
2442 {
2443 i++;
2446 /* Now check it more carefully */
2458 count--;
2459 }
2461 /* Perform a quick check so we don't blow up below. */
2472 {
2486 }
2489 }
2491 /* Return 1 if OP is a store multiple operation. It is known to be
2492 parallel and the first section will be tested. */
2494 int
2496 rtx op;
2498 {
2501 rtx dest_addr;
2503 rtx elt;
2509 /* Check to see if this might be a write-back */
2511 {
2512 i++;
2515 /* Now check it more carefully */
2527 count--;
2528 }
2530 /* Perform a quick check so we don't blow up below. */
2541 {
2555 }
2558 }
2560 int
2567 {
2574 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2575 extended if required. */
2579 /* Loop over the operands and check that the memory references are
2580 suitable (ie immediate offsets from the same base register). At
2581 the same time, extract the target register, and the memory
2582 offsets. */
2584 {
2585 rtx reg;
2586 rtx offset;
2588 /* Convert a subreg of a mem into the mem itself. */
2595 /* Don't reorder volatile memory references; it doesn't seem worth
2596 looking for the case where the order is ok anyway. */
2612 {
2614 {
2620 }
2621 else
2622 {
2624 /* Not addressed from the same base register. */
2632 }
2634 /* If it isn't an integer register, or if it overwrites the
2635 base register but isn't the last insn in the list, then
2636 we can't do this. */
2642 }
2643 else
2644 /* Not a suitable memory address. */
2646 }
2648 /* All the useful information has now been extracted from the
2649 operands into unsorted_regs and unsorted_offsets; additionally,
2650 order[0] has been set to the lowest numbered register in the
2651 list. Sort the registers into order, and check that the memory
2652 offsets are ascending and adjacent. */
2655 {
2665 /* Have we found a suitable register? if not, one must be used more
2666 than once. */
2670 /* Is the memory address adjacent and ascending? */
2673 }
2676 {
2683 }
2697 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if
2698 the offset isn't small enough. The reason 2 ldrs are faster is because
2699 these ARMs are able to do more than one cache access in a single cycle.
2700 The ARM9 and StrongARM have Harvard caches, whilst the ARM8 has a double
2701 bandwidth cache. This means that these cores can do both an instruction
2702 fetch and a data fetch in a single cycle, so the trick of calculating the
2703 address into a scratch register (one of the result regs) and then doing a
2704 load multiple actually becomes slower (and no smaller in code size). That
2705 is the transformation
2707 ldr rd1, [rbase + offset]
2708 ldr rd2, [rbase + offset + 4]
2710 to
2712 add rd1, rbase, offset
2713 ldmia rd1, {rd1, rd2}
2715 produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles
2716 + any stalls on rd2'. On ARMs with only one cache access per cycle, the
2717 first sequence could never complete in less than 6 cycles, whereas the ldm
2718 sequence would only take 5 and would make better use of sequential accesses
2719 if not hitting the cache.
2721 We cheat here and test 'arm_ld_sched' which we currently know to only be
2722 true for the ARM8, ARM9 and StrongARM. If this ever changes, then the test
2723 below needs to be reworked. */
2727 /* Can't do it without setting up the offset, only do this if it takes
2728 no more than one insn. */
2731 }
2737 {
2740 HOST_WIDE_INT offset;
2745 {
2767 else
2778 }
2791 }
2793 int
2800 {
2807 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2808 extended if required. */
2812 /* Loop over the operands and check that the memory references are
2813 suitable (ie immediate offsets from the same base register). At
2814 the same time, extract the target register, and the memory
2815 offsets. */
2817 {
2818 rtx reg;
2819 rtx offset;
2821 /* Convert a subreg of a mem into the mem itself. */
2828 /* Don't reorder volatile memory references; it doesn't seem worth
2829 looking for the case where the order is ok anyway. */
2845 {
2847 {
2853 }
2854 else
2855 {
2857 /* Not addressed from the same base register. */
2865 }
2867 /* If it isn't an integer register, then we can't do this. */
2872 }
2873 else
2874 /* Not a suitable memory address. */
2876 }
2878 /* All the useful information has now been extracted from the
2879 operands into unsorted_regs and unsorted_offsets; additionally,
2880 order[0] has been set to the lowest numbered register in the
2881 list. Sort the registers into order, and check that the memory
2882 offsets are ascending and adjacent. */
2885 {
2895 /* Have we found a suitable register? if not, one must be used more
2896 than once. */
2900 /* Is the memory address adjacent and ascending? */
2903 }
2906 {
2913 }
2928 }
2934 {
2937 HOST_WIDE_INT offset;
2942 {
2961 }
2974 }
2976 int
2978 rtx op;
2980 {
2988 }
2990 \f
2991 /* Routines for use with attributes */
2993 /* Return nonzero if ATTR is a valid attribute for DECL.
2994 ATTRIBUTES are any existing attributes and ARGS are the arguments
2995 supplied with ATTR.
2997 Supported attributes:
2999 naked: don't output any prologue or epilogue code, the user is assumed
3000 to do the right thing. */
3002 int
3004 tree decl;
3005 tree attributes;
3006 tree attr;
3007 tree args;
3008 {
3015 }
3017 /* Return non-zero if FUNC is a naked function. */
3019 static int
3021 tree func;
3022 {
3023 tree a;
3030 }
3031 \f
3032 /* Routines for use in generating RTL */
3034 rtx
3039 rtx from;
3045 {
3047 rtx result;
3049 rtx mem;
3054 {
3059 count++;
3060 }
3063 {
3070 }
3076 }
3078 rtx
3083 rtx to;
3089 {
3091 rtx result;
3093 rtx mem;
3098 {
3103 count++;
3104 }
3107 {
3115 }
3121 }
3123 int
3126 {
3132 rtx mem;
3163 {
3166 src_unchanging_p,
3167 src_in_struct_p,
3168 src_scalar_p));
3169 else
3175 {
3178 dst_unchanging_p,
3179 dst_in_struct_p,
3180 dst_scalar_p));
3186 dst_unchanging_p,
3187 dst_in_struct_p,
3188 dst_scalar_p));
3189 else
3190 {
3198 }
3199 }
3203 }
3205 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3207 {
3208 rtx sreg;
3223 in_words_to_go--;
3227 }
3230 {
3239 }
3242 {
3248 /* The bytes we want are in the top end of the word */
3254 {
3261 {
3265 }
3266 }
3268 }
3269 else
3270 {
3272 {
3282 {
3288 }
3289 }
3290 }
3293 }
3295 /* Generate a memory reference for a half word, such that it will be loaded
3296 into the top 16 bits of the word. We can assume that the address is
3297 known to be alignable and of the form reg, or plus (reg, const). */
3298 rtx
3300 rtx memref;
3301 {
3306 {
3309 }
3311 /* If we aren't allowed to generate unaligned addresses, then fail. */
3322 }
3324 static enum machine_mode
3327 rtx x;
3328 rtx y;
3329 HOST_WIDE_INT cond_or;
3330 {
3334 /* Currently we will probably get the wrong result if the individual
3335 comparisons are not simple. This also ensures that it is safe to
3336 reverse a comparison if necessary. */
3346 /* If the comparisons are not equal, and one doesn't dominate the other,
3347 then we can't do this. */
3354 {
3358 }
3361 {
3367 {
3373 }
3413 /* The remaining cases only occur when both comparisons are the
3414 same. */
3432 }
3435 }
3437 enum machine_mode
3440 rtx x;
3441 rtx y;
3442 {
3443 /* All floating point compares return CCFP if it is an equality
3444 comparison, and CCFPE otherwise. */
3448 /* A compare with a shifted operand. Because of canonicalization, the
3449 comparison will have to be swapped when we emit the assembler. */
3456 /* This is a special case that is used by combine to allow a
3457 comparison of a shifted byte load to be split into a zero-extend
3458 followed by a comparison of the shifted integer (only valid for
3459 equalities and unsigned inequalities). */
3471 /* An operation that sets the condition codes as a side-effect, the
3472 V flag is not set correctly, so we can only use comparisons where
3473 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3474 instead. */
3487 /* A construct for a conditional compare, if the false arm contains
3488 0, then both conditions must be true, otherwise either condition
3489 must be true. Not all conditions are possible, so CCmode is
3490 returned if it can't be done. */
3508 }
3510 /* X and Y are two things to compare using CODE. Emit the compare insn and
3511 return the rtx for register 0 in the proper mode. FP means this is a
3512 floating point compare: I don't think that it is needed on the arm. */
3514 rtx
3519 {
3527 }
3529 void
3532 {
3536 /* Handle the case where the address is too complex to be offset by 1. */
3539 {
3544 }
3552 gen_rtx_ASHIFT
3557 else
3564 }
3566 void
3569 {
3573 {
3581 }
3582 else
3583 {
3591 }
3592 }
3593 \f
3594 /* Routines for manipulation of the constant pool. */
3595 /* This is unashamedly hacked from the version in sh.c, since the problem is
3596 extremely similar. */
3598 /* Arm instructions cannot load a large constant into a register,
3599 constants have to come from a pc relative load. The reference of a pc
3600 relative load instruction must be less than 1k infront of the instruction.
3601 This means that we often have to dump a constant inside a function, and
3602 generate code to branch around it.
3604 It is important to minimize this, since the branches will slow things
3605 down and make things bigger.
3607 Worst case code looks like:
3609 ldr rn, L1
3610 b L2
3611 align
3612 L1: .long value
3613 L2:
3614 ..
3616 ldr rn, L3
3617 b L4
3618 align
3619 L3: .long value
3620 L4:
3621 ..
3623 We fix this by performing a scan before scheduling, which notices which
3624 instructions need to have their operands fetched from the constant table
3625 and builds the table.
3628 The algorithm is:
3630 scan, find an instruction which needs a pcrel move. Look forward, find th
3631 last barrier which is within MAX_COUNT bytes of the requirement.
3632 If there isn't one, make one. Process all the instructions between
3633 the find and the barrier.
3635 In the above example, we can tell that L3 is within 1k of L1, so
3636 the first move can be shrunk from the 2 insn+constant sequence into
3637 just 1 insn, and the constant moved to L3 to make:
3639 ldr rn, L1
3640 ..
3641 ldr rn, L3
3642 b L4
3643 align
3644 L1: .long value
3645 L3: .long value
3646 L4:
3648 Then the second move becomes the target for the shortening process.
3650 */
3653 {
3655 HOST_WIDE_INT next_offset;
3659 /* The maximum number of constants that can fit into one pool, since
3660 the pc relative range is 0...1020 bytes and constants are at least 4
3661 bytes long */
3663 #define MAX_POOL_SIZE (1020/4)
3668 /* Add a constant to the pool and return its offset within the current
3669 pool.
3671 X is the rtx we want to replace. MODE is its mode. On return,
3672 ADDRESS_ONLY will be non-zero if we really want the address of such
3673 a constant, not the constant itself. */
3674 static HOST_WIDE_INT
3676 rtx x;
3679 {
3681 HOST_WIDE_INT offset;
3689 {
3693 }
3694 #ifndef AOF_ASSEMBLER
3697 #endif
3699 #ifdef AOF_ASSEMBLER
3700 /* PIC Symbol references need to be converted into offsets into the
3701 based area. */
3706 /* First see if we've already got it */
3708 {
3711 {
3713 {
3716 }
3719 }
3720 }
3722 /* Need a new one */
3727 else
3733 pool_size++;
3735 }
3737 /* Output the literal table */
3738 static void
3740 rtx scan;
3741 {
3749 {
3753 {
3765 }
3766 }
3771 }
3773 /* Non zero if the src operand needs to be fixed up */
3774 static int
3776 rtx src;
3779 {
3781 {
3791 }
3792 #ifndef AOF_ASSEMBLER
3795 #endif
3796 else
3800 }
3802 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3803 static rtx
3805 rtx from;
3807 {
3813 {
3814 rtx tmp;
3819 /* Count the length of this insn */
3825 /* Handle table jumps as a single entity. */
3834 {
3838 /* Continue after the dispatch table. */
3842 }
3843 else
3848 }
3851 {
3852 /* We didn't find a barrier in time to
3853 dump our stuff, so we'll make one. */
3858 else
3861 /* Walk back to be just before any jump. */
3871 }
3874 }
3876 /* Non zero if the insn is a move instruction which needs to be fixed. */
3877 static int
3879 rtx insn;
3880 {
3884 {
3898 else
3902 }
3904 }
3906 void
3908 rtx first;
3909 {
3910 rtx insn;
3913 #if 0
3914 /* The ldr instruction can work with up to a 4k offset, and most constants
3915 will be loaded with one of these instructions; however, the adr
3916 instruction and the ldf instructions only work with a 1k offset. This
3917 code needs to be rewritten to use the 4k offset when possible, and to
3918 adjust when a 1k offset is needed. For now we just use a 1k offset
3919 from the start. */
3922 /* Floating point operands can't work further than 1024 bytes from the
3923 PC, so to make things simple we restrict all loads for such functions.
3924 */
3926 {
3931 {
3934 }
3935 }
3936 #else
3941 {
3943 {
3944 /* This is a broken move instruction, scan ahead looking for
3945 a barrier to stick the constant table behind */
3946 rtx scan;
3949 /* Now find all the moves between the points and modify them */
3951 {
3953 {
3954 /* This is a broken move instruction, add it to the pool */
3959 HOST_WIDE_INT offset;
3961 rtx newsrc;
3962 rtx addr;
3966 /* If this is an HImode constant load, convert it into
3967 an SImode constant load. Since the register is always
3968 32 bits this is safe. We have to do this, since the
3969 load pc-relative instruction only does a 32-bit load. */
3971 {
3976 }
3980 pool_vector_label),
3981 offset);
3983 /* If we only want the address of the pool entry, or
3984 for wide moves to integer regs we need to split
3985 the address calculation off into a separate insn.
3986 If necessary, the load can then be done with a
3987 load-multiple. This is safe, since we have
3988 already noted the length of such insns to be 8,
3989 and we are immediately over-writing the scratch
3990 we have grabbed with the final result. */
3993 {
3994 rtx reg;
3998 else
4002 newinsn);
4004 }
4007 {
4010 /* XXX Fixme -- I think the following is bogus. */
4011 /* Build a jump insn wrapper around the move instead
4012 of an ordinary insn, because we want to have room for
4013 the target label rtx in fld[7], which an ordinary
4014 insn doesn't have. */
4015 newinsn
4017 newsrc),
4018 newinsn);
4021 /* But it's still an ordinary insn */
4023 }
4025 /* Kill old insn */
4028 }
4029 }
4032 }
4033 }
4036 }
4038 \f
4039 /* Routines to output assembly language. */
4041 /* If the rtx is the correct value then return the string of the number.
4042 In this way we can ensure that valid double constants are generated even
4043 when cross compiling. */
4046 rtx x;
4047 {
4048 REAL_VALUE_TYPE r;
4060 }
4062 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4066 {
4077 }
4079 /* Output the operands of a LDM/STM instruction to STREAM.
4080 MASK is the ARM register set mask of which only bits 0-15 are important.
4081 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4082 must follow the register list. */
4084 void
4089 {
4098 {
4103 }
4106 }
4108 /* Output a 'call' insn. */
4113 {
4114 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4117 {
4120 }
4125 else
4129 }
4131 static int
4134 {
4142 {
4145 {
4148 }
4151 /* Scan through the sub-elements and change any references there */
4160 }
4161 }
4163 /* Output a 'call' insn that is a reference in memory. */
4168 {
4170 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4171 */
4176 {
4180 }
4181 else
4182 {
4185 }
4188 }
4191 /* Output a move from arm registers to an fpu registers.
4192 OPERANDS[0] is an fpu register.
4193 OPERANDS[1] is the first registers of an arm register pair. */
4198 {
4212 }
4214 /* Output a move from an fpu register to arm registers.
4215 OPERANDS[0] is the first registers of an arm register pair.
4216 OPERANDS[1] is an fpu register. */
4221 {
4235 }
4237 /* Output a move from arm registers to arm registers of a long double
4238 OPERANDS[0] is the destination.
4239 OPERANDS[1] is the source. */
4243 {
4244 /* We have to be careful here because the two might overlap */
4251 {
4253 {
4257 }
4258 }
4259 else
4260 {
4262 {
4266 }
4267 }
4270 }
4273 /* Output a move from arm registers to an fpu registers.
4274 OPERANDS[0] is an fpu register.
4275 OPERANDS[1] is the first registers of an arm register pair. */
4280 {
4291 }
4293 /* Output a move from an fpu register to arm registers.
4294 OPERANDS[0] is the first registers of an arm register pair.
4295 OPERANDS[1] is an fpu register. */
4300 {
4312 }
4314 /* Output a move between double words.
4315 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4316 or MEM<-REG and all MEMs must be offsettable addresses. */
4321 {
4327 {
4332 {
4337 /* Ensure the second source is not overwritten */
4340 else
4342 }
4344 {
4346 {
4355 }
4359 {
4363 }
4364 else
4365 {
4369 }
4372 }
4374 {
4375 #if HOST_BITS_PER_WIDE_INT > 32
4376 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4377 what the upper word is. */
4379 {
4382 }
4383 else
4384 {
4387 }
4388 #else
4389 /* Sign extend the intval into the high-order word */
4391 {
4395 }
4396 else
4398 #endif
4401 }
4403 {
4405 {
4434 {
4439 {
4441 {
4443 {
4453 }
4456 else
4458 }
4459 else
4461 }
4462 else
4465 }
4466 else
4467 {
4469 /* Take care of overlapping base/data reg. */
4471 {
4474 }
4475 else
4476 {
4479 }
4480 }
4481 }
4482 }
4483 else
4485 }
4487 {
4492 {
4515 {
4517 {
4529 }
4530 }
4531 /* Fall through */
4538 }
4539 }
4540 else
4544 }
4547 /* Output an arbitrary MOV reg, #n.
4548 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4553 {
4558 /* Try to use one MOV */
4560 {
4563 }
4565 /* Try to use one MVN */
4567 {
4571 }
4573 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4577 n_ones++;
4582 else
4584 n);
4587 }
4590 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4591 adding zero to one register, output nothing. */
4596 {
4600 {
4605 else
4608 n);
4609 }
4612 }
4614 /* Output a multiple immediate operation.
4615 OPERANDS is the vector of operands referred to in the output patterns.
4616 INSTR1 is the output pattern to use for the first constant.
4617 INSTR2 is the output pattern to use for subsequent constants.
4618 IMMED_OP is the index of the constant slot in OPERANDS.
4619 N is the constant value. */
4626 HOST_WIDE_INT n;
4627 {
4628 #if HOST_BITS_PER_WIDE_INT > 32
4630 #endif
4633 {
4636 }
4637 else
4638 {
4642 /* Note that n is never zero here (which would give no output) */
4644 {
4646 {
4651 }
4652 }
4653 }
4655 }
4658 /* Return the appropriate ARM instruction for the operation code.
4659 The returned result should not be overwritten. OP is the rtx of the
4660 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4661 was shifted. */
4665 rtx op;
4667 {
4669 {
4687 }
4688 }
4691 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4692 for the operation code. The returned result should not be overwritten.
4693 OP is the rtx code of the shift.
4694 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4695 shift. */
4699 rtx op;
4701 {
4709 else
4713 {
4731 /* We never have to worry about the amount being other than a
4732 power of 2, since this case can never be reloaded from a reg. */
4735 else
4741 }
4744 {
4745 /* This is not 100% correct, but follows from the desire to merge
4746 multiplication by a power of 2 with the recognizer for a
4747 shift. >=32 is not a valid shift for "asl", so we must try and
4748 output a shift that produces the correct arithmetical result.
4749 Using lsr #32 is identical except for the fact that the carry bit
4750 is not set correctly if we set the flags; but we never use the
4751 carry bit from such an operation, so we can ignore that. */
4755 {
4759 }
4761 /* Shifts of 0 are no-ops. */
4764 }
4767 }
4770 /* Obtain the shift from the POWER of two. */
4772 static HOST_WIDE_INT
4774 HOST_WIDE_INT power;
4775 {
4779 {
4782 shift++;
4783 }
4786 }
4788 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4789 /bin/as is horribly restrictive. */
4791 void
4796 {
4802 {
4806 {
4812 }
4815 {
4817 len_so_far++;
4818 }
4821 {
4823 len_so_far++;
4824 }
4825 else
4826 {
4829 }
4831 chars_so_far++;
4832 }
4835 }
4836 \f
4838 /* Try to determine whether a pattern really clobbers the link register.
4839 This information is useful when peepholing, so that lr need not be pushed
4840 if we combine a call followed by a return.
4841 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4842 such a check should not be needed because these only update an existing
4843 value within a register; the register must still be set elsewhere within
4844 the function. */
4846 static int
4848 rtx x;
4849 {
4853 {
4856 {
4870 }
4880 {
4891 }
4898 }
4899 }
4901 static int
4903 rtx first;
4904 {
4908 {
4910 {
4924 /* Don't yet know how to handle those calls that are not to a
4925 SYMBOL_REF */
4930 {
4946 }
4948 /* A call can be made (by peepholing) not to clobber lr iff it is
4949 followed by a return. There may, however, be a use insn iff
4950 we are returning the result of the call.
4951 If we run off the end of the insn chain, then that means the
4952 call was at the end of the function. Unfortunately we don't
4953 have a return insn for the peephole to recognize, so we
4954 must reject this. (Can this be fixed by adding our own insn?) */
4958 /* No need to worry about lr if the call never returns */
4976 }
4977 }
4979 /* We have reached the end of the chain so lr was _not_ clobbered */
4981 }
4985 rtx operand;
4988 {
4997 {
4999 /* If this function was declared non-returning, and we have found a tail
5000 call, then we have to trust that the called function won't return. */
5004 /* Otherwise, trap an attempted return by aborting. */
5010 }
5017 live_regs++;
5020 live_regs++;
5026 {
5028 live_regs++;
5033 else
5039 {
5044 }
5047 {
5057 }
5058 else
5059 {
5063 else
5065 }
5070 {
5077 }
5078 }
5080 {
5083 else
5088 }
5091 }
5093 /* Return nonzero if optimizing and the current function is volatile.
5094 Such functions never return, and many memory cycles can be saved
5095 by not storing register values that will never be needed again.
5096 This optimization was added to speed up context switching in a
5097 kernel application. */
5099 int
5101 {
5103 }
5105 /* The amount of stack adjustment that happens here, in output_return and in
5106 output_epilogue must be exactly the same as was calculated during reload,
5107 or things will point to the wrong place. The only time we can safely
5108 ignore this constraint is when a function has no arguments on the stack,
5109 no stack frame requirement and no live registers execpt for `lr'. If we
5110 can guarantee that by making all function calls into tail calls and that
5111 lr is not clobbered in any other way, then there is no need to push lr
5112 onto the stack. */
5114 void
5118 {
5123 /* Nonzero if we must stuff some register arguments onto the stack as if
5124 they were passed there. */
5141 current_function_anonymous_args);
5156 {
5160 else
5162 }
5165 {
5166 /* if a di mode load/store multiple is used, and the base register
5167 is r3, then r4 can become an ever live register without lr
5168 doing so, in this case we need to push lr as well, or we
5169 will fail to get a proper return. */
5174 }
5178 ASM_COMMENT_START);
5180 #ifdef AOF_ASSEMBLER
5184 #endif
5185 }
5188 void
5192 {
5194 /* If we need this then it will always be at least this much */
5201 {
5206 }
5208 /* Naked functions don't have epilogues. */
5212 /* A volatile function should never return. Call abort. */
5214 {
5219 }
5223 {
5226 }
5229 {
5231 {
5234 {
5238 }
5239 }
5240 else
5241 {
5245 {
5247 {
5249 /* We can't unstack more than four registers at once */
5251 {
5256 }
5257 }
5258 else
5259 {
5266 }
5267 }
5269 /* Just in case the last register checked also needs unstacking. */
5274 }
5277 {
5281 }
5282 else
5283 {
5287 }
5288 }
5289 else
5290 {
5291 /* Restore stack pointer if necessary. */
5293 {
5298 }
5301 {
5306 }
5307 else
5308 {
5312 {
5314 {
5316 {
5319 REGISTER_PREFIX);
5321 }
5322 }
5323 else
5324 {
5331 }
5332 }
5334 /* Just in case the last register checked also needs unstacking. */
5339 }
5342 {
5344 {
5352 }
5357 else
5360 }
5361 else
5362 {
5364 {
5365 /* Restore the integer regs, and the return address into lr */
5371 }
5374 {
5375 /* Unwind the pre-pushed regs */
5379 }
5380 /* And finally, go home */
5385 else
5387 }
5388 }
5390 epilogue_done:
5392 /* Reset the ARM-specific per-function variables. */
5395 }
5397 static void
5400 {
5403 rtx par;
5407 num_regs++;
5415 {
5417 {
5422 stack_pointer_rtx)),
5428 }
5429 }
5432 {
5434 {
5437 j++;
5438 }
5439 }
5442 }
5444 static void
5448 {
5449 rtx par;
5460 base_reg++)),
5467 }
5469 void
5471 {
5480 /* Naked functions don't have prologues. */
5496 {
5499 stack_pointer_rtx));
5500 }
5503 {
5507 else
5510 }
5513 {
5514 /* If we have to push any regs, then we must push lr as well, or
5515 we won't get a proper return. */
5518 }
5520 /* For now the integer regs are still pushed in output_func_epilogue (). */
5523 {
5525 {
5532 stack_pointer_rtx)),
5534 }
5535 else
5536 {
5540 {
5542 {
5544 {
5547 }
5548 }
5549 else
5550 {
5554 }
5555 }
5559 }
5560 }
5564 (GEN_INT
5568 {
5572 }
5574 /* If we are profiling, make sure no instructions are scheduled before
5575 the call to mcount. Similarly if the user has requested no
5576 scheduling in the prolog. */
5579 }
5581 \f
5582 /* If CODE is 'd', then the X is a condition operand and the instruction
5583 should only be executed if the condition is true.
5584 if CODE is 'D', then the X is a condition operand and the instruction
5585 should only be executed if the condition is false: however, if the mode
5586 of the comparison is CCFPEmode, then always execute the instruction -- we
5587 do this because in these circumstances !GE does not necessarily imply LT;
5588 in these cases the instruction pattern will take care to make sure that
5589 an instruction containing %d will follow, thereby undoing the effects of
5590 doing this instruction unconditionally.
5591 If CODE is 'N' then X is a floating point operand that must be negated
5592 before output.
5593 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5594 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5596 void
5599 rtx x;
5601 {
5603 {
5618 {
5619 REAL_VALUE_TYPE r;
5623 }
5629 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5631 #else
5633 #endif
5635 else
5636 {
5639 }
5651 {
5652 HOST_WIDE_INT val;
5656 {
5660 else
5662 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5664 #else
5666 #endif
5667 val);
5668 }
5669 }
5690 else
5705 stream);
5712 stream);
5720 {
5723 }
5725 {
5728 }
5733 else
5734 {
5737 }
5738 }
5739 }
5741 \f
5742 /* A finite state machine takes care of noticing whether or not instructions
5743 can be conditionally executed, and thus decrease execution time and code
5744 size by deleting branch instructions. The fsm is controlled by
5745 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
5747 /* The state of the fsm controlling condition codes are:
5748 0: normal, do nothing special
5749 1: make ASM_OUTPUT_OPCODE not output this instruction
5750 2: make ASM_OUTPUT_OPCODE not output this instruction
5751 3: make instructions conditional
5752 4: make instructions conditional
5754 State transitions (state->state by whom under condition):
5755 0 -> 1 final_prescan_insn if the `target' is a label
5756 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
5757 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
5758 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
5759 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
5760 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
5761 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
5762 (the target insn is arm_target_insn).
5764 If the jump clobbers the conditions then we use states 2 and 4.
5766 A similar thing can be done with conditional return insns.
5768 XXX In case the `target' is an unconditional branch, this conditionalising
5769 of the instructions always reduces code size, but not always execution
5770 time. But then, I want to reduce the code size to somewhere near what
5771 /bin/cc produces. */
5773 /* Returns the index of the ARM condition code string in
5774 `arm_condition_codes'. COMPARISON should be an rtx like
5775 `(eq (...) (...))'. */
5777 static enum arm_cond_code
5779 rtx comparison;
5780 {
5790 {
5802 dominance:
5812 {
5818 }
5823 {
5827 }
5831 {
5837 }
5841 {
5853 }
5857 {
5861 }
5865 {
5877 }
5880 }
5883 }
5886 void
5888 rtx insn;
5891 {
5892 /* BODY will hold the body of INSN. */
5895 /* This will be 1 if trying to repeat the trick, and things need to be
5896 reversed if it appears to fail. */
5899 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5900 taken are clobbered, even if the rtl suggests otherwise. It also
5901 means that we have to grub around within the jump expression to find
5902 out what the conditions are when the jump isn't taken. */
5905 /* If we start with a return insn, we only succeed if we find another one. */
5908 /* START_INSN will hold the insn from where we start looking. This is the
5909 first insn after the following code_label if REVERSE is true. */
5912 /* If in state 4, check if the target branch is reached, in order to
5913 change back to state 0. */
5915 {
5917 {
5920 }
5922 }
5924 /* If in state 3, it is possible to repeat the trick, if this insn is an
5925 unconditional branch to a label, and immediately following this branch
5926 is the previous target label which is only used once, and the label this
5927 branch jumps to is not too far off. */
5929 {
5931 {
5934 {
5935 /* XXX Isn't this always a barrier? */
5937 }
5942 else
5944 }
5946 {
5953 {
5956 }
5957 else
5959 }
5960 else
5962 }
5969 /* This jump might be paralleled with a clobber of the condition codes
5970 the jump should always come first */
5974 #if 0
5975 /* If this is a conditional return then we don't want to know */
5981 #endif
5986 {
5989 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5994 {
5995 /* The code below is wrong for these, and I haven't time to
5996 fix it now. So we just do the safe thing and return. This
5997 whole function needs re-writing anyway. */
6000 }
6002 /* Register the insn jumped to. */
6004 {
6007 }
6011 {
6014 }
6018 {
6021 }
6022 else
6025 /* See how many insns this branch skips, and what kind of insns. If all
6026 insns are okay, and the label or unconditional branch to the same
6027 label is not too far away, succeed. */
6030 {
6031 rtx scanbody;
6038 {
6040 /* Succeed if it is the target label, otherwise fail since
6041 control falls in from somewhere else. */
6043 {
6045 {
6048 }
6049 else
6052 }
6053 else
6058 /* Succeed if the following insn is the target label.
6059 Otherwise fail.
6060 If return insns are used then the last insn in a function
6061 will be a barrier. */
6064 {
6066 {
6069 }
6070 else
6073 }
6074 else
6079 /* If using 32-bit addresses the cc is not preserved over
6080 calls */
6082 {
6083 /* Succeed if the following insn is the target label,
6084 or if the following two insns are a barrier and
6085 the target label. */
6092 {
6094 {
6097 }
6098 else
6101 }
6102 else
6104 }
6108 /* If this is an unconditional branch to the same label, succeed.
6109 If it is to another label, do nothing. If it is conditional,
6110 fail. */
6111 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6116 {
6119 {
6122 }
6125 }
6126 /* Fail if a conditional return is undesirable (eg on a
6127 StrongARM), but still allow this if optimizing for size. */
6134 {
6137 }
6139 {
6141 {
6147 }
6148 }
6152 /* Instructions using or affecting the condition codes make it
6153 fail. */
6163 }
6164 }
6166 {
6170 {
6172 {
6177 }
6179 {
6180 /* Oh, dear! we ran off the end.. give up */
6185 }
6187 }
6188 else
6191 {
6194 arm_current_cc =
6201 }
6202 else
6203 {
6204 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6205 what it was. */
6209 }
6213 }
6214 /* restore recog_operand (getting the attributes of other insns can
6215 destroy this array, but final.c assumes that it remains intact
6216 across this call; since the insn has been recognized already we
6217 call recog direct). */
6219 }
6220 }
6222 #ifdef AOF_ASSEMBLER
6223 /* Special functions only needed when producing AOF syntax assembler. */
6226 struct pic_chain
6227 {
6230 };
6234 rtx
6236 rtx x;
6237 {
6242 {
6243 /* This needs to persist throughout the compilation. */
6247 }
6258 }
6260 void
6263 {
6275 {
6279 }
6280 }
6286 {
6289 arm_text_section_count++);
6293 }
6299 {
6303 }
6305 /* The AOF assembler is religiously strict about declarations of
6306 imported and exported symbols, so that it is impossible to declare
6307 a function as imported near the beginning of the file, and then to
6308 export it later on. It is, however, possible to delay the decision
6309 until all the functions in the file have been compiled. To get
6310 around this, we maintain a list of the imports and exports, and
6311 delete from it any that are subsequently defined. At the end of
6312 compilation we spit the remainder of the list out before the END
6313 directive. */
6315 struct import
6316 {
6319 };
6323 void
6326 {
6337 }
6339 void
6342 {
6346 {
6348 {
6351 }
6352 }
6353 }
6357 void
6360 {
6361 /* The AOF assembler needs this to cause the startup code to be extracted
6362 from the library. Brining in __main causes the whole thing to work
6363 automagically. */
6365 {
6369 }
6371 /* Now dump the remaining imports. */
6373 {
6378 }
6379 }