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* config/arm/elf.h (ASM_OUTPUT_ALIGNED_COMMON): Remove definition.
[official-gcc.git] / gcc / combine.c
blobf7c98526833e23f11bb7f2d6123a34dc8d375dd1
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
77 #include "config.h"
78 #include "system.h"
79 #include "coretypes.h"
80 #include "tm.h"
81 #include "rtl.h"
82 #include "tm_p.h"
83 #include "flags.h"
84 #include "regs.h"
85 #include "hard-reg-set.h"
86 #include "basic-block.h"
87 #include "insn-config.h"
88 #include "function.h"
89 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "expr.h"
91 #include "insn-attr.h"
92 #include "recog.h"
93 #include "real.h"
94 #include "toplev.h"
95
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
99
100 /* Number of attempts to combine instructions in this function. */
101
102 static int combine_attempts;
103
104 /* Number of attempts that got as far as substitution in this function. */
105
106 static int combine_merges;
107
108 /* Number of instructions combined with added SETs in this function. */
109
110 static int combine_extras;
111
112 /* Number of instructions combined in this function. */
113
114 static int combine_successes;
115
116 /* Totals over entire compilation. */
117
118 static int total_attempts, total_merges, total_extras, total_successes;
119
120 \f
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
127
128 static int *uid_cuid;
129 static int max_uid_cuid;
130
131 /* Get the cuid of an insn. */
132
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
135
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
138
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
141
142 #define nonzero_bits(X, M) \
143 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
144
145 #define num_sign_bit_copies(X, M) \
146 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
147
148 /* Maximum register number, which is the size of the tables below. */
149
150 static unsigned int combine_max_regno;
151
152 /* Record last point of death of (hard or pseudo) register n. */
153
154 static rtx *reg_last_death;
155
156 /* Record last point of modification of (hard or pseudo) register n. */
157
158 static rtx *reg_last_set;
159
160 /* Record the cuid of the last insn that invalidated memory
161 (anything that writes memory, and subroutine calls, but not pushes). */
162
163 static int mem_last_set;
164
165 /* Record the cuid of the last CALL_INSN
166 so we can tell whether a potential combination crosses any calls. */
167
168 static int last_call_cuid;
169
170 /* When `subst' is called, this is the insn that is being modified
171 (by combining in a previous insn). The PATTERN of this insn
172 is still the old pattern partially modified and it should not be
173 looked at, but this may be used to examine the successors of the insn
174 to judge whether a simplification is valid. */
175
176 static rtx subst_insn;
177
178 /* This is the lowest CUID that `subst' is currently dealing with.
179 get_last_value will not return a value if the register was set at or
180 after this CUID. If not for this mechanism, we could get confused if
181 I2 or I1 in try_combine were an insn that used the old value of a register
182 to obtain a new value. In that case, we might erroneously get the
183 new value of the register when we wanted the old one. */
184
185 static int subst_low_cuid;
186
187 /* This contains any hard registers that are used in newpat; reg_dead_at_p
188 must consider all these registers to be always live. */
189
190 static HARD_REG_SET newpat_used_regs;
191
192 /* This is an insn to which a LOG_LINKS entry has been added. If this
193 insn is the earlier than I2 or I3, combine should rescan starting at
194 that location. */
195
196 static rtx added_links_insn;
197
198 /* Basic block in which we are performing combines. */
199 static basic_block this_basic_block;
200
201 /* A bitmap indicating which blocks had registers go dead at entry.
202 After combine, we'll need to re-do global life analysis with
203 those blocks as starting points. */
204 static sbitmap refresh_blocks;
205 \f
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if an
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
211
212 We use an approach similar to that used by cse, but change it in the
213 following ways:
214
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
218
219 Therefore, we maintain the following arrays:
220
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to nonzero when it is not valid
227 to use the value of this register in some
228 register's value
229
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
233 table.
234
235 Entry I in reg_last_set_value is valid if it is nonzero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
237
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
242
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
246
247 reg_last_set_invalid[i] is set nonzero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
249
250 /* Record last value assigned to (hard or pseudo) register n. */
251
252 static rtx *reg_last_set_value;
253
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
256
257 static int *reg_last_set_label;
258
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
261
262 static int *reg_last_set_table_tick;
263
264 /* Set nonzero if references to register n in expressions should not be
265 used. */
266
267 static char *reg_last_set_invalid;
268
269 /* Incremented for each label. */
270
271 static int label_tick;
272
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
277
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
280
281 If an entry is zero, it means that we don't know anything special. */
282
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
284
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
287
288 static enum machine_mode nonzero_bits_mode;
289
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
292
293 static unsigned char *reg_sign_bit_copies;
294
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
299
300 static int nonzero_sign_valid;
301
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
306
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
310 \f
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
314
315 struct undo
316 {
317 struct undo *next;
318 int is_int;
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
321 };
322
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
325
326 other_insn is nonzero if we have modified some other insn in the process
327 of working on subst_insn. It must be verified too. */
328
329 struct undobuf
330 {
331 struct undo *undos;
332 struct undo *frees;
333 rtx other_insn;
334 };
335
336 static struct undobuf undobuf;
337
338 /* Number of times the pseudo being substituted for
339 was found and replaced. */
340
341 static int n_occurrences;
342
343 static void do_SUBST PARAMS ((rtx *, rtx));
344 static void do_SUBST_INT PARAMS ((int *, int));
345 static void init_reg_last_arrays PARAMS ((void));
346 static void setup_incoming_promotions PARAMS ((void));
347 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
348 static int cant_combine_insn_p PARAMS ((rtx));
349 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
350 static int sets_function_arg_p PARAMS ((rtx));
351 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
352 static int contains_muldiv PARAMS ((rtx));
353 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
354 static void undo_all PARAMS ((void));
355 static void undo_commit PARAMS ((void));
356 static rtx *find_split_point PARAMS ((rtx *, rtx));
357 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
358 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
359 static rtx simplify_if_then_else PARAMS ((rtx));
360 static rtx simplify_set PARAMS ((rtx));
361 static rtx simplify_logical PARAMS ((rtx, int));
362 static rtx expand_compound_operation PARAMS ((rtx));
363 static rtx expand_field_assignment PARAMS ((rtx));
364 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
365 rtx, unsigned HOST_WIDE_INT, int,
366 int, int));
367 static rtx extract_left_shift PARAMS ((rtx, int));
368 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
369 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
370 unsigned HOST_WIDE_INT *));
371 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
372 unsigned HOST_WIDE_INT, rtx, int));
373 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
374 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
375 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
376 static rtx make_field_assignment PARAMS ((rtx));
377 static rtx apply_distributive_law PARAMS ((rtx));
378 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
379 unsigned HOST_WIDE_INT));
380 static unsigned HOST_WIDE_INT cached_nonzero_bits
381 PARAMS ((rtx, enum machine_mode, rtx,
382 enum machine_mode,
383 unsigned HOST_WIDE_INT));
384 static unsigned HOST_WIDE_INT nonzero_bits1
385 PARAMS ((rtx, enum machine_mode, rtx,
386 enum machine_mode,
387 unsigned HOST_WIDE_INT));
388 static unsigned int cached_num_sign_bit_copies
389 PARAMS ((rtx, enum machine_mode, rtx,
390 enum machine_mode, unsigned int));
391 static unsigned int num_sign_bit_copies1
392 PARAMS ((rtx, enum machine_mode, rtx,
393 enum machine_mode, unsigned int));
394 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
395 enum rtx_code, HOST_WIDE_INT,
396 enum machine_mode, int *));
397 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
398 rtx, int));
399 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
400 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
401 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
402 rtx, rtx));
403 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
404 static void update_table_tick PARAMS ((rtx));
405 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
406 static void check_promoted_subreg PARAMS ((rtx, rtx));
407 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
408 static void record_dead_and_set_regs PARAMS ((rtx));
409 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
410 static rtx get_last_value PARAMS ((rtx));
411 static int use_crosses_set_p PARAMS ((rtx, int));
412 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
413 static int reg_dead_at_p PARAMS ((rtx, rtx));
414 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
415 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
416 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
417 static void distribute_links PARAMS ((rtx));
418 static void mark_used_regs_combine PARAMS ((rtx));
419 static int insn_cuid PARAMS ((rtx));
420 static void record_promoted_value PARAMS ((rtx, rtx));
421 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
422 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
423 \f
424 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
425 insn. The substitution can be undone by undo_all. If INTO is already
426 set to NEWVAL, do not record this change. Because computing NEWVAL might
427 also call SUBST, we have to compute it before we put anything into
428 the undo table. */
429
430 static void
431 do_SUBST (into, newval)
432 rtx *into, newval;
433 {
434 struct undo *buf;
435 rtx oldval = *into;
436
437 if (oldval == newval)
438 return;
439
440 /* We'd like to catch as many invalid transformations here as
441 possible. Unfortunately, there are way too many mode changes
442 that are perfectly valid, so we'd waste too much effort for
443 little gain doing the checks here. Focus on catching invalid
444 transformations involving integer constants. */
445 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
446 && GET_CODE (newval) == CONST_INT)
447 {
448 /* Sanity check that we're replacing oldval with a CONST_INT
449 that is a valid sign-extension for the original mode. */
450 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
451 GET_MODE (oldval)))
452 abort ();
453
454 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
455 CONST_INT is not valid, because after the replacement, the
456 original mode would be gone. Unfortunately, we can't tell
457 when do_SUBST is called to replace the operand thereof, so we
458 perform this test on oldval instead, checking whether an
459 invalid replacement took place before we got here. */
460 if ((GET_CODE (oldval) == SUBREG
461 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
462 || (GET_CODE (oldval) == ZERO_EXTEND
463 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
464 abort ();
465 }
466
467 if (undobuf.frees)
468 buf = undobuf.frees, undobuf.frees = buf->next;
469 else
470 buf = (struct undo *) xmalloc (sizeof (struct undo));
471
472 buf->is_int = 0;
473 buf->where.r = into;
474 buf->old_contents.r = oldval;
475 *into = newval;
476
477 buf->next = undobuf.undos, undobuf.undos = buf;
478 }
479
480 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
481
482 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
483 for the value of a HOST_WIDE_INT value (including CONST_INT) is
484 not safe. */
485
486 static void
487 do_SUBST_INT (into, newval)
488 int *into, newval;
489 {
490 struct undo *buf;
491 int oldval = *into;
492
493 if (oldval == newval)
494 return;
495
496 if (undobuf.frees)
497 buf = undobuf.frees, undobuf.frees = buf->next;
498 else
499 buf = (struct undo *) xmalloc (sizeof (struct undo));
500
501 buf->is_int = 1;
502 buf->where.i = into;
503 buf->old_contents.i = oldval;
504 *into = newval;
505
506 buf->next = undobuf.undos, undobuf.undos = buf;
507 }
508
509 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
510 \f
511 /* Main entry point for combiner. F is the first insn of the function.
512 NREGS is the first unused pseudo-reg number.
513
514 Return nonzero if the combiner has turned an indirect jump
515 instruction into a direct jump. */
516 int
517 combine_instructions (f, nregs)
518 rtx f;
519 unsigned int nregs;
520 {
521 rtx insn, next;
522 #ifdef HAVE_cc0
523 rtx prev;
524 #endif
525 int i;
526 rtx links, nextlinks;
527
528 int new_direct_jump_p = 0;
529
530 combine_attempts = 0;
531 combine_merges = 0;
532 combine_extras = 0;
533 combine_successes = 0;
534
535 combine_max_regno = nregs;
536
537 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
538 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
539 reg_sign_bit_copies
540 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
541
542 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
543 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
544 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
545 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
546 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
547 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
548 reg_last_set_mode
549 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
550 reg_last_set_nonzero_bits
551 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
552 reg_last_set_sign_bit_copies
553 = (char *) xmalloc (nregs * sizeof (char));
554
555 init_reg_last_arrays ();
556
557 init_recog_no_volatile ();
558
559 /* Compute maximum uid value so uid_cuid can be allocated. */
560
561 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
562 if (INSN_UID (insn) > i)
563 i = INSN_UID (insn);
564
565 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
566 max_uid_cuid = i;
567
568 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
569
570 /* Don't use reg_nonzero_bits when computing it. This can cause problems
571 when, for example, we have j <<= 1 in a loop. */
572
573 nonzero_sign_valid = 0;
574
575 /* Compute the mapping from uids to cuids.
576 Cuids are numbers assigned to insns, like uids,
577 except that cuids increase monotonically through the code.
578
579 Scan all SETs and see if we can deduce anything about what
580 bits are known to be zero for some registers and how many copies
581 of the sign bit are known to exist for those registers.
582
583 Also set any known values so that we can use it while searching
584 for what bits are known to be set. */
585
586 label_tick = 1;
587
588 setup_incoming_promotions ();
589
590 refresh_blocks = sbitmap_alloc (last_basic_block);
591 sbitmap_zero (refresh_blocks);
592
593 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
594 {
595 uid_cuid[INSN_UID (insn)] = ++i;
596 subst_low_cuid = i;
597 subst_insn = insn;
598
599 if (INSN_P (insn))
600 {
601 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
602 NULL);
603 record_dead_and_set_regs (insn);
604
605 #ifdef AUTO_INC_DEC
606 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
607 if (REG_NOTE_KIND (links) == REG_INC)
608 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
609 NULL);
610 #endif
611 }
612
613 if (GET_CODE (insn) == CODE_LABEL)
614 label_tick++;
615 }
616
617 nonzero_sign_valid = 1;
618
619 /* Now scan all the insns in forward order. */
620
621 label_tick = 1;
622 last_call_cuid = 0;
623 mem_last_set = 0;
624 init_reg_last_arrays ();
625 setup_incoming_promotions ();
626
627 FOR_EACH_BB (this_basic_block)
628 {
629 for (insn = this_basic_block->head;
630 insn != NEXT_INSN (this_basic_block->end);
631 insn = next ? next : NEXT_INSN (insn))
632 {
633 next = 0;
634
635 if (GET_CODE (insn) == CODE_LABEL)
636 label_tick++;
637
638 else if (INSN_P (insn))
639 {
640 /* See if we know about function return values before this
641 insn based upon SUBREG flags. */
642 check_promoted_subreg (insn, PATTERN (insn));
643
644 /* Try this insn with each insn it links back to. */
645
646 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 if ((next = try_combine (insn, XEXP (links, 0),
648 NULL_RTX, &new_direct_jump_p)) != 0)
649 goto retry;
650
651 /* Try each sequence of three linked insns ending with this one. */
652
653 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
654 {
655 rtx link = XEXP (links, 0);
656
657 /* If the linked insn has been replaced by a note, then there
658 is no point in pursuing this chain any further. */
659 if (GET_CODE (link) == NOTE)
660 continue;
661
662 for (nextlinks = LOG_LINKS (link);
663 nextlinks;
664 nextlinks = XEXP (nextlinks, 1))
665 if ((next = try_combine (insn, link,
666 XEXP (nextlinks, 0),
667 &new_direct_jump_p)) != 0)
668 goto retry;
669 }
670
671 #ifdef HAVE_cc0
672 /* Try to combine a jump insn that uses CC0
673 with a preceding insn that sets CC0, and maybe with its
674 logical predecessor as well.
675 This is how we make decrement-and-branch insns.
676 We need this special code because data flow connections
677 via CC0 do not get entered in LOG_LINKS. */
678
679 if (GET_CODE (insn) == JUMP_INSN
680 && (prev = prev_nonnote_insn (insn)) != 0
681 && GET_CODE (prev) == INSN
682 && sets_cc0_p (PATTERN (prev)))
683 {
684 if ((next = try_combine (insn, prev,
685 NULL_RTX, &new_direct_jump_p)) != 0)
686 goto retry;
687
688 for (nextlinks = LOG_LINKS (prev); nextlinks;
689 nextlinks = XEXP (nextlinks, 1))
690 if ((next = try_combine (insn, prev,
691 XEXP (nextlinks, 0),
692 &new_direct_jump_p)) != 0)
693 goto retry;
694 }
695
696 /* Do the same for an insn that explicitly references CC0. */
697 if (GET_CODE (insn) == INSN
698 && (prev = prev_nonnote_insn (insn)) != 0
699 && GET_CODE (prev) == INSN
700 && sets_cc0_p (PATTERN (prev))
701 && GET_CODE (PATTERN (insn)) == SET
702 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
703 {
704 if ((next = try_combine (insn, prev,
705 NULL_RTX, &new_direct_jump_p)) != 0)
706 goto retry;
707
708 for (nextlinks = LOG_LINKS (prev); nextlinks;
709 nextlinks = XEXP (nextlinks, 1))
710 if ((next = try_combine (insn, prev,
711 XEXP (nextlinks, 0),
712 &new_direct_jump_p)) != 0)
713 goto retry;
714 }
715
716 /* Finally, see if any of the insns that this insn links to
717 explicitly references CC0. If so, try this insn, that insn,
718 and its predecessor if it sets CC0. */
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 if (GET_CODE (XEXP (links, 0)) == INSN
721 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
722 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
723 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
724 && GET_CODE (prev) == INSN
725 && sets_cc0_p (PATTERN (prev))
726 && (next = try_combine (insn, XEXP (links, 0),
727 prev, &new_direct_jump_p)) != 0)
728 goto retry;
729 #endif
730
731 /* Try combining an insn with two different insns whose results it
732 uses. */
733 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
734 for (nextlinks = XEXP (links, 1); nextlinks;
735 nextlinks = XEXP (nextlinks, 1))
736 if ((next = try_combine (insn, XEXP (links, 0),
737 XEXP (nextlinks, 0),
738 &new_direct_jump_p)) != 0)
739 goto retry;
740
741 if (GET_CODE (insn) != NOTE)
742 record_dead_and_set_regs (insn);
743
744 retry:
745 ;
746 }
747 }
748 }
749 clear_bb_flags ();
750
751 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
752 BASIC_BLOCK (i)->flags |= BB_DIRTY);
753 new_direct_jump_p |= purge_all_dead_edges (0);
754 delete_noop_moves (f);
755
756 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
757 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
758 | PROP_KILL_DEAD_CODE);
759
760 /* Clean up. */
761 sbitmap_free (refresh_blocks);
762 free (reg_nonzero_bits);
763 free (reg_sign_bit_copies);
764 free (reg_last_death);
765 free (reg_last_set);
766 free (reg_last_set_value);
767 free (reg_last_set_table_tick);
768 free (reg_last_set_label);
769 free (reg_last_set_invalid);
770 free (reg_last_set_mode);
771 free (reg_last_set_nonzero_bits);
772 free (reg_last_set_sign_bit_copies);
773 free (uid_cuid);
774
775 {
776 struct undo *undo, *next;
777 for (undo = undobuf.frees; undo; undo = next)
778 {
779 next = undo->next;
780 free (undo);
781 }
782 undobuf.frees = 0;
783 }
784
785 total_attempts += combine_attempts;
786 total_merges += combine_merges;
787 total_extras += combine_extras;
788 total_successes += combine_successes;
789
790 nonzero_sign_valid = 0;
791
792 /* Make recognizer allow volatile MEMs again. */
793 init_recog ();
794
795 return new_direct_jump_p;
796 }
797
798 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
799
800 static void
801 init_reg_last_arrays ()
802 {
803 unsigned int nregs = combine_max_regno;
804
805 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
806 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
807 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
808 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
809 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
810 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
811 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
812 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
813 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
814 }
815 \f
816 /* Set up any promoted values for incoming argument registers. */
817
818 static void
819 setup_incoming_promotions ()
820 {
821 #ifdef PROMOTE_FUNCTION_ARGS
822 unsigned int regno;
823 rtx reg;
824 enum machine_mode mode;
825 int unsignedp;
826 rtx first = get_insns ();
827
828 #ifndef OUTGOING_REGNO
829 #define OUTGOING_REGNO(N) N
830 #endif
831 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
832 /* Check whether this register can hold an incoming pointer
833 argument. FUNCTION_ARG_REGNO_P tests outgoing register
834 numbers, so translate if necessary due to register windows. */
835 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
836 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
837 {
838 record_value_for_reg
839 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
840 : SIGN_EXTEND),
841 GET_MODE (reg),
842 gen_rtx_CLOBBER (mode, const0_rtx)));
843 }
844 #endif
845 }
846 \f
847 /* Called via note_stores. If X is a pseudo that is narrower than
848 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
849
850 If we are setting only a portion of X and we can't figure out what
851 portion, assume all bits will be used since we don't know what will
852 be happening.
853
854 Similarly, set how many bits of X are known to be copies of the sign bit
855 at all locations in the function. This is the smallest number implied
856 by any set of X. */
857
858 static void
859 set_nonzero_bits_and_sign_copies (x, set, data)
860 rtx x;
861 rtx set;
862 void *data ATTRIBUTE_UNUSED;
863 {
864 unsigned int num;
865
866 if (GET_CODE (x) == REG
867 && REGNO (x) >= FIRST_PSEUDO_REGISTER
868 /* If this register is undefined at the start of the file, we can't
869 say what its contents were. */
870 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
871 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
872 {
873 if (set == 0 || GET_CODE (set) == CLOBBER)
874 {
875 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
876 reg_sign_bit_copies[REGNO (x)] = 1;
877 return;
878 }
879
880 /* If this is a complex assignment, see if we can convert it into a
881 simple assignment. */
882 set = expand_field_assignment (set);
883
884 /* If this is a simple assignment, or we have a paradoxical SUBREG,
885 set what we know about X. */
886
887 if (SET_DEST (set) == x
888 || (GET_CODE (SET_DEST (set)) == SUBREG
889 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
890 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
891 && SUBREG_REG (SET_DEST (set)) == x))
892 {
893 rtx src = SET_SRC (set);
894
895 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
896 /* If X is narrower than a word and SRC is a non-negative
897 constant that would appear negative in the mode of X,
898 sign-extend it for use in reg_nonzero_bits because some
899 machines (maybe most) will actually do the sign-extension
900 and this is the conservative approach.
901
902 ??? For 2.5, try to tighten up the MD files in this regard
903 instead of this kludge. */
904
905 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
906 && GET_CODE (src) == CONST_INT
907 && INTVAL (src) > 0
908 && 0 != (INTVAL (src)
909 & ((HOST_WIDE_INT) 1
910 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
911 src = GEN_INT (INTVAL (src)
912 | ((HOST_WIDE_INT) (-1)
913 << GET_MODE_BITSIZE (GET_MODE (x))));
914 #endif
915
916 /* Don't call nonzero_bits if it cannot change anything. */
917 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
918 reg_nonzero_bits[REGNO (x)]
919 |= nonzero_bits (src, nonzero_bits_mode);
920 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
921 if (reg_sign_bit_copies[REGNO (x)] == 0
922 || reg_sign_bit_copies[REGNO (x)] > num)
923 reg_sign_bit_copies[REGNO (x)] = num;
924 }
925 else
926 {
927 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
928 reg_sign_bit_copies[REGNO (x)] = 1;
929 }
930 }
931 }
932 \f
933 /* See if INSN can be combined into I3. PRED and SUCC are optionally
934 insns that were previously combined into I3 or that will be combined
935 into the merger of INSN and I3.
936
937 Return 0 if the combination is not allowed for any reason.
938
939 If the combination is allowed, *PDEST will be set to the single
940 destination of INSN and *PSRC to the single source, and this function
941 will return 1. */
942
943 static int
944 can_combine_p (insn, i3, pred, succ, pdest, psrc)
945 rtx insn;
946 rtx i3;
947 rtx pred ATTRIBUTE_UNUSED;
948 rtx succ;
949 rtx *pdest, *psrc;
950 {
951 int i;
952 rtx set = 0, src, dest;
953 rtx p;
954 #ifdef AUTO_INC_DEC
955 rtx link;
956 #endif
957 int all_adjacent = (succ ? (next_active_insn (insn) == succ
958 && next_active_insn (succ) == i3)
959 : next_active_insn (insn) == i3);
960
961 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
962 or a PARALLEL consisting of such a SET and CLOBBERs.
963
964 If INSN has CLOBBER parallel parts, ignore them for our processing.
965 By definition, these happen during the execution of the insn. When it
966 is merged with another insn, all bets are off. If they are, in fact,
967 needed and aren't also supplied in I3, they may be added by
968 recog_for_combine. Otherwise, it won't match.
969
970 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
971 note.
972
973 Get the source and destination of INSN. If more than one, can't
974 combine. */
975
976 if (GET_CODE (PATTERN (insn)) == SET)
977 set = PATTERN (insn);
978 else if (GET_CODE (PATTERN (insn)) == PARALLEL
979 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
980 {
981 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
982 {
983 rtx elt = XVECEXP (PATTERN (insn), 0, i);
984
985 switch (GET_CODE (elt))
986 {
987 /* This is important to combine floating point insns
988 for the SH4 port. */
989 case USE:
990 /* Combining an isolated USE doesn't make sense.
991 We depend here on combinable_i3pat to reject them. */
992 /* The code below this loop only verifies that the inputs of
993 the SET in INSN do not change. We call reg_set_between_p
994 to verify that the REG in the USE does not change between
995 I3 and INSN.
996 If the USE in INSN was for a pseudo register, the matching
997 insn pattern will likely match any register; combining this
998 with any other USE would only be safe if we knew that the
999 used registers have identical values, or if there was
1000 something to tell them apart, e.g. different modes. For
1001 now, we forgo such complicated tests and simply disallow
1002 combining of USES of pseudo registers with any other USE. */
1003 if (GET_CODE (XEXP (elt, 0)) == REG
1004 && GET_CODE (PATTERN (i3)) == PARALLEL)
1005 {
1006 rtx i3pat = PATTERN (i3);
1007 int i = XVECLEN (i3pat, 0) - 1;
1008 unsigned int regno = REGNO (XEXP (elt, 0));
1009
1010 do
1011 {
1012 rtx i3elt = XVECEXP (i3pat, 0, i);
1013
1014 if (GET_CODE (i3elt) == USE
1015 && GET_CODE (XEXP (i3elt, 0)) == REG
1016 && (REGNO (XEXP (i3elt, 0)) == regno
1017 ? reg_set_between_p (XEXP (elt, 0),
1018 PREV_INSN (insn), i3)
1019 : regno >= FIRST_PSEUDO_REGISTER))
1020 return 0;
1021 }
1022 while (--i >= 0);
1023 }
1024 break;
1025
1026 /* We can ignore CLOBBERs. */
1027 case CLOBBER:
1028 break;
1029
1030 case SET:
1031 /* Ignore SETs whose result isn't used but not those that
1032 have side-effects. */
1033 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1034 && ! side_effects_p (elt))
1035 break;
1036
1037 /* If we have already found a SET, this is a second one and
1038 so we cannot combine with this insn. */
1039 if (set)
1040 return 0;
1041
1042 set = elt;
1043 break;
1044
1045 default:
1046 /* Anything else means we can't combine. */
1047 return 0;
1048 }
1049 }
1050
1051 if (set == 0
1052 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1053 so don't do anything with it. */
1054 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1055 return 0;
1056 }
1057 else
1058 return 0;
1059
1060 if (set == 0)
1061 return 0;
1062
1063 set = expand_field_assignment (set);
1064 src = SET_SRC (set), dest = SET_DEST (set);
1065
1066 /* Don't eliminate a store in the stack pointer. */
1067 if (dest == stack_pointer_rtx
1068 /* Don't combine with an insn that sets a register to itself if it has
1069 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1070 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1071 /* Can't merge an ASM_OPERANDS. */
1072 || GET_CODE (src) == ASM_OPERANDS
1073 /* Can't merge a function call. */
1074 || GET_CODE (src) == CALL
1075 /* Don't eliminate a function call argument. */
1076 || (GET_CODE (i3) == CALL_INSN
1077 && (find_reg_fusage (i3, USE, dest)
1078 || (GET_CODE (dest) == REG
1079 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1080 && global_regs[REGNO (dest)])))
1081 /* Don't substitute into an incremented register. */
1082 || FIND_REG_INC_NOTE (i3, dest)
1083 || (succ && FIND_REG_INC_NOTE (succ, dest))
1084 #if 0
1085 /* Don't combine the end of a libcall into anything. */
1086 /* ??? This gives worse code, and appears to be unnecessary, since no
1087 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1088 use REG_RETVAL notes for noconflict blocks, but other code here
1089 makes sure that those insns don't disappear. */
1090 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1091 #endif
1092 /* Make sure that DEST is not used after SUCC but before I3. */
1093 || (succ && ! all_adjacent
1094 && reg_used_between_p (dest, succ, i3))
1095 /* Make sure that the value that is to be substituted for the register
1096 does not use any registers whose values alter in between. However,
1097 If the insns are adjacent, a use can't cross a set even though we
1098 think it might (this can happen for a sequence of insns each setting
1099 the same destination; reg_last_set of that register might point to
1100 a NOTE). If INSN has a REG_EQUIV note, the register is always
1101 equivalent to the memory so the substitution is valid even if there
1102 are intervening stores. Also, don't move a volatile asm or
1103 UNSPEC_VOLATILE across any other insns. */
1104 || (! all_adjacent
1105 && (((GET_CODE (src) != MEM
1106 || ! find_reg_note (insn, REG_EQUIV, src))
1107 && use_crosses_set_p (src, INSN_CUID (insn)))
1108 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1109 || GET_CODE (src) == UNSPEC_VOLATILE))
1110 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1111 better register allocation by not doing the combine. */
1112 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1113 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1114 /* Don't combine across a CALL_INSN, because that would possibly
1115 change whether the life span of some REGs crosses calls or not,
1116 and it is a pain to update that information.
1117 Exception: if source is a constant, moving it later can't hurt.
1118 Accept that special case, because it helps -fforce-addr a lot. */
1119 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1120 return 0;
1121
1122 /* DEST must either be a REG or CC0. */
1123 if (GET_CODE (dest) == REG)
1124 {
1125 /* If register alignment is being enforced for multi-word items in all
1126 cases except for parameters, it is possible to have a register copy
1127 insn referencing a hard register that is not allowed to contain the
1128 mode being copied and which would not be valid as an operand of most
1129 insns. Eliminate this problem by not combining with such an insn.
1130
1131 Also, on some machines we don't want to extend the life of a hard
1132 register. */
1133
1134 if (GET_CODE (src) == REG
1135 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1136 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1137 /* Don't extend the life of a hard register unless it is
1138 user variable (if we have few registers) or it can't
1139 fit into the desired register (meaning something special
1140 is going on).
1141 Also avoid substituting a return register into I3, because
1142 reload can't handle a conflict with constraints of other
1143 inputs. */
1144 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1145 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1146 return 0;
1147 }
1148 else if (GET_CODE (dest) != CC0)
1149 return 0;
1150
1151 /* Don't substitute for a register intended as a clobberable operand.
1152 Similarly, don't substitute an expression containing a register that
1153 will be clobbered in I3. */
1154 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1155 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1156 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1157 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1158 src)
1159 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1160 return 0;
1161
1162 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1163 or not), reject, unless nothing volatile comes between it and I3 */
1164
1165 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1166 {
1167 /* Make sure succ doesn't contain a volatile reference. */
1168 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1169 return 0;
1170
1171 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1172 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1173 return 0;
1174 }
1175
1176 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1177 to be an explicit register variable, and was chosen for a reason. */
1178
1179 if (GET_CODE (src) == ASM_OPERANDS
1180 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1181 return 0;
1182
1183 /* If there are any volatile insns between INSN and I3, reject, because
1184 they might affect machine state. */
1185
1186 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1187 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1188 return 0;
1189
1190 /* If INSN or I2 contains an autoincrement or autodecrement,
1191 make sure that register is not used between there and I3,
1192 and not already used in I3 either.
1193 Also insist that I3 not be a jump; if it were one
1194 and the incremented register were spilled, we would lose. */
1195
1196 #ifdef AUTO_INC_DEC
1197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1198 if (REG_NOTE_KIND (link) == REG_INC
1199 && (GET_CODE (i3) == JUMP_INSN
1200 || reg_used_between_p (XEXP (link, 0), insn, i3)
1201 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1202 return 0;
1203 #endif
1204
1205 #ifdef HAVE_cc0
1206 /* Don't combine an insn that follows a CC0-setting insn.
1207 An insn that uses CC0 must not be separated from the one that sets it.
1208 We do, however, allow I2 to follow a CC0-setting insn if that insn
1209 is passed as I1; in that case it will be deleted also.
1210 We also allow combining in this case if all the insns are adjacent
1211 because that would leave the two CC0 insns adjacent as well.
1212 It would be more logical to test whether CC0 occurs inside I1 or I2,
1213 but that would be much slower, and this ought to be equivalent. */
1214
1215 p = prev_nonnote_insn (insn);
1216 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1217 && ! all_adjacent)
1218 return 0;
1219 #endif
1220
1221 /* If we get here, we have passed all the tests and the combination is
1222 to be allowed. */
1223
1224 *pdest = dest;
1225 *psrc = src;
1226
1227 return 1;
1228 }
1229 \f
1230 /* Check if PAT is an insn - or a part of it - used to set up an
1231 argument for a function in a hard register. */
1232
1233 static int
1234 sets_function_arg_p (pat)
1235 rtx pat;
1236 {
1237 int i;
1238 rtx inner_dest;
1239
1240 switch (GET_CODE (pat))
1241 {
1242 case INSN:
1243 return sets_function_arg_p (PATTERN (pat));
1244
1245 case PARALLEL:
1246 for (i = XVECLEN (pat, 0); --i >= 0;)
1247 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1248 return 1;
1249
1250 break;
1251
1252 case SET:
1253 inner_dest = SET_DEST (pat);
1254 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1255 || GET_CODE (inner_dest) == SUBREG
1256 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1257 inner_dest = XEXP (inner_dest, 0);
1258
1259 return (GET_CODE (inner_dest) == REG
1260 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1261 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1262
1263 default:
1264 break;
1265 }
1266
1267 return 0;
1268 }
1269
1270 /* LOC is the location within I3 that contains its pattern or the component
1271 of a PARALLEL of the pattern. We validate that it is valid for combining.
1272
1273 One problem is if I3 modifies its output, as opposed to replacing it
1274 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1275 so would produce an insn that is not equivalent to the original insns.
1276
1277 Consider:
1278
1279 (set (reg:DI 101) (reg:DI 100))
1280 (set (subreg:SI (reg:DI 101) 0) <foo>)
1281
1282 This is NOT equivalent to:
1283
1284 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1285 (set (reg:DI 101) (reg:DI 100))])
1286
1287 Not only does this modify 100 (in which case it might still be valid
1288 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1289
1290 We can also run into a problem if I2 sets a register that I1
1291 uses and I1 gets directly substituted into I3 (not via I2). In that
1292 case, we would be getting the wrong value of I2DEST into I3, so we
1293 must reject the combination. This case occurs when I2 and I1 both
1294 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1295 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1296 of a SET must prevent combination from occurring.
1297
1298 Before doing the above check, we first try to expand a field assignment
1299 into a set of logical operations.
1300
1301 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1302 we place a register that is both set and used within I3. If more than one
1303 such register is detected, we fail.
1304
1305 Return 1 if the combination is valid, zero otherwise. */
1306
1307 static int
1308 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1309 rtx i3;
1310 rtx *loc;
1311 rtx i2dest;
1312 rtx i1dest;
1313 int i1_not_in_src;
1314 rtx *pi3dest_killed;
1315 {
1316 rtx x = *loc;
1317
1318 if (GET_CODE (x) == SET)
1319 {
1320 rtx set = x ;
1321 rtx dest = SET_DEST (set);
1322 rtx src = SET_SRC (set);
1323 rtx inner_dest = dest;
1324
1325 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1326 || GET_CODE (inner_dest) == SUBREG
1327 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1328 inner_dest = XEXP (inner_dest, 0);
1329
1330 /* Check for the case where I3 modifies its output, as
1331 discussed above. */
1332 if ((inner_dest != dest
1333 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1334 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1335
1336 /* This is the same test done in can_combine_p except we can't test
1337 all_adjacent; we don't have to, since this instruction will stay
1338 in place, thus we are not considering increasing the lifetime of
1339 INNER_DEST.
1340
1341 Also, if this insn sets a function argument, combining it with
1342 something that might need a spill could clobber a previous
1343 function argument; the all_adjacent test in can_combine_p also
1344 checks this; here, we do a more specific test for this case. */
1345
1346 || (GET_CODE (inner_dest) == REG
1347 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1348 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1349 GET_MODE (inner_dest))))
1350 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1351 return 0;
1352
1353 /* If DEST is used in I3, it is being killed in this insn,
1354 so record that for later.
1355 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1356 STACK_POINTER_REGNUM, since these are always considered to be
1357 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1358 if (pi3dest_killed && GET_CODE (dest) == REG
1359 && reg_referenced_p (dest, PATTERN (i3))
1360 && REGNO (dest) != FRAME_POINTER_REGNUM
1361 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1362 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1363 #endif
1364 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1365 && (REGNO (dest) != ARG_POINTER_REGNUM
1366 || ! fixed_regs [REGNO (dest)])
1367 #endif
1368 && REGNO (dest) != STACK_POINTER_REGNUM)
1369 {
1370 if (*pi3dest_killed)
1371 return 0;
1372
1373 *pi3dest_killed = dest;
1374 }
1375 }
1376
1377 else if (GET_CODE (x) == PARALLEL)
1378 {
1379 int i;
1380
1381 for (i = 0; i < XVECLEN (x, 0); i++)
1382 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1383 i1_not_in_src, pi3dest_killed))
1384 return 0;
1385 }
1386
1387 return 1;
1388 }
1389 \f
1390 /* Return 1 if X is an arithmetic expression that contains a multiplication
1391 and division. We don't count multiplications by powers of two here. */
1392
1393 static int
1394 contains_muldiv (x)
1395 rtx x;
1396 {
1397 switch (GET_CODE (x))
1398 {
1399 case MOD: case DIV: case UMOD: case UDIV:
1400 return 1;
1401
1402 case MULT:
1403 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1404 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1405 default:
1406 switch (GET_RTX_CLASS (GET_CODE (x)))
1407 {
1408 case 'c': case '<': case '2':
1409 return contains_muldiv (XEXP (x, 0))
1410 || contains_muldiv (XEXP (x, 1));
1411
1412 case '1':
1413 return contains_muldiv (XEXP (x, 0));
1414
1415 default:
1416 return 0;
1417 }
1418 }
1419 }
1420 \f
1421 /* Determine whether INSN can be used in a combination. Return nonzero if
1422 not. This is used in try_combine to detect early some cases where we
1423 can't perform combinations. */
1424
1425 static int
1426 cant_combine_insn_p (insn)
1427 rtx insn;
1428 {
1429 rtx set;
1430 rtx src, dest;
1431
1432 /* If this isn't really an insn, we can't do anything.
1433 This can occur when flow deletes an insn that it has merged into an
1434 auto-increment address. */
1435 if (! INSN_P (insn))
1436 return 1;
1437
1438 /* Never combine loads and stores involving hard regs that are likely
1439 to be spilled. The register allocator can usually handle such
1440 reg-reg moves by tying. If we allow the combiner to make
1441 substitutions of likely-spilled regs, we may abort in reload.
1442 As an exception, we allow combinations involving fixed regs; these are
1443 not available to the register allocator so there's no risk involved. */
1444
1445 set = single_set (insn);
1446 if (! set)
1447 return 0;
1448 src = SET_SRC (set);
1449 dest = SET_DEST (set);
1450 if (GET_CODE (src) == SUBREG)
1451 src = SUBREG_REG (src);
1452 if (GET_CODE (dest) == SUBREG)
1453 dest = SUBREG_REG (dest);
1454 if (REG_P (src) && REG_P (dest)
1455 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1456 && ! fixed_regs[REGNO (src)]
1457 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1458 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1459 && ! fixed_regs[REGNO (dest)]
1460 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1461 return 1;
1462
1463 return 0;
1464 }
1465
1466 /* Try to combine the insns I1 and I2 into I3.
1467 Here I1 and I2 appear earlier than I3.
1468 I1 can be zero; then we combine just I2 into I3.
1469
1470 If we are combining three insns and the resulting insn is not recognized,
1471 try splitting it into two insns. If that happens, I2 and I3 are retained
1472 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1473 are pseudo-deleted.
1474
1475 Return 0 if the combination does not work. Then nothing is changed.
1476 If we did the combination, return the insn at which combine should
1477 resume scanning.
1478
1479 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1480 new direct jump instruction. */
1481
1482 static rtx
1483 try_combine (i3, i2, i1, new_direct_jump_p)
1484 rtx i3, i2, i1;
1485 int *new_direct_jump_p;
1486 {
1487 /* New patterns for I3 and I2, respectively. */
1488 rtx newpat, newi2pat = 0;
1489 int substed_i2 = 0, substed_i1 = 0;
1490 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1491 int added_sets_1, added_sets_2;
1492 /* Total number of SETs to put into I3. */
1493 int total_sets;
1494 /* Nonzero is I2's body now appears in I3. */
1495 int i2_is_used;
1496 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1497 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1498 /* Contains I3 if the destination of I3 is used in its source, which means
1499 that the old life of I3 is being killed. If that usage is placed into
1500 I2 and not in I3, a REG_DEAD note must be made. */
1501 rtx i3dest_killed = 0;
1502 /* SET_DEST and SET_SRC of I2 and I1. */
1503 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1504 /* PATTERN (I2), or a copy of it in certain cases. */
1505 rtx i2pat;
1506 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1507 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1508 int i1_feeds_i3 = 0;
1509 /* Notes that must be added to REG_NOTES in I3 and I2. */
1510 rtx new_i3_notes, new_i2_notes;
1511 /* Notes that we substituted I3 into I2 instead of the normal case. */
1512 int i3_subst_into_i2 = 0;
1513 /* Notes that I1, I2 or I3 is a MULT operation. */
1514 int have_mult = 0;
1515
1516 int maxreg;
1517 rtx temp;
1518 rtx link;
1519 int i;
1520
1521 /* Exit early if one of the insns involved can't be used for
1522 combinations. */
1523 if (cant_combine_insn_p (i3)
1524 || cant_combine_insn_p (i2)
1525 || (i1 && cant_combine_insn_p (i1))
1526 /* We also can't do anything if I3 has a
1527 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1528 libcall. */
1529 #if 0
1530 /* ??? This gives worse code, and appears to be unnecessary, since no
1531 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1532 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1533 #endif
1534 )
1535 return 0;
1536
1537 combine_attempts++;
1538 undobuf.other_insn = 0;
1539
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs);
1542
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1546 temp = i1, i1 = i2, i2 = temp;
1547
1548 added_links_insn = 0;
1549
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1557
1558 Note that this case handles both multiple sets in I2 and also
1559 cases where I2 has a number of CLOBBER or PARALLELs.
1560
1561 We make very conservative checks below and only try to handle the
1562 most common cases of this. For example, we only handle the case
1563 where I2 and I3 are adjacent to avoid making difficult register
1564 usage tests. */
1565
1566 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1567 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1568 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1569 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1570 && GET_CODE (PATTERN (i2)) == PARALLEL
1571 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1572 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1573 below would need to check what is inside (and reg_overlap_mentioned_p
1574 doesn't support those codes anyway). Don't allow those destinations;
1575 the resulting insn isn't likely to be recognized anyway. */
1576 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1577 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1578 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1579 SET_DEST (PATTERN (i3)))
1580 && next_real_insn (i2) == i3)
1581 {
1582 rtx p2 = PATTERN (i2);
1583
1584 /* Make sure that the destination of I3,
1585 which we are going to substitute into one output of I2,
1586 is not used within another output of I2. We must avoid making this:
1587 (parallel [(set (mem (reg 69)) ...)
1588 (set (reg 69) ...)])
1589 which is not well-defined as to order of actions.
1590 (Besides, reload can't handle output reloads for this.)
1591
1592 The problem can also happen if the dest of I3 is a memory ref,
1593 if another dest in I2 is an indirect memory ref. */
1594 for (i = 0; i < XVECLEN (p2, 0); i++)
1595 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1596 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1597 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1598 SET_DEST (XVECEXP (p2, 0, i))))
1599 break;
1600
1601 if (i == XVECLEN (p2, 0))
1602 for (i = 0; i < XVECLEN (p2, 0); i++)
1603 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1604 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1605 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1606 {
1607 combine_merges++;
1608
1609 subst_insn = i3;
1610 subst_low_cuid = INSN_CUID (i2);
1611
1612 added_sets_2 = added_sets_1 = 0;
1613 i2dest = SET_SRC (PATTERN (i3));
1614
1615 /* Replace the dest in I2 with our dest and make the resulting
1616 insn the new pattern for I3. Then skip to where we
1617 validate the pattern. Everything was set up above. */
1618 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1619 SET_DEST (PATTERN (i3)));
1620
1621 newpat = p2;
1622 i3_subst_into_i2 = 1;
1623 goto validate_replacement;
1624 }
1625 }
1626
1627 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1628 one of those words to another constant, merge them by making a new
1629 constant. */
1630 if (i1 == 0
1631 && (temp = single_set (i2)) != 0
1632 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1633 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1634 && GET_CODE (SET_DEST (temp)) == REG
1635 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1636 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1637 && GET_CODE (PATTERN (i3)) == SET
1638 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1639 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1640 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1641 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1642 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1643 {
1644 HOST_WIDE_INT lo, hi;
1645
1646 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1647 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1648 else
1649 {
1650 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1651 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1652 }
1653
1654 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1655 {
1656 /* We don't handle the case of the target word being wider
1657 than a host wide int. */
1658 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1659 abort ();
1660
1661 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1662 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1663 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1664 }
1665 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1666 hi = INTVAL (SET_SRC (PATTERN (i3)));
1667 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1668 {
1669 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1670 >> (HOST_BITS_PER_WIDE_INT - 1));
1671
1672 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1673 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1674 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1675 (INTVAL (SET_SRC (PATTERN (i3)))));
1676 if (hi == sign)
1677 hi = lo < 0 ? -1 : 0;
1678 }
1679 else
1680 /* We don't handle the case of the higher word not fitting
1681 entirely in either hi or lo. */
1682 abort ();
1683
1684 combine_merges++;
1685 subst_insn = i3;
1686 subst_low_cuid = INSN_CUID (i2);
1687 added_sets_2 = added_sets_1 = 0;
1688 i2dest = SET_DEST (temp);
1689
1690 SUBST (SET_SRC (temp),
1691 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1692
1693 newpat = PATTERN (i2);
1694 goto validate_replacement;
1695 }
1696
1697 #ifndef HAVE_cc0
1698 /* If we have no I1 and I2 looks like:
1699 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1700 (set Y OP)])
1701 make up a dummy I1 that is
1702 (set Y OP)
1703 and change I2 to be
1704 (set (reg:CC X) (compare:CC Y (const_int 0)))
1705
1706 (We can ignore any trailing CLOBBERs.)
1707
1708 This undoes a previous combination and allows us to match a branch-and-
1709 decrement insn. */
1710
1711 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1712 && XVECLEN (PATTERN (i2), 0) >= 2
1713 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1714 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1715 == MODE_CC)
1716 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1717 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1718 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1719 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1720 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1721 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1722 {
1723 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1724 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1725 break;
1726
1727 if (i == 1)
1728 {
1729 /* We make I1 with the same INSN_UID as I2. This gives it
1730 the same INSN_CUID for value tracking. Our fake I1 will
1731 never appear in the insn stream so giving it the same INSN_UID
1732 as I2 will not cause a problem. */
1733
1734 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1735 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1736 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1737 NULL_RTX);
1738
1739 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1740 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1741 SET_DEST (PATTERN (i1)));
1742 }
1743 }
1744 #endif
1745
1746 /* Verify that I2 and I1 are valid for combining. */
1747 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1748 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1749 {
1750 undo_all ();
1751 return 0;
1752 }
1753
1754 /* Record whether I2DEST is used in I2SRC and similarly for the other
1755 cases. Knowing this will help in register status updating below. */
1756 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1757 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1758 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1759
1760 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1761 in I2SRC. */
1762 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1763
1764 /* Ensure that I3's pattern can be the destination of combines. */
1765 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1766 i1 && i2dest_in_i1src && i1_feeds_i3,
1767 &i3dest_killed))
1768 {
1769 undo_all ();
1770 return 0;
1771 }
1772
1773 /* See if any of the insns is a MULT operation. Unless one is, we will
1774 reject a combination that is, since it must be slower. Be conservative
1775 here. */
1776 if (GET_CODE (i2src) == MULT
1777 || (i1 != 0 && GET_CODE (i1src) == MULT)
1778 || (GET_CODE (PATTERN (i3)) == SET
1779 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1780 have_mult = 1;
1781
1782 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1783 We used to do this EXCEPT in one case: I3 has a post-inc in an
1784 output operand. However, that exception can give rise to insns like
1785 mov r3,(r3)+
1786 which is a famous insn on the PDP-11 where the value of r3 used as the
1787 source was model-dependent. Avoid this sort of thing. */
1788
1789 #if 0
1790 if (!(GET_CODE (PATTERN (i3)) == SET
1791 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1792 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1793 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1794 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1795 /* It's not the exception. */
1796 #endif
1797 #ifdef AUTO_INC_DEC
1798 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1799 if (REG_NOTE_KIND (link) == REG_INC
1800 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1801 || (i1 != 0
1802 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1803 {
1804 undo_all ();
1805 return 0;
1806 }
1807 #endif
1808
1809 /* See if the SETs in I1 or I2 need to be kept around in the merged
1810 instruction: whenever the value set there is still needed past I3.
1811 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1812
1813 For the SET in I1, we have two cases: If I1 and I2 independently
1814 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1815 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1816 in I1 needs to be kept around unless I1DEST dies or is set in either
1817 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1818 I1DEST. If so, we know I1 feeds into I2. */
1819
1820 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1821
1822 added_sets_1
1823 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1824 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1825
1826 /* If the set in I2 needs to be kept around, we must make a copy of
1827 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1828 PATTERN (I2), we are only substituting for the original I1DEST, not into
1829 an already-substituted copy. This also prevents making self-referential
1830 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1831 I2DEST. */
1832
1833 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1834 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1835 : PATTERN (i2));
1836
1837 if (added_sets_2)
1838 i2pat = copy_rtx (i2pat);
1839
1840 combine_merges++;
1841
1842 /* Substitute in the latest insn for the regs set by the earlier ones. */
1843
1844 maxreg = max_reg_num ();
1845
1846 subst_insn = i3;
1847
1848 /* It is possible that the source of I2 or I1 may be performing an
1849 unneeded operation, such as a ZERO_EXTEND of something that is known
1850 to have the high part zero. Handle that case by letting subst look at
1851 the innermost one of them.
1852
1853 Another way to do this would be to have a function that tries to
1854 simplify a single insn instead of merging two or more insns. We don't
1855 do this because of the potential of infinite loops and because
1856 of the potential extra memory required. However, doing it the way
1857 we are is a bit of a kludge and doesn't catch all cases.
1858
1859 But only do this if -fexpensive-optimizations since it slows things down
1860 and doesn't usually win. */
1861
1862 if (flag_expensive_optimizations)
1863 {
1864 /* Pass pc_rtx so no substitutions are done, just simplifications.
1865 The cases that we are interested in here do not involve the few
1866 cases were is_replaced is checked. */
1867 if (i1)
1868 {
1869 subst_low_cuid = INSN_CUID (i1);
1870 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1871 }
1872 else
1873 {
1874 subst_low_cuid = INSN_CUID (i2);
1875 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1876 }
1877 }
1878
1879 #ifndef HAVE_cc0
1880 /* Many machines that don't use CC0 have insns that can both perform an
1881 arithmetic operation and set the condition code. These operations will
1882 be represented as a PARALLEL with the first element of the vector
1883 being a COMPARE of an arithmetic operation with the constant zero.
1884 The second element of the vector will set some pseudo to the result
1885 of the same arithmetic operation. If we simplify the COMPARE, we won't
1886 match such a pattern and so will generate an extra insn. Here we test
1887 for this case, where both the comparison and the operation result are
1888 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1889 I2SRC. Later we will make the PARALLEL that contains I2. */
1890
1891 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1892 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1893 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1894 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1895 {
1896 #ifdef EXTRA_CC_MODES
1897 rtx *cc_use;
1898 enum machine_mode compare_mode;
1899 #endif
1900
1901 newpat = PATTERN (i3);
1902 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1903
1904 i2_is_used = 1;
1905
1906 #ifdef EXTRA_CC_MODES
1907 /* See if a COMPARE with the operand we substituted in should be done
1908 with the mode that is currently being used. If not, do the same
1909 processing we do in `subst' for a SET; namely, if the destination
1910 is used only once, try to replace it with a register of the proper
1911 mode and also replace the COMPARE. */
1912 if (undobuf.other_insn == 0
1913 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1914 &undobuf.other_insn))
1915 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1916 i2src, const0_rtx))
1917 != GET_MODE (SET_DEST (newpat))))
1918 {
1919 unsigned int regno = REGNO (SET_DEST (newpat));
1920 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1921
1922 if (regno < FIRST_PSEUDO_REGISTER
1923 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1924 && ! REG_USERVAR_P (SET_DEST (newpat))))
1925 {
1926 if (regno >= FIRST_PSEUDO_REGISTER)
1927 SUBST (regno_reg_rtx[regno], new_dest);
1928
1929 SUBST (SET_DEST (newpat), new_dest);
1930 SUBST (XEXP (*cc_use, 0), new_dest);
1931 SUBST (SET_SRC (newpat),
1932 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1933 }
1934 else
1935 undobuf.other_insn = 0;
1936 }
1937 #endif
1938 }
1939 else
1940 #endif
1941 {
1942 n_occurrences = 0; /* `subst' counts here */
1943
1944 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1945 need to make a unique copy of I2SRC each time we substitute it
1946 to avoid self-referential rtl. */
1947
1948 subst_low_cuid = INSN_CUID (i2);
1949 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1950 ! i1_feeds_i3 && i1dest_in_i1src);
1951 substed_i2 = 1;
1952
1953 /* Record whether i2's body now appears within i3's body. */
1954 i2_is_used = n_occurrences;
1955 }
1956
1957 /* If we already got a failure, don't try to do more. Otherwise,
1958 try to substitute in I1 if we have it. */
1959
1960 if (i1 && GET_CODE (newpat) != CLOBBER)
1961 {
1962 /* Before we can do this substitution, we must redo the test done
1963 above (see detailed comments there) that ensures that I1DEST
1964 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1965
1966 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1967 0, (rtx*) 0))
1968 {
1969 undo_all ();
1970 return 0;
1971 }
1972
1973 n_occurrences = 0;
1974 subst_low_cuid = INSN_CUID (i1);
1975 newpat = subst (newpat, i1dest, i1src, 0, 0);
1976 substed_i1 = 1;
1977 }
1978
1979 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1980 to count all the ways that I2SRC and I1SRC can be used. */
1981 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1982 && i2_is_used + added_sets_2 > 1)
1983 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1984 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1985 > 1))
1986 /* Fail if we tried to make a new register (we used to abort, but there's
1987 really no reason to). */
1988 || max_reg_num () != maxreg
1989 /* Fail if we couldn't do something and have a CLOBBER. */
1990 || GET_CODE (newpat) == CLOBBER
1991 /* Fail if this new pattern is a MULT and we didn't have one before
1992 at the outer level. */
1993 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1994 && ! have_mult))
1995 {
1996 undo_all ();
1997 return 0;
1998 }
1999
2000 /* If the actions of the earlier insns must be kept
2001 in addition to substituting them into the latest one,
2002 we must make a new PARALLEL for the latest insn
2003 to hold additional the SETs. */
2004
2005 if (added_sets_1 || added_sets_2)
2006 {
2007 combine_extras++;
2008
2009 if (GET_CODE (newpat) == PARALLEL)
2010 {
2011 rtvec old = XVEC (newpat, 0);
2012 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2013 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2014 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2015 sizeof (old->elem[0]) * old->num_elem);
2016 }
2017 else
2018 {
2019 rtx old = newpat;
2020 total_sets = 1 + added_sets_1 + added_sets_2;
2021 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2022 XVECEXP (newpat, 0, 0) = old;
2023 }
2024
2025 if (added_sets_1)
2026 XVECEXP (newpat, 0, --total_sets)
2027 = (GET_CODE (PATTERN (i1)) == PARALLEL
2028 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2029
2030 if (added_sets_2)
2031 {
2032 /* If there is no I1, use I2's body as is. We used to also not do
2033 the subst call below if I2 was substituted into I3,
2034 but that could lose a simplification. */
2035 if (i1 == 0)
2036 XVECEXP (newpat, 0, --total_sets) = i2pat;
2037 else
2038 /* See comment where i2pat is assigned. */
2039 XVECEXP (newpat, 0, --total_sets)
2040 = subst (i2pat, i1dest, i1src, 0, 0);
2041 }
2042 }
2043
2044 /* We come here when we are replacing a destination in I2 with the
2045 destination of I3. */
2046 validate_replacement:
2047
2048 /* Note which hard regs this insn has as inputs. */
2049 mark_used_regs_combine (newpat);
2050
2051 /* Is the result of combination a valid instruction? */
2052 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2053
2054 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2055 the second SET's destination is a register that is unused. In that case,
2056 we just need the first SET. This can occur when simplifying a divmod
2057 insn. We *must* test for this case here because the code below that
2058 splits two independent SETs doesn't handle this case correctly when it
2059 updates the register status. Also check the case where the first
2060 SET's destination is unused. That would not cause incorrect code, but
2061 does cause an unneeded insn to remain. */
2062
2063 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2064 && XVECLEN (newpat, 0) == 2
2065 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2066 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2067 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2068 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2069 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2070 && asm_noperands (newpat) < 0)
2071 {
2072 newpat = XVECEXP (newpat, 0, 0);
2073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2074 }
2075
2076 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2077 && XVECLEN (newpat, 0) == 2
2078 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2079 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2080 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2081 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2082 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2083 && asm_noperands (newpat) < 0)
2084 {
2085 newpat = XVECEXP (newpat, 0, 1);
2086 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2087 }
2088
2089 /* If we were combining three insns and the result is a simple SET
2090 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2091 insns. There are two ways to do this. It can be split using a
2092 machine-specific method (like when you have an addition of a large
2093 constant) or by combine in the function find_split_point. */
2094
2095 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2096 && asm_noperands (newpat) < 0)
2097 {
2098 rtx m_split, *split;
2099 rtx ni2dest = i2dest;
2100
2101 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2102 use I2DEST as a scratch register will help. In the latter case,
2103 convert I2DEST to the mode of the source of NEWPAT if we can. */
2104
2105 m_split = split_insns (newpat, i3);
2106
2107 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2108 inputs of NEWPAT. */
2109
2110 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2111 possible to try that as a scratch reg. This would require adding
2112 more code to make it work though. */
2113
2114 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2115 {
2116 /* If I2DEST is a hard register or the only use of a pseudo,
2117 we can change its mode. */
2118 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2119 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2120 && GET_CODE (i2dest) == REG
2121 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2122 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2123 && ! REG_USERVAR_P (i2dest))))
2124 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2125 REGNO (i2dest));
2126
2127 m_split = split_insns (gen_rtx_PARALLEL
2128 (VOIDmode,
2129 gen_rtvec (2, newpat,
2130 gen_rtx_CLOBBER (VOIDmode,
2131 ni2dest))),
2132 i3);
2133 /* If the split with the mode-changed register didn't work, try
2134 the original register. */
2135 if (! m_split && ni2dest != i2dest)
2136 {
2137 ni2dest = i2dest;
2138 m_split = split_insns (gen_rtx_PARALLEL
2139 (VOIDmode,
2140 gen_rtvec (2, newpat,
2141 gen_rtx_CLOBBER (VOIDmode,
2142 i2dest))),
2143 i3);
2144 }
2145 }
2146
2147 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2148 {
2149 m_split = PATTERN (m_split);
2150 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2151 if (insn_code_number >= 0)
2152 newpat = m_split;
2153 }
2154 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2155 && (next_real_insn (i2) == i3
2156 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2157 {
2158 rtx i2set, i3set;
2159 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2160 newi2pat = PATTERN (m_split);
2161
2162 i3set = single_set (NEXT_INSN (m_split));
2163 i2set = single_set (m_split);
2164
2165 /* In case we changed the mode of I2DEST, replace it in the
2166 pseudo-register table here. We can't do it above in case this
2167 code doesn't get executed and we do a split the other way. */
2168
2169 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2170 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2171
2172 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2173
2174 /* If I2 or I3 has multiple SETs, we won't know how to track
2175 register status, so don't use these insns. If I2's destination
2176 is used between I2 and I3, we also can't use these insns. */
2177
2178 if (i2_code_number >= 0 && i2set && i3set
2179 && (next_real_insn (i2) == i3
2180 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2181 insn_code_number = recog_for_combine (&newi3pat, i3,
2182 &new_i3_notes);
2183 if (insn_code_number >= 0)
2184 newpat = newi3pat;
2185
2186 /* It is possible that both insns now set the destination of I3.
2187 If so, we must show an extra use of it. */
2188
2189 if (insn_code_number >= 0)
2190 {
2191 rtx new_i3_dest = SET_DEST (i3set);
2192 rtx new_i2_dest = SET_DEST (i2set);
2193
2194 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2195 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2196 || GET_CODE (new_i3_dest) == SUBREG)
2197 new_i3_dest = XEXP (new_i3_dest, 0);
2198
2199 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2200 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2201 || GET_CODE (new_i2_dest) == SUBREG)
2202 new_i2_dest = XEXP (new_i2_dest, 0);
2203
2204 if (GET_CODE (new_i3_dest) == REG
2205 && GET_CODE (new_i2_dest) == REG
2206 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2207 REG_N_SETS (REGNO (new_i2_dest))++;
2208 }
2209 }
2210
2211 /* If we can split it and use I2DEST, go ahead and see if that
2212 helps things be recognized. Verify that none of the registers
2213 are set between I2 and I3. */
2214 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2215 #ifdef HAVE_cc0
2216 && GET_CODE (i2dest) == REG
2217 #endif
2218 /* We need I2DEST in the proper mode. If it is a hard register
2219 or the only use of a pseudo, we can change its mode. */
2220 && (GET_MODE (*split) == GET_MODE (i2dest)
2221 || GET_MODE (*split) == VOIDmode
2222 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2223 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2224 && ! REG_USERVAR_P (i2dest)))
2225 && (next_real_insn (i2) == i3
2226 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2227 /* We can't overwrite I2DEST if its value is still used by
2228 NEWPAT. */
2229 && ! reg_referenced_p (i2dest, newpat))
2230 {
2231 rtx newdest = i2dest;
2232 enum rtx_code split_code = GET_CODE (*split);
2233 enum machine_mode split_mode = GET_MODE (*split);
2234
2235 /* Get NEWDEST as a register in the proper mode. We have already
2236 validated that we can do this. */
2237 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2238 {
2239 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2240
2241 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2242 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2243 }
2244
2245 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2246 an ASHIFT. This can occur if it was inside a PLUS and hence
2247 appeared to be a memory address. This is a kludge. */
2248 if (split_code == MULT
2249 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2250 && INTVAL (XEXP (*split, 1)) > 0
2251 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2252 {
2253 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2254 XEXP (*split, 0), GEN_INT (i)));
2255 /* Update split_code because we may not have a multiply
2256 anymore. */
2257 split_code = GET_CODE (*split);
2258 }
2259
2260 #ifdef INSN_SCHEDULING
2261 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2262 be written as a ZERO_EXTEND. */
2263 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2264 {
2265 #ifdef LOAD_EXTEND_OP
2266 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2267 what it really is. */
2268 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2269 == SIGN_EXTEND)
2270 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2271 SUBREG_REG (*split)));
2272 else
2273 #endif
2274 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2275 SUBREG_REG (*split)));
2276 }
2277 #endif
2278
2279 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2280 SUBST (*split, newdest);
2281 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2282
2283 /* If the split point was a MULT and we didn't have one before,
2284 don't use one now. */
2285 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2286 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2287 }
2288 }
2289
2290 /* Check for a case where we loaded from memory in a narrow mode and
2291 then sign extended it, but we need both registers. In that case,
2292 we have a PARALLEL with both loads from the same memory location.
2293 We can split this into a load from memory followed by a register-register
2294 copy. This saves at least one insn, more if register allocation can
2295 eliminate the copy.
2296
2297 We cannot do this if the destination of the first assignment is a
2298 condition code register or cc0. We eliminate this case by making sure
2299 the SET_DEST and SET_SRC have the same mode.
2300
2301 We cannot do this if the destination of the second assignment is
2302 a register that we have already assumed is zero-extended. Similarly
2303 for a SUBREG of such a register. */
2304
2305 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2306 && GET_CODE (newpat) == PARALLEL
2307 && XVECLEN (newpat, 0) == 2
2308 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2309 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2310 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2311 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2312 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2313 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2314 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2315 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2316 INSN_CUID (i2))
2317 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2318 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2319 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2320 (GET_CODE (temp) == REG
2321 && reg_nonzero_bits[REGNO (temp)] != 0
2322 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2323 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2324 && (reg_nonzero_bits[REGNO (temp)]
2325 != GET_MODE_MASK (word_mode))))
2326 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2327 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2328 (GET_CODE (temp) == REG
2329 && reg_nonzero_bits[REGNO (temp)] != 0
2330 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2331 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2332 && (reg_nonzero_bits[REGNO (temp)]
2333 != GET_MODE_MASK (word_mode)))))
2334 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2335 SET_SRC (XVECEXP (newpat, 0, 1)))
2336 && ! find_reg_note (i3, REG_UNUSED,
2337 SET_DEST (XVECEXP (newpat, 0, 0))))
2338 {
2339 rtx ni2dest;
2340
2341 newi2pat = XVECEXP (newpat, 0, 0);
2342 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2343 newpat = XVECEXP (newpat, 0, 1);
2344 SUBST (SET_SRC (newpat),
2345 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2346 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2347
2348 if (i2_code_number >= 0)
2349 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2350
2351 if (insn_code_number >= 0)
2352 {
2353 rtx insn;
2354 rtx link;
2355
2356 /* If we will be able to accept this, we have made a change to the
2357 destination of I3. This can invalidate a LOG_LINKS pointing
2358 to I3. No other part of combine.c makes such a transformation.
2359
2360 The new I3 will have a destination that was previously the
2361 destination of I1 or I2 and which was used in i2 or I3. Call
2362 distribute_links to make a LOG_LINK from the next use of
2363 that destination. */
2364
2365 PATTERN (i3) = newpat;
2366 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2367
2368 /* I3 now uses what used to be its destination and which is
2369 now I2's destination. That means we need a LOG_LINK from
2370 I3 to I2. But we used to have one, so we still will.
2371
2372 However, some later insn might be using I2's dest and have
2373 a LOG_LINK pointing at I3. We must remove this link.
2374 The simplest way to remove the link is to point it at I1,
2375 which we know will be a NOTE. */
2376
2377 for (insn = NEXT_INSN (i3);
2378 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2379 || insn != this_basic_block->next_bb->head);
2380 insn = NEXT_INSN (insn))
2381 {
2382 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2383 {
2384 for (link = LOG_LINKS (insn); link;
2385 link = XEXP (link, 1))
2386 if (XEXP (link, 0) == i3)
2387 XEXP (link, 0) = i1;
2388
2389 break;
2390 }
2391 }
2392 }
2393 }
2394
2395 /* Similarly, check for a case where we have a PARALLEL of two independent
2396 SETs but we started with three insns. In this case, we can do the sets
2397 as two separate insns. This case occurs when some SET allows two
2398 other insns to combine, but the destination of that SET is still live. */
2399
2400 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2401 && GET_CODE (newpat) == PARALLEL
2402 && XVECLEN (newpat, 0) == 2
2403 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2404 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2405 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2406 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2407 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2408 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2409 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2410 INSN_CUID (i2))
2411 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2412 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2413 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2414 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2415 XVECEXP (newpat, 0, 0))
2416 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2417 XVECEXP (newpat, 0, 1))
2418 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2419 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2420 {
2421 /* Normally, it doesn't matter which of the two is done first,
2422 but it does if one references cc0. In that case, it has to
2423 be first. */
2424 #ifdef HAVE_cc0
2425 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2426 {
2427 newi2pat = XVECEXP (newpat, 0, 0);
2428 newpat = XVECEXP (newpat, 0, 1);
2429 }
2430 else
2431 #endif
2432 {
2433 newi2pat = XVECEXP (newpat, 0, 1);
2434 newpat = XVECEXP (newpat, 0, 0);
2435 }
2436
2437 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2438
2439 if (i2_code_number >= 0)
2440 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2441 }
2442
2443 /* If it still isn't recognized, fail and change things back the way they
2444 were. */
2445 if ((insn_code_number < 0
2446 /* Is the result a reasonable ASM_OPERANDS? */
2447 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2448 {
2449 undo_all ();
2450 return 0;
2451 }
2452
2453 /* If we had to change another insn, make sure it is valid also. */
2454 if (undobuf.other_insn)
2455 {
2456 rtx other_pat = PATTERN (undobuf.other_insn);
2457 rtx new_other_notes;
2458 rtx note, next;
2459
2460 CLEAR_HARD_REG_SET (newpat_used_regs);
2461
2462 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2463 &new_other_notes);
2464
2465 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2466 {
2467 undo_all ();
2468 return 0;
2469 }
2470
2471 PATTERN (undobuf.other_insn) = other_pat;
2472
2473 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2474 are still valid. Then add any non-duplicate notes added by
2475 recog_for_combine. */
2476 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2477 {
2478 next = XEXP (note, 1);
2479
2480 if (REG_NOTE_KIND (note) == REG_UNUSED
2481 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2482 {
2483 if (GET_CODE (XEXP (note, 0)) == REG)
2484 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2485
2486 remove_note (undobuf.other_insn, note);
2487 }
2488 }
2489
2490 for (note = new_other_notes; note; note = XEXP (note, 1))
2491 if (GET_CODE (XEXP (note, 0)) == REG)
2492 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2493
2494 distribute_notes (new_other_notes, undobuf.other_insn,
2495 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2496 }
2497 #ifdef HAVE_cc0
2498 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2499 they are adjacent to each other or not. */
2500 {
2501 rtx p = prev_nonnote_insn (i3);
2502 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2503 && sets_cc0_p (newi2pat))
2504 {
2505 undo_all ();
2506 return 0;
2507 }
2508 }
2509 #endif
2510
2511 /* We now know that we can do this combination. Merge the insns and
2512 update the status of registers and LOG_LINKS. */
2513
2514 {
2515 rtx i3notes, i2notes, i1notes = 0;
2516 rtx i3links, i2links, i1links = 0;
2517 rtx midnotes = 0;
2518 unsigned int regno;
2519 /* Compute which registers we expect to eliminate. newi2pat may be setting
2520 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2521 same as i3dest, in which case newi2pat may be setting i1dest. */
2522 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2523 || i2dest_in_i2src || i2dest_in_i1src
2524 ? 0 : i2dest);
2525 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2526 || (newi2pat && reg_set_p (i1dest, newi2pat))
2527 ? 0 : i1dest);
2528
2529 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2530 clear them. */
2531 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2532 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2533 if (i1)
2534 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2535
2536 /* Ensure that we do not have something that should not be shared but
2537 occurs multiple times in the new insns. Check this by first
2538 resetting all the `used' flags and then copying anything is shared. */
2539
2540 reset_used_flags (i3notes);
2541 reset_used_flags (i2notes);
2542 reset_used_flags (i1notes);
2543 reset_used_flags (newpat);
2544 reset_used_flags (newi2pat);
2545 if (undobuf.other_insn)
2546 reset_used_flags (PATTERN (undobuf.other_insn));
2547
2548 i3notes = copy_rtx_if_shared (i3notes);
2549 i2notes = copy_rtx_if_shared (i2notes);
2550 i1notes = copy_rtx_if_shared (i1notes);
2551 newpat = copy_rtx_if_shared (newpat);
2552 newi2pat = copy_rtx_if_shared (newi2pat);
2553 if (undobuf.other_insn)
2554 reset_used_flags (PATTERN (undobuf.other_insn));
2555
2556 INSN_CODE (i3) = insn_code_number;
2557 PATTERN (i3) = newpat;
2558
2559 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2560 {
2561 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2562
2563 reset_used_flags (call_usage);
2564 call_usage = copy_rtx (call_usage);
2565
2566 if (substed_i2)
2567 replace_rtx (call_usage, i2dest, i2src);
2568
2569 if (substed_i1)
2570 replace_rtx (call_usage, i1dest, i1src);
2571
2572 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2573 }
2574
2575 if (undobuf.other_insn)
2576 INSN_CODE (undobuf.other_insn) = other_code_number;
2577
2578 /* We had one special case above where I2 had more than one set and
2579 we replaced a destination of one of those sets with the destination
2580 of I3. In that case, we have to update LOG_LINKS of insns later
2581 in this basic block. Note that this (expensive) case is rare.
2582
2583 Also, in this case, we must pretend that all REG_NOTEs for I2
2584 actually came from I3, so that REG_UNUSED notes from I2 will be
2585 properly handled. */
2586
2587 if (i3_subst_into_i2)
2588 {
2589 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2590 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2591 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2592 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2593 && ! find_reg_note (i2, REG_UNUSED,
2594 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2595 for (temp = NEXT_INSN (i2);
2596 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2597 || this_basic_block->head != temp);
2598 temp = NEXT_INSN (temp))
2599 if (temp != i3 && INSN_P (temp))
2600 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2601 if (XEXP (link, 0) == i2)
2602 XEXP (link, 0) = i3;
2603
2604 if (i3notes)
2605 {
2606 rtx link = i3notes;
2607 while (XEXP (link, 1))
2608 link = XEXP (link, 1);
2609 XEXP (link, 1) = i2notes;
2610 }
2611 else
2612 i3notes = i2notes;
2613 i2notes = 0;
2614 }
2615
2616 LOG_LINKS (i3) = 0;
2617 REG_NOTES (i3) = 0;
2618 LOG_LINKS (i2) = 0;
2619 REG_NOTES (i2) = 0;
2620
2621 if (newi2pat)
2622 {
2623 INSN_CODE (i2) = i2_code_number;
2624 PATTERN (i2) = newi2pat;
2625 }
2626 else
2627 {
2628 PUT_CODE (i2, NOTE);
2629 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2630 NOTE_SOURCE_FILE (i2) = 0;
2631 }
2632
2633 if (i1)
2634 {
2635 LOG_LINKS (i1) = 0;
2636 REG_NOTES (i1) = 0;
2637 PUT_CODE (i1, NOTE);
2638 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2639 NOTE_SOURCE_FILE (i1) = 0;
2640 }
2641
2642 /* Get death notes for everything that is now used in either I3 or
2643 I2 and used to die in a previous insn. If we built two new
2644 patterns, move from I1 to I2 then I2 to I3 so that we get the
2645 proper movement on registers that I2 modifies. */
2646
2647 if (newi2pat)
2648 {
2649 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2650 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2651 }
2652 else
2653 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2654 i3, &midnotes);
2655
2656 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2657 if (i3notes)
2658 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2659 elim_i2, elim_i1);
2660 if (i2notes)
2661 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2662 elim_i2, elim_i1);
2663 if (i1notes)
2664 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2665 elim_i2, elim_i1);
2666 if (midnotes)
2667 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2668 elim_i2, elim_i1);
2669
2670 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2671 know these are REG_UNUSED and want them to go to the desired insn,
2672 so we always pass it as i3. We have not counted the notes in
2673 reg_n_deaths yet, so we need to do so now. */
2674
2675 if (newi2pat && new_i2_notes)
2676 {
2677 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2678 if (GET_CODE (XEXP (temp, 0)) == REG)
2679 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2680
2681 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2682 }
2683
2684 if (new_i3_notes)
2685 {
2686 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2687 if (GET_CODE (XEXP (temp, 0)) == REG)
2688 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2689
2690 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2691 }
2692
2693 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2694 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2695 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2696 in that case, it might delete I2. Similarly for I2 and I1.
2697 Show an additional death due to the REG_DEAD note we make here. If
2698 we discard it in distribute_notes, we will decrement it again. */
2699
2700 if (i3dest_killed)
2701 {
2702 if (GET_CODE (i3dest_killed) == REG)
2703 REG_N_DEATHS (REGNO (i3dest_killed))++;
2704
2705 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2706 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2707 NULL_RTX),
2708 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2709 else
2710 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2711 NULL_RTX),
2712 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2713 elim_i2, elim_i1);
2714 }
2715
2716 if (i2dest_in_i2src)
2717 {
2718 if (GET_CODE (i2dest) == REG)
2719 REG_N_DEATHS (REGNO (i2dest))++;
2720
2721 if (newi2pat && reg_set_p (i2dest, newi2pat))
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2723 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2724 else
2725 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2726 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2727 NULL_RTX, NULL_RTX);
2728 }
2729
2730 if (i1dest_in_i1src)
2731 {
2732 if (GET_CODE (i1dest) == REG)
2733 REG_N_DEATHS (REGNO (i1dest))++;
2734
2735 if (newi2pat && reg_set_p (i1dest, newi2pat))
2736 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2737 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2738 else
2739 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2740 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2741 NULL_RTX, NULL_RTX);
2742 }
2743
2744 distribute_links (i3links);
2745 distribute_links (i2links);
2746 distribute_links (i1links);
2747
2748 if (GET_CODE (i2dest) == REG)
2749 {
2750 rtx link;
2751 rtx i2_insn = 0, i2_val = 0, set;
2752
2753 /* The insn that used to set this register doesn't exist, and
2754 this life of the register may not exist either. See if one of
2755 I3's links points to an insn that sets I2DEST. If it does,
2756 that is now the last known value for I2DEST. If we don't update
2757 this and I2 set the register to a value that depended on its old
2758 contents, we will get confused. If this insn is used, thing
2759 will be set correctly in combine_instructions. */
2760
2761 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2762 if ((set = single_set (XEXP (link, 0))) != 0
2763 && rtx_equal_p (i2dest, SET_DEST (set)))
2764 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2765
2766 record_value_for_reg (i2dest, i2_insn, i2_val);
2767
2768 /* If the reg formerly set in I2 died only once and that was in I3,
2769 zero its use count so it won't make `reload' do any work. */
2770 if (! added_sets_2
2771 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2772 && ! i2dest_in_i2src)
2773 {
2774 regno = REGNO (i2dest);
2775 REG_N_SETS (regno)--;
2776 }
2777 }
2778
2779 if (i1 && GET_CODE (i1dest) == REG)
2780 {
2781 rtx link;
2782 rtx i1_insn = 0, i1_val = 0, set;
2783
2784 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2785 if ((set = single_set (XEXP (link, 0))) != 0
2786 && rtx_equal_p (i1dest, SET_DEST (set)))
2787 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2788
2789 record_value_for_reg (i1dest, i1_insn, i1_val);
2790
2791 regno = REGNO (i1dest);
2792 if (! added_sets_1 && ! i1dest_in_i1src)
2793 REG_N_SETS (regno)--;
2794 }
2795
2796 /* Update reg_nonzero_bits et al for any changes that may have been made
2797 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2798 important. Because newi2pat can affect nonzero_bits of newpat */
2799 if (newi2pat)
2800 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2801 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2802
2803 /* Set new_direct_jump_p if a new return or simple jump instruction
2804 has been created.
2805
2806 If I3 is now an unconditional jump, ensure that it has a
2807 BARRIER following it since it may have initially been a
2808 conditional jump. It may also be the last nonnote insn. */
2809
2810 if (returnjump_p (i3) || any_uncondjump_p (i3))
2811 {
2812 *new_direct_jump_p = 1;
2813
2814 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2815 || GET_CODE (temp) != BARRIER)
2816 emit_barrier_after (i3);
2817 }
2818
2819 if (undobuf.other_insn != NULL_RTX
2820 && (returnjump_p (undobuf.other_insn)
2821 || any_uncondjump_p (undobuf.other_insn)))
2822 {
2823 *new_direct_jump_p = 1;
2824
2825 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2826 || GET_CODE (temp) != BARRIER)
2827 emit_barrier_after (undobuf.other_insn);
2828 }
2829
2830 /* An NOOP jump does not need barrier, but it does need cleaning up
2831 of CFG. */
2832 if (GET_CODE (newpat) == SET
2833 && SET_SRC (newpat) == pc_rtx
2834 && SET_DEST (newpat) == pc_rtx)
2835 *new_direct_jump_p = 1;
2836 }
2837
2838 combine_successes++;
2839 undo_commit ();
2840
2841 if (added_links_insn
2842 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2843 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2844 return added_links_insn;
2845 else
2846 return newi2pat ? i2 : i3;
2847 }
2848 \f
2849 /* Undo all the modifications recorded in undobuf. */
2850
2851 static void
2852 undo_all ()
2853 {
2854 struct undo *undo, *next;
2855
2856 for (undo = undobuf.undos; undo; undo = next)
2857 {
2858 next = undo->next;
2859 if (undo->is_int)
2860 *undo->where.i = undo->old_contents.i;
2861 else
2862 *undo->where.r = undo->old_contents.r;
2863
2864 undo->next = undobuf.frees;
2865 undobuf.frees = undo;
2866 }
2867
2868 undobuf.undos = 0;
2869 }
2870
2871 /* We've committed to accepting the changes we made. Move all
2872 of the undos to the free list. */
2873
2874 static void
2875 undo_commit ()
2876 {
2877 struct undo *undo, *next;
2878
2879 for (undo = undobuf.undos; undo; undo = next)
2880 {
2881 next = undo->next;
2882 undo->next = undobuf.frees;
2883 undobuf.frees = undo;
2884 }
2885 undobuf.undos = 0;
2886 }
2887
2888 \f
2889 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2890 where we have an arithmetic expression and return that point. LOC will
2891 be inside INSN.
2892
2893 try_combine will call this function to see if an insn can be split into
2894 two insns. */
2895
2896 static rtx *
2897 find_split_point (loc, insn)
2898 rtx *loc;
2899 rtx insn;
2900 {
2901 rtx x = *loc;
2902 enum rtx_code code = GET_CODE (x);
2903 rtx *split;
2904 unsigned HOST_WIDE_INT len = 0;
2905 HOST_WIDE_INT pos = 0;
2906 int unsignedp = 0;
2907 rtx inner = NULL_RTX;
2908
2909 /* First special-case some codes. */
2910 switch (code)
2911 {
2912 case SUBREG:
2913 #ifdef INSN_SCHEDULING
2914 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2915 point. */
2916 if (GET_CODE (SUBREG_REG (x)) == MEM)
2917 return loc;
2918 #endif
2919 return find_split_point (&SUBREG_REG (x), insn);
2920
2921 case MEM:
2922 #ifdef HAVE_lo_sum
2923 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2924 using LO_SUM and HIGH. */
2925 if (GET_CODE (XEXP (x, 0)) == CONST
2926 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2927 {
2928 SUBST (XEXP (x, 0),
2929 gen_rtx_LO_SUM (Pmode,
2930 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2931 XEXP (x, 0)));
2932 return &XEXP (XEXP (x, 0), 0);
2933 }
2934 #endif
2935
2936 /* If we have a PLUS whose second operand is a constant and the
2937 address is not valid, perhaps will can split it up using
2938 the machine-specific way to split large constants. We use
2939 the first pseudo-reg (one of the virtual regs) as a placeholder;
2940 it will not remain in the result. */
2941 if (GET_CODE (XEXP (x, 0)) == PLUS
2942 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2943 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2944 {
2945 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2946 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2947 subst_insn);
2948
2949 /* This should have produced two insns, each of which sets our
2950 placeholder. If the source of the second is a valid address,
2951 we can make put both sources together and make a split point
2952 in the middle. */
2953
2954 if (seq
2955 && NEXT_INSN (seq) != NULL_RTX
2956 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2957 && GET_CODE (seq) == INSN
2958 && GET_CODE (PATTERN (seq)) == SET
2959 && SET_DEST (PATTERN (seq)) == reg
2960 && ! reg_mentioned_p (reg,
2961 SET_SRC (PATTERN (seq)))
2962 && GET_CODE (NEXT_INSN (seq)) == INSN
2963 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2964 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2965 && memory_address_p (GET_MODE (x),
2966 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2967 {
2968 rtx src1 = SET_SRC (PATTERN (seq));
2969 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2970
2971 /* Replace the placeholder in SRC2 with SRC1. If we can
2972 find where in SRC2 it was placed, that can become our
2973 split point and we can replace this address with SRC2.
2974 Just try two obvious places. */
2975
2976 src2 = replace_rtx (src2, reg, src1);
2977 split = 0;
2978 if (XEXP (src2, 0) == src1)
2979 split = &XEXP (src2, 0);
2980 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2981 && XEXP (XEXP (src2, 0), 0) == src1)
2982 split = &XEXP (XEXP (src2, 0), 0);
2983
2984 if (split)
2985 {
2986 SUBST (XEXP (x, 0), src2);
2987 return split;
2988 }
2989 }
2990
2991 /* If that didn't work, perhaps the first operand is complex and
2992 needs to be computed separately, so make a split point there.
2993 This will occur on machines that just support REG + CONST
2994 and have a constant moved through some previous computation. */
2995
2996 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2997 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2998 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2999 == 'o')))
3000 return &XEXP (XEXP (x, 0), 0);
3001 }
3002 break;
3003
3004 case SET:
3005 #ifdef HAVE_cc0
3006 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3007 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3008 we need to put the operand into a register. So split at that
3009 point. */
3010
3011 if (SET_DEST (x) == cc0_rtx
3012 && GET_CODE (SET_SRC (x)) != COMPARE
3013 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3014 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3015 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3016 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3017 return &SET_SRC (x);
3018 #endif
3019
3020 /* See if we can split SET_SRC as it stands. */
3021 split = find_split_point (&SET_SRC (x), insn);
3022 if (split && split != &SET_SRC (x))
3023 return split;
3024
3025 /* See if we can split SET_DEST as it stands. */
3026 split = find_split_point (&SET_DEST (x), insn);
3027 if (split && split != &SET_DEST (x))
3028 return split;
3029
3030 /* See if this is a bitfield assignment with everything constant. If
3031 so, this is an IOR of an AND, so split it into that. */
3032 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3033 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3034 <= HOST_BITS_PER_WIDE_INT)
3035 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3036 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3037 && GET_CODE (SET_SRC (x)) == CONST_INT
3038 && ((INTVAL (XEXP (SET_DEST (x), 1))
3039 + INTVAL (XEXP (SET_DEST (x), 2)))
3040 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3041 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3042 {
3043 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3044 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3045 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3046 rtx dest = XEXP (SET_DEST (x), 0);
3047 enum machine_mode mode = GET_MODE (dest);
3048 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3049
3050 if (BITS_BIG_ENDIAN)
3051 pos = GET_MODE_BITSIZE (mode) - len - pos;
3052
3053 if (src == mask)
3054 SUBST (SET_SRC (x),
3055 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3056 else
3057 SUBST (SET_SRC (x),
3058 gen_binary (IOR, mode,
3059 gen_binary (AND, mode, dest,
3060 gen_int_mode (~(mask << pos),
3061 mode)),
3062 GEN_INT (src << pos)));
3063
3064 SUBST (SET_DEST (x), dest);
3065
3066 split = find_split_point (&SET_SRC (x), insn);
3067 if (split && split != &SET_SRC (x))
3068 return split;
3069 }
3070
3071 /* Otherwise, see if this is an operation that we can split into two.
3072 If so, try to split that. */
3073 code = GET_CODE (SET_SRC (x));
3074
3075 switch (code)
3076 {
3077 case AND:
3078 /* If we are AND'ing with a large constant that is only a single
3079 bit and the result is only being used in a context where we
3080 need to know if it is zero or nonzero, replace it with a bit
3081 extraction. This will avoid the large constant, which might
3082 have taken more than one insn to make. If the constant were
3083 not a valid argument to the AND but took only one insn to make,
3084 this is no worse, but if it took more than one insn, it will
3085 be better. */
3086
3087 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3088 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3089 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3090 && GET_CODE (SET_DEST (x)) == REG
3091 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3092 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3093 && XEXP (*split, 0) == SET_DEST (x)
3094 && XEXP (*split, 1) == const0_rtx)
3095 {
3096 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3097 XEXP (SET_SRC (x), 0),
3098 pos, NULL_RTX, 1, 1, 0, 0);
3099 if (extraction != 0)
3100 {
3101 SUBST (SET_SRC (x), extraction);
3102 return find_split_point (loc, insn);
3103 }
3104 }
3105 break;
3106
3107 case NE:
3108 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3109 is known to be on, this can be converted into a NEG of a shift. */
3110 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3111 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3112 && 1 <= (pos = exact_log2
3113 (nonzero_bits (XEXP (SET_SRC (x), 0),
3114 GET_MODE (XEXP (SET_SRC (x), 0))))))
3115 {
3116 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3117
3118 SUBST (SET_SRC (x),
3119 gen_rtx_NEG (mode,
3120 gen_rtx_LSHIFTRT (mode,
3121 XEXP (SET_SRC (x), 0),
3122 GEN_INT (pos))));
3123
3124 split = find_split_point (&SET_SRC (x), insn);
3125 if (split && split != &SET_SRC (x))
3126 return split;
3127 }
3128 break;
3129
3130 case SIGN_EXTEND:
3131 inner = XEXP (SET_SRC (x), 0);
3132
3133 /* We can't optimize if either mode is a partial integer
3134 mode as we don't know how many bits are significant
3135 in those modes. */
3136 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3137 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3138 break;
3139
3140 pos = 0;
3141 len = GET_MODE_BITSIZE (GET_MODE (inner));
3142 unsignedp = 0;
3143 break;
3144
3145 case SIGN_EXTRACT:
3146 case ZERO_EXTRACT:
3147 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3148 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3149 {
3150 inner = XEXP (SET_SRC (x), 0);
3151 len = INTVAL (XEXP (SET_SRC (x), 1));
3152 pos = INTVAL (XEXP (SET_SRC (x), 2));
3153
3154 if (BITS_BIG_ENDIAN)
3155 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3156 unsignedp = (code == ZERO_EXTRACT);
3157 }
3158 break;
3159
3160 default:
3161 break;
3162 }
3163
3164 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3165 {
3166 enum machine_mode mode = GET_MODE (SET_SRC (x));
3167
3168 /* For unsigned, we have a choice of a shift followed by an
3169 AND or two shifts. Use two shifts for field sizes where the
3170 constant might be too large. We assume here that we can
3171 always at least get 8-bit constants in an AND insn, which is
3172 true for every current RISC. */
3173
3174 if (unsignedp && len <= 8)
3175 {
3176 SUBST (SET_SRC (x),
3177 gen_rtx_AND (mode,
3178 gen_rtx_LSHIFTRT
3179 (mode, gen_lowpart_for_combine (mode, inner),
3180 GEN_INT (pos)),
3181 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3182
3183 split = find_split_point (&SET_SRC (x), insn);
3184 if (split && split != &SET_SRC (x))
3185 return split;
3186 }
3187 else
3188 {
3189 SUBST (SET_SRC (x),
3190 gen_rtx_fmt_ee
3191 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3192 gen_rtx_ASHIFT (mode,
3193 gen_lowpart_for_combine (mode, inner),
3194 GEN_INT (GET_MODE_BITSIZE (mode)
3195 - len - pos)),
3196 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3197
3198 split = find_split_point (&SET_SRC (x), insn);
3199 if (split && split != &SET_SRC (x))
3200 return split;
3201 }
3202 }
3203
3204 /* See if this is a simple operation with a constant as the second
3205 operand. It might be that this constant is out of range and hence
3206 could be used as a split point. */
3207 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3208 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3209 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3210 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3211 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3212 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3213 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3214 == 'o'))))
3215 return &XEXP (SET_SRC (x), 1);
3216
3217 /* Finally, see if this is a simple operation with its first operand
3218 not in a register. The operation might require this operand in a
3219 register, so return it as a split point. We can always do this
3220 because if the first operand were another operation, we would have
3221 already found it as a split point. */
3222 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3223 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3224 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3225 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3226 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3227 return &XEXP (SET_SRC (x), 0);
3228
3229 return 0;
3230
3231 case AND:
3232 case IOR:
3233 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3234 it is better to write this as (not (ior A B)) so we can split it.
3235 Similarly for IOR. */
3236 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3237 {
3238 SUBST (*loc,
3239 gen_rtx_NOT (GET_MODE (x),
3240 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3241 GET_MODE (x),
3242 XEXP (XEXP (x, 0), 0),
3243 XEXP (XEXP (x, 1), 0))));
3244 return find_split_point (loc, insn);
3245 }
3246
3247 /* Many RISC machines have a large set of logical insns. If the
3248 second operand is a NOT, put it first so we will try to split the
3249 other operand first. */
3250 if (GET_CODE (XEXP (x, 1)) == NOT)
3251 {
3252 rtx tem = XEXP (x, 0);
3253 SUBST (XEXP (x, 0), XEXP (x, 1));
3254 SUBST (XEXP (x, 1), tem);
3255 }
3256 break;
3257
3258 default:
3259 break;
3260 }
3261
3262 /* Otherwise, select our actions depending on our rtx class. */
3263 switch (GET_RTX_CLASS (code))
3264 {
3265 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3266 case '3':
3267 split = find_split_point (&XEXP (x, 2), insn);
3268 if (split)
3269 return split;
3270 /* ... fall through ... */
3271 case '2':
3272 case 'c':
3273 case '<':
3274 split = find_split_point (&XEXP (x, 1), insn);
3275 if (split)
3276 return split;
3277 /* ... fall through ... */
3278 case '1':
3279 /* Some machines have (and (shift ...) ...) insns. If X is not
3280 an AND, but XEXP (X, 0) is, use it as our split point. */
3281 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3282 return &XEXP (x, 0);
3283
3284 split = find_split_point (&XEXP (x, 0), insn);
3285 if (split)
3286 return split;
3287 return loc;
3288 }
3289
3290 /* Otherwise, we don't have a split point. */
3291 return 0;
3292 }
3293 \f
3294 /* Throughout X, replace FROM with TO, and return the result.
3295 The result is TO if X is FROM;
3296 otherwise the result is X, but its contents may have been modified.
3297 If they were modified, a record was made in undobuf so that
3298 undo_all will (among other things) return X to its original state.
3299
3300 If the number of changes necessary is too much to record to undo,
3301 the excess changes are not made, so the result is invalid.
3302 The changes already made can still be undone.
3303 undobuf.num_undo is incremented for such changes, so by testing that
3304 the caller can tell whether the result is valid.
3305
3306 `n_occurrences' is incremented each time FROM is replaced.
3307
3308 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3309
3310 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3311 by copying if `n_occurrences' is nonzero. */
3312
3313 static rtx
3314 subst (x, from, to, in_dest, unique_copy)
3315 rtx x, from, to;
3316 int in_dest;
3317 int unique_copy;
3318 {
3319 enum rtx_code code = GET_CODE (x);
3320 enum machine_mode op0_mode = VOIDmode;
3321 const char *fmt;
3322 int len, i;
3323 rtx new;
3324
3325 /* Two expressions are equal if they are identical copies of a shared
3326 RTX or if they are both registers with the same register number
3327 and mode. */
3328
3329 #define COMBINE_RTX_EQUAL_P(X,Y) \
3330 ((X) == (Y) \
3331 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3332 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3333
3334 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3335 {
3336 n_occurrences++;
3337 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3338 }
3339
3340 /* If X and FROM are the same register but different modes, they will
3341 not have been seen as equal above. However, flow.c will make a
3342 LOG_LINKS entry for that case. If we do nothing, we will try to
3343 rerecognize our original insn and, when it succeeds, we will
3344 delete the feeding insn, which is incorrect.
3345
3346 So force this insn not to match in this (rare) case. */
3347 if (! in_dest && code == REG && GET_CODE (from) == REG
3348 && REGNO (x) == REGNO (from))
3349 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3350
3351 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3352 of which may contain things that can be combined. */
3353 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3354 return x;
3355
3356 /* It is possible to have a subexpression appear twice in the insn.
3357 Suppose that FROM is a register that appears within TO.
3358 Then, after that subexpression has been scanned once by `subst',
3359 the second time it is scanned, TO may be found. If we were
3360 to scan TO here, we would find FROM within it and create a
3361 self-referent rtl structure which is completely wrong. */
3362 if (COMBINE_RTX_EQUAL_P (x, to))
3363 return to;
3364
3365 /* Parallel asm_operands need special attention because all of the
3366 inputs are shared across the arms. Furthermore, unsharing the
3367 rtl results in recognition failures. Failure to handle this case
3368 specially can result in circular rtl.
3369
3370 Solve this by doing a normal pass across the first entry of the
3371 parallel, and only processing the SET_DESTs of the subsequent
3372 entries. Ug. */
3373
3374 if (code == PARALLEL
3375 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3376 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3377 {
3378 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3379
3380 /* If this substitution failed, this whole thing fails. */
3381 if (GET_CODE (new) == CLOBBER
3382 && XEXP (new, 0) == const0_rtx)
3383 return new;
3384
3385 SUBST (XVECEXP (x, 0, 0), new);
3386
3387 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3388 {
3389 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3390
3391 if (GET_CODE (dest) != REG
3392 && GET_CODE (dest) != CC0
3393 && GET_CODE (dest) != PC)
3394 {
3395 new = subst (dest, from, to, 0, unique_copy);
3396
3397 /* If this substitution failed, this whole thing fails. */
3398 if (GET_CODE (new) == CLOBBER
3399 && XEXP (new, 0) == const0_rtx)
3400 return new;
3401
3402 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3403 }
3404 }
3405 }
3406 else
3407 {
3408 len = GET_RTX_LENGTH (code);
3409 fmt = GET_RTX_FORMAT (code);
3410
3411 /* We don't need to process a SET_DEST that is a register, CC0,
3412 or PC, so set up to skip this common case. All other cases
3413 where we want to suppress replacing something inside a
3414 SET_SRC are handled via the IN_DEST operand. */
3415 if (code == SET
3416 && (GET_CODE (SET_DEST (x)) == REG
3417 || GET_CODE (SET_DEST (x)) == CC0
3418 || GET_CODE (SET_DEST (x)) == PC))
3419 fmt = "ie";
3420
3421 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3422 constant. */
3423 if (fmt[0] == 'e')
3424 op0_mode = GET_MODE (XEXP (x, 0));
3425
3426 for (i = 0; i < len; i++)
3427 {
3428 if (fmt[i] == 'E')
3429 {
3430 int j;
3431 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3432 {
3433 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3434 {
3435 new = (unique_copy && n_occurrences
3436 ? copy_rtx (to) : to);
3437 n_occurrences++;
3438 }
3439 else
3440 {
3441 new = subst (XVECEXP (x, i, j), from, to, 0,
3442 unique_copy);
3443
3444 /* If this substitution failed, this whole thing
3445 fails. */
3446 if (GET_CODE (new) == CLOBBER
3447 && XEXP (new, 0) == const0_rtx)
3448 return new;
3449 }
3450
3451 SUBST (XVECEXP (x, i, j), new);
3452 }
3453 }
3454 else if (fmt[i] == 'e')
3455 {
3456 /* If this is a register being set, ignore it. */
3457 new = XEXP (x, i);
3458 if (in_dest
3459 && (code == SUBREG || code == STRICT_LOW_PART
3460 || code == ZERO_EXTRACT)
3461 && i == 0
3462 && GET_CODE (new) == REG)
3463 ;
3464
3465 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3466 {
3467 /* In general, don't install a subreg involving two
3468 modes not tieable. It can worsen register
3469 allocation, and can even make invalid reload
3470 insns, since the reg inside may need to be copied
3471 from in the outside mode, and that may be invalid
3472 if it is an fp reg copied in integer mode.
3473
3474 We allow two exceptions to this: It is valid if
3475 it is inside another SUBREG and the mode of that
3476 SUBREG and the mode of the inside of TO is
3477 tieable and it is valid if X is a SET that copies
3478 FROM to CC0. */
3479
3480 if (GET_CODE (to) == SUBREG
3481 && ! MODES_TIEABLE_P (GET_MODE (to),
3482 GET_MODE (SUBREG_REG (to)))
3483 && ! (code == SUBREG
3484 && MODES_TIEABLE_P (GET_MODE (x),
3485 GET_MODE (SUBREG_REG (to))))
3486 #ifdef HAVE_cc0
3487 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3488 #endif
3489 )
3490 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3491
3492 #ifdef CANNOT_CHANGE_MODE_CLASS
3493 if (code == SUBREG
3494 && GET_CODE (to) == REG
3495 && REGNO (to) < FIRST_PSEUDO_REGISTER
3496 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3497 GET_MODE (to),
3498 GET_MODE (x)))
3499 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3500 #endif
3501
3502 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3503 n_occurrences++;
3504 }
3505 else
3506 /* If we are in a SET_DEST, suppress most cases unless we
3507 have gone inside a MEM, in which case we want to
3508 simplify the address. We assume here that things that
3509 are actually part of the destination have their inner
3510 parts in the first expression. This is true for SUBREG,
3511 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3512 things aside from REG and MEM that should appear in a
3513 SET_DEST. */
3514 new = subst (XEXP (x, i), from, to,
3515 (((in_dest
3516 && (code == SUBREG || code == STRICT_LOW_PART
3517 || code == ZERO_EXTRACT))
3518 || code == SET)
3519 && i == 0), unique_copy);
3520
3521 /* If we found that we will have to reject this combination,
3522 indicate that by returning the CLOBBER ourselves, rather than
3523 an expression containing it. This will speed things up as
3524 well as prevent accidents where two CLOBBERs are considered
3525 to be equal, thus producing an incorrect simplification. */
3526
3527 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3528 return new;
3529
3530 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3531 {
3532 enum machine_mode mode = GET_MODE (x);
3533
3534 x = simplify_subreg (GET_MODE (x), new,
3535 GET_MODE (SUBREG_REG (x)),
3536 SUBREG_BYTE (x));
3537 if (! x)
3538 x = gen_rtx_CLOBBER (mode, const0_rtx);
3539 }
3540 else if (GET_CODE (new) == CONST_INT
3541 && GET_CODE (x) == ZERO_EXTEND)
3542 {
3543 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3544 new, GET_MODE (XEXP (x, 0)));
3545 if (! x)
3546 abort ();
3547 }
3548 else
3549 SUBST (XEXP (x, i), new);
3550 }
3551 }
3552 }
3553
3554 /* Try to simplify X. If the simplification changed the code, it is likely
3555 that further simplification will help, so loop, but limit the number
3556 of repetitions that will be performed. */
3557
3558 for (i = 0; i < 4; i++)
3559 {
3560 /* If X is sufficiently simple, don't bother trying to do anything
3561 with it. */
3562 if (code != CONST_INT && code != REG && code != CLOBBER)
3563 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3564
3565 if (GET_CODE (x) == code)
3566 break;
3567
3568 code = GET_CODE (x);
3569
3570 /* We no longer know the original mode of operand 0 since we
3571 have changed the form of X) */
3572 op0_mode = VOIDmode;
3573 }
3574
3575 return x;
3576 }
3577 \f
3578 /* Simplify X, a piece of RTL. We just operate on the expression at the
3579 outer level; call `subst' to simplify recursively. Return the new
3580 expression.
3581
3582 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3583 will be the iteration even if an expression with a code different from
3584 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3585
3586 static rtx
3587 combine_simplify_rtx (x, op0_mode, last, in_dest)
3588 rtx x;
3589 enum machine_mode op0_mode;
3590 int last;
3591 int in_dest;
3592 {
3593 enum rtx_code code = GET_CODE (x);
3594 enum machine_mode mode = GET_MODE (x);
3595 rtx temp;
3596 rtx reversed;
3597 int i;
3598
3599 /* If this is a commutative operation, put a constant last and a complex
3600 expression first. We don't need to do this for comparisons here. */
3601 if (GET_RTX_CLASS (code) == 'c'
3602 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3603 {
3604 temp = XEXP (x, 0);
3605 SUBST (XEXP (x, 0), XEXP (x, 1));
3606 SUBST (XEXP (x, 1), temp);
3607 }
3608
3609 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3610 sign extension of a PLUS with a constant, reverse the order of the sign
3611 extension and the addition. Note that this not the same as the original
3612 code, but overflow is undefined for signed values. Also note that the
3613 PLUS will have been partially moved "inside" the sign-extension, so that
3614 the first operand of X will really look like:
3615 (ashiftrt (plus (ashift A C4) C5) C4).
3616 We convert this to
3617 (plus (ashiftrt (ashift A C4) C2) C4)
3618 and replace the first operand of X with that expression. Later parts
3619 of this function may simplify the expression further.
3620
3621 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3622 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3623 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3624
3625 We do this to simplify address expressions. */
3626
3627 if ((code == PLUS || code == MINUS || code == MULT)
3628 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3629 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3630 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3631 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3632 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3633 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3634 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3635 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3636 XEXP (XEXP (XEXP (x, 0), 0), 1),
3637 XEXP (XEXP (x, 0), 1))) != 0)
3638 {
3639 rtx new
3640 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3641 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3642 INTVAL (XEXP (XEXP (x, 0), 1)));
3643
3644 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3645 INTVAL (XEXP (XEXP (x, 0), 1)));
3646
3647 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3648 }
3649
3650 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3651 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3652 things. Check for cases where both arms are testing the same
3653 condition.
3654
3655 Don't do anything if all operands are very simple. */
3656
3657 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3658 || GET_RTX_CLASS (code) == '<')
3659 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3660 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3661 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3662 == 'o')))
3663 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3664 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3665 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3666 == 'o')))))
3667 || (GET_RTX_CLASS (code) == '1'
3668 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3669 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3670 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3671 == 'o'))))))
3672 {
3673 rtx cond, true_rtx, false_rtx;
3674
3675 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3676 if (cond != 0
3677 /* If everything is a comparison, what we have is highly unlikely
3678 to be simpler, so don't use it. */
3679 && ! (GET_RTX_CLASS (code) == '<'
3680 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3681 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3682 {
3683 rtx cop1 = const0_rtx;
3684 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3685
3686 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3687 return x;
3688
3689 /* Simplify the alternative arms; this may collapse the true and
3690 false arms to store-flag values. */
3691 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3692 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3693
3694 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3695 is unlikely to be simpler. */
3696 if (general_operand (true_rtx, VOIDmode)
3697 && general_operand (false_rtx, VOIDmode))
3698 {
3699 enum rtx_code reversed;
3700
3701 /* Restarting if we generate a store-flag expression will cause
3702 us to loop. Just drop through in this case. */
3703
3704 /* If the result values are STORE_FLAG_VALUE and zero, we can
3705 just make the comparison operation. */
3706 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3707 x = gen_binary (cond_code, mode, cond, cop1);
3708 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3709 && ((reversed = reversed_comparison_code_parts
3710 (cond_code, cond, cop1, NULL))
3711 != UNKNOWN))
3712 x = gen_binary (reversed, mode, cond, cop1);
3713
3714 /* Likewise, we can make the negate of a comparison operation
3715 if the result values are - STORE_FLAG_VALUE and zero. */
3716 else if (GET_CODE (true_rtx) == CONST_INT
3717 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3718 && false_rtx == const0_rtx)
3719 x = simplify_gen_unary (NEG, mode,
3720 gen_binary (cond_code, mode, cond,
3721 cop1),
3722 mode);
3723 else if (GET_CODE (false_rtx) == CONST_INT
3724 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3725 && true_rtx == const0_rtx
3726 && ((reversed = reversed_comparison_code_parts
3727 (cond_code, cond, cop1, NULL))
3728 != UNKNOWN))
3729 x = simplify_gen_unary (NEG, mode,
3730 gen_binary (reversed, mode,
3731 cond, cop1),
3732 mode);
3733 else
3734 return gen_rtx_IF_THEN_ELSE (mode,
3735 gen_binary (cond_code, VOIDmode,
3736 cond, cop1),
3737 true_rtx, false_rtx);
3738
3739 code = GET_CODE (x);
3740 op0_mode = VOIDmode;
3741 }
3742 }
3743 }
3744
3745 /* Try to fold this expression in case we have constants that weren't
3746 present before. */
3747 temp = 0;
3748 switch (GET_RTX_CLASS (code))
3749 {
3750 case '1':
3751 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3752 break;
3753 case '<':
3754 {
3755 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3756 if (cmp_mode == VOIDmode)
3757 {
3758 cmp_mode = GET_MODE (XEXP (x, 1));
3759 if (cmp_mode == VOIDmode)
3760 cmp_mode = op0_mode;
3761 }
3762 temp = simplify_relational_operation (code, cmp_mode,
3763 XEXP (x, 0), XEXP (x, 1));
3764 }
3765 #ifdef FLOAT_STORE_FLAG_VALUE
3766 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3767 {
3768 if (temp == const0_rtx)
3769 temp = CONST0_RTX (mode);
3770 else
3771 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3772 mode);
3773 }
3774 #endif
3775 break;
3776 case 'c':
3777 case '2':
3778 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3779 break;
3780 case 'b':
3781 case '3':
3782 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3783 XEXP (x, 1), XEXP (x, 2));
3784 break;
3785 }
3786
3787 if (temp)
3788 {
3789 x = temp;
3790 code = GET_CODE (temp);
3791 op0_mode = VOIDmode;
3792 mode = GET_MODE (temp);
3793 }
3794
3795 /* First see if we can apply the inverse distributive law. */
3796 if (code == PLUS || code == MINUS
3797 || code == AND || code == IOR || code == XOR)
3798 {
3799 x = apply_distributive_law (x);
3800 code = GET_CODE (x);
3801 op0_mode = VOIDmode;
3802 }
3803
3804 /* If CODE is an associative operation not otherwise handled, see if we
3805 can associate some operands. This can win if they are constants or
3806 if they are logically related (i.e. (a & b) & a). */
3807 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3808 || code == AND || code == IOR || code == XOR
3809 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3810 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3811 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3812 {
3813 if (GET_CODE (XEXP (x, 0)) == code)
3814 {
3815 rtx other = XEXP (XEXP (x, 0), 0);
3816 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3817 rtx inner_op1 = XEXP (x, 1);
3818 rtx inner;
3819
3820 /* Make sure we pass the constant operand if any as the second
3821 one if this is a commutative operation. */
3822 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3823 {
3824 rtx tem = inner_op0;
3825 inner_op0 = inner_op1;
3826 inner_op1 = tem;
3827 }
3828 inner = simplify_binary_operation (code == MINUS ? PLUS
3829 : code == DIV ? MULT
3830 : code,
3831 mode, inner_op0, inner_op1);
3832
3833 /* For commutative operations, try the other pair if that one
3834 didn't simplify. */
3835 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3836 {
3837 other = XEXP (XEXP (x, 0), 1);
3838 inner = simplify_binary_operation (code, mode,
3839 XEXP (XEXP (x, 0), 0),
3840 XEXP (x, 1));
3841 }
3842
3843 if (inner)
3844 return gen_binary (code, mode, other, inner);
3845 }
3846 }
3847
3848 /* A little bit of algebraic simplification here. */
3849 switch (code)
3850 {
3851 case MEM:
3852 /* Ensure that our address has any ASHIFTs converted to MULT in case
3853 address-recognizing predicates are called later. */
3854 temp = make_compound_operation (XEXP (x, 0), MEM);
3855 SUBST (XEXP (x, 0), temp);
3856 break;
3857
3858 case SUBREG:
3859 if (op0_mode == VOIDmode)
3860 op0_mode = GET_MODE (SUBREG_REG (x));
3861
3862 /* simplify_subreg can't use gen_lowpart_for_combine. */
3863 if (CONSTANT_P (SUBREG_REG (x))
3864 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3865 /* Don't call gen_lowpart_for_combine if the inner mode
3866 is VOIDmode and we cannot simplify it, as SUBREG without
3867 inner mode is invalid. */
3868 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3869 || gen_lowpart_common (mode, SUBREG_REG (x))))
3870 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3871
3872 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3873 break;
3874 {
3875 rtx temp;
3876 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3877 SUBREG_BYTE (x));
3878 if (temp)
3879 return temp;
3880 }
3881
3882 /* Don't change the mode of the MEM if that would change the meaning
3883 of the address. */
3884 if (GET_CODE (SUBREG_REG (x)) == MEM
3885 && (MEM_VOLATILE_P (SUBREG_REG (x))
3886 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3887 return gen_rtx_CLOBBER (mode, const0_rtx);
3888
3889 /* Note that we cannot do any narrowing for non-constants since
3890 we might have been counting on using the fact that some bits were
3891 zero. We now do this in the SET. */
3892
3893 break;
3894
3895 case NOT:
3896 /* (not (plus X -1)) can become (neg X). */
3897 if (GET_CODE (XEXP (x, 0)) == PLUS
3898 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3899 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3900
3901 /* Similarly, (not (neg X)) is (plus X -1). */
3902 if (GET_CODE (XEXP (x, 0)) == NEG)
3903 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3904
3905 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3906 if (GET_CODE (XEXP (x, 0)) == XOR
3907 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3908 && (temp = simplify_unary_operation (NOT, mode,
3909 XEXP (XEXP (x, 0), 1),
3910 mode)) != 0)
3911 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3912
3913 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3914 other than 1, but that is not valid. We could do a similar
3915 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3916 but this doesn't seem common enough to bother with. */
3917 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3918 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3919 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3920 const1_rtx, mode),
3921 XEXP (XEXP (x, 0), 1));
3922
3923 if (GET_CODE (XEXP (x, 0)) == SUBREG
3924 && subreg_lowpart_p (XEXP (x, 0))
3925 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3926 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3927 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3928 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3929 {
3930 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3931
3932 x = gen_rtx_ROTATE (inner_mode,
3933 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3934 inner_mode),
3935 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3936 return gen_lowpart_for_combine (mode, x);
3937 }
3938
3939 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3940 reversing the comparison code if valid. */
3941 if (STORE_FLAG_VALUE == -1
3942 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3943 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3944 XEXP (XEXP (x, 0), 1))))
3945 return reversed;
3946
3947 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3948 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3949 perform the above simplification. */
3950
3951 if (STORE_FLAG_VALUE == -1
3952 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3953 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3954 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3955 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3956
3957 /* Apply De Morgan's laws to reduce number of patterns for machines
3958 with negating logical insns (and-not, nand, etc.). If result has
3959 only one NOT, put it first, since that is how the patterns are
3960 coded. */
3961
3962 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3963 {
3964 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3965 enum machine_mode op_mode;
3966
3967 op_mode = GET_MODE (in1);
3968 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3969
3970 op_mode = GET_MODE (in2);
3971 if (op_mode == VOIDmode)
3972 op_mode = mode;
3973 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3974
3975 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3976 {
3977 rtx tem = in2;
3978 in2 = in1; in1 = tem;
3979 }
3980
3981 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3982 mode, in1, in2);
3983 }
3984 break;
3985
3986 case NEG:
3987 /* (neg (plus X 1)) can become (not X). */
3988 if (GET_CODE (XEXP (x, 0)) == PLUS
3989 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3990 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3991
3992 /* Similarly, (neg (not X)) is (plus X 1). */
3993 if (GET_CODE (XEXP (x, 0)) == NOT)
3994 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3995
3996 /* (neg (minus X Y)) can become (minus Y X). This transformation
3997 isn't safe for modes with signed zeros, since if X and Y are
3998 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3999 mode is towards +infinity (or -infinity) then the two expressions
4000 will be rounded differently. */
4001 if (GET_CODE (XEXP (x, 0)) == MINUS
4002 && !HONOR_SIGNED_ZEROS (mode)
4003 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4004 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4005 XEXP (XEXP (x, 0), 0));
4006
4007 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4008 if (GET_CODE (XEXP (x, 0)) == PLUS
4009 && !HONOR_SIGNED_ZEROS (mode)
4010 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4011 {
4012 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4013 temp = combine_simplify_rtx (temp, mode, last, in_dest);
4014 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
4015 }
4016
4017 /* (neg (mult A B)) becomes (mult (neg A) B).
4018 This works even for floating-point values. */
4019 if (GET_CODE (XEXP (x, 0)) == MULT)
4020 {
4021 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4022 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
4023 }
4024
4025 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4026 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4027 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4028 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4029
4030 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4031 if we can then eliminate the NEG (e.g.,
4032 if the operand is a constant). */
4033
4034 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4035 {
4036 temp = simplify_unary_operation (NEG, mode,
4037 XEXP (XEXP (x, 0), 0), mode);
4038 if (temp)
4039 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4040 }
4041
4042 temp = expand_compound_operation (XEXP (x, 0));
4043
4044 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4045 replaced by (lshiftrt X C). This will convert
4046 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4047
4048 if (GET_CODE (temp) == ASHIFTRT
4049 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4050 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4051 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4052 INTVAL (XEXP (temp, 1)));
4053
4054 /* If X has only a single bit that might be nonzero, say, bit I, convert
4055 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4056 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4057 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4058 or a SUBREG of one since we'd be making the expression more
4059 complex if it was just a register. */
4060
4061 if (GET_CODE (temp) != REG
4062 && ! (GET_CODE (temp) == SUBREG
4063 && GET_CODE (SUBREG_REG (temp)) == REG)
4064 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4065 {
4066 rtx temp1 = simplify_shift_const
4067 (NULL_RTX, ASHIFTRT, mode,
4068 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4069 GET_MODE_BITSIZE (mode) - 1 - i),
4070 GET_MODE_BITSIZE (mode) - 1 - i);
4071
4072 /* If all we did was surround TEMP with the two shifts, we
4073 haven't improved anything, so don't use it. Otherwise,
4074 we are better off with TEMP1. */
4075 if (GET_CODE (temp1) != ASHIFTRT
4076 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4077 || XEXP (XEXP (temp1, 0), 0) != temp)
4078 return temp1;
4079 }
4080 break;
4081
4082 case TRUNCATE:
4083 /* We can't handle truncation to a partial integer mode here
4084 because we don't know the real bitsize of the partial
4085 integer mode. */
4086 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4087 break;
4088
4089 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4090 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4091 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4092 SUBST (XEXP (x, 0),
4093 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4094 GET_MODE_MASK (mode), NULL_RTX, 0));
4095
4096 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4097 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4098 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4099 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4100 return XEXP (XEXP (x, 0), 0);
4101
4102 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4103 (OP:SI foo:SI) if OP is NEG or ABS. */
4104 if ((GET_CODE (XEXP (x, 0)) == ABS
4105 || GET_CODE (XEXP (x, 0)) == NEG)
4106 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4107 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4108 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4109 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4110 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4111
4112 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4113 (truncate:SI x). */
4114 if (GET_CODE (XEXP (x, 0)) == SUBREG
4115 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4116 && subreg_lowpart_p (XEXP (x, 0)))
4117 return SUBREG_REG (XEXP (x, 0));
4118
4119 /* If we know that the value is already truncated, we can
4120 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4121 is nonzero for the corresponding modes. But don't do this
4122 for an (LSHIFTRT (MULT ...)) since this will cause problems
4123 with the umulXi3_highpart patterns. */
4124 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4125 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4126 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4127 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4128 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4129 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4130 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4131
4132 /* A truncate of a comparison can be replaced with a subreg if
4133 STORE_FLAG_VALUE permits. This is like the previous test,
4134 but it works even if the comparison is done in a mode larger
4135 than HOST_BITS_PER_WIDE_INT. */
4136 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4137 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4138 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4139 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4140
4141 /* Similarly, a truncate of a register whose value is a
4142 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4143 permits. */
4144 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4145 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4146 && (temp = get_last_value (XEXP (x, 0)))
4147 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4148 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4149
4150 break;
4151
4152 case FLOAT_TRUNCATE:
4153 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4154 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4155 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4156 return XEXP (XEXP (x, 0), 0);
4157
4158 /* (float_truncate:SF (float_truncate:DF foo:XF))
4159 = (float_truncate:SF foo:XF).
4160 This may elliminate double rounding, so it is unsafe.
4161
4162 (float_truncate:SF (float_extend:XF foo:DF))
4163 = (float_truncate:SF foo:DF).
4164
4165 (float_truncate:DF (float_extend:XF foo:SF))
4166 = (float_extend:SF foo:DF). */
4167 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4168 && flag_unsafe_math_optimizations)
4169 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4170 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4171 0)))
4172 > GET_MODE_SIZE (mode)
4173 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4174 mode,
4175 XEXP (XEXP (x, 0), 0), mode);
4176
4177 /* (float_truncate (float x)) is (float x) */
4178 if (GET_CODE (XEXP (x, 0)) == FLOAT
4179 && (flag_unsafe_math_optimizations
4180 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4181 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4182 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4183 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4184 return simplify_gen_unary (FLOAT, mode,
4185 XEXP (XEXP (x, 0), 0),
4186 GET_MODE (XEXP (XEXP (x, 0), 0)));
4187
4188 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4189 (OP:SF foo:SF) if OP is NEG or ABS. */
4190 if ((GET_CODE (XEXP (x, 0)) == ABS
4191 || GET_CODE (XEXP (x, 0)) == NEG)
4192 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4193 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4194 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4195 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4196
4197 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4198 is (float_truncate:SF x). */
4199 if (GET_CODE (XEXP (x, 0)) == SUBREG
4200 && subreg_lowpart_p (XEXP (x, 0))
4201 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4202 return SUBREG_REG (XEXP (x, 0));
4203 break;
4204 case FLOAT_EXTEND:
4205 /* (float_extend (float_extend x)) is (float_extend x)
4206
4207 (float_extend (float x)) is (float x) assuming that double
4208 rounding can't happen.
4209 */
4210 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4211 || (GET_CODE (XEXP (x, 0)) == FLOAT
4212 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4213 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4214 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4215 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4216 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4217 XEXP (XEXP (x, 0), 0),
4218 GET_MODE (XEXP (XEXP (x, 0), 0)));
4219
4220 break;
4221 #ifdef HAVE_cc0
4222 case COMPARE:
4223 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4224 using cc0, in which case we want to leave it as a COMPARE
4225 so we can distinguish it from a register-register-copy. */
4226 if (XEXP (x, 1) == const0_rtx)
4227 return XEXP (x, 0);
4228
4229 /* x - 0 is the same as x unless x's mode has signed zeros and
4230 allows rounding towards -infinity. Under those conditions,
4231 0 - 0 is -0. */
4232 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4233 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4234 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4235 return XEXP (x, 0);
4236 break;
4237 #endif
4238
4239 case CONST:
4240 /* (const (const X)) can become (const X). Do it this way rather than
4241 returning the inner CONST since CONST can be shared with a
4242 REG_EQUAL note. */
4243 if (GET_CODE (XEXP (x, 0)) == CONST)
4244 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4245 break;
4246
4247 #ifdef HAVE_lo_sum
4248 case LO_SUM:
4249 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4250 can add in an offset. find_split_point will split this address up
4251 again if it doesn't match. */
4252 if (GET_CODE (XEXP (x, 0)) == HIGH
4253 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4254 return XEXP (x, 1);
4255 break;
4256 #endif
4257
4258 case PLUS:
4259 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4260 */
4261 if (GET_CODE (XEXP (x, 0)) == MULT
4262 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4263 {
4264 rtx in1, in2;
4265
4266 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4267 in2 = XEXP (XEXP (x, 0), 1);
4268 return gen_binary (MINUS, mode, XEXP (x, 1),
4269 gen_binary (MULT, mode, in1, in2));
4270 }
4271
4272 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4273 outermost. That's because that's the way indexed addresses are
4274 supposed to appear. This code used to check many more cases, but
4275 they are now checked elsewhere. */
4276 if (GET_CODE (XEXP (x, 0)) == PLUS
4277 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4278 return gen_binary (PLUS, mode,
4279 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4280 XEXP (x, 1)),
4281 XEXP (XEXP (x, 0), 1));
4282
4283 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4284 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4285 bit-field and can be replaced by either a sign_extend or a
4286 sign_extract. The `and' may be a zero_extend and the two
4287 <c>, -<c> constants may be reversed. */
4288 if (GET_CODE (XEXP (x, 0)) == XOR
4289 && GET_CODE (XEXP (x, 1)) == CONST_INT
4290 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4291 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4292 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4293 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4294 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4295 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4296 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4297 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4298 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4299 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4300 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4301 == (unsigned int) i + 1))))
4302 return simplify_shift_const
4303 (NULL_RTX, ASHIFTRT, mode,
4304 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4305 XEXP (XEXP (XEXP (x, 0), 0), 0),
4306 GET_MODE_BITSIZE (mode) - (i + 1)),
4307 GET_MODE_BITSIZE (mode) - (i + 1));
4308
4309 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4310 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4311 is 1. This produces better code than the alternative immediately
4312 below. */
4313 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4314 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4315 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4316 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4317 XEXP (XEXP (x, 0), 0),
4318 XEXP (XEXP (x, 0), 1))))
4319 return
4320 simplify_gen_unary (NEG, mode, reversed, mode);
4321
4322 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4323 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4324 the bitsize of the mode - 1. This allows simplification of
4325 "a = (b & 8) == 0;" */
4326 if (XEXP (x, 1) == constm1_rtx
4327 && GET_CODE (XEXP (x, 0)) != REG
4328 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4329 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4330 && nonzero_bits (XEXP (x, 0), mode) == 1)
4331 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4332 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4333 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4334 GET_MODE_BITSIZE (mode) - 1),
4335 GET_MODE_BITSIZE (mode) - 1);
4336
4337 /* If we are adding two things that have no bits in common, convert
4338 the addition into an IOR. This will often be further simplified,
4339 for example in cases like ((a & 1) + (a & 2)), which can
4340 become a & 3. */
4341
4342 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4343 && (nonzero_bits (XEXP (x, 0), mode)
4344 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4345 {
4346 /* Try to simplify the expression further. */
4347 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4348 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4349
4350 /* If we could, great. If not, do not go ahead with the IOR
4351 replacement, since PLUS appears in many special purpose
4352 address arithmetic instructions. */
4353 if (GET_CODE (temp) != CLOBBER && temp != tor)
4354 return temp;
4355 }
4356 break;
4357
4358 case MINUS:
4359 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4360 by reversing the comparison code if valid. */
4361 if (STORE_FLAG_VALUE == 1
4362 && XEXP (x, 0) == const1_rtx
4363 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4364 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4365 XEXP (XEXP (x, 1), 0),
4366 XEXP (XEXP (x, 1), 1))))
4367 return reversed;
4368
4369 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4370 (and <foo> (const_int pow2-1)) */
4371 if (GET_CODE (XEXP (x, 1)) == AND
4372 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4373 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4374 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4375 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4376 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4377
4378 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4379 */
4380 if (GET_CODE (XEXP (x, 1)) == MULT
4381 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4382 {
4383 rtx in1, in2;
4384
4385 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4386 in2 = XEXP (XEXP (x, 1), 1);
4387 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4388 XEXP (x, 0));
4389 }
4390
4391 /* Canonicalize (minus (neg A) (mult B C)) to
4392 (minus (mult (neg B) C) A). */
4393 if (GET_CODE (XEXP (x, 1)) == MULT
4394 && GET_CODE (XEXP (x, 0)) == NEG)
4395 {
4396 rtx in1, in2;
4397
4398 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4399 in2 = XEXP (XEXP (x, 1), 1);
4400 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4401 XEXP (XEXP (x, 0), 0));
4402 }
4403
4404 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4405 integers. */
4406 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4407 return gen_binary (MINUS, mode,
4408 gen_binary (MINUS, mode, XEXP (x, 0),
4409 XEXP (XEXP (x, 1), 0)),
4410 XEXP (XEXP (x, 1), 1));
4411 break;
4412
4413 case MULT:
4414 /* If we have (mult (plus A B) C), apply the distributive law and then
4415 the inverse distributive law to see if things simplify. This
4416 occurs mostly in addresses, often when unrolling loops. */
4417
4418 if (GET_CODE (XEXP (x, 0)) == PLUS)
4419 {
4420 x = apply_distributive_law
4421 (gen_binary (PLUS, mode,
4422 gen_binary (MULT, mode,
4423 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4424 gen_binary (MULT, mode,
4425 XEXP (XEXP (x, 0), 1),
4426 copy_rtx (XEXP (x, 1)))));
4427
4428 if (GET_CODE (x) != MULT)
4429 return x;
4430 }
4431 /* Try simplify a*(b/c) as (a*b)/c. */
4432 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4433 && GET_CODE (XEXP (x, 0)) == DIV)
4434 {
4435 rtx tem = simplify_binary_operation (MULT, mode,
4436 XEXP (XEXP (x, 0), 0),
4437 XEXP (x, 1));
4438 if (tem)
4439 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4440 }
4441 break;
4442
4443 case UDIV:
4444 /* If this is a divide by a power of two, treat it as a shift if
4445 its first operand is a shift. */
4446 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4447 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4448 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4449 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4450 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4451 || GET_CODE (XEXP (x, 0)) == ROTATE
4452 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4453 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4454 break;
4455
4456 case EQ: case NE:
4457 case GT: case GTU: case GE: case GEU:
4458 case LT: case LTU: case LE: case LEU:
4459 case UNEQ: case LTGT:
4460 case UNGT: case UNGE:
4461 case UNLT: case UNLE:
4462 case UNORDERED: case ORDERED:
4463 /* If the first operand is a condition code, we can't do anything
4464 with it. */
4465 if (GET_CODE (XEXP (x, 0)) == COMPARE
4466 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4467 && ! CC0_P (XEXP (x, 0))))
4468 {
4469 rtx op0 = XEXP (x, 0);
4470 rtx op1 = XEXP (x, 1);
4471 enum rtx_code new_code;
4472
4473 if (GET_CODE (op0) == COMPARE)
4474 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4475
4476 /* Simplify our comparison, if possible. */
4477 new_code = simplify_comparison (code, &op0, &op1);
4478
4479 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4480 if only the low-order bit is possibly nonzero in X (such as when
4481 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4482 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4483 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4484 (plus X 1).
4485
4486 Remove any ZERO_EXTRACT we made when thinking this was a
4487 comparison. It may now be simpler to use, e.g., an AND. If a
4488 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4489 the call to make_compound_operation in the SET case. */
4490
4491 if (STORE_FLAG_VALUE == 1
4492 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4493 && op1 == const0_rtx
4494 && mode == GET_MODE (op0)
4495 && nonzero_bits (op0, mode) == 1)
4496 return gen_lowpart_for_combine (mode,
4497 expand_compound_operation (op0));
4498
4499 else if (STORE_FLAG_VALUE == 1
4500 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4501 && op1 == const0_rtx
4502 && mode == GET_MODE (op0)
4503 && (num_sign_bit_copies (op0, mode)
4504 == GET_MODE_BITSIZE (mode)))
4505 {
4506 op0 = expand_compound_operation (op0);
4507 return simplify_gen_unary (NEG, mode,
4508 gen_lowpart_for_combine (mode, op0),
4509 mode);
4510 }
4511
4512 else if (STORE_FLAG_VALUE == 1
4513 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4514 && op1 == const0_rtx
4515 && mode == GET_MODE (op0)
4516 && nonzero_bits (op0, mode) == 1)
4517 {
4518 op0 = expand_compound_operation (op0);
4519 return gen_binary (XOR, mode,
4520 gen_lowpart_for_combine (mode, op0),
4521 const1_rtx);
4522 }
4523
4524 else if (STORE_FLAG_VALUE == 1
4525 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4526 && op1 == const0_rtx
4527 && mode == GET_MODE (op0)
4528 && (num_sign_bit_copies (op0, mode)
4529 == GET_MODE_BITSIZE (mode)))
4530 {
4531 op0 = expand_compound_operation (op0);
4532 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4533 }
4534
4535 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4536 those above. */
4537 if (STORE_FLAG_VALUE == -1
4538 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4539 && op1 == const0_rtx
4540 && (num_sign_bit_copies (op0, mode)
4541 == GET_MODE_BITSIZE (mode)))
4542 return gen_lowpart_for_combine (mode,
4543 expand_compound_operation (op0));
4544
4545 else if (STORE_FLAG_VALUE == -1
4546 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4547 && op1 == const0_rtx
4548 && mode == GET_MODE (op0)
4549 && nonzero_bits (op0, mode) == 1)
4550 {
4551 op0 = expand_compound_operation (op0);
4552 return simplify_gen_unary (NEG, mode,
4553 gen_lowpart_for_combine (mode, op0),
4554 mode);
4555 }
4556
4557 else if (STORE_FLAG_VALUE == -1
4558 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4559 && op1 == const0_rtx
4560 && mode == GET_MODE (op0)
4561 && (num_sign_bit_copies (op0, mode)
4562 == GET_MODE_BITSIZE (mode)))
4563 {
4564 op0 = expand_compound_operation (op0);
4565 return simplify_gen_unary (NOT, mode,
4566 gen_lowpart_for_combine (mode, op0),
4567 mode);
4568 }
4569
4570 /* If X is 0/1, (eq X 0) is X-1. */
4571 else if (STORE_FLAG_VALUE == -1
4572 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4573 && op1 == const0_rtx
4574 && mode == GET_MODE (op0)
4575 && nonzero_bits (op0, mode) == 1)
4576 {
4577 op0 = expand_compound_operation (op0);
4578 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4579 }
4580
4581 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4582 one bit that might be nonzero, we can convert (ne x 0) to
4583 (ashift x c) where C puts the bit in the sign bit. Remove any
4584 AND with STORE_FLAG_VALUE when we are done, since we are only
4585 going to test the sign bit. */
4586 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4587 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4588 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4589 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4590 && op1 == const0_rtx
4591 && mode == GET_MODE (op0)
4592 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4593 {
4594 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4595 expand_compound_operation (op0),
4596 GET_MODE_BITSIZE (mode) - 1 - i);
4597 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4598 return XEXP (x, 0);
4599 else
4600 return x;
4601 }
4602
4603 /* If the code changed, return a whole new comparison. */
4604 if (new_code != code)
4605 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4606
4607 /* Otherwise, keep this operation, but maybe change its operands.
4608 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4609 SUBST (XEXP (x, 0), op0);
4610 SUBST (XEXP (x, 1), op1);
4611 }
4612 break;
4613
4614 case IF_THEN_ELSE:
4615 return simplify_if_then_else (x);
4616
4617 case ZERO_EXTRACT:
4618 case SIGN_EXTRACT:
4619 case ZERO_EXTEND:
4620 case SIGN_EXTEND:
4621 /* If we are processing SET_DEST, we are done. */
4622 if (in_dest)
4623 return x;
4624
4625 return expand_compound_operation (x);
4626
4627 case SET:
4628 return simplify_set (x);
4629
4630 case AND:
4631 case IOR:
4632 case XOR:
4633 return simplify_logical (x, last);
4634
4635 case ABS:
4636 /* (abs (neg <foo>)) -> (abs <foo>) */
4637 if (GET_CODE (XEXP (x, 0)) == NEG)
4638 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4639
4640 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4641 do nothing. */
4642 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4643 break;
4644
4645 /* If operand is something known to be positive, ignore the ABS. */
4646 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4647 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4648 <= HOST_BITS_PER_WIDE_INT)
4649 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4650 & ((HOST_WIDE_INT) 1
4651 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4652 == 0)))
4653 return XEXP (x, 0);
4654
4655 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4656 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4657 return gen_rtx_NEG (mode, XEXP (x, 0));
4658
4659 break;
4660
4661 case FFS:
4662 /* (ffs (*_extend <X>)) = (ffs <X>) */
4663 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4664 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4665 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4666 break;
4667
4668 case POPCOUNT:
4669 case PARITY:
4670 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4671 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4672 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4673 break;
4674
4675 case FLOAT:
4676 /* (float (sign_extend <X>)) = (float <X>). */
4677 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4678 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4679 break;
4680
4681 case ASHIFT:
4682 case LSHIFTRT:
4683 case ASHIFTRT:
4684 case ROTATE:
4685 case ROTATERT:
4686 /* If this is a shift by a constant amount, simplify it. */
4687 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4688 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4689 INTVAL (XEXP (x, 1)));
4690
4691 #ifdef SHIFT_COUNT_TRUNCATED
4692 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4693 SUBST (XEXP (x, 1),
4694 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4695 ((HOST_WIDE_INT) 1
4696 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4697 - 1,
4698 NULL_RTX, 0));
4699 #endif
4700
4701 break;
4702
4703 case VEC_SELECT:
4704 {
4705 rtx op0 = XEXP (x, 0);
4706 rtx op1 = XEXP (x, 1);
4707 int len;
4708
4709 if (GET_CODE (op1) != PARALLEL)
4710 abort ();
4711 len = XVECLEN (op1, 0);
4712 if (len == 1
4713 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4714 && GET_CODE (op0) == VEC_CONCAT)
4715 {
4716 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4717
4718 /* Try to find the element in the VEC_CONCAT. */
4719 for (;;)
4720 {
4721 if (GET_MODE (op0) == GET_MODE (x))
4722 return op0;
4723 if (GET_CODE (op0) == VEC_CONCAT)
4724 {
4725 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4726 if (op0_size < offset)
4727 op0 = XEXP (op0, 0);
4728 else
4729 {
4730 offset -= op0_size;
4731 op0 = XEXP (op0, 1);
4732 }
4733 }
4734 else
4735 break;
4736 }
4737 }
4738 }
4739
4740 break;
4741
4742 default:
4743 break;
4744 }
4745
4746 return x;
4747 }
4748 \f
4749 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4750
4751 static rtx
4752 simplify_if_then_else (x)
4753 rtx x;
4754 {
4755 enum machine_mode mode = GET_MODE (x);
4756 rtx cond = XEXP (x, 0);
4757 rtx true_rtx = XEXP (x, 1);
4758 rtx false_rtx = XEXP (x, 2);
4759 enum rtx_code true_code = GET_CODE (cond);
4760 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4761 rtx temp;
4762 int i;
4763 enum rtx_code false_code;
4764 rtx reversed;
4765
4766 /* Simplify storing of the truth value. */
4767 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4768 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4769
4770 /* Also when the truth value has to be reversed. */
4771 if (comparison_p
4772 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4773 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4774 XEXP (cond, 1))))
4775 return reversed;
4776
4777 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4778 in it is being compared against certain values. Get the true and false
4779 comparisons and see if that says anything about the value of each arm. */
4780
4781 if (comparison_p
4782 && ((false_code = combine_reversed_comparison_code (cond))
4783 != UNKNOWN)
4784 && GET_CODE (XEXP (cond, 0)) == REG)
4785 {
4786 HOST_WIDE_INT nzb;
4787 rtx from = XEXP (cond, 0);
4788 rtx true_val = XEXP (cond, 1);
4789 rtx false_val = true_val;
4790 int swapped = 0;
4791
4792 /* If FALSE_CODE is EQ, swap the codes and arms. */
4793
4794 if (false_code == EQ)
4795 {
4796 swapped = 1, true_code = EQ, false_code = NE;
4797 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4798 }
4799
4800 /* If we are comparing against zero and the expression being tested has
4801 only a single bit that might be nonzero, that is its value when it is
4802 not equal to zero. Similarly if it is known to be -1 or 0. */
4803
4804 if (true_code == EQ && true_val == const0_rtx
4805 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4806 false_code = EQ, false_val = GEN_INT (nzb);
4807 else if (true_code == EQ && true_val == const0_rtx
4808 && (num_sign_bit_copies (from, GET_MODE (from))
4809 == GET_MODE_BITSIZE (GET_MODE (from))))
4810 false_code = EQ, false_val = constm1_rtx;
4811
4812 /* Now simplify an arm if we know the value of the register in the
4813 branch and it is used in the arm. Be careful due to the potential
4814 of locally-shared RTL. */
4815
4816 if (reg_mentioned_p (from, true_rtx))
4817 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4818 from, true_val),
4819 pc_rtx, pc_rtx, 0, 0);
4820 if (reg_mentioned_p (from, false_rtx))
4821 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4822 from, false_val),
4823 pc_rtx, pc_rtx, 0, 0);
4824
4825 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4826 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4827
4828 true_rtx = XEXP (x, 1);
4829 false_rtx = XEXP (x, 2);
4830 true_code = GET_CODE (cond);
4831 }
4832
4833 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4834 reversed, do so to avoid needing two sets of patterns for
4835 subtract-and-branch insns. Similarly if we have a constant in the true
4836 arm, the false arm is the same as the first operand of the comparison, or
4837 the false arm is more complicated than the true arm. */
4838
4839 if (comparison_p
4840 && combine_reversed_comparison_code (cond) != UNKNOWN
4841 && (true_rtx == pc_rtx
4842 || (CONSTANT_P (true_rtx)
4843 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4844 || true_rtx == const0_rtx
4845 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4846 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4847 || (GET_CODE (true_rtx) == SUBREG
4848 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4849 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4850 || reg_mentioned_p (true_rtx, false_rtx)
4851 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4852 {
4853 true_code = reversed_comparison_code (cond, NULL);
4854 SUBST (XEXP (x, 0),
4855 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4856 XEXP (cond, 1)));
4857
4858 SUBST (XEXP (x, 1), false_rtx);
4859 SUBST (XEXP (x, 2), true_rtx);
4860
4861 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4862 cond = XEXP (x, 0);
4863
4864 /* It is possible that the conditional has been simplified out. */
4865 true_code = GET_CODE (cond);
4866 comparison_p = GET_RTX_CLASS (true_code) == '<';
4867 }
4868
4869 /* If the two arms are identical, we don't need the comparison. */
4870
4871 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4872 return true_rtx;
4873
4874 /* Convert a == b ? b : a to "a". */
4875 if (true_code == EQ && ! side_effects_p (cond)
4876 && !HONOR_NANS (mode)
4877 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4878 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4879 return false_rtx;
4880 else if (true_code == NE && ! side_effects_p (cond)
4881 && !HONOR_NANS (mode)
4882 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4883 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4884 return true_rtx;
4885
4886 /* Look for cases where we have (abs x) or (neg (abs X)). */
4887
4888 if (GET_MODE_CLASS (mode) == MODE_INT
4889 && GET_CODE (false_rtx) == NEG
4890 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4891 && comparison_p
4892 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4893 && ! side_effects_p (true_rtx))
4894 switch (true_code)
4895 {
4896 case GT:
4897 case GE:
4898 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4899 case LT:
4900 case LE:
4901 return
4902 simplify_gen_unary (NEG, mode,
4903 simplify_gen_unary (ABS, mode, true_rtx, mode),
4904 mode);
4905 default:
4906 break;
4907 }
4908
4909 /* Look for MIN or MAX. */
4910
4911 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4912 && comparison_p
4913 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4914 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4915 && ! side_effects_p (cond))
4916 switch (true_code)
4917 {
4918 case GE:
4919 case GT:
4920 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4921 case LE:
4922 case LT:
4923 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4924 case GEU:
4925 case GTU:
4926 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4927 case LEU:
4928 case LTU:
4929 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4930 default:
4931 break;
4932 }
4933
4934 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4935 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4936 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4937 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4938 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4939 neither 1 or -1, but it isn't worth checking for. */
4940
4941 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4942 && comparison_p
4943 && GET_MODE_CLASS (mode) == MODE_INT
4944 && ! side_effects_p (x))
4945 {
4946 rtx t = make_compound_operation (true_rtx, SET);
4947 rtx f = make_compound_operation (false_rtx, SET);
4948 rtx cond_op0 = XEXP (cond, 0);
4949 rtx cond_op1 = XEXP (cond, 1);
4950 enum rtx_code op = NIL, extend_op = NIL;
4951 enum machine_mode m = mode;
4952 rtx z = 0, c1 = NULL_RTX;
4953
4954 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4955 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4956 || GET_CODE (t) == ASHIFT
4957 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4958 && rtx_equal_p (XEXP (t, 0), f))
4959 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4960
4961 /* If an identity-zero op is commutative, check whether there
4962 would be a match if we swapped the operands. */
4963 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4964 || GET_CODE (t) == XOR)
4965 && rtx_equal_p (XEXP (t, 1), f))
4966 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4967 else if (GET_CODE (t) == SIGN_EXTEND
4968 && (GET_CODE (XEXP (t, 0)) == PLUS
4969 || GET_CODE (XEXP (t, 0)) == MINUS
4970 || GET_CODE (XEXP (t, 0)) == IOR
4971 || GET_CODE (XEXP (t, 0)) == XOR
4972 || GET_CODE (XEXP (t, 0)) == ASHIFT
4973 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4974 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4975 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4976 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4977 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4978 && (num_sign_bit_copies (f, GET_MODE (f))
4979 > (unsigned int)
4980 (GET_MODE_BITSIZE (mode)
4981 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4982 {
4983 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4984 extend_op = SIGN_EXTEND;
4985 m = GET_MODE (XEXP (t, 0));
4986 }
4987 else if (GET_CODE (t) == SIGN_EXTEND
4988 && (GET_CODE (XEXP (t, 0)) == PLUS
4989 || GET_CODE (XEXP (t, 0)) == IOR
4990 || GET_CODE (XEXP (t, 0)) == XOR)
4991 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4992 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4993 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4994 && (num_sign_bit_copies (f, GET_MODE (f))
4995 > (unsigned int)
4996 (GET_MODE_BITSIZE (mode)
4997 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4998 {
4999 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5000 extend_op = SIGN_EXTEND;
5001 m = GET_MODE (XEXP (t, 0));
5002 }
5003 else if (GET_CODE (t) == ZERO_EXTEND
5004 && (GET_CODE (XEXP (t, 0)) == PLUS
5005 || GET_CODE (XEXP (t, 0)) == MINUS
5006 || GET_CODE (XEXP (t, 0)) == IOR
5007 || GET_CODE (XEXP (t, 0)) == XOR
5008 || GET_CODE (XEXP (t, 0)) == ASHIFT
5009 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5010 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5011 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5012 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5013 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5014 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5015 && ((nonzero_bits (f, GET_MODE (f))
5016 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5017 == 0))
5018 {
5019 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5020 extend_op = ZERO_EXTEND;
5021 m = GET_MODE (XEXP (t, 0));
5022 }
5023 else if (GET_CODE (t) == ZERO_EXTEND
5024 && (GET_CODE (XEXP (t, 0)) == PLUS
5025 || GET_CODE (XEXP (t, 0)) == IOR
5026 || GET_CODE (XEXP (t, 0)) == XOR)
5027 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5028 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5029 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5030 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5031 && ((nonzero_bits (f, GET_MODE (f))
5032 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5033 == 0))
5034 {
5035 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5036 extend_op = ZERO_EXTEND;
5037 m = GET_MODE (XEXP (t, 0));
5038 }
5039
5040 if (z)
5041 {
5042 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5043 pc_rtx, pc_rtx, 0, 0);
5044 temp = gen_binary (MULT, m, temp,
5045 gen_binary (MULT, m, c1, const_true_rtx));
5046 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5047 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5048
5049 if (extend_op != NIL)
5050 temp = simplify_gen_unary (extend_op, mode, temp, m);
5051
5052 return temp;
5053 }
5054 }
5055
5056 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5057 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5058 negation of a single bit, we can convert this operation to a shift. We
5059 can actually do this more generally, but it doesn't seem worth it. */
5060
5061 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5062 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5063 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5064 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5065 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5066 == GET_MODE_BITSIZE (mode))
5067 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5068 return
5069 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5070 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5071
5072 return x;
5073 }
5074 \f
5075 /* Simplify X, a SET expression. Return the new expression. */
5076
5077 static rtx
5078 simplify_set (x)
5079 rtx x;
5080 {
5081 rtx src = SET_SRC (x);
5082 rtx dest = SET_DEST (x);
5083 enum machine_mode mode
5084 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5085 rtx other_insn;
5086 rtx *cc_use;
5087
5088 /* (set (pc) (return)) gets written as (return). */
5089 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5090 return src;
5091
5092 /* Now that we know for sure which bits of SRC we are using, see if we can
5093 simplify the expression for the object knowing that we only need the
5094 low-order bits. */
5095
5096 if (GET_MODE_CLASS (mode) == MODE_INT
5097 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5098 {
5099 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5100 SUBST (SET_SRC (x), src);
5101 }
5102
5103 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5104 the comparison result and try to simplify it unless we already have used
5105 undobuf.other_insn. */
5106 if ((GET_MODE_CLASS (mode) == MODE_CC
5107 || GET_CODE (src) == COMPARE
5108 || CC0_P (dest))
5109 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5110 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5111 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5112 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5113 {
5114 enum rtx_code old_code = GET_CODE (*cc_use);
5115 enum rtx_code new_code;
5116 rtx op0, op1, tmp;
5117 int other_changed = 0;
5118 enum machine_mode compare_mode = GET_MODE (dest);
5119 enum machine_mode tmp_mode;
5120
5121 if (GET_CODE (src) == COMPARE)
5122 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5123 else
5124 op0 = src, op1 = const0_rtx;
5125
5126 /* Check whether the comparison is known at compile time. */
5127 if (GET_MODE (op0) != VOIDmode)
5128 tmp_mode = GET_MODE (op0);
5129 else if (GET_MODE (op1) != VOIDmode)
5130 tmp_mode = GET_MODE (op1);
5131 else
5132 tmp_mode = compare_mode;
5133 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5134 if (tmp != NULL_RTX)
5135 {
5136 rtx pat = PATTERN (other_insn);
5137 undobuf.other_insn = other_insn;
5138 SUBST (*cc_use, tmp);
5139
5140 /* Attempt to simplify CC user. */
5141 if (GET_CODE (pat) == SET)
5142 {
5143 rtx new = simplify_rtx (SET_SRC (pat));
5144 if (new != NULL_RTX)
5145 SUBST (SET_SRC (pat), new);
5146 }
5147
5148 /* Convert X into a no-op move. */
5149 SUBST (SET_DEST (x), pc_rtx);
5150 SUBST (SET_SRC (x), pc_rtx);
5151 return x;
5152 }
5153
5154 /* Simplify our comparison, if possible. */
5155 new_code = simplify_comparison (old_code, &op0, &op1);
5156
5157 #ifdef EXTRA_CC_MODES
5158 /* If this machine has CC modes other than CCmode, check to see if we
5159 need to use a different CC mode here. */
5160 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5161 #endif /* EXTRA_CC_MODES */
5162
5163 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5164 /* If the mode changed, we have to change SET_DEST, the mode in the
5165 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5166 a hard register, just build new versions with the proper mode. If it
5167 is a pseudo, we lose unless it is only time we set the pseudo, in
5168 which case we can safely change its mode. */
5169 if (compare_mode != GET_MODE (dest))
5170 {
5171 unsigned int regno = REGNO (dest);
5172 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5173
5174 if (regno < FIRST_PSEUDO_REGISTER
5175 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5176 {
5177 if (regno >= FIRST_PSEUDO_REGISTER)
5178 SUBST (regno_reg_rtx[regno], new_dest);
5179
5180 SUBST (SET_DEST (x), new_dest);
5181 SUBST (XEXP (*cc_use, 0), new_dest);
5182 other_changed = 1;
5183
5184 dest = new_dest;
5185 }
5186 }
5187 #endif
5188
5189 /* If the code changed, we have to build a new comparison in
5190 undobuf.other_insn. */
5191 if (new_code != old_code)
5192 {
5193 unsigned HOST_WIDE_INT mask;
5194
5195 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5196 dest, const0_rtx));
5197
5198 /* If the only change we made was to change an EQ into an NE or
5199 vice versa, OP0 has only one bit that might be nonzero, and OP1
5200 is zero, check if changing the user of the condition code will
5201 produce a valid insn. If it won't, we can keep the original code
5202 in that insn by surrounding our operation with an XOR. */
5203
5204 if (((old_code == NE && new_code == EQ)
5205 || (old_code == EQ && new_code == NE))
5206 && ! other_changed && op1 == const0_rtx
5207 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5208 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5209 {
5210 rtx pat = PATTERN (other_insn), note = 0;
5211
5212 if ((recog_for_combine (&pat, other_insn, &note) < 0
5213 && ! check_asm_operands (pat)))
5214 {
5215 PUT_CODE (*cc_use, old_code);
5216 other_insn = 0;
5217
5218 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5219 }
5220 }
5221
5222 other_changed = 1;
5223 }
5224
5225 if (other_changed)
5226 undobuf.other_insn = other_insn;
5227
5228 #ifdef HAVE_cc0
5229 /* If we are now comparing against zero, change our source if
5230 needed. If we do not use cc0, we always have a COMPARE. */
5231 if (op1 == const0_rtx && dest == cc0_rtx)
5232 {
5233 SUBST (SET_SRC (x), op0);
5234 src = op0;
5235 }
5236 else
5237 #endif
5238
5239 /* Otherwise, if we didn't previously have a COMPARE in the
5240 correct mode, we need one. */
5241 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5242 {
5243 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5244 src = SET_SRC (x);
5245 }
5246 else
5247 {
5248 /* Otherwise, update the COMPARE if needed. */
5249 SUBST (XEXP (src, 0), op0);
5250 SUBST (XEXP (src, 1), op1);
5251 }
5252 }
5253 else
5254 {
5255 /* Get SET_SRC in a form where we have placed back any
5256 compound expressions. Then do the checks below. */
5257 src = make_compound_operation (src, SET);
5258 SUBST (SET_SRC (x), src);
5259 }
5260
5261 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5262 and X being a REG or (subreg (reg)), we may be able to convert this to
5263 (set (subreg:m2 x) (op)).
5264
5265 We can always do this if M1 is narrower than M2 because that means that
5266 we only care about the low bits of the result.
5267
5268 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5269 perform a narrower operation than requested since the high-order bits will
5270 be undefined. On machine where it is defined, this transformation is safe
5271 as long as M1 and M2 have the same number of words. */
5272
5273 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5274 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5275 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5276 / UNITS_PER_WORD)
5277 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5278 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5279 #ifndef WORD_REGISTER_OPERATIONS
5280 && (GET_MODE_SIZE (GET_MODE (src))
5281 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5282 #endif
5283 #ifdef CANNOT_CHANGE_MODE_CLASS
5284 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5285 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5286 GET_MODE (SUBREG_REG (src)),
5287 GET_MODE (src)))
5288 #endif
5289 && (GET_CODE (dest) == REG
5290 || (GET_CODE (dest) == SUBREG
5291 && GET_CODE (SUBREG_REG (dest)) == REG)))
5292 {
5293 SUBST (SET_DEST (x),
5294 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5295 dest));
5296 SUBST (SET_SRC (x), SUBREG_REG (src));
5297
5298 src = SET_SRC (x), dest = SET_DEST (x);
5299 }
5300
5301 #ifdef HAVE_cc0
5302 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5303 in SRC. */
5304 if (dest == cc0_rtx
5305 && GET_CODE (src) == SUBREG
5306 && subreg_lowpart_p (src)
5307 && (GET_MODE_BITSIZE (GET_MODE (src))
5308 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5309 {
5310 rtx inner = SUBREG_REG (src);
5311 enum machine_mode inner_mode = GET_MODE (inner);
5312
5313 /* Here we make sure that we don't have a sign bit on. */
5314 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5315 && (nonzero_bits (inner, inner_mode)
5316 < ((unsigned HOST_WIDE_INT) 1
5317 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5318 {
5319 SUBST (SET_SRC (x), inner);
5320 src = SET_SRC (x);
5321 }
5322 }
5323 #endif
5324
5325 #ifdef LOAD_EXTEND_OP
5326 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5327 would require a paradoxical subreg. Replace the subreg with a
5328 zero_extend to avoid the reload that would otherwise be required. */
5329
5330 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5331 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5332 && SUBREG_BYTE (src) == 0
5333 && (GET_MODE_SIZE (GET_MODE (src))
5334 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5335 && GET_CODE (SUBREG_REG (src)) == MEM)
5336 {
5337 SUBST (SET_SRC (x),
5338 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5339 GET_MODE (src), SUBREG_REG (src)));
5340
5341 src = SET_SRC (x);
5342 }
5343 #endif
5344
5345 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5346 are comparing an item known to be 0 or -1 against 0, use a logical
5347 operation instead. Check for one of the arms being an IOR of the other
5348 arm with some value. We compute three terms to be IOR'ed together. In
5349 practice, at most two will be nonzero. Then we do the IOR's. */
5350
5351 if (GET_CODE (dest) != PC
5352 && GET_CODE (src) == IF_THEN_ELSE
5353 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5354 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5355 && XEXP (XEXP (src, 0), 1) == const0_rtx
5356 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5357 #ifdef HAVE_conditional_move
5358 && ! can_conditionally_move_p (GET_MODE (src))
5359 #endif
5360 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5361 GET_MODE (XEXP (XEXP (src, 0), 0)))
5362 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5363 && ! side_effects_p (src))
5364 {
5365 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5366 ? XEXP (src, 1) : XEXP (src, 2));
5367 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5368 ? XEXP (src, 2) : XEXP (src, 1));
5369 rtx term1 = const0_rtx, term2, term3;
5370
5371 if (GET_CODE (true_rtx) == IOR
5372 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5373 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5374 else if (GET_CODE (true_rtx) == IOR
5375 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5376 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5377 else if (GET_CODE (false_rtx) == IOR
5378 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5379 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5380 else if (GET_CODE (false_rtx) == IOR
5381 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5382 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5383
5384 term2 = gen_binary (AND, GET_MODE (src),
5385 XEXP (XEXP (src, 0), 0), true_rtx);
5386 term3 = gen_binary (AND, GET_MODE (src),
5387 simplify_gen_unary (NOT, GET_MODE (src),
5388 XEXP (XEXP (src, 0), 0),
5389 GET_MODE (src)),
5390 false_rtx);
5391
5392 SUBST (SET_SRC (x),
5393 gen_binary (IOR, GET_MODE (src),
5394 gen_binary (IOR, GET_MODE (src), term1, term2),
5395 term3));
5396
5397 src = SET_SRC (x);
5398 }
5399
5400 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5401 whole thing fail. */
5402 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5403 return src;
5404 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5405 return dest;
5406 else
5407 /* Convert this into a field assignment operation, if possible. */
5408 return make_field_assignment (x);
5409 }
5410 \f
5411 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5412 result. LAST is nonzero if this is the last retry. */
5413
5414 static rtx
5415 simplify_logical (x, last)
5416 rtx x;
5417 int last;
5418 {
5419 enum machine_mode mode = GET_MODE (x);
5420 rtx op0 = XEXP (x, 0);
5421 rtx op1 = XEXP (x, 1);
5422 rtx reversed;
5423
5424 switch (GET_CODE (x))
5425 {
5426 case AND:
5427 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5428 insn (and may simplify more). */
5429 if (GET_CODE (op0) == XOR
5430 && rtx_equal_p (XEXP (op0, 0), op1)
5431 && ! side_effects_p (op1))
5432 x = gen_binary (AND, mode,
5433 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5434 op1);
5435
5436 if (GET_CODE (op0) == XOR
5437 && rtx_equal_p (XEXP (op0, 1), op1)
5438 && ! side_effects_p (op1))
5439 x = gen_binary (AND, mode,
5440 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5441 op1);
5442
5443 /* Similarly for (~(A ^ B)) & A. */
5444 if (GET_CODE (op0) == NOT
5445 && GET_CODE (XEXP (op0, 0)) == XOR
5446 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5447 && ! side_effects_p (op1))
5448 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5449
5450 if (GET_CODE (op0) == NOT
5451 && GET_CODE (XEXP (op0, 0)) == XOR
5452 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5453 && ! side_effects_p (op1))
5454 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5455
5456 /* We can call simplify_and_const_int only if we don't lose
5457 any (sign) bits when converting INTVAL (op1) to
5458 "unsigned HOST_WIDE_INT". */
5459 if (GET_CODE (op1) == CONST_INT
5460 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5461 || INTVAL (op1) > 0))
5462 {
5463 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5464
5465 /* If we have (ior (and (X C1) C2)) and the next restart would be
5466 the last, simplify this by making C1 as small as possible
5467 and then exit. */
5468 if (last
5469 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5470 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5471 && GET_CODE (op1) == CONST_INT)
5472 return gen_binary (IOR, mode,
5473 gen_binary (AND, mode, XEXP (op0, 0),
5474 GEN_INT (INTVAL (XEXP (op0, 1))
5475 & ~INTVAL (op1))), op1);
5476
5477 if (GET_CODE (x) != AND)
5478 return x;
5479
5480 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5481 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5482 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5483 }
5484
5485 /* Convert (A | B) & A to A. */
5486 if (GET_CODE (op0) == IOR
5487 && (rtx_equal_p (XEXP (op0, 0), op1)
5488 || rtx_equal_p (XEXP (op0, 1), op1))
5489 && ! side_effects_p (XEXP (op0, 0))
5490 && ! side_effects_p (XEXP (op0, 1)))
5491 return op1;
5492
5493 /* In the following group of tests (and those in case IOR below),
5494 we start with some combination of logical operations and apply
5495 the distributive law followed by the inverse distributive law.
5496 Most of the time, this results in no change. However, if some of
5497 the operands are the same or inverses of each other, simplifications
5498 will result.
5499
5500 For example, (and (ior A B) (not B)) can occur as the result of
5501 expanding a bit field assignment. When we apply the distributive
5502 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5503 which then simplifies to (and (A (not B))).
5504
5505 If we have (and (ior A B) C), apply the distributive law and then
5506 the inverse distributive law to see if things simplify. */
5507
5508 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5509 {
5510 x = apply_distributive_law
5511 (gen_binary (GET_CODE (op0), mode,
5512 gen_binary (AND, mode, XEXP (op0, 0), op1),
5513 gen_binary (AND, mode, XEXP (op0, 1),
5514 copy_rtx (op1))));
5515 if (GET_CODE (x) != AND)
5516 return x;
5517 }
5518
5519 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5520 return apply_distributive_law
5521 (gen_binary (GET_CODE (op1), mode,
5522 gen_binary (AND, mode, XEXP (op1, 0), op0),
5523 gen_binary (AND, mode, XEXP (op1, 1),
5524 copy_rtx (op0))));
5525
5526 /* Similarly, taking advantage of the fact that
5527 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5528
5529 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5530 return apply_distributive_law
5531 (gen_binary (XOR, mode,
5532 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5533 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5534 XEXP (op1, 1))));
5535
5536 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5537 return apply_distributive_law
5538 (gen_binary (XOR, mode,
5539 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5540 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5541 break;
5542
5543 case IOR:
5544 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5545 if (GET_CODE (op1) == CONST_INT
5546 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5547 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5548 return op1;
5549
5550 /* Convert (A & B) | A to A. */
5551 if (GET_CODE (op0) == AND
5552 && (rtx_equal_p (XEXP (op0, 0), op1)
5553 || rtx_equal_p (XEXP (op0, 1), op1))
5554 && ! side_effects_p (XEXP (op0, 0))
5555 && ! side_effects_p (XEXP (op0, 1)))
5556 return op1;
5557
5558 /* If we have (ior (and A B) C), apply the distributive law and then
5559 the inverse distributive law to see if things simplify. */
5560
5561 if (GET_CODE (op0) == AND)
5562 {
5563 x = apply_distributive_law
5564 (gen_binary (AND, mode,
5565 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5566 gen_binary (IOR, mode, XEXP (op0, 1),
5567 copy_rtx (op1))));
5568
5569 if (GET_CODE (x) != IOR)
5570 return x;
5571 }
5572
5573 if (GET_CODE (op1) == AND)
5574 {
5575 x = apply_distributive_law
5576 (gen_binary (AND, mode,
5577 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5578 gen_binary (IOR, mode, XEXP (op1, 1),
5579 copy_rtx (op0))));
5580
5581 if (GET_CODE (x) != IOR)
5582 return x;
5583 }
5584
5585 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5586 mode size to (rotate A CX). */
5587
5588 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5589 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5590 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5591 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5592 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5593 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5594 == GET_MODE_BITSIZE (mode)))
5595 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5596 (GET_CODE (op0) == ASHIFT
5597 ? XEXP (op0, 1) : XEXP (op1, 1)));
5598
5599 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5600 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5601 does not affect any of the bits in OP1, it can really be done
5602 as a PLUS and we can associate. We do this by seeing if OP1
5603 can be safely shifted left C bits. */
5604 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5605 && GET_CODE (XEXP (op0, 0)) == PLUS
5606 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5607 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5608 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5609 {
5610 int count = INTVAL (XEXP (op0, 1));
5611 HOST_WIDE_INT mask = INTVAL (op1) << count;
5612
5613 if (mask >> count == INTVAL (op1)
5614 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5615 {
5616 SUBST (XEXP (XEXP (op0, 0), 1),
5617 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5618 return op0;
5619 }
5620 }
5621 break;
5622
5623 case XOR:
5624 /* If we are XORing two things that have no bits in common,
5625 convert them into an IOR. This helps to detect rotation encoded
5626 using those methods and possibly other simplifications. */
5627
5628 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5629 && (nonzero_bits (op0, mode)
5630 & nonzero_bits (op1, mode)) == 0)
5631 return (gen_binary (IOR, mode, op0, op1));
5632
5633 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5634 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5635 (NOT y). */
5636 {
5637 int num_negated = 0;
5638
5639 if (GET_CODE (op0) == NOT)
5640 num_negated++, op0 = XEXP (op0, 0);
5641 if (GET_CODE (op1) == NOT)
5642 num_negated++, op1 = XEXP (op1, 0);
5643
5644 if (num_negated == 2)
5645 {
5646 SUBST (XEXP (x, 0), op0);
5647 SUBST (XEXP (x, 1), op1);
5648 }
5649 else if (num_negated == 1)
5650 return
5651 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5652 mode);
5653 }
5654
5655 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5656 correspond to a machine insn or result in further simplifications
5657 if B is a constant. */
5658
5659 if (GET_CODE (op0) == AND
5660 && rtx_equal_p (XEXP (op0, 1), op1)
5661 && ! side_effects_p (op1))
5662 return gen_binary (AND, mode,
5663 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5664 op1);
5665
5666 else if (GET_CODE (op0) == AND
5667 && rtx_equal_p (XEXP (op0, 0), op1)
5668 && ! side_effects_p (op1))
5669 return gen_binary (AND, mode,
5670 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5671 op1);
5672
5673 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5674 comparison if STORE_FLAG_VALUE is 1. */
5675 if (STORE_FLAG_VALUE == 1
5676 && op1 == const1_rtx
5677 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5678 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5679 XEXP (op0, 1))))
5680 return reversed;
5681
5682 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5683 is (lt foo (const_int 0)), so we can perform the above
5684 simplification if STORE_FLAG_VALUE is 1. */
5685
5686 if (STORE_FLAG_VALUE == 1
5687 && op1 == const1_rtx
5688 && GET_CODE (op0) == LSHIFTRT
5689 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5690 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5691 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5692
5693 /* (xor (comparison foo bar) (const_int sign-bit))
5694 when STORE_FLAG_VALUE is the sign bit. */
5695 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5696 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5697 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5698 && op1 == const_true_rtx
5699 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5700 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5701 XEXP (op0, 1))))
5702 return reversed;
5703
5704 break;
5705
5706 default:
5707 abort ();
5708 }
5709
5710 return x;
5711 }
5712 \f
5713 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5714 operations" because they can be replaced with two more basic operations.
5715 ZERO_EXTEND is also considered "compound" because it can be replaced with
5716 an AND operation, which is simpler, though only one operation.
5717
5718 The function expand_compound_operation is called with an rtx expression
5719 and will convert it to the appropriate shifts and AND operations,
5720 simplifying at each stage.
5721
5722 The function make_compound_operation is called to convert an expression
5723 consisting of shifts and ANDs into the equivalent compound expression.
5724 It is the inverse of this function, loosely speaking. */
5725
5726 static rtx
5727 expand_compound_operation (x)
5728 rtx x;
5729 {
5730 unsigned HOST_WIDE_INT pos = 0, len;
5731 int unsignedp = 0;
5732 unsigned int modewidth;
5733 rtx tem;
5734
5735 switch (GET_CODE (x))
5736 {
5737 case ZERO_EXTEND:
5738 unsignedp = 1;
5739 case SIGN_EXTEND:
5740 /* We can't necessarily use a const_int for a multiword mode;
5741 it depends on implicitly extending the value.
5742 Since we don't know the right way to extend it,
5743 we can't tell whether the implicit way is right.
5744
5745 Even for a mode that is no wider than a const_int,
5746 we can't win, because we need to sign extend one of its bits through
5747 the rest of it, and we don't know which bit. */
5748 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5749 return x;
5750
5751 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5752 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5753 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5754 reloaded. If not for that, MEM's would very rarely be safe.
5755
5756 Reject MODEs bigger than a word, because we might not be able
5757 to reference a two-register group starting with an arbitrary register
5758 (and currently gen_lowpart might crash for a SUBREG). */
5759
5760 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5761 return x;
5762
5763 /* Reject MODEs that aren't scalar integers because turning vector
5764 or complex modes into shifts causes problems. */
5765
5766 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5767 return x;
5768
5769 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5770 /* If the inner object has VOIDmode (the only way this can happen
5771 is if it is an ASM_OPERANDS), we can't do anything since we don't
5772 know how much masking to do. */
5773 if (len == 0)
5774 return x;
5775
5776 break;
5777
5778 case ZERO_EXTRACT:
5779 unsignedp = 1;
5780 case SIGN_EXTRACT:
5781 /* If the operand is a CLOBBER, just return it. */
5782 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5783 return XEXP (x, 0);
5784
5785 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5786 || GET_CODE (XEXP (x, 2)) != CONST_INT
5787 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5788 return x;
5789
5790 /* Reject MODEs that aren't scalar integers because turning vector
5791 or complex modes into shifts causes problems. */
5792
5793 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5794 return x;
5795
5796 len = INTVAL (XEXP (x, 1));
5797 pos = INTVAL (XEXP (x, 2));
5798
5799 /* If this goes outside the object being extracted, replace the object
5800 with a (use (mem ...)) construct that only combine understands
5801 and is used only for this purpose. */
5802 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5803 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5804
5805 if (BITS_BIG_ENDIAN)
5806 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5807
5808 break;
5809
5810 default:
5811 return x;
5812 }
5813 /* Convert sign extension to zero extension, if we know that the high
5814 bit is not set, as this is easier to optimize. It will be converted
5815 back to cheaper alternative in make_extraction. */
5816 if (GET_CODE (x) == SIGN_EXTEND
5817 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5818 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5819 & ~(((unsigned HOST_WIDE_INT)
5820 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5821 >> 1))
5822 == 0)))
5823 {
5824 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5825 return expand_compound_operation (temp);
5826 }
5827
5828 /* We can optimize some special cases of ZERO_EXTEND. */
5829 if (GET_CODE (x) == ZERO_EXTEND)
5830 {
5831 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5832 know that the last value didn't have any inappropriate bits
5833 set. */
5834 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5835 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5836 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5837 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5838 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5839 return XEXP (XEXP (x, 0), 0);
5840
5841 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5842 if (GET_CODE (XEXP (x, 0)) == SUBREG
5843 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5844 && subreg_lowpart_p (XEXP (x, 0))
5845 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5846 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5847 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5848 return SUBREG_REG (XEXP (x, 0));
5849
5850 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5851 is a comparison and STORE_FLAG_VALUE permits. This is like
5852 the first case, but it works even when GET_MODE (x) is larger
5853 than HOST_WIDE_INT. */
5854 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5855 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5856 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5857 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5858 <= HOST_BITS_PER_WIDE_INT)
5859 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5860 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5861 return XEXP (XEXP (x, 0), 0);
5862
5863 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5864 if (GET_CODE (XEXP (x, 0)) == SUBREG
5865 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5866 && subreg_lowpart_p (XEXP (x, 0))
5867 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5868 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5869 <= HOST_BITS_PER_WIDE_INT)
5870 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5871 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5872 return SUBREG_REG (XEXP (x, 0));
5873
5874 }
5875
5876 /* If we reach here, we want to return a pair of shifts. The inner
5877 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5878 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5879 logical depending on the value of UNSIGNEDP.
5880
5881 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5882 converted into an AND of a shift.
5883
5884 We must check for the case where the left shift would have a negative
5885 count. This can happen in a case like (x >> 31) & 255 on machines
5886 that can't shift by a constant. On those machines, we would first
5887 combine the shift with the AND to produce a variable-position
5888 extraction. Then the constant of 31 would be substituted in to produce
5889 a such a position. */
5890
5891 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5892 if (modewidth + len >= pos)
5893 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5894 GET_MODE (x),
5895 simplify_shift_const (NULL_RTX, ASHIFT,
5896 GET_MODE (x),
5897 XEXP (x, 0),
5898 modewidth - pos - len),
5899 modewidth - len);
5900
5901 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5902 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5903 simplify_shift_const (NULL_RTX, LSHIFTRT,
5904 GET_MODE (x),
5905 XEXP (x, 0), pos),
5906 ((HOST_WIDE_INT) 1 << len) - 1);
5907 else
5908 /* Any other cases we can't handle. */
5909 return x;
5910
5911 /* If we couldn't do this for some reason, return the original
5912 expression. */
5913 if (GET_CODE (tem) == CLOBBER)
5914 return x;
5915
5916 return tem;
5917 }
5918 \f
5919 /* X is a SET which contains an assignment of one object into
5920 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5921 or certain SUBREGS). If possible, convert it into a series of
5922 logical operations.
5923
5924 We half-heartedly support variable positions, but do not at all
5925 support variable lengths. */
5926
5927 static rtx
5928 expand_field_assignment (x)
5929 rtx x;
5930 {
5931 rtx inner;
5932 rtx pos; /* Always counts from low bit. */
5933 int len;
5934 rtx mask;
5935 enum machine_mode compute_mode;
5936
5937 /* Loop until we find something we can't simplify. */
5938 while (1)
5939 {
5940 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5941 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5942 {
5943 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5944 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5945 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5946 }
5947 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5948 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5949 {
5950 inner = XEXP (SET_DEST (x), 0);
5951 len = INTVAL (XEXP (SET_DEST (x), 1));
5952 pos = XEXP (SET_DEST (x), 2);
5953
5954 /* If the position is constant and spans the width of INNER,
5955 surround INNER with a USE to indicate this. */
5956 if (GET_CODE (pos) == CONST_INT
5957 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5958 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5959
5960 if (BITS_BIG_ENDIAN)
5961 {
5962 if (GET_CODE (pos) == CONST_INT)
5963 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5964 - INTVAL (pos));
5965 else if (GET_CODE (pos) == MINUS
5966 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5967 && (INTVAL (XEXP (pos, 1))
5968 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5969 /* If position is ADJUST - X, new position is X. */
5970 pos = XEXP (pos, 0);
5971 else
5972 pos = gen_binary (MINUS, GET_MODE (pos),
5973 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5974 - len),
5975 pos);
5976 }
5977 }
5978
5979 /* A SUBREG between two modes that occupy the same numbers of words
5980 can be done by moving the SUBREG to the source. */
5981 else if (GET_CODE (SET_DEST (x)) == SUBREG
5982 /* We need SUBREGs to compute nonzero_bits properly. */
5983 && nonzero_sign_valid
5984 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5985 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5986 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5987 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5988 {
5989 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5990 gen_lowpart_for_combine
5991 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5992 SET_SRC (x)));
5993 continue;
5994 }
5995 else
5996 break;
5997
5998 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5999 inner = SUBREG_REG (inner);
6000
6001 compute_mode = GET_MODE (inner);
6002
6003 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6004 if (! SCALAR_INT_MODE_P (compute_mode))
6005 {
6006 enum machine_mode imode;
6007
6008 /* Don't do anything for vector or complex integral types. */
6009 if (! FLOAT_MODE_P (compute_mode))
6010 break;
6011
6012 /* Try to find an integral mode to pun with. */
6013 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6014 if (imode == BLKmode)
6015 break;
6016
6017 compute_mode = imode;
6018 inner = gen_lowpart_for_combine (imode, inner);
6019 }
6020
6021 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6022 if (len < HOST_BITS_PER_WIDE_INT)
6023 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6024 else
6025 break;
6026
6027 /* Now compute the equivalent expression. Make a copy of INNER
6028 for the SET_DEST in case it is a MEM into which we will substitute;
6029 we don't want shared RTL in that case. */
6030 x = gen_rtx_SET
6031 (VOIDmode, copy_rtx (inner),
6032 gen_binary (IOR, compute_mode,
6033 gen_binary (AND, compute_mode,
6034 simplify_gen_unary (NOT, compute_mode,
6035 gen_binary (ASHIFT,
6036 compute_mode,
6037 mask, pos),
6038 compute_mode),
6039 inner),
6040 gen_binary (ASHIFT, compute_mode,
6041 gen_binary (AND, compute_mode,
6042 gen_lowpart_for_combine
6043 (compute_mode, SET_SRC (x)),
6044 mask),
6045 pos)));
6046 }
6047
6048 return x;
6049 }
6050 \f
6051 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6052 it is an RTX that represents a variable starting position; otherwise,
6053 POS is the (constant) starting bit position (counted from the LSB).
6054
6055 INNER may be a USE. This will occur when we started with a bitfield
6056 that went outside the boundary of the object in memory, which is
6057 allowed on most machines. To isolate this case, we produce a USE
6058 whose mode is wide enough and surround the MEM with it. The only
6059 code that understands the USE is this routine. If it is not removed,
6060 it will cause the resulting insn not to match.
6061
6062 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6063 signed reference.
6064
6065 IN_DEST is nonzero if this is a reference in the destination of a
6066 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6067 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6068 be used.
6069
6070 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6071 ZERO_EXTRACT should be built even for bits starting at bit 0.
6072
6073 MODE is the desired mode of the result (if IN_DEST == 0).
6074
6075 The result is an RTX for the extraction or NULL_RTX if the target
6076 can't handle it. */
6077
6078 static rtx
6079 make_extraction (mode, inner, pos, pos_rtx, len,
6080 unsignedp, in_dest, in_compare)
6081 enum machine_mode mode;
6082 rtx inner;
6083 HOST_WIDE_INT pos;
6084 rtx pos_rtx;
6085 unsigned HOST_WIDE_INT len;
6086 int unsignedp;
6087 int in_dest, in_compare;
6088 {
6089 /* This mode describes the size of the storage area
6090 to fetch the overall value from. Within that, we
6091 ignore the POS lowest bits, etc. */
6092 enum machine_mode is_mode = GET_MODE (inner);
6093 enum machine_mode inner_mode;
6094 enum machine_mode wanted_inner_mode = byte_mode;
6095 enum machine_mode wanted_inner_reg_mode = word_mode;
6096 enum machine_mode pos_mode = word_mode;
6097 enum machine_mode extraction_mode = word_mode;
6098 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6099 int spans_byte = 0;
6100 rtx new = 0;
6101 rtx orig_pos_rtx = pos_rtx;
6102 HOST_WIDE_INT orig_pos;
6103
6104 /* Get some information about INNER and get the innermost object. */
6105 if (GET_CODE (inner) == USE)
6106 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6107 /* We don't need to adjust the position because we set up the USE
6108 to pretend that it was a full-word object. */
6109 spans_byte = 1, inner = XEXP (inner, 0);
6110 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6111 {
6112 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6113 consider just the QI as the memory to extract from.
6114 The subreg adds or removes high bits; its mode is
6115 irrelevant to the meaning of this extraction,
6116 since POS and LEN count from the lsb. */
6117 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6118 is_mode = GET_MODE (SUBREG_REG (inner));
6119 inner = SUBREG_REG (inner);
6120 }
6121 else if (GET_CODE (inner) == ASHIFT
6122 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6123 && pos_rtx == 0 && pos == 0
6124 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6125 {
6126 /* We're extracting the least significant bits of an rtx
6127 (ashift X (const_int C)), where LEN > C. Extract the
6128 least significant (LEN - C) bits of X, giving an rtx
6129 whose mode is MODE, then shift it left C times. */
6130 new = make_extraction (mode, XEXP (inner, 0),
6131 0, 0, len - INTVAL (XEXP (inner, 1)),
6132 unsignedp, in_dest, in_compare);
6133 if (new != 0)
6134 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6135 }
6136
6137 inner_mode = GET_MODE (inner);
6138
6139 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6140 pos = INTVAL (pos_rtx), pos_rtx = 0;
6141
6142 /* See if this can be done without an extraction. We never can if the
6143 width of the field is not the same as that of some integer mode. For
6144 registers, we can only avoid the extraction if the position is at the
6145 low-order bit and this is either not in the destination or we have the
6146 appropriate STRICT_LOW_PART operation available.
6147
6148 For MEM, we can avoid an extract if the field starts on an appropriate
6149 boundary and we can change the mode of the memory reference. However,
6150 we cannot directly access the MEM if we have a USE and the underlying
6151 MEM is not TMODE. This combination means that MEM was being used in a
6152 context where bits outside its mode were being referenced; that is only
6153 valid in bit-field insns. */
6154
6155 if (tmode != BLKmode
6156 && ! (spans_byte && inner_mode != tmode)
6157 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6158 && GET_CODE (inner) != MEM
6159 && (! in_dest
6160 || (GET_CODE (inner) == REG
6161 && have_insn_for (STRICT_LOW_PART, tmode))))
6162 || (GET_CODE (inner) == MEM && pos_rtx == 0
6163 && (pos
6164 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6165 : BITS_PER_UNIT)) == 0
6166 /* We can't do this if we are widening INNER_MODE (it
6167 may not be aligned, for one thing). */
6168 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6169 && (inner_mode == tmode
6170 || (! mode_dependent_address_p (XEXP (inner, 0))
6171 && ! MEM_VOLATILE_P (inner))))))
6172 {
6173 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6174 field. If the original and current mode are the same, we need not
6175 adjust the offset. Otherwise, we do if bytes big endian.
6176
6177 If INNER is not a MEM, get a piece consisting of just the field
6178 of interest (in this case POS % BITS_PER_WORD must be 0). */
6179
6180 if (GET_CODE (inner) == MEM)
6181 {
6182 HOST_WIDE_INT offset;
6183
6184 /* POS counts from lsb, but make OFFSET count in memory order. */
6185 if (BYTES_BIG_ENDIAN)
6186 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6187 else
6188 offset = pos / BITS_PER_UNIT;
6189
6190 new = adjust_address_nv (inner, tmode, offset);
6191 }
6192 else if (GET_CODE (inner) == REG)
6193 {
6194 /* We can't call gen_lowpart_for_combine here since we always want
6195 a SUBREG and it would sometimes return a new hard register. */
6196 if (tmode != inner_mode)
6197 {
6198 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6199
6200 if (WORDS_BIG_ENDIAN
6201 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6202 final_word = ((GET_MODE_SIZE (inner_mode)
6203 - GET_MODE_SIZE (tmode))
6204 / UNITS_PER_WORD) - final_word;
6205
6206 final_word *= UNITS_PER_WORD;
6207 if (BYTES_BIG_ENDIAN &&
6208 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6209 final_word += (GET_MODE_SIZE (inner_mode)
6210 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6211
6212 /* Avoid creating invalid subregs, for example when
6213 simplifying (x>>32)&255. */
6214 if (final_word >= GET_MODE_SIZE (inner_mode))
6215 return NULL_RTX;
6216
6217 new = gen_rtx_SUBREG (tmode, inner, final_word);
6218 }
6219 else
6220 new = inner;
6221 }
6222 else
6223 new = force_to_mode (inner, tmode,
6224 len >= HOST_BITS_PER_WIDE_INT
6225 ? ~(unsigned HOST_WIDE_INT) 0
6226 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6227 NULL_RTX, 0);
6228
6229 /* If this extraction is going into the destination of a SET,
6230 make a STRICT_LOW_PART unless we made a MEM. */
6231
6232 if (in_dest)
6233 return (GET_CODE (new) == MEM ? new
6234 : (GET_CODE (new) != SUBREG
6235 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6236 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6237
6238 if (mode == tmode)
6239 return new;
6240
6241 if (GET_CODE (new) == CONST_INT)
6242 return gen_int_mode (INTVAL (new), mode);
6243
6244 /* If we know that no extraneous bits are set, and that the high
6245 bit is not set, convert the extraction to the cheaper of
6246 sign and zero extension, that are equivalent in these cases. */
6247 if (flag_expensive_optimizations
6248 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6249 && ((nonzero_bits (new, tmode)
6250 & ~(((unsigned HOST_WIDE_INT)
6251 GET_MODE_MASK (tmode))
6252 >> 1))
6253 == 0)))
6254 {
6255 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6256 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6257
6258 /* Prefer ZERO_EXTENSION, since it gives more information to
6259 backends. */
6260 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6261 return temp;
6262 return temp1;
6263 }
6264
6265 /* Otherwise, sign- or zero-extend unless we already are in the
6266 proper mode. */
6267
6268 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6269 mode, new));
6270 }
6271
6272 /* Unless this is a COMPARE or we have a funny memory reference,
6273 don't do anything with zero-extending field extracts starting at
6274 the low-order bit since they are simple AND operations. */
6275 if (pos_rtx == 0 && pos == 0 && ! in_dest
6276 && ! in_compare && ! spans_byte && unsignedp)
6277 return 0;
6278
6279 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6280 we would be spanning bytes or if the position is not a constant and the
6281 length is not 1. In all other cases, we would only be going outside
6282 our object in cases when an original shift would have been
6283 undefined. */
6284 if (! spans_byte && GET_CODE (inner) == MEM
6285 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6286 || (pos_rtx != 0 && len != 1)))
6287 return 0;
6288
6289 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6290 and the mode for the result. */
6291 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6292 {
6293 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6294 pos_mode = mode_for_extraction (EP_insv, 2);
6295 extraction_mode = mode_for_extraction (EP_insv, 3);
6296 }
6297
6298 if (! in_dest && unsignedp
6299 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6300 {
6301 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6302 pos_mode = mode_for_extraction (EP_extzv, 3);
6303 extraction_mode = mode_for_extraction (EP_extzv, 0);
6304 }
6305
6306 if (! in_dest && ! unsignedp
6307 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6308 {
6309 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6310 pos_mode = mode_for_extraction (EP_extv, 3);
6311 extraction_mode = mode_for_extraction (EP_extv, 0);
6312 }
6313
6314 /* Never narrow an object, since that might not be safe. */
6315
6316 if (mode != VOIDmode
6317 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6318 extraction_mode = mode;
6319
6320 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6321 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6322 pos_mode = GET_MODE (pos_rtx);
6323
6324 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6325 if we have to change the mode of memory and cannot, the desired mode is
6326 EXTRACTION_MODE. */
6327 if (GET_CODE (inner) != MEM)
6328 wanted_inner_mode = wanted_inner_reg_mode;
6329 else if (inner_mode != wanted_inner_mode
6330 && (mode_dependent_address_p (XEXP (inner, 0))
6331 || MEM_VOLATILE_P (inner)))
6332 wanted_inner_mode = extraction_mode;
6333
6334 orig_pos = pos;
6335
6336 if (BITS_BIG_ENDIAN)
6337 {
6338 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6339 BITS_BIG_ENDIAN style. If position is constant, compute new
6340 position. Otherwise, build subtraction.
6341 Note that POS is relative to the mode of the original argument.
6342 If it's a MEM we need to recompute POS relative to that.
6343 However, if we're extracting from (or inserting into) a register,
6344 we want to recompute POS relative to wanted_inner_mode. */
6345 int width = (GET_CODE (inner) == MEM
6346 ? GET_MODE_BITSIZE (is_mode)
6347 : GET_MODE_BITSIZE (wanted_inner_mode));
6348
6349 if (pos_rtx == 0)
6350 pos = width - len - pos;
6351 else
6352 pos_rtx
6353 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6354 /* POS may be less than 0 now, but we check for that below.
6355 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6356 }
6357
6358 /* If INNER has a wider mode, make it smaller. If this is a constant
6359 extract, try to adjust the byte to point to the byte containing
6360 the value. */
6361 if (wanted_inner_mode != VOIDmode
6362 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6363 && ((GET_CODE (inner) == MEM
6364 && (inner_mode == wanted_inner_mode
6365 || (! mode_dependent_address_p (XEXP (inner, 0))
6366 && ! MEM_VOLATILE_P (inner))))))
6367 {
6368 int offset = 0;
6369
6370 /* The computations below will be correct if the machine is big
6371 endian in both bits and bytes or little endian in bits and bytes.
6372 If it is mixed, we must adjust. */
6373
6374 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6375 adjust OFFSET to compensate. */
6376 if (BYTES_BIG_ENDIAN
6377 && ! spans_byte
6378 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6379 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6380
6381 /* If this is a constant position, we can move to the desired byte. */
6382 if (pos_rtx == 0)
6383 {
6384 offset += pos / BITS_PER_UNIT;
6385 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6386 }
6387
6388 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6389 && ! spans_byte
6390 && is_mode != wanted_inner_mode)
6391 offset = (GET_MODE_SIZE (is_mode)
6392 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6393
6394 if (offset != 0 || inner_mode != wanted_inner_mode)
6395 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6396 }
6397
6398 /* If INNER is not memory, we can always get it into the proper mode. If we
6399 are changing its mode, POS must be a constant and smaller than the size
6400 of the new mode. */
6401 else if (GET_CODE (inner) != MEM)
6402 {
6403 if (GET_MODE (inner) != wanted_inner_mode
6404 && (pos_rtx != 0
6405 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6406 return 0;
6407
6408 inner = force_to_mode (inner, wanted_inner_mode,
6409 pos_rtx
6410 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6411 ? ~(unsigned HOST_WIDE_INT) 0
6412 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6413 << orig_pos),
6414 NULL_RTX, 0);
6415 }
6416
6417 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6418 have to zero extend. Otherwise, we can just use a SUBREG. */
6419 if (pos_rtx != 0
6420 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6421 {
6422 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6423
6424 /* If we know that no extraneous bits are set, and that the high
6425 bit is not set, convert extraction to cheaper one - either
6426 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6427 cases. */
6428 if (flag_expensive_optimizations
6429 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6430 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6431 & ~(((unsigned HOST_WIDE_INT)
6432 GET_MODE_MASK (GET_MODE (pos_rtx)))
6433 >> 1))
6434 == 0)))
6435 {
6436 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6437
6438 /* Prefer ZERO_EXTENSION, since it gives more information to
6439 backends. */
6440 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6441 temp = temp1;
6442 }
6443 pos_rtx = temp;
6444 }
6445 else if (pos_rtx != 0
6446 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6447 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6448
6449 /* Make POS_RTX unless we already have it and it is correct. If we don't
6450 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6451 be a CONST_INT. */
6452 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6453 pos_rtx = orig_pos_rtx;
6454
6455 else if (pos_rtx == 0)
6456 pos_rtx = GEN_INT (pos);
6457
6458 /* Make the required operation. See if we can use existing rtx. */
6459 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6460 extraction_mode, inner, GEN_INT (len), pos_rtx);
6461 if (! in_dest)
6462 new = gen_lowpart_for_combine (mode, new);
6463
6464 return new;
6465 }
6466 \f
6467 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6468 with any other operations in X. Return X without that shift if so. */
6469
6470 static rtx
6471 extract_left_shift (x, count)
6472 rtx x;
6473 int count;
6474 {
6475 enum rtx_code code = GET_CODE (x);
6476 enum machine_mode mode = GET_MODE (x);
6477 rtx tem;
6478
6479 switch (code)
6480 {
6481 case ASHIFT:
6482 /* This is the shift itself. If it is wide enough, we will return
6483 either the value being shifted if the shift count is equal to
6484 COUNT or a shift for the difference. */
6485 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6486 && INTVAL (XEXP (x, 1)) >= count)
6487 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6488 INTVAL (XEXP (x, 1)) - count);
6489 break;
6490
6491 case NEG: case NOT:
6492 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6493 return simplify_gen_unary (code, mode, tem, mode);
6494
6495 break;
6496
6497 case PLUS: case IOR: case XOR: case AND:
6498 /* If we can safely shift this constant and we find the inner shift,
6499 make a new operation. */
6500 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6501 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6502 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6503 return gen_binary (code, mode, tem,
6504 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6505
6506 break;
6507
6508 default:
6509 break;
6510 }
6511
6512 return 0;
6513 }
6514 \f
6515 /* Look at the expression rooted at X. Look for expressions
6516 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6517 Form these expressions.
6518
6519 Return the new rtx, usually just X.
6520
6521 Also, for machines like the VAX that don't have logical shift insns,
6522 try to convert logical to arithmetic shift operations in cases where
6523 they are equivalent. This undoes the canonicalizations to logical
6524 shifts done elsewhere.
6525
6526 We try, as much as possible, to re-use rtl expressions to save memory.
6527
6528 IN_CODE says what kind of expression we are processing. Normally, it is
6529 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6530 being kludges), it is MEM. When processing the arguments of a comparison
6531 or a COMPARE against zero, it is COMPARE. */
6532
6533 static rtx
6534 make_compound_operation (x, in_code)
6535 rtx x;
6536 enum rtx_code in_code;
6537 {
6538 enum rtx_code code = GET_CODE (x);
6539 enum machine_mode mode = GET_MODE (x);
6540 int mode_width = GET_MODE_BITSIZE (mode);
6541 rtx rhs, lhs;
6542 enum rtx_code next_code;
6543 int i;
6544 rtx new = 0;
6545 rtx tem;
6546 const char *fmt;
6547
6548 /* Select the code to be used in recursive calls. Once we are inside an
6549 address, we stay there. If we have a comparison, set to COMPARE,
6550 but once inside, go back to our default of SET. */
6551
6552 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6553 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6554 && XEXP (x, 1) == const0_rtx) ? COMPARE
6555 : in_code == COMPARE ? SET : in_code);
6556
6557 /* Process depending on the code of this operation. If NEW is set
6558 nonzero, it will be returned. */
6559
6560 switch (code)
6561 {
6562 case ASHIFT:
6563 /* Convert shifts by constants into multiplications if inside
6564 an address. */
6565 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6566 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6567 && INTVAL (XEXP (x, 1)) >= 0)
6568 {
6569 new = make_compound_operation (XEXP (x, 0), next_code);
6570 new = gen_rtx_MULT (mode, new,
6571 GEN_INT ((HOST_WIDE_INT) 1
6572 << INTVAL (XEXP (x, 1))));
6573 }
6574 break;
6575
6576 case AND:
6577 /* If the second operand is not a constant, we can't do anything
6578 with it. */
6579 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6580 break;
6581
6582 /* If the constant is a power of two minus one and the first operand
6583 is a logical right shift, make an extraction. */
6584 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6585 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6586 {
6587 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6588 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6589 0, in_code == COMPARE);
6590 }
6591
6592 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6593 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6594 && subreg_lowpart_p (XEXP (x, 0))
6595 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6596 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6597 {
6598 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6599 next_code);
6600 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6601 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6602 0, in_code == COMPARE);
6603 }
6604 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6605 else if ((GET_CODE (XEXP (x, 0)) == XOR
6606 || GET_CODE (XEXP (x, 0)) == IOR)
6607 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6608 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6609 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6610 {
6611 /* Apply the distributive law, and then try to make extractions. */
6612 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6613 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6614 XEXP (x, 1)),
6615 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6616 XEXP (x, 1)));
6617 new = make_compound_operation (new, in_code);
6618 }
6619
6620 /* If we are have (and (rotate X C) M) and C is larger than the number
6621 of bits in M, this is an extraction. */
6622
6623 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6624 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6625 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6626 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6627 {
6628 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6629 new = make_extraction (mode, new,
6630 (GET_MODE_BITSIZE (mode)
6631 - INTVAL (XEXP (XEXP (x, 0), 1))),
6632 NULL_RTX, i, 1, 0, in_code == COMPARE);
6633 }
6634
6635 /* On machines without logical shifts, if the operand of the AND is
6636 a logical shift and our mask turns off all the propagated sign
6637 bits, we can replace the logical shift with an arithmetic shift. */
6638 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6639 && !have_insn_for (LSHIFTRT, mode)
6640 && have_insn_for (ASHIFTRT, mode)
6641 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6642 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6643 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6644 && mode_width <= HOST_BITS_PER_WIDE_INT)
6645 {
6646 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6647
6648 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6649 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6650 SUBST (XEXP (x, 0),
6651 gen_rtx_ASHIFTRT (mode,
6652 make_compound_operation
6653 (XEXP (XEXP (x, 0), 0), next_code),
6654 XEXP (XEXP (x, 0), 1)));
6655 }
6656
6657 /* If the constant is one less than a power of two, this might be
6658 representable by an extraction even if no shift is present.
6659 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6660 we are in a COMPARE. */
6661 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6662 new = make_extraction (mode,
6663 make_compound_operation (XEXP (x, 0),
6664 next_code),
6665 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6666
6667 /* If we are in a comparison and this is an AND with a power of two,
6668 convert this into the appropriate bit extract. */
6669 else if (in_code == COMPARE
6670 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6671 new = make_extraction (mode,
6672 make_compound_operation (XEXP (x, 0),
6673 next_code),
6674 i, NULL_RTX, 1, 1, 0, 1);
6675
6676 break;
6677
6678 case LSHIFTRT:
6679 /* If the sign bit is known to be zero, replace this with an
6680 arithmetic shift. */
6681 if (have_insn_for (ASHIFTRT, mode)
6682 && ! have_insn_for (LSHIFTRT, mode)
6683 && mode_width <= HOST_BITS_PER_WIDE_INT
6684 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6685 {
6686 new = gen_rtx_ASHIFTRT (mode,
6687 make_compound_operation (XEXP (x, 0),
6688 next_code),
6689 XEXP (x, 1));
6690 break;
6691 }
6692
6693 /* ... fall through ... */
6694
6695 case ASHIFTRT:
6696 lhs = XEXP (x, 0);
6697 rhs = XEXP (x, 1);
6698
6699 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6700 this is a SIGN_EXTRACT. */
6701 if (GET_CODE (rhs) == CONST_INT
6702 && GET_CODE (lhs) == ASHIFT
6703 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6704 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6705 {
6706 new = make_compound_operation (XEXP (lhs, 0), next_code);
6707 new = make_extraction (mode, new,
6708 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6709 NULL_RTX, mode_width - INTVAL (rhs),
6710 code == LSHIFTRT, 0, in_code == COMPARE);
6711 break;
6712 }
6713
6714 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6715 If so, try to merge the shifts into a SIGN_EXTEND. We could
6716 also do this for some cases of SIGN_EXTRACT, but it doesn't
6717 seem worth the effort; the case checked for occurs on Alpha. */
6718
6719 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6720 && ! (GET_CODE (lhs) == SUBREG
6721 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6722 && GET_CODE (rhs) == CONST_INT
6723 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6724 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6725 new = make_extraction (mode, make_compound_operation (new, next_code),
6726 0, NULL_RTX, mode_width - INTVAL (rhs),
6727 code == LSHIFTRT, 0, in_code == COMPARE);
6728
6729 break;
6730
6731 case SUBREG:
6732 /* Call ourselves recursively on the inner expression. If we are
6733 narrowing the object and it has a different RTL code from
6734 what it originally did, do this SUBREG as a force_to_mode. */
6735
6736 tem = make_compound_operation (SUBREG_REG (x), in_code);
6737 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6738 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6739 && subreg_lowpart_p (x))
6740 {
6741 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6742 NULL_RTX, 0);
6743
6744 /* If we have something other than a SUBREG, we might have
6745 done an expansion, so rerun ourselves. */
6746 if (GET_CODE (newer) != SUBREG)
6747 newer = make_compound_operation (newer, in_code);
6748
6749 return newer;
6750 }
6751
6752 /* If this is a paradoxical subreg, and the new code is a sign or
6753 zero extension, omit the subreg and widen the extension. If it
6754 is a regular subreg, we can still get rid of the subreg by not
6755 widening so much, or in fact removing the extension entirely. */
6756 if ((GET_CODE (tem) == SIGN_EXTEND
6757 || GET_CODE (tem) == ZERO_EXTEND)
6758 && subreg_lowpart_p (x))
6759 {
6760 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6761 || (GET_MODE_SIZE (mode) >
6762 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6763 {
6764 if (! SCALAR_INT_MODE_P (mode))
6765 break;
6766 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6767 }
6768 else
6769 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6770 return tem;
6771 }
6772 break;
6773
6774 default:
6775 break;
6776 }
6777
6778 if (new)
6779 {
6780 x = gen_lowpart_for_combine (mode, new);
6781 code = GET_CODE (x);
6782 }
6783
6784 /* Now recursively process each operand of this operation. */
6785 fmt = GET_RTX_FORMAT (code);
6786 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6787 if (fmt[i] == 'e')
6788 {
6789 new = make_compound_operation (XEXP (x, i), next_code);
6790 SUBST (XEXP (x, i), new);
6791 }
6792
6793 return x;
6794 }
6795 \f
6796 /* Given M see if it is a value that would select a field of bits
6797 within an item, but not the entire word. Return -1 if not.
6798 Otherwise, return the starting position of the field, where 0 is the
6799 low-order bit.
6800
6801 *PLEN is set to the length of the field. */
6802
6803 static int
6804 get_pos_from_mask (m, plen)
6805 unsigned HOST_WIDE_INT m;
6806 unsigned HOST_WIDE_INT *plen;
6807 {
6808 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6809 int pos = exact_log2 (m & -m);
6810 int len;
6811
6812 if (pos < 0)
6813 return -1;
6814
6815 /* Now shift off the low-order zero bits and see if we have a power of
6816 two minus 1. */
6817 len = exact_log2 ((m >> pos) + 1);
6818
6819 if (len <= 0)
6820 return -1;
6821
6822 *plen = len;
6823 return pos;
6824 }
6825 \f
6826 /* See if X can be simplified knowing that we will only refer to it in
6827 MODE and will only refer to those bits that are nonzero in MASK.
6828 If other bits are being computed or if masking operations are done
6829 that select a superset of the bits in MASK, they can sometimes be
6830 ignored.
6831
6832 Return a possibly simplified expression, but always convert X to
6833 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6834
6835 Also, if REG is nonzero and X is a register equal in value to REG,
6836 replace X with REG.
6837
6838 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6839 are all off in X. This is used when X will be complemented, by either
6840 NOT, NEG, or XOR. */
6841
6842 static rtx
6843 force_to_mode (x, mode, mask, reg, just_select)
6844 rtx x;
6845 enum machine_mode mode;
6846 unsigned HOST_WIDE_INT mask;
6847 rtx reg;
6848 int just_select;
6849 {
6850 enum rtx_code code = GET_CODE (x);
6851 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6852 enum machine_mode op_mode;
6853 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6854 rtx op0, op1, temp;
6855
6856 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6857 code below will do the wrong thing since the mode of such an
6858 expression is VOIDmode.
6859
6860 Also do nothing if X is a CLOBBER; this can happen if X was
6861 the return value from a call to gen_lowpart_for_combine. */
6862 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6863 return x;
6864
6865 /* We want to perform the operation is its present mode unless we know
6866 that the operation is valid in MODE, in which case we do the operation
6867 in MODE. */
6868 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6869 && have_insn_for (code, mode))
6870 ? mode : GET_MODE (x));
6871
6872 /* It is not valid to do a right-shift in a narrower mode
6873 than the one it came in with. */
6874 if ((code == LSHIFTRT || code == ASHIFTRT)
6875 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6876 op_mode = GET_MODE (x);
6877
6878 /* Truncate MASK to fit OP_MODE. */
6879 if (op_mode)
6880 mask &= GET_MODE_MASK (op_mode);
6881
6882 /* When we have an arithmetic operation, or a shift whose count we
6883 do not know, we need to assume that all bit the up to the highest-order
6884 bit in MASK will be needed. This is how we form such a mask. */
6885 if (op_mode)
6886 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6887 ? GET_MODE_MASK (op_mode)
6888 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6889 - 1));
6890 else
6891 fuller_mask = ~(HOST_WIDE_INT) 0;
6892
6893 /* Determine what bits of X are guaranteed to be (non)zero. */
6894 nonzero = nonzero_bits (x, mode);
6895
6896 /* If none of the bits in X are needed, return a zero. */
6897 if (! just_select && (nonzero & mask) == 0)
6898 x = const0_rtx;
6899
6900 /* If X is a CONST_INT, return a new one. Do this here since the
6901 test below will fail. */
6902 if (GET_CODE (x) == CONST_INT)
6903 {
6904 if (SCALAR_INT_MODE_P (mode))
6905 return gen_int_mode (INTVAL (x) & mask, mode);
6906 else
6907 {
6908 x = GEN_INT (INTVAL (x) & mask);
6909 return gen_lowpart_common (mode, x);
6910 }
6911 }
6912
6913 /* If X is narrower than MODE and we want all the bits in X's mode, just
6914 get X in the proper mode. */
6915 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6916 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6917 return gen_lowpart_for_combine (mode, x);
6918
6919 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6920 MASK are already known to be zero in X, we need not do anything. */
6921 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6922 return x;
6923
6924 switch (code)
6925 {
6926 case CLOBBER:
6927 /* If X is a (clobber (const_int)), return it since we know we are
6928 generating something that won't match. */
6929 return x;
6930
6931 case USE:
6932 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6933 spanned the boundary of the MEM. If we are now masking so it is
6934 within that boundary, we don't need the USE any more. */
6935 if (! BITS_BIG_ENDIAN
6936 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6937 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6938 break;
6939
6940 case SIGN_EXTEND:
6941 case ZERO_EXTEND:
6942 case ZERO_EXTRACT:
6943 case SIGN_EXTRACT:
6944 x = expand_compound_operation (x);
6945 if (GET_CODE (x) != code)
6946 return force_to_mode (x, mode, mask, reg, next_select);
6947 break;
6948
6949 case REG:
6950 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6951 || rtx_equal_p (reg, get_last_value (x))))
6952 x = reg;
6953 break;
6954
6955 case SUBREG:
6956 if (subreg_lowpart_p (x)
6957 /* We can ignore the effect of this SUBREG if it narrows the mode or
6958 if the constant masks to zero all the bits the mode doesn't
6959 have. */
6960 && ((GET_MODE_SIZE (GET_MODE (x))
6961 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6962 || (0 == (mask
6963 & GET_MODE_MASK (GET_MODE (x))
6964 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6965 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6966 break;
6967
6968 case AND:
6969 /* If this is an AND with a constant, convert it into an AND
6970 whose constant is the AND of that constant with MASK. If it
6971 remains an AND of MASK, delete it since it is redundant. */
6972
6973 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6974 {
6975 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6976 mask & INTVAL (XEXP (x, 1)));
6977
6978 /* If X is still an AND, see if it is an AND with a mask that
6979 is just some low-order bits. If so, and it is MASK, we don't
6980 need it. */
6981
6982 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6983 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6984 == mask))
6985 x = XEXP (x, 0);
6986
6987 /* If it remains an AND, try making another AND with the bits
6988 in the mode mask that aren't in MASK turned on. If the
6989 constant in the AND is wide enough, this might make a
6990 cheaper constant. */
6991
6992 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6993 && GET_MODE_MASK (GET_MODE (x)) != mask
6994 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6995 {
6996 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6997 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6998 int width = GET_MODE_BITSIZE (GET_MODE (x));
6999 rtx y;
7000
7001 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
7002 number, sign extend it. */
7003 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7004 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7005 cval |= (HOST_WIDE_INT) -1 << width;
7006
7007 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7008 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7009 x = y;
7010 }
7011
7012 break;
7013 }
7014
7015 goto binop;
7016
7017 case PLUS:
7018 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7019 low-order bits (as in an alignment operation) and FOO is already
7020 aligned to that boundary, mask C1 to that boundary as well.
7021 This may eliminate that PLUS and, later, the AND. */
7022
7023 {
7024 unsigned int width = GET_MODE_BITSIZE (mode);
7025 unsigned HOST_WIDE_INT smask = mask;
7026
7027 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7028 number, sign extend it. */
7029
7030 if (width < HOST_BITS_PER_WIDE_INT
7031 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7032 smask |= (HOST_WIDE_INT) -1 << width;
7033
7034 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7035 && exact_log2 (- smask) >= 0
7036 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7037 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7038 return force_to_mode (plus_constant (XEXP (x, 0),
7039 (INTVAL (XEXP (x, 1)) & smask)),
7040 mode, smask, reg, next_select);
7041 }
7042
7043 /* ... fall through ... */
7044
7045 case MULT:
7046 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7047 most significant bit in MASK since carries from those bits will
7048 affect the bits we are interested in. */
7049 mask = fuller_mask;
7050 goto binop;
7051
7052 case MINUS:
7053 /* If X is (minus C Y) where C's least set bit is larger than any bit
7054 in the mask, then we may replace with (neg Y). */
7055 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7056 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7057 & -INTVAL (XEXP (x, 0))))
7058 > mask))
7059 {
7060 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7061 GET_MODE (x));
7062 return force_to_mode (x, mode, mask, reg, next_select);
7063 }
7064
7065 /* Similarly, if C contains every bit in the fuller_mask, then we may
7066 replace with (not Y). */
7067 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7068 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7069 == INTVAL (XEXP (x, 0))))
7070 {
7071 x = simplify_gen_unary (NOT, GET_MODE (x),
7072 XEXP (x, 1), GET_MODE (x));
7073 return force_to_mode (x, mode, mask, reg, next_select);
7074 }
7075
7076 mask = fuller_mask;
7077 goto binop;
7078
7079 case IOR:
7080 case XOR:
7081 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7082 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7083 operation which may be a bitfield extraction. Ensure that the
7084 constant we form is not wider than the mode of X. */
7085
7086 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7087 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7088 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7089 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7090 && GET_CODE (XEXP (x, 1)) == CONST_INT
7091 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7092 + floor_log2 (INTVAL (XEXP (x, 1))))
7093 < GET_MODE_BITSIZE (GET_MODE (x)))
7094 && (INTVAL (XEXP (x, 1))
7095 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7096 {
7097 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7098 << INTVAL (XEXP (XEXP (x, 0), 1)));
7099 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7100 XEXP (XEXP (x, 0), 0), temp);
7101 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7102 XEXP (XEXP (x, 0), 1));
7103 return force_to_mode (x, mode, mask, reg, next_select);
7104 }
7105
7106 binop:
7107 /* For most binary operations, just propagate into the operation and
7108 change the mode if we have an operation of that mode. */
7109
7110 op0 = gen_lowpart_for_combine (op_mode,
7111 force_to_mode (XEXP (x, 0), mode, mask,
7112 reg, next_select));
7113 op1 = gen_lowpart_for_combine (op_mode,
7114 force_to_mode (XEXP (x, 1), mode, mask,
7115 reg, next_select));
7116
7117 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7118 x = gen_binary (code, op_mode, op0, op1);
7119 break;
7120
7121 case ASHIFT:
7122 /* For left shifts, do the same, but just for the first operand.
7123 However, we cannot do anything with shifts where we cannot
7124 guarantee that the counts are smaller than the size of the mode
7125 because such a count will have a different meaning in a
7126 wider mode. */
7127
7128 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7129 && INTVAL (XEXP (x, 1)) >= 0
7130 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7131 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7132 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7133 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7134 break;
7135
7136 /* If the shift count is a constant and we can do arithmetic in
7137 the mode of the shift, refine which bits we need. Otherwise, use the
7138 conservative form of the mask. */
7139 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7140 && INTVAL (XEXP (x, 1)) >= 0
7141 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7142 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7143 mask >>= INTVAL (XEXP (x, 1));
7144 else
7145 mask = fuller_mask;
7146
7147 op0 = gen_lowpart_for_combine (op_mode,
7148 force_to_mode (XEXP (x, 0), op_mode,
7149 mask, reg, next_select));
7150
7151 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7152 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7153 break;
7154
7155 case LSHIFTRT:
7156 /* Here we can only do something if the shift count is a constant,
7157 this shift constant is valid for the host, and we can do arithmetic
7158 in OP_MODE. */
7159
7160 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7161 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7162 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7163 {
7164 rtx inner = XEXP (x, 0);
7165 unsigned HOST_WIDE_INT inner_mask;
7166
7167 /* Select the mask of the bits we need for the shift operand. */
7168 inner_mask = mask << INTVAL (XEXP (x, 1));
7169
7170 /* We can only change the mode of the shift if we can do arithmetic
7171 in the mode of the shift and INNER_MASK is no wider than the
7172 width of OP_MODE. */
7173 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7174 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7175 op_mode = GET_MODE (x);
7176
7177 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7178
7179 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7180 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7181 }
7182
7183 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7184 shift and AND produces only copies of the sign bit (C2 is one less
7185 than a power of two), we can do this with just a shift. */
7186
7187 if (GET_CODE (x) == LSHIFTRT
7188 && GET_CODE (XEXP (x, 1)) == CONST_INT
7189 /* The shift puts one of the sign bit copies in the least significant
7190 bit. */
7191 && ((INTVAL (XEXP (x, 1))
7192 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7193 >= GET_MODE_BITSIZE (GET_MODE (x)))
7194 && exact_log2 (mask + 1) >= 0
7195 /* Number of bits left after the shift must be more than the mask
7196 needs. */
7197 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7198 <= GET_MODE_BITSIZE (GET_MODE (x)))
7199 /* Must be more sign bit copies than the mask needs. */
7200 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7201 >= exact_log2 (mask + 1)))
7202 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7203 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7204 - exact_log2 (mask + 1)));
7205
7206 goto shiftrt;
7207
7208 case ASHIFTRT:
7209 /* If we are just looking for the sign bit, we don't need this shift at
7210 all, even if it has a variable count. */
7211 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7212 && (mask == ((unsigned HOST_WIDE_INT) 1
7213 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7214 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7215
7216 /* If this is a shift by a constant, get a mask that contains those bits
7217 that are not copies of the sign bit. We then have two cases: If
7218 MASK only includes those bits, this can be a logical shift, which may
7219 allow simplifications. If MASK is a single-bit field not within
7220 those bits, we are requesting a copy of the sign bit and hence can
7221 shift the sign bit to the appropriate location. */
7222
7223 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7224 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7225 {
7226 int i = -1;
7227
7228 /* If the considered data is wider than HOST_WIDE_INT, we can't
7229 represent a mask for all its bits in a single scalar.
7230 But we only care about the lower bits, so calculate these. */
7231
7232 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7233 {
7234 nonzero = ~(HOST_WIDE_INT) 0;
7235
7236 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7237 is the number of bits a full-width mask would have set.
7238 We need only shift if these are fewer than nonzero can
7239 hold. If not, we must keep all bits set in nonzero. */
7240
7241 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7242 < HOST_BITS_PER_WIDE_INT)
7243 nonzero >>= INTVAL (XEXP (x, 1))
7244 + HOST_BITS_PER_WIDE_INT
7245 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7246 }
7247 else
7248 {
7249 nonzero = GET_MODE_MASK (GET_MODE (x));
7250 nonzero >>= INTVAL (XEXP (x, 1));
7251 }
7252
7253 if ((mask & ~nonzero) == 0
7254 || (i = exact_log2 (mask)) >= 0)
7255 {
7256 x = simplify_shift_const
7257 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7258 i < 0 ? INTVAL (XEXP (x, 1))
7259 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7260
7261 if (GET_CODE (x) != ASHIFTRT)
7262 return force_to_mode (x, mode, mask, reg, next_select);
7263 }
7264 }
7265
7266 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7267 even if the shift count isn't a constant. */
7268 if (mask == 1)
7269 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7270
7271 shiftrt:
7272
7273 /* If this is a zero- or sign-extension operation that just affects bits
7274 we don't care about, remove it. Be sure the call above returned
7275 something that is still a shift. */
7276
7277 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7278 && GET_CODE (XEXP (x, 1)) == CONST_INT
7279 && INTVAL (XEXP (x, 1)) >= 0
7280 && (INTVAL (XEXP (x, 1))
7281 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7282 && GET_CODE (XEXP (x, 0)) == ASHIFT
7283 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7284 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7285 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7286 reg, next_select);
7287
7288 break;
7289
7290 case ROTATE:
7291 case ROTATERT:
7292 /* If the shift count is constant and we can do computations
7293 in the mode of X, compute where the bits we care about are.
7294 Otherwise, we can't do anything. Don't change the mode of
7295 the shift or propagate MODE into the shift, though. */
7296 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7297 && INTVAL (XEXP (x, 1)) >= 0)
7298 {
7299 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7300 GET_MODE (x), GEN_INT (mask),
7301 XEXP (x, 1));
7302 if (temp && GET_CODE (temp) == CONST_INT)
7303 SUBST (XEXP (x, 0),
7304 force_to_mode (XEXP (x, 0), GET_MODE (x),
7305 INTVAL (temp), reg, next_select));
7306 }
7307 break;
7308
7309 case NEG:
7310 /* If we just want the low-order bit, the NEG isn't needed since it
7311 won't change the low-order bit. */
7312 if (mask == 1)
7313 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7314
7315 /* We need any bits less significant than the most significant bit in
7316 MASK since carries from those bits will affect the bits we are
7317 interested in. */
7318 mask = fuller_mask;
7319 goto unop;
7320
7321 case NOT:
7322 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7323 same as the XOR case above. Ensure that the constant we form is not
7324 wider than the mode of X. */
7325
7326 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7327 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7328 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7329 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7330 < GET_MODE_BITSIZE (GET_MODE (x)))
7331 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7332 {
7333 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7334 GET_MODE (x));
7335 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7336 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7337
7338 return force_to_mode (x, mode, mask, reg, next_select);
7339 }
7340
7341 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7342 use the full mask inside the NOT. */
7343 mask = fuller_mask;
7344
7345 unop:
7346 op0 = gen_lowpart_for_combine (op_mode,
7347 force_to_mode (XEXP (x, 0), mode, mask,
7348 reg, next_select));
7349 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7350 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7351 break;
7352
7353 case NE:
7354 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7355 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7356 which is equal to STORE_FLAG_VALUE. */
7357 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7358 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7359 && (nonzero_bits (XEXP (x, 0), mode)
7360 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7361 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7362
7363 break;
7364
7365 case IF_THEN_ELSE:
7366 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7367 written in a narrower mode. We play it safe and do not do so. */
7368
7369 SUBST (XEXP (x, 1),
7370 gen_lowpart_for_combine (GET_MODE (x),
7371 force_to_mode (XEXP (x, 1), mode,
7372 mask, reg, next_select)));
7373 SUBST (XEXP (x, 2),
7374 gen_lowpart_for_combine (GET_MODE (x),
7375 force_to_mode (XEXP (x, 2), mode,
7376 mask, reg, next_select)));
7377 break;
7378
7379 default:
7380 break;
7381 }
7382
7383 /* Ensure we return a value of the proper mode. */
7384 return gen_lowpart_for_combine (mode, x);
7385 }
7386 \f
7387 /* Return nonzero if X is an expression that has one of two values depending on
7388 whether some other value is zero or nonzero. In that case, we return the
7389 value that is being tested, *PTRUE is set to the value if the rtx being
7390 returned has a nonzero value, and *PFALSE is set to the other alternative.
7391
7392 If we return zero, we set *PTRUE and *PFALSE to X. */
7393
7394 static rtx
7395 if_then_else_cond (x, ptrue, pfalse)
7396 rtx x;
7397 rtx *ptrue, *pfalse;
7398 {
7399 enum machine_mode mode = GET_MODE (x);
7400 enum rtx_code code = GET_CODE (x);
7401 rtx cond0, cond1, true0, true1, false0, false1;
7402 unsigned HOST_WIDE_INT nz;
7403
7404 /* If we are comparing a value against zero, we are done. */
7405 if ((code == NE || code == EQ)
7406 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7407 {
7408 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7409 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7410 return XEXP (x, 0);
7411 }
7412
7413 /* If this is a unary operation whose operand has one of two values, apply
7414 our opcode to compute those values. */
7415 else if (GET_RTX_CLASS (code) == '1'
7416 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7417 {
7418 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7419 *pfalse = simplify_gen_unary (code, mode, false0,
7420 GET_MODE (XEXP (x, 0)));
7421 return cond0;
7422 }
7423
7424 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7425 make can't possibly match and would suppress other optimizations. */
7426 else if (code == COMPARE)
7427 ;
7428
7429 /* If this is a binary operation, see if either side has only one of two
7430 values. If either one does or if both do and they are conditional on
7431 the same value, compute the new true and false values. */
7432 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7433 || GET_RTX_CLASS (code) == '<')
7434 {
7435 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7436 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7437
7438 if ((cond0 != 0 || cond1 != 0)
7439 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7440 {
7441 /* If if_then_else_cond returned zero, then true/false are the
7442 same rtl. We must copy one of them to prevent invalid rtl
7443 sharing. */
7444 if (cond0 == 0)
7445 true0 = copy_rtx (true0);
7446 else if (cond1 == 0)
7447 true1 = copy_rtx (true1);
7448
7449 *ptrue = gen_binary (code, mode, true0, true1);
7450 *pfalse = gen_binary (code, mode, false0, false1);
7451 return cond0 ? cond0 : cond1;
7452 }
7453
7454 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7455 operands is zero when the other is nonzero, and vice-versa,
7456 and STORE_FLAG_VALUE is 1 or -1. */
7457
7458 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7459 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7460 || code == UMAX)
7461 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7462 {
7463 rtx op0 = XEXP (XEXP (x, 0), 1);
7464 rtx op1 = XEXP (XEXP (x, 1), 1);
7465
7466 cond0 = XEXP (XEXP (x, 0), 0);
7467 cond1 = XEXP (XEXP (x, 1), 0);
7468
7469 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7470 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7471 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7472 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7473 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7474 || ((swap_condition (GET_CODE (cond0))
7475 == combine_reversed_comparison_code (cond1))
7476 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7477 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7478 && ! side_effects_p (x))
7479 {
7480 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7481 *pfalse = gen_binary (MULT, mode,
7482 (code == MINUS
7483 ? simplify_gen_unary (NEG, mode, op1,
7484 mode)
7485 : op1),
7486 const_true_rtx);
7487 return cond0;
7488 }
7489 }
7490
7491 /* Similarly for MULT, AND and UMIN, except that for these the result
7492 is always zero. */
7493 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7494 && (code == MULT || code == AND || code == UMIN)
7495 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7496 {
7497 cond0 = XEXP (XEXP (x, 0), 0);
7498 cond1 = XEXP (XEXP (x, 1), 0);
7499
7500 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7501 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7502 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7503 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7504 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7505 || ((swap_condition (GET_CODE (cond0))
7506 == combine_reversed_comparison_code (cond1))
7507 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7508 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7509 && ! side_effects_p (x))
7510 {
7511 *ptrue = *pfalse = const0_rtx;
7512 return cond0;
7513 }
7514 }
7515 }
7516
7517 else if (code == IF_THEN_ELSE)
7518 {
7519 /* If we have IF_THEN_ELSE already, extract the condition and
7520 canonicalize it if it is NE or EQ. */
7521 cond0 = XEXP (x, 0);
7522 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7523 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7524 return XEXP (cond0, 0);
7525 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7526 {
7527 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7528 return XEXP (cond0, 0);
7529 }
7530 else
7531 return cond0;
7532 }
7533
7534 /* If X is a SUBREG, we can narrow both the true and false values
7535 if the inner expression, if there is a condition. */
7536 else if (code == SUBREG
7537 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7538 &true0, &false0)))
7539 {
7540 *ptrue = simplify_gen_subreg (mode, true0,
7541 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7542 *pfalse = simplify_gen_subreg (mode, false0,
7543 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7544
7545 return cond0;
7546 }
7547
7548 /* If X is a constant, this isn't special and will cause confusions
7549 if we treat it as such. Likewise if it is equivalent to a constant. */
7550 else if (CONSTANT_P (x)
7551 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7552 ;
7553
7554 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7555 will be least confusing to the rest of the compiler. */
7556 else if (mode == BImode)
7557 {
7558 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7559 return x;
7560 }
7561
7562 /* If X is known to be either 0 or -1, those are the true and
7563 false values when testing X. */
7564 else if (x == constm1_rtx || x == const0_rtx
7565 || (mode != VOIDmode
7566 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7567 {
7568 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7569 return x;
7570 }
7571
7572 /* Likewise for 0 or a single bit. */
7573 else if (mode != VOIDmode
7574 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7575 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7576 {
7577 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7578 return x;
7579 }
7580
7581 /* Otherwise fail; show no condition with true and false values the same. */
7582 *ptrue = *pfalse = x;
7583 return 0;
7584 }
7585 \f
7586 /* Return the value of expression X given the fact that condition COND
7587 is known to be true when applied to REG as its first operand and VAL
7588 as its second. X is known to not be shared and so can be modified in
7589 place.
7590
7591 We only handle the simplest cases, and specifically those cases that
7592 arise with IF_THEN_ELSE expressions. */
7593
7594 static rtx
7595 known_cond (x, cond, reg, val)
7596 rtx x;
7597 enum rtx_code cond;
7598 rtx reg, val;
7599 {
7600 enum rtx_code code = GET_CODE (x);
7601 rtx temp;
7602 const char *fmt;
7603 int i, j;
7604
7605 if (side_effects_p (x))
7606 return x;
7607
7608 /* If either operand of the condition is a floating point value,
7609 then we have to avoid collapsing an EQ comparison. */
7610 if (cond == EQ
7611 && rtx_equal_p (x, reg)
7612 && ! FLOAT_MODE_P (GET_MODE (x))
7613 && ! FLOAT_MODE_P (GET_MODE (val)))
7614 return val;
7615
7616 if (cond == UNEQ && rtx_equal_p (x, reg))
7617 return val;
7618
7619 /* If X is (abs REG) and we know something about REG's relationship
7620 with zero, we may be able to simplify this. */
7621
7622 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7623 switch (cond)
7624 {
7625 case GE: case GT: case EQ:
7626 return XEXP (x, 0);
7627 case LT: case LE:
7628 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7629 XEXP (x, 0),
7630 GET_MODE (XEXP (x, 0)));
7631 default:
7632 break;
7633 }
7634
7635 /* The only other cases we handle are MIN, MAX, and comparisons if the
7636 operands are the same as REG and VAL. */
7637
7638 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7639 {
7640 if (rtx_equal_p (XEXP (x, 0), val))
7641 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7642
7643 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7644 {
7645 if (GET_RTX_CLASS (code) == '<')
7646 {
7647 if (comparison_dominates_p (cond, code))
7648 return const_true_rtx;
7649
7650 code = combine_reversed_comparison_code (x);
7651 if (code != UNKNOWN
7652 && comparison_dominates_p (cond, code))
7653 return const0_rtx;
7654 else
7655 return x;
7656 }
7657 else if (code == SMAX || code == SMIN
7658 || code == UMIN || code == UMAX)
7659 {
7660 int unsignedp = (code == UMIN || code == UMAX);
7661
7662 /* Do not reverse the condition when it is NE or EQ.
7663 This is because we cannot conclude anything about
7664 the value of 'SMAX (x, y)' when x is not equal to y,
7665 but we can when x equals y. */
7666 if ((code == SMAX || code == UMAX)
7667 && ! (cond == EQ || cond == NE))
7668 cond = reverse_condition (cond);
7669
7670 switch (cond)
7671 {
7672 case GE: case GT:
7673 return unsignedp ? x : XEXP (x, 1);
7674 case LE: case LT:
7675 return unsignedp ? x : XEXP (x, 0);
7676 case GEU: case GTU:
7677 return unsignedp ? XEXP (x, 1) : x;
7678 case LEU: case LTU:
7679 return unsignedp ? XEXP (x, 0) : x;
7680 default:
7681 break;
7682 }
7683 }
7684 }
7685 }
7686 else if (code == SUBREG)
7687 {
7688 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7689 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7690
7691 if (SUBREG_REG (x) != r)
7692 {
7693 /* We must simplify subreg here, before we lose track of the
7694 original inner_mode. */
7695 new = simplify_subreg (GET_MODE (x), r,
7696 inner_mode, SUBREG_BYTE (x));
7697 if (new)
7698 return new;
7699 else
7700 SUBST (SUBREG_REG (x), r);
7701 }
7702
7703 return x;
7704 }
7705 /* We don't have to handle SIGN_EXTEND here, because even in the
7706 case of replacing something with a modeless CONST_INT, a
7707 CONST_INT is already (supposed to be) a valid sign extension for
7708 its narrower mode, which implies it's already properly
7709 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7710 story is different. */
7711 else if (code == ZERO_EXTEND)
7712 {
7713 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7714 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7715
7716 if (XEXP (x, 0) != r)
7717 {
7718 /* We must simplify the zero_extend here, before we lose
7719 track of the original inner_mode. */
7720 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7721 r, inner_mode);
7722 if (new)
7723 return new;
7724 else
7725 SUBST (XEXP (x, 0), r);
7726 }
7727
7728 return x;
7729 }
7730
7731 fmt = GET_RTX_FORMAT (code);
7732 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7733 {
7734 if (fmt[i] == 'e')
7735 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7736 else if (fmt[i] == 'E')
7737 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7738 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7739 cond, reg, val));
7740 }
7741
7742 return x;
7743 }
7744 \f
7745 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7746 assignment as a field assignment. */
7747
7748 static int
7749 rtx_equal_for_field_assignment_p (x, y)
7750 rtx x;
7751 rtx y;
7752 {
7753 if (x == y || rtx_equal_p (x, y))
7754 return 1;
7755
7756 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7757 return 0;
7758
7759 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7760 Note that all SUBREGs of MEM are paradoxical; otherwise they
7761 would have been rewritten. */
7762 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7763 && GET_CODE (SUBREG_REG (y)) == MEM
7764 && rtx_equal_p (SUBREG_REG (y),
7765 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7766 return 1;
7767
7768 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7769 && GET_CODE (SUBREG_REG (x)) == MEM
7770 && rtx_equal_p (SUBREG_REG (x),
7771 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7772 return 1;
7773
7774 /* We used to see if get_last_value of X and Y were the same but that's
7775 not correct. In one direction, we'll cause the assignment to have
7776 the wrong destination and in the case, we'll import a register into this
7777 insn that might have already have been dead. So fail if none of the
7778 above cases are true. */
7779 return 0;
7780 }
7781 \f
7782 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7783 Return that assignment if so.
7784
7785 We only handle the most common cases. */
7786
7787 static rtx
7788 make_field_assignment (x)
7789 rtx x;
7790 {
7791 rtx dest = SET_DEST (x);
7792 rtx src = SET_SRC (x);
7793 rtx assign;
7794 rtx rhs, lhs;
7795 HOST_WIDE_INT c1;
7796 HOST_WIDE_INT pos;
7797 unsigned HOST_WIDE_INT len;
7798 rtx other;
7799 enum machine_mode mode;
7800
7801 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7802 a clear of a one-bit field. We will have changed it to
7803 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7804 for a SUBREG. */
7805
7806 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7807 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7808 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7809 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7810 {
7811 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7812 1, 1, 1, 0);
7813 if (assign != 0)
7814 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7815 return x;
7816 }
7817
7818 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7819 && subreg_lowpart_p (XEXP (src, 0))
7820 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7821 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7822 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7823 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7824 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7825 {
7826 assign = make_extraction (VOIDmode, dest, 0,
7827 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7828 1, 1, 1, 0);
7829 if (assign != 0)
7830 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7831 return x;
7832 }
7833
7834 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7835 one-bit field. */
7836 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7837 && XEXP (XEXP (src, 0), 0) == const1_rtx
7838 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7839 {
7840 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7841 1, 1, 1, 0);
7842 if (assign != 0)
7843 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7844 return x;
7845 }
7846
7847 /* The other case we handle is assignments into a constant-position
7848 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7849 a mask that has all one bits except for a group of zero bits and
7850 OTHER is known to have zeros where C1 has ones, this is such an
7851 assignment. Compute the position and length from C1. Shift OTHER
7852 to the appropriate position, force it to the required mode, and
7853 make the extraction. Check for the AND in both operands. */
7854
7855 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7856 return x;
7857
7858 rhs = expand_compound_operation (XEXP (src, 0));
7859 lhs = expand_compound_operation (XEXP (src, 1));
7860
7861 if (GET_CODE (rhs) == AND
7862 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7863 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7864 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7865 else if (GET_CODE (lhs) == AND
7866 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7867 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7868 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7869 else
7870 return x;
7871
7872 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7873 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7874 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7875 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7876 return x;
7877
7878 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7879 if (assign == 0)
7880 return x;
7881
7882 /* The mode to use for the source is the mode of the assignment, or of
7883 what is inside a possible STRICT_LOW_PART. */
7884 mode = (GET_CODE (assign) == STRICT_LOW_PART
7885 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7886
7887 /* Shift OTHER right POS places and make it the source, restricting it
7888 to the proper length and mode. */
7889
7890 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7891 GET_MODE (src), other, pos),
7892 mode,
7893 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7894 ? ~(unsigned HOST_WIDE_INT) 0
7895 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7896 dest, 0);
7897
7898 /* If SRC is masked by an AND that does not make a difference in
7899 the value being stored, strip it. */
7900 if (GET_CODE (assign) == ZERO_EXTRACT
7901 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7902 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7903 && GET_CODE (src) == AND
7904 && GET_CODE (XEXP (src, 1)) == CONST_INT
7905 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7906 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7907 src = XEXP (src, 0);
7908
7909 return gen_rtx_SET (VOIDmode, assign, src);
7910 }
7911 \f
7912 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7913 if so. */
7914
7915 static rtx
7916 apply_distributive_law (x)
7917 rtx x;
7918 {
7919 enum rtx_code code = GET_CODE (x);
7920 rtx lhs, rhs, other;
7921 rtx tem;
7922 enum rtx_code inner_code;
7923
7924 /* Distributivity is not true for floating point.
7925 It can change the value. So don't do it.
7926 -- rms and moshier@world.std.com. */
7927 if (FLOAT_MODE_P (GET_MODE (x)))
7928 return x;
7929
7930 /* The outer operation can only be one of the following: */
7931 if (code != IOR && code != AND && code != XOR
7932 && code != PLUS && code != MINUS)
7933 return x;
7934
7935 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7936
7937 /* If either operand is a primitive we can't do anything, so get out
7938 fast. */
7939 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7940 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7941 return x;
7942
7943 lhs = expand_compound_operation (lhs);
7944 rhs = expand_compound_operation (rhs);
7945 inner_code = GET_CODE (lhs);
7946 if (inner_code != GET_CODE (rhs))
7947 return x;
7948
7949 /* See if the inner and outer operations distribute. */
7950 switch (inner_code)
7951 {
7952 case LSHIFTRT:
7953 case ASHIFTRT:
7954 case AND:
7955 case IOR:
7956 /* These all distribute except over PLUS. */
7957 if (code == PLUS || code == MINUS)
7958 return x;
7959 break;
7960
7961 case MULT:
7962 if (code != PLUS && code != MINUS)
7963 return x;
7964 break;
7965
7966 case ASHIFT:
7967 /* This is also a multiply, so it distributes over everything. */
7968 break;
7969
7970 case SUBREG:
7971 /* Non-paradoxical SUBREGs distributes over all operations, provided
7972 the inner modes and byte offsets are the same, this is an extraction
7973 of a low-order part, we don't convert an fp operation to int or
7974 vice versa, and we would not be converting a single-word
7975 operation into a multi-word operation. The latter test is not
7976 required, but it prevents generating unneeded multi-word operations.
7977 Some of the previous tests are redundant given the latter test, but
7978 are retained because they are required for correctness.
7979
7980 We produce the result slightly differently in this case. */
7981
7982 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7983 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7984 || ! subreg_lowpart_p (lhs)
7985 || (GET_MODE_CLASS (GET_MODE (lhs))
7986 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7987 || (GET_MODE_SIZE (GET_MODE (lhs))
7988 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7989 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7990 return x;
7991
7992 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7993 SUBREG_REG (lhs), SUBREG_REG (rhs));
7994 return gen_lowpart_for_combine (GET_MODE (x), tem);
7995
7996 default:
7997 return x;
7998 }
7999
8000 /* Set LHS and RHS to the inner operands (A and B in the example
8001 above) and set OTHER to the common operand (C in the example).
8002 These is only one way to do this unless the inner operation is
8003 commutative. */
8004 if (GET_RTX_CLASS (inner_code) == 'c'
8005 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8006 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8007 else if (GET_RTX_CLASS (inner_code) == 'c'
8008 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8009 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8010 else if (GET_RTX_CLASS (inner_code) == 'c'
8011 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8012 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8013 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8014 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8015 else
8016 return x;
8017
8018 /* Form the new inner operation, seeing if it simplifies first. */
8019 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8020
8021 /* There is one exception to the general way of distributing:
8022 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
8023 if (code == XOR && inner_code == IOR)
8024 {
8025 inner_code = AND;
8026 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8027 }
8028
8029 /* We may be able to continuing distributing the result, so call
8030 ourselves recursively on the inner operation before forming the
8031 outer operation, which we return. */
8032 return gen_binary (inner_code, GET_MODE (x),
8033 apply_distributive_law (tem), other);
8034 }
8035 \f
8036 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8037 in MODE.
8038
8039 Return an equivalent form, if different from X. Otherwise, return X. If
8040 X is zero, we are to always construct the equivalent form. */
8041
8042 static rtx
8043 simplify_and_const_int (x, mode, varop, constop)
8044 rtx x;
8045 enum machine_mode mode;
8046 rtx varop;
8047 unsigned HOST_WIDE_INT constop;
8048 {
8049 unsigned HOST_WIDE_INT nonzero;
8050 int i;
8051
8052 /* Simplify VAROP knowing that we will be only looking at some of the
8053 bits in it.
8054
8055 Note by passing in CONSTOP, we guarantee that the bits not set in
8056 CONSTOP are not significant and will never be examined. We must
8057 ensure that is the case by explicitly masking out those bits
8058 before returning. */
8059 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8060
8061 /* If VAROP is a CLOBBER, we will fail so return it. */
8062 if (GET_CODE (varop) == CLOBBER)
8063 return varop;
8064
8065 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8066 to VAROP and return the new constant. */
8067 if (GET_CODE (varop) == CONST_INT)
8068 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8069
8070 /* See what bits may be nonzero in VAROP. Unlike the general case of
8071 a call to nonzero_bits, here we don't care about bits outside
8072 MODE. */
8073
8074 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8075
8076 /* Turn off all bits in the constant that are known to already be zero.
8077 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8078 which is tested below. */
8079
8080 constop &= nonzero;
8081
8082 /* If we don't have any bits left, return zero. */
8083 if (constop == 0)
8084 return const0_rtx;
8085
8086 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8087 a power of two, we can replace this with an ASHIFT. */
8088 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8089 && (i = exact_log2 (constop)) >= 0)
8090 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8091
8092 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8093 or XOR, then try to apply the distributive law. This may eliminate
8094 operations if either branch can be simplified because of the AND.
8095 It may also make some cases more complex, but those cases probably
8096 won't match a pattern either with or without this. */
8097
8098 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8099 return
8100 gen_lowpart_for_combine
8101 (mode,
8102 apply_distributive_law
8103 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8104 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8105 XEXP (varop, 0), constop),
8106 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8107 XEXP (varop, 1), constop))));
8108
8109 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8110 the AND and see if one of the operands simplifies to zero. If so, we
8111 may eliminate it. */
8112
8113 if (GET_CODE (varop) == PLUS
8114 && exact_log2 (constop + 1) >= 0)
8115 {
8116 rtx o0, o1;
8117
8118 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8119 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8120 if (o0 == const0_rtx)
8121 return o1;
8122 if (o1 == const0_rtx)
8123 return o0;
8124 }
8125
8126 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8127 if we already had one (just check for the simplest cases). */
8128 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8129 && GET_MODE (XEXP (x, 0)) == mode
8130 && SUBREG_REG (XEXP (x, 0)) == varop)
8131 varop = XEXP (x, 0);
8132 else
8133 varop = gen_lowpart_for_combine (mode, varop);
8134
8135 /* If we can't make the SUBREG, try to return what we were given. */
8136 if (GET_CODE (varop) == CLOBBER)
8137 return x ? x : varop;
8138
8139 /* If we are only masking insignificant bits, return VAROP. */
8140 if (constop == nonzero)
8141 x = varop;
8142 else
8143 {
8144 /* Otherwise, return an AND. */
8145 constop = trunc_int_for_mode (constop, mode);
8146 /* See how much, if any, of X we can use. */
8147 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8148 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8149
8150 else
8151 {
8152 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8153 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8154 SUBST (XEXP (x, 1), GEN_INT (constop));
8155
8156 SUBST (XEXP (x, 0), varop);
8157 }
8158 }
8159
8160 return x;
8161 }
8162 \f
8163 #define nonzero_bits_with_known(X, MODE) \
8164 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8165
8166 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8167 It avoids exponential behavior in nonzero_bits1 when X has
8168 identical subexpressions on the first or the second level. */
8169
8170 static unsigned HOST_WIDE_INT
8171 cached_nonzero_bits (x, mode, known_x, known_mode, known_ret)
8172 rtx x;
8173 enum machine_mode mode;
8174 rtx known_x;
8175 enum machine_mode known_mode;
8176 unsigned HOST_WIDE_INT known_ret;
8177 {
8178 if (x == known_x && mode == known_mode)
8179 return known_ret;
8180
8181 /* Try to find identical subexpressions. If found call
8182 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8183 precomputed value for the subexpression as KNOWN_RET. */
8184
8185 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8186 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8187 {
8188 rtx x0 = XEXP (x, 0);
8189 rtx x1 = XEXP (x, 1);
8190
8191 /* Check the first level. */
8192 if (x0 == x1)
8193 return nonzero_bits1 (x, mode, x0, mode,
8194 nonzero_bits_with_known (x0, mode));
8195
8196 /* Check the second level. */
8197 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8198 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8199 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8200 return nonzero_bits1 (x, mode, x1, mode,
8201 nonzero_bits_with_known (x1, mode));
8202
8203 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8204 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8205 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8206 return nonzero_bits1 (x, mode, x0, mode,
8207 nonzero_bits_with_known (x0, mode));
8208 }
8209
8210 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8211 }
8212
8213 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8214 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8215 is less useful. We can't allow both, because that results in exponential
8216 run time recursion. There is a nullstone testcase that triggered
8217 this. This macro avoids accidental uses of num_sign_bit_copies. */
8218 #define cached_num_sign_bit_copies()
8219
8220 /* Given an expression, X, compute which bits in X can be nonzero.
8221 We don't care about bits outside of those defined in MODE.
8222
8223 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8224 a shift, AND, or zero_extract, we can do better. */
8225
8226 static unsigned HOST_WIDE_INT
8227 nonzero_bits1 (x, mode, known_x, known_mode, known_ret)
8228 rtx x;
8229 enum machine_mode mode;
8230 rtx known_x;
8231 enum machine_mode known_mode;
8232 unsigned HOST_WIDE_INT known_ret;
8233 {
8234 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8235 unsigned HOST_WIDE_INT inner_nz;
8236 enum rtx_code code;
8237 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8238 rtx tem;
8239
8240 /* For floating-point values, assume all bits are needed. */
8241 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8242 return nonzero;
8243
8244 /* If X is wider than MODE, use its mode instead. */
8245 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8246 {
8247 mode = GET_MODE (x);
8248 nonzero = GET_MODE_MASK (mode);
8249 mode_width = GET_MODE_BITSIZE (mode);
8250 }
8251
8252 if (mode_width > HOST_BITS_PER_WIDE_INT)
8253 /* Our only callers in this case look for single bit values. So
8254 just return the mode mask. Those tests will then be false. */
8255 return nonzero;
8256
8257 #ifndef WORD_REGISTER_OPERATIONS
8258 /* If MODE is wider than X, but both are a single word for both the host
8259 and target machines, we can compute this from which bits of the
8260 object might be nonzero in its own mode, taking into account the fact
8261 that on many CISC machines, accessing an object in a wider mode
8262 causes the high-order bits to become undefined. So they are
8263 not known to be zero. */
8264
8265 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8266 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8267 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8268 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8269 {
8270 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8271 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8272 return nonzero;
8273 }
8274 #endif
8275
8276 code = GET_CODE (x);
8277 switch (code)
8278 {
8279 case REG:
8280 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8281 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8282 all the bits above ptr_mode are known to be zero. */
8283 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8284 && REG_POINTER (x))
8285 nonzero &= GET_MODE_MASK (ptr_mode);
8286 #endif
8287
8288 /* Include declared information about alignment of pointers. */
8289 /* ??? We don't properly preserve REG_POINTER changes across
8290 pointer-to-integer casts, so we can't trust it except for
8291 things that we know must be pointers. See execute/960116-1.c. */
8292 if ((x == stack_pointer_rtx
8293 || x == frame_pointer_rtx
8294 || x == arg_pointer_rtx)
8295 && REGNO_POINTER_ALIGN (REGNO (x)))
8296 {
8297 unsigned HOST_WIDE_INT alignment
8298 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8299
8300 #ifdef PUSH_ROUNDING
8301 /* If PUSH_ROUNDING is defined, it is possible for the
8302 stack to be momentarily aligned only to that amount,
8303 so we pick the least alignment. */
8304 if (x == stack_pointer_rtx && PUSH_ARGS)
8305 alignment = MIN (PUSH_ROUNDING (1), alignment);
8306 #endif
8307
8308 nonzero &= ~(alignment - 1);
8309 }
8310
8311 /* If X is a register whose nonzero bits value is current, use it.
8312 Otherwise, if X is a register whose value we can find, use that
8313 value. Otherwise, use the previously-computed global nonzero bits
8314 for this register. */
8315
8316 if (reg_last_set_value[REGNO (x)] != 0
8317 && (reg_last_set_mode[REGNO (x)] == mode
8318 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8319 && GET_MODE_CLASS (mode) == MODE_INT))
8320 && (reg_last_set_label[REGNO (x)] == label_tick
8321 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8322 && REG_N_SETS (REGNO (x)) == 1
8323 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8324 REGNO (x))))
8325 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8326 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8327
8328 tem = get_last_value (x);
8329
8330 if (tem)
8331 {
8332 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8333 /* If X is narrower than MODE and TEM is a non-negative
8334 constant that would appear negative in the mode of X,
8335 sign-extend it for use in reg_nonzero_bits because some
8336 machines (maybe most) will actually do the sign-extension
8337 and this is the conservative approach.
8338
8339 ??? For 2.5, try to tighten up the MD files in this regard
8340 instead of this kludge. */
8341
8342 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8343 && GET_CODE (tem) == CONST_INT
8344 && INTVAL (tem) > 0
8345 && 0 != (INTVAL (tem)
8346 & ((HOST_WIDE_INT) 1
8347 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8348 tem = GEN_INT (INTVAL (tem)
8349 | ((HOST_WIDE_INT) (-1)
8350 << GET_MODE_BITSIZE (GET_MODE (x))));
8351 #endif
8352 return nonzero_bits_with_known (tem, mode) & nonzero;
8353 }
8354 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8355 {
8356 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8357
8358 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8359 /* We don't know anything about the upper bits. */
8360 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8361 return nonzero & mask;
8362 }
8363 else
8364 return nonzero;
8365
8366 case CONST_INT:
8367 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8368 /* If X is negative in MODE, sign-extend the value. */
8369 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8370 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8371 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8372 #endif
8373
8374 return INTVAL (x);
8375
8376 case MEM:
8377 #ifdef LOAD_EXTEND_OP
8378 /* In many, if not most, RISC machines, reading a byte from memory
8379 zeros the rest of the register. Noticing that fact saves a lot
8380 of extra zero-extends. */
8381 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8382 nonzero &= GET_MODE_MASK (GET_MODE (x));
8383 #endif
8384 break;
8385
8386 case EQ: case NE:
8387 case UNEQ: case LTGT:
8388 case GT: case GTU: case UNGT:
8389 case LT: case LTU: case UNLT:
8390 case GE: case GEU: case UNGE:
8391 case LE: case LEU: case UNLE:
8392 case UNORDERED: case ORDERED:
8393
8394 /* If this produces an integer result, we know which bits are set.
8395 Code here used to clear bits outside the mode of X, but that is
8396 now done above. */
8397
8398 if (GET_MODE_CLASS (mode) == MODE_INT
8399 && mode_width <= HOST_BITS_PER_WIDE_INT)
8400 nonzero = STORE_FLAG_VALUE;
8401 break;
8402
8403 case NEG:
8404 #if 0
8405 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8406 and num_sign_bit_copies. */
8407 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8408 == GET_MODE_BITSIZE (GET_MODE (x)))
8409 nonzero = 1;
8410 #endif
8411
8412 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8413 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8414 break;
8415
8416 case ABS:
8417 #if 0
8418 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8419 and num_sign_bit_copies. */
8420 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8421 == GET_MODE_BITSIZE (GET_MODE (x)))
8422 nonzero = 1;
8423 #endif
8424 break;
8425
8426 case TRUNCATE:
8427 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8428 & GET_MODE_MASK (mode));
8429 break;
8430
8431 case ZERO_EXTEND:
8432 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8433 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8434 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8435 break;
8436
8437 case SIGN_EXTEND:
8438 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8439 Otherwise, show all the bits in the outer mode but not the inner
8440 may be nonzero. */
8441 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8442 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8443 {
8444 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8445 if (inner_nz
8446 & (((HOST_WIDE_INT) 1
8447 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8448 inner_nz |= (GET_MODE_MASK (mode)
8449 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8450 }
8451
8452 nonzero &= inner_nz;
8453 break;
8454
8455 case AND:
8456 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8457 & nonzero_bits_with_known (XEXP (x, 1), mode));
8458 break;
8459
8460 case XOR: case IOR:
8461 case UMIN: case UMAX: case SMIN: case SMAX:
8462 {
8463 unsigned HOST_WIDE_INT nonzero0 =
8464 nonzero_bits_with_known (XEXP (x, 0), mode);
8465
8466 /* Don't call nonzero_bits for the second time if it cannot change
8467 anything. */
8468 if ((nonzero & nonzero0) != nonzero)
8469 nonzero &= (nonzero0
8470 | nonzero_bits_with_known (XEXP (x, 1), mode));
8471 }
8472 break;
8473
8474 case PLUS: case MINUS:
8475 case MULT:
8476 case DIV: case UDIV:
8477 case MOD: case UMOD:
8478 /* We can apply the rules of arithmetic to compute the number of
8479 high- and low-order zero bits of these operations. We start by
8480 computing the width (position of the highest-order nonzero bit)
8481 and the number of low-order zero bits for each value. */
8482 {
8483 unsigned HOST_WIDE_INT nz0 =
8484 nonzero_bits_with_known (XEXP (x, 0), mode);
8485 unsigned HOST_WIDE_INT nz1 =
8486 nonzero_bits_with_known (XEXP (x, 1), mode);
8487 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8488 int width0 = floor_log2 (nz0) + 1;
8489 int width1 = floor_log2 (nz1) + 1;
8490 int low0 = floor_log2 (nz0 & -nz0);
8491 int low1 = floor_log2 (nz1 & -nz1);
8492 HOST_WIDE_INT op0_maybe_minusp
8493 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8494 HOST_WIDE_INT op1_maybe_minusp
8495 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8496 unsigned int result_width = mode_width;
8497 int result_low = 0;
8498
8499 switch (code)
8500 {
8501 case PLUS:
8502 result_width = MAX (width0, width1) + 1;
8503 result_low = MIN (low0, low1);
8504 break;
8505 case MINUS:
8506 result_low = MIN (low0, low1);
8507 break;
8508 case MULT:
8509 result_width = width0 + width1;
8510 result_low = low0 + low1;
8511 break;
8512 case DIV:
8513 if (width1 == 0)
8514 break;
8515 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8516 result_width = width0;
8517 break;
8518 case UDIV:
8519 if (width1 == 0)
8520 break;
8521 result_width = width0;
8522 break;
8523 case MOD:
8524 if (width1 == 0)
8525 break;
8526 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8527 result_width = MIN (width0, width1);
8528 result_low = MIN (low0, low1);
8529 break;
8530 case UMOD:
8531 if (width1 == 0)
8532 break;
8533 result_width = MIN (width0, width1);
8534 result_low = MIN (low0, low1);
8535 break;
8536 default:
8537 abort ();
8538 }
8539
8540 if (result_width < mode_width)
8541 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8542
8543 if (result_low > 0)
8544 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8545
8546 #ifdef POINTERS_EXTEND_UNSIGNED
8547 /* If pointers extend unsigned and this is an addition or subtraction
8548 to a pointer in Pmode, all the bits above ptr_mode are known to be
8549 zero. */
8550 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8551 && (code == PLUS || code == MINUS)
8552 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8553 nonzero &= GET_MODE_MASK (ptr_mode);
8554 #endif
8555 }
8556 break;
8557
8558 case ZERO_EXTRACT:
8559 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8560 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8561 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8562 break;
8563
8564 case SUBREG:
8565 /* If this is a SUBREG formed for a promoted variable that has
8566 been zero-extended, we know that at least the high-order bits
8567 are zero, though others might be too. */
8568
8569 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8570 nonzero = (GET_MODE_MASK (GET_MODE (x))
8571 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8572
8573 /* If the inner mode is a single word for both the host and target
8574 machines, we can compute this from which bits of the inner
8575 object might be nonzero. */
8576 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8577 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8578 <= HOST_BITS_PER_WIDE_INT))
8579 {
8580 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8581
8582 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8583 /* If this is a typical RISC machine, we only have to worry
8584 about the way loads are extended. */
8585 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8586 ? (((nonzero
8587 & (((unsigned HOST_WIDE_INT) 1
8588 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8589 != 0))
8590 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8591 || GET_CODE (SUBREG_REG (x)) != MEM)
8592 #endif
8593 {
8594 /* On many CISC machines, accessing an object in a wider mode
8595 causes the high-order bits to become undefined. So they are
8596 not known to be zero. */
8597 if (GET_MODE_SIZE (GET_MODE (x))
8598 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8599 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8600 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8601 }
8602 }
8603 break;
8604
8605 case ASHIFTRT:
8606 case LSHIFTRT:
8607 case ASHIFT:
8608 case ROTATE:
8609 /* The nonzero bits are in two classes: any bits within MODE
8610 that aren't in GET_MODE (x) are always significant. The rest of the
8611 nonzero bits are those that are significant in the operand of
8612 the shift when shifted the appropriate number of bits. This
8613 shows that high-order bits are cleared by the right shift and
8614 low-order bits by left shifts. */
8615 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8616 && INTVAL (XEXP (x, 1)) >= 0
8617 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8618 {
8619 enum machine_mode inner_mode = GET_MODE (x);
8620 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8621 int count = INTVAL (XEXP (x, 1));
8622 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8623 unsigned HOST_WIDE_INT op_nonzero =
8624 nonzero_bits_with_known (XEXP (x, 0), mode);
8625 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8626 unsigned HOST_WIDE_INT outer = 0;
8627
8628 if (mode_width > width)
8629 outer = (op_nonzero & nonzero & ~mode_mask);
8630
8631 if (code == LSHIFTRT)
8632 inner >>= count;
8633 else if (code == ASHIFTRT)
8634 {
8635 inner >>= count;
8636
8637 /* If the sign bit may have been nonzero before the shift, we
8638 need to mark all the places it could have been copied to
8639 by the shift as possibly nonzero. */
8640 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8641 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8642 }
8643 else if (code == ASHIFT)
8644 inner <<= count;
8645 else
8646 inner = ((inner << (count % width)
8647 | (inner >> (width - (count % width)))) & mode_mask);
8648
8649 nonzero &= (outer | inner);
8650 }
8651 break;
8652
8653 case FFS:
8654 case POPCOUNT:
8655 /* This is at most the number of bits in the mode. */
8656 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8657 break;
8658
8659 case CLZ:
8660 /* If CLZ has a known value at zero, then the nonzero bits are
8661 that value, plus the number of bits in the mode minus one. */
8662 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8663 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8664 else
8665 nonzero = -1;
8666 break;
8667
8668 case CTZ:
8669 /* If CTZ has a known value at zero, then the nonzero bits are
8670 that value, plus the number of bits in the mode minus one. */
8671 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8672 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8673 else
8674 nonzero = -1;
8675 break;
8676
8677 case PARITY:
8678 nonzero = 1;
8679 break;
8680
8681 case IF_THEN_ELSE:
8682 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8683 | nonzero_bits_with_known (XEXP (x, 2), mode));
8684 break;
8685
8686 default:
8687 break;
8688 }
8689
8690 return nonzero;
8691 }
8692
8693 /* See the macro definition above. */
8694 #undef cached_num_sign_bit_copies
8695 \f
8696 #define num_sign_bit_copies_with_known(X, M) \
8697 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8698
8699 /* The function cached_num_sign_bit_copies is a wrapper around
8700 num_sign_bit_copies1. It avoids exponential behavior in
8701 num_sign_bit_copies1 when X has identical subexpressions on the
8702 first or the second level. */
8703
8704 static unsigned int
8705 cached_num_sign_bit_copies (x, mode, known_x, known_mode, known_ret)
8706 rtx x;
8707 enum machine_mode mode;
8708 rtx known_x;
8709 enum machine_mode known_mode;
8710 unsigned int known_ret;
8711 {
8712 if (x == known_x && mode == known_mode)
8713 return known_ret;
8714
8715 /* Try to find identical subexpressions. If found call
8716 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8717 the precomputed value for the subexpression as KNOWN_RET. */
8718
8719 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8720 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8721 {
8722 rtx x0 = XEXP (x, 0);
8723 rtx x1 = XEXP (x, 1);
8724
8725 /* Check the first level. */
8726 if (x0 == x1)
8727 return
8728 num_sign_bit_copies1 (x, mode, x0, mode,
8729 num_sign_bit_copies_with_known (x0, mode));
8730
8731 /* Check the second level. */
8732 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8733 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8734 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8735 return
8736 num_sign_bit_copies1 (x, mode, x1, mode,
8737 num_sign_bit_copies_with_known (x1, mode));
8738
8739 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8740 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8741 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8742 return
8743 num_sign_bit_copies1 (x, mode, x0, mode,
8744 num_sign_bit_copies_with_known (x0, mode));
8745 }
8746
8747 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8748 }
8749
8750 /* Return the number of bits at the high-order end of X that are known to
8751 be equal to the sign bit. X will be used in mode MODE; if MODE is
8752 VOIDmode, X will be used in its own mode. The returned value will always
8753 be between 1 and the number of bits in MODE. */
8754
8755 static unsigned int
8756 num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret)
8757 rtx x;
8758 enum machine_mode mode;
8759 rtx known_x;
8760 enum machine_mode known_mode;
8761 unsigned int known_ret;
8762 {
8763 enum rtx_code code = GET_CODE (x);
8764 unsigned int bitwidth;
8765 int num0, num1, result;
8766 unsigned HOST_WIDE_INT nonzero;
8767 rtx tem;
8768
8769 /* If we weren't given a mode, use the mode of X. If the mode is still
8770 VOIDmode, we don't know anything. Likewise if one of the modes is
8771 floating-point. */
8772
8773 if (mode == VOIDmode)
8774 mode = GET_MODE (x);
8775
8776 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8777 return 1;
8778
8779 bitwidth = GET_MODE_BITSIZE (mode);
8780
8781 /* For a smaller object, just ignore the high bits. */
8782 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8783 {
8784 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8785 return MAX (1,
8786 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8787 }
8788
8789 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8790 {
8791 #ifndef WORD_REGISTER_OPERATIONS
8792 /* If this machine does not do all register operations on the entire
8793 register and MODE is wider than the mode of X, we can say nothing
8794 at all about the high-order bits. */
8795 return 1;
8796 #else
8797 /* Likewise on machines that do, if the mode of the object is smaller
8798 than a word and loads of that size don't sign extend, we can say
8799 nothing about the high order bits. */
8800 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8801 #ifdef LOAD_EXTEND_OP
8802 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8803 #endif
8804 )
8805 return 1;
8806 #endif
8807 }
8808
8809 switch (code)
8810 {
8811 case REG:
8812
8813 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8814 /* If pointers extend signed and this is a pointer in Pmode, say that
8815 all the bits above ptr_mode are known to be sign bit copies. */
8816 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8817 && REG_POINTER (x))
8818 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8819 #endif
8820
8821 if (reg_last_set_value[REGNO (x)] != 0
8822 && reg_last_set_mode[REGNO (x)] == mode
8823 && (reg_last_set_label[REGNO (x)] == label_tick
8824 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8825 && REG_N_SETS (REGNO (x)) == 1
8826 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8827 REGNO (x))))
8828 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8829 return reg_last_set_sign_bit_copies[REGNO (x)];
8830
8831 tem = get_last_value (x);
8832 if (tem != 0)
8833 return num_sign_bit_copies_with_known (tem, mode);
8834
8835 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8836 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8837 return reg_sign_bit_copies[REGNO (x)];
8838 break;
8839
8840 case MEM:
8841 #ifdef LOAD_EXTEND_OP
8842 /* Some RISC machines sign-extend all loads of smaller than a word. */
8843 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8844 return MAX (1, ((int) bitwidth
8845 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8846 #endif
8847 break;
8848
8849 case CONST_INT:
8850 /* If the constant is negative, take its 1's complement and remask.
8851 Then see how many zero bits we have. */
8852 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8853 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8854 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8855 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8856
8857 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8858
8859 case SUBREG:
8860 /* If this is a SUBREG for a promoted object that is sign-extended
8861 and we are looking at it in a wider mode, we know that at least the
8862 high-order bits are known to be sign bit copies. */
8863
8864 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8865 {
8866 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8867 return MAX ((int) bitwidth
8868 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8869 num0);
8870 }
8871
8872 /* For a smaller object, just ignore the high bits. */
8873 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8874 {
8875 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8876 return MAX (1, (num0
8877 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8878 - bitwidth)));
8879 }
8880
8881 #ifdef WORD_REGISTER_OPERATIONS
8882 #ifdef LOAD_EXTEND_OP
8883 /* For paradoxical SUBREGs on machines where all register operations
8884 affect the entire register, just look inside. Note that we are
8885 passing MODE to the recursive call, so the number of sign bit copies
8886 will remain relative to that mode, not the inner mode. */
8887
8888 /* This works only if loads sign extend. Otherwise, if we get a
8889 reload for the inner part, it may be loaded from the stack, and
8890 then we lose all sign bit copies that existed before the store
8891 to the stack. */
8892
8893 if ((GET_MODE_SIZE (GET_MODE (x))
8894 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8895 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8896 && GET_CODE (SUBREG_REG (x)) == MEM)
8897 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8898 #endif
8899 #endif
8900 break;
8901
8902 case SIGN_EXTRACT:
8903 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8904 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8905 break;
8906
8907 case SIGN_EXTEND:
8908 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8909 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8910
8911 case TRUNCATE:
8912 /* For a smaller object, just ignore the high bits. */
8913 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8914 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8915 - bitwidth)));
8916
8917 case NOT:
8918 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8919
8920 case ROTATE: case ROTATERT:
8921 /* If we are rotating left by a number of bits less than the number
8922 of sign bit copies, we can just subtract that amount from the
8923 number. */
8924 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8925 && INTVAL (XEXP (x, 1)) >= 0
8926 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8927 {
8928 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8929 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8930 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8931 }
8932 break;
8933
8934 case NEG:
8935 /* In general, this subtracts one sign bit copy. But if the value
8936 is known to be positive, the number of sign bit copies is the
8937 same as that of the input. Finally, if the input has just one bit
8938 that might be nonzero, all the bits are copies of the sign bit. */
8939 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8940 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8941 return num0 > 1 ? num0 - 1 : 1;
8942
8943 nonzero = nonzero_bits (XEXP (x, 0), mode);
8944 if (nonzero == 1)
8945 return bitwidth;
8946
8947 if (num0 > 1
8948 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8949 num0--;
8950
8951 return num0;
8952
8953 case IOR: case AND: case XOR:
8954 case SMIN: case SMAX: case UMIN: case UMAX:
8955 /* Logical operations will preserve the number of sign-bit copies.
8956 MIN and MAX operations always return one of the operands. */
8957 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8958 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8959 return MIN (num0, num1);
8960
8961 case PLUS: case MINUS:
8962 /* For addition and subtraction, we can have a 1-bit carry. However,
8963 if we are subtracting 1 from a positive number, there will not
8964 be such a carry. Furthermore, if the positive number is known to
8965 be 0 or 1, we know the result is either -1 or 0. */
8966
8967 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8968 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8969 {
8970 nonzero = nonzero_bits (XEXP (x, 0), mode);
8971 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8972 return (nonzero == 1 || nonzero == 0 ? bitwidth
8973 : bitwidth - floor_log2 (nonzero) - 1);
8974 }
8975
8976 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8977 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8978 result = MAX (1, MIN (num0, num1) - 1);
8979
8980 #ifdef POINTERS_EXTEND_UNSIGNED
8981 /* If pointers extend signed and this is an addition or subtraction
8982 to a pointer in Pmode, all the bits above ptr_mode are known to be
8983 sign bit copies. */
8984 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8985 && (code == PLUS || code == MINUS)
8986 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8987 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8988 - GET_MODE_BITSIZE (ptr_mode) + 1),
8989 result);
8990 #endif
8991 return result;
8992
8993 case MULT:
8994 /* The number of bits of the product is the sum of the number of
8995 bits of both terms. However, unless one of the terms if known
8996 to be positive, we must allow for an additional bit since negating
8997 a negative number can remove one sign bit copy. */
8998
8999 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9000 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9001
9002 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
9003 if (result > 0
9004 && (bitwidth > HOST_BITS_PER_WIDE_INT
9005 || (((nonzero_bits (XEXP (x, 0), mode)
9006 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9007 && ((nonzero_bits (XEXP (x, 1), mode)
9008 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
9009 result--;
9010
9011 return MAX (1, result);
9012
9013 case UDIV:
9014 /* The result must be <= the first operand. If the first operand
9015 has the high bit set, we know nothing about the number of sign
9016 bit copies. */
9017 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9018 return 1;
9019 else if ((nonzero_bits (XEXP (x, 0), mode)
9020 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9021 return 1;
9022 else
9023 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9024
9025 case UMOD:
9026 /* The result must be <= the second operand. */
9027 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9028
9029 case DIV:
9030 /* Similar to unsigned division, except that we have to worry about
9031 the case where the divisor is negative, in which case we have
9032 to add 1. */
9033 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9034 if (result > 1
9035 && (bitwidth > HOST_BITS_PER_WIDE_INT
9036 || (nonzero_bits (XEXP (x, 1), mode)
9037 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9038 result--;
9039
9040 return result;
9041
9042 case MOD:
9043 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9044 if (result > 1
9045 && (bitwidth > HOST_BITS_PER_WIDE_INT
9046 || (nonzero_bits (XEXP (x, 1), mode)
9047 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9048 result--;
9049
9050 return result;
9051
9052 case ASHIFTRT:
9053 /* Shifts by a constant add to the number of bits equal to the
9054 sign bit. */
9055 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9056 if (GET_CODE (XEXP (x, 1)) == CONST_INT
9057 && INTVAL (XEXP (x, 1)) > 0)
9058 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
9059
9060 return num0;
9061
9062 case ASHIFT:
9063 /* Left shifts destroy copies. */
9064 if (GET_CODE (XEXP (x, 1)) != CONST_INT
9065 || INTVAL (XEXP (x, 1)) < 0
9066 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
9067 return 1;
9068
9069 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9070 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
9071
9072 case IF_THEN_ELSE:
9073 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9074 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
9075 return MIN (num0, num1);
9076
9077 case EQ: case NE: case GE: case GT: case LE: case LT:
9078 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
9079 case GEU: case GTU: case LEU: case LTU:
9080 case UNORDERED: case ORDERED:
9081 /* If the constant is negative, take its 1's complement and remask.
9082 Then see how many zero bits we have. */
9083 nonzero = STORE_FLAG_VALUE;
9084 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9085 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9086 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9087
9088 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9089 break;
9090
9091 default:
9092 break;
9093 }
9094
9095 /* If we haven't been able to figure it out by one of the above rules,
9096 see if some of the high-order bits are known to be zero. If so,
9097 count those bits and return one less than that amount. If we can't
9098 safely compute the mask for this mode, always return BITWIDTH. */
9099
9100 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9101 return 1;
9102
9103 nonzero = nonzero_bits (x, mode);
9104 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9105 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9106 }
9107 \f
9108 /* Return the number of "extended" bits there are in X, when interpreted
9109 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9110 unsigned quantities, this is the number of high-order zero bits.
9111 For signed quantities, this is the number of copies of the sign bit
9112 minus 1. In both case, this function returns the number of "spare"
9113 bits. For example, if two quantities for which this function returns
9114 at least 1 are added, the addition is known not to overflow.
9115
9116 This function will always return 0 unless called during combine, which
9117 implies that it must be called from a define_split. */
9118
9119 unsigned int
9120 extended_count (x, mode, unsignedp)
9121 rtx x;
9122 enum machine_mode mode;
9123 int unsignedp;
9124 {
9125 if (nonzero_sign_valid == 0)
9126 return 0;
9127
9128 return (unsignedp
9129 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9130 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9131 - floor_log2 (nonzero_bits (x, mode)))
9132 : 0)
9133 : num_sign_bit_copies (x, mode) - 1);
9134 }
9135 \f
9136 /* This function is called from `simplify_shift_const' to merge two
9137 outer operations. Specifically, we have already found that we need
9138 to perform operation *POP0 with constant *PCONST0 at the outermost
9139 position. We would now like to also perform OP1 with constant CONST1
9140 (with *POP0 being done last).
9141
9142 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9143 the resulting operation. *PCOMP_P is set to 1 if we would need to
9144 complement the innermost operand, otherwise it is unchanged.
9145
9146 MODE is the mode in which the operation will be done. No bits outside
9147 the width of this mode matter. It is assumed that the width of this mode
9148 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9149
9150 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9151 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9152 result is simply *PCONST0.
9153
9154 If the resulting operation cannot be expressed as one operation, we
9155 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9156
9157 static int
9158 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
9159 enum rtx_code *pop0;
9160 HOST_WIDE_INT *pconst0;
9161 enum rtx_code op1;
9162 HOST_WIDE_INT const1;
9163 enum machine_mode mode;
9164 int *pcomp_p;
9165 {
9166 enum rtx_code op0 = *pop0;
9167 HOST_WIDE_INT const0 = *pconst0;
9168
9169 const0 &= GET_MODE_MASK (mode);
9170 const1 &= GET_MODE_MASK (mode);
9171
9172 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9173 if (op0 == AND)
9174 const1 &= const0;
9175
9176 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9177 if OP0 is SET. */
9178
9179 if (op1 == NIL || op0 == SET)
9180 return 1;
9181
9182 else if (op0 == NIL)
9183 op0 = op1, const0 = const1;
9184
9185 else if (op0 == op1)
9186 {
9187 switch (op0)
9188 {
9189 case AND:
9190 const0 &= const1;
9191 break;
9192 case IOR:
9193 const0 |= const1;
9194 break;
9195 case XOR:
9196 const0 ^= const1;
9197 break;
9198 case PLUS:
9199 const0 += const1;
9200 break;
9201 case NEG:
9202 op0 = NIL;
9203 break;
9204 default:
9205 break;
9206 }
9207 }
9208
9209 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9210 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9211 return 0;
9212
9213 /* If the two constants aren't the same, we can't do anything. The
9214 remaining six cases can all be done. */
9215 else if (const0 != const1)
9216 return 0;
9217
9218 else
9219 switch (op0)
9220 {
9221 case IOR:
9222 if (op1 == AND)
9223 /* (a & b) | b == b */
9224 op0 = SET;
9225 else /* op1 == XOR */
9226 /* (a ^ b) | b == a | b */
9227 {;}
9228 break;
9229
9230 case XOR:
9231 if (op1 == AND)
9232 /* (a & b) ^ b == (~a) & b */
9233 op0 = AND, *pcomp_p = 1;
9234 else /* op1 == IOR */
9235 /* (a | b) ^ b == a & ~b */
9236 op0 = AND, const0 = ~const0;
9237 break;
9238
9239 case AND:
9240 if (op1 == IOR)
9241 /* (a | b) & b == b */
9242 op0 = SET;
9243 else /* op1 == XOR */
9244 /* (a ^ b) & b) == (~a) & b */
9245 *pcomp_p = 1;
9246 break;
9247 default:
9248 break;
9249 }
9250
9251 /* Check for NO-OP cases. */
9252 const0 &= GET_MODE_MASK (mode);
9253 if (const0 == 0
9254 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9255 op0 = NIL;
9256 else if (const0 == 0 && op0 == AND)
9257 op0 = SET;
9258 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9259 && op0 == AND)
9260 op0 = NIL;
9261
9262 /* ??? Slightly redundant with the above mask, but not entirely.
9263 Moving this above means we'd have to sign-extend the mode mask
9264 for the final test. */
9265 const0 = trunc_int_for_mode (const0, mode);
9266
9267 *pop0 = op0;
9268 *pconst0 = const0;
9269
9270 return 1;
9271 }
9272 \f
9273 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9274 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9275 that we started with.
9276
9277 The shift is normally computed in the widest mode we find in VAROP, as
9278 long as it isn't a different number of words than RESULT_MODE. Exceptions
9279 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9280
9281 static rtx
9282 simplify_shift_const (x, code, result_mode, varop, orig_count)
9283 rtx x;
9284 enum rtx_code code;
9285 enum machine_mode result_mode;
9286 rtx varop;
9287 int orig_count;
9288 {
9289 enum rtx_code orig_code = code;
9290 unsigned int count;
9291 int signed_count;
9292 enum machine_mode mode = result_mode;
9293 enum machine_mode shift_mode, tmode;
9294 unsigned int mode_words
9295 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9296 /* We form (outer_op (code varop count) (outer_const)). */
9297 enum rtx_code outer_op = NIL;
9298 HOST_WIDE_INT outer_const = 0;
9299 rtx const_rtx;
9300 int complement_p = 0;
9301 rtx new;
9302
9303 /* Make sure and truncate the "natural" shift on the way in. We don't
9304 want to do this inside the loop as it makes it more difficult to
9305 combine shifts. */
9306 #ifdef SHIFT_COUNT_TRUNCATED
9307 if (SHIFT_COUNT_TRUNCATED)
9308 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9309 #endif
9310
9311 /* If we were given an invalid count, don't do anything except exactly
9312 what was requested. */
9313
9314 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9315 {
9316 if (x)
9317 return x;
9318
9319 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9320 }
9321
9322 count = orig_count;
9323
9324 /* Unless one of the branches of the `if' in this loop does a `continue',
9325 we will `break' the loop after the `if'. */
9326
9327 while (count != 0)
9328 {
9329 /* If we have an operand of (clobber (const_int 0)), just return that
9330 value. */
9331 if (GET_CODE (varop) == CLOBBER)
9332 return varop;
9333
9334 /* If we discovered we had to complement VAROP, leave. Making a NOT
9335 here would cause an infinite loop. */
9336 if (complement_p)
9337 break;
9338
9339 /* Convert ROTATERT to ROTATE. */
9340 if (code == ROTATERT)
9341 {
9342 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9343 code = ROTATE;
9344 if (VECTOR_MODE_P (result_mode))
9345 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9346 else
9347 count = bitsize - count;
9348 }
9349
9350 /* We need to determine what mode we will do the shift in. If the
9351 shift is a right shift or a ROTATE, we must always do it in the mode
9352 it was originally done in. Otherwise, we can do it in MODE, the
9353 widest mode encountered. */
9354 shift_mode
9355 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9356 ? result_mode : mode);
9357
9358 /* Handle cases where the count is greater than the size of the mode
9359 minus 1. For ASHIFT, use the size minus one as the count (this can
9360 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9361 take the count modulo the size. For other shifts, the result is
9362 zero.
9363
9364 Since these shifts are being produced by the compiler by combining
9365 multiple operations, each of which are defined, we know what the
9366 result is supposed to be. */
9367
9368 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9369 {
9370 if (code == ASHIFTRT)
9371 count = GET_MODE_BITSIZE (shift_mode) - 1;
9372 else if (code == ROTATE || code == ROTATERT)
9373 count %= GET_MODE_BITSIZE (shift_mode);
9374 else
9375 {
9376 /* We can't simply return zero because there may be an
9377 outer op. */
9378 varop = const0_rtx;
9379 count = 0;
9380 break;
9381 }
9382 }
9383
9384 /* An arithmetic right shift of a quantity known to be -1 or 0
9385 is a no-op. */
9386 if (code == ASHIFTRT
9387 && (num_sign_bit_copies (varop, shift_mode)
9388 == GET_MODE_BITSIZE (shift_mode)))
9389 {
9390 count = 0;
9391 break;
9392 }
9393
9394 /* If we are doing an arithmetic right shift and discarding all but
9395 the sign bit copies, this is equivalent to doing a shift by the
9396 bitsize minus one. Convert it into that shift because it will often
9397 allow other simplifications. */
9398
9399 if (code == ASHIFTRT
9400 && (count + num_sign_bit_copies (varop, shift_mode)
9401 >= GET_MODE_BITSIZE (shift_mode)))
9402 count = GET_MODE_BITSIZE (shift_mode) - 1;
9403
9404 /* We simplify the tests below and elsewhere by converting
9405 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9406 `make_compound_operation' will convert it to an ASHIFTRT for
9407 those machines (such as VAX) that don't have an LSHIFTRT. */
9408 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9409 && code == ASHIFTRT
9410 && ((nonzero_bits (varop, shift_mode)
9411 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9412 == 0))
9413 code = LSHIFTRT;
9414
9415 if (code == LSHIFTRT
9416 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9417 && !(nonzero_bits (varop, shift_mode) >> count))
9418 varop = const0_rtx;
9419 if (code == ASHIFT
9420 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9421 && !((nonzero_bits (varop, shift_mode) << count)
9422 & GET_MODE_MASK (shift_mode)))
9423 varop = const0_rtx;
9424
9425 switch (GET_CODE (varop))
9426 {
9427 case SIGN_EXTEND:
9428 case ZERO_EXTEND:
9429 case SIGN_EXTRACT:
9430 case ZERO_EXTRACT:
9431 new = expand_compound_operation (varop);
9432 if (new != varop)
9433 {
9434 varop = new;
9435 continue;
9436 }
9437 break;
9438
9439 case MEM:
9440 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9441 minus the width of a smaller mode, we can do this with a
9442 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9443 if ((code == ASHIFTRT || code == LSHIFTRT)
9444 && ! mode_dependent_address_p (XEXP (varop, 0))
9445 && ! MEM_VOLATILE_P (varop)
9446 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9447 MODE_INT, 1)) != BLKmode)
9448 {
9449 new = adjust_address_nv (varop, tmode,
9450 BYTES_BIG_ENDIAN ? 0
9451 : count / BITS_PER_UNIT);
9452
9453 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9454 : ZERO_EXTEND, mode, new);
9455 count = 0;
9456 continue;
9457 }
9458 break;
9459
9460 case USE:
9461 /* Similar to the case above, except that we can only do this if
9462 the resulting mode is the same as that of the underlying
9463 MEM and adjust the address depending on the *bits* endianness
9464 because of the way that bit-field extract insns are defined. */
9465 if ((code == ASHIFTRT || code == LSHIFTRT)
9466 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9467 MODE_INT, 1)) != BLKmode
9468 && tmode == GET_MODE (XEXP (varop, 0)))
9469 {
9470 if (BITS_BIG_ENDIAN)
9471 new = XEXP (varop, 0);
9472 else
9473 {
9474 new = copy_rtx (XEXP (varop, 0));
9475 SUBST (XEXP (new, 0),
9476 plus_constant (XEXP (new, 0),
9477 count / BITS_PER_UNIT));
9478 }
9479
9480 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9481 : ZERO_EXTEND, mode, new);
9482 count = 0;
9483 continue;
9484 }
9485 break;
9486
9487 case SUBREG:
9488 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9489 the same number of words as what we've seen so far. Then store
9490 the widest mode in MODE. */
9491 if (subreg_lowpart_p (varop)
9492 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9493 > GET_MODE_SIZE (GET_MODE (varop)))
9494 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9495 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9496 == mode_words)
9497 {
9498 varop = SUBREG_REG (varop);
9499 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9500 mode = GET_MODE (varop);
9501 continue;
9502 }
9503 break;
9504
9505 case MULT:
9506 /* Some machines use MULT instead of ASHIFT because MULT
9507 is cheaper. But it is still better on those machines to
9508 merge two shifts into one. */
9509 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9510 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9511 {
9512 varop
9513 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9514 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9515 continue;
9516 }
9517 break;
9518
9519 case UDIV:
9520 /* Similar, for when divides are cheaper. */
9521 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9522 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9523 {
9524 varop
9525 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9526 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9527 continue;
9528 }
9529 break;
9530
9531 case ASHIFTRT:
9532 /* If we are extracting just the sign bit of an arithmetic
9533 right shift, that shift is not needed. However, the sign
9534 bit of a wider mode may be different from what would be
9535 interpreted as the sign bit in a narrower mode, so, if
9536 the result is narrower, don't discard the shift. */
9537 if (code == LSHIFTRT
9538 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9539 && (GET_MODE_BITSIZE (result_mode)
9540 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9541 {
9542 varop = XEXP (varop, 0);
9543 continue;
9544 }
9545
9546 /* ... fall through ... */
9547
9548 case LSHIFTRT:
9549 case ASHIFT:
9550 case ROTATE:
9551 /* Here we have two nested shifts. The result is usually the
9552 AND of a new shift with a mask. We compute the result below. */
9553 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9554 && INTVAL (XEXP (varop, 1)) >= 0
9555 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9556 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9557 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9558 {
9559 enum rtx_code first_code = GET_CODE (varop);
9560 unsigned int first_count = INTVAL (XEXP (varop, 1));
9561 unsigned HOST_WIDE_INT mask;
9562 rtx mask_rtx;
9563
9564 /* We have one common special case. We can't do any merging if
9565 the inner code is an ASHIFTRT of a smaller mode. However, if
9566 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9567 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9568 we can convert it to
9569 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9570 This simplifies certain SIGN_EXTEND operations. */
9571 if (code == ASHIFT && first_code == ASHIFTRT
9572 && count == (unsigned int)
9573 (GET_MODE_BITSIZE (result_mode)
9574 - GET_MODE_BITSIZE (GET_MODE (varop))))
9575 {
9576 /* C3 has the low-order C1 bits zero. */
9577
9578 mask = (GET_MODE_MASK (mode)
9579 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9580
9581 varop = simplify_and_const_int (NULL_RTX, result_mode,
9582 XEXP (varop, 0), mask);
9583 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9584 varop, count);
9585 count = first_count;
9586 code = ASHIFTRT;
9587 continue;
9588 }
9589
9590 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9591 than C1 high-order bits equal to the sign bit, we can convert
9592 this to either an ASHIFT or an ASHIFTRT depending on the
9593 two counts.
9594
9595 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9596
9597 if (code == ASHIFTRT && first_code == ASHIFT
9598 && GET_MODE (varop) == shift_mode
9599 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9600 > first_count))
9601 {
9602 varop = XEXP (varop, 0);
9603
9604 signed_count = count - first_count;
9605 if (signed_count < 0)
9606 count = -signed_count, code = ASHIFT;
9607 else
9608 count = signed_count;
9609
9610 continue;
9611 }
9612
9613 /* There are some cases we can't do. If CODE is ASHIFTRT,
9614 we can only do this if FIRST_CODE is also ASHIFTRT.
9615
9616 We can't do the case when CODE is ROTATE and FIRST_CODE is
9617 ASHIFTRT.
9618
9619 If the mode of this shift is not the mode of the outer shift,
9620 we can't do this if either shift is a right shift or ROTATE.
9621
9622 Finally, we can't do any of these if the mode is too wide
9623 unless the codes are the same.
9624
9625 Handle the case where the shift codes are the same
9626 first. */
9627
9628 if (code == first_code)
9629 {
9630 if (GET_MODE (varop) != result_mode
9631 && (code == ASHIFTRT || code == LSHIFTRT
9632 || code == ROTATE))
9633 break;
9634
9635 count += first_count;
9636 varop = XEXP (varop, 0);
9637 continue;
9638 }
9639
9640 if (code == ASHIFTRT
9641 || (code == ROTATE && first_code == ASHIFTRT)
9642 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9643 || (GET_MODE (varop) != result_mode
9644 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9645 || first_code == ROTATE
9646 || code == ROTATE)))
9647 break;
9648
9649 /* To compute the mask to apply after the shift, shift the
9650 nonzero bits of the inner shift the same way the
9651 outer shift will. */
9652
9653 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9654
9655 mask_rtx
9656 = simplify_binary_operation (code, result_mode, mask_rtx,
9657 GEN_INT (count));
9658
9659 /* Give up if we can't compute an outer operation to use. */
9660 if (mask_rtx == 0
9661 || GET_CODE (mask_rtx) != CONST_INT
9662 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9663 INTVAL (mask_rtx),
9664 result_mode, &complement_p))
9665 break;
9666
9667 /* If the shifts are in the same direction, we add the
9668 counts. Otherwise, we subtract them. */
9669 signed_count = count;
9670 if ((code == ASHIFTRT || code == LSHIFTRT)
9671 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9672 signed_count += first_count;
9673 else
9674 signed_count -= first_count;
9675
9676 /* If COUNT is positive, the new shift is usually CODE,
9677 except for the two exceptions below, in which case it is
9678 FIRST_CODE. If the count is negative, FIRST_CODE should
9679 always be used */
9680 if (signed_count > 0
9681 && ((first_code == ROTATE && code == ASHIFT)
9682 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9683 code = first_code, count = signed_count;
9684 else if (signed_count < 0)
9685 code = first_code, count = -signed_count;
9686 else
9687 count = signed_count;
9688
9689 varop = XEXP (varop, 0);
9690 continue;
9691 }
9692
9693 /* If we have (A << B << C) for any shift, we can convert this to
9694 (A << C << B). This wins if A is a constant. Only try this if
9695 B is not a constant. */
9696
9697 else if (GET_CODE (varop) == code
9698 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9699 && 0 != (new
9700 = simplify_binary_operation (code, mode,
9701 XEXP (varop, 0),
9702 GEN_INT (count))))
9703 {
9704 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9705 count = 0;
9706 continue;
9707 }
9708 break;
9709
9710 case NOT:
9711 /* Make this fit the case below. */
9712 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9713 GEN_INT (GET_MODE_MASK (mode)));
9714 continue;
9715
9716 case IOR:
9717 case AND:
9718 case XOR:
9719 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9720 with C the size of VAROP - 1 and the shift is logical if
9721 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9722 we have an (le X 0) operation. If we have an arithmetic shift
9723 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9724 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9725
9726 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9727 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9728 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9729 && (code == LSHIFTRT || code == ASHIFTRT)
9730 && count == (unsigned int)
9731 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9732 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9733 {
9734 count = 0;
9735 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9736 const0_rtx);
9737
9738 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9739 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9740
9741 continue;
9742 }
9743
9744 /* If we have (shift (logical)), move the logical to the outside
9745 to allow it to possibly combine with another logical and the
9746 shift to combine with another shift. This also canonicalizes to
9747 what a ZERO_EXTRACT looks like. Also, some machines have
9748 (and (shift)) insns. */
9749
9750 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9751 && (new = simplify_binary_operation (code, result_mode,
9752 XEXP (varop, 1),
9753 GEN_INT (count))) != 0
9754 && GET_CODE (new) == CONST_INT
9755 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9756 INTVAL (new), result_mode, &complement_p))
9757 {
9758 varop = XEXP (varop, 0);
9759 continue;
9760 }
9761
9762 /* If we can't do that, try to simplify the shift in each arm of the
9763 logical expression, make a new logical expression, and apply
9764 the inverse distributive law. */
9765 {
9766 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9767 XEXP (varop, 0), count);
9768 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9769 XEXP (varop, 1), count);
9770
9771 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9772 varop = apply_distributive_law (varop);
9773
9774 count = 0;
9775 }
9776 break;
9777
9778 case EQ:
9779 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9780 says that the sign bit can be tested, FOO has mode MODE, C is
9781 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9782 that may be nonzero. */
9783 if (code == LSHIFTRT
9784 && XEXP (varop, 1) == const0_rtx
9785 && GET_MODE (XEXP (varop, 0)) == result_mode
9786 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9787 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9788 && ((STORE_FLAG_VALUE
9789 & ((HOST_WIDE_INT) 1
9790 < (GET_MODE_BITSIZE (result_mode) - 1))))
9791 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9792 && merge_outer_ops (&outer_op, &outer_const, XOR,
9793 (HOST_WIDE_INT) 1, result_mode,
9794 &complement_p))
9795 {
9796 varop = XEXP (varop, 0);
9797 count = 0;
9798 continue;
9799 }
9800 break;
9801
9802 case NEG:
9803 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9804 than the number of bits in the mode is equivalent to A. */
9805 if (code == LSHIFTRT
9806 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9807 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9808 {
9809 varop = XEXP (varop, 0);
9810 count = 0;
9811 continue;
9812 }
9813
9814 /* NEG commutes with ASHIFT since it is multiplication. Move the
9815 NEG outside to allow shifts to combine. */
9816 if (code == ASHIFT
9817 && merge_outer_ops (&outer_op, &outer_const, NEG,
9818 (HOST_WIDE_INT) 0, result_mode,
9819 &complement_p))
9820 {
9821 varop = XEXP (varop, 0);
9822 continue;
9823 }
9824 break;
9825
9826 case PLUS:
9827 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9828 is one less than the number of bits in the mode is
9829 equivalent to (xor A 1). */
9830 if (code == LSHIFTRT
9831 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9832 && XEXP (varop, 1) == constm1_rtx
9833 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9834 && merge_outer_ops (&outer_op, &outer_const, XOR,
9835 (HOST_WIDE_INT) 1, result_mode,
9836 &complement_p))
9837 {
9838 count = 0;
9839 varop = XEXP (varop, 0);
9840 continue;
9841 }
9842
9843 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9844 that might be nonzero in BAR are those being shifted out and those
9845 bits are known zero in FOO, we can replace the PLUS with FOO.
9846 Similarly in the other operand order. This code occurs when
9847 we are computing the size of a variable-size array. */
9848
9849 if ((code == ASHIFTRT || code == LSHIFTRT)
9850 && count < HOST_BITS_PER_WIDE_INT
9851 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9852 && (nonzero_bits (XEXP (varop, 1), result_mode)
9853 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9854 {
9855 varop = XEXP (varop, 0);
9856 continue;
9857 }
9858 else if ((code == ASHIFTRT || code == LSHIFTRT)
9859 && count < HOST_BITS_PER_WIDE_INT
9860 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9861 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9862 >> count)
9863 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9864 & nonzero_bits (XEXP (varop, 1),
9865 result_mode)))
9866 {
9867 varop = XEXP (varop, 1);
9868 continue;
9869 }
9870
9871 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9872 if (code == ASHIFT
9873 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9874 && (new = simplify_binary_operation (ASHIFT, result_mode,
9875 XEXP (varop, 1),
9876 GEN_INT (count))) != 0
9877 && GET_CODE (new) == CONST_INT
9878 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9879 INTVAL (new), result_mode, &complement_p))
9880 {
9881 varop = XEXP (varop, 0);
9882 continue;
9883 }
9884 break;
9885
9886 case MINUS:
9887 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9888 with C the size of VAROP - 1 and the shift is logical if
9889 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9890 we have a (gt X 0) operation. If the shift is arithmetic with
9891 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9892 we have a (neg (gt X 0)) operation. */
9893
9894 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9895 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9896 && count == (unsigned int)
9897 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9898 && (code == LSHIFTRT || code == ASHIFTRT)
9899 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9900 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9901 == count
9902 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9903 {
9904 count = 0;
9905 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9906 const0_rtx);
9907
9908 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9909 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9910
9911 continue;
9912 }
9913 break;
9914
9915 case TRUNCATE:
9916 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9917 if the truncate does not affect the value. */
9918 if (code == LSHIFTRT
9919 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9920 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9921 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9922 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9923 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9924 {
9925 rtx varop_inner = XEXP (varop, 0);
9926
9927 varop_inner
9928 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9929 XEXP (varop_inner, 0),
9930 GEN_INT
9931 (count + INTVAL (XEXP (varop_inner, 1))));
9932 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9933 count = 0;
9934 continue;
9935 }
9936 break;
9937
9938 default:
9939 break;
9940 }
9941
9942 break;
9943 }
9944
9945 /* We need to determine what mode to do the shift in. If the shift is
9946 a right shift or ROTATE, we must always do it in the mode it was
9947 originally done in. Otherwise, we can do it in MODE, the widest mode
9948 encountered. The code we care about is that of the shift that will
9949 actually be done, not the shift that was originally requested. */
9950 shift_mode
9951 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9952 ? result_mode : mode);
9953
9954 /* We have now finished analyzing the shift. The result should be
9955 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9956 OUTER_OP is non-NIL, it is an operation that needs to be applied
9957 to the result of the shift. OUTER_CONST is the relevant constant,
9958 but we must turn off all bits turned off in the shift.
9959
9960 If we were passed a value for X, see if we can use any pieces of
9961 it. If not, make new rtx. */
9962
9963 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9964 && GET_CODE (XEXP (x, 1)) == CONST_INT
9965 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9966 const_rtx = XEXP (x, 1);
9967 else
9968 const_rtx = GEN_INT (count);
9969
9970 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9971 && GET_MODE (XEXP (x, 0)) == shift_mode
9972 && SUBREG_REG (XEXP (x, 0)) == varop)
9973 varop = XEXP (x, 0);
9974 else if (GET_MODE (varop) != shift_mode)
9975 varop = gen_lowpart_for_combine (shift_mode, varop);
9976
9977 /* If we can't make the SUBREG, try to return what we were given. */
9978 if (GET_CODE (varop) == CLOBBER)
9979 return x ? x : varop;
9980
9981 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9982 if (new != 0)
9983 x = new;
9984 else
9985 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9986
9987 /* If we have an outer operation and we just made a shift, it is
9988 possible that we could have simplified the shift were it not
9989 for the outer operation. So try to do the simplification
9990 recursively. */
9991
9992 if (outer_op != NIL && GET_CODE (x) == code
9993 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9994 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9995 INTVAL (XEXP (x, 1)));
9996
9997 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9998 turn off all the bits that the shift would have turned off. */
9999 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10000 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10001 GET_MODE_MASK (result_mode) >> orig_count);
10002
10003 /* Do the remainder of the processing in RESULT_MODE. */
10004 x = gen_lowpart_for_combine (result_mode, x);
10005
10006 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10007 operation. */
10008 if (complement_p)
10009 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10010
10011 if (outer_op != NIL)
10012 {
10013 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10014 outer_const = trunc_int_for_mode (outer_const, result_mode);
10015
10016 if (outer_op == AND)
10017 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10018 else if (outer_op == SET)
10019 /* This means that we have determined that the result is
10020 equivalent to a constant. This should be rare. */
10021 x = GEN_INT (outer_const);
10022 else if (GET_RTX_CLASS (outer_op) == '1')
10023 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10024 else
10025 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
10026 }
10027
10028 return x;
10029 }
10030 \f
10031 /* Like recog, but we receive the address of a pointer to a new pattern.
10032 We try to match the rtx that the pointer points to.
10033 If that fails, we may try to modify or replace the pattern,
10034 storing the replacement into the same pointer object.
10035
10036 Modifications include deletion or addition of CLOBBERs.
10037
10038 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10039 the CLOBBERs are placed.
10040
10041 The value is the final insn code from the pattern ultimately matched,
10042 or -1. */
10043
10044 static int
10045 recog_for_combine (pnewpat, insn, pnotes)
10046 rtx *pnewpat;
10047 rtx insn;
10048 rtx *pnotes;
10049 {
10050 rtx pat = *pnewpat;
10051 int insn_code_number;
10052 int num_clobbers_to_add = 0;
10053 int i;
10054 rtx notes = 0;
10055 rtx dummy_insn;
10056
10057 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10058 we use to indicate that something didn't match. If we find such a
10059 thing, force rejection. */
10060 if (GET_CODE (pat) == PARALLEL)
10061 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10062 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10063 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10064 return -1;
10065
10066 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
10067 instruction for pattern recognition. */
10068 dummy_insn = shallow_copy_rtx (insn);
10069 PATTERN (dummy_insn) = pat;
10070 REG_NOTES (dummy_insn) = 0;
10071
10072 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10073
10074 /* If it isn't, there is the possibility that we previously had an insn
10075 that clobbered some register as a side effect, but the combined
10076 insn doesn't need to do that. So try once more without the clobbers
10077 unless this represents an ASM insn. */
10078
10079 if (insn_code_number < 0 && ! check_asm_operands (pat)
10080 && GET_CODE (pat) == PARALLEL)
10081 {
10082 int pos;
10083
10084 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10085 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10086 {
10087 if (i != pos)
10088 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10089 pos++;
10090 }
10091
10092 SUBST_INT (XVECLEN (pat, 0), pos);
10093
10094 if (pos == 1)
10095 pat = XVECEXP (pat, 0, 0);
10096
10097 PATTERN (dummy_insn) = pat;
10098 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10099 }
10100
10101 /* Recognize all noop sets, these will be killed by followup pass. */
10102 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10103 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10104
10105 /* If we had any clobbers to add, make a new pattern than contains
10106 them. Then check to make sure that all of them are dead. */
10107 if (num_clobbers_to_add)
10108 {
10109 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10110 rtvec_alloc (GET_CODE (pat) == PARALLEL
10111 ? (XVECLEN (pat, 0)
10112 + num_clobbers_to_add)
10113 : num_clobbers_to_add + 1));
10114
10115 if (GET_CODE (pat) == PARALLEL)
10116 for (i = 0; i < XVECLEN (pat, 0); i++)
10117 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10118 else
10119 XVECEXP (newpat, 0, 0) = pat;
10120
10121 add_clobbers (newpat, insn_code_number);
10122
10123 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10124 i < XVECLEN (newpat, 0); i++)
10125 {
10126 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10127 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10128 return -1;
10129 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10130 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10131 }
10132 pat = newpat;
10133 }
10134
10135 *pnewpat = pat;
10136 *pnotes = notes;
10137
10138 return insn_code_number;
10139 }
10140 \f
10141 /* Like gen_lowpart but for use by combine. In combine it is not possible
10142 to create any new pseudoregs. However, it is safe to create
10143 invalid memory addresses, because combine will try to recognize
10144 them and all they will do is make the combine attempt fail.
10145
10146 If for some reason this cannot do its job, an rtx
10147 (clobber (const_int 0)) is returned.
10148 An insn containing that will not be recognized. */
10149
10150 #undef gen_lowpart
10151
10152 static rtx
10153 gen_lowpart_for_combine (mode, x)
10154 enum machine_mode mode;
10155 rtx x;
10156 {
10157 rtx result;
10158
10159 if (GET_MODE (x) == mode)
10160 return x;
10161
10162 /* We can only support MODE being wider than a word if X is a
10163 constant integer or has a mode the same size. */
10164
10165 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10166 && ! ((GET_MODE (x) == VOIDmode
10167 && (GET_CODE (x) == CONST_INT
10168 || GET_CODE (x) == CONST_DOUBLE))
10169 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10170 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10171
10172 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10173 won't know what to do. So we will strip off the SUBREG here and
10174 process normally. */
10175 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10176 {
10177 x = SUBREG_REG (x);
10178 if (GET_MODE (x) == mode)
10179 return x;
10180 }
10181
10182 result = gen_lowpart_common (mode, x);
10183 #ifdef CANNOT_CHANGE_MODE_CLASS
10184 if (result != 0
10185 && GET_CODE (result) == SUBREG
10186 && GET_CODE (SUBREG_REG (result)) == REG
10187 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10188 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10189 * MAX_MACHINE_MODE
10190 + GET_MODE (result));
10191 #endif
10192
10193 if (result)
10194 return result;
10195
10196 if (GET_CODE (x) == MEM)
10197 {
10198 int offset = 0;
10199
10200 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10201 address. */
10202 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10203 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10204
10205 /* If we want to refer to something bigger than the original memref,
10206 generate a perverse subreg instead. That will force a reload
10207 of the original memref X. */
10208 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10209 return gen_rtx_SUBREG (mode, x, 0);
10210
10211 if (WORDS_BIG_ENDIAN)
10212 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10213 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10214
10215 if (BYTES_BIG_ENDIAN)
10216 {
10217 /* Adjust the address so that the address-after-the-data is
10218 unchanged. */
10219 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10220 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10221 }
10222
10223 return adjust_address_nv (x, mode, offset);
10224 }
10225
10226 /* If X is a comparison operator, rewrite it in a new mode. This
10227 probably won't match, but may allow further simplifications. */
10228 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10229 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10230
10231 /* If we couldn't simplify X any other way, just enclose it in a
10232 SUBREG. Normally, this SUBREG won't match, but some patterns may
10233 include an explicit SUBREG or we may simplify it further in combine. */
10234 else
10235 {
10236 int offset = 0;
10237 rtx res;
10238 enum machine_mode sub_mode = GET_MODE (x);
10239
10240 offset = subreg_lowpart_offset (mode, sub_mode);
10241 if (sub_mode == VOIDmode)
10242 {
10243 sub_mode = int_mode_for_mode (mode);
10244 x = gen_lowpart_common (sub_mode, x);
10245 }
10246 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10247 if (res)
10248 return res;
10249 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10250 }
10251 }
10252 \f
10253 /* These routines make binary and unary operations by first seeing if they
10254 fold; if not, a new expression is allocated. */
10255
10256 static rtx
10257 gen_binary (code, mode, op0, op1)
10258 enum rtx_code code;
10259 enum machine_mode mode;
10260 rtx op0, op1;
10261 {
10262 rtx result;
10263 rtx tem;
10264
10265 if (GET_RTX_CLASS (code) == 'c'
10266 && swap_commutative_operands_p (op0, op1))
10267 tem = op0, op0 = op1, op1 = tem;
10268
10269 if (GET_RTX_CLASS (code) == '<')
10270 {
10271 enum machine_mode op_mode = GET_MODE (op0);
10272
10273 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10274 just (REL_OP X Y). */
10275 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10276 {
10277 op1 = XEXP (op0, 1);
10278 op0 = XEXP (op0, 0);
10279 op_mode = GET_MODE (op0);
10280 }
10281
10282 if (op_mode == VOIDmode)
10283 op_mode = GET_MODE (op1);
10284 result = simplify_relational_operation (code, op_mode, op0, op1);
10285 }
10286 else
10287 result = simplify_binary_operation (code, mode, op0, op1);
10288
10289 if (result)
10290 return result;
10291
10292 /* Put complex operands first and constants second. */
10293 if (GET_RTX_CLASS (code) == 'c'
10294 && swap_commutative_operands_p (op0, op1))
10295 return gen_rtx_fmt_ee (code, mode, op1, op0);
10296
10297 /* If we are turning off bits already known off in OP0, we need not do
10298 an AND. */
10299 else if (code == AND && GET_CODE (op1) == CONST_INT
10300 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10301 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10302 return op0;
10303
10304 return gen_rtx_fmt_ee (code, mode, op0, op1);
10305 }
10306 \f
10307 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10308 comparison code that will be tested.
10309
10310 The result is a possibly different comparison code to use. *POP0 and
10311 *POP1 may be updated.
10312
10313 It is possible that we might detect that a comparison is either always
10314 true or always false. However, we do not perform general constant
10315 folding in combine, so this knowledge isn't useful. Such tautologies
10316 should have been detected earlier. Hence we ignore all such cases. */
10317
10318 static enum rtx_code
10319 simplify_comparison (code, pop0, pop1)
10320 enum rtx_code code;
10321 rtx *pop0;
10322 rtx *pop1;
10323 {
10324 rtx op0 = *pop0;
10325 rtx op1 = *pop1;
10326 rtx tem, tem1;
10327 int i;
10328 enum machine_mode mode, tmode;
10329
10330 /* Try a few ways of applying the same transformation to both operands. */
10331 while (1)
10332 {
10333 #ifndef WORD_REGISTER_OPERATIONS
10334 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10335 so check specially. */
10336 if (code != GTU && code != GEU && code != LTU && code != LEU
10337 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10338 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10339 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10340 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10341 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10342 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10343 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10344 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10345 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10346 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10347 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10348 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10349 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10350 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10351 && (INTVAL (XEXP (op0, 1))
10352 == (GET_MODE_BITSIZE (GET_MODE (op0))
10353 - (GET_MODE_BITSIZE
10354 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10355 {
10356 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10357 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10358 }
10359 #endif
10360
10361 /* If both operands are the same constant shift, see if we can ignore the
10362 shift. We can if the shift is a rotate or if the bits shifted out of
10363 this shift are known to be zero for both inputs and if the type of
10364 comparison is compatible with the shift. */
10365 if (GET_CODE (op0) == GET_CODE (op1)
10366 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10367 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10368 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10369 && (code != GT && code != LT && code != GE && code != LE))
10370 || (GET_CODE (op0) == ASHIFTRT
10371 && (code != GTU && code != LTU
10372 && code != GEU && code != LEU)))
10373 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10374 && INTVAL (XEXP (op0, 1)) >= 0
10375 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10376 && XEXP (op0, 1) == XEXP (op1, 1))
10377 {
10378 enum machine_mode mode = GET_MODE (op0);
10379 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10380 int shift_count = INTVAL (XEXP (op0, 1));
10381
10382 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10383 mask &= (mask >> shift_count) << shift_count;
10384 else if (GET_CODE (op0) == ASHIFT)
10385 mask = (mask & (mask << shift_count)) >> shift_count;
10386
10387 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10388 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10389 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10390 else
10391 break;
10392 }
10393
10394 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10395 SUBREGs are of the same mode, and, in both cases, the AND would
10396 be redundant if the comparison was done in the narrower mode,
10397 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10398 and the operand's possibly nonzero bits are 0xffffff01; in that case
10399 if we only care about QImode, we don't need the AND). This case
10400 occurs if the output mode of an scc insn is not SImode and
10401 STORE_FLAG_VALUE == 1 (e.g., the 386).
10402
10403 Similarly, check for a case where the AND's are ZERO_EXTEND
10404 operations from some narrower mode even though a SUBREG is not
10405 present. */
10406
10407 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10408 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10409 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10410 {
10411 rtx inner_op0 = XEXP (op0, 0);
10412 rtx inner_op1 = XEXP (op1, 0);
10413 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10414 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10415 int changed = 0;
10416
10417 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10418 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10419 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10420 && (GET_MODE (SUBREG_REG (inner_op0))
10421 == GET_MODE (SUBREG_REG (inner_op1)))
10422 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10423 <= HOST_BITS_PER_WIDE_INT)
10424 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10425 GET_MODE (SUBREG_REG (inner_op0)))))
10426 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10427 GET_MODE (SUBREG_REG (inner_op1))))))
10428 {
10429 op0 = SUBREG_REG (inner_op0);
10430 op1 = SUBREG_REG (inner_op1);
10431
10432 /* The resulting comparison is always unsigned since we masked
10433 off the original sign bit. */
10434 code = unsigned_condition (code);
10435
10436 changed = 1;
10437 }
10438
10439 else if (c0 == c1)
10440 for (tmode = GET_CLASS_NARROWEST_MODE
10441 (GET_MODE_CLASS (GET_MODE (op0)));
10442 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10443 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10444 {
10445 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10446 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10447 code = unsigned_condition (code);
10448 changed = 1;
10449 break;
10450 }
10451
10452 if (! changed)
10453 break;
10454 }
10455
10456 /* If both operands are NOT, we can strip off the outer operation
10457 and adjust the comparison code for swapped operands; similarly for
10458 NEG, except that this must be an equality comparison. */
10459 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10460 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10461 && (code == EQ || code == NE)))
10462 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10463
10464 else
10465 break;
10466 }
10467
10468 /* If the first operand is a constant, swap the operands and adjust the
10469 comparison code appropriately, but don't do this if the second operand
10470 is already a constant integer. */
10471 if (swap_commutative_operands_p (op0, op1))
10472 {
10473 tem = op0, op0 = op1, op1 = tem;
10474 code = swap_condition (code);
10475 }
10476
10477 /* We now enter a loop during which we will try to simplify the comparison.
10478 For the most part, we only are concerned with comparisons with zero,
10479 but some things may really be comparisons with zero but not start
10480 out looking that way. */
10481
10482 while (GET_CODE (op1) == CONST_INT)
10483 {
10484 enum machine_mode mode = GET_MODE (op0);
10485 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10486 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10487 int equality_comparison_p;
10488 int sign_bit_comparison_p;
10489 int unsigned_comparison_p;
10490 HOST_WIDE_INT const_op;
10491
10492 /* We only want to handle integral modes. This catches VOIDmode,
10493 CCmode, and the floating-point modes. An exception is that we
10494 can handle VOIDmode if OP0 is a COMPARE or a comparison
10495 operation. */
10496
10497 if (GET_MODE_CLASS (mode) != MODE_INT
10498 && ! (mode == VOIDmode
10499 && (GET_CODE (op0) == COMPARE
10500 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10501 break;
10502
10503 /* Get the constant we are comparing against and turn off all bits
10504 not on in our mode. */
10505 const_op = INTVAL (op1);
10506 if (mode != VOIDmode)
10507 const_op = trunc_int_for_mode (const_op, mode);
10508 op1 = GEN_INT (const_op);
10509
10510 /* If we are comparing against a constant power of two and the value
10511 being compared can only have that single bit nonzero (e.g., it was
10512 `and'ed with that bit), we can replace this with a comparison
10513 with zero. */
10514 if (const_op
10515 && (code == EQ || code == NE || code == GE || code == GEU
10516 || code == LT || code == LTU)
10517 && mode_width <= HOST_BITS_PER_WIDE_INT
10518 && exact_log2 (const_op) >= 0
10519 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10520 {
10521 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10522 op1 = const0_rtx, const_op = 0;
10523 }
10524
10525 /* Similarly, if we are comparing a value known to be either -1 or
10526 0 with -1, change it to the opposite comparison against zero. */
10527
10528 if (const_op == -1
10529 && (code == EQ || code == NE || code == GT || code == LE
10530 || code == GEU || code == LTU)
10531 && num_sign_bit_copies (op0, mode) == mode_width)
10532 {
10533 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10534 op1 = const0_rtx, const_op = 0;
10535 }
10536
10537 /* Do some canonicalizations based on the comparison code. We prefer
10538 comparisons against zero and then prefer equality comparisons.
10539 If we can reduce the size of a constant, we will do that too. */
10540
10541 switch (code)
10542 {
10543 case LT:
10544 /* < C is equivalent to <= (C - 1) */
10545 if (const_op > 0)
10546 {
10547 const_op -= 1;
10548 op1 = GEN_INT (const_op);
10549 code = LE;
10550 /* ... fall through to LE case below. */
10551 }
10552 else
10553 break;
10554
10555 case LE:
10556 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10557 if (const_op < 0)
10558 {
10559 const_op += 1;
10560 op1 = GEN_INT (const_op);
10561 code = LT;
10562 }
10563
10564 /* If we are doing a <= 0 comparison on a value known to have
10565 a zero sign bit, we can replace this with == 0. */
10566 else if (const_op == 0
10567 && mode_width <= HOST_BITS_PER_WIDE_INT
10568 && (nonzero_bits (op0, mode)
10569 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10570 code = EQ;
10571 break;
10572
10573 case GE:
10574 /* >= C is equivalent to > (C - 1). */
10575 if (const_op > 0)
10576 {
10577 const_op -= 1;
10578 op1 = GEN_INT (const_op);
10579 code = GT;
10580 /* ... fall through to GT below. */
10581 }
10582 else
10583 break;
10584
10585 case GT:
10586 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10587 if (const_op < 0)
10588 {
10589 const_op += 1;
10590 op1 = GEN_INT (const_op);
10591 code = GE;
10592 }
10593
10594 /* If we are doing a > 0 comparison on a value known to have
10595 a zero sign bit, we can replace this with != 0. */
10596 else if (const_op == 0
10597 && mode_width <= HOST_BITS_PER_WIDE_INT
10598 && (nonzero_bits (op0, mode)
10599 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10600 code = NE;
10601 break;
10602
10603 case LTU:
10604 /* < C is equivalent to <= (C - 1). */
10605 if (const_op > 0)
10606 {
10607 const_op -= 1;
10608 op1 = GEN_INT (const_op);
10609 code = LEU;
10610 /* ... fall through ... */
10611 }
10612
10613 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10614 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10615 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10616 {
10617 const_op = 0, op1 = const0_rtx;
10618 code = GE;
10619 break;
10620 }
10621 else
10622 break;
10623
10624 case LEU:
10625 /* unsigned <= 0 is equivalent to == 0 */
10626 if (const_op == 0)
10627 code = EQ;
10628
10629 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10630 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10631 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10632 {
10633 const_op = 0, op1 = const0_rtx;
10634 code = GE;
10635 }
10636 break;
10637
10638 case GEU:
10639 /* >= C is equivalent to < (C - 1). */
10640 if (const_op > 1)
10641 {
10642 const_op -= 1;
10643 op1 = GEN_INT (const_op);
10644 code = GTU;
10645 /* ... fall through ... */
10646 }
10647
10648 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10649 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10650 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10651 {
10652 const_op = 0, op1 = const0_rtx;
10653 code = LT;
10654 break;
10655 }
10656 else
10657 break;
10658
10659 case GTU:
10660 /* unsigned > 0 is equivalent to != 0 */
10661 if (const_op == 0)
10662 code = NE;
10663
10664 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10665 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10666 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10667 {
10668 const_op = 0, op1 = const0_rtx;
10669 code = LT;
10670 }
10671 break;
10672
10673 default:
10674 break;
10675 }
10676
10677 /* Compute some predicates to simplify code below. */
10678
10679 equality_comparison_p = (code == EQ || code == NE);
10680 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10681 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10682 || code == GEU);
10683
10684 /* If this is a sign bit comparison and we can do arithmetic in
10685 MODE, say that we will only be needing the sign bit of OP0. */
10686 if (sign_bit_comparison_p
10687 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10688 op0 = force_to_mode (op0, mode,
10689 ((HOST_WIDE_INT) 1
10690 << (GET_MODE_BITSIZE (mode) - 1)),
10691 NULL_RTX, 0);
10692
10693 /* Now try cases based on the opcode of OP0. If none of the cases
10694 does a "continue", we exit this loop immediately after the
10695 switch. */
10696
10697 switch (GET_CODE (op0))
10698 {
10699 case ZERO_EXTRACT:
10700 /* If we are extracting a single bit from a variable position in
10701 a constant that has only a single bit set and are comparing it
10702 with zero, we can convert this into an equality comparison
10703 between the position and the location of the single bit. */
10704
10705 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10706 && XEXP (op0, 1) == const1_rtx
10707 && equality_comparison_p && const_op == 0
10708 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10709 {
10710 if (BITS_BIG_ENDIAN)
10711 {
10712 enum machine_mode new_mode
10713 = mode_for_extraction (EP_extzv, 1);
10714 if (new_mode == MAX_MACHINE_MODE)
10715 i = BITS_PER_WORD - 1 - i;
10716 else
10717 {
10718 mode = new_mode;
10719 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10720 }
10721 }
10722
10723 op0 = XEXP (op0, 2);
10724 op1 = GEN_INT (i);
10725 const_op = i;
10726
10727 /* Result is nonzero iff shift count is equal to I. */
10728 code = reverse_condition (code);
10729 continue;
10730 }
10731
10732 /* ... fall through ... */
10733
10734 case SIGN_EXTRACT:
10735 tem = expand_compound_operation (op0);
10736 if (tem != op0)
10737 {
10738 op0 = tem;
10739 continue;
10740 }
10741 break;
10742
10743 case NOT:
10744 /* If testing for equality, we can take the NOT of the constant. */
10745 if (equality_comparison_p
10746 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10747 {
10748 op0 = XEXP (op0, 0);
10749 op1 = tem;
10750 continue;
10751 }
10752
10753 /* If just looking at the sign bit, reverse the sense of the
10754 comparison. */
10755 if (sign_bit_comparison_p)
10756 {
10757 op0 = XEXP (op0, 0);
10758 code = (code == GE ? LT : GE);
10759 continue;
10760 }
10761 break;
10762
10763 case NEG:
10764 /* If testing for equality, we can take the NEG of the constant. */
10765 if (equality_comparison_p
10766 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10767 {
10768 op0 = XEXP (op0, 0);
10769 op1 = tem;
10770 continue;
10771 }
10772
10773 /* The remaining cases only apply to comparisons with zero. */
10774 if (const_op != 0)
10775 break;
10776
10777 /* When X is ABS or is known positive,
10778 (neg X) is < 0 if and only if X != 0. */
10779
10780 if (sign_bit_comparison_p
10781 && (GET_CODE (XEXP (op0, 0)) == ABS
10782 || (mode_width <= HOST_BITS_PER_WIDE_INT
10783 && (nonzero_bits (XEXP (op0, 0), mode)
10784 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10785 {
10786 op0 = XEXP (op0, 0);
10787 code = (code == LT ? NE : EQ);
10788 continue;
10789 }
10790
10791 /* If we have NEG of something whose two high-order bits are the
10792 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10793 if (num_sign_bit_copies (op0, mode) >= 2)
10794 {
10795 op0 = XEXP (op0, 0);
10796 code = swap_condition (code);
10797 continue;
10798 }
10799 break;
10800
10801 case ROTATE:
10802 /* If we are testing equality and our count is a constant, we
10803 can perform the inverse operation on our RHS. */
10804 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10805 && (tem = simplify_binary_operation (ROTATERT, mode,
10806 op1, XEXP (op0, 1))) != 0)
10807 {
10808 op0 = XEXP (op0, 0);
10809 op1 = tem;
10810 continue;
10811 }
10812
10813 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10814 a particular bit. Convert it to an AND of a constant of that
10815 bit. This will be converted into a ZERO_EXTRACT. */
10816 if (const_op == 0 && sign_bit_comparison_p
10817 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10818 && mode_width <= HOST_BITS_PER_WIDE_INT)
10819 {
10820 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10821 ((HOST_WIDE_INT) 1
10822 << (mode_width - 1
10823 - INTVAL (XEXP (op0, 1)))));
10824 code = (code == LT ? NE : EQ);
10825 continue;
10826 }
10827
10828 /* Fall through. */
10829
10830 case ABS:
10831 /* ABS is ignorable inside an equality comparison with zero. */
10832 if (const_op == 0 && equality_comparison_p)
10833 {
10834 op0 = XEXP (op0, 0);
10835 continue;
10836 }
10837 break;
10838
10839 case SIGN_EXTEND:
10840 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10841 to (compare FOO CONST) if CONST fits in FOO's mode and we
10842 are either testing inequality or have an unsigned comparison
10843 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10844 if (! unsigned_comparison_p
10845 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10846 <= HOST_BITS_PER_WIDE_INT)
10847 && ((unsigned HOST_WIDE_INT) const_op
10848 < (((unsigned HOST_WIDE_INT) 1
10849 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10850 {
10851 op0 = XEXP (op0, 0);
10852 continue;
10853 }
10854 break;
10855
10856 case SUBREG:
10857 /* Check for the case where we are comparing A - C1 with C2,
10858 both constants are smaller than 1/2 the maximum positive
10859 value in MODE, and the comparison is equality or unsigned.
10860 In that case, if A is either zero-extended to MODE or has
10861 sufficient sign bits so that the high-order bit in MODE
10862 is a copy of the sign in the inner mode, we can prove that it is
10863 safe to do the operation in the wider mode. This simplifies
10864 many range checks. */
10865
10866 if (mode_width <= HOST_BITS_PER_WIDE_INT
10867 && subreg_lowpart_p (op0)
10868 && GET_CODE (SUBREG_REG (op0)) == PLUS
10869 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10870 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10871 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10872 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10873 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10874 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10875 GET_MODE (SUBREG_REG (op0)))
10876 & ~GET_MODE_MASK (mode))
10877 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10878 GET_MODE (SUBREG_REG (op0)))
10879 > (unsigned int)
10880 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10881 - GET_MODE_BITSIZE (mode)))))
10882 {
10883 op0 = SUBREG_REG (op0);
10884 continue;
10885 }
10886
10887 /* If the inner mode is narrower and we are extracting the low part,
10888 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10889 if (subreg_lowpart_p (op0)
10890 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10891 /* Fall through */ ;
10892 else
10893 break;
10894
10895 /* ... fall through ... */
10896
10897 case ZERO_EXTEND:
10898 if ((unsigned_comparison_p || equality_comparison_p)
10899 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10900 <= HOST_BITS_PER_WIDE_INT)
10901 && ((unsigned HOST_WIDE_INT) const_op
10902 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10903 {
10904 op0 = XEXP (op0, 0);
10905 continue;
10906 }
10907 break;
10908
10909 case PLUS:
10910 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10911 this for equality comparisons due to pathological cases involving
10912 overflows. */
10913 if (equality_comparison_p
10914 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10915 op1, XEXP (op0, 1))))
10916 {
10917 op0 = XEXP (op0, 0);
10918 op1 = tem;
10919 continue;
10920 }
10921
10922 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10923 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10924 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10925 {
10926 op0 = XEXP (XEXP (op0, 0), 0);
10927 code = (code == LT ? EQ : NE);
10928 continue;
10929 }
10930 break;
10931
10932 case MINUS:
10933 /* We used to optimize signed comparisons against zero, but that
10934 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10935 arrive here as equality comparisons, or (GEU, LTU) are
10936 optimized away. No need to special-case them. */
10937
10938 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10939 (eq B (minus A C)), whichever simplifies. We can only do
10940 this for equality comparisons due to pathological cases involving
10941 overflows. */
10942 if (equality_comparison_p
10943 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10944 XEXP (op0, 1), op1)))
10945 {
10946 op0 = XEXP (op0, 0);
10947 op1 = tem;
10948 continue;
10949 }
10950
10951 if (equality_comparison_p
10952 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10953 XEXP (op0, 0), op1)))
10954 {
10955 op0 = XEXP (op0, 1);
10956 op1 = tem;
10957 continue;
10958 }
10959
10960 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10961 of bits in X minus 1, is one iff X > 0. */
10962 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10963 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10964 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10965 == mode_width - 1
10966 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10967 {
10968 op0 = XEXP (op0, 1);
10969 code = (code == GE ? LE : GT);
10970 continue;
10971 }
10972 break;
10973
10974 case XOR:
10975 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10976 if C is zero or B is a constant. */
10977 if (equality_comparison_p
10978 && 0 != (tem = simplify_binary_operation (XOR, mode,
10979 XEXP (op0, 1), op1)))
10980 {
10981 op0 = XEXP (op0, 0);
10982 op1 = tem;
10983 continue;
10984 }
10985 break;
10986
10987 case EQ: case NE:
10988 case UNEQ: case LTGT:
10989 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10990 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10991 case UNORDERED: case ORDERED:
10992 /* We can't do anything if OP0 is a condition code value, rather
10993 than an actual data value. */
10994 if (const_op != 0
10995 || CC0_P (XEXP (op0, 0))
10996 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10997 break;
10998
10999 /* Get the two operands being compared. */
11000 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11001 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11002 else
11003 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11004
11005 /* Check for the cases where we simply want the result of the
11006 earlier test or the opposite of that result. */
11007 if (code == NE || code == EQ
11008 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11009 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11010 && (STORE_FLAG_VALUE
11011 & (((HOST_WIDE_INT) 1
11012 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11013 && (code == LT || code == GE)))
11014 {
11015 enum rtx_code new_code;
11016 if (code == LT || code == NE)
11017 new_code = GET_CODE (op0);
11018 else
11019 new_code = combine_reversed_comparison_code (op0);
11020
11021 if (new_code != UNKNOWN)
11022 {
11023 code = new_code;
11024 op0 = tem;
11025 op1 = tem1;
11026 continue;
11027 }
11028 }
11029 break;
11030
11031 case IOR:
11032 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11033 iff X <= 0. */
11034 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11035 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11036 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11037 {
11038 op0 = XEXP (op0, 1);
11039 code = (code == GE ? GT : LE);
11040 continue;
11041 }
11042 break;
11043
11044 case AND:
11045 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11046 will be converted to a ZERO_EXTRACT later. */
11047 if (const_op == 0 && equality_comparison_p
11048 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11049 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11050 {
11051 op0 = simplify_and_const_int
11052 (op0, mode, gen_rtx_LSHIFTRT (mode,
11053 XEXP (op0, 1),
11054 XEXP (XEXP (op0, 0), 1)),
11055 (HOST_WIDE_INT) 1);
11056 continue;
11057 }
11058
11059 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11060 zero and X is a comparison and C1 and C2 describe only bits set
11061 in STORE_FLAG_VALUE, we can compare with X. */
11062 if (const_op == 0 && equality_comparison_p
11063 && mode_width <= HOST_BITS_PER_WIDE_INT
11064 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11065 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11066 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11067 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11068 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11069 {
11070 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11071 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11072 if ((~STORE_FLAG_VALUE & mask) == 0
11073 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
11074 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11075 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
11076 {
11077 op0 = XEXP (XEXP (op0, 0), 0);
11078 continue;
11079 }
11080 }
11081
11082 /* If we are doing an equality comparison of an AND of a bit equal
11083 to the sign bit, replace this with a LT or GE comparison of
11084 the underlying value. */
11085 if (equality_comparison_p
11086 && const_op == 0
11087 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11088 && mode_width <= HOST_BITS_PER_WIDE_INT
11089 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11090 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11091 {
11092 op0 = XEXP (op0, 0);
11093 code = (code == EQ ? GE : LT);
11094 continue;
11095 }
11096
11097 /* If this AND operation is really a ZERO_EXTEND from a narrower
11098 mode, the constant fits within that mode, and this is either an
11099 equality or unsigned comparison, try to do this comparison in
11100 the narrower mode. */
11101 if ((equality_comparison_p || unsigned_comparison_p)
11102 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11103 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11104 & GET_MODE_MASK (mode))
11105 + 1)) >= 0
11106 && const_op >> i == 0
11107 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11108 {
11109 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11110 continue;
11111 }
11112
11113 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11114 fits in both M1 and M2 and the SUBREG is either paradoxical
11115 or represents the low part, permute the SUBREG and the AND
11116 and try again. */
11117 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11118 {
11119 unsigned HOST_WIDE_INT c1;
11120 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11121 /* Require an integral mode, to avoid creating something like
11122 (AND:SF ...). */
11123 if (SCALAR_INT_MODE_P (tmode)
11124 /* It is unsafe to commute the AND into the SUBREG if the
11125 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11126 not defined. As originally written the upper bits
11127 have a defined value due to the AND operation.
11128 However, if we commute the AND inside the SUBREG then
11129 they no longer have defined values and the meaning of
11130 the code has been changed. */
11131 && (0
11132 #ifdef WORD_REGISTER_OPERATIONS
11133 || (mode_width > GET_MODE_BITSIZE (tmode)
11134 && mode_width <= BITS_PER_WORD)
11135 #endif
11136 || (mode_width <= GET_MODE_BITSIZE (tmode)
11137 && subreg_lowpart_p (XEXP (op0, 0))))
11138 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11139 && mode_width <= HOST_BITS_PER_WIDE_INT
11140 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11141 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11142 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11143 && c1 != mask
11144 && c1 != GET_MODE_MASK (tmode))
11145 {
11146 op0 = gen_binary (AND, tmode,
11147 SUBREG_REG (XEXP (op0, 0)),
11148 gen_int_mode (c1, tmode));
11149 op0 = gen_lowpart_for_combine (mode, op0);
11150 continue;
11151 }
11152 }
11153
11154 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11155 (eq (and (lshiftrt X) 1) 0). */
11156 if (const_op == 0 && equality_comparison_p
11157 && XEXP (op0, 1) == const1_rtx
11158 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11159 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11160 {
11161 op0 = simplify_and_const_int
11162 (op0, mode,
11163 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11164 XEXP (XEXP (op0, 0), 1)),
11165 (HOST_WIDE_INT) 1);
11166 code = (code == NE ? EQ : NE);
11167 continue;
11168 }
11169 break;
11170
11171 case ASHIFT:
11172 /* If we have (compare (ashift FOO N) (const_int C)) and
11173 the high order N bits of FOO (N+1 if an inequality comparison)
11174 are known to be zero, we can do this by comparing FOO with C
11175 shifted right N bits so long as the low-order N bits of C are
11176 zero. */
11177 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11178 && INTVAL (XEXP (op0, 1)) >= 0
11179 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11180 < HOST_BITS_PER_WIDE_INT)
11181 && ((const_op
11182 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11183 && mode_width <= HOST_BITS_PER_WIDE_INT
11184 && (nonzero_bits (XEXP (op0, 0), mode)
11185 & ~(mask >> (INTVAL (XEXP (op0, 1))
11186 + ! equality_comparison_p))) == 0)
11187 {
11188 /* We must perform a logical shift, not an arithmetic one,
11189 as we want the top N bits of C to be zero. */
11190 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11191
11192 temp >>= INTVAL (XEXP (op0, 1));
11193 op1 = gen_int_mode (temp, mode);
11194 op0 = XEXP (op0, 0);
11195 continue;
11196 }
11197
11198 /* If we are doing a sign bit comparison, it means we are testing
11199 a particular bit. Convert it to the appropriate AND. */
11200 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11201 && mode_width <= HOST_BITS_PER_WIDE_INT)
11202 {
11203 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11204 ((HOST_WIDE_INT) 1
11205 << (mode_width - 1
11206 - INTVAL (XEXP (op0, 1)))));
11207 code = (code == LT ? NE : EQ);
11208 continue;
11209 }
11210
11211 /* If this an equality comparison with zero and we are shifting
11212 the low bit to the sign bit, we can convert this to an AND of the
11213 low-order bit. */
11214 if (const_op == 0 && equality_comparison_p
11215 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11216 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11217 == mode_width - 1)
11218 {
11219 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11220 (HOST_WIDE_INT) 1);
11221 continue;
11222 }
11223 break;
11224
11225 case ASHIFTRT:
11226 /* If this is an equality comparison with zero, we can do this
11227 as a logical shift, which might be much simpler. */
11228 if (equality_comparison_p && const_op == 0
11229 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11230 {
11231 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11232 XEXP (op0, 0),
11233 INTVAL (XEXP (op0, 1)));
11234 continue;
11235 }
11236
11237 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11238 do the comparison in a narrower mode. */
11239 if (! unsigned_comparison_p
11240 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11241 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11242 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11243 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11244 MODE_INT, 1)) != BLKmode
11245 && (((unsigned HOST_WIDE_INT) const_op
11246 + (GET_MODE_MASK (tmode) >> 1) + 1)
11247 <= GET_MODE_MASK (tmode)))
11248 {
11249 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11250 continue;
11251 }
11252
11253 /* Likewise if OP0 is a PLUS of a sign extension with a
11254 constant, which is usually represented with the PLUS
11255 between the shifts. */
11256 if (! unsigned_comparison_p
11257 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11258 && GET_CODE (XEXP (op0, 0)) == PLUS
11259 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11260 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11261 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11262 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11263 MODE_INT, 1)) != BLKmode
11264 && (((unsigned HOST_WIDE_INT) const_op
11265 + (GET_MODE_MASK (tmode) >> 1) + 1)
11266 <= GET_MODE_MASK (tmode)))
11267 {
11268 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11269 rtx add_const = XEXP (XEXP (op0, 0), 1);
11270 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11271 XEXP (op0, 1));
11272
11273 op0 = gen_binary (PLUS, tmode,
11274 gen_lowpart_for_combine (tmode, inner),
11275 new_const);
11276 continue;
11277 }
11278
11279 /* ... fall through ... */
11280 case LSHIFTRT:
11281 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11282 the low order N bits of FOO are known to be zero, we can do this
11283 by comparing FOO with C shifted left N bits so long as no
11284 overflow occurs. */
11285 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11286 && INTVAL (XEXP (op0, 1)) >= 0
11287 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11288 && mode_width <= HOST_BITS_PER_WIDE_INT
11289 && (nonzero_bits (XEXP (op0, 0), mode)
11290 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11291 && (((unsigned HOST_WIDE_INT) const_op
11292 + (GET_CODE (op0) != LSHIFTRT
11293 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11294 + 1)
11295 : 0))
11296 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11297 {
11298 /* If the shift was logical, then we must make the condition
11299 unsigned. */
11300 if (GET_CODE (op0) == LSHIFTRT)
11301 code = unsigned_condition (code);
11302
11303 const_op <<= INTVAL (XEXP (op0, 1));
11304 op1 = GEN_INT (const_op);
11305 op0 = XEXP (op0, 0);
11306 continue;
11307 }
11308
11309 /* If we are using this shift to extract just the sign bit, we
11310 can replace this with an LT or GE comparison. */
11311 if (const_op == 0
11312 && (equality_comparison_p || sign_bit_comparison_p)
11313 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11314 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11315 == mode_width - 1)
11316 {
11317 op0 = XEXP (op0, 0);
11318 code = (code == NE || code == GT ? LT : GE);
11319 continue;
11320 }
11321 break;
11322
11323 default:
11324 break;
11325 }
11326
11327 break;
11328 }
11329
11330 /* Now make any compound operations involved in this comparison. Then,
11331 check for an outmost SUBREG on OP0 that is not doing anything or is
11332 paradoxical. The latter transformation must only be performed when
11333 it is known that the "extra" bits will be the same in op0 and op1 or
11334 that they don't matter. There are three cases to consider:
11335
11336 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11337 care bits and we can assume they have any convenient value. So
11338 making the transformation is safe.
11339
11340 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11341 In this case the upper bits of op0 are undefined. We should not make
11342 the simplification in that case as we do not know the contents of
11343 those bits.
11344
11345 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11346 NIL. In that case we know those bits are zeros or ones. We must
11347 also be sure that they are the same as the upper bits of op1.
11348
11349 We can never remove a SUBREG for a non-equality comparison because
11350 the sign bit is in a different place in the underlying object. */
11351
11352 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11353 op1 = make_compound_operation (op1, SET);
11354
11355 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11356 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11357 implemented. */
11358 && GET_CODE (SUBREG_REG (op0)) == REG
11359 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11360 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11361 && (code == NE || code == EQ))
11362 {
11363 if (GET_MODE_SIZE (GET_MODE (op0))
11364 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11365 {
11366 op0 = SUBREG_REG (op0);
11367 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11368 }
11369 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11370 <= HOST_BITS_PER_WIDE_INT)
11371 && (nonzero_bits (SUBREG_REG (op0),
11372 GET_MODE (SUBREG_REG (op0)))
11373 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11374 {
11375 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11376
11377 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11378 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11379 op0 = SUBREG_REG (op0), op1 = tem;
11380 }
11381 }
11382
11383 /* We now do the opposite procedure: Some machines don't have compare
11384 insns in all modes. If OP0's mode is an integer mode smaller than a
11385 word and we can't do a compare in that mode, see if there is a larger
11386 mode for which we can do the compare. There are a number of cases in
11387 which we can use the wider mode. */
11388
11389 mode = GET_MODE (op0);
11390 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11391 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11392 && ! have_insn_for (COMPARE, mode))
11393 for (tmode = GET_MODE_WIDER_MODE (mode);
11394 (tmode != VOIDmode
11395 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11396 tmode = GET_MODE_WIDER_MODE (tmode))
11397 if (have_insn_for (COMPARE, tmode))
11398 {
11399 int zero_extended;
11400
11401 /* If the only nonzero bits in OP0 and OP1 are those in the
11402 narrower mode and this is an equality or unsigned comparison,
11403 we can use the wider mode. Similarly for sign-extended
11404 values, in which case it is true for all comparisons. */
11405 zero_extended = ((code == EQ || code == NE
11406 || code == GEU || code == GTU
11407 || code == LEU || code == LTU)
11408 && (nonzero_bits (op0, tmode)
11409 & ~GET_MODE_MASK (mode)) == 0
11410 && ((GET_CODE (op1) == CONST_INT
11411 || (nonzero_bits (op1, tmode)
11412 & ~GET_MODE_MASK (mode)) == 0)));
11413
11414 if (zero_extended
11415 || ((num_sign_bit_copies (op0, tmode)
11416 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11417 - GET_MODE_BITSIZE (mode)))
11418 && (num_sign_bit_copies (op1, tmode)
11419 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11420 - GET_MODE_BITSIZE (mode)))))
11421 {
11422 /* If OP0 is an AND and we don't have an AND in MODE either,
11423 make a new AND in the proper mode. */
11424 if (GET_CODE (op0) == AND
11425 && !have_insn_for (AND, mode))
11426 op0 = gen_binary (AND, tmode,
11427 gen_lowpart_for_combine (tmode,
11428 XEXP (op0, 0)),
11429 gen_lowpart_for_combine (tmode,
11430 XEXP (op0, 1)));
11431
11432 op0 = gen_lowpart_for_combine (tmode, op0);
11433 if (zero_extended && GET_CODE (op1) == CONST_INT)
11434 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11435 op1 = gen_lowpart_for_combine (tmode, op1);
11436 break;
11437 }
11438
11439 /* If this is a test for negative, we can make an explicit
11440 test of the sign bit. */
11441
11442 if (op1 == const0_rtx && (code == LT || code == GE)
11443 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11444 {
11445 op0 = gen_binary (AND, tmode,
11446 gen_lowpart_for_combine (tmode, op0),
11447 GEN_INT ((HOST_WIDE_INT) 1
11448 << (GET_MODE_BITSIZE (mode) - 1)));
11449 code = (code == LT) ? NE : EQ;
11450 break;
11451 }
11452 }
11453
11454 #ifdef CANONICALIZE_COMPARISON
11455 /* If this machine only supports a subset of valid comparisons, see if we
11456 can convert an unsupported one into a supported one. */
11457 CANONICALIZE_COMPARISON (code, op0, op1);
11458 #endif
11459
11460 *pop0 = op0;
11461 *pop1 = op1;
11462
11463 return code;
11464 }
11465 \f
11466 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11467 searching backward. */
11468 static enum rtx_code
11469 combine_reversed_comparison_code (exp)
11470 rtx exp;
11471 {
11472 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11473 rtx x;
11474
11475 if (code1 != UNKNOWN
11476 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11477 return code1;
11478 /* Otherwise try and find where the condition codes were last set and
11479 use that. */
11480 x = get_last_value (XEXP (exp, 0));
11481 if (!x || GET_CODE (x) != COMPARE)
11482 return UNKNOWN;
11483 return reversed_comparison_code_parts (GET_CODE (exp),
11484 XEXP (x, 0), XEXP (x, 1), NULL);
11485 }
11486
11487 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11488 Return NULL_RTX in case we fail to do the reversal. */
11489 static rtx
11490 reversed_comparison (exp, mode, op0, op1)
11491 rtx exp, op0, op1;
11492 enum machine_mode mode;
11493 {
11494 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11495 if (reversed_code == UNKNOWN)
11496 return NULL_RTX;
11497 else
11498 return gen_binary (reversed_code, mode, op0, op1);
11499 }
11500 \f
11501 /* Utility function for following routine. Called when X is part of a value
11502 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11503 for each register mentioned. Similar to mention_regs in cse.c */
11504
11505 static void
11506 update_table_tick (x)
11507 rtx x;
11508 {
11509 enum rtx_code code = GET_CODE (x);
11510 const char *fmt = GET_RTX_FORMAT (code);
11511 int i;
11512
11513 if (code == REG)
11514 {
11515 unsigned int regno = REGNO (x);
11516 unsigned int endregno
11517 = regno + (regno < FIRST_PSEUDO_REGISTER
11518 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11519 unsigned int r;
11520
11521 for (r = regno; r < endregno; r++)
11522 reg_last_set_table_tick[r] = label_tick;
11523
11524 return;
11525 }
11526
11527 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11528 /* Note that we can't have an "E" in values stored; see
11529 get_last_value_validate. */
11530 if (fmt[i] == 'e')
11531 {
11532 /* Check for identical subexpressions. If x contains
11533 identical subexpression we only have to traverse one of
11534 them. */
11535 if (i == 0
11536 && (GET_RTX_CLASS (code) == '2'
11537 || GET_RTX_CLASS (code) == 'c'))
11538 {
11539 /* Note that at this point x1 has already been
11540 processed. */
11541 rtx x0 = XEXP (x, 0);
11542 rtx x1 = XEXP (x, 1);
11543
11544 /* If x0 and x1 are identical then there is no need to
11545 process x0. */
11546 if (x0 == x1)
11547 break;
11548
11549 /* If x0 is identical to a subexpression of x1 then while
11550 processing x1, x0 has already been processed. Thus we
11551 are done with x. */
11552 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11553 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11554 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11555 break;
11556
11557 /* If x1 is identical to a subexpression of x0 then we
11558 still have to process the rest of x0. */
11559 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11560 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11561 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11562 {
11563 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11564 break;
11565 }
11566 }
11567
11568 update_table_tick (XEXP (x, i));
11569 }
11570 }
11571
11572 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11573 are saying that the register is clobbered and we no longer know its
11574 value. If INSN is zero, don't update reg_last_set; this is only permitted
11575 with VALUE also zero and is used to invalidate the register. */
11576
11577 static void
11578 record_value_for_reg (reg, insn, value)
11579 rtx reg;
11580 rtx insn;
11581 rtx value;
11582 {
11583 unsigned int regno = REGNO (reg);
11584 unsigned int endregno
11585 = regno + (regno < FIRST_PSEUDO_REGISTER
11586 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11587 unsigned int i;
11588
11589 /* If VALUE contains REG and we have a previous value for REG, substitute
11590 the previous value. */
11591 if (value && insn && reg_overlap_mentioned_p (reg, value))
11592 {
11593 rtx tem;
11594
11595 /* Set things up so get_last_value is allowed to see anything set up to
11596 our insn. */
11597 subst_low_cuid = INSN_CUID (insn);
11598 tem = get_last_value (reg);
11599
11600 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11601 it isn't going to be useful and will take a lot of time to process,
11602 so just use the CLOBBER. */
11603
11604 if (tem)
11605 {
11606 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11607 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11608 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11609 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11610 tem = XEXP (tem, 0);
11611
11612 value = replace_rtx (copy_rtx (value), reg, tem);
11613 }
11614 }
11615
11616 /* For each register modified, show we don't know its value, that
11617 we don't know about its bitwise content, that its value has been
11618 updated, and that we don't know the location of the death of the
11619 register. */
11620 for (i = regno; i < endregno; i++)
11621 {
11622 if (insn)
11623 reg_last_set[i] = insn;
11624
11625 reg_last_set_value[i] = 0;
11626 reg_last_set_mode[i] = 0;
11627 reg_last_set_nonzero_bits[i] = 0;
11628 reg_last_set_sign_bit_copies[i] = 0;
11629 reg_last_death[i] = 0;
11630 }
11631
11632 /* Mark registers that are being referenced in this value. */
11633 if (value)
11634 update_table_tick (value);
11635
11636 /* Now update the status of each register being set.
11637 If someone is using this register in this block, set this register
11638 to invalid since we will get confused between the two lives in this
11639 basic block. This makes using this register always invalid. In cse, we
11640 scan the table to invalidate all entries using this register, but this
11641 is too much work for us. */
11642
11643 for (i = regno; i < endregno; i++)
11644 {
11645 reg_last_set_label[i] = label_tick;
11646 if (value && reg_last_set_table_tick[i] == label_tick)
11647 reg_last_set_invalid[i] = 1;
11648 else
11649 reg_last_set_invalid[i] = 0;
11650 }
11651
11652 /* The value being assigned might refer to X (like in "x++;"). In that
11653 case, we must replace it with (clobber (const_int 0)) to prevent
11654 infinite loops. */
11655 if (value && ! get_last_value_validate (&value, insn,
11656 reg_last_set_label[regno], 0))
11657 {
11658 value = copy_rtx (value);
11659 if (! get_last_value_validate (&value, insn,
11660 reg_last_set_label[regno], 1))
11661 value = 0;
11662 }
11663
11664 /* For the main register being modified, update the value, the mode, the
11665 nonzero bits, and the number of sign bit copies. */
11666
11667 reg_last_set_value[regno] = value;
11668
11669 if (value)
11670 {
11671 enum machine_mode mode = GET_MODE (reg);
11672 subst_low_cuid = INSN_CUID (insn);
11673 reg_last_set_mode[regno] = mode;
11674 if (GET_MODE_CLASS (mode) == MODE_INT
11675 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11676 mode = nonzero_bits_mode;
11677 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11678 reg_last_set_sign_bit_copies[regno]
11679 = num_sign_bit_copies (value, GET_MODE (reg));
11680 }
11681 }
11682
11683 /* Called via note_stores from record_dead_and_set_regs to handle one
11684 SET or CLOBBER in an insn. DATA is the instruction in which the
11685 set is occurring. */
11686
11687 static void
11688 record_dead_and_set_regs_1 (dest, setter, data)
11689 rtx dest, setter;
11690 void *data;
11691 {
11692 rtx record_dead_insn = (rtx) data;
11693
11694 if (GET_CODE (dest) == SUBREG)
11695 dest = SUBREG_REG (dest);
11696
11697 if (GET_CODE (dest) == REG)
11698 {
11699 /* If we are setting the whole register, we know its value. Otherwise
11700 show that we don't know the value. We can handle SUBREG in
11701 some cases. */
11702 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11703 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11704 else if (GET_CODE (setter) == SET
11705 && GET_CODE (SET_DEST (setter)) == SUBREG
11706 && SUBREG_REG (SET_DEST (setter)) == dest
11707 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11708 && subreg_lowpart_p (SET_DEST (setter)))
11709 record_value_for_reg (dest, record_dead_insn,
11710 gen_lowpart_for_combine (GET_MODE (dest),
11711 SET_SRC (setter)));
11712 else
11713 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11714 }
11715 else if (GET_CODE (dest) == MEM
11716 /* Ignore pushes, they clobber nothing. */
11717 && ! push_operand (dest, GET_MODE (dest)))
11718 mem_last_set = INSN_CUID (record_dead_insn);
11719 }
11720
11721 /* Update the records of when each REG was most recently set or killed
11722 for the things done by INSN. This is the last thing done in processing
11723 INSN in the combiner loop.
11724
11725 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11726 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11727 and also the similar information mem_last_set (which insn most recently
11728 modified memory) and last_call_cuid (which insn was the most recent
11729 subroutine call). */
11730
11731 static void
11732 record_dead_and_set_regs (insn)
11733 rtx insn;
11734 {
11735 rtx link;
11736 unsigned int i;
11737
11738 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11739 {
11740 if (REG_NOTE_KIND (link) == REG_DEAD
11741 && GET_CODE (XEXP (link, 0)) == REG)
11742 {
11743 unsigned int regno = REGNO (XEXP (link, 0));
11744 unsigned int endregno
11745 = regno + (regno < FIRST_PSEUDO_REGISTER
11746 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11747 : 1);
11748
11749 for (i = regno; i < endregno; i++)
11750 reg_last_death[i] = insn;
11751 }
11752 else if (REG_NOTE_KIND (link) == REG_INC)
11753 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11754 }
11755
11756 if (GET_CODE (insn) == CALL_INSN)
11757 {
11758 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11759 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11760 {
11761 reg_last_set_value[i] = 0;
11762 reg_last_set_mode[i] = 0;
11763 reg_last_set_nonzero_bits[i] = 0;
11764 reg_last_set_sign_bit_copies[i] = 0;
11765 reg_last_death[i] = 0;
11766 }
11767
11768 last_call_cuid = mem_last_set = INSN_CUID (insn);
11769
11770 /* Don't bother recording what this insn does. It might set the
11771 return value register, but we can't combine into a call
11772 pattern anyway, so there's no point trying (and it may cause
11773 a crash, if e.g. we wind up asking for last_set_value of a
11774 SUBREG of the return value register). */
11775 return;
11776 }
11777
11778 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11779 }
11780
11781 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11782 register present in the SUBREG, so for each such SUBREG go back and
11783 adjust nonzero and sign bit information of the registers that are
11784 known to have some zero/sign bits set.
11785
11786 This is needed because when combine blows the SUBREGs away, the
11787 information on zero/sign bits is lost and further combines can be
11788 missed because of that. */
11789
11790 static void
11791 record_promoted_value (insn, subreg)
11792 rtx insn;
11793 rtx subreg;
11794 {
11795 rtx links, set;
11796 unsigned int regno = REGNO (SUBREG_REG (subreg));
11797 enum machine_mode mode = GET_MODE (subreg);
11798
11799 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11800 return;
11801
11802 for (links = LOG_LINKS (insn); links;)
11803 {
11804 insn = XEXP (links, 0);
11805 set = single_set (insn);
11806
11807 if (! set || GET_CODE (SET_DEST (set)) != REG
11808 || REGNO (SET_DEST (set)) != regno
11809 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11810 {
11811 links = XEXP (links, 1);
11812 continue;
11813 }
11814
11815 if (reg_last_set[regno] == insn)
11816 {
11817 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11818 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11819 }
11820
11821 if (GET_CODE (SET_SRC (set)) == REG)
11822 {
11823 regno = REGNO (SET_SRC (set));
11824 links = LOG_LINKS (insn);
11825 }
11826 else
11827 break;
11828 }
11829 }
11830
11831 /* Scan X for promoted SUBREGs. For each one found,
11832 note what it implies to the registers used in it. */
11833
11834 static void
11835 check_promoted_subreg (insn, x)
11836 rtx insn;
11837 rtx x;
11838 {
11839 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11840 && GET_CODE (SUBREG_REG (x)) == REG)
11841 record_promoted_value (insn, x);
11842 else
11843 {
11844 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11845 int i, j;
11846
11847 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11848 switch (format[i])
11849 {
11850 case 'e':
11851 check_promoted_subreg (insn, XEXP (x, i));
11852 break;
11853 case 'V':
11854 case 'E':
11855 if (XVEC (x, i) != 0)
11856 for (j = 0; j < XVECLEN (x, i); j++)
11857 check_promoted_subreg (insn, XVECEXP (x, i, j));
11858 break;
11859 }
11860 }
11861 }
11862 \f
11863 /* Utility routine for the following function. Verify that all the registers
11864 mentioned in *LOC are valid when *LOC was part of a value set when
11865 label_tick == TICK. Return 0 if some are not.
11866
11867 If REPLACE is nonzero, replace the invalid reference with
11868 (clobber (const_int 0)) and return 1. This replacement is useful because
11869 we often can get useful information about the form of a value (e.g., if
11870 it was produced by a shift that always produces -1 or 0) even though
11871 we don't know exactly what registers it was produced from. */
11872
11873 static int
11874 get_last_value_validate (loc, insn, tick, replace)
11875 rtx *loc;
11876 rtx insn;
11877 int tick;
11878 int replace;
11879 {
11880 rtx x = *loc;
11881 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11882 int len = GET_RTX_LENGTH (GET_CODE (x));
11883 int i;
11884
11885 if (GET_CODE (x) == REG)
11886 {
11887 unsigned int regno = REGNO (x);
11888 unsigned int endregno
11889 = regno + (regno < FIRST_PSEUDO_REGISTER
11890 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11891 unsigned int j;
11892
11893 for (j = regno; j < endregno; j++)
11894 if (reg_last_set_invalid[j]
11895 /* If this is a pseudo-register that was only set once and not
11896 live at the beginning of the function, it is always valid. */
11897 || (! (regno >= FIRST_PSEUDO_REGISTER
11898 && REG_N_SETS (regno) == 1
11899 && (! REGNO_REG_SET_P
11900 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11901 && reg_last_set_label[j] > tick))
11902 {
11903 if (replace)
11904 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11905 return replace;
11906 }
11907
11908 return 1;
11909 }
11910 /* If this is a memory reference, make sure that there were
11911 no stores after it that might have clobbered the value. We don't
11912 have alias info, so we assume any store invalidates it. */
11913 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11914 && INSN_CUID (insn) <= mem_last_set)
11915 {
11916 if (replace)
11917 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11918 return replace;
11919 }
11920
11921 for (i = 0; i < len; i++)
11922 {
11923 if (fmt[i] == 'e')
11924 {
11925 /* Check for identical subexpressions. If x contains
11926 identical subexpression we only have to traverse one of
11927 them. */
11928 if (i == 1
11929 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11930 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11931 {
11932 /* Note that at this point x0 has already been checked
11933 and found valid. */
11934 rtx x0 = XEXP (x, 0);
11935 rtx x1 = XEXP (x, 1);
11936
11937 /* If x0 and x1 are identical then x is also valid. */
11938 if (x0 == x1)
11939 return 1;
11940
11941 /* If x1 is identical to a subexpression of x0 then
11942 while checking x0, x1 has already been checked. Thus
11943 it is valid and so as x. */
11944 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11945 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11946 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11947 return 1;
11948
11949 /* If x0 is identical to a subexpression of x1 then x is
11950 valid iff the rest of x1 is valid. */
11951 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11952 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11953 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11954 return
11955 get_last_value_validate (&XEXP (x1,
11956 x0 == XEXP (x1, 0) ? 1 : 0),
11957 insn, tick, replace);
11958 }
11959
11960 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11961 replace) == 0)
11962 return 0;
11963 }
11964 /* Don't bother with these. They shouldn't occur anyway. */
11965 else if (fmt[i] == 'E')
11966 return 0;
11967 }
11968
11969 /* If we haven't found a reason for it to be invalid, it is valid. */
11970 return 1;
11971 }
11972
11973 /* Get the last value assigned to X, if known. Some registers
11974 in the value may be replaced with (clobber (const_int 0)) if their value
11975 is known longer known reliably. */
11976
11977 static rtx
11978 get_last_value (x)
11979 rtx x;
11980 {
11981 unsigned int regno;
11982 rtx value;
11983
11984 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11985 then convert it to the desired mode. If this is a paradoxical SUBREG,
11986 we cannot predict what values the "extra" bits might have. */
11987 if (GET_CODE (x) == SUBREG
11988 && subreg_lowpart_p (x)
11989 && (GET_MODE_SIZE (GET_MODE (x))
11990 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11991 && (value = get_last_value (SUBREG_REG (x))) != 0)
11992 return gen_lowpart_for_combine (GET_MODE (x), value);
11993
11994 if (GET_CODE (x) != REG)
11995 return 0;
11996
11997 regno = REGNO (x);
11998 value = reg_last_set_value[regno];
11999
12000 /* If we don't have a value, or if it isn't for this basic block and
12001 it's either a hard register, set more than once, or it's a live
12002 at the beginning of the function, return 0.
12003
12004 Because if it's not live at the beginning of the function then the reg
12005 is always set before being used (is never used without being set).
12006 And, if it's set only once, and it's always set before use, then all
12007 uses must have the same last value, even if it's not from this basic
12008 block. */
12009
12010 if (value == 0
12011 || (reg_last_set_label[regno] != label_tick
12012 && (regno < FIRST_PSEUDO_REGISTER
12013 || REG_N_SETS (regno) != 1
12014 || (REGNO_REG_SET_P
12015 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
12016 return 0;
12017
12018 /* If the value was set in a later insn than the ones we are processing,
12019 we can't use it even if the register was only set once. */
12020 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
12021 return 0;
12022
12023 /* If the value has all its registers valid, return it. */
12024 if (get_last_value_validate (&value, reg_last_set[regno],
12025 reg_last_set_label[regno], 0))
12026 return value;
12027
12028 /* Otherwise, make a copy and replace any invalid register with
12029 (clobber (const_int 0)). If that fails for some reason, return 0. */
12030
12031 value = copy_rtx (value);
12032 if (get_last_value_validate (&value, reg_last_set[regno],
12033 reg_last_set_label[regno], 1))
12034 return value;
12035
12036 return 0;
12037 }
12038 \f
12039 /* Return nonzero if expression X refers to a REG or to memory
12040 that is set in an instruction more recent than FROM_CUID. */
12041
12042 static int
12043 use_crosses_set_p (x, from_cuid)
12044 rtx x;
12045 int from_cuid;
12046 {
12047 const char *fmt;
12048 int i;
12049 enum rtx_code code = GET_CODE (x);
12050
12051 if (code == REG)
12052 {
12053 unsigned int regno = REGNO (x);
12054 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
12055 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12056
12057 #ifdef PUSH_ROUNDING
12058 /* Don't allow uses of the stack pointer to be moved,
12059 because we don't know whether the move crosses a push insn. */
12060 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12061 return 1;
12062 #endif
12063 for (; regno < endreg; regno++)
12064 if (reg_last_set[regno]
12065 && INSN_CUID (reg_last_set[regno]) > from_cuid)
12066 return 1;
12067 return 0;
12068 }
12069
12070 if (code == MEM && mem_last_set > from_cuid)
12071 return 1;
12072
12073 fmt = GET_RTX_FORMAT (code);
12074
12075 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12076 {
12077 if (fmt[i] == 'E')
12078 {
12079 int j;
12080 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12081 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
12082 return 1;
12083 }
12084 else if (fmt[i] == 'e'
12085 && use_crosses_set_p (XEXP (x, i), from_cuid))
12086 return 1;
12087 }
12088 return 0;
12089 }
12090 \f
12091 /* Define three variables used for communication between the following
12092 routines. */
12093
12094 static unsigned int reg_dead_regno, reg_dead_endregno;
12095 static int reg_dead_flag;
12096
12097 /* Function called via note_stores from reg_dead_at_p.
12098
12099 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12100 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12101
12102 static void
12103 reg_dead_at_p_1 (dest, x, data)
12104 rtx dest;
12105 rtx x;
12106 void *data ATTRIBUTE_UNUSED;
12107 {
12108 unsigned int regno, endregno;
12109
12110 if (GET_CODE (dest) != REG)
12111 return;
12112
12113 regno = REGNO (dest);
12114 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
12115 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
12116
12117 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12118 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12119 }
12120
12121 /* Return nonzero if REG is known to be dead at INSN.
12122
12123 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12124 referencing REG, it is dead. If we hit a SET referencing REG, it is
12125 live. Otherwise, see if it is live or dead at the start of the basic
12126 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12127 must be assumed to be always live. */
12128
12129 static int
12130 reg_dead_at_p (reg, insn)
12131 rtx reg;
12132 rtx insn;
12133 {
12134 basic_block block;
12135 unsigned int i;
12136
12137 /* Set variables for reg_dead_at_p_1. */
12138 reg_dead_regno = REGNO (reg);
12139 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12140 ? HARD_REGNO_NREGS (reg_dead_regno,
12141 GET_MODE (reg))
12142 : 1);
12143
12144 reg_dead_flag = 0;
12145
12146 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12147 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12148 {
12149 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12150 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12151 return 0;
12152 }
12153
12154 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12155 beginning of function. */
12156 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12157 insn = prev_nonnote_insn (insn))
12158 {
12159 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12160 if (reg_dead_flag)
12161 return reg_dead_flag == 1 ? 1 : 0;
12162
12163 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12164 return 1;
12165 }
12166
12167 /* Get the basic block that we were in. */
12168 if (insn == 0)
12169 block = ENTRY_BLOCK_PTR->next_bb;
12170 else
12171 {
12172 FOR_EACH_BB (block)
12173 if (insn == block->head)
12174 break;
12175
12176 if (block == EXIT_BLOCK_PTR)
12177 return 0;
12178 }
12179
12180 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12181 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12182 return 0;
12183
12184 return 1;
12185 }
12186 \f
12187 /* Note hard registers in X that are used. This code is similar to
12188 that in flow.c, but much simpler since we don't care about pseudos. */
12189
12190 static void
12191 mark_used_regs_combine (x)
12192 rtx x;
12193 {
12194 RTX_CODE code = GET_CODE (x);
12195 unsigned int regno;
12196 int i;
12197
12198 switch (code)
12199 {
12200 case LABEL_REF:
12201 case SYMBOL_REF:
12202 case CONST_INT:
12203 case CONST:
12204 case CONST_DOUBLE:
12205 case CONST_VECTOR:
12206 case PC:
12207 case ADDR_VEC:
12208 case ADDR_DIFF_VEC:
12209 case ASM_INPUT:
12210 #ifdef HAVE_cc0
12211 /* CC0 must die in the insn after it is set, so we don't need to take
12212 special note of it here. */
12213 case CC0:
12214 #endif
12215 return;
12216
12217 case CLOBBER:
12218 /* If we are clobbering a MEM, mark any hard registers inside the
12219 address as used. */
12220 if (GET_CODE (XEXP (x, 0)) == MEM)
12221 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12222 return;
12223
12224 case REG:
12225 regno = REGNO (x);
12226 /* A hard reg in a wide mode may really be multiple registers.
12227 If so, mark all of them just like the first. */
12228 if (regno < FIRST_PSEUDO_REGISTER)
12229 {
12230 unsigned int endregno, r;
12231
12232 /* None of this applies to the stack, frame or arg pointers. */
12233 if (regno == STACK_POINTER_REGNUM
12234 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12235 || regno == HARD_FRAME_POINTER_REGNUM
12236 #endif
12237 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12238 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12239 #endif
12240 || regno == FRAME_POINTER_REGNUM)
12241 return;
12242
12243 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12244 for (r = regno; r < endregno; r++)
12245 SET_HARD_REG_BIT (newpat_used_regs, r);
12246 }
12247 return;
12248
12249 case SET:
12250 {
12251 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12252 the address. */
12253 rtx testreg = SET_DEST (x);
12254
12255 while (GET_CODE (testreg) == SUBREG
12256 || GET_CODE (testreg) == ZERO_EXTRACT
12257 || GET_CODE (testreg) == SIGN_EXTRACT
12258 || GET_CODE (testreg) == STRICT_LOW_PART)
12259 testreg = XEXP (testreg, 0);
12260
12261 if (GET_CODE (testreg) == MEM)
12262 mark_used_regs_combine (XEXP (testreg, 0));
12263
12264 mark_used_regs_combine (SET_SRC (x));
12265 }
12266 return;
12267
12268 default:
12269 break;
12270 }
12271
12272 /* Recursively scan the operands of this expression. */
12273
12274 {
12275 const char *fmt = GET_RTX_FORMAT (code);
12276
12277 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12278 {
12279 if (fmt[i] == 'e')
12280 mark_used_regs_combine (XEXP (x, i));
12281 else if (fmt[i] == 'E')
12282 {
12283 int j;
12284
12285 for (j = 0; j < XVECLEN (x, i); j++)
12286 mark_used_regs_combine (XVECEXP (x, i, j));
12287 }
12288 }
12289 }
12290 }
12291 \f
12292 /* Remove register number REGNO from the dead registers list of INSN.
12293
12294 Return the note used to record the death, if there was one. */
12295
12296 rtx
12297 remove_death (regno, insn)
12298 unsigned int regno;
12299 rtx insn;
12300 {
12301 rtx note = find_regno_note (insn, REG_DEAD, regno);
12302
12303 if (note)
12304 {
12305 REG_N_DEATHS (regno)--;
12306 remove_note (insn, note);
12307 }
12308
12309 return note;
12310 }
12311
12312 /* For each register (hardware or pseudo) used within expression X, if its
12313 death is in an instruction with cuid between FROM_CUID (inclusive) and
12314 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12315 list headed by PNOTES.
12316
12317 That said, don't move registers killed by maybe_kill_insn.
12318
12319 This is done when X is being merged by combination into TO_INSN. These
12320 notes will then be distributed as needed. */
12321
12322 static void
12323 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
12324 rtx x;
12325 rtx maybe_kill_insn;
12326 int from_cuid;
12327 rtx to_insn;
12328 rtx *pnotes;
12329 {
12330 const char *fmt;
12331 int len, i;
12332 enum rtx_code code = GET_CODE (x);
12333
12334 if (code == REG)
12335 {
12336 unsigned int regno = REGNO (x);
12337 rtx where_dead = reg_last_death[regno];
12338 rtx before_dead, after_dead;
12339
12340 /* Don't move the register if it gets killed in between from and to. */
12341 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12342 && ! reg_referenced_p (x, maybe_kill_insn))
12343 return;
12344
12345 /* WHERE_DEAD could be a USE insn made by combine, so first we
12346 make sure that we have insns with valid INSN_CUID values. */
12347 before_dead = where_dead;
12348 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12349 before_dead = PREV_INSN (before_dead);
12350
12351 after_dead = where_dead;
12352 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12353 after_dead = NEXT_INSN (after_dead);
12354
12355 if (before_dead && after_dead
12356 && INSN_CUID (before_dead) >= from_cuid
12357 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12358 || (where_dead != after_dead
12359 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12360 {
12361 rtx note = remove_death (regno, where_dead);
12362
12363 /* It is possible for the call above to return 0. This can occur
12364 when reg_last_death points to I2 or I1 that we combined with.
12365 In that case make a new note.
12366
12367 We must also check for the case where X is a hard register
12368 and NOTE is a death note for a range of hard registers
12369 including X. In that case, we must put REG_DEAD notes for
12370 the remaining registers in place of NOTE. */
12371
12372 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12373 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12374 > GET_MODE_SIZE (GET_MODE (x))))
12375 {
12376 unsigned int deadregno = REGNO (XEXP (note, 0));
12377 unsigned int deadend
12378 = (deadregno + HARD_REGNO_NREGS (deadregno,
12379 GET_MODE (XEXP (note, 0))));
12380 unsigned int ourend
12381 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12382 unsigned int i;
12383
12384 for (i = deadregno; i < deadend; i++)
12385 if (i < regno || i >= ourend)
12386 REG_NOTES (where_dead)
12387 = gen_rtx_EXPR_LIST (REG_DEAD,
12388 regno_reg_rtx[i],
12389 REG_NOTES (where_dead));
12390 }
12391
12392 /* If we didn't find any note, or if we found a REG_DEAD note that
12393 covers only part of the given reg, and we have a multi-reg hard
12394 register, then to be safe we must check for REG_DEAD notes
12395 for each register other than the first. They could have
12396 their own REG_DEAD notes lying around. */
12397 else if ((note == 0
12398 || (note != 0
12399 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12400 < GET_MODE_SIZE (GET_MODE (x)))))
12401 && regno < FIRST_PSEUDO_REGISTER
12402 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12403 {
12404 unsigned int ourend
12405 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12406 unsigned int i, offset;
12407 rtx oldnotes = 0;
12408
12409 if (note)
12410 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12411 else
12412 offset = 1;
12413
12414 for (i = regno + offset; i < ourend; i++)
12415 move_deaths (regno_reg_rtx[i],
12416 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12417 }
12418
12419 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12420 {
12421 XEXP (note, 1) = *pnotes;
12422 *pnotes = note;
12423 }
12424 else
12425 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12426
12427 REG_N_DEATHS (regno)++;
12428 }
12429
12430 return;
12431 }
12432
12433 else if (GET_CODE (x) == SET)
12434 {
12435 rtx dest = SET_DEST (x);
12436
12437 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12438
12439 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12440 that accesses one word of a multi-word item, some
12441 piece of everything register in the expression is used by
12442 this insn, so remove any old death. */
12443 /* ??? So why do we test for equality of the sizes? */
12444
12445 if (GET_CODE (dest) == ZERO_EXTRACT
12446 || GET_CODE (dest) == STRICT_LOW_PART
12447 || (GET_CODE (dest) == SUBREG
12448 && (((GET_MODE_SIZE (GET_MODE (dest))
12449 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12450 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12451 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12452 {
12453 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12454 return;
12455 }
12456
12457 /* If this is some other SUBREG, we know it replaces the entire
12458 value, so use that as the destination. */
12459 if (GET_CODE (dest) == SUBREG)
12460 dest = SUBREG_REG (dest);
12461
12462 /* If this is a MEM, adjust deaths of anything used in the address.
12463 For a REG (the only other possibility), the entire value is
12464 being replaced so the old value is not used in this insn. */
12465
12466 if (GET_CODE (dest) == MEM)
12467 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12468 to_insn, pnotes);
12469 return;
12470 }
12471
12472 else if (GET_CODE (x) == CLOBBER)
12473 return;
12474
12475 len = GET_RTX_LENGTH (code);
12476 fmt = GET_RTX_FORMAT (code);
12477
12478 for (i = 0; i < len; i++)
12479 {
12480 if (fmt[i] == 'E')
12481 {
12482 int j;
12483 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12484 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12485 to_insn, pnotes);
12486 }
12487 else if (fmt[i] == 'e')
12488 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12489 }
12490 }
12491 \f
12492 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12493 pattern of an insn. X must be a REG. */
12494
12495 static int
12496 reg_bitfield_target_p (x, body)
12497 rtx x;
12498 rtx body;
12499 {
12500 int i;
12501
12502 if (GET_CODE (body) == SET)
12503 {
12504 rtx dest = SET_DEST (body);
12505 rtx target;
12506 unsigned int regno, tregno, endregno, endtregno;
12507
12508 if (GET_CODE (dest) == ZERO_EXTRACT)
12509 target = XEXP (dest, 0);
12510 else if (GET_CODE (dest) == STRICT_LOW_PART)
12511 target = SUBREG_REG (XEXP (dest, 0));
12512 else
12513 return 0;
12514
12515 if (GET_CODE (target) == SUBREG)
12516 target = SUBREG_REG (target);
12517
12518 if (GET_CODE (target) != REG)
12519 return 0;
12520
12521 tregno = REGNO (target), regno = REGNO (x);
12522 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12523 return target == x;
12524
12525 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12526 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12527
12528 return endregno > tregno && regno < endtregno;
12529 }
12530
12531 else if (GET_CODE (body) == PARALLEL)
12532 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12533 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12534 return 1;
12535
12536 return 0;
12537 }
12538 \f
12539 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12540 as appropriate. I3 and I2 are the insns resulting from the combination
12541 insns including FROM (I2 may be zero).
12542
12543 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12544 not need REG_DEAD notes because they are being substituted for. This
12545 saves searching in the most common cases.
12546
12547 Each note in the list is either ignored or placed on some insns, depending
12548 on the type of note. */
12549
12550 static void
12551 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12552 rtx notes;
12553 rtx from_insn;
12554 rtx i3, i2;
12555 rtx elim_i2, elim_i1;
12556 {
12557 rtx note, next_note;
12558 rtx tem;
12559
12560 for (note = notes; note; note = next_note)
12561 {
12562 rtx place = 0, place2 = 0;
12563
12564 /* If this NOTE references a pseudo register, ensure it references
12565 the latest copy of that register. */
12566 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12567 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12568 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12569
12570 next_note = XEXP (note, 1);
12571 switch (REG_NOTE_KIND (note))
12572 {
12573 case REG_BR_PROB:
12574 case REG_BR_PRED:
12575 /* Doesn't matter much where we put this, as long as it's somewhere.
12576 It is preferable to keep these notes on branches, which is most
12577 likely to be i3. */
12578 place = i3;
12579 break;
12580
12581 case REG_VTABLE_REF:
12582 /* ??? Should remain with *a particular* memory load. Given the
12583 nature of vtable data, the last insn seems relatively safe. */
12584 place = i3;
12585 break;
12586
12587 case REG_NON_LOCAL_GOTO:
12588 if (GET_CODE (i3) == JUMP_INSN)
12589 place = i3;
12590 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12591 place = i2;
12592 else
12593 abort ();
12594 break;
12595
12596 case REG_EH_REGION:
12597 /* These notes must remain with the call or trapping instruction. */
12598 if (GET_CODE (i3) == CALL_INSN)
12599 place = i3;
12600 else if (i2 && GET_CODE (i2) == CALL_INSN)
12601 place = i2;
12602 else if (flag_non_call_exceptions)
12603 {
12604 if (may_trap_p (i3))
12605 place = i3;
12606 else if (i2 && may_trap_p (i2))
12607 place = i2;
12608 /* ??? Otherwise assume we've combined things such that we
12609 can now prove that the instructions can't trap. Drop the
12610 note in this case. */
12611 }
12612 else
12613 abort ();
12614 break;
12615
12616 case REG_NORETURN:
12617 case REG_SETJMP:
12618 /* These notes must remain with the call. It should not be
12619 possible for both I2 and I3 to be a call. */
12620 if (GET_CODE (i3) == CALL_INSN)
12621 place = i3;
12622 else if (i2 && GET_CODE (i2) == CALL_INSN)
12623 place = i2;
12624 else
12625 abort ();
12626 break;
12627
12628 case REG_UNUSED:
12629 /* Any clobbers for i3 may still exist, and so we must process
12630 REG_UNUSED notes from that insn.
12631
12632 Any clobbers from i2 or i1 can only exist if they were added by
12633 recog_for_combine. In that case, recog_for_combine created the
12634 necessary REG_UNUSED notes. Trying to keep any original
12635 REG_UNUSED notes from these insns can cause incorrect output
12636 if it is for the same register as the original i3 dest.
12637 In that case, we will notice that the register is set in i3,
12638 and then add a REG_UNUSED note for the destination of i3, which
12639 is wrong. However, it is possible to have REG_UNUSED notes from
12640 i2 or i1 for register which were both used and clobbered, so
12641 we keep notes from i2 or i1 if they will turn into REG_DEAD
12642 notes. */
12643
12644 /* If this register is set or clobbered in I3, put the note there
12645 unless there is one already. */
12646 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12647 {
12648 if (from_insn != i3)
12649 break;
12650
12651 if (! (GET_CODE (XEXP (note, 0)) == REG
12652 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12653 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12654 place = i3;
12655 }
12656 /* Otherwise, if this register is used by I3, then this register
12657 now dies here, so we must put a REG_DEAD note here unless there
12658 is one already. */
12659 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12660 && ! (GET_CODE (XEXP (note, 0)) == REG
12661 ? find_regno_note (i3, REG_DEAD,
12662 REGNO (XEXP (note, 0)))
12663 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12664 {
12665 PUT_REG_NOTE_KIND (note, REG_DEAD);
12666 place = i3;
12667 }
12668 break;
12669
12670 case REG_EQUAL:
12671 case REG_EQUIV:
12672 case REG_NOALIAS:
12673 /* These notes say something about results of an insn. We can
12674 only support them if they used to be on I3 in which case they
12675 remain on I3. Otherwise they are ignored.
12676
12677 If the note refers to an expression that is not a constant, we
12678 must also ignore the note since we cannot tell whether the
12679 equivalence is still true. It might be possible to do
12680 slightly better than this (we only have a problem if I2DEST
12681 or I1DEST is present in the expression), but it doesn't
12682 seem worth the trouble. */
12683
12684 if (from_insn == i3
12685 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12686 place = i3;
12687 break;
12688
12689 case REG_INC:
12690 case REG_NO_CONFLICT:
12691 /* These notes say something about how a register is used. They must
12692 be present on any use of the register in I2 or I3. */
12693 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12694 place = i3;
12695
12696 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12697 {
12698 if (place)
12699 place2 = i2;
12700 else
12701 place = i2;
12702 }
12703 break;
12704
12705 case REG_LABEL:
12706 /* This can show up in several ways -- either directly in the
12707 pattern, or hidden off in the constant pool with (or without?)
12708 a REG_EQUAL note. */
12709 /* ??? Ignore the without-reg_equal-note problem for now. */
12710 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12711 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12712 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12713 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12714 place = i3;
12715
12716 if (i2
12717 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12718 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12719 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12720 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12721 {
12722 if (place)
12723 place2 = i2;
12724 else
12725 place = i2;
12726 }
12727
12728 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12729 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12730 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12731 {
12732 if (JUMP_LABEL (place) != XEXP (note, 0))
12733 abort ();
12734 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12735 LABEL_NUSES (JUMP_LABEL (place))--;
12736 place = 0;
12737 }
12738 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12739 {
12740 if (JUMP_LABEL (place2) != XEXP (note, 0))
12741 abort ();
12742 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12743 LABEL_NUSES (JUMP_LABEL (place2))--;
12744 place2 = 0;
12745 }
12746 break;
12747
12748 case REG_NONNEG:
12749 case REG_WAS_0:
12750 /* These notes say something about the value of a register prior
12751 to the execution of an insn. It is too much trouble to see
12752 if the note is still correct in all situations. It is better
12753 to simply delete it. */
12754 break;
12755
12756 case REG_RETVAL:
12757 /* If the insn previously containing this note still exists,
12758 put it back where it was. Otherwise move it to the previous
12759 insn. Adjust the corresponding REG_LIBCALL note. */
12760 if (GET_CODE (from_insn) != NOTE)
12761 place = from_insn;
12762 else
12763 {
12764 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12765 place = prev_real_insn (from_insn);
12766 if (tem && place)
12767 XEXP (tem, 0) = place;
12768 /* If we're deleting the last remaining instruction of a
12769 libcall sequence, don't add the notes. */
12770 else if (XEXP (note, 0) == from_insn)
12771 tem = place = 0;
12772 }
12773 break;
12774
12775 case REG_LIBCALL:
12776 /* This is handled similarly to REG_RETVAL. */
12777 if (GET_CODE (from_insn) != NOTE)
12778 place = from_insn;
12779 else
12780 {
12781 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12782 place = next_real_insn (from_insn);
12783 if (tem && place)
12784 XEXP (tem, 0) = place;
12785 /* If we're deleting the last remaining instruction of a
12786 libcall sequence, don't add the notes. */
12787 else if (XEXP (note, 0) == from_insn)
12788 tem = place = 0;
12789 }
12790 break;
12791
12792 case REG_DEAD:
12793 /* If the register is used as an input in I3, it dies there.
12794 Similarly for I2, if it is nonzero and adjacent to I3.
12795
12796 If the register is not used as an input in either I3 or I2
12797 and it is not one of the registers we were supposed to eliminate,
12798 there are two possibilities. We might have a non-adjacent I2
12799 or we might have somehow eliminated an additional register
12800 from a computation. For example, we might have had A & B where
12801 we discover that B will always be zero. In this case we will
12802 eliminate the reference to A.
12803
12804 In both cases, we must search to see if we can find a previous
12805 use of A and put the death note there. */
12806
12807 if (from_insn
12808 && GET_CODE (from_insn) == CALL_INSN
12809 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12810 place = from_insn;
12811 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12812 place = i3;
12813 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12814 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12815 place = i2;
12816
12817 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12818 || rtx_equal_p (XEXP (note, 0), elim_i1))
12819 break;
12820
12821 if (place == 0)
12822 {
12823 basic_block bb = this_basic_block;
12824
12825 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12826 {
12827 if (! INSN_P (tem))
12828 {
12829 if (tem == bb->head)
12830 break;
12831 continue;
12832 }
12833
12834 /* If the register is being set at TEM, see if that is all
12835 TEM is doing. If so, delete TEM. Otherwise, make this
12836 into a REG_UNUSED note instead. */
12837 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12838 {
12839 rtx set = single_set (tem);
12840 rtx inner_dest = 0;
12841 #ifdef HAVE_cc0
12842 rtx cc0_setter = NULL_RTX;
12843 #endif
12844
12845 if (set != 0)
12846 for (inner_dest = SET_DEST (set);
12847 (GET_CODE (inner_dest) == STRICT_LOW_PART
12848 || GET_CODE (inner_dest) == SUBREG
12849 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12850 inner_dest = XEXP (inner_dest, 0))
12851 ;
12852
12853 /* Verify that it was the set, and not a clobber that
12854 modified the register.
12855
12856 CC0 targets must be careful to maintain setter/user
12857 pairs. If we cannot delete the setter due to side
12858 effects, mark the user with an UNUSED note instead
12859 of deleting it. */
12860
12861 if (set != 0 && ! side_effects_p (SET_SRC (set))
12862 && rtx_equal_p (XEXP (note, 0), inner_dest)
12863 #ifdef HAVE_cc0
12864 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12865 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12866 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12867 #endif
12868 )
12869 {
12870 /* Move the notes and links of TEM elsewhere.
12871 This might delete other dead insns recursively.
12872 First set the pattern to something that won't use
12873 any register. */
12874
12875 PATTERN (tem) = pc_rtx;
12876
12877 distribute_notes (REG_NOTES (tem), tem, tem,
12878 NULL_RTX, NULL_RTX, NULL_RTX);
12879 distribute_links (LOG_LINKS (tem));
12880
12881 PUT_CODE (tem, NOTE);
12882 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12883 NOTE_SOURCE_FILE (tem) = 0;
12884
12885 #ifdef HAVE_cc0
12886 /* Delete the setter too. */
12887 if (cc0_setter)
12888 {
12889 PATTERN (cc0_setter) = pc_rtx;
12890
12891 distribute_notes (REG_NOTES (cc0_setter),
12892 cc0_setter, cc0_setter,
12893 NULL_RTX, NULL_RTX, NULL_RTX);
12894 distribute_links (LOG_LINKS (cc0_setter));
12895
12896 PUT_CODE (cc0_setter, NOTE);
12897 NOTE_LINE_NUMBER (cc0_setter)
12898 = NOTE_INSN_DELETED;
12899 NOTE_SOURCE_FILE (cc0_setter) = 0;
12900 }
12901 #endif
12902 }
12903 /* If the register is both set and used here, put the
12904 REG_DEAD note here, but place a REG_UNUSED note
12905 here too unless there already is one. */
12906 else if (reg_referenced_p (XEXP (note, 0),
12907 PATTERN (tem)))
12908 {
12909 place = tem;
12910
12911 if (! find_regno_note (tem, REG_UNUSED,
12912 REGNO (XEXP (note, 0))))
12913 REG_NOTES (tem)
12914 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12915 REG_NOTES (tem));
12916 }
12917 else
12918 {
12919 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12920
12921 /* If there isn't already a REG_UNUSED note, put one
12922 here. */
12923 if (! find_regno_note (tem, REG_UNUSED,
12924 REGNO (XEXP (note, 0))))
12925 place = tem;
12926 break;
12927 }
12928 }
12929 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12930 || (GET_CODE (tem) == CALL_INSN
12931 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12932 {
12933 place = tem;
12934
12935 /* If we are doing a 3->2 combination, and we have a
12936 register which formerly died in i3 and was not used
12937 by i2, which now no longer dies in i3 and is used in
12938 i2 but does not die in i2, and place is between i2
12939 and i3, then we may need to move a link from place to
12940 i2. */
12941 if (i2 && INSN_UID (place) <= max_uid_cuid
12942 && INSN_CUID (place) > INSN_CUID (i2)
12943 && from_insn
12944 && INSN_CUID (from_insn) > INSN_CUID (i2)
12945 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12946 {
12947 rtx links = LOG_LINKS (place);
12948 LOG_LINKS (place) = 0;
12949 distribute_links (links);
12950 }
12951 break;
12952 }
12953
12954 if (tem == bb->head)
12955 break;
12956 }
12957
12958 /* We haven't found an insn for the death note and it
12959 is still a REG_DEAD note, but we have hit the beginning
12960 of the block. If the existing life info says the reg
12961 was dead, there's nothing left to do. Otherwise, we'll
12962 need to do a global life update after combine. */
12963 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12964 && REGNO_REG_SET_P (bb->global_live_at_start,
12965 REGNO (XEXP (note, 0))))
12966 SET_BIT (refresh_blocks, this_basic_block->index);
12967 }
12968
12969 /* If the register is set or already dead at PLACE, we needn't do
12970 anything with this note if it is still a REG_DEAD note.
12971 We can here if it is set at all, not if is it totally replace,
12972 which is what `dead_or_set_p' checks, so also check for it being
12973 set partially. */
12974
12975 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12976 {
12977 unsigned int regno = REGNO (XEXP (note, 0));
12978
12979 /* Similarly, if the instruction on which we want to place
12980 the note is a noop, we'll need do a global live update
12981 after we remove them in delete_noop_moves. */
12982 if (noop_move_p (place))
12983 SET_BIT (refresh_blocks, this_basic_block->index);
12984
12985 if (dead_or_set_p (place, XEXP (note, 0))
12986 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12987 {
12988 /* Unless the register previously died in PLACE, clear
12989 reg_last_death. [I no longer understand why this is
12990 being done.] */
12991 if (reg_last_death[regno] != place)
12992 reg_last_death[regno] = 0;
12993 place = 0;
12994 }
12995 else
12996 reg_last_death[regno] = place;
12997
12998 /* If this is a death note for a hard reg that is occupying
12999 multiple registers, ensure that we are still using all
13000 parts of the object. If we find a piece of the object
13001 that is unused, we must arrange for an appropriate REG_DEAD
13002 note to be added for it. However, we can't just emit a USE
13003 and tag the note to it, since the register might actually
13004 be dead; so we recourse, and the recursive call then finds
13005 the previous insn that used this register. */
13006
13007 if (place && regno < FIRST_PSEUDO_REGISTER
13008 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
13009 {
13010 unsigned int endregno
13011 = regno + HARD_REGNO_NREGS (regno,
13012 GET_MODE (XEXP (note, 0)));
13013 int all_used = 1;
13014 unsigned int i;
13015
13016 for (i = regno; i < endregno; i++)
13017 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13018 && ! find_regno_fusage (place, USE, i))
13019 || dead_or_set_regno_p (place, i))
13020 all_used = 0;
13021
13022 if (! all_used)
13023 {
13024 /* Put only REG_DEAD notes for pieces that are
13025 not already dead or set. */
13026
13027 for (i = regno; i < endregno;
13028 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
13029 {
13030 rtx piece = regno_reg_rtx[i];
13031 basic_block bb = this_basic_block;
13032
13033 if (! dead_or_set_p (place, piece)
13034 && ! reg_bitfield_target_p (piece,
13035 PATTERN (place)))
13036 {
13037 rtx new_note
13038 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
13039
13040 distribute_notes (new_note, place, place,
13041 NULL_RTX, NULL_RTX, NULL_RTX);
13042 }
13043 else if (! refers_to_regno_p (i, i + 1,
13044 PATTERN (place), 0)
13045 && ! find_regno_fusage (place, USE, i))
13046 for (tem = PREV_INSN (place); ;
13047 tem = PREV_INSN (tem))
13048 {
13049 if (! INSN_P (tem))
13050 {
13051 if (tem == bb->head)
13052 {
13053 SET_BIT (refresh_blocks,
13054 this_basic_block->index);
13055 break;
13056 }
13057 continue;
13058 }
13059 if (dead_or_set_p (tem, piece)
13060 || reg_bitfield_target_p (piece,
13061 PATTERN (tem)))
13062 {
13063 REG_NOTES (tem)
13064 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
13065 REG_NOTES (tem));
13066 break;
13067 }
13068 }
13069
13070 }
13071
13072 place = 0;
13073 }
13074 }
13075 }
13076 break;
13077
13078 default:
13079 /* Any other notes should not be present at this point in the
13080 compilation. */
13081 abort ();
13082 }
13083
13084 if (place)
13085 {
13086 XEXP (note, 1) = REG_NOTES (place);
13087 REG_NOTES (place) = note;
13088 }
13089 else if ((REG_NOTE_KIND (note) == REG_DEAD
13090 || REG_NOTE_KIND (note) == REG_UNUSED)
13091 && GET_CODE (XEXP (note, 0)) == REG)
13092 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
13093
13094 if (place2)
13095 {
13096 if ((REG_NOTE_KIND (note) == REG_DEAD
13097 || REG_NOTE_KIND (note) == REG_UNUSED)
13098 && GET_CODE (XEXP (note, 0)) == REG)
13099 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
13100
13101 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
13102 REG_NOTE_KIND (note),
13103 XEXP (note, 0),
13104 REG_NOTES (place2));
13105 }
13106 }
13107 }
13108 \f
13109 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13110 I3, I2, and I1 to new locations. This is also called in one case to
13111 add a link pointing at I3 when I3's destination is changed. */
13112
13113 static void
13114 distribute_links (links)
13115 rtx links;
13116 {
13117 rtx link, next_link;
13118
13119 for (link = links; link; link = next_link)
13120 {
13121 rtx place = 0;
13122 rtx insn;
13123 rtx set, reg;
13124
13125 next_link = XEXP (link, 1);
13126
13127 /* If the insn that this link points to is a NOTE or isn't a single
13128 set, ignore it. In the latter case, it isn't clear what we
13129 can do other than ignore the link, since we can't tell which
13130 register it was for. Such links wouldn't be used by combine
13131 anyway.
13132
13133 It is not possible for the destination of the target of the link to
13134 have been changed by combine. The only potential of this is if we
13135 replace I3, I2, and I1 by I3 and I2. But in that case the
13136 destination of I2 also remains unchanged. */
13137
13138 if (GET_CODE (XEXP (link, 0)) == NOTE
13139 || (set = single_set (XEXP (link, 0))) == 0)
13140 continue;
13141
13142 reg = SET_DEST (set);
13143 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13144 || GET_CODE (reg) == SIGN_EXTRACT
13145 || GET_CODE (reg) == STRICT_LOW_PART)
13146 reg = XEXP (reg, 0);
13147
13148 /* A LOG_LINK is defined as being placed on the first insn that uses
13149 a register and points to the insn that sets the register. Start
13150 searching at the next insn after the target of the link and stop
13151 when we reach a set of the register or the end of the basic block.
13152
13153 Note that this correctly handles the link that used to point from
13154 I3 to I2. Also note that not much searching is typically done here
13155 since most links don't point very far away. */
13156
13157 for (insn = NEXT_INSN (XEXP (link, 0));
13158 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13159 || this_basic_block->next_bb->head != insn));
13160 insn = NEXT_INSN (insn))
13161 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13162 {
13163 if (reg_referenced_p (reg, PATTERN (insn)))
13164 place = insn;
13165 break;
13166 }
13167 else if (GET_CODE (insn) == CALL_INSN
13168 && find_reg_fusage (insn, USE, reg))
13169 {
13170 place = insn;
13171 break;
13172 }
13173
13174 /* If we found a place to put the link, place it there unless there
13175 is already a link to the same insn as LINK at that point. */
13176
13177 if (place)
13178 {
13179 rtx link2;
13180
13181 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13182 if (XEXP (link2, 0) == XEXP (link, 0))
13183 break;
13184
13185 if (link2 == 0)
13186 {
13187 XEXP (link, 1) = LOG_LINKS (place);
13188 LOG_LINKS (place) = link;
13189
13190 /* Set added_links_insn to the earliest insn we added a
13191 link to. */
13192 if (added_links_insn == 0
13193 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13194 added_links_insn = place;
13195 }
13196 }
13197 }
13198 }
13199 \f
13200 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13201
13202 static int
13203 insn_cuid (insn)
13204 rtx insn;
13205 {
13206 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13207 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13208 insn = NEXT_INSN (insn);
13209
13210 if (INSN_UID (insn) > max_uid_cuid)
13211 abort ();
13212
13213 return INSN_CUID (insn);
13214 }
13215 \f
13216 void
13217 dump_combine_stats (file)
13218 FILE *file;
13219 {
13220 fnotice
13221 (file,
13222 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13223 combine_attempts, combine_merges, combine_extras, combine_successes);
13224 }
13225
13226 void
13227 dump_combine_total_stats (file)
13228 FILE *file;
13229 {
13230 fnotice
13231 (file,
13232 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13233 total_attempts, total_merges, total_extras, total_successes);
13234 }
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