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Patch from Phillip Blundell <pb@nexus.co.uk> to add arm/thumb uclinux support.
[official-gcc.git] / gcc / config / arm / thumb.h
blob65d6d4ba9cc5276d371753ba173f578a8575b856
1 /* Definitions of target machine for GNU compiler, for ARM/Thumb.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 The basis of this contribution was generated by
4 Richard Earnshaw, Advanced RISC Machines Ltd
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 /* ??? The files thumb.{c,h,md} are all seriously lacking comments. */
24
25 /* ??? The files thumb.{c,h,md} need to be reviewed by an experienced
26 gcc hacker in their entirety. */
27
28 /* ??? The files thumb.{c,h,md} and tcoff.h are all separate from the arm
29 files, which will lead to many maintenance problems. These files are
30 likely missing all bug fixes made to the arm port since they diverged. */
31
32 /* ??? Many patterns in the md file accept operands that will require a
33 reload. These should be eliminated if possible by tightening the
34 predicates and/or constraints. This will give faster/smaller code. */
35
36 /* ??? There is no pattern for the TST instuction. Check for other unsupported
37 instructions. */
38
39 /* Run Time Target Specifications */
40 #ifndef CPP_PREDEFINES
41 #define CPP_PREDEFINES "-Dthumb -D__thumb -Acpu(arm) -Amachine(arm)"
42 #endif
43
44 #ifndef CPP_SPEC
45 #define CPP_SPEC "\
46 %{mbig-endian:-D__ARMEB__ -D__THUMBEB__} \
47 %{mbe:-D__ARMEB__ -D__THUMBEB__} \
48 %{!mbe: %{!mbig-endian:-D__ARMEL__ -D__THUMBEL__}} \
49 "
50 #endif
51
52 #define ASM_SPEC "-marm7tdmi %{mthumb-interwork:-mthumb-interwork} %{mbig-endian:-EB}"
53 #ifndef LINK_SPEC
54 #define LINK_SPEC "%{mbig-endian:-EB} -X"
55 #endif
56
57 #define TARGET_VERSION fputs (" (ARM/THUMB:generic)", stderr);
58
59 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
60 #define THUMB_FLAG_BIG_END 0x0001
61 #define THUMB_FLAG_BACKTRACE 0x0002
62 #define THUMB_FLAG_LEAF_BACKTRACE 0x0004
63 #define ARM_FLAG_THUMB 0x1000 /* same as in arm.h */
64 #define THUMB_FLAG_SINGLE_PIC_BASE 0x4000 /* same as in arm.h */
65 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING 0x40000
66 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING 0x80000
67
68
69 /* Run-time compilation parameters selecting different hardware/software subsets. */
70 extern int target_flags;
71 #define TARGET_DEFAULT 0 /* ARM_FLAG_THUMB */
72 #define TARGET_BIG_END (target_flags & THUMB_FLAG_BIG_END)
73 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
74 #define TARGET_BACKTRACE (leaf_function_p() \
75 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
76 : (target_flags & THUMB_FLAG_BACKTRACE))
77 #define TARGET_SINGLE_PIC_BASE (target_flags & THUMB_FLAG_SINGLE_PIC_BASE)
78
79 #ifndef GOT_PCREL
80 #define GOT_PCREL 0
81 #endif
82
83 #ifndef NEED_GOT_RELOC
84 #define NEED_GOT_RELOC 1
85 #endif
86
87 /* Set if externally visible functions should assume that they
88 might be called in ARM mode, from a non-thumb aware code. */
89 #define TARGET_CALLEE_INTERWORKING \
90 (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
91
92 /* Set if calls via function pointers should assume that their
93 destination is non-Thumb aware. */
94 #define TARGET_CALLER_INTERWORKING \
95 (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
96
97 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
98 #ifndef SUBTARGET_SWITCHES
99 #define SUBTARGET_SWITCHES
100 #endif
101
102 #define TARGET_SWITCHES \
103 { \
104 {"big-endian", THUMB_FLAG_BIG_END}, \
105 {"little-endian", -THUMB_FLAG_BIG_END}, \
106 {"thumb-interwork", ARM_FLAG_THUMB}, \
107 {"no-thumb-interwork", -ARM_FLAG_THUMB}, \
108 {"tpcs-frame", THUMB_FLAG_BACKTRACE}, \
109 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE}, \
110 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE}, \
111 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE}, \
112 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING}, \
113 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING}, \
114 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING}, \
115 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING}, \
116 {"single-pic-base", THUMB_FLAG_SINGLE_PIC_BASE, \
117 "Do not load the PIC register in function prologues" }, \
118 {"no-single-pic-base", -THUMB_FLAG_SINGLE_PIC_BASE, "" }, \
119 SUBTARGET_SWITCHES \
120 {"", TARGET_DEFAULT} \
121 }
122
123 #define TARGET_OPTIONS \
124 { \
125 { "structure-size-boundary=", & structure_size_string }, \
126 { "pic-register=", & thumb_pic_register_string, \
127 "Specify the register to be used for PIC addressing" } \
128 }
129
130 #define REGISTER_PREFIX ""
131
132 #define CAN_DEBUG_WITHOUT_FP 1
133 \f
134 #define ASM_APP_ON ""
135 #define ASM_APP_OFF "\t.code\t16\n"
136
137 /* Output a gap. In fact we fill it with nulls. */
138 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
139 fprintf ((STREAM), "\t.space\t%u\n", (NBYTES))
140
141 /* This is how to output an assembler line
142 that says to advance the location counter
143 to a multiple of 2**LOG bytes. */
144 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
145 { \
146 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
147 }
148
149 /* Output a common block */
150 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
151 (fprintf ((STREAM), "\t.comm\t"), \
152 assemble_name ((STREAM), (NAME)), \
153 fprintf((STREAM), ", %d\t%s %d\n", (ROUNDED), (ASM_COMMENT_START), (SIZE)))
154
155 #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \
156 sprintf ((STRING), "*%s%s%d", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM))
157
158 /* This is how to output an internal numbered label where
159 PREFIX is the class of label and NUM is the number within the class. */
160 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
161 fprintf ((STREAM), "%s%s%d:\n", (LOCAL_LABEL_PREFIX), (PREFIX), (NUM))
162
163 /* This is how to output a label which precedes a jumptable. Since
164 instructions are 2 bytes, we need explicit alignment here. */
165
166 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE) \
167 do { \
168 ASM_OUTPUT_ALIGN (FILE, 2); \
169 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
170 } while (0)
171
172 /* This says how to define a local common symbol (ie, not visible to
173 linker). */
174 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
175 (fprintf((STREAM),"\n\t.lcomm\t"), \
176 assemble_name((STREAM),(NAME)), \
177 fprintf((STREAM),",%u\n",(SIZE)))
178
179 /* Output a reference to a label. */
180 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
181 fprintf ((STREAM), "%s%s", user_label_prefix, (NAME))
182
183 /* This is how to output an assembler line for a numeric constant byte. */
184 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
185 fprintf ((STREAM), "\t.byte\t0x%x\n", (VALUE))
186
187 #define ASM_OUTPUT_INT(STREAM,VALUE) \
188 { \
189 fprintf (STREAM, "\t.word\t"); \
190 OUTPUT_INT_ADDR_CONST (STREAM, (VALUE)); \
191 fprintf (STREAM, "\n"); \
192 }
193
194 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
195 { \
196 fprintf (STREAM, "\t.short\t"); \
197 output_addr_const (STREAM, (VALUE)); \
198 fprintf (STREAM, "\n"); \
199 }
200
201 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
202 { \
203 fprintf (STREAM, "\t.byte\t"); \
204 output_addr_const (STREAM, (VALUE)); \
205 fprintf (STREAM, "\n"); \
206 }
207
208 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
209 do { char dstr[30]; \
210 long l[3]; \
211 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
212 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
213 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%s long double %s\n", \
214 l[0], l[1], l[2], ASM_COMMENT_START, dstr); \
215 } while (0)
216
217 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
218 do { char dstr[30]; \
219 long l[2]; \
220 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
221 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
222 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%s double %s\n", l[0], \
223 l[1], ASM_COMMENT_START, dstr); \
224 } while (0)
225
226 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
227 do { char dstr[30]; \
228 long l; \
229 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
230 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
231 fprintf (STREAM, "\t.word 0x%lx\t%s float %s\n", l, \
232 ASM_COMMENT_START, dstr); \
233 } while (0);
234
235 /* Define results of standard character escape sequences. */
236 #define TARGET_BELL 007
237 #define TARGET_BS 010
238 #define TARGET_TAB 011
239 #define TARGET_NEWLINE 012
240 #define TARGET_VT 013
241 #define TARGET_FF 014
242 #define TARGET_CR 015
243
244 /* This is how to output a string. */
245 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
246 do { \
247 register int i, c, len = (LEN), cur_pos = 17; \
248 register unsigned char *string = (unsigned char *)(STRING); \
249 fprintf ((STREAM), "\t.ascii\t\""); \
250 for (i = 0; i < len; i++) \
251 { \
252 register int c = string[i]; \
253 \
254 switch (c) \
255 { \
256 case '\"': \
257 case '\\': \
258 putc ('\\', (STREAM)); \
259 putc (c, (STREAM)); \
260 cur_pos += 2; \
261 break; \
262 \
263 case TARGET_NEWLINE: \
264 fputs ("\\n", (STREAM)); \
265 if (i+1 < len \
266 && (((c = string[i+1]) >= '\040' && c <= '~') \
267 || c == TARGET_TAB)) \
268 cur_pos = 32767; /* break right here */ \
269 else \
270 cur_pos += 2; \
271 break; \
272 \
273 case TARGET_TAB: \
274 fputs ("\\t", (STREAM)); \
275 cur_pos += 2; \
276 break; \
277 \
278 case TARGET_FF: \
279 fputs ("\\f", (STREAM)); \
280 cur_pos += 2; \
281 break; \
282 \
283 case TARGET_BS: \
284 fputs ("\\b", (STREAM)); \
285 cur_pos += 2; \
286 break; \
287 \
288 case TARGET_CR: \
289 fputs ("\\r", (STREAM)); \
290 cur_pos += 2; \
291 break; \
292 \
293 default: \
294 if (c >= ' ' && c < 0177) \
295 { \
296 putc (c, (STREAM)); \
297 cur_pos++; \
298 } \
299 else \
300 { \
301 fprintf ((STREAM), "\\%03o", c); \
302 cur_pos += 4; \
303 } \
304 } \
305 \
306 if (cur_pos > 72 && i+1 < len) \
307 { \
308 cur_pos = 17; \
309 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
310 } \
311 } \
312 fprintf ((STREAM), "\"\n"); \
313 } while (0)
314
315 /* Output and Generation of Labels */
316 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
317 (assemble_name ((STREAM), (NAME)), \
318 fprintf ((STREAM), ":\n"))
319
320 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
321 (fprintf ((STREAM), "\t.globl\t"), \
322 assemble_name ((STREAM), (NAME)), \
323 fputc ('\n', (STREAM)))
324
325 /* Construct a private name. */
326 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
327 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
328 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
329
330 /* Switch to the text or data segment. */
331 #define TEXT_SECTION_ASM_OP ".text"
332 #define DATA_SECTION_ASM_OP ".data"
333 #define BSS_SECTION_ASM_OP ".bss"
334
335 /* The assembler's names for the registers. */
336 #ifndef REGISTER_NAMES
337 #define REGISTER_NAMES \
338 { \
339 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
340 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", "ap" \
341 }
342 #endif
343
344 #ifndef ADDITIONAL_REGISTER_NAMES
345 #define ADDITIONAL_REGISTER_NAMES \
346 { \
347 {"a1", 0}, \
348 {"a2", 1}, \
349 {"a3", 2}, \
350 {"a4", 3}, \
351 {"v1", 4}, \
352 {"v2", 5}, \
353 {"v3", 6}, \
354 {"v4", 7}, \
355 {"v5", 8}, \
356 {"v6", 9}, \
357 {"sb", 9}, \
358 {"v7", 10}, \
359 {"r10", 10}, /* sl */ \
360 {"r11", 11}, /* fp */ \
361 {"r12", 12}, /* ip */ \
362 {"r13", 13}, /* sp */ \
363 {"r14", 14}, /* lr */ \
364 {"r15", 15} /* pc */ \
365 }
366 #endif
367
368 /* The assembler's parentheses characters. */
369 #define ASM_OPEN_PAREN "("
370 #define ASM_CLOSE_PAREN ")"
371
372 #ifndef ASM_COMMENT_START
373 #define ASM_COMMENT_START "@"
374 #endif
375
376 /* Output an element of a dispatch table. */
377 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
378 fprintf (STREAM, "\t.word\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE))
379
380 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
381 fprintf (STREAM, "\tb\t%sL%d\n", (LOCAL_LABEL_PREFIX), (VALUE))
382 \f
383 /* Storage Layout */
384
385 /* Define this is most significant bit is lowest numbered in
386 instructions that operate on numbered bit-fields. */
387 #define BITS_BIG_ENDIAN 0
388
389 /* Define this if most significant byte of a word is the lowest
390 numbered. */
391 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
392
393 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
394
395 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
396 on processor pre-defineds when compiling libgcc2.c. */
397 #if defined(__THUMBEB__) && !defined(__THUMBEL__)
398 #define LIBGCC2_WORDS_BIG_ENDIAN 1
399 #else
400 #define LIBGCC2_WORDS_BIG_ENDIAN 0
401 #endif
402
403 #define FLOAT_WORDS_BIG_ENDIAN 1
404
405 #define BITS_PER_UNIT 8
406 #define BITS_PER_WORD 32
407
408 #define UNITS_PER_WORD 4
409
410 #define POINTER_SIZE 32
411
412 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
413 { \
414 if (GET_MODE_CLASS (MODE) == MODE_INT \
415 && GET_MODE_SIZE (MODE) < 4) \
416 { \
417 (UNSIGNEDP) = 1; \
418 (MODE) = SImode; \
419 } \
420 }
421
422 #define PARM_BOUNDARY 32
423 #define STACK_BOUNDARY 32
424
425 #define FUNCTION_BOUNDARY 32
426 #define BIGGEST_ALIGNMENT 32
427
428 /* Make strings word-aligned so strcpy from constants will be faster. */
429 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
430 (TREE_CODE (EXP) == STRING_CST \
431 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
432
433 #define EMPTY_FIELD_BOUNDARY 32
434
435 #define STRUCTURE_SIZE_BOUNDARY 32
436
437 /* Used when parsing command line option -mstructure_size_boundary. */
438 extern char * structure_size_string;
439
440 #define STRICT_ALIGNMENT 1
441
442 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
443
444 \f
445 /* Layout of Source Language Data Types */
446
447 #define DEFAULT_SIGNED_CHAR 0
448
449 #define TARGET_BELL 007
450 #define TARGET_BS 010
451 #define TARGET_TAB 011
452 #define TARGET_NEWLINE 012
453 #define TARGET_VT 013
454 #define TARGET_FF 014
455 #define TARGET_CR 015
456
457 \f
458 /* Register Usage */
459
460 /* Note there are 16 hard registers on the Thumb. We invent a 17th register
461 which is assigned to ARG_POINTER_REGNUM, but this is later removed by
462 elimination passes in the compiler. */
463 #define FIRST_PSEUDO_REGISTER 17
464
465 /* ??? This is questionable. */
466 #define FIXED_REGISTERS \
467 { \
468 0,0,0,0, \
469 0,0,0,0, \
470 0,0,0,1, \
471 0,1,1,1,1 \
472 }
473
474 /* ??? This is questionable. */
475 #define CALL_USED_REGISTERS \
476 { \
477 1,1,1,1, \
478 0,0,0,0, \
479 0,0,0,1, \
480 1,1,1,1,1 \
481 }
482
483 #define HARD_REGNO_NREGS(REGNO,MODE) \
484 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
485 / UNITS_PER_WORD)
486
487 /* ??? Probably should only allow DImode/DFmode in even numbered registers. */
488 #define HARD_REGNO_MODE_OK(REGNO,MODE) ((GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (REGNO < 7) : 1)
489
490 #define MODES_TIEABLE_P(MODE1,MODE2) 1
491
492 /* The NOARG_LO_REGS class is the set of LO_REGS that are not used for passing
493 arguments to functions. These are the registers that are available for
494 spilling during reload. The code in reload1.c:init_reload() will detect this
495 class and place it into 'reload_address_base_reg_class'. */
496
497 enum reg_class
498 {
499 NO_REGS,
500 NONARG_LO_REGS,
501 LO_REGS,
502 STACK_REG,
503 BASE_REGS,
504 HI_REGS,
505 ALL_REGS,
506 LIM_REG_CLASSES
507 };
508
509 #define GENERAL_REGS ALL_REGS
510
511 #define N_REG_CLASSES (int) LIM_REG_CLASSES
512
513 #define REG_CLASS_NAMES \
514 { \
515 "NO_REGS", \
516 "NONARG_LO_REGS", \
517 "LO_REGS", \
518 "STACK_REG", \
519 "BASE_REGS", \
520 "HI_REGS", \
521 "ALL_REGS" \
522 }
523
524 #define REG_CLASS_CONTENTS \
525 { \
526 0x00000, \
527 0x000f0, \
528 0x000ff, \
529 0x02000, \
530 0x020ff, \
531 0x0ff00, \
532 0x1ffff, \
533 }
534
535 #define REGNO_REG_CLASS(REGNO) \
536 ((REGNO) == STACK_POINTER_REGNUM ? STACK_REG \
537 : (REGNO) < 8 ? ((REGNO) < 4 ? LO_REGS \
538 : NONARG_LO_REGS) \
539 : HI_REGS)
540
541 #define BASE_REG_CLASS BASE_REGS
542
543 #define INDEX_REG_CLASS LO_REGS
544
545 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
546 registers explicitly used in the rtl to be used as spill registers
547 but prevents the compiler from extending the lifetime of these
548 registers. */
549
550 #define SMALL_REGISTER_CLASSES 1
551
552 #define REG_CLASS_FROM_LETTER(C) \
553 ((C) == 'l' ? LO_REGS \
554 : (C) == 'h' ? HI_REGS \
555 : (C) == 'b' ? BASE_REGS \
556 : (C) == 'k' ? STACK_REG \
557 : NO_REGS)
558
559 #define REGNO_OK_FOR_BASE_P(REGNO) \
560 ((REGNO) < 8 \
561 || (REGNO) == STACK_POINTER_REGNUM \
562 || (unsigned) reg_renumber[REGNO] < 8 \
563 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM)
564
565 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
566 ((REGNO) < 8 \
567 || (unsigned) reg_renumber[REGNO] < 8 \
568 || (GET_MODE_SIZE (MODE) >= 4 \
569 && ((REGNO) == STACK_POINTER_REGNUM \
570 || (unsigned) reg_renumber[REGNO] == STACK_POINTER_REGNUM)))
571
572 #define REGNO_OK_FOR_INDEX_P(REGNO) \
573 ((REGNO) < 8 \
574 || (unsigned) reg_renumber[REGNO] < 8)
575
576 #define INDEX_REGISTER_RTX_P(X) \
577 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
578
579 /* ??? This looks suspiciously wrong. */
580 /* We need to leave BASE_REGS reloads alone, in order to avoid caller_save
581 lossage. Caller_saves requests a BASE_REGS reload (caller_save_spill_class)
582 and then later we verify that one was allocated. If PREFERRED_RELOAD_CLASS
583 says to allocate a LO_REGS spill instead, then this mismatch gives an
584 abort. Alternatively, this could be fixed by modifying BASE_REG_CLASS
585 to be LO_REGS instead of BASE_REGS. It is not clear what affect this
586 change would have. */
587 /* ??? This looks even more suspiciously wrong. PREFERRED_RELOAD_CLASS
588 must always return a strict subset of the input class. Just blindly
589 returning LO_REGS is safe only if the input class is a superset of LO_REGS,
590 but there is no check for this. Added another exception for NONARG_LO_REGS
591 because it is not a superset of LO_REGS. */
592 /* ??? We now use NONARG_LO_REGS for caller_save_spill_class, so the
593 comments about BASE_REGS are now obsolete. */
594 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
595 ((CLASS) == BASE_REGS || (CLASS) == NONARG_LO_REGS ? (CLASS) \
596 : LO_REGS)
597 /*
598 ((CONSTANT_P ((X)) && GET_CODE ((X)) != CONST_INT \
599 && ! CONSTANT_POOL_ADDRESS_P((X))) ? NO_REGS \
600 : (GET_CODE ((X)) == CONST_INT \
601 && (unsigned HOST_WIDE_INT) INTVAL ((X)) > 255) ? NO_REGS \
602 : LO_REGS) */
603
604 /* Must leave BASE_REGS and NONARG_LO_REGS reloads alone, see comment
605 above. */
606 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
607 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS && (CLASS) != NONARG_LO_REGS \
608 ? ((true_regnum (X) == -1 ? LO_REGS \
609 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
610 : NO_REGS)) \
611 : NO_REGS)
612
613 #define CLASS_MAX_NREGS(CLASS,MODE) HARD_REGNO_NREGS(0,(MODE))
614
615 int thumb_shiftable_const ();
616
617 #define CONST_OK_FOR_LETTER_P(VAL,C) \
618 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 \
619 : (C) == 'J' ? (VAL) > -256 && (VAL) <= 0 \
620 : (C) == 'K' ? thumb_shiftable_const (VAL) \
621 : (C) == 'L' ? (VAL) > -8 && (VAL) < 8 \
622 : (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
623 && ((VAL) & 3) == 0) \
624 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
625 : (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
626 : 0)
627
628 #define CONST_DOUBLE_OK_FOR_LETTER_P(VAL,C) 0
629
630 #define EXTRA_CONSTRAINT(X,C) \
631 ((C) == 'Q' ? (GET_CODE (X) == MEM \
632 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
633 \f
634 /* Stack Layout and Calling Conventions */
635
636 #define STACK_GROWS_DOWNWARD 1
637
638 /* #define FRAME_GROWS_DOWNWARD 1 */
639
640 /* #define ARGS_GROW_DOWNWARD 1 */
641
642 #define STARTING_FRAME_OFFSET 0
643
644 #define FIRST_PARM_OFFSET(FNDECL) 0
645
646 /* Registers that address the stack frame */
647
648 #define STACK_POINTER_REGNUM 13 /* Defined by the TPCS. */
649
650 #define FRAME_POINTER_REGNUM 7 /* TPCS defines this as 11 but it does not really mean it. */
651
652 #define ARG_POINTER_REGNUM 16 /* A fake hard register that is eliminated later on. */
653
654 #define STATIC_CHAIN_REGNUM 9
655
656 /* Define this if the program counter is overloaded on a register. */
657 #define PC_REGNUM 15
658
659 #define FRAME_POINTER_REQUIRED 0
660
661 #define ELIMINABLE_REGS \
662 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
663 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
664 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
665
666 /* On the Thumb we always want to perform the eliminations as we
667 actually only have one real register pointing to the stashed
668 variables: the stack pointer, and we never use the frame pointer. */
669 #define CAN_ELIMINATE(FROM,TO) 1
670
671 /* Note: This macro must match the code in thumb_function_prologue() in thumb.c. */
672 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,OFFSET) \
673 { \
674 (OFFSET) = 0; \
675 if ((FROM) == ARG_POINTER_REGNUM) \
676 { \
677 int count_regs = 0; \
678 int regno; \
679 (OFFSET) += get_frame_size (); \
680 for (regno = 8; regno < 13; regno++) \
681 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
682 count_regs++; \
683 if (count_regs) \
684 (OFFSET) += 4 * count_regs; \
685 count_regs = 0; \
686 for (regno = 0; regno < 8; regno++) \
687 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
688 count_regs++; \
689 if (count_regs || ! leaf_function_p () || far_jump_used_p()) \
690 (OFFSET) += 4 * (count_regs + 1); \
691 if (TARGET_BACKTRACE) { \
692 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
693 (OFFSET) += 20; \
694 else \
695 (OFFSET) += 16; } \
696 } \
697 if ((TO) == STACK_POINTER_REGNUM) \
698 (OFFSET) += current_function_outgoing_args_size; \
699 }
700
701 /* Passing Arguments on the stack */
702
703 #define PROMOTE_PROTOTYPES 1
704
705 #define ACCUMULATE_OUTGOING_ARGS 1
706
707 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
708
709 #define FUNCTION_ARG(CUM,MODE,TYPE,NAMED) \
710 ((NAMED) ? ((CUM) >= 16 ? 0 : gen_rtx (REG, (MODE), (CUM) / 4)) \
711 : 0)
712
713 #define FUNCTION_ARG_PARTIAL_NREGS(CUM,MODE,TYPE,NAMED) \
714 (((CUM) < 16 && (CUM) + (((MODE) == BLKmode) \
715 ? int_size_in_bytes (TYPE) \
716 : HARD_REGNO_NREGS (0, (MODE)) * 4) > 16) \
717 ? 4 - (CUM) / 4 : 0)
718
719 #define CUMULATIVE_ARGS int
720
721 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
722 ((CUM) = ((FNTYPE) && aggregate_value_p (TREE_TYPE (FNTYPE))) ? 4 : 0)
723
724 #define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED) \
725 (CUM) += ((((MODE) == BLKmode) \
726 ? int_size_in_bytes (TYPE) \
727 : GET_MODE_SIZE (MODE)) + 3) & ~3
728
729 #define FUNCTION_ARG_REGNO_P(REGNO) \
730 ((REGNO) >=0 && (REGNO) <= 3)
731
732 #define FUNCTION_VALUE(VALTYPE,FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
733
734 #define LIBCALL_VALUE(MODE) gen_rtx (REG, (MODE), 0)
735
736 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == 0)
737
738 /* How large values are returned */
739 /* A C expression which can inhibit the returning of certain function values
740 in registers, based on the type of value. */
741 #define RETURN_IN_MEMORY(TYPE) thumb_return_in_memory (TYPE)
742
743 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
744 values must be in memory. On the ARM, they need only do so if larger
745 than a word, or if they contain elements offset from zero in the struct. */
746 #define DEFAULT_PCC_STRUCT_RETURN 0
747
748
749 #define STRUCT_VALUE_REGNUM 0
750
751 #define FUNCTION_PROLOGUE(FILE,SIZE) thumb_function_prologue((FILE),(SIZE))
752
753 #define FUNCTION_EPILOGUE(FILE,SIZE) thumb_function_epilogue((FILE),(SIZE))
754
755 /* Generating code for profiling */
756 #define FUNCTION_PROFILER(STREAM,LABELNO) \
757 { \
758 fprintf ((STREAM), "\tmov\\tip, lr\n"); \
759 fprintf ((STREAM), "\tbl\tmcount\n"); \
760 fprintf ((STREAM), "\t.word\tLP%d\n", (LABELNO)); \
761 }
762
763 /* Implementing the Varargs Macros */
764
765 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
766 { \
767 extern int current_function_anonymous_args; \
768 current_function_anonymous_args = 1; \
769 if ((CUM) < 16) \
770 (PRETEND_SIZE) = 16 - (CUM); \
771 }
772
773 /* Trampolines for nested functions */
774
775 /* Output assembler code for a block containing the constant parts of
776 a trampoline, leaving space for the variable parts.
777
778 On the Thumb we always switch into ARM mode to execute the trampoline.
779 Why - because it is easier. This code will always be branched to via
780 a BX instruction and since the compiler magically generates the address
781 of the function the linker has no opportunity to ensure that the
782 bottom bit is set. Thus the processor will be in ARM mode when it
783 reaches this code. So we duplicate the ARM trampoline code and add
784 a switch into Thumb mode as well.
785
786 On the ARM, (if r8 is the static chain regnum, and remembering that
787 referencing pc adds an offset of 8) the trampoline looks like:
788 ldr r8, [pc, #0]
789 ldr pc, [pc]
790 .word static chain value
791 .word function's address
792 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
793 #define TRAMPOLINE_TEMPLATE(FILE) \
794 { \
795 fprintf ((FILE), "\t.code 32\n"); \
796 fprintf ((FILE), ".Ltrampoline_start:\n"); \
797 fprintf ((FILE), "\tldr\t%s, [%spc, #8]\n", \
798 reg_names[STATIC_CHAIN_REGNUM], REGISTER_PREFIX); \
799 fprintf ((FILE), "\tldr\t%sip, [%spc, #8]\n", \
800 REGISTER_PREFIX, REGISTER_PREFIX); \
801 fprintf ((FILE), "\torr\t%sip, %sip, #1\n", \
802 REGISTER_PREFIX, REGISTER_PREFIX); \
803 fprintf ((FILE), "\tbx\t%sip\n", REGISTER_PREFIX); \
804 fprintf ((FILE), "\t.word\t0\n"); \
805 fprintf ((FILE), "\t.word\t0\n"); \
806 fprintf ((FILE), "\t.code 16\n"); \
807 }
808
809 /* Length in units of the trampoline for entering a nested function. */
810 #define TRAMPOLINE_SIZE 24
811
812 /* Alignment required for a trampoline in units. */
813 #define TRAMPOLINE_ALIGN 4
814
815 #define INITIALIZE_TRAMPOLINE(ADDR,FNADDR,CHAIN) \
816 { \
817 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 16)), \
818 (CHAIN)); \
819 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((ADDR), 20)), \
820 (FNADDR)); \
821 }
822
823 \f
824 /* Position Independent Code. */
825 /* We decide which register to use based on the compilation options and
826 the assembler in use. @@@ Actually, we don't currently for Thumb. */
827 extern int thumb_pic_register;
828
829 /* The register number of the register used to address a table of static
830 data addresses in memory. */
831 #define PIC_OFFSET_TABLE_REGNUM thumb_pic_register
832
833 #define FINALIZE_PIC thumb_finalize_pic ()
834
835 /* We can't directly access anything that contains a symbol,
836 nor can we indirect via the constant pool. */
837 #define LEGITIMATE_PIC_OPERAND_P(X) \
838 (! symbol_mentioned_p (X) \
839 && (! CONSTANT_POOL_ADDRESS_P (X) \
840 || ! symbol_mentioned_p (get_pool_constant (X))))
841
842 /* We need to know when we are making a constant pool; this determines
843 whether data needs to be in the GOT or can be referenced via a GOT
844 offset. */
845 extern int making_const_table;
846
847 #define CONDITIONAL_REGISTER_USAGE \
848 { \
849 if (flag_pic) \
850 { \
851 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
852 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
853 } \
854 }
855
856 \f
857 /* Implicit Calls to Library Routines */
858
859 #define TARGET_MEM_FUNCTIONS 1
860
861 #define OVERRIDE_OPTIONS thumb_override_options ()
862
863 \f
864 /* Addressing Modes */
865
866 #define HAVE_POST_INCREMENT 1
867
868 #define CONSTANT_ADDRESS_P(X) \
869 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
870
871 #define MAX_REGS_PER_ADDRESS 2
872
873 #ifdef REG_OK_STRICT
874
875 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
876 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
877
878 #define REG_MODE_OK_FOR_BASE_P(X,MODE) \
879 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
880
881 #else /* REG_OK_STRICT */
882
883 #define REG_OK_FOR_BASE_P(X) \
884 (REGNO (X) < 8 || REGNO (X) == STACK_POINTER_REGNUM \
885 || (X) == arg_pointer_rtx \
886 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
887
888 #define REG_MODE_OK_FOR_BASE_P(X,MODE) \
889 (REGNO (X) < 8 \
890 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
891 || (GET_MODE_SIZE (MODE) >= 4 \
892 && (REGNO (X) == STACK_POINTER_REGNUM \
893 || (X) == arg_pointer_rtx)))
894
895 #define REG_OK_FOR_INDEX_P(X) \
896 (REGNO (X) < 8 \
897 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
898
899 #endif /* REG_OK_STRICT */
900
901 /* In a REG+REG address, both must be INDEX registers. */
902 #define REG_OK_FOR_INDEXED_BASE_P(X) REG_OK_FOR_INDEX_P(X)
903
904 #define LEGITIMATE_OFFSET(MODE,VAL) \
905 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
906 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
907 && ((VAL) & 1) == 0) \
908 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
909 && ((VAL) & 3) == 0))
910
911 /* The AP may be eliminated to either the SP or the FP, so we use the
912 least common denominator, e.g. SImode, and offsets from 0 to 64. */
913
914 /* ??? Verify whether the above is the right approach. */
915
916 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
917 needs special handling also. */
918
919 /* ??? Look at how the mips16 port solves this problem. It probably uses
920 better ways to solve some of these problems. */
921
922 /* Although it is not incorrect, we don't accept QImode and HImode
923 addresses based on the frame pointer or arg pointer until the reload pass starts.
924 This is so that eliminating such addresses into stack based ones
925 won't produce impossible code. */
926 #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
927 { \
928 /* ??? Not clear if this is right. Experiment. */ \
929 if (GET_MODE_SIZE (MODE) < 4 \
930 && ! (reload_in_progress || reload_completed) \
931 && (reg_mentioned_p (frame_pointer_rtx, X) \
932 || reg_mentioned_p (arg_pointer_rtx, X) \
933 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
934 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
935 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
936 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
937 ; \
938 /* Accept any base register. SP only in SImode or larger. */ \
939 else if (GET_CODE (X) == REG && REG_MODE_OK_FOR_BASE_P(X, MODE)) \
940 goto WIN; \
941 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
942 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
943 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
944 goto WIN; \
945 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
946 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
947 && (GET_CODE (X) == LABEL_REF \
948 || (GET_CODE (X) == CONST \
949 && GET_CODE (XEXP (X, 0)) == PLUS \
950 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
951 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
952 goto WIN; \
953 /* Post-inc indexing only supported for SImode and larger. */ \
954 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
955 && GET_CODE (XEXP (X, 0)) == REG \
956 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
957 goto WIN; \
958 else if (GET_CODE (X) == PLUS) \
959 { \
960 /* REG+REG address can be any two index registers. */ \
961 /* ??? REG+REG addresses have been completely disabled before \
962 reload completes, because we do not have enough available \
963 reload registers. We only have 3 guaranteed reload registers \
964 (NONARG_LO_REGS - the frame pointer), but we need at least 4 \
965 to support REG+REG addresses. We have left them enabled after \
966 reload completes, in the hope that reload_cse_regs and related \
967 routines will be able to create them after the fact. It is \
968 probably possible to support REG+REG addresses with additional \
969 reload work, but I do not not have enough time to attempt such \
970 a change at this time. */ \
971 /* ??? Normally checking the mode here is wrong, since it isn't \
972 impossible to use REG+REG with DFmode. However, the movdf \
973 pattern requires offsettable addresses, and REG+REG is not \
974 offsettable, so it must be rejected somehow. Trying to use \
975 'o' fails, because offsettable_address_p does a QImode check. \
976 QImode is not valid for stack addresses, and has a smaller \
977 range for non-stack bases, and this causes valid addresses \
978 to be rejected. So we just eliminate REG+REG here by checking \
979 the mode. */ \
980 /* We also disallow FRAME+REG addressing since we know that FRAME \
981 will be replaced with STACK, and SP relative addressing only \
982 permits SP+OFFSET. */ \
983 if (GET_MODE_SIZE (MODE) <= 4 \
984 /* ??? See comment above. */ \
985 && reload_completed \
986 && GET_CODE (XEXP (X, 0)) == REG \
987 && GET_CODE (XEXP (X, 1)) == REG \
988 && XEXP (X, 0) != frame_pointer_rtx \
989 && XEXP (X, 1) != frame_pointer_rtx \
990 && XEXP (X, 0) != virtual_stack_vars_rtx \
991 && XEXP (X, 1) != virtual_stack_vars_rtx \
992 && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
993 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
994 goto WIN; \
995 /* REG+const has 5-7 bit offset for non-SP registers. */ \
996 else if (GET_CODE (XEXP (X, 0)) == REG \
997 && (REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
998 || XEXP (X, 0) == arg_pointer_rtx) \
999 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1000 && LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1001 goto WIN; \
1002 /* REG+const has 10 bit offset for SP, but only SImode and \
1003 larger is supported. */ \
1004 /* ??? Should probably check for DI/DFmode overflow here \
1005 just like GO_IF_LEGITIMATE_OFFSET does. */ \
1006 else if (GET_CODE (XEXP (X, 0)) == REG \
1007 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
1008 && GET_MODE_SIZE (MODE) >= 4 \
1009 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1010 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) < 1024 \
1011 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
1012 goto WIN; \
1013 } \
1014 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1015 && GET_CODE (X) == SYMBOL_REF \
1016 && CONSTANT_POOL_ADDRESS_P (X) \
1017 && ! (flag_pic \
1018 && symbol_mentioned_p (get_pool_constant (X)))) \
1019 goto WIN; \
1020 }
1021
1022 /* ??? If an HImode FP+large_offset address is converted to an HImode
1023 SP+large_offset address, then reload won't know how to fix it. It sees
1024 only that SP isn't valid for HImode, and so reloads the SP into an index
1025 register, but the resulting address is still invalid because the offset
1026 is too big. We fix it here instead by reloading the entire address. */
1027 /* We could probably achieve better results by defining PROMOTE_MODE to help
1028 cope with the variances between the Thumb's signed and unsigned byte and
1029 halfword load instructions. */
1030 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1031 { \
1032 if (GET_CODE (X) == PLUS \
1033 && GET_MODE_SIZE (MODE) < 4 \
1034 && GET_CODE (XEXP (X, 0)) == REG \
1035 && XEXP (X, 0) == stack_pointer_rtx \
1036 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1037 && ! LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1038 { \
1039 rtx orig_X = X; \
1040 X = copy_rtx (X); \
1041 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1042 BASE_REG_CLASS, \
1043 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1044 goto WIN; \
1045 } \
1046 }
1047
1048 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1049
1050 extern struct rtx_def * legitimize_pic_address ();
1051 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1052 if (flag_pic) \
1053 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
1054
1055 #define LEGITIMATE_CONSTANT_P(X) \
1056 (GET_CODE (X) == CONST_INT \
1057 || GET_CODE (X) == CONST_DOUBLE \
1058 || CONSTANT_ADDRESS_P (X))
1059
1060 \f
1061 /* Condition Code Status */
1062
1063 #define NOTICE_UPDATE_CC(EXP,INSN) \
1064 { \
1065 if (get_attr_conds ((INSN)) != CONDS_UNCHANGED) \
1066 CC_STATUS_INIT; \
1067 }
1068
1069 \f
1070 /* Describing Relative Costs of Operations */
1071
1072 #define SLOW_BYTE_ACCESS 0
1073
1074 #define SLOW_UNALIGNED_ACCESS 1
1075
1076 #define NO_FUNCTION_CSE 1
1077
1078 #define NO_RECURSIVE_FUNCTION_CSE 1
1079
1080 #define REGISTER_MOVE_COST(FROM,TO) \
1081 (((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1082
1083 #define MEMORY_MOVE_COST(M,CLASS,IN) \
1084 ((GET_MODE_SIZE(M) < 4 ? 8 : 2 * GET_MODE_SIZE(M)) * (CLASS == LO_REGS ? 1 : 2))
1085
1086 /* This will allow better space optimization when compiling with -O */
1087 #define BRANCH_COST (optimize > 1 ? 1 : 0)
1088
1089 #define RTX_COSTS(X,CODE,OUTER) \
1090 case MULT: \
1091 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1092 { \
1093 int cycles = 0; \
1094 unsigned HOST_WIDE_INT i = INTVAL (XEXP (X, 1)); \
1095 while (i) \
1096 { \
1097 i >>= 2; \
1098 cycles++; \
1099 } \
1100 return COSTS_N_INSNS (2) + cycles; \
1101 } \
1102 return COSTS_N_INSNS (1) + 16; \
1103 case ASHIFT: case ASHIFTRT: case LSHIFTRT: case ROTATERT: \
1104 case PLUS: case MINUS: case COMPARE: case NEG: case NOT: \
1105 return COSTS_N_INSNS (1); \
1106 case SET: \
1107 return (COSTS_N_INSNS (1) \
1108 + 4 * ((GET_CODE (SET_SRC (X)) == MEM) \
1109 + GET_CODE (SET_DEST (X)) == MEM))
1110
1111 #define CONST_COSTS(X,CODE,OUTER) \
1112 case CONST_INT: \
1113 if ((OUTER) == SET) \
1114 { \
1115 if ((unsigned HOST_WIDE_INT) INTVAL (X) < 256) \
1116 return 0; \
1117 if (thumb_shiftable_const (INTVAL (X))) \
1118 return COSTS_N_INSNS (2); \
1119 return COSTS_N_INSNS (3); \
1120 } \
1121 else if (OUTER == PLUS \
1122 && INTVAL (X) < 256 && INTVAL (X) > -256) \
1123 return 0; \
1124 else if (OUTER == COMPARE \
1125 && (unsigned HOST_WIDE_INT) INTVAL (X) < 256) \
1126 return 0; \
1127 else if (OUTER == ASHIFT || OUTER == ASHIFTRT \
1128 || OUTER == LSHIFTRT) \
1129 return 0; \
1130 return COSTS_N_INSNS (2); \
1131 case CONST: \
1132 case CONST_DOUBLE: \
1133 case LABEL_REF: \
1134 case SYMBOL_REF: \
1135 return COSTS_N_INSNS(3);
1136
1137 #define ADDRESS_COST(X) \
1138 ((GET_CODE (X) == REG \
1139 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1140 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
1141 ? 1 : 2)
1142
1143 \f
1144 /* Position Independent Code */
1145
1146 extern const char * thumb_pic_register_string;
1147 extern int thumb_pic_register;
1148
1149 /* The register number of the register used to address a table of static
1150 data addresses in memory. */
1151 #define PIC_OFFSET_TABLE_REGNUM thumb_pic_register
1152
1153 #define FINALIZE_PIC thumb_finalize_pic ()
1154
1155 /* We can't directly access anything that contains a symbol,
1156 nor can we indirect via the constant pool. */
1157 #define LEGITIMATE_PIC_OPERAND_P(X) \
1158 (! symbol_mentioned_p (X) \
1159 && (! CONSTANT_POOL_ADDRESS_P (X) \
1160 || ! symbol_mentioned_p (get_pool_constant (X))))
1161
1162 /* We need to know when we are making a constant pool; this determines
1163 whether data needs to be in the GOT or can be referenced via a GOT
1164 offset. */
1165 extern int making_const_table;
1166
1167 \f
1168 #define PRINT_OPERAND(STREAM,X,CODE) \
1169 thumb_print_operand((STREAM), (X), (CODE))
1170
1171 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1172 { \
1173 if (GET_CODE ((X)) == REG) \
1174 fprintf ((STREAM), "[%s]", reg_names[REGNO ((X))]); \
1175 else if (GET_CODE ((X)) == POST_INC) \
1176 fprintf ((STREAM), "%s!", reg_names[REGNO (XEXP (X, 0))]); \
1177 else if (GET_CODE ((X)) == PLUS) \
1178 { \
1179 if (GET_CODE (XEXP ((X), 1)) == CONST_INT) \
1180 fprintf ((STREAM), "[%s, #%d]", \
1181 reg_names[REGNO (XEXP ((X), 0))], \
1182 (int) INTVAL (XEXP ((X), 1))); \
1183 else \
1184 fprintf ((STREAM), "[%s, %s]", \
1185 reg_names[REGNO (XEXP ((X), 0))], \
1186 reg_names[REGNO (XEXP ((X), 1))]); \
1187 } \
1188 else \
1189 output_addr_const ((STREAM), (X)); \
1190 }
1191
1192 /* Handles PIC addr specially */
1193 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
1194 { \
1195 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
1196 { \
1197 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
1198 fputs(" - (", STREAM); \
1199 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
1200 fputs(")", STREAM); \
1201 } \
1202 else output_addr_const(STREAM, X); \
1203 \
1204 /* Mark symbols as position independent. We only do this in the \
1205 .text segment, not in the .data segment. */ \
1206 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
1207 (GET_CODE(X) == SYMBOL_REF || GET_CODE(X) == LABEL_REF)) \
1208 { \
1209 if (GET_CODE(X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(X)) \
1210 fprintf(STREAM, "(GOTOFF)"); \
1211 else if (GET_CODE (X) == LABEL_REF) \
1212 fprintf(STREAM, "(GOTOFF)"); \
1213 else \
1214 fprintf(STREAM, "(GOT)"); \
1215 } \
1216 }
1217
1218 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '@' || ((CODE) == '_') || ((CODE) == '|'))
1219
1220 /* Emit a special directive when defining a function name.
1221 This is used by the assembler to assit with interworking. */
1222 #define ASM_DECLARE_FUNCTION_NAME(file, name, decl) \
1223 if (! is_called_in_ARM_mode (decl)) \
1224 fprintf (file, "\t.thumb_func\n") ; \
1225 else \
1226 fprintf (file, "\t.code\t32\n") ; \
1227 ASM_OUTPUT_LABEL (file, name)
1228
1229 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1230 asm_fprintf ((STREAM), "\tpush {%R%s}\n", reg_names[(REGNO)])
1231
1232 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1233 fprintf ((STREAM), "\tpop {%R%s}\n", reg_names[(REGNO)])
1234
1235 #define FINAL_PRESCAN_INSN(INSN,OPVEC,NOPERANDS) \
1236 final_prescan_insn((INSN))
1237 \f
1238 /* Controlling Debugging Information Format */
1239 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1240
1241 /* Specific options for DBX Output */
1242
1243 #define DEFAULT_GDB_EXTENSIONS 1
1244
1245 \f
1246 /* Cross Compilation and Floating Point */
1247
1248 #define REAL_ARITHMETIC
1249
1250 \f
1251 /* Miscellaneous Parameters */
1252
1253 #define PREDICATE_CODES \
1254 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}},
1255
1256 #define CASE_VECTOR_MODE Pmode
1257
1258 #define WORD_REGISTER_OPERATIONS
1259
1260 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1261
1262 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1263
1264 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1265
1266 #define MOVE_MAX 4
1267
1268 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1269
1270 #define STORE_FLAG_VALUE 1
1271
1272 #define Pmode SImode
1273
1274 #define FUNCTION_MODE SImode
1275
1276 #define DOLLARS_IN_IDENTIFIERS 0
1277
1278 #define NO_DOLLAR_IN_LABEL 1
1279
1280 #define HAVE_ATEXIT
1281
1282 /* The literal pool needs to reside in the text area due to the
1283 limited PC addressing range: */
1284 #define MACHINE_DEPENDENT_REORG(INSN) thumb_reorg ((INSN))
1285
1286 \f
1287 /* Options specific to Thumb */
1288
1289 /* True if a return instruction can be used in this function. */
1290 int thumb_trivial_epilogue ();
1291 #define USE_RETURN (reload_completed && thumb_trivial_epilogue ())
1292
1293 extern char * thumb_unexpanded_epilogue ();
1294 extern char * output_move_mem_multiple ();
1295 extern char * thumb_load_double_from_address ();
1296 extern char * output_return ();
1297 extern int far_jump_used_p();
1298 extern int is_called_in_ARM_mode ();
1299
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