gcc/config/rs6000/rs6000-c.c

   1 /* Subroutines for the C front end on the PowerPC architecture.
   2    Copyright (C) 2002-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Zack Weinberg <zack@codesourcery.com>
   5    and Paolo Bonzini <bonzini@gnu.org>
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published
  11    by the Free Software Foundation; either version 3, or (at your
  12    option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GCC; see the file COPYING3.  If not see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "target.h"
  27 #include "c-family/c-common.h"
  28 #include "memmodel.h"
  29 #include "tm_p.h"
  30 #include "stringpool.h"
  31 #include "stor-layout.h"
  32 #include "c-family/c-pragma.h"
  33 #include "langhooks.h"
  34 #include "c/c-tree.h"
  35
  36
  37
  38 /* Handle the machine specific pragma longcall.  Its syntax is
  39
  40    # pragma longcall ( TOGGLE )
  41
  42    where TOGGLE is either 0 or 1.
  43
  44    rs6000_default_long_calls is set to the value of TOGGLE, changing
  45    whether or not new function declarations receive a longcall
  46    attribute by default.  */
  47
  48 #define SYNTAX_ERROR(gmsgid) do {                                       \
  49   warning (OPT_Wpragmas, gmsgid);                                       \
  50   warning (OPT_Wpragmas, "ignoring malformed #pragma longcall");        \
  51   return;                                                               \
  52 } while (0)
  53
  54 void
  55 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
  56 {
  57   tree x, n;
  58
  59   /* If we get here, generic code has already scanned the directive
  60      leader and the word "longcall".  */
  61
  62   if (pragma_lex (&x) != CPP_OPEN_PAREN)
  63     SYNTAX_ERROR ("missing open paren");
  64   if (pragma_lex (&n) != CPP_NUMBER)
  65     SYNTAX_ERROR ("missing number");
  66   if (pragma_lex (&x) != CPP_CLOSE_PAREN)
  67     SYNTAX_ERROR ("missing close paren");
  68
  69   if (n != integer_zero_node && n != integer_one_node)
  70     SYNTAX_ERROR ("number must be 0 or 1");
  71
  72   if (pragma_lex (&x) != CPP_EOF)
  73     warning (OPT_Wpragmas, "junk at end of #pragma longcall");
  74
  75   rs6000_default_long_calls = (n == integer_one_node);
  76 }
  77
  78 /* Handle defining many CPP flags based on TARGET_xxx.  As a general
  79    policy, rather than trying to guess what flags a user might want a
  80    #define for, it's better to define a flag for everything.  */
  81
  82 #define builtin_define(TXT) cpp_define (pfile, TXT)
  83 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
  84
  85 /* Keep the AltiVec keywords handy for fast comparisons.  */
  86 static GTY(()) tree __vector_keyword;
  87 static GTY(()) tree vector_keyword;
  88 static GTY(()) tree __pixel_keyword;
  89 static GTY(()) tree pixel_keyword;
  90 static GTY(()) tree __bool_keyword;
  91 static GTY(()) tree bool_keyword;
  92 static GTY(()) tree _Bool_keyword;
  93 static GTY(()) tree __int128_type;
  94 static GTY(()) tree __uint128_type;
  95
  96 /* Preserved across calls.  */
  97 static tree expand_bool_pixel;
  98
  99 static cpp_hashnode *
 100 altivec_categorize_keyword (const cpp_token *tok)
 101 {
 102   if (tok->type == CPP_NAME)
 103     {
 104       cpp_hashnode *ident = tok->val.node.node;
 105
 106       if (ident == C_CPP_HASHNODE (vector_keyword))
 107         return C_CPP_HASHNODE (__vector_keyword);
 108
 109       if (ident == C_CPP_HASHNODE (pixel_keyword))
 110         return C_CPP_HASHNODE (__pixel_keyword);
 111
 112       if (ident == C_CPP_HASHNODE (bool_keyword))
 113         return C_CPP_HASHNODE (__bool_keyword);
 114
 115       if (ident == C_CPP_HASHNODE (_Bool_keyword))
 116         return C_CPP_HASHNODE (__bool_keyword);
 117
 118       return ident;
 119     }
 120
 121   return 0;
 122 }
 123
 124 static void
 125 init_vector_keywords (void)
 126 {
 127   /* Keywords without two leading underscores are context-sensitive, and hence
 128      implemented as conditional macros, controlled by the
 129      rs6000_macro_to_expand() function below.  If we have ISA 2.07 64-bit
 130      support, record the __int128_t and __uint128_t types.  */
 131
 132   __vector_keyword = get_identifier ("__vector");
 133   C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
 134
 135   __pixel_keyword = get_identifier ("__pixel");
 136   C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
 137
 138   __bool_keyword = get_identifier ("__bool");
 139   C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
 140
 141   vector_keyword = get_identifier ("vector");
 142   C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
 143
 144   pixel_keyword = get_identifier ("pixel");
 145   C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
 146
 147   bool_keyword = get_identifier ("bool");
 148   C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
 149
 150   _Bool_keyword = get_identifier ("_Bool");
 151   C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 152
 153   if (TARGET_VADDUQM)
 154     {
 155       __int128_type = get_identifier ("__int128_t");
 156       __uint128_type = get_identifier ("__uint128_t");
 157     }
 158 }
 159
 160 /* Helper function to find out which RID_INT_N_* code is the one for
 161    __int128, if any.  Returns RID_MAX+1 if none apply, which is safe
 162    (for our purposes, since we always expect to have __int128) to
 163    compare against.  */
 164 static int
 165 rid_int128(void)
 166 {
 167   int i;
 168
 169   for (i = 0; i < NUM_INT_N_ENTS; i ++)
 170     if (int_n_enabled_p[i]
 171         && int_n_data[i].bitsize == 128)
 172       return RID_INT_N_0 + i;
 173
 174   return RID_MAX + 1;
 175 }
 176
 177 /* Called to decide whether a conditional macro should be expanded.
 178    Since we have exactly one such macro (i.e, 'vector'), we do not
 179    need to examine the 'tok' parameter.  */
 180
 181 static cpp_hashnode *
 182 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
 183 {
 184   cpp_hashnode *expand_this = tok->val.node.node;
 185   cpp_hashnode *ident;
 186
 187   /* If the current machine does not have altivec, don't look for the
 188      keywords.  */
 189   if (!TARGET_ALTIVEC)
 190     return NULL;
 191
 192   ident = altivec_categorize_keyword (tok);
 193
 194   if (ident != expand_this)
 195     expand_this = NULL;
 196
 197   if (ident == C_CPP_HASHNODE (__vector_keyword))
 198     {
 199       int idx = 0;
 200       do
 201         tok = cpp_peek_token (pfile, idx++);
 202       while (tok->type == CPP_PADDING);
 203       ident = altivec_categorize_keyword (tok);
 204
 205       if (ident == C_CPP_HASHNODE (__pixel_keyword))
 206         {
 207           expand_this = C_CPP_HASHNODE (__vector_keyword);
 208           expand_bool_pixel = __pixel_keyword;
 209         }
 210       else if (ident == C_CPP_HASHNODE (__bool_keyword))
 211         {
 212           expand_this = C_CPP_HASHNODE (__vector_keyword);
 213           expand_bool_pixel = __bool_keyword;
 214         }
 215       /* The boost libraries have code with Iterator::vector vector in it.  If
 216          we allow the normal handling, this module will be called recursively,
 217          and the vector will be skipped.; */
 218       else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
 219         {
 220           enum rid rid_code = (enum rid)(ident->rid_code);
 221           enum node_type itype = ident->type;
 222           /* If there is a function-like macro, check if it is going to be
 223              invoked with or without arguments.  Without following ( treat
 224              it like non-macro, otherwise the following cpp_get_token eats
 225              what should be preserved.  */
 226           if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
 227             {
 228               int idx2 = idx;
 229               do
 230                 tok = cpp_peek_token (pfile, idx2++);
 231               while (tok->type == CPP_PADDING);
 232               if (tok->type != CPP_OPEN_PAREN)
 233                 itype = NT_VOID;
 234             }
 235           if (itype == NT_MACRO)
 236             {
 237               do
 238                 (void) cpp_get_token (pfile);
 239               while (--idx > 0);
 240               do
 241                 tok = cpp_peek_token (pfile, idx++);
 242               while (tok->type == CPP_PADDING);
 243               ident = altivec_categorize_keyword (tok);
 244               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 245                 {
 246                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 247                   expand_bool_pixel = __pixel_keyword;
 248                   rid_code = RID_MAX;
 249                 }
 250               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 251                 {
 252                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 253                   expand_bool_pixel = __bool_keyword;
 254                   rid_code = RID_MAX;
 255                 }
 256               else if (ident)
 257                 rid_code = (enum rid)(ident->rid_code);
 258             }
 259
 260           if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
 261               || rid_code == RID_SHORT || rid_code == RID_SIGNED
 262               || rid_code == RID_INT || rid_code == RID_CHAR
 263               || rid_code == RID_FLOAT
 264               || (rid_code == RID_DOUBLE && TARGET_VSX)
 265               || (rid_code == rid_int128 () && TARGET_VADDUQM))
 266             {
 267               expand_this = C_CPP_HASHNODE (__vector_keyword);
 268               /* If the next keyword is bool or pixel, it
 269                  will need to be expanded as well.  */
 270               do
 271                 tok = cpp_peek_token (pfile, idx++);
 272               while (tok->type == CPP_PADDING);
 273               ident = altivec_categorize_keyword (tok);
 274
 275               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 276                 expand_bool_pixel = __pixel_keyword;
 277               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 278                 expand_bool_pixel = __bool_keyword;
 279               else
 280                 {
 281                   /* Try two tokens down, too.  */
 282                   do
 283                     tok = cpp_peek_token (pfile, idx++);
 284                   while (tok->type == CPP_PADDING);
 285                   ident = altivec_categorize_keyword (tok);
 286                   if (ident == C_CPP_HASHNODE (__pixel_keyword))
 287                     expand_bool_pixel = __pixel_keyword;
 288                   else if (ident == C_CPP_HASHNODE (__bool_keyword))
 289                     expand_bool_pixel = __bool_keyword;
 290                 }
 291             }
 292
 293           /* Support vector __int128_t, but we don't need to worry about bool
 294              or pixel on this type.  */
 295           else if (TARGET_VADDUQM
 296                    && (ident == C_CPP_HASHNODE (__int128_type)
 297                        || ident == C_CPP_HASHNODE (__uint128_type)))
 298             expand_this = C_CPP_HASHNODE (__vector_keyword);
 299         }
 300     }
 301   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
 302     {
 303       expand_this = C_CPP_HASHNODE (__pixel_keyword);
 304       expand_bool_pixel = 0;
 305     }
 306   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
 307     {
 308       expand_this = C_CPP_HASHNODE (__bool_keyword);
 309       expand_bool_pixel = 0;
 310     }
 311
 312   return expand_this;
 313 }
 314
 315
 316 /* Define or undefine a single macro.  */
 317
 318 static void
 319 rs6000_define_or_undefine_macro (bool define_p, const char *name)
 320 {
 321   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 322     fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
 323
 324   if (define_p)
 325     cpp_define (parse_in, name);
 326   else
 327     cpp_undef (parse_in, name);
 328 }
 329
 330 /* Define or undefine macros based on the current target.  If the user does
 331    #pragma GCC target, we need to adjust the macros dynamically.  Note, some of
 332    the options needed for builtins have been moved to separate variables, so
 333    have both the target flags and the builtin flags as arguments.  */
 334
 335 void
 336 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
 337                              HOST_WIDE_INT bu_mask)
 338 {
 339   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 340     fprintf (stderr,
 341              "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
 342              ", " HOST_WIDE_INT_PRINT_HEX ")\n",
 343              (define_p) ? "define" : "undef",
 344              flags, bu_mask);
 345
 346   /* Each of the flags mentioned below controls whether certain
 347      preprocessor macros will be automatically defined when
 348      preprocessing source files for compilation by this compiler.
 349      While most of these flags can be enabled or disabled
 350      explicitly by specifying certain command-line options when
 351      invoking the compiler, there are also many ways in which these
 352      flags are enabled or disabled implicitly, based on compiler
 353      defaults, configuration choices, and on the presence of certain
 354      related command-line options.  Many, but not all, of these
 355      implicit behaviors can be found in file "rs6000.c", the
 356      rs6000_option_override_internal() function.
 357
 358      In general, each of the flags may be automatically enabled in
 359      any of the following conditions:
 360
 361      1. If no -mcpu target is specified on the command line and no
 362         --with-cpu target is specified to the configure command line
 363         and the TARGET_DEFAULT macro for this default cpu host
 364         includes the flag, and the flag has not been explicitly disabled
 365         by command-line options.
 366
 367      2. If the target specified with -mcpu=target on the command line, or
 368         in the absence of a -mcpu=target command-line option, if the
 369         target specified using --with-cpu=target on the configure
 370         command line, is disqualified because the associated binary
 371         tools (e.g. the assembler) lack support for the requested cpu,
 372         and the TARGET_DEFAULT macro for this default cpu host
 373         includes the flag, and the flag has not been explicitly disabled
 374         by command-line options.
 375
 376      3. If either of the above two conditions apply except that the
 377         TARGET_DEFAULT macro is defined to equal zero, and
 378         TARGET_POWERPC64 and
 379         a) BYTES_BIG_ENDIAN and the flag to be enabled is either
 380            MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
 381            target), or
 382         b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
 383            MASK_POWERPC64 or it is one of the flags included in
 384            ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
 385
 386      4. If a cpu has been requested with a -mcpu=target command-line option
 387         and this cpu has not been disqualified due to shortcomings of the
 388         binary tools, and the set of flags associated with the requested cpu
 389         include the flag to be enabled.  See rs6000-cpus.def for macro
 390         definitions that represent various ABI standards
 391         (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
 392         the specific flags that are associated with each of the cpu
 393         choices that can be specified as the target of a -mcpu=target
 394         compile option, or as the the target of a --with-cpu=target
 395         configure option.  Target flags that are specified in either
 396         of these two ways are considered "implicit" since the flags
 397         are not mentioned specifically by name.
 398
 399         Additional documentation describing behavior specific to
 400         particular flags is provided below, immediately preceding the
 401         use of each relevant flag.
 402
 403      5. If there is no -mcpu=target command-line option, and the cpu
 404         requested by a --with-cpu=target command-line option has not
 405         been disqualified due to shortcomings of the binary tools, and
 406         the set of flags associated with the specified target include
 407         the flag to be enabled.  See the notes immediately above for a
 408         summary of the flags associated with particular cpu
 409         definitions.  */
 410
 411   /* rs6000_isa_flags based options.  */
 412   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
 413   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 414     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
 415   if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 416     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
 417   if ((flags & OPTION_MASK_POWERPC64) != 0)
 418     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
 419   if ((flags & OPTION_MASK_MFCRF) != 0)
 420     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
 421   if ((flags & OPTION_MASK_POPCNTB) != 0)
 422     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
 423   if ((flags & OPTION_MASK_FPRND) != 0)
 424     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
 425   if ((flags & OPTION_MASK_CMPB) != 0)
 426     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
 427   if ((flags & OPTION_MASK_MFPGPR) != 0)
 428     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
 429   if ((flags & OPTION_MASK_POPCNTD) != 0)
 430     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
 431   /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 432      turned off in any of the following conditions:
 433      1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
 434         disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
 435         enabled.
 436      2. TARGET_VSX is off.  */
 437   if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
 438     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
 439   if ((flags & OPTION_MASK_MODULO) != 0)
 440     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
 441   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 442     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
 443   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
 444     rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
 445   /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
 446      in any of the following conditions:
 447      1. The command line specifies either -maltivec=le or -maltivec=be.
 448      2. The operating system is Darwin and it is configured for 64
 449         bit.  (See darwin_rs6000_override_options.)
 450      3. The operating system is Darwin and the operating system
 451         version is 10.5 or higher and the user has not explicitly
 452         disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
 453         the compiler is not producing code for integration within the
 454         kernel.  (See darwin_rs6000_override_options.)
 455      Note that the OPTION_MASK_ALTIVEC flag is automatically turned
 456      off in any of the following conditions:
 457      1. The operating system does not support saving of AltiVec
 458         registers (OS_MISSING_ALTIVEC).
 459      2. If an inner context (as introduced by
 460         __attribute__((__target__())) or #pragma GCC target()
 461         requests a target that normally enables the
 462         OPTION_MASK_ALTIVEC flag but the outer-most "main target"
 463         does not support the rs6000_altivec_abi, this flag is
 464         turned off for the inner context unless OPTION_MASK_ALTIVEC
 465         was explicitly enabled for the inner context.  */
 466   if ((flags & OPTION_MASK_ALTIVEC) != 0)
 467     {
 468       const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
 469       rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
 470       rs6000_define_or_undefine_macro (define_p, vec_str);
 471
 472           /* Define this when supporting context-sensitive keywords.  */
 473       if (!flag_iso)
 474         rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
 475     }
 476   /* Note that the OPTION_MASK_VSX flag is automatically turned off in
 477      the following conditions:
 478      1. The operating system does not support saving of AltiVec
 479         registers (OS_MISSING_ALTIVEC).
 480      2. If any of the options TARGET_HARD_FLOAT, TARGET_FPRS,
 481         TARGET_SINGLE_FLOAT, or TARGET_DOUBLE_FLOAT are turned off.
 482         Hereafter, the OPTION_MASK_VSX flag is considered to have been
 483         turned off explicitly.
 484      3. If TARGET_PAIRED_FLOAT was enabled.  Hereafter, the
 485         OPTION_MASK_VSX flag is considered to have been turned off
 486         explicitly.
 487      4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
 488         compilation context, or if it is turned on by any means in an
 489         inner compilation context.  Hereafter, the OPTION_MASK_VSX
 490         flag is considered to have been turned off explicitly.
 491      5. If TARGET_ALTIVEC was explicitly disabled.  Hereafter, the
 492         OPTION_MASK_VSX flag is considered to have been turned off
 493         explicitly.
 494      6. If an inner context (as introduced by
 495         __attribute__((__target__())) or #pragma GCC target()
 496         requests a target that normally enables the
 497         OPTION_MASK_VSX flag but the outer-most "main target"
 498         does not support the rs6000_altivec_abi, this flag is
 499         turned off for the inner context unless OPTION_MASK_VSX
 500         was explicitly enabled for the inner context.  */
 501   if ((flags & OPTION_MASK_VSX) != 0)
 502     rs6000_define_or_undefine_macro (define_p, "__VSX__");
 503   if ((flags & OPTION_MASK_HTM) != 0)
 504     {
 505       rs6000_define_or_undefine_macro (define_p, "__HTM__");
 506       /* Tell the user that our HTM insn patterns act as memory barriers.  */
 507       rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
 508     }
 509   /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 510      off in the following conditions:
 511      1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
 512         were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
 513         not turned on explicitly.
 514      2. If TARGET_ALTIVEC is turned off.  Hereafter, the
 515         OPTION_MASK_P8_VECTOR flag is considered to have been turned off
 516         explicitly.
 517      3. If TARGET_VSX is turned off.  Hereafter, the OPTION_MASK_P8_VECTOR
 518         flag is considered to have been turned off explicitly.  */
 519   if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 520     rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
 521   /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
 522      off in the following conditions:
 523      1. If TARGET_P8_VECTOR is turned off. Hereafter, the
 524         OPTION_MASK_P9_VECTOR flag is considered to have been turned off
 525         explicitly.  */
 526   if ((flags & OPTION_MASK_P9_VECTOR) != 0)
 527     rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
 528   /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
 529      turned off in the following conditions:
 530      1. If TARGET_POWERPC64 is turned off.
 531      2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
 532         load/store are disabled on little endian).  */
 533   if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
 534     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
 535   /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
 536      turned off in the following conditions:
 537      1. If TARGET_POWERPC64 is turned off.
 538      Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
 539      automatically turned on in the following conditions:
 540      1. If TARGET_QUAD_MEMORY and this flag was not explicitly
 541         disabled.  */
 542   if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
 543     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
 544   /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
 545      in the following conditions:
 546      1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
 547         are turned off explicitly and OPTION_MASK_CRYPTO is not turned
 548         on explicitly.
 549      2. If TARGET_ALTIVEC is turned off.  */
 550   if ((flags & OPTION_MASK_CRYPTO) != 0)
 551     rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
 552   /* Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
 553      turned on in the following conditions:
 554      1. If TARGET_UPPER_REGS is explicitly turned on and
 555         TARGET_VSX is turned on and OPTION_MASK_UPPER_REGS_DF is not
 556         explicitly turned off.  Hereafter, the
 557         OPTION_MASK_UPPER_REGS_DF flag is considered to have been
 558         explicitly set.
 559      Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
 560      turned off in the following conditions:
 561      1. If TARGET_UPPER_REGS is explicitly turned off and TARGET_VSX
 562         is turned on and OPTION_MASK_UPPER_REGS_DF is not explicitly
 563         turned on.  Hereafter, the OPTION_MASK_UPPER_REGS_DF flag is
 564         considered to have been explicitly cleared.
 565      2. If TARGET_UPPER_REGS_DF is turned on but TARGET_VSX is turned
 566         off.  */
 567   if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
 568     rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
 569   /* Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
 570      turned on in the following conditions:
 571      1. If TARGET_UPPER_REGS is explicitly turned on and
 572         TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
 573         turned off explicitly.  Hereafter, the
 574         OPTION_MASK_UPPER_REGS_SF flag is considered to have been
 575         explicitly set.
 576      Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
 577      turned off in the following conditions:
 578      1. If TARGET_UPPER_REGS is explicitly turned off and
 579         TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
 580         turned off explicitly.  Hereafter, the
 581         OPTION_MASK_UPPER_REGS_SF flag is considered to have been
 582         explicitly cleared.
 583      2. If TARGET_P8_VECTOR is off.  */
 584   if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
 585     rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
 586
 587   /* options from the builtin masks.  */
 588   /* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE
 589      (e.g. -mspe).  */
 590   if ((bu_mask & RS6000_BTM_SPE) != 0)
 591     rs6000_define_or_undefine_macro (define_p, "__SPE__");
 592   /* Note that RS6000_BTM_PAIRED is enabled only if
 593      TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired).  */
 594   if ((bu_mask & RS6000_BTM_PAIRED) != 0)
 595     rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
 596   /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
 597      PROCESSOR_CELL) (e.g. -mcpu=cell).  */
 598   if ((bu_mask & RS6000_BTM_CELL) != 0)
 599     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 600 }
 601
 602 void
 603 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 604 {
 605   /* Define all of the common macros.  */
 606   rs6000_target_modify_macros (true, rs6000_isa_flags,
 607                                rs6000_builtin_mask_calculate ());
 608
 609   if (TARGET_FRE)
 610     builtin_define ("__RECIP__");
 611   if (TARGET_FRES)
 612     builtin_define ("__RECIPF__");
 613   if (TARGET_FRSQRTE)
 614     builtin_define ("__RSQRTE__");
 615   if (TARGET_FRSQRTES)
 616     builtin_define ("__RSQRTEF__");
 617   if (TARGET_FLOAT128_KEYWORD)
 618     builtin_define ("__FLOAT128__");
 619   if (TARGET_FLOAT128_TYPE)
 620     builtin_define ("__FLOAT128_TYPE__");
 621   if (TARGET_FLOAT128_HW)
 622     builtin_define ("__FLOAT128_HARDWARE__");
 623   if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
 624     builtin_define ("__ibm128=long double");
 625
 626   /* We needed to create a keyword if -mfloat128-type was used but not -mfloat,
 627      so we used __ieee128.  If -mfloat128 was used, create a #define back to
 628      the real keyword in case somebody used it.  */
 629   if (TARGET_FLOAT128_KEYWORD)
 630     builtin_define ("__ieee128=__float128");
 631
 632   if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
 633     {
 634       /* Define the AltiVec syntactic elements.  */
 635       builtin_define ("__vector=__attribute__((altivec(vector__)))");
 636       builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
 637       builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
 638
 639       if (!flag_iso)
 640         {
 641           builtin_define ("vector=vector");
 642           builtin_define ("pixel=pixel");
 643           builtin_define ("bool=bool");
 644           builtin_define ("_Bool=_Bool");
 645           init_vector_keywords ();
 646
 647           /* Enable context-sensitive macros.  */
 648           cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
 649         }
 650     }
 651   if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
 652       ||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
 653     builtin_define ("_SOFT_DOUBLE");
 654   /* Used by lwarx/stwcx. errata work-around.  */
 655   if (rs6000_cpu == PROCESSOR_PPC405)
 656     builtin_define ("__PPC405__");
 657   /* Used by libstdc++.  */
 658   if (TARGET_NO_LWSYNC)
 659     builtin_define ("__NO_LWSYNC__");
 660
 661   if (TARGET_EXTRA_BUILTINS)
 662     {
 663       /* For the VSX builtin functions identical to Altivec functions, just map
 664          the altivec builtin into the vsx version (the altivec functions
 665          generate VSX code if -mvsx).  */
 666       builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
 667       builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
 668       builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
 669       builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
 670       builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
 671       builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
 672       builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
 673
 674       /* Also map the a and m versions of the multiply/add instructions to the
 675          builtin for people blindly going off the instruction manual.  */
 676       builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
 677       builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
 678       builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
 679       builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
 680       builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
 681       builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
 682       builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
 683       builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
 684       builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
 685       builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
 686       builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
 687       builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
 688       builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
 689       builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
 690       builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
 691       builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
 692     }
 693
 694   /* Tell users they can use __builtin_bswap{16,64}.  */
 695   builtin_define ("__HAVE_BSWAP__");
 696
 697   /* May be overridden by target configuration.  */
 698   RS6000_CPU_CPP_ENDIAN_BUILTINS();
 699
 700   if (TARGET_LONG_DOUBLE_128)
 701     {
 702       builtin_define ("__LONG_DOUBLE_128__");
 703       builtin_define ("__LONGDOUBLE128");
 704
 705       if (TARGET_IEEEQUAD)
 706         builtin_define ("__LONG_DOUBLE_IEEE128__");
 707       else
 708         builtin_define ("__LONG_DOUBLE_IBM128__");
 709     }
 710
 711   switch (TARGET_CMODEL)
 712     {
 713       /* Deliberately omit __CMODEL_SMALL__ since that was the default
 714          before --mcmodel support was added.  */
 715     case CMODEL_MEDIUM:
 716       builtin_define ("__CMODEL_MEDIUM__");
 717       break;
 718     case CMODEL_LARGE:
 719       builtin_define ("__CMODEL_LARGE__");
 720       break;
 721     default:
 722       break;
 723     }
 724
 725   switch (rs6000_current_abi)
 726     {
 727     case ABI_V4:
 728       builtin_define ("_CALL_SYSV");
 729       break;
 730     case ABI_AIX:
 731       builtin_define ("_CALL_AIXDESC");
 732       builtin_define ("_CALL_AIX");
 733       builtin_define ("_CALL_ELF=1");
 734       break;
 735     case ABI_ELFv2:
 736       builtin_define ("_CALL_ELF=2");
 737       break;
 738     case ABI_DARWIN:
 739       builtin_define ("_CALL_DARWIN");
 740       break;
 741     default:
 742       break;
 743     }
 744
 745   /* Vector element order.  */
 746   if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
 747     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
 748   else
 749     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
 750
 751   /* Let the compiled code know if 'f' class registers will not be available.  */
 752   if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
 753     builtin_define ("__NO_FPRS__");
 754
 755   /* Whether aggregates passed by value are aligned to a 16 byte boundary
 756      if their alignment is 16 bytes or larger.  */
 757   if ((TARGET_MACHO && rs6000_darwin64_abi)
 758       || DEFAULT_ABI == ABI_ELFv2
 759       || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
 760     builtin_define ("__STRUCT_PARM_ALIGN__=16");
 761
 762   /* Generate defines for Xilinx FPU. */
 763   if (rs6000_xilinx_fpu)
 764     {
 765       builtin_define ("_XFPU");
 766       if (rs6000_single_float && ! rs6000_double_float)
 767         {
 768           if (rs6000_simple_fpu)
 769             builtin_define ("_XFPU_SP_LITE");
 770           else
 771             builtin_define ("_XFPU_SP_FULL");
 772         }
 773       if (rs6000_double_float)
 774         {
 775           if (rs6000_simple_fpu)
 776             builtin_define ("_XFPU_DP_LITE");
 777           else
 778             builtin_define ("_XFPU_DP_FULL");
 779         }
 780     }
 781 }
 782
 783 \f
 784 struct altivec_builtin_types
 785 {
 786   enum rs6000_builtins code;
 787   enum rs6000_builtins overloaded_code;
 788   signed char ret_type;
 789   signed char op1;
 790   signed char op2;
 791   signed char op3;
 792 };
 793
 794 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
 795   /* Unary AltiVec/VSX builtins.  */
 796   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
 797     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 798   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
 799     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 800   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
 801     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 802   { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
 803     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
 804   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
 805     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 806   { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
 807     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 808   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
 809     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 810   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
 811     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 812   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
 813     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 814   { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
 815     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 816   { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
 817     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 818   { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
 819     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 820   { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
 821     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 822   { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
 823     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 824   { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
 825     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 826   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 827     RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
 828   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 829     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
 830   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 831     RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
 832   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 833     RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
 834   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 835     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
 836   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 837     RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
 838   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 839     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
 840   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 841     RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
 842   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 843     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
 844   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 845     RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
 846   { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
 847     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 848   { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
 849     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 850   { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
 851     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 852   { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
 853     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 854   { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
 855     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 856   { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
 857     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 858   { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
 859     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 860   { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
 861     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 862   { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
 863     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 864   { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
 865     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 866   { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
 867     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 868   { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
 869     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 870   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 871     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 872   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 873     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 874   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 875     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 876   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 877     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 878   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 879     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 880   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 881     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 882   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
 883     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 884   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 885     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 886   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 887     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 888   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 889     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 890   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 891     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 892   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 893     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 894   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 895     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 896   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 897     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 898   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 899     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 900   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 901     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 902   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 903     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 904   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
 905     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 906   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 907     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 908   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 909     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 910   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 911     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 912   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 913     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 914   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 915     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 916   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 917     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 918   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 919     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 920   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 921     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 922   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 923     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 924   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 925     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 926
 927   /* Binary AltiVec/VSX builtins.  */
 928   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 929     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
 930   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 931     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
 932   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 933     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
 934   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 935     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 936   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 937     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
 938   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 939     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 940   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 941     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
 942   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 943     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
 944   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 945     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 946   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 947     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 948   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 949     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
 950   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 951     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 952   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 953     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 954   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 955     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 956   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 957     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 958   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 959     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 960   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 961     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 962   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 963     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 964   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 965     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
 966   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 967     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
 968   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 969     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
 970   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 971     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 972   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 973     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
 974   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 975     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 976   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
 977     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 978   { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
 979     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 980   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 981     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
 982   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 983     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
 984     RS6000_BTI_unsigned_V1TI, 0 },
 985   { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
 986     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 987   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 988     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 989   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 990     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 991   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 992     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
 993   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 994     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 995   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 996     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 997   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 998     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 999   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1000     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1001   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1002     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1003   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1004     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1005   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1006     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1007   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1008     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1009   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1010     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1011   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1012     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1013   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1014     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1015   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1016     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1017   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1018     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1019   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1020     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1021   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1022     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1023   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1024     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1025   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1026     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1027   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1028     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1029   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1030     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1031   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1032     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1033   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1034     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1035   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1036     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1037   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1038     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1039     RS6000_BTI_unsigned_V4SI, 0 },
1040   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1041     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1042     RS6000_BTI_unsigned_V1TI, 0 },
1043   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1044     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1045   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1046     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1047     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1048   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1049     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1050   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1051     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1052   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1053     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1054   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1055     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1056   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1057     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1058   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1059     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1060   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1061     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1062   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1063     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1064   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1065     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1066   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1067     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1068   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1069     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1070   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1071     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1072   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1073     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1074   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1075     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1076   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1077     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1078   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1079     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1080   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1081     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1082   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1083     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1084   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1085     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1086   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1087     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1088   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1089     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1090   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1091     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1092   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1093     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1094   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1095     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1096   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1097     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1098   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1099     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1100   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1101     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1102   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1103     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1104   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1105     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1106   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1107     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1108   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1109     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1110   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1111     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1112   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1113     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1114   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1115     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1116   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1117     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1118   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1119     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1120   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1121     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1122   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1123     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1124   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1125     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1126   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1127     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1128   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1129     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1130   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1131     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1132   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1133     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1134   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1135     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1136   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1137     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1138   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1139     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1140   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1141     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1142   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1143     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1144   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1145     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1146   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1147     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1148   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1149     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1150   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1151     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1152   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1153     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1154   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1155     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1156   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1157     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1158   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1159     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1160   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1161     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1162   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1163     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1164   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1165     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1166   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1167     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1168   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1169     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1170   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1171     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1172   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1173     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1174   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1175     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1176   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1177     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1178   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1179     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1180   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1181     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1182   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1183     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1184   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1185     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1186   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1187     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1188   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1189     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1190   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1191     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1192   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1193     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1194   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1195     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1196   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1197     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1198   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1199     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1200   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1201     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1202   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1203     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1204   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1205     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1206   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1207     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1208   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1209     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1210   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1211     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1212   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1213     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1214   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1215     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1216   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1217     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1218   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1219     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1220   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1221     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1222   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1223     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1224   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1225     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1226   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1227     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1228   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1229     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1230   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1231     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1232   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1233     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1234   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1235     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1236   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1237     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1238   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1239     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1240   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1241     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1242   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1243     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1244   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1245     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1246   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1247     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1248   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1249     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1250   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1251     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1252   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1253     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1254   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1255     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1256   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1257     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1258   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1259     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1260   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1261     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1262   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1263     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1264   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1265     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1266   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1267     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1268   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1269     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1270   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1271     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1272   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1273     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1274   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1275     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1276   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1277     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1278   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1279     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1280   { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1281     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1282   { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1283     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1284   { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1285     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1286   { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1287     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1288   { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1289     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1290   { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1291     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1292   { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1293     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1294   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1295     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1296   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1297     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1298   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1299     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1300   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1301     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1302   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1303     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1304   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1305     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1306   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1307     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1308   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1309     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1310   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1311     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1312   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1313     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1314   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1315     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1316   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1317     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1318   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1319     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1320   { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1321     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1322   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1323     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1324
1325   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1326     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1327   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1328     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1329
1330   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1331     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1332   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1333     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1334
1335   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1336     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1337   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1338     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1339
1340   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1341     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1342   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1343     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1344   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1345     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1346   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1347     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1348     RS6000_BTI_unsigned_V16QI, 0},
1349   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1350     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1351   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1352     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1353     RS6000_BTI_unsigned_V8HI, 0},
1354   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1355     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1356   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1357     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1358     RS6000_BTI_unsigned_V4SI, 0},
1359   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1360     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1361   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1362     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1363     RS6000_BTI_unsigned_V2DI, 0},
1364   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1365     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1366   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1367     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1368   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1369     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1370   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1371     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1372   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1373     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1374   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1375     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1376   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1377     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1378   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1379     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1380   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1381     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1382   { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1383     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1384   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1385     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1386   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1387     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1388   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1389     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1390   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1391     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1392   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1393     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1394   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1395     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1396   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1397     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1398   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1399     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1400   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1401     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1402   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1403     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1404   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1405     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1406   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1407     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1408   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1409     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1410   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1411     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1412   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1413     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1414   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1415     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1416   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1417     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1418     RS6000_BTI_unsigned_V16QI, 0},
1419   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1420     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1421   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1422     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1423     RS6000_BTI_unsigned_V8HI, 0},
1424   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1425     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1426   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1427     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1428     RS6000_BTI_unsigned_V4SI, 0},
1429   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1430     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1431   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1432     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1433     RS6000_BTI_unsigned_V2DI, 0},
1434   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1435     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1436   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1437     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1438   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1439     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1440   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1441     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1442   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1443     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1444   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1445     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1446   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1447     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1448   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1449     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1450   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1451     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1452   { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1453     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1454   { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1455     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1456   { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1457     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1458   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1459     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1460   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1461     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1462   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1463     RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1464   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1465     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1466   { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1467     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1468   { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1469     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1470   { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1471     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1472   { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1473     RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1474   { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1475     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1476   { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1477     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1478   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1479     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1480   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1481     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1482   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1483     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1484   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1485     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1486   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1487     RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1488   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1489     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1490   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1491     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1492   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1493     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1494   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1495     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1496     ~RS6000_BTI_unsigned_V2DI, 0 },
1497   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1498     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1499   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1500     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1501   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1502     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1503   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1504     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1505   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1506     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1507   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1508     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1509   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1510     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1511   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1512     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1513   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1514     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1515   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1516     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1517   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1518     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1519   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1520     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1521   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1522     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1523   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1524     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1525   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1526     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1527   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1528     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1529   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1530     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1531   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1532     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1533   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1534     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1535   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1536     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1537   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1538     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1539   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1540     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1541   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1542     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1543   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1544     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1545   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1546     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1547   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1548     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1549   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1550     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1551   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1552     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1553   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1554     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1555   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1556     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1557   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1558     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1559   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1560     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1561   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1562     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1563   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1564     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1565   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1566     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1567   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1568     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1569   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1570     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1571   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1572     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1573   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1574     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1575   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1576     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1577   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1578     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1579   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1580     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1581   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1582     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1583   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1584     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1585   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1586     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1587   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1588     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1589   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1590     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1591   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1592     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1593   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1594     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1595   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1596     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1597   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1598     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1599   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1600     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1601   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1602     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1603   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1604     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1605   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1606     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1607   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1608     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1609   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1610     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1611   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1612     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1613     ~RS6000_BTI_unsigned_V16QI, 0 },
1614   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1615     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1616   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1617     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1618   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1619     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1620   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1621     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1622     ~RS6000_BTI_unsigned_V2DI, 0 },
1623   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1624     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1625   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1626     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1627   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1628     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1629   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1630     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1631   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1632     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1633   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1634     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1635   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1636     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1637   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1638     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1639   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1640     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1641   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1642     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1643   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1644     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1645   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1646     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1647   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1648     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1649   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1650     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1651   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1652     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1653     ~RS6000_BTI_unsigned_long_long, 0 },
1654   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1655     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1656   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1657     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1658   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1659     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1660   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1661     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1662   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1663     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1664   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1665     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1666   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1667     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1668   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1669     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1670   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1671     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1672   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1673     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1674   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1675     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1676   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1677     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1678   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1679     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1680   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1681     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1682     ~RS6000_BTI_unsigned_long_long, 0 },
1683   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1684     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1685   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1686     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1687   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1688     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1689   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1690     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1691   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1692     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1693   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1694     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1695   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1696     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1697   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1698     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1699   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1700     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1701   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1702     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1703   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1704     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1705   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1706     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1707   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1708     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1709   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1710     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1711   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1712     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1713   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1714     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1715   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1716     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1717   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1718     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1719   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1720     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1721   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1722     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1723   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1724     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1725   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1726     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1727   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1728     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1729   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1730     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1731   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1732     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1733   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1734     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1735   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1736     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1737   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1738     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1739   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1740     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1741   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1742     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1743   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1744     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1745   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1746     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1747   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1748     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1749   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1750     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1751   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1752     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1753   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1754     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1755   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1756     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1757   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1758     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1759   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1760     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1761   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1762     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1763   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1764     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1765   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1766     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1767   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1768     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1769   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1770     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1771   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1772     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1773   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1774     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1775   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1776     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1777   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1778     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1779   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1780     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1781   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1782     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1783   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1784     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1785   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1786     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1787   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1788     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1789   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1790     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1791   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1792     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1793   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1794     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1795   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1796     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1797   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1798     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1799   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1800     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1801   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1802     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1803   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1804     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1805   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1806     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1807   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1808     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1809   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1810     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1811   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1812     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1813   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1814     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1815   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1816     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1817   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1818     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1819   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1820     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1821   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1822     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1823   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1824     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1825   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1826     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1827   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1828     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1829   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1830     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1831   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1832     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1833   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1834     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1835   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1836     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1837   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1838     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1839   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1840     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1841   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1842     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1843   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1844     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1845   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1846     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1847   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1848     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1849   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1850     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1851   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1852     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1853   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1854     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1855   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1856     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1857   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1858     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1859   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1860     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1861   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1862     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1863   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1864     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1865   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1866     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1867   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1868     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1869   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1870     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1871   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1872     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1873   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1874     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1875   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1876     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1877   { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1878     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1879   { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1880     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1881   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1882     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1883   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1884     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1885   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1886     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1887   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1888     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1889   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1890     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1891   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1892     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1893   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1894     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1895   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1896     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1897   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1898     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1899   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1900     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1901   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1902     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1903   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1904     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1905   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1906     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1907   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1908     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1909   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1910     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1911   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1912     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1913   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1914     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1915   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1916     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1917   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1918     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1919   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1920     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1921   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1922     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1923   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1924     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1925   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1926     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1927   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1928     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1929   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1930     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1931   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1932     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1933   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1934     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1935   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1936     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1937   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1938     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1939   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1940     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1941   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1942     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1943   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1944     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1945   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1946     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1947   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1948     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1949   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1950     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1951   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1952     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1953   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1954     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1955   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1956     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1957   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1958     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1959   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1960     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1961   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1962     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1963   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1964     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1965   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1966     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1967   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1968     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1969   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1970     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1971   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1972     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1973   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1974     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1975   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1976     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1977   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1978     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1979   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1980     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1981   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
1982     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1983   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1984     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1985   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1986     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1987   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
1988     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1989   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1990     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1991   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1992     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1993   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
1994     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1995   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1996     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1997   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
1998     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1999   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2000     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2001   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2002     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2003   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2004     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2005   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2006     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2007   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2008     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2009   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2010     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2011   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2012     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2013   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2014     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2015   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2016     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2017   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2018     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2019   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2020     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2021   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2022     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2023   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2024     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2025   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2026     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2027   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2028     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2029   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2030     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2031   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2032     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2033   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2034     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2035   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2036     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2037   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2038     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2039   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2040     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2041   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2042     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2043   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2044     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2045   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2046     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2047   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2048     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2049   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2050     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2051   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2052     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2053   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2054     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2055   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2056     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2057   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2058     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2059   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2060     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2061   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2062     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2063   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2064     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2065   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2066     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2067   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2068     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2069   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2070     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2071   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2072     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2073   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2074     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2075   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2076     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2077   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2078     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2079   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2080     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2081   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2082     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2083   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2084     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2085   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2086     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2087   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2088     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2089   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2090     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2091   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2092     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2093   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2094     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2095   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2096     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2097   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2098     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2099   { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2100     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2101   { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2102     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2103   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2104     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2105   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2106     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2107   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2108     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2109   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2110     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2111   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2112     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2113   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2114     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2115   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2116     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2117   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2118     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2119   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2120     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2121   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2122     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2123   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2124     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2125   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2126     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2127   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2128     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2129   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2130     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2131   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2132     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2133   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2134     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2135   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2136     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2137   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2138     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2139   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2140     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2141   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2142     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2143   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2144     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2145   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2146     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2147   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2148     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2149   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2150     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2151   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2152     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2153   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2154     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2155   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2156     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2157   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2158     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2159   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2160     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2161   { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2162     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2163   { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2164     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2165   { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2166     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2167   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2168     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2169   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2170     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2171   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2172     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2173   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2174     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2175   { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2176     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2177   { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2178     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2179   { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2180     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2181   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2182     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2183   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2184     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2185   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2186     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2187   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2188     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2189   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2190     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2191   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2192     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2193   { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2194     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2195   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2196     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2197   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2198     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2199   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2200     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2201   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2202     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2203   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2204     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2205   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2206     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2207   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2208     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2209   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2210     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2211   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2212     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2213   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2214     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2215   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2216     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2217   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2218     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2219   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2220     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2221   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2222     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2223   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2224     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2225   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2226     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2227   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2228     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2229   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2230     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2231   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2232     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2233   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2234     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2235   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2236     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2237   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2238     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2239   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2240     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2241   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2242     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2243   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2244     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2245   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2246     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2247   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2248     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2249   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2250     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2251   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2252     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2253   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2254     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2255   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2256     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2257   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2258     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2259   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2260     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2261   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2262     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2263   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2264     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2265   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2266     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2267   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2268     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2269   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2270     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2271   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2272     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2273   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2274     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2275   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2276     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2277   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2278     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2279   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2280     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2281   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2282     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2283   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2284     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2285   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2286     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2287   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2288     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2289   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2290     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2291   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2292     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2293   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2294     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2295   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2296     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2297   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2298     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2299   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2300     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2301   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2302     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2303   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2304     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2305   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2306     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2307   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2308     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2309   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2310     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2311   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2312     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2313   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2314     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2315   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2316     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2317   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2318     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2319   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2320     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2321   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2322     RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2323   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2324     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2325   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2326     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2327   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2328     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2329   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2330     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2331   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2332     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2333   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2334     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2335   { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2336     RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2337   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2338     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2339   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2340     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2341   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2342     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2343   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2344     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2345   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2346     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2347   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2348     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2349   { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2350     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2351   { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2352     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2353   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2354     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2355   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2356     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2357   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2358     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2359   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2360     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2361   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2362     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2363   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2364     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2365   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2366     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2367   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2368     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2369   { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2370     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2371   { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2372     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2373   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2374     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2375   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2376     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2377   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2378     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2379   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2380     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2381   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2382     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2383   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2384     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2385   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2386     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2387   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2388     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2389   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2390     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2391   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2392     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2393   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2394     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2395   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2396     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2397   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2398     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2399   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2400     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2401   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2402     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2403   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2404     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2405   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2406     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2407     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2408   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2409     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2410     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2411   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2412     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2413     RS6000_BTI_unsigned_V4SI, 0 },
2414   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2415     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2416     RS6000_BTI_unsigned_V2DI, 0 },
2417   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2418     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2419   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2420     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2421   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2422     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2423   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2424     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2425   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2426     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2427   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2428     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2429   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2430     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2431   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2432     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2433   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2434     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2435   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2436     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2437   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2438     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2439   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2440     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2441   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2442     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2443   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2444     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2445   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2446     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2447   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2448     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2449   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2450     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2451   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2452     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2453   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2454     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2455   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2456     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2457   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2458     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2459   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2460     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2461   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2462     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2463   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2464     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2465   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2466     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2467   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2468     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2469   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2470     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2471   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2472     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2473   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2474     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2475   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2476     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2477   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2478     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2479   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2480     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2481   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2482     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2483   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2484     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2485   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2486     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2487   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2488     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2489   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2490     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2491   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2492     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2493   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2494     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2495   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2496     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2497   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2498     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2499   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2500     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2501   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2502     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2503   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2504     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2505   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2506     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2507   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2508     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2509   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2510     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2511   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2512     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2513   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2514     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2515   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2516     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2517   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2518     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2519   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2520     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2521   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2522     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2523   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2524     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2525   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2526     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2527   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2528     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2529   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2530     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2531   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2532     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2533   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2534     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2535   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2536     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2537   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2538     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2539   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2540     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2541   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2542     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2543   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2544     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2545   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2546     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2547   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2548     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2549   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2550     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2551   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2552     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2553   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2554     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2555   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2556     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2557   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2558     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2559   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2560     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2561   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2562     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2563   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2564     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2565   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2566     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2567   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2568     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2569   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2570     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2571   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2572     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2573   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2574     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2575   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2576     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2577   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2578     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2579   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2580     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2581   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2582     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2583   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2584     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2585   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2586     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2587   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2588     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2589   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2590     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2591   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2592     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2593   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2594     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2595   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2596     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2597   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2598     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2599   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2600     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2601   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2602     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2603   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2604     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2605   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2606     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2607   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2608     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2609   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2610     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2611   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2612     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2613   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2614     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2615   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2616     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2617   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2618     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2619   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2620     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2621   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2622     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2623   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2624     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2625   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2626     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2627   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2628     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2629   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2630     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2631   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2632     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2633   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2634     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2635   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2636     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2637   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2638     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2639   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2640     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2641   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2642     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2643   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2644     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2645   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2646     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2647   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2648     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2649   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2650     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2651   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2652     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2653   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2654     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2655   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2656     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2657   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2658     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2659   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2660     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2661   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2662     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2663   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2664     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2665   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2666     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2667   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2668     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2669   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2670     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2671   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2672     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2673   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2674     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2675   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2676     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2677   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2678     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2679   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2680     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2681   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2682     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2683   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2684     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2685   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2686     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2687   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2688     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2689   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2690     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2691   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2692     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2693   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2694     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2695   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2696     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2697   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2698     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2699   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2700     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2701   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2702     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2703   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2704     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2705   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2706     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2707   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2708     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2709   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2710     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2711   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2712     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2713   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2714     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2715   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2716     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2717   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2718     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2719   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2720     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2721   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2722     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2723   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2724     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2725   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2726     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2727   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2728     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2729   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2730     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2731   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2732     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2733   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2734     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2735   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2736     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2737   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2738     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2739   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2740     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2741   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2742     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2743   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2744     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2745   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2746     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2747   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2748     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2749   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2750     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2751   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2752     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2753   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2754     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2755   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2756     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2757   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2758     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2759   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2760     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2761   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2762     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2763   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2764     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2765   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2766     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2767   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2768     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2769   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2770     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2771   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2772     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2773   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2774     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2775   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2776     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2777   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2778     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2779   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2780     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2781   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2782     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2783   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2784     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2785   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2786     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2787   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2788     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2789   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2790     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2791   { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2792     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2793   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2794     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2795   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2796     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2797     RS6000_BTI_unsigned_V1TI, 0 },
2798   { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2799     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2800   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2801     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2802   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2803     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2804   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2805     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2806   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2807     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2808   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2809     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2810   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2811     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2812   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2813     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2814   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2815     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2816   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2817     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2818   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2819     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2820   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2821     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2822   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2823     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2824   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2825     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2826   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2827     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2828   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2829     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2830   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2831     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2832   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2833     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2834   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2835     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2836   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2837     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2838   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2839     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2840   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2841     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2842   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2843     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2844   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2845     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2846   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2847     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2848   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2849     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2850   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2851     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2852   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2853     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2854   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2855     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2856   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2857     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2858   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2859     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2860   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2861     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2862   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2863     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2864   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2865     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2866   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2867     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2868   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2869     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2870   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2871     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2872   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2873     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2874   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2875     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2876   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2877     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2878   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2879     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2880   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2881     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2882   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2883     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2884   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2885     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2886   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2887     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2888   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2889     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2890   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2891     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2892   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2893     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2894   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2895     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2896   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2897     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2898   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2899     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2900   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2901     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2902   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2903     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2904   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2905     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2906   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2907     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2908   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2909     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2910   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2911     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2912   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2913     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2914   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2915     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2916   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2917     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2918   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2919     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2920   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2921     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2922   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2923     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2924   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2925     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2926   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2927     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2928   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2929     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2930   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2931     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2932   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2933     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2934   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2935     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2936   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2937     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2938   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2939     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2940   { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
2941     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
2942   { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
2943     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2944   { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
2945     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2946   { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
2947     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2948   { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
2949     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2950   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
2951     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
2952   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
2953     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
2954   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
2955     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
2956   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
2957     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
2958   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
2959     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2960     ~RS6000_BTI_unsigned_V2DI, 0 },
2961   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
2962     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
2963     ~RS6000_BTI_unsigned_long_long, 0 },
2964   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
2965     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
2966   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
2967     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
2968   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
2969     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
2970   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
2971     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
2972   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
2973     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
2974   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
2975     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
2976   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
2977     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
2978   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
2979     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
2980   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
2981     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
2982   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
2983     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
2984   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
2985     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
2986   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
2987     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
2988   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
2989     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
2990     ~RS6000_BTI_unsigned_V16QI, 0 },
2991   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
2992     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
2993   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
2994     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2995   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
2996     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2997   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
2998     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2999   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3000     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3001   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3002     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3003   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3004     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3005   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3006     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3007   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3008     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3009   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3010     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3011   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3012     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3013   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3014     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3015   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3016     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3017   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3018     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3019   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3020     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3021   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3022     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3023   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3024     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3025   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3026     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3027   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3028     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3029   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3030     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3031   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3032     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3033   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3034     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3035   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3036     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3037   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3038     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3039   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3040     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3041   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3042     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3043   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3044     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3045   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3046     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3047   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3048     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3049   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3050     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3051   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3052     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3053   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3054     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3055   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3056     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3057   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3058     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3059   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3060     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3061
3062   /* Ternary AltiVec/VSX builtins.  */
3063   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3064     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3065   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3066     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3067   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3068     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3069   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3070     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3071   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3072     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3073   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3074     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3075   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3076     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3077   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3078     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3079   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3080     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3081   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3082     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3083   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3084     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3085   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3086     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3087   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3088     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3089   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3090     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3091   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3092     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3093   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3094     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3095   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3096     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3097   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3098     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3099   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3100     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3101   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3102     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3103   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3104     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3105   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3106     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3107   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3108     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3109   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3110     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3111   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3112     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3113   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3114     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3115   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3116     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3117   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3118     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3119   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3120     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3121   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3122     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3123   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3124     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3125   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3126     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3127   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3128     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3129   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3130     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3131   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3132     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3133   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3134     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3135   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3136     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3137   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3138     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3139   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3140     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3141   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3142     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3143   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3144     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3145   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3146     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3147   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3148     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3149   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3150     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3151   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3152     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3153   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3154     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3155   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3156     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3157   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3158     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3159   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3160     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3161   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3162     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3163   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3164     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3165   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3166     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3167   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3168     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3169   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3170     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3171   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3172     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3173   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3174     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3175   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3176     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3177   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3178     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3179   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3180     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3181   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3182     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3183   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3184     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3185   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3186     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3187   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3188     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3189   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3190     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3191   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3192     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3193   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3194     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3195   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3196     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3197   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3198     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3199   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3200     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3201   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3202     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3203   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3204     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3205   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3206     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3207   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3208     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3209   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3210     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3211   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3212     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3213   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3214     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3215   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3216     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3217   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3218     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3219   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3220     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3221   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3222     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3223   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3224     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3225   { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3226     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3227   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3228     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3229   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3230     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3231   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3232     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3233   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3234     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3235   { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3236     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3237   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3238     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3239   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3240     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3241   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3242     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3243   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3244     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3245   { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3246     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3247   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3248     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3249   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3250     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3251   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3252     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3253   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3254     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3255   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3256     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3257   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3258     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3259   { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3260     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3261   { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3262     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3263   { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3264     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3265   { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3266     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3267   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3268     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3269   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3270     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3271   { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3272     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3273   { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3274     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3275   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3276     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3277   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3278     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3279   { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3280     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3281   { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3282     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3283   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3284     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3285   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3286     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3287   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3288     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3289   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3290     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3291     RS6000_BTI_unsigned_V16QI },
3292   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3293     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3294   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3295     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3296   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3297     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3298   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3299     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3300   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3301     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3302   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3303     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3304   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3305     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3306   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3307     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3308   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3309     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3310   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3311     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3312   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3313     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3314   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3315     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3316   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3317     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3318   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3319     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3320   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3321     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3322   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3323     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3324   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3325     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3326   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3327     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3328   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3329     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3330   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3331     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3332   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3333     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3334   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3335     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3336   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3337     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3338   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3339     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3340     RS6000_BTI_bool_V2DI },
3341   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3342     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3343     RS6000_BTI_unsigned_V2DI },
3344   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3345     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3346   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3347     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3348   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3349     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3350   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3351     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3352   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3353     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3354   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3355     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3356   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3357     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3358   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3359     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3360   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3361     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3362   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3363     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3364   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3365     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3366   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3367     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3368   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3369     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3370   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3371     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3372   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3373     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3374   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3375     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3376   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3377     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3378   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3379     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3380   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3381     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3382   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3383     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3384   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3385     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3386   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3387     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3388   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3389     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3390   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3391     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3392   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3393     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE },
3394   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3395     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3396   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3397     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3398   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3399     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3400   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3401     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE },
3402   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3403     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE },
3404   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3405     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3406   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3407     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3408   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3409     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
3410   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3411     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3412   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3413     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3414   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3415     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3416   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3417     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3418     ~RS6000_BTI_unsigned_V2DI },
3419   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3420     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3421     ~RS6000_BTI_bool_V2DI },
3422   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3423     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3424   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3425     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3426   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3427     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3428   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3429     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3430   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3431     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3432   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3433     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3434   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3435     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3436   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3437     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3438   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3439     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3440   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3441     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3442   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3443     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3444   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3445     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3446   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3447     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3448   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3449     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3450   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3451     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3452   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3453     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3454   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3455     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3456   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3457     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3458   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3459     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3460   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3461     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3462   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3463     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3464   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3465     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3466   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3467     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3468   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3469     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3470   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3471     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3472   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3473     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3474   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3475     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3476   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3477     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3478   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3479     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3480   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3481     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3482   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3483     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3484   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3485     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3486   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3487     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3488   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3489     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3490   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3491     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3492   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3493     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3494   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3495     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3496   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3497     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3498   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3499     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3500   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3501     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3502   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3503     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3504   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3505     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3506   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3507     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3508   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3509     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3510   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3511     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3512   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3513     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3514   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3515     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3516   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3517     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3518   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3519     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3520   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3521     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3522   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3523     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3524   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3525     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3526   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3527     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3528   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3529     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3530   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3531     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3532   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3533     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3534   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3535     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3536   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3537     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3538   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3539     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3540   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3541     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3542   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3543     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3544   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3545     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3546   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3547     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3548   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3549     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3550   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3551     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3552   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3553     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3554   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3555     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3556   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3557     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3558   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3559     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3560   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3561     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3562   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3563     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3564   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3565     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3566   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3567     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3568   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3569     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3570   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3571     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3572   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3573     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3574   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3575     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3576   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3577     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3578   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3579     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3580   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3581     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3582   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3583     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3584   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3585     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3586   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3587     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3588   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3589     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3590   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3591     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3592   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3593     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3594   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3595     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3596     ~RS6000_BTI_unsigned_V2DI },
3597   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3598     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3599     ~RS6000_BTI_bool_V2DI },
3600   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3601     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3602   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3603     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3604   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3605     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3606   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3607     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3608   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3609     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3610   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3611     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3612   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3613     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3614   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3615     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3616   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3617     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3618   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3619     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3620   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3621     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3622   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3623     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3624   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3625     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3626   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3627     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3628   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3629     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3630   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3631     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3632   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3633     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3634   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3635     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3636   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3637     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3638   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3639     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3640   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3641     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3642   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3643     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3644   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3645     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3646   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3647     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3648   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3649     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3650   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3651     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3652   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3653     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3654   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3655     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3656   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3657     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3658   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3659     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3660   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3661     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3662   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3663     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3664   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3665     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3666   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3667     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3668   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3669     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3670   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3671     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3672   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3673     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3674   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3675     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3676   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3677     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3678   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3679     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3680   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3681     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3682   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3683     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3684   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3685     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3686   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3687     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3688   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3689     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3690   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3691     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3692   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3693     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3694   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3695     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3696   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3697     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3698   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3699     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3700   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3701     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3702   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3703     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3704   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3705     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3706   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3707     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3708   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3709     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3710   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3711     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3712   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3713     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3714   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3715     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3716   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3717     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3718   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3719     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3720   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3721     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3722   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3723     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3724   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3725     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3726   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3727     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3728   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3729     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3730   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3731     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3732   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3733     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3734   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3735     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3736   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3737     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3738   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3739     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3740   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3741     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3742   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3743     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3744   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3745     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3746   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3747     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3748   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3749     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3750   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3751     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3752     ~RS6000_BTI_long_long },
3753   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3754     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3755     ~RS6000_BTI_unsigned_V2DI },
3756   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3757     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3758     ~RS6000_BTI_unsigned_long_long },
3759   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3760     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3761   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3762     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3763   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3764     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3765   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3766     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3767   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3768     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3769     ~RS6000_BTI_unsigned_V4SI },
3770   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3771     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3772     ~RS6000_BTI_UINTSI },
3773   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3774     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3775   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3776     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3777   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3778     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3779     ~RS6000_BTI_unsigned_V8HI },
3780   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3781     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3782     ~RS6000_BTI_UINTHI },
3783   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3784     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3785   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3786     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3787   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3788     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3789     ~RS6000_BTI_unsigned_V16QI },
3790   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3791     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3792     ~RS6000_BTI_UINTQI },
3793   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3794     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3795   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3796     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3797     RS6000_BTI_NOT_OPAQUE },
3798   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3799     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3800   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3801     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3802     RS6000_BTI_NOT_OPAQUE },
3803   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3804     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3805   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3806     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3807     RS6000_BTI_NOT_OPAQUE },
3808   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3809     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3810   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3811     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3812     RS6000_BTI_NOT_OPAQUE },
3813   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3814     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3815   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3816     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3817   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3818     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3819   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3820     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3821   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3822     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3823     RS6000_BTI_NOT_OPAQUE },
3824   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3825     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3826   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3827     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3828   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3829     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3830     RS6000_BTI_NOT_OPAQUE },
3831   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3832     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3833   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3834     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3835     RS6000_BTI_NOT_OPAQUE },
3836   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3837     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3838   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3839     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3840     RS6000_BTI_NOT_OPAQUE },
3841
3842   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3843     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3844   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3845     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3846   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3847     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3848   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3849     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3850     ~RS6000_BTI_unsigned_V2DI, 0 },
3851   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3852     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3853   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3854     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3855   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3856     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3857   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3858     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3859   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3860     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3861   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3862     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3863   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3864     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3865   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3866     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3867     ~RS6000_BTI_unsigned_V4SI, 0 },
3868   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3869     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3870   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3871     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3872     ~RS6000_BTI_unsigned_long, 0 },
3873   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3874     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3875   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3876     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3877   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3878     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3879   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3880     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3881   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3882     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3883     ~RS6000_BTI_unsigned_V8HI, 0 },
3884   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3885     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3886   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3887     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3888   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3889     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3890   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3891     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3892   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3893     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3894     ~RS6000_BTI_unsigned_V16QI, 0 },
3895   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3896     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3897
3898   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3899     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3900   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3901     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3902   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3903     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3904   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3905     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3906     ~RS6000_BTI_unsigned_V2DI },
3907   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3908     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3909     ~RS6000_BTI_bool_V2DI },
3910   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3911     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3912   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3913     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3914   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3915     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3916   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3917     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3918   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3919     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3920     ~RS6000_BTI_unsigned_V4SI },
3921   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3922     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3923     ~RS6000_BTI_UINTSI },
3924   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3925     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3926     ~RS6000_BTI_bool_V4SI },
3927   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3928     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3929     ~RS6000_BTI_UINTSI },
3930   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3931     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
3932     ~RS6000_BTI_INTSI },
3933   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3934     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3935   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3936     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3937   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3938     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3939     ~RS6000_BTI_unsigned_V8HI },
3940   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3941     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3942     ~RS6000_BTI_UINTHI },
3943   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3944     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3945     ~RS6000_BTI_bool_V8HI },
3946   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3947     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3948     ~RS6000_BTI_UINTHI },
3949   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
3950     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
3951     ~RS6000_BTI_INTHI },
3952   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3953     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3954   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3955     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3956   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3957     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3958     ~RS6000_BTI_unsigned_V16QI },
3959   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3960     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3961     ~RS6000_BTI_UINTQI },
3962   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3963     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3964     ~RS6000_BTI_bool_V16QI },
3965   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3966     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3967     ~RS6000_BTI_UINTQI },
3968   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3969     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
3970     ~RS6000_BTI_INTQI },
3971   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
3972     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
3973     ~RS6000_BTI_pixel_V8HI },
3974
3975   /* Predicates.  */
3976   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3977     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3978   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3979     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3980   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
3981     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3982   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3983     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
3984   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3985     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3986   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
3987     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
3988   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3989     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3990   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3991     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3992   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
3993     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3994   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3995     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3996   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3997     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
3998   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
3999     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4000   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4001     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4002   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4003     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4004   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4005     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4006   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4007     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4008   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4009     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4010   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4011     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4012   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4013     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4014   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4015     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4016   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4017     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4018   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4019     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4020   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4021     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4022   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4023     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4024   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4025     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4026   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4027     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4028
4029
4030   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4031     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4032   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4033     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4034   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4035     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4036   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4037     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4038   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4039     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4040   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4041     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4042   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4043     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4044   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4045     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4046   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4047     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4048   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4049     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4050   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4051     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4052   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4053     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4054   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4055     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4056   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4057     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4058   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4059     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4060   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4061     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4062   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4063     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4064   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4065     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4066   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4067     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4068   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4069     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4070   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4071     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4072   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4073     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4074   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4075     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4076   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4077     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4078   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4079     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4080   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4081     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4082   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4083     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4084   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4085     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4086   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4087     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4088   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4089     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4090   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4091     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4092
4093
4094   /* cmpge is the same as cmpgt for all cases except floating point.
4095      There is further code to deal with this special case in
4096      altivec_build_resolved_builtin.  */
4097   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4098     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4099   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4100     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4101   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4102     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4103   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4104     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4105   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4106     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4107   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4108     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4109   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4110     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4111   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4112     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4113   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4114     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4115   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4116     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4117   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4118     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4119   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4120     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4121   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4122     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4123   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4124     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4125   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4126     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4127   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4128     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4129   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4130     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4131   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4132     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4133   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4134     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4135   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4136     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4137   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4138     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4139   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4140     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4141   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4142     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4143   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4144     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4145   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4146     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4147   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4148     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4149
4150   /* Power8 vector overloaded functions.  */
4151   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4152     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4153   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4154     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4155   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4156     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4157   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4158     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4159   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4160     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4161     RS6000_BTI_unsigned_V16QI, 0 },
4162   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4163     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4164     RS6000_BTI_bool_V16QI, 0 },
4165   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4166     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4167     RS6000_BTI_unsigned_V16QI, 0 },
4168   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4169     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4170   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4171     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4172   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4173     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4174   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4175     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4176   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4177     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4178     RS6000_BTI_unsigned_V8HI, 0 },
4179   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4180     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4181     RS6000_BTI_bool_V8HI, 0 },
4182   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4183     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4184     RS6000_BTI_unsigned_V8HI, 0 },
4185   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4186     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4187   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4188     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4189   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4190     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4191   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4192     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4193   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4194     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4195     RS6000_BTI_unsigned_V4SI, 0 },
4196   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4197     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4198     RS6000_BTI_bool_V4SI, 0 },
4199   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4200     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4201     RS6000_BTI_unsigned_V4SI, 0 },
4202   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4203     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4204   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4205     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4206   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4207     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4208   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4209     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4210   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4211     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4212     RS6000_BTI_unsigned_V2DI, 0 },
4213   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4214     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4215     RS6000_BTI_bool_V2DI, 0 },
4216   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4217     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4218     RS6000_BTI_unsigned_V2DI, 0 },
4219   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4220     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4221   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4222     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4223
4224   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4225     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4226   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4227     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4228   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4229     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4230   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4231     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4232     RS6000_BTI_unsigned_V16QI, 0 },
4233   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4234     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4235     RS6000_BTI_bool_V16QI, 0 },
4236   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4237     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4238     RS6000_BTI_unsigned_V16QI, 0 },
4239   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4240     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4241   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4242     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4243   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4244     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4245   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4246     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4247   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4248     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4249     RS6000_BTI_unsigned_V8HI, 0 },
4250   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4251     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4252     RS6000_BTI_bool_V8HI, 0 },
4253   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4254     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4255     RS6000_BTI_unsigned_V8HI, 0 },
4256   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4257     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4258   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4259     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4260   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4261     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4262   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4263     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4264   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4265     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4266     RS6000_BTI_unsigned_V4SI, 0 },
4267   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4268     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4269     RS6000_BTI_bool_V4SI, 0 },
4270   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4271     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4272     RS6000_BTI_unsigned_V4SI, 0 },
4273   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4274     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4275   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4276     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4277   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4278     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4279   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4280     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4281   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4282     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4283     RS6000_BTI_unsigned_V2DI, 0 },
4284   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4285     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4286     RS6000_BTI_bool_V2DI, 0 },
4287   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4288     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4289     RS6000_BTI_unsigned_V2DI, 0 },
4290   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4291     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4292   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4293     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4294   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4295     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4296
4297   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4298     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4299   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4300     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4301   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4302     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4303   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4304     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4305     RS6000_BTI_unsigned_V16QI, 0 },
4306   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4307     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4308     RS6000_BTI_bool_V16QI, 0 },
4309   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4310     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4311     RS6000_BTI_unsigned_V16QI, 0 },
4312   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4313     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4314   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4315     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4316   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4317     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4318   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4319     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4320   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4321     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4322     RS6000_BTI_unsigned_V8HI, 0 },
4323   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4324     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4325     RS6000_BTI_bool_V8HI, 0 },
4326   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4327     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4328     RS6000_BTI_unsigned_V8HI, 0 },
4329   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4330     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4331   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4332     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4333   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4334     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4335   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4336     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4337   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4338     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4339     RS6000_BTI_unsigned_V4SI, 0 },
4340   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4341     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4342     RS6000_BTI_bool_V4SI, 0 },
4343   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4344     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4345     RS6000_BTI_unsigned_V4SI, 0 },
4346   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4347     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4348   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4349     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4350   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4351     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4352   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4353     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4354   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4355     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4356     RS6000_BTI_unsigned_V2DI, 0 },
4357   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4358     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4359     RS6000_BTI_bool_V2DI, 0 },
4360   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4361     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4362     RS6000_BTI_unsigned_V2DI, 0 },
4363   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4364     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4365   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4366     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4367   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4368     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4369
4370   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4371     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4372   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4373     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4374     RS6000_BTI_unsigned_V1TI, 0 },
4375
4376   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4377     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4378   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4379     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4380   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4381     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4382   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4383     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4384   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4385     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4386   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4387     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4388
4389   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4390     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4391   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4392     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4393     RS6000_BTI_unsigned_V1TI, 0 },
4394
4395   { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4396     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4397     RS6000_BTI_unsigned_V16QI, 0 },
4398   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4399     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4400     RS6000_BTI_unsigned_V16QI, 0 },
4401   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4402     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4403     RS6000_BTI_unsigned_V16QI, 0 },
4404
4405   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4406     RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4407   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4408     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4409     RS6000_BTI_unsigned_V16QI, 0 },
4410   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4411     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4412     RS6000_BTI_unsigned_V16QI, 0 },
4413
4414   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4415     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4416   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4417     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4418   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4419     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4420   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4421     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4422   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4423     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4424   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4425     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4426   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4427     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4428   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4429     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4430
4431   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4432     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4433   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4434     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4435
4436   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4437     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4438   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4439     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4440
4441   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4442     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4443   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4444     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4445
4446   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4447     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4448   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4449     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4450
4451   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4452     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4453   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4454     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4455
4456   { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4457     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4458   { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4459     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4460
4461   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4462     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4463   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4464     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4465
4466   { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4467     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4468   { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4469     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4470
4471   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4472     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4473   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4474     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4475
4476   { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4477     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4478   { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4479     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4480
4481   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4482     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4483   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4484     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4485
4486   { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4487     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4488   { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4489     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4490
4491   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4492     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4493   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4494     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4495   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4496     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4497   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4498     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4499   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4500     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4501   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4502     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4503   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4504     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4505   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4506     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4507
4508   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4509     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4510   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4511     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4512
4513   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4514     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4515   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4516     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4517
4518   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4519     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4520   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4521     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4522
4523   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4524     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4525   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4526     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4527
4528   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4529     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4530     RS6000_BTI_unsigned_V16QI, 0 },
4531   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4532     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4533     RS6000_BTI_unsigned_V8HI, 0 },
4534   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4535     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4536     RS6000_BTI_unsigned_V4SI, 0 },
4537
4538   { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4539     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4540     RS6000_BTI_unsigned_V16QI, 0 },
4541
4542   { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4543     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4544     RS6000_BTI_unsigned_V8HI, 0 },
4545
4546   { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4547     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4548     RS6000_BTI_unsigned_V4SI, 0 },
4549
4550   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4551     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4552   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4553     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4554
4555   { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4556     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4557   { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4558     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4559
4560   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4561     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4562   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4563     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4564
4565   { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4566     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4567   { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4568     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4569
4570   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4571     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4572   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4573     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4574
4575   { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4576     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4577   { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4578     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4579
4580   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4581     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4582   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4583     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4584
4585   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4586     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4587   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4588     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4589
4590   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4591     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4592   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4593     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4594
4595   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4596     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4597   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4598     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4599
4600   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4601     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4602   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4603     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4604
4605   { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4606     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4607   { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4608     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4609
4610   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4611     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4612   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4613     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4614
4615   { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4616     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4617   { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4618     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4619
4620   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4621     RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4622
4623   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4624     RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4625
4626   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4627     RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4628   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4629     RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4630
4631   { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
4632     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4633   { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
4634     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4635   { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
4636     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4637   { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
4638     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4639
4640   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4641     RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4642     RS6000_BTI_unsigned_long_long, 0 },
4643   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4644     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4645     RS6000_BTI_unsigned_long_long, 0 },
4646
4647   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4648     RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4649     RS6000_BTI_unsigned_long_long, 0 },
4650   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4651     RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4652     RS6000_BTI_unsigned_long_long, 0 },
4653
4654   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4655     RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4656     RS6000_BTI_unsigned_long_long, 0 },
4657   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4658     RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4659     RS6000_BTI_unsigned_long_long, 0 },
4660
4661   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4662     RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4663     RS6000_BTI_unsigned_long_long, 0 },
4664   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4665     RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4666     RS6000_BTI_unsigned_long_long, 0 },
4667
4668   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4669     RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4670     RS6000_BTI_unsigned_long_long, 0 },
4671   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4672     RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4673     RS6000_BTI_unsigned_long_long, 0 },
4674
4675   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4676     RS6000_BTI_V2DF, ~RS6000_BTI_double,
4677     RS6000_BTI_unsigned_long_long, 0 },
4678   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4679     RS6000_BTI_V4SF, ~RS6000_BTI_float,
4680     RS6000_BTI_unsigned_long_long, 0 },
4681   /* At an appropriate future time, add support for the
4682      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4683
4684   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4685     RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4686     RS6000_BTI_unsigned_long_long },
4687   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4688     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4689     RS6000_BTI_unsigned_long_long },
4690
4691   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4692     RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4693     RS6000_BTI_unsigned_long_long },
4694   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4695     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4696     RS6000_BTI_unsigned_long_long },
4697
4698   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4699     RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4700     RS6000_BTI_unsigned_long_long },
4701   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4702     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4703     RS6000_BTI_unsigned_long_long },
4704
4705   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4706     RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4707     RS6000_BTI_unsigned_long_long },
4708   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4709     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4710     RS6000_BTI_unsigned_long_long },
4711
4712   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4713     RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4714     RS6000_BTI_unsigned_long_long },
4715   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4716     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4717     RS6000_BTI_unsigned_long_long },
4718
4719   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4720     RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4721     RS6000_BTI_unsigned_long_long },
4722   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4723     RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4724     RS6000_BTI_unsigned_long_long },
4725   /* At an appropriate future time, add support for the
4726      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4727
4728   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4729     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4730     RS6000_BTI_bool_V16QI, 0 },
4731   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4732     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4733     RS6000_BTI_V16QI, 0 },
4734   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4735     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4736     RS6000_BTI_unsigned_V16QI, 0 },
4737
4738   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4739     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4740     RS6000_BTI_bool_V8HI, 0 },
4741   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4742     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4743     RS6000_BTI_V8HI, 0 },
4744   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4745     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4746     RS6000_BTI_unsigned_V8HI, 0 },
4747
4748   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4749     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4750     RS6000_BTI_bool_V4SI, 0 },
4751   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4752     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4753     RS6000_BTI_V4SI, 0 },
4754   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4755     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4756     RS6000_BTI_unsigned_V4SI, 0 },
4757
4758   /* The following 2 entries have been deprecated.  */
4759   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4760     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4761     RS6000_BTI_unsigned_V16QI, 0 },
4762   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4763     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4764     RS6000_BTI_bool_V16QI, 0 },
4765   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4766     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4767     RS6000_BTI_unsigned_V16QI, 0 },
4768
4769   /* The following 2 entries have been deprecated.  */
4770   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4771     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4772     RS6000_BTI_V16QI, 0 },
4773   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4774     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4775     RS6000_BTI_bool_V16QI, 0 },
4776   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4777     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4778   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4779     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4780     RS6000_BTI_bool_V16QI, 0 },
4781
4782   /* The following 2 entries have been deprecated.  */
4783   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4784     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4785     RS6000_BTI_unsigned_V8HI, 0 },
4786   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4787     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4788     RS6000_BTI_bool_V8HI, 0 },
4789   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4790     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4791     RS6000_BTI_unsigned_V8HI, 0 },
4792   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4793     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4794
4795   /* The following 2 entries have been deprecated.  */
4796   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4797     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4798     RS6000_BTI_V8HI, 0 },
4799   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4800     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4801     RS6000_BTI_bool_V8HI, 0 },
4802   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4803     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4804     RS6000_BTI_bool_V8HI, 0 },
4805   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4806     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4807     RS6000_BTI_pixel_V8HI, 0 },
4808
4809   /* The following 2 entries have been deprecated.  */
4810   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4811     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4812     RS6000_BTI_unsigned_V4SI, 0 },
4813   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4814     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4815     RS6000_BTI_bool_V4SI, 0 },
4816   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4817     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4818     RS6000_BTI_unsigned_V4SI, 0 },
4819
4820   /* The following 2 entries have been deprecated.  */
4821   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4822     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4823     RS6000_BTI_V4SI, 0 },
4824   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4825     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4826     RS6000_BTI_bool_V4SI, 0 },
4827   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4828     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4829   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4830     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4831     RS6000_BTI_bool_V4SI, 0 },
4832
4833   /* The following 2 entries have been deprecated.  */
4834   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4835     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4836     RS6000_BTI_unsigned_V2DI, 0 },
4837   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4838     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4839     RS6000_BTI_bool_V2DI, 0 },
4840   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4841     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4842     RS6000_BTI_unsigned_V2DI, 0
4843   },
4844
4845   /* The following 2 entries have been deprecated.  */
4846   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4847     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4848     RS6000_BTI_V2DI, 0 },
4849   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4850     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4851     RS6000_BTI_bool_V2DI, 0 },
4852   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4853     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4854   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4855     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4856     RS6000_BTI_bool_V2DI, 0 },
4857
4858   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
4859     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4860   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
4861     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4862
4863   /* The following 2 entries have been deprecated.  */
4864   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4865     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4866     RS6000_BTI_unsigned_V16QI, 0 },
4867   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4868     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4869     RS6000_BTI_bool_V16QI, 0 },
4870   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4871     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4872     RS6000_BTI_unsigned_V16QI, 0 },
4873
4874   /* The following 2 entries have been deprecated.  */
4875   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4876     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4877     RS6000_BTI_V16QI, 0 },
4878   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4879     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4880     RS6000_BTI_bool_V16QI, 0 },
4881   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4882     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4883   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4884     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4885     RS6000_BTI_bool_V16QI, 0 },
4886
4887   /* The following 2 entries have been deprecated.  */
4888   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4889     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4890     RS6000_BTI_unsigned_V8HI, 0 },
4891   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4892     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4893     RS6000_BTI_bool_V8HI, 0 },
4894   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4895     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4896     RS6000_BTI_unsigned_V8HI, 0 },
4897   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4898     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4899
4900   /* The following 2 entries have been deprecated.  */
4901   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4902     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4903     RS6000_BTI_V8HI, 0 },
4904   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4905     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4906     RS6000_BTI_bool_V8HI, 0 },
4907   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4908     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4909     RS6000_BTI_bool_V8HI, 0 },
4910   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4911     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4912     RS6000_BTI_pixel_V8HI, 0 },
4913
4914   /* The following 2 entries have been deprecated.  */
4915   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4916     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4917     RS6000_BTI_unsigned_V4SI, 0 },
4918   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4919     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4920     RS6000_BTI_bool_V4SI, 0 },
4921   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4922     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4923     RS6000_BTI_unsigned_V4SI, 0 },
4924
4925   /* The following 2 entries have been deprecated.  */
4926   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4927     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4928     RS6000_BTI_V4SI, 0 },
4929   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4930     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4931     RS6000_BTI_bool_V4SI, 0 },
4932   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4933     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4934   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
4935     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4936     RS6000_BTI_bool_V4SI, 0 },
4937
4938   /* The following 2 entries have been deprecated.  */
4939   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4940     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4941     RS6000_BTI_unsigned_V2DI, 0 },
4942   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4943     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4944     RS6000_BTI_bool_V2DI, 0 },
4945   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4946     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4947     RS6000_BTI_unsigned_V2DI, 0
4948   },
4949
4950   /* The following 2 entries have been deprecated.  */
4951   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4952     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4953     RS6000_BTI_V2DI, 0 },
4954   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4955     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4956     RS6000_BTI_bool_V2DI, 0 },
4957   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4958     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4959   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
4960     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4961     RS6000_BTI_bool_V2DI, 0 },
4962
4963   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
4964     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4965   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
4966     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4967
4968   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4969     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4970     RS6000_BTI_unsigned_V16QI },
4971   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
4972     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4973
4974   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4975     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4976     RS6000_BTI_unsigned_V8HI },
4977   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
4978     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4979
4980   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4981     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4982     RS6000_BTI_unsigned_V4SI },
4983   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
4984     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4985
4986   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
4987     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4988     RS6000_BTI_V16QI, 0 },
4989   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
4990     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4991     RS6000_BTI_unsigned_V16QI, 0 },
4992
4993   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
4994     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4995     RS6000_BTI_V8HI, 0 },
4996   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
4997     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4998     RS6000_BTI_unsigned_V8HI, 0 },
4999
5000   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5001     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5002     RS6000_BTI_V4SI, 0 },
5003   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5004     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5005     RS6000_BTI_unsigned_V4SI, 0 },
5006
5007   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5008     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5009   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5010     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5011
5012   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5013     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5014   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5015     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5016
5017   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5018     RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5019   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5020     RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 },
5021
5022   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5023     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5024     RS6000_BTI_V16QI, 0 },
5025   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5026     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5027     RS6000_BTI_unsigned_V16QI, 0 },
5028
5029   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5030     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5031     RS6000_BTI_V8HI, 0 },
5032   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5033     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5034     RS6000_BTI_unsigned_V8HI, 0 },
5035
5036   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5037     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5038     RS6000_BTI_V4SI, 0 },
5039   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5040     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5041     RS6000_BTI_unsigned_V4SI, 0 },
5042   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5043     RS6000_BTI_float, RS6000_BTI_UINTSI,
5044     RS6000_BTI_V4SF, 0 },
5045
5046   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5047     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5048     RS6000_BTI_V16QI, 0 },
5049   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5050     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5051     RS6000_BTI_unsigned_V16QI, 0 },
5052
5053   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5054     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5055     RS6000_BTI_V8HI, 0 },
5056   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5057     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5058     RS6000_BTI_unsigned_V8HI, 0 },
5059
5060   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5061     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5062     RS6000_BTI_V4SI, 0 },
5063   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5064     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5065     RS6000_BTI_unsigned_V4SI, 0 },
5066   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5067     RS6000_BTI_float, RS6000_BTI_UINTSI,
5068     RS6000_BTI_V4SF, 0 },
5069
5070   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5071     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5072   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5073     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5074
5075   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5076     RS6000_BTI_V16QI, RS6000_BTI_V4SI,
5077     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5078   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5079     RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
5080     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5081   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5082     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5083     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5084   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5085     RS6000_BTI_V16QI, RS6000_BTI_INTDI,
5086     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5087   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5088     RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
5089     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5090   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5091     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
5092     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5093   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5094     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
5095     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5096
5097   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5098     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5099   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5100     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5101     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5102
5103   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5104     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5105   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5106     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5107     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5108
5109   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5110     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5111   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5112     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5113     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5114
5115   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5116     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5117   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5118     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5119     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5120
5121   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5122     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5123   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5124     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5125   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5126     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5127
5128   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5129     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5130   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5131     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5132   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5133     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5134
5135   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5136     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5137     RS6000_BTI_unsigned_V2DI, 0 },
5138   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5139     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5140     RS6000_BTI_bool_V2DI, 0 },
5141   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5142     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5143     RS6000_BTI_unsigned_V2DI, 0 },
5144
5145   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5146     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5147     RS6000_BTI_unsigned_V2DI, 0 },
5148   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5149     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5150     RS6000_BTI_bool_V2DI, 0 },
5151   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5152     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5153     RS6000_BTI_unsigned_V2DI, 0 },
5154
5155   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5156     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5157   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5158     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5159     RS6000_BTI_unsigned_V4SI, 0 },
5160   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5161     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5162
5163   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5164     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5165   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5166     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5167     RS6000_BTI_unsigned_V4SI, 0 },
5168   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5169     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5170
5171   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5172     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5173     RS6000_BTI_unsigned_V16QI, 0 },
5174   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5175     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5176     RS6000_BTI_unsigned_V8HI, 0 },
5177   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5178     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5179     RS6000_BTI_unsigned_V4SI, 0 },
5180   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5181     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5182     RS6000_BTI_unsigned_V2DI, 0 },
5183
5184   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5185     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5186   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5187     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5188   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5189     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5190   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5191     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5192   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5193     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5194   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5195     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5196   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5197     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5198   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5199     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5200
5201   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5202     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5203   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5204     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5205
5206   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5207     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5208   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5209     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5210
5211   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5212     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5213   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5214     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5215
5216   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5217     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5218   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5219     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5220
5221   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5222     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5223   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5224     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5225   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5226     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5227   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5228     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5229   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5230     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5231   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5232     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5233   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5234     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5235   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5236     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5237
5238   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5239     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5240   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5241     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5242
5243   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5244     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5245   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5246     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5247
5248   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5249     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5250   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5251     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5252   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5253     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5254   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5255     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5256
5257   { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5258     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5259   { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5260     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5261   { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5262     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5263
5264   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5265     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5266   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5267     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5268   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5269     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5270
5271   { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5272     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5273
5274   { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5275     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5276
5277   { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5278     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5279
5280   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5281     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5282   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5283     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5284
5285   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5286     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5287   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5288     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5289
5290   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5291     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5292   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5293     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5294
5295   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5296     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5297   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5298     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5299
5300   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5301     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5302   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5303     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5304     RS6000_BTI_unsigned_V1TI, 0 },
5305
5306   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5307     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5308   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5309     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5310   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5311     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5312   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5313     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5314   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5315     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5316   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5317     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5318
5319   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5320     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5321   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5322     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5323     RS6000_BTI_unsigned_V1TI, 0 },
5324
5325   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5326     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5327   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5328     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5329
5330   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5331     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5332   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5333     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5334
5335   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5336     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5337     RS6000_BTI_unsigned_V16QI, 0 },
5338   { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5339     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5340     RS6000_BTI_unsigned_V16QI, 0 },
5341
5342   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5343     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5344   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5345     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5346   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5347     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5348   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5349     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5350   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5351     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5352   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5353     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5354   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
5355     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5356   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5357     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5358   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5359     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5360   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
5361     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5362   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5363     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5364   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5365     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5366
5367   /* Crypto builtins.  */
5368   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5369     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5370     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5371   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5372     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5373     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5374   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5375     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5376     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5377   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5378     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5379     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5380
5381   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5382     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5383     RS6000_BTI_unsigned_V16QI, 0 },
5384   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5385     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5386     RS6000_BTI_unsigned_V8HI, 0 },
5387   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5388     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5389     RS6000_BTI_unsigned_V4SI, 0 },
5390   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5391     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5392     RS6000_BTI_unsigned_V2DI, 0 },
5393
5394   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5395     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5396     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5397   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5398     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5399     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5400
5401   { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
5402 };
5403 \f
5404
5405 /* Convert a type stored into a struct altivec_builtin_types as ID,
5406    into a tree.  The types are in rs6000_builtin_types: negative values
5407    create a pointer type for the type associated to ~ID.  Note it is
5408    a logical NOT, rather than a negation, otherwise you cannot represent
5409    a pointer type for ID 0.  */
5410
5411 static inline tree
5412 rs6000_builtin_type (int id)
5413 {
5414   tree t;
5415   t = rs6000_builtin_types[id < 0 ? ~id : id];
5416   return id < 0 ? build_pointer_type (t) : t;
5417 }
5418
5419 /* Check whether the type of an argument, T, is compatible with a
5420    type ID stored into a struct altivec_builtin_types.  Integer
5421    types are considered compatible; otherwise, the language hook
5422    lang_hooks.types_compatible_p makes the decision.  */
5423
5424 static inline bool
5425 rs6000_builtin_type_compatible (tree t, int id)
5426 {
5427   tree builtin_type;
5428   builtin_type = rs6000_builtin_type (id);
5429   if (t == error_mark_node)
5430     return false;
5431   if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
5432     return true;
5433   else
5434     return lang_hooks.types_compatible_p (t, builtin_type);
5435 }
5436
5437
5438 /* In addition to calling fold_convert for EXPR of type TYPE, also
5439    call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
5440    hiding there (PR47197).  */
5441
5442 static tree
5443 fully_fold_convert (tree type, tree expr)
5444 {
5445   tree result = fold_convert (type, expr);
5446   bool maybe_const = true;
5447
5448   if (!c_dialect_cxx ())
5449     result = c_fully_fold (result, false, &maybe_const);
5450
5451   return result;
5452 }
5453
5454 /* Build a tree for a function call to an Altivec non-overloaded builtin.
5455    The overloaded builtin that matched the types and args is described
5456    by DESC.  The N arguments are given in ARGS, respectively.
5457
5458    Actually the only thing it does is calling fold_convert on ARGS, with
5459    a small exception for vec_{all,any}_{ge,le} predicates. */
5460
5461 static tree
5462 altivec_build_resolved_builtin (tree *args, int n,
5463                                 const struct altivec_builtin_types *desc)
5464 {
5465   tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
5466   tree ret_type = rs6000_builtin_type (desc->ret_type);
5467   tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
5468   tree arg_type[3];
5469   tree call;
5470
5471   int i;
5472   for (i = 0; i < n; i++)
5473     arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
5474
5475   /* The AltiVec overloading implementation is overall gross, but this
5476      is particularly disgusting.  The vec_{all,any}_{ge,le} builtins
5477      are completely different for floating-point vs. integer vector
5478      types, because the former has vcmpgefp, but the latter should use
5479      vcmpgtXX.
5480
5481      In practice, the second and third arguments are swapped, and the
5482      condition (LT vs. EQ, which is recognizable by bit 1 of the first
5483      argument) is reversed.  Patch the arguments here before building
5484      the resolved CALL_EXPR.  */
5485   if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
5486       && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
5487       && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
5488     {
5489       tree t;
5490       t = args[2], args[2] = args[1], args[1] = t;
5491       t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
5492
5493       args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
5494                              build_int_cst (NULL_TREE, 2));
5495     }
5496
5497   switch (n)
5498     {
5499     case 0:
5500       call = build_call_expr (impl_fndecl, 0);
5501       break;
5502     case 1:
5503       call = build_call_expr (impl_fndecl, 1,
5504                               fully_fold_convert (arg_type[0], args[0]));
5505       break;
5506     case 2:
5507       call = build_call_expr (impl_fndecl, 2,
5508                               fully_fold_convert (arg_type[0], args[0]),
5509                               fully_fold_convert (arg_type[1], args[1]));
5510       break;
5511     case 3:
5512       call = build_call_expr (impl_fndecl, 3,
5513                               fully_fold_convert (arg_type[0], args[0]),
5514                               fully_fold_convert (arg_type[1], args[1]),
5515                               fully_fold_convert (arg_type[2], args[2]));
5516       break;
5517     default:
5518       gcc_unreachable ();
5519     }
5520   return fold_convert (ret_type, call);
5521 }
5522
5523 /* Implementation of the resolve_overloaded_builtin target hook, to
5524    support Altivec's overloaded builtins.  */
5525
5526 tree
5527 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
5528                                     void *passed_arglist)
5529 {
5530   vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
5531   unsigned int nargs = vec_safe_length (arglist);
5532   enum rs6000_builtins fcode
5533     = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
5534   tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
5535   tree types[3], args[3];
5536   const struct altivec_builtin_types *desc;
5537   unsigned int n;
5538
5539   if (!rs6000_overloaded_builtin_p (fcode))
5540     return NULL_TREE;
5541
5542   if (TARGET_DEBUG_BUILTIN)
5543     fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
5544              (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
5545
5546   /* vec_lvsl and vec_lvsr are deprecated for use with LE element order.  */
5547   if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
5548     warning (OPT_Wdeprecated,
5549              "vec_lvsl is deprecated for little endian; use "
5550              "assignment for unaligned loads and stores");
5551   else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
5552     warning (OPT_Wdeprecated,
5553              "vec_lvsr is deprecated for little endian; use "
5554              "assignment for unaligned loads and stores");
5555
5556   if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
5557     {
5558       /* vec_mul needs to be special cased because there are no instructions
5559          for it for the {un}signed char, {un}signed short, and {un}signed int
5560          types.  */
5561       if (nargs != 2)
5562         {
5563           error ("vec_mul only accepts 2 arguments");
5564           return error_mark_node;
5565         }
5566
5567       tree arg0 = (*arglist)[0];
5568       tree arg0_type = TREE_TYPE (arg0);
5569       tree arg1 = (*arglist)[1];
5570       tree arg1_type = TREE_TYPE (arg1);
5571
5572       /* Both arguments must be vectors and the types must match.  */
5573       if (arg0_type != arg1_type)
5574         goto bad;
5575       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5576         goto bad;
5577
5578       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5579         {
5580           case QImode:
5581           case HImode:
5582           case SImode:
5583           case DImode:
5584           case TImode:
5585             {
5586               /* For scalar types just use a multiply expression.  */
5587               return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0),
5588                                         arg0, arg1);
5589             }
5590           case SFmode:
5591             {
5592               /* For floats use the xvmulsp instruction directly.  */
5593               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
5594               return build_call_expr (call, 2, arg0, arg1);
5595             }
5596           case DFmode:
5597             {
5598               /* For doubles use the xvmuldp instruction directly.  */
5599               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
5600               return build_call_expr (call, 2, arg0, arg1);
5601             }
5602           /* Other types are errors.  */
5603           default:
5604             goto bad;
5605         }
5606     }
5607
5608   if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
5609     {
5610       /* vec_cmpne needs to be special cased because there are no instructions
5611          for it (prior to power 9).  */
5612       if (nargs != 2)
5613         {
5614           error ("vec_cmpne only accepts 2 arguments");
5615           return error_mark_node;
5616         }
5617
5618       tree arg0 = (*arglist)[0];
5619       tree arg0_type = TREE_TYPE (arg0);
5620       tree arg1 = (*arglist)[1];
5621       tree arg1_type = TREE_TYPE (arg1);
5622
5623       /* Power9 instructions provide the most efficient implementation of
5624          ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
5625          or SFmode or DFmode.  */
5626       if (!TARGET_P9_VECTOR
5627           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
5628           || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
5629           || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
5630           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
5631         {
5632           /* Both arguments must be vectors and the types must match.  */
5633           if (arg0_type != arg1_type)
5634             goto bad;
5635           if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5636             goto bad;
5637
5638
5639           switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5640             {
5641               /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
5642                  vec_cmpeq (va, vb)).  */
5643               /* Note:  vec_nand also works but opt changes vec_nand's
5644                  to vec_nor's anyway.  */
5645             case QImode:
5646             case HImode:
5647             case SImode:
5648             case DImode:
5649             case TImode:
5650             case SFmode:
5651             case DFmode:
5652               {
5653                 /* call = vec_cmpeq (va, vb)
5654                    result = vec_nor (call, call).  */
5655                 vec<tree, va_gc> *params = make_tree_vector ();
5656                 vec_safe_push (params, arg0);
5657                 vec_safe_push (params, arg1);
5658                 tree call = altivec_resolve_overloaded_builtin
5659                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
5660                    params);
5661                 /* Use save_expr to ensure that operands used more than once
5662                    that may have side effects (like calls) are only evaluated
5663                    once.  */
5664                 call = save_expr (call);
5665                 params = make_tree_vector ();
5666                 vec_safe_push (params, call);
5667                 vec_safe_push (params, call);
5668                 return altivec_resolve_overloaded_builtin
5669                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
5670               }
5671               /* Other types are errors.  */
5672             default:
5673               goto bad;
5674             }
5675         }
5676       /* else, fall through and process the Power9 alternative below */
5677     }
5678
5679   if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
5680     {
5681       /* vec_adde needs to be special cased because there is no instruction
5682           for the {un}signed int version.  */
5683       if (nargs != 3)
5684         {
5685           error ("vec_adde only accepts 3 arguments");
5686           return error_mark_node;
5687         }
5688
5689       tree arg0 = (*arglist)[0];
5690       tree arg0_type = TREE_TYPE (arg0);
5691       tree arg1 = (*arglist)[1];
5692       tree arg1_type = TREE_TYPE (arg1);
5693       tree arg2 = (*arglist)[2];
5694       tree arg2_type = TREE_TYPE (arg2);
5695
5696       /* All 3 arguments must be vectors of (signed or unsigned) (int or
5697           __int128) and the types must match.  */
5698       if ((arg0_type != arg1_type) || (arg1_type != arg2_type))
5699         goto bad;
5700       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5701         goto bad;
5702
5703       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5704         {
5705           /* For {un}signed ints,
5706              vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
5707                                                    vec_and (carryv, 0x1)).  */
5708           case SImode:
5709             {
5710               vec<tree, va_gc> *params = make_tree_vector ();
5711               vec_safe_push (params, arg0);
5712               vec_safe_push (params, arg1);
5713               tree add_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5714               tree call = altivec_resolve_overloaded_builtin (loc, add_builtin,
5715                                                               params);
5716               tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
5717               tree ones_vector = build_vector_from_val (arg0_type, const1);
5718               tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
5719                                                arg2, ones_vector);
5720               params = make_tree_vector ();
5721               vec_safe_push (params, call);
5722               vec_safe_push (params, and_expr);
5723               return altivec_resolve_overloaded_builtin (loc, add_builtin,
5724                                                          params);
5725             }
5726           /* For {un}signed __int128s use the vaddeuqm instruction
5727                 directly.  */
5728           case TImode:
5729             {
5730               tree adde_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
5731               return altivec_resolve_overloaded_builtin (loc, adde_bii,
5732                                                          arglist);
5733             }
5734
5735           /* Types other than {un}signed int and {un}signed __int128
5736                 are errors.  */
5737           default:
5738             goto bad;
5739         }
5740     }
5741
5742   if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
5743     {
5744       /* vec_addec needs to be special cased because there is no instruction
5745         for the {un}signed int version.  */
5746       if (nargs != 3)
5747         {
5748           error ("vec_addec only accepts 3 arguments");
5749           return error_mark_node;
5750         }
5751
5752       tree arg0 = (*arglist)[0];
5753       tree arg0_type = TREE_TYPE (arg0);
5754       tree arg1 = (*arglist)[1];
5755       tree arg1_type = TREE_TYPE (arg1);
5756       tree arg2 = (*arglist)[2];
5757       tree arg2_type = TREE_TYPE (arg2);
5758
5759       /* All 3 arguments must be vectors of (signed or unsigned) (int or
5760         __int128) and the types must match.  */
5761       if (arg0_type != arg1_type || arg1_type != arg2_type)
5762         goto bad;
5763       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5764         goto bad;
5765
5766       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5767         {
5768           /* For {un}signed ints,
5769               vec_addec (va, vb, carryv) ==
5770                                 vec_or (vec_addc (va, vb),
5771                                         vec_addc (vec_add (va, vb),
5772                                                   vec_and (carryv, 0x1))).  */
5773           case SImode:
5774             {
5775             /* Use save_expr to ensure that operands used more than once
5776                 that may have side effects (like calls) are only evaluated
5777                 once.  */
5778             arg0 = save_expr (arg0);
5779             arg1 = save_expr (arg1);
5780             vec<tree, va_gc> *params = make_tree_vector ();
5781             vec_safe_push (params, arg0);
5782             vec_safe_push (params, arg1);
5783             tree addc_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
5784             tree call1 = altivec_resolve_overloaded_builtin (loc, addc_builtin,
5785                                                              params);
5786             params = make_tree_vector ();
5787             vec_safe_push (params, arg0);
5788             vec_safe_push (params, arg1);
5789             tree add_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5790             tree call2 = altivec_resolve_overloaded_builtin (loc, add_builtin,
5791                                                              params);
5792             tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
5793             tree ones_vector = build_vector_from_val (arg0_type, const1);
5794             tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
5795                                              arg2, ones_vector);
5796             params = make_tree_vector ();
5797             vec_safe_push (params, call2);
5798             vec_safe_push (params, and_expr);
5799             call2 = altivec_resolve_overloaded_builtin (loc, addc_builtin,
5800                                                         params);
5801             params = make_tree_vector ();
5802             vec_safe_push (params, call1);
5803             vec_safe_push (params, call2);
5804             tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
5805             return altivec_resolve_overloaded_builtin (loc, or_builtin,
5806                                                        params);
5807             }
5808           /* For {un}signed __int128s use the vaddecuq instruction.  */
5809           case TImode:
5810             {
5811             tree VADDECUQ_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
5812             return altivec_resolve_overloaded_builtin (loc, VADDECUQ_bii,
5813                                                        arglist);
5814             }
5815           /* Types other than {un}signed int and {un}signed __int128
5816                 are errors.  */
5817           default:
5818             goto bad;
5819         }
5820     }
5821
5822   /* For now treat vec_splats and vec_promote as the same.  */
5823   if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
5824       || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
5825     {
5826       tree type, arg;
5827       int size;
5828       int i;
5829       bool unsigned_p;
5830       vec<constructor_elt, va_gc> *vec;
5831       const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
5832
5833       if (nargs == 0)
5834         {
5835           error ("%s only accepts %d arguments", name, (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)+1 );
5836           return error_mark_node;
5837         }
5838       if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
5839         {
5840           error ("%s only accepts 1 argument", name);
5841           return error_mark_node;
5842         }
5843       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
5844         {
5845           error ("%s only accepts 2 arguments", name);
5846           return error_mark_node;
5847         }
5848       /* Ignore promote's element argument.  */
5849       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
5850           && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
5851         goto bad;
5852
5853       arg = (*arglist)[0];
5854       type = TREE_TYPE (arg);
5855       if (!SCALAR_FLOAT_TYPE_P (type)
5856           && !INTEGRAL_TYPE_P (type))
5857         goto bad;
5858       unsigned_p = TYPE_UNSIGNED (type);
5859       switch (TYPE_MODE (type))
5860         {
5861           case TImode:
5862             type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
5863             size = 1;
5864             break;
5865           case DImode:
5866             type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
5867             size = 2;
5868             break;
5869           case SImode:
5870             type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
5871             size = 4;
5872             break;
5873           case HImode:
5874             type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
5875             size = 8;
5876             break;
5877           case QImode:
5878             type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
5879             size = 16;
5880             break;
5881           case SFmode: type = V4SF_type_node; size = 4; break;
5882           case DFmode: type = V2DF_type_node; size = 2; break;
5883           default:
5884             goto bad;
5885         }
5886       arg = save_expr (fold_convert (TREE_TYPE (type), arg));
5887       vec_alloc (vec, size);
5888       for(i = 0; i < size; i++)
5889         {
5890           constructor_elt elt = {NULL_TREE, arg};
5891           vec->quick_push (elt);
5892         }
5893         return build_constructor (type, vec);
5894     }
5895
5896   /* For now use pointer tricks to do the extraction, unless we are on VSX
5897      extracting a double from a constant offset.  */
5898   if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
5899     {
5900       tree arg1;
5901       tree arg1_type;
5902       tree arg2;
5903       tree arg1_inner_type;
5904       tree decl, stmt;
5905       tree innerptrtype;
5906       machine_mode mode;
5907
5908       /* No second argument. */
5909       if (nargs != 2)
5910         {
5911           error ("vec_extract only accepts 2 arguments");
5912           return error_mark_node;
5913         }
5914
5915       arg2 = (*arglist)[1];
5916       arg1 = (*arglist)[0];
5917       arg1_type = TREE_TYPE (arg1);
5918
5919       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
5920         goto bad;
5921       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
5922         goto bad;
5923
5924       /* If we are targeting little-endian, but -maltivec=be has been
5925          specified to override the element order, adjust the element
5926          number accordingly.  */
5927       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
5928         {
5929           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
5930           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
5931                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
5932                                   arg2);
5933         }
5934
5935       /* See if we can optimize vec_extracts with the current VSX instruction
5936          set.  */
5937       mode = TYPE_MODE (arg1_type);
5938       if (VECTOR_MEM_VSX_P (mode))
5939
5940         {
5941           tree call = NULL_TREE;
5942           int nunits = GET_MODE_NUNITS (mode);
5943
5944           /* If the second argument is an integer constant, if the value is in
5945              the expected range, generate the built-in code if we can.  We need
5946              64-bit and direct move to extract the small integer vectors.  */
5947           if (TREE_CODE (arg2) == INTEGER_CST && wi::ltu_p (arg2, nunits))
5948             {
5949               switch (mode)
5950                 {
5951                 default:
5952                   break;
5953
5954                 case V1TImode:
5955                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
5956                   break;
5957
5958                 case V2DFmode:
5959                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
5960                   break;
5961
5962                 case V2DImode:
5963                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
5964                   break;
5965
5966                 case V4SFmode:
5967                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
5968                   break;
5969
5970                 case V4SImode:
5971                   if (TARGET_DIRECT_MOVE_64BIT)
5972                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
5973                   break;
5974
5975                 case V8HImode:
5976                   if (TARGET_DIRECT_MOVE_64BIT)
5977                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
5978                   break;
5979
5980                 case V16QImode:
5981                   if (TARGET_DIRECT_MOVE_64BIT)
5982                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
5983                   break;
5984                 }
5985             }
5986
5987           /* If the second argument is variable, we can optimize it if we are
5988              generating 64-bit code on a machine with direct move.  */
5989           else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
5990             {
5991               switch (mode)
5992                 {
5993                 default:
5994                   break;
5995
5996                 case V2DFmode:
5997                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
5998                   break;
5999
6000                 case V2DImode:
6001                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6002                   break;
6003
6004                 case V4SFmode:
6005                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6006                   break;
6007
6008                 case V4SImode:
6009                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6010                   break;
6011
6012                 case V8HImode:
6013                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6014                   break;
6015
6016                 case V16QImode:
6017                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6018                   break;
6019                 }
6020             }
6021
6022           if (call)
6023             return build_call_expr (call, 2, arg1, arg2);
6024         }
6025
6026       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6027       arg1_inner_type = TREE_TYPE (arg1_type);
6028       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6029                               build_int_cst (TREE_TYPE (arg2),
6030                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6031                                              - 1), 0);
6032       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6033       DECL_EXTERNAL (decl) = 0;
6034       TREE_PUBLIC (decl) = 0;
6035       DECL_CONTEXT (decl) = current_function_decl;
6036       TREE_USED (decl) = 1;
6037       TREE_TYPE (decl) = arg1_type;
6038       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6039       if (c_dialect_cxx ())
6040         {
6041           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6042                          NULL_TREE, NULL_TREE);
6043           SET_EXPR_LOCATION (stmt, loc);
6044         }
6045       else
6046         {
6047           DECL_INITIAL (decl) = arg1;
6048           stmt = build1 (DECL_EXPR, arg1_type, decl);
6049           TREE_ADDRESSABLE (decl) = 1;
6050           SET_EXPR_LOCATION (stmt, loc);
6051           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6052         }
6053
6054       innerptrtype = build_pointer_type (arg1_inner_type);
6055
6056       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6057       stmt = convert (innerptrtype, stmt);
6058       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6059       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6060
6061       return stmt;
6062     }
6063
6064   /* For now use pointer tricks to do the insertion, unless we are on VSX
6065      inserting a double to a constant offset..  */
6066   if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6067     {
6068       tree arg0;
6069       tree arg1;
6070       tree arg2;
6071       tree arg1_type;
6072       tree arg1_inner_type;
6073       tree decl, stmt;
6074       tree innerptrtype;
6075       machine_mode mode;
6076
6077       /* No second or third arguments. */
6078       if (nargs != 3)
6079         {
6080           error ("vec_insert only accepts 3 arguments");
6081           return error_mark_node;
6082         }
6083
6084       arg0 = (*arglist)[0];
6085       arg1 = (*arglist)[1];
6086       arg1_type = TREE_TYPE (arg1);
6087       arg2 = (*arglist)[2];
6088
6089       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6090         goto bad;
6091       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6092         goto bad;
6093
6094       /* If we are targeting little-endian, but -maltivec=be has been
6095          specified to override the element order, adjust the element
6096          number accordingly.  */
6097       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6098         {
6099           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6100           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6101                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6102                                   arg2);
6103         }
6104
6105       /* If we can use the VSX xxpermdi instruction, use that for insert.  */
6106       mode = TYPE_MODE (arg1_type);
6107       if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6108           && TREE_CODE (arg2) == INTEGER_CST
6109           && wi::ltu_p (arg2, 2))
6110         {
6111           tree call = NULL_TREE;
6112
6113           if (mode == V2DFmode)
6114             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6115           else if (mode == V2DImode)
6116             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6117
6118           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6119              reversed.  */
6120           if (call)
6121             return build_call_expr (call, 3, arg1, arg0, arg2);
6122         }
6123       else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6124                && TREE_CODE (arg2) == INTEGER_CST
6125                && wi::eq_p (arg2, 0))
6126         {
6127           tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6128
6129           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6130              reversed.  */
6131           return build_call_expr (call, 3, arg1, arg0, arg2);
6132         }
6133
6134       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6135       arg1_inner_type = TREE_TYPE (arg1_type);
6136       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6137                               build_int_cst (TREE_TYPE (arg2),
6138                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6139                                              - 1), 0);
6140       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6141       DECL_EXTERNAL (decl) = 0;
6142       TREE_PUBLIC (decl) = 0;
6143       DECL_CONTEXT (decl) = current_function_decl;
6144       TREE_USED (decl) = 1;
6145       TREE_TYPE (decl) = arg1_type;
6146       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6147       if (c_dialect_cxx ())
6148         {
6149           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6150                          NULL_TREE, NULL_TREE);
6151           SET_EXPR_LOCATION (stmt, loc);
6152         }
6153       else
6154         {
6155           DECL_INITIAL (decl) = arg1;
6156           stmt = build1 (DECL_EXPR, arg1_type, decl);
6157           TREE_ADDRESSABLE (decl) = 1;
6158           SET_EXPR_LOCATION (stmt, loc);
6159           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6160         }
6161
6162       innerptrtype = build_pointer_type (arg1_inner_type);
6163
6164       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6165       stmt = convert (innerptrtype, stmt);
6166       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6167       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6168       stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6169                      convert (TREE_TYPE (stmt), arg0));
6170       stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6171       return stmt;
6172     }
6173
6174   /* Expand vec_ld into an expression that masks the address and
6175      performs the load.  We need to expand this early to allow
6176      the best aliasing, as by the time we get into RTL we no longer
6177      are able to honor __restrict__, for example.  We may want to
6178      consider this for all memory access built-ins.
6179
6180      When -maltivec=be is specified, or the wrong number of arguments
6181      is provided, simply punt to existing built-in processing.  */
6182   if (fcode == ALTIVEC_BUILTIN_VEC_LD
6183       && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6184       && nargs == 2)
6185     {
6186       tree arg0 = (*arglist)[0];
6187       tree arg1 = (*arglist)[1];
6188
6189       /* Strip qualifiers like "const" from the pointer arg.  */
6190       tree arg1_type = TREE_TYPE (arg1);
6191       tree inner_type = TREE_TYPE (arg1_type);
6192       if (TYPE_QUALS (TREE_TYPE (arg1_type)) != 0)
6193         {
6194           arg1_type = build_pointer_type (build_qualified_type (inner_type,
6195                                                                 0));
6196           arg1 = fold_convert (arg1_type, arg1);
6197         }
6198
6199       /* Construct the masked address.  Let existing error handling take
6200          over if we don't have a constant offset.  */
6201       arg0 = fold (arg0);
6202
6203       if (TREE_CODE (arg0) == INTEGER_CST)
6204         {
6205           if (!ptrofftype_p (TREE_TYPE (arg0)))
6206             arg0 = build1 (NOP_EXPR, sizetype, arg0);
6207
6208           tree arg1_type = TREE_TYPE (arg1);
6209           if (TREE_CODE (arg1_type) == ARRAY_TYPE)
6210             {
6211               arg1_type = TYPE_POINTER_TO (TREE_TYPE (arg1_type));
6212               tree const0 = build_int_cstu (sizetype, 0);
6213               tree arg1_elt0 = build_array_ref (loc, arg1, const0);
6214               arg1 = build1 (ADDR_EXPR, arg1_type, arg1_elt0);
6215             }
6216
6217           tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg1_type,
6218                                        arg1, arg0);
6219           tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg1_type, addr,
6220                                           build_int_cst (arg1_type, -16));
6221
6222           /* Find the built-in to get the return type so we can convert
6223              the result properly (or fall back to default handling if the
6224              arguments aren't compatible).  */
6225           for (desc = altivec_overloaded_builtins;
6226                desc->code && desc->code != fcode; desc++)
6227             continue;
6228
6229           for (; desc->code == fcode; desc++)
6230             if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6231                 && (rs6000_builtin_type_compatible (TREE_TYPE (arg1),
6232                                                     desc->op2)))
6233               {
6234                 tree ret_type = rs6000_builtin_type (desc->ret_type);
6235                 if (TYPE_MODE (ret_type) == V2DImode)
6236                   /* Type-based aliasing analysis thinks vector long
6237                      and vector long long are different and will put them
6238                      in distinct alias classes.  Force our return type
6239                      to be a may-alias type to avoid this.  */
6240                   ret_type
6241                     = build_pointer_type_for_mode (ret_type, Pmode,
6242                                                    true/*can_alias_all*/);
6243                 else
6244                   ret_type = build_pointer_type (ret_type);
6245                 aligned = build1 (NOP_EXPR, ret_type, aligned);
6246                 tree ret_val = build_indirect_ref (loc, aligned, RO_NULL);
6247                 return ret_val;
6248               }
6249         }
6250     }
6251
6252   /* Similarly for stvx.  */
6253   if (fcode == ALTIVEC_BUILTIN_VEC_ST
6254       && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6255       && nargs == 3)
6256     {
6257       tree arg0 = (*arglist)[0];
6258       tree arg1 = (*arglist)[1];
6259       tree arg2 = (*arglist)[2];
6260
6261       /* Construct the masked address.  Let existing error handling take
6262          over if we don't have a constant offset.  */
6263       arg1 = fold (arg1);
6264
6265       if (TREE_CODE (arg1) == INTEGER_CST)
6266         {
6267           if (!ptrofftype_p (TREE_TYPE (arg1)))
6268             arg1 = build1 (NOP_EXPR, sizetype, arg1);
6269
6270           tree arg2_type = TREE_TYPE (arg2);
6271           if (TREE_CODE (arg2_type) == ARRAY_TYPE)
6272             {
6273               arg2_type = TYPE_POINTER_TO (TREE_TYPE (arg2_type));
6274               tree const0 = build_int_cstu (sizetype, 0);
6275               tree arg2_elt0 = build_array_ref (loc, arg2, const0);
6276               arg2 = build1 (ADDR_EXPR, arg2_type, arg2_elt0);
6277             }
6278
6279           tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg2_type,
6280                                        arg2, arg1);
6281           tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg2_type, addr,
6282                                           build_int_cst (arg2_type, -16));
6283
6284           /* Find the built-in to make sure a compatible one exists; if not
6285              we fall back to default handling to get the error message.  */
6286           for (desc = altivec_overloaded_builtins;
6287                desc->code && desc->code != fcode; desc++)
6288             continue;
6289
6290           for (; desc->code == fcode; desc++)
6291             if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6292                 && rs6000_builtin_type_compatible (TREE_TYPE (arg1), desc->op2)
6293                 && rs6000_builtin_type_compatible (TREE_TYPE (arg2),
6294                                                    desc->op3))
6295               {
6296                 tree arg0_type = TREE_TYPE (arg0);
6297                 if (TYPE_MODE (arg0_type) == V2DImode)
6298                   /* Type-based aliasing analysis thinks vector long
6299                      and vector long long are different and will put them
6300                      in distinct alias classes.  Force our address type
6301                      to be a may-alias type to avoid this.  */
6302                   arg0_type
6303                     = build_pointer_type_for_mode (arg0_type, Pmode,
6304                                                    true/*can_alias_all*/);
6305                 else
6306                   arg0_type = build_pointer_type (arg0_type);
6307                 aligned = build1 (NOP_EXPR, arg0_type, aligned);
6308                 tree stg = build_indirect_ref (loc, aligned, RO_NULL);
6309                 tree retval = build2 (MODIFY_EXPR, TREE_TYPE (stg), stg,
6310                                       convert (TREE_TYPE (stg), arg0));
6311                 return retval;
6312               }
6313         }
6314     }
6315
6316   for (n = 0;
6317        !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6318        fnargs = TREE_CHAIN (fnargs), n++)
6319     {
6320       tree decl_type = TREE_VALUE (fnargs);
6321       tree arg = (*arglist)[n];
6322       tree type;
6323
6324       if (arg == error_mark_node)
6325         return error_mark_node;
6326
6327       if (n >= 3)
6328         abort ();
6329
6330       arg = default_conversion (arg);
6331
6332       /* The C++ front-end converts float * to const void * using
6333          NOP_EXPR<const void *> (NOP_EXPR<void *> (x)).  */
6334       type = TREE_TYPE (arg);
6335       if (POINTER_TYPE_P (type)
6336           && TREE_CODE (arg) == NOP_EXPR
6337           && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6338                                             const_ptr_type_node)
6339           && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6340                                             ptr_type_node))
6341         {
6342           arg = TREE_OPERAND (arg, 0);
6343           type = TREE_TYPE (arg);
6344         }
6345
6346       /* Remove the const from the pointers to simplify the overload
6347          matching further down.  */
6348       if (POINTER_TYPE_P (decl_type)
6349           && POINTER_TYPE_P (type)
6350           && TYPE_QUALS (TREE_TYPE (type)) != 0)
6351         {
6352           if (TYPE_READONLY (TREE_TYPE (type))
6353               && !TYPE_READONLY (TREE_TYPE (decl_type)))
6354             warning (0, "passing arg %d of %qE discards qualifiers from "
6355                         "pointer target type", n + 1, fndecl);
6356           type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6357                                                            0));
6358           arg = fold_convert (type, arg);
6359         }
6360
6361       args[n] = arg;
6362       types[n] = type;
6363     }
6364
6365   /* If the number of arguments did not match the prototype, return NULL
6366      and the generic code will issue the appropriate error message.  */
6367   if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6368     return NULL;
6369
6370   if (n == 0)
6371     abort ();
6372
6373   if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6374     {
6375       if (TREE_CODE (types[0]) != VECTOR_TYPE)
6376         goto bad;
6377
6378       return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6379     }
6380
6381   {
6382     bool unsupported_builtin = false;
6383     for (desc = altivec_overloaded_builtins;
6384          desc->code && desc->code != fcode; desc++)
6385       continue;
6386
6387     /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
6388        the opX fields.  */
6389     for (; desc->code == fcode; desc++)
6390       {
6391         if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
6392              || rs6000_builtin_type_compatible (types[0], desc->op1))
6393             && (desc->op2 == RS6000_BTI_NOT_OPAQUE
6394                 || rs6000_builtin_type_compatible (types[1], desc->op2))
6395             && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6396                 || rs6000_builtin_type_compatible (types[2], desc->op3)))
6397           {
6398             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6399               return altivec_build_resolved_builtin (args, n, desc);
6400             else
6401               unsupported_builtin = true;
6402           }
6403       }
6404
6405     if (unsupported_builtin)
6406       {
6407         const char *name = rs6000_overloaded_builtin_name (fcode);
6408         error ("Builtin function %s not supported in this compiler configuration",
6409                name);
6410         return error_mark_node;
6411       }
6412   }
6413  bad:
6414     {
6415       const char *name = rs6000_overloaded_builtin_name (fcode);
6416       error ("invalid parameter combination for AltiVec intrinsic %s", name);
6417       return error_mark_node;
6418     }
6419 }