| blob | d5fe01ca1cbb3475262e6747ee19bd9f510c370b |
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #ifndef GCC_MCORE_H
23 #define GCC_MCORE_H
25 /* RBE: need to move these elsewhere. */
26 #undef LIKE_PPC_ABI
27 #define MCORE_STRUCT_ARGS
28 /* RBE: end of "move elsewhere". */
32 #ifndef HAVE_MACHINE_MODES
34 #endif
36 /* Run-time Target Specification. */
37 #define TARGET_MCORE
39 /* Get tree.c to declare a target-specific specialization of
40 merge_decl_attributes. */
41 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
43 /* Support the __declspec keyword by turning them into attributes.
44 We currently only support: dllexport and dllimport.
45 Note that the current way we do this may result in a collision with
46 predefined attributes later on. This can be solved by using one attribute,
47 say __declspec__, and passing args to it. The problem with that approach
48 is that args are not accumulated: each new appearance would clobber any
49 existing args. XXX- FIXME the definition below relies upon string
50 concatenation, which is non-portable. */
51 #define CPP_PREDEFINES \
54 /* If -m4align is ever re-enabled then uncomment this line as well:
55 #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */
57 #undef CPP_SPEC
59 %{mbig-endian: \
60 %{mlittle-endian:%echoose either big or little endian, not both} \
61 -D__MCOREBE__} \
62 %{m210: \
63 %{m340:%echoose either m340 or m210 not both} \
64 %{mlittle-endian:%ethe m210 does not have little endian support} \
65 -D__M210__} \
66 %{!mbig-endian: -D__MCORELE__} \
67 %{!m210: -D__M340__} \
68 "
69 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
70 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
72 /* We don't have a -lg library, so don't put it in the list. */
73 #undef LIB_SPEC
76 #undef ASM_SPEC
79 #undef LINK_SPEC
82 /* Can only count on 16 bits of availability; change to long would affect
83 many architecture specific files (other architectures...). */
97 #define TARGET_DEFAULT \
98 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
100 #ifndef MULTILIB_DEFAULTS
102 #endif
104 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
105 /* The ability to have 4 byte alignment is being suppressed for now.
106 If this ability is reenabled, you must enable the definition below
107 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
108 #if 0
109 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
110 #else
111 #define TARGET_8ALIGN 1
112 #endif
113 #define TARGET_DIV (target_flags & DIV_BIT)
114 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
115 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
116 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
117 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
118 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
119 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
120 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
121 #define TARGET_M340 (target_flags & M340_BIT)
124 #define TARGET_SWITCHES \
168 }
172 /* Target specific options (as opposed to the switches above). */
175 #define TARGET_OPTIONS \
176 { \
179 }
181 #ifndef CC1_SPEC
182 /* The MCore ABI says that bitfields are unsigned by default. */
184 #endif
186 /* What options are we going to default to specific settings when
187 -O* happens; the user can subsequently override these settings.
189 Omitting the frame pointer is a very good idea on the MCore.
190 Scheduling isn't worth anything on the current MCore implementation. */
191 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
192 { \
193 if (LEVEL) \
194 { \
195 flag_no_function_cse = 1; \
196 flag_omit_frame_pointer = 1; \
197 \
198 if (LEVEL >= 2) \
199 { \
200 flag_caller_saves = 0; \
201 flag_schedule_insns = 0; \
202 flag_schedule_insns_after_reload = 0; \
203 } \
204 } \
205 if (SIZE) \
206 { \
207 target_flags &= ~ HARDLIT_BIT; \
208 } \
209 }
211 /* What options are we going to force to specific settings,
212 regardless of what the user thought he wanted.
213 We also use this for some post-processing of options. */
214 #define OVERRIDE_OPTIONS mcore_override_options ()
216 /* Target machine storage Layout. */
218 /* Define to use software floating point emulator for REAL_ARITHMETIC and
219 decimal <-> binary conversion. */
220 #define REAL_ARITHMETIC
222 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
223 if (GET_MODE_CLASS (MODE) == MODE_INT \
224 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
225 { \
226 (MODE) = SImode; \
227 (UNSIGNEDP) = 1; \
228 }
230 #define PROMOTE_FUNCTION_ARGS
232 #define PROMOTE_FUNCTION_RETURN
234 /* Define this if most significant bit is lowest numbered
235 in instructions that operate on numbered bit-fields. */
236 #define BITS_BIG_ENDIAN 0
238 /* Define this if most significant byte of a word is the lowest numbered. */
239 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
241 /* Define this if most significant word of a multiword number is the lowest
242 numbered. */
243 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
245 #define LIBGCC2_WORDS_BIG_ENDIAN 1
246 #ifdef __MCORELE__
247 #undef LIBGCC2_WORDS_BIG_ENDIAN
248 #define LIBGCC2_WORDS_BIG_ENDIAN 0
249 #endif
251 /* Number of bits in an addressable storage unit. */
252 #define BITS_PER_UNIT 8
254 /* Width in bits of a "word", which is the contents of a machine register.
255 Note that this is not necessarily the width of data type `int';
256 if using 16-bit ints on a 68000, this would still be 32.
257 But on a machine with 16-bit registers, this would be 16. */
258 #define BITS_PER_WORD 32
259 #define MAX_BITS_PER_WORD 32
261 /* Width of a word, in units (bytes). */
262 #define UNITS_PER_WORD 4
264 /* Width in bits of a pointer.
265 See also the macro `Pmode' defined below. */
266 #define POINTER_SIZE 32
268 /* A C expression for the size in bits of the type `long long' on the
269 target machine. If you don't define this, the default is two
270 words. */
271 #define LONG_LONG_TYPE_SIZE 64
273 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
274 #define PARM_BOUNDARY 32
276 /* Doubles must be alogned to an 8 byte boundary. */
277 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
278 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
279 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
281 /* Boundary (in *bits*) on which stack pointer should be aligned. */
282 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
284 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
286 #define STACK_UNITS_MAXSTEP 4096
288 /* Allocation boundary (in *bits*) for the code of a function. */
289 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
291 /* Alignment of field after `int : 0' in a structure. */
292 #define EMPTY_FIELD_BOUNDARY 32
294 /* No data type wants to be aligned rounder than this. */
295 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
297 /* The best alignment to use in cases where we have a choice. */
298 #define FASTEST_ALIGNMENT 32
300 /* Every structures size must be a multiple of 8 bits. */
301 #define STRUCTURE_SIZE_BOUNDARY 8
303 /* Look at the fundamental type that is used for a bitfield and use
304 that to impose alignment on the enclosing structure.
305 struct s {int a:8}; should have same alignment as "int", not "char". */
306 #define PCC_BITFIELD_TYPE_MATTERS 1
308 /* Largest integer machine mode for structures. If undefined, the default
309 is GET_MODE_SIZE(DImode). */
310 #define MAX_FIXED_MODE_SIZE 32
312 /* Make strings word-aligned so strcpy from constants will be faster. */
313 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
314 ((TREE_CODE (EXP) == STRING_CST \
315 && (ALIGN) < FASTEST_ALIGNMENT) \
316 ? FASTEST_ALIGNMENT : (ALIGN))
318 /* Make arrays of chars word-aligned for the same reasons. */
319 #define DATA_ALIGNMENT(TYPE, ALIGN) \
320 (TREE_CODE (TYPE) == ARRAY_TYPE \
321 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
322 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
324 /* Set this nonzero if move instructions will actually fail to work
325 when given unaligned data. */
326 #define STRICT_ALIGNMENT 1
328 /* Standard register usage. */
330 /* Register allocation for our first guess
332 r0 stack pointer
333 r1 scratch, target reg for xtrb?
334 r2-r7 arguments.
335 r8-r14 call saved
336 r15 link register
337 ap arg pointer (doesn't really exist, always eliminated)
338 c c bit
339 fp frame pointer (doesn't really exist, always eliminated)
340 x19 two control registers */
342 /* Number of actual hardware registers.
343 The hardware registers are assigned numbers for the compiler
344 from 0 to just below FIRST_PSEUDO_REGISTER.
345 All registers that the compiler knows about must be given numbers,
346 even those that are not normally considered general registers.
348 MCore has 16 integer registers and 2 control registers + the arg
349 pointer. */
351 #define FIRST_PSEUDO_REGISTER 20
356 /* RBE: mcore.md depends on CC_REG being set to 17 */
360 /* Specify the registers used for certain standard purposes.
361 The values of these macros are register numbers. */
368 /* The assembler's names for the registers. RFP need not always be used as
369 the Real framepointer; it can also be used as a normal general register.
370 Note that the name `fp' is horribly misleading since `fp' is in fact only
371 the argument-and-return-context pointer. */
372 #define REGISTER_NAMES \
373 { \
377 }
379 /* 1 for registers that have pervasive standard uses
380 and are not available for the register allocator. */
381 #define FIXED_REGISTERS \
383 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
385 /* 1 for registers not available across function calls.
386 These must include the FIXED_REGISTERS and also any
387 registers that can be used without being saved.
388 The latter must include the registers where values are returned
389 and the register where structure-value addresses are passed.
390 Aside from that, you can include as many other registers as you like. */
392 /* RBE: r15 {link register} not available across calls,
393 * But we don't mark it that way here... */
394 #define CALL_USED_REGISTERS \
396 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
398 /* The order in which register should be allocated. */
399 #define REG_ALLOC_ORDER \
401 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
403 /* Return number of consecutive hard regs needed starting at reg REGNO
404 to hold something of mode MODE.
405 This is ordinarily the length in words of a value of mode MODE
406 but can be less for certain modes in special long registers.
408 On the MCore regs are UNITS_PER_WORD bits wide; */
409 #define HARD_REGNO_NREGS(REGNO, MODE) \
410 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
412 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
413 We may keep double values in even registers. */
414 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
415 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
417 /* Value is 1 if it is a good idea to tie two pseudo registers
418 when one has mode MODE1 and one has mode MODE2.
419 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
420 for any hard reg, then this must be 0 for correct output. */
421 #define MODES_TIEABLE_P(MODE1, MODE2) \
422 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
424 /* Value should be nonzero if functions must have frame pointers.
425 Zero means the frame pointer need not be set up (and parms may be accessed
426 via the stack pointer) in functions that seem suitable. */
427 #define FRAME_POINTER_REQUIRED 0
429 /* Definitions for register eliminations.
431 We have two registers that can be eliminated on the MCore. First, the
432 frame pointer register can often be eliminated in favor of the stack
433 pointer register. Secondly, the argument pointer register can always be
434 eliminated; it is replaced with either the stack or frame pointer. */
436 /* Base register for access to arguments of the function. */
437 #define ARG_POINTER_REGNUM 16
439 /* Register in which the static-chain is passed to a function. */
440 #define STATIC_CHAIN_REGNUM 1
442 /* This is an array of structures. Each structure initializes one pair
443 of eliminable registers. The "from" register number is given first,
444 followed by "to". Eliminations of the same "from" register are listed
445 in order of preference. */
446 #define ELIMINABLE_REGS \
447 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
448 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
449 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
451 /* Given FROM and TO register numbers, say whether this elimination
452 is allowed. */
453 #define CAN_ELIMINATE(FROM, TO) \
454 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
456 /* Define the offset between two registers, one to be eliminated, and the other
457 its replacement, at the start of a routine. */
458 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
459 OFFSET = mcore_initial_elimination_offset (FROM, TO)
461 /* Place that structure value return address is placed. */
462 #define STRUCT_VALUE 0
464 /* Define the classes of registers for register constraints in the
465 machine description. Also define ranges of constants.
467 One of the classes must always be named ALL_REGS and include all hard regs.
468 If there is more than one class, another class must be named NO_REGS
469 and contain no registers.
471 The name GENERAL_REGS must be the name of a class (or an alias for
472 another name such as ALL_REGS). This is the class of registers
473 that is allowed by "g" or "r" in a register constraint.
474 Also, registers outside this class are allocated only when
475 instructions express preferences for them.
477 The classes must be numbered in nondecreasing order; that is,
478 a larger-numbered class must never be contained completely
479 in a smaller-numbered class.
481 For any two classes, it is very desirable that there be another
482 class that represents their union. */
484 /* The MCore has only general registers. There are
485 also some special purpose registers: the T bit register, the
486 procedure Link and the Count Registers */
487 enum reg_class
488 {
489 NO_REGS,
490 ONLYR1_REGS,
491 LRW_REGS,
492 GENERAL_REGS,
493 C_REGS,
494 ALL_REGS,
495 LIM_REG_CLASSES
496 };
498 #define N_REG_CLASSES (int) LIM_REG_CLASSES
500 /* Give names of register classes as strings for dump file. */
501 #define REG_CLASS_NAMES \
502 { \
509 }
511 /* Define which registers fit in which classes.
512 This is an initializer for a vector of HARD_REG_SET
513 of length N_REG_CLASSES. */
515 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
516 #define REG_CLASS_CONTENTS \
517 { \
524 }
526 /* The same information, inverted:
527 Return the class number of the smallest class containing
528 reg number REGNO. This could be a conditional expression
529 or could index an array. */
532 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
534 /* When defined, the compiler allows registers explicitly used in the
535 rtl to be used as spill registers but prevents the compiler from
536 extending the lifetime of these registers. */
537 #define SMALL_REGISTER_CLASSES 1
539 /* The class value for index registers, and the one for base regs. */
540 #define INDEX_REG_CLASS NO_REGS
541 #define BASE_REG_CLASS GENERAL_REGS
543 /* Get reg_class from a letter such as appears in the machine
544 description. */
547 #define REG_CLASS_FROM_LETTER(C) \
550 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
551 can be used to stand for particular ranges of immediate operands.
552 This macro defines what the ranges are.
553 C is the letter, and VALUE is a constant value.
554 Return 1 if VALUE is in the range specified by C.
555 I: loadable by movi (0..127)
556 J: arithmetic operand 1..32
557 K: shift operand 0..31
558 L: negative arithmetic operand -1..-32
559 M: powers of two, constants loadable by bgeni
560 N: powers of two minus 1, constants loadable by bmaski, including -1
561 O: allowed by cmov with two constants +/- 1 of each other
562 P: values we will generate 'inline' -- without an 'lrw'
564 Others defined for use after reload
565 Q: constant 1
566 R: a label
567 S: 0/1/2 cleared bits out of 32 [for bclri's]
568 T: 2 set bits out of 32 [for bseti's]
569 U: constant 0
570 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
571 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
572 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
573 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
574 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
575 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
576 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
577 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
578 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
579 CONST_OK_FOR_M(VALUE) || \
580 CONST_OK_FOR_N(VALUE) || \
581 CONST_OK_FOR_M((int)(VALUE) - 1) || \
582 CONST_OK_FOR_N((int)(VALUE) + 1))
584 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
586 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
595 : 0)
597 /* Similar, but for floating constants, and defining letters G and H.
598 Here VALUE is the CONST_DOUBLE rtx itself. */
599 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
601 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
602 : 0)
604 /* Letters in the range `Q' through `U' in a register constraint string
605 may be defined in a machine-dependent fashion to stand for arbitrary
606 operand types. */
607 #define EXTRA_CONSTRAINT(OP, C) \
609 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
611 && mcore_num_zeros (INTVAL (OP)) <= 2) \
613 && mcore_num_ones (INTVAL (OP)) == 2) \
615 && INTVAL(OP) == 1) \
617 && INTVAL(OP) == 0) \
618 : 0)
620 /* Given an rtx X being reloaded into a reg required to be
621 in class CLASS, return the class of reg to actually use.
622 In general this is just CLASS; but on some machines
623 in some cases it is preferable to use a more restrictive class. */
624 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
626 /* Return the register class of a scratch register needed to copy IN into
627 or out of a register in CLASS in MODE. If it can be done directly,
628 NO_REGS is returned. */
629 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
631 /* Return the maximum number of consecutive registers
632 needed to represent mode MODE in a register of class CLASS.
634 On MCore this is the size of MODE in words. */
635 #define CLASS_MAX_NREGS(CLASS, MODE) \
636 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
638 /* Stack layout; function entry, exit and calling. */
640 /* Define the number of register that can hold parameters.
641 These two macros are used only in other macro definitions below. */
642 #define NPARM_REGS 6
643 #define FIRST_PARM_REG 2
644 #define FIRST_RET_REG 2
646 /* Define this if pushing a word on the stack
647 makes the stack pointer a smaller address. */
648 #define STACK_GROWS_DOWNWARD
650 /* Define this if the nominal address of the stack frame
651 is at the high-address end of the local variables;
652 that is, each additional local variable allocated
653 goes at a more negative offset in the frame. */
654 /* We don't define this, because the MCore does not support
655 addresses with negative offsets. */
656 /* #define FRAME_GROWS_DOWNWARD */
658 /* Offset within stack frame to start allocating local variables at.
659 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
660 first local allocated. Otherwise, it is the offset to the BEGINNING
661 of the first local allocated. */
662 #define STARTING_FRAME_OFFSET 0
664 /* If defined, the maximum amount of space required for outgoing arguments
665 will be computed and placed into the variable
666 `current_function_outgoing_args_size'. No space will be pushed
667 onto the stack for each call; instead, the function prologue should
668 increase the stack frame size by this amount. */
669 #define ACCUMULATE_OUTGOING_ARGS 1
671 /* Offset of first parameter from the argument pointer register value. */
672 #define FIRST_PARM_OFFSET(FNDECL) 0
674 /* Value is the number of byte of arguments automatically
675 popped when returning from a subroutine call.
676 FUNTYPE is the data type of the function (as a tree),
677 or for a library call it is an identifier node for the subroutine name.
678 SIZE is the number of bytes of arguments passed on the stack.
680 On the MCore, the callee does not pop any of its arguments that were passed
681 on the stack. */
682 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
684 /* Define how to find the value returned by a function.
685 VALTYPE is the data type of the value (as a tree).
686 If the precise function being called is known, FUNC is its FUNCTION_DECL;
687 otherwise, FUNC is 0. */
688 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
690 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
691 we want to retain compatibility with older gcc versions. */
692 #define DEFAULT_PCC_STRUCT_RETURN 0
694 /* how we are going to return big values */
695 /*
696 * #define RETURN_IN_MEMORY(TYPE) \
697 * (TYPE_MODE (TYPE) == BLKmode \
698 * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
699 * && !(TYPE_MODE (TYPE) == SImode \
700 * || (TYPE_MODE (TYPE) == BLKmode \
701 * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \
702 * && int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
703 */
706 /* How many registers to use for struct return. */
707 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
709 /* Define how to find the value returned by a library function
710 assuming the value has mode MODE. */
711 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
713 /* 1 if N is a possible register number for a function value.
714 On the MCore, only r4 can return results. */
715 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
717 #define MUST_PASS_IN_STACK(MODE,TYPE) \
718 mcore_must_pass_on_stack (MODE, TYPE)
720 /* 1 if N is a possible register number for function argument passing. */
721 #define FUNCTION_ARG_REGNO_P(REGNO) \
722 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
724 /* Define a data type for recording info about an argument list
725 during the scan of that argument list. This data type should
726 hold all necessary information about the function itself
727 and about the args processed so far, enough to enable macros
728 such as FUNCTION_ARG to determine where the next arg should go.
730 On MCore, this is a single integer, which is a number of words
731 of arguments scanned so far (including the invisible argument,
732 if any, which holds the structure-value-address).
733 Thus NARGREGS or more means all following args should go on the stack. */
734 #define CUMULATIVE_ARGS int
736 #define ROUND_ADVANCE(SIZE) \
737 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
739 /* Round a register number up to a proper boundary for an arg of mode
740 MODE.
742 We round to an even reg for things larger than a word. */
743 #define ROUND_REG(X, MODE) \
744 ((TARGET_8ALIGN \
745 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
746 ? ((X) + ((X) & 1)) : (X))
749 /* Initialize a variable CUM of type CUMULATIVE_ARGS
750 for a call to a function whose data type is FNTYPE.
751 For a library call, FNTYPE is 0.
753 On MCore, the offset always starts at 0: the first parm reg is always
754 the same reg. */
755 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
756 ((CUM) = 0)
758 /* Update the data in CUM to advance over an argument
759 of mode MODE and data type TYPE.
760 (TYPE is null for libcalls where that information may not be
761 available.) */
762 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
763 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
764 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
766 /* Define where to put the arguments to a function. */
767 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
768 mcore_function_arg (CUM, MODE, TYPE, NAMED)
770 /* A C expression that indicates when an argument must be passed by
771 reference. If nonzero for an argument, a copy of that argument is
772 made in memory and a pointer to the argument is passed instead of
773 the argument itself. The pointer is passed in whatever way is
774 appropriate for passing a pointer to that type. */
775 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
776 MUST_PASS_IN_STACK (MODE, TYPE)
778 /* For an arg passed partly in registers and partly in memory,
779 this is the number of registers used.
780 For args passed entirely in registers or entirely in memory, zero.
781 Any arg that starts in the first NPARM_REGS regs but won't entirely
782 fit in them needs partial registers on the MCore. */
783 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
784 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
786 /* Perform any needed actions needed for a function that is receiving a
787 variable number of arguments. */
788 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
789 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
791 /* Call the function profiler with a given profile label. */
792 #define FUNCTION_PROFILER(STREAM,LABELNO) \
793 { \
797 }
799 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
800 the stack pointer does not matter. The value is tested only in
801 functions that have frame pointers.
802 No definition is equivalent to always zero. */
803 #define EXIT_IGNORE_STACK 0
805 /* Output assembler code for a block containing the constant parts
806 of a trampoline, leaving space for the variable parts.
808 On the MCore, the trapoline looks like:
809 lrw r1, function
810 lrw r13, area
811 jmp r13
812 or r0, r0
813 .literals */
814 #define TRAMPOLINE_TEMPLATE(FILE) \
815 { \
822 }
824 /* Length in units of the trampoline for entering a nested function. */
825 #define TRAMPOLINE_SIZE 12
827 /* Alignment required for a trampoline in bits. */
828 #define TRAMPOLINE_ALIGNMENT 32
830 /* Emit RTL insns to initialize the variable parts of a trampoline.
831 FNADDR is an RTX for the address of the function's pure code.
832 CXT is an RTX for the static chain value for the function. */
833 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
834 { \
835 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
836 (CXT)); \
837 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
838 (FNADDR)); \
839 }
841 /* Macros to check register numbers against specific register classes. */
843 /* These assume that REGNO is a hard or pseudo reg number.
844 They give nonzero only if REGNO is a hard reg of the suitable class
845 or a pseudo reg currently allocated to a suitable hard reg.
846 Since they use reg_renumber, they are safe only once reg_renumber
847 has been allocated, which happens in local-alloc.c. */
848 #define REGNO_OK_FOR_BASE_P(REGNO) \
849 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
851 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
853 /* Maximum number of registers that can appear in a valid memory
854 address. */
855 #define MAX_REGS_PER_ADDRESS 1
857 /* Recognize any constant value that is a valid address. */
858 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
860 /* Nonzero if the constant value X is a legitimate general operand.
861 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
863 On the MCore, allow anything but a double. */
864 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
866 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
867 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
868 and check its validity for a certain class.
869 We have two alternate definitions for each of them.
870 The usual definition accepts all pseudo regs; the other rejects
871 them unless they have been allocated suitable hard regs.
872 The symbol REG_OK_STRICT causes the latter definition to be used. */
873 #ifndef REG_OK_STRICT
875 /* Nonzero if X is a hard reg that can be used as a base reg
876 or if it is a pseudo reg. */
877 #define REG_OK_FOR_BASE_P(X) \
878 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
880 /* Nonzero if X is a hard reg that can be used as an index
881 or if it is a pseudo reg. */
882 #define REG_OK_FOR_INDEX_P(X) 0
884 #else
886 /* Nonzero if X is a hard reg that can be used as a base reg. */
887 #define REG_OK_FOR_BASE_P(X) \
888 REGNO_OK_FOR_BASE_P (REGNO (X))
890 /* Nonzero if X is a hard reg that can be used as an index. */
891 #define REG_OK_FOR_INDEX_P(X) 0
893 #endif
894 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
895 that is a valid memory address for an instruction.
896 The MODE argument is the machine mode for the MEM expression
897 that wants to use this address.
899 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
900 #define BASE_REGISTER_RTX_P(X) \
901 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
903 #define INDEX_REGISTER_RTX_P(X) \
904 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
907 /* Jump to LABEL if X is a valid address RTX. This must also take
908 REG_OK_STRICT into account when deciding about valid registers, but it uses
909 the above macros so we are in luck.
911 Allow REG
912 REG+disp
914 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
915 and for DI is 0..56 because we use two SI loads, etc. */
916 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
917 do \
918 { \
919 if (GET_CODE (OP) == CONST_INT) \
920 { \
921 if (GET_MODE_SIZE (MODE) >= 4 \
922 && (((unsigned)INTVAL (OP)) % 4) == 0 \
923 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
924 goto LABEL; \
925 if (GET_MODE_SIZE (MODE) == 2 \
926 && (((unsigned)INTVAL (OP)) % 2) == 0 \
927 && ((unsigned)INTVAL (OP)) <= 30) \
928 goto LABEL; \
929 if (GET_MODE_SIZE (MODE) == 1 \
930 && ((unsigned)INTVAL (OP)) <= 15) \
931 goto LABEL; \
932 } \
933 } \
934 while (0)
936 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
937 { \
938 if (BASE_REGISTER_RTX_P (X)) \
939 goto LABEL; \
940 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
941 { \
942 rtx xop0 = XEXP (X,0); \
943 rtx xop1 = XEXP (X,1); \
944 if (BASE_REGISTER_RTX_P (xop0)) \
945 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
946 if (BASE_REGISTER_RTX_P (xop1)) \
947 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
948 } \
949 }
951 /* Go to LABEL if ADDR (a legitimate address expression)
952 has an effect that depends on the machine mode it is used for. */
953 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
954 { \
955 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
956 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
957 goto LABEL; \
958 }
960 /* Specify the machine mode that this machine uses
961 for the index in the tablejump instruction. */
962 #define CASE_VECTOR_MODE SImode
964 /* Define this if the tablejump instruction expects the table
965 to contain offsets from the address of the table.
966 Do not define this if the table should contain absolute addresses. */
967 /* #define CASE_VECTOR_PC_RELATIVE */
969 /* 'char' is signed by default. */
970 #define DEFAULT_SIGNED_CHAR 0
972 /* The type of size_t unsigned int. */
975 /* Don't cse the address of the function being compiled. */
976 #define NO_RECURSIVE_FUNCTION_CSE 1
978 /* Max number of bytes we can move from memory to memory
979 in one reasonably fast instruction. */
980 #define MOVE_MAX 4
982 /* Define if operations between registers always perform the operation
983 on the full register even if a narrower mode is specified. */
984 #define WORD_REGISTER_OPERATIONS
986 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
987 will either zero-extend or sign-extend. The value of this macro should
988 be the code that says which one of the two operations is implicitly
989 done, NIL if none. */
990 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
992 /* Nonzero if access to memory by bytes is slow and undesirable. */
993 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
995 /* We assume that the store-condition-codes instructions store 0 for false
996 and some other value for true. This is the value stored for true. */
997 #define STORE_FLAG_VALUE 1
999 /* Immediate shift counts are truncated by the output routines (or was it
1000 the assembler?). Shift counts in a register are truncated by ARM. Note
1001 that the native compiler puts too large (> 32) immediate shift counts
1002 into a register and shifts by the register, letting the ARM decide what
1003 to do instead of doing that itself. */
1004 #define SHIFT_COUNT_TRUNCATED 1
1006 /* All integers have the same format so truncation is easy. */
1007 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1009 /* Define this if addresses of constant functions
1010 shouldn't be put through pseudo regs where they can be cse'd.
1011 Desirable on machines where ordinary constants are expensive
1012 but a CALL with constant address is cheap. */
1013 /* why is this defined??? -- dac */
1014 #define NO_FUNCTION_CSE 1
1016 /* Chars and shorts should be passed as ints. */
1017 #define PROMOTE_PROTOTYPES 1
1019 /* The machine modes of pointers and functions. */
1020 #define Pmode SImode
1021 #define FUNCTION_MODE Pmode
1023 /* The relative costs of various types of constants. Note that cse.c defines
1024 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1025 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1026 case CONST_INT: \
1027 return mcore_const_costs (RTX, OUTER_CODE); \
1028 case CONST: \
1029 case LABEL_REF: \
1030 case SYMBOL_REF: \
1031 return 5; \
1032 case CONST_DOUBLE: \
1033 return 10;
1035 /* provide the cost for an address calculation.
1036 All addressing modes cost the same on the MCore. */
1037 #define ADDRESS_COST(RTX) 1
1039 /* Provide the cost of an rtl expression. */
1040 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1041 case AND: \
1042 return COSTS_N_INSNS (mcore_and_cost (X)); \
1043 case IOR: \
1044 return COSTS_N_INSNS (mcore_ior_cost (X)); \
1045 case DIV: \
1046 case UDIV: \
1047 case MOD: \
1048 case UMOD: \
1049 return COSTS_N_INSNS (100); \
1050 case FLOAT: \
1051 case FIX: \
1052 return 100;
1054 /* Compute extra cost of moving data between one register class
1055 and another. All register moves are cheap. */
1056 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
1058 #define WORD_REGISTER_OPERATIONS
1060 /* Implicit library calls should use memcpy, not bcopy, etc. */
1061 #define TARGET_MEM_FUNCTIONS
1063 /* Assembler output control. */
1071 /* Switch to the text or data segment. */
1075 #undef EXTRA_SECTIONS
1076 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
1078 #undef EXTRA_SECTION_FUNCTIONS
1079 #define EXTRA_SECTION_FUNCTIONS \
1080 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
1081 SWITCH_SECTION_FUNCTION
1083 /* Switch to SECTION (an `enum in_section').
1085 ??? This facility should be provided by GCC proper.
1086 The problem is that we want to temporarily switch sections in
1087 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1088 afterwards. */
1089 #define SWITCH_SECTION_FUNCTION \
1090 static void switch_to_section PARAMS ((enum in_section, tree)); \
1091 static void \
1092 switch_to_section (section, decl) \
1093 enum in_section section; \
1094 tree decl; \
1095 { \
1096 switch (section) \
1097 { \
1098 case in_text: text_section (); break; \
1099 case in_data: data_section (); break; \
1100 case in_named: named_section (decl, NULL, 0); break; \
1101 SUBTARGET_SWITCH_SECTIONS \
1102 default: abort (); break; \
1103 } \
1104 }
1106 /* Switch into a generic section. */
1107 #undef TARGET_ASM_NAMED_SECTION
1108 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
1110 /* This is how to output an insn to push a register on the stack.
1111 It need not be very fast code. */
1112 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1114 reg_names[STACK_POINTER_REGNUM], \
1115 (STACK_BOUNDARY / BITS_PER_UNIT), \
1116 reg_names[REGNO], \
1117 reg_names[STACK_POINTER_REGNUM])
1119 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1120 #define REG_PUSH_LENGTH 2
1122 /* This is how to output an insn to pop a register from the stack. */
1123 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1125 reg_names[REGNO], \
1126 reg_names[STACK_POINTER_REGNUM], \
1127 reg_names[STACK_POINTER_REGNUM], \
1128 (STACK_BOUNDARY / BITS_PER_UNIT))
1131 /* Output a label definition. */
1132 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1135 /* Output a reference to a label. */
1136 #undef ASM_OUTPUT_LABELREF
1137 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1141 /* This is how to output an assembler line
1142 that says to advance the location counter
1143 to a multiple of 2**LOG bytes. */
1144 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1145 if ((LOG) != 0) \
1148 #ifndef ASM_DECLARE_RESULT
1149 #define ASM_DECLARE_RESULT(FILE, RESULT)
1150 #endif
1152 /* Strip export encoding from a function name. */
1153 #define MCORE_STRIP_NAME_ENCODING(SYM_NAME) \
1156 /* Strip any text from SYM_NAME added by ENCODE_SECTION_INFO and store
1157 the result in VAR. */
1158 #undef STRIP_NAME_ENCODING
1159 #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \
1160 (VAR) = MCORE_STRIP_NAME_ENCODING (SYM_NAME)
1162 #undef UNIQUE_SECTION
1163 #define UNIQUE_SECTION(DECL, RELOC) mcore_unique_section (DECL, RELOC)
1165 #define REDO_SECTION_INFO_P(DECL) 1
1167 #define MULTIPLE_SYMBOL_SPACES 1
1169 #define SUPPORTS_ONE_ONLY 1
1171 /* A pair of macros to output things for the callgraph data.
1172 VALUE means (to the tools that reads this info later):
1173 0 a call from src to dst
1174 1 the call is special (e.g. dst is "unknown" or "alloca")
1175 2 the call is special (e.g., the src is a table instead of routine)
1177 Frame sizes are augmented with timestamps to help later tools
1178 differentiate between static entities with same names in different
1179 files. */
1181 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1182 do \
1183 { \
1184 if (mcore_current_compilation_timestamp == 0) \
1185 mcore_current_compilation_timestamp = time (0); \
1187 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1188 } \
1189 while (0)
1191 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1192 do \
1193 { \
1195 (SRCNAME), (DSTNAME), (VALUE)); \
1196 } \
1197 while (0)
1199 /* Output a globalising directive for a label. */
1200 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1202 assemble_name (STREAM, NAME), \
1205 /* The prefix to add to user-visible assembler symbols. */
1206 #undef USER_LABEL_PREFIX
1209 /* Make an internal label into a string. */
1210 #undef ASM_GENERATE_INTERNAL_LABEL
1211 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1214 /* Output an internal label definition. */
1215 #undef ASM_OUTPUT_INTERNAL_LABEL
1216 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1219 /* Construct a private name. */
1220 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1221 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1224 /* Jump tables must be 32 bit aligned. */
1225 #undef ASM_OUTPUT_CASE_LABEL
1226 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1229 /* Output a relative address. Not needed since jump tables are absolute
1230 but we must define it anyway. */
1231 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1234 /* Output an element of a dispatch table. */
1235 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1238 /* Output various types of constants. */
1240 /* This is how to output an assembler line
1241 that says to advance the location counter by SIZE bytes. */
1242 #undef ASM_OUTPUT_SKIP
1243 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1246 /* This says how to output an assembler line
1247 to define a global common symbol, with alignment information. */
1248 /* XXX - for now we ignore the alignment. */
1249 #undef ASM_OUTPUT_ALIGNED_COMMON
1250 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1251 do \
1252 { \
1253 if (mcore_dllexport_name_p (NAME)) \
1254 MCORE_EXPORT_NAME (FILE, NAME) \
1255 if (! mcore_dllimport_name_p (NAME)) \
1256 { \
1258 assemble_name (FILE, NAME); \
1260 } \
1261 } \
1262 while (0)
1264 /* This says how to output an assembler line
1265 to define an external symbol. */
1266 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1267 do \
1268 { \
1270 assemble_name ((FILE), (NAME)); \
1272 } \
1273 while (0)
1275 #undef ASM_OUTPUT_EXTERNAL
1276 /* RBE: we undefined this and let gas do it's "undefined is imported"
1277 games. This is because when we use this, we get a marked
1278 reference through the call to assemble_name and this forces C++
1279 inlined member functions (or any inlined function) to be instantiated
1280 regardless of whether any callsites remain.
1281 This makes this aspect of the compiler non-ABI compliant. */
1283 /* Similar, but for libcall. FUN is an rtx. */
1284 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1285 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1286 do \
1287 { \
1289 assemble_name (FILE, XSTR (FUN, 0)); \
1291 } \
1292 while (0)
1295 /* This says how to output an assembler line
1296 to define a local common symbol... */
1297 #undef ASM_OUTPUT_LOCAL
1298 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1300 assemble_name (FILE, NAME), \
1303 /* ... and how to define a local common symbol whose alignment
1304 we wish to specify. ALIGN comes in as bits, we have to turn
1305 it into bytes. */
1306 #undef ASM_OUTPUT_ALIGNED_LOCAL
1307 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1308 do \
1309 { \
1311 assemble_name ((FILE), (NAME)); \
1313 } \
1314 while (0)
1316 /* We must mark dll symbols specially. Definitions of dllexport'd objects
1317 install some info in the .drective (PE) or .exports (ELF) sections. */
1318 #undef ENCODE_SECTION_INFO
1319 #define ENCODE_SECTION_INFO(DECL) mcore_encode_section_info (DECL)
1321 /* Print operand X (an rtx) in assembler syntax to file FILE.
1322 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1323 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1324 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1326 /* Print a memory address as an operand to reference that memory location. */
1327 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1329 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1332 /* This is to handle loads from the constant pool. */
1333 #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X)
1335 #define PREDICATE_CODES \