| blob | 8290342c80d378412b50c63fa2ab8393ad1cb0e1 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
55 /* Information about the loop being processed used to compute
56 the number of loop iterations for loop unrolling and doloop
57 optimization. */
60 /* Vector mapping INSN_UIDs to luids.
61 The luids are like uids but increase monotonically always.
62 We use them to see whether a jump comes from outside a given loop. */
66 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
67 number the insn is contained in. */
71 /* 1 + largest uid of any insn. */
75 /* 1 + luid of last insn. */
79 /* Number of loops detected in current function. Used as index to the
80 next few tables. */
84 /* Indexed by loop number, contains the first and last insn of each loop. */
88 /* Likewise for the continue insn */
91 /* The first code_label that is reached in every loop iteration.
92 0 when not computed yet, initially const0_rtx if a jump couldn't be
93 followed.
94 Also set to 0 when there is no such label before the NOTE_INSN_LOOP_CONT
95 of this loop, or in verify_dominator, if a jump couldn't be followed. */
98 /* For each loop, gives the containing loop number, -1 if none. */
102 #ifdef HAVE_decrement_and_branch_on_count
103 /* Records whether resource in use by inner loop. */
108 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
109 really a loop (an insn outside the loop branches into it). */
113 /* Indexed by loop number, links together all LABEL_REFs which refer to
114 code labels outside the loop. Used by routines that need to know all
115 loop exits, such as final_biv_value and final_giv_value.
117 This does not include loop exits due to return instructions. This is
118 because all bivs and givs are pseudos, and hence must be dead after a
119 return, so the presense of a return does not affect any of the
120 optimizations that use this info. It is simpler to just not include return
121 instructions on this list. */
125 /* Indexed by loop number, counts the number of LABEL_REFs on
126 loop_number_exit_labels for this loop and all loops nested inside it. */
130 /* Indexed by register number, contains the number of times the reg
131 is set during the loop being scanned.
132 During code motion, a negative value indicates a reg that has been
133 made a candidate; in particular -2 means that it is an candidate that
134 we know is equal to a constant and -1 means that it is an candidate
135 not known equal to a constant.
136 After code motion, regs moved have 0 (which is accurate now)
137 while the failed candidates have the original number of times set.
139 Therefore, at all times, == 0 indicates an invariant register;
140 < 0 a conditionally invariant one. */
144 /* Original value of set_in_loop; same except that this value
145 is not set negative for a reg whose sets have been made candidates
146 and not set to 0 for a reg that is moved. */
150 /* Index by register number, 1 indicates that the register
151 cannot be moved or strength reduced. */
155 /* Contains the insn in which a register was used if it was used
156 exactly once; contains const0_rtx if it was used more than once. */
160 /* Nonzero means reg N has already been moved out of one loop.
161 This reduces the desire to move it out of another. */
165 /* List of MEMs that are stored in this loop. */
169 /* The insn where the first of these was found. */
178 /* Array of MEMs that are used (read or written) in this loop, but
179 cannot be aliased by anything in this loop, except perhaps
180 themselves. In other words, if loop_mems[i] is altered during the
181 loop, it is altered by an expression that is rtx_equal_p to it. */
185 /* The index of the next available slot in LOOP_MEMS. */
189 /* The number of elements allocated in LOOP_MEMs. */
193 /* Nonzero if we don't know what MEMs were changed in the current
194 loop. This happens if the loop contains a call (in which case
195 `loop_info->has_call' will also be set) or if we store into more
196 than NUM_STORES MEMs. */
200 /* The above doesn't count any readonly memory locations that are stored.
201 This does. */
205 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
208 /* Count of memory write instructions discovered in the loop. */
211 /* Bound on pseudo register number before loop optimization.
212 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
215 /* This obstack is used in product_cheap_p to allocate its rtl. It
216 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
217 If we used the same obstack that it did, we would be deallocating
218 that array. */
222 /* This is where the pointer to the obstack being used for RTL is stored. */
226 #define obstack_chunk_alloc xmalloc
227 #define obstack_chunk_free free
228 \f
229 /* During the analysis of a loop, a chain of `struct movable's
230 is made to record all the movable insns found.
231 Then the entire chain can be scanned to decide which to move. */
233 struct movable
234 {
239 of any registers used within the LIBCALL. */
241 that must be moved with this one. */
244 may be adjusted when matching movables
245 that load the same value are found. */
247 including other movables that force this
248 or match this one. */
252 /* If PARTIAL is 1, GLOBAL means something different:
253 that the reg is live outside the range from where it is set
254 to the following label. */
258 In particular, moving it does not make it
259 invariant. */
261 load SRC, rather than copying INSN. */
263 first insn of a consecutive sets group. */
266 that we should avoid changing when clearing
267 the rest of the reg. */
271 };
277 /* Forward declarations. */
294 #if 0
296 #endif
315 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, int, rtx *, rtx, rtx));
343 rtx r;
348 rtx r1;
349 rtx r2;
352 /* Nonzero iff INSN is between START and END, inclusive. */
353 #define INSN_IN_RANGE_P(INSN, START, END) \
354 (INSN_UID (INSN) < max_uid_for_loop \
355 && INSN_LUID (INSN) >= INSN_LUID (START) \
356 && INSN_LUID (INSN) <= INSN_LUID (END))
358 #ifdef HAVE_decrement_and_branch_on_count
359 /* Test whether BCT applicable and safe. */
362 /* Auxiliary function that inserts the BCT pattern into the loop. */
366 /* Indirect_jump_in_function is computed once per function. */
374 \f
375 /* Relative gain of eliminating various kinds of operations. */
377 #if 0
380 #endif
382 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
383 copy the value of the strength reduced giv to its original register. */
386 /* Cost of using a register, to normalize the benefits of a giv. */
390 void
392 {
398 #ifdef ADDRESS_COST
400 #else
402 #endif
404 /* We multiply by 2 to reconcile the difference in scale between
405 these two ways of computing costs. Otherwise the cost of a copy
406 will be far less than the cost of an add. */
410 /* Free the objects we just allocated. */
413 /* Initialize the obstack used for rtl in product_cheap_p. */
415 }
416 \f
417 /* Compute the mapping from uids to luids.
418 LUIDs are numbers assigned to insns, like uids,
419 except that luids increase monotonically through the code.
420 Start at insn START and stop just before END. Assign LUIDs
421 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
422 static int
426 {
428 rtx insn;
431 {
434 /* Don't assign luids to line-number NOTEs, so that the distance in
435 luids between two insns is not affected by -g. */
439 else
440 /* Give a line number note the same luid as preceding insn. */
442 }
444 }
445 \f
446 /* Entry point of this file. Perform loop optimization
447 on the current function. F is the first insn of the function
448 and DUMPFILE is a stream for output of a trace of actions taken
449 (or 0 if none should be output). */
451 void
453 /* f is the first instruction of a chain of insns for one function */
454 rtx f;
457 {
469 /* Count the number of loops. */
473 {
476 max_loop_num++;
477 }
479 /* Don't waste time if no loops. */
485 /* Get size to use for tables indexed by uids.
486 Leave some space for labels allocated by find_and_verify_loops. */
492 /* Allocate tables for recording each loop. We set each entry, so they need
493 not be zeroed. */
503 #ifdef HAVE_decrement_and_branch_on_count
504 /* Allocate for BCT optimization */
508 /* Find and process each loop.
509 First, find them, and record them in order of their beginnings. */
512 /* Now find all register lifetimes. This must be done after
513 find_and_verify_loops, because it might reorder the insns in the
514 function. */
517 /* This must occur after reg_scan so that registers created by gcse
518 will have entries in the register tables.
520 We could have added a call to reg_scan after gcse_main in toplev.c,
521 but moving this call to init_alias_analysis is more efficient. */
524 /* See if we went too far. Note that get_max_uid already returns
525 one more that the maximum uid of all insn. */
528 /* Now reset it to the actual size we need. See above. */
531 /* find_and_verify_loops has already called compute_luids, but it might
532 have rearranged code afterwards, so we need to recompute the luids now. */
535 /* Don't leave gaps in uid_luid for insns that have been
536 deleted. It is possible that the first or last insn
537 using some register has been deleted by cross-jumping.
538 Make sure that uid_luid for that former insn's uid
539 points to the general area where that insn used to be. */
541 {
545 }
550 /* Create a mapping from loops to BLOCK tree nodes. */
554 /* Determine if the function has indirect jump. On some systems
555 this prevents low overhead loop instructions from being used. */
558 /* Now scan the loops, last ones first, since this means inner ones are done
559 before outer ones. */
565 /* If debugging and unrolling loops, we must replicate the tree nodes
566 corresponding to the blocks inside the loop, so that the original one
567 to one mapping will remain. */
573 /* Clean up. */
585 #ifdef HAVE_decrement_and_branch_on_count
589 }
590 \f
591 /* Returns the next insn, in execution order, after INSN. START and
592 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
593 respectively. LOOP_TOP, if non-NULL, is the top of the loop in the
594 insn-stream; it is used with loops that are entered near the
595 bottom. */
597 static rtx
599 rtx insn;
600 rtx start;
601 rtx end;
602 rtx loop_top;
603 {
607 {
609 /* Go to the top of the loop, and continue there. */
611 else
612 /* We're done. */
614 }
617 /* We're done. */
621 }
623 /* Optimize one loop whose start is LOOP_START and end is END.
624 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
625 NOTE_INSN_LOOP_END.
626 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
628 /* ??? Could also move memory writes out of loops if the destination address
629 is invariant, the source is invariant, the memory write is not volatile,
630 and if we can prove that no read inside the loop can read this address
631 before the write occurs. If there is a read of this address after the
632 write, then we can also mark the memory read as invariant. */
634 static void
638 {
640 rtx p;
641 /* 1 if we are scanning insns that could be executed zero times. */
643 /* 1 if we are scanning insns that might never be executed
644 due to a subroutine call which might exit before they are reached. */
646 /* For a rotated loop that is entered near the bottom,
647 this is the label at the top. Otherwise it is zero. */
649 /* Jump insn that enters the loop, or 0 if control drops in. */
651 /* Place in the loop where control enters. */
652 rtx scan_start;
653 /* Number of insns in the loop. */
657 rtx temp;
658 /* The SET from an insn, if it is the only SET in the insn. */
660 /* Chain describing insns movable in current loop. */
662 /* Last element in `movables' -- so we can add elements at the end. */
664 /* Ratio of extra register life span we can justify
665 for saving an instruction. More if loop doesn't call subroutines
666 since in that case saving an insn makes more difference
667 and more registers are available. */
669 /* Nonzero if we are scanning instructions in a sub-loop. */
674 /* Determine whether this loop starts with a jump down to a test at
675 the end. This will occur for a small number of loops with a test
676 that is too complex to duplicate in front of the loop.
678 We search for the first insn or label in the loop, skipping NOTEs.
679 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
680 (because we might have a loop executed only once that contains a
681 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
682 (in case we have a degenerate loop).
684 Note that if we mistakenly think that a loop is entered at the top
685 when, in fact, it is entered at the exit test, the only effect will be
686 slightly poorer optimization. Making the opposite error can generate
687 incorrect code. Since very few loops now start with a jump to the
688 exit test, the code here to detect that case is very conservative. */
691 p != end
697 ;
701 /* Set up variables describing this loop. */
705 /* If loop has a jump before the first label,
706 the true entry is the target of that jump.
707 Start scan from there.
708 But record in LOOP_TOP the place where the end-test jumps
709 back to so we can scan that after the end of the loop. */
711 {
714 /* Loop entry must be unconditional jump (and not a RETURN) */
717 /* Check to see whether the jump actually
718 jumps out of the loop (meaning it's no loop).
719 This case can happen for things like
720 do {..} while (0). If this label was generated previously
721 by loop, we can't tell anything about it and have to reject
722 the loop. */
724 {
727 }
728 }
730 /* If SCAN_START was an insn created by loop, we don't know its luid
731 as required by loop_reg_used_before_p. So skip such loops. (This
732 test may never be true, but it's best to play it safe.)
734 Also, skip loops where we do not start scanning at a label. This
735 test also rejects loops starting with a JUMP_INSN that failed the
736 test above. */
740 {
745 }
747 /* Count number of times each reg is set during this loop.
748 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
749 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
751 /* Allocate extra space for REGS that might be created by
752 load_mems. We allocate a little extra slop as well, in the hopes
753 that even after the moving of movables creates some new registers
754 we won't have to reallocate these arrays. However, we do grow
755 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
766 {
769 }
771 #ifdef AVOID_CCMODE_COPIES
772 /* Don't try to move insns which set CC registers if we should not
773 create CCmode register copies. */
777 #endif
783 {
789 }
791 /* Scan through the loop finding insns that are safe to move.
792 Set set_in_loop negative for the reg being set, so that
793 this reg will be considered invariant for subsequent insns.
794 We consider whether subsequent insns use the reg
795 in deciding whether it is worth actually moving.
797 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
798 and therefore it is possible that the insns we are scanning
799 would never be executed. At such times, we must make sure
800 that it is safe to execute the insn once instead of zero times.
801 When MAYBE_NEVER is 0, all insns will be executed at least once
802 so that is not a problem. */
807 {
819 {
826 /* Figure out what to use as a source of this insn. If a REG_EQUIV
827 note is given or if a REG_EQUAL note with a constant operand is
828 specified, use it as the source and mark that we should move
829 this insn by calling emit_move_insn rather that duplicating the
830 insn.
832 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
833 is present. */
837 else
838 {
843 {
845 /* A libcall block can use regs that don't appear in
846 the equivalent expression. To move the libcall,
847 we must move those regs too. */
849 }
850 }
852 /* Don't try to optimize a register that was made
853 by loop-optimization for an inner loop.
854 We don't know its life-span, so we can't compute the benefit. */
856 ;
858 than the one where it is set (meaning that
859 something after this point in the loop might
860 depend on its value before the set). */
862 /* And the set is not guaranteed to be executed one
863 the loop starts, or the value before the set is
864 needed before the set occurs...
866 ??? Note we have quadratic behaviour here, mitigated
867 by the fact that the previous test will often fail for
868 large loops. Rather than re-scanning the entire loop
869 each time for register usage, we should build tables
870 of the register usage and use them here instead. */
871 && (maybe_never
874 /* It is unsafe to move the set.
876 This code used to consider it OK to move a set of a variable
877 which was not created by the user and not used in an exit test.
878 That behavior is incorrect and was removed. */
879 ;
885 || (tem1
886 = consec_sets_invariant_p
889 p)))
890 /* If the insn can cause a trap (such as divide by zero),
891 can't move it unless it's guaranteed to be executed
892 once loop is entered. Even a function call might
893 prevent the trap insn from being reached
894 (since it might exit!) */
897 {
901 /* A potential lossage is where we have a case where two insns
902 can be combined as long as they are both in the loop, but
903 we move one of them outside the loop. For large loops,
904 this can lose. The most common case of this is the address
905 of a function being called.
907 Therefore, if this register is marked as being used exactly
908 once if we are in a loop with calls (a "large loop"), see if
909 we can replace the usage of this register with the source
910 of this SET. If we can, delete this insn.
912 Don't do this if P has a REG_RETVAL note or if we have
913 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
924 && (! SMALL_REGISTER_CLASSES
927 /* This test is not redundant; SET_SRC (set) might be
928 a call-clobbered register and the life of REGNO
929 might span a call. */
931 VARRAY_RTX
935 VARRAY_RTX
937 {
938 /* Replace any usage in a REG_EQUAL note. Must copy the
939 new source, so that we don't get rtx sharing between the
940 SET_SOURCE and REG_NOTES of insn p. */
951 }
970 /* Set M->cond if either invariant_p or consec_sets_invariant_p
971 returned 2 (only conditionally invariant). */
982 /* Add M to the end of the chain MOVABLES. */
985 else
990 {
991 /* It is possible for the first instruction to have a
992 REG_EQUAL note but a non-invariant SET_SRC, so we must
993 remember the status of the first instruction in case
994 the last instruction doesn't have a REG_EQUAL note. */
997 /* Skip this insn, not checking REG_LIBCALL notes. */
999 /* Skip the consecutive insns, if there are any. */
1001 /* Back up to the last insn of the consecutive group. */
1004 /* We must now reset m->move_insn, m->is_equiv, and possibly
1005 m->set_src to correspond to the effects of all the
1006 insns. */
1010 else
1011 {
1015 else
1018 }
1020 }
1021 }
1022 /* If this register is always set within a STRICT_LOW_PART
1023 or set to zero, then its high bytes are constant.
1024 So clear them outside the loop and within the loop
1025 just load the low bytes.
1026 We must check that the machine has an instruction to do so.
1027 Also, if the value loaded into the register
1028 depends on the same register, this cannot be done. */
1038 {
1041 {
1055 /* If the insn may not be executed on some cycles,
1056 we can't clear the whole reg; clear just high part.
1057 Not even if the reg is used only within this loop.
1058 Consider this:
1059 while (1)
1060 while (s != t) {
1061 if (foo ()) x = *s;
1062 use (x);
1063 }
1064 Clearing x before the inner loop could clobber a value
1065 being saved from the last time around the outer loop.
1066 However, if the reg is not used outside this loop
1067 and all uses of the register are in the same
1068 basic block as the store, there is no problem.
1070 If this insn was made by loop, we don't know its
1071 INSN_LUID and hence must make a conservative
1072 assumption. */
1078 || (labels_in_range_p
1082 else
1091 /* Add M to the end of the chain MOVABLES. */
1094 else
1097 }
1098 }
1099 }
1100 /* Past a call insn, we get to insns which might not be executed
1101 because the call might exit. This matters for insns that trap.
1102 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1103 so they don't count. */
1106 /* Past a label or a jump, we get to insns for which we
1107 can't count on whether or how many times they will be
1108 executed during each iteration. Therefore, we can
1109 only move out sets of trivial variables
1110 (those not used after the loop). */
1111 /* Similar code appears twice in strength_reduce. */
1113 /* If we enter the loop in the middle, and scan around to the
1114 beginning, don't set maybe_never for that. This must be an
1115 unconditional jump, otherwise the code at the top of the
1116 loop might never be executed. Unconditional jumps are
1117 followed a by barrier then loop end. */
1123 {
1124 /* At the virtual top of a converted loop, insns are again known to
1125 be executed: logically, the loop begins here even though the exit
1126 code has been duplicated. */
1130 loop_depth++;
1132 loop_depth--;
1133 }
1134 }
1136 /* If one movable subsumes another, ignore that other. */
1140 /* For each movable insn, see if the reg that it loads
1141 leads when it dies right into another conditionally movable insn.
1142 If so, record that the second insn "forces" the first one,
1143 since the second can be moved only if the first is. */
1147 /* See if there are multiple movable insns that load the same value.
1148 If there are, make all but the first point at the first one
1149 through the `match' field, and add the priorities of them
1150 all together as the priority of the first. */
1154 /* Now consider each movable insn to decide whether it is worth moving.
1155 Store 0 in set_in_loop for each reg that is moved.
1157 Generally this increases code size, so do not move moveables when
1158 optimizing for code size. */
1164 /* Now candidates that still are negative are those not moved.
1165 Change set_in_loop to indicate that those are not actually invariant. */
1170 /* Now that we've moved some things out of the loop, we might be able to
1171 hoist even more memory references. */
1176 {
1181 }
1187 }
1188 \f
1189 /* Add elements to *OUTPUT to record all the pseudo-regs
1190 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1192 void
1196 {
1204 {
1222 }
1226 {
1230 {
1239 }
1240 }
1241 }
1242 \f
1243 /* Check what regs are referred to in the libcall block ending with INSN,
1244 aside from those mentioned in the equivalent value.
1245 If there are none, return 0.
1246 If there are one or more, return an EXPR_LIST containing all of them. */
1248 rtx
1251 {
1256 /* First, find all the regs used in the libcall block
1257 that are not mentioned as inputs to the result. */
1260 {
1265 }
1268 }
1269 \f
1270 /* Return 1 if all uses of REG
1271 are between INSN and the end of the basic block. */
1273 static int
1276 {
1278 rtx p;
1283 /* Search this basic block for the already recorded last use of the reg. */
1285 {
1287 {
1293 /* Ordinary insn: if this is the last use, we win. */
1299 /* Jump insn: if this is the last use, we win. */
1302 /* Otherwise, it's the end of the basic block, so we lose. */
1307 /* It's the end of the basic block, so we lose. */
1312 }
1313 }
1315 /* The "last use" doesn't follow the "first use"?? */
1317 }
1318 \f
1319 /* Compute the benefit of eliminating the insns in the block whose
1320 last insn is LAST. This may be a group of insns used to compute a
1321 value directly or can contain a library call. */
1323 static int
1325 rtx last;
1326 {
1327 rtx insn;
1332 {
1335 routine. */
1339 benefit++;
1340 }
1343 }
1344 \f
1345 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1347 static rtx
1349 rtx insn;
1351 {
1353 {
1354 rtx temp;
1356 /* If first insn of libcall sequence, skip to end. */
1357 /* Do this at start of loop, since INSN is guaranteed to
1358 be an insn here. */
1365 }
1368 }
1370 /* Ignore any movable whose insn falls within a libcall
1371 which is part of another movable.
1372 We make use of the fact that the movable for the libcall value
1373 was made later and so appears later on the chain. */
1375 static void
1378 {
1382 {
1383 /* Is this a movable for the value of a libcall? */
1386 {
1387 rtx insn;
1388 /* Check for earlier movables inside that range,
1389 and mark them invalid. We cannot use LUIDs here because
1390 insns created by loop.c for prior loops don't have LUIDs.
1391 Rather than reject all such insns from movables, we just
1392 explicitly check each insn in the libcall (since invariant
1393 libcalls aren't that common). */
1398 }
1399 }
1400 }
1402 /* For each movable insn, see if the reg that it loads
1403 leads when it dies right into another conditionally movable insn.
1404 If so, record that the second insn "forces" the first one,
1405 since the second can be moved only if the first is. */
1407 static void
1410 {
1413 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1415 {
1418 /* ??? Could this be a bug? What if CSE caused the
1419 register of M1 to be used after this insn?
1420 Since CSE does not update regno_last_uid,
1421 this insn M->insn might not be where it dies.
1422 But very likely this doesn't matter; what matters is
1423 that M's reg is computed from M1's reg. */
1428 /* If m->consec, m->set_src isn't valid. */
1432 /* Increase the priority of the moving the first insn
1433 since it permits the second to be moved as well. */
1435 {
1439 }
1440 }
1441 }
1442 \f
1443 /* Find invariant expressions that are equal and can be combined into
1444 one register. */
1446 static void
1450 {
1455 /* Regs that are set more than once are not allowed to match
1456 or be matched. I'm no longer sure why not. */
1457 /* Perhaps testing m->consec_sets would be more appropriate here? */
1461 {
1468 /* We want later insns to match the first one. Don't make the first
1469 one match any later ones. So start this loop at m->next. */
1472 /* A reg used outside the loop mustn't be eliminated. */
1474 /* A reg used for zero-extending mustn't be eliminated. */
1477 ||
1478 (
1479 /* Can combine regs with different modes loaded from the
1480 same constant only if the modes are the same or
1481 if both are integer modes with M wider or the same
1482 width as M1. The check for integer is redundant, but
1483 safe, since the only case of differing destination
1484 modes with equal sources is when both sources are
1485 VOIDmode, i.e., CONST_INT. */
1491 /* See if the source of M1 says it matches M. */
1495 movables))))
1498 {
1504 }
1505 }
1507 /* Now combine the regs used for zero-extension.
1508 This can be done for those not marked `global'
1509 provided their lives don't overlap. */
1513 {
1516 /* Combine all the registers for extension from mode MODE.
1517 Don't combine any that are used outside this loop. */
1521 {
1527 {
1528 /* First one: don't check for overlap, just record it. */
1531 }
1533 /* Make sure they extend to the same mode.
1534 (Almost always true.) */
1538 /* We already have one: check for overlap with those
1539 already combined together. */
1546 /* No overlap: we can combine this with the others. */
1552 overlap: ;
1553 }
1554 }
1555 }
1556 \f
1557 /* Return 1 if regs X and Y will become the same if moved. */
1559 static int
1563 {
1580 }
1582 /* Return 1 if X and Y are identical-looking rtx's.
1583 This is the Lisp function EQUAL for rtx arguments.
1585 If two registers are matching movables or a movable register and an
1586 equivalent constant, consider them equal. */
1588 static int
1592 {
1606 /* If we have a register and a constant, they may sometimes be
1607 equal. */
1610 {
1615 }
1618 {
1623 }
1625 /* Otherwise, rtx's of different codes cannot be equal. */
1629 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1630 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1635 /* These three types of rtx's can be compared nonrecursively. */
1644 /* Compare the elements. If any pair of corresponding elements
1645 fail to match, return 0 for the whole things. */
1649 {
1651 {
1663 /* Two vectors must have the same length. */
1667 /* And the corresponding elements must match. */
1684 /* These are just backpointers, so they don't matter. */
1690 /* It is believed that rtx's at this level will never
1691 contain anything but integers and other rtx's,
1692 except for within LABEL_REFs and SYMBOL_REFs. */
1695 }
1696 }
1698 }
1699 \f
1700 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1701 insns in INSNS which use the reference. */
1703 static void
1705 rtx x;
1706 rtx insns;
1707 {
1711 rtx insn;
1714 {
1715 /* This code used to ignore labels that referred to dispatch tables to
1716 avoid flow generating (slighly) worse code.
1718 We no longer ignore such label references (see LABEL_REF handling in
1719 mark_jump_label for additional information). */
1724 }
1728 {
1734 }
1735 }
1736 \f
1737 /* Scan MOVABLES, and move the insns that deserve to be moved.
1738 If two matching movables are combined, replace one reg with the
1739 other throughout. */
1741 static void
1746 rtx loop_start;
1747 rtx end;
1749 {
1753 /* Map of pseudo-register replacements to handle combining
1754 when we move several insns that load the same value
1755 into different pseudo-registers. */
1765 {
1766 /* Describe this movable insn. */
1769 {
1790 }
1792 /* Count movables. Value used in heuristics in strength_reduce. */
1793 num_movables++;
1795 /* Ignore the insn if it's already done (it matched something else).
1796 Otherwise, see if it is now safe to move. */
1808 {
1813 /* We have an insn that is safe to move.
1814 Compute its desirability. */
1825 /* An insn MUST be moved if we already moved something else
1826 which is safe only if this one is moved too: that is,
1827 if already_moved[REGNO] is nonzero. */
1829 /* An insn is desirable to move if the new lifetime of the
1830 register is no more than THRESHOLD times the old lifetime.
1831 If it's not desirable, it means the loop is so big
1832 that moving won't speed things up much,
1833 and it is liable to make register usage worse. */
1835 /* It is also desirable to move if it can be moved at no
1836 extra cost because something else was already moved. */
1839 || flag_move_all_movables
1844 {
1849 /* Now move the insns that set the reg. */
1852 {
1855 /* Find the end of this chain of matching regs.
1856 Thus, we load each reg in the chain from that one reg.
1857 And that reg is loaded with 0 directly,
1858 since it has ->match == 0. */
1864 /* Mark the moved, invariant reg as being allowed to
1865 share a hard reg with the other matching invariant. */
1869 regs_may_share
1872 regs_may_share));
1880 }
1881 /* If we are to re-generate the item being moved with a
1882 new move insn, first delete what we have and then emit
1883 the move insn before the loop. */
1885 {
1889 {
1890 /* If this is the first insn of a library call sequence,
1891 skip to the end. */
1896 /* If this is the last insn of a libcall sequence, then
1897 delete every insn in the sequence except the last.
1898 The last insn is handled in the normal manner. */
1901 {
1905 }
1910 /* simplify_giv_expr expects that it can walk the insns
1911 at m->insn forwards and see this old sequence we are
1912 tossing here. delete_insn does preserve the next
1913 pointers, but when we skip over a NOTE we must fix
1914 it up. Otherwise that code walks into the non-deleted
1915 insn stream. */
1918 }
1936 /* The more regs we move, the less we like moving them. */
1938 }
1939 else
1940 {
1942 {
1945 /* If first insn of libcall sequence, skip to end. */
1946 /* Do this at start of loop, since p is guaranteed to
1947 be an insn here. */
1952 /* If last insn of libcall sequence, move all
1953 insns except the last before the loop. The last
1954 insn is handled in the normal manner. */
1957 {
1965 {
1966 rtx body;
1967 rtx n;
1968 rtx next;
1975 /* Find the next insn after TEMP,
1976 not counting USE or NOTE insns. */
1984 /* If that is the call, this may be the insn
1985 that loads the function address.
1987 Extract the function address from the insn
1988 that loads it into a register.
1989 If this insn was cse'd, we get incorrect code.
1991 So emit a new move insn that copies the
1992 function address into the register that the
1993 call insn will use. flow.c will delete any
1994 redundant stores that we have created. */
1999 NULL_RTX)))
2000 {
2006 }
2007 /* We have the call insn.
2008 If it uses the register we suspect it might,
2009 load it with the correct address directly. */
2014 fn_address),
2015 fn_address_insn);
2018 {
2020 /* Because the USAGE information potentially
2021 contains objects other than hard registers
2022 we need to copy it. */
2026 }
2027 else
2035 }
2038 }
2040 {
2041 /* P sets REG to zero; but we should clear only
2042 the bits that are not covered by the mode
2043 m->savemode. */
2045 rtx sequence;
2046 rtx tem;
2049 tem = expand_binop
2062 }
2064 {
2066 /* Because the USAGE information potentially
2067 contains objects other than hard registers
2068 we need to copy it. */
2072 }
2074 {
2075 /* The SET_SRC might not be invariant, so we must
2076 use the REG_EQUAL note. */
2090 }
2091 else
2095 {
2098 /* If there is a REG_EQUAL note present whose value
2099 is not loop invariant, then delete it, since it
2100 may cause problems with later optimization passes.
2101 It is possible for cse to create such notes
2102 like this as a result of record_jump_cond. */
2107 }
2116 /* If library call, now fix the REG_NOTES that contain
2117 insn pointers, namely REG_LIBCALL on FIRST
2118 and REG_RETVAL on I1. */
2120 {
2124 }
2130 /* simplify_giv_expr expects that it can walk the insns
2131 at m->insn forwards and see this old sequence we are
2132 tossing here. delete_insn does preserve the next
2133 pointers, but when we skip over a NOTE we must fix
2134 it up. Otherwise that code walks into the non-deleted
2135 insn stream. */
2138 }
2140 /* The more regs we move, the less we like moving them. */
2142 }
2144 /* Any other movable that loads the same register
2145 MUST be moved. */
2148 /* This reg has been moved out of one loop. */
2151 /* The reg set here is now invariant. */
2157 /* Change the length-of-life info for the register
2158 to say it lives at least the full length of this loop.
2159 This will help guide optimizations in outer loops. */
2162 /* This is the old insn before all the moved insns.
2163 We can't use the moved insn because it is out of range
2164 in uid_luid. Only the old insns have luids. */
2169 /* Combine with this moved insn any other matching movables. */
2174 {
2175 rtx temp;
2177 /* Schedule the reg loaded by M1
2178 for replacement so that shares the reg of M.
2179 If the modes differ (only possible in restricted
2180 circumstances, make a SUBREG.
2182 Note this assumes that the target dependent files
2183 treat REG and SUBREG equally, including within
2184 GO_IF_LEGITIMATE_ADDRESS and in all the
2185 predicates since we never verify that replacing the
2186 original register with a SUBREG results in a
2187 recognizable insn. */
2190 else
2195 /* Get rid of the matching insn
2196 and prevent further processing of it. */
2199 /* if library call, delete all insn except last, which
2200 is deleted below */
2202 NULL_RTX)))
2203 {
2207 }
2210 /* Any other movable that loads the same register
2211 MUST be moved. */
2214 /* The reg merged here is now invariant,
2215 if the reg it matches is invariant. */
2218 }
2219 }
2222 }
2228 }
2233 /* Go through all the instructions in the loop, making
2234 all the register substitutions scheduled in REG_MAP. */
2238 {
2242 }
2243 }
2244 \f
2245 #if 0
2246 /* Scan X and replace the address of any MEM in it with ADDR.
2247 REG is the address that MEM should have before the replacement. */
2249 static void
2252 {
2261 {
2273 /* Short cut for very common case. */
2278 /* Short cut for very common case. */
2283 /* If this MEM uses a reg other than the one we expected,
2284 something is wrong. */
2292 }
2296 {
2300 {
2304 }
2305 }
2306 }
2307 #endif
2308 \f
2309 /* Return the number of memory refs to addresses that vary
2310 in the rtx X. */
2312 static int
2314 rtx x;
2315 {
2326 {
2343 }
2348 {
2352 {
2356 }
2357 }
2359 }
2361 \f
2362 #if 0
2363 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2364 Replace it with an instruction to load just the low bytes
2365 if the machine supports such an instruction,
2366 and insert above LOOP_START an instruction to clear the register. */
2368 static void
2371 {
2375 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2376 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2378 new
2379 = gen_rtx_SET
2381 gen_rtx_STRICT_LOW_PART
2390 {
2393 /* Clear destination register before the loop. */
2396 loop_start);
2398 /* Inside the loop, just load the low part. */
2400 }
2401 }
2402 #endif
2403 \f
2404 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2405 `has_call', `has_volatile', and `has_tablejump' within LOOP_INFO.
2406 Set the global variables `unknown_address_altered',
2407 `unknown_constant_address_altered', and `num_mem_sets'. Also, fill
2408 in the array `loop_mems' and the list `loop_store_mems'. */
2410 static void
2414 {
2416 rtx insn;
2417 /* The label after END. Jumping here is just like falling off the
2418 end of the loop. We use next_nonnote_insn instead of next_label
2419 as a hedge against the (pathological) case where some actual insn
2420 might end up between the two. */
2442 {
2444 {
2446 {
2448 /* Count number of loops contained in this one. */
2450 }
2452 {
2455 {
2458 }
2459 }
2461 {
2464 }
2466 {
2467 /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for
2468 or while style loop, with a loop exit test at the
2469 start. Thus, we can assume that the loop condition
2470 was true when the loop was entered. */
2473 }
2474 }
2476 {
2480 }
2482 {
2502 {
2504 {
2507 }
2508 else
2509 {
2511 }
2515 {
2517 {
2518 /* Something tricky. */
2521 }
2524 {
2525 /* A jump outside the current loop. */
2528 }
2529 }
2534 }
2535 }
2538 }
2540 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2542 !unknown_address_altered
2543 /* An exception thrown by a called function might land us
2544 anywhere. */
2546 /* We don't want loads for MEMs moved to a location before the
2547 one at which their stack memory becomes allocated. (Note
2548 that this is not a problem for malloc, etc., since those
2549 require actual function calls. */
2550 && !current_function_calls_alloca
2551 /* There are ways to leave the loop other than falling off the
2552 end. */
2557 }
2558 \f
2559 /* LOOP_NUMBER_CONT_DOMINATOR is now the last label between the loop start
2560 and the continue note that is a the destination of a (cond)jump after
2561 the continue note. If there is any (cond)jump between the loop start
2562 and what we have so far as LOOP_NUMBER_CONT_DOMINATOR that has a
2563 target between LOOP_DOMINATOR and the continue note, move
2564 LOOP_NUMBER_CONT_DOMINATOR forward to that label; if a jump's
2565 destination cannot be determined, clear LOOP_NUMBER_CONT_DOMINATOR. */
2567 static void
2570 {
2571 rtx insn;
2574 /* This can happen for an empty loop, e.g. in
2575 gcc.c-torture/compile/920410-2.c */
2578 {
2581 }
2585 {
2588 {
2592 /* If it is not a jump we can easily understand or for
2593 which we do not have jump target information in the JUMP_LABEL
2594 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2595 LOOP_NUMBER_CONT_DOMINATOR. */
2599 {
2602 }
2606 && (label_luid
2609 }
2610 }
2611 }
2613 /* Scan the function looking for loops. Record the start and end of each loop.
2614 Also mark as invalid loops any loops that contain a setjmp or are branched
2615 to from outside the loop. */
2617 static void
2619 rtx f;
2620 {
2628 /* If there are jumps to undefined labels,
2629 treat them as jumps out of any/all loops.
2630 This also avoids writing past end of tables when there are no loops. */
2633 /* Find boundaries of loops, mark which loops are contained within
2634 loops, and invalidate loops that have setjmp. */
2637 {
2640 {
2654 /* In this case, we must invalidate our current loop and any
2655 enclosing loop. */
2657 {
2663 }
2680 }
2681 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2682 and NOTE_INSN_LOOP_END notes, update loop_number_loop_dominator. */
2686 {
2694 do
2695 {
2696 /* First see if we care about this loop. */
2699 {
2700 /* If the jump destination is not known, invalidate
2701 loop_number_const_dominator. */
2704 else
2705 /* Check if the destination is between loop start and
2706 cont. */
2711 /* And if there is no later destination already
2712 recorded. */
2718 }
2720 }
2722 }
2724 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2725 enclosing loop, but this doesn't matter. */
2727 }
2729 /* Any loop containing a label used in an initializer must be invalidated,
2730 because it can be jumped into from anywhere. */
2733 {
2740 }
2742 /* Any loop containing a label used for an exception handler must be
2743 invalidated, because it can be jumped into from anywhere. */
2746 {
2753 }
2755 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2756 loop that it is not contained within, that loop is marked invalid.
2757 If any INSN or CALL_INSN uses a label's address, then the loop containing
2758 that label is marked invalid, because it could be jumped into from
2759 anywhere.
2761 Also look for blocks of code ending in an unconditional branch that
2762 exits the loop. If such a block is surrounded by a conditional
2763 branch around the block, move the block elsewhere (see below) and
2764 invert the jump to point to the code block. This may eliminate a
2765 label in our loop and will simplify processing by both us and a
2766 possible second cse pass. */
2770 {
2774 {
2777 {
2784 }
2785 }
2792 /* See if this is an unconditional branch outside the loop. */
2799 {
2800 rtx p;
2806 /* Go backwards until we reach the start of the loop, a label,
2807 or a JUMP_INSN. */
2814 ;
2816 /* Check for the case where we have a jump to an inner nested
2817 loop, and do not perform the optimization in that case. */
2820 {
2823 {
2828 }
2829 }
2831 /* Make sure that the target of P is within the current loop. */
2837 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2838 we have a block of code to try to move.
2840 We look backward and then forward from the target of INSN
2841 to find a BARRIER at the same loop depth as the target.
2842 If we find such a BARRIER, we make a new label for the start
2843 of the block, invert the jump in P and point it to that label,
2844 and move the block of code to the spot we found. */
2849 /* Just ignore jumps to labels that were never emitted.
2850 These always indicate compilation errors. */
2855 /* If it's not safe to move the sequence, then we
2856 mustn't try. */
2859 {
2860 rtx target
2867 /* Don't move things inside a tablejump. */
2880 /* Don't move things inside a tablejump. */
2891 {
2895 /* Ensure our label doesn't go away. */
2898 /* Verify that uid_loop_num is large enough and that
2899 we can invert P. */
2901 {
2904 /* If no suitable BARRIER was found, create a suitable
2905 one before TARGET. Since TARGET is a fall through
2906 path, we'll need to insert an jump around our block
2907 and a add a BARRIER before TARGET.
2909 This creates an extra unconditional jump outside
2910 the loop. However, the benefits of removing rarely
2911 executed instructions from inside the loop usually
2912 outweighs the cost of the extra unconditional jump
2913 outside the loop. */
2915 {
2916 rtx temp;
2923 }
2925 /* Include the BARRIER after INSN and copy the
2926 block after LOC. */
2928 last_insn_to_move);
2931 /* All those insns are now in TARGET_LOOP_NUM. */
2937 /* The label jumped to by INSN is no longer a loop exit.
2938 Unless INSN does not have a label (e.g., it is a
2939 RETURN insn), search loop_number_exit_labels to find
2940 its label_ref, and remove it. Also turn off
2941 LABEL_OUTSIDE_LOOP_P bit. */
2943 {
2950 {
2954 else
2958 }
2965 /* If we didn't find it, then something is wrong. */
2968 }
2970 /* P is now a jump outside the loop, so it must be put
2971 in loop_number_exit_labels, and marked as such.
2972 The easiest way to do this is to just call
2973 mark_loop_jump again for P. */
2976 /* If INSN now jumps to the insn after it,
2977 delete INSN. */
2982 }
2984 /* Continue the loop after where the conditional
2985 branch used to jump, since the only branch insn
2986 in the block (if it still remains) is an inter-loop
2987 branch and hence needs no processing. */
2993 /* This loop will be continued with NEXT_INSN (insn). */
2995 }
2996 }
2997 }
2998 }
2999 }
3001 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3002 loops it is contained in, mark the target loop invalid.
3004 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3006 static void
3008 rtx x;
3010 {
3016 {
3028 /* There could be a label reference in here. */
3040 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3052 /* Link together all labels that branch outside the loop. This
3053 is used by final_[bg]iv_value and the loop unrolling code. Also
3054 mark this LABEL_REF so we know that this branch should predict
3055 false. */
3057 /* A check to make sure the label is not in an inner nested loop,
3058 since this does not count as a loop exit. */
3060 {
3065 }
3066 else
3070 {
3079 }
3081 /* If this is inside a loop, but not in the current loop or one enclosed
3082 by it, it invalidates at least one loop. */
3087 /* We must invalidate every nested loop containing the target of this
3088 label, except those that also contain the jump insn. */
3091 {
3092 /* Stop when we reach a loop that also contains the jump insn. */
3098 /* If we get here, we know we need to invalidate a loop. */
3105 }
3109 /* If this is not setting pc, ignore. */
3131 /* Strictly speaking this is not a jump into the loop, only a possible
3132 jump out of the loop. However, we have no way to link the destination
3133 of this jump onto the list of exit labels. To be safe we mark this
3134 loop and any containing loops as invalid. */
3136 {
3139 {
3145 }
3146 }
3148 }
3149 }
3150 \f
3151 /* Return nonzero if there is a label in the range from
3152 insn INSN to and including the insn whose luid is END
3153 INSN must have an assigned luid (i.e., it must not have
3154 been previously created by loop.c). */
3156 static int
3158 rtx insn;
3160 {
3162 {
3166 }
3169 }
3171 /* Record that a memory reference X is being set. */
3173 static void
3175 rtx x;
3176 rtx y ATTRIBUTE_UNUSED;
3178 {
3182 /* Count number of memory writes.
3183 This affects heuristics in strength_reduce. */
3184 num_mem_sets++;
3186 /* BLKmode MEM means all memory is clobbered. */
3188 {
3191 else
3195 }
3198 }
3200 /* X is a value modified by an INSN that references a biv inside a loop
3201 exit test (ie, X is somehow related to the value of the biv). If X
3202 is a pseudo that is used more than once, then the biv is (effectively)
3203 used more than once. DATA is really an `int *', and is set if the
3204 biv is used more than once. */
3206 static void
3208 rtx x;
3209 rtx y ATTRIBUTE_UNUSED;
3211 {
3224 /* If we do not have usage information, or if we know the register
3225 is used more than once, note that fact for check_dbra_loop. */
3230 }
3231 \f
3232 /* Return nonzero if the rtx X is invariant over the current loop.
3234 The value is 2 if we refer to something only conditionally invariant.
3236 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3237 Otherwise, a memory ref is invariant if it does not conflict with
3238 anything stored in `loop_store_mems'. */
3240 int
3243 {
3248 rtx mem_list_entry;
3254 {
3262 /* A LABEL_REF is normally invariant, however, if we are unrolling
3263 loops, and this label is inside the loop, then it isn't invariant.
3264 This is because each unrolled copy of the loop body will have
3265 a copy of this label. If this was invariant, then an insn loading
3266 the address of this label into a register might get moved outside
3267 the loop, and then each loop body would end up using the same label.
3269 We don't know the loop bounds here though, so just fail for all
3270 labels. */
3273 else
3282 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3283 since the reg might be set by initialization within the loop. */
3300 /* If we had a subroutine call, any location in memory could
3301 have been clobbered. We used to test here for volatile and
3302 readonly, but true_dependence knows how to do that better
3303 than we do. */
3308 /* See if there is any dependence between a store and this load. */
3311 {
3317 }
3319 /* It's not invalidated by a store in memory
3320 but we must still verify the address is invariant. */
3324 /* Don't mess with insns declared volatile. */
3331 }
3335 {
3337 {
3343 }
3345 {
3348 {
3354 }
3356 }
3357 }
3360 }
3362 \f
3363 /* Return nonzero if all the insns in the loop that set REG
3364 are INSN and the immediately following insns,
3365 and if each of those insns sets REG in an invariant way
3366 (not counting uses of REG in them).
3368 The value is 2 if some of these insns are only conditionally invariant.
3370 We assume that INSN itself is the first set of REG
3371 and that its source is invariant. */
3373 static int
3377 {
3380 rtx temp;
3381 /* Number of sets we have to insist on finding after INSN. */
3387 /* If N_SETS hit the limit, we can't rely on its value. */
3394 {
3396 rtx set;
3401 /* If library call, skip to end of it. */
3410 {
3415 {
3416 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3417 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3418 notes are OK. */
3424 }
3425 }
3427 count--;
3429 {
3432 }
3433 }
3436 /* If invariant_p ever returned 2, we return 2. */
3438 }
3440 #if 0
3441 /* I don't think this condition is sufficient to allow INSN
3442 to be moved, so we no longer test it. */
3444 /* Return 1 if all insns in the basic block of INSN and following INSN
3445 that set REG are invariant according to TABLE. */
3447 static int
3451 {
3456 {
3465 {
3468 }
3469 }
3470 }
3472 \f
3473 /* Look at all uses (not sets) of registers in X. For each, if it is
3474 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3475 a different insn, set USAGE[REGNO] to const0_rtx. */
3477 static void
3479 rtx insn;
3480 rtx x;
3481 varray_type usage;
3482 {
3494 {
3495 /* Don't count SET_DEST if it is a REG; otherwise count things
3496 in SET_DEST because if a register is partially modified, it won't
3497 show up as a potential movable so we don't care how USAGE is set
3498 for it. */
3502 }
3503 else
3505 {
3511 }
3512 }
3513 \f
3514 /* Count and record any set in X which is contained in INSN. Update
3515 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3517 static void
3520 varray_type may_not_move;
3522 {
3524 /* Don't move a reg that has an explicit clobber.
3525 It's not worth the pain to try to do it correctly. */
3529 {
3537 {
3539 /* If this is the first setting of this reg
3540 in current basic block, and it was set before,
3541 it must be set in two basic blocks, so it cannot
3542 be moved out of the loop. */
3546 /* If this is not first setting in current basic block,
3547 see if reg was used in between previous one and this.
3548 If so, neither one can be moved. */
3555 }
3556 }
3557 }
3559 /* Increment SET_IN_LOOP at the index of each register
3560 that is modified by an insn between FROM and TO.
3561 If the value of an element of SET_IN_LOOP becomes 127 or more,
3562 stop incrementing it, to avoid overflow.
3564 Store in SINGLE_USAGE[I] the single insn in which register I is
3565 used, if it is only used once. Otherwise, it is set to 0 (for no
3566 uses) or const0_rtx for more than one use. This parameter may be zero,
3567 in which case this processing is not done.
3569 Store in *COUNT_PTR the number of actual instruction
3570 in the loop. We use this to decide what is worth moving out. */
3572 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3573 In that case, it is the insn that last set reg n. */
3575 static void
3578 varray_type may_not_move;
3579 varray_type single_usage;
3582 {
3589 {
3591 {
3594 /* Record registers that have exactly one use. */
3597 /* Include uses in REG_EQUAL notes. */
3605 {
3610 }
3611 }
3615 }
3617 }
3618 \f
3619 /* Given a loop that is bounded by LOOP_START and LOOP_END
3620 and that is entered at SCAN_START,
3621 return 1 if the register set in SET contained in insn INSN is used by
3622 any insn that precedes INSN in cyclic order starting
3623 from the loop entry point.
3625 We don't want to use INSN_LUID here because if we restrict INSN to those
3626 that have a valid INSN_LUID, it means we cannot move an invariant out
3627 from an inner loop past two loops. */
3629 static int
3632 {
3634 rtx p;
3636 /* Scan forward checking for register usage. If we hit INSN, we
3637 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3639 {
3646 }
3649 }
3650 \f
3651 /* A "basic induction variable" or biv is a pseudo reg that is set
3652 (within this loop) only by incrementing or decrementing it. */
3653 /* A "general induction variable" or giv is a pseudo reg whose
3654 value is a linear function of a biv. */
3656 /* Bivs are recognized by `basic_induction_var';
3657 Givs by `general_induction_var'. */
3659 /* Indexed by register number, indicates whether or not register is an
3660 induction variable, and if so what type. */
3662 varray_type reg_iv_type;
3664 /* Indexed by register number, contains pointer to `struct induction'
3665 if register is an induction variable. This holds general info for
3666 all induction variables. */
3668 varray_type reg_iv_info;
3670 /* Indexed by register number, contains pointer to `struct iv_class'
3671 if register is a basic induction variable. This holds info describing
3672 the class (a related group) of induction variables that the biv belongs
3673 to. */
3677 /* The head of a list which links together (via the next field)
3678 every iv class for the current loop. */
3682 /* Givs made from biv increments are always splittable for loop unrolling.
3683 Since there is no regscan info for them, we have to keep track of them
3684 separately. */
3687 /* Communication with routines called via `note_stores'. */
3691 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3695 /* ??? Unfinished optimizations, and possible future optimizations,
3696 for the strength reduction code. */
3698 /* ??? The interaction of biv elimination, and recognition of 'constant'
3699 bivs, may cause problems. */
3701 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3702 performance problems.
3704 Perhaps don't eliminate things that can be combined with an addressing
3705 mode. Find all givs that have the same biv, mult_val, and add_val;
3706 then for each giv, check to see if its only use dies in a following
3707 memory address. If so, generate a new memory address and check to see
3708 if it is valid. If it is valid, then store the modified memory address,
3709 otherwise, mark the giv as not done so that it will get its own iv. */
3711 /* ??? Could try to optimize branches when it is known that a biv is always
3712 positive. */
3714 /* ??? When replace a biv in a compare insn, we should replace with closest
3715 giv so that an optimized branch can still be recognized by the combiner,
3716 e.g. the VAX acb insn. */
3718 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3719 was rerun in loop_optimize whenever a register was added or moved.
3720 Also, some of the optimizations could be a little less conservative. */
3721 \f
3722 /* Perform strength reduction and induction variable elimination.
3724 Pseudo registers created during this function will be beyond the last
3725 valid index in several tables including n_times_set and regno_last_uid.
3726 This does not cause a problem here, because the added registers cannot be
3727 givs outside of their loop, and hence will never be reconsidered.
3728 But scan_loop must check regnos to make sure they are in bounds.
3730 SCAN_START is the first instruction in the loop, as the loop would
3731 actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is
3732 the first instruction in the loop, as it is layed out in the
3733 instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG.
3734 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
3736 static void
3739 rtx scan_start;
3740 rtx end;
3741 rtx loop_top;
3743 rtx loop_start;
3744 rtx loop_end;
3746 rtx loop_cont;
3748 {
3749 rtx p;
3750 rtx set;
3751 rtx inc_val;
3752 rtx mult_val;
3753 rtx dest_reg;
3755 /* This is 1 if current insn is not executed at least once for every loop
3756 iteration. */
3758 /* This is 1 if current insn may be executed more than once for every
3759 loop iteration. */
3761 /* This is 1 if we have past a branch back to the top of the loop
3762 (aka a loop latch). */
3764 /* Temporary list pointers for traversing loop_iv_list. */
3766 /* Ratio of extra register life span we can justify
3767 for saving an instruction. More if loop doesn't call subroutines
3768 since in that case saving an insn makes more difference
3769 and more registers are available. */
3770 /* ??? could set this to last value of threshold in move_movables */
3772 /* Map of pseudo-register replacements. */
3776 rtx test;
3777 rtx end_insert_before;
3782 /* If scan_start points to the loop exit test, we have to be wary of
3783 subversive use of gotos inside expression statements. */
3797 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3798 must be put before this insn, so that they will appear in the right
3799 order (i.e. loop order).
3801 If loop_end is the end of the current function, then emit a
3802 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3803 dummy note insn. */
3806 else
3809 /* Scan through loop to find all possible bivs. */
3814 {
3818 {
3823 {
3827 {
3828 /* It is a possible basic induction variable.
3829 Create and initialize an induction structure for it. */
3837 }
3840 }
3841 }
3843 /* Past CODE_LABEL, we get to insns that may be executed multiple
3844 times. The only way we can be sure that they can't is if every
3845 jump insn between here and the end of the loop either
3846 returns, exits the loop, is a jump to a location that is still
3847 behind the label, or is a jump to the loop start. */
3850 {
3856 {
3861 {
3864 else
3868 }
3876 {
3879 }
3880 }
3881 }
3883 /* Past a jump, we get to insns for which we can't count
3884 on whether they will be executed during each iteration. */
3885 /* This code appears twice in strength_reduce. There is also similar
3886 code in scan_loop. */
3888 /* If we enter the loop in the middle, and scan around to the
3889 beginning, don't set not_every_iteration for that.
3890 This can be any kind of jump, since we want to know if insns
3891 will be executed if the loop is executed. */
3895 {
3898 /* If this is a jump outside the loop, then it also doesn't
3899 matter. Check to see if the target of this branch is on the
3900 loop_number_exits_labels list. */
3903 label;
3910 }
3913 {
3914 /* At the virtual top of a converted loop, insns are again known to
3915 be executed each iteration: logically, the loop begins here
3916 even though the exit code has been duplicated.
3918 Insns are also again known to be executed each iteration at
3919 the LOOP_CONT note. */
3925 loop_depth++;
3927 loop_depth--;
3928 }
3930 /* Note if we pass a loop latch. If we do, then we can not clear
3931 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3932 a loop since a jump before the last CODE_LABEL may have started
3933 a new loop iteration.
3935 Note that LOOP_TOP is only set for rotated loops and we need
3936 this check for all loops, so compare against the CODE_LABEL
3937 which immediately follows LOOP_START. */
3941 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3942 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3943 or not an insn is known to be executed each iteration of the
3944 loop, whether or not any iterations are known to occur.
3946 Therefore, if we have just passed a label and have no more labels
3947 between here and the test insn of the loop, and we have not passed
3948 a jump to the top of the loop, then we know these insns will be
3949 executed each iteration. */
3952 && ! past_loop_latch
3957 }
3959 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3960 Make a sanity check against n_times_set. */
3962 {
3964 /* Above happens if register modified by subreg, etc. */
3965 /* Make sure it is not recognized as a basic induction var: */
3967 /* If never incremented, it is invariant that we decided not to
3968 move. So leave it alone. */
3970 {
3981 }
3982 else
3983 {
3988 }
3989 }
3991 /* Exit if there are no bivs. */
3993 {
3994 /* Can still unroll the loop anyways, but indicate that there is no
3995 strength reduction info available. */
4001 }
4003 /* Find initial value for each biv by searching backwards from loop_start,
4004 halting at first label. Also record any test condition. */
4008 {
4018 /* Record any test of a biv that branches around the loop if no store
4019 between it and the start of loop. We only care about tests with
4020 constants and registers and only certain of those. */
4030 {
4031 /* If an NE test, we have an initial value! */
4033 {
4037 }
4038 else
4040 }
4041 }
4043 /* Look at the each biv and see if we can say anything better about its
4044 initial value from any initializing insns set up above. (This is done
4045 in two passes to avoid missing SETs in a PARALLEL.) */
4047 {
4048 rtx src;
4049 rtx note;
4054 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4055 is a constant, use the value of that. */
4061 else
4072 {
4076 {
4078 {
4081 }
4082 else
4083 {
4086 }
4087 }
4088 }
4089 else
4090 {
4094 /* Biv initial value is not a simple move. If it is the sum of
4095 another biv and a constant, check if both bivs are incremented
4096 in lockstep. Then we are actually looking at a giv.
4097 For simplicity, we only handle the case where there is but a
4098 single increment, and the register is not used elsewhere. */
4107 {
4113 }
4115 /* Now, can we transform this biv into a giv? */
4120 /* init_insn is only set to insns that are before loop_start
4121 without any intervening labels. */
4124 /* The register from BL2 must be set before the register from
4125 BL is set, or we must be able to move the latter set after
4126 the former set. Currently there can't be any labels
4127 in-between when biv_total_increment returns nonzero both times
4128 but we test it here in case some day some real cfg analysis
4129 gets used to set always_computable. */
4138 {
4147 /* Let this giv be discovered by the generic code. */
4150 /* We can get better optimization if we can move the giv setting
4151 before the first giv use. */
4155 dominator)
4158 {
4159 rtx p;
4160 rtx next;
4163 {
4169 #ifdef HAVE_cc0
4172 #endif
4174 }
4178 /* Avoid problems with luids by actually moving the insn
4179 and adjusting all luids in the range. */
4184 /* If the only purpose of the init insn is to initialize
4185 this giv, delete it. */
4189 }
4191 {
4198 }
4199 /* Remove this biv from the chain. */
4201 {
4202 /* We move the following giv from *bl->next into *bl.
4203 We have to update reg_biv_class for that moved biv
4204 to point to its new address. */
4207 }
4208 else
4209 {
4212 }
4213 }
4215 /* If we can't make it a giv,
4216 let biv keep initial value of "itself". */
4219 }
4220 }
4222 /* If a biv is unconditionally incremented several times in a row, convert
4223 all but the last increment into a giv. */
4225 /* Get an upper bound for the number of registers
4226 we might have after all bivs have been processed. */
4231 /* If the loop contains volatile memory references do not allow any
4232 replacements to take place, since this could loose the volatile markers. */
4234 {
4237 /* Reallocate reg_iv_type and reg_iv_info. */
4242 {
4246 /* The biv increments lists are in reverse order. Fix this first. */
4248 {
4252 }
4254 /* We must guard against the case that an early exit between v->insn
4255 and next->insn leaves the biv live after the loop, since that
4256 would mean that we'd be missing an increment for the final
4257 value. The following test to set biv_dead_after_loop is like
4258 the first part of the test to set bl->eliminable.
4259 We don't check here if we can calculate the final value, since
4260 this can't succeed if we already know that there is a jump
4261 between v->insn and next->insn, yet next->always_executed is
4262 set and next->maybe_multiple is cleared. Such a combination
4263 implies that the jump destination is outside the loop.
4264 If we want to make this check more sophisticated, we should
4265 check each branch between v->insn and next->insn individually
4266 to see if the biv is dead at its destination. */
4273 #ifdef HAVE_decrement_and_branch_until_zero
4275 #endif
4280 {
4281 HOST_WIDE_INT offset;
4293 || ! (biv_dead_after_loop
4295 {
4298 }
4305 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4306 have been allocated with some slop space, so we may not
4307 actually need to reallocate them. If we do, the following
4308 if statement will be executed just once in this loop. */
4310 {
4311 /* Grow all the remaining arrays. */
4316 }
4319 {
4322 }
4324 /* Here we can try to eliminate the increment by combining
4325 it into the uses. */
4327 /* Set last_use_insn so that we can check against it. */
4332 {
4336 {
4338 }
4339 }
4341 /* If we can't get the LUIDs for the insns, we can't
4342 calculate the lifetime. This is likely from unrolling
4343 of an inner loop, so there is little point in making this
4344 a DEST_REG giv anyways. */
4348 {
4349 /* Change the increment at NEXT back to what it was. */
4355 }
4389 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4390 it must be replaced. */
4395 /* Remove the increment from the list of biv increments,
4396 and record it as a giv. */
4405 /* Now replace the biv with DEST_REG in all insns between
4406 the replaced increment and the next increment, and
4407 remember the last insn that needed a replacement. */
4411 {
4412 rtx note;
4417 {
4421 }
4423 {
4427 }
4428 }
4432 /* If the lifetime is zero, it means that this register is really
4433 a dead store. So mark this as a giv that can be ignored.
4434 This will not prevent the biv from being eliminated. */
4442 }
4443 }
4444 }
4447 /* Search the loop for general induction variables. */
4449 /* A register is a giv if: it is only set once, it is a function of a
4450 biv and a constant (or invariant), and it is not a biv. */
4457 {
4459 /* At end of a straight-in loop, we are done.
4460 At end of a loop entered at the bottom, scan the top. */
4464 {
4467 else
4471 }
4473 /* Look for a general induction variable in a register. */
4478 {
4479 rtx src_reg;
4480 rtx add_val;
4481 rtx mult_val;
4484 rtx last_consec_insn;
4493 /* Equivalent expression is a giv. */
4498 /* Don't try to handle any regs made by loop optimization.
4499 We have nothing on them in regno_first_uid, etc. */
4501 /* Don't recognize a BASIC_INDUCT_VAR here. */
4503 /* This must be the only place where the register is set. */
4505 /* or all sets must be consecutive and make a giv. */
4510 {
4514 /* If this is a library call, increase benefit. */
4518 /* Skip the consecutive insns, if there are any. */
4526 }
4527 }
4529 #ifndef DONT_REDUCE_ADDR
4530 /* Look for givs which are memory addresses. */
4531 /* This resulted in worse code on a VAX 8600. I wonder if it
4532 still does. */
4536 #endif
4538 /* Update the status of whether giv can derive other givs. This can
4539 change when we pass a label or an insn that updates a biv. */
4544 /* Past CODE_LABEL, we get to insns that may be executed multiple
4545 times. The only way we can be sure that they can't is if every
4546 every jump insn between here and the end of the loop either
4547 returns, exits the loop, is a forward jump, or is a jump
4548 to the loop start. */
4551 {
4557 {
4562 {
4565 else
4569 }
4580 {
4583 }
4584 }
4585 }
4587 /* Past a jump, we get to insns for which we can't count
4588 on whether they will be executed during each iteration. */
4589 /* This code appears twice in strength_reduce. There is also similar
4590 code in scan_loop. */
4592 /* If we enter the loop in the middle, and scan around to the
4593 beginning, don't set not_every_iteration for that.
4594 This can be any kind of jump, since we want to know if insns
4595 will be executed if the loop is executed. */
4599 {
4602 /* If this is a jump outside the loop, then it also doesn't
4603 matter. Check to see if the target of this branch is on the
4604 loop_number_exits_labels list. */
4607 label;
4614 }
4617 {
4618 /* At the virtual top of a converted loop, insns are again known to
4619 be executed each iteration: logically, the loop begins here
4620 even though the exit code has been duplicated.
4622 Insns are also again known to be executed each iteration at
4623 the LOOP_CONT note. */
4629 loop_depth++;
4631 loop_depth--;
4632 }
4634 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4635 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4636 or not an insn is known to be executed each iteration of the
4637 loop, whether or not any iterations are known to occur.
4639 Therefore, if we have just passed a label and have no more labels
4640 between here and the test insn of the loop, we know these insns
4641 will be executed each iteration. */
4647 }
4649 /* Try to calculate and save the number of loop iterations. This is
4650 set to zero if the actual number can not be calculated. This must
4651 be called after all giv's have been identified, since otherwise it may
4652 fail if the iteration variable is a giv. */
4656 /* Now for each giv for which we still don't know whether or not it is
4657 replaceable, check to see if it is replaceable because its final value
4658 can be calculated. This must be done after loop_iterations is called,
4659 so that final_giv_value will work correctly. */
4662 {
4668 }
4670 /* Try to prove that the loop counter variable (if any) is always
4671 nonnegative; if so, record that fact with a REG_NONNEG note
4672 so that "decrement and branch until zero" insn can be used. */
4675 /* Create reg_map to hold substitutions for replaceable giv regs.
4676 Some givs might have been made from biv increments, so look at
4677 reg_iv_type for a suitable size. */
4682 /* Examine each iv class for feasibility of strength reduction/induction
4683 variable elimination. */
4686 {
4693 /* Test whether it will be possible to eliminate this biv
4694 provided all givs are reduced. This is possible if either
4695 the reg is not used outside the loop, or we can compute
4696 what its final value will be.
4698 For architectures with a decrement_and_branch_until_zero insn,
4699 don't do this if we put a REG_NONNEG note on the endtest for
4700 this biv. */
4702 /* Compare against bl->init_insn rather than loop_start.
4703 We aren't concerned with any uses of the biv between
4704 init_insn and loop_start since these won't be affected
4705 by the value of the biv elsewhere in the function, so
4706 long as init_insn doesn't use the biv itself.
4707 March 14, 1989 -- self@bayes.arc.nasa.gov */
4713 #ifdef HAVE_decrement_and_branch_until_zero
4715 #endif
4719 #ifdef HAVE_decrement_and_branch_until_zero
4721 #endif
4722 ))
4725 else
4726 {
4728 {
4736 }
4737 }
4739 /* Combine all giv's for this iv_class. */
4742 /* This will be true at the end, if all givs which depend on this
4743 biv have been strength reduced.
4744 We can't (currently) eliminate the biv unless this is so. */
4747 /* Check each giv in this class to see if we will benefit by reducing
4748 it. Skip giv's combined with others. */
4750 {
4758 /* Reduce benefit if not replaceable, since we will insert
4759 a move-insn to replace the insn that calculates this giv.
4760 Don't do this unless the giv is a user variable, since it
4761 will often be marked non-replaceable because of the duplication
4762 of the exit code outside the loop. In such a case, the copies
4763 we insert are dead and will be deleted. So they don't have
4764 a cost. Similar situations exist. */
4765 /* ??? The new final_[bg]iv_value code does a much better job
4766 of finding replaceable giv's, and hence this code may no longer
4767 be necessary. */
4772 /* Decrease the benefit to count the add-insns that we will
4773 insert to increment the reduced reg for the giv. */
4776 /* Decide whether to strength-reduce this giv or to leave the code
4777 unchanged (recompute it from the biv each time it is used).
4778 This decision can be made independently for each giv. */
4780 #ifdef AUTO_INC_DEC
4781 /* Attempt to guess whether autoincrement will handle some of the
4782 new add insns; if so, increase BENEFIT (undo the subtraction of
4783 add_cost that was done above). */
4786 {
4799 }
4800 #endif
4802 /* If an insn is not to be strength reduced, then set its ignore
4803 flag, and clear all_reduced. */
4805 /* A giv that depends on a reversed biv must be reduced if it is
4806 used after the loop exit, otherwise, it would have the wrong
4807 value after the loop exit. To make it simple, just reduce all
4808 of such giv's whether or not we know they are used after the loop
4809 exit. */
4813 {
4821 }
4822 else
4823 {
4824 /* Check that we can increment the reduced giv without a
4825 multiply insn. If not, reject it. */
4830 {
4838 }
4839 }
4840 }
4842 /* Check for givs whose first use is their definition and whose
4843 last use is the definition of another giv. If so, it is likely
4844 dead and should not be used to derive another giv nor to
4845 eliminate a biv. */
4847 {
4853 {
4859 }
4862 {
4868 }
4869 }
4871 /* Now that we know which givs will be reduced, try to rearrange the
4872 combinations to reduce register pressure.
4873 recombine_givs calls find_life_end, which needs reg_iv_type and
4874 reg_iv_info to be valid for all pseudos. We do the necessary
4875 reallocation here since it allows to check if there are still
4876 more bivs to process. */
4879 {
4880 /* If there are still more bivs to process, allocate some slack
4881 space so that we're not constantly reallocating these arrays. */
4884 /* Reallocate reg_iv_type and reg_iv_info. */
4887 }
4890 /* Reduce each giv that we decided to reduce. */
4893 {
4896 {
4899 /* If the code for derived givs immediately below has already
4900 allocated a new_reg, we must keep it. */
4905 {
4908 /* In case d->dest_reg is not replaceable, we have
4909 to replace it in v->insn now. */
4916 /* For each place where the biv is incremented, add an
4917 insn to set the new, reduced reg for the giv.
4918 We used to do this only for biv_count != 1, but
4919 this fails when there is a giv after a single biv
4920 increment, e.g. when the last giv was expressed as
4921 pre-decrement. */
4923 {
4924 /* We always emit reduced giv increments before the
4925 biv increment when bl->biv_count != 1. So by
4926 emitting the add insns for derived givs after the
4927 biv increment, they pick up the updated value of
4928 the reduced giv.
4929 If the reduced giv is processed with
4930 auto_inc_opt == 1, then it is incremented earlier
4931 than the biv, hence we'll still pick up the right
4932 value.
4933 If it's processed with auto_inc_opt == -1,
4934 that implies that the biv increment is before the
4935 first reduced giv's use. The derived giv's lifetime
4936 is after the reduced giv's lifetime, hence in this
4937 case, the biv increment doesn't matter. */
4939 }
4941 }
4943 #ifdef AUTO_INC_DEC
4944 /* If the target has auto-increment addressing modes, and
4945 this is an address giv, then try to put the increment
4946 immediately after its use, so that flow can create an
4947 auto-increment addressing mode. */
4950 /* We don't handle reversed biv's because bl->biv->insn
4951 does not have a valid INSN_LUID. */
4955 {
4956 /* If other giv's have been combined with this one, then
4957 this will work only if all uses of the other giv's occur
4958 before this giv's insn. This is difficult to check.
4960 We simplify this by looking for the common case where
4961 there is one DEST_REG giv, and this giv's insn is the
4962 last use of the dest_reg of that DEST_REG giv. If the
4963 increment occurs after the address giv, then we can
4964 perform the optimization. (Otherwise, the increment
4965 would have to go before other_giv, and we would not be
4966 able to combine it with the address giv to get an
4967 auto-inc address.) */
4969 {
4974 {
4977 else
4979 }
4986 }
4987 /* Check for case where increment is before the address
4988 giv. Do this test in "loop order". */
4997 else
5000 #ifdef HAVE_cc0
5001 {
5002 rtx prev;
5004 /* We can't put an insn immediately after one setting
5005 cc0, or immediately before one using cc0. */
5012 }
5013 #endif
5017 }
5018 #endif
5020 /* For each place where the biv is incremented, add an insn
5021 to increment the new, reduced reg for the giv. */
5023 {
5024 rtx insert_before;
5030 else
5037 /* A multiply is acceptable here
5038 since this is presumed to be seldom executed. */
5041 }
5043 /* Add code at loop start to initialize giv's reduced reg. */
5047 }
5048 }
5050 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5051 as not reduced.
5053 For each giv register that can be reduced now: if replaceable,
5054 substitute reduced reg wherever the old giv occurs;
5055 else add new move insn "giv_reg = reduced_reg". */
5058 {
5065 /* Update expression if this was combined, in case other giv was
5066 replaced. */
5072 /* Store reduced reg as the address in the memref where we found
5073 this giv. */
5076 {
5079 #if 0
5080 /* I can no longer duplicate the original problem. Perhaps
5081 this is unnecessary now? */
5083 /* Replaceable; it isn't strictly necessary to delete the old
5084 insn and emit a new one, because v->dest_reg is now dead.
5086 However, especially when unrolling loops, the special
5087 handling for (set REG0 REG1) in the second cse pass may
5088 make v->dest_reg live again. To avoid this problem, emit
5089 an insn to set the original giv reg from the reduced giv.
5090 We can not delete the original insn, since it may be part
5091 of a LIBCALL, and the code in flow that eliminates dead
5092 libcalls will fail if it is deleted. */
5095 #endif
5096 }
5097 else
5098 {
5099 /* Not replaceable; emit an insn to set the original giv reg from
5100 the reduced giv, same as above. */
5103 }
5105 /* When a loop is reversed, givs which depend on the reversed
5106 biv, and which are live outside the loop, must be set to their
5107 correct final value. This insn is only needed if the giv is
5108 not replaceable. The correct final value is the same as the
5109 value that the giv starts the reversed loop with. */
5114 {
5115 rtx insert_before;
5117 /* If the loop has multiple exits, emit the insn before the
5118 loop to ensure that it will always be executed no matter
5119 how the loop exits. Otherwise, emit the insn after the loop,
5120 since this is slightly more efficient. */
5123 else
5126 insert_before);
5128 #if 0
5129 /* If the insn to set the final value of the giv was emitted
5130 before the loop, then we must delete the insn inside the loop
5131 that sets it. If this is a LIBCALL, then we must delete
5132 every insn in the libcall. Note, however, that
5133 final_giv_value will only succeed when there are multiple
5134 exits if the giv is dead at each exit, hence it does not
5135 matter that the original insn remains because it is dead
5136 anyways. */
5137 /* Delete the insn inside the loop that sets the giv since
5138 the giv is now set before (or after) the loop. */
5140 #endif
5141 }
5144 {
5149 }
5150 }
5152 /* All the givs based on the biv bl have been reduced if they
5153 merit it. */
5155 /* For each giv not marked as maybe dead that has been combined with a
5156 second giv, clear any "maybe dead" mark on that second giv.
5157 v->new_reg will either be or refer to the register of the giv it
5158 combined with.
5160 Doing this clearing avoids problems in biv elimination where a
5161 giv's new_reg is a complex value that can't be put in the insn but
5162 the giv combined with (with a reg as new_reg) is marked maybe_dead.
5163 Since the register will be used in either case, we'd prefer it be
5164 used from the simpler giv. */
5170 /* Try to eliminate the biv, if it is a candidate.
5171 This won't work if ! all_reduced,
5172 since the givs we planned to use might not have been reduced.
5174 We have to be careful that we didn't initially think we could eliminate
5175 this biv because of a giv that we now think may be dead and shouldn't
5176 be used as a biv replacement.
5178 Also, there is the possibility that we may have a giv that looks
5179 like it can be used to eliminate a biv, but the resulting insn
5180 isn't valid. This can happen, for example, on the 88k, where a
5181 JUMP_INSN can compare a register only with zero. Attempts to
5182 replace it with a compare with a constant will fail.
5184 Note that in cases where this call fails, we may have replaced some
5185 of the occurrences of the biv with a giv, but no harm was done in
5186 doing so in the rare cases where it can occur. */
5192 {
5193 /* ?? If we created a new test to bypass the loop entirely,
5194 or otherwise drop straight in, based on this test, then
5195 we might want to rewrite it also. This way some later
5196 pass has more hope of removing the initialization of this
5197 biv entirely. */
5199 /* If final_value != 0, then the biv may be used after loop end
5200 and we must emit an insn to set it just in case.
5202 Reversed bivs already have an insn after the loop setting their
5203 value, so we don't need another one. We can't calculate the
5204 proper final value for such a biv here anyways. */
5206 {
5207 rtx insert_before;
5209 /* If the loop has multiple exits, emit the insn before the
5210 loop to ensure that it will always be executed no matter
5211 how the loop exits. Otherwise, emit the insn after the
5212 loop, since this is slightly more efficient. */
5215 else
5219 end_insert_before);
5220 }
5222 #if 0
5223 /* Delete all of the instructions inside the loop which set
5224 the biv, as they are all dead. If is safe to delete them,
5225 because an insn setting a biv will never be part of a libcall. */
5226 /* However, deleting them will invalidate the regno_last_uid info,
5227 so keeping them around is more convenient. Final_biv_value
5228 will only succeed when there are multiple exits if the biv
5229 is dead at each exit, hence it does not matter that the original
5230 insn remains, because it is dead anyways. */
5233 #endif
5238 }
5239 }
5241 /* Go through all the instructions in the loop, making all the
5242 register substitutions scheduled in REG_MAP. */
5247 {
5251 }
5254 {
5255 /* When we completely unroll a loop we will likely not need the increment
5256 of the loop BIV and we will not need the conditional branch at the
5257 end of the loop. */
5260 #ifdef HAVE_cc0
5261 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5262 need the comparison before the conditional branch at the end of the
5263 loop. */
5265 #endif
5267 /* We'll need one copy for each loop iteration. */
5270 /* A little slop to account for the ability to remove initialization
5271 code, better CSE, and other secondary benefits of completely
5272 unrolling some loops. */
5275 /* Clamp the value. */
5278 }
5280 /* Unroll loops from within strength reduction so that we can use the
5281 induction variable information that strength_reduce has already
5282 collected. Always unroll loops that would be as small or smaller
5283 unrolled than when rolled. */
5290 #ifdef HAVE_decrement_and_branch_on_count
5291 /* Instrument the loop with BCT insn. */
5300 egress:
5303 }
5304 \f
5305 /* Return 1 if X is a valid source for an initial value (or as value being
5306 compared against in an initial test).
5308 X must be either a register or constant and must not be clobbered between
5309 the current insn and the start of the loop.
5311 INSN is the insn containing X. */
5313 static int
5315 rtx x;
5316 rtx insn;
5318 rtx loop_start;
5319 {
5323 /* Only consider pseudos we know about initialized in insns whose luids
5324 we know. */
5329 /* Don't use call-clobbered registers across a call which clobbers it. On
5330 some machines, don't use any hard registers at all. */
5332 && (SMALL_REGISTER_CLASSES
5336 /* Don't use registers that have been clobbered before the start of the
5337 loop. */
5342 }
5343 \f
5344 /* Scan X for memory refs and check each memory address
5345 as a possible giv. INSN is the insn whose pattern X comes from.
5346 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5347 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5348 more thanonce in each loop iteration. */
5350 static void
5352 loop_end)
5353 rtx x;
5354 rtx insn;
5357 {
5367 {
5383 {
5384 rtx src_reg;
5385 rtx add_val;
5386 rtx mult_val;
5389 /* This code used to disable creating GIVs with mult_val == 1 and
5390 add_val == 0. However, this leads to lost optimizations when
5391 it comes time to combine a set of related DEST_ADDR GIVs, since
5392 this one would not be seen. */
5396 {
5397 /* Found one; record it. */
5406 }
5407 }
5412 }
5414 /* Recursively scan the subexpressions for other mem refs. */
5425 }
5426 \f
5427 /* Fill in the data about one biv update.
5428 V is the `struct induction' in which we record the biv. (It is
5429 allocated by the caller, with alloca.)
5430 INSN is the insn that sets it.
5431 DEST_REG is the biv's reg.
5433 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5434 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5435 being set to INC_VAL.
5437 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5438 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5439 can be executed more than once per iteration. If MAYBE_MULTIPLE
5440 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5441 executed exactly once per iteration. */
5443 static void
5447 rtx insn;
5448 rtx dest_reg;
5449 rtx inc_val;
5450 rtx mult_val;
5454 {
5468 /* Add this to the reg's iv_class, creating a class
5469 if this is the first incrementation of the reg. */
5473 {
5474 /* Create and initialize new iv_class. */
5484 /* Set initial value to the reg itself. */
5486 /* We haven't seen the initializing insn yet */
5496 /* Add this class to loop_iv_list. */
5500 /* Put it in the array of biv register classes. */
5502 }
5504 /* Update IV_CLASS entry for this biv. */
5512 {
5517 {
5521 }
5522 else
5523 {
5527 }
5528 }
5529 }
5530 \f
5531 /* Fill in the data about one giv.
5532 V is the `struct induction' in which we record the giv. (It is
5533 allocated by the caller, with alloca.)
5534 INSN is the insn that sets it.
5535 BENEFIT estimates the savings from deleting this insn.
5536 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5537 into a register or is used as a memory address.
5539 SRC_REG is the biv reg which the giv is computed from.
5540 DEST_REG is the giv's reg (if the giv is stored in a reg).
5541 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5542 LOCATION points to the place where this giv's value appears in INSN. */
5544 static void
5547 loop_end)
5549 rtx insn;
5550 rtx src_reg;
5551 rtx dest_reg;
5558 {
5587 /* The v->always_computable field is used in update_giv_derive, to
5588 determine whether a giv can be used to derive another giv. For a
5589 DEST_REG giv, INSN computes a new value for the giv, so its value
5590 isn't computable if INSN insn't executed every iteration.
5591 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5592 it does not compute a new value. Hence the value is always computable
5593 regardless of whether INSN is executed each iteration. */
5597 else
5603 {
5606 }
5608 {
5614 /* If the lifetime is zero, it means that this register is
5615 really a dead store. So mark this as a giv that can be
5616 ignored. This will not prevent the biv from being eliminated. */
5622 }
5624 /* Add the giv to the class of givs computed from one biv. */
5628 {
5631 /* Don't count DEST_ADDR. This is supposed to count the number of
5632 insns that calculate givs. */
5636 }
5637 else
5638 /* Fatal error, biv missing for this giv? */
5643 else
5644 {
5645 /* The giv can be replaced outright by the reduced register only if all
5646 of the following conditions are true:
5647 - the insn that sets the giv is always executed on any iteration
5648 on which the giv is used at all
5649 (there are two ways to deduce this:
5650 either the insn is executed on every iteration,
5651 or all uses follow that insn in the same basic block),
5652 - the giv is not used outside the loop
5653 - no assignments to the biv occur during the giv's lifetime. */
5656 /* Previous line always fails if INSN was moved by loop opt. */
5658 && (! not_every_iteration
5660 {
5661 /* Now check that there are no assignments to the biv within the
5662 giv's lifetime. This requires two separate checks. */
5664 /* Check each biv update, and fail if any are between the first
5665 and last use of the giv.
5667 If this loop contains an inner loop that was unrolled, then
5668 the insn modifying the biv may have been emitted by the loop
5669 unrolling code, and hence does not have a valid luid. Just
5670 mark the biv as not replaceable in this case. It is not very
5671 useful as a biv, because it is used in two different loops.
5672 It is very unlikely that we would be able to optimize the giv
5673 using this biv anyways. */
5677 {
5683 {
5687 }
5688 }
5690 /* If there are any backwards branches that go from after the
5691 biv update to before it, then this giv is not replaceable. */
5695 {
5699 }
5700 }
5701 else
5702 {
5703 /* May still be replaceable, we don't have enough info here to
5704 decide. */
5707 }
5708 }
5710 /* Record whether the add_val contains a const_int, for later use by
5711 combine_givs. */
5712 {
5717 ;
5721 {
5723 {
5728 else
5730 }
5733 }
5734 }
5737 {
5741 else
5757 {
5760 }
5761 else
5762 {
5765 }
5768 {
5771 }
5772 else
5773 {
5776 }
5777 }
5782 }
5785 /* All this does is determine whether a giv can be made replaceable because
5786 its final value can be calculated. This code can not be part of record_giv
5787 above, because final_giv_value requires that the number of loop iterations
5788 be known, and that can not be accurately calculated until after all givs
5789 have been identified. */
5791 static void
5796 {
5802 /* DEST_ADDR givs will never reach here, because they are always marked
5803 replaceable above in record_giv. */
5805 /* The giv can be replaced outright by the reduced register only if all
5806 of the following conditions are true:
5807 - the insn that sets the giv is always executed on any iteration
5808 on which the giv is used at all
5809 (there are two ways to deduce this:
5810 either the insn is executed on every iteration,
5811 or all uses follow that insn in the same basic block),
5812 - its final value can be calculated (this condition is different
5813 than the one above in record_giv)
5814 - no assignments to the biv occur during the giv's lifetime. */
5816 #if 0
5817 /* This is only called now when replaceable is known to be false. */
5818 /* Clear replaceable, so that it won't confuse final_giv_value. */
5820 #endif
5824 {
5827 rtx last_giv_use;
5831 /* When trying to determine whether or not a biv increment occurs
5832 during the lifetime of the giv, we can ignore uses of the variable
5833 outside the loop because final_value is true. Hence we can not
5834 use regno_last_uid and regno_first_uid as above in record_giv. */
5836 /* Search the loop to determine whether any assignments to the
5837 biv occur during the giv's lifetime. Start with the insn
5838 that sets the giv, and search around the loop until we come
5839 back to that insn again.
5841 Also fail if there is a jump within the giv's lifetime that jumps
5842 to somewhere outside the lifetime but still within the loop. This
5843 catches spaghetti code where the execution order is not linear, and
5844 hence the above test fails. Here we assume that the giv lifetime
5845 does not extend from one iteration of the loop to the next, so as
5846 to make the test easier. Since the lifetime isn't known yet,
5847 this requires two loops. See also record_giv above. */
5852 {
5861 {
5863 {
5865 {
5869 }
5870 }
5875 }
5876 }
5878 /* Now that the lifetime of the giv is known, check for branches
5879 from within the lifetime to outside the lifetime if it is still
5880 replaceable. */
5883 {
5886 {
5899 {
5908 }
5909 }
5910 }
5912 /* If it is replaceable, then save the final value. */
5915 }
5920 }
5921 \f
5922 /* Update the status of whether a giv can derive other givs.
5924 We need to do something special if there is or may be an update to the biv
5925 between the time the giv is defined and the time it is used to derive
5926 another giv.
5928 In addition, a giv that is only conditionally set is not allowed to
5929 derive another giv once a label has been passed.
5931 The cases we look at are when a label or an update to a biv is passed. */
5933 static void
5935 rtx p;
5936 {
5939 rtx tem;
5942 /* Search all IV classes, then all bivs, and finally all givs.
5944 There are three cases we are concerned with. First we have the situation
5945 of a giv that is only updated conditionally. In that case, it may not
5946 derive any givs after a label is passed.
5948 The second case is when a biv update occurs, or may occur, after the
5949 definition of a giv. For certain biv updates (see below) that are
5950 known to occur between the giv definition and use, we can adjust the
5951 giv definition. For others, or when the biv update is conditional,
5952 we must prevent the giv from deriving any other givs. There are two
5953 sub-cases within this case.
5955 If this is a label, we are concerned with any biv update that is done
5956 conditionally, since it may be done after the giv is defined followed by
5957 a branch here (actually, we need to pass both a jump and a label, but
5958 this extra tracking doesn't seem worth it).
5960 If this is a jump, we are concerned about any biv update that may be
5961 executed multiple times. We are actually only concerned about
5962 backward jumps, but it is probably not worth performing the test
5963 on the jump again here.
5965 If this is a biv update, we must adjust the giv status to show that a
5966 subsequent biv update was performed. If this adjustment cannot be done,
5967 the giv cannot derive further givs. */
5973 {
5975 {
5976 /* If cant_derive is already true, there is no point in
5977 checking all of these conditions again. */
5981 /* If this giv is conditionally set and we have passed a label,
5982 it cannot derive anything. */
5986 /* Skip givs that have mult_val == 0, since
5987 they are really invariants. Also skip those that are
5988 replaceable, since we know their lifetime doesn't contain
5989 any biv update. */
5993 /* The only way we can allow this giv to derive another
5994 is if this is a biv increment and we can form the product
5995 of biv->add_val and giv->mult_val. In this case, we will
5996 be able to compute a compensation. */
5998 {
6008 tem = simplify_giv_expr
6014 else
6016 }
6020 }
6021 }
6022 }
6023 \f
6024 /* Check whether an insn is an increment legitimate for a basic induction var.
6025 X is the source of insn P, or a part of it.
6026 MODE is the mode in which X should be interpreted.
6028 DEST_REG is the putative biv, also the destination of the insn.
6029 We accept patterns of these forms:
6030 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6031 REG = INVARIANT + REG
6033 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6034 store the additive term into *INC_VAL, and store the place where
6035 we found the additive term into *LOCATION.
6037 If X is an assignment of an invariant into DEST_REG, we set
6038 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6040 We also want to detect a BIV when it corresponds to a variable
6041 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6042 of the variable may be a PLUS that adds a SUBREG of that variable to
6043 an invariant and then sign- or zero-extends the result of the PLUS
6044 into the variable.
6046 Most GIVs in such cases will be in the promoted mode, since that is the
6047 probably the natural computation mode (and almost certainly the mode
6048 used for addresses) on the machine. So we view the pseudo-reg containing
6049 the variable as the BIV, as if it were simply incremented.
6051 Note that treating the entire pseudo as a BIV will result in making
6052 simple increments to any GIVs based on it. However, if the variable
6053 overflows in its declared mode but not its promoted mode, the result will
6054 be incorrect. This is acceptable if the variable is signed, since
6055 overflows in such cases are undefined, but not if it is unsigned, since
6056 those overflows are defined. So we only check for SIGN_EXTEND and
6057 not ZERO_EXTEND.
6059 If we cannot find a biv, we return 0. */
6061 static int
6065 rtx p;
6066 rtx dest_reg;
6070 {
6078 {
6084 {
6086 }
6091 {
6093 }
6094 else
6107 /* If this is a SUBREG for a promoted variable, check the inner
6108 value. */
6115 /* If this register is assigned in a previous insn, look at its
6116 source, but don't go outside the loop or past a label. */
6120 {
6146 }
6147 /* ... fall through ... */
6149 /* Can accept constant setting of biv only when inside inner most loop.
6150 Otherwise, a biv of an inner loop may be incorrectly recognized
6151 as a biv of the outer loop,
6152 causing code to be moved INTO the inner loop. */
6159 /* convert_modes aborts if we try to convert to or from CCmode, so just
6160 exclude that case. It is very unlikely that a condition code value
6161 would be a useful iterator anyways. */
6165 {
6166 /* Possible bug here? Perhaps we don't know the mode of X. */
6170 }
6171 else
6179 /* Similar, since this can be a sign extension. */
6184 ;
6197 location);
6202 }
6203 }
6204 \f
6205 /* A general induction variable (giv) is any quantity that is a linear
6206 function of a basic induction variable,
6207 i.e. giv = biv * mult_val + add_val.
6208 The coefficients can be any loop invariant quantity.
6209 A giv need not be computed directly from the biv;
6210 it can be computed by way of other givs. */
6212 /* Determine whether X computes a giv.
6213 If it does, return a nonzero value
6214 which is the benefit from eliminating the computation of X;
6215 set *SRC_REG to the register of the biv that it is computed from;
6216 set *ADD_VAL and *MULT_VAL to the coefficients,
6217 such that the value of X is biv * mult + add; */
6219 static int
6221 rtx x;
6227 {
6231 /* If this is an invariant, forget it, it isn't a giv. */
6235 /* See if the expression could be a giv and get its form.
6236 Mark our place on the obstack in case we don't find a giv. */
6241 {
6244 }
6247 {
6250 /* Since this is now an invariant and wasn't before, it must be a giv
6251 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6252 with. */
6259 /* This is equivalent to a BIV. */
6266 /* Either (plus (biv) (invar)) or
6267 (plus (mult (biv) (invar_1)) (invar_2)). */
6269 {
6272 }
6273 else
6274 {
6277 }
6282 /* ADD_VAL is zero. */
6290 }
6292 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6293 unless they are CONST_INT). */
6300 {
6301 #ifdef ADDRESS_COST
6303 #else
6305 #endif
6306 }
6307 else
6310 /* Always return true if this is a giv so it will be detected as such,
6311 even if the benefit is zero or negative. This allows elimination
6312 of bivs that might otherwise not be eliminated. */
6314 }
6315 \f
6316 /* Given an expression, X, try to form it as a linear function of a biv.
6317 We will canonicalize it to be of the form
6318 (plus (mult (BIV) (invar_1))
6319 (invar_2))
6320 with possible degeneracies.
6322 The invariant expressions must each be of a form that can be used as a
6323 machine operand. We surround then with a USE rtx (a hack, but localized
6324 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6325 routine; it is the caller's responsibility to strip them.
6327 If no such canonicalization is possible (i.e., two biv's are used or an
6328 expression that is neither invariant nor a biv or giv), this routine
6329 returns 0.
6331 For a non-zero return, the result will have a code of CONST_INT, USE,
6332 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6334 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6341 static rtx
6343 rtx x;
6345 {
6348 rtx tem;
6350 /* If this is not an integer mode, or if we cannot do arithmetic in this
6351 mode, this can't be a giv. */
6358 {
6365 /* Put constant last, CONST_INT last if both constant. */
6373 /* Handle addition of zero, then addition of an invariant. */
6378 {
6381 /* Adding two invariants must result in an invariant, so enclose
6382 addition operation inside a USE and return it. */
6392 else
6401 /* biv + invar or mult + invar. Return sum. */
6405 /* (a + invar_1) + invar_2. Associate. */
6406 return
6411 arg1)),
6412 benefit);
6416 }
6418 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6419 MULT to reduce cases. */
6425 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6426 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6427 Recurse to associate the second PLUS. */
6432 return
6437 benefit);
6439 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6451 benefit);
6454 /* Handle "a - b" as "a + b * (-1)". */
6459 constm1_rtx)),
6460 benefit);
6468 /* Put constant last, CONST_INT last if both constant. */
6473 /* If second argument is not now constant, not giv. */
6477 /* Handle multiply by 0 or 1. */
6485 {
6487 /* biv * invar. Done. */
6491 /* Product of two constants. */
6495 /* invar * invar. It is a giv, but very few of these will
6496 actually pay off, so limit to simple registers. */
6506 {
6510 }
6511 else
6516 /* (a * invar_1) * invar_2. Associate. */
6521 arg1)),
6522 benefit);
6525 /* (a + invar_1) * invar_2. Distribute. */
6529 arg1),
6532 arg1)),
6533 benefit);
6537 }
6540 /* Shift by constant is multiply by power of two. */
6544 return
6549 benefit);
6552 /* "-a" is "a * (-1)" */
6554 benefit);
6557 /* "~a" is "-a - 1". Silly, but easy. */
6560 const1_rtx),
6561 benefit);
6564 /* Already in proper form for invariant. */
6568 /* If this is a new register, we can't deal with it. */
6572 /* Check for biv or giv. */
6574 {
6578 {
6581 /* Form expression from giv and add benefit. Ensure this giv
6582 can derive another and subtract any needed adjustment if so. */
6594 }
6597 /* If it isn't an induction variable, and it is invariant, we
6598 may be able to simplify things further by looking through
6599 the bits we just moved outside the loop. */
6601 {
6606 {
6607 /* Ok, we found a match. Substitute and simplify. */
6609 /* If we match another movable, we must use that, as
6610 this one is going away. */
6614 /* If consec is non-zero, this is a member of a group of
6615 instructions that were moved together. We handle this
6616 case only to the point of seeking to the last insn and
6617 looking for a REG_EQUAL. Fail if we don't find one. */
6619 {
6627 }
6628 else
6629 {
6633 }
6636 {
6637 /* What we are most interested in is pointer
6638 arithmetic on invariants -- only take
6639 patterns we may be able to do something with. */
6645 {
6649 }
6654 {
6658 }
6659 }
6661 }
6662 }
6664 }
6666 /* Fall through to general case. */
6668 /* If invariant, return as USE (unless CONST_INT).
6669 Otherwise, not giv. */
6674 {
6683 }
6684 else
6686 }
6687 }
6689 /* This routine folds invariants such that there is only ever one
6690 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6692 static rtx
6695 {
6701 {
6704 }
6707 {
6710 }
6711 else
6712 {
6715 }
6716 }
6718 static rtx
6722 {
6724 {
6728 else
6731 }
6734 else
6737 }
6738 \f
6739 /* Help detect a giv that is calculated by several consecutive insns;
6740 for example,
6741 giv = biv * M
6742 giv = giv + A
6743 The caller has already identified the first insn P as having a giv as dest;
6744 we check that all other insns that set the same register follow
6745 immediately after P, that they alter nothing else,
6746 and that the result of the last is still a giv.
6748 The value is 0 if the reg set in P is not really a giv.
6749 Otherwise, the value is the amount gained by eliminating
6750 all the consecutive insns that compute the value.
6752 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6753 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6755 The coefficients of the ultimate giv value are stored in
6756 *MULT_VAL and *ADD_VAL. */
6758 static int
6762 rtx p;
6763 rtx src_reg;
6764 rtx dest_reg;
6768 {
6772 rtx temp;
6773 rtx set;
6775 /* Indicate that this is a giv so that we can update the value produced in
6776 each insn of the multi-insn sequence.
6778 This induction structure will be used only by the call to
6779 general_induction_var below, so we can allocate it on our stack.
6780 If this is a giv, our caller will replace the induct var entry with
6781 a new induction structure. */
6797 {
6801 /* If libcall, skip to end of call sequence. */
6811 /* Giv created by equivalent expression. */
6816 {
6820 count--;
6824 }
6826 {
6827 /* Allow insns that set something other than this giv to a
6828 constant. Such insns are needed on machines which cannot
6829 include long constants and should not disqualify a giv. */
6838 }
6839 }
6843 }
6844 \f
6845 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6846 represented by G1. If no such expression can be found, or it is clear that
6847 it cannot possibly be a valid address, 0 is returned.
6849 To perform the computation, we note that
6850 G1 = x * v + a and
6851 G2 = y * v + b
6852 where `v' is the biv.
6854 So G2 = (y/b) * G1 + (b - a*y/x).
6856 Note that MULT = y/x.
6858 Update: A and B are now allowed to be additive expressions such that
6859 B contains all variables in A. That is, computing B-A will not require
6860 subtracting variables. */
6862 static rtx
6865 {
6866 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6871 /* If MULT is not 1, we cannot handle A with non-constants, since we
6872 would then be required to subtract multiples of the registers in A.
6873 This is theoretically possible, and may even apply to some Fortran
6874 constructs, but it is a lot of work and we do not attempt it here. */
6879 /* In general these structures are sorted top to bottom (down the PLUS
6880 chain), but not left to right across the PLUS. If B is a higher
6881 order giv than A, we can strip one level and recurse. If A is higher
6882 order, we'll eventually bail out, but won't know that until the end.
6883 If they are the same, we'll strip one level around this loop. */
6886 {
6898 /* We matched: remove one reg completely. */
6901 /* An alternate match. */
6904 /* An alternate match. */
6906 else
6907 {
6908 /* Indicates an extra register in B. Strip one level from B and
6909 recurse, hoping B was the higher order expression. */
6914 }
6915 }
6917 /* Here we are at the last level of A, go through the cases hoping to
6918 get rid of everything but a constant. */
6921 {
6934 }
6936 {
6938 }
6940 {
6945 else
6947 }
6952 }
6954 rtx
6957 {
6960 /* The value that G1 will be multiplied by must be a constant integer. Also,
6961 the only chance we have of getting a valid address is if b*c/a (see above
6962 for notation) is also an integer. */
6965 {
6970 }
6973 else
6974 {
6975 /* ??? Find out if the one is a multiple of the other? */
6977 }
6981 {
6982 /* Failed. If we've got a multiplication factor between G1 and G2,
6983 scale G1's addend and try again. */
6985 {
6989 {
6990 HOST_WIDE_INT m;
6994 }
6995 else
6996 {
6998 mult);
6999 }
7002 }
7003 }
7007 /* Form simplified final result. */
7012 else
7017 else
7018 {
7021 {
7025 }
7028 }
7030 }
7031 \f
7032 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7033 represented by G1. This indicates that G2 should be combined with G1 and
7034 that G2 can use (either directly or via an address expression) a register
7035 used to represent G1. */
7037 static rtx
7040 {
7043 /* If these givs are identical, they can be combined. We use the results
7044 of express_from because the addends are not in a canonical form, so
7045 rtx_equal_p is a weaker test. */
7046 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7047 combination to be the other way round. */
7050 {
7052 }
7054 /* If G2 can be expressed as a function of G1 and that function is valid
7055 as an address and no more expensive than using a register for G2,
7056 the expression of G2 in terms of G1 can be used. */
7060 /* ??? Looses, especially with -fforce-addr, where *g2->location
7061 will always be a register, and so anything more complicated
7062 gets discarded. */
7063 #if 0
7064 #ifdef ADDRESS_COST
7066 #else
7068 #endif
7069 #endif
7070 )
7071 {
7073 }
7076 }
7077 \f
7078 struct combine_givs_stats
7079 {
7082 };
7084 static int
7088 {
7095 /* Stabilize the sort. */
7099 }
7101 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7102 any other. If so, point SAME to the giv combined with and set NEW_REG to
7103 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7104 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7106 static void
7109 {
7110 /* Additional benefit to add for being combined multiple times. */
7118 /* Count givs, because bl->giv_count is incorrect here. */
7122 giv_count++;
7124 giv_array
7135 {
7137 rtx single_use;
7142 /* If a DEST_REG GIV is used only once, do not allow it to combine
7143 with anything, for in doing so we will gain nothing that cannot
7144 be had by simply letting the GIV with which we would have combined
7145 to be reduced on its own. The losage shows up in particular with
7146 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7147 be seen elsewhere as well. */
7154 /* Add an additional weight for zero addends. */
7159 {
7160 rtx this_combine;
7165 {
7168 }
7169 }
7171 }
7173 /* Iterate, combining until we can't. */
7174 restart:
7178 {
7181 {
7187 }
7189 }
7192 {
7198 /* If it has already been combined, skip. */
7203 {
7206 /* If it has already been combined, skip. */
7208 {
7218 /* ??? The new final_[bg]iv_value code does a much better job
7219 of finding replaceable giv's, and hence this code may no
7220 longer be necessary. */
7224 /* To help optimize the next set of combinations, remove
7225 this giv from the benefits of other potential mates. */
7227 {
7231 }
7237 }
7238 }
7240 /* To help optimize the next set of combinations, remove
7241 this giv from the benefits of other potential mates. */
7243 {
7245 {
7249 }
7253 /* We've finished with this giv, and everything it touched.
7254 Restart the combination so that proper weights for the
7255 rest of the givs are properly taken into account. */
7256 /* ??? Ideally we would compact the arrays at this point, so
7257 as to not cover old ground. But sanely compacting
7258 can_combine is tricky. */
7260 }
7261 }
7263 /* Clean up. */
7266 }
7267 \f
7268 struct recombine_givs_stats
7269 {
7272 };
7274 /* Used below as comparison function for qsort. We want a ascending luid
7275 when scanning the array starting at the end, thus the arguments are
7276 used in reverse. */
7277 static int
7281 {
7288 /* Stabilize the sort. */
7292 }
7294 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7295 look for the start of life of a giv where the start has not been seen
7296 yet to unlock the search for the end of its life.
7297 Only consider givs that belong to BIV.
7298 Return the total number of lifetime ends that have been found. */
7299 static int
7303 {
7311 {
7313 {
7316 {
7324 {
7325 /* If we see a 0 here for end_luid, it means that we have
7326 scanned the entire loop without finding any use at all.
7327 We must not predicate this code on a start_luid match
7328 since that would make the test fail for givs that have
7329 been hoisted out of inner loops. */
7331 {
7334 }
7337 }
7339 }
7341 }
7343 {
7351 {
7356 }
7358 }
7366 }
7370 {
7377 }
7379 }
7381 /* For each giv that has been combined with another, look if
7382 we can combine it with the most recently used one instead.
7383 This tends to shorten giv lifetimes, and helps the next step:
7384 try to derive givs from other givs. */
7385 static void
7390 {
7398 {
7400 giv_count++;
7401 }
7402 giv_array
7406 /* Initialize stats and set up the ix field for each giv in stats to name
7407 the corresponding index into stats. */
7409 {
7410 rtx p;
7416 /* If this giv has been hoisted out of an inner loop, use the luid of
7417 the previous insn. */
7421 i++;
7422 }
7426 /* Set up the ix field for each giv in stats to name
7427 the corresponding index into stats, and
7428 do the actual most-recently-used recombination. */
7430 {
7434 {
7436 rtx new_combine;
7438 /* combine_givs_p actually says if we can make this transformation.
7439 The other tests are here only to avoid keeping a giv alive
7440 that could otherwise be eliminated. */
7446 {
7451 /* No need to update lifetimes / benefits here since we have
7452 already decided what to reduce. */
7455 {
7461 }
7463 }
7465 }
7473 }
7476 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7477 lifetime ends from regscan info. */
7479 {
7484 {
7485 /* Loop unrolling of an inner loop can even create new DEST_REG
7486 givs. */
7487 rtx p;
7493 }
7495 {
7497 {
7500 }
7502 {
7503 rtx p;
7504 /* This insn has been created by loop optimization on an inner
7505 loop. We don't have a proper start_luid that will match
7506 when we see the first set. But we do know that there will
7507 be no use before the set, so we can set end_luid to 0 so that
7508 we'll start looking for the last use right away. */
7513 ends_need_computing++;
7514 }
7515 else
7516 {
7521 /* Find the first insn that sets the giv, so that we can verify
7522 if this giv's lifetime wraps around the loop. We also need
7523 the luid of the first setting insn in order to detect the
7524 last use properly. */
7526 {
7529 count--;
7530 }
7534 {
7536 ends_need_computing++;
7537 }
7538 else
7539 {
7542 {
7544 ends_need_computing++;
7545 }
7546 }
7547 }
7548 }
7549 }
7551 /* If the regscan information was unconclusive for one or more DEST_REG
7552 givs, scan the all insn in the loop to find out lifetime ends. */
7554 {
7558 do
7559 {
7566 }
7568 }
7570 /* Set start_luid back to the last insn that sets the giv. This allows
7571 more combinations. */
7573 {
7579 }
7581 /* Now adjust lifetime ends by taking combined givs into account. */
7583 {
7591 {
7594 /* Use unsigned arithmetic to model loop wrap-around. */
7598 }
7599 }
7603 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7604 same mult_val and non-overlapping lifetime. This reduces register
7605 pressure.
7606 Once we find a DEST_REG giv that is suitable to derive others from,
7607 we set last_giv to this giv, and try to derive as many other DEST_REG
7608 givs from it without joining overlapping lifetimes. If we then
7609 encounter a DEST_REG giv that we can't derive, we set rescan to the
7610 index for this giv (unless rescan is already set).
7611 When we are finished with the current LAST_GIV (i.e. the inner loop
7612 terminates), we start again with rescan, which then becomes the new
7613 LAST_GIV. */
7615 {
7619 {
7620 rtx sum;
7626 {
7627 /* Don't use a giv that's likely to be dead to derive
7628 others - that would be likely to keep that giv alive. */
7630 {
7634 }
7636 }
7637 /* Use unsigned arithmetic to model loop wrap around. */
7642 /* Check that the giv insn we're about to use for deriving
7643 precedes all uses of that giv. Note that initializing the
7644 derived giv would defeat the purpose of reducing register
7645 pressure.
7646 ??? We could arrange to move the insn. */
7650 /* ??? Could handle libcalls, but would need more logic. */
7652 /* We would really like to know if for any giv that v
7653 is combined with, v->insn or any intervening biv increment
7654 dominates that combined giv. However, we
7655 don't have this detailed control flow information.
7656 N.B. since last_giv will be reduced, it is valid
7657 anywhere in the loop, so we don't need to check the
7658 validity of last_giv.
7659 We rely here on the fact that v->always_executed implies that
7660 there is no jump to someplace else in the loop before the
7661 giv insn, and hence any insn that is executed before the
7662 giv insn in the loop will have a lower luid. */
7665 /* Make sure we don't make the add more expensive. ADD_COST
7666 doesn't take different costs of registers and constants into
7667 account, so compare the cost of the actual SET_SRCs. */
7670 /* ??? unroll can't understand anything but reg + const_int
7671 sums. It would be cleaner to fix unroll. */
7678 {
7683 {
7689 }
7690 }
7693 }
7694 }
7696 /* Clean up. */
7699 }
7700 \f
7701 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7703 void
7709 rtx insert_before;
7710 {
7711 rtx seq;
7712 rtx result;
7714 /* Prevent unexpected sharing of these rtx. */
7718 /* Increase the lifetime of any invariants moved further in code. */
7732 /* It is entirely possible that the expansion created lots of new
7733 registers. Iterate over the sequence we just created and
7734 record them all. */
7737 {
7740 {
7744 }
7745 }
7749 }
7750 \f
7751 /* Test whether A * B can be computed without
7752 an actual multiply insn. Value is 1 if so. */
7754 static int
7756 rtx a;
7757 rtx b;
7758 {
7760 rtx tmp;
7765 /* If only one is constant, make it B. */
7769 /* If first constant, both constant, so don't need multiply. */
7773 /* If second not constant, neither is constant, so would need multiply. */
7777 /* One operand is constant, so might not need multiply insn. Generate the
7778 code for the multiply and see if a call or multiply, or long sequence
7779 of insns is generated. */
7788 {
7793 else
7795 {
7804 {
7807 }
7808 }
7809 }
7818 /* Free any storage we obtained in generating this multiply and restore rtl
7819 allocation to its normal obstack. */
7824 }
7825 \f
7826 /* Check to see if loop can be terminated by a "decrement and branch until
7827 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7828 Also try reversing an increment loop to a decrement loop
7829 to see if the optimization can be performed.
7830 Value is nonzero if optimization was performed. */
7832 /* This is useful even if the architecture doesn't have such an insn,
7833 because it might change a loops which increments from 0 to n to a loop
7834 which decrements from n to 0. A loop that decrements to zero is usually
7835 faster than one that increments from zero. */
7837 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7838 such as approx_final_value, biv_total_increment, loop_iterations, and
7839 final_[bg]iv_value. */
7841 static int
7843 rtx loop_end;
7845 rtx loop_start;
7847 {
7849 rtx reg;
7850 rtx jump_label;
7851 rtx final_value;
7852 rtx start_value;
7853 rtx new_add_val;
7854 rtx comparison;
7855 rtx before_comparison;
7856 rtx p;
7857 rtx jump;
7858 rtx first_compare;
7861 /* If last insn is a conditional branch, and the insn before tests a
7862 register value, try to optimize it. Otherwise, we can't do anything. */
7869 /* Try to compute whether the compare/branch at the loop end is one or
7870 two instructions. */
7876 else
7879 /* Check all of the bivs to see if the compare uses one of them.
7880 Skip biv's set more than once because we can't guarantee that
7881 it will be zero on the last iteration. Also skip if the biv is
7882 used between its update and the test insn. */
7885 {
7889 first_compare))
7891 }
7896 /* Look for the case where the basic induction variable is always
7897 nonnegative, and equals zero on the last iteration.
7898 In this case, add a reg_note REG_NONNEG, which allows the
7899 m68k DBRA instruction to be used. */
7907 {
7908 /* Initial value must be greater than 0,
7909 init_val % -dec_value == 0 to ensure that it equals zero on
7910 the last iteration */
7916 {
7917 /* register always nonnegative, add REG_NOTE to branch */
7924 }
7926 /* If the decrement is 1 and the value was tested as >= 0 before
7927 the loop, then we can safely optimize. */
7929 {
7942 {
7949 }
7950 }
7951 }
7954 {
7955 /* Try to change inc to dec, so can apply above optimization. */
7956 /* Can do this if:
7957 all registers modified are induction variables or invariant,
7958 all memory references have non-overlapping addresses
7959 (obviously true if only one write)
7960 allow 2 insns for the compare/jump at the end of the loop. */
7961 /* Also, we must avoid any instructions which use both the reversed
7962 biv and another biv. Such instructions will fail if the loop is
7963 reversed. We meet this condition by requiring that either
7964 no_use_except_counting is true, or else that there is only
7965 one biv. */
7967 /* 1 if the iteration var is used only to count iterations. */
7969 /* 1 if the loop has no memory store, or it has a single memory store
7970 which is reversible. */
7975 {
7978 /* If there are no givs for this biv, and the only exit is the
7979 fall through at the end of the loop, then
7980 see if perhaps there are no uses except to count. */
7984 {
7989 /* An insn that sets the biv is okay. */
7990 ;
7994 {
7995 /* If either of these insns uses the biv and sets a pseudo
7996 that has more than one usage, then the biv has uses
7997 other than counting since it's used to derive a value
7998 that is used more than one time. */
8003 {
8006 }
8007 }
8009 {
8012 }
8013 }
8014 }
8019 {
8024 /* If the loop has a single store, and the destination address is
8025 invariant, then we can't reverse the loop, because this address
8026 might then have the wrong value at loop exit.
8027 This would work if the source was invariant also, however, in that
8028 case, the insn should have been moved out of the loop. */
8031 {
8034 reversible_mem_store
8035 = (! unknown_address_altered
8036 && ! unknown_constant_address_altered
8039 /* If the store depends on a register that is set after the
8040 store, it depends on the initial value, and is thus not
8041 reversible. */
8043 {
8049 }
8050 }
8051 }
8052 else
8055 /* This code only acts for innermost loops. Also it simplifies
8056 the memory address check by only reversing loops with
8057 zero or one memory access.
8058 Two memory accesses could involve parts of the same array,
8059 and that can't be reversed.
8060 If the biv is used only for counting, than we don't need to worry
8061 about all these things. */
8066 && reversible_mem_store
8071 {
8072 rtx tem;
8074 /* Loop can be reversed. */
8078 /* Now check other conditions:
8080 The increment must be a constant, as must the initial value,
8081 and the comparison code must be LT.
8083 This test can probably be improved since +/- 1 in the constant
8084 can be obtained by changing LT to LE and vice versa; this is
8085 confusing. */
8088 /* for constants, LE gets turned into LT */
8092 {
8103 comparison_const_width
8105 else
8106 comparison_const_width
8110 comparison_sign_mask
8113 /* If the comparison value is not a loop invariant, then we
8114 can not reverse this loop.
8116 ??? If the insns which initialize the comparison value as
8117 a whole compute an invariant result, then we could move
8118 them out of the loop and proceed with loop reversal. */
8126 /* Normalize the initial value if it is an integer and
8127 has no other use except as a counter. This will allow
8128 a few more loops to be reversed. */
8132 {
8134 /* The code below requires comparison_val to be a multiple
8135 of add_val in order to do the loop reversal, so
8136 round up comparison_val to a multiple of add_val.
8137 Since comparison_value is constant, we know that the
8138 current comparison code is LT. */
8140 comparison_val
8142 /* We postpone overflow checks for COMPARISON_VAL here;
8143 even if there is an overflow, we might still be able to
8144 reverse the loop, if converting the loop exit test to
8145 NE is possible. */
8147 }
8149 /* First check if we can do a vanilla loop reversal. */
8151 /* If we have a decrement_and_branch_on_count,
8152 prefer the NE test, since this will allow that
8153 instruction to be generated. Note that we must
8154 use a vanilla loop reversal if the biv is used to
8155 calculate a giv or has a non-counting use. */
8156 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8157 && defined (HAVE_decrement_and_branch_on_count)
8161 #endif
8163 /* Now do postponed overflow checks on COMPARISON_VAL. */
8166 {
8167 /* Register will always be nonnegative, with value
8168 0 on last iteration */
8172 }
8176 {
8179 }
8180 else
8186 /* If the initial value is not zero, or if the comparison
8187 value is not an exact multiple of the increment, then we
8188 can not reverse this loop. */
8191 {
8194 }
8195 else
8196 {
8199 }
8203 /* Reset these in case we normalized the initial value
8204 and comparison value above. */
8207 {
8209 final_value
8211 }
8214 /* Save some info needed to produce the new insns. */
8221 /* Set start_value; if this is not a CONST_INT, we need
8222 to generate a SUB.
8223 Initialize biv to start_value before loop start.
8224 The old initializing insn will be deleted as a
8225 dead store by flow.c. */
8228 {
8231 loop_start);
8232 }
8234 {
8237 enum insn_code icode
8246 start_value
8250 loop_start);
8254 }
8256 {
8258 enum insn_code icode
8266 start_value
8270 loop_start);
8271 }
8272 else
8273 /* We could handle the other cases too, but it'll be
8274 better to have a testcase first. */
8277 /* We may not have a single insn which can increment a reg, so
8278 create a sequence to hold all the insns from expand_inc. */
8287 /* Update biv info to reflect its new status. */
8292 /* Update loop info. */
8301 /* Inc LABEL_NUSES so that delete_insn will
8302 not delete the label. */
8305 /* Emit an insn after the end of the loop to set the biv's
8306 proper exit value if it is used anywhere outside the loop. */
8311 loop_end);
8313 /* Delete compare/branch at end of loop. */
8318 /* Add new compare/branch insn at end of loop. */
8330 ;
8336 {
8338 {
8339 /* Increment of LABEL_NUSES done above. */
8340 /* Register is now always nonnegative,
8341 so add REG_NONNEG note to the branch. */
8344 }
8346 }
8348 /* No insn may reference both the reversed and another biv or it
8349 will fail (see comment near the top of the loop reversal
8350 code).
8351 Earlier on, we have verified that the biv has no use except
8352 counting, or it is the only biv in this function.
8353 However, the code that computes no_use_except_counting does
8354 not verify reg notes. It's possible to have an insn that
8355 references another biv, and has a REG_EQUAL note with an
8356 expression based on the reversed biv. To avoid this case,
8357 remove all REG_EQUAL notes based on the reversed biv
8358 here. */
8361 {
8364 /* If this is a set of a GIV based on the reversed biv, any
8365 REG_EQUAL notes should still be correct. */
8372 {
8377 else
8379 }
8380 }
8382 /* Mark that this biv has been reversed. Each giv which depends
8383 on this biv, and which is also live past the end of the loop
8384 will have to be fixed up. */
8389 {
8393 else
8395 }
8398 }
8399 }
8400 }
8403 }
8404 \f
8405 /* Verify whether the biv BL appears to be eliminable,
8406 based on the insns in the loop that refer to it.
8407 LOOP_START is the first insn of the loop, and END is the end insn.
8409 If ELIMINATE_P is non-zero, actually do the elimination.
8411 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8412 determine whether invariant insns should be placed inside or at the
8413 start of the loop. */
8415 static int
8418 rtx loop_start;
8419 rtx end;
8422 {
8424 rtx p;
8426 /* Scan all insns in the loop, stopping if we find one that uses the
8427 biv in a way that we cannot eliminate. */
8430 {
8434 /* If this is a libcall that sets a giv, skip ahead to its end. */
8436 {
8440 {
8445 {
8452 }
8453 }
8454 }
8458 {
8464 }
8465 }
8468 {
8473 }
8476 }
8477 \f
8478 /* INSN and REFERENCE are instructions in the same insn chain.
8479 Return non-zero if INSN is first. */
8481 int
8484 {
8488 {
8489 /* Start with test for not first so that INSN == REFERENCE yields not
8490 first. */
8496 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8497 previous insn, hence the <= comparison below does not work if
8498 P is a note. */
8509 }
8510 }
8512 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8513 the offset that we have to take into account due to auto-increment /
8514 div derivation is zero. */
8515 static int
8518 rtx insn;
8519 {
8520 /* If the giv V had the auto-inc address optimization applied
8521 to it, and INSN occurs between the giv insn and the biv
8522 insn, then we'd have to adjust the value used here.
8523 This is rare, so we don't bother to make this possible. */
8531 /* If the giv V was derived from another giv, and INSN does
8532 not occur between the giv insn and the biv insn, then we'd
8533 have to adjust the value used here. This is rare, so we don't
8534 bother to make this possible. */
8548 }
8550 /* If BL appears in X (part of the pattern of INSN), see if we can
8551 eliminate its use. If so, return 1. If not, return 0.
8553 If BIV does not appear in X, return 1.
8555 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8556 where extra insns should be added. Depending on how many items have been
8557 moved out of the loop, it will either be before INSN or at the start of
8558 the loop. */
8560 static int
8565 rtx where;
8566 {
8572 #ifdef HAVE_cc0
8574 #endif
8580 {
8582 /* If we haven't already been able to do something with this BIV,
8583 we can't eliminate it. */
8589 /* If this sets the BIV, it is not a problem. */
8593 /* If this is an insn that defines a giv, it is also ok because
8594 it will go away when the giv is reduced. */
8599 #ifdef HAVE_cc0
8601 {
8602 /* Can replace with any giv that was reduced and
8603 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8604 Require a constant for MULT_VAL, so we know it's nonzero.
8605 ??? We disable this optimization to avoid potential
8606 overflows. */
8614 {
8621 /* If the giv has the opposite direction of change,
8622 then reverse the comparison. */
8626 else
8629 /* We can probably test that giv's reduced reg. */
8632 }
8634 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8635 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8636 Require a constant for MULT_VAL, so we know it's nonzero.
8637 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8638 overflow problem. */
8649 {
8656 /* If the giv has the opposite direction of change,
8657 then reverse the comparison. */
8661 else
8665 /* Replace biv with the giv's reduced register. */
8670 /* Insn doesn't support that constant or invariant. Copy it
8671 into a register (it will be a loop invariant.) */
8675 where);
8677 /* Substitute the new register for its invariant value in
8678 the compare expression. */
8682 }
8683 }
8684 #endif
8691 /* See if either argument is the biv. */
8696 else
8700 {
8701 /* First try to replace with any giv that has constant positive
8702 mult_val and constant add_val. We might be able to support
8703 negative mult_val, but it seems complex to do it in general. */
8714 {
8721 /* Replace biv with the giv's reduced reg. */
8724 /* If all constants are actually constant integers and
8725 the derived constant can be directly placed in the COMPARE,
8726 do so. */
8736 /* Otherwise, load it into a register. */
8742 /* If that failed, put back the change we made above. */
8744 }
8746 /* Look for giv with positive constant mult_val and nonconst add_val.
8747 Insert insns to calculate new compare value.
8748 ??? Turn this off due to possible overflow. */
8755 {
8756 rtx tem;
8766 /* Replace biv with giv's reduced register. */
8770 /* Compute value to compare against. */
8772 /* Use it in this insn. */
8776 }
8777 }
8779 {
8781 {
8782 /* Look for giv with constant positive mult_val and nonconst
8783 add_val. Insert insns to compute new compare value.
8784 ??? Turn this off due to possible overflow. */
8791 {
8792 rtx tem;
8802 /* Replace biv with giv's reduced register. */
8806 /* Compute value to compare against. */
8812 }
8813 }
8815 /* This code has problems. Basically, you can't know when
8816 seeing if we will eliminate BL, whether a particular giv
8817 of ARG will be reduced. If it isn't going to be reduced,
8818 we can't eliminate BL. We can try forcing it to be reduced,
8819 but that can generate poor code.
8821 The problem is that the benefit of reducing TV, below should
8822 be increased if BL can actually be eliminated, but this means
8823 we might have to do a topological sort of the order in which
8824 we try to process biv. It doesn't seem worthwhile to do
8825 this sort of thing now. */
8827 #if 0
8828 /* Otherwise the reg compared with had better be a biv. */
8833 /* Look for a pair of givs, one for each biv,
8834 with identical coefficients. */
8836 {
8847 {
8854 /* Replace biv with its giv's reduced reg. */
8856 /* Replace other operand with the other giv's
8857 reduced reg. */
8860 }
8861 }
8862 #endif
8863 }
8865 /* If we get here, the biv can't be eliminated. */
8869 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8870 biv is used in it, since it will be replaced. */
8878 }
8880 /* See if any subexpression fails elimination. */
8883 {
8885 {
8898 }
8899 }
8902 }
8903 \f
8904 /* Return nonzero if the last use of REG
8905 is in an insn following INSN in the same basic block. */
8907 static int
8909 rtx reg;
8910 rtx insn;
8911 {
8912 rtx n;
8916 {
8919 }
8921 }
8922 \f
8923 /* Called via `note_stores' to record the initial value of a biv. Here we
8924 just record the location of the set and process it later. */
8926 static void
8928 rtx dest;
8929 rtx set;
8931 {
8941 /* If this is the first set found, record it. */
8943 {
8946 }
8947 }
8948 \f
8949 /* If any of the registers in X are "old" and currently have a last use earlier
8950 than INSN, update them to have a last use of INSN. Their actual last use
8951 will be the previous insn but it will not have a valid uid_luid so we can't
8952 use it. */
8954 static void
8956 rtx x;
8957 rtx insn;
8958 {
8959 /* Check for the case where INSN does not have a valid luid. In this case,
8960 there is no need to modify the regno_last_uid, as this can only happen
8961 when code is inserted after the loop_end to set a pseudo's final value,
8962 and hence this insn will never be the last use of x. */
8967 else
8968 {
8972 {
8978 }
8979 }
8980 }
8981 \f
8982 /* Given a jump insn JUMP, return the condition that will cause it to branch
8983 to its JUMP_LABEL. If the condition cannot be understood, or is an
8984 inequality floating-point comparison which needs to be reversed, 0 will
8985 be returned.
8987 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8988 insn used in locating the condition was found. If a replacement test
8989 of the condition is desired, it should be placed in front of that
8990 insn and we will be sure that the inputs are still valid.
8992 The condition will be returned in a canonical form to simplify testing by
8993 callers. Specifically:
8995 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8996 (2) Both operands will be machine operands; (cc0) will have been replaced.
8997 (3) If an operand is a constant, it will be the second operand.
8998 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8999 for GE, GEU, and LEU. */
9001 rtx
9003 rtx jump;
9005 {
9008 rtx set;
9009 rtx tem;
9015 /* If this is not a standard conditional jump, we can't parse it. */
9028 /* If this branches to JUMP_LABEL when the condition is false, reverse
9029 the condition. */
9034 /* If we are comparing a register with zero, see if the register is set
9035 in the previous insn to a COMPARE or a comparison operation. Perform
9036 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9037 in cse.c */
9040 {
9041 /* Set non-zero when we find something of interest. */
9044 #ifdef HAVE_cc0
9045 /* If comparison with cc0, import actual comparison from compare
9046 insn. */
9048 {
9059 }
9060 #endif
9062 /* If this is a COMPARE, pick up the two things being compared. */
9064 {
9068 }
9072 /* Go back to the previous insn. Stop if it is not an INSN. We also
9073 stop if it isn't a single set or if it has a REG_INC note because
9074 we don't want to bother dealing with it. */
9082 /* If this is setting OP0, get what it sets it to if it looks
9083 relevant. */
9085 {
9088 /* ??? We may not combine comparisons done in a CCmode with
9089 comparisons not done in a CCmode. This is to aid targets
9090 like Alpha that have an IEEE compliant EQ instruction, and
9091 a non-IEEE compliant BEQ instruction. The use of CCmode is
9092 actually artificial, simply to prevent the combination, but
9093 should not affect other platforms.
9095 However, we must allow VOIDmode comparisons to match either
9096 CCmode or non-CCmode comparison, because some ports have
9097 modeless comparisons inside branch patterns.
9099 ??? This mode check should perhaps look more like the mode check
9100 in simplify_comparison in combine. */
9108 && (STORE_FLAG_VALUE
9111 #ifdef FLOAT_STORE_FLAG_VALUE
9115 #endif
9116 ))
9127 && (STORE_FLAG_VALUE
9130 #ifdef FLOAT_STORE_FLAG_VALUE
9134 #endif
9135 ))
9141 {
9142 /* We might have reversed a LT to get a GE here. But this wasn't
9143 actually the comparison of data, so we don't flag that we
9144 have had to reverse the condition. */
9148 }
9149 else
9151 }
9154 /* If this sets OP0, but not directly, we have to give up. */
9158 {
9162 {
9166 }
9171 }
9172 }
9174 /* If constant is first, put it last. */
9178 /* If OP0 is the result of a comparison, we weren't able to find what
9179 was really being compared, so fail. */
9183 /* Canonicalize any ordered comparison with integers involving equality
9184 if we can do computations in the relevant mode and we do not
9185 overflow. */
9190 {
9193 unsigned HOST_WIDE_INT max_val
9197 {
9203 /* When cross-compiling, const_val might be sign-extended from
9204 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9224 }
9225 }
9227 /* If this was floating-point and we reversed anything other than an
9228 EQ or NE, return zero. */
9231 && ! flag_fast_math
9235 #ifdef HAVE_cc0
9236 /* Never return CC0; return zero instead. */
9239 #endif
9242 }
9244 /* Similar to above routine, except that we also put an invariant last
9245 unless both operands are invariants. */
9247 rtx
9249 rtx x;
9250 {
9260 }
9262 #ifdef HAVE_decrement_and_branch_on_count
9263 /* Instrument loop for insertion of bct instruction. We distinguish between
9264 loops with compile-time bounds and those with run-time bounds.
9265 Information from loop_iterations() is used to compute compile-time bounds.
9266 Run-time bounds should use loop preconditioning, but currently ignored.
9267 */
9269 static void
9273 {
9279 /* If the loop condition is <= or >=, the number of iteration
9280 is 1 more than the range of the bounds of the loop. */
9287 /* It's impossible to instrument a competely unrolled loop. */
9291 /* Make sure that the count register is not in use. */
9293 {
9297 loop_num);
9299 }
9301 /* Make sure that the function has no indirect jumps. */
9303 {
9307 loop_num);
9309 }
9311 /* Make sure that the last loop insn is a conditional jump. */
9315 {
9319 loop_num);
9321 }
9323 /* Make sure that the loop does not contain a function call
9324 (the count register might be altered by the called function). */
9326 {
9330 loop_num);
9332 }
9334 /* Make sure that the loop does not jump via a table.
9335 (the count register might be used to perform the branch on table). */
9337 {
9341 loop_num);
9343 }
9345 /* Account for loop unrolling in instrumented iteration count. */
9348 else
9352 {
9353 /* Allow an enclosing outer loop to benefit if possible. */
9357 loop_num);
9359 }
9361 /* Try to instrument the loop. */
9363 /* Handle the simpler case, where the bounds are known at compile time. */
9365 {
9366 /* Mark all enclosing loops that they cannot use count register. */
9371 }
9373 /* Handle the more complex case, that the bounds are NOT known
9374 at compile time. In this case we generate run_time calculation
9375 of the number of iterations. */
9378 {
9382 loop_num);
9384 }
9388 {
9392 loop_num);
9394 }
9396 /* With runtime bounds, if the compare is of the form '!=' we give up */
9398 {
9402 loop_num);
9404 }
9405 /* Use common loop preconditioning code instead. */
9406 #if 0
9407 else
9408 {
9409 /* We rely on the existence of run-time guard to ensure that the
9410 loop executes at least once. */
9411 rtx sequence;
9412 rtx iterations_num_reg;
9414 unsigned HOST_WIDE_INT increment_value_abs
9417 /* make sure that the increment is a power of two, otherwise (an
9418 expensive) divide is needed. */
9420 {
9425 }
9427 /* compute the number of iterations */
9429 {
9430 rtx temp_reg;
9432 /* Again, the number of iterations is calculated by:
9433 ;
9434 ; compare-val - initial-val + (increment -1) + additional-iteration
9435 ; num_iterations = -----------------------------------------------------------------
9436 ; increment
9437 */
9438 /* ??? Do we have to call copy_rtx here before passing rtx to
9439 expand_binop? */
9441 {
9442 /* <, <= :the loop variable is increasing */
9446 }
9447 else
9448 {
9452 }
9462 temp_reg,
9465 else
9467 }
9472 }
9476 }
9478 /* Instrument loop by inserting a bct in it as follows:
9479 1. A new counter register is created.
9480 2. In the head of the loop the new variable is initialized to the value
9481 passed in the loop_num_iterations parameter.
9482 3. At the end of the loop, comparison of the register with 0 is generated.
9483 The created comparison follows the pattern defined for the
9484 decrement_and_branch_on_count insn, so this insn will be generated.
9485 4. The branch on the old variable are deleted. The compare must remain
9486 because it might be used elsewhere. If the loop-variable or condition
9487 register are used elsewhere, they will be eliminated by flow. */
9489 static void
9492 rtx loop_num_iterations;
9493 {
9494 rtx counter_reg;
9495 rtx start_label;
9496 rtx sequence;
9499 {
9501 {
9506 else
9509 }
9511 /* Discard original jump to continue loop. Original compare result
9512 may still be live, so it cannot be discarded explicitly. */
9515 /* Insert the label which will delimit the start of the loop. */
9519 /* Insert initialization of the count register into the loop header. */
9527 /* Insert new comparison on the count register instead of the
9528 old one, generating the needed BCT pattern (that will be
9529 later recognized by assembly generation phase). */
9531 start_label),
9532 loop_end);
9534 }
9536 }
9539 /* Scan the function and determine whether it has indirect (computed) jumps.
9541 This is taken mostly from flow.c; similar code exists elsewhere
9542 in the compiler. It may be useful to put this into rtlanal.c. */
9543 static int
9545 rtx start;
9546 {
9547 rtx insn;
9554 }
9556 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9557 documentation for LOOP_MEMS for the definition of `appropriate'.
9558 This function is called from prescan_loop via for_each_rtx. */
9560 static int
9564 {
9572 {
9577 /* We're not interested in the MEM associated with a
9578 CONST_DOUBLE, so there's no need to traverse into this. */
9582 /* This is not a MEM. */
9584 }
9586 /* See if we've already seen this MEM. */
9589 {
9591 /* The modes of the two memory accesses are different. If
9592 this happens, something tricky is going on, and we just
9593 don't optimize accesses to this MEM. */
9597 }
9599 /* Resize the array, if necessary. */
9601 {
9604 else
9610 }
9612 /* Actually insert the MEM. */
9614 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9615 because we can't put it in a register. We still store it in the
9616 table, though, so that if we see the same address later, but in a
9617 non-BLK mode, we'll not think we can optimize it at that point. */
9623 }
9625 /* Like load_mems, but also ensures that SET_IN_LOOP,
9626 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9627 values after load_mems. */
9629 static void
9631 insn_count)
9632 rtx scan_start;
9633 rtx end;
9634 rtx loop_top;
9635 rtx start;
9637 {
9642 /* Recalculate set_in_loop and friends since load_mems may have
9643 created new registers. */
9645 {
9653 {
9654 /* Grow all the arrays. */
9659 }
9660 /* Clear the arrays */
9670 {
9673 }
9675 #ifdef AVOID_CCMODE_COPIES
9676 /* Don't try to move insns which set CC registers if we should not
9677 create CCmode register copies. */
9681 #endif
9683 /* Set n_times_set for the new registers. */
9687 }
9688 }
9690 /* Move MEMs into registers for the duration of the loop. SCAN_START
9691 is the first instruction in the loop (as it is executed). The
9692 other parameters are as for next_insn_in_loop. */
9694 static void
9696 rtx scan_start;
9697 rtx end;
9698 rtx loop_top;
9699 rtx start;
9700 {
9703 rtx p;
9708 {
9709 /* Nonzero if the next instruction may never be executed. */
9712 /* Check to see if it's possible that some instructions in the
9713 loop are never executed. */
9717 {
9721 /* If we enter the loop in the middle, and scan
9722 around to the beginning, don't set maybe_never
9723 for that. This must be an unconditional jump,
9724 otherwise the code at the top of the loop might
9725 never be executed. Unconditional jumps are
9726 followed a by barrier then loop end. */
9731 {
9733 /* Something complicated. */
9735 else
9736 /* If there are any more instructions in the loop, they
9737 might not be reached. */
9739 }
9742 }
9744 /* Actually move the MEMs. */
9746 {
9748 rtx reg;
9750 rtx mem_list_entry;
9754 /* There's no telling whether or not MEM is modified. */
9757 /* Go through the MEMs written to in the loop to see if this
9758 one is aliased by one of them. */
9761 {
9766 {
9767 /* MEM is indeed aliased by this store. */
9770 }
9772 }
9774 /* If this MEM is written to, we must be sure that there
9775 are no reads from another MEM that aliases this one. */
9777 {
9781 {
9785 VOIDmode,
9787 rtx_varies_p))
9788 {
9789 /* It's not safe to hoist loop_mems[i] out of
9790 the loop because writes to it might not be
9791 seen by reads from loop_mems[j]. */
9794 }
9795 }
9796 }
9799 /* We can't access the MEM outside the loop; it might
9800 cause a trap that wouldn't have happened otherwise. */
9804 /* We thought we were going to lift this MEM out of the
9805 loop, but later discovered that we could not. */
9808 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9809 order to keep scan_loop from moving stores to this MEM
9810 out of the loop just because this REG is neither a
9811 user-variable nor used in the loop test. */
9816 /* Now, replace all references to the MEM with the
9817 corresponding pesudos. */
9821 {
9822 rtx_and_int ri;
9826 }
9829 /* We couldn't replace all occurrences of the MEM. */
9831 else
9832 {
9833 rtx set;
9835 /* Load the memory immediately before START, which is
9836 the NOTE_LOOP_BEG. */
9841 {
9843 {
9844 /* We must compute the former
9845 right-after-the-end label before we insert
9846 the new one. */
9850 }
9852 /* Store the memory immediately after END, which is
9853 the NOTE_LOOP_END. */
9856 }
9859 {
9864 }
9865 }
9866 }
9867 }
9870 {
9871 /* Now, we need to replace all references to the previous exit
9872 label with the new one. */
9873 rtx_pair rr;
9878 {
9881 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9882 field. This is not handled by for_each_rtx because it doesn't
9883 handle unprinted ('0') fields. We need to update JUMP_LABEL
9884 because the immediately following unroll pass will use it.
9885 replace_label would not work anyways, because that only handles
9886 LABEL_REFs. */
9889 }
9890 }
9891 }
9893 /* Replace MEM with its associated pseudo register. This function is
9894 called from load_mems via for_each_rtx. DATA is actually an
9895 rtx_and_int * describing the instruction currently being scanned
9896 and the MEM we are currently replacing. */
9898 static int
9902 {
9904 rtx insn;
9912 {
9917 /* We're not interested in the MEM associated with a
9918 CONST_DOUBLE, so there's no need to traverse into one. */
9922 /* This is not a MEM. */
9924 }
9930 /* This is not the MEM we are currently replacing. */
9935 /* Actually replace the MEM. */
9939 }
9941 /* Replace occurrences of the old exit label for the loop with the new
9942 one. DATA is an rtx_pair containing the old and new labels,
9943 respectively. */
9945 static int
9949 {
9968 }