| blob | 398518329e275925d7b4135910cbd4b632fe9b92 |
1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 (define_insn "*thumb2_incscc"
28 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
29 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
30 [(match_operand:CC 3 "cc_register" "") (const_int 0)])
31 (match_operand:SI 1 "s_register_operand" "0,?r")))]
32 "TARGET_THUMB2"
33 "@
34 it\\t%d2\;add%d2\\t%0, %1, #1
35 ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
36 [(set_attr "conds" "use")
37 (set_attr "length" "6,10")]
38 )
40 (define_insn "*thumb2_decscc"
41 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
42 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
43 (match_operator:SI 2 "arm_comparison_operator"
44 [(match_operand 3 "cc_register" "") (const_int 0)])))]
45 "TARGET_THUMB2"
46 "@
47 it\\t%d2\;sub%d2\\t%0, %1, #1
48 ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
49 [(set_attr "conds" "use")
50 (set_attr "length" "6,10")]
51 )
53 ;; Thumb-2 only allows shift by constant on data processing instructions
54 (define_insn "*thumb_andsi_not_shiftsi_si"
55 [(set (match_operand:SI 0 "s_register_operand" "=r")
56 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
57 [(match_operand:SI 2 "s_register_operand" "r")
58 (match_operand:SI 3 "const_int_operand" "M")]))
59 (match_operand:SI 1 "s_register_operand" "r")))]
60 "TARGET_THUMB2"
61 "bic%?\\t%0, %1, %2%S4"
62 [(set_attr "predicable" "yes")
63 (set_attr "shift" "2")
64 (set_attr "type" "alu_shift")]
65 )
67 (define_insn "*thumb2_smaxsi3"
68 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
69 (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
70 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
71 (clobber (reg:CC CC_REGNUM))]
72 "TARGET_THUMB2"
73 "@
74 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
75 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
76 cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
77 [(set_attr "conds" "clob")
78 (set_attr "length" "10,10,14")]
79 )
81 (define_insn "*thumb2_sminsi3"
82 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
83 (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
84 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
85 (clobber (reg:CC CC_REGNUM))]
86 "TARGET_THUMB2"
87 "@
88 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
89 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
90 cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
91 [(set_attr "conds" "clob")
92 (set_attr "length" "10,10,14")]
93 )
95 (define_insn "*thumb32_umaxsi3"
96 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
97 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
98 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
99 (clobber (reg:CC CC_REGNUM))]
100 "TARGET_THUMB2"
101 "@
102 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
103 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
104 cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
105 [(set_attr "conds" "clob")
106 (set_attr "length" "10,10,14")]
107 )
109 (define_insn "*thumb2_uminsi3"
110 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
111 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
112 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
113 (clobber (reg:CC CC_REGNUM))]
114 "TARGET_THUMB2"
115 "@
116 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
117 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
118 cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
119 [(set_attr "conds" "clob")
120 (set_attr "length" "10,10,14")]
121 )
123 (define_insn "*thumb2_notsi_shiftsi"
124 [(set (match_operand:SI 0 "s_register_operand" "=r")
125 (not:SI (match_operator:SI 3 "shift_operator"
126 [(match_operand:SI 1 "s_register_operand" "r")
127 (match_operand:SI 2 "const_int_operand" "M")])))]
128 "TARGET_THUMB2"
129 "mvn%?\\t%0, %1%S3"
130 [(set_attr "predicable" "yes")
131 (set_attr "shift" "1")
132 (set_attr "type" "alu_shift")]
133 )
135 (define_insn "*thumb2_notsi_shiftsi_compare0"
136 [(set (reg:CC_NOOV CC_REGNUM)
137 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
138 [(match_operand:SI 1 "s_register_operand" "r")
139 (match_operand:SI 2 "const_int_operand" "M")]))
140 (const_int 0)))
141 (set (match_operand:SI 0 "s_register_operand" "=r")
142 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
143 "TARGET_THUMB2"
144 "mvn%.\\t%0, %1%S3"
145 [(set_attr "conds" "set")
146 (set_attr "shift" "1")
147 (set_attr "type" "alu_shift")]
148 )
150 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
151 [(set (reg:CC_NOOV CC_REGNUM)
152 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
153 [(match_operand:SI 1 "s_register_operand" "r")
154 (match_operand:SI 2 "const_int_operand" "M")]))
155 (const_int 0)))
156 (clobber (match_scratch:SI 0 "=r"))]
157 "TARGET_THUMB2"
158 "mvn%.\\t%0, %1%S3"
159 [(set_attr "conds" "set")
160 (set_attr "shift" "1")
161 (set_attr "type" "alu_shift")]
162 )
164 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
165 (define_insn "*thumb2_negdi2"
166 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
167 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
168 (clobber (reg:CC CC_REGNUM))]
169 "TARGET_THUMB2"
170 "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
171 [(set_attr "conds" "clob")
172 (set_attr "length" "8")]
173 )
175 (define_insn "*thumb2_abssi2"
176 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
177 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
178 (clobber (reg:CC CC_REGNUM))]
179 "TARGET_THUMB2"
180 "@
181 cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
182 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
183 [(set_attr "conds" "clob,*")
184 (set_attr "shift" "1")
185 ;; predicable can't be set based on the variant, so left as no
186 (set_attr "length" "10,8")]
187 )
189 (define_insn "*thumb2_neg_abssi2"
190 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
191 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
192 (clobber (reg:CC CC_REGNUM))]
193 "TARGET_THUMB2"
194 "@
195 cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
196 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
197 [(set_attr "conds" "clob,*")
198 (set_attr "shift" "1")
199 ;; predicable can't be set based on the variant, so left as no
200 (set_attr "length" "10,8")]
201 )
203 (define_insn "*thumb2_movdi"
204 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
205 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
206 "TARGET_THUMB2
207 && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
208 && !TARGET_IWMMXT"
209 "*
210 switch (which_alternative)
211 {
212 case 0:
213 case 1:
214 case 2:
215 return \"#\";
216 default:
217 return output_move_double (operands);
218 }
219 "
220 [(set_attr "length" "8,12,16,8,8")
221 (set_attr "type" "*,*,*,load2,store2")
222 (set_attr "pool_range" "*,*,*,4096,*")
223 (set_attr "neg_pool_range" "*,*,*,0,*")]
224 )
226 ;; We have two alternatives here for memory loads (and similarly for stores)
227 ;; to reflect the fact that the permissible constant pool ranges differ
228 ;; between ldr instructions taking low regs and ldr instructions taking high
229 ;; regs. The high register alternatives are not taken into account when
230 ;; choosing register preferences in order to reflect their expense.
231 (define_insn "*thumb2_movsi_insn"
232 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
233 (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
234 "TARGET_THUMB2 && ! TARGET_IWMMXT
235 && !(TARGET_HARD_FLOAT && TARGET_VFP)
236 && ( register_operand (operands[0], SImode)
237 || register_operand (operands[1], SImode))"
238 "@
239 mov%?\\t%0, %1
240 mov%?\\t%0, %1
241 mvn%?\\t%0, #%B1
242 movw%?\\t%0, %1
243 ldr%?\\t%0, %1
244 ldr%?\\t%0, %1
245 str%?\\t%1, %0
246 str%?\\t%1, %0"
247 [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
248 (set_attr "predicable" "yes")
249 (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
250 (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
251 )
253 (define_insn "tls_load_dot_plus_four"
254 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
255 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
256 (const_int 4)
257 (match_operand 3 "" "")]
258 UNSPEC_PIC_BASE)))
259 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
260 "TARGET_THUMB2"
261 "*
262 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
263 INTVAL (operands[3]));
264 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
265 "
266 [(set_attr "length" "4,4,6,6")]
267 )
269 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
270 ;; of the messiness associated with the ARM patterns.
271 (define_insn "*thumb2_movhi_insn"
272 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
273 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
274 "TARGET_THUMB2"
275 "@
276 mov%?\\t%0, %1\\t%@ movhi
277 movw%?\\t%0, %L1\\t%@ movhi
278 str%(h%)\\t%1, %0\\t%@ movhi
279 ldr%(h%)\\t%0, %1\\t%@ movhi"
280 [(set_attr "type" "*,*,store1,load1")
281 (set_attr "predicable" "yes")
282 (set_attr "pool_range" "*,*,*,4096")
283 (set_attr "neg_pool_range" "*,*,*,250")]
284 )
286 (define_insn "*thumb2_movsf_soft_insn"
287 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
288 (match_operand:SF 1 "general_operand" "r,mE,r"))]
289 "TARGET_THUMB2
290 && TARGET_SOFT_FLOAT
291 && (GET_CODE (operands[0]) != MEM
292 || register_operand (operands[1], SFmode))"
293 "@
294 mov%?\\t%0, %1
295 ldr%?\\t%0, %1\\t%@ float
296 str%?\\t%1, %0\\t%@ float"
297 [(set_attr "predicable" "yes")
298 (set_attr "type" "*,load1,store1")
299 (set_attr "pool_range" "*,4096,*")
300 (set_attr "neg_pool_range" "*,0,*")]
301 )
303 (define_insn "*thumb2_movdf_soft_insn"
304 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
305 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
306 "TARGET_THUMB2 && TARGET_SOFT_FLOAT
307 && ( register_operand (operands[0], DFmode)
308 || register_operand (operands[1], DFmode))"
309 "*
310 switch (which_alternative)
311 {
312 case 0:
313 case 1:
314 case 2:
315 return \"#\";
316 default:
317 return output_move_double (operands);
318 }
319 "
320 [(set_attr "length" "8,12,16,8,8")
321 (set_attr "type" "*,*,*,load2,store2")
322 (set_attr "pool_range" "*,*,*,1020,*")
323 (set_attr "neg_pool_range" "*,*,*,0,*")]
324 )
326 (define_insn "*thumb2_cmpsi_shiftsi"
327 [(set (reg:CC CC_REGNUM)
328 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
329 (match_operator:SI 3 "shift_operator"
330 [(match_operand:SI 1 "s_register_operand" "r")
331 (match_operand:SI 2 "const_int_operand" "M")])))]
332 "TARGET_THUMB2"
333 "cmp%?\\t%0, %1%S3"
334 [(set_attr "conds" "set")
335 (set_attr "shift" "1")
336 (set_attr "type" "alu_shift")]
337 )
339 (define_insn "*thumb2_cmpsi_shiftsi_swp"
340 [(set (reg:CC_SWP CC_REGNUM)
341 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
342 [(match_operand:SI 1 "s_register_operand" "r")
343 (match_operand:SI 2 "const_int_operand" "M")])
344 (match_operand:SI 0 "s_register_operand" "r")))]
345 "TARGET_THUMB2"
346 "cmp%?\\t%0, %1%S3"
347 [(set_attr "conds" "set")
348 (set_attr "shift" "1")
349 (set_attr "type" "alu_shift")]
350 )
352 (define_insn "*thumb2_cmpsi_neg_shiftsi"
353 [(set (reg:CC CC_REGNUM)
354 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
355 (neg:SI (match_operator:SI 3 "shift_operator"
356 [(match_operand:SI 1 "s_register_operand" "r")
357 (match_operand:SI 2 "const_int_operand" "M")]))))]
358 "TARGET_THUMB2"
359 "cmn%?\\t%0, %1%S3"
360 [(set_attr "conds" "set")
361 (set_attr "shift" "1")
362 (set_attr "type" "alu_shift")]
363 )
365 (define_insn "*thumb2_mov_scc"
366 [(set (match_operand:SI 0 "s_register_operand" "=r")
367 (match_operator:SI 1 "arm_comparison_operator"
368 [(match_operand 2 "cc_register" "") (const_int 0)]))]
369 "TARGET_THUMB2"
370 "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
371 [(set_attr "conds" "use")
372 (set_attr "length" "10")]
373 )
375 (define_insn "*thumb2_mov_negscc"
376 [(set (match_operand:SI 0 "s_register_operand" "=r")
377 (neg:SI (match_operator:SI 1 "arm_comparison_operator"
378 [(match_operand 2 "cc_register" "") (const_int 0)])))]
379 "TARGET_THUMB2"
380 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
381 [(set_attr "conds" "use")
382 (set_attr "length" "10")]
383 )
385 (define_insn "*thumb2_mov_notscc"
386 [(set (match_operand:SI 0 "s_register_operand" "=r")
387 (not:SI (match_operator:SI 1 "arm_comparison_operator"
388 [(match_operand 2 "cc_register" "") (const_int 0)])))]
389 "TARGET_THUMB2"
390 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
391 [(set_attr "conds" "use")
392 (set_attr "length" "10")]
393 )
395 (define_insn "*thumb2_movsicc_insn"
396 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
397 (if_then_else:SI
398 (match_operator 3 "arm_comparison_operator"
399 [(match_operand 4 "cc_register" "") (const_int 0)])
400 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
401 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
402 "TARGET_THUMB2"
403 "@
404 it\\t%D3\;mov%D3\\t%0, %2
405 it\\t%D3\;mvn%D3\\t%0, #%B2
406 it\\t%d3\;mov%d3\\t%0, %1
407 it\\t%d3\;mvn%d3\\t%0, #%B1
408 ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
409 ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
410 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
411 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
412 [(set_attr "length" "6,6,6,6,10,10,10,10")
413 (set_attr "conds" "use")]
414 )
416 (define_insn "*thumb2_movsfcc_soft_insn"
417 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
418 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
419 [(match_operand 4 "cc_register" "") (const_int 0)])
420 (match_operand:SF 1 "s_register_operand" "0,r")
421 (match_operand:SF 2 "s_register_operand" "r,0")))]
422 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
423 "@
424 it\\t%D3\;mov%D3\\t%0, %2
425 it\\t%d3\;mov%d3\\t%0, %1"
426 [(set_attr "length" "6,6")
427 (set_attr "conds" "use")]
428 )
430 (define_insn "*call_reg_thumb2"
431 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
432 (match_operand 1 "" ""))
433 (use (match_operand 2 "" ""))
434 (clobber (reg:SI LR_REGNUM))]
435 "TARGET_THUMB2"
436 "blx%?\\t%0"
437 [(set_attr "type" "call")]
438 )
440 (define_insn "*call_value_reg_thumb2"
441 [(set (match_operand 0 "" "")
442 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
443 (match_operand 2 "" "")))
444 (use (match_operand 3 "" ""))
445 (clobber (reg:SI LR_REGNUM))]
446 "TARGET_THUMB2"
447 "blx\\t%1"
448 [(set_attr "type" "call")]
449 )
451 (define_insn "*thumb2_indirect_jump"
452 [(set (pc)
453 (match_operand:SI 0 "register_operand" "l*r"))]
454 "TARGET_THUMB2"
455 "bx\\t%0"
456 [(set_attr "conds" "clob")]
457 )
458 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
459 ;; addresses will have the thumb bit set correctly.
462 ;; Patterns to allow combination of arithmetic, cond code and shifts
464 (define_insn "*thumb2_arith_shiftsi"
465 [(set (match_operand:SI 0 "s_register_operand" "=r")
466 (match_operator:SI 1 "shiftable_operator"
467 [(match_operator:SI 3 "shift_operator"
468 [(match_operand:SI 4 "s_register_operand" "r")
469 (match_operand:SI 5 "const_int_operand" "M")])
470 (match_operand:SI 2 "s_register_operand" "r")]))]
471 "TARGET_THUMB2"
472 "%i1%?\\t%0, %2, %4%S3"
473 [(set_attr "predicable" "yes")
474 (set_attr "shift" "4")
475 (set_attr "type" "alu_shift")]
476 )
478 ;; ??? What does this splitter do? Copied from the ARM version
479 (define_split
480 [(set (match_operand:SI 0 "s_register_operand" "")
481 (match_operator:SI 1 "shiftable_operator"
482 [(match_operator:SI 2 "shiftable_operator"
483 [(match_operator:SI 3 "shift_operator"
484 [(match_operand:SI 4 "s_register_operand" "")
485 (match_operand:SI 5 "const_int_operand" "")])
486 (match_operand:SI 6 "s_register_operand" "")])
487 (match_operand:SI 7 "arm_rhs_operand" "")]))
488 (clobber (match_operand:SI 8 "s_register_operand" ""))]
489 "TARGET_32BIT"
490 [(set (match_dup 8)
491 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
492 (match_dup 6)]))
493 (set (match_dup 0)
494 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
495 "")
497 (define_insn "*thumb2_arith_shiftsi_compare0"
498 [(set (reg:CC_NOOV CC_REGNUM)
499 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
500 [(match_operator:SI 3 "shift_operator"
501 [(match_operand:SI 4 "s_register_operand" "r")
502 (match_operand:SI 5 "const_int_operand" "M")])
503 (match_operand:SI 2 "s_register_operand" "r")])
504 (const_int 0)))
505 (set (match_operand:SI 0 "s_register_operand" "=r")
506 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
507 (match_dup 2)]))]
508 "TARGET_32BIT"
509 "%i1%.\\t%0, %2, %4%S3"
510 [(set_attr "conds" "set")
511 (set_attr "shift" "4")
512 (set_attr "type" "alu_shift")]
513 )
515 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
516 [(set (reg:CC_NOOV CC_REGNUM)
517 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
518 [(match_operator:SI 3 "shift_operator"
519 [(match_operand:SI 4 "s_register_operand" "r")
520 (match_operand:SI 5 "const_int_operand" "M")])
521 (match_operand:SI 2 "s_register_operand" "r")])
522 (const_int 0)))
523 (clobber (match_scratch:SI 0 "=r"))]
524 "TARGET_THUMB2"
525 "%i1%.\\t%0, %2, %4%S3"
526 [(set_attr "conds" "set")
527 (set_attr "shift" "4")
528 (set_attr "type" "alu_shift")]
529 )
531 (define_insn "*thumb2_sub_shiftsi"
532 [(set (match_operand:SI 0 "s_register_operand" "=r")
533 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
534 (match_operator:SI 2 "shift_operator"
535 [(match_operand:SI 3 "s_register_operand" "r")
536 (match_operand:SI 4 "const_int_operand" "M")])))]
537 "TARGET_THUMB2"
538 "sub%?\\t%0, %1, %3%S2"
539 [(set_attr "predicable" "yes")
540 (set_attr "shift" "3")
541 (set_attr "type" "alu_shift")]
542 )
544 (define_insn "*thumb2_sub_shiftsi_compare0"
545 [(set (reg:CC_NOOV CC_REGNUM)
546 (compare:CC_NOOV
547 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
548 (match_operator:SI 2 "shift_operator"
549 [(match_operand:SI 3 "s_register_operand" "r")
550 (match_operand:SI 4 "const_int_operand" "M")]))
551 (const_int 0)))
552 (set (match_operand:SI 0 "s_register_operand" "=r")
553 (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
554 (match_dup 4)])))]
555 "TARGET_THUMB2"
556 "sub%.\\t%0, %1, %3%S2"
557 [(set_attr "conds" "set")
558 (set_attr "shift" "3")
559 (set_attr "type" "alu_shift")]
560 )
562 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
563 [(set (reg:CC_NOOV CC_REGNUM)
564 (compare:CC_NOOV
565 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
566 (match_operator:SI 2 "shift_operator"
567 [(match_operand:SI 3 "s_register_operand" "r")
568 (match_operand:SI 4 "const_int_operand" "M")]))
569 (const_int 0)))
570 (clobber (match_scratch:SI 0 "=r"))]
571 "TARGET_THUMB2"
572 "sub%.\\t%0, %1, %3%S2"
573 [(set_attr "conds" "set")
574 (set_attr "shift" "3")
575 (set_attr "type" "alu_shift")]
576 )
578 (define_insn "*thumb2_and_scc"
579 [(set (match_operand:SI 0 "s_register_operand" "=r")
580 (and:SI (match_operator:SI 1 "arm_comparison_operator"
581 [(match_operand 3 "cc_register" "") (const_int 0)])
582 (match_operand:SI 2 "s_register_operand" "r")))]
583 "TARGET_THUMB2"
584 "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
585 [(set_attr "conds" "use")
586 (set_attr "length" "10")]
587 )
589 (define_insn "*thumb2_ior_scc"
590 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
591 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
592 [(match_operand 3 "cc_register" "") (const_int 0)])
593 (match_operand:SI 1 "s_register_operand" "0,?r")))]
594 "TARGET_THUMB2"
595 "@
596 it\\t%d2\;orr%d2\\t%0, %1, #1
597 ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
598 [(set_attr "conds" "use")
599 (set_attr "length" "6,10")]
600 )
602 (define_insn "*thumb2_compare_scc"
603 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
604 (match_operator:SI 1 "arm_comparison_operator"
605 [(match_operand:SI 2 "s_register_operand" "r,r")
606 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
607 (clobber (reg:CC CC_REGNUM))]
608 "TARGET_THUMB2"
609 "*
610 if (operands[3] == const0_rtx)
611 {
612 if (GET_CODE (operands[1]) == LT)
613 return \"lsr\\t%0, %2, #31\";
615 if (GET_CODE (operands[1]) == GE)
616 return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
618 if (GET_CODE (operands[1]) == EQ)
619 return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
620 }
622 if (GET_CODE (operands[1]) == NE)
623 {
624 if (which_alternative == 1)
625 return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
626 return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
627 }
628 if (which_alternative == 1)
629 output_asm_insn (\"cmn\\t%2, #%n3\", operands);
630 else
631 output_asm_insn (\"cmp\\t%2, %3\", operands);
632 return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
633 "
634 [(set_attr "conds" "clob")
635 (set_attr "length" "14")]
636 )
638 (define_insn "*thumb2_cond_move"
639 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
640 (if_then_else:SI (match_operator 3 "equality_operator"
641 [(match_operator 4 "arm_comparison_operator"
642 [(match_operand 5 "cc_register" "") (const_int 0)])
643 (const_int 0)])
644 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
645 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
646 "TARGET_THUMB2"
647 "*
648 if (GET_CODE (operands[3]) == NE)
649 {
650 if (which_alternative != 1)
651 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
652 if (which_alternative != 0)
653 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
654 return \"\";
655 }
656 switch (which_alternative)
657 {
658 case 0:
659 output_asm_insn (\"it\\t%d4\", operands);
660 break;
661 case 1:
662 output_asm_insn (\"it\\t%D4\", operands);
663 break;
664 case 2:
665 output_asm_insn (\"ite\\t%D4\", operands);
666 break;
667 default:
668 abort();
669 }
670 if (which_alternative != 0)
671 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
672 if (which_alternative != 1)
673 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
674 return \"\";
675 "
676 [(set_attr "conds" "use")
677 (set_attr "length" "6,6,10")]
678 )
680 (define_insn "*thumb2_cond_arith"
681 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
682 (match_operator:SI 5 "shiftable_operator"
683 [(match_operator:SI 4 "arm_comparison_operator"
684 [(match_operand:SI 2 "s_register_operand" "r,r")
685 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
686 (match_operand:SI 1 "s_register_operand" "0,?r")]))
687 (clobber (reg:CC CC_REGNUM))]
688 "TARGET_THUMB2"
689 "*
690 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
691 return \"%i5\\t%0, %1, %2, lsr #31\";
693 output_asm_insn (\"cmp\\t%2, %3\", operands);
694 if (GET_CODE (operands[5]) == AND)
695 {
696 output_asm_insn (\"ite\\t%D4\", operands);
697 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
698 }
699 else if (GET_CODE (operands[5]) == MINUS)
700 {
701 output_asm_insn (\"ite\\t%D4\", operands);
702 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
703 }
704 else if (which_alternative != 0)
705 {
706 output_asm_insn (\"ite\\t%D4\", operands);
707 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
708 }
709 else
710 output_asm_insn (\"it\\t%d4\", operands);
711 return \"%i5%d4\\t%0, %1, #1\";
712 "
713 [(set_attr "conds" "clob")
714 (set_attr "length" "14")]
715 )
717 (define_insn "*thumb2_cond_sub"
718 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
719 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
720 (match_operator:SI 4 "arm_comparison_operator"
721 [(match_operand:SI 2 "s_register_operand" "r,r")
722 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
723 (clobber (reg:CC CC_REGNUM))]
724 "TARGET_THUMB2"
725 "*
726 output_asm_insn (\"cmp\\t%2, %3\", operands);
727 if (which_alternative != 0)
728 {
729 output_asm_insn (\"ite\\t%D4\", operands);
730 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
731 }
732 else
733 output_asm_insn (\"it\\t%d4\", operands);
734 return \"sub%d4\\t%0, %1, #1\";
735 "
736 [(set_attr "conds" "clob")
737 (set_attr "length" "10,14")]
738 )
740 (define_insn "*thumb2_negscc"
741 [(set (match_operand:SI 0 "s_register_operand" "=r")
742 (neg:SI (match_operator 3 "arm_comparison_operator"
743 [(match_operand:SI 1 "s_register_operand" "r")
744 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
745 (clobber (reg:CC CC_REGNUM))]
746 "TARGET_THUMB2"
747 "*
748 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
749 return \"asr\\t%0, %1, #31\";
751 if (GET_CODE (operands[3]) == NE)
752 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
754 output_asm_insn (\"cmp\\t%1, %2\", operands);
755 output_asm_insn (\"ite\\t%D3\", operands);
756 output_asm_insn (\"mov%D3\\t%0, #0\", operands);
757 return \"mvn%d3\\t%0, #0\";
758 "
759 [(set_attr "conds" "clob")
760 (set_attr "length" "14")]
761 )
763 (define_insn "*thumb2_movcond"
764 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
765 (if_then_else:SI
766 (match_operator 5 "arm_comparison_operator"
767 [(match_operand:SI 3 "s_register_operand" "r,r,r")
768 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
769 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
770 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
771 (clobber (reg:CC CC_REGNUM))]
772 "TARGET_THUMB2"
773 "*
774 if (GET_CODE (operands[5]) == LT
775 && (operands[4] == const0_rtx))
776 {
777 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
778 {
779 if (operands[2] == const0_rtx)
780 return \"and\\t%0, %1, %3, asr #31\";
781 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
782 }
783 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
784 {
785 if (operands[1] == const0_rtx)
786 return \"bic\\t%0, %2, %3, asr #31\";
787 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
788 }
789 /* The only case that falls through to here is when both ops 1 & 2
790 are constants. */
791 }
793 if (GET_CODE (operands[5]) == GE
794 && (operands[4] == const0_rtx))
795 {
796 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
797 {
798 if (operands[2] == const0_rtx)
799 return \"bic\\t%0, %1, %3, asr #31\";
800 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
801 }
802 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
803 {
804 if (operands[1] == const0_rtx)
805 return \"and\\t%0, %2, %3, asr #31\";
806 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
807 }
808 /* The only case that falls through to here is when both ops 1 & 2
809 are constants. */
810 }
811 if (GET_CODE (operands[4]) == CONST_INT
812 && !const_ok_for_arm (INTVAL (operands[4])))
813 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
814 else
815 output_asm_insn (\"cmp\\t%3, %4\", operands);
816 switch (which_alternative)
817 {
818 case 0:
819 output_asm_insn (\"it\\t%D5\", operands);
820 break;
821 case 1:
822 output_asm_insn (\"it\\t%d5\", operands);
823 break;
824 case 2:
825 output_asm_insn (\"ite\\t%d5\", operands);
826 break;
827 default:
828 abort();
829 }
830 if (which_alternative != 0)
831 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
832 if (which_alternative != 1)
833 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
834 return \"\";
835 "
836 [(set_attr "conds" "clob")
837 (set_attr "length" "10,10,14")]
838 )
840 ;; Zero and sign extension instructions.
842 (define_insn_and_split "*thumb2_zero_extendsidi2"
843 [(set (match_operand:DI 0 "s_register_operand" "=r")
844 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
845 "TARGET_THUMB2"
846 "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
847 "&& reload_completed"
848 [(set (match_dup 0) (match_dup 1))]
849 "
850 {
851 rtx lo_part = gen_lowpart (SImode, operands[0]);
852 if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
853 emit_move_insn (lo_part, operands[1]);
854 operands[0] = gen_highpart (SImode, operands[0]);
855 operands[1] = const0_rtx;
856 }
857 "
858 [(set_attr "length" "8")
859 (set_attr "ce_count" "2")
860 (set_attr "predicable" "yes")]
861 )
863 (define_insn_and_split "*thumb2_zero_extendhidi2"
864 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
865 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
866 "TARGET_THUMB2"
867 "@
868 uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
869 ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
870 "&& reload_completed"
871 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
872 (set (match_dup 2) (match_dup 3))]
873 "
874 {
875 operands[2] = gen_highpart (SImode, operands[0]);
876 operands[0] = gen_lowpart (SImode, operands[0]);
877 operands[3] = const0_rtx;
878 }
879 "
880 [(set_attr "length" "8")
881 (set_attr "ce_count" "2")
882 (set_attr "predicable" "yes")
883 (set_attr "type" "*,load_byte")
884 (set_attr "pool_range" "*,4092")
885 (set_attr "neg_pool_range" "*,250")]
886 )
888 (define_insn_and_split "*thumb2_zero_extendqidi2"
889 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
890 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
891 "TARGET_THUMB2"
892 "@
893 uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
894 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
895 "&& reload_completed"
896 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2) (match_dup 3))]
898 "
899 {
900 operands[2] = gen_highpart (SImode, operands[0]);
901 operands[0] = gen_lowpart (SImode, operands[0]);
902 operands[3] = const0_rtx;
903 }
904 "
905 [(set_attr "length" "8")
906 (set_attr "ce_count" "2")
907 (set_attr "predicable" "yes")
908 (set_attr "type" "*,load_byte")
909 (set_attr "pool_range" "*,4092")
910 (set_attr "neg_pool_range" "*,250")]
911 )
913 (define_insn_and_split "*thumb2_extendsidi2"
914 [(set (match_operand:DI 0 "s_register_operand" "=r")
915 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
916 "TARGET_THUMB2"
917 "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
918 "&& reload_completed"
919 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
920 {
921 rtx lo_part = gen_lowpart (SImode, operands[0]);
923 if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
924 emit_move_insn (lo_part, operands[1]);
925 operands[0] = gen_highpart (SImode, operands[0]);
926 }
927 [(set_attr "length" "8")
928 (set_attr "ce_count" "2")
929 (set_attr "shift" "1")
930 (set_attr "predicable" "yes")]
931 )
933 (define_insn_and_split "*thumb2_extendhidi2"
934 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
935 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
936 "TARGET_THUMB2"
937 "@
938 sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
939 ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
940 "&& reload_completed"
941 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
942 (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
943 "
944 {
945 operands[2] = gen_highpart (SImode, operands[0]);
946 operands[0] = gen_lowpart (SImode, operands[0]);
947 }
948 "
949 [(set_attr "length" "8")
950 (set_attr "ce_count" "2")
951 (set_attr "predicable" "yes")
952 (set_attr "type" "*,load_byte")
953 (set_attr "pool_range" "*,4092")
954 (set_attr "neg_pool_range" "*,250")]
955 )
957 (define_insn_and_split "*thumb2_extendqidi2"
958 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
959 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
960 "TARGET_THUMB2"
961 "@
962 sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
963 ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
964 "&& reload_completed"
965 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
966 (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
967 "
968 {
969 operands[2] = gen_highpart (SImode, operands[0]);
970 operands[0] = gen_lowpart (SImode, operands[0]);
971 }
972 "
973 [(set_attr "length" "8")
974 (set_attr "ce_count" "2")
975 (set_attr "predicable" "yes")
976 (set_attr "type" "*,load_byte")
977 (set_attr "pool_range" "*,4092")
978 (set_attr "neg_pool_range" "*,250")]
979 )
981 ;; All supported Thumb2 implementations are armv6, so only that case is
982 ;; provided.
983 (define_insn "*thumb2_extendqisi_v6"
984 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
985 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
986 "TARGET_THUMB2 && arm_arch6"
987 "@
988 sxtb%?\\t%0, %1
989 ldr%(sb%)\\t%0, %1"
990 [(set_attr "type" "alu_shift,load_byte")
991 (set_attr "predicable" "yes")
992 (set_attr "pool_range" "*,4096")
993 (set_attr "neg_pool_range" "*,250")]
994 )
996 (define_insn "*thumb2_zero_extendhisi2_v6"
997 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
998 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
999 "TARGET_THUMB2 && arm_arch6"
1000 "@
1001 uxth%?\\t%0, %1
1002 ldr%(h%)\\t%0, %1"
1003 [(set_attr "type" "alu_shift,load_byte")
1004 (set_attr "predicable" "yes")
1005 (set_attr "pool_range" "*,4096")
1006 (set_attr "neg_pool_range" "*,250")]
1007 )
1009 (define_insn "*thumb2_zero_extendqisi2_v6"
1010 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1011 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1012 "TARGET_THUMB2 && arm_arch6"
1013 "@
1014 uxtb%(%)\\t%0, %1
1015 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
1016 [(set_attr "type" "alu_shift,load_byte")
1017 (set_attr "predicable" "yes")
1018 (set_attr "pool_range" "*,4096")
1019 (set_attr "neg_pool_range" "*,250")]
1020 )
1022 (define_insn "thumb2_casesi_internal"
1023 [(parallel [(set (pc)
1024 (if_then_else
1025 (leu (match_operand:SI 0 "s_register_operand" "r")
1026 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1027 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1028 (label_ref (match_operand 2 "" ""))))
1029 (label_ref (match_operand 3 "" ""))))
1030 (clobber (reg:CC CC_REGNUM))
1031 (clobber (match_scratch:SI 4 "=&r"))
1032 (use (label_ref (match_dup 2)))])]
1033 "TARGET_THUMB2 && !flag_pic"
1034 "* return thumb2_output_casesi(operands);"
1035 [(set_attr "conds" "clob")
1036 (set_attr "length" "16")]
1037 )
1039 (define_insn "thumb2_casesi_internal_pic"
1040 [(parallel [(set (pc)
1041 (if_then_else
1042 (leu (match_operand:SI 0 "s_register_operand" "r")
1043 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1044 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1045 (label_ref (match_operand 2 "" ""))))
1046 (label_ref (match_operand 3 "" ""))))
1047 (clobber (reg:CC CC_REGNUM))
1048 (clobber (match_scratch:SI 4 "=&r"))
1049 (clobber (match_scratch:SI 5 "=r"))
1050 (use (label_ref (match_dup 2)))])]
1051 "TARGET_THUMB2 && flag_pic"
1052 "* return thumb2_output_casesi(operands);"
1053 [(set_attr "conds" "clob")
1054 (set_attr "length" "20")]
1055 )
1057 ;; Note: this is not predicable, to avoid issues with linker-generated
1058 ;; interworking stubs.
1059 (define_insn "*thumb2_return"
1060 [(return)]
1061 "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
1062 "*
1063 {
1064 return output_return_instruction (const_true_rtx, TRUE, FALSE);
1065 }"
1066 [(set_attr "type" "load1")
1067 (set_attr "length" "12")]
1068 )
1070 (define_insn_and_split "thumb2_eh_return"
1071 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1072 VUNSPEC_EH_RETURN)
1073 (clobber (match_scratch:SI 1 "=&r"))]
1074 "TARGET_THUMB2"
1075 "#"
1076 "&& reload_completed"
1077 [(const_int 0)]
1078 "
1079 {
1080 thumb_set_return_address (operands[0], operands[1]);
1081 DONE;
1082 }"
1083 )
1085 (define_insn "*thumb2_alusi3_short"
1086 [(set (match_operand:SI 0 "s_register_operand" "=l")
1087 (match_operator:SI 3 "thumb_16bit_operator"
1088 [(match_operand:SI 1 "s_register_operand" "0")
1089 (match_operand:SI 2 "s_register_operand" "l")]))
1090 (clobber (reg:CC CC_REGNUM))]
1091 "TARGET_THUMB2 && reload_completed
1092 && GET_CODE(operands[3]) != PLUS
1093 && GET_CODE(operands[3]) != MINUS"
1094 "%I3%!\\t%0, %1, %2"
1095 [(set_attr "predicable" "yes")
1096 (set_attr "length" "2")]
1097 )
1099 ;; Similarly for 16-bit shift instructions
1100 ;; There is no 16-bit rotate by immediate instruction.
1101 (define_peephole2
1102 [(set (match_operand:SI 0 "low_register_operand" "")
1103 (match_operator:SI 3 "shift_operator"
1104 [(match_operand:SI 1 "low_register_operand" "")
1105 (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1106 "TARGET_THUMB2
1107 && peep2_regno_dead_p(0, CC_REGNUM)
1108 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1109 || REG_P(operands[2]))"
1110 [(parallel
1111 [(set (match_dup 0)
1112 (match_op_dup 3
1113 [(match_dup 1)
1114 (match_dup 2)]))
1115 (clobber (reg:CC CC_REGNUM))])]
1116 ""
1117 )
1119 (define_insn "*thumb2_shiftsi3_short"
1120 [(set (match_operand:SI 0 "low_register_operand" "=l")
1121 (match_operator:SI 3 "shift_operator"
1122 [(match_operand:SI 1 "low_register_operand" "l")
1123 (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1124 (clobber (reg:CC CC_REGNUM))]
1125 "TARGET_THUMB2 && reload_completed
1126 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1127 || REG_P(operands[2]))"
1128 "* return arm_output_shift(operands, 2);"
1129 [(set_attr "predicable" "yes")
1130 (set_attr "shift" "1")
1131 (set_attr "length" "2")
1132 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1133 (const_string "alu_shift")
1134 (const_string "alu_shift_reg")))]
1135 )
1137 ;; 16-bit load immediate
1138 (define_peephole2
1139 [(set (match_operand:QHSI 0 "low_register_operand" "")
1140 (match_operand:QHSI 1 "const_int_operand" ""))]
1141 "TARGET_THUMB2
1142 && peep2_regno_dead_p(0, CC_REGNUM)
1143 && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1144 [(parallel
1145 [(set (match_dup 0)
1146 (match_dup 1))
1147 (clobber (reg:CC CC_REGNUM))])]
1148 ""
1149 )
1151 (define_insn "*thumb2_mov<mode>_shortim"
1152 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1153 (match_operand:QHSI 1 "const_int_operand" "I"))
1154 (clobber (reg:CC CC_REGNUM))]
1155 "TARGET_THUMB2 && reload_completed"
1156 "mov%!\t%0, %1"
1157 [(set_attr "predicable" "yes")
1158 (set_attr "length" "2")]
1159 )
1161 ;; 16-bit add/sub immediate
1162 (define_peephole2
1163 [(set (match_operand:SI 0 "low_register_operand" "")
1164 (plus:SI (match_operand:SI 1 "low_register_operand" "")
1165 (match_operand:SI 2 "const_int_operand" "")))]
1166 "TARGET_THUMB2
1167 && peep2_regno_dead_p(0, CC_REGNUM)
1168 && ((rtx_equal_p(operands[0], operands[1])
1169 && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1170 || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1171 [(parallel
1172 [(set (match_dup 0)
1173 (plus:SI (match_dup 1)
1174 (match_dup 2)))
1175 (clobber (reg:CC CC_REGNUM))])]
1176 ""
1177 )
1179 (define_insn "*thumb2_addsi_short"
1180 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1181 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1182 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1183 (clobber (reg:CC CC_REGNUM))]
1184 "TARGET_THUMB2 && reload_completed"
1185 "*
1186 HOST_WIDE_INT val;
1188 if (GET_CODE (operands[2]) == CONST_INT)
1189 val = INTVAL(operands[2]);
1190 else
1191 val = 0;
1193 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1194 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1195 return \"sub%!\\t%0, %1, #%n2\";
1196 else
1197 return \"add%!\\t%0, %1, %2\";
1198 "
1199 [(set_attr "predicable" "yes")
1200 (set_attr "length" "2")]
1201 )
1203 (define_insn "divsi3"
1204 [(set (match_operand:SI 0 "s_register_operand" "=r")
1205 (div:SI (match_operand:SI 1 "s_register_operand" "r")
1206 (match_operand:SI 2 "s_register_operand" "r")))]
1207 "TARGET_THUMB2 && arm_arch_hwdiv"
1208 "sdiv%?\t%0, %1, %2"
1209 [(set_attr "predicable" "yes")
1210 (set_attr "insn" "sdiv")]
1211 )
1213 (define_insn "udivsi3"
1214 [(set (match_operand:SI 0 "s_register_operand" "=r")
1215 (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
1216 (match_operand:SI 2 "s_register_operand" "r")))]
1217 "TARGET_THUMB2 && arm_arch_hwdiv"
1218 "udiv%?\t%0, %1, %2"
1219 [(set_attr "predicable" "yes")
1220 (set_attr "insn" "udiv")]
1221 )
1223 (define_insn "*thumb2_subsi_short"
1224 [(set (match_operand:SI 0 "low_register_operand" "=l")
1225 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1226 (match_operand:SI 2 "low_register_operand" "l")))
1227 (clobber (reg:CC CC_REGNUM))]
1228 "TARGET_THUMB2 && reload_completed"
1229 "sub%!\\t%0, %1, %2"
1230 [(set_attr "predicable" "yes")
1231 (set_attr "length" "2")]
1232 )
1234 (define_peephole2
1235 [(set (match_operand:CC 0 "cc_register" "")
1236 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1237 (match_operand:SI 2 "const_int_operand" "")))]
1238 "TARGET_THUMB2
1239 && peep2_reg_dead_p (1, operands[1])
1240 && satisfies_constraint_Pw (operands[2])"
1241 [(parallel
1242 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1243 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1244 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1245 )
1247 (define_peephole2
1248 [(match_scratch:SI 3 "l")
1249 (set (match_operand:CC 0 "cc_register" "")
1250 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1251 (match_operand:SI 2 "const_int_operand" "")))]
1252 "TARGET_THUMB2
1253 && satisfies_constraint_Px (operands[2])"
1254 [(parallel
1255 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1256 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1257 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1258 )
1260 (define_insn "*thumb2_addsi3_compare0"
1261 [(set (reg:CC_NOOV CC_REGNUM)
1262 (compare:CC_NOOV
1263 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1264 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1265 (const_int 0)))
1266 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1267 (plus:SI (match_dup 1) (match_dup 2)))]
1268 "TARGET_THUMB2"
1269 "*
1270 HOST_WIDE_INT val;
1272 if (GET_CODE (operands[2]) == CONST_INT)
1273 val = INTVAL (operands[2]);
1274 else
1275 val = 0;
1277 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1278 return \"subs\\t%0, %1, #%n2\";
1279 else
1280 return \"adds\\t%0, %1, %2\";
1281 "
1282 [(set_attr "conds" "set")
1283 (set_attr "length" "2,2,4")]
1284 )
1286 (define_insn "*thumb2_addsi3_compare0_scratch"
1287 [(set (reg:CC_NOOV CC_REGNUM)
1288 (compare:CC_NOOV
1289 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1290 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1291 (const_int 0)))]
1292 "TARGET_THUMB2"
1293 "*
1294 HOST_WIDE_INT val;
1296 if (GET_CODE (operands[1]) == CONST_INT)
1297 val = INTVAL (operands[1]);
1298 else
1299 val = 0;
1301 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1302 return \"cmp\\t%0, #%n1\";
1303 else
1304 return \"cmn\\t%0, %1\";
1305 "
1306 [(set_attr "conds" "set")
1307 (set_attr "length" "2,4")]
1308 )
1310 ;; 16-bit encodings of "muls" and "mul<c>". We only use these when
1311 ;; optimizing for size since "muls" is slow on all known
1312 ;; implementations and since "mul<c>" will be generated by
1313 ;; "*arm_mulsi3_v6" anyhow. The assembler will use a 16-bit encoding
1314 ;; for "mul<c>" whenever possible anyhow.
1315 (define_peephole2
1316 [(set (match_operand:SI 0 "low_register_operand" "")
1317 (mult:SI (match_operand:SI 1 "low_register_operand" "")
1318 (match_dup 0)))]
1319 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1320 [(parallel
1321 [(set (match_dup 0)
1322 (mult:SI (match_dup 0) (match_dup 1)))
1323 (clobber (reg:CC CC_REGNUM))])]
1324 ""
1325 )
1327 (define_peephole2
1328 [(set (match_operand:SI 0 "low_register_operand" "")
1329 (mult:SI (match_dup 0)
1330 (match_operand:SI 1 "low_register_operand" "")))]
1331 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1332 [(parallel
1333 [(set (match_dup 0)
1334 (mult:SI (match_dup 0) (match_dup 1)))
1335 (clobber (reg:CC CC_REGNUM))])]
1336 ""
1337 )
1339 (define_insn "*thumb2_mulsi_short"
1340 [(set (match_operand:SI 0 "low_register_operand" "=l")
1341 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1342 (match_operand:SI 2 "low_register_operand" "l")))
1343 (clobber (reg:CC CC_REGNUM))]
1344 "TARGET_THUMB2 && optimize_size && reload_completed"
1345 "mul%!\\t%0, %2, %0"
1346 [(set_attr "predicable" "yes")
1347 (set_attr "length" "2")
1348 (set_attr "insn" "muls")])
1350 (define_insn "*thumb2_mulsi_short_compare0"
1351 [(set (reg:CC_NOOV CC_REGNUM)
1352 (compare:CC_NOOV
1353 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1354 (match_operand:SI 2 "register_operand" "l"))
1355 (const_int 0)))
1356 (set (match_operand:SI 0 "register_operand" "=l")
1357 (mult:SI (match_dup 1) (match_dup 2)))]
1358 "TARGET_THUMB2 && optimize_size"
1359 "muls\\t%0, %2, %0"
1360 [(set_attr "length" "2")
1361 (set_attr "insn" "muls")])
1363 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1364 [(set (reg:CC_NOOV CC_REGNUM)
1365 (compare:CC_NOOV
1366 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1367 (match_operand:SI 2 "register_operand" "l"))
1368 (const_int 0)))
1369 (clobber (match_scratch:SI 0 "=l"))]
1370 "TARGET_THUMB2 && optimize_size"
1371 "muls\\t%0, %2, %0"
1372 [(set_attr "length" "2")
1373 (set_attr "insn" "muls")])
1375 (define_insn "*thumb2_cbz"
1376 [(set (pc) (if_then_else
1377 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1378 (const_int 0))
1379 (label_ref (match_operand 1 "" ""))
1380 (pc)))
1381 (clobber (reg:CC CC_REGNUM))]
1382 "TARGET_THUMB2"
1383 "*
1384 if (get_attr_length (insn) == 2)
1385 return \"cbz\\t%0, %l1\";
1386 else
1387 return \"cmp\\t%0, #0\;beq\\t%l1\";
1388 "
1389 [(set (attr "length")
1390 (if_then_else
1391 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1392 (le (minus (match_dup 1) (pc)) (const_int 128))
1393 (eq (symbol_ref ("which_alternative")) (const_int 0)))
1394 (const_int 2)
1395 (const_int 8)))]
1396 )
1398 (define_insn "*thumb2_cbnz"
1399 [(set (pc) (if_then_else
1400 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1401 (const_int 0))
1402 (label_ref (match_operand 1 "" ""))
1403 (pc)))
1404 (clobber (reg:CC CC_REGNUM))]
1405 "TARGET_THUMB2"
1406 "*
1407 if (get_attr_length (insn) == 2)
1408 return \"cbnz\\t%0, %l1\";
1409 else
1410 return \"cmp\\t%0, #0\;bne\\t%l1\";
1411 "
1412 [(set (attr "length")
1413 (if_then_else
1414 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1415 (le (minus (match_dup 1) (pc)) (const_int 128))
1416 (eq (symbol_ref ("which_alternative")) (const_int 0)))
1417 (const_int 2)
1418 (const_int 8)))]
1419 )
1421 ;; 16-bit complement
1422 (define_peephole2
1423 [(set (match_operand:SI 0 "low_register_operand" "")
1424 (not:SI (match_operand:SI 1 "low_register_operand" "")))]
1425 "TARGET_THUMB2
1426 && peep2_regno_dead_p(0, CC_REGNUM)"
1427 [(parallel
1428 [(set (match_dup 0)
1429 (not:SI (match_dup 1)))
1430 (clobber (reg:CC CC_REGNUM))])]
1431 ""
1432 )
1434 (define_insn "*thumb2_one_cmplsi2_short"
1435 [(set (match_operand:SI 0 "low_register_operand" "=l")
1436 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1437 (clobber (reg:CC CC_REGNUM))]
1438 "TARGET_THUMB2 && reload_completed"
1439 "mvn%!\t%0, %1"
1440 [(set_attr "predicable" "yes")
1441 (set_attr "length" "2")]
1442 )
1444 ;; 16-bit negate
1445 (define_peephole2
1446 [(set (match_operand:SI 0 "low_register_operand" "")
1447 (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1448 "TARGET_THUMB2
1449 && peep2_regno_dead_p(0, CC_REGNUM)"
1450 [(parallel
1451 [(set (match_dup 0)
1452 (neg:SI (match_dup 1)))
1453 (clobber (reg:CC CC_REGNUM))])]
1454 ""
1455 )
1457 (define_insn "*thumb2_negsi2_short"
1458 [(set (match_operand:SI 0 "low_register_operand" "=l")
1459 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1460 (clobber (reg:CC CC_REGNUM))]
1461 "TARGET_THUMB2 && reload_completed"
1462 "neg%!\t%0, %1"
1463 [(set_attr "predicable" "yes")
1464 (set_attr "length" "2")]
1465 )
1467 (define_insn "orsi_notsi_si"
1468 [(set (match_operand:SI 0 "s_register_operand" "=r")
1469 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1470 (match_operand:SI 1 "s_register_operand" "r")))]
1471 "TARGET_THUMB2"
1472 "orn%?\\t%0, %1, %2"
1473 [(set_attr "predicable" "yes")]
1474 )
1476 (define_insn "*thumb_orsi_not_shiftsi_si"
1477 [(set (match_operand:SI 0 "s_register_operand" "=r")
1478 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1479 [(match_operand:SI 2 "s_register_operand" "r")
1480 (match_operand:SI 3 "const_int_operand" "M")]))
1481 (match_operand:SI 1 "s_register_operand" "r")))]
1482 "TARGET_THUMB2"
1483 "orn%?\\t%0, %1, %2%S4"
1484 [(set_attr "predicable" "yes")
1485 (set_attr "shift" "2")
1486 (set_attr "type" "alu_shift")]
1487 )
1489 (define_insn_and_split "*thumb2_iorsi3"
1490 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1491 (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
1492 (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
1493 "TARGET_THUMB2"
1494 "@
1495 orr%?\\t%0, %1, %2
1496 orn%?\\t%0, %1, #%B2
1497 #"
1498 "TARGET_THUMB2
1499 && GET_CODE (operands[2]) == CONST_INT
1500 && !(const_ok_for_arm (INTVAL (operands[2]))
1501 || const_ok_for_arm (~INTVAL (operands[2])))"
1502 [(clobber (const_int 0))]
1503 "
1504 arm_split_constant (IOR, SImode, curr_insn,
1505 INTVAL (operands[2]), operands[0], operands[1], 0);
1506 DONE;
1507 "
1508 [(set_attr "length" "4,4,16")
1509 (set_attr "predicable" "yes")]
1510 )
1512 (define_peephole2
1513 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1514 (compare:CC_NOOV (zero_extract:SI
1515 (match_operand:SI 1 "low_register_operand" "")
1516 (const_int 1)
1517 (match_operand:SI 2 "const_int_operand" ""))
1518 (const_int 0)))
1519 (match_scratch:SI 3 "l")
1520 (set (pc)
1521 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1522 [(match_dup 0) (const_int 0)])
1523 (match_operand 5 "" "")
1524 (match_operand 6 "" "")))]
1525 "TARGET_THUMB2
1526 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1527 [(parallel [(set (match_dup 0)
1528 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1529 (const_int 0)))
1530 (clobber (match_dup 3))])
1531 (set (pc)
1532 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1533 (match_dup 5) (match_dup 6)))]
1534 "
1535 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1536 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1537 VOIDmode, operands[0], const0_rtx);
1538 ")