1 ;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
3 ;; This file is free software; you can redistribute it and/or modify it under
4 ;; the terms of the GNU General Public License as published by the Free
5 ;; Software Foundation; either version 3 of the License, or (at your option)
8 ;; This file is distributed in the hope that it will be useful, but WITHOUT
9 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 ;; You should have received a copy of the GNU General Public License
14 ;; along with GCC; see the file COPYING3. If not see
15 ;; <http://www.gnu.org/licenses/>.
18 ;; This includes expands for all the intrinsics.
19 ;; spu_expand_builtin looks at the mode of match_operand.
24 (define_expand "spu_lqd"
25 [(set (match_operand:TI 0 "spu_reg_operand" "")
26 (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
27 (match_operand:SI 2 "spu_nonmem_operand" ""))
31 if (GET_CODE (operands[2]) == CONST_INT
32 && (INTVAL (operands[2]) & 15) != 0)
33 operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
34 if (GET_CODE (operands[2]) != CONST_INT)
36 rtx op2 = operands[2];
37 operands[2] = force_reg (Pmode, operands[2]);
38 if (!ALIGNED_SYMBOL_REF_P (op2))
39 emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
43 (define_expand "spu_lqx"
44 [(set (match_operand:TI 0 "spu_reg_operand" "")
45 (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
46 (match_operand:SI 2 "spu_reg_operand" ""))
51 (define_expand "spu_lqa"
52 [(set (match_operand:TI 0 "spu_reg_operand" "")
53 (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
57 if (GET_CODE (operands[1]) == CONST_INT
58 && (INTVAL (operands[1]) & 15) != 0)
59 operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
62 (define_expand "spu_lqr"
63 [(set (match_operand:TI 0 "spu_reg_operand" "")
64 (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
69 (define_expand "spu_stqd"
70 [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
71 (match_operand:SI 2 "spu_nonmem_operand" ""))
73 (match_operand:TI 0 "spu_reg_operand" "r,r"))]
76 if (GET_CODE (operands[2]) == CONST_INT
77 && (INTVAL (operands[2]) & 15) != 0)
78 operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
79 if (GET_CODE (operands[2]) != CONST_INT)
81 rtx op2 = operands[2];
82 operands[2] = force_reg (Pmode, operands[2]);
83 if (!ALIGNED_SYMBOL_REF_P (op2))
84 emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
88 (define_expand "spu_stqx"
89 [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
90 (match_operand:SI 2 "spu_reg_operand" ""))
92 (match_operand:TI 0 "spu_reg_operand" "r"))]
96 (define_expand "spu_stqa"
97 [(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
99 (match_operand:TI 0 "spu_reg_operand" "r"))]
102 if (GET_CODE (operands[1]) == CONST_INT
103 && (INTVAL (operands[1]) & 15) != 0)
104 operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
107 (define_expand "spu_stqr"
108 [(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
110 (match_operand:TI 0 "spu_reg_operand" ""))]
115 ;; generate control word
117 (define_expand "spu_cbx"
118 [(set (match_operand:TI 0 "spu_reg_operand" "")
119 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
120 (match_operand:SI 2 "spu_nonmem_operand" "")
121 (const_int 1)] UNSPEC_CPAT))]
125 (define_expand "spu_chx"
126 [(set (match_operand:TI 0 "spu_reg_operand" "")
127 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
128 (match_operand:SI 2 "spu_nonmem_operand" "")
129 (const_int 2)] UNSPEC_CPAT))]
133 (define_expand "spu_cwx"
134 [(set (match_operand:TI 0 "spu_reg_operand" "")
135 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
136 (match_operand:SI 2 "spu_nonmem_operand" "")
137 (const_int 4)] UNSPEC_CPAT))]
141 (define_expand "spu_cdx"
142 [(set (match_operand:TI 0 "spu_reg_operand" "")
143 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
144 (match_operand:SI 2 "spu_nonmem_operand" "")
145 (const_int 8)] UNSPEC_CPAT))]
151 ;; Constant formation
153 (define_expand "spu_ilhu"
154 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
155 (const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))]
157 "{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16))));
163 (define_expand "spu_sfh"
164 [(set (match_operand:V8HI 0 "spu_reg_operand" "")
165 (minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "")
166 (match_operand:V8HI 1 "spu_reg_operand" "")))]
170 (define_expand "spu_sf"
171 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
172 (minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "")
173 (match_operand:V4SI 1 "spu_reg_operand" "")))]
177 (define_expand "spu_sfx"
178 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
179 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
180 (match_operand:V4SI 1 "spu_reg_operand" "")
181 (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))]
185 (define_expand "spu_bg"
186 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
187 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
188 (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))]
192 (define_expand "spu_bgx"
193 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
194 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
195 (match_operand:V4SI 1 "spu_reg_operand" "")
196 (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))]
200 (define_insn "spu_mpya"
201 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
206 (match_operand:V8HI 1 "spu_reg_operand" "r")
207 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
210 (match_operand:V8HI 2 "spu_reg_operand" "r")
211 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
212 (match_operand:V4SI 3 "spu_reg_operand" "r")))]
215 [(set_attr "type" "fp7")])
217 (define_insn "spu_mpyh"
218 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
223 (match_operand:V8HI 1 "spu_reg_operand" "r")
224 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
227 (match_operand:V8HI 2 "spu_reg_operand" "r")
228 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
229 (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
232 [(set_attr "type" "fp7")])
234 (define_insn "spu_mpys"
235 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
240 (match_operand:V8HI 1 "spu_reg_operand" "r")
241 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
244 (match_operand:V8HI 2 "spu_reg_operand" "r")
245 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
246 (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
249 [(set_attr "type" "fp7")])
251 (define_insn "spu_mpyhhau"
252 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
257 (match_operand:V8HI 1 "spu_reg_operand" "r")
258 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
261 (match_operand:V8HI 2 "spu_reg_operand" "r")
262 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
263 (match_operand:V4SI 3 "spu_reg_operand" "0")))]
266 [(set_attr "type" "fp7")])
268 (define_insn "spu_mpyhha"
269 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
274 (match_operand:V8HI 1 "spu_reg_operand" "r")
275 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
278 (match_operand:V8HI 2 "spu_reg_operand" "r")
279 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
280 (match_operand:V4SI 3 "spu_reg_operand" "0")))]
283 [(set_attr "type" "fp7")])
286 (define_insn "spu_fsmb"
287 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r")
288 (unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))]
293 [(set_attr "type" "shuf")])
295 (define_insn "spu_fsmh"
296 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
297 (unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))]
300 [(set_attr "type" "shuf")])
302 (define_insn "spu_fsm"
303 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
304 (unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))]
307 [(set_attr "type" "shuf")])
311 (define_insn "spu_gbb"
312 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
313 (unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))]
316 [(set_attr "type" "shuf")])
318 (define_insn "spu_gbh"
319 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
320 (unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))]
323 [(set_attr "type" "shuf")])
325 (define_insn "spu_gb"
326 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
327 (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))]
330 [(set_attr "type" "shuf")])
332 ;; misc byte operations
333 (define_insn "spu_avgb"
334 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
335 (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
336 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))]
339 [(set_attr "type" "fxb")])
341 (define_insn "spu_absdb"
342 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
343 (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
344 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))]
347 [(set_attr "type" "fxb")])
349 (define_insn "spu_sumb"
350 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
351 (unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r")
352 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))]
355 [(set_attr "type" "fxb")])
358 (define_insn "spu_xsbh"
359 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
362 (match_operand:V16QI 1 "spu_reg_operand" "r")
363 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
364 (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
368 (define_insn "spu_xshw"
369 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
372 (match_operand:V8HI 1 "spu_reg_operand" "r")
373 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
377 (define_insn "spu_xswd"
378 [(set (match_operand:V2DI 0 "spu_reg_operand" "=r")
381 (match_operand:V4SI 1 "spu_reg_operand" "r")
382 (parallel [(const_int 1)(const_int 3)]))))]
388 (define_insn "spu_orx"
389 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
390 (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))]
396 (define_insn "spu_heq"
397 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
398 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)]
404 (define_insn "spu_hgt"
405 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
406 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)]
412 (define_insn "spu_hlgt"
413 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
414 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)]
422 ;; The description below hides the fact that bisled conditionally
423 ;; executes the call depending on the value in channel 0. This was
424 ;; done so that the description would conform to the format of a call
425 ;; insn. Otherwise (if this were not part of call insn), the link
426 ;; register, $lr, would not be saved/restored in the prologue/epilogue.
428 (define_insn "spu_bisled"
430 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
433 (clobber (reg:SI 130))
434 (use (match_operand:SI 1 "address_operand" ""))
435 (use (const_int 0))])]
438 [(set_attr "type" "br")])
440 (define_insn "spu_bisledd"
442 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
445 (clobber (reg:SI 130))
446 (use (match_operand:SI 1 "address_operand" ""))
447 (use (const_int 1))])]
450 [(set_attr "type" "br")])
452 (define_insn "spu_bislede"
454 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
457 (clobber (reg:SI 130))
458 (use (match_operand:SI 1 "address_operand" ""))
459 (use (const_int 2))])]
462 [(set_attr "type" "br")])
465 (define_expand "spu_csflt"
466 [(set (match_operand:V4SF 0 "spu_reg_operand")
467 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
468 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
471 if (GET_CODE (operands[2]) == CONST_INT
472 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
474 error ("spu_convtf expects an integer literal in the range [0, 127].");
475 operands[2] = force_reg (SImode, operands[2]);
477 if (GET_CODE (operands[2]) != CONST_INT)
480 rtx cnv = gen_reg_rtx (V4SFmode);
481 rtx scale = gen_reg_rtx (SImode);
482 rtx op2 = force_reg (SImode, operands[2]);
483 rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
484 emit_insn (gen_subsi3 (scale, const1_rtx, op2));
485 exp2 = spu_gen_exp2 (V4SFmode, scale);
486 emit_insn (gen_floatv4siv4sf2_mul (cnv, operands[1], m1));
487 emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
491 rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
492 emit_insn (gen_floatv4siv4sf2_div (operands[0], operands[1], exp2));
497 (define_expand "spu_cflts"
498 [(set (match_operand:V4SI 0 "spu_reg_operand")
499 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
500 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
504 if (GET_CODE (operands[2]) == CONST_INT
505 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
507 error ("spu_convts expects an integer literal in the range [0, 127].");
508 operands[2] = force_reg (SImode, operands[2]);
510 exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
511 if (GET_CODE (operands[2]) != CONST_INT)
513 rtx mul = gen_reg_rtx (V4SFmode);
514 emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
515 emit_insn (gen_fix_truncv4sfv4si2 (operands[0], mul));
518 emit_insn (gen_fix_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
522 (define_expand "spu_cuflt"
523 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
524 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
525 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
528 if (GET_CODE (operands[2]) == CONST_INT
529 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
531 error ("spu_convtf expects an integer literal in the range [0, 127].");
532 operands[2] = force_reg (SImode, operands[2]);
534 if (GET_CODE (operands[2]) != CONST_INT)
537 rtx cnv = gen_reg_rtx (V4SFmode);
538 rtx scale = gen_reg_rtx (SImode);
539 rtx op2 = force_reg (SImode, operands[2]);
540 rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
541 emit_insn (gen_subsi3 (scale, const1_rtx, op2));
542 exp2 = spu_gen_exp2 (V4SFmode, scale);
543 emit_insn (gen_floatunsv4siv4sf2_mul (cnv, operands[1], m1));
544 emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
548 rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
549 emit_insn (gen_floatunsv4siv4sf2_div (operands[0], operands[1], exp2));
554 (define_expand "spu_cfltu"
555 [(set (match_operand:V4SI 0 "spu_reg_operand")
556 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
557 (match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
561 if (GET_CODE (operands[2]) == CONST_INT
562 && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
564 error ("spu_convtu expects an integer literal in the range [0, 127].");
565 operands[2] = force_reg (SImode, operands[2]);
567 exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
568 if (GET_CODE (operands[2]) != CONST_INT)
570 rtx mul = gen_reg_rtx (V4SFmode);
571 emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
572 emit_insn (gen_fixuns_truncv4sfv4si2 (operands[0], mul));
575 emit_insn (gen_fixuns_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
579 (define_expand "spu_frds"
580 [(set (match_operand:V4SF 0 "spu_reg_operand" "")
583 (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" ""))
585 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
587 "operands[2] = spu_const(V2SFmode, 0);")
590 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
593 (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r"))
594 (match_operand:V2SF 2 "vec_imm_operand" "i"))
595 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
598 [(set_attr "type" "fpd")])
600 (define_insn "spu_fesd"
601 [(set (match_operand:V2DF 0 "spu_reg_operand" "=r")
604 (match_operand:V4SF 1 "spu_reg_operand" "r")
605 (parallel [(const_int 0)(const_int 2)]))))]
608 [(set_attr "type" "fpd")])
611 (define_insn "spu_stop"
612 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)]
615 [(set_attr "type" "br")])
617 (define_insn "spu_stopd"
618 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r")
619 (match_operand:SI 1 "spu_reg_operand" "r")
620 (match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)]
623 [(set_attr "type" "br")])
625 ;; interrupt disable/enable
626 (define_expand "spu_idisable"
628 [(unspec_volatile [(const_int 0)] UNSPEC_SET_INTR)
629 (clobber (match_dup:SI 0))
630 (clobber (mem:BLK (scratch)))])]
632 "operands[0] = gen_reg_rtx (SImode);")
634 (define_expand "spu_ienable"
636 [(unspec_volatile [(const_int 1)] UNSPEC_SET_INTR)
637 (clobber (match_dup:SI 0))
638 (clobber (mem:BLK (scratch)))])]
640 "operands[0] = gen_reg_rtx (SImode);")
642 (define_insn "set_intr"
643 [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
644 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
645 (clobber (mem:BLK (scratch)))]
647 "ila\t%0,.+8\;bi%I1\t%0"
648 [(set_attr "length" "8")
649 (set_attr "type" "multi0")])
651 (define_insn "set_intr_pic"
652 [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
653 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
654 (clobber (mem:BLK (scratch)))]
656 "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0"
657 [(set_attr "length" "12")
658 (set_attr "type" "multi1")])
660 (define_insn "set_intr_cc"
661 [(cond_exec (match_operator 1 "branch_comparison_operator"
662 [(match_operand 2 "spu_reg_operand" "r")
664 (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
665 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
666 (clobber (mem:BLK (scratch)))]))]
668 "ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0"
669 [(set_attr "length" "8")
670 (set_attr "type" "multi0")])
672 (define_insn "set_intr_cc_pic"
673 [(cond_exec (match_operator 1 "branch_comparison_operator"
674 [(match_operand 2 "spu_reg_operand" "r")
676 (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
677 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
678 (clobber (mem:BLK (scratch)))]))]
680 "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%b2%b1z%I3\t%2,%0"
681 [(set_attr "length" "12")
682 (set_attr "type" "multi1")])
684 (define_insn "set_intr_return"
685 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")] UNSPEC_SET_INTR)
689 [(set_attr "type" "br")])
693 [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPEC_SET_INTR)
694 (clobber (match_operand:SI 1 "spu_reg_operand"))
695 (clobber (mem:BLK (scratch)))])
701 [(unspec_volatile [(match_dup:SI 0)] UNSPEC_SET_INTR)
705 ;; special purpose registers
706 (define_insn "spu_fscrrd"
707 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
708 (unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))]
711 [(set_attr "type" "spr")])
713 (define_insn "spu_fscrwr"
714 [(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)]
717 [(set_attr "type" "spr")])
719 (define_insn "spu_mfspr"
720 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
721 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))]
724 [(set_attr "type" "spr")])
726 (define_insn "spu_mtspr"
727 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
728 (match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)]
731 [(set_attr "type" "spr")])
734 (define_expand "spu_rdch"
735 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
736 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))]
739 if (spu_safe_dma (INTVAL (operands[1])))
741 emit_insn (gen_spu_rdch_clobber (operands[0], operands[1]));
746 (define_expand "spu_rchcnt"
747 [(set (match_operand:SI 0 "spu_reg_operand" "")
748 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))]
751 if (spu_safe_dma (INTVAL (operands[1])))
753 emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1]));
758 (define_expand "spu_wrch"
759 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "")
760 (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)]
763 if (spu_safe_dma (INTVAL (operands[0])))
765 emit_insn (gen_spu_wrch_clobber (operands[0], operands[1]));
770 (define_insn "spu_rdch_noclobber"
771 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
772 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))]
775 [(set_attr "type" "spr")])
777 (define_insn "spu_rchcnt_noclobber"
778 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
779 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))]
782 [(set_attr "type" "spr")])
784 (define_insn "spu_wrch_noclobber"
785 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
786 (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)]
789 [(set_attr "type" "spr")])
791 (define_insn "spu_rdch_clobber"
792 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
793 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))
794 (clobber (mem:BLK (scratch)))]
797 [(set_attr "type" "spr")])
799 (define_insn "spu_rchcnt_clobber"
800 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
801 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))
802 (clobber (mem:BLK (scratch)))]
805 [(set_attr "type" "spr")])
807 (define_insn "spu_wrch_clobber"
808 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
809 (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)
810 (clobber (mem:BLK (scratch)))]
813 [(set_attr "type" "spr")])
815 (define_expand "spu_splats"
816 [(set (match_operand 0 "spu_reg_operand" "")
817 (vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))]
820 spu_builtin_splats(operands);
824 (define_expand "spu_extract"
825 [(set (match_operand 0 "spu_reg_operand" "")
826 (unspec [(match_operand 1 "spu_reg_operand" "")
827 (match_operand 2 "spu_nonmem_operand" "")] 0))]
830 spu_builtin_extract (operands);
834 (define_expand "spu_insert"
835 [(set (match_operand 0 "spu_reg_operand" "")
836 (unspec [(match_operand 1 "spu_reg_operand" "")
837 (match_operand 2 "spu_reg_operand" "")
838 (match_operand:SI 3 "spu_nonmem_operand" "")] 0))]
841 spu_builtin_insert(operands);
845 (define_expand "spu_promote"
846 [(set (match_operand 0 "spu_reg_operand" "")
847 (unspec [(match_operand 1 "spu_reg_operand" "")
848 (match_operand:SI 2 "immediate_operand" "")] 0))]
851 spu_builtin_promote(operands);
855 ;; Currently doing nothing with this but expanding its args.
856 (define_expand "spu_align_hint"
857 [(unspec [(match_operand:SI 0 "address_operand" "")
858 (match_operand:SI 1 "immediate_operand" "")
859 (match_operand:SI 2 "immediate_operand" "")] 0)]