| blob | 64c03da63a782c0fd204bde5fe8b4cac8224c580 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement HARD_REGNO_NREGS. */
1072 int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1088 static bool
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1109 return
1111 else
1113 }
1116 }
1118 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1119 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1120 clobbers the top 64 bits when restoring the bottom 64 bits. */
1122 static bool
1124 {
1126 }
1128 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1129 machine_mode
1131 machine_mode mode)
1132 {
1133 /* Handle modes that fit within single registers. */
1135 {
1138 else
1140 }
1141 /* Fall back to generic for multi-reg and very large modes. */
1142 else
1144 }
1146 /* Return true if calls to DECL should be treated as
1147 long-calls (ie called via a register). */
1148 static bool
1150 {
1152 }
1154 /* Return true if calls to symbol-ref SYM should be treated as
1155 long-calls (ie called via a register). */
1156 bool
1158 {
1160 }
1162 /* Return true if calls to symbol-ref SYM should not go through
1163 plt stubs. */
1165 bool
1167 {
1171 && decl
1172 && (!flag_plt
1178 }
1180 /* Return true if the offsets to a zero/sign-extract operation
1181 represent an expression that matches an extend operation. The
1182 operands represent the paramters from
1184 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1185 bool
1187 rtx extract_imm)
1188 {
1205 }
1207 /* Emit an insn that's a simple single-set. Both the operands must be
1208 known to be valid. */
1211 {
1213 }
1215 /* X and Y are two things to compare using CODE. Emit the compare insn and
1216 return the rtx for register 0 in the proper mode. */
1217 rtx
1219 {
1225 }
1227 /* Build the SYMBOL_REF for __tls_get_addr. */
1231 rtx
1233 {
1237 }
1239 /* Return the TLS model to use for ADDR. */
1241 static enum tls_model
1243 {
1248 {
1252 }
1257 }
1259 /* We'll allow lo_sum's in addresses in our legitimate addresses
1260 so that combine would take care of combining addresses where
1261 necessary, but for generation purposes, we'll generate the address
1262 as :
1263 RTL Absolute
1264 tmp = hi (symbol_ref); adrp x1, foo
1265 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1266 nop
1268 PIC TLS
1269 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1270 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1271 bl __tls_get_addr
1272 nop
1274 Load TLS symbol, depending on TLS mechanism and TLS access model.
1276 Global Dynamic - Traditional TLS:
1277 adrp tmp, :tlsgd:imm
1278 add dest, tmp, #:tlsgd_lo12:imm
1279 bl __tls_get_addr
1281 Global Dynamic - TLS Descriptors:
1282 adrp dest, :tlsdesc:imm
1283 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1284 add dest, dest, #:tlsdesc_lo12:imm
1285 blr tmp
1286 mrs tp, tpidr_el0
1287 add dest, dest, tp
1289 Initial Exec:
1290 mrs tp, tpidr_el0
1291 adrp tmp, :gottprel:imm
1292 ldr dest, [tmp, #:gottprel_lo12:imm]
1293 add dest, dest, tp
1295 Local Exec:
1296 mrs tp, tpidr_el0
1297 add t0, tp, #:tprel_hi12:imm, lsl #12
1298 add t0, t0, #:tprel_lo12_nc:imm
1299 */
1301 static void
1304 {
1306 {
1308 {
1309 /* In ILP32, the mode of dest can be either SImode or DImode. */
1321 }
1328 {
1331 rtx insn;
1332 rtx mem;
1334 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1335 here before rtl expand. Tree IVOPT will generate rtl pattern to
1336 decide rtx costs, in which case pic_offset_table_rtx is not
1337 initialized. For that case no need to generate the first adrp
1338 instruction as the final cost for global variable access is
1339 one instruction. */
1341 {
1342 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1343 using the page base as GOT base, the first page may be wasted,
1344 in the worst scenario, there is only 28K space for GOT).
1346 The generate instruction sequence for accessing global variable
1347 is:
1349 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1351 Only one instruction needed. But we must initialize
1352 pic_offset_table_rtx properly. We generate initialize insn for
1353 every global access, and allow CSE to remove all redundant.
1355 The final instruction sequences will look like the following
1356 for multiply global variables access.
1358 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1360 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1361 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1362 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1363 ... */
1372 }
1375 {
1378 else
1382 }
1383 else
1384 {
1389 }
1391 /* The operand is expected to be MEM. Whenever the related insn
1392 pattern changed, above code which calculate mem should be
1393 updated. */
1399 }
1402 {
1403 /* In ILP32, the mode of dest can be either SImode or DImode,
1404 while the got entry is always of SImode size. The mode of
1405 dest depends on how dest is used: if dest is assigned to a
1406 pointer (e.g. in the memory), it has SImode; it may have
1407 DImode if dest is dereferenced to access the memeory.
1408 This is why we have to handle three different ldr_got_small
1409 patterns here (two patterns for ILP32). */
1411 rtx insn;
1412 rtx mem;
1421 {
1424 else
1428 }
1429 else
1430 {
1435 }
1442 }
1445 {
1453 else
1461 }
1464 {
1467 rtx tp;
1471 /* In ILP32, the got entry is always of SImode size. Unlike
1472 small GOT, the dest is fixed at reg 0. */
1475 else
1485 }
1488 {
1489 /* In ILP32, the mode of dest can be either SImode or DImode,
1490 while the got entry is always of SImode size. The mode of
1491 dest depends on how dest is used: if dest is assigned to a
1492 pointer (e.g. in the memory), it has SImode; it may have
1493 DImode if dest is dereferenced to access the memeory.
1494 This is why we have to handle three different tlsie_small
1495 patterns here (two patterns for ILP32). */
1501 {
1504 else
1505 {
1508 }
1509 }
1510 else
1511 {
1514 }
1519 }
1525 {
1533 {
1556 }
1560 }
1567 {
1572 {
1575 else
1576 {
1579 }
1580 }
1581 else
1582 {
1585 }
1589 }
1593 }
1594 }
1596 /* Emit a move from SRC to DEST. Assume that the move expanders can
1597 handle all moves if !can_create_pseudo_p (). The distinction is
1598 important because, unlike emit_move_insn, the move expanders know
1599 how to force Pmode objects into the constant pool even when the
1600 constant pool address is not itself legitimate. */
1601 static rtx
1603 {
1607 }
1609 /* Split a 128-bit move operation into two 64-bit move operations,
1610 taking care to handle partial overlap of register to register
1611 copies. Special cases are needed when moving between GP regs and
1612 FP regs. SRC can be a register, constant or memory; DST a register
1613 or memory. If either operand is memory it must not have any side
1614 effects. */
1615 void
1617 {
1628 {
1632 /* Handle FP <-> GP regs. */
1634 {
1639 {
1642 }
1643 else
1644 {
1647 }
1649 }
1651 {
1656 {
1659 }
1660 else
1661 {
1664 }
1666 }
1667 }
1674 /* At most one pairing may overlap. */
1676 {
1679 }
1680 else
1681 {
1684 }
1685 }
1687 bool
1689 {
1692 }
1694 /* Split a complex SIMD combine. */
1696 void
1698 {
1710 {
1734 }
1738 }
1740 /* Split a complex SIMD move. */
1742 void
1744 {
1751 {
1757 {
1781 }
1785 }
1786 }
1788 bool
1791 {
1795 }
1798 static rtx
1800 {
1803 else
1804 {
1807 }
1808 }
1811 static rtx
1813 HOST_WIDE_INT offset)
1814 {
1816 {
1817 rtx high;
1818 /* Load the full offset into a register. This
1819 might be improvable in the future. */
1825 }
1827 }
1829 static int
1831 scalar_int_mode mode)
1832 {
1841 {
1845 }
1847 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1848 (with XXXX non-zero). In that case check to see if the move can be done in
1849 a smaller mode. */
1854 {
1858 /* Check if we have to emit a second instruction by checking to see
1859 if any of the upper 32 bits of the original DI mode value is set. */
1870 }
1873 {
1875 {
1880 else
1883 }
1885 }
1887 /* Remaining cases are all for DImode. */
1896 {
1897 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1898 For a 64-bit bitmask try whether changing 16 bits to all ones or
1899 zeroes creates a valid bitmask. To check any repeated bitmask,
1900 try using 16 bits from the other 32-bit half of val. */
1903 {
1914 }
1916 {
1918 {
1922 }
1924 }
1925 }
1927 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1928 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1929 otherwise skip zero bits. */
1941 {
1947 num_insns ++;
1948 }
1951 }
1954 void
1956 {
1961 /* Check on what type of symbol it is. */
1962 scalar_int_mode int_mode;
1967 {
1971 /* If we have (const (plus symbol offset)), separate out the offset
1972 before we start classifying the symbol. */
1977 {
1981 {
1988 }
1993 /* If we aren't generating PC relative literals, then
1994 we need to expand the literal pool access carefully.
1995 This is something that needs to be done in a number
1996 of places, so could well live as a separate function. */
1998 {
2005 }
2022 {
2029 }
2030 /* FALLTHRU */
2043 }
2044 }
2047 {
2050 else
2051 {
2055 }
2058 }
2062 }
2064 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2065 temporary value if necessary. FRAME_RELATED_P should be true if
2066 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2067 to the generated instructions. If SCRATCHREG is known to hold
2068 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2069 immediate again.
2071 Since this function may be used to adjust the stack pointer, we must
2072 ensure that it cannot cause transient stack deallocation (for example
2073 by first incrementing SP and then decrementing when adjusting by a
2074 large immediate). */
2076 static void
2080 {
2088 /* Single instruction adjustment. */
2090 {
2094 }
2096 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2097 Only do this if mdelta is not a 16-bit move as adjusting using a move
2098 is better. */
2100 {
2109 }
2111 /* Emit a move immediate if required and an addition/subtraction. */
2118 {
2122 }
2123 }
2127 HOST_WIDE_INT delta)
2128 {
2130 }
2134 {
2137 }
2141 {
2144 }
2146 static bool
2148 tree exp ATTRIBUTE_UNUSED)
2149 {
2150 /* Currently, always true. */
2152 }
2154 /* Implement TARGET_PASS_BY_REFERENCE. */
2156 static bool
2158 machine_mode mode,
2159 const_tree type,
2161 {
2162 HOST_WIDE_INT size;
2163 machine_mode dummymode;
2166 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2170 /* Aggregates are passed by reference based on their size. */
2172 {
2174 }
2176 /* Variable sized arguments are always returned by reference. */
2180 /* Can this be a candidate to be passed in fp/simd register(s)? */
2183 NULL))
2186 /* Arguments which are variable sized or larger than 2 registers are
2187 passed by reference unless they are a homogenous floating point
2188 aggregate. */
2190 }
2192 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2193 static bool
2195 {
2196 machine_mode dummy_mode;
2199 /* Never happens in little-endian mode. */
2203 /* Only composite types smaller than or equal to 16 bytes can
2204 be potentially returned in registers. */
2210 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2211 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2212 is always passed/returned in the least significant bits of fp/simd
2213 register(s). */
2219 }
2221 /* Implement TARGET_FUNCTION_VALUE.
2222 Define how to find the value returned by a function. */
2224 static rtx
2227 {
2228 machine_mode mode;
2231 machine_mode ag_mode;
2238 {
2242 {
2245 }
2246 }
2250 {
2252 {
2255 }
2256 else
2257 {
2259 rtx par;
2263 {
2268 }
2270 }
2271 }
2272 else
2274 }
2276 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2277 Return true if REGNO is the number of a hard register in which the values
2278 of called function may come back. */
2280 static bool
2282 {
2283 /* Maximum of 16 bytes can be returned in the general registers. Examples
2284 of 16-byte return values are: 128-bit integers and 16-byte small
2285 structures (excluding homogeneous floating-point aggregates). */
2289 /* Up to four fp/simd registers can return a function value, e.g. a
2290 homogeneous floating-point aggregate having four members. */
2295 }
2297 /* Implement TARGET_RETURN_IN_MEMORY.
2299 If the type T of the result of a function is such that
2300 void func (T arg)
2301 would require that arg be passed as a value in a register (or set of
2302 registers) according to the parameter passing rules, then the result
2303 is returned in the same registers as would be used for such an
2304 argument. */
2306 static bool
2308 {
2309 HOST_WIDE_INT size;
2310 machine_mode ag_mode;
2316 /* Simple scalar types always returned in registers. */
2320 type,
2323 NULL))
2326 /* Types larger than 2 registers returned in memory. */
2329 }
2331 static bool
2334 {
2337 type,
2339 nregs,
2340 NULL);
2341 }
2343 /* Given MODE and TYPE of a function argument, return the alignment in
2344 bits. The idea is to suppress any stronger alignment requested by
2345 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2346 This is a helper function for local use only. */
2348 static unsigned int
2350 {
2371 }
2373 /* Layout a function argument according to the AAPCS64 rules. The rule
2374 numbers refer to the rule numbers in the AAPCS64. */
2376 static void
2378 const_tree type,
2380 {
2384 HOST_WIDE_INT size;
2386 /* We need to do this once per argument. */
2392 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2393 size
2395 UNITS_PER_WORD);
2399 mode,
2400 type,
2403 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2404 The following code thus handles passing by SIMD/FP registers first. */
2408 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2409 and homogenous short-vector aggregates (HVA). */
2411 {
2416 {
2419 {
2422 }
2423 else
2424 {
2425 rtx par;
2429 {
2432 tmp = gen_rtx_EXPR_LIST
2436 }
2438 }
2440 }
2441 else
2442 {
2443 /* C.3 NSRN is set to 8. */
2446 }
2447 }
2452 /* C6 - C9. though the sign and zero extension semantics are
2453 handled elsewhere. This is the case where the argument fits
2454 entirely general registers. */
2456 {
2460 /* C.8 if the argument has an alignment of 16 then the NGRN is
2461 rounded up to the next even number. */
2464 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2465 comparison is there because for > 16 * BITS_PER_UNIT
2466 alignment nregs should be > 2 and therefore it should be
2467 passed by reference rather than value. */
2469 {
2472 }
2474 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2475 A reg is still generated for it, but the caller should be smart
2476 enough not to use it. */
2479 else
2480 {
2481 rtx par;
2486 {
2491 }
2493 }
2497 }
2499 /* C.11 */
2502 /* The argument is passed on stack; record the needed number of words for
2503 this argument and align the total size if necessary. */
2504 on_stack:
2511 }
2513 /* Implement TARGET_FUNCTION_ARG. */
2515 static rtx
2518 {
2527 }
2529 void
2531 const_tree fntype ATTRIBUTE_UNUSED,
2532 rtx libname ATTRIBUTE_UNUSED,
2533 const_tree fndecl ATTRIBUTE_UNUSED,
2535 {
2549 {
2556 }
2558 }
2560 static void
2562 machine_mode mode,
2563 const_tree type,
2565 {
2568 {
2578 }
2579 }
2581 bool
2583 {
2586 }
2588 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2589 PARM_BOUNDARY bits of alignment, but will be given anything up
2590 to STACK_BOUNDARY bits if the type requires it. This makes sure
2591 that both before and after the layout of each argument, the Next
2592 Stacked Argument Address (NSAA) will have a minimum alignment of
2593 8 bytes. */
2595 static unsigned int
2597 {
2600 }
2602 /* Implement TARGET_FUNCTION_ARG_PADDING.
2604 Small aggregate types are placed in the lowest memory address.
2606 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2608 static pad_direction
2610 {
2611 /* On little-endian targets, the least significant byte of every stack
2612 argument is passed at the lowest byte address of the stack slot. */
2616 /* Otherwise, integral, floating-point and pointer types are padded downward:
2617 the least significant byte of a stack argument is passed at the highest
2618 byte address of the stack slot. */
2625 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2627 }
2629 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2631 It specifies padding for the last (may also be the only)
2632 element of a block move between registers and memory. If
2633 assuming the block is in the memory, padding upward means that
2634 the last element is padded after its highest significant byte,
2635 while in downward padding, the last element is padded at the
2636 its least significant byte side.
2638 Small aggregates and small complex types are always padded
2639 upwards.
2641 We don't need to worry about homogeneous floating-point or
2642 short-vector aggregates; their move is not affected by the
2643 padding direction determined here. Regardless of endianness,
2644 each element of such an aggregate is put in the least
2645 significant bits of a fp/simd register.
2647 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2648 register has useful data, and return the opposite if the most
2649 significant byte does. */
2651 bool
2654 {
2656 /* Small composite types are always padded upward. */
2658 {
2663 }
2665 /* Otherwise, use the default padding. */
2667 }
2669 static scalar_int_mode
2671 {
2673 }
2675 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2677 /* We use the 12-bit shifted immediate arithmetic instructions so values
2678 must be multiple of (1 << 12), i.e. 4096. */
2679 #define ARITH_FACTOR 4096
2681 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2682 #error Cannot use simple address calculation for stack probing
2683 #endif
2685 /* The pair of scratch registers used for stack probing. */
2686 #define PROBE_STACK_FIRST_REG 9
2687 #define PROBE_STACK_SECOND_REG 10
2689 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2690 inclusive. These are offsets from the current stack pointer. */
2692 static void
2694 {
2697 /* See the same assertion on PROBE_INTERVAL above. */
2700 /* See if we have a constant small number of probes to generate. If so,
2701 that's the easy case. */
2703 {
2710 }
2712 /* The run-time loop is made up of 8 insns in the generic case while the
2713 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2715 {
2720 stack_pointer_rtx,
2724 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2725 it exceeds SIZE. If only two probes are needed, this will not
2726 generate any code. Then probe at FIRST + SIZE. */
2728 {
2732 }
2736 {
2741 }
2742 else
2744 }
2746 /* Otherwise, do the same as above, but in a loop. Note that we must be
2747 extra careful with variables wrapping around because we might be at
2748 the very top (or the very bottom) of the address space and we have
2749 to be able to handle this case properly; in particular, we use an
2750 equality test for the loop condition. */
2751 else
2752 {
2755 /* Step 1: round SIZE to the previous multiple of the interval. */
2760 /* Step 2: compute initial and final value of the loop counter. */
2762 /* TEST_ADDR = SP + FIRST. */
2766 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2769 {
2773 }
2774 else
2775 {
2778 }
2780 /* Step 3: the loop
2782 do
2783 {
2784 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2785 probe at TEST_ADDR
2786 }
2787 while (TEST_ADDR != LAST_ADDR)
2789 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2790 until it is equal to ROUNDED_SIZE. */
2795 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2796 that SIZE is equal to ROUNDED_SIZE. */
2799 {
2803 {
2808 }
2809 else
2811 }
2812 }
2814 /* Make sure nothing is scheduled before we are done. */
2816 }
2818 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2819 absolute addresses. */
2823 {
2830 /* Loop. */
2833 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2838 /* Probe at TEST_ADDR. */
2841 /* Test if TEST_ADDR == LAST_ADDR. */
2845 /* Branch. */
2851 }
2853 static bool
2855 {
2856 /* In aarch64_override_options_after_change
2857 flag_omit_leaf_frame_pointer turns off the frame pointer by
2858 default. Turn it back on now if we've not got a leaf
2859 function. */
2864 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2869 }
2871 /* Mark the registers that need to be saved by the callee and calculate
2872 the size of the callee-saved registers area and frame record (both FP
2873 and LR may be omitted). */
2874 static void
2876 {
2883 #define SLOT_NOT_REQUIRED (-2)
2884 #define SLOT_REQUIRED (-1)
2889 /* First mark all the registers that really need to be saved... */
2896 /* ... that includes the eh data registers (if needed)... */
2902 /* ... and any callee saved register that dataflow says is live. */
2912 {
2915 }
2918 {
2919 /* FP and LR are placed in the linkage record. */
2925 }
2927 /* Now assign stack slots for them. */
2930 {
2937 }
2945 {
2946 /* If there is an alignment gap between integer and fp callee-saves,
2947 allocate the last fp register to it if possible. */
2949 {
2952 }
2961 }
2967 HOST_WIDE_INT varargs_and_saved_regs_size
2994 {
2995 /* Simple, small frame with no outgoing arguments:
2996 stp reg1, reg2, [sp, -frame_size]!
2997 stp reg3, reg4, [sp, 16] */
2999 }
3004 {
3005 /* Frame with small outgoing arguments:
3006 sub sp, sp, frame_size
3007 stp reg1, reg2, [sp, outgoing_args_size]
3008 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3012 }
3014 {
3015 /* Frame with large outgoing arguments but a small local area:
3016 stp reg1, reg2, [sp, -hard_fp_offset]!
3017 stp reg3, reg4, [sp, 16]
3018 sub sp, sp, outgoing_args_size */
3022 }
3025 {
3026 /* Frame with large local area and outgoing arguments (this pushes the
3027 callee-saves first, followed by the locals and outgoing area):
3028 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3029 stp reg3, reg4, [sp, 16]
3030 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3036 }
3037 else
3038 {
3039 /* Frame with large local area and outgoing arguments using frame pointer:
3040 sub sp, sp, hard_fp_offset
3041 stp x29, x30, [sp, 0]
3042 add x29, sp, 0
3043 stp reg3, reg4, [sp, 16]
3044 sub sp, sp, outgoing_args_size */
3048 }
3051 }
3053 /* Return true if the register REGNO is saved on entry to
3054 the current function. */
3056 static bool
3058 {
3060 }
3062 /* Return the next register up from REGNO up to LIMIT for the callee
3063 to save. */
3065 static unsigned
3067 {
3069 regno ++;
3071 }
3073 /* Push the register number REGNO of mode MODE to the stack with write-back
3074 adjusting the stack by ADJUSTMENT. */
3076 static void
3078 HOST_WIDE_INT adjustment)
3079 {
3090 }
3092 /* Generate and return an instruction to store the pair of registers
3093 REG and REG2 of mode MODE to location BASE with write-back adjusting
3094 the stack location BASE by ADJUSTMENT. */
3096 static rtx
3098 HOST_WIDE_INT adjustment)
3099 {
3101 {
3112 }
3113 }
3115 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3116 stack pointer by ADJUSTMENT. */
3118 static void
3120 {
3135 }
3137 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3138 adjusting it by ADJUSTMENT afterwards. */
3140 static rtx
3142 HOST_WIDE_INT adjustment)
3143 {
3145 {
3154 }
3155 }
3157 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3158 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3159 into CFI_OPS. */
3161 static void
3164 {
3171 {
3175 }
3176 else
3177 {
3182 }
3183 }
3185 /* Generate and return a store pair instruction of mode MODE to store
3186 register REG1 to MEM1 and register REG2 to MEM2. */
3188 static rtx
3190 rtx reg2)
3191 {
3193 {
3202 }
3203 }
3205 /* Generate and regurn a load pair isntruction of mode MODE to load register
3206 REG1 from MEM1 and register REG2 from MEM2. */
3208 static rtx
3210 rtx mem2)
3211 {
3213 {
3222 }
3223 }
3225 /* Return TRUE if return address signing should be enabled for the current
3226 function, otherwise return FALSE. */
3228 bool
3230 {
3231 /* This function should only be called after frame laid out. */
3234 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3235 if it's LR is pushed onto stack. */
3239 }
3241 /* Emit code to save the callee-saved registers from register number START
3242 to LIMIT to the stack at the location starting at offset START_OFFSET,
3243 skipping any write-back candidates if SKIP_WB is true. */
3245 static void
3248 {
3256 {
3258 HOST_WIDE_INT offset;
3271 offset));
3280 {
3282 rtx mem2;
3286 offset));
3288 reg2));
3290 /* The first part of a frame-related parallel insn is
3291 always assumed to be relevant to the frame
3292 calculations; subsequent parts, are only
3293 frame-related if explicitly marked. */
3296 }
3297 else
3301 }
3302 }
3304 /* Emit code to restore the callee registers of mode MODE from register
3305 number START up to and including LIMIT. Restore from the stack offset
3306 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3307 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3309 static void
3313 {
3317 HOST_WIDE_INT offset;
3322 {
3343 {
3345 rtx mem2;
3353 }
3354 else
3357 }
3358 }
3362 HOST_WIDE_INT offset)
3363 {
3365 }
3369 {
3373 }
3375 bool
3377 {
3381 }
3383 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3385 static sbitmap
3387 {
3393 /* The registers we need saved to the frame. */
3396 {
3401 /* Check that we can access the stack slot of the register with one
3402 direct load with no adjustments needed. */
3405 }
3407 /* Don't mess with the hard frame pointer. */
3413 /* If aarch64_layout_frame has chosen registers to store/restore with
3414 writeback don't interfere with them to avoid having to output explicit
3415 stack adjustment instructions. */
3425 }
3427 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3429 static sbitmap
3431 {
3439 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3448 }
3450 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3451 Nothing to do for aarch64. */
3453 static void
3455 {
3456 }
3458 /* Return the next set bit in BMP from START onwards. Return the total number
3459 of bits in BMP if no set bit is found at or after START. */
3461 static unsigned int
3463 {
3474 }
3476 /* Do the work for aarch64_emit_prologue_components and
3477 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3478 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3479 for these components or the epilogue sequence. That is, it determines
3480 whether we should emit stores or loads and what kind of CFA notes to attach
3481 to the insns. Otherwise the logic for the two sequences is very
3482 similar. */
3484 static void
3486 {
3488 ? HARD_FRAME_POINTER_REGNUM
3496 {
3497 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3498 so DFmode for the vector registers is enough. */
3510 /* No more registers to handle after REGNO.
3511 Emit a single save/restore and exit. */
3513 {
3518 else
3521 }
3524 /* The next register is not of the same class or its offset is not
3525 mergeable with the current one into a pair. */
3530 {
3535 else
3540 }
3542 /* REGNO2 can be saved/restored in a pair with REGNO. */
3554 else
3559 {
3562 }
3563 else
3564 {
3567 }
3570 }
3571 }
3573 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3575 static void
3577 {
3579 }
3581 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3583 static void
3585 {
3587 }
3589 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3591 static void
3593 {
3597 }
3599 /* AArch64 stack frames generated by this compiler look like:
3601 +-------------------------------+
3602 | |
3603 | incoming stack arguments |
3604 | |
3605 +-------------------------------+
3606 | | <-- incoming stack pointer (aligned)
3607 | callee-allocated save area |
3608 | for register varargs |
3609 | |
3610 +-------------------------------+
3611 | local variables | <-- frame_pointer_rtx
3612 | |
3613 +-------------------------------+
3614 | padding0 | \
3615 +-------------------------------+ |
3616 | callee-saved registers | | frame.saved_regs_size
3617 +-------------------------------+ |
3618 | LR' | |
3619 +-------------------------------+ |
3620 | FP' | / <- hard_frame_pointer_rtx (aligned)
3621 +-------------------------------+
3622 | dynamic allocation |
3623 +-------------------------------+
3624 | padding |
3625 +-------------------------------+
3626 | outgoing stack arguments | <-- arg_pointer
3627 | |
3628 +-------------------------------+
3629 | | <-- stack_pointer_rtx (aligned)
3631 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3632 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3633 unchanged. */
3635 /* Generate the prologue instructions for entry into a function.
3636 Establish the stack frame by decreasing the stack pointer with a
3637 properly calculated size and, if necessary, create a frame record
3638 filled with the values of LR and previous frame pointer. The
3639 current FP is also set up if it is in use. */
3641 void
3643 {
3655 /* Sign return address for functions. */
3657 {
3661 }
3667 {
3669 {
3673 }
3676 }
3684 {
3689 stack_pointer_rtx,
3693 }
3700 }
3702 /* Return TRUE if we can use a simple_return insn.
3704 This function checks whether the callee saved stack is empty, which
3705 means no restore actions are need. The pro_and_epilogue will use
3706 this to check whether shrink-wrapping opt is feasible. */
3708 bool
3710 {
3720 }
3722 /* Generate the epilogue instructions for returning from a function.
3723 This is almost exactly the reverse of the prolog sequence, except
3724 that we need to insert barriers to avoid scheduling loads that read
3725 from a deallocated stack, and we optimize the unwind records by
3726 emitting them all together if possible. */
3727 void
3729 {
3741 /* We need to add memory barrier to prevent read from deallocated stack. */
3745 /* Emit a barrier to prevent loads from a deallocated stack. */
3748 {
3751 }
3753 /* Restore the stack pointer from the frame pointer if it may not
3754 be the same as the stack pointer. */
3756 {
3758 hard_frame_pointer_rtx,
3760 /* If writeback is used when restoring callee-saves, the CFA
3761 is restored on the instruction doing the writeback. */
3763 }
3764 else
3779 {
3780 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3786 }
3791 {
3792 /* Emit delayed restores and reset the CFA to be SP. */
3797 }
3799 /* We prefer to emit the combined return/authenticate instruction RETAA,
3800 however there are three cases in which we must instead emit an explicit
3801 authentication instruction.
3803 1) Sibcalls don't return in a normal way, so if we're about to call one
3804 we must authenticate.
3806 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3807 generating code for !TARGET_ARMV8_3 we can't use it and must
3808 explicitly authenticate.
3810 3) On an eh_return path we make extra stack adjustments to update the
3811 canonical frame address to be the exception handler's CFA. We want
3812 to authenticate using the CFA of the function which calls eh_return.
3813 */
3816 {
3820 }
3822 /* Stack adjustment for exception handler. */
3824 {
3825 /* We need to unwind the stack by the offset computed by
3826 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3827 to be SP; letting the CFA move during this adjustment
3828 is just as correct as retaining the CFA from the body
3829 of the function. Therefore, do nothing special. */
3831 }
3836 }
3838 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3839 normally or return to a previous frame after unwinding.
3841 An EH return uses a single shared return sequence. The epilogue is
3842 exactly like a normal epilogue except that it has an extra input
3843 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3844 that must be applied after the frame has been destroyed. An extra label
3845 is inserted before the epilogue which initializes this register to zero,
3846 and this is the entry point for a normal return.
3848 An actual EH return updates the return address, initializes the stack
3849 adjustment and jumps directly into the epilogue (bypassing the zeroing
3850 of the adjustment). Since the return address is typically saved on the
3851 stack when a function makes a call, the saved LR must be updated outside
3852 the epilogue.
3854 This poses problems as the store is generated well before the epilogue,
3855 so the offset of LR is not known yet. Also optimizations will remove the
3856 store as it appears dead, even after the epilogue is generated (as the
3857 base or offset for loading LR is different in many cases).
3859 To avoid these problems this implementation forces the frame pointer
3860 in eh_return functions so that the location of LR is fixed and known early.
3861 It also marks the store volatile, so no optimization is permitted to
3862 remove the store. */
3863 rtx
3865 {
3869 /* Mark the store volatile, so no optimization is permitted to remove it. */
3872 }
3874 /* Output code to add DELTA to the first argument, and then jump
3875 to FUNCTION. Used for C++ multiple inheritance. */
3876 static void
3878 HOST_WIDE_INT delta,
3879 HOST_WIDE_INT vcall_offset,
3880 tree function)
3881 {
3882 /* The this pointer is always in x0. Note that this differs from
3883 Arm where the this pointer maybe bumped to r1 if r0 is required
3884 to return a pointer to an aggregate. On AArch64 a result value
3885 pointer will be in x8. */
3895 else
3896 {
3905 {
3909 else
3911 }
3915 else
3922 else
3923 {
3925 Pmode);
3927 }
3931 else
3937 }
3939 /* Generate a tail call to the target function. */
3941 {
3944 }
3956 /* Stop pretending to be a post-reload pass. */
3958 }
3960 static bool
3962 {
3967 {
3971 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3972 TLS offsets, not real symbol references. */
3975 }
3977 }
3980 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3981 a left shift of 0 or 12 bits. */
3982 bool
3984 {
3987 );
3988 }
3991 /* Return true if val is an immediate that can be loaded into a
3992 register by a MOVZ instruction. */
3993 static bool
3995 {
3997 {
4001 }
4002 else
4003 {
4004 /* Ignore sign extension. */
4006 }
4009 }
4011 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4014 {
4020 };
4023 /* Return true if val is a valid bitmask immediate. */
4025 bool
4027 {
4031 /* Check for a single sequence of one bits and return quickly if so.
4032 The special cases of all ones and all zeroes returns false. */
4039 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4043 /* Invert if the immediate doesn't start with a zero bit - this means we
4044 only need to search for sequences of one bits. */
4048 /* Find the first set bit and set tmp to val with the first sequence of one
4049 bits removed. Return success if there is a single sequence of ones. */
4056 /* Find the next set bit and compute the difference in bit position. */
4061 /* Check the bit position difference is a power of 2, and that the first
4062 sequence of one bits fits within 'bits' bits. */
4066 /* Check the sequence of one bits is repeated 64/bits times. */
4068 }
4070 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4071 Assumed precondition: VAL_IN Is not zero. */
4073 unsigned HOST_WIDE_INT
4075 {
4082 }
4084 /* Create constant where bits outside of lowest bit set to highest bit set
4085 are set to 1. */
4087 unsigned HOST_WIDE_INT
4089 {
4091 }
4093 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4095 bool
4097 {
4098 scalar_int_mode int_mode;
4111 }
4113 /* Return true if val is an immediate that can be loaded into a
4114 register in a single instruction. */
4115 bool
4117 {
4118 scalar_int_mode int_mode;
4125 }
4127 static bool
4129 {
4137 {
4141 else
4142 /* Avoid generating a 64-bit relocation in ILP32; leave
4143 to aarch64_expand_mov_immediate to handle it properly. */
4145 }
4148 }
4150 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4151 The expansion for a table switch is quite expensive due to the number
4152 of instructions, the table lookup and hard to predict indirect jump.
4153 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4154 set, otherwise use tables for > 16 cases as a tradeoff between size and
4155 performance. When optimizing for size, use the default setting. */
4157 static unsigned int
4159 {
4160 /* Use the specified limit for the number of cases before using jump
4161 tables at higher optimization levels. */
4165 else
4167 }
4169 /* Return true if register REGNO is a valid index register.
4170 STRICT_P is true if REG_OK_STRICT is in effect. */
4172 bool
4174 {
4176 {
4184 }
4186 }
4188 /* Return true if register REGNO is a valid base register for mode MODE.
4189 STRICT_P is true if REG_OK_STRICT is in effect. */
4191 bool
4193 {
4195 {
4203 }
4205 /* The fake registers will be eliminated to either the stack or
4206 hard frame pointer, both of which are usually valid base registers.
4207 Reload deals with the cases where the eliminated form isn't valid. */
4212 }
4214 /* Return true if X is a valid base register for mode MODE.
4215 STRICT_P is true if REG_OK_STRICT is in effect. */
4217 static bool
4219 {
4226 }
4228 /* Return true if address offset is a valid index. If it is, fill in INFO
4229 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4231 static bool
4234 {
4236 rtx index;
4239 /* (reg:P) */
4242 {
4246 }
4247 /* (sign_extend:DI (reg:SI)) */
4252 {
4257 }
4258 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4265 {
4270 }
4271 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4278 {
4283 }
4284 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4291 {
4299 }
4300 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4301 (const_int 0xffffffff<<shift)) */
4308 {
4314 }
4315 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4322 {
4330 }
4331 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4332 (const_int 0xffffffff<<shift)) */
4339 {
4345 }
4346 /* (mult:P (reg:P) (const_int scale)) */
4351 {
4355 }
4356 /* (ashift:P (reg:P) (const_int shift)) */
4361 {
4365 }
4366 else
4379 {
4384 }
4387 }
4389 /* Return true if MODE is one of the modes for which we
4390 support LDP/STP operations. */
4392 static bool
4394 {
4399 }
4401 /* Return true if REGNO is a virtual pointer register, or an eliminable
4402 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4403 include stack_pointer or hard_frame_pointer. */
4404 static bool
4406 {
4411 }
4413 /* Return true if X is a valid address for machine mode MODE. If it is,
4414 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4415 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4417 static bool
4421 {
4425 /* On BE, we use load/store pair for all large int mode load/stores.
4426 TI/TFmode may also use a load/store pair. */
4430 || (BYTES_BIG_ENDIAN
4434 !load_store_pair_p
4438 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4439 REG addressing. */
4445 {
4461 {
4467 }
4472 {
4479 /* TImode and TFmode values are allowed in both pairs of X
4480 registers and individual Q registers. The available
4481 address modes are:
4482 X,X: 7-bit signed scaled offset
4483 Q: 9-bit signed offset
4484 We conservatively require an offset representable in either mode.
4485 When performing the check for pairs of X registers i.e. LDP/STP
4486 pass down DImode since that is the natural size of the LDP/STP
4487 instruction memory accesses. */
4493 /* A 7bit offset check because OImode will emit a ldp/stp
4494 instruction (only big endian will get here).
4495 For ldp/stp instructions, the offset is scaled for the size of a
4496 single element of the pair. */
4500 /* Three 9/12 bit offsets checks because CImode will emit three
4501 ldr/str instructions (only big endian will get here). */
4508 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4509 instructions (only big endian will get here). */
4518 else
4521 }
4524 {
4525 /* Look for base + (scaled/extended) index register. */
4528 {
4531 }
4534 {
4537 }
4538 }
4559 {
4560 HOST_WIDE_INT offset;
4564 /* TImode and TFmode values are allowed in both pairs of X
4565 registers and individual Q registers. The available
4566 address modes are:
4567 X,X: 7-bit signed scaled offset
4568 Q: 9-bit signed offset
4569 We conservatively require an offset representable in either mode.
4570 */
4578 else
4580 }
4586 /* load literal: pc-relative constant pool entry. Only supported
4587 for SI mode or larger. */
4591 {
4599 }
4608 {
4613 {
4614 /* The symbol and offset must be aligned to the access size. */
4621 {
4625 }
4631 else
4640 }
4641 }
4646 }
4647 }
4649 /* Return true if the address X is valid for a PRFM instruction.
4650 STRICT_P is true if we should do strict checking with
4651 aarch64_classify_address. */
4653 bool
4655 {
4658 /* PRFM accepts the same addresses as DImode... */
4663 /* ... except writeback forms. */
4665 }
4667 bool
4669 {
4670 rtx offset;
4674 }
4676 /* Classify the base of symbolic expression X. */
4678 enum aarch64_symbol_type
4680 {
4681 rtx offset;
4685 }
4688 /* Return TRUE if X is a legitimate address for accessing memory in
4689 mode MODE. */
4690 static bool
4692 {
4696 }
4698 /* Return TRUE if X is a legitimate address for accessing memory in
4699 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4700 pair operation. */
4701 bool
4704 {
4708 }
4710 /* Split an out-of-range address displacement into a base and offset.
4711 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4712 to increase opportunities for sharing the base address of different sizes.
4713 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4714 static bool
4716 {
4727 }
4729 /* Return the binary representation of floating point constant VALUE in INTVAL.
4730 If the value cannot be converted, return false without setting INTVAL.
4731 The conversion is done in the given MODE. */
4732 bool
4734 {
4736 /* We make a general exception for 0. */
4738 {
4741 }
4747 /* Only support up to DF mode. */
4759 {
4763 }
4764 else
4769 }
4771 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4772 single MOV(+MOVK) followed by an FMOV. */
4773 bool
4775 {
4780 /* Determine whether it's cheaper to write float constants as
4781 mov/movk pairs over ldr/adrp pairs. */
4787 {
4789 ? SImode
4794 }
4797 }
4799 /* Return TRUE if rtx X is immediate constant 0.0 */
4800 bool
4802 {
4809 }
4811 /* Return TRUE if rtx X is immediate constant that fits in a single
4812 MOVI immediate operation. */
4813 bool
4815 {
4819 machine_mode vmode;
4820 scalar_int_mode imode;
4825 {
4829 /* We make a general exception for 0. */
4834 }
4838 else
4841 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4842 a 128 bit vector mode. */
4849 }
4852 /* Return the fixed registers used for condition codes. */
4854 static bool
4856 {
4860 }
4862 /* This function is used by the call expanders of the machine description.
4863 RESULT is the register in which the result is returned. It's NULL for
4864 "call" and "sibcall".
4865 MEM is the location of the function call.
4866 SIBCALL indicates whether this function call is normal call or sibling call.
4867 It will generate different pattern accordingly. */
4869 void
4871 {
4873 rtvec vec;
4874 machine_mode mode;
4881 /* Decide if we should generate indirect calls by loading the
4882 address of the callee into a register before performing
4883 the branch-and-link. */
4897 else
4904 }
4906 /* Emit call insn with PAT and do aarch64-specific handling. */
4908 void
4910 {
4916 }
4918 machine_mode
4920 {
4921 /* All floating point compares return CCFP if it is an equality
4922 comparison, and CCFPE otherwise. */
4924 {
4926 {
4947 }
4948 }
4950 /* Equality comparisons of short modes against zero can be performed
4951 using the TST instruction with the appropriate bitmask. */
4957 /* Similarly, comparisons of zero_extends from shorter modes can
4958 be performed using an ANDS with an immediate mask. */
4974 /* A compare with a shifted operand. Because of canonicalization,
4975 the comparison will have to be swapped when we emit the assembly
4976 code. */
4984 /* Similarly for a negated operand, but we can only do this for
4985 equalities. */
4992 /* A test for unsigned overflow. */
4999 /* For everything else, return CCmode. */
5001 }
5003 static int
5006 int
5008 {
5015 }
5017 static int
5019 {
5021 {
5025 {
5039 }
5044 {
5056 }
5061 {
5073 }
5078 {
5084 }
5089 {
5093 }
5098 {
5102 }
5107 }
5110 }
5112 bool
5114 HOST_WIDE_INT minval,
5115 HOST_WIDE_INT maxval)
5116 {
5117 HOST_WIDE_INT firstval;
5134 }
5136 bool
5138 {
5140 }
5143 /* N Z C V. */
5144 #define AARCH64_CC_V 1
5145 #define AARCH64_CC_C (1 << 1)
5146 #define AARCH64_CC_Z (1 << 2)
5147 #define AARCH64_CC_N (1 << 3)
5149 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5151 {
5168 };
5170 /* Print operand X to file F in a target specific manner according to CODE.
5171 The acceptable formatting commands given by CODE are:
5172 'c': An integer or symbol address without a preceding #
5173 sign.
5174 'e': Print the sign/zero-extend size as a character 8->b,
5175 16->h, 32->w.
5176 'p': Prints N such that 2^N == X (X must be power of 2 and
5177 const int).
5178 'P': Print the number of non-zero bits in X (a const_int).
5179 'H': Print the higher numbered register of a pair (TImode)
5180 of regs.
5181 'm': Print a condition (eq, ne, etc).
5182 'M': Same as 'm', but invert condition.
5183 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5184 'S/T/U/V': Print a FP/SIMD register name for a register list.
5185 The register printed is the FP/SIMD register name
5186 of X + 0/1/2/3 for S/T/U/V.
5187 'R': Print a scalar FP/SIMD register name + 1.
5188 'X': Print bottom 16 bits of integer constant in hex.
5189 'w/x': Print a general register name or the zero register
5190 (32-bit or 64-bit).
5191 '0': Print a normal operand, if it's a general register,
5192 then we assume DImode.
5193 'k': Print NZCV for conditional compare instructions.
5194 'A': Output address constant representing the first
5195 argument of X, specifying a relocation offset
5196 if appropriate.
5197 'L': Output constant address specified by X
5198 with a relocation offset if appropriate.
5199 'G': Prints address of X, specifying a PC relative
5200 relocation mode if appropriate. */
5202 static void
5204 {
5206 {
5209 {
5221 {
5224 }
5225 /* Fall through. */
5229 }
5233 {
5238 {
5241 }
5244 {
5257 }
5258 }
5262 {
5266 {
5269 }
5272 }
5277 {
5280 }
5287 {
5290 }
5297 {
5299 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5301 {
5305 }
5308 {
5311 }
5318 }
5327 {
5328 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5330 }
5339 {
5340 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5342 }
5348 {
5349 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5351 }
5357 {
5360 }
5368 {
5371 }
5374 {
5377 }
5380 {
5383 }
5385 /* Fall through */
5389 {
5392 }
5395 {
5402 /* Check all memory references are Pmode - even with ILP32. */
5418 {
5421 HOST_WIDE_INT_MIN,
5422 HOST_WIDE_INT_MAX));
5424 }
5426 {
5428 }
5429 else
5434 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5435 be getting CONST_DOUBLEs holding integers. */
5438 {
5441 }
5443 {
5444 #define buf_size 20
5452 #undef buf_size
5453 }
5459 }
5467 {
5494 }
5500 {
5535 }
5541 {
5547 }
5552 {
5553 HOST_WIDE_INT cond_code;
5556 {
5559 }
5564 }
5570 }
5571 }
5573 static void
5575 {
5580 {
5584 else
5593 else
5602 else
5611 else
5618 {
5645 }
5656 }
5659 }
5661 bool
5663 {
5670 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5671 referencing instruction, but they are constant offsets, not
5672 symbols. */
5678 {
5680 {
5686 }
5689 }
5692 }
5694 /* Implement REGNO_REG_CLASS. */
5696 enum reg_class
5698 {
5713 }
5715 static rtx
5717 {
5718 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5719 where mask is selected by alignment and size of the offset.
5720 We try to pick as large a range for the offset as possible to
5721 maximize the chance of a CSE. However, for aligned addresses
5722 we limit the range to 4k so that structures with different sized
5723 elements are likely to use the same base. We need to be careful
5724 not to split a CONST for some forms of address expression, otherwise
5725 it will generate sub-optimal code. */
5728 {
5734 {
5738 /* Force any scaling into a temp for CSE. */
5742 /* Let the pointer register be in op0. */
5746 /* If the pointer is virtual or frame related, then we know that
5747 virtual register instantiation or register elimination is going
5748 to apply a second constant. We want the two constants folded
5749 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5751 {
5755 }
5757 /* Otherwise, in order to encourage CSE (and thence loop strength
5758 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5762 }
5764 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5765 HOST_WIDE_INT base_offset;
5768 /* For offsets aren't a multiple of the access size, the limit is
5769 -256...255. */
5771 {
5774 /* BLKmode typically uses LDP of X-registers. */
5777 }
5778 /* Small negative offsets are supported. */
5783 /* Use 12-bit offset by access size. */
5784 else
5788 {
5792 }
5793 }
5796 }
5798 /* Return the reload icode required for a constant pool in mode. */
5799 static enum insn_code
5801 {
5803 {
5839 }
5842 }
5843 static reg_class_t
5845 reg_class_t rclass,
5846 machine_mode mode,
5848 {
5850 /* If we have to disable direct literal pool loads and stores because the
5851 function is too big, then we need a scratch register. */
5856 {
5859 }
5861 /* Without the TARGET_SIMD instructions we cannot move a Q register
5862 to a Q register directly. We need a scratch. */
5866 {
5872 }
5874 /* A TFmode or TImode memory access should be handled via an FP_REGS
5875 because AArch64 has richer addressing modes for LDR/STR instructions
5876 than LDP/STP instructions. */
5885 }
5887 static bool
5889 {
5890 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5891 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5894 {
5906 }
5907 else
5908 {
5909 /* If we decided that we didn't need a leaf frame pointer but then used
5910 LR in the function, then we'll want a frame pointer after all, so
5911 prevent this elimination to ensure a frame pointer is used. */
5913 && flag_omit_leaf_frame_pointer
5916 }
5919 }
5921 HOST_WIDE_INT
5923 {
5927 {
5934 }
5937 {
5941 }
5944 }
5946 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5947 previous frame. */
5949 rtx
5951 {
5955 }
5958 static void
5960 {
5962 {
5965 }
5966 else
5967 {
5970 }
5975 }
5977 static void
5979 {
5983 /* Don't need to copy the trailing D-words, we fill those in below. */
5995 /* XXX We should really define a "clear_cache" pattern and use
5996 gen_clear_cache(). */
6001 ptr_mode);
6002 }
6004 static unsigned char
6006 {
6008 {
6015 return
6027 }
6029 }
6031 static reg_class_t
6033 {
6038 {
6044 }
6046 /* Register eliminiation can result in a request for
6047 SP+constant->FP_REGS. We cannot support such operations which
6048 use SP as source and an FP_REG as destination, so reject out
6049 right now. */
6051 {
6054 /* Look through a possible SUBREG introduced by ILP32. */
6060 POINTER_REGS));
6062 }
6065 }
6067 void
6069 {
6071 }
6073 static void
6075 {
6078 else
6079 {
6081 /* While priority is known to be in range [0, 65535], so 18 bytes
6082 would be enough, the compiler might not know that. To avoid
6083 -Wformat-truncation false positive, use a larger size. */
6090 }
6091 }
6093 static void
6095 {
6098 else
6099 {
6101 /* While priority is known to be in range [0, 65535], so 18 bytes
6102 would be enough, the compiler might not know that. To avoid
6103 -Wformat-truncation false positive, use a larger size. */
6110 }
6111 }
6115 {
6121 {
6122 {
6125 },
6126 {
6129 },
6130 {
6133 },
6134 /* We assume that DImode is only generated when not optimizing and
6135 that we don't really need 64-bit address offsets. That would
6136 imply an object file with 8GB of code in a single function! */
6137 {
6140 }
6141 };
6150 /* Need to implement table size reduction, by chaning the code below. */
6160 }
6163 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6164 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6165 operator. */
6167 int
6169 {
6171 {
6174 {
6178 }
6179 }
6181 }
6183 /* Constant pools are per function only when PC relative
6184 literal loads are true or we are in the large memory
6185 model. */
6189 {
6192 }
6194 static bool
6196 {
6197 /* Fixme:: In an ideal world this would work similar
6198 to the logic in aarch64_select_rtx_section but this
6199 breaks bootstrap in gcc go. For now we workaround
6200 this by returning false here. */
6202 }
6204 /* Select appropriate section for constants depending
6205 on where we place literal pools. */
6209 rtx x,
6211 {
6216 }
6218 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6219 void
6221 HOST_WIDE_INT offset)
6222 {
6223 /* When using per-function literal pools, we must ensure that any code
6224 section is aligned to the minimal instruction length, lest we get
6225 errors from the assembler re "unaligned instructions". */
6228 }
6230 /* Costs. */
6232 /* Helper function for rtx cost calculation. Strip a shift expression
6233 from X. Returns the inner operand if successful, or the original
6234 expression on failure. */
6235 static rtx
6237 {
6240 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6241 we can convert both to ROR during final output. */
6256 }
6258 /* Helper function for rtx cost calculation. Strip an extend
6259 expression from X. Returns the inner operand if successful, or the
6260 original expression on failure. We deal with a number of possible
6261 canonicalization variations here. If STRIP_SHIFT is true, then
6262 we can strip off a shift also. */
6263 static rtx
6265 {
6266 scalar_int_mode mode;
6272 /* Zero and sign extraction of a widened value. */
6280 /* It can also be represented (for zero-extend) as an AND with an
6281 immediate. */
6290 /* Now handle extended register, as this may also have an optional
6291 left shift by 1..4. */
6306 }
6308 /* Return true iff CODE is a shift supported in combination
6309 with arithmetic instructions. */
6311 static bool
6313 {
6315 }
6318 /* Return true iff X is a cheap shift without a sign extend. */
6320 static bool
6322 {
6348 }
6350 /* Helper function for rtx cost calculation. Calculate the cost of
6351 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6352 Return the calculated cost of the expression, recursing manually in to
6353 operands where needed. */
6355 static int
6357 {
6373 /* Integer multiply/fma. */
6375 {
6376 /* The multiply will be canonicalized as a shift, cost it as such. */
6380 {
6384 {
6386 {
6387 /* If the shift is considered cheap,
6388 then don't add any cost. */
6390 ;
6392 /* ARITH + shift-by-register. */
6395 /* ARITH + extended register. We don't have a cost field
6396 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6398 else
6399 /* ARITH + shift-by-immediate. */
6401 }
6402 else
6403 /* LSL (immediate). */
6406 }
6407 /* Strip extends as we will have costed them in the case above. */
6414 }
6416 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6417 compound and let the below cases handle it. After all, MNEG is a
6418 special-case alias of MSUB. */
6420 {
6423 }
6425 /* Integer multiplies or FMAs have zero/sign extending variants. */
6430 {
6435 {
6437 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6439 else
6440 /* MUL/SMULL/UMULL. */
6442 }
6445 }
6447 /* This is either an integer multiply or a MADD. In both cases
6448 we want to recurse and cost the operands. */
6453 {
6455 /* MADD/MSUB. */
6457 else
6458 /* MUL. */
6460 }
6463 }
6464 else
6465 {
6467 {
6468 /* Floating-point FMA/FMUL can also support negations of the
6469 operands, unless the rounding mode is upward or downward in
6470 which case FNMUL is different than FMUL with operand negation. */
6474 {
6479 }
6482 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6484 else
6485 /* FMUL/FNMUL. */
6487 }
6492 }
6493 }
6495 static int
6497 machine_mode mode,
6498 addr_space_t as ATTRIBUTE_UNUSED,
6500 {
6508 {
6510 {
6511 /* This is a CONST or SYMBOL ref which will be split
6512 in a different way depending on the code model in use.
6513 Cost it through the generic infrastructure. */
6515 /* Divide through by the cost of one instruction to
6516 bring it to the same units as the address costs. */
6518 /* The cost is then the cost of preparing the address,
6519 followed by an immediate (possibly 0) offset. */
6521 }
6522 else
6523 {
6524 /* This is most likely a jump table from a case
6525 statement. */
6527 }
6528 }
6531 {
6543 else
6562 }
6566 {
6567 /* For the sake of calculating the cost of the shifted register
6568 component, we can treat same sized modes in the same way. */
6570 {
6583 /* We can't tell, or this is a 128-bit vector. */
6587 }
6588 }
6591 }
6593 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6594 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6595 to be taken. */
6597 int
6599 {
6600 /* When optimizing for speed, use the cost of unpredictable branches. */
6606 else
6608 }
6610 /* Return true if the RTX X in mode MODE is a zero or sign extract
6611 usable in an ADD or SUB (extended register) instruction. */
6612 static bool
6614 {
6615 /* Catch add with a sign extract.
6616 This is add_<optab><mode>_multp2. */
6619 {
6630 op1))
6631 {
6633 }
6634 }
6635 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6636 No shift. */
6642 }
6644 static bool
6646 {
6648 {
6660 }
6661 }
6663 /* Return true iff X is an rtx that will match an extr instruction
6664 i.e. as described in the *extr<mode>5_insn family of patterns.
6665 OP0 and OP1 will be set to the operands of the shifts involved
6666 on success and will be NULL_RTX otherwise. */
6668 static bool
6670 {
6672 scalar_int_mode mode;
6687 {
6688 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6700 {
6704 }
6705 }
6708 }
6710 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6711 storing it in *COST. Result is true if the total cost of the operation
6712 has now been calculated. */
6713 static bool
6715 {
6716 rtx inner;
6717 rtx comparator;
6721 {
6725 }
6726 else
6727 {
6731 }
6734 {
6735 /* Conditional branch. */
6738 else
6739 {
6741 {
6743 {
6744 /* TBZ/TBNZ/CBZ/CBNZ. */
6746 /* TBZ/TBNZ. */
6749 else
6750 /* CBZ/CBNZ. */
6754 }
6755 }
6757 {
6758 /* TBZ/TBNZ. */
6761 }
6762 }
6763 }
6765 {
6766 /* CCMP. */
6768 {
6769 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6773 {
6780 else
6782 }
6784 }
6786 /* It's a conditional operation based on the status flags,
6787 so it must be some flavor of CSEL. */
6789 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6795 {
6796 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6799 }
6804 }
6806 /* We don't know what this is, cost all operands. */
6808 }
6810 /* Check whether X is a bitfield operation of the form shift + extend that
6811 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6812 operand to which the bitfield operation is applied. Otherwise return
6813 NULL_RTX. */
6815 static rtx
6817 {
6831 {
6849 }
6852 }
6854 /* Return true if the mask and a shift amount from an RTX of the form
6855 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6856 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6858 bool
6860 rtx shft_amnt)
6861 {
6866 }
6868 /* Calculate the cost of calculating X, storing it in *COST. Result
6869 is true if the total cost of the operation has now been calculated. */
6870 static bool
6873 {
6878 scalar_int_mode int_mode;
6880 /* By default, assume that everything has equivalent cost to the
6881 cheapest instruction. Any additional costs are applied as a delta
6882 above this default. */
6886 {
6888 /* The cost depends entirely on the operands to SET. */
6894 {
6897 {
6911 }
6920 /* Fall through. */
6922 /* The cost is one per vector-register copied. */
6924 {
6928 }
6929 /* const0_rtx is in general free, but we will use an
6930 instruction to set a register to 0. */
6932 {
6933 /* The cost is 1 per register copied. */
6937 }
6938 else
6939 /* Cost is just the cost of the RHS of the set. */
6945 /* Bit-field insertion. Strip any redundant widening of
6946 the RHS to meet the width of the target. */
6957 {
6958 /* MOV immediate is assumed to always be cheap. */
6960 }
6961 else
6962 {
6963 /* BFM. */
6967 }
6972 /* We can't make sense of this, assume default cost. */
6975 }
6979 /* If an instruction can incorporate a constant within the
6980 instruction, the instruction's expression avoids calling
6981 rtx_cost() on the constant. If rtx_cost() is called on a
6982 constant, then it is usually because the constant must be
6983 moved into a register by one or more instructions.
6985 The exception is constant 0, which can be expressed
6986 as XZR/WZR and is therefore free. The exception to this is
6987 if we have (set (reg) (const0_rtx)) in which case we must cost
6988 the move. However, we can catch that when we cost the SET, so
6989 we don't need to consider that here. */
6992 else
6993 {
6994 /* To an approximation, building any other constant is
6995 proportionally expensive to the number of instructions
6996 required to build that constant. This is true whether we
6997 are compiling for SPEED or otherwise. */
7002 }
7007 /* First determine number of instructions to do the move
7008 as an integer constant. */
7012 {
7018 ? SImode
7024 }
7027 {
7028 /* mov[df,sf]_aarch64. */
7030 /* FMOV (scalar immediate). */
7033 {
7034 /* This will be a load from memory. */
7037 else
7039 }
7040 else
7041 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7042 or MOV v0.s[0], wzr - neither of which are modeled by the
7043 cost tables. Just use the default cost. */
7044 {
7045 }
7046 }
7052 {
7053 /* For loads we want the base cost of a load, plus an
7054 approximation for the additional cost of the addressing
7055 mode. */
7069 }
7077 {
7079 {
7080 /* FNEG. */
7082 }
7084 }
7087 {
7090 {
7091 /* CSETM. */
7094 }
7096 /* Cost this as SUB wzr, X. */
7100 }
7103 {
7104 /* Support (neg(fma...)) as a single instruction only if
7105 sign of zeros is unimportant. This matches the decision
7106 making in aarch64.md. */
7108 {
7109 /* FNMADD. */
7112 }
7114 {
7115 /* FNMUL. */
7118 }
7120 /* FNEG. */
7123 }
7130 {
7133 else
7135 }
7145 {
7149 }
7152 {
7153 /* TODO: A write to the CC flags possibly costs extra, this
7154 needs encoding in the cost tables. */
7157 /* ANDS. */
7159 {
7162 }
7165 {
7166 /* ADDS (and CMN alias). */
7169 }
7172 {
7173 /* SUBS. */
7176 }
7181 {
7182 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7183 Handle it here directly rather than going to cost_logic
7184 since we know the immediate generated for the TST is valid
7185 so we can avoid creating an intermediate rtx for it only
7186 for costing purposes. */
7193 }
7196 {
7197 /* CMN. */
7204 }
7206 /* CMP.
7208 Compare can freely swap the order of operands, and
7209 canonicalization puts the more complex operation first.
7210 But the integer MINUS logic expects the shift/extend
7211 operation in op1. */
7214 {
7217 }
7219 }
7222 {
7223 /* FCMP. */
7228 {
7230 /* FCMP supports constant 0.0 for no extra cost. */
7232 }
7234 }
7237 {
7238 /* Vector compare. */
7243 {
7244 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7245 cost. */
7247 }
7249 }
7253 {
7257 cost_minus:
7260 /* Detect valid immediates. */
7266 {
7268 /* SUB(S) (immediate). */
7271 }
7273 /* Look for SUB (extended register). */
7276 {
7284 }
7288 /* Cost this as an FMA-alike operation. */
7292 {
7295 speed);
7297 }
7302 {
7304 {
7305 /* Vector SUB. */
7307 }
7309 {
7310 /* SUB(S). */
7312 }
7314 {
7315 /* FSUB. */
7317 }
7318 }
7320 }
7323 {
7324 rtx new_op0;
7329 cost_plus:
7332 {
7333 /* CSINC. */
7337 }
7342 {
7346 /* ADD (immediate). */
7349 }
7353 /* Look for ADD (extended register). */
7356 {
7364 }
7366 /* Strip any extend, leave shifts behind as we will
7367 cost them through mult_cost. */
7372 {
7374 speed);
7376 }
7381 {
7383 {
7384 /* Vector ADD. */
7386 }
7388 {
7389 /* ADD. */
7391 }
7393 {
7394 /* FADD. */
7396 }
7397 }
7399 }
7405 {
7408 else
7410 }
7415 {
7419 {
7422 else
7424 }
7426 }
7429 {
7436 }
7437 /* Fall through. */
7440 cost_logic:
7445 {
7449 }
7457 {
7458 /* This is a UBFM/SBFM. */
7463 }
7466 {
7468 {
7469 /* We have a mask + shift version of a UBFIZ
7470 i.e. the *andim_ashift<mode>_bfiz pattern. */
7474 {
7481 }
7483 {
7484 /* We possibly get the immediate for free, this is not
7485 modelled. */
7492 }
7493 }
7494 else
7495 {
7498 /* Handle ORN, EON, or BIC. */
7504 /* If we had a shift on op0 then this is a logical-shift-
7505 by-register/immediate operation. Otherwise, this is just
7506 a logical operation. */
7508 {
7510 {
7511 /* Shift by immediate. */
7514 else
7516 }
7517 else
7519 }
7521 /* In both cases we want to cost both operands. */
7528 }
7529 }
7537 {
7538 /* Vector NOT. */
7541 }
7543 /* MVN-shifted-reg. */
7545 {
7552 }
7553 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7554 Handle the second form here taking care that 'a' in the above can
7555 be a shift. */
7557 {
7566 {
7569 else
7571 }
7574 }
7575 /* MVN. */
7584 /* If a value is written in SI mode, then zero extended to DI
7585 mode, the operation will in general be free as a write to
7586 a 'w' register implicitly zeroes the upper bits of an 'x'
7587 register. However, if this is
7589 (set (reg) (zero_extend (reg)))
7591 we must cost the explicit register move. */
7595 {
7598 /* If OP_COST is non-zero, then the cost of the zero extend
7599 is effectively the cost of the inner operation. Otherwise
7600 we have a MOV instruction and we take the cost from the MOV
7601 itself. This is true independently of whether we are
7602 optimizing for space or time. */
7607 }
7609 {
7610 /* All loads can zero extend to any size for free. */
7613 }
7617 {
7622 }
7625 {
7627 {
7628 /* UMOV. */
7630 }
7631 else
7632 {
7633 /* We generate an AND instead of UXTB/UXTH. */
7635 }
7636 }
7641 {
7642 /* LDRSH. */
7644 {
7651 }
7653 }
7657 {
7662 }
7665 {
7668 else
7670 }
7678 {
7680 {
7682 {
7683 /* Vector shift (immediate). */
7685 }
7686 else
7687 {
7688 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7689 aliases. */
7691 }
7692 }
7694 /* We can incorporate zero/sign extend for free. */
7701 }
7702 else
7703 {
7705 {
7707 /* Vector shift (register). */
7709 }
7710 else
7711 {
7713 /* LSLV. */
7719 {
7721 /* We already demanded XEXP (op1, 0) to be REG_P, so
7722 don't recurse into it. */
7724 }
7725 }
7727 }
7737 {
7738 /* ASR (immediate) and friends. */
7740 {
7743 else
7745 }
7749 }
7750 else
7751 {
7753 {
7755 /* Vector shift (register). */
7757 }
7758 else
7759 {
7761 /* ASR (register) and friends. */
7767 {
7769 /* We already demanded XEXP (op1, 0) to be REG_P, so
7770 don't recurse into it. */
7772 }
7773 }
7775 }
7781 {
7782 /* LDR. */
7785 }
7788 {
7789 /* ADRP, followed by ADD. */
7793 }
7796 {
7797 /* ADR. */
7800 }
7803 {
7804 /* One extra load instruction, after accessing the GOT. */
7808 }
7813 /* ADRP/ADD (immediate). */
7820 /* UBFX/SBFX. */
7822 {
7825 else
7827 }
7829 /* We can trust that the immediates used will be correct (there
7830 are no by-register forms), so we need only cost op0. */
7836 /* aarch64_rtx_mult_cost always handles recursion to its
7837 operands. */
7841 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7842 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7843 an unconditional negate. This case should only ever be reached through
7844 the set_smod_pow2_cheap check in expmed.c. */
7848 {
7849 /* We expand to 4 instructions. Reset the baseline. */
7857 }
7859 /* Fall-through. */
7862 {
7863 /* Slighly prefer UMOD over SMOD. */
7870 }
7877 {
7881 /* There is no integer SQRT, so only DIV and UDIV can get
7882 here. */
7884 /* Slighly prefer UDIV over SDIV. */
7886 else
7888 }
7914 {
7917 else
7919 }
7921 /* FMSUB, FNMADD, and FNMSUB are free. */
7928 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7929 and the by-element operand as operand 0. */
7933 /* Catch vector-by-element operations. The by-element operand can
7934 either be (vec_duplicate (vec_select (x))) or just
7935 (vec_select (x)), depending on whether we are multiplying by
7936 a vector or a scalar.
7938 Canonicalization is not very good in these cases, FMA4 will put the
7939 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7950 /* If the remaining parameters are not registers,
7951 get the cost to put them into registers. */
7965 {
7967 {
7968 /*Vector truncate. */
7970 }
7971 else
7973 }
7978 {
7980 {
7981 /*Vector conversion. */
7983 }
7984 else
7986 }
7992 /* Strip the rounding part. They will all be implemented
7993 by the fcvt* family of instructions anyway. */
7995 {
8004 }
8007 {
8010 else
8012 }
8014 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8015 fixed-point fcvt. */
8020 {
8024 }
8031 {
8032 /* ABS (vector). */
8035 }
8037 {
8040 /* FABD, which is analogous to FADD. */
8042 {
8049 }
8050 /* Simple FABS is analogous to FNEG. */
8053 }
8054 else
8055 {
8056 /* Integer ABS will either be split to
8057 two arithmetic instructions, or will be an ABS
8058 (scalar), which we don't model. */
8062 }
8068 {
8071 else
8072 {
8073 /* FMAXNM/FMINNM/FMAX/FMIN.
8074 TODO: This may not be accurate for all implementations, but
8075 we do not model this in the cost tables. */
8077 }
8078 }
8082 /* The floating point round to integer frint* instructions. */
8084 {
8089 }
8092 {
8097 }
8102 /* Decompose <su>muldi3_highpart. */
8104 mode == DImode
8105 /* (lshiftrt:TI */
8108 /* (mult:TI */
8110 /* (ANY_EXTEND:TI (reg:DI))
8111 (ANY_EXTEND:TI (reg:DI))) */
8118 /* (const_int 64) */
8121 {
8122 /* UMULH/SMULH. */
8130 }
8132 /* Fall through. */
8135 }
8143 }
8145 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8146 calculated for X. This cost is stored in *COST. Returns true
8147 if the total cost of X was calculated. */
8148 static bool
8151 {
8156 {
8161 }
8164 }
8166 static int
8169 {
8175 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8182 /* Moving between GPR and stack cost is the same as GP2GP. */
8187 /* To/From the stack register, we move via the gprs. */
8193 {
8194 /* 128-bit operations on general registers require 2 instructions. */
8202 /* When AdvSIMD instructions are disabled it is not possible to move
8203 a 128-bit value directly between Q registers. This is handled in
8204 secondary reload. A general register is used as a scratch to move
8205 the upper DI value and the lower DI value is moved directly,
8206 hence the cost is the sum of three moves. */
8211 }
8221 }
8223 static int
8225 reg_class_t rclass ATTRIBUTE_UNUSED,
8227 {
8229 }
8231 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8232 to optimize 1.0/sqrt. */
8234 static bool
8236 {
8238 && flag_unsafe_math_optimizations
8242 }
8244 /* Function to decide when to use the approximate reciprocal square root
8245 builtin. */
8247 static tree
8249 {
8255 }
8259 /* Select reciprocal square root initial estimate insn depending on machine
8260 mode. */
8262 static rsqrte_type
8264 {
8266 {
8273 }
8274 }
8278 /* Select reciprocal square root series step insn depending on machine mode. */
8280 static rsqrts_type
8282 {
8284 {
8291 }
8292 }
8294 /* Emit instruction sequence to compute either the approximate square root
8295 or its approximate reciprocal, depending on the flag RECP, and return
8296 whether the sequence was emitted or not. */
8298 bool
8300 {
8304 {
8307 }
8310 {
8317 || flag_trapping_math
8318 || !flag_unsafe_math_optimizations
8321 }
8322 else
8323 /* Caller assumes we cannot fail. */
8329 /* When calculating the approximate square root, compare the
8330 argument with 0.0 and create a mask. */
8336 /* Estimate the approximate reciprocal square root. */
8340 /* Iterate over the series twice for SF and thrice for DF. */
8343 /* Optionally iterate over the series once less for faster performance
8344 while sacrificing the accuracy. */
8347 iterations--;
8349 /* Iterate over the series to calculate the approximate reciprocal square
8350 root. */
8353 {
8361 }
8364 {
8365 /* Qualify the approximate reciprocal square root when the argument is
8366 0.0 by squashing the intermediary result to 0.0. */
8372 /* Calculate the approximate square root. */
8374 }
8376 /* Finalize the approximation. */
8380 }
8384 /* Select reciprocal initial estimate insn depending on machine mode. */
8386 static recpe_type
8388 {
8390 {
8397 }
8398 }
8402 /* Select reciprocal series step insn depending on machine mode. */
8404 static recps_type
8406 {
8408 {
8415 }
8416 }
8418 /* Emit the instruction sequence to compute the approximation for the division
8419 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8421 bool
8423 {
8434 || flag_trapping_math
8435 || !flag_unsafe_math_optimizations
8440 /* Estimate the approximate reciprocal. */
8444 /* Iterate over the series twice for SF and thrice for DF. */
8447 /* Optionally iterate over the series once less for faster performance,
8448 while sacrificing the accuracy. */
8450 iterations--;
8452 /* Iterate over the series to calculate the approximate reciprocal. */
8455 {
8460 }
8463 {
8464 /* As the approximate reciprocal of DEN is already calculated, only
8465 calculate the approximate division when NUM is not 1.0. */
8468 }
8470 /* Finalize the approximation. */
8473 }
8475 /* Return the number of instructions that can be issued per cycle. */
8476 static int
8478 {
8480 }
8482 static int
8484 {
8488 }
8491 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8492 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8493 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8495 static int
8498 {
8500 }
8503 /* Vectorizer cost model target hooks. */
8505 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8506 static int
8508 tree vectype,
8510 {
8519 {
8568 }
8569 }
8571 /* Implement targetm.vectorize.add_stmt_cost. */
8572 static unsigned
8576 {
8581 {
8586 /* Statements in an inner loop relative to the loop being
8587 vectorized are weighted more heavily. The value here is
8588 arbitrary and could potentially be improved with analysis. */
8594 }
8597 }
8601 /* Parse the TO_PARSE string and put the architecture struct that it
8602 selects into RES and the architectural features into ISA_FLAGS.
8603 Return an aarch64_parse_opt_result describing the parse result.
8604 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8606 static enum aarch64_parse_opt_result
8609 {
8621 else
8628 /* Loop through the list of supported ARCHes to find a match. */
8630 {
8632 {
8636 {
8637 /* TO_PARSE string contains at least one extension. */
8638 enum aarch64_parse_opt_result ext_res
8643 }
8644 /* Extension parsing was successful. Confirm the result
8645 arch and ISA flags. */
8649 }
8650 }
8652 /* ARCH name not found in list. */
8654 }
8656 /* Parse the TO_PARSE string and put the result tuning in RES and the
8657 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8658 describing the parse result. If there is an error parsing, RES and
8659 ISA_FLAGS are left unchanged. */
8661 static enum aarch64_parse_opt_result
8664 {
8676 else
8683 /* Loop through the list of supported CPUs to find a match. */
8685 {
8687 {
8692 {
8693 /* TO_PARSE string contains at least one extension. */
8694 enum aarch64_parse_opt_result ext_res
8699 }
8700 /* Extension parsing was successfull. Confirm the result
8701 cpu and ISA flags. */
8705 }
8706 }
8708 /* CPU name not found in list. */
8710 }
8712 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8713 Return an aarch64_parse_opt_result describing the parse result.
8714 If the parsing fails the RES does not change. */
8716 static enum aarch64_parse_opt_result
8718 {
8724 /* Loop through the list of supported CPUs to find a match. */
8726 {
8728 {
8731 }
8732 }
8734 /* CPU name not found in list. */
8736 }
8738 /* Parse TOKEN, which has length LENGTH to see if it is an option
8739 described in FLAG. If it is, return the index bit for that fusion type.
8740 If not, error (printing OPTION_NAME) and return zero. */
8742 static unsigned int
8747 {
8749 {
8753 }
8757 }
8759 /* Parse OPTION which is a comma-separated list of flags to enable.
8760 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8761 default state we inherit from the CPU tuning structures. OPTION_NAME
8762 gives the top-level option we are parsing in the -moverride string,
8763 for use in error messages. */
8765 static unsigned int
8770 {
8777 {
8780 token_length,
8781 flags,
8782 option_name);
8783 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8784 in the token stream, reset the supported operations. So:
8786 adrp+add.cmp+branch.none.adrp+add
8788 would have the result of turning on only adrp+add fusion. */
8794 }
8796 /* We ended with a comma, print something. */
8798 {
8801 }
8803 /* We still have one more token to parse. */
8806 token_length,
8807 flags,
8808 option_name);
8814 }
8816 /* Support for overriding instruction fusion. */
8818 static void
8821 {
8823 aarch64_fusible_pairs,
8826 }
8828 /* Support for overriding other tuning flags. */
8830 static void
8833 {
8834 tune->extra_tuning_flags
8836 aarch64_tuning_flags,
8839 }
8841 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8842 we understand. If it is, extract the option string and handoff to
8843 the appropriate function. */
8845 void
8849 {
8855 {
8858 }
8860 /* Get the length of the option name. */
8862 /* Skip the '=' to get to the option string. */
8863 option_part++;
8866 {
8868 {
8871 }
8872 }
8876 }
8878 /* A checking mechanism for the implementation of the tls size. */
8880 static void
8882 {
8887 {
8889 /* Both the default and maximum TLS size allowed under tiny is 1M which
8890 needs two instructions to address, so we clamp the size to 24. */
8895 /* The maximum TLS size allowed under small is 4G. */
8900 /* The maximum TLS size allowed under large is 16E.
8901 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8907 }
8910 }
8912 /* Parse STRING looking for options in the format:
8913 string :: option:string
8914 option :: name=substring
8915 name :: {a-z}
8916 substring :: defined by option. */
8918 static void
8921 {
8932 {
8934 /* Make this substring look like a string. */
8938 }
8940 /* One last option to parse. */
8943 }
8946 static void
8948 {
8949 /* The logic here is that if we are disabling all frame pointer generation
8950 then we do not need to disable leaf frame pointer generation as a
8951 separate operation. But if we are *only* disabling leaf frame pointer
8952 generation then we set flag_omit_frame_pointer to true, but in
8953 aarch64_frame_pointer_required we return false only for leaf functions.
8955 PR 70044: We have to be careful about being called multiple times for the
8956 same function. Once we have decided to set flag_omit_frame_pointer just
8957 so that we can omit leaf frame pointers, we must then not interpret a
8958 second call as meaning that all frame pointer generation should be
8959 omitted. We do this by setting flag_omit_frame_pointer to a special,
8960 non-zero value. */
8969 /* If not optimizing for size, set the default
8970 alignment to what the target wants. */
8972 {
8979 }
8981 /* We default to no pc-relative literal loads. */
8985 /* If -mpc-relative-literal-loads is set on the command line, this
8986 implies that the user asked for PC relative literal loads. */
8990 /* This is PR70113. When building the Linux kernel with
8991 CONFIG_ARM64_ERRATUM_843419, support for relocations
8992 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8993 removed from the kernel to avoid loading objects with possibly
8994 offending sequences. Without -mpc-relative-literal-loads we would
8995 generate such relocations, preventing the kernel build from
8996 succeeding. */
9001 /* In the tiny memory model it makes no sense to disallow PC relative
9002 literal pool loads. */
9007 /* When enabling the lower precision Newton series for the square root, also
9008 enable it for the reciprocal square root, since the latter is an
9009 intermediary step for the former. */
9012 }
9014 /* 'Unpack' up the internal tuning structs and update the options
9015 in OPTS. The caller must have set up selected_tune and selected_arch
9016 as all the other target-specific codegen decisions are
9017 derived from them. */
9019 void
9021 {
9024 /* Make a copy of the tuning parameters attached to the core, which
9025 we may later overwrite. */
9033 /* This target defaults to strict volatile bitfields. */
9042 {
9054 }
9056 /* We don't mind passing in global_options_set here as we don't use
9057 the *options_set structs anyway. */
9059 queue_depth,
9063 /* Set up parameters to be used in prefetching algorithm. Do not
9064 override the defaults unless we are tuning for a core we have
9065 researched values for. */
9087 /* Enable sw prefetching at specified optimization level for
9088 CPUS that have prefetch. Lower optimization level threshold by 1
9089 when profiling is enabled. */
9097 }
9099 /* Print a hint with a suggestion for a core or architecture name that
9100 most closely resembles what the user passed in STR. ARCH is true if
9101 the user is asking for an architecture name. ARCH is false if the user
9102 is asking for a core name. */
9104 static void
9106 {
9117 }
9119 /* Print a hint with a suggestion for a core name that most closely resembles
9120 what the user passed in STR. */
9124 {
9126 }
9128 /* Print a hint with a suggestion for an architecture name that most closely
9129 resembles what the user passed in STR. */
9133 {
9135 }
9137 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9138 specified in STR and throw errors if appropriate. Put the results if
9139 they are valid in RES and ISA_FLAGS. Return whether the option is
9140 valid. */
9142 static bool
9145 {
9146 enum aarch64_parse_opt_result parse_res
9153 {
9166 }
9169 }
9171 /* Validate a command-line -march option. Parse the arch and extensions
9172 (if any) specified in STR and throw errors if appropriate. Put the
9173 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9174 option is valid. */
9176 static bool
9179 {
9180 enum aarch64_parse_opt_result parse_res
9187 {
9200 }
9203 }
9205 /* Validate a command-line -mtune option. Parse the cpu
9206 specified in STR and throw errors if appropriate. Put the
9207 result, if it is valid, in RES. Return whether the option is
9208 valid. */
9210 static bool
9212 {
9213 enum aarch64_parse_opt_result parse_res
9220 {
9230 }
9232 }
9234 /* Return the CPU corresponding to the enum CPU.
9235 If it doesn't specify a cpu, return the default. */
9239 {
9243 /* The & 0x3f is to extract the bottom 6 bits that encode the
9244 default cpu as selected by the --with-cpu GCC configure option
9245 in config.gcc.
9246 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9247 flags mechanism should be reworked to make it more sane. */
9249 }
9251 /* Return the architecture corresponding to the enum ARCH.
9252 If it doesn't specify a valid architecture, return the default. */
9256 {
9263 }
9265 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9266 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9267 tuning structs. In particular it must set selected_tune and
9268 aarch64_isa_flags that define the available ISA features and tuning
9269 decisions. It must also set selected_arch as this will be used to
9270 output the .arch asm tags for each function. */
9272 static void
9274 {
9287 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9288 If either of -march or -mtune is given, they override their
9289 respective component of -mcpu. */
9301 /* If the user did not specify a processor, choose the default
9302 one for them. This will be the CPU set during configuration using
9303 --with-cpu, otherwise it is "generic". */
9305 {
9307 {
9311 }
9312 else
9313 {
9314 /* Get default configure-time CPU. */
9317 }
9321 }
9322 /* If both -mcpu and -march are specified check that they are architecturally
9323 compatible, warn if they're not and prefer the -march ISA flags. */
9325 {
9327 {
9331 }
9336 }
9337 else
9338 {
9339 /* -mcpu but no -march. */
9346 }
9348 /* Set the arch as well as we will need it when outputing
9349 the .arch directive in assembly. */
9351 {
9354 }
9359 #ifndef HAVE_AS_MABI_OPTION
9360 /* The compiler may have been configured with 2.23.* binutils, which does
9361 not have support for ILP32. */
9364 #endif
9369 /* Make sure we properly set up the explicit options. */
9380 /* Save these options as the default ones in case we push and pop them later
9381 while processing functions with potential target attributes. */
9382 target_option_default_node = target_option_current_node
9384 }
9386 /* Implement targetm.override_options_after_change. */
9388 static void
9390 {
9392 }
9396 {
9400 }
9402 void
9404 {
9406 }
9408 /* A checking mechanism for the implementation of the various code models. */
9409 static void
9411 {
9413 {
9415 {
9420 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9422 ? AARCH64_CMODEL_SMALL_PIC
9424 #else
9426 #endif
9434 }
9435 }
9436 else
9438 }
9440 /* Implement TARGET_OPTION_SAVE. */
9442 static void
9444 {
9446 }
9448 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9449 using the information saved in PTR. */
9451 static void
9453 {
9461 }
9463 /* Implement TARGET_OPTION_PRINT. */
9465 static void
9467 {
9478 }
9482 void
9484 {
9486 }
9488 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9489 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9490 make sure optab availability predicates are recomputed when necessary. */
9492 void
9494 {
9499 else
9501 }
9503 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9504 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9505 of the function, if such exists. This function may be called multiple
9506 times on a single function so use aarch64_previous_fndecl to avoid
9507 setting up identical state. */
9509 static void
9511 {
9515 tree old_tree = (aarch64_previous_fndecl
9521 /* If current function has no attributes but the previous one did,
9522 use the default node. */
9526 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9527 the default have been handled by aarch64_save_restore_target_globals from
9528 aarch64_pragma_target_parse. */
9534 /* First set the target options. */
9538 }
9540 /* Enum describing the various ways we can handle attributes.
9541 In many cases we can reuse the generic option handling machinery. */
9543 enum aarch64_attr_opt_type
9544 {
9548 aarch64_attr_custom /* Attribute requires a custom handling function. */
9549 };
9551 /* All the information needed to handle a target attribute.
9552 NAME is the name of the attribute.
9553 ATTR_TYPE specifies the type of behavior of the attribute as described
9554 in the definition of enum aarch64_attr_opt_type.
9555 ALLOW_NEG is true if the attribute supports a "no-" form.
9556 HANDLER is the function that takes the attribute string and whether
9557 it is a pragma or attribute and handles the option. It is needed only
9558 when the ATTR_TYPE is aarch64_attr_custom.
9559 OPT_NUM is the enum specifying the option that the attribute modifies.
9560 This is needed for attributes that mirror the behavior of a command-line
9561 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9562 aarch64_attr_enum. */
9564 struct aarch64_attribute_info
9565 {
9571 };
9573 /* Handle the ARCH_STR argument to the arch= target attribute.
9574 PRAGMA_OR_ATTR is used in potential error messages. */
9576 static bool
9578 {
9580 enum aarch64_parse_opt_result parse_res
9584 {
9589 }
9592 {
9606 }
9609 }
9611 /* Handle the argument CPU_STR to the cpu= target attribute.
9612 PRAGMA_OR_ATTR is used in potential error messages. */
9614 static bool
9616 {
9618 enum aarch64_parse_opt_result parse_res
9622 {
9630 }
9633 {
9647 }
9650 }
9652 /* Handle the argument STR to the tune= target attribute.
9653 PRAGMA_OR_ATTR is used in potential error messages. */
9655 static bool
9657 {
9659 enum aarch64_parse_opt_result parse_res
9663 {
9668 }
9671 {
9678 }
9681 }
9683 /* Parse an architecture extensions target attribute string specified in STR.
9684 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9685 if successful. Update aarch64_isa_flags to reflect the ISA features
9686 modified.
9687 PRAGMA_OR_ATTR is used in potential error messages. */
9689 static bool
9691 {
9695 /* We allow "+nothing" in the beginning to clear out all architectural
9696 features if the user wants to handpick specific features. */
9698 {
9701 }
9706 {
9709 }
9712 {
9725 }
9728 }
9730 /* The target attributes that we support. On top of these we also support just
9731 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9732 handled explicitly in aarch64_process_one_target_attr. */
9735 {
9737 OPT_mgeneral_regs_only },
9739 OPT_mfix_cortex_a53_835769 },
9741 OPT_mfix_cortex_a53_843419 },
9745 OPT_momit_leaf_frame_pointer },
9748 OPT_march_ },
9751 OPT_mtune_ },
9753 OPT_msign_return_address_ },
9755 };
9757 /* Parse ARG_STR which contains the definition of one target attribute.
9758 Show appropriate errors if any or return true if the attribute is valid.
9759 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9760 we're processing a target attribute or pragma. */
9762 static bool
9764 {
9770 {
9773 }
9778 /* Skip leading whitespace. */
9780 str_to_check++;
9782 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9783 It is easier to detect and handle it explicitly here rather than going
9784 through the machinery for the rest of the target attributes in this
9785 function. */
9790 {
9793 }
9796 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9797 and point ARG to "foo". */
9799 {
9801 arg++;
9802 }
9806 {
9807 /* If the names don't match up, or the user has given an argument
9808 to an attribute that doesn't accept one, or didn't give an argument
9809 to an attribute that expects one, fail to match. */
9818 {
9822 }
9824 /* If the name matches but the attribute does not allow "no-" versions
9825 then we can't match. */
9827 {
9831 }
9834 {
9835 /* Has a custom handler registered.
9836 For example, cpu=, arch=, tune=. */
9843 /* Either set or unset a boolean option. */
9845 {
9853 }
9854 /* Set or unset a bit in the target_flags. aarch64_handle_option
9855 should know what mask to apply given the option number. */
9857 {
9859 /* We only need to specify the option number.
9860 aarch64_handle_option will know which mask to apply. */
9866 }
9867 /* Use the option setting machinery to set an option to an enum. */
9869 {
9876 {
9879 global_dc);
9880 }
9881 else
9882 {
9885 }
9887 }
9890 }
9891 }
9893 /* If we reached here we either have found an attribute and validated
9894 it or didn't match any. If we matched an attribute but its arguments
9895 were malformed we will have returned false already. */
9897 }
9899 /* Count how many times the character C appears in
9900 NULL-terminated string STR. */
9902 static unsigned int
9904 {
9907 {
9909 res++;
9911 str++;
9912 }
9915 }
9917 /* Parse the tree in ARGS that contains the target attribute information
9918 and update the global target options space. PRAGMA_OR_ATTR is a string
9919 to be used in error messages, specifying whether this is processing
9920 a target attribute or a target pragma. */
9922 bool
9924 {
9926 {
9927 do
9928 {
9931 {
9934 }
9939 }
9942 {
9945 }
9952 {
9955 }
9957 /* Used to catch empty spaces between commas i.e.
9958 attribute ((target ("attr1,,attr2"))). */
9961 /* Handle multiple target attributes separated by ','. */
9966 {
9967 num_attrs++;
9969 {
9972 }
9975 }
9978 {
9982 }
9985 }
9987 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9988 process attribute ((target ("..."))). */
9990 static bool
9992 {
9995 tree old_optimize;
9999 /* If what we're processing is the current pragma string then the
10000 target option node is already stored in target_option_current_node
10001 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
10002 having to re-parse the string. This is especially useful to keep
10003 arm_neon.h compile times down since that header contains a lot
10004 of intrinsics enclosed in pragmas. */
10006 {
10009 }
10015 /* If the function changed the optimization levels as well as setting
10016 target options, start with the optimizations specified. */
10021 /* Save the current target options to restore at the end. */
10024 /* If fndecl already has some target attributes applied to it, unpack
10025 them so that we add this attribute on top of them, rather than
10026 overwriting them. */
10028 {
10034 }
10035 else
10042 /* Set up any additional state. */
10044 {
10046 /* Initialize SIMD builtins if we haven't already.
10047 Set current_target_pragma to NULL for the duration so that
10048 the builtin initialization code doesn't try to tag the functions
10049 being built with the attributes specified by any current pragma, thus
10050 going into an infinite recursion. */
10052 {
10057 }
10059 }
10060 else
10066 {
10071 }
10079 }
10081 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10082 tri-bool options (yes, no, don't care) and the default value is
10083 DEF, determine whether to reject inlining. */
10085 static bool
10088 {
10089 /* If the callee doesn't care, always allow inlining. */
10093 /* If the caller doesn't care, always allow inlining. */
10097 /* Otherwise, allow inlining if either the callee and caller values
10098 agree, or if the callee is using the default value. */
10100 }
10102 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10103 to inline CALLEE into CALLER based on target-specific info.
10104 Make sure that the caller and callee have compatible architectural
10105 features. Then go through the other possible target attributes
10106 and see if they can block inlining. Try not to reject always_inline
10107 callees unless they are incompatible architecturally. */
10109 static bool
10111 {
10115 /* If callee has no option attributes, then it is ok to inline. */
10126 /* Callee's ISA flags should be a subset of the caller's. */
10131 /* Allow non-strict aligned functions inlining into strict
10132 aligned ones. */
10142 /* If the architectural features match up and the callee is always_inline
10143 then the other attributes don't matter. */
10155 /* Honour explicit requests to workaround errata. */
10168 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10169 caller and calle and they don't match up, reject inlining. */
10176 /* If the callee has specific tuning overrides, respect them. */
10181 /* If the user specified tuning override strings for the
10182 caller and callee and they don't match up, reject inlining.
10183 We just do a string compare here, we don't analyze the meaning
10184 of the string, as it would be too costly for little gain. */
10192 }
10194 /* Return true if SYMBOL_REF X binds locally. */
10196 static bool
10198 {
10202 }
10204 /* Return true if SYMBOL_REF X is thread local */
10205 static bool
10207 {
10215 }
10217 /* Classify a TLS symbol into one of the TLS kinds. */
10218 enum aarch64_symbol_type
10220 {
10224 {
10231 {
10237 }
10248 else
10257 }
10258 }
10260 /* Return the method that should be used to access SYMBOL_REF or
10261 LABEL_REF X. */
10263 enum aarch64_symbol_type
10265 {
10267 {
10269 {
10284 }
10285 }
10288 {
10293 {
10295 /* When we retrieve symbol + offset address, we have to make sure
10296 the offset does not cause overflow of the final address. But
10297 we have no way of knowing the address of symbol at compile time
10298 so we can't accurately say if the distance between the PC and
10299 symbol + offset is outside the addressible range of +/-1M in the
10300 TINY code model. So we rely on images not being greater than
10301 1M and cap the offset at 1M and anything beyond 1M will have to
10302 be loaded using an alternative mechanism. Furthermore if the
10303 symbol is a weak reference to something that isn't known to
10304 resolve to a symbol in this module, then force to memory. */
10312 /* Same reasoning as the tiny code model, but the offset cap here is
10313 4G. */
10334 /* This is alright even in PIC code as the constant
10335 pool reference is always PC relative and within
10336 the same translation unit. */
10339 else
10344 }
10345 }
10347 /* By default push everything into the constant pool. */
10349 }
10351 bool
10353 {
10355 }
10357 bool
10359 {
10367 }
10369 /* Return true if X holds either a quarter-precision or
10370 floating-point +0.0 constant. */
10371 static bool
10373 {
10377 /* This call determines which constants can be used in mov<mode>
10378 as integer moves instead of constant loads. */
10383 }
10385 static bool
10387 {
10388 /* Do not allow vector struct mode constants. We could support
10389 0 and -1 easily, but they need support in aarch64-simd.md. */
10393 /* For these cases we never want to use a literal load.
10394 As such we have to prevent the compiler from forcing these
10395 to memory. */
10408 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10409 so spilling them is better than rematerialization. */
10414 }
10416 rtx
10418 {
10424 /* Can return in any reg. */
10427 }
10429 /* On AAPCS systems, this is the "struct __va_list". */
10432 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10433 Return the type to use as __builtin_va_list.
10435 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10437 struct __va_list
10438 {
10439 void *__stack;
10440 void *__gr_top;
10441 void *__vr_top;
10442 int __gr_offs;
10443 int __vr_offs;
10444 }; */
10446 static tree
10448 {
10449 tree va_list_name;
10452 /* Create the type. */
10454 /* Give it the required name. */
10456 TYPE_DECL,
10458 va_list_type);
10463 /* Create the fields. */
10466 ptr_type_node);
10469 ptr_type_node);
10472 ptr_type_node);
10475 integer_type_node);
10478 integer_type_node);
10480 /* Tell tree-stdarg pass about our internal offset fields.
10481 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10482 purpose to identify whether the code is updating va_list internal
10483 offset fields through irregular way. */
10505 /* Compute its layout. */
10509 }
10511 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10512 static void
10514 {
10518 tree t;
10532 {
10535 }
10544 NULL_TREE);
10546 NULL_TREE);
10548 NULL_TREE);
10550 NULL_TREE);
10552 NULL_TREE);
10554 /* Emit code to initialize STACK, which points to the next varargs stack
10555 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10556 by named arguments. STACK is 8-byte aligned. */
10563 /* Emit code to initialize GRTOP, the top of the GR save area.
10564 virtual_incoming_args_rtx should have been 16 byte aligned. */
10569 /* Emit code to initialize VRTOP, the top of the VR save area.
10570 This address is gr_save_area_bytes below GRTOP, rounded
10571 down to the next 16-byte boundary. */
10581 /* Emit code to initialize GROFF, the offset from GRTOP of the
10582 next GPR argument. */
10587 /* Likewise emit code to initialize VROFF, the offset from FTOP
10588 of the next VR argument. */
10592 }
10594 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10596 static tree
10599 {
10600 tree addr;
10606 machine_mode mode;
10633 type,
10637 {
10638 /* TYPE passed in fp/simd registers. */
10650 {
10653 }
10656 {
10658 }
10659 }
10660 else
10661 {
10662 /* TYPE passed in general registers. */
10675 {
10677 }
10678 }
10680 /* Get a local temporary for the field value. */
10683 /* Emit code to branch if off >= 0. */
10689 {
10690 /* Emit: offs = (offs + 15) & -16. */
10696 }
10697 else
10700 /* Update ap.__[g|v]r_offs */
10705 /* String up. */
10709 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10714 /* String up: make sure the assignment happens before the use. */
10718 /* Prepare the trees handling the argument that is passed on the stack;
10719 the top level node will store in ON_STACK. */
10722 {
10723 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10731 }
10732 else
10734 /* Advance ap.__stack */
10742 /* String up roundup and advance. */
10745 /* String up with arg */
10747 /* Big-endianness related address adjustment. */
10750 {
10754 }
10759 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10769 {
10770 /* type ha; // treat as "struct {ftype field[n];}"
10771 ... [computing offs]
10772 for (i = 0; i <nregs; ++i, offs += 16)
10773 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10774 return ha; */
10778 /* Declare a local variable. */
10782 /* Establish the base type. */
10784 {
10803 {
10807 }
10811 }
10813 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10821 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10823 {
10833 }
10837 }
10847 }
10849 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10851 static void
10855 {
10857 CUMULATIVE_ARGS local_cum;
10861 /* The caller has advanced CUM up to, but not beyond, the last named
10862 argument. Advance a local copy of CUM past the last "real" named
10863 argument, to find out how many registers are left over. */
10867 /* Found out how many registers we need to save.
10868 Honor tree-stdvar analysis results. */
10877 {
10880 }
10883 {
10885 {
10888 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10896 }
10898 {
10899 /* We can't use move_block_from_reg, because it will use
10900 the wrong mode, storing D regs only. */
10904 /* Set OFF to the offset from virtual_incoming_args_rtx of
10905 the first vector register. The VR save area lies below
10906 the GR one, and is aligned to 16 bytes. */
10913 {
10921 }
10922 }
10923 }
10925 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10926 any complication of having crtl->args.pretend_args_size changed. */
10931 }
10933 static void
10935 {
10938 {
10940 {
10943 }
10944 }
10945 }
10947 /* Walk down the type tree of TYPE counting consecutive base elements.
10948 If *MODEP is VOIDmode, then set it to the first valid floating point
10949 type. If a non-floating point type is found, or if a floating point
10950 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10951 otherwise return the count in the sub-tree. */
10952 static int
10954 {
10955 machine_mode mode;
10956 HOST_WIDE_INT size;
10959 {
10989 /* Use V2SImode and V4SImode as representatives of all 64-bit
10990 and 128-bit vector types. */
10993 {
11002 }
11007 /* Vector modes are considered to be opaque: two vectors are
11008 equivalent for the purposes of being homogeneous aggregates
11009 if they are the same size. */
11016 {
11020 /* Can't handle incomplete types nor sizes that are not
11021 fixed. */
11028 || !index
11039 /* There must be no padding. */
11044 }
11047 {
11050 tree field;
11052 /* Can't handle incomplete types nor sizes that are not
11053 fixed. */
11059 {
11067 }
11069 /* There must be no padding. */
11074 }
11078 {
11079 /* These aren't very interesting except in a degenerate case. */
11082 tree field;
11084 /* Can't handle incomplete types nor sizes that are not
11085 fixed. */
11091 {
11099 }
11101 /* There must be no padding. */
11106 }
11110 }
11113 }
11115 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11116 type as described in AAPCS64 \S 4.1.2.
11118 See the comment above aarch64_composite_type_p for the notes on MODE. */
11120 static bool
11122 machine_mode mode)
11123 {
11133 }
11135 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11136 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11137 array types. The C99 floating-point complex types are also considered
11138 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11139 types, which are GCC extensions and out of the scope of AAPCS64, are
11140 treated as composite types here as well.
11142 Note that MODE itself is not sufficient in determining whether a type
11143 is such a composite type or not. This is because
11144 stor-layout.c:compute_record_mode may have already changed the MODE
11145 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11146 structure with only one field may have its MODE set to the mode of the
11147 field. Also an integer mode whose size matches the size of the
11148 RECORD_TYPE type may be used to substitute the original mode
11149 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11150 solely relied on. */
11152 static bool
11154 machine_mode mode)
11155 {
11168 }
11170 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11171 shall be passed or returned in simd/fp register(s) (providing these
11172 parameter passing registers are available).
11174 Upon successful return, *COUNT returns the number of needed registers,
11175 *BASE_MODE returns the mode of the individual register and when IS_HAF
11176 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11177 floating-point aggregate or a homogeneous short-vector aggregate. */
11179 static bool
11181 const_tree type,
11185 {
11193 {
11196 }
11198 {
11202 }
11204 {
11208 {
11211 }
11212 else
11214 }
11215 else
11220 }
11222 /* Implement TARGET_STRUCT_VALUE_RTX. */
11224 static rtx
11227 {
11229 }
11231 /* Implements target hook vector_mode_supported_p. */
11232 static bool
11234 {
11246 }
11248 /* Return appropriate SIMD container
11249 for MODE within a vector of WIDTH bits. */
11250 static machine_mode
11252 {
11255 {
11258 {
11275 }
11276 else
11278 {
11291 }
11292 }
11294 }
11296 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11297 static machine_mode
11299 {
11301 }
11303 /* Return the bitmask of possible vector sizes for the vectorizer
11304 to iterate over. */
11305 static unsigned int
11307 {
11309 }
11311 /* Implement TARGET_MANGLE_TYPE. */
11315 {
11316 /* The AArch64 ABI documents say that "__va_list" has to be
11317 managled as if it is in the "std" namespace. */
11321 /* Half-precision float. */
11325 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11326 builtin types. */
11330 /* Use the default mangling. */
11332 }
11334 /* Find the first rtx_insn before insn that will generate an assembly
11335 instruction. */
11339 {
11343 do
11344 {
11346 }
11350 }
11352 static bool
11354 {
11356 /* A number of these may be AArch32 only. */
11361 };
11364 {
11367 }
11370 }
11372 /* Check if there is a register dependency between a load and the insn
11373 for which we hold recog_data. */
11375 static bool
11377 {
11378 rtx load_reg;
11388 {
11394 }
11396 }
11399 /* When working around the Cortex-A53 erratum 835769,
11400 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11401 instruction and has a preceding memory instruction such that a NOP
11402 should be inserted between them. */
11404 bool
11406 {
11409 rtx body;
11422 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11423 Restore recog state to INSN to avoid state corruption. */
11431 /* If the previous insn is a memory op and there is no dependency between
11432 it and the DImode madd, emit a NOP between them. If body is NULL then we
11433 have a complex memory operation, probably a load/store pair.
11434 Be conservative for now and emit a NOP. */
11441 }
11444 /* Implement FINAL_PRESCAN_INSN. */
11446 void
11448 {
11451 }
11454 /* Return the equivalent letter for size. */
11455 static char
11457 {
11459 {
11465 }
11466 }
11468 /* Return true iff x is a uniform vector of floating-point
11469 constants, and the constant can be represented in
11470 quarter-precision form. Note, as aarch64_float_const_representable
11471 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11472 static bool
11474 {
11475 rtx elt;
11479 }
11481 /* Return true for valid and false for invalid. */
11482 bool
11485 {
11486 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11487 matches = 1; \
11488 for (i = 0; i < idx; i += (STRIDE)) \
11489 if (!(TEST)) \
11490 matches = 0; \
11491 if (matches) \
11492 { \
11493 immtype = (CLASS); \
11494 elsize = (ELSIZE); \
11495 eshift = (SHIFT); \
11496 emvn = (NEG); \
11497 break; \
11498 }
11508 {
11514 {
11516 scalar_float_mode elt_mode
11523 }
11526 }
11528 /* Splat vector constant out into a byte vector. */
11530 {
11531 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11532 it must be laid out in the vector register in reverse order. */
11540 {
11543 }
11545 }
11547 /* Sanity check. */
11550 do
11551 {
11600 }
11607 {
11617 /* Un-invert bytes of recognized vector, if necessary. */
11623 {
11624 /* FIXME: Broken on 32-bit H_W_I hosts. */
11633 }
11634 else
11635 {
11639 /* Construct 'abcdefgh' because the assembler cannot handle
11640 generic constants. */
11645 }
11646 }
11649 #undef CHECK
11650 }
11652 /* Check of immediate shift constants are within range. */
11653 bool
11655 {
11659 else
11661 }
11663 /* Return true if X is a uniform vector where all elements
11664 are either the floating-point constant 0.0 or the
11665 integer constant 0. */
11666 bool
11668 {
11670 }
11673 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11674 operation of width WIDTH at bit position POS. */
11676 rtx
11678 {
11682 unsigned HOST_WIDE_INT mask
11685 }
11687 bool
11689 {
11702 }
11704 /* Return a const_int vector of VAL. */
11705 rtx
11707 {
11718 }
11720 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11722 bool
11724 {
11725 machine_mode vmode;
11730 }
11732 /* Construct and return a PARALLEL RTX vector with elements numbering the
11733 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11734 the vector - from the perspective of the architecture. This does not
11735 line up with GCC's perspective on lane numbers, so we end up with
11736 different masks depending on our target endian-ness. The diagram
11737 below may help. We must draw the distinction when building masks
11738 which select one half of the vector. An instruction selecting
11739 architectural low-lanes for a big-endian target, must be described using
11740 a mask selecting GCC high-lanes.
11742 Big-Endian Little-Endian
11744 GCC 0 1 2 3 3 2 1 0
11745 | x | x | x | x | | x | x | x | x |
11746 Architecture 3 2 1 0 3 2 1 0
11748 Low Mask: { 2, 3 } { 0, 1 }
11749 High Mask: { 0, 1 } { 2, 3 }
11750 */
11752 rtx
11754 {
11760 rtx t1;
11765 else
11773 }
11775 /* Check OP for validity as a PARALLEL RTX vector with elements
11776 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11777 from the perspective of the architecture. See the diagram above
11778 aarch64_simd_vect_par_cnst_half for more details. */
11780 bool
11783 {
11796 {
11803 }
11805 }
11807 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11808 HIGH (exclusive). */
11809 void
11811 const_tree exp)
11812 {
11813 HOST_WIDE_INT lane;
11818 {
11821 else
11823 }
11824 }
11826 /* Return TRUE if OP is a valid vector addressing mode. */
11827 bool
11829 {
11832 }
11834 /* Emit a register copy from operand to operand, taking care not to
11835 early-clobber source registers in the process.
11837 COUNT is the number of components into which the copy needs to be
11838 decomposed. */
11839 void
11842 {
11852 else
11856 }
11858 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11859 one of VSTRUCT modes: OI, CI, or XI. */
11860 int
11862 {
11864 }
11866 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11867 alignment of a vector to 128 bits. */
11868 static HOST_WIDE_INT
11870 {
11873 }
11875 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11876 static bool
11878 {
11882 /* We guarantee alignment for vectors up to 128-bits. */
11887 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11889 }
11891 /* Return true if the vector misalignment factor is supported by the
11892 target. */
11893 static bool
11897 {
11899 {
11900 /* Return if movmisalign pattern is not supported for this mode. */
11905 {
11906 /* Misalignment factor is unknown at compile time but we know
11907 it's word aligned. */
11909 {
11914 }
11916 }
11917 }
11919 is_packed);
11920 }
11922 /* If VALS is a vector constant that can be loaded into a register
11923 using DUP, generate instructions to do so and return an RTX to
11924 assign to the register. Otherwise return NULL_RTX. */
11925 static rtx
11927 {
11930 rtx x;
11935 /* We can load this constant by using DUP and a constant in a
11936 single ARM register. This will be cheaper than a vector
11937 load. */
11940 }
11943 /* Generate code to load VALS, which is a PARALLEL containing only
11944 constants (for vec_init) or CONST_VECTOR, efficiently into a
11945 register. Returns an RTX to copy into the register, or NULL_RTX
11946 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11947 static rtx
11949 {
11951 rtx const_dup;
11960 {
11961 /* A CONST_VECTOR must contain only CONST_INTs and
11962 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11963 Only store valid constants in a CONST_VECTOR. */
11965 {
11968 n_const++;
11969 }
11972 }
11973 else
11978 /* Load using MOVI/MVNI. */
11981 /* Loaded using DUP. */
11984 /* Load from constant pool. We can not take advantage of single-cycle
11985 LD1 because we need a PC-relative addressing mode. */
11987 else
11988 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11989 We can not construct an initializer. */
11991 }
11993 /* Expand a vector initialisation sequence, such that TARGET is
11994 initialised to contain VALS. */
11996 void
11998 {
12001 /* The number of vector elements. */
12003 /* The number of vector elements which are not constant. */
12006 /* The first element of vals. */
12010 /* Count the number of variable elements to initialise. */
12012 {
12016 else
12020 }
12022 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12023 how best to handle this. */
12025 {
12028 {
12031 }
12032 }
12034 /* Splat a single non-constant element if we can. */
12036 {
12040 }
12045 /* If there are only variable elements, try to optimize
12046 the insertion using dup for the most common element
12047 followed by insertions. */
12049 /* The algorithm will fill matches[*][0] with the earliest matching element,
12050 and matches[X][1] with the count of duplicate elements (if X is the
12051 earliest element which has duplicates). */
12054 {
12057 {
12059 {
12061 {
12065 }
12066 }
12067 }
12072 {
12075 }
12077 /* Create a duplicate of the most common element. */
12081 /* Insert the rest. */
12083 {
12089 }
12091 }
12093 /* Initialise a vector which is part-variable. We want to first try
12094 to build those lanes which are constant in the most efficient way we
12095 can. */
12097 {
12100 /* Load constant part of vector. We really don't care what goes into the
12101 parts we will overwrite, but we're more likely to be able to load the
12102 constant efficiently if it has fewer, larger, repeating parts
12103 (see aarch64_simd_valid_immediate). */
12105 {
12111 {
12112 /* Look in the copied vector, as more elements are const. */
12115 {
12118 }
12119 }
12121 }
12123 }
12125 /* Insert the variable lanes directly. */
12127 {
12133 }
12134 }
12136 static unsigned HOST_WIDE_INT
12138 {
12139 return
12140 (!SHIFT_COUNT_TRUNCATED
12143 }
12145 /* Select a format to encode pointers in exception handling data. */
12146 int
12148 {
12151 {
12157 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12158 for everything. */
12162 /* No assumptions here. 8-byte relocs required. */
12165 }
12167 }
12169 /* The last .arch and .tune assembly strings that we printed. */
12173 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12174 by the function fndecl. */
12176 void
12178 tree fndecl)
12179 {
12185 else
12196 /* Only update the assembler .arch string if it is distinct from the last
12197 such string we printed. */
12200 {
12203 }
12205 /* Print the cpu name we're tuning for in the comments, might be
12206 useful to readers of the generated asm. Do it only when it changes
12207 from function to function and verbose assembly is requested. */
12212 {
12216 }
12218 /* Don't forget the type directive for ELF. */
12221 }
12223 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12225 static void
12227 {
12244 }
12246 /* Emit load exclusive. */
12248 static void
12251 {
12255 {
12262 }
12265 }
12267 /* Emit store exclusive. */
12269 static void
12272 {
12276 {
12283 }
12286 }
12288 /* Mark the previous jump instruction as unlikely. */
12290 static void
12292 {
12295 }
12297 /* Expand a compare and swap pattern. */
12299 void
12301 {
12306 gen_cas_fn gen;
12308 {
12309 gen_aarch64_compare_and_swapqi,
12310 gen_aarch64_compare_and_swaphi,
12311 gen_aarch64_compare_and_swapsi,
12312 gen_aarch64_compare_and_swapdi
12313 };
12315 {
12316 gen_aarch64_compare_and_swapqi_lse,
12317 gen_aarch64_compare_and_swaphi_lse,
12318 gen_aarch64_compare_and_swapsi_lse,
12319 gen_aarch64_compare_and_swapdi_lse
12320 };
12333 /* Normally the succ memory model must be stronger than fail, but in the
12334 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12335 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12342 {
12345 /* For short modes, we're going to perform the comparison in SImode,
12346 so do the zero-extension now. */
12350 /* Fall through. */
12354 /* Force the value into a register if needed. */
12361 }
12364 {
12371 }
12374 else
12385 }
12387 /* Test whether the target supports using a atomic load-operate instruction.
12388 CODE is the operation and AFTER is TRUE if the data in memory after the
12389 operation should be returned and FALSE if the data before the operation
12390 should be returned. Returns FALSE if the operation isn't supported by the
12391 architecture. */
12393 bool
12395 {
12400 {
12410 }
12411 }
12413 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12414 sequence implementing an atomic operation. */
12416 static void
12418 {
12425 {
12427 }
12428 }
12430 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12431 for the data in memory. EXPECTED is the value expected to be in memory.
12432 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12433 is the memory ordering to use. */
12435 void
12438 rtx model)
12439 {
12441 machine_mode mode;
12446 {
12453 }
12455 /* Move the expected value into the CAS destination register. */
12458 /* Emit the CAS. */
12461 /* Compare the expected value with the value loaded by the CAS, to establish
12462 whether the swap was made. */
12464 }
12466 /* Split a compare and swap pattern. */
12468 void
12470 {
12472 machine_mode mode;
12477 rtx model_rtx;
12489 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12490 loop:
12491 .label1:
12492 LD[A]XR rval, [mem]
12493 CBNZ rval, .label2
12494 ST[L]XR scratch, newval, [mem]
12495 CBNZ scratch, .label1
12496 .label2:
12497 CMP rval, 0. */
12502 {
12505 }
12508 /* The initial load can be relaxed for a __sync operation since a final
12509 barrier will be emitted to stop code hoisting. */
12513 else
12517 {
12522 }
12523 else
12524 {
12530 }
12535 {
12540 }
12541 else
12542 {
12546 }
12549 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12550 to set the condition flags. If this is not used it will be removed by
12551 later passes. */
12553 {
12557 }
12558 /* Emit any final barrier needed for a __sync operation. */
12561 }
12563 /* Emit a BIC instruction. */
12565 static void
12567 {
12572 {
12577 }
12580 }
12582 /* Emit an atomic swap. */
12584 static void
12587 {
12591 {
12598 }
12601 }
12603 /* Operations supported by aarch64_emit_atomic_load_op. */
12605 enum aarch64_atomic_load_op_code
12606 {
12610 AARCH64_LDOP_BIC /* A & ~B */
12611 };
12613 /* Emit an atomic load-operate. */
12615 static void
12619 {
12622 {
12623 gen_aarch64_atomic_loadaddqi,
12624 gen_aarch64_atomic_loadaddhi,
12625 gen_aarch64_atomic_loadaddsi,
12626 gen_aarch64_atomic_loadadddi
12627 };
12629 {
12630 gen_aarch64_atomic_loadeorqi,
12631 gen_aarch64_atomic_loadeorhi,
12632 gen_aarch64_atomic_loadeorsi,
12633 gen_aarch64_atomic_loadeordi
12634 };
12636 {
12637 gen_aarch64_atomic_loadsetqi,
12638 gen_aarch64_atomic_loadsethi,
12639 gen_aarch64_atomic_loadsetsi,
12640 gen_aarch64_atomic_loadsetdi
12641 };
12643 {
12644 gen_aarch64_atomic_loadclrqi,
12645 gen_aarch64_atomic_loadclrhi,
12646 gen_aarch64_atomic_loadclrsi,
12647 gen_aarch64_atomic_loadclrdi
12648 };
12649 aarch64_atomic_load_op_fn gen;
12653 {
12660 }
12663 {
12670 }
12673 }
12675 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12676 location to store the data read from memory. OUT_RESULT is the location to
12677 store the result of the operation. MEM is the memory location to read and
12678 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12679 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12680 be NULL. */
12682 void
12685 {
12689 aarch64_atomic_load_op_code ldop_code;
12690 rtx src;
12691 rtx x;
12699 /* Make sure the value is in a register, putting it into a destination
12700 register if it needs to be manipulated. */
12703 {
12706 }
12707 else
12711 /* Preprocess the data for the operation as necessary. If the operation is
12712 a SET then emit a swap instruction and finish. */
12714 {
12720 /* Negate the value and treat it as a PLUS. */
12721 {
12722 rtx neg_src;
12724 /* Resize the value if necessary. */
12733 }
12734 /* Fall-through. */
12748 {
12749 rtx not_src;
12751 /* Resize the value if necessary. */
12760 }
12765 /* The operation can't be done with atomic instructions. */
12767 }
12771 /* If necessary, calculate the data in memory after the update by redoing the
12772 operation from values in registers. */
12777 {
12781 }
12786 {
12802 }
12807 }
12809 /* Split an atomic operation. */
12811 void
12814 {
12820 rtx x;
12822 /* Split the atomic operation into a sequence. */
12830 else
12834 /* The initial load can be relaxed for a __sync operation since a final
12835 barrier will be emitted to stop code hoisting. */
12839 else
12843 {
12857 {
12860 }
12861 /* Fall through. */
12867 }
12877 /* Emit any final barrier needed for a __sync operation. */
12880 }
12882 static void
12884 {
12885 /* Half-precision float operations. The compiler handles all operations
12886 with NULL libfuncs by converting to SFmode. */
12888 /* Conversions. */
12892 /* Arithmetic. */
12899 /* Comparisons. */
12907 }
12909 /* Target hook for c_mode_for_suffix. */
12910 static machine_mode
12912 {
12917 }
12919 /* We can only represent floating point constants which will fit in
12920 "quarter-precision" values. These values are characterised by
12921 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12922 by:
12924 (-1)^s * (n/16) * 2^r
12926 Where:
12927 's' is the sign bit.
12928 'n' is an integer in the range 16 <= n <= 31.
12929 'r' is an integer in the range -3 <= r <= 4. */
12931 /* Return true iff X can be represented by a quarter-precision
12932 floating point immediate operand X. Note, we cannot represent 0.0. */
12933 bool
12935 {
12936 /* This represents our current view of how many bits
12937 make up the mantissa. */
12947 /* We don't support HFmode constants yet. */
12953 /* We cannot represent infinities, NaNs or +/-zero. We won't
12954 know if we have +zero until we analyse the mantissa, but we
12955 can reject the other invalid values. */
12960 /* Extract exponent. */
12964 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12965 highest (sign) bit, with a fixed binary point at bit point_pos.
12966 m1 holds the low part of the mantissa, m2 the high part.
12967 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12968 bits for the mantissa, this can fail (low bits will be lost). */
12972 /* If the low part of the mantissa has bits set we cannot represent
12973 the value. */
12976 /* We have rejected the lower HOST_WIDE_INT, so update our
12977 understanding of how many bits lie in the mantissa and
12978 look only at the high HOST_WIDE_INT. */
12982 /* We can only represent values with a mantissa of the form 1.xxxx. */
12987 /* Having filtered unrepresentable values, we may now remove all
12988 but the highest 5 bits. */
12991 /* We cannot represent the value 0.0, so reject it. This is handled
12992 elsewhere. */
12996 /* Then, as bit 4 is always set, we can mask it off, leaving
12997 the mantissa in the range [0, 15]. */
13001 /* GCC internally does not use IEEE754-like encoding (where normalized
13002 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
13003 Our mantissa values are shifted 4 places to the left relative to
13004 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
13005 by 5 places to correct for GCC's representation. */
13009 }
13013 machine_mode mode,
13015 {
13025 /* This will return true to show const_vector is legal for use as either
13026 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
13027 also update INFO to show how the immediate should be generated. */
13036 {
13038 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13039 move immediate path. */
13042 else
13043 {
13052 else
13056 }
13057 }
13070 else
13074 }
13078 {
13080 /* If a floating point number was passed and we desire to use it in an
13081 integer mode do the conversion to integer. */
13083 {
13088 }
13090 machine_mode vmode;
13091 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13092 a 128 bit vector mode. */
13098 }
13100 /* Split operands into moves from op[1] + op[2] into op[0]. */
13102 void
13104 {
13115 {
13116 /* No-op move. Can't split to nothing; emit something. */
13119 }
13121 /* Preserve register attributes for variable tracking. */
13126 /* Special case of reversed high/low parts. */
13129 {
13133 }
13135 {
13136 /* Try to avoid unnecessary moves if part of the result
13137 is in the right place already. */
13142 }
13143 else
13144 {
13149 }
13150 }
13152 /* vec_perm support. */
13154 #define MAX_VECT_LEN 16
13156 struct expand_vec_perm_d
13157 {
13160 machine_mode vmode;
13164 };
13166 /* Generate a variable permutation. */
13168 static void
13170 {
13181 {
13183 {
13184 /* Expand the argument to a V16QI mode by duplicating it. */
13188 }
13189 else
13190 {
13192 }
13193 }
13194 else
13195 {
13196 rtx pair;
13199 {
13203 }
13204 else
13205 {
13209 }
13210 }
13211 }
13213 void
13215 {
13219 rtx mask;
13221 /* The TBL instruction does not use a modulo index, so we must take care
13222 of that ourselves. */
13227 /* For big-endian, we also need to reverse the index within the vector
13228 (but not which vector). */
13230 {
13231 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13236 }
13238 }
13240 /* Recognize patterns suitable for the TRN instructions. */
13241 static bool
13243 {
13252 /* Note that these are little-endian tests.
13253 We correct for big-endian later. */
13258 else
13263 {
13268 }
13270 /* Success! */
13277 {
13280 }
13284 {
13286 {
13301 }
13302 }
13303 else
13304 {
13306 {
13321 }
13322 }
13326 }
13328 /* Recognize patterns suitable for the UZP instructions. */
13329 static bool
13331 {
13340 /* Note that these are little-endian tests.
13341 We correct for big-endian later. */
13346 else
13351 {
13355 }
13357 /* Success! */
13364 {
13367 }
13371 {
13373 {
13388 }
13389 }
13390 else
13391 {
13393 {
13408 }
13409 }
13413 }
13415 /* Recognize patterns suitable for the ZIP instructions. */
13416 static bool
13418 {
13427 /* Note that these are little-endian tests.
13428 We correct for big-endian later. */
13431 /* Do Nothing. */
13432 ;
13435 else
13440 {
13447 }
13449 /* Success! */
13456 {
13459 }
13463 {
13465 {
13480 }
13481 }
13482 else
13483 {
13485 {
13500 }
13501 }
13505 }
13507 /* Recognize patterns for the EXT insn. */
13509 static bool
13511 {
13514 rtx offset;
13518 /* Check if the extracted indices are increasing by one. */
13520 {
13523 {
13524 /* We'll pass the same vector in twice, so allow indices to wrap. */
13526 }
13529 }
13532 {
13547 }
13549 /* Success! */
13553 /* The case where (location == 0) is a no-op for both big- and little-endian,
13554 and is removed by the mid-end at optimization levels -O1 and higher. */
13557 {
13558 /* After setup, we want the high elements of the first vector (stored
13559 at the LSB end of the register), and the low elements of the second
13560 vector (stored at the MSB end of the register). So swap. */
13562 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13564 }
13569 }
13571 /* Recognize patterns for the REV insns. */
13573 static bool
13575 {
13584 {
13587 {
13592 }
13596 {
13603 }
13607 {
13620 }
13624 }
13628 {
13629 /* This is guaranteed to be true as the value of diff
13630 is 7, 3, 1 and we should have enough elements in the
13631 queue to generate this. Getting a vector mask with a
13632 value of diff other than these values implies that
13633 something is wrong by the time we get here. */
13637 }
13639 /* Success! */
13645 }
13647 static bool
13649 {
13652 rtx in0;
13655 rtx lane;
13659 {
13662 }
13664 /* The generic preparation in aarch64_expand_vec_perm_const_1
13665 swaps the operand order and the permute indices if it finds
13666 d->perm[0] to be in the second operand. Thus, we can always
13667 use d->op0 and need not do any extra arithmetic to get the
13668 correct lane number. */
13673 {
13688 }
13692 }
13694 static bool
13696 {
13704 /* Generic code will try constant permutation twice. Once with the
13705 original mode and again with the elements lowered to QImode.
13706 So wait and don't do the selector expansion ourselves. */
13711 {
13714 /* If big-endian and two vectors we end up with a weird mixed-endian
13715 mode on NEON. Reverse the index within each word but not the word
13716 itself. */
13719 }
13725 }
13727 static bool
13729 {
13730 /* The pattern matching functions above are written to look for a small
13731 number to begin the sequence (0, 1, N/2). If we begin with an index
13732 from the second operand, we can swap the operands. */
13734 {
13742 }
13745 {
13759 }
13761 }
13763 /* Expand a vec_perm_const pattern. */
13765 bool
13767 {
13781 {
13786 }
13789 {
13798 /* The elements of PERM do not suggest that only the first operand
13799 is used, but both operands are identical. Allow easier matching
13800 of the permutation by folding the permutation into the single
13801 input vector. */
13802 /* Fall Through. */
13814 }
13817 }
13819 static bool
13822 {
13832 /* Calculate whether all elements are in one vector. */
13834 {
13838 }
13840 /* If all elements are from the second vector, reindex as if from the
13841 first vector. */
13846 /* Check whether the mask can be applied to a single vector. */
13859 }
13861 rtx
13863 {
13864 /* We have to reverse each vector because we dont have
13865 a permuted load that can reverse-load according to ABI rules. */
13866 rtx mask;
13880 }
13882 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13883 true. However due to issues with register allocation it is preferable
13884 to avoid tieing integer scalar and FP scalar modes. Executing integer
13885 operations in general registers is better than treating them as scalar
13886 vector operations. This reduces latency and avoids redundant int<->FP
13887 moves. So tie modes if they are either the same class, or vector modes
13888 with other vector modes, vector structs or any scalar mode. */
13890 static bool
13892 {
13896 /* We specifically want to allow elements of "structure" modes to
13897 be tieable to the structure. This more general condition allows
13898 other rarer situations too. */
13902 /* Also allow any scalar modes with vectors. */
13908 }
13910 /* Return a new RTX holding the result of moving POINTER forward by
13911 AMOUNT bytes. */
13913 static rtx
13915 {
13920 }
13922 /* Return a new RTX holding the result of moving POINTER forward by the
13923 size of the mode it points to. */
13925 static rtx
13927 {
13931 }
13933 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13934 MODE bytes. */
13936 static void
13938 machine_mode mode)
13939 {
13942 /* "Cast" the pointers to the correct mode. */
13945 /* Emit the memcpy. */
13948 /* Move the pointers forward. */
13951 }
13953 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13954 we succeed, otherwise return false. */
13956 bool
13958 {
13962 rtx base;
13965 /* When optimizing for size, give a better estimate of the length of a
13966 memcpy call, but use the default otherwise. */
13969 /* We can't do anything smart if the amount to copy is not constant. */
13975 /* Try to keep the number of instructions low. For cases below 16 bytes we
13976 need to make at most two moves. For cases above 16 bytes it will be one
13977 move for each 16 byte chunk, then at most two additional moves. */
13987 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13988 1-byte chunk. */
13990 {
13992 {
13995 }
14001 }
14003 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
14004 4-byte chunk, partially overlapping with the previously copied chunk. */
14006 {
14010 {
14016 }
14018 }
14020 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14021 them, then (if applicable) an 8-byte chunk. */
14023 {
14025 {
14028 }
14029 else
14030 {
14033 }
14034 }
14036 /* Finish the final bytes of the copy. We can always do this in one
14037 instruction. We either copy the exact amount we need, or partially
14038 overlap with the previous chunk we copied and copy 8-bytes. */
14047 else
14048 {
14050 {
14054 }
14055 else
14056 {
14062 }
14063 }
14066 }
14068 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14069 SImode stores. Handle the case when the constant has identical
14070 bottom and top halves. This is beneficial when the two stores can be
14071 merged into an STP and we avoid synthesising potentially expensive
14072 immediates twice. Return true if such a split is possible. */
14074 bool
14076 {
14085 unsigned int orig_cost
14087 unsigned int lo_cost
14090 /* We want to transform:
14091 MOV x1, 49370
14092 MOVK x1, 0x140, lsl 16
14093 MOVK x1, 0xc0da, lsl 32
14094 MOVK x1, 0x140, lsl 48
14095 STR x1, [x0]
14096 into:
14097 MOV w1, 49370
14098 MOVK w1, 0x140, lsl 16
14099 STP w1, w1, [x0]
14100 So we want to perform this only when we save two instructions
14101 or more. When optimizing for size, however, accept any code size
14102 savings we can. */
14117 /* Don't emit an explicit store pair as this may not be always profitable.
14118 Let the sched-fusion logic decide whether to merge them. */
14123 }
14125 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14127 static unsigned HOST_WIDE_INT
14129 {
14131 }
14133 static bool
14138 {
14139 /* STORE_BY_PIECES can be used when copying a constant string, but
14140 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14141 For now we always fail this and let the move_by_pieces code copy
14142 the string from read-only memory. */
14147 }
14149 static rtx
14152 {
14156 insn_code icode;
14167 {
14195 }
14200 {
14203 }
14212 {
14215 }
14221 }
14223 static rtx
14226 {
14230 insn_code icode;
14242 {
14270 }
14275 {
14278 }
14286 {
14291 }
14302 {
14305 }
14311 }
14313 #undef TARGET_GEN_CCMP_FIRST
14314 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14316 #undef TARGET_GEN_CCMP_NEXT
14317 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14319 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14320 instruction fusion of some sort. */
14322 static bool
14324 {
14326 }
14329 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14330 should be kept together during scheduling. */
14332 static bool
14334 {
14335 rtx set_dest;
14338 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14345 {
14346 /* We are trying to match:
14347 prev (mov) == (set (reg r0) (const_int imm16))
14348 curr (movk) == (set (zero_extract (reg r0)
14349 (const_int 16)
14350 (const_int 16))
14351 (const_int imm16_1)) */
14363 {
14365 }
14366 }
14369 {
14371 /* We're trying to match:
14372 prev (adrp) == (set (reg r1)
14373 (high (symbol_ref ("SYM"))))
14374 curr (add) == (set (reg r0)
14375 (lo_sum (reg r1)
14376 (symbol_ref ("SYM"))))
14377 Note that r0 need not necessarily be the same as r1, especially
14378 during pre-regalloc scheduling. */
14382 {
14390 }
14391 }
14394 {
14396 /* We're trying to match:
14397 prev (movk) == (set (zero_extract (reg r0)
14398 (const_int 16)
14399 (const_int 32))
14400 (const_int imm16_1))
14401 curr (movk) == (set (zero_extract (reg r0)
14402 (const_int 16)
14403 (const_int 48))
14404 (const_int imm16_2)) */
14420 }
14422 {
14423 /* We're trying to match:
14424 prev (adrp) == (set (reg r0)
14425 (high (symbol_ref ("SYM"))))
14426 curr (ldr) == (set (reg r1)
14427 (mem (lo_sum (reg r0)
14428 (symbol_ref ("SYM")))))
14429 or
14430 curr (ldr) == (set (reg r1)
14431 (zero_extend (mem
14432 (lo_sum (reg r0)
14433 (symbol_ref ("SYM")))))) */
14436 {
14449 }
14450 }
14458 {
14462 rtx cc_reg_1;
14467 && prev
14469 {
14470 /* FIXME: this misses some which is considered simple arthematic
14471 instructions for ThunderX. Simple shifts are missed here. */
14477 }
14478 }
14481 && curr_set
14484 {
14485 /* We're trying to match:
14486 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14487 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14488 (const_int 0))
14489 (label_ref ("SYM"))
14490 (pc)) */
14497 {
14498 /* Fuse ALU operations followed by conditional branch instruction. */
14500 {
14521 }
14522 }
14523 }
14526 }
14528 /* Return true iff the instruction fusion described by OP is enabled. */
14530 bool
14532 {
14534 }
14536 /* If MEM is in the form of [base+offset], extract the two parts
14537 of address and set to BASE and OFFSET, otherwise return false
14538 after clearing BASE and OFFSET. */
14540 bool
14542 {
14543 rtx addr;
14550 {
14554 }
14558 {
14562 }
14568 }
14570 /* Types for scheduling fusion. */
14571 enum sched_fusion_type
14572 {
14574 SCHED_FUSION_LD_SIGN_EXTEND,
14575 SCHED_FUSION_LD_ZERO_EXTEND,
14576 SCHED_FUSION_LD,
14577 SCHED_FUSION_ST,
14578 SCHED_FUSION_NUM
14579 };
14581 /* If INSN is a load or store of address in the form of [base+offset],
14582 extract the two parts and set to BASE and OFFSET. Return scheduling
14583 fusion type this INSN is. */
14585 static enum sched_fusion_type
14587 {
14605 {
14610 }
14612 {
14617 }
14622 {
14625 }
14626 else
14633 }
14635 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14637 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14638 and PRI are only calculated for these instructions. For other instruction,
14639 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14640 type instruction fusion can be added by returning different priorities.
14642 It's important that irrelevant instructions get the largest FUSION_PRI. */
14644 static void
14647 {
14657 {
14661 }
14663 /* Set FUSION_PRI according to fusion type and base register. */
14666 /* Calculate PRI. */
14669 /* INSN with smaller offset goes first. */
14673 else
14678 }
14680 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14681 Adjust priority of sha1h instructions so they are scheduled before
14682 other SHA1 instructions. */
14684 static int
14686 {
14690 {
14695 }
14698 }
14700 /* Given OPERANDS of consecutive load/store, check if we can merge
14701 them into ldp/stp. LOAD is true if they are load instructions.
14702 MODE is the mode of memory operands. */
14704 bool
14706 machine_mode mode)
14707 {
14713 {
14721 }
14722 else
14723 {
14728 }
14730 /* The mems cannot be volatile. */
14734 /* If we have SImode and slow unaligned ldp,
14735 check the alignment to be at least 8 byte. */
14739 && !optimize_size
14743 /* Check if the addresses are in the form of [base+offset]. */
14751 /* Check if the bases are same. */
14758 /* Check if the offsets are consecutive. */
14762 /* Check if the addresses are clobbered by load. */
14764 {
14768 /* In increasing order, the last load can clobber the address. */
14771 }
14775 else
14780 else
14783 /* Check if the registers are of same class. */
14788 }
14790 /* Given OPERANDS of consecutive load/store, check if we can merge
14791 them into ldp/stp by adjusting the offset. LOAD is true if they
14792 are load instructions. MODE is the mode of memory operands.
14794 Given below consecutive stores:
14796 str w1, [xb, 0x100]
14797 str w1, [xb, 0x104]
14798 str w1, [xb, 0x108]
14799 str w1, [xb, 0x10c]
14801 Though the offsets are out of the range supported by stp, we can
14802 still pair them after adjusting the offset, like:
14804 add scratch, xb, 0x100
14805 stp w1, w1, [scratch]
14806 stp w1, w1, [scratch, 0x8]
14808 The peephole patterns detecting this opportunity should guarantee
14809 the scratch register is avaliable. */
14811 bool
14813 scalar_mode mode)
14814 {
14821 {
14834 }
14835 else
14836 {
14845 }
14846 /* Skip if memory operand is by itslef valid for ldp/stp. */
14850 /* The mems cannot be volatile. */
14855 /* Check if the addresses are in the form of [base+offset]. */
14869 /* Check if the bases are same. */
14880 /* Check if the offsets are consecutive. */
14889 /* Check if the addresses are clobbered by load. */
14891 {
14897 /* In increasing order, the last load can clobber the address. */
14900 }
14902 /* If we have SImode and slow unaligned ldp,
14903 check the alignment to be at least 8 byte. */
14907 && !optimize_size
14913 else
14918 else
14923 else
14928 else
14931 /* Check if the registers are of same class. */
14936 }
14938 /* Given OPERANDS of consecutive load/store, this function pairs them
14939 into ldp/stp after adjusting the offset. It depends on the fact
14940 that addresses of load/store instructions are in increasing order.
14941 MODE is the mode of memory operands. CODE is the rtl operator
14942 which should be applied to all memory operands, it's SIGN_EXTEND,
14943 ZERO_EXTEND or UNKNOWN. */
14945 bool
14948 {
14954 {
14959 }
14960 else
14961 {
14967 }
14972 /* Adjust offset thus it can fit in ldp/stp instruction. */
14980 /* Further adjust to make sure all offsets are OK. */
14982 {
14985 }
14987 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14992 {
14995 }
14997 /* Create new memory references. */
15001 /* Check if the adjusted address is OK for ldp/stp. */
15020 {
15025 }
15027 {
15032 }
15035 {
15040 }
15041 else
15042 {
15047 }
15049 /* Emit adjusting instruction. */
15051 /* Emit ldp/stp instructions. */
15059 }
15061 /* Return 1 if pseudo register should be created and used to hold
15062 GOT address for PIC code. */
15064 bool
15066 {
15068 }
15070 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15072 static int
15074 {
15076 {
15083 }
15086 }
15089 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15090 return the log2 of that value. Otherwise return -1. */
15092 int
15094 {
15109 }
15111 /* If X is a vector of equal CONST_DOUBLE values and that value is
15112 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15114 int
15116 {
15132 }
15134 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15135 to float.
15137 __fp16 always promotes through this hook.
15138 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15139 through the generic excess precision logic rather than here. */
15141 static tree
15143 {
15149 }
15151 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15153 static bool
15155 optimization_type opt_type)
15156 {
15158 {
15164 }
15165 }
15167 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15168 if MODE is HFmode, and punt to the generic implementation otherwise. */
15170 static bool
15172 {
15176 }
15178 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15179 if MODE is HFmode, and punt to the generic implementation otherwise. */
15181 static bool
15183 {
15187 }
15189 /* Set the value of FLT_EVAL_METHOD.
15190 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15192 0: evaluate all operations and constants, whose semantic type has at
15193 most the range and precision of type float, to the range and
15194 precision of float; evaluate all other operations and constants to
15195 the range and precision of the semantic type;
15197 N, where _FloatN is a supported interchange floating type
15198 evaluate all operations and constants, whose semantic type has at
15199 most the range and precision of _FloatN type, to the range and
15200 precision of the _FloatN type; evaluate all other operations and
15201 constants to the range and precision of the semantic type;
15203 If we have the ARMv8.2-A extensions then we support _Float16 in native
15204 precision, so we should set this to 16. Otherwise, we support the type,
15205 but want to evaluate expressions in float precision, so set this to
15206 0. */
15208 static enum flt_eval_method
15210 {
15212 {
15215 /* We can calculate either in 16-bit range and precision or
15216 32-bit range and precision. Make that decision based on whether
15217 we have native support for the ARMv8.2-A 16-bit floating-point
15218 instructions or not. */
15220 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15226 }
15228 }
15230 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15231 scheduled for speculative execution. Reject the long-running division
15232 and square-root instructions. */
15234 static bool
15236 {
15238 {
15256 }
15257 }
15259 /* Target-specific selftests. */
15261 #if CHECKING_P
15265 /* Selftest for the RTL loader.
15266 Verify that the RTL loader copes with a dump from
15267 print_rtx_function. This is essentially just a test that class
15268 function_reader can handle a real dump, but it also verifies
15269 that lookup_reg_by_dump_name correctly handles hard regs.
15270 The presence of hard reg names in the dump means that the test is
15271 target-specific, hence it is in this file. */
15273 static void
15275 {
15287 /* Verify crtl->return_rtx. */
15291 }
15293 /* Run all target-specific selftests. */
15295 static void
15297 {
15299 }
15305 #undef TARGET_ADDRESS_COST
15306 #define TARGET_ADDRESS_COST aarch64_address_cost
15308 /* This hook will determines whether unnamed bitfields affect the alignment
15309 of the containing structure. The hook returns true if the structure
15310 should inherit the alignment requirements of an unnamed bitfield's
15311 type. */
15312 #undef TARGET_ALIGN_ANON_BITFIELD
15313 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15315 #undef TARGET_ASM_ALIGNED_DI_OP
15318 #undef TARGET_ASM_ALIGNED_HI_OP
15321 #undef TARGET_ASM_ALIGNED_SI_OP
15324 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15325 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15326 hook_bool_const_tree_hwi_hwi_const_tree_true
15328 #undef TARGET_ASM_FILE_START
15329 #define TARGET_ASM_FILE_START aarch64_start_file
15331 #undef TARGET_ASM_OUTPUT_MI_THUNK
15332 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15334 #undef TARGET_ASM_SELECT_RTX_SECTION
15335 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15337 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15338 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15340 #undef TARGET_BUILD_BUILTIN_VA_LIST
15341 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15343 #undef TARGET_CALLEE_COPIES
15344 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15346 #undef TARGET_CAN_ELIMINATE
15347 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15349 #undef TARGET_CAN_INLINE_P
15350 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15352 #undef TARGET_CANNOT_FORCE_CONST_MEM
15353 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15355 #undef TARGET_CASE_VALUES_THRESHOLD
15356 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15358 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15359 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15361 /* Only the least significant bit is used for initialization guard
15362 variables. */
15363 #undef TARGET_CXX_GUARD_MASK_BIT
15364 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15366 #undef TARGET_C_MODE_FOR_SUFFIX
15367 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15369 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15370 #undef TARGET_DEFAULT_TARGET_FLAGS
15371 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15372 #endif
15374 #undef TARGET_CLASS_MAX_NREGS
15375 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15377 #undef TARGET_BUILTIN_DECL
15378 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15380 #undef TARGET_BUILTIN_RECIPROCAL
15381 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15383 #undef TARGET_C_EXCESS_PRECISION
15384 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15386 #undef TARGET_EXPAND_BUILTIN
15387 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15389 #undef TARGET_EXPAND_BUILTIN_VA_START
15390 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15392 #undef TARGET_FOLD_BUILTIN
15393 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15395 #undef TARGET_FUNCTION_ARG
15396 #define TARGET_FUNCTION_ARG aarch64_function_arg
15398 #undef TARGET_FUNCTION_ARG_ADVANCE
15399 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15401 #undef TARGET_FUNCTION_ARG_BOUNDARY
15402 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15404 #undef TARGET_FUNCTION_ARG_PADDING
15405 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15407 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15408 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15410 #undef TARGET_FUNCTION_VALUE
15411 #define TARGET_FUNCTION_VALUE aarch64_function_value
15413 #undef TARGET_FUNCTION_VALUE_REGNO_P
15414 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15416 #undef TARGET_FRAME_POINTER_REQUIRED
15417 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15419 #undef TARGET_GIMPLE_FOLD_BUILTIN
15420 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15422 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15423 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15425 #undef TARGET_INIT_BUILTINS
15426 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15428 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15429 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15430 aarch64_ira_change_pseudo_allocno_class
15432 #undef TARGET_LEGITIMATE_ADDRESS_P
15433 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15435 #undef TARGET_LEGITIMATE_CONSTANT_P
15436 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15438 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15439 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15440 aarch64_legitimize_address_displacement
15442 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15443 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15445 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15446 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15447 aarch64_libgcc_floating_mode_supported_p
15449 #undef TARGET_MANGLE_TYPE
15450 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15452 #undef TARGET_MEMORY_MOVE_COST
15453 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15455 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15456 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15458 #undef TARGET_MUST_PASS_IN_STACK
15459 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15461 /* This target hook should return true if accesses to volatile bitfields
15462 should use the narrowest mode possible. It should return false if these
15463 accesses should use the bitfield container type. */
15464 #undef TARGET_NARROW_VOLATILE_BITFIELD
15465 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15467 #undef TARGET_OPTION_OVERRIDE
15468 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15470 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15471 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15472 aarch64_override_options_after_change
15474 #undef TARGET_OPTION_SAVE
15475 #define TARGET_OPTION_SAVE aarch64_option_save
15477 #undef TARGET_OPTION_RESTORE
15478 #define TARGET_OPTION_RESTORE aarch64_option_restore
15480 #undef TARGET_OPTION_PRINT
15481 #define TARGET_OPTION_PRINT aarch64_option_print
15483 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15484 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15486 #undef TARGET_SET_CURRENT_FUNCTION
15487 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15489 #undef TARGET_PASS_BY_REFERENCE
15490 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15492 #undef TARGET_PREFERRED_RELOAD_CLASS
15493 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15495 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15496 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15498 #undef TARGET_PROMOTED_TYPE
15499 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15501 #undef TARGET_SECONDARY_RELOAD
15502 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15504 #undef TARGET_SHIFT_TRUNCATION_MASK
15505 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15507 #undef TARGET_SETUP_INCOMING_VARARGS
15508 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15510 #undef TARGET_STRUCT_VALUE_RTX
15511 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15513 #undef TARGET_REGISTER_MOVE_COST
15514 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15516 #undef TARGET_RETURN_IN_MEMORY
15517 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15519 #undef TARGET_RETURN_IN_MSB
15520 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15522 #undef TARGET_RTX_COSTS
15523 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15525 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15526 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15528 #undef TARGET_SCHED_ISSUE_RATE
15529 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15531 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15532 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15533 aarch64_sched_first_cycle_multipass_dfa_lookahead
15535 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15536 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15537 aarch64_first_cycle_multipass_dfa_lookahead_guard
15539 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15540 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15541 aarch64_get_separate_components
15543 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15544 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15545 aarch64_components_for_bb
15547 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15548 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15549 aarch64_disqualify_components
15551 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15552 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15553 aarch64_emit_prologue_components
15555 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15556 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15557 aarch64_emit_epilogue_components
15559 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15560 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15561 aarch64_set_handled_components
15563 #undef TARGET_TRAMPOLINE_INIT
15564 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15566 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15567 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15569 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15570 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15572 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15573 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15574 aarch64_builtin_support_vector_misalignment
15576 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15577 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15579 #undef TARGET_VECTORIZE_ADD_STMT_COST
15580 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15582 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15583 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15584 aarch64_builtin_vectorization_cost
15586 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15587 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15589 #undef TARGET_VECTORIZE_BUILTINS
15590 #define TARGET_VECTORIZE_BUILTINS
15592 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15593 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15594 aarch64_builtin_vectorized_function
15596 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15597 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15598 aarch64_autovectorize_vector_sizes
15600 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15601 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15602 aarch64_atomic_assign_expand_fenv
15604 /* Section anchor support. */
15606 #undef TARGET_MIN_ANCHOR_OFFSET
15607 #define TARGET_MIN_ANCHOR_OFFSET -256
15609 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15610 byte offset; we can do much more for larger data types, but have no way
15611 to determine the size of the access. We assume accesses are aligned. */
15612 #undef TARGET_MAX_ANCHOR_OFFSET
15613 #define TARGET_MAX_ANCHOR_OFFSET 4095
15615 #undef TARGET_VECTOR_ALIGNMENT
15616 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15618 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15619 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15620 aarch64_simd_vector_alignment_reachable
15622 /* vec_perm support. */
15624 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15625 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15626 aarch64_vectorize_vec_perm_const_ok
15628 #undef TARGET_INIT_LIBFUNCS
15629 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15631 #undef TARGET_FIXED_CONDITION_CODE_REGS
15632 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15634 #undef TARGET_FLAGS_REGNUM
15635 #define TARGET_FLAGS_REGNUM CC_REGNUM
15637 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15638 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15640 #undef TARGET_ASAN_SHADOW_OFFSET
15641 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15643 #undef TARGET_LEGITIMIZE_ADDRESS
15644 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15646 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15647 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15648 aarch64_use_by_pieces_infrastructure_p
15650 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15651 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15653 #undef TARGET_CAN_USE_DOLOOP_P
15654 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15656 #undef TARGET_SCHED_ADJUST_PRIORITY
15657 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15659 #undef TARGET_SCHED_MACRO_FUSION_P
15660 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15662 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15663 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15665 #undef TARGET_SCHED_FUSION_PRIORITY
15666 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15668 #undef TARGET_UNSPEC_MAY_TRAP_P
15669 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15671 #undef TARGET_USE_PSEUDO_PIC_REG
15672 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15674 #undef TARGET_PRINT_OPERAND
15675 #define TARGET_PRINT_OPERAND aarch64_print_operand
15677 #undef TARGET_PRINT_OPERAND_ADDRESS
15678 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15680 #undef TARGET_OPTAB_SUPPORTED_P
15681 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15683 #undef TARGET_OMIT_STRUCT_RETURN_REG
15684 #define TARGET_OMIT_STRUCT_RETURN_REG true
15686 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15687 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15688 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15690 #undef TARGET_HARD_REGNO_MODE_OK
15691 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15693 #undef TARGET_MODES_TIEABLE_P
15694 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15696 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15697 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15698 aarch64_hard_regno_call_part_clobbered
15700 #if CHECKING_P
15701 #undef TARGET_RUN_TARGET_SELFTESTS
15702 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests