1 /* Definitions of target machine for GNU compiler
, for IBM S
/390
2 Copyright (C
) 2002-2015 Free Software Foundation
, Inc.
3 Contributed by Hartmut
Penner (hpenner@de.ibm.com
) and
4 Ulrich
Weigand (uweigand@de.ibm.com
).
6 This file is part of GCC.
8 GCC is free software
; you can redistribute it and
/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation
; either version
3, or (at your option
) any later
13 GCC is distributed in the hope that it will be useful
, but WITHOUT ANY
14 WARRANTY
; without even the implied warranty of MERCHANTABILITY or
15 FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC
; see the file COPYING3. If not see
20 <http
://www.gnu.org
/licenses
/>.
*/
22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.
*/
25 /* Define TFmode to work around reload problem PR
20927.
*/
26 FLOAT_MODE (TF
, 16, ieee_quad_format
);
28 /* Add any extra modes needed to represent the condition code.
*/
41 CCU
: EQ LTU GTU
NE (CLG
/R
, CL
/R
/Y
, CLM
/Y
, CLI
/Y
)
42 CCUR
: EQ GTU LTU
NE (CLGF
/R
)
46 CCS
: EQ LT GT
UNORDERED (LTGFR
, LTGR
, LTR
, ICM
/Y
,
47 LTDBR
, LTDR
, LTEBR
, LTER
,
48 CG
/R
, C
/R
/Y
, CGHI
, CHI
,
49 CDB
/R
, CD
/R
, CEB
/R
, CE
/R
,
50 ADB
/R
, AEB
/R
, SDB
/R
, SEB
/R
,
52 CCSR
: EQ GT LT
UNORDERED (CGF
/R
, CH
/Y
)
54 Condition codes resulting from add with overflow
56 CCA
: EQ LT GT Overflow
57 CCAP
: EQ LT GT
LT (AGHI
, AHI
)
58 CCAN
: EQ LT GT
GT (AGHI
, AHI
)
60 Condition codes of unsigned adds and subs
62 CCL
: EQ NE EQ
NE (ALGF
/R
, ALG
/R
, AL
/R
/Y
,
64 SLGF
/R
, SLG
/R
, SL
/R
/Y
,
66 CCL1
: GEU GEU LTU
LTU (ALG
/R
, AL
/R
/Y
)
67 CCL2
: GTU GTU LEU
LEU (SLG
/R
, SL
/R
/Y
)
68 CCL3
: EQ LTU EQ
GTU (SLG
/R
, SL
/R
/Y
)
70 Test under mask checks
72 CCT
: EQ NE NE
NE (ICM
/Y
, TML
, CG
/R
, CGHI
,
73 C
/R
/Y
, CHI
, NG
/R
, N
/R
/Y
,
74 OG
/R
, O
/R
/Y
, XG
/R
, X
/R
/Y
)
75 CCT1
: NE EQ NE
NE (TMH
, TML
)
76 CCT2
: NE NE EQ
NE (TMH
, TML
)
77 CCT3
: NE NE NE
EQ (TMH
, TML
)
79 CCA and CCT modes are request only modes. These modes are never returned by
80 s390_select_cc_mode. They are only intended to match other modes.
82 Requested mode
-> Destination CC register mode
84 CCS
, CCU
, CCT
, CCSR
, CCUR
-> CCZ
87 Vector comparison modes
89 CCVEQ EQ
- - NE (VCEQ
)
90 CCVEQANY EQ EQ
- NE (VCEQ
)
93 CCVHANY GT GT
- LE (VCH
)
94 CCVHU GTU
- - LEU (VCHL
)
95 CCVHUANY GTU GTU
- LEU (VCHL
)
97 CCVFH GT
- - UNLE (VFCH
)
98 CCVFHANY GT GT
- UNLE (VFCH
)
99 CCVFHE GE
- - UNLT (VFCHE
)
100 CCVFHEANY GE GE
- UNLT (VFCHE
)
109 The CC obtained from add instruction usually can
't be used for comparisons
110 because its coupling with overflow flag. In case of an overflow the
111 less than/greater than data are lost. Nevertheless a comparison can be done
112 whenever immediate values are involved because they are known at compile time.
113 If you know whether the used constant is positive or negative you can predict
114 the sign of the result even in case of an overflow.
117 CCT, CCT1, CCT2, CCT3
119 If bits of an integer masked with an AND instruction are checked, the test under
120 mask instructions turn out to be very handy for a set of special cases.
121 The simple cases are checks whether all masked bits are zero or ones:
124 if ((a & (16 + 128)) == 0) -> CCT/CCZ
125 if ((a & (16 + 128)) == 16 + 128) -> CCT3
127 Using two extra modes makes it possible to do complete checks on two bits of an
128 integer (This is possible on register operands only. TM does not provide the
129 information necessary for CCT1 and CCT2 modes.):
132 if ((a & (16 + 128)) == 16) -> CCT1
133 if ((a & (16 + 128)) == 128) -> CCT2
138 There are several instructions comparing 32 bit with 64-bit unsigned/signed
139 values. Such instructions can be considered to have a builtin zero/sign_extend.
140 The problem is that in the RTL (to be canonical) the zero/sign extended operand
141 has to be the first one but the machine instructions like it the other way
142 around. The following both modes can be considered as CCS and CCU modes with
148 These modes represent the result of overflow checks.
150 if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3)
151 if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1)
153 They are used when multi word numbers are computed dealing one SImode part after
154 another or whenever manual overflow checks like the examples above are
160 A logical subtract instruction sets the borrow bit in case of an overflow.
161 The resulting condition code of those instructions is represented by the
162 CCL3 mode. Together with the CCU mode this mode is used for jumpless
163 implementations of several if-constructs - see s390_expand_addcc for more
168 The compare and swap instructions sets the condition code to 0/1 if the
169 operands were equal/unequal. The CCZ1 mode ensures the result can be
170 effectively placed into a register.
175 The variants with and without ANY are generated by the same
176 instructions and therefore are holding the same information. However,
177 when generating a condition code mask they require checking different
178 bits of CC. In that case the variants without ANY represent the
179 results for *all* elements.
183 The cc mode generated by a non-compare instruction. The condition
184 code mask for the CC consumer is determined by the comparison operator
185 (only EQ and NE allowed) and the immediate value given as second
186 operand to the operator. For the other CC modes this value used to be
227 VECTOR_MODES (INT, 2); /* V2QI */
228 VECTOR_MODES (INT, 4); /* V4QI V2HI */
229 VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
230 VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
232 VECTOR_MODE (FLOAT, SF, 2); /* V2SF */
233 VECTOR_MODE (FLOAT, SF, 4); /* V4SF */
234 VECTOR_MODE (FLOAT, DF, 2); /* V2DF */
236 VECTOR_MODE (INT, QI, 1); /* V1QI */
237 VECTOR_MODE (INT, HI, 1); /* V1HI */
238 VECTOR_MODE (INT, SI, 1); /* V1SI */
239 VECTOR_MODE (INT, DI, 1); /* V1DI */
240 VECTOR_MODE (INT, TI, 1); /* V1TI */
242 VECTOR_MODE (FLOAT, SF, 1); /* V1SF */
243 VECTOR_MODE (FLOAT, DF, 1); /* V1DF */
244 VECTOR_MODE (FLOAT, TF, 1); /* V1TF */