1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts
;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges
;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras
;
118 /* Number of instructions combined in this function. */
120 static int combine_successes
;
122 /* Totals over entire compilation. */
124 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid
;
135 static int max_uid_cuid
;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno
;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick
;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
222 char last_set_sign_bit_copies
;
223 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid
;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies
;
245 unsigned HOST_WIDE_INT nonzero_bits
;
247 /* Record the value of the label_tick when the last truncation
248 happened. The field truncated_to_mode is only valid if
249 truncation_label == label_tick. */
251 int truncation_label
;
253 /* Record the last truncation seen for this register. If truncation
254 is not a nop to this mode we might be able to save an explicit
255 truncation if we know that value already contains a truncated
258 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
261 static struct reg_stat
*reg_stat
;
263 /* Record the cuid of the last insn that invalidated memory
264 (anything that writes memory, and subroutine calls, but not pushes). */
266 static int mem_last_set
;
268 /* Record the cuid of the last CALL_INSN
269 so we can tell whether a potential combination crosses any calls. */
271 static int last_call_cuid
;
273 /* When `subst' is called, this is the insn that is being modified
274 (by combining in a previous insn). The PATTERN of this insn
275 is still the old pattern partially modified and it should not be
276 looked at, but this may be used to examine the successors of the insn
277 to judge whether a simplification is valid. */
279 static rtx subst_insn
;
281 /* This is the lowest CUID that `subst' is currently dealing with.
282 get_last_value will not return a value if the register was set at or
283 after this CUID. If not for this mechanism, we could get confused if
284 I2 or I1 in try_combine were an insn that used the old value of a register
285 to obtain a new value. In that case, we might erroneously get the
286 new value of the register when we wanted the old one. */
288 static int subst_low_cuid
;
290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
291 must consider all these registers to be always live. */
293 static HARD_REG_SET newpat_used_regs
;
295 /* This is an insn to which a LOG_LINKS entry has been added. If this
296 insn is the earlier than I2 or I3, combine should rescan starting at
299 static rtx added_links_insn
;
301 /* Basic block in which we are performing combines. */
302 static basic_block this_basic_block
;
304 /* A bitmap indicating which blocks had registers go dead at entry.
305 After combine, we'll need to re-do global life analysis with
306 those blocks as starting points. */
307 static sbitmap refresh_blocks
;
309 /* The following array records the insn_rtx_cost for every insn
310 in the instruction stream. */
312 static int *uid_insn_cost
;
314 /* Length of the currently allocated uid_insn_cost array. */
316 static int last_insn_cost
;
318 /* Incremented for each label. */
320 static int label_tick
;
322 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
323 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
325 static enum machine_mode nonzero_bits_mode
;
327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
328 be safely used. It is zero while computing them and after combine has
329 completed. This former test prevents propagating values based on
330 previously set values, which can be incorrect if a variable is modified
333 static int nonzero_sign_valid
;
336 /* Record one modification to rtl structure
337 to be undone by storing old_contents into *where. */
342 enum { UNDO_RTX
, UNDO_INT
, UNDO_MODE
} kind
;
343 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
344 union { rtx
*r
; int *i
; } where
;
347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
348 num_undo says how many are currently recorded.
350 other_insn is nonzero if we have modified some other insn in the process
351 of working on subst_insn. It must be verified too. */
360 static struct undobuf undobuf
;
362 /* Number of times the pseudo being substituted for
363 was found and replaced. */
365 static int n_occurrences
;
367 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
369 unsigned HOST_WIDE_INT
,
370 unsigned HOST_WIDE_INT
*);
371 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
373 unsigned int, unsigned int *);
374 static void do_SUBST (rtx
*, rtx
);
375 static void do_SUBST_INT (int *, int);
376 static void init_reg_last (void);
377 static void setup_incoming_promotions (void);
378 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
379 static int cant_combine_insn_p (rtx
);
380 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
381 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
382 static int contains_muldiv (rtx
);
383 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
384 static void undo_all (void);
385 static void undo_commit (void);
386 static rtx
*find_split_point (rtx
*, rtx
);
387 static rtx
subst (rtx
, rtx
, rtx
, int, int);
388 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
389 static rtx
simplify_if_then_else (rtx
);
390 static rtx
simplify_set (rtx
);
391 static rtx
simplify_logical (rtx
);
392 static rtx
expand_compound_operation (rtx
);
393 static rtx
expand_field_assignment (rtx
);
394 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
395 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
396 static rtx
extract_left_shift (rtx
, int);
397 static rtx
make_compound_operation (rtx
, enum rtx_code
);
398 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
399 unsigned HOST_WIDE_INT
*);
400 static rtx
canon_reg_for_combine (rtx
, rtx
);
401 static rtx
force_to_mode (rtx
, enum machine_mode
,
402 unsigned HOST_WIDE_INT
, int);
403 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
404 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
405 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
406 static rtx
make_field_assignment (rtx
);
407 static rtx
apply_distributive_law (rtx
);
408 static rtx
distribute_and_simplify_rtx (rtx
, int);
409 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
410 unsigned HOST_WIDE_INT
);
411 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
412 unsigned HOST_WIDE_INT
);
413 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
414 HOST_WIDE_INT
, enum machine_mode
, int *);
415 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
416 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
418 static int recog_for_combine (rtx
*, rtx
, rtx
*);
419 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
420 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
421 static void update_table_tick (rtx
);
422 static void record_value_for_reg (rtx
, rtx
, rtx
);
423 static void check_conversions (rtx
, rtx
);
424 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
425 static void record_dead_and_set_regs (rtx
);
426 static int get_last_value_validate (rtx
*, rtx
, int, int);
427 static rtx
get_last_value (rtx
);
428 static int use_crosses_set_p (rtx
, int);
429 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
430 static int reg_dead_at_p (rtx
, rtx
);
431 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
432 static int reg_bitfield_target_p (rtx
, rtx
);
433 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
434 static void distribute_links (rtx
);
435 static void mark_used_regs_combine (rtx
);
436 static int insn_cuid (rtx
);
437 static void record_promoted_value (rtx
, rtx
);
438 static int unmentioned_reg_p_1 (rtx
*, void *);
439 static bool unmentioned_reg_p (rtx
, rtx
);
440 static void record_truncated_value (rtx
);
441 static bool reg_truncated_to_mode (enum machine_mode
, rtx
);
442 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
445 /* It is not safe to use ordinary gen_lowpart in combine.
446 See comments in gen_lowpart_for_combine. */
447 #undef RTL_HOOKS_GEN_LOWPART
448 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
450 /* Our implementation of gen_lowpart never emits a new pseudo. */
451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
455 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
460 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
463 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
464 insn. The substitution can be undone by undo_all. If INTO is already
465 set to NEWVAL, do not record this change. Because computing NEWVAL might
466 also call SUBST, we have to compute it before we put anything into
470 do_SUBST (rtx
*into
, rtx newval
)
475 if (oldval
== newval
)
478 /* We'd like to catch as many invalid transformations here as
479 possible. Unfortunately, there are way too many mode changes
480 that are perfectly valid, so we'd waste too much effort for
481 little gain doing the checks here. Focus on catching invalid
482 transformations involving integer constants. */
483 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
484 && GET_CODE (newval
) == CONST_INT
)
486 /* Sanity check that we're replacing oldval with a CONST_INT
487 that is a valid sign-extension for the original mode. */
488 gcc_assert (INTVAL (newval
)
489 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
491 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
492 CONST_INT is not valid, because after the replacement, the
493 original mode would be gone. Unfortunately, we can't tell
494 when do_SUBST is called to replace the operand thereof, so we
495 perform this test on oldval instead, checking whether an
496 invalid replacement took place before we got here. */
497 gcc_assert (!(GET_CODE (oldval
) == SUBREG
498 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
499 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
500 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
504 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
506 buf
= xmalloc (sizeof (struct undo
));
508 buf
->kind
= UNDO_RTX
;
510 buf
->old_contents
.r
= oldval
;
513 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
516 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
518 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
519 for the value of a HOST_WIDE_INT value (including CONST_INT) is
523 do_SUBST_INT (int *into
, int newval
)
528 if (oldval
== newval
)
532 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
534 buf
= xmalloc (sizeof (struct undo
));
536 buf
->kind
= UNDO_INT
;
538 buf
->old_contents
.i
= oldval
;
541 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
544 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
546 /* Similar to SUBST, but just substitute the mode. This is used when
547 changing the mode of a pseudo-register, so that any other
548 references to the entry in the regno_reg_rtx array will change as
552 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
555 enum machine_mode oldval
= GET_MODE (*into
);
557 if (oldval
== newval
)
561 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
563 buf
= xmalloc (sizeof (struct undo
));
565 buf
->kind
= UNDO_MODE
;
567 buf
->old_contents
.m
= oldval
;
568 PUT_MODE (*into
, newval
);
570 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
573 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
575 /* Subroutine of try_combine. Determine whether the combine replacement
576 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
577 that the original instruction sequence I1, I2 and I3. Note that I1
578 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
579 costs of all instructions can be estimated, and the replacements are
580 more expensive than the original sequence. */
583 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
585 int i1_cost
, i2_cost
, i3_cost
;
586 int new_i2_cost
, new_i3_cost
;
587 int old_cost
, new_cost
;
589 /* Lookup the original insn_rtx_costs. */
590 i2_cost
= INSN_UID (i2
) <= last_insn_cost
591 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
592 i3_cost
= INSN_UID (i3
) <= last_insn_cost
593 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
597 i1_cost
= INSN_UID (i1
) <= last_insn_cost
598 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
599 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
600 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
604 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
608 /* Calculate the replacement insn_rtx_costs. */
609 new_i3_cost
= insn_rtx_cost (newpat
);
612 new_i2_cost
= insn_rtx_cost (newi2pat
);
613 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
614 ? new_i2_cost
+ new_i3_cost
: 0;
618 new_cost
= new_i3_cost
;
622 if (undobuf
.other_insn
)
624 int old_other_cost
, new_other_cost
;
626 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
627 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
628 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
629 if (old_other_cost
> 0 && new_other_cost
> 0)
631 old_cost
+= old_other_cost
;
632 new_cost
+= new_other_cost
;
638 /* Disallow this recombination if both new_cost and old_cost are
639 greater than zero, and new_cost is greater than old cost. */
641 && new_cost
> old_cost
)
648 "rejecting combination of insns %d, %d and %d\n",
649 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
650 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
651 i1_cost
, i2_cost
, i3_cost
, old_cost
);
656 "rejecting combination of insns %d and %d\n",
657 INSN_UID (i2
), INSN_UID (i3
));
658 fprintf (dump_file
, "original costs %d + %d = %d\n",
659 i2_cost
, i3_cost
, old_cost
);
664 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
665 new_i2_cost
, new_i3_cost
, new_cost
);
668 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
674 /* Update the uid_insn_cost array with the replacement costs. */
675 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
676 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
678 uid_insn_cost
[INSN_UID (i1
)] = 0;
683 /* Main entry point for combiner. F is the first insn of the function.
684 NREGS is the first unused pseudo-reg number.
686 Return nonzero if the combiner has turned an indirect jump
687 instruction into a direct jump. */
689 combine_instructions (rtx f
, unsigned int nregs
)
697 rtx links
, nextlinks
;
698 sbitmap_iterator sbi
;
700 int new_direct_jump_p
= 0;
702 combine_attempts
= 0;
705 combine_successes
= 0;
707 combine_max_regno
= nregs
;
709 rtl_hooks
= combine_rtl_hooks
;
711 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
713 init_recog_no_volatile ();
715 /* Compute maximum uid value so uid_cuid can be allocated. */
717 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
718 if (INSN_UID (insn
) > i
)
721 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
724 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
726 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
727 problems when, for example, we have j <<= 1 in a loop. */
729 nonzero_sign_valid
= 0;
731 /* Compute the mapping from uids to cuids.
732 Cuids are numbers assigned to insns, like uids,
733 except that cuids increase monotonically through the code.
735 Scan all SETs and see if we can deduce anything about what
736 bits are known to be zero for some registers and how many copies
737 of the sign bit are known to exist for those registers.
739 Also set any known values so that we can use it while searching
740 for what bits are known to be set. */
744 setup_incoming_promotions ();
746 refresh_blocks
= sbitmap_alloc (last_basic_block
);
747 sbitmap_zero (refresh_blocks
);
749 /* Allocate array of current insn_rtx_costs. */
750 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
751 last_insn_cost
= max_uid_cuid
;
753 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
755 uid_cuid
[INSN_UID (insn
)] = ++i
;
761 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
763 record_dead_and_set_regs (insn
);
766 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
767 if (REG_NOTE_KIND (links
) == REG_INC
)
768 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
772 /* Record the current insn_rtx_cost of this instruction. */
773 if (NONJUMP_INSN_P (insn
))
774 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
776 fprintf(dump_file
, "insn_cost %d: %d\n",
777 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
784 nonzero_sign_valid
= 1;
786 /* Now scan all the insns in forward order. */
792 setup_incoming_promotions ();
794 FOR_EACH_BB (this_basic_block
)
796 for (insn
= BB_HEAD (this_basic_block
);
797 insn
!= NEXT_INSN (BB_END (this_basic_block
));
798 insn
= next
? next
: NEXT_INSN (insn
))
805 else if (INSN_P (insn
))
807 /* See if we know about function return values before this
808 insn based upon SUBREG flags. */
809 check_conversions (insn
, PATTERN (insn
));
811 /* Try this insn with each insn it links back to. */
813 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
814 if ((next
= try_combine (insn
, XEXP (links
, 0),
815 NULL_RTX
, &new_direct_jump_p
)) != 0)
818 /* Try each sequence of three linked insns ending with this one. */
820 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
822 rtx link
= XEXP (links
, 0);
824 /* If the linked insn has been replaced by a note, then there
825 is no point in pursuing this chain any further. */
829 for (nextlinks
= LOG_LINKS (link
);
831 nextlinks
= XEXP (nextlinks
, 1))
832 if ((next
= try_combine (insn
, link
,
834 &new_direct_jump_p
)) != 0)
839 /* Try to combine a jump insn that uses CC0
840 with a preceding insn that sets CC0, and maybe with its
841 logical predecessor as well.
842 This is how we make decrement-and-branch insns.
843 We need this special code because data flow connections
844 via CC0 do not get entered in LOG_LINKS. */
847 && (prev
= prev_nonnote_insn (insn
)) != 0
848 && NONJUMP_INSN_P (prev
)
849 && sets_cc0_p (PATTERN (prev
)))
851 if ((next
= try_combine (insn
, prev
,
852 NULL_RTX
, &new_direct_jump_p
)) != 0)
855 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
856 nextlinks
= XEXP (nextlinks
, 1))
857 if ((next
= try_combine (insn
, prev
,
859 &new_direct_jump_p
)) != 0)
863 /* Do the same for an insn that explicitly references CC0. */
864 if (NONJUMP_INSN_P (insn
)
865 && (prev
= prev_nonnote_insn (insn
)) != 0
866 && NONJUMP_INSN_P (prev
)
867 && sets_cc0_p (PATTERN (prev
))
868 && GET_CODE (PATTERN (insn
)) == SET
869 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
871 if ((next
= try_combine (insn
, prev
,
872 NULL_RTX
, &new_direct_jump_p
)) != 0)
875 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
876 nextlinks
= XEXP (nextlinks
, 1))
877 if ((next
= try_combine (insn
, prev
,
879 &new_direct_jump_p
)) != 0)
883 /* Finally, see if any of the insns that this insn links to
884 explicitly references CC0. If so, try this insn, that insn,
885 and its predecessor if it sets CC0. */
886 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
887 if (NONJUMP_INSN_P (XEXP (links
, 0))
888 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
889 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
890 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
891 && NONJUMP_INSN_P (prev
)
892 && sets_cc0_p (PATTERN (prev
))
893 && (next
= try_combine (insn
, XEXP (links
, 0),
894 prev
, &new_direct_jump_p
)) != 0)
898 /* Try combining an insn with two different insns whose results it
900 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
901 for (nextlinks
= XEXP (links
, 1); nextlinks
;
902 nextlinks
= XEXP (nextlinks
, 1))
903 if ((next
= try_combine (insn
, XEXP (links
, 0),
905 &new_direct_jump_p
)) != 0)
908 /* Try this insn with each REG_EQUAL note it links back to. */
909 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
912 rtx temp
= XEXP (links
, 0);
913 if ((set
= single_set (temp
)) != 0
914 && (note
= find_reg_equal_equiv_note (temp
)) != 0
915 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
916 /* Avoid using a register that may already been marked
917 dead by an earlier instruction. */
918 && ! unmentioned_reg_p (note
, SET_SRC (set
))
919 && (GET_MODE (note
) == VOIDmode
920 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
921 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
923 /* Temporarily replace the set's source with the
924 contents of the REG_EQUAL note. The insn will
925 be deleted or recognized by try_combine. */
926 rtx orig
= SET_SRC (set
);
927 SET_SRC (set
) = note
;
928 next
= try_combine (insn
, temp
, NULL_RTX
,
932 SET_SRC (set
) = orig
;
937 record_dead_and_set_regs (insn
);
946 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, j
, sbi
)
947 BASIC_BLOCK (j
)->flags
|= BB_DIRTY
;
948 new_direct_jump_p
|= purge_all_dead_edges ();
949 delete_noop_moves ();
951 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
952 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
953 | PROP_KILL_DEAD_CODE
);
956 sbitmap_free (refresh_blocks
);
957 free (uid_insn_cost
);
962 struct undo
*undo
, *next
;
963 for (undo
= undobuf
.frees
; undo
; undo
= next
)
971 total_attempts
+= combine_attempts
;
972 total_merges
+= combine_merges
;
973 total_extras
+= combine_extras
;
974 total_successes
+= combine_successes
;
976 nonzero_sign_valid
= 0;
977 rtl_hooks
= general_rtl_hooks
;
979 /* Make recognizer allow volatile MEMs again. */
982 return new_direct_jump_p
;
985 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
991 for (i
= 0; i
< combine_max_regno
; i
++)
992 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
995 /* Set up any promoted values for incoming argument registers. */
998 setup_incoming_promotions (void)
1002 enum machine_mode mode
;
1004 rtx first
= get_insns ();
1006 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
1008 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1009 /* Check whether this register can hold an incoming pointer
1010 argument. FUNCTION_ARG_REGNO_P tests outgoing register
1011 numbers, so translate if necessary due to register windows. */
1012 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
1013 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
1015 record_value_for_reg
1016 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
1019 gen_rtx_CLOBBER (mode
, const0_rtx
)));
1024 /* Called via note_stores. If X is a pseudo that is narrower than
1025 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1027 If we are setting only a portion of X and we can't figure out what
1028 portion, assume all bits will be used since we don't know what will
1031 Similarly, set how many bits of X are known to be copies of the sign bit
1032 at all locations in the function. This is the smallest number implied
1036 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
1037 void *data ATTRIBUTE_UNUSED
)
1042 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1043 /* If this register is undefined at the start of the file, we can't
1044 say what its contents were. */
1045 && ! REGNO_REG_SET_P
1046 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
, REGNO (x
))
1047 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1049 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1051 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1052 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1056 /* If this is a complex assignment, see if we can convert it into a
1057 simple assignment. */
1058 set
= expand_field_assignment (set
);
1060 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1061 set what we know about X. */
1063 if (SET_DEST (set
) == x
1064 || (GET_CODE (SET_DEST (set
)) == SUBREG
1065 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1066 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1067 && SUBREG_REG (SET_DEST (set
)) == x
))
1069 rtx src
= SET_SRC (set
);
1071 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1072 /* If X is narrower than a word and SRC is a non-negative
1073 constant that would appear negative in the mode of X,
1074 sign-extend it for use in reg_stat[].nonzero_bits because some
1075 machines (maybe most) will actually do the sign-extension
1076 and this is the conservative approach.
1078 ??? For 2.5, try to tighten up the MD files in this regard
1079 instead of this kludge. */
1081 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1082 && GET_CODE (src
) == CONST_INT
1084 && 0 != (INTVAL (src
)
1085 & ((HOST_WIDE_INT
) 1
1086 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1087 src
= GEN_INT (INTVAL (src
)
1088 | ((HOST_WIDE_INT
) (-1)
1089 << GET_MODE_BITSIZE (GET_MODE (x
))));
1092 /* Don't call nonzero_bits if it cannot change anything. */
1093 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1094 reg_stat
[REGNO (x
)].nonzero_bits
1095 |= nonzero_bits (src
, nonzero_bits_mode
);
1096 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1097 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1098 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1099 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1103 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1104 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1109 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1110 insns that were previously combined into I3 or that will be combined
1111 into the merger of INSN and I3.
1113 Return 0 if the combination is not allowed for any reason.
1115 If the combination is allowed, *PDEST will be set to the single
1116 destination of INSN and *PSRC to the single source, and this function
1120 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1121 rtx
*pdest
, rtx
*psrc
)
1124 rtx set
= 0, src
, dest
;
1129 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1130 && next_active_insn (succ
) == i3
)
1131 : next_active_insn (insn
) == i3
);
1133 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1134 or a PARALLEL consisting of such a SET and CLOBBERs.
1136 If INSN has CLOBBER parallel parts, ignore them for our processing.
1137 By definition, these happen during the execution of the insn. When it
1138 is merged with another insn, all bets are off. If they are, in fact,
1139 needed and aren't also supplied in I3, they may be added by
1140 recog_for_combine. Otherwise, it won't match.
1142 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1145 Get the source and destination of INSN. If more than one, can't
1148 if (GET_CODE (PATTERN (insn
)) == SET
)
1149 set
= PATTERN (insn
);
1150 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1151 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1153 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1155 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1158 switch (GET_CODE (elt
))
1160 /* This is important to combine floating point insns
1161 for the SH4 port. */
1163 /* Combining an isolated USE doesn't make sense.
1164 We depend here on combinable_i3pat to reject them. */
1165 /* The code below this loop only verifies that the inputs of
1166 the SET in INSN do not change. We call reg_set_between_p
1167 to verify that the REG in the USE does not change between
1169 If the USE in INSN was for a pseudo register, the matching
1170 insn pattern will likely match any register; combining this
1171 with any other USE would only be safe if we knew that the
1172 used registers have identical values, or if there was
1173 something to tell them apart, e.g. different modes. For
1174 now, we forgo such complicated tests and simply disallow
1175 combining of USES of pseudo registers with any other USE. */
1176 if (REG_P (XEXP (elt
, 0))
1177 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1179 rtx i3pat
= PATTERN (i3
);
1180 int i
= XVECLEN (i3pat
, 0) - 1;
1181 unsigned int regno
= REGNO (XEXP (elt
, 0));
1185 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1187 if (GET_CODE (i3elt
) == USE
1188 && REG_P (XEXP (i3elt
, 0))
1189 && (REGNO (XEXP (i3elt
, 0)) == regno
1190 ? reg_set_between_p (XEXP (elt
, 0),
1191 PREV_INSN (insn
), i3
)
1192 : regno
>= FIRST_PSEUDO_REGISTER
))
1199 /* We can ignore CLOBBERs. */
1204 /* Ignore SETs whose result isn't used but not those that
1205 have side-effects. */
1206 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1207 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1208 || INTVAL (XEXP (note
, 0)) <= 0)
1209 && ! side_effects_p (elt
))
1212 /* If we have already found a SET, this is a second one and
1213 so we cannot combine with this insn. */
1221 /* Anything else means we can't combine. */
1227 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1228 so don't do anything with it. */
1229 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1238 set
= expand_field_assignment (set
);
1239 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1241 /* Don't eliminate a store in the stack pointer. */
1242 if (dest
== stack_pointer_rtx
1243 /* Don't combine with an insn that sets a register to itself if it has
1244 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1245 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1246 /* Can't merge an ASM_OPERANDS. */
1247 || GET_CODE (src
) == ASM_OPERANDS
1248 /* Can't merge a function call. */
1249 || GET_CODE (src
) == CALL
1250 /* Don't eliminate a function call argument. */
1252 && (find_reg_fusage (i3
, USE
, dest
)
1254 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1255 && global_regs
[REGNO (dest
)])))
1256 /* Don't substitute into an incremented register. */
1257 || FIND_REG_INC_NOTE (i3
, dest
)
1258 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1259 /* Don't substitute into a non-local goto, this confuses CFG. */
1260 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1262 /* Don't combine the end of a libcall into anything. */
1263 /* ??? This gives worse code, and appears to be unnecessary, since no
1264 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1265 use REG_RETVAL notes for noconflict blocks, but other code here
1266 makes sure that those insns don't disappear. */
1267 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1269 /* Make sure that DEST is not used after SUCC but before I3. */
1270 || (succ
&& ! all_adjacent
1271 && reg_used_between_p (dest
, succ
, i3
))
1272 /* Make sure that the value that is to be substituted for the register
1273 does not use any registers whose values alter in between. However,
1274 If the insns are adjacent, a use can't cross a set even though we
1275 think it might (this can happen for a sequence of insns each setting
1276 the same destination; last_set of that register might point to
1277 a NOTE). If INSN has a REG_EQUIV note, the register is always
1278 equivalent to the memory so the substitution is valid even if there
1279 are intervening stores. Also, don't move a volatile asm or
1280 UNSPEC_VOLATILE across any other insns. */
1283 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1284 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1285 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1286 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1287 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1288 better register allocation by not doing the combine. */
1289 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1290 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1291 /* Don't combine across a CALL_INSN, because that would possibly
1292 change whether the life span of some REGs crosses calls or not,
1293 and it is a pain to update that information.
1294 Exception: if source is a constant, moving it later can't hurt.
1295 Accept that special case, because it helps -fforce-addr a lot. */
1296 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1299 /* DEST must either be a REG or CC0. */
1302 /* If register alignment is being enforced for multi-word items in all
1303 cases except for parameters, it is possible to have a register copy
1304 insn referencing a hard register that is not allowed to contain the
1305 mode being copied and which would not be valid as an operand of most
1306 insns. Eliminate this problem by not combining with such an insn.
1308 Also, on some machines we don't want to extend the life of a hard
1312 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1313 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1314 /* Don't extend the life of a hard register unless it is
1315 user variable (if we have few registers) or it can't
1316 fit into the desired register (meaning something special
1318 Also avoid substituting a return register into I3, because
1319 reload can't handle a conflict with constraints of other
1321 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1322 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1325 else if (GET_CODE (dest
) != CC0
)
1329 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1330 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1331 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1333 /* Don't substitute for a register intended as a clobberable
1335 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1336 if (rtx_equal_p (reg
, dest
))
1339 /* If the clobber represents an earlyclobber operand, we must not
1340 substitute an expression containing the clobbered register.
1341 As we do not analyze the constraint strings here, we have to
1342 make the conservative assumption. However, if the register is
1343 a fixed hard reg, the clobber cannot represent any operand;
1344 we leave it up to the machine description to either accept or
1345 reject use-and-clobber patterns. */
1347 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1348 || !fixed_regs
[REGNO (reg
)])
1349 if (reg_overlap_mentioned_p (reg
, src
))
1353 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1354 or not), reject, unless nothing volatile comes between it and I3 */
1356 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1358 /* Make sure succ doesn't contain a volatile reference. */
1359 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1362 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1363 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1367 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1368 to be an explicit register variable, and was chosen for a reason. */
1370 if (GET_CODE (src
) == ASM_OPERANDS
1371 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1374 /* If there are any volatile insns between INSN and I3, reject, because
1375 they might affect machine state. */
1377 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1378 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1381 /* If INSN contains an autoincrement or autodecrement, make sure that
1382 register is not used between there and I3, and not already used in
1383 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1384 Also insist that I3 not be a jump; if it were one
1385 and the incremented register were spilled, we would lose. */
1388 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1389 if (REG_NOTE_KIND (link
) == REG_INC
1391 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1392 || (pred
!= NULL_RTX
1393 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1394 || (succ
!= NULL_RTX
1395 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1396 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1401 /* Don't combine an insn that follows a CC0-setting insn.
1402 An insn that uses CC0 must not be separated from the one that sets it.
1403 We do, however, allow I2 to follow a CC0-setting insn if that insn
1404 is passed as I1; in that case it will be deleted also.
1405 We also allow combining in this case if all the insns are adjacent
1406 because that would leave the two CC0 insns adjacent as well.
1407 It would be more logical to test whether CC0 occurs inside I1 or I2,
1408 but that would be much slower, and this ought to be equivalent. */
1410 p
= prev_nonnote_insn (insn
);
1411 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1416 /* If we get here, we have passed all the tests and the combination is
1425 /* LOC is the location within I3 that contains its pattern or the component
1426 of a PARALLEL of the pattern. We validate that it is valid for combining.
1428 One problem is if I3 modifies its output, as opposed to replacing it
1429 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1430 so would produce an insn that is not equivalent to the original insns.
1434 (set (reg:DI 101) (reg:DI 100))
1435 (set (subreg:SI (reg:DI 101) 0) <foo>)
1437 This is NOT equivalent to:
1439 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1440 (set (reg:DI 101) (reg:DI 100))])
1442 Not only does this modify 100 (in which case it might still be valid
1443 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1445 We can also run into a problem if I2 sets a register that I1
1446 uses and I1 gets directly substituted into I3 (not via I2). In that
1447 case, we would be getting the wrong value of I2DEST into I3, so we
1448 must reject the combination. This case occurs when I2 and I1 both
1449 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1450 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1451 of a SET must prevent combination from occurring.
1453 Before doing the above check, we first try to expand a field assignment
1454 into a set of logical operations.
1456 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1457 we place a register that is both set and used within I3. If more than one
1458 such register is detected, we fail.
1460 Return 1 if the combination is valid, zero otherwise. */
1463 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1464 int i1_not_in_src
, rtx
*pi3dest_killed
)
1468 if (GET_CODE (x
) == SET
)
1471 rtx dest
= SET_DEST (set
);
1472 rtx src
= SET_SRC (set
);
1473 rtx inner_dest
= dest
;
1476 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1477 || GET_CODE (inner_dest
) == SUBREG
1478 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1479 inner_dest
= XEXP (inner_dest
, 0);
1481 /* Check for the case where I3 modifies its output, as discussed
1482 above. We don't want to prevent pseudos from being combined
1483 into the address of a MEM, so only prevent the combination if
1484 i1 or i2 set the same MEM. */
1485 if ((inner_dest
!= dest
&&
1486 (!MEM_P (inner_dest
)
1487 || rtx_equal_p (i2dest
, inner_dest
)
1488 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1489 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1490 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1492 /* This is the same test done in can_combine_p except we can't test
1493 all_adjacent; we don't have to, since this instruction will stay
1494 in place, thus we are not considering increasing the lifetime of
1497 Also, if this insn sets a function argument, combining it with
1498 something that might need a spill could clobber a previous
1499 function argument; the all_adjacent test in can_combine_p also
1500 checks this; here, we do a more specific test for this case. */
1502 || (REG_P (inner_dest
)
1503 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1504 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1505 GET_MODE (inner_dest
))))
1506 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1509 /* If DEST is used in I3, it is being killed in this insn, so
1510 record that for later. We have to consider paradoxical
1511 subregs here, since they kill the whole register, but we
1512 ignore partial subregs, STRICT_LOW_PART, etc.
1513 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1514 STACK_POINTER_REGNUM, since these are always considered to be
1515 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1517 if (GET_CODE (subdest
) == SUBREG
1518 && (GET_MODE_SIZE (GET_MODE (subdest
))
1519 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
1520 subdest
= SUBREG_REG (subdest
);
1523 && reg_referenced_p (subdest
, PATTERN (i3
))
1524 && REGNO (subdest
) != FRAME_POINTER_REGNUM
1525 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
1528 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529 && (REGNO (subdest
) != ARG_POINTER_REGNUM
1530 || ! fixed_regs
[REGNO (subdest
)])
1532 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
1534 if (*pi3dest_killed
)
1537 *pi3dest_killed
= subdest
;
1541 else if (GET_CODE (x
) == PARALLEL
)
1545 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1546 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1547 i1_not_in_src
, pi3dest_killed
))
1554 /* Return 1 if X is an arithmetic expression that contains a multiplication
1555 and division. We don't count multiplications by powers of two here. */
1558 contains_muldiv (rtx x
)
1560 switch (GET_CODE (x
))
1562 case MOD
: case DIV
: case UMOD
: case UDIV
:
1566 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1567 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1570 return contains_muldiv (XEXP (x
, 0))
1571 || contains_muldiv (XEXP (x
, 1));
1574 return contains_muldiv (XEXP (x
, 0));
1580 /* Determine whether INSN can be used in a combination. Return nonzero if
1581 not. This is used in try_combine to detect early some cases where we
1582 can't perform combinations. */
1585 cant_combine_insn_p (rtx insn
)
1590 /* If this isn't really an insn, we can't do anything.
1591 This can occur when flow deletes an insn that it has merged into an
1592 auto-increment address. */
1593 if (! INSN_P (insn
))
1596 /* Never combine loads and stores involving hard regs that are likely
1597 to be spilled. The register allocator can usually handle such
1598 reg-reg moves by tying. If we allow the combiner to make
1599 substitutions of likely-spilled regs, reload might die.
1600 As an exception, we allow combinations involving fixed regs; these are
1601 not available to the register allocator so there's no risk involved. */
1603 set
= single_set (insn
);
1606 src
= SET_SRC (set
);
1607 dest
= SET_DEST (set
);
1608 if (GET_CODE (src
) == SUBREG
)
1609 src
= SUBREG_REG (src
);
1610 if (GET_CODE (dest
) == SUBREG
)
1611 dest
= SUBREG_REG (dest
);
1612 if (REG_P (src
) && REG_P (dest
)
1613 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1614 && ! fixed_regs
[REGNO (src
)]
1615 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1616 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1617 && ! fixed_regs
[REGNO (dest
)]
1618 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1624 struct likely_spilled_retval_info
1626 unsigned regno
, nregs
;
1630 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1631 hard registers that are known to be written to / clobbered in full. */
1633 likely_spilled_retval_1 (rtx x
, rtx set
, void *data
)
1635 struct likely_spilled_retval_info
*info
= data
;
1636 unsigned regno
, nregs
;
1639 if (!REG_P (XEXP (set
, 0)))
1642 if (regno
>= info
->regno
+ info
->nregs
)
1644 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1645 if (regno
+ nregs
<= info
->regno
)
1647 new_mask
= (2U << (nregs
- 1)) - 1;
1648 if (regno
< info
->regno
)
1649 new_mask
>>= info
->regno
- regno
;
1651 new_mask
<<= regno
- info
->regno
;
1652 info
->mask
&= new_mask
;
1655 /* Return nonzero iff part of the return value is live during INSN, and
1656 it is likely spilled. This can happen when more than one insn is needed
1657 to copy the return value, e.g. when we consider to combine into the
1658 second copy insn for a complex value. */
1661 likely_spilled_retval_p (rtx insn
)
1663 rtx use
= BB_END (this_basic_block
);
1665 unsigned regno
, nregs
;
1666 /* We assume here that no machine mode needs more than
1667 32 hard registers when the value overlaps with a register
1668 for which FUNCTION_VALUE_REGNO_P is true. */
1670 struct likely_spilled_retval_info info
;
1672 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
1674 reg
= XEXP (PATTERN (use
), 0);
1675 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
1677 regno
= REGNO (reg
);
1678 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1681 mask
= (2U << (nregs
- 1)) - 1;
1683 /* Disregard parts of the return value that are set later. */
1687 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
1688 note_stores (PATTERN (insn
), likely_spilled_retval_1
, &info
);
1691 /* Check if any of the (probably) live return value registers is
1696 if ((mask
& 1 << nregs
)
1697 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
1703 /* Adjust INSN after we made a change to its destination.
1705 Changing the destination can invalidate notes that say something about
1706 the results of the insn and a LOG_LINK pointing to the insn. */
1709 adjust_for_new_dest (rtx insn
)
1713 /* For notes, be conservative and simply remove them. */
1714 loc
= ®_NOTES (insn
);
1717 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1718 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1719 *loc
= XEXP (*loc
, 1);
1721 loc
= &XEXP (*loc
, 1);
1724 /* The new insn will have a destination that was previously the destination
1725 of an insn just above it. Call distribute_links to make a LOG_LINK from
1726 the next use of that destination. */
1727 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1730 /* Return TRUE if combine can reuse reg X in mode MODE.
1731 ADDED_SETS is nonzero if the original set is still required. */
1733 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
1741 /* Allow hard registers if the new mode is legal, and occupies no more
1742 registers than the old mode. */
1743 if (regno
< FIRST_PSEUDO_REGISTER
)
1744 return (HARD_REGNO_MODE_OK (regno
, mode
)
1745 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
1746 >= hard_regno_nregs
[regno
][mode
]));
1748 /* Or a pseudo that is only used once. */
1749 return (REG_N_SETS (regno
) == 1 && !added_sets
1750 && !REG_USERVAR_P (x
));
1754 /* Check whether X, the destination of a set, refers to part of
1755 the register specified by REG. */
1758 reg_subword_p (rtx x
, rtx reg
)
1760 /* Check that reg is an integer mode register. */
1761 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
1764 if (GET_CODE (x
) == STRICT_LOW_PART
1765 || GET_CODE (x
) == ZERO_EXTRACT
)
1768 return GET_CODE (x
) == SUBREG
1769 && SUBREG_REG (x
) == reg
1770 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
1774 /* Try to combine the insns I1 and I2 into I3.
1775 Here I1 and I2 appear earlier than I3.
1776 I1 can be zero; then we combine just I2 into I3.
1778 If we are combining three insns and the resulting insn is not recognized,
1779 try splitting it into two insns. If that happens, I2 and I3 are retained
1780 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1783 Return 0 if the combination does not work. Then nothing is changed.
1784 If we did the combination, return the insn at which combine should
1787 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1788 new direct jump instruction. */
1791 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1793 /* New patterns for I3 and I2, respectively. */
1794 rtx newpat
, newi2pat
= 0;
1795 rtvec newpat_vec_with_clobbers
= 0;
1796 int substed_i2
= 0, substed_i1
= 0;
1797 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1798 int added_sets_1
, added_sets_2
;
1799 /* Total number of SETs to put into I3. */
1801 /* Nonzero if I2's body now appears in I3. */
1803 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1804 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1805 /* Contains I3 if the destination of I3 is used in its source, which means
1806 that the old life of I3 is being killed. If that usage is placed into
1807 I2 and not in I3, a REG_DEAD note must be made. */
1808 rtx i3dest_killed
= 0;
1809 /* SET_DEST and SET_SRC of I2 and I1. */
1810 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1811 /* PATTERN (I2), or a copy of it in certain cases. */
1813 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1814 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1815 int i2dest_killed
= 0, i1dest_killed
= 0;
1816 int i1_feeds_i3
= 0;
1817 /* Notes that must be added to REG_NOTES in I3 and I2. */
1818 rtx new_i3_notes
, new_i2_notes
;
1819 /* Notes that we substituted I3 into I2 instead of the normal case. */
1820 int i3_subst_into_i2
= 0;
1821 /* Notes that I1, I2 or I3 is a MULT operation. */
1830 /* Exit early if one of the insns involved can't be used for
1832 if (cant_combine_insn_p (i3
)
1833 || cant_combine_insn_p (i2
)
1834 || (i1
&& cant_combine_insn_p (i1
))
1835 || likely_spilled_retval_p (i3
)
1836 /* We also can't do anything if I3 has a
1837 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1840 /* ??? This gives worse code, and appears to be unnecessary, since no
1841 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1842 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1848 undobuf
.other_insn
= 0;
1850 /* Reset the hard register usage information. */
1851 CLEAR_HARD_REG_SET (newpat_used_regs
);
1853 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1854 code below, set I1 to be the earlier of the two insns. */
1855 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1856 temp
= i1
, i1
= i2
, i2
= temp
;
1858 added_links_insn
= 0;
1860 /* First check for one important special-case that the code below will
1861 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1862 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1863 we may be able to replace that destination with the destination of I3.
1864 This occurs in the common code where we compute both a quotient and
1865 remainder into a structure, in which case we want to do the computation
1866 directly into the structure to avoid register-register copies.
1868 Note that this case handles both multiple sets in I2 and also
1869 cases where I2 has a number of CLOBBER or PARALLELs.
1871 We make very conservative checks below and only try to handle the
1872 most common cases of this. For example, we only handle the case
1873 where I2 and I3 are adjacent to avoid making difficult register
1876 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1877 && REG_P (SET_SRC (PATTERN (i3
)))
1878 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1879 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1880 && GET_CODE (PATTERN (i2
)) == PARALLEL
1881 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1882 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1883 below would need to check what is inside (and reg_overlap_mentioned_p
1884 doesn't support those codes anyway). Don't allow those destinations;
1885 the resulting insn isn't likely to be recognized anyway. */
1886 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1887 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1888 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1889 SET_DEST (PATTERN (i3
)))
1890 && next_real_insn (i2
) == i3
)
1892 rtx p2
= PATTERN (i2
);
1894 /* Make sure that the destination of I3,
1895 which we are going to substitute into one output of I2,
1896 is not used within another output of I2. We must avoid making this:
1897 (parallel [(set (mem (reg 69)) ...)
1898 (set (reg 69) ...)])
1899 which is not well-defined as to order of actions.
1900 (Besides, reload can't handle output reloads for this.)
1902 The problem can also happen if the dest of I3 is a memory ref,
1903 if another dest in I2 is an indirect memory ref. */
1904 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1905 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1906 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1907 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1908 SET_DEST (XVECEXP (p2
, 0, i
))))
1911 if (i
== XVECLEN (p2
, 0))
1912 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1913 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1914 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1915 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1920 subst_low_cuid
= INSN_CUID (i2
);
1922 added_sets_2
= added_sets_1
= 0;
1923 i2dest
= SET_SRC (PATTERN (i3
));
1924 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
1926 /* Replace the dest in I2 with our dest and make the resulting
1927 insn the new pattern for I3. Then skip to where we
1928 validate the pattern. Everything was set up above. */
1929 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1930 SET_DEST (PATTERN (i3
)));
1933 i3_subst_into_i2
= 1;
1934 goto validate_replacement
;
1938 /* If I2 is setting a pseudo to a constant and I3 is setting some
1939 sub-part of it to another constant, merge them by making a new
1942 && (temp
= single_set (i2
)) != 0
1943 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1944 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1945 && GET_CODE (PATTERN (i3
)) == SET
1946 && (GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
1947 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
1948 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
1950 rtx dest
= SET_DEST (PATTERN (i3
));
1954 if (GET_CODE (dest
) == STRICT_LOW_PART
)
1956 width
= GET_MODE_BITSIZE (GET_MODE (XEXP (dest
, 0)));
1959 else if (GET_CODE (dest
) == ZERO_EXTRACT
)
1961 if (GET_CODE (XEXP (dest
, 1)) == CONST_INT
1962 && GET_CODE (XEXP (dest
, 2)) == CONST_INT
)
1964 width
= INTVAL (XEXP (dest
, 1));
1965 offset
= INTVAL (XEXP (dest
, 2));
1967 if (BITS_BIG_ENDIAN
)
1968 offset
= GET_MODE_BITSIZE (GET_MODE (XEXP (dest
, 0)))
1972 else if (subreg_lowpart_p (dest
))
1974 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
1977 /* ??? Preserve the original logic to handle setting the high word
1978 of double-word pseudos, where inner is half the size of outer
1979 but not the lowpart. This could be generalized by handling
1980 SUBREG_BYTE, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN ourselves.
1981 Unfortunately this logic is tricky to get right and probably
1982 not worth the effort. */
1983 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
1984 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
1986 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
1992 HOST_WIDE_INT mhi
, ohi
, ihi
;
1993 HOST_WIDE_INT mlo
, olo
, ilo
;
1994 rtx inner
= SET_SRC (PATTERN (i3
));
1995 rtx outer
= SET_SRC (temp
);
1997 if (GET_CODE (outer
) == CONST_INT
)
1999 olo
= INTVAL (outer
);
2000 ohi
= olo
< 0 ? -1 : 0;
2004 olo
= CONST_DOUBLE_LOW (outer
);
2005 ohi
= CONST_DOUBLE_HIGH (outer
);
2008 if (GET_CODE (inner
) == CONST_INT
)
2010 ilo
= INTVAL (inner
);
2011 ihi
= ilo
< 0 ? -1 : 0;
2015 ilo
= CONST_DOUBLE_LOW (inner
);
2016 ihi
= CONST_DOUBLE_HIGH (inner
);
2019 if (width
< HOST_BITS_PER_WIDE_INT
)
2021 mlo
= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
2024 else if (width
< HOST_BITS_PER_WIDE_INT
* 2)
2026 mhi
= ((unsigned HOST_WIDE_INT
) 1
2027 << (width
- HOST_BITS_PER_WIDE_INT
)) - 1;
2039 if (offset
>= HOST_BITS_PER_WIDE_INT
)
2041 mhi
= mlo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2043 ihi
= ilo
<< (offset
- HOST_BITS_PER_WIDE_INT
);
2046 else if (offset
> 0)
2048 mhi
= (mhi
<< offset
) | ((unsigned HOST_WIDE_INT
) mlo
2049 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2050 mlo
= mlo
<< offset
;
2051 ihi
= (ihi
<< offset
) | ((unsigned HOST_WIDE_INT
) ilo
2052 >> (HOST_BITS_PER_WIDE_INT
- offset
));
2053 ilo
= ilo
<< offset
;
2056 olo
= (olo
& ~mlo
) | ilo
;
2057 ohi
= (ohi
& ~mhi
) | ihi
;
2061 subst_low_cuid
= INSN_CUID (i2
);
2062 added_sets_2
= added_sets_1
= 0;
2063 i2dest
= SET_DEST (temp
);
2064 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2066 SUBST (SET_SRC (temp
),
2067 immed_double_const (olo
, ohi
, GET_MODE (SET_DEST (temp
))));
2069 newpat
= PATTERN (i2
);
2070 goto validate_replacement
;
2075 /* If we have no I1 and I2 looks like:
2076 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2078 make up a dummy I1 that is
2081 (set (reg:CC X) (compare:CC Y (const_int 0)))
2083 (We can ignore any trailing CLOBBERs.)
2085 This undoes a previous combination and allows us to match a branch-and-
2088 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2089 && XVECLEN (PATTERN (i2
), 0) >= 2
2090 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2091 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2093 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2094 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2095 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2096 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2097 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2098 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2100 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2101 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2106 /* We make I1 with the same INSN_UID as I2. This gives it
2107 the same INSN_CUID for value tracking. Our fake I1 will
2108 never appear in the insn stream so giving it the same INSN_UID
2109 as I2 will not cause a problem. */
2111 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2112 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
2113 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
2116 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2117 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2118 SET_DEST (PATTERN (i1
)));
2123 /* Verify that I2 and I1 are valid for combining. */
2124 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
2125 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
2131 /* Record whether I2DEST is used in I2SRC and similarly for the other
2132 cases. Knowing this will help in register status updating below. */
2133 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2134 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2135 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2136 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2137 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2139 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2141 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
2143 /* Ensure that I3's pattern can be the destination of combines. */
2144 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
2145 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
2152 /* See if any of the insns is a MULT operation. Unless one is, we will
2153 reject a combination that is, since it must be slower. Be conservative
2155 if (GET_CODE (i2src
) == MULT
2156 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2157 || (GET_CODE (PATTERN (i3
)) == SET
2158 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2161 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2162 We used to do this EXCEPT in one case: I3 has a post-inc in an
2163 output operand. However, that exception can give rise to insns like
2165 which is a famous insn on the PDP-11 where the value of r3 used as the
2166 source was model-dependent. Avoid this sort of thing. */
2169 if (!(GET_CODE (PATTERN (i3
)) == SET
2170 && REG_P (SET_SRC (PATTERN (i3
)))
2171 && MEM_P (SET_DEST (PATTERN (i3
)))
2172 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2173 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2174 /* It's not the exception. */
2177 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2178 if (REG_NOTE_KIND (link
) == REG_INC
2179 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2181 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2188 /* See if the SETs in I1 or I2 need to be kept around in the merged
2189 instruction: whenever the value set there is still needed past I3.
2190 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2192 For the SET in I1, we have two cases: If I1 and I2 independently
2193 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2194 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2195 in I1 needs to be kept around unless I1DEST dies or is set in either
2196 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2197 I1DEST. If so, we know I1 feeds into I2. */
2199 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2202 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2203 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2205 /* If the set in I2 needs to be kept around, we must make a copy of
2206 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2207 PATTERN (I2), we are only substituting for the original I1DEST, not into
2208 an already-substituted copy. This also prevents making self-referential
2209 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2212 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
2213 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
2217 i2pat
= copy_rtx (i2pat
);
2221 /* Substitute in the latest insn for the regs set by the earlier ones. */
2223 maxreg
= max_reg_num ();
2228 /* Many machines that don't use CC0 have insns that can both perform an
2229 arithmetic operation and set the condition code. These operations will
2230 be represented as a PARALLEL with the first element of the vector
2231 being a COMPARE of an arithmetic operation with the constant zero.
2232 The second element of the vector will set some pseudo to the result
2233 of the same arithmetic operation. If we simplify the COMPARE, we won't
2234 match such a pattern and so will generate an extra insn. Here we test
2235 for this case, where both the comparison and the operation result are
2236 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2237 I2SRC. Later we will make the PARALLEL that contains I2. */
2239 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2240 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2241 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2242 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2244 #ifdef SELECT_CC_MODE
2246 enum machine_mode compare_mode
;
2249 newpat
= PATTERN (i3
);
2250 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2254 #ifdef SELECT_CC_MODE
2255 /* See if a COMPARE with the operand we substituted in should be done
2256 with the mode that is currently being used. If not, do the same
2257 processing we do in `subst' for a SET; namely, if the destination
2258 is used only once, try to replace it with a register of the proper
2259 mode and also replace the COMPARE. */
2260 if (undobuf
.other_insn
== 0
2261 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2262 &undobuf
.other_insn
))
2263 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2265 != GET_MODE (SET_DEST (newpat
))))
2267 if (can_change_dest_mode(SET_DEST (newpat
), added_sets_2
,
2270 unsigned int regno
= REGNO (SET_DEST (newpat
));
2273 if (regno
< FIRST_PSEUDO_REGISTER
)
2274 new_dest
= gen_rtx_REG (compare_mode
, regno
);
2277 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2278 new_dest
= regno_reg_rtx
[regno
];
2281 SUBST (SET_DEST (newpat
), new_dest
);
2282 SUBST (XEXP (*cc_use
, 0), new_dest
);
2283 SUBST (SET_SRC (newpat
),
2284 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2287 undobuf
.other_insn
= 0;
2294 /* It is possible that the source of I2 or I1 may be performing
2295 an unneeded operation, such as a ZERO_EXTEND of something
2296 that is known to have the high part zero. Handle that case
2297 by letting subst look at the innermost one of them.
2299 Another way to do this would be to have a function that tries
2300 to simplify a single insn instead of merging two or more
2301 insns. We don't do this because of the potential of infinite
2302 loops and because of the potential extra memory required.
2303 However, doing it the way we are is a bit of a kludge and
2304 doesn't catch all cases.
2306 But only do this if -fexpensive-optimizations since it slows
2307 things down and doesn't usually win.
2309 This is not done in the COMPARE case above because the
2310 unmodified I2PAT is used in the PARALLEL and so a pattern
2311 with a modified I2SRC would not match. */
2313 if (flag_expensive_optimizations
)
2315 /* Pass pc_rtx so no substitutions are done, just
2319 subst_low_cuid
= INSN_CUID (i1
);
2320 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2324 subst_low_cuid
= INSN_CUID (i2
);
2325 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2329 n_occurrences
= 0; /* `subst' counts here */
2331 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2332 need to make a unique copy of I2SRC each time we substitute it
2333 to avoid self-referential rtl. */
2335 subst_low_cuid
= INSN_CUID (i2
);
2336 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2337 ! i1_feeds_i3
&& i1dest_in_i1src
);
2340 /* Record whether i2's body now appears within i3's body. */
2341 i2_is_used
= n_occurrences
;
2344 /* If we already got a failure, don't try to do more. Otherwise,
2345 try to substitute in I1 if we have it. */
2347 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2349 /* Before we can do this substitution, we must redo the test done
2350 above (see detailed comments there) that ensures that I1DEST
2351 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2353 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2361 subst_low_cuid
= INSN_CUID (i1
);
2362 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2366 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2367 to count all the ways that I2SRC and I1SRC can be used. */
2368 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2369 && i2_is_used
+ added_sets_2
> 1)
2370 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2371 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2373 /* Fail if we tried to make a new register. */
2374 || max_reg_num () != maxreg
2375 /* Fail if we couldn't do something and have a CLOBBER. */
2376 || GET_CODE (newpat
) == CLOBBER
2377 /* Fail if this new pattern is a MULT and we didn't have one before
2378 at the outer level. */
2379 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2386 /* If the actions of the earlier insns must be kept
2387 in addition to substituting them into the latest one,
2388 we must make a new PARALLEL for the latest insn
2389 to hold additional the SETs. */
2391 if (added_sets_1
|| added_sets_2
)
2395 if (GET_CODE (newpat
) == PARALLEL
)
2397 rtvec old
= XVEC (newpat
, 0);
2398 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2399 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2400 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2401 sizeof (old
->elem
[0]) * old
->num_elem
);
2406 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2407 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2408 XVECEXP (newpat
, 0, 0) = old
;
2412 XVECEXP (newpat
, 0, --total_sets
)
2413 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2414 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2418 /* If there is no I1, use I2's body as is. We used to also not do
2419 the subst call below if I2 was substituted into I3,
2420 but that could lose a simplification. */
2422 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2424 /* See comment where i2pat is assigned. */
2425 XVECEXP (newpat
, 0, --total_sets
)
2426 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2430 /* We come here when we are replacing a destination in I2 with the
2431 destination of I3. */
2432 validate_replacement
:
2434 /* Note which hard regs this insn has as inputs. */
2435 mark_used_regs_combine (newpat
);
2437 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2438 consider splitting this pattern, we might need these clobbers. */
2439 if (i1
&& GET_CODE (newpat
) == PARALLEL
2440 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2442 int len
= XVECLEN (newpat
, 0);
2444 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2445 for (i
= 0; i
< len
; i
++)
2446 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2449 /* Is the result of combination a valid instruction? */
2450 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2452 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2453 the second SET's destination is a register that is unused and isn't
2454 marked as an instruction that might trap in an EH region. In that case,
2455 we just need the first SET. This can occur when simplifying a divmod
2456 insn. We *must* test for this case here because the code below that
2457 splits two independent SETs doesn't handle this case correctly when it
2458 updates the register status.
2460 It's pointless doing this if we originally had two sets, one from
2461 i3, and one from i2. Combining then splitting the parallel results
2462 in the original i2 again plus an invalid insn (which we delete).
2463 The net effect is only to move instructions around, which makes
2464 debug info less accurate.
2466 Also check the case where the first SET's destination is unused.
2467 That would not cause incorrect code, but does cause an unneeded
2470 if (insn_code_number
< 0
2471 && !(added_sets_2
&& i1
== 0)
2472 && GET_CODE (newpat
) == PARALLEL
2473 && XVECLEN (newpat
, 0) == 2
2474 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2475 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2476 && asm_noperands (newpat
) < 0)
2478 rtx set0
= XVECEXP (newpat
, 0, 0);
2479 rtx set1
= XVECEXP (newpat
, 0, 1);
2482 if (((REG_P (SET_DEST (set1
))
2483 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2484 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2485 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2486 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2487 || INTVAL (XEXP (note
, 0)) <= 0)
2488 && ! side_effects_p (SET_SRC (set1
)))
2491 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2494 else if (((REG_P (SET_DEST (set0
))
2495 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2496 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2497 && find_reg_note (i3
, REG_UNUSED
,
2498 SUBREG_REG (SET_DEST (set0
)))))
2499 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2500 || INTVAL (XEXP (note
, 0)) <= 0)
2501 && ! side_effects_p (SET_SRC (set0
)))
2504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2506 if (insn_code_number
>= 0)
2508 /* If we will be able to accept this, we have made a
2509 change to the destination of I3. This requires us to
2510 do a few adjustments. */
2512 PATTERN (i3
) = newpat
;
2513 adjust_for_new_dest (i3
);
2518 /* If we were combining three insns and the result is a simple SET
2519 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2520 insns. There are two ways to do this. It can be split using a
2521 machine-specific method (like when you have an addition of a large
2522 constant) or by combine in the function find_split_point. */
2524 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2525 && asm_noperands (newpat
) < 0)
2527 rtx m_split
, *split
;
2529 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2530 use I2DEST as a scratch register will help. In the latter case,
2531 convert I2DEST to the mode of the source of NEWPAT if we can. */
2533 m_split
= split_insns (newpat
, i3
);
2535 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2536 inputs of NEWPAT. */
2538 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2539 possible to try that as a scratch reg. This would require adding
2540 more code to make it work though. */
2542 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
2544 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
2546 /* First try to split using the original register as a
2547 scratch register. */
2548 m_split
= split_insns (gen_rtx_PARALLEL
2550 gen_rtvec (2, newpat
,
2551 gen_rtx_CLOBBER (VOIDmode
,
2555 /* If that didn't work, try changing the mode of I2DEST if
2558 && new_mode
!= GET_MODE (i2dest
)
2559 && new_mode
!= VOIDmode
2560 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
2562 enum machine_mode old_mode
= GET_MODE (i2dest
);
2565 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
2566 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
2569 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
2570 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
2573 m_split
= split_insns (gen_rtx_PARALLEL
2575 gen_rtvec (2, newpat
,
2576 gen_rtx_CLOBBER (VOIDmode
,
2581 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2585 PUT_MODE (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
2586 buf
= undobuf
.undos
;
2587 undobuf
.undos
= buf
->next
;
2588 buf
->next
= undobuf
.frees
;
2589 undobuf
.frees
= buf
;
2594 /* If recog_for_combine has discarded clobbers, try to use them
2595 again for the split. */
2596 if (m_split
== 0 && newpat_vec_with_clobbers
)
2598 = split_insns (gen_rtx_PARALLEL (VOIDmode
,
2599 newpat_vec_with_clobbers
), i3
);
2601 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2603 m_split
= PATTERN (m_split
);
2604 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2605 if (insn_code_number
>= 0)
2608 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2609 && (next_real_insn (i2
) == i3
2610 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2613 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2614 newi2pat
= PATTERN (m_split
);
2616 i3set
= single_set (NEXT_INSN (m_split
));
2617 i2set
= single_set (m_split
);
2619 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2621 /* If I2 or I3 has multiple SETs, we won't know how to track
2622 register status, so don't use these insns. If I2's destination
2623 is used between I2 and I3, we also can't use these insns. */
2625 if (i2_code_number
>= 0 && i2set
&& i3set
2626 && (next_real_insn (i2
) == i3
2627 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2628 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2630 if (insn_code_number
>= 0)
2633 /* It is possible that both insns now set the destination of I3.
2634 If so, we must show an extra use of it. */
2636 if (insn_code_number
>= 0)
2638 rtx new_i3_dest
= SET_DEST (i3set
);
2639 rtx new_i2_dest
= SET_DEST (i2set
);
2641 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2642 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2643 || GET_CODE (new_i3_dest
) == SUBREG
)
2644 new_i3_dest
= XEXP (new_i3_dest
, 0);
2646 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2647 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2648 || GET_CODE (new_i2_dest
) == SUBREG
)
2649 new_i2_dest
= XEXP (new_i2_dest
, 0);
2651 if (REG_P (new_i3_dest
)
2652 && REG_P (new_i2_dest
)
2653 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2654 REG_N_SETS (REGNO (new_i2_dest
))++;
2658 /* If we can split it and use I2DEST, go ahead and see if that
2659 helps things be recognized. Verify that none of the registers
2660 are set between I2 and I3. */
2661 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2665 /* We need I2DEST in the proper mode. If it is a hard register
2666 or the only use of a pseudo, we can change its mode.
2667 Make sure we don't change a hard register to have a mode that
2668 isn't valid for it, or change the number of registers. */
2669 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2670 || GET_MODE (*split
) == VOIDmode
2671 || can_change_dest_mode (i2dest
, added_sets_2
,
2673 && (next_real_insn (i2
) == i3
2674 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2675 /* We can't overwrite I2DEST if its value is still used by
2677 && ! reg_referenced_p (i2dest
, newpat
))
2679 rtx newdest
= i2dest
;
2680 enum rtx_code split_code
= GET_CODE (*split
);
2681 enum machine_mode split_mode
= GET_MODE (*split
);
2682 bool subst_done
= false;
2683 newi2pat
= NULL_RTX
;
2685 /* Get NEWDEST as a register in the proper mode. We have already
2686 validated that we can do this. */
2687 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2689 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
2690 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2693 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
2694 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
2698 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2699 an ASHIFT. This can occur if it was inside a PLUS and hence
2700 appeared to be a memory address. This is a kludge. */
2701 if (split_code
== MULT
2702 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2703 && INTVAL (XEXP (*split
, 1)) > 0
2704 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2706 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2707 XEXP (*split
, 0), GEN_INT (i
)));
2708 /* Update split_code because we may not have a multiply
2710 split_code
= GET_CODE (*split
);
2713 #ifdef INSN_SCHEDULING
2714 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2715 be written as a ZERO_EXTEND. */
2716 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2718 #ifdef LOAD_EXTEND_OP
2719 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2720 what it really is. */
2721 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2723 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2724 SUBREG_REG (*split
)));
2727 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2728 SUBREG_REG (*split
)));
2732 /* Attempt to split binary operators using arithmetic identities. */
2733 if (BINARY_P (SET_SRC (newpat
))
2734 && split_mode
== GET_MODE (SET_SRC (newpat
))
2735 && ! side_effects_p (SET_SRC (newpat
)))
2737 rtx setsrc
= SET_SRC (newpat
);
2738 enum machine_mode mode
= GET_MODE (setsrc
);
2739 enum rtx_code code
= GET_CODE (setsrc
);
2740 rtx src_op0
= XEXP (setsrc
, 0);
2741 rtx src_op1
= XEXP (setsrc
, 1);
2743 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2744 if (rtx_equal_p (src_op0
, src_op1
))
2746 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
2747 SUBST (XEXP (setsrc
, 0), newdest
);
2748 SUBST (XEXP (setsrc
, 1), newdest
);
2751 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2752 else if ((code
== PLUS
|| code
== MULT
)
2753 && GET_CODE (src_op0
) == code
2754 && GET_CODE (XEXP (src_op0
, 0)) == code
2755 && (INTEGRAL_MODE_P (mode
)
2756 || (FLOAT_MODE_P (mode
)
2757 && flag_unsafe_math_optimizations
)))
2759 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
2760 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
2761 rtx r
= XEXP (src_op0
, 1);
2764 /* Split both "((X op Y) op X) op Y" and
2765 "((X op Y) op Y) op X" as "T op T" where T is
2767 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
2768 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
2770 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
2772 SUBST (XEXP (setsrc
, 0), newdest
);
2773 SUBST (XEXP (setsrc
, 1), newdest
);
2776 /* Split "((X op X) op Y) op Y)" as "T op T" where
2778 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
2780 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
2781 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
2782 SUBST (XEXP (setsrc
, 0), newdest
);
2783 SUBST (XEXP (setsrc
, 1), newdest
);
2791 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2792 SUBST (*split
, newdest
);
2795 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2797 /* recog_for_combine might have added CLOBBERs to newi2pat.
2798 Make sure NEWPAT does not depend on the clobbered regs. */
2799 if (GET_CODE (newi2pat
) == PARALLEL
)
2800 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2801 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2803 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2804 if (reg_overlap_mentioned_p (reg
, newpat
))
2811 /* If the split point was a MULT and we didn't have one before,
2812 don't use one now. */
2813 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2814 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2818 /* Check for a case where we loaded from memory in a narrow mode and
2819 then sign extended it, but we need both registers. In that case,
2820 we have a PARALLEL with both loads from the same memory location.
2821 We can split this into a load from memory followed by a register-register
2822 copy. This saves at least one insn, more if register allocation can
2825 We cannot do this if the destination of the first assignment is a
2826 condition code register or cc0. We eliminate this case by making sure
2827 the SET_DEST and SET_SRC have the same mode.
2829 We cannot do this if the destination of the second assignment is
2830 a register that we have already assumed is zero-extended. Similarly
2831 for a SUBREG of such a register. */
2833 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2834 && GET_CODE (newpat
) == PARALLEL
2835 && XVECLEN (newpat
, 0) == 2
2836 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2837 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2838 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2839 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2840 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2841 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2842 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2843 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2845 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2846 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2847 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2849 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2850 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2851 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2852 && (reg_stat
[REGNO (temp
)].nonzero_bits
2853 != GET_MODE_MASK (word_mode
))))
2854 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2855 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2857 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2858 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2859 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2860 && (reg_stat
[REGNO (temp
)].nonzero_bits
2861 != GET_MODE_MASK (word_mode
)))))
2862 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2863 SET_SRC (XVECEXP (newpat
, 0, 1)))
2864 && ! find_reg_note (i3
, REG_UNUSED
,
2865 SET_DEST (XVECEXP (newpat
, 0, 0))))
2869 newi2pat
= XVECEXP (newpat
, 0, 0);
2870 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2871 newpat
= XVECEXP (newpat
, 0, 1);
2872 SUBST (SET_SRC (newpat
),
2873 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2874 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2876 if (i2_code_number
>= 0)
2877 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2879 if (insn_code_number
>= 0)
2883 /* Similarly, check for a case where we have a PARALLEL of two independent
2884 SETs but we started with three insns. In this case, we can do the sets
2885 as two separate insns. This case occurs when some SET allows two
2886 other insns to combine, but the destination of that SET is still live. */
2888 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2889 && GET_CODE (newpat
) == PARALLEL
2890 && XVECLEN (newpat
, 0) == 2
2891 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2892 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2893 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2894 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2895 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2896 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2897 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2899 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2900 XVECEXP (newpat
, 0, 0))
2901 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2902 XVECEXP (newpat
, 0, 1))
2903 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2904 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2906 /* Normally, it doesn't matter which of the two is done first,
2907 but it does if one references cc0. In that case, it has to
2910 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2912 newi2pat
= XVECEXP (newpat
, 0, 0);
2913 newpat
= XVECEXP (newpat
, 0, 1);
2918 newi2pat
= XVECEXP (newpat
, 0, 1);
2919 newpat
= XVECEXP (newpat
, 0, 0);
2922 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2924 if (i2_code_number
>= 0)
2925 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2928 /* If it still isn't recognized, fail and change things back the way they
2930 if ((insn_code_number
< 0
2931 /* Is the result a reasonable ASM_OPERANDS? */
2932 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2938 /* If we had to change another insn, make sure it is valid also. */
2939 if (undobuf
.other_insn
)
2941 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2942 rtx new_other_notes
;
2945 CLEAR_HARD_REG_SET (newpat_used_regs
);
2947 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2950 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2956 PATTERN (undobuf
.other_insn
) = other_pat
;
2958 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2959 are still valid. Then add any non-duplicate notes added by
2960 recog_for_combine. */
2961 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2963 next
= XEXP (note
, 1);
2965 if (REG_NOTE_KIND (note
) == REG_UNUSED
2966 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2968 if (REG_P (XEXP (note
, 0)))
2969 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2971 remove_note (undobuf
.other_insn
, note
);
2975 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2976 if (REG_P (XEXP (note
, 0)))
2977 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2979 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2980 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2983 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2984 they are adjacent to each other or not. */
2986 rtx p
= prev_nonnote_insn (i3
);
2987 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2988 && sets_cc0_p (newi2pat
))
2996 /* Only allow this combination if insn_rtx_costs reports that the
2997 replacement instructions are cheaper than the originals. */
2998 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
3004 /* We now know that we can do this combination. Merge the insns and
3005 update the status of registers and LOG_LINKS. */
3013 /* I3 now uses what used to be its destination and which is now
3014 I2's destination. This requires us to do a few adjustments. */
3015 PATTERN (i3
) = newpat
;
3016 adjust_for_new_dest (i3
);
3018 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3021 However, some later insn might be using I2's dest and have
3022 a LOG_LINK pointing at I3. We must remove this link.
3023 The simplest way to remove the link is to point it at I1,
3024 which we know will be a NOTE. */
3026 /* newi2pat is usually a SET here; however, recog_for_combine might
3027 have added some clobbers. */
3028 if (GET_CODE (newi2pat
) == PARALLEL
)
3029 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3031 ni2dest
= SET_DEST (newi2pat
);
3033 for (insn
= NEXT_INSN (i3
);
3034 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3035 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3036 insn
= NEXT_INSN (insn
))
3038 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3040 for (link
= LOG_LINKS (insn
); link
;
3041 link
= XEXP (link
, 1))
3042 if (XEXP (link
, 0) == i3
)
3043 XEXP (link
, 0) = i1
;
3051 rtx i3notes
, i2notes
, i1notes
= 0;
3052 rtx i3links
, i2links
, i1links
= 0;
3055 /* Compute which registers we expect to eliminate. newi2pat may be setting
3056 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3057 same as i3dest, in which case newi2pat may be setting i1dest. */
3058 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3059 || i2dest_in_i2src
|| i2dest_in_i1src
3062 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
3063 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3067 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3069 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3070 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3072 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3074 /* Ensure that we do not have something that should not be shared but
3075 occurs multiple times in the new insns. Check this by first
3076 resetting all the `used' flags and then copying anything is shared. */
3078 reset_used_flags (i3notes
);
3079 reset_used_flags (i2notes
);
3080 reset_used_flags (i1notes
);
3081 reset_used_flags (newpat
);
3082 reset_used_flags (newi2pat
);
3083 if (undobuf
.other_insn
)
3084 reset_used_flags (PATTERN (undobuf
.other_insn
));
3086 i3notes
= copy_rtx_if_shared (i3notes
);
3087 i2notes
= copy_rtx_if_shared (i2notes
);
3088 i1notes
= copy_rtx_if_shared (i1notes
);
3089 newpat
= copy_rtx_if_shared (newpat
);
3090 newi2pat
= copy_rtx_if_shared (newi2pat
);
3091 if (undobuf
.other_insn
)
3092 reset_used_flags (PATTERN (undobuf
.other_insn
));
3094 INSN_CODE (i3
) = insn_code_number
;
3095 PATTERN (i3
) = newpat
;
3097 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3099 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3101 reset_used_flags (call_usage
);
3102 call_usage
= copy_rtx (call_usage
);
3105 replace_rtx (call_usage
, i2dest
, i2src
);
3108 replace_rtx (call_usage
, i1dest
, i1src
);
3110 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
3113 if (undobuf
.other_insn
)
3114 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
3116 /* We had one special case above where I2 had more than one set and
3117 we replaced a destination of one of those sets with the destination
3118 of I3. In that case, we have to update LOG_LINKS of insns later
3119 in this basic block. Note that this (expensive) case is rare.
3121 Also, in this case, we must pretend that all REG_NOTEs for I2
3122 actually came from I3, so that REG_UNUSED notes from I2 will be
3123 properly handled. */
3125 if (i3_subst_into_i2
)
3127 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
3128 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
3129 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
3130 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
3131 && ! find_reg_note (i2
, REG_UNUSED
,
3132 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
3133 for (temp
= NEXT_INSN (i2
);
3134 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3135 || BB_HEAD (this_basic_block
) != temp
);
3136 temp
= NEXT_INSN (temp
))
3137 if (temp
!= i3
&& INSN_P (temp
))
3138 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
3139 if (XEXP (link
, 0) == i2
)
3140 XEXP (link
, 0) = i3
;
3145 while (XEXP (link
, 1))
3146 link
= XEXP (link
, 1);
3147 XEXP (link
, 1) = i2notes
;
3161 INSN_CODE (i2
) = i2_code_number
;
3162 PATTERN (i2
) = newi2pat
;
3165 SET_INSN_DELETED (i2
);
3171 SET_INSN_DELETED (i1
);
3174 /* Get death notes for everything that is now used in either I3 or
3175 I2 and used to die in a previous insn. If we built two new
3176 patterns, move from I1 to I2 then I2 to I3 so that we get the
3177 proper movement on registers that I2 modifies. */
3181 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
3182 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
3185 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
3188 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3190 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
3193 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
3196 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
3199 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3202 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3203 know these are REG_UNUSED and want them to go to the desired insn,
3204 so we always pass it as i3. We have not counted the notes in
3205 reg_n_deaths yet, so we need to do so now. */
3207 if (newi2pat
&& new_i2_notes
)
3209 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
3210 if (REG_P (XEXP (temp
, 0)))
3211 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
3213 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3218 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
3219 if (REG_P (XEXP (temp
, 0)))
3220 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
3222 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3225 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3226 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3227 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3228 in that case, it might delete I2. Similarly for I2 and I1.
3229 Show an additional death due to the REG_DEAD note we make here. If
3230 we discard it in distribute_notes, we will decrement it again. */
3234 if (REG_P (i3dest_killed
))
3235 REG_N_DEATHS (REGNO (i3dest_killed
))++;
3237 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
3238 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3240 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
3242 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
3244 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3248 if (i2dest_in_i2src
)
3251 REG_N_DEATHS (REGNO (i2dest
))++;
3253 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3254 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3255 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3257 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
3258 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3259 NULL_RTX
, NULL_RTX
);
3262 if (i1dest_in_i1src
)
3265 REG_N_DEATHS (REGNO (i1dest
))++;
3267 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3268 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3269 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
3271 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3272 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
3273 NULL_RTX
, NULL_RTX
);
3276 distribute_links (i3links
);
3277 distribute_links (i2links
);
3278 distribute_links (i1links
);
3283 rtx i2_insn
= 0, i2_val
= 0, set
;
3285 /* The insn that used to set this register doesn't exist, and
3286 this life of the register may not exist either. See if one of
3287 I3's links points to an insn that sets I2DEST. If it does,
3288 that is now the last known value for I2DEST. If we don't update
3289 this and I2 set the register to a value that depended on its old
3290 contents, we will get confused. If this insn is used, thing
3291 will be set correctly in combine_instructions. */
3293 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3294 if ((set
= single_set (XEXP (link
, 0))) != 0
3295 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3296 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3298 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3300 /* If the reg formerly set in I2 died only once and that was in I3,
3301 zero its use count so it won't make `reload' do any work. */
3303 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3304 && ! i2dest_in_i2src
)
3306 regno
= REGNO (i2dest
);
3307 REG_N_SETS (regno
)--;
3311 if (i1
&& REG_P (i1dest
))
3314 rtx i1_insn
= 0, i1_val
= 0, set
;
3316 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3317 if ((set
= single_set (XEXP (link
, 0))) != 0
3318 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3319 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3321 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3323 regno
= REGNO (i1dest
);
3324 if (! added_sets_1
&& ! i1dest_in_i1src
)
3325 REG_N_SETS (regno
)--;
3328 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3329 been made to this insn. The order of
3330 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3331 can affect nonzero_bits of newpat */
3333 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3334 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3336 /* Set new_direct_jump_p if a new return or simple jump instruction
3339 If I3 is now an unconditional jump, ensure that it has a
3340 BARRIER following it since it may have initially been a
3341 conditional jump. It may also be the last nonnote insn. */
3343 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3345 *new_direct_jump_p
= 1;
3346 mark_jump_label (PATTERN (i3
), i3
, 0);
3348 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
3349 || !BARRIER_P (temp
))
3350 emit_barrier_after (i3
);
3353 if (undobuf
.other_insn
!= NULL_RTX
3354 && (returnjump_p (undobuf
.other_insn
)
3355 || any_uncondjump_p (undobuf
.other_insn
)))
3357 *new_direct_jump_p
= 1;
3359 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3360 || !BARRIER_P (temp
))
3361 emit_barrier_after (undobuf
.other_insn
);
3364 /* An NOOP jump does not need barrier, but it does need cleaning up
3366 if (GET_CODE (newpat
) == SET
3367 && SET_SRC (newpat
) == pc_rtx
3368 && SET_DEST (newpat
) == pc_rtx
)
3369 *new_direct_jump_p
= 1;
3372 combine_successes
++;
3375 if (added_links_insn
3376 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
3377 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
3378 return added_links_insn
;
3380 return newi2pat
? i2
: i3
;
3383 /* Undo all the modifications recorded in undobuf. */
3388 struct undo
*undo
, *next
;
3390 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3396 *undo
->where
.r
= undo
->old_contents
.r
;
3399 *undo
->where
.i
= undo
->old_contents
.i
;
3402 PUT_MODE (*undo
->where
.r
, undo
->old_contents
.m
);
3408 undo
->next
= undobuf
.frees
;
3409 undobuf
.frees
= undo
;
3415 /* We've committed to accepting the changes we made. Move all
3416 of the undos to the free list. */
3421 struct undo
*undo
, *next
;
3423 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3426 undo
->next
= undobuf
.frees
;
3427 undobuf
.frees
= undo
;
3433 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3434 where we have an arithmetic expression and return that point. LOC will
3437 try_combine will call this function to see if an insn can be split into
3441 find_split_point (rtx
*loc
, rtx insn
)
3444 enum rtx_code code
= GET_CODE (x
);
3446 unsigned HOST_WIDE_INT len
= 0;
3447 HOST_WIDE_INT pos
= 0;
3449 rtx inner
= NULL_RTX
;
3451 /* First special-case some codes. */
3455 #ifdef INSN_SCHEDULING
3456 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3458 if (MEM_P (SUBREG_REG (x
)))
3461 return find_split_point (&SUBREG_REG (x
), insn
);
3465 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3466 using LO_SUM and HIGH. */
3467 if (GET_CODE (XEXP (x
, 0)) == CONST
3468 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3471 gen_rtx_LO_SUM (Pmode
,
3472 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3474 return &XEXP (XEXP (x
, 0), 0);
3478 /* If we have a PLUS whose second operand is a constant and the
3479 address is not valid, perhaps will can split it up using
3480 the machine-specific way to split large constants. We use
3481 the first pseudo-reg (one of the virtual regs) as a placeholder;
3482 it will not remain in the result. */
3483 if (GET_CODE (XEXP (x
, 0)) == PLUS
3484 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3485 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3487 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3488 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3491 /* This should have produced two insns, each of which sets our
3492 placeholder. If the source of the second is a valid address,
3493 we can make put both sources together and make a split point
3497 && NEXT_INSN (seq
) != NULL_RTX
3498 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3499 && NONJUMP_INSN_P (seq
)
3500 && GET_CODE (PATTERN (seq
)) == SET
3501 && SET_DEST (PATTERN (seq
)) == reg
3502 && ! reg_mentioned_p (reg
,
3503 SET_SRC (PATTERN (seq
)))
3504 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3505 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3506 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3507 && memory_address_p (GET_MODE (x
),
3508 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3510 rtx src1
= SET_SRC (PATTERN (seq
));
3511 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3513 /* Replace the placeholder in SRC2 with SRC1. If we can
3514 find where in SRC2 it was placed, that can become our
3515 split point and we can replace this address with SRC2.
3516 Just try two obvious places. */
3518 src2
= replace_rtx (src2
, reg
, src1
);
3520 if (XEXP (src2
, 0) == src1
)
3521 split
= &XEXP (src2
, 0);
3522 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3523 && XEXP (XEXP (src2
, 0), 0) == src1
)
3524 split
= &XEXP (XEXP (src2
, 0), 0);
3528 SUBST (XEXP (x
, 0), src2
);
3533 /* If that didn't work, perhaps the first operand is complex and
3534 needs to be computed separately, so make a split point there.
3535 This will occur on machines that just support REG + CONST
3536 and have a constant moved through some previous computation. */
3538 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3539 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3540 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3541 return &XEXP (XEXP (x
, 0), 0);
3547 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3548 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3549 we need to put the operand into a register. So split at that
3552 if (SET_DEST (x
) == cc0_rtx
3553 && GET_CODE (SET_SRC (x
)) != COMPARE
3554 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3555 && !OBJECT_P (SET_SRC (x
))
3556 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3557 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3558 return &SET_SRC (x
);
3561 /* See if we can split SET_SRC as it stands. */
3562 split
= find_split_point (&SET_SRC (x
), insn
);
3563 if (split
&& split
!= &SET_SRC (x
))
3566 /* See if we can split SET_DEST as it stands. */
3567 split
= find_split_point (&SET_DEST (x
), insn
);
3568 if (split
&& split
!= &SET_DEST (x
))
3571 /* See if this is a bitfield assignment with everything constant. If
3572 so, this is an IOR of an AND, so split it into that. */
3573 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3574 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3575 <= HOST_BITS_PER_WIDE_INT
)
3576 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3577 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3578 && GET_CODE (SET_SRC (x
)) == CONST_INT
3579 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3580 + INTVAL (XEXP (SET_DEST (x
), 2)))
3581 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3582 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3584 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3585 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3586 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3587 rtx dest
= XEXP (SET_DEST (x
), 0);
3588 enum machine_mode mode
= GET_MODE (dest
);
3589 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3592 if (BITS_BIG_ENDIAN
)
3593 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3595 or_mask
= gen_int_mode (src
<< pos
, mode
);
3598 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
3601 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3603 simplify_gen_binary (IOR
, mode
,
3604 simplify_gen_binary (AND
, mode
,
3609 SUBST (SET_DEST (x
), dest
);
3611 split
= find_split_point (&SET_SRC (x
), insn
);
3612 if (split
&& split
!= &SET_SRC (x
))
3616 /* Otherwise, see if this is an operation that we can split into two.
3617 If so, try to split that. */
3618 code
= GET_CODE (SET_SRC (x
));
3623 /* If we are AND'ing with a large constant that is only a single
3624 bit and the result is only being used in a context where we
3625 need to know if it is zero or nonzero, replace it with a bit
3626 extraction. This will avoid the large constant, which might
3627 have taken more than one insn to make. If the constant were
3628 not a valid argument to the AND but took only one insn to make,
3629 this is no worse, but if it took more than one insn, it will
3632 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3633 && REG_P (XEXP (SET_SRC (x
), 0))
3634 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3635 && REG_P (SET_DEST (x
))
3636 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3637 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3638 && XEXP (*split
, 0) == SET_DEST (x
)
3639 && XEXP (*split
, 1) == const0_rtx
)
3641 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3642 XEXP (SET_SRC (x
), 0),
3643 pos
, NULL_RTX
, 1, 1, 0, 0);
3644 if (extraction
!= 0)
3646 SUBST (SET_SRC (x
), extraction
);
3647 return find_split_point (loc
, insn
);
3653 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3654 is known to be on, this can be converted into a NEG of a shift. */
3655 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3656 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3657 && 1 <= (pos
= exact_log2
3658 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3659 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3661 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3665 gen_rtx_LSHIFTRT (mode
,
3666 XEXP (SET_SRC (x
), 0),
3669 split
= find_split_point (&SET_SRC (x
), insn
);
3670 if (split
&& split
!= &SET_SRC (x
))
3676 inner
= XEXP (SET_SRC (x
), 0);
3678 /* We can't optimize if either mode is a partial integer
3679 mode as we don't know how many bits are significant
3681 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3682 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3686 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3692 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3693 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3695 inner
= XEXP (SET_SRC (x
), 0);
3696 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3697 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3699 if (BITS_BIG_ENDIAN
)
3700 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3701 unsignedp
= (code
== ZERO_EXTRACT
);
3709 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3711 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3713 /* For unsigned, we have a choice of a shift followed by an
3714 AND or two shifts. Use two shifts for field sizes where the
3715 constant might be too large. We assume here that we can
3716 always at least get 8-bit constants in an AND insn, which is
3717 true for every current RISC. */
3719 if (unsignedp
&& len
<= 8)
3724 (mode
, gen_lowpart (mode
, inner
),
3726 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3728 split
= find_split_point (&SET_SRC (x
), insn
);
3729 if (split
&& split
!= &SET_SRC (x
))
3736 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3737 gen_rtx_ASHIFT (mode
,
3738 gen_lowpart (mode
, inner
),
3739 GEN_INT (GET_MODE_BITSIZE (mode
)
3741 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3743 split
= find_split_point (&SET_SRC (x
), insn
);
3744 if (split
&& split
!= &SET_SRC (x
))
3749 /* See if this is a simple operation with a constant as the second
3750 operand. It might be that this constant is out of range and hence
3751 could be used as a split point. */
3752 if (BINARY_P (SET_SRC (x
))
3753 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3754 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3755 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3756 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3757 return &XEXP (SET_SRC (x
), 1);
3759 /* Finally, see if this is a simple operation with its first operand
3760 not in a register. The operation might require this operand in a
3761 register, so return it as a split point. We can always do this
3762 because if the first operand were another operation, we would have
3763 already found it as a split point. */
3764 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3765 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3766 return &XEXP (SET_SRC (x
), 0);
3772 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3773 it is better to write this as (not (ior A B)) so we can split it.
3774 Similarly for IOR. */
3775 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3778 gen_rtx_NOT (GET_MODE (x
),
3779 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3781 XEXP (XEXP (x
, 0), 0),
3782 XEXP (XEXP (x
, 1), 0))));
3783 return find_split_point (loc
, insn
);
3786 /* Many RISC machines have a large set of logical insns. If the
3787 second operand is a NOT, put it first so we will try to split the
3788 other operand first. */
3789 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3791 rtx tem
= XEXP (x
, 0);
3792 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3793 SUBST (XEXP (x
, 1), tem
);
3801 /* Otherwise, select our actions depending on our rtx class. */
3802 switch (GET_RTX_CLASS (code
))
3804 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3806 split
= find_split_point (&XEXP (x
, 2), insn
);
3809 /* ... fall through ... */
3811 case RTX_COMM_ARITH
:
3813 case RTX_COMM_COMPARE
:
3814 split
= find_split_point (&XEXP (x
, 1), insn
);
3817 /* ... fall through ... */
3819 /* Some machines have (and (shift ...) ...) insns. If X is not
3820 an AND, but XEXP (X, 0) is, use it as our split point. */
3821 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3822 return &XEXP (x
, 0);
3824 split
= find_split_point (&XEXP (x
, 0), insn
);
3830 /* Otherwise, we don't have a split point. */
3835 /* Throughout X, replace FROM with TO, and return the result.
3836 The result is TO if X is FROM;
3837 otherwise the result is X, but its contents may have been modified.
3838 If they were modified, a record was made in undobuf so that
3839 undo_all will (among other things) return X to its original state.
3841 If the number of changes necessary is too much to record to undo,
3842 the excess changes are not made, so the result is invalid.
3843 The changes already made can still be undone.
3844 undobuf.num_undo is incremented for such changes, so by testing that
3845 the caller can tell whether the result is valid.
3847 `n_occurrences' is incremented each time FROM is replaced.
3849 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3851 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3852 by copying if `n_occurrences' is nonzero. */
3855 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3857 enum rtx_code code
= GET_CODE (x
);
3858 enum machine_mode op0_mode
= VOIDmode
;
3863 /* Two expressions are equal if they are identical copies of a shared
3864 RTX or if they are both registers with the same register number
3867 #define COMBINE_RTX_EQUAL_P(X,Y) \
3869 || (REG_P (X) && REG_P (Y) \
3870 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3872 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3875 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3878 /* If X and FROM are the same register but different modes, they will
3879 not have been seen as equal above. However, flow.c will make a
3880 LOG_LINKS entry for that case. If we do nothing, we will try to
3881 rerecognize our original insn and, when it succeeds, we will
3882 delete the feeding insn, which is incorrect.
3884 So force this insn not to match in this (rare) case. */
3885 if (! in_dest
&& code
== REG
&& REG_P (from
)
3886 && REGNO (x
) == REGNO (from
))
3887 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3889 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3890 of which may contain things that can be combined. */
3891 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3894 /* It is possible to have a subexpression appear twice in the insn.
3895 Suppose that FROM is a register that appears within TO.
3896 Then, after that subexpression has been scanned once by `subst',
3897 the second time it is scanned, TO may be found. If we were
3898 to scan TO here, we would find FROM within it and create a
3899 self-referent rtl structure which is completely wrong. */
3900 if (COMBINE_RTX_EQUAL_P (x
, to
))
3903 /* Parallel asm_operands need special attention because all of the
3904 inputs are shared across the arms. Furthermore, unsharing the
3905 rtl results in recognition failures. Failure to handle this case
3906 specially can result in circular rtl.
3908 Solve this by doing a normal pass across the first entry of the
3909 parallel, and only processing the SET_DESTs of the subsequent
3912 if (code
== PARALLEL
3913 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3914 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3916 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3918 /* If this substitution failed, this whole thing fails. */
3919 if (GET_CODE (new) == CLOBBER
3920 && XEXP (new, 0) == const0_rtx
)
3923 SUBST (XVECEXP (x
, 0, 0), new);
3925 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3927 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3930 && GET_CODE (dest
) != CC0
3931 && GET_CODE (dest
) != PC
)
3933 new = subst (dest
, from
, to
, 0, unique_copy
);
3935 /* If this substitution failed, this whole thing fails. */
3936 if (GET_CODE (new) == CLOBBER
3937 && XEXP (new, 0) == const0_rtx
)
3940 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3946 len
= GET_RTX_LENGTH (code
);
3947 fmt
= GET_RTX_FORMAT (code
);
3949 /* We don't need to process a SET_DEST that is a register, CC0,
3950 or PC, so set up to skip this common case. All other cases
3951 where we want to suppress replacing something inside a
3952 SET_SRC are handled via the IN_DEST operand. */
3954 && (REG_P (SET_DEST (x
))
3955 || GET_CODE (SET_DEST (x
)) == CC0
3956 || GET_CODE (SET_DEST (x
)) == PC
))
3959 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3962 op0_mode
= GET_MODE (XEXP (x
, 0));
3964 for (i
= 0; i
< len
; i
++)
3969 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3971 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3973 new = (unique_copy
&& n_occurrences
3974 ? copy_rtx (to
) : to
);
3979 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3982 /* If this substitution failed, this whole thing
3984 if (GET_CODE (new) == CLOBBER
3985 && XEXP (new, 0) == const0_rtx
)
3989 SUBST (XVECEXP (x
, i
, j
), new);
3992 else if (fmt
[i
] == 'e')
3994 /* If this is a register being set, ignore it. */
3998 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
4000 || code
== STRICT_LOW_PART
))
4003 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
4005 /* In general, don't install a subreg involving two
4006 modes not tieable. It can worsen register
4007 allocation, and can even make invalid reload
4008 insns, since the reg inside may need to be copied
4009 from in the outside mode, and that may be invalid
4010 if it is an fp reg copied in integer mode.
4012 We allow two exceptions to this: It is valid if
4013 it is inside another SUBREG and the mode of that
4014 SUBREG and the mode of the inside of TO is
4015 tieable and it is valid if X is a SET that copies
4018 if (GET_CODE (to
) == SUBREG
4019 && ! MODES_TIEABLE_P (GET_MODE (to
),
4020 GET_MODE (SUBREG_REG (to
)))
4021 && ! (code
== SUBREG
4022 && MODES_TIEABLE_P (GET_MODE (x
),
4023 GET_MODE (SUBREG_REG (to
))))
4025 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
4028 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4030 #ifdef CANNOT_CHANGE_MODE_CLASS
4033 && REGNO (to
) < FIRST_PSEUDO_REGISTER
4034 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
4037 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
4040 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
4044 /* If we are in a SET_DEST, suppress most cases unless we
4045 have gone inside a MEM, in which case we want to
4046 simplify the address. We assume here that things that
4047 are actually part of the destination have their inner
4048 parts in the first expression. This is true for SUBREG,
4049 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4050 things aside from REG and MEM that should appear in a
4052 new = subst (XEXP (x
, i
), from
, to
,
4054 && (code
== SUBREG
|| code
== STRICT_LOW_PART
4055 || code
== ZERO_EXTRACT
))
4057 && i
== 0), unique_copy
);
4059 /* If we found that we will have to reject this combination,
4060 indicate that by returning the CLOBBER ourselves, rather than
4061 an expression containing it. This will speed things up as
4062 well as prevent accidents where two CLOBBERs are considered
4063 to be equal, thus producing an incorrect simplification. */
4065 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
4068 if (GET_CODE (x
) == SUBREG
4069 && (GET_CODE (new) == CONST_INT
4070 || GET_CODE (new) == CONST_DOUBLE
))
4072 enum machine_mode mode
= GET_MODE (x
);
4074 x
= simplify_subreg (GET_MODE (x
), new,
4075 GET_MODE (SUBREG_REG (x
)),
4078 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
4080 else if (GET_CODE (new) == CONST_INT
4081 && GET_CODE (x
) == ZERO_EXTEND
)
4083 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
4084 new, GET_MODE (XEXP (x
, 0)));
4088 SUBST (XEXP (x
, i
), new);
4093 /* Try to simplify X. If the simplification changed the code, it is likely
4094 that further simplification will help, so loop, but limit the number
4095 of repetitions that will be performed. */
4097 for (i
= 0; i
< 4; i
++)
4099 /* If X is sufficiently simple, don't bother trying to do anything
4101 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
4102 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
4104 if (GET_CODE (x
) == code
)
4107 code
= GET_CODE (x
);
4109 /* We no longer know the original mode of operand 0 since we
4110 have changed the form of X) */
4111 op0_mode
= VOIDmode
;
4117 /* Simplify X, a piece of RTL. We just operate on the expression at the
4118 outer level; call `subst' to simplify recursively. Return the new
4121 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4122 if we are inside a SET_DEST. */
4125 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
4127 enum rtx_code code
= GET_CODE (x
);
4128 enum machine_mode mode
= GET_MODE (x
);
4132 /* If this is a commutative operation, put a constant last and a complex
4133 expression first. We don't need to do this for comparisons here. */
4134 if (COMMUTATIVE_ARITH_P (x
)
4135 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
4138 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4139 SUBST (XEXP (x
, 1), temp
);
4142 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4143 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4144 things. Check for cases where both arms are testing the same
4147 Don't do anything if all operands are very simple. */
4150 && ((!OBJECT_P (XEXP (x
, 0))
4151 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4152 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
4153 || (!OBJECT_P (XEXP (x
, 1))
4154 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
4155 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
4157 && (!OBJECT_P (XEXP (x
, 0))
4158 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4159 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
4161 rtx cond
, true_rtx
, false_rtx
;
4163 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
4165 /* If everything is a comparison, what we have is highly unlikely
4166 to be simpler, so don't use it. */
4167 && ! (COMPARISON_P (x
)
4168 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
4170 rtx cop1
= const0_rtx
;
4171 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
4173 if (cond_code
== NE
&& COMPARISON_P (cond
))
4176 /* Simplify the alternative arms; this may collapse the true and
4177 false arms to store-flag values. Be careful to use copy_rtx
4178 here since true_rtx or false_rtx might share RTL with x as a
4179 result of the if_then_else_cond call above. */
4180 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4181 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
4183 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4184 is unlikely to be simpler. */
4185 if (general_operand (true_rtx
, VOIDmode
)
4186 && general_operand (false_rtx
, VOIDmode
))
4188 enum rtx_code reversed
;
4190 /* Restarting if we generate a store-flag expression will cause
4191 us to loop. Just drop through in this case. */
4193 /* If the result values are STORE_FLAG_VALUE and zero, we can
4194 just make the comparison operation. */
4195 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4196 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
4198 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4199 && ((reversed
= reversed_comparison_code_parts
4200 (cond_code
, cond
, cop1
, NULL
))
4202 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
4205 /* Likewise, we can make the negate of a comparison operation
4206 if the result values are - STORE_FLAG_VALUE and zero. */
4207 else if (GET_CODE (true_rtx
) == CONST_INT
4208 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
4209 && false_rtx
== const0_rtx
)
4210 x
= simplify_gen_unary (NEG
, mode
,
4211 simplify_gen_relational (cond_code
,
4215 else if (GET_CODE (false_rtx
) == CONST_INT
4216 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
4217 && true_rtx
== const0_rtx
4218 && ((reversed
= reversed_comparison_code_parts
4219 (cond_code
, cond
, cop1
, NULL
))
4221 x
= simplify_gen_unary (NEG
, mode
,
4222 simplify_gen_relational (reversed
,
4227 return gen_rtx_IF_THEN_ELSE (mode
,
4228 simplify_gen_relational (cond_code
,
4233 true_rtx
, false_rtx
);
4235 code
= GET_CODE (x
);
4236 op0_mode
= VOIDmode
;
4241 /* Try to fold this expression in case we have constants that weren't
4244 switch (GET_RTX_CLASS (code
))
4247 if (op0_mode
== VOIDmode
)
4248 op0_mode
= GET_MODE (XEXP (x
, 0));
4249 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
4252 case RTX_COMM_COMPARE
:
4254 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
4255 if (cmp_mode
== VOIDmode
)
4257 cmp_mode
= GET_MODE (XEXP (x
, 1));
4258 if (cmp_mode
== VOIDmode
)
4259 cmp_mode
= op0_mode
;
4261 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
4262 XEXP (x
, 0), XEXP (x
, 1));
4265 case RTX_COMM_ARITH
:
4267 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4269 case RTX_BITFIELD_OPS
:
4271 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
4272 XEXP (x
, 1), XEXP (x
, 2));
4281 code
= GET_CODE (temp
);
4282 op0_mode
= VOIDmode
;
4283 mode
= GET_MODE (temp
);
4286 /* First see if we can apply the inverse distributive law. */
4287 if (code
== PLUS
|| code
== MINUS
4288 || code
== AND
|| code
== IOR
|| code
== XOR
)
4290 x
= apply_distributive_law (x
);
4291 code
= GET_CODE (x
);
4292 op0_mode
= VOIDmode
;
4295 /* If CODE is an associative operation not otherwise handled, see if we
4296 can associate some operands. This can win if they are constants or
4297 if they are logically related (i.e. (a & b) & a). */
4298 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4299 || code
== AND
|| code
== IOR
|| code
== XOR
4300 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4301 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4302 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
4304 if (GET_CODE (XEXP (x
, 0)) == code
)
4306 rtx other
= XEXP (XEXP (x
, 0), 0);
4307 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4308 rtx inner_op1
= XEXP (x
, 1);
4311 /* Make sure we pass the constant operand if any as the second
4312 one if this is a commutative operation. */
4313 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4315 rtx tem
= inner_op0
;
4316 inner_op0
= inner_op1
;
4319 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4320 : code
== DIV
? MULT
4322 mode
, inner_op0
, inner_op1
);
4324 /* For commutative operations, try the other pair if that one
4326 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4328 other
= XEXP (XEXP (x
, 0), 1);
4329 inner
= simplify_binary_operation (code
, mode
,
4330 XEXP (XEXP (x
, 0), 0),
4335 return simplify_gen_binary (code
, mode
, other
, inner
);
4339 /* A little bit of algebraic simplification here. */
4343 /* Ensure that our address has any ASHIFTs converted to MULT in case
4344 address-recognizing predicates are called later. */
4345 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4346 SUBST (XEXP (x
, 0), temp
);
4350 if (op0_mode
== VOIDmode
)
4351 op0_mode
= GET_MODE (SUBREG_REG (x
));
4353 /* See if this can be moved to simplify_subreg. */
4354 if (CONSTANT_P (SUBREG_REG (x
))
4355 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4356 /* Don't call gen_lowpart if the inner mode
4357 is VOIDmode and we cannot simplify it, as SUBREG without
4358 inner mode is invalid. */
4359 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4360 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4361 return gen_lowpart (mode
, SUBREG_REG (x
));
4363 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4367 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4373 /* Don't change the mode of the MEM if that would change the meaning
4375 if (MEM_P (SUBREG_REG (x
))
4376 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4377 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4378 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4380 /* Note that we cannot do any narrowing for non-constants since
4381 we might have been counting on using the fact that some bits were
4382 zero. We now do this in the SET. */
4387 temp
= expand_compound_operation (XEXP (x
, 0));
4389 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4390 replaced by (lshiftrt X C). This will convert
4391 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4393 if (GET_CODE (temp
) == ASHIFTRT
4394 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4395 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4396 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4397 INTVAL (XEXP (temp
, 1)));
4399 /* If X has only a single bit that might be nonzero, say, bit I, convert
4400 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4401 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4402 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4403 or a SUBREG of one since we'd be making the expression more
4404 complex if it was just a register. */
4407 && ! (GET_CODE (temp
) == SUBREG
4408 && REG_P (SUBREG_REG (temp
)))
4409 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4411 rtx temp1
= simplify_shift_const
4412 (NULL_RTX
, ASHIFTRT
, mode
,
4413 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4414 GET_MODE_BITSIZE (mode
) - 1 - i
),
4415 GET_MODE_BITSIZE (mode
) - 1 - i
);
4417 /* If all we did was surround TEMP with the two shifts, we
4418 haven't improved anything, so don't use it. Otherwise,
4419 we are better off with TEMP1. */
4420 if (GET_CODE (temp1
) != ASHIFTRT
4421 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4422 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4428 /* We can't handle truncation to a partial integer mode here
4429 because we don't know the real bitsize of the partial
4431 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4434 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4435 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4436 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4438 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4439 GET_MODE_MASK (mode
), 0));
4441 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4442 whose value is a comparison can be replaced with a subreg if
4443 STORE_FLAG_VALUE permits. */
4444 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4445 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4446 && (temp
= get_last_value (XEXP (x
, 0)))
4447 && COMPARISON_P (temp
))
4448 return gen_lowpart (mode
, XEXP (x
, 0));
4453 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4454 using cc0, in which case we want to leave it as a COMPARE
4455 so we can distinguish it from a register-register-copy. */
4456 if (XEXP (x
, 1) == const0_rtx
)
4459 /* x - 0 is the same as x unless x's mode has signed zeros and
4460 allows rounding towards -infinity. Under those conditions,
4462 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4463 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4464 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4470 /* (const (const X)) can become (const X). Do it this way rather than
4471 returning the inner CONST since CONST can be shared with a
4473 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4474 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4479 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4480 can add in an offset. find_split_point will split this address up
4481 again if it doesn't match. */
4482 if (GET_CODE (XEXP (x
, 0)) == HIGH
4483 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4489 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4490 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4491 bit-field and can be replaced by either a sign_extend or a
4492 sign_extract. The `and' may be a zero_extend and the two
4493 <c>, -<c> constants may be reversed. */
4494 if (GET_CODE (XEXP (x
, 0)) == XOR
4495 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4496 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4497 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4498 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4499 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4500 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4501 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4502 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4503 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4504 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4505 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4506 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4507 == (unsigned int) i
+ 1))))
4508 return simplify_shift_const
4509 (NULL_RTX
, ASHIFTRT
, mode
,
4510 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4511 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4512 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4513 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4515 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4516 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4517 the bitsize of the mode - 1. This allows simplification of
4518 "a = (b & 8) == 0;" */
4519 if (XEXP (x
, 1) == constm1_rtx
4520 && !REG_P (XEXP (x
, 0))
4521 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4522 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4523 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4524 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4525 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4526 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4527 GET_MODE_BITSIZE (mode
) - 1),
4528 GET_MODE_BITSIZE (mode
) - 1);
4530 /* If we are adding two things that have no bits in common, convert
4531 the addition into an IOR. This will often be further simplified,
4532 for example in cases like ((a & 1) + (a & 2)), which can
4535 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4536 && (nonzero_bits (XEXP (x
, 0), mode
)
4537 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4539 /* Try to simplify the expression further. */
4540 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4541 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4543 /* If we could, great. If not, do not go ahead with the IOR
4544 replacement, since PLUS appears in many special purpose
4545 address arithmetic instructions. */
4546 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4552 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4553 (and <foo> (const_int pow2-1)) */
4554 if (GET_CODE (XEXP (x
, 1)) == AND
4555 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4556 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4557 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4558 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4559 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4563 /* If we have (mult (plus A B) C), apply the distributive law and then
4564 the inverse distributive law to see if things simplify. This
4565 occurs mostly in addresses, often when unrolling loops. */
4567 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4569 rtx result
= distribute_and_simplify_rtx (x
, 0);
4574 /* Try simplify a*(b/c) as (a*b)/c. */
4575 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4576 && GET_CODE (XEXP (x
, 0)) == DIV
)
4578 rtx tem
= simplify_binary_operation (MULT
, mode
,
4579 XEXP (XEXP (x
, 0), 0),
4582 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4587 /* If this is a divide by a power of two, treat it as a shift if
4588 its first operand is a shift. */
4589 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4590 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4591 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4592 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4593 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4594 || GET_CODE (XEXP (x
, 0)) == ROTATE
4595 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4596 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4600 case GT
: case GTU
: case GE
: case GEU
:
4601 case LT
: case LTU
: case LE
: case LEU
:
4602 case UNEQ
: case LTGT
:
4603 case UNGT
: case UNGE
:
4604 case UNLT
: case UNLE
:
4605 case UNORDERED
: case ORDERED
:
4606 /* If the first operand is a condition code, we can't do anything
4608 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4609 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4610 && ! CC0_P (XEXP (x
, 0))))
4612 rtx op0
= XEXP (x
, 0);
4613 rtx op1
= XEXP (x
, 1);
4614 enum rtx_code new_code
;
4616 if (GET_CODE (op0
) == COMPARE
)
4617 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4619 /* Simplify our comparison, if possible. */
4620 new_code
= simplify_comparison (code
, &op0
, &op1
);
4622 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4623 if only the low-order bit is possibly nonzero in X (such as when
4624 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4625 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4626 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4629 Remove any ZERO_EXTRACT we made when thinking this was a
4630 comparison. It may now be simpler to use, e.g., an AND. If a
4631 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4632 the call to make_compound_operation in the SET case. */
4634 if (STORE_FLAG_VALUE
== 1
4635 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4636 && op1
== const0_rtx
4637 && mode
== GET_MODE (op0
)
4638 && nonzero_bits (op0
, mode
) == 1)
4639 return gen_lowpart (mode
,
4640 expand_compound_operation (op0
));
4642 else if (STORE_FLAG_VALUE
== 1
4643 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4644 && op1
== const0_rtx
4645 && mode
== GET_MODE (op0
)
4646 && (num_sign_bit_copies (op0
, mode
)
4647 == GET_MODE_BITSIZE (mode
)))
4649 op0
= expand_compound_operation (op0
);
4650 return simplify_gen_unary (NEG
, mode
,
4651 gen_lowpart (mode
, op0
),
4655 else if (STORE_FLAG_VALUE
== 1
4656 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4657 && op1
== const0_rtx
4658 && mode
== GET_MODE (op0
)
4659 && nonzero_bits (op0
, mode
) == 1)
4661 op0
= expand_compound_operation (op0
);
4662 return simplify_gen_binary (XOR
, mode
,
4663 gen_lowpart (mode
, op0
),
4667 else if (STORE_FLAG_VALUE
== 1
4668 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4669 && op1
== const0_rtx
4670 && mode
== GET_MODE (op0
)
4671 && (num_sign_bit_copies (op0
, mode
)
4672 == GET_MODE_BITSIZE (mode
)))
4674 op0
= expand_compound_operation (op0
);
4675 return plus_constant (gen_lowpart (mode
, op0
), 1);
4678 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4680 if (STORE_FLAG_VALUE
== -1
4681 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4682 && op1
== const0_rtx
4683 && (num_sign_bit_copies (op0
, mode
)
4684 == GET_MODE_BITSIZE (mode
)))
4685 return gen_lowpart (mode
,
4686 expand_compound_operation (op0
));
4688 else if (STORE_FLAG_VALUE
== -1
4689 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4690 && op1
== const0_rtx
4691 && mode
== GET_MODE (op0
)
4692 && nonzero_bits (op0
, mode
) == 1)
4694 op0
= expand_compound_operation (op0
);
4695 return simplify_gen_unary (NEG
, mode
,
4696 gen_lowpart (mode
, op0
),
4700 else if (STORE_FLAG_VALUE
== -1
4701 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4702 && op1
== const0_rtx
4703 && mode
== GET_MODE (op0
)
4704 && (num_sign_bit_copies (op0
, mode
)
4705 == GET_MODE_BITSIZE (mode
)))
4707 op0
= expand_compound_operation (op0
);
4708 return simplify_gen_unary (NOT
, mode
,
4709 gen_lowpart (mode
, op0
),
4713 /* If X is 0/1, (eq X 0) is X-1. */
4714 else if (STORE_FLAG_VALUE
== -1
4715 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4716 && op1
== const0_rtx
4717 && mode
== GET_MODE (op0
)
4718 && nonzero_bits (op0
, mode
) == 1)
4720 op0
= expand_compound_operation (op0
);
4721 return plus_constant (gen_lowpart (mode
, op0
), -1);
4724 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4725 one bit that might be nonzero, we can convert (ne x 0) to
4726 (ashift x c) where C puts the bit in the sign bit. Remove any
4727 AND with STORE_FLAG_VALUE when we are done, since we are only
4728 going to test the sign bit. */
4729 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4730 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4731 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4732 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4733 && op1
== const0_rtx
4734 && mode
== GET_MODE (op0
)
4735 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4737 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4738 expand_compound_operation (op0
),
4739 GET_MODE_BITSIZE (mode
) - 1 - i
);
4740 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4746 /* If the code changed, return a whole new comparison. */
4747 if (new_code
!= code
)
4748 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4750 /* Otherwise, keep this operation, but maybe change its operands.
4751 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4752 SUBST (XEXP (x
, 0), op0
);
4753 SUBST (XEXP (x
, 1), op1
);
4758 return simplify_if_then_else (x
);
4764 /* If we are processing SET_DEST, we are done. */
4768 return expand_compound_operation (x
);
4771 return simplify_set (x
);
4775 return simplify_logical (x
);
4782 /* If this is a shift by a constant amount, simplify it. */
4783 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4784 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4785 INTVAL (XEXP (x
, 1)));
4787 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4789 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4791 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4803 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4806 simplify_if_then_else (rtx x
)
4808 enum machine_mode mode
= GET_MODE (x
);
4809 rtx cond
= XEXP (x
, 0);
4810 rtx true_rtx
= XEXP (x
, 1);
4811 rtx false_rtx
= XEXP (x
, 2);
4812 enum rtx_code true_code
= GET_CODE (cond
);
4813 int comparison_p
= COMPARISON_P (cond
);
4816 enum rtx_code false_code
;
4819 /* Simplify storing of the truth value. */
4820 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4821 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
4822 XEXP (cond
, 0), XEXP (cond
, 1));
4824 /* Also when the truth value has to be reversed. */
4826 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4827 && (reversed
= reversed_comparison (cond
, mode
)))
4830 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4831 in it is being compared against certain values. Get the true and false
4832 comparisons and see if that says anything about the value of each arm. */
4835 && ((false_code
= reversed_comparison_code (cond
, NULL
))
4837 && REG_P (XEXP (cond
, 0)))
4840 rtx from
= XEXP (cond
, 0);
4841 rtx true_val
= XEXP (cond
, 1);
4842 rtx false_val
= true_val
;
4845 /* If FALSE_CODE is EQ, swap the codes and arms. */
4847 if (false_code
== EQ
)
4849 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4850 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4853 /* If we are comparing against zero and the expression being tested has
4854 only a single bit that might be nonzero, that is its value when it is
4855 not equal to zero. Similarly if it is known to be -1 or 0. */
4857 if (true_code
== EQ
&& true_val
== const0_rtx
4858 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4859 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4860 else if (true_code
== EQ
&& true_val
== const0_rtx
4861 && (num_sign_bit_copies (from
, GET_MODE (from
))
4862 == GET_MODE_BITSIZE (GET_MODE (from
))))
4863 false_code
= EQ
, false_val
= constm1_rtx
;
4865 /* Now simplify an arm if we know the value of the register in the
4866 branch and it is used in the arm. Be careful due to the potential
4867 of locally-shared RTL. */
4869 if (reg_mentioned_p (from
, true_rtx
))
4870 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4872 pc_rtx
, pc_rtx
, 0, 0);
4873 if (reg_mentioned_p (from
, false_rtx
))
4874 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4876 pc_rtx
, pc_rtx
, 0, 0);
4878 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4879 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4881 true_rtx
= XEXP (x
, 1);
4882 false_rtx
= XEXP (x
, 2);
4883 true_code
= GET_CODE (cond
);
4886 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4887 reversed, do so to avoid needing two sets of patterns for
4888 subtract-and-branch insns. Similarly if we have a constant in the true
4889 arm, the false arm is the same as the first operand of the comparison, or
4890 the false arm is more complicated than the true arm. */
4893 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
4894 && (true_rtx
== pc_rtx
4895 || (CONSTANT_P (true_rtx
)
4896 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4897 || true_rtx
== const0_rtx
4898 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4899 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4900 && !OBJECT_P (false_rtx
))
4901 || reg_mentioned_p (true_rtx
, false_rtx
)
4902 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4904 true_code
= reversed_comparison_code (cond
, NULL
);
4905 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
4906 SUBST (XEXP (x
, 1), false_rtx
);
4907 SUBST (XEXP (x
, 2), true_rtx
);
4909 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4912 /* It is possible that the conditional has been simplified out. */
4913 true_code
= GET_CODE (cond
);
4914 comparison_p
= COMPARISON_P (cond
);
4917 /* If the two arms are identical, we don't need the comparison. */
4919 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4922 /* Convert a == b ? b : a to "a". */
4923 if (true_code
== EQ
&& ! side_effects_p (cond
)
4924 && !HONOR_NANS (mode
)
4925 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4926 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4928 else if (true_code
== NE
&& ! side_effects_p (cond
)
4929 && !HONOR_NANS (mode
)
4930 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4931 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4934 /* Look for cases where we have (abs x) or (neg (abs X)). */
4936 if (GET_MODE_CLASS (mode
) == MODE_INT
4937 && GET_CODE (false_rtx
) == NEG
4938 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4940 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4941 && ! side_effects_p (true_rtx
))
4946 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4950 simplify_gen_unary (NEG
, mode
,
4951 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4957 /* Look for MIN or MAX. */
4959 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4961 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4962 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4963 && ! side_effects_p (cond
))
4968 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4971 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4974 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4977 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4982 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4983 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4984 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4985 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4986 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4987 neither 1 or -1, but it isn't worth checking for. */
4989 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4991 && GET_MODE_CLASS (mode
) == MODE_INT
4992 && ! side_effects_p (x
))
4994 rtx t
= make_compound_operation (true_rtx
, SET
);
4995 rtx f
= make_compound_operation (false_rtx
, SET
);
4996 rtx cond_op0
= XEXP (cond
, 0);
4997 rtx cond_op1
= XEXP (cond
, 1);
4998 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4999 enum machine_mode m
= mode
;
5000 rtx z
= 0, c1
= NULL_RTX
;
5002 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5003 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5004 || GET_CODE (t
) == ASHIFT
5005 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5006 && rtx_equal_p (XEXP (t
, 0), f
))
5007 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5009 /* If an identity-zero op is commutative, check whether there
5010 would be a match if we swapped the operands. */
5011 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5012 || GET_CODE (t
) == XOR
)
5013 && rtx_equal_p (XEXP (t
, 1), f
))
5014 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5015 else if (GET_CODE (t
) == SIGN_EXTEND
5016 && (GET_CODE (XEXP (t
, 0)) == PLUS
5017 || GET_CODE (XEXP (t
, 0)) == MINUS
5018 || GET_CODE (XEXP (t
, 0)) == IOR
5019 || GET_CODE (XEXP (t
, 0)) == XOR
5020 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5021 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5022 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5023 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5024 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5025 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5026 && (num_sign_bit_copies (f
, GET_MODE (f
))
5028 (GET_MODE_BITSIZE (mode
)
5029 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5031 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5032 extend_op
= SIGN_EXTEND
;
5033 m
= GET_MODE (XEXP (t
, 0));
5035 else if (GET_CODE (t
) == SIGN_EXTEND
5036 && (GET_CODE (XEXP (t
, 0)) == PLUS
5037 || GET_CODE (XEXP (t
, 0)) == IOR
5038 || GET_CODE (XEXP (t
, 0)) == XOR
)
5039 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5040 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5041 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5042 && (num_sign_bit_copies (f
, GET_MODE (f
))
5044 (GET_MODE_BITSIZE (mode
)
5045 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5047 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5048 extend_op
= SIGN_EXTEND
;
5049 m
= GET_MODE (XEXP (t
, 0));
5051 else if (GET_CODE (t
) == ZERO_EXTEND
5052 && (GET_CODE (XEXP (t
, 0)) == PLUS
5053 || GET_CODE (XEXP (t
, 0)) == MINUS
5054 || GET_CODE (XEXP (t
, 0)) == IOR
5055 || GET_CODE (XEXP (t
, 0)) == XOR
5056 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5057 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5058 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5059 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5060 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5061 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5062 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5063 && ((nonzero_bits (f
, GET_MODE (f
))
5064 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5067 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5068 extend_op
= ZERO_EXTEND
;
5069 m
= GET_MODE (XEXP (t
, 0));
5071 else if (GET_CODE (t
) == ZERO_EXTEND
5072 && (GET_CODE (XEXP (t
, 0)) == PLUS
5073 || GET_CODE (XEXP (t
, 0)) == IOR
5074 || GET_CODE (XEXP (t
, 0)) == XOR
)
5075 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5076 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5077 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5078 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5079 && ((nonzero_bits (f
, GET_MODE (f
))
5080 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5083 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5084 extend_op
= ZERO_EXTEND
;
5085 m
= GET_MODE (XEXP (t
, 0));
5090 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5091 cond_op0
, cond_op1
),
5092 pc_rtx
, pc_rtx
, 0, 0);
5093 temp
= simplify_gen_binary (MULT
, m
, temp
,
5094 simplify_gen_binary (MULT
, m
, c1
,
5096 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5097 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5099 if (extend_op
!= UNKNOWN
)
5100 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5106 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5107 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5108 negation of a single bit, we can convert this operation to a shift. We
5109 can actually do this more generally, but it doesn't seem worth it. */
5111 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5112 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5113 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5114 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5115 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5116 == GET_MODE_BITSIZE (mode
))
5117 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5119 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5120 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5122 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5123 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5124 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5125 && GET_MODE (XEXP (cond
, 0)) == mode
5126 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5127 == nonzero_bits (XEXP (cond
, 0), mode
)
5128 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5129 return XEXP (cond
, 0);
5134 /* Simplify X, a SET expression. Return the new expression. */
5137 simplify_set (rtx x
)
5139 rtx src
= SET_SRC (x
);
5140 rtx dest
= SET_DEST (x
);
5141 enum machine_mode mode
5142 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5146 /* (set (pc) (return)) gets written as (return). */
5147 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5150 /* Now that we know for sure which bits of SRC we are using, see if we can
5151 simplify the expression for the object knowing that we only need the
5154 if (GET_MODE_CLASS (mode
) == MODE_INT
5155 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5157 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
5158 SUBST (SET_SRC (x
), src
);
5161 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5162 the comparison result and try to simplify it unless we already have used
5163 undobuf.other_insn. */
5164 if ((GET_MODE_CLASS (mode
) == MODE_CC
5165 || GET_CODE (src
) == COMPARE
5167 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5168 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5169 && COMPARISON_P (*cc_use
)
5170 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5172 enum rtx_code old_code
= GET_CODE (*cc_use
);
5173 enum rtx_code new_code
;
5175 int other_changed
= 0;
5176 enum machine_mode compare_mode
= GET_MODE (dest
);
5178 if (GET_CODE (src
) == COMPARE
)
5179 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5181 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5183 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5186 new_code
= old_code
;
5187 else if (!CONSTANT_P (tmp
))
5189 new_code
= GET_CODE (tmp
);
5190 op0
= XEXP (tmp
, 0);
5191 op1
= XEXP (tmp
, 1);
5195 rtx pat
= PATTERN (other_insn
);
5196 undobuf
.other_insn
= other_insn
;
5197 SUBST (*cc_use
, tmp
);
5199 /* Attempt to simplify CC user. */
5200 if (GET_CODE (pat
) == SET
)
5202 rtx
new = simplify_rtx (SET_SRC (pat
));
5203 if (new != NULL_RTX
)
5204 SUBST (SET_SRC (pat
), new);
5207 /* Convert X into a no-op move. */
5208 SUBST (SET_DEST (x
), pc_rtx
);
5209 SUBST (SET_SRC (x
), pc_rtx
);
5213 /* Simplify our comparison, if possible. */
5214 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5216 #ifdef SELECT_CC_MODE
5217 /* If this machine has CC modes other than CCmode, check to see if we
5218 need to use a different CC mode here. */
5219 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5220 compare_mode
= GET_MODE (op0
);
5222 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5225 /* If the mode changed, we have to change SET_DEST, the mode in the
5226 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5227 a hard register, just build new versions with the proper mode. If it
5228 is a pseudo, we lose unless it is only time we set the pseudo, in
5229 which case we can safely change its mode. */
5230 if (compare_mode
!= GET_MODE (dest
))
5232 if (can_change_dest_mode (dest
, 0, compare_mode
))
5234 unsigned int regno
= REGNO (dest
);
5237 if (regno
< FIRST_PSEUDO_REGISTER
)
5238 new_dest
= gen_rtx_REG (compare_mode
, regno
);
5241 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
5242 new_dest
= regno_reg_rtx
[regno
];
5245 SUBST (SET_DEST (x
), new_dest
);
5246 SUBST (XEXP (*cc_use
, 0), new_dest
);
5253 #endif /* SELECT_CC_MODE */
5255 /* If the code changed, we have to build a new comparison in
5256 undobuf.other_insn. */
5257 if (new_code
!= old_code
)
5259 int other_changed_previously
= other_changed
;
5260 unsigned HOST_WIDE_INT mask
;
5262 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5266 /* If the only change we made was to change an EQ into an NE or
5267 vice versa, OP0 has only one bit that might be nonzero, and OP1
5268 is zero, check if changing the user of the condition code will
5269 produce a valid insn. If it won't, we can keep the original code
5270 in that insn by surrounding our operation with an XOR. */
5272 if (((old_code
== NE
&& new_code
== EQ
)
5273 || (old_code
== EQ
&& new_code
== NE
))
5274 && ! other_changed_previously
&& op1
== const0_rtx
5275 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5276 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5278 rtx pat
= PATTERN (other_insn
), note
= 0;
5280 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5281 && ! check_asm_operands (pat
)))
5283 PUT_CODE (*cc_use
, old_code
);
5286 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5287 op0
, GEN_INT (mask
));
5293 undobuf
.other_insn
= other_insn
;
5296 /* If we are now comparing against zero, change our source if
5297 needed. If we do not use cc0, we always have a COMPARE. */
5298 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5300 SUBST (SET_SRC (x
), op0
);
5306 /* Otherwise, if we didn't previously have a COMPARE in the
5307 correct mode, we need one. */
5308 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5310 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5313 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5315 SUBST(SET_SRC (x
), op0
);
5320 /* Otherwise, update the COMPARE if needed. */
5321 SUBST (XEXP (src
, 0), op0
);
5322 SUBST (XEXP (src
, 1), op1
);
5327 /* Get SET_SRC in a form where we have placed back any
5328 compound expressions. Then do the checks below. */
5329 src
= make_compound_operation (src
, SET
);
5330 SUBST (SET_SRC (x
), src
);
5333 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5334 and X being a REG or (subreg (reg)), we may be able to convert this to
5335 (set (subreg:m2 x) (op)).
5337 We can always do this if M1 is narrower than M2 because that means that
5338 we only care about the low bits of the result.
5340 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5341 perform a narrower operation than requested since the high-order bits will
5342 be undefined. On machine where it is defined, this transformation is safe
5343 as long as M1 and M2 have the same number of words. */
5345 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5346 && !OBJECT_P (SUBREG_REG (src
))
5347 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5349 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5350 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5351 #ifndef WORD_REGISTER_OPERATIONS
5352 && (GET_MODE_SIZE (GET_MODE (src
))
5353 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5355 #ifdef CANNOT_CHANGE_MODE_CLASS
5356 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5357 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5358 GET_MODE (SUBREG_REG (src
)),
5362 || (GET_CODE (dest
) == SUBREG
5363 && REG_P (SUBREG_REG (dest
)))))
5365 SUBST (SET_DEST (x
),
5366 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5368 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5370 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5374 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5377 && GET_CODE (src
) == SUBREG
5378 && subreg_lowpart_p (src
)
5379 && (GET_MODE_BITSIZE (GET_MODE (src
))
5380 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5382 rtx inner
= SUBREG_REG (src
);
5383 enum machine_mode inner_mode
= GET_MODE (inner
);
5385 /* Here we make sure that we don't have a sign bit on. */
5386 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5387 && (nonzero_bits (inner
, inner_mode
)
5388 < ((unsigned HOST_WIDE_INT
) 1
5389 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5391 SUBST (SET_SRC (x
), inner
);
5397 #ifdef LOAD_EXTEND_OP
5398 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5399 would require a paradoxical subreg. Replace the subreg with a
5400 zero_extend to avoid the reload that would otherwise be required. */
5402 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5403 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5404 && SUBREG_BYTE (src
) == 0
5405 && (GET_MODE_SIZE (GET_MODE (src
))
5406 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5407 && MEM_P (SUBREG_REG (src
)))
5410 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5411 GET_MODE (src
), SUBREG_REG (src
)));
5417 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5418 are comparing an item known to be 0 or -1 against 0, use a logical
5419 operation instead. Check for one of the arms being an IOR of the other
5420 arm with some value. We compute three terms to be IOR'ed together. In
5421 practice, at most two will be nonzero. Then we do the IOR's. */
5423 if (GET_CODE (dest
) != PC
5424 && GET_CODE (src
) == IF_THEN_ELSE
5425 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5426 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5427 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5428 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5429 #ifdef HAVE_conditional_move
5430 && ! can_conditionally_move_p (GET_MODE (src
))
5432 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5433 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5434 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5435 && ! side_effects_p (src
))
5437 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5438 ? XEXP (src
, 1) : XEXP (src
, 2));
5439 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5440 ? XEXP (src
, 2) : XEXP (src
, 1));
5441 rtx term1
= const0_rtx
, term2
, term3
;
5443 if (GET_CODE (true_rtx
) == IOR
5444 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5445 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5446 else if (GET_CODE (true_rtx
) == IOR
5447 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5448 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5449 else if (GET_CODE (false_rtx
) == IOR
5450 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5451 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5452 else if (GET_CODE (false_rtx
) == IOR
5453 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5454 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5456 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5457 XEXP (XEXP (src
, 0), 0), true_rtx
);
5458 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5459 simplify_gen_unary (NOT
, GET_MODE (src
),
5460 XEXP (XEXP (src
, 0), 0),
5465 simplify_gen_binary (IOR
, GET_MODE (src
),
5466 simplify_gen_binary (IOR
, GET_MODE (src
),
5473 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5474 whole thing fail. */
5475 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5477 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5480 /* Convert this into a field assignment operation, if possible. */
5481 return make_field_assignment (x
);
5484 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5488 simplify_logical (rtx x
)
5490 enum machine_mode mode
= GET_MODE (x
);
5491 rtx op0
= XEXP (x
, 0);
5492 rtx op1
= XEXP (x
, 1);
5494 switch (GET_CODE (x
))
5497 /* We can call simplify_and_const_int only if we don't lose
5498 any (sign) bits when converting INTVAL (op1) to
5499 "unsigned HOST_WIDE_INT". */
5500 if (GET_CODE (op1
) == CONST_INT
5501 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5502 || INTVAL (op1
) > 0))
5504 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5505 if (GET_CODE (x
) != AND
)
5512 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5513 apply the distributive law and then the inverse distributive
5514 law to see if things simplify. */
5515 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5517 rtx result
= distribute_and_simplify_rtx (x
, 0);
5521 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5523 rtx result
= distribute_and_simplify_rtx (x
, 1);
5530 /* If we have (ior (and A B) C), apply the distributive law and then
5531 the inverse distributive law to see if things simplify. */
5533 if (GET_CODE (op0
) == AND
)
5535 rtx result
= distribute_and_simplify_rtx (x
, 0);
5540 if (GET_CODE (op1
) == AND
)
5542 rtx result
= distribute_and_simplify_rtx (x
, 1);
5555 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5556 operations" because they can be replaced with two more basic operations.
5557 ZERO_EXTEND is also considered "compound" because it can be replaced with
5558 an AND operation, which is simpler, though only one operation.
5560 The function expand_compound_operation is called with an rtx expression
5561 and will convert it to the appropriate shifts and AND operations,
5562 simplifying at each stage.
5564 The function make_compound_operation is called to convert an expression
5565 consisting of shifts and ANDs into the equivalent compound expression.
5566 It is the inverse of this function, loosely speaking. */
5569 expand_compound_operation (rtx x
)
5571 unsigned HOST_WIDE_INT pos
= 0, len
;
5573 unsigned int modewidth
;
5576 switch (GET_CODE (x
))
5581 /* We can't necessarily use a const_int for a multiword mode;
5582 it depends on implicitly extending the value.
5583 Since we don't know the right way to extend it,
5584 we can't tell whether the implicit way is right.
5586 Even for a mode that is no wider than a const_int,
5587 we can't win, because we need to sign extend one of its bits through
5588 the rest of it, and we don't know which bit. */
5589 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5592 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5593 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5594 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5595 reloaded. If not for that, MEM's would very rarely be safe.
5597 Reject MODEs bigger than a word, because we might not be able
5598 to reference a two-register group starting with an arbitrary register
5599 (and currently gen_lowpart might crash for a SUBREG). */
5601 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5604 /* Reject MODEs that aren't scalar integers because turning vector
5605 or complex modes into shifts causes problems. */
5607 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5610 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5611 /* If the inner object has VOIDmode (the only way this can happen
5612 is if it is an ASM_OPERANDS), we can't do anything since we don't
5613 know how much masking to do. */
5622 /* ... fall through ... */
5625 /* If the operand is a CLOBBER, just return it. */
5626 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5629 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5630 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5631 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5634 /* Reject MODEs that aren't scalar integers because turning vector
5635 or complex modes into shifts causes problems. */
5637 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5640 len
= INTVAL (XEXP (x
, 1));
5641 pos
= INTVAL (XEXP (x
, 2));
5643 /* This should stay within the object being extracted, fail otherwise. */
5644 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5647 if (BITS_BIG_ENDIAN
)
5648 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5655 /* Convert sign extension to zero extension, if we know that the high
5656 bit is not set, as this is easier to optimize. It will be converted
5657 back to cheaper alternative in make_extraction. */
5658 if (GET_CODE (x
) == SIGN_EXTEND
5659 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5660 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5661 & ~(((unsigned HOST_WIDE_INT
)
5662 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5666 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5667 rtx temp2
= expand_compound_operation (temp
);
5669 /* Make sure this is a profitable operation. */
5670 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5672 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5678 /* We can optimize some special cases of ZERO_EXTEND. */
5679 if (GET_CODE (x
) == ZERO_EXTEND
)
5681 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5682 know that the last value didn't have any inappropriate bits
5684 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5685 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5686 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5687 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5688 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5689 return XEXP (XEXP (x
, 0), 0);
5691 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5692 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5693 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5694 && subreg_lowpart_p (XEXP (x
, 0))
5695 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5696 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5697 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5698 return SUBREG_REG (XEXP (x
, 0));
5700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5701 is a comparison and STORE_FLAG_VALUE permits. This is like
5702 the first case, but it works even when GET_MODE (x) is larger
5703 than HOST_WIDE_INT. */
5704 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5705 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5706 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5707 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5708 <= HOST_BITS_PER_WIDE_INT
)
5709 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5710 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5711 return XEXP (XEXP (x
, 0), 0);
5713 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5714 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5715 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5716 && subreg_lowpart_p (XEXP (x
, 0))
5717 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5719 <= HOST_BITS_PER_WIDE_INT
)
5720 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5722 return SUBREG_REG (XEXP (x
, 0));
5726 /* If we reach here, we want to return a pair of shifts. The inner
5727 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5728 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5729 logical depending on the value of UNSIGNEDP.
5731 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5732 converted into an AND of a shift.
5734 We must check for the case where the left shift would have a negative
5735 count. This can happen in a case like (x >> 31) & 255 on machines
5736 that can't shift by a constant. On those machines, we would first
5737 combine the shift with the AND to produce a variable-position
5738 extraction. Then the constant of 31 would be substituted in to produce
5739 a such a position. */
5741 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5742 if (modewidth
+ len
>= pos
)
5743 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5745 simplify_shift_const (NULL_RTX
, ASHIFT
,
5748 modewidth
- pos
- len
),
5751 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5752 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5753 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5756 ((HOST_WIDE_INT
) 1 << len
) - 1);
5758 /* Any other cases we can't handle. */
5761 /* If we couldn't do this for some reason, return the original
5763 if (GET_CODE (tem
) == CLOBBER
)
5769 /* X is a SET which contains an assignment of one object into
5770 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5771 or certain SUBREGS). If possible, convert it into a series of
5774 We half-heartedly support variable positions, but do not at all
5775 support variable lengths. */
5778 expand_field_assignment (rtx x
)
5781 rtx pos
; /* Always counts from low bit. */
5783 rtx mask
, cleared
, masked
;
5784 enum machine_mode compute_mode
;
5786 /* Loop until we find something we can't simplify. */
5789 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5790 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5792 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5793 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5794 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5796 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5797 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5799 inner
= XEXP (SET_DEST (x
), 0);
5800 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5801 pos
= XEXP (SET_DEST (x
), 2);
5803 /* A constant position should stay within the width of INNER. */
5804 if (GET_CODE (pos
) == CONST_INT
5805 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5808 if (BITS_BIG_ENDIAN
)
5810 if (GET_CODE (pos
) == CONST_INT
)
5811 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5813 else if (GET_CODE (pos
) == MINUS
5814 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5815 && (INTVAL (XEXP (pos
, 1))
5816 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5817 /* If position is ADJUST - X, new position is X. */
5818 pos
= XEXP (pos
, 0);
5820 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
5821 GEN_INT (GET_MODE_BITSIZE (
5828 /* A SUBREG between two modes that occupy the same numbers of words
5829 can be done by moving the SUBREG to the source. */
5830 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5831 /* We need SUBREGs to compute nonzero_bits properly. */
5832 && nonzero_sign_valid
5833 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5834 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5835 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5836 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5838 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5840 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5847 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5848 inner
= SUBREG_REG (inner
);
5850 compute_mode
= GET_MODE (inner
);
5852 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5853 if (! SCALAR_INT_MODE_P (compute_mode
))
5855 enum machine_mode imode
;
5857 /* Don't do anything for vector or complex integral types. */
5858 if (! FLOAT_MODE_P (compute_mode
))
5861 /* Try to find an integral mode to pun with. */
5862 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5863 if (imode
== BLKmode
)
5866 compute_mode
= imode
;
5867 inner
= gen_lowpart (imode
, inner
);
5870 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5871 if (len
>= HOST_BITS_PER_WIDE_INT
)
5874 /* Now compute the equivalent expression. Make a copy of INNER
5875 for the SET_DEST in case it is a MEM into which we will substitute;
5876 we don't want shared RTL in that case. */
5877 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5878 cleared
= simplify_gen_binary (AND
, compute_mode
,
5879 simplify_gen_unary (NOT
, compute_mode
,
5880 simplify_gen_binary (ASHIFT
,
5885 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
5886 simplify_gen_binary (
5888 gen_lowpart (compute_mode
, SET_SRC (x
)),
5892 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
5893 simplify_gen_binary (IOR
, compute_mode
,
5900 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5901 it is an RTX that represents a variable starting position; otherwise,
5902 POS is the (constant) starting bit position (counted from the LSB).
5904 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5907 IN_DEST is nonzero if this is a reference in the destination of a
5908 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5909 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5912 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5913 ZERO_EXTRACT should be built even for bits starting at bit 0.
5915 MODE is the desired mode of the result (if IN_DEST == 0).
5917 The result is an RTX for the extraction or NULL_RTX if the target
5921 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5922 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5923 int in_dest
, int in_compare
)
5925 /* This mode describes the size of the storage area
5926 to fetch the overall value from. Within that, we
5927 ignore the POS lowest bits, etc. */
5928 enum machine_mode is_mode
= GET_MODE (inner
);
5929 enum machine_mode inner_mode
;
5930 enum machine_mode wanted_inner_mode
;
5931 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5932 enum machine_mode pos_mode
= word_mode
;
5933 enum machine_mode extraction_mode
= word_mode
;
5934 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5936 rtx orig_pos_rtx
= pos_rtx
;
5937 HOST_WIDE_INT orig_pos
;
5939 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5941 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5942 consider just the QI as the memory to extract from.
5943 The subreg adds or removes high bits; its mode is
5944 irrelevant to the meaning of this extraction,
5945 since POS and LEN count from the lsb. */
5946 if (MEM_P (SUBREG_REG (inner
)))
5947 is_mode
= GET_MODE (SUBREG_REG (inner
));
5948 inner
= SUBREG_REG (inner
);
5950 else if (GET_CODE (inner
) == ASHIFT
5951 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5952 && pos_rtx
== 0 && pos
== 0
5953 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5955 /* We're extracting the least significant bits of an rtx
5956 (ashift X (const_int C)), where LEN > C. Extract the
5957 least significant (LEN - C) bits of X, giving an rtx
5958 whose mode is MODE, then shift it left C times. */
5959 new = make_extraction (mode
, XEXP (inner
, 0),
5960 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5961 unsignedp
, in_dest
, in_compare
);
5963 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5966 inner_mode
= GET_MODE (inner
);
5968 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5969 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5971 /* See if this can be done without an extraction. We never can if the
5972 width of the field is not the same as that of some integer mode. For
5973 registers, we can only avoid the extraction if the position is at the
5974 low-order bit and this is either not in the destination or we have the
5975 appropriate STRICT_LOW_PART operation available.
5977 For MEM, we can avoid an extract if the field starts on an appropriate
5978 boundary and we can change the mode of the memory reference. */
5980 if (tmode
!= BLKmode
5981 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5983 && (inner_mode
== tmode
5985 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
5986 GET_MODE_BITSIZE (inner_mode
))
5987 || reg_truncated_to_mode (tmode
, inner
))
5990 && have_insn_for (STRICT_LOW_PART
, tmode
))))
5991 || (MEM_P (inner
) && pos_rtx
== 0
5993 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5994 : BITS_PER_UNIT
)) == 0
5995 /* We can't do this if we are widening INNER_MODE (it
5996 may not be aligned, for one thing). */
5997 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5998 && (inner_mode
== tmode
5999 || (! mode_dependent_address_p (XEXP (inner
, 0))
6000 && ! MEM_VOLATILE_P (inner
))))))
6002 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6003 field. If the original and current mode are the same, we need not
6004 adjust the offset. Otherwise, we do if bytes big endian.
6006 If INNER is not a MEM, get a piece consisting of just the field
6007 of interest (in this case POS % BITS_PER_WORD must be 0). */
6011 HOST_WIDE_INT offset
;
6013 /* POS counts from lsb, but make OFFSET count in memory order. */
6014 if (BYTES_BIG_ENDIAN
)
6015 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6017 offset
= pos
/ BITS_PER_UNIT
;
6019 new = adjust_address_nv (inner
, tmode
, offset
);
6021 else if (REG_P (inner
))
6023 if (tmode
!= inner_mode
)
6025 /* We can't call gen_lowpart in a DEST since we
6026 always want a SUBREG (see below) and it would sometimes
6027 return a new hard register. */
6030 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6032 if (WORDS_BIG_ENDIAN
6033 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6034 final_word
= ((GET_MODE_SIZE (inner_mode
)
6035 - GET_MODE_SIZE (tmode
))
6036 / UNITS_PER_WORD
) - final_word
;
6038 final_word
*= UNITS_PER_WORD
;
6039 if (BYTES_BIG_ENDIAN
&&
6040 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6041 final_word
+= (GET_MODE_SIZE (inner_mode
)
6042 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6044 /* Avoid creating invalid subregs, for example when
6045 simplifying (x>>32)&255. */
6046 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
6049 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6052 new = gen_lowpart (tmode
, inner
);
6058 new = force_to_mode (inner
, tmode
,
6059 len
>= HOST_BITS_PER_WIDE_INT
6060 ? ~(unsigned HOST_WIDE_INT
) 0
6061 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6064 /* If this extraction is going into the destination of a SET,
6065 make a STRICT_LOW_PART unless we made a MEM. */
6068 return (MEM_P (new) ? new
6069 : (GET_CODE (new) != SUBREG
6070 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6071 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6076 if (GET_CODE (new) == CONST_INT
)
6077 return gen_int_mode (INTVAL (new), mode
);
6079 /* If we know that no extraneous bits are set, and that the high
6080 bit is not set, convert the extraction to the cheaper of
6081 sign and zero extension, that are equivalent in these cases. */
6082 if (flag_expensive_optimizations
6083 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6084 && ((nonzero_bits (new, tmode
)
6085 & ~(((unsigned HOST_WIDE_INT
)
6086 GET_MODE_MASK (tmode
))
6090 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6091 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6093 /* Prefer ZERO_EXTENSION, since it gives more information to
6095 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6100 /* Otherwise, sign- or zero-extend unless we already are in the
6103 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6107 /* Unless this is a COMPARE or we have a funny memory reference,
6108 don't do anything with zero-extending field extracts starting at
6109 the low-order bit since they are simple AND operations. */
6110 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6111 && ! in_compare
&& unsignedp
)
6114 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6115 if the position is not a constant and the length is not 1. In all
6116 other cases, we would only be going outside our object in cases when
6117 an original shift would have been undefined. */
6119 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6120 || (pos_rtx
!= 0 && len
!= 1)))
6123 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6124 and the mode for the result. */
6125 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6127 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6128 pos_mode
= mode_for_extraction (EP_insv
, 2);
6129 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6132 if (! in_dest
&& unsignedp
6133 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6135 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6136 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6137 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6140 if (! in_dest
&& ! unsignedp
6141 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6143 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6144 pos_mode
= mode_for_extraction (EP_extv
, 3);
6145 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6148 /* Never narrow an object, since that might not be safe. */
6150 if (mode
!= VOIDmode
6151 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6152 extraction_mode
= mode
;
6154 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6155 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6156 pos_mode
= GET_MODE (pos_rtx
);
6158 /* If this is not from memory, the desired mode is the preferred mode
6159 for an extraction pattern's first input operand, or word_mode if there
6162 wanted_inner_mode
= wanted_inner_reg_mode
;
6165 /* Be careful not to go beyond the extracted object and maintain the
6166 natural alignment of the memory. */
6167 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
6168 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
6169 > GET_MODE_BITSIZE (wanted_inner_mode
))
6171 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
6172 gcc_assert (wanted_inner_mode
!= VOIDmode
);
6175 /* If we have to change the mode of memory and cannot, the desired mode
6176 is EXTRACTION_MODE. */
6177 if (inner_mode
!= wanted_inner_mode
6178 && (mode_dependent_address_p (XEXP (inner
, 0))
6179 || MEM_VOLATILE_P (inner
)
6181 wanted_inner_mode
= extraction_mode
;
6186 if (BITS_BIG_ENDIAN
)
6188 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6189 BITS_BIG_ENDIAN style. If position is constant, compute new
6190 position. Otherwise, build subtraction.
6191 Note that POS is relative to the mode of the original argument.
6192 If it's a MEM we need to recompute POS relative to that.
6193 However, if we're extracting from (or inserting into) a register,
6194 we want to recompute POS relative to wanted_inner_mode. */
6195 int width
= (MEM_P (inner
)
6196 ? GET_MODE_BITSIZE (is_mode
)
6197 : GET_MODE_BITSIZE (wanted_inner_mode
));
6200 pos
= width
- len
- pos
;
6203 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6204 /* POS may be less than 0 now, but we check for that below.
6205 Note that it can only be less than 0 if !MEM_P (inner). */
6208 /* If INNER has a wider mode, and this is a constant extraction, try to
6209 make it smaller and adjust the byte to point to the byte containing
6211 if (wanted_inner_mode
!= VOIDmode
6212 && inner_mode
!= wanted_inner_mode
6214 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6216 && ! mode_dependent_address_p (XEXP (inner
, 0))
6217 && ! MEM_VOLATILE_P (inner
))
6221 /* The computations below will be correct if the machine is big
6222 endian in both bits and bytes or little endian in bits and bytes.
6223 If it is mixed, we must adjust. */
6225 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6226 adjust OFFSET to compensate. */
6227 if (BYTES_BIG_ENDIAN
6228 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6229 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6231 /* We can now move to the desired byte. */
6232 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
6233 * GET_MODE_SIZE (wanted_inner_mode
);
6234 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6236 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6237 && is_mode
!= wanted_inner_mode
)
6238 offset
= (GET_MODE_SIZE (is_mode
)
6239 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6241 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6244 /* If INNER is not memory, we can always get it into the proper mode. If we
6245 are changing its mode, POS must be a constant and smaller than the size
6247 else if (!MEM_P (inner
))
6249 if (GET_MODE (inner
) != wanted_inner_mode
6251 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6254 inner
= force_to_mode (inner
, wanted_inner_mode
,
6256 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6257 ? ~(unsigned HOST_WIDE_INT
) 0
6258 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6263 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6264 have to zero extend. Otherwise, we can just use a SUBREG. */
6266 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6268 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6270 /* If we know that no extraneous bits are set, and that the high
6271 bit is not set, convert extraction to cheaper one - either
6272 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6274 if (flag_expensive_optimizations
6275 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6276 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6277 & ~(((unsigned HOST_WIDE_INT
)
6278 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6282 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6284 /* Prefer ZERO_EXTENSION, since it gives more information to
6286 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6291 else if (pos_rtx
!= 0
6292 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6293 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6295 /* Make POS_RTX unless we already have it and it is correct. If we don't
6296 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6298 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6299 pos_rtx
= orig_pos_rtx
;
6301 else if (pos_rtx
== 0)
6302 pos_rtx
= GEN_INT (pos
);
6304 /* Make the required operation. See if we can use existing rtx. */
6305 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6306 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6308 new = gen_lowpart (mode
, new);
6313 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6314 with any other operations in X. Return X without that shift if so. */
6317 extract_left_shift (rtx x
, int count
)
6319 enum rtx_code code
= GET_CODE (x
);
6320 enum machine_mode mode
= GET_MODE (x
);
6326 /* This is the shift itself. If it is wide enough, we will return
6327 either the value being shifted if the shift count is equal to
6328 COUNT or a shift for the difference. */
6329 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6330 && INTVAL (XEXP (x
, 1)) >= count
)
6331 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6332 INTVAL (XEXP (x
, 1)) - count
);
6336 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6337 return simplify_gen_unary (code
, mode
, tem
, mode
);
6341 case PLUS
: case IOR
: case XOR
: case AND
:
6342 /* If we can safely shift this constant and we find the inner shift,
6343 make a new operation. */
6344 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6345 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6346 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6347 return simplify_gen_binary (code
, mode
, tem
,
6348 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6359 /* Look at the expression rooted at X. Look for expressions
6360 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6361 Form these expressions.
6363 Return the new rtx, usually just X.
6365 Also, for machines like the VAX that don't have logical shift insns,
6366 try to convert logical to arithmetic shift operations in cases where
6367 they are equivalent. This undoes the canonicalizations to logical
6368 shifts done elsewhere.
6370 We try, as much as possible, to re-use rtl expressions to save memory.
6372 IN_CODE says what kind of expression we are processing. Normally, it is
6373 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6374 being kludges), it is MEM. When processing the arguments of a comparison
6375 or a COMPARE against zero, it is COMPARE. */
6378 make_compound_operation (rtx x
, enum rtx_code in_code
)
6380 enum rtx_code code
= GET_CODE (x
);
6381 enum machine_mode mode
= GET_MODE (x
);
6382 int mode_width
= GET_MODE_BITSIZE (mode
);
6384 enum rtx_code next_code
;
6390 /* Select the code to be used in recursive calls. Once we are inside an
6391 address, we stay there. If we have a comparison, set to COMPARE,
6392 but once inside, go back to our default of SET. */
6394 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6395 : ((code
== COMPARE
|| COMPARISON_P (x
))
6396 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6397 : in_code
== COMPARE
? SET
: in_code
);
6399 /* Process depending on the code of this operation. If NEW is set
6400 nonzero, it will be returned. */
6405 /* Convert shifts by constants into multiplications if inside
6407 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6408 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6409 && INTVAL (XEXP (x
, 1)) >= 0)
6411 new = make_compound_operation (XEXP (x
, 0), next_code
);
6412 new = gen_rtx_MULT (mode
, new,
6413 GEN_INT ((HOST_WIDE_INT
) 1
6414 << INTVAL (XEXP (x
, 1))));
6419 /* If the second operand is not a constant, we can't do anything
6421 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6424 /* If the constant is a power of two minus one and the first operand
6425 is a logical right shift, make an extraction. */
6426 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6427 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6429 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6430 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6431 0, in_code
== COMPARE
);
6434 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6435 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6436 && subreg_lowpart_p (XEXP (x
, 0))
6437 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6438 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6440 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6442 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6443 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6444 0, in_code
== COMPARE
);
6446 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6447 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6448 || GET_CODE (XEXP (x
, 0)) == IOR
)
6449 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6450 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6451 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6453 /* Apply the distributive law, and then try to make extractions. */
6454 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6455 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6457 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6459 new = make_compound_operation (new, in_code
);
6462 /* If we are have (and (rotate X C) M) and C is larger than the number
6463 of bits in M, this is an extraction. */
6465 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6466 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6467 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6468 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6470 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6471 new = make_extraction (mode
, new,
6472 (GET_MODE_BITSIZE (mode
)
6473 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6474 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6477 /* On machines without logical shifts, if the operand of the AND is
6478 a logical shift and our mask turns off all the propagated sign
6479 bits, we can replace the logical shift with an arithmetic shift. */
6480 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6481 && !have_insn_for (LSHIFTRT
, mode
)
6482 && have_insn_for (ASHIFTRT
, mode
)
6483 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6484 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6485 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6486 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6488 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6490 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6491 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6493 gen_rtx_ASHIFTRT (mode
,
6494 make_compound_operation
6495 (XEXP (XEXP (x
, 0), 0), next_code
),
6496 XEXP (XEXP (x
, 0), 1)));
6499 /* If the constant is one less than a power of two, this might be
6500 representable by an extraction even if no shift is present.
6501 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6502 we are in a COMPARE. */
6503 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6504 new = make_extraction (mode
,
6505 make_compound_operation (XEXP (x
, 0),
6507 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6509 /* If we are in a comparison and this is an AND with a power of two,
6510 convert this into the appropriate bit extract. */
6511 else if (in_code
== COMPARE
6512 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6513 new = make_extraction (mode
,
6514 make_compound_operation (XEXP (x
, 0),
6516 i
, NULL_RTX
, 1, 1, 0, 1);
6521 /* If the sign bit is known to be zero, replace this with an
6522 arithmetic shift. */
6523 if (have_insn_for (ASHIFTRT
, mode
)
6524 && ! have_insn_for (LSHIFTRT
, mode
)
6525 && mode_width
<= HOST_BITS_PER_WIDE_INT
6526 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6528 new = gen_rtx_ASHIFTRT (mode
,
6529 make_compound_operation (XEXP (x
, 0),
6535 /* ... fall through ... */
6541 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6542 this is a SIGN_EXTRACT. */
6543 if (GET_CODE (rhs
) == CONST_INT
6544 && GET_CODE (lhs
) == ASHIFT
6545 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6546 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6548 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6549 new = make_extraction (mode
, new,
6550 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6551 NULL_RTX
, mode_width
- INTVAL (rhs
),
6552 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6556 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6557 If so, try to merge the shifts into a SIGN_EXTEND. We could
6558 also do this for some cases of SIGN_EXTRACT, but it doesn't
6559 seem worth the effort; the case checked for occurs on Alpha. */
6562 && ! (GET_CODE (lhs
) == SUBREG
6563 && (OBJECT_P (SUBREG_REG (lhs
))))
6564 && GET_CODE (rhs
) == CONST_INT
6565 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6566 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6567 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6568 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6569 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6574 /* Call ourselves recursively on the inner expression. If we are
6575 narrowing the object and it has a different RTL code from
6576 what it originally did, do this SUBREG as a force_to_mode. */
6578 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6582 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
6588 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6589 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6590 && subreg_lowpart_p (x
))
6592 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6595 /* If we have something other than a SUBREG, we might have
6596 done an expansion, so rerun ourselves. */
6597 if (GET_CODE (newer
) != SUBREG
)
6598 newer
= make_compound_operation (newer
, in_code
);
6614 x
= gen_lowpart (mode
, new);
6615 code
= GET_CODE (x
);
6618 /* Now recursively process each operand of this operation. */
6619 fmt
= GET_RTX_FORMAT (code
);
6620 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6623 new = make_compound_operation (XEXP (x
, i
), next_code
);
6624 SUBST (XEXP (x
, i
), new);
6627 /* If this is a commutative operation, the changes to the operands
6628 may have made it noncanonical. */
6629 if (COMMUTATIVE_ARITH_P (x
)
6630 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
6633 SUBST (XEXP (x
, 0), XEXP (x
, 1));
6634 SUBST (XEXP (x
, 1), tem
);
6640 /* Given M see if it is a value that would select a field of bits
6641 within an item, but not the entire word. Return -1 if not.
6642 Otherwise, return the starting position of the field, where 0 is the
6645 *PLEN is set to the length of the field. */
6648 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6650 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6651 int pos
= exact_log2 (m
& -m
);
6655 /* Now shift off the low-order zero bits and see if we have a
6656 power of two minus 1. */
6657 len
= exact_log2 ((m
>> pos
) + 1);
6666 /* If X refers to a register that equals REG in value, replace these
6667 references with REG. */
6669 canon_reg_for_combine (rtx x
, rtx reg
)
6676 enum rtx_code code
= GET_CODE (x
);
6677 switch (GET_RTX_CLASS (code
))
6680 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
6681 if (op0
!= XEXP (x
, 0))
6682 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
6687 case RTX_COMM_ARITH
:
6688 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
6689 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
6690 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6691 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
6695 case RTX_COMM_COMPARE
:
6696 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
6697 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
6698 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6699 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
6700 GET_MODE (op0
), op0
, op1
);
6704 case RTX_BITFIELD_OPS
:
6705 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
6706 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
6707 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
6708 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
6709 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
6710 GET_MODE (op0
), op0
, op1
, op2
);
6715 if (rtx_equal_p (get_last_value (reg
), x
)
6716 || rtx_equal_p (reg
, get_last_value (x
)))
6725 fmt
= GET_RTX_FORMAT (code
);
6727 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6730 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
6731 if (op
!= XEXP (x
, i
))
6741 else if (fmt
[i
] == 'E')
6744 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6746 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
6747 if (op
!= XVECEXP (x
, i
, j
))
6754 XVECEXP (x
, i
, j
) = op
;
6765 /* Return X converted to MODE. If the value is already truncated to
6766 MODE we can just return a subreg even though in the general case we
6767 would need an explicit truncation. */
6770 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
6772 if (GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (mode
)
6773 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
6774 GET_MODE_BITSIZE (GET_MODE (x
)))
6775 || (REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
6776 return gen_lowpart (mode
, x
);
6778 return gen_rtx_TRUNCATE (mode
, x
);
6781 /* See if X can be simplified knowing that we will only refer to it in
6782 MODE and will only refer to those bits that are nonzero in MASK.
6783 If other bits are being computed or if masking operations are done
6784 that select a superset of the bits in MASK, they can sometimes be
6787 Return a possibly simplified expression, but always convert X to
6788 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6790 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6791 are all off in X. This is used when X will be complemented, by either
6792 NOT, NEG, or XOR. */
6795 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6798 enum rtx_code code
= GET_CODE (x
);
6799 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6800 enum machine_mode op_mode
;
6801 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6804 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6805 code below will do the wrong thing since the mode of such an
6806 expression is VOIDmode.
6808 Also do nothing if X is a CLOBBER; this can happen if X was
6809 the return value from a call to gen_lowpart. */
6810 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6813 /* We want to perform the operation is its present mode unless we know
6814 that the operation is valid in MODE, in which case we do the operation
6816 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6817 && have_insn_for (code
, mode
))
6818 ? mode
: GET_MODE (x
));
6820 /* It is not valid to do a right-shift in a narrower mode
6821 than the one it came in with. */
6822 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6823 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6824 op_mode
= GET_MODE (x
);
6826 /* Truncate MASK to fit OP_MODE. */
6828 mask
&= GET_MODE_MASK (op_mode
);
6830 /* When we have an arithmetic operation, or a shift whose count we
6831 do not know, we need to assume that all bits up to the highest-order
6832 bit in MASK will be needed. This is how we form such a mask. */
6833 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6834 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6836 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6839 /* Determine what bits of X are guaranteed to be (non)zero. */
6840 nonzero
= nonzero_bits (x
, mode
);
6842 /* If none of the bits in X are needed, return a zero. */
6843 if (! just_select
&& (nonzero
& mask
) == 0)
6846 /* If X is a CONST_INT, return a new one. Do this here since the
6847 test below will fail. */
6848 if (GET_CODE (x
) == CONST_INT
)
6850 if (SCALAR_INT_MODE_P (mode
))
6851 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6854 x
= GEN_INT (INTVAL (x
) & mask
);
6855 return gen_lowpart_common (mode
, x
);
6859 /* If X is narrower than MODE and we want all the bits in X's mode, just
6860 get X in the proper mode. */
6861 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6862 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6863 return gen_lowpart (mode
, x
);
6868 /* If X is a (clobber (const_int)), return it since we know we are
6869 generating something that won't match. */
6876 x
= expand_compound_operation (x
);
6877 if (GET_CODE (x
) != code
)
6878 return force_to_mode (x
, mode
, mask
, next_select
);
6882 if (subreg_lowpart_p (x
)
6883 /* We can ignore the effect of this SUBREG if it narrows the mode or
6884 if the constant masks to zero all the bits the mode doesn't
6886 && ((GET_MODE_SIZE (GET_MODE (x
))
6887 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6889 & GET_MODE_MASK (GET_MODE (x
))
6890 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6891 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
6895 /* If this is an AND with a constant, convert it into an AND
6896 whose constant is the AND of that constant with MASK. If it
6897 remains an AND of MASK, delete it since it is redundant. */
6899 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6901 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6902 mask
& INTVAL (XEXP (x
, 1)));
6904 /* If X is still an AND, see if it is an AND with a mask that
6905 is just some low-order bits. If so, and it is MASK, we don't
6908 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6909 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6913 /* If it remains an AND, try making another AND with the bits
6914 in the mode mask that aren't in MASK turned on. If the
6915 constant in the AND is wide enough, this might make a
6916 cheaper constant. */
6918 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6919 && GET_MODE_MASK (GET_MODE (x
)) != mask
6920 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6922 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6923 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6924 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6927 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6928 number, sign extend it. */
6929 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6930 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6931 cval
|= (HOST_WIDE_INT
) -1 << width
;
6933 y
= simplify_gen_binary (AND
, GET_MODE (x
),
6934 XEXP (x
, 0), GEN_INT (cval
));
6935 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6945 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6946 low-order bits (as in an alignment operation) and FOO is already
6947 aligned to that boundary, mask C1 to that boundary as well.
6948 This may eliminate that PLUS and, later, the AND. */
6951 unsigned int width
= GET_MODE_BITSIZE (mode
);
6952 unsigned HOST_WIDE_INT smask
= mask
;
6954 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6955 number, sign extend it. */
6957 if (width
< HOST_BITS_PER_WIDE_INT
6958 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6959 smask
|= (HOST_WIDE_INT
) -1 << width
;
6961 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6962 && exact_log2 (- smask
) >= 0
6963 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6964 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6965 return force_to_mode (plus_constant (XEXP (x
, 0),
6966 (INTVAL (XEXP (x
, 1)) & smask
)),
6967 mode
, smask
, next_select
);
6970 /* ... fall through ... */
6973 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6974 most significant bit in MASK since carries from those bits will
6975 affect the bits we are interested in. */
6980 /* If X is (minus C Y) where C's least set bit is larger than any bit
6981 in the mask, then we may replace with (neg Y). */
6982 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6983 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6984 & -INTVAL (XEXP (x
, 0))))
6987 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6989 return force_to_mode (x
, mode
, mask
, next_select
);
6992 /* Similarly, if C contains every bit in the fuller_mask, then we may
6993 replace with (not Y). */
6994 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6995 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6996 == INTVAL (XEXP (x
, 0))))
6998 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6999 XEXP (x
, 1), GET_MODE (x
));
7000 return force_to_mode (x
, mode
, mask
, next_select
);
7008 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7009 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7010 operation which may be a bitfield extraction. Ensure that the
7011 constant we form is not wider than the mode of X. */
7013 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7014 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7015 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7016 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7017 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7018 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7019 + floor_log2 (INTVAL (XEXP (x
, 1))))
7020 < GET_MODE_BITSIZE (GET_MODE (x
)))
7021 && (INTVAL (XEXP (x
, 1))
7022 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7024 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7025 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7026 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7027 XEXP (XEXP (x
, 0), 0), temp
);
7028 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7029 XEXP (XEXP (x
, 0), 1));
7030 return force_to_mode (x
, mode
, mask
, next_select
);
7034 /* For most binary operations, just propagate into the operation and
7035 change the mode if we have an operation of that mode. */
7037 op0
= gen_lowpart_or_truncate (op_mode
,
7038 force_to_mode (XEXP (x
, 0), mode
, mask
,
7040 op1
= gen_lowpart_or_truncate (op_mode
,
7041 force_to_mode (XEXP (x
, 1), mode
, mask
,
7044 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7045 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7049 /* For left shifts, do the same, but just for the first operand.
7050 However, we cannot do anything with shifts where we cannot
7051 guarantee that the counts are smaller than the size of the mode
7052 because such a count will have a different meaning in a
7055 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7056 && INTVAL (XEXP (x
, 1)) >= 0
7057 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7058 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7059 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7060 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7063 /* If the shift count is a constant and we can do arithmetic in
7064 the mode of the shift, refine which bits we need. Otherwise, use the
7065 conservative form of the mask. */
7066 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7067 && INTVAL (XEXP (x
, 1)) >= 0
7068 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7069 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7070 mask
>>= INTVAL (XEXP (x
, 1));
7074 op0
= gen_lowpart_or_truncate (op_mode
,
7075 force_to_mode (XEXP (x
, 0), op_mode
,
7076 mask
, next_select
));
7078 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7079 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7083 /* Here we can only do something if the shift count is a constant,
7084 this shift constant is valid for the host, and we can do arithmetic
7087 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7088 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7089 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7091 rtx inner
= XEXP (x
, 0);
7092 unsigned HOST_WIDE_INT inner_mask
;
7094 /* Select the mask of the bits we need for the shift operand. */
7095 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7097 /* We can only change the mode of the shift if we can do arithmetic
7098 in the mode of the shift and INNER_MASK is no wider than the
7099 width of X's mode. */
7100 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7101 op_mode
= GET_MODE (x
);
7103 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
7105 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7106 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7109 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7110 shift and AND produces only copies of the sign bit (C2 is one less
7111 than a power of two), we can do this with just a shift. */
7113 if (GET_CODE (x
) == LSHIFTRT
7114 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7115 /* The shift puts one of the sign bit copies in the least significant
7117 && ((INTVAL (XEXP (x
, 1))
7118 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7119 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7120 && exact_log2 (mask
+ 1) >= 0
7121 /* Number of bits left after the shift must be more than the mask
7123 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7124 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7125 /* Must be more sign bit copies than the mask needs. */
7126 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7127 >= exact_log2 (mask
+ 1)))
7128 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7129 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7130 - exact_log2 (mask
+ 1)));
7135 /* If we are just looking for the sign bit, we don't need this shift at
7136 all, even if it has a variable count. */
7137 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7138 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7139 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7140 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7142 /* If this is a shift by a constant, get a mask that contains those bits
7143 that are not copies of the sign bit. We then have two cases: If
7144 MASK only includes those bits, this can be a logical shift, which may
7145 allow simplifications. If MASK is a single-bit field not within
7146 those bits, we are requesting a copy of the sign bit and hence can
7147 shift the sign bit to the appropriate location. */
7149 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7150 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7154 /* If the considered data is wider than HOST_WIDE_INT, we can't
7155 represent a mask for all its bits in a single scalar.
7156 But we only care about the lower bits, so calculate these. */
7158 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7160 nonzero
= ~(HOST_WIDE_INT
) 0;
7162 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7163 is the number of bits a full-width mask would have set.
7164 We need only shift if these are fewer than nonzero can
7165 hold. If not, we must keep all bits set in nonzero. */
7167 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7168 < HOST_BITS_PER_WIDE_INT
)
7169 nonzero
>>= INTVAL (XEXP (x
, 1))
7170 + HOST_BITS_PER_WIDE_INT
7171 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7175 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7176 nonzero
>>= INTVAL (XEXP (x
, 1));
7179 if ((mask
& ~nonzero
) == 0)
7181 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
7182 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
7183 if (GET_CODE (x
) != ASHIFTRT
)
7184 return force_to_mode (x
, mode
, mask
, next_select
);
7187 else if ((i
= exact_log2 (mask
)) >= 0)
7189 x
= simplify_shift_const
7190 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7191 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7193 if (GET_CODE (x
) != ASHIFTRT
)
7194 return force_to_mode (x
, mode
, mask
, next_select
);
7198 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7199 even if the shift count isn't a constant. */
7201 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7202 XEXP (x
, 0), XEXP (x
, 1));
7206 /* If this is a zero- or sign-extension operation that just affects bits
7207 we don't care about, remove it. Be sure the call above returned
7208 something that is still a shift. */
7210 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7211 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7212 && INTVAL (XEXP (x
, 1)) >= 0
7213 && (INTVAL (XEXP (x
, 1))
7214 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7215 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7216 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7217 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7224 /* If the shift count is constant and we can do computations
7225 in the mode of X, compute where the bits we care about are.
7226 Otherwise, we can't do anything. Don't change the mode of
7227 the shift or propagate MODE into the shift, though. */
7228 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7229 && INTVAL (XEXP (x
, 1)) >= 0)
7231 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7232 GET_MODE (x
), GEN_INT (mask
),
7234 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7236 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7237 INTVAL (temp
), next_select
));
7242 /* If we just want the low-order bit, the NEG isn't needed since it
7243 won't change the low-order bit. */
7245 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
7247 /* We need any bits less significant than the most significant bit in
7248 MASK since carries from those bits will affect the bits we are
7254 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7255 same as the XOR case above. Ensure that the constant we form is not
7256 wider than the mode of X. */
7258 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7259 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7260 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7261 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7262 < GET_MODE_BITSIZE (GET_MODE (x
)))
7263 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7265 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7267 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7268 XEXP (XEXP (x
, 0), 0), temp
);
7269 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7270 temp
, XEXP (XEXP (x
, 0), 1));
7272 return force_to_mode (x
, mode
, mask
, next_select
);
7275 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7276 use the full mask inside the NOT. */
7280 op0
= gen_lowpart_or_truncate (op_mode
,
7281 force_to_mode (XEXP (x
, 0), mode
, mask
,
7283 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7284 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7288 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7289 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7290 which is equal to STORE_FLAG_VALUE. */
7291 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7292 && GET_MODE (XEXP (x
, 0)) == mode
7293 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7294 && (nonzero_bits (XEXP (x
, 0), mode
)
7295 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7296 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
7301 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7302 written in a narrower mode. We play it safe and do not do so. */
7305 gen_lowpart_or_truncate (GET_MODE (x
),
7306 force_to_mode (XEXP (x
, 1), mode
,
7307 mask
, next_select
)));
7309 gen_lowpart_or_truncate (GET_MODE (x
),
7310 force_to_mode (XEXP (x
, 2), mode
,
7311 mask
, next_select
)));
7318 /* Ensure we return a value of the proper mode. */
7319 return gen_lowpart_or_truncate (mode
, x
);
7322 /* Return nonzero if X is an expression that has one of two values depending on
7323 whether some other value is zero or nonzero. In that case, we return the
7324 value that is being tested, *PTRUE is set to the value if the rtx being
7325 returned has a nonzero value, and *PFALSE is set to the other alternative.
7327 If we return zero, we set *PTRUE and *PFALSE to X. */
7330 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7332 enum machine_mode mode
= GET_MODE (x
);
7333 enum rtx_code code
= GET_CODE (x
);
7334 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7335 unsigned HOST_WIDE_INT nz
;
7337 /* If we are comparing a value against zero, we are done. */
7338 if ((code
== NE
|| code
== EQ
)
7339 && XEXP (x
, 1) == const0_rtx
)
7341 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7342 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7346 /* If this is a unary operation whose operand has one of two values, apply
7347 our opcode to compute those values. */
7348 else if (UNARY_P (x
)
7349 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7351 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7352 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7353 GET_MODE (XEXP (x
, 0)));
7357 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7358 make can't possibly match and would suppress other optimizations. */
7359 else if (code
== COMPARE
)
7362 /* If this is a binary operation, see if either side has only one of two
7363 values. If either one does or if both do and they are conditional on
7364 the same value, compute the new true and false values. */
7365 else if (BINARY_P (x
))
7367 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7368 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7370 if ((cond0
!= 0 || cond1
!= 0)
7371 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7373 /* If if_then_else_cond returned zero, then true/false are the
7374 same rtl. We must copy one of them to prevent invalid rtl
7377 true0
= copy_rtx (true0
);
7378 else if (cond1
== 0)
7379 true1
= copy_rtx (true1
);
7381 if (COMPARISON_P (x
))
7383 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7385 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7390 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7391 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7394 return cond0
? cond0
: cond1
;
7397 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7398 operands is zero when the other is nonzero, and vice-versa,
7399 and STORE_FLAG_VALUE is 1 or -1. */
7401 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7402 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7404 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7406 rtx op0
= XEXP (XEXP (x
, 0), 1);
7407 rtx op1
= XEXP (XEXP (x
, 1), 1);
7409 cond0
= XEXP (XEXP (x
, 0), 0);
7410 cond1
= XEXP (XEXP (x
, 1), 0);
7412 if (COMPARISON_P (cond0
)
7413 && COMPARISON_P (cond1
)
7414 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7415 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7416 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7417 || ((swap_condition (GET_CODE (cond0
))
7418 == reversed_comparison_code (cond1
, NULL
))
7419 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7420 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7421 && ! side_effects_p (x
))
7423 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7424 *pfalse
= simplify_gen_binary (MULT
, mode
,
7426 ? simplify_gen_unary (NEG
, mode
,
7434 /* Similarly for MULT, AND and UMIN, except that for these the result
7436 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7437 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7438 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7440 cond0
= XEXP (XEXP (x
, 0), 0);
7441 cond1
= XEXP (XEXP (x
, 1), 0);
7443 if (COMPARISON_P (cond0
)
7444 && COMPARISON_P (cond1
)
7445 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7446 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7447 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7448 || ((swap_condition (GET_CODE (cond0
))
7449 == reversed_comparison_code (cond1
, NULL
))
7450 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7451 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7452 && ! side_effects_p (x
))
7454 *ptrue
= *pfalse
= const0_rtx
;
7460 else if (code
== IF_THEN_ELSE
)
7462 /* If we have IF_THEN_ELSE already, extract the condition and
7463 canonicalize it if it is NE or EQ. */
7464 cond0
= XEXP (x
, 0);
7465 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7466 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7467 return XEXP (cond0
, 0);
7468 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7470 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7471 return XEXP (cond0
, 0);
7477 /* If X is a SUBREG, we can narrow both the true and false values
7478 if the inner expression, if there is a condition. */
7479 else if (code
== SUBREG
7480 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7483 true0
= simplify_gen_subreg (mode
, true0
,
7484 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7485 false0
= simplify_gen_subreg (mode
, false0
,
7486 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7487 if (true0
&& false0
)
7495 /* If X is a constant, this isn't special and will cause confusions
7496 if we treat it as such. Likewise if it is equivalent to a constant. */
7497 else if (CONSTANT_P (x
)
7498 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7501 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7502 will be least confusing to the rest of the compiler. */
7503 else if (mode
== BImode
)
7505 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7509 /* If X is known to be either 0 or -1, those are the true and
7510 false values when testing X. */
7511 else if (x
== constm1_rtx
|| x
== const0_rtx
7512 || (mode
!= VOIDmode
7513 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7515 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7519 /* Likewise for 0 or a single bit. */
7520 else if (SCALAR_INT_MODE_P (mode
)
7521 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7522 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7524 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7528 /* Otherwise fail; show no condition with true and false values the same. */
7529 *ptrue
= *pfalse
= x
;
7533 /* Return the value of expression X given the fact that condition COND
7534 is known to be true when applied to REG as its first operand and VAL
7535 as its second. X is known to not be shared and so can be modified in
7538 We only handle the simplest cases, and specifically those cases that
7539 arise with IF_THEN_ELSE expressions. */
7542 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7544 enum rtx_code code
= GET_CODE (x
);
7549 if (side_effects_p (x
))
7552 /* If either operand of the condition is a floating point value,
7553 then we have to avoid collapsing an EQ comparison. */
7555 && rtx_equal_p (x
, reg
)
7556 && ! FLOAT_MODE_P (GET_MODE (x
))
7557 && ! FLOAT_MODE_P (GET_MODE (val
)))
7560 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7563 /* If X is (abs REG) and we know something about REG's relationship
7564 with zero, we may be able to simplify this. */
7566 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7569 case GE
: case GT
: case EQ
:
7572 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7574 GET_MODE (XEXP (x
, 0)));
7579 /* The only other cases we handle are MIN, MAX, and comparisons if the
7580 operands are the same as REG and VAL. */
7582 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7584 if (rtx_equal_p (XEXP (x
, 0), val
))
7585 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7587 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7589 if (COMPARISON_P (x
))
7591 if (comparison_dominates_p (cond
, code
))
7592 return const_true_rtx
;
7594 code
= reversed_comparison_code (x
, NULL
);
7596 && comparison_dominates_p (cond
, code
))
7601 else if (code
== SMAX
|| code
== SMIN
7602 || code
== UMIN
|| code
== UMAX
)
7604 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7606 /* Do not reverse the condition when it is NE or EQ.
7607 This is because we cannot conclude anything about
7608 the value of 'SMAX (x, y)' when x is not equal to y,
7609 but we can when x equals y. */
7610 if ((code
== SMAX
|| code
== UMAX
)
7611 && ! (cond
== EQ
|| cond
== NE
))
7612 cond
= reverse_condition (cond
);
7617 return unsignedp
? x
: XEXP (x
, 1);
7619 return unsignedp
? x
: XEXP (x
, 0);
7621 return unsignedp
? XEXP (x
, 1) : x
;
7623 return unsignedp
? XEXP (x
, 0) : x
;
7630 else if (code
== SUBREG
)
7632 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7633 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7635 if (SUBREG_REG (x
) != r
)
7637 /* We must simplify subreg here, before we lose track of the
7638 original inner_mode. */
7639 new = simplify_subreg (GET_MODE (x
), r
,
7640 inner_mode
, SUBREG_BYTE (x
));
7644 SUBST (SUBREG_REG (x
), r
);
7649 /* We don't have to handle SIGN_EXTEND here, because even in the
7650 case of replacing something with a modeless CONST_INT, a
7651 CONST_INT is already (supposed to be) a valid sign extension for
7652 its narrower mode, which implies it's already properly
7653 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7654 story is different. */
7655 else if (code
== ZERO_EXTEND
)
7657 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7658 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7660 if (XEXP (x
, 0) != r
)
7662 /* We must simplify the zero_extend here, before we lose
7663 track of the original inner_mode. */
7664 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7669 SUBST (XEXP (x
, 0), r
);
7675 fmt
= GET_RTX_FORMAT (code
);
7676 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7679 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7680 else if (fmt
[i
] == 'E')
7681 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7682 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7689 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7690 assignment as a field assignment. */
7693 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7695 if (x
== y
|| rtx_equal_p (x
, y
))
7698 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7701 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7702 Note that all SUBREGs of MEM are paradoxical; otherwise they
7703 would have been rewritten. */
7704 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7705 && MEM_P (SUBREG_REG (y
))
7706 && rtx_equal_p (SUBREG_REG (y
),
7707 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7710 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7711 && MEM_P (SUBREG_REG (x
))
7712 && rtx_equal_p (SUBREG_REG (x
),
7713 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7716 /* We used to see if get_last_value of X and Y were the same but that's
7717 not correct. In one direction, we'll cause the assignment to have
7718 the wrong destination and in the case, we'll import a register into this
7719 insn that might have already have been dead. So fail if none of the
7720 above cases are true. */
7724 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7725 Return that assignment if so.
7727 We only handle the most common cases. */
7730 make_field_assignment (rtx x
)
7732 rtx dest
= SET_DEST (x
);
7733 rtx src
= SET_SRC (x
);
7738 unsigned HOST_WIDE_INT len
;
7740 enum machine_mode mode
;
7742 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7743 a clear of a one-bit field. We will have changed it to
7744 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7747 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7748 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7749 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7750 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7752 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7755 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7759 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7760 && subreg_lowpart_p (XEXP (src
, 0))
7761 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7762 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7763 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7764 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7765 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7766 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7768 assign
= make_extraction (VOIDmode
, dest
, 0,
7769 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7772 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7776 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7778 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7779 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7780 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7782 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7785 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7789 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7790 SRC is an AND with all bits of that field set, then we can discard
7792 if (GET_CODE (dest
) == ZERO_EXTRACT
7793 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7794 && GET_CODE (src
) == AND
7795 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7797 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7798 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7799 unsigned HOST_WIDE_INT ze_mask
;
7801 if (width
>= HOST_BITS_PER_WIDE_INT
)
7804 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7806 /* Complete overlap. We can remove the source AND. */
7807 if ((and_mask
& ze_mask
) == ze_mask
)
7808 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7810 /* Partial overlap. We can reduce the source AND. */
7811 if ((and_mask
& ze_mask
) != and_mask
)
7813 mode
= GET_MODE (src
);
7814 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7815 gen_int_mode (and_mask
& ze_mask
, mode
));
7816 return gen_rtx_SET (VOIDmode
, dest
, src
);
7820 /* The other case we handle is assignments into a constant-position
7821 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7822 a mask that has all one bits except for a group of zero bits and
7823 OTHER is known to have zeros where C1 has ones, this is such an
7824 assignment. Compute the position and length from C1. Shift OTHER
7825 to the appropriate position, force it to the required mode, and
7826 make the extraction. Check for the AND in both operands. */
7828 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7831 rhs
= expand_compound_operation (XEXP (src
, 0));
7832 lhs
= expand_compound_operation (XEXP (src
, 1));
7834 if (GET_CODE (rhs
) == AND
7835 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7836 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7837 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7838 else if (GET_CODE (lhs
) == AND
7839 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7840 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7841 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7845 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7846 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7847 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7848 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7851 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7855 /* The mode to use for the source is the mode of the assignment, or of
7856 what is inside a possible STRICT_LOW_PART. */
7857 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7858 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7860 /* Shift OTHER right POS places and make it the source, restricting it
7861 to the proper length and mode. */
7863 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7867 src
= force_to_mode (src
, mode
,
7868 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7869 ? ~(unsigned HOST_WIDE_INT
) 0
7870 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7873 /* If SRC is masked by an AND that does not make a difference in
7874 the value being stored, strip it. */
7875 if (GET_CODE (assign
) == ZERO_EXTRACT
7876 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7877 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7878 && GET_CODE (src
) == AND
7879 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7880 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7881 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7882 src
= XEXP (src
, 0);
7884 return gen_rtx_SET (VOIDmode
, assign
, src
);
7887 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7891 apply_distributive_law (rtx x
)
7893 enum rtx_code code
= GET_CODE (x
);
7894 enum rtx_code inner_code
;
7895 rtx lhs
, rhs
, other
;
7898 /* Distributivity is not true for floating point as it can change the
7899 value. So we don't do it unless -funsafe-math-optimizations. */
7900 if (FLOAT_MODE_P (GET_MODE (x
))
7901 && ! flag_unsafe_math_optimizations
)
7904 /* The outer operation can only be one of the following: */
7905 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7906 && code
!= PLUS
&& code
!= MINUS
)
7912 /* If either operand is a primitive we can't do anything, so get out
7914 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7917 lhs
= expand_compound_operation (lhs
);
7918 rhs
= expand_compound_operation (rhs
);
7919 inner_code
= GET_CODE (lhs
);
7920 if (inner_code
!= GET_CODE (rhs
))
7923 /* See if the inner and outer operations distribute. */
7930 /* These all distribute except over PLUS. */
7931 if (code
== PLUS
|| code
== MINUS
)
7936 if (code
!= PLUS
&& code
!= MINUS
)
7941 /* This is also a multiply, so it distributes over everything. */
7945 /* Non-paradoxical SUBREGs distributes over all operations,
7946 provided the inner modes and byte offsets are the same, this
7947 is an extraction of a low-order part, we don't convert an fp
7948 operation to int or vice versa, this is not a vector mode,
7949 and we would not be converting a single-word operation into a
7950 multi-word operation. The latter test is not required, but
7951 it prevents generating unneeded multi-word operations. Some
7952 of the previous tests are redundant given the latter test,
7953 but are retained because they are required for correctness.
7955 We produce the result slightly differently in this case. */
7957 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7958 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7959 || ! subreg_lowpart_p (lhs
)
7960 || (GET_MODE_CLASS (GET_MODE (lhs
))
7961 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7962 || (GET_MODE_SIZE (GET_MODE (lhs
))
7963 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7964 || VECTOR_MODE_P (GET_MODE (lhs
))
7965 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
7966 /* Result might need to be truncated. Don't change mode if
7967 explicit truncation is needed. */
7968 || !TRULY_NOOP_TRUNCATION
7969 (GET_MODE_BITSIZE (GET_MODE (x
)),
7970 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
7973 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7974 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7975 return gen_lowpart (GET_MODE (x
), tem
);
7981 /* Set LHS and RHS to the inner operands (A and B in the example
7982 above) and set OTHER to the common operand (C in the example).
7983 There is only one way to do this unless the inner operation is
7985 if (COMMUTATIVE_ARITH_P (lhs
)
7986 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7987 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7988 else if (COMMUTATIVE_ARITH_P (lhs
)
7989 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7990 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7991 else if (COMMUTATIVE_ARITH_P (lhs
)
7992 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7993 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7994 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7995 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7999 /* Form the new inner operation, seeing if it simplifies first. */
8000 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8002 /* There is one exception to the general way of distributing:
8003 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8004 if (code
== XOR
&& inner_code
== IOR
)
8007 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8010 /* We may be able to continuing distributing the result, so call
8011 ourselves recursively on the inner operation before forming the
8012 outer operation, which we return. */
8013 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8014 apply_distributive_law (tem
), other
);
8017 /* See if X is of the form (* (+ A B) C), and if so convert to
8018 (+ (* A C) (* B C)) and try to simplify.
8020 Most of the time, this results in no change. However, if some of
8021 the operands are the same or inverses of each other, simplifications
8024 For example, (and (ior A B) (not B)) can occur as the result of
8025 expanding a bit field assignment. When we apply the distributive
8026 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8027 which then simplifies to (and (A (not B))).
8029 Note that no checks happen on the validity of applying the inverse
8030 distributive law. This is pointless since we can do it in the
8031 few places where this routine is called.
8033 N is the index of the term that is decomposed (the arithmetic operation,
8034 i.e. (+ A B) in the first example above). !N is the index of the term that
8035 is distributed, i.e. of C in the first example above. */
8037 distribute_and_simplify_rtx (rtx x
, int n
)
8039 enum machine_mode mode
;
8040 enum rtx_code outer_code
, inner_code
;
8041 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8043 decomposed
= XEXP (x
, n
);
8044 if (!ARITHMETIC_P (decomposed
))
8047 mode
= GET_MODE (x
);
8048 outer_code
= GET_CODE (x
);
8049 distributed
= XEXP (x
, !n
);
8051 inner_code
= GET_CODE (decomposed
);
8052 inner_op0
= XEXP (decomposed
, 0);
8053 inner_op1
= XEXP (decomposed
, 1);
8055 /* Special case (and (xor B C) (not A)), which is equivalent to
8056 (xor (ior A B) (ior A C)) */
8057 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8059 distributed
= XEXP (distributed
, 0);
8065 /* Distribute the second term. */
8066 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8067 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8071 /* Distribute the first term. */
8072 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8073 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8076 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8078 if (GET_CODE (tmp
) != outer_code
8079 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8085 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8086 in MODE. Return an equivalent form, if different from (and VAROP
8087 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8090 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
8091 unsigned HOST_WIDE_INT constop
)
8093 unsigned HOST_WIDE_INT nonzero
;
8094 unsigned HOST_WIDE_INT orig_constop
;
8099 orig_constop
= constop
;
8100 if (GET_CODE (varop
) == CLOBBER
)
8103 /* Simplify VAROP knowing that we will be only looking at some of the
8106 Note by passing in CONSTOP, we guarantee that the bits not set in
8107 CONSTOP are not significant and will never be examined. We must
8108 ensure that is the case by explicitly masking out those bits
8109 before returning. */
8110 varop
= force_to_mode (varop
, mode
, constop
, 0);
8112 /* If VAROP is a CLOBBER, we will fail so return it. */
8113 if (GET_CODE (varop
) == CLOBBER
)
8116 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8117 to VAROP and return the new constant. */
8118 if (GET_CODE (varop
) == CONST_INT
)
8119 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8121 /* See what bits may be nonzero in VAROP. Unlike the general case of
8122 a call to nonzero_bits, here we don't care about bits outside
8125 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8127 /* Turn off all bits in the constant that are known to already be zero.
8128 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8129 which is tested below. */
8133 /* If we don't have any bits left, return zero. */
8137 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8138 a power of two, we can replace this with an ASHIFT. */
8139 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8140 && (i
= exact_log2 (constop
)) >= 0)
8141 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8143 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8144 or XOR, then try to apply the distributive law. This may eliminate
8145 operations if either branch can be simplified because of the AND.
8146 It may also make some cases more complex, but those cases probably
8147 won't match a pattern either with or without this. */
8149 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8153 apply_distributive_law
8154 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8155 simplify_and_const_int (NULL_RTX
,
8159 simplify_and_const_int (NULL_RTX
,
8164 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8165 the AND and see if one of the operands simplifies to zero. If so, we
8166 may eliminate it. */
8168 if (GET_CODE (varop
) == PLUS
8169 && exact_log2 (constop
+ 1) >= 0)
8173 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8174 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8175 if (o0
== const0_rtx
)
8177 if (o1
== const0_rtx
)
8181 /* Make a SUBREG if necessary. If we can't make it, fail. */
8182 varop
= gen_lowpart (mode
, varop
);
8183 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
8186 /* If we are only masking insignificant bits, return VAROP. */
8187 if (constop
== nonzero
)
8190 if (varop
== orig_varop
&& constop
== orig_constop
)
8193 /* Otherwise, return an AND. */
8194 constop
= trunc_int_for_mode (constop
, mode
);
8195 return simplify_gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8199 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8202 Return an equivalent form, if different from X. Otherwise, return X. If
8203 X is zero, we are to always construct the equivalent form. */
8206 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8207 unsigned HOST_WIDE_INT constop
)
8209 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
8214 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
, GEN_INT (constop
));
8215 if (GET_MODE (x
) != mode
)
8216 x
= gen_lowpart (mode
, x
);
8220 /* Given a REG, X, compute which bits in X can be nonzero.
8221 We don't care about bits outside of those defined in MODE.
8223 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8224 a shift, AND, or zero_extract, we can do better. */
8227 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8228 rtx known_x ATTRIBUTE_UNUSED
,
8229 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8230 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8231 unsigned HOST_WIDE_INT
*nonzero
)
8235 /* If X is a register whose nonzero bits value is current, use it.
8236 Otherwise, if X is a register whose value we can find, use that
8237 value. Otherwise, use the previously-computed global nonzero bits
8238 for this register. */
8240 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8241 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8242 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8243 && GET_MODE_CLASS (mode
) == MODE_INT
))
8244 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8245 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8246 && REG_N_SETS (REGNO (x
)) == 1
8247 && ! REGNO_REG_SET_P
8248 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8250 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8252 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8256 tem
= get_last_value (x
);
8260 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8261 /* If X is narrower than MODE and TEM is a non-negative
8262 constant that would appear negative in the mode of X,
8263 sign-extend it for use in reg_nonzero_bits because some
8264 machines (maybe most) will actually do the sign-extension
8265 and this is the conservative approach.
8267 ??? For 2.5, try to tighten up the MD files in this regard
8268 instead of this kludge. */
8270 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8271 && GET_CODE (tem
) == CONST_INT
8273 && 0 != (INTVAL (tem
)
8274 & ((HOST_WIDE_INT
) 1
8275 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8276 tem
= GEN_INT (INTVAL (tem
)
8277 | ((HOST_WIDE_INT
) (-1)
8278 << GET_MODE_BITSIZE (GET_MODE (x
))));
8282 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8284 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8286 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8287 /* We don't know anything about the upper bits. */
8288 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8295 /* Return the number of bits at the high-order end of X that are known to
8296 be equal to the sign bit. X will be used in mode MODE; if MODE is
8297 VOIDmode, X will be used in its own mode. The returned value will always
8298 be between 1 and the number of bits in MODE. */
8301 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8302 rtx known_x ATTRIBUTE_UNUSED
,
8303 enum machine_mode known_mode
8305 unsigned int known_ret ATTRIBUTE_UNUSED
,
8306 unsigned int *result
)
8310 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8311 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8312 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8313 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8314 && REG_N_SETS (REGNO (x
)) == 1
8315 && ! REGNO_REG_SET_P
8316 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8318 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8320 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8324 tem
= get_last_value (x
);
8328 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8329 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8330 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8335 /* Return the number of "extended" bits there are in X, when interpreted
8336 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8337 unsigned quantities, this is the number of high-order zero bits.
8338 For signed quantities, this is the number of copies of the sign bit
8339 minus 1. In both case, this function returns the number of "spare"
8340 bits. For example, if two quantities for which this function returns
8341 at least 1 are added, the addition is known not to overflow.
8343 This function will always return 0 unless called during combine, which
8344 implies that it must be called from a define_split. */
8347 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8349 if (nonzero_sign_valid
== 0)
8353 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8354 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8355 - floor_log2 (nonzero_bits (x
, mode
)))
8357 : num_sign_bit_copies (x
, mode
) - 1);
8360 /* This function is called from `simplify_shift_const' to merge two
8361 outer operations. Specifically, we have already found that we need
8362 to perform operation *POP0 with constant *PCONST0 at the outermost
8363 position. We would now like to also perform OP1 with constant CONST1
8364 (with *POP0 being done last).
8366 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8367 the resulting operation. *PCOMP_P is set to 1 if we would need to
8368 complement the innermost operand, otherwise it is unchanged.
8370 MODE is the mode in which the operation will be done. No bits outside
8371 the width of this mode matter. It is assumed that the width of this mode
8372 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8374 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8375 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8376 result is simply *PCONST0.
8378 If the resulting operation cannot be expressed as one operation, we
8379 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8382 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8384 enum rtx_code op0
= *pop0
;
8385 HOST_WIDE_INT const0
= *pconst0
;
8387 const0
&= GET_MODE_MASK (mode
);
8388 const1
&= GET_MODE_MASK (mode
);
8390 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8394 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8397 if (op1
== UNKNOWN
|| op0
== SET
)
8400 else if (op0
== UNKNOWN
)
8401 op0
= op1
, const0
= const1
;
8403 else if (op0
== op1
)
8427 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8428 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8431 /* If the two constants aren't the same, we can't do anything. The
8432 remaining six cases can all be done. */
8433 else if (const0
!= const1
)
8441 /* (a & b) | b == b */
8443 else /* op1 == XOR */
8444 /* (a ^ b) | b == a | b */
8450 /* (a & b) ^ b == (~a) & b */
8451 op0
= AND
, *pcomp_p
= 1;
8452 else /* op1 == IOR */
8453 /* (a | b) ^ b == a & ~b */
8454 op0
= AND
, const0
= ~const0
;
8459 /* (a | b) & b == b */
8461 else /* op1 == XOR */
8462 /* (a ^ b) & b) == (~a) & b */
8469 /* Check for NO-OP cases. */
8470 const0
&= GET_MODE_MASK (mode
);
8472 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8474 else if (const0
== 0 && op0
== AND
)
8476 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8480 /* ??? Slightly redundant with the above mask, but not entirely.
8481 Moving this above means we'd have to sign-extend the mode mask
8482 for the final test. */
8483 const0
= trunc_int_for_mode (const0
, mode
);
8491 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8492 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8493 simplify it. Otherwise, return a simplified value.
8495 The shift is normally computed in the widest mode we find in VAROP, as
8496 long as it isn't a different number of words than RESULT_MODE. Exceptions
8497 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8500 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
8501 rtx varop
, int orig_count
)
8503 enum rtx_code orig_code
= code
;
8504 rtx orig_varop
= varop
;
8506 enum machine_mode mode
= result_mode
;
8507 enum machine_mode shift_mode
, tmode
;
8508 unsigned int mode_words
8509 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8510 /* We form (outer_op (code varop count) (outer_const)). */
8511 enum rtx_code outer_op
= UNKNOWN
;
8512 HOST_WIDE_INT outer_const
= 0;
8513 int complement_p
= 0;
8516 /* Make sure and truncate the "natural" shift on the way in. We don't
8517 want to do this inside the loop as it makes it more difficult to
8519 if (SHIFT_COUNT_TRUNCATED
)
8520 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8522 /* If we were given an invalid count, don't do anything except exactly
8523 what was requested. */
8525 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8530 /* Unless one of the branches of the `if' in this loop does a `continue',
8531 we will `break' the loop after the `if'. */
8535 /* If we have an operand of (clobber (const_int 0)), fail. */
8536 if (GET_CODE (varop
) == CLOBBER
)
8539 /* If we discovered we had to complement VAROP, leave. Making a NOT
8540 here would cause an infinite loop. */
8544 /* Convert ROTATERT to ROTATE. */
8545 if (code
== ROTATERT
)
8547 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8549 if (VECTOR_MODE_P (result_mode
))
8550 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8552 count
= bitsize
- count
;
8555 /* We need to determine what mode we will do the shift in. If the
8556 shift is a right shift or a ROTATE, we must always do it in the mode
8557 it was originally done in. Otherwise, we can do it in MODE, the
8558 widest mode encountered. */
8560 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8561 ? result_mode
: mode
);
8563 /* Handle cases where the count is greater than the size of the mode
8564 minus 1. For ASHIFT, use the size minus one as the count (this can
8565 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8566 take the count modulo the size. For other shifts, the result is
8569 Since these shifts are being produced by the compiler by combining
8570 multiple operations, each of which are defined, we know what the
8571 result is supposed to be. */
8573 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
8575 if (code
== ASHIFTRT
)
8576 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8577 else if (code
== ROTATE
|| code
== ROTATERT
)
8578 count
%= GET_MODE_BITSIZE (shift_mode
);
8581 /* We can't simply return zero because there may be an
8589 /* An arithmetic right shift of a quantity known to be -1 or 0
8591 if (code
== ASHIFTRT
8592 && (num_sign_bit_copies (varop
, shift_mode
)
8593 == GET_MODE_BITSIZE (shift_mode
)))
8599 /* If we are doing an arithmetic right shift and discarding all but
8600 the sign bit copies, this is equivalent to doing a shift by the
8601 bitsize minus one. Convert it into that shift because it will often
8602 allow other simplifications. */
8604 if (code
== ASHIFTRT
8605 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8606 >= GET_MODE_BITSIZE (shift_mode
)))
8607 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8609 /* We simplify the tests below and elsewhere by converting
8610 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8611 `make_compound_operation' will convert it to an ASHIFTRT for
8612 those machines (such as VAX) that don't have an LSHIFTRT. */
8613 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8615 && ((nonzero_bits (varop
, shift_mode
)
8616 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8620 if (code
== LSHIFTRT
8621 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8622 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8625 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8626 && !((nonzero_bits (varop
, shift_mode
) << count
)
8627 & GET_MODE_MASK (shift_mode
)))
8630 switch (GET_CODE (varop
))
8636 new = expand_compound_operation (varop
);
8645 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8646 minus the width of a smaller mode, we can do this with a
8647 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8648 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8649 && ! mode_dependent_address_p (XEXP (varop
, 0))
8650 && ! MEM_VOLATILE_P (varop
)
8651 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8652 MODE_INT
, 1)) != BLKmode
)
8654 new = adjust_address_nv (varop
, tmode
,
8655 BYTES_BIG_ENDIAN
? 0
8656 : count
/ BITS_PER_UNIT
);
8658 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8659 : ZERO_EXTEND
, mode
, new);
8666 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8667 the same number of words as what we've seen so far. Then store
8668 the widest mode in MODE. */
8669 if (subreg_lowpart_p (varop
)
8670 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8671 > GET_MODE_SIZE (GET_MODE (varop
)))
8672 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8673 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8676 varop
= SUBREG_REG (varop
);
8677 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8678 mode
= GET_MODE (varop
);
8684 /* Some machines use MULT instead of ASHIFT because MULT
8685 is cheaper. But it is still better on those machines to
8686 merge two shifts into one. */
8687 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8688 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8691 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
8693 GEN_INT (exact_log2 (
8694 INTVAL (XEXP (varop
, 1)))));
8700 /* Similar, for when divides are cheaper. */
8701 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8702 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8705 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
8707 GEN_INT (exact_log2 (
8708 INTVAL (XEXP (varop
, 1)))));
8714 /* If we are extracting just the sign bit of an arithmetic
8715 right shift, that shift is not needed. However, the sign
8716 bit of a wider mode may be different from what would be
8717 interpreted as the sign bit in a narrower mode, so, if
8718 the result is narrower, don't discard the shift. */
8719 if (code
== LSHIFTRT
8720 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
8721 && (GET_MODE_BITSIZE (result_mode
)
8722 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8724 varop
= XEXP (varop
, 0);
8728 /* ... fall through ... */
8733 /* Here we have two nested shifts. The result is usually the
8734 AND of a new shift with a mask. We compute the result below. */
8735 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8736 && INTVAL (XEXP (varop
, 1)) >= 0
8737 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8738 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8739 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8741 enum rtx_code first_code
= GET_CODE (varop
);
8742 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8743 unsigned HOST_WIDE_INT mask
;
8746 /* We have one common special case. We can't do any merging if
8747 the inner code is an ASHIFTRT of a smaller mode. However, if
8748 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8749 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8750 we can convert it to
8751 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8752 This simplifies certain SIGN_EXTEND operations. */
8753 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8754 && count
== (GET_MODE_BITSIZE (result_mode
)
8755 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8757 /* C3 has the low-order C1 bits zero. */
8759 mask
= (GET_MODE_MASK (mode
)
8760 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8762 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8763 XEXP (varop
, 0), mask
);
8764 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8766 count
= first_count
;
8771 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8772 than C1 high-order bits equal to the sign bit, we can convert
8773 this to either an ASHIFT or an ASHIFTRT depending on the
8776 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8778 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8779 && GET_MODE (varop
) == shift_mode
8780 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8783 varop
= XEXP (varop
, 0);
8784 count
-= first_count
;
8794 /* There are some cases we can't do. If CODE is ASHIFTRT,
8795 we can only do this if FIRST_CODE is also ASHIFTRT.
8797 We can't do the case when CODE is ROTATE and FIRST_CODE is
8800 If the mode of this shift is not the mode of the outer shift,
8801 we can't do this if either shift is a right shift or ROTATE.
8803 Finally, we can't do any of these if the mode is too wide
8804 unless the codes are the same.
8806 Handle the case where the shift codes are the same
8809 if (code
== first_code
)
8811 if (GET_MODE (varop
) != result_mode
8812 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8816 count
+= first_count
;
8817 varop
= XEXP (varop
, 0);
8821 if (code
== ASHIFTRT
8822 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8823 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8824 || (GET_MODE (varop
) != result_mode
8825 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8826 || first_code
== ROTATE
8827 || code
== ROTATE
)))
8830 /* To compute the mask to apply after the shift, shift the
8831 nonzero bits of the inner shift the same way the
8832 outer shift will. */
8834 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8837 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
8840 /* Give up if we can't compute an outer operation to use. */
8842 || GET_CODE (mask_rtx
) != CONST_INT
8843 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8845 result_mode
, &complement_p
))
8848 /* If the shifts are in the same direction, we add the
8849 counts. Otherwise, we subtract them. */
8850 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8851 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8852 count
+= first_count
;
8854 count
-= first_count
;
8856 /* If COUNT is positive, the new shift is usually CODE,
8857 except for the two exceptions below, in which case it is
8858 FIRST_CODE. If the count is negative, FIRST_CODE should
8861 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8862 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8865 code
= first_code
, count
= -count
;
8867 varop
= XEXP (varop
, 0);
8871 /* If we have (A << B << C) for any shift, we can convert this to
8872 (A << C << B). This wins if A is a constant. Only try this if
8873 B is not a constant. */
8875 else if (GET_CODE (varop
) == code
8876 && GET_CODE (XEXP (varop
, 0)) == CONST_INT
8877 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
)
8879 rtx
new = simplify_const_binary_operation (code
, mode
,
8882 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8889 /* Make this fit the case below. */
8890 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8891 GEN_INT (GET_MODE_MASK (mode
)));
8897 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8898 with C the size of VAROP - 1 and the shift is logical if
8899 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8900 we have an (le X 0) operation. If we have an arithmetic shift
8901 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8902 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8904 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8905 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8906 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8907 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8908 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8909 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8912 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8915 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8916 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8921 /* If we have (shift (logical)), move the logical to the outside
8922 to allow it to possibly combine with another logical and the
8923 shift to combine with another shift. This also canonicalizes to
8924 what a ZERO_EXTRACT looks like. Also, some machines have
8925 (and (shift)) insns. */
8927 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8928 /* We can't do this if we have (ashiftrt (xor)) and the
8929 constant has its sign bit set in shift_mode. */
8930 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8931 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8933 && (new = simplify_const_binary_operation (code
, result_mode
,
8935 GEN_INT (count
))) != 0
8936 && GET_CODE (new) == CONST_INT
8937 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8938 INTVAL (new), result_mode
, &complement_p
))
8940 varop
= XEXP (varop
, 0);
8944 /* If we can't do that, try to simplify the shift in each arm of the
8945 logical expression, make a new logical expression, and apply
8946 the inverse distributive law. This also can't be done
8947 for some (ashiftrt (xor)). */
8948 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8949 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8950 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8953 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8954 XEXP (varop
, 0), count
);
8955 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8956 XEXP (varop
, 1), count
);
8958 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
8960 varop
= apply_distributive_law (varop
);
8968 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8969 says that the sign bit can be tested, FOO has mode MODE, C is
8970 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8971 that may be nonzero. */
8972 if (code
== LSHIFTRT
8973 && XEXP (varop
, 1) == const0_rtx
8974 && GET_MODE (XEXP (varop
, 0)) == result_mode
8975 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
8976 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8977 && STORE_FLAG_VALUE
== -1
8978 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8979 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8980 (HOST_WIDE_INT
) 1, result_mode
,
8983 varop
= XEXP (varop
, 0);
8990 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8991 than the number of bits in the mode is equivalent to A. */
8992 if (code
== LSHIFTRT
8993 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
8994 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8996 varop
= XEXP (varop
, 0);
9001 /* NEG commutes with ASHIFT since it is multiplication. Move the
9002 NEG outside to allow shifts to combine. */
9004 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9005 (HOST_WIDE_INT
) 0, result_mode
,
9008 varop
= XEXP (varop
, 0);
9014 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9015 is one less than the number of bits in the mode is
9016 equivalent to (xor A 1). */
9017 if (code
== LSHIFTRT
9018 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9019 && XEXP (varop
, 1) == constm1_rtx
9020 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9021 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9022 (HOST_WIDE_INT
) 1, result_mode
,
9026 varop
= XEXP (varop
, 0);
9030 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9031 that might be nonzero in BAR are those being shifted out and those
9032 bits are known zero in FOO, we can replace the PLUS with FOO.
9033 Similarly in the other operand order. This code occurs when
9034 we are computing the size of a variable-size array. */
9036 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9037 && count
< HOST_BITS_PER_WIDE_INT
9038 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9039 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9040 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9042 varop
= XEXP (varop
, 0);
9045 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9046 && count
< HOST_BITS_PER_WIDE_INT
9047 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9048 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9050 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9051 & nonzero_bits (XEXP (varop
, 1),
9054 varop
= XEXP (varop
, 1);
9058 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9060 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9061 && (new = simplify_const_binary_operation (ASHIFT
, result_mode
,
9063 GEN_INT (count
))) != 0
9064 && GET_CODE (new) == CONST_INT
9065 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9066 INTVAL (new), result_mode
, &complement_p
))
9068 varop
= XEXP (varop
, 0);
9072 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9073 signbit', and attempt to change the PLUS to an XOR and move it to
9074 the outer operation as is done above in the AND/IOR/XOR case
9075 leg for shift(logical). See details in logical handling above
9076 for reasoning in doing so. */
9077 if (code
== LSHIFTRT
9078 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9079 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9080 && (new = simplify_const_binary_operation (code
, result_mode
,
9082 GEN_INT (count
))) != 0
9083 && GET_CODE (new) == CONST_INT
9084 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9085 INTVAL (new), result_mode
, &complement_p
))
9087 varop
= XEXP (varop
, 0);
9094 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9095 with C the size of VAROP - 1 and the shift is logical if
9096 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9097 we have a (gt X 0) operation. If the shift is arithmetic with
9098 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9099 we have a (neg (gt X 0)) operation. */
9101 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9102 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9103 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9104 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9105 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9106 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9107 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9110 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9113 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9114 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9121 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9122 if the truncate does not affect the value. */
9123 if (code
== LSHIFTRT
9124 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9125 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9126 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9127 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9128 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9130 rtx varop_inner
= XEXP (varop
, 0);
9133 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9134 XEXP (varop_inner
, 0),
9136 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9137 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9150 /* We need to determine what mode to do the shift in. If the shift is
9151 a right shift or ROTATE, we must always do it in the mode it was
9152 originally done in. Otherwise, we can do it in MODE, the widest mode
9153 encountered. The code we care about is that of the shift that will
9154 actually be done, not the shift that was originally requested. */
9156 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9157 ? result_mode
: mode
);
9159 /* We have now finished analyzing the shift. The result should be
9160 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9161 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9162 to the result of the shift. OUTER_CONST is the relevant constant,
9163 but we must turn off all bits turned off in the shift. */
9165 if (outer_op
== UNKNOWN
9166 && orig_code
== code
&& orig_count
== count
9167 && varop
== orig_varop
9168 && shift_mode
== GET_MODE (varop
))
9171 /* Make a SUBREG if necessary. If we can't make it, fail. */
9172 varop
= gen_lowpart (shift_mode
, varop
);
9173 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9176 /* If we have an outer operation and we just made a shift, it is
9177 possible that we could have simplified the shift were it not
9178 for the outer operation. So try to do the simplification
9181 if (outer_op
!= UNKNOWN
)
9182 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
9187 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
9189 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9190 turn off all the bits that the shift would have turned off. */
9191 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9192 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9193 GET_MODE_MASK (result_mode
) >> orig_count
);
9195 /* Do the remainder of the processing in RESULT_MODE. */
9196 x
= gen_lowpart (result_mode
, x
);
9198 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9201 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9203 if (outer_op
!= UNKNOWN
)
9205 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9206 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9208 if (outer_op
== AND
)
9209 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9210 else if (outer_op
== SET
)
9211 /* This means that we have determined that the result is
9212 equivalent to a constant. This should be rare. */
9213 x
= GEN_INT (outer_const
);
9214 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9215 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9217 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9218 GEN_INT (outer_const
));
9224 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9225 The result of the shift is RESULT_MODE. If we cannot simplify it,
9226 return X or, if it is NULL, synthesize the expression with
9227 simplify_gen_binary. Otherwise, return a simplified value.
9229 The shift is normally computed in the widest mode we find in VAROP, as
9230 long as it isn't a different number of words than RESULT_MODE. Exceptions
9231 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9234 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
9235 rtx varop
, int count
)
9237 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
9242 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
9243 if (GET_MODE (x
) != result_mode
)
9244 x
= gen_lowpart (result_mode
, x
);
9249 /* Like recog, but we receive the address of a pointer to a new pattern.
9250 We try to match the rtx that the pointer points to.
9251 If that fails, we may try to modify or replace the pattern,
9252 storing the replacement into the same pointer object.
9254 Modifications include deletion or addition of CLOBBERs.
9256 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9257 the CLOBBERs are placed.
9259 The value is the final insn code from the pattern ultimately matched,
9263 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9266 int insn_code_number
;
9267 int num_clobbers_to_add
= 0;
9270 rtx old_notes
, old_pat
;
9272 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9273 we use to indicate that something didn't match. If we find such a
9274 thing, force rejection. */
9275 if (GET_CODE (pat
) == PARALLEL
)
9276 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9277 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9278 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9281 old_pat
= PATTERN (insn
);
9282 old_notes
= REG_NOTES (insn
);
9283 PATTERN (insn
) = pat
;
9284 REG_NOTES (insn
) = 0;
9286 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9288 /* If it isn't, there is the possibility that we previously had an insn
9289 that clobbered some register as a side effect, but the combined
9290 insn doesn't need to do that. So try once more without the clobbers
9291 unless this represents an ASM insn. */
9293 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9294 && GET_CODE (pat
) == PARALLEL
)
9298 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9299 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9302 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9306 SUBST_INT (XVECLEN (pat
, 0), pos
);
9309 pat
= XVECEXP (pat
, 0, 0);
9311 PATTERN (insn
) = pat
;
9312 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9314 PATTERN (insn
) = old_pat
;
9315 REG_NOTES (insn
) = old_notes
;
9317 /* Recognize all noop sets, these will be killed by followup pass. */
9318 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9319 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9321 /* If we had any clobbers to add, make a new pattern than contains
9322 them. Then check to make sure that all of them are dead. */
9323 if (num_clobbers_to_add
)
9325 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9326 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9328 + num_clobbers_to_add
)
9329 : num_clobbers_to_add
+ 1));
9331 if (GET_CODE (pat
) == PARALLEL
)
9332 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9333 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9335 XVECEXP (newpat
, 0, 0) = pat
;
9337 add_clobbers (newpat
, insn_code_number
);
9339 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9340 i
< XVECLEN (newpat
, 0); i
++)
9342 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9343 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9345 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9346 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9354 return insn_code_number
;
9357 /* Like gen_lowpart_general but for use by combine. In combine it
9358 is not possible to create any new pseudoregs. However, it is
9359 safe to create invalid memory addresses, because combine will
9360 try to recognize them and all they will do is make the combine
9363 If for some reason this cannot do its job, an rtx
9364 (clobber (const_int 0)) is returned.
9365 An insn containing that will not be recognized. */
9368 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9370 enum machine_mode imode
= GET_MODE (x
);
9371 unsigned int osize
= GET_MODE_SIZE (omode
);
9372 unsigned int isize
= GET_MODE_SIZE (imode
);
9378 /* Return identity if this is a CONST or symbolic reference. */
9380 && (GET_CODE (x
) == CONST
9381 || GET_CODE (x
) == SYMBOL_REF
9382 || GET_CODE (x
) == LABEL_REF
))
9385 /* We can only support MODE being wider than a word if X is a
9386 constant integer or has a mode the same size. */
9387 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9388 && ! ((imode
== VOIDmode
9389 && (GET_CODE (x
) == CONST_INT
9390 || GET_CODE (x
) == CONST_DOUBLE
))
9394 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9395 won't know what to do. So we will strip off the SUBREG here and
9396 process normally. */
9397 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9401 /* For use in case we fall down into the address adjustments
9402 further below, we need to adjust the known mode and size of
9403 x; imode and isize, since we just adjusted x. */
9404 imode
= GET_MODE (x
);
9409 isize
= GET_MODE_SIZE (imode
);
9412 result
= gen_lowpart_common (omode
, x
);
9414 #ifdef CANNOT_CHANGE_MODE_CLASS
9415 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9416 record_subregs_of_mode (result
);
9426 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9428 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9431 /* If we want to refer to something bigger than the original memref,
9432 generate a paradoxical subreg instead. That will force a reload
9433 of the original memref X. */
9435 return gen_rtx_SUBREG (omode
, x
, 0);
9437 if (WORDS_BIG_ENDIAN
)
9438 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9440 /* Adjust the address so that the address-after-the-data is
9442 if (BYTES_BIG_ENDIAN
)
9443 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9445 return adjust_address_nv (x
, omode
, offset
);
9448 /* If X is a comparison operator, rewrite it in a new mode. This
9449 probably won't match, but may allow further simplifications. */
9450 else if (COMPARISON_P (x
))
9451 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9453 /* If we couldn't simplify X any other way, just enclose it in a
9454 SUBREG. Normally, this SUBREG won't match, but some patterns may
9455 include an explicit SUBREG or we may simplify it further in combine. */
9461 offset
= subreg_lowpart_offset (omode
, imode
);
9462 if (imode
== VOIDmode
)
9464 imode
= int_mode_for_mode (omode
);
9465 x
= gen_lowpart_common (imode
, x
);
9469 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9475 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9478 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9479 comparison code that will be tested.
9481 The result is a possibly different comparison code to use. *POP0 and
9482 *POP1 may be updated.
9484 It is possible that we might detect that a comparison is either always
9485 true or always false. However, we do not perform general constant
9486 folding in combine, so this knowledge isn't useful. Such tautologies
9487 should have been detected earlier. Hence we ignore all such cases. */
9489 static enum rtx_code
9490 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9496 enum machine_mode mode
, tmode
;
9498 /* Try a few ways of applying the same transformation to both operands. */
9501 #ifndef WORD_REGISTER_OPERATIONS
9502 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9503 so check specially. */
9504 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9505 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9506 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9507 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9508 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9509 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9510 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9511 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9512 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9513 && XEXP (op0
, 1) == XEXP (op1
, 1)
9514 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9515 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9516 && (INTVAL (XEXP (op0
, 1))
9517 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9519 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9521 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9522 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9526 /* If both operands are the same constant shift, see if we can ignore the
9527 shift. We can if the shift is a rotate or if the bits shifted out of
9528 this shift are known to be zero for both inputs and if the type of
9529 comparison is compatible with the shift. */
9530 if (GET_CODE (op0
) == GET_CODE (op1
)
9531 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9532 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9533 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9534 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9535 || (GET_CODE (op0
) == ASHIFTRT
9536 && (code
!= GTU
&& code
!= LTU
9537 && code
!= GEU
&& code
!= LEU
)))
9538 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9539 && INTVAL (XEXP (op0
, 1)) >= 0
9540 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9541 && XEXP (op0
, 1) == XEXP (op1
, 1))
9543 enum machine_mode mode
= GET_MODE (op0
);
9544 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9545 int shift_count
= INTVAL (XEXP (op0
, 1));
9547 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9548 mask
&= (mask
>> shift_count
) << shift_count
;
9549 else if (GET_CODE (op0
) == ASHIFT
)
9550 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9552 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9553 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9554 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9559 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9560 SUBREGs are of the same mode, and, in both cases, the AND would
9561 be redundant if the comparison was done in the narrower mode,
9562 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9563 and the operand's possibly nonzero bits are 0xffffff01; in that case
9564 if we only care about QImode, we don't need the AND). This case
9565 occurs if the output mode of an scc insn is not SImode and
9566 STORE_FLAG_VALUE == 1 (e.g., the 386).
9568 Similarly, check for a case where the AND's are ZERO_EXTEND
9569 operations from some narrower mode even though a SUBREG is not
9572 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9573 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9574 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9576 rtx inner_op0
= XEXP (op0
, 0);
9577 rtx inner_op1
= XEXP (op1
, 0);
9578 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9579 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9582 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9583 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9584 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9585 && (GET_MODE (SUBREG_REG (inner_op0
))
9586 == GET_MODE (SUBREG_REG (inner_op1
)))
9587 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9588 <= HOST_BITS_PER_WIDE_INT
)
9589 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9590 GET_MODE (SUBREG_REG (inner_op0
)))))
9591 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9592 GET_MODE (SUBREG_REG (inner_op1
))))))
9594 op0
= SUBREG_REG (inner_op0
);
9595 op1
= SUBREG_REG (inner_op1
);
9597 /* The resulting comparison is always unsigned since we masked
9598 off the original sign bit. */
9599 code
= unsigned_condition (code
);
9605 for (tmode
= GET_CLASS_NARROWEST_MODE
9606 (GET_MODE_CLASS (GET_MODE (op0
)));
9607 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9608 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9610 op0
= gen_lowpart (tmode
, inner_op0
);
9611 op1
= gen_lowpart (tmode
, inner_op1
);
9612 code
= unsigned_condition (code
);
9621 /* If both operands are NOT, we can strip off the outer operation
9622 and adjust the comparison code for swapped operands; similarly for
9623 NEG, except that this must be an equality comparison. */
9624 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9625 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9626 && (code
== EQ
|| code
== NE
)))
9627 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9633 /* If the first operand is a constant, swap the operands and adjust the
9634 comparison code appropriately, but don't do this if the second operand
9635 is already a constant integer. */
9636 if (swap_commutative_operands_p (op0
, op1
))
9638 tem
= op0
, op0
= op1
, op1
= tem
;
9639 code
= swap_condition (code
);
9642 /* We now enter a loop during which we will try to simplify the comparison.
9643 For the most part, we only are concerned with comparisons with zero,
9644 but some things may really be comparisons with zero but not start
9645 out looking that way. */
9647 while (GET_CODE (op1
) == CONST_INT
)
9649 enum machine_mode mode
= GET_MODE (op0
);
9650 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9651 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9652 int equality_comparison_p
;
9653 int sign_bit_comparison_p
;
9654 int unsigned_comparison_p
;
9655 HOST_WIDE_INT const_op
;
9657 /* We only want to handle integral modes. This catches VOIDmode,
9658 CCmode, and the floating-point modes. An exception is that we
9659 can handle VOIDmode if OP0 is a COMPARE or a comparison
9662 if (GET_MODE_CLASS (mode
) != MODE_INT
9663 && ! (mode
== VOIDmode
9664 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9667 /* Get the constant we are comparing against and turn off all bits
9668 not on in our mode. */
9669 const_op
= INTVAL (op1
);
9670 if (mode
!= VOIDmode
)
9671 const_op
= trunc_int_for_mode (const_op
, mode
);
9672 op1
= GEN_INT (const_op
);
9674 /* If we are comparing against a constant power of two and the value
9675 being compared can only have that single bit nonzero (e.g., it was
9676 `and'ed with that bit), we can replace this with a comparison
9679 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9680 || code
== LT
|| code
== LTU
)
9681 && mode_width
<= HOST_BITS_PER_WIDE_INT
9682 && exact_log2 (const_op
) >= 0
9683 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9685 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9686 op1
= const0_rtx
, const_op
= 0;
9689 /* Similarly, if we are comparing a value known to be either -1 or
9690 0 with -1, change it to the opposite comparison against zero. */
9693 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9694 || code
== GEU
|| code
== LTU
)
9695 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9697 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9698 op1
= const0_rtx
, const_op
= 0;
9701 /* Do some canonicalizations based on the comparison code. We prefer
9702 comparisons against zero and then prefer equality comparisons.
9703 If we can reduce the size of a constant, we will do that too. */
9708 /* < C is equivalent to <= (C - 1) */
9712 op1
= GEN_INT (const_op
);
9714 /* ... fall through to LE case below. */
9720 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9724 op1
= GEN_INT (const_op
);
9728 /* If we are doing a <= 0 comparison on a value known to have
9729 a zero sign bit, we can replace this with == 0. */
9730 else if (const_op
== 0
9731 && mode_width
<= HOST_BITS_PER_WIDE_INT
9732 && (nonzero_bits (op0
, mode
)
9733 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9738 /* >= C is equivalent to > (C - 1). */
9742 op1
= GEN_INT (const_op
);
9744 /* ... fall through to GT below. */
9750 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9754 op1
= GEN_INT (const_op
);
9758 /* If we are doing a > 0 comparison on a value known to have
9759 a zero sign bit, we can replace this with != 0. */
9760 else if (const_op
== 0
9761 && mode_width
<= HOST_BITS_PER_WIDE_INT
9762 && (nonzero_bits (op0
, mode
)
9763 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9768 /* < C is equivalent to <= (C - 1). */
9772 op1
= GEN_INT (const_op
);
9774 /* ... fall through ... */
9777 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9778 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9779 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9781 const_op
= 0, op1
= const0_rtx
;
9789 /* unsigned <= 0 is equivalent to == 0 */
9793 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9794 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9795 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9797 const_op
= 0, op1
= const0_rtx
;
9803 /* >= C is equivalent to > (C - 1). */
9807 op1
= GEN_INT (const_op
);
9809 /* ... fall through ... */
9812 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9813 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9814 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9816 const_op
= 0, op1
= const0_rtx
;
9824 /* unsigned > 0 is equivalent to != 0 */
9828 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9829 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9830 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9832 const_op
= 0, op1
= const0_rtx
;
9841 /* Compute some predicates to simplify code below. */
9843 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9844 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9845 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9848 /* If this is a sign bit comparison and we can do arithmetic in
9849 MODE, say that we will only be needing the sign bit of OP0. */
9850 if (sign_bit_comparison_p
9851 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9852 op0
= force_to_mode (op0
, mode
,
9854 << (GET_MODE_BITSIZE (mode
) - 1)),
9857 /* Now try cases based on the opcode of OP0. If none of the cases
9858 does a "continue", we exit this loop immediately after the
9861 switch (GET_CODE (op0
))
9864 /* If we are extracting a single bit from a variable position in
9865 a constant that has only a single bit set and are comparing it
9866 with zero, we can convert this into an equality comparison
9867 between the position and the location of the single bit. */
9868 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9869 have already reduced the shift count modulo the word size. */
9870 if (!SHIFT_COUNT_TRUNCATED
9871 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9872 && XEXP (op0
, 1) == const1_rtx
9873 && equality_comparison_p
&& const_op
== 0
9874 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9876 if (BITS_BIG_ENDIAN
)
9878 enum machine_mode new_mode
9879 = mode_for_extraction (EP_extzv
, 1);
9880 if (new_mode
== MAX_MACHINE_MODE
)
9881 i
= BITS_PER_WORD
- 1 - i
;
9885 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9889 op0
= XEXP (op0
, 2);
9893 /* Result is nonzero iff shift count is equal to I. */
9894 code
= reverse_condition (code
);
9898 /* ... fall through ... */
9901 tem
= expand_compound_operation (op0
);
9910 /* If testing for equality, we can take the NOT of the constant. */
9911 if (equality_comparison_p
9912 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9914 op0
= XEXP (op0
, 0);
9919 /* If just looking at the sign bit, reverse the sense of the
9921 if (sign_bit_comparison_p
)
9923 op0
= XEXP (op0
, 0);
9924 code
= (code
== GE
? LT
: GE
);
9930 /* If testing for equality, we can take the NEG of the constant. */
9931 if (equality_comparison_p
9932 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9934 op0
= XEXP (op0
, 0);
9939 /* The remaining cases only apply to comparisons with zero. */
9943 /* When X is ABS or is known positive,
9944 (neg X) is < 0 if and only if X != 0. */
9946 if (sign_bit_comparison_p
9947 && (GET_CODE (XEXP (op0
, 0)) == ABS
9948 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9949 && (nonzero_bits (XEXP (op0
, 0), mode
)
9950 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9952 op0
= XEXP (op0
, 0);
9953 code
= (code
== LT
? NE
: EQ
);
9957 /* If we have NEG of something whose two high-order bits are the
9958 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9959 if (num_sign_bit_copies (op0
, mode
) >= 2)
9961 op0
= XEXP (op0
, 0);
9962 code
= swap_condition (code
);
9968 /* If we are testing equality and our count is a constant, we
9969 can perform the inverse operation on our RHS. */
9970 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9971 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9972 op1
, XEXP (op0
, 1))) != 0)
9974 op0
= XEXP (op0
, 0);
9979 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9980 a particular bit. Convert it to an AND of a constant of that
9981 bit. This will be converted into a ZERO_EXTRACT. */
9982 if (const_op
== 0 && sign_bit_comparison_p
9983 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9984 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
9986 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
9989 - INTVAL (XEXP (op0
, 1)))));
9990 code
= (code
== LT
? NE
: EQ
);
9997 /* ABS is ignorable inside an equality comparison with zero. */
9998 if (const_op
== 0 && equality_comparison_p
)
10000 op0
= XEXP (op0
, 0);
10006 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10007 (compare FOO CONST) if CONST fits in FOO's mode and we
10008 are either testing inequality or have an unsigned
10009 comparison with ZERO_EXTEND or a signed comparison with
10010 SIGN_EXTEND. But don't do it if we don't have a compare
10011 insn of the given mode, since we'd have to revert it
10012 later on, and then we wouldn't know whether to sign- or
10014 mode
= GET_MODE (XEXP (op0
, 0));
10015 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10016 && ! unsigned_comparison_p
10017 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10018 && ((unsigned HOST_WIDE_INT
) const_op
10019 < (((unsigned HOST_WIDE_INT
) 1
10020 << (GET_MODE_BITSIZE (mode
) - 1))))
10021 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10023 op0
= XEXP (op0
, 0);
10029 /* Check for the case where we are comparing A - C1 with C2, that is
10031 (subreg:MODE (plus (A) (-C1))) op (C2)
10033 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10034 comparison in the wider mode. One of the following two conditions
10035 must be true in order for this to be valid:
10037 1. The mode extension results in the same bit pattern being added
10038 on both sides and the comparison is equality or unsigned. As
10039 C2 has been truncated to fit in MODE, the pattern can only be
10042 2. The mode extension results in the sign bit being copied on
10045 The difficulty here is that we have predicates for A but not for
10046 (A - C1) so we need to check that C1 is within proper bounds so
10047 as to perturbate A as little as possible. */
10049 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10050 && subreg_lowpart_p (op0
)
10051 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10052 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10053 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10055 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10056 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10057 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10060 && (unsigned HOST_WIDE_INT
) c1
10061 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10062 && (equality_comparison_p
|| unsigned_comparison_p
)
10063 /* (A - C1) zero-extends if it is positive and sign-extends
10064 if it is negative, C2 both zero- and sign-extends. */
10065 && ((0 == (nonzero_bits (a
, inner_mode
)
10066 & ~GET_MODE_MASK (mode
))
10068 /* (A - C1) sign-extends if it is positive and 1-extends
10069 if it is negative, C2 both sign- and 1-extends. */
10070 || (num_sign_bit_copies (a
, inner_mode
)
10071 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10074 || ((unsigned HOST_WIDE_INT
) c1
10075 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10076 /* (A - C1) always sign-extends, like C2. */
10077 && num_sign_bit_copies (a
, inner_mode
)
10078 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10079 - (mode_width
- 1))))
10081 op0
= SUBREG_REG (op0
);
10086 /* If the inner mode is narrower and we are extracting the low part,
10087 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10088 if (subreg_lowpart_p (op0
)
10089 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10090 /* Fall through */ ;
10094 /* ... fall through ... */
10097 mode
= GET_MODE (XEXP (op0
, 0));
10098 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10099 && (unsigned_comparison_p
|| equality_comparison_p
)
10100 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10101 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10102 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10104 op0
= XEXP (op0
, 0);
10110 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10111 this for equality comparisons due to pathological cases involving
10113 if (equality_comparison_p
10114 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10115 op1
, XEXP (op0
, 1))))
10117 op0
= XEXP (op0
, 0);
10122 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10123 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10124 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10126 op0
= XEXP (XEXP (op0
, 0), 0);
10127 code
= (code
== LT
? EQ
: NE
);
10133 /* We used to optimize signed comparisons against zero, but that
10134 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10135 arrive here as equality comparisons, or (GEU, LTU) are
10136 optimized away. No need to special-case them. */
10138 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10139 (eq B (minus A C)), whichever simplifies. We can only do
10140 this for equality comparisons due to pathological cases involving
10142 if (equality_comparison_p
10143 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10144 XEXP (op0
, 1), op1
)))
10146 op0
= XEXP (op0
, 0);
10151 if (equality_comparison_p
10152 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10153 XEXP (op0
, 0), op1
)))
10155 op0
= XEXP (op0
, 1);
10160 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10161 of bits in X minus 1, is one iff X > 0. */
10162 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10163 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10164 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10166 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10168 op0
= XEXP (op0
, 1);
10169 code
= (code
== GE
? LE
: GT
);
10175 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10176 if C is zero or B is a constant. */
10177 if (equality_comparison_p
10178 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10179 XEXP (op0
, 1), op1
)))
10181 op0
= XEXP (op0
, 0);
10188 case UNEQ
: case LTGT
:
10189 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10190 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10191 case UNORDERED
: case ORDERED
:
10192 /* We can't do anything if OP0 is a condition code value, rather
10193 than an actual data value. */
10195 || CC0_P (XEXP (op0
, 0))
10196 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10199 /* Get the two operands being compared. */
10200 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10201 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10203 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10205 /* Check for the cases where we simply want the result of the
10206 earlier test or the opposite of that result. */
10207 if (code
== NE
|| code
== EQ
10208 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10209 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10210 && (STORE_FLAG_VALUE
10211 & (((HOST_WIDE_INT
) 1
10212 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10213 && (code
== LT
|| code
== GE
)))
10215 enum rtx_code new_code
;
10216 if (code
== LT
|| code
== NE
)
10217 new_code
= GET_CODE (op0
);
10219 new_code
= reversed_comparison_code (op0
, NULL
);
10221 if (new_code
!= UNKNOWN
)
10232 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10234 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10235 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10236 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10238 op0
= XEXP (op0
, 1);
10239 code
= (code
== GE
? GT
: LE
);
10245 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10246 will be converted to a ZERO_EXTRACT later. */
10247 if (const_op
== 0 && equality_comparison_p
10248 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10249 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10251 op0
= simplify_and_const_int
10252 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
10254 XEXP (XEXP (op0
, 0), 1)),
10255 (HOST_WIDE_INT
) 1);
10259 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10260 zero and X is a comparison and C1 and C2 describe only bits set
10261 in STORE_FLAG_VALUE, we can compare with X. */
10262 if (const_op
== 0 && equality_comparison_p
10263 && mode_width
<= HOST_BITS_PER_WIDE_INT
10264 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10265 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10266 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10267 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10268 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10270 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10271 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10272 if ((~STORE_FLAG_VALUE
& mask
) == 0
10273 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10274 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10275 && COMPARISON_P (tem
))))
10277 op0
= XEXP (XEXP (op0
, 0), 0);
10282 /* If we are doing an equality comparison of an AND of a bit equal
10283 to the sign bit, replace this with a LT or GE comparison of
10284 the underlying value. */
10285 if (equality_comparison_p
10287 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10288 && mode_width
<= HOST_BITS_PER_WIDE_INT
10289 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10290 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10292 op0
= XEXP (op0
, 0);
10293 code
= (code
== EQ
? GE
: LT
);
10297 /* If this AND operation is really a ZERO_EXTEND from a narrower
10298 mode, the constant fits within that mode, and this is either an
10299 equality or unsigned comparison, try to do this comparison in
10300 the narrower mode. */
10301 if ((equality_comparison_p
|| unsigned_comparison_p
)
10302 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10303 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10304 & GET_MODE_MASK (mode
))
10306 && const_op
>> i
== 0
10307 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10309 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10313 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10314 fits in both M1 and M2 and the SUBREG is either paradoxical
10315 or represents the low part, permute the SUBREG and the AND
10317 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10319 unsigned HOST_WIDE_INT c1
;
10320 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10321 /* Require an integral mode, to avoid creating something like
10323 if (SCALAR_INT_MODE_P (tmode
)
10324 /* It is unsafe to commute the AND into the SUBREG if the
10325 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10326 not defined. As originally written the upper bits
10327 have a defined value due to the AND operation.
10328 However, if we commute the AND inside the SUBREG then
10329 they no longer have defined values and the meaning of
10330 the code has been changed. */
10332 #ifdef WORD_REGISTER_OPERATIONS
10333 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10334 && mode_width
<= BITS_PER_WORD
)
10336 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10337 && subreg_lowpart_p (XEXP (op0
, 0))))
10338 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10339 && mode_width
<= HOST_BITS_PER_WIDE_INT
10340 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10341 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10342 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10344 && c1
!= GET_MODE_MASK (tmode
))
10346 op0
= simplify_gen_binary (AND
, tmode
,
10347 SUBREG_REG (XEXP (op0
, 0)),
10348 gen_int_mode (c1
, tmode
));
10349 op0
= gen_lowpart (mode
, op0
);
10354 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10355 if (const_op
== 0 && equality_comparison_p
10356 && XEXP (op0
, 1) == const1_rtx
10357 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10359 op0
= simplify_and_const_int
10360 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10361 code
= (code
== NE
? EQ
: NE
);
10365 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10366 (eq (and (lshiftrt X) 1) 0).
10367 Also handle the case where (not X) is expressed using xor. */
10368 if (const_op
== 0 && equality_comparison_p
10369 && XEXP (op0
, 1) == const1_rtx
10370 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10372 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10373 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10375 if (GET_CODE (shift_op
) == NOT
10376 || (GET_CODE (shift_op
) == XOR
10377 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10378 && GET_CODE (shift_count
) == CONST_INT
10379 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10380 && (INTVAL (XEXP (shift_op
, 1))
10381 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10383 op0
= simplify_and_const_int
10385 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10386 (HOST_WIDE_INT
) 1);
10387 code
= (code
== NE
? EQ
: NE
);
10394 /* If we have (compare (ashift FOO N) (const_int C)) and
10395 the high order N bits of FOO (N+1 if an inequality comparison)
10396 are known to be zero, we can do this by comparing FOO with C
10397 shifted right N bits so long as the low-order N bits of C are
10399 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10400 && INTVAL (XEXP (op0
, 1)) >= 0
10401 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10402 < HOST_BITS_PER_WIDE_INT
)
10404 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10405 && mode_width
<= HOST_BITS_PER_WIDE_INT
10406 && (nonzero_bits (XEXP (op0
, 0), mode
)
10407 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10408 + ! equality_comparison_p
))) == 0)
10410 /* We must perform a logical shift, not an arithmetic one,
10411 as we want the top N bits of C to be zero. */
10412 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10414 temp
>>= INTVAL (XEXP (op0
, 1));
10415 op1
= gen_int_mode (temp
, mode
);
10416 op0
= XEXP (op0
, 0);
10420 /* If we are doing a sign bit comparison, it means we are testing
10421 a particular bit. Convert it to the appropriate AND. */
10422 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10423 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10425 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10428 - INTVAL (XEXP (op0
, 1)))));
10429 code
= (code
== LT
? NE
: EQ
);
10433 /* If this an equality comparison with zero and we are shifting
10434 the low bit to the sign bit, we can convert this to an AND of the
10436 if (const_op
== 0 && equality_comparison_p
10437 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10438 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10441 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10442 (HOST_WIDE_INT
) 1);
10448 /* If this is an equality comparison with zero, we can do this
10449 as a logical shift, which might be much simpler. */
10450 if (equality_comparison_p
&& const_op
== 0
10451 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10453 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10455 INTVAL (XEXP (op0
, 1)));
10459 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10460 do the comparison in a narrower mode. */
10461 if (! unsigned_comparison_p
10462 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10463 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10464 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10465 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10466 MODE_INT
, 1)) != BLKmode
10467 && (((unsigned HOST_WIDE_INT
) const_op
10468 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10469 <= GET_MODE_MASK (tmode
)))
10471 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10475 /* Likewise if OP0 is a PLUS of a sign extension with a
10476 constant, which is usually represented with the PLUS
10477 between the shifts. */
10478 if (! unsigned_comparison_p
10479 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10480 && GET_CODE (XEXP (op0
, 0)) == PLUS
10481 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10482 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10483 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10484 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10485 MODE_INT
, 1)) != BLKmode
10486 && (((unsigned HOST_WIDE_INT
) const_op
10487 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10488 <= GET_MODE_MASK (tmode
)))
10490 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10491 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10492 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10493 add_const
, XEXP (op0
, 1));
10495 op0
= simplify_gen_binary (PLUS
, tmode
,
10496 gen_lowpart (tmode
, inner
),
10501 /* ... fall through ... */
10503 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10504 the low order N bits of FOO are known to be zero, we can do this
10505 by comparing FOO with C shifted left N bits so long as no
10506 overflow occurs. */
10507 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10508 && INTVAL (XEXP (op0
, 1)) >= 0
10509 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10510 && mode_width
<= HOST_BITS_PER_WIDE_INT
10511 && (nonzero_bits (XEXP (op0
, 0), mode
)
10512 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10513 && (((unsigned HOST_WIDE_INT
) const_op
10514 + (GET_CODE (op0
) != LSHIFTRT
10515 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10518 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10520 /* If the shift was logical, then we must make the condition
10522 if (GET_CODE (op0
) == LSHIFTRT
)
10523 code
= unsigned_condition (code
);
10525 const_op
<<= INTVAL (XEXP (op0
, 1));
10526 op1
= GEN_INT (const_op
);
10527 op0
= XEXP (op0
, 0);
10531 /* If we are using this shift to extract just the sign bit, we
10532 can replace this with an LT or GE comparison. */
10534 && (equality_comparison_p
|| sign_bit_comparison_p
)
10535 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10536 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10539 op0
= XEXP (op0
, 0);
10540 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10552 /* Now make any compound operations involved in this comparison. Then,
10553 check for an outmost SUBREG on OP0 that is not doing anything or is
10554 paradoxical. The latter transformation must only be performed when
10555 it is known that the "extra" bits will be the same in op0 and op1 or
10556 that they don't matter. There are three cases to consider:
10558 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10559 care bits and we can assume they have any convenient value. So
10560 making the transformation is safe.
10562 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10563 In this case the upper bits of op0 are undefined. We should not make
10564 the simplification in that case as we do not know the contents of
10567 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10568 UNKNOWN. In that case we know those bits are zeros or ones. We must
10569 also be sure that they are the same as the upper bits of op1.
10571 We can never remove a SUBREG for a non-equality comparison because
10572 the sign bit is in a different place in the underlying object. */
10574 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10575 op1
= make_compound_operation (op1
, SET
);
10577 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10578 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10579 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10580 && (code
== NE
|| code
== EQ
))
10582 if (GET_MODE_SIZE (GET_MODE (op0
))
10583 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10585 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10587 if (REG_P (SUBREG_REG (op0
)))
10589 op0
= SUBREG_REG (op0
);
10590 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10593 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10594 <= HOST_BITS_PER_WIDE_INT
)
10595 && (nonzero_bits (SUBREG_REG (op0
),
10596 GET_MODE (SUBREG_REG (op0
)))
10597 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10599 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10601 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10602 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10603 op0
= SUBREG_REG (op0
), op1
= tem
;
10607 /* We now do the opposite procedure: Some machines don't have compare
10608 insns in all modes. If OP0's mode is an integer mode smaller than a
10609 word and we can't do a compare in that mode, see if there is a larger
10610 mode for which we can do the compare. There are a number of cases in
10611 which we can use the wider mode. */
10613 mode
= GET_MODE (op0
);
10614 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10615 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10616 && ! have_insn_for (COMPARE
, mode
))
10617 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10619 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10620 tmode
= GET_MODE_WIDER_MODE (tmode
))
10621 if (have_insn_for (COMPARE
, tmode
))
10625 /* If the only nonzero bits in OP0 and OP1 are those in the
10626 narrower mode and this is an equality or unsigned comparison,
10627 we can use the wider mode. Similarly for sign-extended
10628 values, in which case it is true for all comparisons. */
10629 zero_extended
= ((code
== EQ
|| code
== NE
10630 || code
== GEU
|| code
== GTU
10631 || code
== LEU
|| code
== LTU
)
10632 && (nonzero_bits (op0
, tmode
)
10633 & ~GET_MODE_MASK (mode
)) == 0
10634 && ((GET_CODE (op1
) == CONST_INT
10635 || (nonzero_bits (op1
, tmode
)
10636 & ~GET_MODE_MASK (mode
)) == 0)));
10639 || ((num_sign_bit_copies (op0
, tmode
)
10640 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10641 - GET_MODE_BITSIZE (mode
)))
10642 && (num_sign_bit_copies (op1
, tmode
)
10643 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10644 - GET_MODE_BITSIZE (mode
)))))
10646 /* If OP0 is an AND and we don't have an AND in MODE either,
10647 make a new AND in the proper mode. */
10648 if (GET_CODE (op0
) == AND
10649 && !have_insn_for (AND
, mode
))
10650 op0
= simplify_gen_binary (AND
, tmode
,
10651 gen_lowpart (tmode
,
10653 gen_lowpart (tmode
,
10656 op0
= gen_lowpart (tmode
, op0
);
10657 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10658 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10659 op1
= gen_lowpart (tmode
, op1
);
10663 /* If this is a test for negative, we can make an explicit
10664 test of the sign bit. */
10666 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10667 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10669 op0
= simplify_gen_binary (AND
, tmode
,
10670 gen_lowpart (tmode
, op0
),
10671 GEN_INT ((HOST_WIDE_INT
) 1
10672 << (GET_MODE_BITSIZE (mode
)
10674 code
= (code
== LT
) ? NE
: EQ
;
10679 #ifdef CANONICALIZE_COMPARISON
10680 /* If this machine only supports a subset of valid comparisons, see if we
10681 can convert an unsupported one into a supported one. */
10682 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10691 /* Utility function for record_value_for_reg. Count number of
10696 enum rtx_code code
= GET_CODE (x
);
10700 if (GET_RTX_CLASS (code
) == '2'
10701 || GET_RTX_CLASS (code
) == 'c')
10703 rtx x0
= XEXP (x
, 0);
10704 rtx x1
= XEXP (x
, 1);
10707 return 1 + 2 * count_rtxs (x0
);
10709 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10710 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10711 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10712 return 2 + 2 * count_rtxs (x0
)
10713 + count_rtxs (x
== XEXP (x1
, 0)
10714 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10716 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10717 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10718 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10719 return 2 + 2 * count_rtxs (x1
)
10720 + count_rtxs (x
== XEXP (x0
, 0)
10721 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10724 fmt
= GET_RTX_FORMAT (code
);
10725 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10727 ret
+= count_rtxs (XEXP (x
, i
));
10732 /* Utility function for following routine. Called when X is part of a value
10733 being stored into last_set_value. Sets last_set_table_tick
10734 for each register mentioned. Similar to mention_regs in cse.c */
10737 update_table_tick (rtx x
)
10739 enum rtx_code code
= GET_CODE (x
);
10740 const char *fmt
= GET_RTX_FORMAT (code
);
10745 unsigned int regno
= REGNO (x
);
10746 unsigned int endregno
10747 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10748 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10751 for (r
= regno
; r
< endregno
; r
++)
10752 reg_stat
[r
].last_set_table_tick
= label_tick
;
10757 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10758 /* Note that we can't have an "E" in values stored; see
10759 get_last_value_validate. */
10762 /* Check for identical subexpressions. If x contains
10763 identical subexpression we only have to traverse one of
10765 if (i
== 0 && ARITHMETIC_P (x
))
10767 /* Note that at this point x1 has already been
10769 rtx x0
= XEXP (x
, 0);
10770 rtx x1
= XEXP (x
, 1);
10772 /* If x0 and x1 are identical then there is no need to
10777 /* If x0 is identical to a subexpression of x1 then while
10778 processing x1, x0 has already been processed. Thus we
10779 are done with x. */
10780 if (ARITHMETIC_P (x1
)
10781 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10784 /* If x1 is identical to a subexpression of x0 then we
10785 still have to process the rest of x0. */
10786 if (ARITHMETIC_P (x0
)
10787 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10789 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10794 update_table_tick (XEXP (x
, i
));
10798 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10799 are saying that the register is clobbered and we no longer know its
10800 value. If INSN is zero, don't update reg_stat[].last_set; this is
10801 only permitted with VALUE also zero and is used to invalidate the
10805 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10807 unsigned int regno
= REGNO (reg
);
10808 unsigned int endregno
10809 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10810 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10813 /* If VALUE contains REG and we have a previous value for REG, substitute
10814 the previous value. */
10815 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10819 /* Set things up so get_last_value is allowed to see anything set up to
10821 subst_low_cuid
= INSN_CUID (insn
);
10822 tem
= get_last_value (reg
);
10824 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10825 it isn't going to be useful and will take a lot of time to process,
10826 so just use the CLOBBER. */
10830 if (ARITHMETIC_P (tem
)
10831 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10832 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10833 tem
= XEXP (tem
, 0);
10834 else if (count_occurrences (value
, reg
, 1) >= 2)
10836 /* If there are two or more occurrences of REG in VALUE,
10837 prevent the value from growing too much. */
10838 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10839 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10842 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10846 /* For each register modified, show we don't know its value, that
10847 we don't know about its bitwise content, that its value has been
10848 updated, and that we don't know the location of the death of the
10850 for (i
= regno
; i
< endregno
; i
++)
10853 reg_stat
[i
].last_set
= insn
;
10855 reg_stat
[i
].last_set_value
= 0;
10856 reg_stat
[i
].last_set_mode
= 0;
10857 reg_stat
[i
].last_set_nonzero_bits
= 0;
10858 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10859 reg_stat
[i
].last_death
= 0;
10860 reg_stat
[i
].truncated_to_mode
= 0;
10863 /* Mark registers that are being referenced in this value. */
10865 update_table_tick (value
);
10867 /* Now update the status of each register being set.
10868 If someone is using this register in this block, set this register
10869 to invalid since we will get confused between the two lives in this
10870 basic block. This makes using this register always invalid. In cse, we
10871 scan the table to invalidate all entries using this register, but this
10872 is too much work for us. */
10874 for (i
= regno
; i
< endregno
; i
++)
10876 reg_stat
[i
].last_set_label
= label_tick
;
10877 if (!insn
|| (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
))
10878 reg_stat
[i
].last_set_invalid
= 1;
10880 reg_stat
[i
].last_set_invalid
= 0;
10883 /* The value being assigned might refer to X (like in "x++;"). In that
10884 case, we must replace it with (clobber (const_int 0)) to prevent
10886 if (value
&& ! get_last_value_validate (&value
, insn
,
10887 reg_stat
[regno
].last_set_label
, 0))
10889 value
= copy_rtx (value
);
10890 if (! get_last_value_validate (&value
, insn
,
10891 reg_stat
[regno
].last_set_label
, 1))
10895 /* For the main register being modified, update the value, the mode, the
10896 nonzero bits, and the number of sign bit copies. */
10898 reg_stat
[regno
].last_set_value
= value
;
10902 enum machine_mode mode
= GET_MODE (reg
);
10903 subst_low_cuid
= INSN_CUID (insn
);
10904 reg_stat
[regno
].last_set_mode
= mode
;
10905 if (GET_MODE_CLASS (mode
) == MODE_INT
10906 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10907 mode
= nonzero_bits_mode
;
10908 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10909 reg_stat
[regno
].last_set_sign_bit_copies
10910 = num_sign_bit_copies (value
, GET_MODE (reg
));
10914 /* Called via note_stores from record_dead_and_set_regs to handle one
10915 SET or CLOBBER in an insn. DATA is the instruction in which the
10916 set is occurring. */
10919 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10921 rtx record_dead_insn
= (rtx
) data
;
10923 if (GET_CODE (dest
) == SUBREG
)
10924 dest
= SUBREG_REG (dest
);
10926 if (!record_dead_insn
)
10929 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
10935 /* If we are setting the whole register, we know its value. Otherwise
10936 show that we don't know the value. We can handle SUBREG in
10938 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10939 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10940 else if (GET_CODE (setter
) == SET
10941 && GET_CODE (SET_DEST (setter
)) == SUBREG
10942 && SUBREG_REG (SET_DEST (setter
)) == dest
10943 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10944 && subreg_lowpart_p (SET_DEST (setter
)))
10945 record_value_for_reg (dest
, record_dead_insn
,
10946 gen_lowpart (GET_MODE (dest
),
10947 SET_SRC (setter
)));
10949 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10951 else if (MEM_P (dest
)
10952 /* Ignore pushes, they clobber nothing. */
10953 && ! push_operand (dest
, GET_MODE (dest
)))
10954 mem_last_set
= INSN_CUID (record_dead_insn
);
10957 /* Update the records of when each REG was most recently set or killed
10958 for the things done by INSN. This is the last thing done in processing
10959 INSN in the combiner loop.
10961 We update reg_stat[], in particular fields last_set, last_set_value,
10962 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10963 last_death, and also the similar information mem_last_set (which insn
10964 most recently modified memory) and last_call_cuid (which insn was the
10965 most recent subroutine call). */
10968 record_dead_and_set_regs (rtx insn
)
10973 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10975 if (REG_NOTE_KIND (link
) == REG_DEAD
10976 && REG_P (XEXP (link
, 0)))
10978 unsigned int regno
= REGNO (XEXP (link
, 0));
10979 unsigned int endregno
10980 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10981 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
10984 for (i
= regno
; i
< endregno
; i
++)
10985 reg_stat
[i
].last_death
= insn
;
10987 else if (REG_NOTE_KIND (link
) == REG_INC
)
10988 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10993 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10994 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
10996 reg_stat
[i
].last_set_value
= 0;
10997 reg_stat
[i
].last_set_mode
= 0;
10998 reg_stat
[i
].last_set_nonzero_bits
= 0;
10999 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11000 reg_stat
[i
].last_death
= 0;
11001 reg_stat
[i
].truncated_to_mode
= 0;
11004 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11006 /* We can't combine into a call pattern. Remember, though, that
11007 the return value register is set at this CUID. We could
11008 still replace a register with the return value from the
11009 wrong subroutine call! */
11010 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
11013 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11016 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11017 register present in the SUBREG, so for each such SUBREG go back and
11018 adjust nonzero and sign bit information of the registers that are
11019 known to have some zero/sign bits set.
11021 This is needed because when combine blows the SUBREGs away, the
11022 information on zero/sign bits is lost and further combines can be
11023 missed because of that. */
11026 record_promoted_value (rtx insn
, rtx subreg
)
11029 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11030 enum machine_mode mode
= GET_MODE (subreg
);
11032 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11035 for (links
= LOG_LINKS (insn
); links
;)
11037 insn
= XEXP (links
, 0);
11038 set
= single_set (insn
);
11040 if (! set
|| !REG_P (SET_DEST (set
))
11041 || REGNO (SET_DEST (set
)) != regno
11042 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11044 links
= XEXP (links
, 1);
11048 if (reg_stat
[regno
].last_set
== insn
)
11050 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11051 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11054 if (REG_P (SET_SRC (set
)))
11056 regno
= REGNO (SET_SRC (set
));
11057 links
= LOG_LINKS (insn
);
11064 /* Check if X, a register, is known to contain a value already
11065 truncated to MODE. In this case we can use a subreg to refer to
11066 the truncated value even though in the generic case we would need
11067 an explicit truncation. */
11070 reg_truncated_to_mode (enum machine_mode mode
, rtx x
)
11072 enum machine_mode truncated
= reg_stat
[REGNO (x
)].truncated_to_mode
;
11074 if (truncated
== 0 || reg_stat
[REGNO (x
)].truncation_label
!= label_tick
)
11076 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
11078 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
11079 GET_MODE_BITSIZE (truncated
)))
11084 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11085 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11086 a truncate into a subreg using this information. */
11089 record_truncated_value (rtx x
)
11091 enum machine_mode truncated_mode
;
11093 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
11095 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
11096 truncated_mode
= GET_MODE (x
);
11098 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
11101 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
11102 GET_MODE_BITSIZE (original_mode
)))
11105 x
= SUBREG_REG (x
);
11107 /* ??? For hard-regs we now record everthing. We might be able to
11108 optimize this using last_set_mode. */
11109 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
11110 truncated_mode
= GET_MODE (x
);
11114 if (reg_stat
[REGNO (x
)].truncated_to_mode
== 0
11115 || reg_stat
[REGNO (x
)].truncation_label
< label_tick
11116 || (GET_MODE_SIZE (truncated_mode
)
11117 < GET_MODE_SIZE (reg_stat
[REGNO (x
)].truncated_to_mode
)))
11119 reg_stat
[REGNO (x
)].truncated_to_mode
= truncated_mode
;
11120 reg_stat
[REGNO (x
)].truncation_label
= label_tick
;
11124 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11125 found, note what it implies to the registers used in it. */
11128 check_conversions (rtx insn
, rtx x
)
11130 if (GET_CODE (x
) == SUBREG
|| REG_P (x
))
11132 if (GET_CODE (x
) == SUBREG
11133 && SUBREG_PROMOTED_VAR_P (x
)
11134 && REG_P (SUBREG_REG (x
)))
11135 record_promoted_value (insn
, x
);
11137 record_truncated_value (x
);
11141 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11144 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11148 check_conversions (insn
, XEXP (x
, i
));
11152 if (XVEC (x
, i
) != 0)
11153 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11154 check_conversions (insn
, XVECEXP (x
, i
, j
));
11160 /* Utility routine for the following function. Verify that all the registers
11161 mentioned in *LOC are valid when *LOC was part of a value set when
11162 label_tick == TICK. Return 0 if some are not.
11164 If REPLACE is nonzero, replace the invalid reference with
11165 (clobber (const_int 0)) and return 1. This replacement is useful because
11166 we often can get useful information about the form of a value (e.g., if
11167 it was produced by a shift that always produces -1 or 0) even though
11168 we don't know exactly what registers it was produced from. */
11171 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11174 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11175 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11180 unsigned int regno
= REGNO (x
);
11181 unsigned int endregno
11182 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11183 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11186 for (j
= regno
; j
< endregno
; j
++)
11187 if (reg_stat
[j
].last_set_invalid
11188 /* If this is a pseudo-register that was only set once and not
11189 live at the beginning of the function, it is always valid. */
11190 || (! (regno
>= FIRST_PSEUDO_REGISTER
11191 && REG_N_SETS (regno
) == 1
11192 && (! REGNO_REG_SET_P
11193 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11195 && reg_stat
[j
].last_set_label
> tick
))
11198 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11204 /* If this is a memory reference, make sure that there were
11205 no stores after it that might have clobbered the value. We don't
11206 have alias info, so we assume any store invalidates it. */
11207 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11208 && INSN_CUID (insn
) <= mem_last_set
)
11211 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11215 for (i
= 0; i
< len
; i
++)
11219 /* Check for identical subexpressions. If x contains
11220 identical subexpression we only have to traverse one of
11222 if (i
== 1 && ARITHMETIC_P (x
))
11224 /* Note that at this point x0 has already been checked
11225 and found valid. */
11226 rtx x0
= XEXP (x
, 0);
11227 rtx x1
= XEXP (x
, 1);
11229 /* If x0 and x1 are identical then x is also valid. */
11233 /* If x1 is identical to a subexpression of x0 then
11234 while checking x0, x1 has already been checked. Thus
11235 it is valid and so as x. */
11236 if (ARITHMETIC_P (x0
)
11237 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11240 /* If x0 is identical to a subexpression of x1 then x is
11241 valid iff the rest of x1 is valid. */
11242 if (ARITHMETIC_P (x1
)
11243 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11245 get_last_value_validate (&XEXP (x1
,
11246 x0
== XEXP (x1
, 0) ? 1 : 0),
11247 insn
, tick
, replace
);
11250 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11254 /* Don't bother with these. They shouldn't occur anyway. */
11255 else if (fmt
[i
] == 'E')
11259 /* If we haven't found a reason for it to be invalid, it is valid. */
11263 /* Get the last value assigned to X, if known. Some registers
11264 in the value may be replaced with (clobber (const_int 0)) if their value
11265 is known longer known reliably. */
11268 get_last_value (rtx x
)
11270 unsigned int regno
;
11273 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11274 then convert it to the desired mode. If this is a paradoxical SUBREG,
11275 we cannot predict what values the "extra" bits might have. */
11276 if (GET_CODE (x
) == SUBREG
11277 && subreg_lowpart_p (x
)
11278 && (GET_MODE_SIZE (GET_MODE (x
))
11279 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11280 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11281 return gen_lowpart (GET_MODE (x
), value
);
11287 value
= reg_stat
[regno
].last_set_value
;
11289 /* If we don't have a value, or if it isn't for this basic block and
11290 it's either a hard register, set more than once, or it's a live
11291 at the beginning of the function, return 0.
11293 Because if it's not live at the beginning of the function then the reg
11294 is always set before being used (is never used without being set).
11295 And, if it's set only once, and it's always set before use, then all
11296 uses must have the same last value, even if it's not from this basic
11300 || (reg_stat
[regno
].last_set_label
!= label_tick
11301 && (regno
< FIRST_PSEUDO_REGISTER
11302 || REG_N_SETS (regno
) != 1
11303 || (REGNO_REG_SET_P
11304 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11308 /* If the value was set in a later insn than the ones we are processing,
11309 we can't use it even if the register was only set once. */
11310 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11313 /* If the value has all its registers valid, return it. */
11314 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11315 reg_stat
[regno
].last_set_label
, 0))
11318 /* Otherwise, make a copy and replace any invalid register with
11319 (clobber (const_int 0)). If that fails for some reason, return 0. */
11321 value
= copy_rtx (value
);
11322 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11323 reg_stat
[regno
].last_set_label
, 1))
11329 /* Return nonzero if expression X refers to a REG or to memory
11330 that is set in an instruction more recent than FROM_CUID. */
11333 use_crosses_set_p (rtx x
, int from_cuid
)
11337 enum rtx_code code
= GET_CODE (x
);
11341 unsigned int regno
= REGNO (x
);
11342 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11343 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11345 #ifdef PUSH_ROUNDING
11346 /* Don't allow uses of the stack pointer to be moved,
11347 because we don't know whether the move crosses a push insn. */
11348 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11351 for (; regno
< endreg
; regno
++)
11352 if (reg_stat
[regno
].last_set
11353 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11358 if (code
== MEM
&& mem_last_set
> from_cuid
)
11361 fmt
= GET_RTX_FORMAT (code
);
11363 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11368 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11369 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11372 else if (fmt
[i
] == 'e'
11373 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11379 /* Define three variables used for communication between the following
11382 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11383 static int reg_dead_flag
;
11385 /* Function called via note_stores from reg_dead_at_p.
11387 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11388 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11391 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11393 unsigned int regno
, endregno
;
11398 regno
= REGNO (dest
);
11399 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11400 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11402 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11403 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11406 /* Return nonzero if REG is known to be dead at INSN.
11408 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11409 referencing REG, it is dead. If we hit a SET referencing REG, it is
11410 live. Otherwise, see if it is live or dead at the start of the basic
11411 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11412 must be assumed to be always live. */
11415 reg_dead_at_p (rtx reg
, rtx insn
)
11420 /* Set variables for reg_dead_at_p_1. */
11421 reg_dead_regno
= REGNO (reg
);
11422 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11423 ? hard_regno_nregs
[reg_dead_regno
]
11429 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11430 we allow the machine description to decide whether use-and-clobber
11431 patterns are OK. */
11432 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11434 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11435 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11439 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11440 beginning of function. */
11441 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11442 insn
= prev_nonnote_insn (insn
))
11444 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11446 return reg_dead_flag
== 1 ? 1 : 0;
11448 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11452 /* Get the basic block that we were in. */
11454 block
= ENTRY_BLOCK_PTR
->next_bb
;
11457 FOR_EACH_BB (block
)
11458 if (insn
== BB_HEAD (block
))
11461 if (block
== EXIT_BLOCK_PTR
)
11465 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11466 if (REGNO_REG_SET_P (block
->il
.rtl
->global_live_at_start
, i
))
11472 /* Note hard registers in X that are used. This code is similar to
11473 that in flow.c, but much simpler since we don't care about pseudos. */
11476 mark_used_regs_combine (rtx x
)
11478 RTX_CODE code
= GET_CODE (x
);
11479 unsigned int regno
;
11492 case ADDR_DIFF_VEC
:
11495 /* CC0 must die in the insn after it is set, so we don't need to take
11496 special note of it here. */
11502 /* If we are clobbering a MEM, mark any hard registers inside the
11503 address as used. */
11504 if (MEM_P (XEXP (x
, 0)))
11505 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11510 /* A hard reg in a wide mode may really be multiple registers.
11511 If so, mark all of them just like the first. */
11512 if (regno
< FIRST_PSEUDO_REGISTER
)
11514 unsigned int endregno
, r
;
11516 /* None of this applies to the stack, frame or arg pointers. */
11517 if (regno
== STACK_POINTER_REGNUM
11518 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11519 || regno
== HARD_FRAME_POINTER_REGNUM
11521 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11522 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11524 || regno
== FRAME_POINTER_REGNUM
)
11527 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11528 for (r
= regno
; r
< endregno
; r
++)
11529 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11535 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11537 rtx testreg
= SET_DEST (x
);
11539 while (GET_CODE (testreg
) == SUBREG
11540 || GET_CODE (testreg
) == ZERO_EXTRACT
11541 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11542 testreg
= XEXP (testreg
, 0);
11544 if (MEM_P (testreg
))
11545 mark_used_regs_combine (XEXP (testreg
, 0));
11547 mark_used_regs_combine (SET_SRC (x
));
11555 /* Recursively scan the operands of this expression. */
11558 const char *fmt
= GET_RTX_FORMAT (code
);
11560 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11563 mark_used_regs_combine (XEXP (x
, i
));
11564 else if (fmt
[i
] == 'E')
11568 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11569 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11575 /* Remove register number REGNO from the dead registers list of INSN.
11577 Return the note used to record the death, if there was one. */
11580 remove_death (unsigned int regno
, rtx insn
)
11582 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11586 REG_N_DEATHS (regno
)--;
11587 remove_note (insn
, note
);
11593 /* For each register (hardware or pseudo) used within expression X, if its
11594 death is in an instruction with cuid between FROM_CUID (inclusive) and
11595 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11596 list headed by PNOTES.
11598 That said, don't move registers killed by maybe_kill_insn.
11600 This is done when X is being merged by combination into TO_INSN. These
11601 notes will then be distributed as needed. */
11604 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11609 enum rtx_code code
= GET_CODE (x
);
11613 unsigned int regno
= REGNO (x
);
11614 rtx where_dead
= reg_stat
[regno
].last_death
;
11615 rtx before_dead
, after_dead
;
11617 /* Don't move the register if it gets killed in between from and to. */
11618 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11619 && ! reg_referenced_p (x
, maybe_kill_insn
))
11622 /* WHERE_DEAD could be a USE insn made by combine, so first we
11623 make sure that we have insns with valid INSN_CUID values. */
11624 before_dead
= where_dead
;
11625 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11626 before_dead
= PREV_INSN (before_dead
);
11628 after_dead
= where_dead
;
11629 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11630 after_dead
= NEXT_INSN (after_dead
);
11632 if (before_dead
&& after_dead
11633 && INSN_CUID (before_dead
) >= from_cuid
11634 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11635 || (where_dead
!= after_dead
11636 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11638 rtx note
= remove_death (regno
, where_dead
);
11640 /* It is possible for the call above to return 0. This can occur
11641 when last_death points to I2 or I1 that we combined with.
11642 In that case make a new note.
11644 We must also check for the case where X is a hard register
11645 and NOTE is a death note for a range of hard registers
11646 including X. In that case, we must put REG_DEAD notes for
11647 the remaining registers in place of NOTE. */
11649 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11650 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11651 > GET_MODE_SIZE (GET_MODE (x
))))
11653 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11654 unsigned int deadend
11655 = (deadregno
+ hard_regno_nregs
[deadregno
]
11656 [GET_MODE (XEXP (note
, 0))]);
11657 unsigned int ourend
11658 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11661 for (i
= deadregno
; i
< deadend
; i
++)
11662 if (i
< regno
|| i
>= ourend
)
11663 REG_NOTES (where_dead
)
11664 = gen_rtx_EXPR_LIST (REG_DEAD
,
11666 REG_NOTES (where_dead
));
11669 /* If we didn't find any note, or if we found a REG_DEAD note that
11670 covers only part of the given reg, and we have a multi-reg hard
11671 register, then to be safe we must check for REG_DEAD notes
11672 for each register other than the first. They could have
11673 their own REG_DEAD notes lying around. */
11674 else if ((note
== 0
11676 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11677 < GET_MODE_SIZE (GET_MODE (x
)))))
11678 && regno
< FIRST_PSEUDO_REGISTER
11679 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11681 unsigned int ourend
11682 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11683 unsigned int i
, offset
;
11687 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11691 for (i
= regno
+ offset
; i
< ourend
; i
++)
11692 move_deaths (regno_reg_rtx
[i
],
11693 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11696 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11698 XEXP (note
, 1) = *pnotes
;
11702 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11704 REG_N_DEATHS (regno
)++;
11710 else if (GET_CODE (x
) == SET
)
11712 rtx dest
= SET_DEST (x
);
11714 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11716 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11717 that accesses one word of a multi-word item, some
11718 piece of everything register in the expression is used by
11719 this insn, so remove any old death. */
11720 /* ??? So why do we test for equality of the sizes? */
11722 if (GET_CODE (dest
) == ZERO_EXTRACT
11723 || GET_CODE (dest
) == STRICT_LOW_PART
11724 || (GET_CODE (dest
) == SUBREG
11725 && (((GET_MODE_SIZE (GET_MODE (dest
))
11726 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11727 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11728 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11730 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11734 /* If this is some other SUBREG, we know it replaces the entire
11735 value, so use that as the destination. */
11736 if (GET_CODE (dest
) == SUBREG
)
11737 dest
= SUBREG_REG (dest
);
11739 /* If this is a MEM, adjust deaths of anything used in the address.
11740 For a REG (the only other possibility), the entire value is
11741 being replaced so the old value is not used in this insn. */
11744 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11749 else if (GET_CODE (x
) == CLOBBER
)
11752 len
= GET_RTX_LENGTH (code
);
11753 fmt
= GET_RTX_FORMAT (code
);
11755 for (i
= 0; i
< len
; i
++)
11760 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11761 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11764 else if (fmt
[i
] == 'e')
11765 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11769 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11770 pattern of an insn. X must be a REG. */
11773 reg_bitfield_target_p (rtx x
, rtx body
)
11777 if (GET_CODE (body
) == SET
)
11779 rtx dest
= SET_DEST (body
);
11781 unsigned int regno
, tregno
, endregno
, endtregno
;
11783 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11784 target
= XEXP (dest
, 0);
11785 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11786 target
= SUBREG_REG (XEXP (dest
, 0));
11790 if (GET_CODE (target
) == SUBREG
)
11791 target
= SUBREG_REG (target
);
11793 if (!REG_P (target
))
11796 tregno
= REGNO (target
), regno
= REGNO (x
);
11797 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11798 return target
== x
;
11800 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11801 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11803 return endregno
> tregno
&& regno
< endtregno
;
11806 else if (GET_CODE (body
) == PARALLEL
)
11807 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11808 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11814 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11815 as appropriate. I3 and I2 are the insns resulting from the combination
11816 insns including FROM (I2 may be zero).
11818 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11819 not need REG_DEAD notes because they are being substituted for. This
11820 saves searching in the most common cases.
11822 Each note in the list is either ignored or placed on some insns, depending
11823 on the type of note. */
11826 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
11829 rtx note
, next_note
;
11832 for (note
= notes
; note
; note
= next_note
)
11834 rtx place
= 0, place2
= 0;
11836 next_note
= XEXP (note
, 1);
11837 switch (REG_NOTE_KIND (note
))
11841 /* Doesn't matter much where we put this, as long as it's somewhere.
11842 It is preferable to keep these notes on branches, which is most
11843 likely to be i3. */
11847 case REG_VALUE_PROFILE
:
11848 /* Just get rid of this note, as it is unused later anyway. */
11851 case REG_NON_LOCAL_GOTO
:
11856 gcc_assert (i2
&& JUMP_P (i2
));
11861 case REG_EH_REGION
:
11862 /* These notes must remain with the call or trapping instruction. */
11865 else if (i2
&& CALL_P (i2
))
11869 gcc_assert (flag_non_call_exceptions
);
11870 if (may_trap_p (i3
))
11872 else if (i2
&& may_trap_p (i2
))
11874 /* ??? Otherwise assume we've combined things such that we
11875 can now prove that the instructions can't trap. Drop the
11876 note in this case. */
11882 /* These notes must remain with the call. It should not be
11883 possible for both I2 and I3 to be a call. */
11888 gcc_assert (i2
&& CALL_P (i2
));
11894 /* Any clobbers for i3 may still exist, and so we must process
11895 REG_UNUSED notes from that insn.
11897 Any clobbers from i2 or i1 can only exist if they were added by
11898 recog_for_combine. In that case, recog_for_combine created the
11899 necessary REG_UNUSED notes. Trying to keep any original
11900 REG_UNUSED notes from these insns can cause incorrect output
11901 if it is for the same register as the original i3 dest.
11902 In that case, we will notice that the register is set in i3,
11903 and then add a REG_UNUSED note for the destination of i3, which
11904 is wrong. However, it is possible to have REG_UNUSED notes from
11905 i2 or i1 for register which were both used and clobbered, so
11906 we keep notes from i2 or i1 if they will turn into REG_DEAD
11909 /* If this register is set or clobbered in I3, put the note there
11910 unless there is one already. */
11911 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11913 if (from_insn
!= i3
)
11916 if (! (REG_P (XEXP (note
, 0))
11917 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11918 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11921 /* Otherwise, if this register is used by I3, then this register
11922 now dies here, so we must put a REG_DEAD note here unless there
11924 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11925 && ! (REG_P (XEXP (note
, 0))
11926 ? find_regno_note (i3
, REG_DEAD
,
11927 REGNO (XEXP (note
, 0)))
11928 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11930 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11938 /* These notes say something about results of an insn. We can
11939 only support them if they used to be on I3 in which case they
11940 remain on I3. Otherwise they are ignored.
11942 If the note refers to an expression that is not a constant, we
11943 must also ignore the note since we cannot tell whether the
11944 equivalence is still true. It might be possible to do
11945 slightly better than this (we only have a problem if I2DEST
11946 or I1DEST is present in the expression), but it doesn't
11947 seem worth the trouble. */
11949 if (from_insn
== i3
11950 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11955 case REG_NO_CONFLICT
:
11956 /* These notes say something about how a register is used. They must
11957 be present on any use of the register in I2 or I3. */
11958 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11961 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11971 /* This can show up in several ways -- either directly in the
11972 pattern, or hidden off in the constant pool with (or without?)
11973 a REG_EQUAL note. */
11974 /* ??? Ignore the without-reg_equal-note problem for now. */
11975 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11976 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11977 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11978 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11982 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11983 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11984 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11985 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11993 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11994 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11995 if (place
&& JUMP_P (place
))
11997 rtx label
= JUMP_LABEL (place
);
12000 JUMP_LABEL (place
) = XEXP (note
, 0);
12003 gcc_assert (label
== XEXP (note
, 0));
12004 if (LABEL_P (label
))
12005 LABEL_NUSES (label
)--;
12009 if (place2
&& JUMP_P (place2
))
12011 rtx label
= JUMP_LABEL (place2
);
12014 JUMP_LABEL (place2
) = XEXP (note
, 0);
12017 gcc_assert (label
== XEXP (note
, 0));
12018 if (LABEL_P (label
))
12019 LABEL_NUSES (label
)--;
12026 /* This note says something about the value of a register prior
12027 to the execution of an insn. It is too much trouble to see
12028 if the note is still correct in all situations. It is better
12029 to simply delete it. */
12033 /* If the insn previously containing this note still exists,
12034 put it back where it was. Otherwise move it to the previous
12035 insn. Adjust the corresponding REG_LIBCALL note. */
12036 if (!NOTE_P (from_insn
))
12040 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12041 place
= prev_real_insn (from_insn
);
12043 XEXP (tem
, 0) = place
;
12044 /* If we're deleting the last remaining instruction of a
12045 libcall sequence, don't add the notes. */
12046 else if (XEXP (note
, 0) == from_insn
)
12048 /* Don't add the dangling REG_RETVAL note. */
12055 /* This is handled similarly to REG_RETVAL. */
12056 if (!NOTE_P (from_insn
))
12060 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12061 place
= next_real_insn (from_insn
);
12063 XEXP (tem
, 0) = place
;
12064 /* If we're deleting the last remaining instruction of a
12065 libcall sequence, don't add the notes. */
12066 else if (XEXP (note
, 0) == from_insn
)
12068 /* Don't add the dangling REG_LIBCALL note. */
12075 /* If the register is used as an input in I3, it dies there.
12076 Similarly for I2, if it is nonzero and adjacent to I3.
12078 If the register is not used as an input in either I3 or I2
12079 and it is not one of the registers we were supposed to eliminate,
12080 there are two possibilities. We might have a non-adjacent I2
12081 or we might have somehow eliminated an additional register
12082 from a computation. For example, we might have had A & B where
12083 we discover that B will always be zero. In this case we will
12084 eliminate the reference to A.
12086 In both cases, we must search to see if we can find a previous
12087 use of A and put the death note there. */
12090 && CALL_P (from_insn
)
12091 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12093 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12095 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12096 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12100 && (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12101 || rtx_equal_p (XEXP (note
, 0), elim_i1
)))
12106 basic_block bb
= this_basic_block
;
12108 /* You might think you could search back from FROM_INSN
12109 rather than from I3, but combine tries to split invalid
12110 combined instructions. This can result in the old I2
12111 or I1 moving later in the insn sequence. */
12112 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12114 if (! INSN_P (tem
))
12116 if (tem
== BB_HEAD (bb
))
12121 /* If the register is being set at TEM, see if that is all
12122 TEM is doing. If so, delete TEM. Otherwise, make this
12123 into a REG_UNUSED note instead. Don't delete sets to
12124 global register vars. */
12125 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12126 || !global_regs
[REGNO (XEXP (note
, 0))])
12127 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12129 rtx set
= single_set (tem
);
12130 rtx inner_dest
= 0;
12132 rtx cc0_setter
= NULL_RTX
;
12136 for (inner_dest
= SET_DEST (set
);
12137 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12138 || GET_CODE (inner_dest
) == SUBREG
12139 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12140 inner_dest
= XEXP (inner_dest
, 0))
12143 /* Verify that it was the set, and not a clobber that
12144 modified the register.
12146 CC0 targets must be careful to maintain setter/user
12147 pairs. If we cannot delete the setter due to side
12148 effects, mark the user with an UNUSED note instead
12151 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12152 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12154 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12155 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12156 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12160 /* Move the notes and links of TEM elsewhere.
12161 This might delete other dead insns recursively.
12162 First set the pattern to something that won't use
12164 rtx old_notes
= REG_NOTES (tem
);
12166 PATTERN (tem
) = pc_rtx
;
12167 REG_NOTES (tem
) = NULL
;
12169 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
12170 NULL_RTX
, NULL_RTX
);
12171 distribute_links (LOG_LINKS (tem
));
12173 SET_INSN_DELETED (tem
);
12176 /* Delete the setter too. */
12179 PATTERN (cc0_setter
) = pc_rtx
;
12180 old_notes
= REG_NOTES (cc0_setter
);
12181 REG_NOTES (cc0_setter
) = NULL
;
12183 distribute_notes (old_notes
, cc0_setter
,
12184 cc0_setter
, NULL_RTX
,
12185 NULL_RTX
, NULL_RTX
);
12186 distribute_links (LOG_LINKS (cc0_setter
));
12188 SET_INSN_DELETED (cc0_setter
);
12194 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12196 /* If there isn't already a REG_UNUSED note, put one
12197 here. Do not place a REG_DEAD note, even if
12198 the register is also used here; that would not
12199 match the algorithm used in lifetime analysis
12200 and can cause the consistency check in the
12201 scheduler to fail. */
12202 if (! find_regno_note (tem
, REG_UNUSED
,
12203 REGNO (XEXP (note
, 0))))
12208 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12210 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12212 /* This may not be the correct place for the death
12213 note if FROM_INSN is before TEM, and the reg is
12214 set between FROM_INSN and TEM. The reg might
12215 die two or more times. An existing death note
12216 means we are looking at the wrong live range. */
12218 && INSN_CUID (from_insn
) < INSN_CUID (tem
)
12219 && find_regno_note (tem
, REG_DEAD
,
12220 REGNO (XEXP (note
, 0))))
12223 if (tem
== BB_HEAD (bb
))
12230 /* If we are doing a 3->2 combination, and we have a
12231 register which formerly died in i3 and was not used
12232 by i2, which now no longer dies in i3 and is used in
12233 i2 but does not die in i2, and place is between i2
12234 and i3, then we may need to move a link from place to
12236 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12237 && INSN_CUID (place
) > INSN_CUID (i2
)
12239 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12240 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12242 rtx links
= LOG_LINKS (place
);
12243 LOG_LINKS (place
) = 0;
12244 distribute_links (links
);
12249 if (tem
== BB_HEAD (bb
))
12253 /* We haven't found an insn for the death note and it
12254 is still a REG_DEAD note, but we have hit the beginning
12255 of the block. If the existing life info says the reg
12256 was dead, there's nothing left to do. Otherwise, we'll
12257 need to do a global life update after combine. */
12258 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12259 && REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
,
12260 REGNO (XEXP (note
, 0))))
12261 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12264 /* If the register is set or already dead at PLACE, we needn't do
12265 anything with this note if it is still a REG_DEAD note.
12266 We check here if it is set at all, not if is it totally replaced,
12267 which is what `dead_or_set_p' checks, so also check for it being
12270 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12272 unsigned int regno
= REGNO (XEXP (note
, 0));
12274 /* Similarly, if the instruction on which we want to place
12275 the note is a noop, we'll need do a global live update
12276 after we remove them in delete_noop_moves. */
12277 if (noop_move_p (place
))
12278 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12280 if (dead_or_set_p (place
, XEXP (note
, 0))
12281 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12283 /* Unless the register previously died in PLACE, clear
12284 last_death. [I no longer understand why this is
12286 if (reg_stat
[regno
].last_death
!= place
)
12287 reg_stat
[regno
].last_death
= 0;
12291 reg_stat
[regno
].last_death
= place
;
12293 /* If this is a death note for a hard reg that is occupying
12294 multiple registers, ensure that we are still using all
12295 parts of the object. If we find a piece of the object
12296 that is unused, we must arrange for an appropriate REG_DEAD
12297 note to be added for it. However, we can't just emit a USE
12298 and tag the note to it, since the register might actually
12299 be dead; so we recourse, and the recursive call then finds
12300 the previous insn that used this register. */
12302 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12303 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12305 unsigned int endregno
12306 = regno
+ hard_regno_nregs
[regno
]
12307 [GET_MODE (XEXP (note
, 0))];
12311 for (i
= regno
; i
< endregno
; i
++)
12312 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12313 && ! find_regno_fusage (place
, USE
, i
))
12314 || dead_or_set_regno_p (place
, i
))
12319 /* Put only REG_DEAD notes for pieces that are
12320 not already dead or set. */
12322 for (i
= regno
; i
< endregno
;
12323 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12325 rtx piece
= regno_reg_rtx
[i
];
12326 basic_block bb
= this_basic_block
;
12328 if (! dead_or_set_p (place
, piece
)
12329 && ! reg_bitfield_target_p (piece
,
12333 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12335 distribute_notes (new_note
, place
, place
,
12336 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12338 else if (! refers_to_regno_p (i
, i
+ 1,
12339 PATTERN (place
), 0)
12340 && ! find_regno_fusage (place
, USE
, i
))
12341 for (tem
= PREV_INSN (place
); ;
12342 tem
= PREV_INSN (tem
))
12344 if (! INSN_P (tem
))
12346 if (tem
== BB_HEAD (bb
))
12348 SET_BIT (refresh_blocks
,
12349 this_basic_block
->index
);
12354 if (dead_or_set_p (tem
, piece
)
12355 || reg_bitfield_target_p (piece
,
12359 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12374 /* Any other notes should not be present at this point in the
12376 gcc_unreachable ();
12381 XEXP (note
, 1) = REG_NOTES (place
);
12382 REG_NOTES (place
) = note
;
12384 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12385 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12386 && REG_P (XEXP (note
, 0)))
12387 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12391 if ((REG_NOTE_KIND (note
) == REG_DEAD
12392 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12393 && REG_P (XEXP (note
, 0)))
12394 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12396 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12397 REG_NOTE_KIND (note
),
12399 REG_NOTES (place2
));
12404 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12405 I3, I2, and I1 to new locations. This is also called to add a link
12406 pointing at I3 when I3's destination is changed. */
12409 distribute_links (rtx links
)
12411 rtx link
, next_link
;
12413 for (link
= links
; link
; link
= next_link
)
12419 next_link
= XEXP (link
, 1);
12421 /* If the insn that this link points to is a NOTE or isn't a single
12422 set, ignore it. In the latter case, it isn't clear what we
12423 can do other than ignore the link, since we can't tell which
12424 register it was for. Such links wouldn't be used by combine
12427 It is not possible for the destination of the target of the link to
12428 have been changed by combine. The only potential of this is if we
12429 replace I3, I2, and I1 by I3 and I2. But in that case the
12430 destination of I2 also remains unchanged. */
12432 if (NOTE_P (XEXP (link
, 0))
12433 || (set
= single_set (XEXP (link
, 0))) == 0)
12436 reg
= SET_DEST (set
);
12437 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12438 || GET_CODE (reg
) == STRICT_LOW_PART
)
12439 reg
= XEXP (reg
, 0);
12441 /* A LOG_LINK is defined as being placed on the first insn that uses
12442 a register and points to the insn that sets the register. Start
12443 searching at the next insn after the target of the link and stop
12444 when we reach a set of the register or the end of the basic block.
12446 Note that this correctly handles the link that used to point from
12447 I3 to I2. Also note that not much searching is typically done here
12448 since most links don't point very far away. */
12450 for (insn
= NEXT_INSN (XEXP (link
, 0));
12451 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12452 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12453 insn
= NEXT_INSN (insn
))
12454 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12456 if (reg_referenced_p (reg
, PATTERN (insn
)))
12460 else if (CALL_P (insn
)
12461 && find_reg_fusage (insn
, USE
, reg
))
12466 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12469 /* If we found a place to put the link, place it there unless there
12470 is already a link to the same insn as LINK at that point. */
12476 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12477 if (XEXP (link2
, 0) == XEXP (link
, 0))
12482 XEXP (link
, 1) = LOG_LINKS (place
);
12483 LOG_LINKS (place
) = link
;
12485 /* Set added_links_insn to the earliest insn we added a
12487 if (added_links_insn
== 0
12488 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12489 added_links_insn
= place
;
12495 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12496 Check whether the expression pointer to by LOC is a register or
12497 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12498 Otherwise return zero. */
12501 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12506 && (REG_P (x
) || MEM_P (x
))
12507 && ! reg_mentioned_p (x
, (rtx
) expr
))
12512 /* Check for any register or memory mentioned in EQUIV that is not
12513 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12514 of EXPR where some registers may have been replaced by constants. */
12517 unmentioned_reg_p (rtx equiv
, rtx expr
)
12519 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12522 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12525 insn_cuid (rtx insn
)
12527 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12528 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12529 insn
= NEXT_INSN (insn
);
12531 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12533 return INSN_CUID (insn
);
12537 dump_combine_stats (FILE *file
)
12541 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12542 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12546 dump_combine_total_stats (FILE *file
)
12550 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12551 total_attempts
, total_merges
, total_extras
, total_successes
);
12556 gate_handle_combine (void)
12558 return (optimize
> 0);
12561 /* Try combining insns through substitution. */
12563 rest_of_handle_combine (void)
12565 int rebuild_jump_labels_after_combine
12566 = combine_instructions (get_insns (), max_reg_num ());
12568 /* Combining insns may have turned an indirect jump into a
12569 direct jump. Rebuild the JUMP_LABEL fields of jumping
12571 if (rebuild_jump_labels_after_combine
)
12573 timevar_push (TV_JUMP
);
12574 rebuild_jump_labels (get_insns ());
12575 timevar_pop (TV_JUMP
);
12577 delete_dead_jumptables ();
12578 cleanup_cfg (CLEANUP_EXPENSIVE
| CLEANUP_UPDATE_LIFE
);
12582 struct tree_opt_pass pass_combine
=
12584 "combine", /* name */
12585 gate_handle_combine
, /* gate */
12586 rest_of_handle_combine
, /* execute */
12589 0, /* static_pass_number */
12590 TV_COMBINE
, /* tv_id */
12591 0, /* properties_required */
12592 0, /* properties_provided */
12593 0, /* properties_destroyed */
12594 0, /* todo_flags_start */
12596 TODO_ggc_collect
, /* todo_flags_finish */