gcc/optabs-query.c

   1 /* IR-agnostic target query functions relating to optabs
   2    Copyright (C) 1987-2017 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20
  21 #include "config.h"
  22 #include "system.h"
  23 #include "coretypes.h"
  24 #include "target.h"
  25 #include "insn-codes.h"
  26 #include "optabs-query.h"
  27 #include "optabs-libfuncs.h"
  28 #include "insn-config.h"
  29 #include "rtl.h"
  30 #include "recog.h"
  31
  32 struct target_optabs default_target_optabs;
  33 struct target_optabs *this_fn_optabs = &default_target_optabs;
  34 #if SWITCHABLE_TARGET
  35 struct target_optabs *this_target_optabs = &default_target_optabs;
  36 #endif
  37
  38 /* Return the insn used to perform conversion OP from mode FROM_MODE
  39    to mode TO_MODE; return CODE_FOR_nothing if the target does not have
  40    such an insn, or if it is unsuitable for optimization type OPT_TYPE.  */
  41
  42 insn_code
  43 convert_optab_handler (convert_optab optab, machine_mode to_mode,
  44                        machine_mode from_mode, optimization_type opt_type)
  45 {
  46   insn_code icode = convert_optab_handler (optab, to_mode, from_mode);
  47   if (icode == CODE_FOR_nothing
  48       || !targetm.optab_supported_p (optab, to_mode, from_mode, opt_type))
  49     return CODE_FOR_nothing;
  50   return icode;
  51 }
  52
  53 /* Return the insn used to implement mode MODE of OP; return
  54    CODE_FOR_nothing if the target does not have such an insn,
  55    or if it is unsuitable for optimization type OPT_TYPE.  */
  56
  57 insn_code
  58 direct_optab_handler (convert_optab optab, machine_mode mode,
  59                       optimization_type opt_type)
  60 {
  61   insn_code icode = direct_optab_handler (optab, mode);
  62   if (icode == CODE_FOR_nothing
  63       || !targetm.optab_supported_p (optab, mode, mode, opt_type))
  64     return CODE_FOR_nothing;
  65   return icode;
  66 }
  67
  68 /* Enumerates the possible types of structure operand to an
  69    extraction_insn.  */
  70 enum extraction_type { ET_unaligned_mem, ET_reg };
  71
  72 /* Check whether insv, extv or extzv pattern ICODE can be used for an
  73    insertion or extraction of type TYPE on a structure of mode MODE.
  74    Return true if so and fill in *INSN accordingly.  STRUCT_OP is the
  75    operand number of the structure (the first sign_extract or zero_extract
  76    operand) and FIELD_OP is the operand number of the field (the other
  77    side of the set from the sign_extract or zero_extract).  */
  78
  79 static bool
  80 get_traditional_extraction_insn (extraction_insn *insn,
  81                                  enum extraction_type type,
  82                                  machine_mode mode,
  83                                  enum insn_code icode,
  84                                  int struct_op, int field_op)
  85 {
  86   const struct insn_data_d *data = &insn_data[icode];
  87
  88   machine_mode struct_mode = data->operand[struct_op].mode;
  89   if (struct_mode == VOIDmode)
  90     struct_mode = word_mode;
  91   if (mode != struct_mode)
  92     return false;
  93
  94   machine_mode field_mode = data->operand[field_op].mode;
  95   if (field_mode == VOIDmode)
  96     field_mode = word_mode;
  97
  98   machine_mode pos_mode = data->operand[struct_op + 2].mode;
  99   if (pos_mode == VOIDmode)
 100     pos_mode = word_mode;
 101
 102   insn->icode = icode;
 103   insn->field_mode = as_a <scalar_int_mode> (field_mode);
 104   if (type == ET_unaligned_mem)
 105     insn->struct_mode = byte_mode;
 106   else if (struct_mode == BLKmode)
 107     insn->struct_mode = opt_scalar_int_mode ();
 108   else
 109     insn->struct_mode = as_a <scalar_int_mode> (struct_mode);
 110   insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
 111   return true;
 112 }
 113
 114 /* Return true if an optab exists to perform an insertion or extraction
 115    of type TYPE in mode MODE.  Describe the instruction in *INSN if so.
 116
 117    REG_OPTAB is the optab to use for register structures and
 118    MISALIGN_OPTAB is the optab to use for misaligned memory structures.
 119    POS_OP is the operand number of the bit position.  */
 120
 121 static bool
 122 get_optab_extraction_insn (struct extraction_insn *insn,
 123                            enum extraction_type type,
 124                            machine_mode mode, direct_optab reg_optab,
 125                            direct_optab misalign_optab, int pos_op)
 126 {
 127   direct_optab optab = (type == ET_unaligned_mem ? misalign_optab : reg_optab);
 128   enum insn_code icode = direct_optab_handler (optab, mode);
 129   if (icode == CODE_FOR_nothing)
 130     return false;
 131
 132   const struct insn_data_d *data = &insn_data[icode];
 133
 134   machine_mode pos_mode = data->operand[pos_op].mode;
 135   if (pos_mode == VOIDmode)
 136     pos_mode = word_mode;
 137
 138   insn->icode = icode;
 139   insn->field_mode = as_a <scalar_int_mode> (mode);
 140   if (type == ET_unaligned_mem)
 141     insn->struct_mode = opt_scalar_int_mode ();
 142   else
 143     insn->struct_mode = insn->field_mode;
 144   insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
 145   return true;
 146 }
 147
 148 /* Return true if an instruction exists to perform an insertion or
 149    extraction (PATTERN says which) of type TYPE in mode MODE.
 150    Describe the instruction in *INSN if so.  */
 151
 152 static bool
 153 get_extraction_insn (extraction_insn *insn,
 154                      enum extraction_pattern pattern,
 155                      enum extraction_type type,
 156                      machine_mode mode)
 157 {
 158   switch (pattern)
 159     {
 160     case EP_insv:
 161       if (targetm.have_insv ()
 162           && get_traditional_extraction_insn (insn, type, mode,
 163                                               targetm.code_for_insv, 0, 3))
 164         return true;
 165       return get_optab_extraction_insn (insn, type, mode, insv_optab,
 166                                         insvmisalign_optab, 2);
 167
 168     case EP_extv:
 169       if (targetm.have_extv ()
 170           && get_traditional_extraction_insn (insn, type, mode,
 171                                               targetm.code_for_extv, 1, 0))
 172         return true;
 173       return get_optab_extraction_insn (insn, type, mode, extv_optab,
 174                                         extvmisalign_optab, 3);
 175
 176     case EP_extzv:
 177       if (targetm.have_extzv ()
 178           && get_traditional_extraction_insn (insn, type, mode,
 179                                               targetm.code_for_extzv, 1, 0))
 180         return true;
 181       return get_optab_extraction_insn (insn, type, mode, extzv_optab,
 182                                         extzvmisalign_optab, 3);
 183
 184     default:
 185       gcc_unreachable ();
 186     }
 187 }
 188
 189 /* Return true if an instruction exists to access a field of mode
 190    FIELDMODE in a structure that has STRUCT_BITS significant bits.
 191    Describe the "best" such instruction in *INSN if so.  PATTERN and
 192    TYPE describe the type of insertion or extraction we want to perform.
 193
 194    For an insertion, the number of significant structure bits includes
 195    all bits of the target.  For an extraction, it need only include the
 196    most significant bit of the field.  Larger widths are acceptable
 197    in both cases.  */
 198
 199 static bool
 200 get_best_extraction_insn (extraction_insn *insn,
 201                           enum extraction_pattern pattern,
 202                           enum extraction_type type,
 203                           unsigned HOST_WIDE_INT struct_bits,
 204                           machine_mode field_mode)
 205 {
 206   opt_scalar_int_mode mode_iter;
 207   FOR_EACH_MODE_FROM (mode_iter, smallest_int_mode_for_size (struct_bits))
 208     {
 209       scalar_int_mode mode = mode_iter.require ();
 210       if (get_extraction_insn (insn, pattern, type, mode))
 211         {
 212           FOR_EACH_MODE_FROM (mode_iter, mode)
 213             {
 214               mode = mode_iter.require ();
 215               if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (field_mode)
 216                   || TRULY_NOOP_TRUNCATION_MODES_P (insn->field_mode,
 217                                                     field_mode))
 218                 break;
 219               get_extraction_insn (insn, pattern, type, mode);
 220             }
 221           return true;
 222         }
 223     }
 224   return false;
 225 }
 226
 227 /* Return true if an instruction exists to access a field of mode
 228    FIELDMODE in a register structure that has STRUCT_BITS significant bits.
 229    Describe the "best" such instruction in *INSN if so.  PATTERN describes
 230    the type of insertion or extraction we want to perform.
 231
 232    For an insertion, the number of significant structure bits includes
 233    all bits of the target.  For an extraction, it need only include the
 234    most significant bit of the field.  Larger widths are acceptable
 235    in both cases.  */
 236
 237 bool
 238 get_best_reg_extraction_insn (extraction_insn *insn,
 239                               enum extraction_pattern pattern,
 240                               unsigned HOST_WIDE_INT struct_bits,
 241                               machine_mode field_mode)
 242 {
 243   return get_best_extraction_insn (insn, pattern, ET_reg, struct_bits,
 244                                    field_mode);
 245 }
 246
 247 /* Return true if an instruction exists to access a field of BITSIZE
 248    bits starting BITNUM bits into a memory structure.  Describe the
 249    "best" such instruction in *INSN if so.  PATTERN describes the type
 250    of insertion or extraction we want to perform and FIELDMODE is the
 251    natural mode of the extracted field.
 252
 253    The instructions considered here only access bytes that overlap
 254    the bitfield; they do not touch any surrounding bytes.  */
 255
 256 bool
 257 get_best_mem_extraction_insn (extraction_insn *insn,
 258                               enum extraction_pattern pattern,
 259                               HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum,
 260                               machine_mode field_mode)
 261 {
 262   unsigned HOST_WIDE_INT struct_bits = (bitnum % BITS_PER_UNIT
 263                                         + bitsize
 264                                         + BITS_PER_UNIT - 1);
 265   struct_bits -= struct_bits % BITS_PER_UNIT;
 266   return get_best_extraction_insn (insn, pattern, ET_unaligned_mem,
 267                                    struct_bits, field_mode);
 268 }
 269
 270 /* Return the insn code used to extend FROM_MODE to TO_MODE.
 271    UNSIGNEDP specifies zero-extension instead of sign-extension.  If
 272    no such operation exists, CODE_FOR_nothing will be returned.  */
 273
 274 enum insn_code
 275 can_extend_p (machine_mode to_mode, machine_mode from_mode,
 276               int unsignedp)
 277 {
 278   if (unsignedp < 0 && targetm.have_ptr_extend ())
 279     return targetm.code_for_ptr_extend;
 280
 281   convert_optab tab = unsignedp ? zext_optab : sext_optab;
 282   return convert_optab_handler (tab, to_mode, from_mode);
 283 }
 284
 285 /* Return the insn code to convert fixed-point mode FIXMODE to floating-point
 286    mode FLTMODE, or CODE_FOR_nothing if no such instruction exists.
 287    UNSIGNEDP specifies whether FIXMODE is unsigned.  */
 288
 289 enum insn_code
 290 can_float_p (machine_mode fltmode, machine_mode fixmode,
 291              int unsignedp)
 292 {
 293   convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab;
 294   return convert_optab_handler (tab, fltmode, fixmode);
 295 }
 296
 297 /* Return the insn code to convert floating-point mode FLTMODE to fixed-point
 298    mode FIXMODE, or CODE_FOR_nothing if no such instruction exists.
 299    UNSIGNEDP specifies whether FIXMODE is unsigned.
 300
 301    On a successful return, set *TRUNCP_PTR to true if it is necessary to
 302    output an explicit FTRUNC before the instruction.  */
 303
 304 enum insn_code
 305 can_fix_p (machine_mode fixmode, machine_mode fltmode,
 306            int unsignedp, bool *truncp_ptr)
 307 {
 308   convert_optab tab;
 309   enum insn_code icode;
 310
 311   tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab;
 312   icode = convert_optab_handler (tab, fixmode, fltmode);
 313   if (icode != CODE_FOR_nothing)
 314     {
 315       *truncp_ptr = false;
 316       return icode;
 317     }
 318
 319   /* FIXME: This requires a port to define both FIX and FTRUNC pattern
 320      for this to work.  We need to rework the fix* and ftrunc* patterns
 321      and documentation.  */
 322   tab = unsignedp ? ufix_optab : sfix_optab;
 323   icode = convert_optab_handler (tab, fixmode, fltmode);
 324   if (icode != CODE_FOR_nothing
 325       && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing)
 326     {
 327       *truncp_ptr = true;
 328       return icode;
 329     }
 330
 331   return CODE_FOR_nothing;
 332 }
 333
 334 /* Return nonzero if a conditional move of mode MODE is supported.
 335
 336    This function is for combine so it can tell whether an insn that looks
 337    like a conditional move is actually supported by the hardware.  If we
 338    guess wrong we lose a bit on optimization, but that's it.  */
 339 /* ??? sparc64 supports conditionally moving integers values based on fp
 340    comparisons, and vice versa.  How do we handle them?  */
 341
 342 bool
 343 can_conditionally_move_p (machine_mode mode)
 344 {
 345   return direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing;
 346 }
 347
 348 /* Return true if VEC_PERM_EXPR of arbitrary input vectors can be
 349    expanded using SIMD extensions of the CPU.  SEL may be NULL, which
 350    stands for an unknown constant.  Note that additional permutations
 351    representing whole-vector shifts may also be handled via the vec_shr
 352    optab, but only where the second input vector is entirely constant
 353    zeroes; this case is not dealt with here.  */
 354
 355 bool
 356 can_vec_perm_p (machine_mode mode, bool variable,
 357                 const unsigned char *sel)
 358 {
 359   machine_mode qimode;
 360
 361   /* If the target doesn't implement a vector mode for the vector type,
 362      then no operations are supported.  */
 363   if (!VECTOR_MODE_P (mode))
 364     return false;
 365
 366   if (!variable)
 367     {
 368       if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing
 369           && (sel == NULL
 370               || targetm.vectorize.vec_perm_const_ok == NULL
 371               || targetm.vectorize.vec_perm_const_ok (mode, sel)))
 372         return true;
 373     }
 374
 375   if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing)
 376     return true;
 377
 378   /* We allow fallback to a QI vector mode, and adjust the mask.  */
 379   if (GET_MODE_INNER (mode) == QImode
 380       || !mode_for_vector (QImode, GET_MODE_SIZE (mode)).exists (&qimode)
 381       || !VECTOR_MODE_P (qimode))
 382     return false;
 383
 384   /* ??? For completeness, we ought to check the QImode version of
 385       vec_perm_const_optab.  But all users of this implicit lowering
 386       feature implement the variable vec_perm_optab.  */
 387   if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing)
 388     return false;
 389
 390   /* In order to support the lowering of variable permutations,
 391      we need to support shifts and adds.  */
 392   if (variable)
 393     {
 394       if (GET_MODE_UNIT_SIZE (mode) > 2
 395           && optab_handler (ashl_optab, mode) == CODE_FOR_nothing
 396           && optab_handler (vashl_optab, mode) == CODE_FOR_nothing)
 397         return false;
 398       if (optab_handler (add_optab, qimode) == CODE_FOR_nothing)
 399         return false;
 400     }
 401
 402   return true;
 403 }
 404
 405 /* Like optab_handler, but for widening_operations that have a
 406    TO_MODE and a FROM_MODE.  */
 407
 408 enum insn_code
 409 widening_optab_handler (optab op, machine_mode to_mode,
 410                         machine_mode from_mode)
 411 {
 412   unsigned scode = (op << 16) | to_mode;
 413   if (to_mode != from_mode && from_mode != VOIDmode)
 414     {
 415       /* ??? Why does find_widening_optab_handler_and_mode attempt to
 416          widen things that can't be widened?  E.g. add_optab... */
 417       if (op > LAST_CONV_OPTAB)
 418         return CODE_FOR_nothing;
 419       scode |= from_mode << 8;
 420     }
 421   return raw_optab_handler (scode);
 422 }
 423
 424 /* Find a widening optab even if it doesn't widen as much as we want.
 425    E.g. if from_mode is HImode, and to_mode is DImode, and there is no
 426    direct HI->SI insn, then return SI->DI, if that exists.
 427    If PERMIT_NON_WIDENING is non-zero then this can be used with
 428    non-widening optabs also.  */
 429
 430 enum insn_code
 431 find_widening_optab_handler_and_mode (optab op, machine_mode to_mode,
 432                                       machine_mode from_mode,
 433                                       int permit_non_widening,
 434                                       machine_mode *found_mode)
 435 {
 436   for (; (permit_non_widening || from_mode != to_mode)
 437          && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode)
 438          && from_mode != VOIDmode;
 439        from_mode = GET_MODE_WIDER_MODE (from_mode).else_void ())
 440     {
 441       enum insn_code handler = widening_optab_handler (op, to_mode,
 442                                                        from_mode);
 443
 444       if (handler != CODE_FOR_nothing)
 445         {
 446           if (found_mode)
 447             *found_mode = from_mode;
 448           return handler;
 449         }
 450     }
 451
 452   return CODE_FOR_nothing;
 453 }
 454
 455 /* Return non-zero if a highpart multiply is supported of can be synthisized.
 456    For the benefit of expand_mult_highpart, the return value is 1 for direct,
 457    2 for even/odd widening, and 3 for hi/lo widening.  */
 458
 459 int
 460 can_mult_highpart_p (machine_mode mode, bool uns_p)
 461 {
 462   optab op;
 463   unsigned char *sel;
 464   unsigned i, nunits;
 465
 466   op = uns_p ? umul_highpart_optab : smul_highpart_optab;
 467   if (optab_handler (op, mode) != CODE_FOR_nothing)
 468     return 1;
 469
 470   /* If the mode is an integral vector, synth from widening operations.  */
 471   if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
 472     return 0;
 473
 474   nunits = GET_MODE_NUNITS (mode);
 475   sel = XALLOCAVEC (unsigned char, nunits);
 476
 477   op = uns_p ? vec_widen_umult_even_optab : vec_widen_smult_even_optab;
 478   if (optab_handler (op, mode) != CODE_FOR_nothing)
 479     {
 480       op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab;
 481       if (optab_handler (op, mode) != CODE_FOR_nothing)
 482         {
 483           for (i = 0; i < nunits; ++i)
 484             sel[i] = !BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0);
 485           if (can_vec_perm_p (mode, false, sel))
 486             return 2;
 487         }
 488     }
 489
 490   op = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab;
 491   if (optab_handler (op, mode) != CODE_FOR_nothing)
 492     {
 493       op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
 494       if (optab_handler (op, mode) != CODE_FOR_nothing)
 495         {
 496           for (i = 0; i < nunits; ++i)
 497             sel[i] = 2 * i + (BYTES_BIG_ENDIAN ? 0 : 1);
 498           if (can_vec_perm_p (mode, false, sel))
 499             return 3;
 500         }
 501     }
 502
 503   return 0;
 504 }
 505
 506 /* Return true if target supports vector masked load/store for mode.  */
 507
 508 bool
 509 can_vec_mask_load_store_p (machine_mode mode,
 510                            machine_mode mask_mode,
 511                            bool is_load)
 512 {
 513   optab op = is_load ? maskload_optab : maskstore_optab;
 514   machine_mode vmode;
 515   unsigned int vector_sizes;
 516
 517   /* If mode is vector mode, check it directly.  */
 518   if (VECTOR_MODE_P (mode))
 519     return convert_optab_handler (op, mode, mask_mode) != CODE_FOR_nothing;
 520
 521   /* Otherwise, return true if there is some vector mode with
 522      the mask load/store supported.  */
 523
 524   /* See if there is any chance the mask load or store might be
 525      vectorized.  If not, punt.  */
 526   scalar_mode smode;
 527   if (!is_a <scalar_mode> (mode, &smode))
 528     return false;
 529
 530   vmode = targetm.vectorize.preferred_simd_mode (smode);
 531   if (!VECTOR_MODE_P (vmode))
 532     return false;
 533
 534   if ((targetm.vectorize.get_mask_mode
 535        (GET_MODE_NUNITS (vmode), GET_MODE_SIZE (vmode)).exists (&mask_mode))
 536       && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
 537     return true;
 538
 539   vector_sizes = targetm.vectorize.autovectorize_vector_sizes ();
 540   while (vector_sizes != 0)
 541     {
 542       unsigned int cur = 1 << floor_log2 (vector_sizes);
 543       vector_sizes &= ~cur;
 544       if (cur <= GET_MODE_SIZE (smode))
 545         continue;
 546       unsigned int nunits = cur / GET_MODE_SIZE (smode);
 547       if (mode_for_vector (smode, nunits).exists (&vmode)
 548           && VECTOR_MODE_P (vmode)
 549           && targetm.vectorize.get_mask_mode (nunits, cur).exists (&mask_mode)
 550           && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
 551         return true;
 552     }
 553   return false;
 554 }
 555
 556 /* Return true if there is a compare_and_swap pattern.  */
 557
 558 bool
 559 can_compare_and_swap_p (machine_mode mode, bool allow_libcall)
 560 {
 561   enum insn_code icode;
 562
 563   /* Check for __atomic_compare_and_swap.  */
 564   icode = direct_optab_handler (atomic_compare_and_swap_optab, mode);
 565   if (icode != CODE_FOR_nothing)
 566     return true;
 567
 568   /* Check for __sync_compare_and_swap.  */
 569   icode = optab_handler (sync_compare_and_swap_optab, mode);
 570   if (icode != CODE_FOR_nothing)
 571     return true;
 572   if (allow_libcall && optab_libfunc (sync_compare_and_swap_optab, mode))
 573     return true;
 574
 575   /* No inline compare and swap.  */
 576   return false;
 577 }
 578
 579 /* Return true if an atomic exchange can be performed.  */
 580
 581 bool
 582 can_atomic_exchange_p (machine_mode mode, bool allow_libcall)
 583 {
 584   enum insn_code icode;
 585
 586   /* Check for __atomic_exchange.  */
 587   icode = direct_optab_handler (atomic_exchange_optab, mode);
 588   if (icode != CODE_FOR_nothing)
 589     return true;
 590
 591   /* Don't check __sync_test_and_set, as on some platforms that
 592      has reduced functionality.  Targets that really do support
 593      a proper exchange should simply be updated to the __atomics.  */
 594
 595   return can_compare_and_swap_p (mode, allow_libcall);
 596 }
 597
 598 /* Return true if an atomic load can be performed without falling back to
 599    a compare-and-swap.  */
 600
 601 bool
 602 can_atomic_load_p (machine_mode mode)
 603 {
 604   enum insn_code icode;
 605
 606   /* Does the target supports the load directly?  */
 607   icode = direct_optab_handler (atomic_load_optab, mode);
 608   if (icode != CODE_FOR_nothing)
 609     return true;
 610
 611   /* If the size of the object is greater than word size on this target,
 612      then we assume that a load will not be atomic.  Also see
 613      expand_atomic_load.  */
 614   return GET_MODE_PRECISION (mode) <= BITS_PER_WORD;
 615 }
 616
 617 /* Determine whether "1 << x" is relatively cheap in word_mode.  */
 618
 619 bool
 620 lshift_cheap_p (bool speed_p)
 621 {
 622   /* FIXME: This should be made target dependent via this "this_target"
 623      mechanism, similar to e.g. can_copy_init_p in gcse.c.  */
 624   static bool init[2] = { false, false };
 625   static bool cheap[2] = { true, true };
 626
 627   /* If the targer has no lshift in word_mode, the operation will most
 628      probably not be cheap.  ??? Does GCC even work for such targets?  */
 629   if (optab_handler (ashl_optab, word_mode) == CODE_FOR_nothing)
 630     return false;
 631
 632   if (!init[speed_p])
 633     {
 634       rtx reg = gen_raw_REG (word_mode, 10000);
 635       int cost = set_src_cost (gen_rtx_ASHIFT (word_mode, const1_rtx, reg),
 636                                word_mode, speed_p);
 637       cheap[speed_p] = cost < COSTS_N_INSNS (3);
 638       init[speed_p] = true;
 639     }
 640
 641   return cheap[speed_p];
 642 }