1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "insn-config.h"
34 #include "addresses.h"
37 /* The flags is set up every time when we calculate pseudo register
38 classes through function ira_set_pseudo_classes. */
39 static bool pseudo_classes_defined_p
= false;
41 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
42 static bool allocno_p
;
44 /* Number of elements in array `costs'. */
45 static int cost_elements_num
;
47 /* The `costs' struct records the cost of using hard registers of each
48 class considered for the calculation and of using memory for each
53 /* Costs for register classes start here. We process only some
58 #define max_struct_costs_size \
59 (this_target_ira_int->x_max_struct_costs_size)
61 (this_target_ira_int->x_init_cost)
63 (this_target_ira_int->x_temp_costs)
65 (this_target_ira_int->x_op_costs)
66 #define this_op_costs \
67 (this_target_ira_int->x_this_op_costs)
69 /* Costs of each class for each allocno or pseudo. */
70 static struct costs
*costs
;
72 /* Accumulated costs of each class for each allocno. */
73 static struct costs
*total_allocno_costs
;
75 /* It is the current size of struct costs. */
76 static int struct_costs_size
;
78 /* Return pointer to structure containing costs of allocno or pseudo
79 with given NUM in array ARR. */
80 #define COSTS(arr, num) \
81 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
83 /* Return index in COSTS when processing reg with REGNO. */
84 #define COST_INDEX(regno) (allocno_p \
85 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
88 /* Record register class preferences of each allocno or pseudo. Null
89 value means no preferences. It happens on the 1st iteration of the
91 static enum reg_class
*pref
;
93 /* Allocated buffers for pref. */
94 static enum reg_class
*pref_buffer
;
96 /* Record allocno class of each allocno with the same regno. */
97 static enum reg_class
*regno_aclass
;
99 /* Record cost gains for not allocating a register with an invariant
101 static int *regno_equiv_gains
;
103 /* Execution frequency of the current insn. */
104 static int frequency
;
108 /* Info about reg classes whose costs are calculated for a pseudo. */
111 /* Number of the cost classes in the subsequent array. */
113 /* Container of the cost classes. */
114 enum reg_class classes
[N_REG_CLASSES
];
115 /* Map reg class -> index of the reg class in the previous array.
116 -1 if it is not a cost class. */
117 int index
[N_REG_CLASSES
];
118 /* Map hard regno index of first class in array CLASSES containing
119 the hard regno, -1 otherwise. */
120 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
123 /* Types of pointers to the structure above. */
124 typedef struct cost_classes
*cost_classes_t
;
125 typedef const struct cost_classes
*const_cost_classes_t
;
127 /* Info about cost classes for each pseudo. */
128 static cost_classes_t
*regno_cost_classes
;
130 /* Helper for cost_classes hashing. */
132 struct cost_classes_hasher
: pointer_hash
<cost_classes
>
134 static inline hashval_t
hash (const cost_classes
*);
135 static inline bool equal (const cost_classes
*, const cost_classes
*);
136 static inline void remove (cost_classes
*);
139 /* Returns hash value for cost classes info HV. */
141 cost_classes_hasher::hash (const cost_classes
*hv
)
143 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
146 /* Compares cost classes info HV1 and HV2. */
148 cost_classes_hasher::equal (const cost_classes
*hv1
, const cost_classes
*hv2
)
150 return (hv1
->num
== hv2
->num
151 && memcmp (hv1
->classes
, hv2
->classes
,
152 sizeof (enum reg_class
) * hv1
->num
) == 0);
155 /* Delete cost classes info V from the hash table. */
157 cost_classes_hasher::remove (cost_classes
*v
)
162 /* Hash table of unique cost classes. */
163 static hash_table
<cost_classes_hasher
> *cost_classes_htab
;
165 /* Map allocno class -> cost classes for pseudo of given allocno
167 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
169 /* Map mode -> cost classes for pseudo of give mode. */
170 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
172 /* Cost classes that include all classes in ira_important_classes. */
173 static cost_classes all_cost_classes
;
175 /* Use the array of classes in CLASSES_PTR to fill out the rest of
178 complete_cost_classes (cost_classes_t classes_ptr
)
180 for (int i
= 0; i
< N_REG_CLASSES
; i
++)
181 classes_ptr
->index
[i
] = -1;
182 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
183 classes_ptr
->hard_regno_index
[i
] = -1;
184 for (int i
= 0; i
< classes_ptr
->num
; i
++)
186 enum reg_class cl
= classes_ptr
->classes
[i
];
187 classes_ptr
->index
[cl
] = i
;
188 for (int j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
190 unsigned int hard_regno
= ira_class_hard_regs
[cl
][j
];
191 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
192 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
197 /* Initialize info about the cost classes for each pseudo. */
199 initiate_regno_cost_classes (void)
201 int size
= sizeof (cost_classes_t
) * max_reg_num ();
203 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
204 memset (regno_cost_classes
, 0, size
);
205 memset (cost_classes_aclass_cache
, 0,
206 sizeof (cost_classes_t
) * N_REG_CLASSES
);
207 memset (cost_classes_mode_cache
, 0,
208 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
209 cost_classes_htab
= new hash_table
<cost_classes_hasher
> (200);
210 all_cost_classes
.num
= ira_important_classes_num
;
211 for (int i
= 0; i
< ira_important_classes_num
; i
++)
212 all_cost_classes
.classes
[i
] = ira_important_classes
[i
];
213 complete_cost_classes (&all_cost_classes
);
216 /* Create new cost classes from cost classes FROM and set up members
217 index and hard_regno_index. Return the new classes. The function
218 implements some common code of two functions
219 setup_regno_cost_classes_by_aclass and
220 setup_regno_cost_classes_by_mode. */
221 static cost_classes_t
222 setup_cost_classes (cost_classes_t from
)
224 cost_classes_t classes_ptr
;
226 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
227 classes_ptr
->num
= from
->num
;
228 for (int i
= 0; i
< from
->num
; i
++)
229 classes_ptr
->classes
[i
] = from
->classes
[i
];
230 complete_cost_classes (classes_ptr
);
234 /* Return a version of FULL that only considers registers in REGS that are
235 valid for mode MODE. Both FULL and the returned class are globally
237 static cost_classes_t
238 restrict_cost_classes (cost_classes_t full
, machine_mode mode
,
239 const HARD_REG_SET
®s
)
241 static struct cost_classes narrow
;
242 int map
[N_REG_CLASSES
];
244 for (int i
= 0; i
< full
->num
; i
++)
246 /* Assume that we'll drop the class. */
249 /* Ignore classes that are too small for the mode. */
250 enum reg_class cl
= full
->classes
[i
];
251 if (!contains_reg_of_mode
[cl
][mode
])
254 /* Calculate the set of registers in CL that belong to REGS and
255 are valid for MODE. */
256 HARD_REG_SET valid_for_cl
;
257 COPY_HARD_REG_SET (valid_for_cl
, reg_class_contents
[cl
]);
258 AND_HARD_REG_SET (valid_for_cl
, regs
);
259 AND_COMPL_HARD_REG_SET (valid_for_cl
,
260 ira_prohibited_class_mode_regs
[cl
][mode
]);
261 AND_COMPL_HARD_REG_SET (valid_for_cl
, ira_no_alloc_regs
);
262 if (hard_reg_set_empty_p (valid_for_cl
))
265 /* Don't use this class if the set of valid registers is a subset
266 of an existing class. For example, suppose we have two classes
267 GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
268 that the mode changes allowed by FR_REGS are not as general as
269 the mode changes allowed by GR_REGS.
271 In this situation, the mode changes for GR_AND_FR_REGS could
272 either be seen as the union or the intersection of the mode
273 changes allowed by the two subclasses. The justification for
274 the union-based definition would be that, if you want a mode
275 change that's only allowed by GR_REGS, you can pick a register
276 from the GR_REGS subclass. The justification for the
277 intersection-based definition would be that every register
278 from the class would allow the mode change.
280 However, if we have a register that needs to be in GR_REGS,
281 using GR_AND_FR_REGS with the intersection-based definition
282 would be too pessimistic, since it would bring in restrictions
283 that only apply to FR_REGS. Conversely, if we have a register
284 that needs to be in FR_REGS, using GR_AND_FR_REGS with the
285 union-based definition would lose the extra restrictions
286 placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
287 for cases where GR_REGS and FP_REGS are both valid. */
289 for (pos
= 0; pos
< narrow
.num
; ++pos
)
291 enum reg_class cl2
= narrow
.classes
[pos
];
292 if (hard_reg_set_subset_p (valid_for_cl
, reg_class_contents
[cl2
]))
296 if (pos
== narrow
.num
)
298 /* If several classes are equivalent, prefer to use the one
299 that was chosen as the allocno class. */
300 enum reg_class cl2
= ira_allocno_class_translate
[cl
];
301 if (ira_class_hard_regs_num
[cl
] == ira_class_hard_regs_num
[cl2
])
303 narrow
.classes
[narrow
.num
++] = cl
;
306 if (narrow
.num
== full
->num
)
309 cost_classes
**slot
= cost_classes_htab
->find_slot (&narrow
, INSERT
);
312 cost_classes_t classes
= setup_cost_classes (&narrow
);
313 /* Map equivalent classes to the representative that we chose above. */
314 for (int i
= 0; i
< ira_important_classes_num
; i
++)
316 enum reg_class cl
= ira_important_classes
[i
];
317 int index
= full
->index
[cl
];
319 classes
->index
[cl
] = map
[index
];
326 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
327 This function is used when we know an initial approximation of
328 allocno class of the pseudo already, e.g. on the second iteration
329 of class cost calculation or after class cost calculation in
330 register-pressure sensitive insn scheduling or register-pressure
331 sensitive loop-invariant motion. */
333 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
335 static struct cost_classes classes
;
336 cost_classes_t classes_ptr
;
340 HARD_REG_SET temp
, temp2
;
343 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
345 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
346 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
347 /* We exclude classes from consideration which are subsets of
348 ACLASS only if ACLASS is an uniform class. */
349 exclude_p
= ira_uniform_class_p
[aclass
];
351 for (i
= 0; i
< ira_important_classes_num
; i
++)
353 cl
= ira_important_classes
[i
];
356 /* Exclude non-uniform classes which are subsets of
358 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
359 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
360 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
363 classes
.classes
[classes
.num
++] = cl
;
365 slot
= cost_classes_htab
->find_slot (&classes
, INSERT
);
368 classes_ptr
= setup_cost_classes (&classes
);
371 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
373 if (regno_reg_rtx
[regno
] != NULL_RTX
)
375 /* Restrict the classes to those that are valid for REGNO's mode
376 (which might for example exclude singleton classes if the mode
377 requires two registers). Also restrict the classes to those that
378 are valid for subregs of REGNO. */
379 const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
);
381 valid_regs
= ®_class_contents
[ALL_REGS
];
382 classes_ptr
= restrict_cost_classes (classes_ptr
,
383 PSEUDO_REGNO_MODE (regno
),
386 regno_cost_classes
[regno
] = classes_ptr
;
389 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
390 decrease number of cost classes for the pseudo, if hard registers
391 of some important classes can not hold a value of MODE. So the
392 pseudo can not get hard register of some important classes and cost
393 calculation for such important classes is only wasting CPU
396 setup_regno_cost_classes_by_mode (int regno
, machine_mode mode
)
398 if (const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
))
399 regno_cost_classes
[regno
] = restrict_cost_classes (&all_cost_classes
,
403 if (cost_classes_mode_cache
[mode
] == NULL
)
404 cost_classes_mode_cache
[mode
]
405 = restrict_cost_classes (&all_cost_classes
, mode
,
406 reg_class_contents
[ALL_REGS
]);
407 regno_cost_classes
[regno
] = cost_classes_mode_cache
[mode
];
411 /* Finalize info about the cost classes for each pseudo. */
413 finish_regno_cost_classes (void)
415 ira_free (regno_cost_classes
);
416 delete cost_classes_htab
;
417 cost_classes_htab
= NULL
;
422 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
423 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
424 be a pseudo register. */
426 copy_cost (rtx x
, machine_mode mode
, reg_class_t rclass
, bool to_p
,
427 secondary_reload_info
*prev_sri
)
429 secondary_reload_info sri
;
430 reg_class_t secondary_class
= NO_REGS
;
432 /* If X is a SCRATCH, there is actually nothing to move since we are
433 assuming optimal allocation. */
434 if (GET_CODE (x
) == SCRATCH
)
437 /* Get the class we will actually use for a reload. */
438 rclass
= targetm
.preferred_reload_class (x
, rclass
);
440 /* If we need a secondary reload for an intermediate, the cost is
441 that to load the input into the intermediate register, then to
443 sri
.prev_sri
= prev_sri
;
445 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
447 if (secondary_class
!= NO_REGS
)
449 ira_init_register_move_cost_if_necessary (mode
);
450 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
452 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
455 /* For memory, use the memory move cost, for (hard) registers, use
456 the cost to move between the register classes, and use 2 for
457 everything else (constants). */
458 if (MEM_P (x
) || rclass
== NO_REGS
)
459 return sri
.extra_cost
460 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
463 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
465 ira_init_register_move_cost_if_necessary (mode
);
466 return (sri
.extra_cost
467 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
470 /* If this is a constant, we may eventually want to call rtx_cost
472 return sri
.extra_cost
+ COSTS_N_INSNS (1);
477 /* Record the cost of using memory or hard registers of various
478 classes for the operands in INSN.
480 N_ALTS is the number of alternatives.
481 N_OPS is the number of operands.
482 OPS is an array of the operands.
483 MODES are the modes of the operands, in case any are VOIDmode.
484 CONSTRAINTS are the constraints to use for the operands. This array
485 is modified by this procedure.
487 This procedure works alternative by alternative. For each
488 alternative we assume that we will be able to allocate all allocnos
489 to their ideal register class and calculate the cost of using that
490 alternative. Then we compute, for each operand that is a
491 pseudo-register, the cost of having the allocno allocated to each
492 register class and using it in that alternative. To this cost is
493 added the cost of the alternative.
495 The cost of each class for this insn is its lowest cost among all
498 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
499 machine_mode
*modes
, const char **constraints
,
500 rtx_insn
*insn
, enum reg_class
*pref
)
504 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
505 move_table
*move_in_cost
, *move_out_cost
;
506 short (*mem_cost
)[2];
508 for (i
= 0; i
< n_ops
; i
++)
509 insn_allows_mem
[i
] = 0;
511 /* Process each alternative, each time minimizing an operand's cost
512 with the cost for each operand in that alternative. */
513 alternative_mask preferred
= get_preferred_alternatives (insn
);
514 for (alt
= 0; alt
< n_alts
; alt
++)
516 enum reg_class classes
[MAX_RECOG_OPERANDS
];
517 int allows_mem
[MAX_RECOG_OPERANDS
];
518 enum reg_class rclass
;
520 int alt_cost
= 0, op_cost_add
;
522 if (!TEST_BIT (preferred
, alt
))
524 for (i
= 0; i
< recog_data
.n_operands
; i
++)
525 constraints
[i
] = skip_alternative (constraints
[i
]);
530 for (i
= 0; i
< n_ops
; i
++)
533 const char *p
= constraints
[i
];
535 machine_mode mode
= modes
[i
];
539 /* Initially show we know nothing about the register class. */
540 classes
[i
] = NO_REGS
;
543 /* If this operand has no constraints at all, we can
544 conclude nothing about it since anything is valid. */
547 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
548 memset (this_op_costs
[i
], 0, struct_costs_size
);
552 /* If this alternative is only relevant when this operand
553 matches a previous operand, we do different things
554 depending on whether this operand is a allocno-reg or not.
555 We must process any modifiers for the operand before we
556 can make this test. */
557 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
560 if (p
[0] >= '0' && p
[0] <= '0' + i
)
562 /* Copy class and whether memory is allowed from the
563 matching alternative. Then perform any needed cost
564 computations and/or adjustments. */
566 classes
[i
] = classes
[j
];
567 allows_mem
[i
] = allows_mem
[j
];
569 insn_allows_mem
[i
] = 1;
571 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
573 /* If this matches the other operand, we have no
574 added cost and we win. */
575 if (rtx_equal_p (ops
[j
], op
))
577 /* If we can put the other operand into a register,
578 add to the cost of this alternative the cost to
579 copy this operand to the register used for the
581 else if (classes
[j
] != NO_REGS
)
583 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
587 else if (! REG_P (ops
[j
])
588 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
590 /* This op is an allocno but the one it matches is
593 /* If we can't put the other operand into a
594 register, this alternative can't be used. */
596 if (classes
[j
] == NO_REGS
)
598 /* Otherwise, add to the cost of this alternative
599 the cost to copy the other operand to the hard
600 register used for this operand. */
602 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
606 /* The costs of this operand are not the same as the
607 other operand since move costs are not symmetric.
608 Moreover, if we cannot tie them, this alternative
609 needs to do a copy, which is one insn. */
610 struct costs
*pp
= this_op_costs
[i
];
611 int *pp_costs
= pp
->cost
;
612 cost_classes_t cost_classes_ptr
613 = regno_cost_classes
[REGNO (op
)];
614 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
615 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
616 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
617 enum reg_class op_class
= classes
[i
];
619 ira_init_register_move_cost_if_necessary (mode
);
623 if (op_class
== NO_REGS
)
625 mem_cost
= ira_memory_move_cost
[mode
];
626 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
628 rclass
= cost_classes
[k
];
629 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
634 move_out_cost
= ira_may_move_out_cost
[mode
];
635 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
637 rclass
= cost_classes
[k
];
639 = move_out_cost
[op_class
][rclass
] * frequency
;
646 if (op_class
== NO_REGS
)
648 mem_cost
= ira_memory_move_cost
[mode
];
649 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
651 rclass
= cost_classes
[k
];
652 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
657 move_in_cost
= ira_may_move_in_cost
[mode
];
658 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
660 rclass
= cost_classes
[k
];
662 = move_in_cost
[rclass
][op_class
] * frequency
;
668 if (op_class
== NO_REGS
)
670 mem_cost
= ira_memory_move_cost
[mode
];
671 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
673 rclass
= cost_classes
[k
];
674 pp_costs
[k
] = ((mem_cost
[rclass
][0]
675 + mem_cost
[rclass
][1])
681 move_in_cost
= ira_may_move_in_cost
[mode
];
682 move_out_cost
= ira_may_move_out_cost
[mode
];
683 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
685 rclass
= cost_classes
[k
];
686 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
687 + move_out_cost
[op_class
][rclass
])
693 /* If the alternative actually allows memory, make
694 things a bit cheaper since we won't need an extra
697 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
698 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
699 - allows_mem
[i
]) * frequency
;
701 /* If we have assigned a class to this allocno in
702 our first pass, add a cost to this alternative
703 corresponding to what we would add if this
704 allocno were not in the appropriate class. */
707 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
709 if (pref_class
== NO_REGS
)
712 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
714 ? ira_memory_move_cost
[mode
][op_class
][1]
716 else if (ira_reg_class_intersect
717 [pref_class
][op_class
] == NO_REGS
)
719 += ira_register_move_cost
[mode
][pref_class
][op_class
];
721 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
722 && ! find_reg_note (insn
, REG_DEAD
, op
))
729 /* Scan all the constraint letters. See if the operand
730 matches any of the constraints. Collect the valid
731 register classes and see if this operand accepts
738 /* Ignore the next letter for this pass. */
753 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
755 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
756 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
760 enum constraint_num cn
= lookup_constraint (p
);
762 switch (get_constraint_type (cn
))
765 cl
= reg_class_for_constraint (cn
);
767 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][cl
];
772 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
777 /* Every MEM can be reloaded to fit. */
778 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
784 /* Every address can be reloaded to fit. */
786 if (address_operand (op
, GET_MODE (op
))
787 || constraint_satisfied_p (op
, cn
))
789 /* We know this operand is an address, so we
790 want it to be allocated to a hard register
791 that can be the base of an address,
792 i.e. BASE_REG_CLASS. */
794 = ira_reg_class_subunion
[classes
[i
]]
795 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
800 if (constraint_satisfied_p (op
, cn
))
806 p
+= CONSTRAINT_LEN (c
, p
);
813 /* How we account for this operand now depends on whether it
814 is a pseudo register or not. If it is, we first check if
815 any register classes are valid. If not, we ignore this
816 alternative, since we want to assume that all allocnos get
817 allocated for register preferencing. If some register
818 class is valid, compute the costs of moving the allocno
820 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
822 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
824 /* We must always fail if the operand is a REG, but
825 we did not find a suitable class and memory is
828 Otherwise we may perform an uninitialized read
829 from this_op_costs after the `continue' statement
835 unsigned int regno
= REGNO (op
);
836 struct costs
*pp
= this_op_costs
[i
];
837 int *pp_costs
= pp
->cost
;
838 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
839 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
840 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
841 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
842 enum reg_class op_class
= classes
[i
];
844 ira_init_register_move_cost_if_necessary (mode
);
848 if (op_class
== NO_REGS
)
850 mem_cost
= ira_memory_move_cost
[mode
];
851 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
853 rclass
= cost_classes
[k
];
854 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
859 move_out_cost
= ira_may_move_out_cost
[mode
];
860 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
862 rclass
= cost_classes
[k
];
864 = move_out_cost
[op_class
][rclass
] * frequency
;
871 if (op_class
== NO_REGS
)
873 mem_cost
= ira_memory_move_cost
[mode
];
874 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
876 rclass
= cost_classes
[k
];
877 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
882 move_in_cost
= ira_may_move_in_cost
[mode
];
883 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
885 rclass
= cost_classes
[k
];
887 = move_in_cost
[rclass
][op_class
] * frequency
;
893 if (op_class
== NO_REGS
)
895 mem_cost
= ira_memory_move_cost
[mode
];
896 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
898 rclass
= cost_classes
[k
];
899 pp_costs
[k
] = ((mem_cost
[rclass
][0]
900 + mem_cost
[rclass
][1])
906 move_in_cost
= ira_may_move_in_cost
[mode
];
907 move_out_cost
= ira_may_move_out_cost
[mode
];
908 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
910 rclass
= cost_classes
[k
];
911 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
912 + move_out_cost
[op_class
][rclass
])
918 if (op_class
== NO_REGS
)
919 /* Although we don't need insn to reload from
920 memory, still accessing memory is usually more
921 expensive than a register. */
922 pp
->mem_cost
= frequency
;
924 /* If the alternative actually allows memory, make
925 things a bit cheaper since we won't need an
926 extra insn to load it. */
928 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
929 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
930 - allows_mem
[i
]) * frequency
;
931 /* If we have assigned a class to this allocno in
932 our first pass, add a cost to this alternative
933 corresponding to what we would add if this
934 allocno were not in the appropriate class. */
937 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
939 if (pref_class
== NO_REGS
)
941 if (op_class
!= NO_REGS
)
944 ? ira_memory_move_cost
[mode
][op_class
][0]
947 ? ira_memory_move_cost
[mode
][op_class
][1]
950 else if (op_class
== NO_REGS
)
953 ? ira_memory_move_cost
[mode
][pref_class
][1]
956 ? ira_memory_move_cost
[mode
][pref_class
][0]
958 else if (ira_reg_class_intersect
[pref_class
][op_class
]
960 alt_cost
+= (ira_register_move_cost
961 [mode
][pref_class
][op_class
]);
966 /* Otherwise, if this alternative wins, either because we
967 have already determined that or if we have a hard
968 register of the proper class, there is no cost for this
970 else if (win
|| (REG_P (op
)
971 && reg_fits_class_p (op
, classes
[i
],
975 /* If registers are valid, the cost of this alternative
976 includes copying the object to and/or from a
978 else if (classes
[i
] != NO_REGS
)
980 if (recog_data
.operand_type
[i
] != OP_OUT
)
981 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
983 if (recog_data
.operand_type
[i
] != OP_IN
)
984 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
986 /* The only other way this alternative can be used is if
987 this is a constant that could be placed into memory. */
988 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
989 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
997 op_cost_add
= alt_cost
* frequency
;
998 /* Finally, update the costs with the information we've
999 calculated about this alternative. */
1000 for (i
= 0; i
< n_ops
; i
++)
1001 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1003 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
1004 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
1005 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1006 cost_classes_t cost_classes_ptr
1007 = regno_cost_classes
[REGNO (ops
[i
])];
1009 pp
->mem_cost
= MIN (pp
->mem_cost
,
1010 (qq
->mem_cost
+ op_cost_add
) * scale
);
1012 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1014 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
1019 for (i
= 0; i
< n_ops
; i
++)
1024 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1026 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
1027 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
1028 ALLOCNO_BAD_SPILL_P (a
) = true;
1035 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1037 ok_for_index_p_nonstrict (rtx reg
)
1039 unsigned regno
= REGNO (reg
);
1041 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1044 /* A version of regno_ok_for_base_p for use here, when all
1045 pseudo-registers should count as OK. Arguments as for
1046 regno_ok_for_base_p. */
1048 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
1049 enum rtx_code outer_code
, enum rtx_code index_code
)
1051 unsigned regno
= REGNO (reg
);
1053 if (regno
>= FIRST_PSEUDO_REGISTER
)
1055 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
1058 /* Record the pseudo registers we must reload into hard registers in a
1059 subexpression of a memory address, X.
1061 If CONTEXT is 0, we are looking at the base part of an address,
1062 otherwise we are looking at the index part.
1064 MODE and AS are the mode and address space of the memory reference;
1065 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1066 These four arguments are passed down to base_reg_class.
1068 SCALE is twice the amount to multiply the cost by (it is twice so
1069 we can represent half-cost adjustments). */
1071 record_address_regs (machine_mode mode
, addr_space_t as
, rtx x
,
1072 int context
, enum rtx_code outer_code
,
1073 enum rtx_code index_code
, int scale
)
1075 enum rtx_code code
= GET_CODE (x
);
1076 enum reg_class rclass
;
1079 rclass
= INDEX_REG_CLASS
;
1081 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1094 /* When we have an address that is a sum, we must determine
1095 whether registers are "base" or "index" regs. If there is a
1096 sum of two registers, we must choose one to be the "base".
1097 Luckily, we can use the REG_POINTER to make a good choice
1098 most of the time. We only need to do this on machines that
1099 can have two registers in an address and where the base and
1100 index register classes are different.
1102 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1103 but that seems bogus since it should only be set when we are
1104 sure the register is being used as a pointer. */
1106 rtx arg0
= XEXP (x
, 0);
1107 rtx arg1
= XEXP (x
, 1);
1108 enum rtx_code code0
= GET_CODE (arg0
);
1109 enum rtx_code code1
= GET_CODE (arg1
);
1111 /* Look inside subregs. */
1112 if (code0
== SUBREG
)
1113 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1114 if (code1
== SUBREG
)
1115 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1117 /* If this machine only allows one register per address, it
1118 must be in the first operand. */
1119 if (MAX_REGS_PER_ADDRESS
== 1)
1120 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1122 /* If index and base registers are the same on this machine,
1123 just record registers in any non-constant operands. We
1124 assume here, as well as in the tests below, that all
1125 addresses are in canonical form. */
1126 else if (INDEX_REG_CLASS
1127 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1129 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1130 if (! CONSTANT_P (arg1
))
1131 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1134 /* If the second operand is a constant integer, it doesn't
1135 change what class the first operand must be. */
1136 else if (CONST_SCALAR_INT_P (arg1
))
1137 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1138 /* If the second operand is a symbolic constant, the first
1139 operand must be an index register. */
1140 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1141 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1142 /* If both operands are registers but one is already a hard
1143 register of index or reg-base class, give the other the
1144 class that the hard register is not. */
1145 else if (code0
== REG
&& code1
== REG
1146 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1147 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1148 || ok_for_index_p_nonstrict (arg0
)))
1149 record_address_regs (mode
, as
, arg1
,
1150 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1153 else if (code0
== REG
&& code1
== REG
1154 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1155 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1156 || ok_for_index_p_nonstrict (arg1
)))
1157 record_address_regs (mode
, as
, arg0
,
1158 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1161 /* If one operand is known to be a pointer, it must be the
1162 base with the other operand the index. Likewise if the
1163 other operand is a MULT. */
1164 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1166 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1167 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1169 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1171 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1172 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1174 /* Otherwise, count equal chances that each might be a base or
1175 index register. This case should be rare. */
1178 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1179 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1180 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1181 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1186 /* Double the importance of an allocno that is incremented or
1187 decremented, since it would take two extra insns if it ends
1188 up in the wrong place. */
1191 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1192 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1193 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1194 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1202 /* Double the importance of an allocno that is incremented or
1203 decremented, since it would take two extra insns if it ends
1204 up in the wrong place. */
1205 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1213 int k
, regno
, add_cost
;
1214 cost_classes_t cost_classes_ptr
;
1215 enum reg_class
*cost_classes
;
1216 move_table
*move_in_cost
;
1218 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1223 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1224 pp
= COSTS (costs
, COST_INDEX (regno
));
1225 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1226 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1227 pp
->mem_cost
= INT_MAX
;
1229 pp
->mem_cost
+= add_cost
;
1230 cost_classes_ptr
= regno_cost_classes
[regno
];
1231 cost_classes
= cost_classes_ptr
->classes
;
1232 pp_costs
= pp
->cost
;
1233 ira_init_register_move_cost_if_necessary (Pmode
);
1234 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1235 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1237 i
= cost_classes
[k
];
1238 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1239 if (INT_MAX
- add_cost
< pp_costs
[k
])
1240 pp_costs
[k
] = INT_MAX
;
1242 pp_costs
[k
] += add_cost
;
1249 const char *fmt
= GET_RTX_FORMAT (code
);
1251 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1253 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1261 /* Calculate the costs of insn operands. */
1263 record_operand_costs (rtx_insn
*insn
, enum reg_class
*pref
)
1265 const char *constraints
[MAX_RECOG_OPERANDS
];
1266 machine_mode modes
[MAX_RECOG_OPERANDS
];
1267 rtx ops
[MAX_RECOG_OPERANDS
];
1271 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1273 constraints
[i
] = recog_data
.constraints
[i
];
1274 modes
[i
] = recog_data
.operand_mode
[i
];
1277 /* If we get here, we are set up to record the costs of all the
1278 operands for this insn. Start by initializing the costs. Then
1279 handle any address registers. Finally record the desired classes
1280 for any allocnos, doing it twice if some pair of operands are
1282 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1284 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1286 ops
[i
] = recog_data
.operand
[i
];
1287 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1288 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1290 if (MEM_P (recog_data
.operand
[i
]))
1291 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1292 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1293 XEXP (recog_data
.operand
[i
], 0),
1294 0, MEM
, SCRATCH
, frequency
* 2);
1295 else if (constraints
[i
][0] == 'p'
1296 || (insn_extra_address_constraint
1297 (lookup_constraint (constraints
[i
]))))
1298 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1299 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1303 /* Check for commutative in a separate loop so everything will have
1304 been initialized. We must do this even if one operand is a
1305 constant--see addsi3 in m68k.md. */
1306 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1307 if (constraints
[i
][0] == '%')
1309 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1312 /* Handle commutative operands by swapping the constraints.
1313 We assume the modes are the same. */
1314 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1315 xconstraints
[j
] = constraints
[j
];
1317 xconstraints
[i
] = constraints
[i
+1];
1318 xconstraints
[i
+1] = constraints
[i
];
1319 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1320 recog_data
.operand
, modes
,
1321 xconstraints
, insn
, pref
);
1323 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1324 recog_data
.operand
, modes
,
1325 constraints
, insn
, pref
);
1327 /* If this insn is a single set copying operand 1 to operand 0 and
1328 one operand is an allocno with the other a hard reg or an allocno
1329 that prefers a hard register that is in its own register class
1330 then we may want to adjust the cost of that register class to -1.
1332 Avoid the adjustment if the source does not die to avoid
1333 stressing of register allocator by preferencing two colliding
1334 registers into single class.
1336 Also avoid the adjustment if a copy between hard registers of the
1337 class is expensive (ten times the cost of a default copy is
1338 considered arbitrarily expensive). This avoids losing when the
1339 preferred class is very expensive as the source of a copy
1341 if ((set
= single_set (insn
)) != NULL_RTX
1342 /* In rare cases the single set insn might have less 2 operands
1343 as the source can be a fixed special reg. */
1344 && recog_data
.n_operands
> 1
1345 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1347 int regno
, other_regno
;
1348 rtx dest
= SET_DEST (set
);
1349 rtx src
= SET_SRC (set
);
1351 if (GET_CODE (dest
) == SUBREG
1352 && (GET_MODE_SIZE (GET_MODE (dest
))
1353 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1354 dest
= SUBREG_REG (dest
);
1355 if (GET_CODE (src
) == SUBREG
1356 && (GET_MODE_SIZE (GET_MODE (src
))
1357 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1358 src
= SUBREG_REG (src
);
1359 if (REG_P (src
) && REG_P (dest
)
1360 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1361 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1362 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1363 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1364 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1366 machine_mode mode
= GET_MODE (src
);
1367 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1368 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1372 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1373 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1375 rclass
= cost_classes
[k
];
1376 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1377 && (reg_class_size
[(int) rclass
]
1378 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1380 if (reg_class_size
[rclass
] == 1)
1381 op_costs
[i
]->cost
[k
] = -frequency
;
1385 nr
< hard_regno_nregs
[other_regno
][mode
];
1387 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1391 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1392 op_costs
[i
]->cost
[k
] = -frequency
;
1402 /* Process one insn INSN. Scan it and record each time it would save
1403 code to put a certain allocnos in a certain class. Return the last
1404 insn processed, so that the scan can be continued from there. */
1406 scan_one_insn (rtx_insn
*insn
)
1408 enum rtx_code pat_code
;
1413 if (!NONDEBUG_INSN_P (insn
))
1416 pat_code
= GET_CODE (PATTERN (insn
));
1417 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1420 counted_mem
= false;
1421 set
= single_set (insn
);
1422 extract_insn (insn
);
1424 /* If this insn loads a parameter from its stack slot, then it
1425 represents a savings, rather than a cost, if the parameter is
1426 stored in memory. Record this fact.
1428 Similarly if we're loading other constants from memory (constant
1429 pool, TOC references, small data areas, etc) and this is the only
1430 assignment to the destination pseudo.
1432 Don't do this if SET_SRC (set) isn't a general operand, if it is
1433 a memory requiring special instructions to load it, decreasing
1434 mem_cost might result in it being loaded using the specialized
1435 instruction into a register, then stored into stack and loaded
1436 again from the stack. See PR52208.
1438 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1439 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1440 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1441 && ((MEM_P (XEXP (note
, 0))
1442 && !side_effects_p (SET_SRC (set
)))
1443 || (CONSTANT_P (XEXP (note
, 0))
1444 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1446 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1447 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1449 enum reg_class cl
= GENERAL_REGS
;
1450 rtx reg
= SET_DEST (set
);
1451 int num
= COST_INDEX (REGNO (reg
));
1453 COSTS (costs
, num
)->mem_cost
1454 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1455 record_address_regs (GET_MODE (SET_SRC (set
)),
1456 MEM_ADDR_SPACE (SET_SRC (set
)),
1457 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1462 record_operand_costs (insn
, pref
);
1464 /* Now add the cost for each operand to the total costs for its
1466 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1467 if (REG_P (recog_data
.operand
[i
])
1468 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1470 int regno
= REGNO (recog_data
.operand
[i
]);
1471 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1472 struct costs
*q
= op_costs
[i
];
1473 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1474 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1477 /* If the already accounted for the memory "cost" above, don't
1481 add_cost
= q
->mem_cost
;
1482 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1483 p
->mem_cost
= INT_MAX
;
1485 p
->mem_cost
+= add_cost
;
1487 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1489 add_cost
= q_costs
[k
];
1490 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1491 p_costs
[k
] = INT_MAX
;
1493 p_costs
[k
] += add_cost
;
1502 /* Print allocnos costs to file F. */
1504 print_allocno_costs (FILE *f
)
1508 ira_allocno_iterator ai
;
1510 ira_assert (allocno_p
);
1512 FOR_EACH_ALLOCNO (a
, ai
)
1516 int regno
= ALLOCNO_REGNO (a
);
1517 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1518 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1520 i
= ALLOCNO_NUM (a
);
1521 fprintf (f
, " a%d(r%d,", i
, regno
);
1522 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1523 fprintf (f
, "b%d", bb
->index
);
1525 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1526 fprintf (f
, ") costs:");
1527 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1529 rclass
= cost_classes
[k
];
1530 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1531 COSTS (costs
, i
)->cost
[k
]);
1532 if (flag_ira_region
== IRA_REGION_ALL
1533 || flag_ira_region
== IRA_REGION_MIXED
)
1534 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1536 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1537 if (flag_ira_region
== IRA_REGION_ALL
1538 || flag_ira_region
== IRA_REGION_MIXED
)
1539 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1544 /* Print pseudo costs to file F. */
1546 print_pseudo_costs (FILE *f
)
1550 cost_classes_t cost_classes_ptr
;
1551 enum reg_class
*cost_classes
;
1553 ira_assert (! allocno_p
);
1555 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1557 if (REG_N_REFS (regno
) <= 0)
1559 cost_classes_ptr
= regno_cost_classes
[regno
];
1560 cost_classes
= cost_classes_ptr
->classes
;
1561 fprintf (f
, " r%d costs:", regno
);
1562 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1564 rclass
= cost_classes
[k
];
1565 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1566 COSTS (costs
, regno
)->cost
[k
]);
1568 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1572 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1575 process_bb_for_costs (basic_block bb
)
1579 frequency
= REG_FREQ_FROM_BB (bb
);
1582 FOR_BB_INSNS (bb
, insn
)
1583 insn
= scan_one_insn (insn
);
1586 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1589 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1593 bb
= loop_tree_node
->bb
;
1595 process_bb_for_costs (bb
);
1598 /* Find costs of register classes and memory for allocnos or pseudos
1599 and their best costs. Set up preferred, alternative and allocno
1600 classes for pseudos. */
1602 find_costs_and_classes (FILE *dump_file
)
1604 int i
, k
, start
, max_cost_classes_num
;
1607 enum reg_class
*regno_best_class
, new_class
;
1611 = (enum reg_class
*) ira_allocate (max_reg_num ()
1612 * sizeof (enum reg_class
));
1613 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1614 regno_best_class
[i
] = NO_REGS
;
1615 if (!resize_reg_info () && allocno_p
1616 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1619 ira_allocno_iterator ai
;
1622 max_cost_classes_num
= 1;
1623 FOR_EACH_ALLOCNO (a
, ai
)
1625 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1626 setup_regno_cost_classes_by_aclass
1627 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1628 max_cost_classes_num
1629 = MAX (max_cost_classes_num
,
1630 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1637 max_cost_classes_num
= ira_important_classes_num
;
1638 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1639 if (regno_reg_rtx
[i
] != NULL_RTX
)
1640 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1642 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1646 /* Clear the flag for the next compiled function. */
1647 pseudo_classes_defined_p
= false;
1648 /* Normally we scan the insns once and determine the best class to
1649 use for each allocno. However, if -fexpensive-optimizations are
1650 on, we do so twice, the second time using the tentative best
1651 classes to guide the selection. */
1652 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1654 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1656 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1660 max_cost_classes_num
= 1;
1661 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1663 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1664 max_cost_classes_num
1665 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1670 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1671 /* Zero out our accumulation of the cost of each class for each
1673 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1677 /* Scan the instructions and record each time it would save code
1678 to put a certain allocno in a certain class. */
1679 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1680 process_bb_node_for_costs
, NULL
);
1682 memcpy (total_allocno_costs
, costs
,
1683 max_struct_costs_size
* ira_allocnos_num
);
1689 FOR_EACH_BB_FN (bb
, cfun
)
1690 process_bb_for_costs (bb
);
1696 /* Now for each allocno look at how desirable each class is and
1697 find which class is preferred. */
1698 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1700 ira_allocno_t a
, parent_a
;
1701 int rclass
, a_num
, parent_a_num
, add_cost
;
1702 ira_loop_tree_node_t parent
;
1703 int best_cost
, allocno_cost
;
1704 enum reg_class best
, alt_class
;
1705 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1706 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1707 int *i_costs
= temp_costs
->cost
;
1709 int equiv_savings
= regno_equiv_gains
[i
];
1713 if (regno_reg_rtx
[i
] == NULL_RTX
)
1715 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1716 i_mem_cost
= temp_costs
->mem_cost
;
1720 if (ira_regno_allocno_map
[i
] == NULL
)
1722 memset (temp_costs
, 0, struct_costs_size
);
1724 /* Find cost of all allocnos with the same regno. */
1725 for (a
= ira_regno_allocno_map
[i
];
1727 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1729 int *a_costs
, *p_costs
;
1731 a_num
= ALLOCNO_NUM (a
);
1732 if ((flag_ira_region
== IRA_REGION_ALL
1733 || flag_ira_region
== IRA_REGION_MIXED
)
1734 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1735 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1736 /* There are no caps yet. */
1737 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1738 (a
)->border_allocnos
,
1741 /* Propagate costs to upper levels in the region
1743 parent_a_num
= ALLOCNO_NUM (parent_a
);
1744 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1745 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1746 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1748 add_cost
= a_costs
[k
];
1749 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1750 p_costs
[k
] = INT_MAX
;
1752 p_costs
[k
] += add_cost
;
1754 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1756 && (INT_MAX
- add_cost
1757 < COSTS (total_allocno_costs
,
1758 parent_a_num
)->mem_cost
))
1759 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1762 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1765 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1766 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1768 a_costs
= COSTS (costs
, a_num
)->cost
;
1769 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1771 add_cost
= a_costs
[k
];
1772 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1773 i_costs
[k
] = INT_MAX
;
1775 i_costs
[k
] += add_cost
;
1777 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1778 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1779 i_mem_cost
= INT_MAX
;
1781 i_mem_cost
+= add_cost
;
1784 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1786 else if (equiv_savings
< 0)
1787 i_mem_cost
= -equiv_savings
;
1788 else if (equiv_savings
> 0)
1791 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1792 i_costs
[k
] += equiv_savings
;
1795 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1797 alt_class
= NO_REGS
;
1798 /* Find best common class for all allocnos with the same
1800 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1802 rclass
= cost_classes
[k
];
1803 if (i_costs
[k
] < best_cost
)
1805 best_cost
= i_costs
[k
];
1806 best
= (enum reg_class
) rclass
;
1808 else if (i_costs
[k
] == best_cost
)
1809 best
= ira_reg_class_subunion
[best
][rclass
];
1810 if (pass
== flag_expensive_optimizations
1811 /* We still prefer registers to memory even at this
1812 stage if their costs are the same. We will make
1813 a final decision during assigning hard registers
1814 when we have all info including more accurate
1815 costs which might be affected by assigning hard
1816 registers to other pseudos because the pseudos
1817 involved in moves can be coalesced. */
1818 && i_costs
[k
] <= i_mem_cost
1819 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1820 > reg_class_size
[alt_class
]))
1821 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1823 alt_class
= ira_allocno_class_translate
[alt_class
];
1824 if (best_cost
> i_mem_cost
1825 && ! non_spilled_static_chain_regno_p (i
))
1826 regno_aclass
[i
] = NO_REGS
;
1827 else if (!optimize
&& !targetm
.class_likely_spilled_p (best
))
1828 /* Registers in the alternative class are likely to need
1829 longer or slower sequences than registers in the best class.
1830 When optimizing we make some effort to use the best class
1831 over the alternative class where possible, but at -O0 we
1832 effectively give the alternative class equal weight.
1833 We then run the risk of using slower alternative registers
1834 when plenty of registers from the best class are still free.
1835 This is especially true because live ranges tend to be very
1836 short in -O0 code and so register pressure tends to be low.
1838 Avoid that by ignoring the alternative class if the best
1839 class has plenty of registers. */
1840 regno_aclass
[i
] = best
;
1843 /* Make the common class the biggest class of best and
1846 = ira_reg_class_superunion
[best
][alt_class
];
1847 ira_assert (regno_aclass
[i
] != NO_REGS
1848 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1851 = (reg_class
) (targetm
.ira_change_pseudo_allocno_class
1852 (i
, regno_aclass
[i
]))) != regno_aclass
[i
])
1854 regno_aclass
[i
] = new_class
;
1855 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1856 reg_class_contents
[best
]))
1858 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1859 reg_class_contents
[alt_class
]))
1860 alt_class
= new_class
;
1862 if (pass
== flag_expensive_optimizations
)
1864 if (best_cost
> i_mem_cost
1865 /* Do not assign NO_REGS to static chain pointer
1866 pseudo when non-local goto is used. */
1867 && ! non_spilled_static_chain_regno_p (i
))
1868 best
= alt_class
= NO_REGS
;
1869 else if (best
== alt_class
)
1870 alt_class
= NO_REGS
;
1871 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1872 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1873 && dump_file
!= NULL
)
1875 " r%d: preferred %s, alternative %s, allocno %s\n",
1876 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1877 reg_class_names
[regno_aclass
[i
]]);
1879 regno_best_class
[i
] = best
;
1882 pref
[i
] = (best_cost
> i_mem_cost
1883 && ! non_spilled_static_chain_regno_p (i
)
1887 for (a
= ira_regno_allocno_map
[i
];
1889 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1891 enum reg_class aclass
= regno_aclass
[i
];
1892 int a_num
= ALLOCNO_NUM (a
);
1893 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1894 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1896 if (aclass
== NO_REGS
)
1900 /* Finding best class which is subset of the common
1902 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1903 allocno_cost
= best_cost
;
1905 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1907 rclass
= cost_classes
[k
];
1908 if (! ira_class_subset_p
[rclass
][aclass
])
1910 if (total_a_costs
[k
] < best_cost
)
1912 best_cost
= total_a_costs
[k
];
1913 allocno_cost
= a_costs
[k
];
1914 best
= (enum reg_class
) rclass
;
1916 else if (total_a_costs
[k
] == best_cost
)
1918 best
= ira_reg_class_subunion
[best
][rclass
];
1919 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1922 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1924 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1925 && (pass
== 0 || pref
[a_num
] != best
))
1927 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1928 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1929 fprintf (dump_file
, "b%d", bb
->index
);
1931 fprintf (dump_file
, "l%d",
1932 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1933 fprintf (dump_file
, ") best %s, allocno %s\n",
1934 reg_class_names
[best
],
1935 reg_class_names
[aclass
]);
1938 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1939 && ira_class_hard_regs_num
[best
] > 0
1940 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1941 >= ira_class_hard_regs_num
[best
]))
1943 int ind
= cost_classes_ptr
->index
[aclass
];
1945 ira_assert (ind
>= 0);
1946 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1947 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1948 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1949 / (ira_register_move_cost
1950 [ALLOCNO_MODE (a
)][best
][aclass
]));
1951 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1952 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1953 a_costs
[k
] = a_costs
[ind
];
1958 if (internal_flag_ira_verbose
> 4 && dump_file
)
1961 print_allocno_costs (dump_file
);
1963 print_pseudo_costs (dump_file
);
1964 fprintf (dump_file
,"\n");
1967 ira_free (regno_best_class
);
1972 /* Process moves involving hard regs to modify allocno hard register
1973 costs. We can do this only after determining allocno class. If a
1974 hard register forms a register class, then moves with the hard
1975 register are already taken into account in class costs for the
1978 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1980 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1982 ira_allocno_t a
, curr_a
;
1983 ira_loop_tree_node_t curr_loop_tree_node
;
1984 enum reg_class rclass
;
1989 bb
= loop_tree_node
->bb
;
1992 freq
= REG_FREQ_FROM_BB (bb
);
1995 FOR_BB_INSNS (bb
, insn
)
1997 if (!NONDEBUG_INSN_P (insn
))
1999 set
= single_set (insn
);
2000 if (set
== NULL_RTX
)
2002 dst
= SET_DEST (set
);
2003 src
= SET_SRC (set
);
2004 if (! REG_P (dst
) || ! REG_P (src
))
2006 dst_regno
= REGNO (dst
);
2007 src_regno
= REGNO (src
);
2008 if (dst_regno
>= FIRST_PSEUDO_REGISTER
2009 && src_regno
< FIRST_PSEUDO_REGISTER
)
2011 hard_regno
= src_regno
;
2012 a
= ira_curr_regno_allocno_map
[dst_regno
];
2015 else if (src_regno
>= FIRST_PSEUDO_REGISTER
2016 && dst_regno
< FIRST_PSEUDO_REGISTER
)
2018 hard_regno
= dst_regno
;
2019 a
= ira_curr_regno_allocno_map
[src_regno
];
2024 rclass
= ALLOCNO_CLASS (a
);
2025 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
2027 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
2030 a_regno
= ALLOCNO_REGNO (a
);
2031 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
2032 curr_loop_tree_node
!= NULL
;
2033 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
2034 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
2035 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
2038 enum reg_class hard_reg_class
;
2041 mode
= ALLOCNO_MODE (a
);
2042 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
2043 ira_init_register_move_cost_if_necessary (mode
);
2044 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
2045 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
2046 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
2047 ALLOCNO_CLASS_COST (a
));
2048 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
2050 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
2051 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
2052 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
2053 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
2058 /* After we find hard register and memory costs for allocnos, define
2059 its class and modify hard register cost because insns moving
2060 allocno to/from hard registers. */
2062 setup_allocno_class_and_costs (void)
2064 int i
, j
, n
, regno
, hard_regno
, num
;
2066 enum reg_class aclass
, rclass
;
2068 ira_allocno_iterator ai
;
2069 cost_classes_t cost_classes_ptr
;
2071 ira_assert (allocno_p
);
2072 FOR_EACH_ALLOCNO (a
, ai
)
2074 i
= ALLOCNO_NUM (a
);
2075 regno
= ALLOCNO_REGNO (a
);
2076 aclass
= regno_aclass
[regno
];
2077 cost_classes_ptr
= regno_cost_classes
[regno
];
2078 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2079 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2080 ira_set_allocno_class (a
, aclass
);
2081 if (aclass
== NO_REGS
)
2083 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2085 n
= ira_class_hard_regs_num
[aclass
];
2086 ALLOCNO_HARD_REG_COSTS (a
)
2087 = reg_costs
= ira_allocate_cost_vector (aclass
);
2088 for (j
= n
- 1; j
>= 0; j
--)
2090 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2091 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2092 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2095 rclass
= REGNO_REG_CLASS (hard_regno
);
2096 num
= cost_classes_ptr
->index
[rclass
];
2099 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2100 ira_assert (num
>= 0);
2102 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2108 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2109 process_bb_node_for_hard_reg_moves
, NULL
);
2114 /* Function called once during compiler work. */
2116 ira_init_costs_once (void)
2121 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2124 this_op_costs
[i
] = NULL
;
2129 /* Free allocated temporary cost vectors. */
2131 target_ira_int::free_ira_costs ()
2137 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2139 free (x_op_costs
[i
]);
2140 free (x_this_op_costs
[i
]);
2141 x_op_costs
[i
] = x_this_op_costs
[i
] = NULL
;
2143 free (x_temp_costs
);
2144 x_temp_costs
= NULL
;
2147 /* This is called each time register related information is
2150 ira_init_costs (void)
2154 this_target_ira_int
->free_ira_costs ();
2155 max_struct_costs_size
2156 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2157 /* Don't use ira_allocate because vectors live through several IRA
2159 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2160 init_cost
->mem_cost
= 1000000;
2161 for (i
= 0; i
< ira_important_classes_num
; i
++)
2162 init_cost
->cost
[i
] = 1000000;
2163 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2165 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2166 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2168 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2173 /* Common initialization function for ira_costs and
2174 ira_set_pseudo_classes. */
2178 init_subregs_of_mode ();
2179 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2180 * cost_elements_num
);
2181 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2182 * cost_elements_num
);
2183 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2185 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2186 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2189 /* Common finalization function for ira_costs and
2190 ira_set_pseudo_classes. */
2194 finish_subregs_of_mode ();
2195 ira_free (regno_equiv_gains
);
2196 ira_free (regno_aclass
);
2197 ira_free (pref_buffer
);
2201 /* Entry function which defines register class, memory and hard
2202 register costs for each allocno. */
2207 cost_elements_num
= ira_allocnos_num
;
2209 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2210 * ira_allocnos_num
);
2211 initiate_regno_cost_classes ();
2212 calculate_elim_costs_all_insns ();
2213 find_costs_and_classes (ira_dump_file
);
2214 setup_allocno_class_and_costs ();
2215 finish_regno_cost_classes ();
2217 ira_free (total_allocno_costs
);
2220 /* Entry function which defines classes for pseudos.
2221 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2223 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2226 internal_flag_ira_verbose
= flag_ira_verbose
;
2227 cost_elements_num
= max_reg_num ();
2229 initiate_regno_cost_classes ();
2230 find_costs_and_classes (dump_file
);
2231 finish_regno_cost_classes ();
2232 if (define_pseudo_classes
)
2233 pseudo_classes_defined_p
= true;
2240 /* Change hard register costs for allocnos which lives through
2241 function calls. This is called only when we found all intersected
2242 calls during building allocno live ranges. */
2244 ira_tune_allocno_costs (void)
2247 int cost
, min_cost
, *reg_costs
;
2248 enum reg_class aclass
, rclass
;
2251 ira_allocno_iterator ai
;
2252 ira_allocno_object_iterator oi
;
2255 HARD_REG_SET
*crossed_calls_clobber_regs
;
2257 FOR_EACH_ALLOCNO (a
, ai
)
2259 aclass
= ALLOCNO_CLASS (a
);
2260 if (aclass
== NO_REGS
)
2262 mode
= ALLOCNO_MODE (a
);
2263 n
= ira_class_hard_regs_num
[aclass
];
2265 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2266 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2268 ira_allocate_and_set_costs
2269 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2270 ALLOCNO_CLASS_COST (a
));
2271 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2272 for (j
= n
- 1; j
>= 0; j
--)
2274 regno
= ira_class_hard_regs
[aclass
][j
];
2276 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2278 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2279 OBJECT_CONFLICT_HARD_REGS
2288 rclass
= REGNO_REG_CLASS (regno
);
2290 crossed_calls_clobber_regs
2291 = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
));
2292 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2293 *crossed_calls_clobber_regs
)
2294 && (ira_hard_reg_set_intersection_p (regno
, mode
,
2296 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2297 cost
+= (ALLOCNO_CALL_FREQ (a
)
2298 * (ira_memory_move_cost
[mode
][rclass
][0]
2299 + ira_memory_move_cost
[mode
][rclass
][1]));
2300 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2301 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2302 + ira_memory_move_cost
[mode
][rclass
][1])
2304 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2306 if (INT_MAX
- cost
< reg_costs
[j
])
2307 reg_costs
[j
] = INT_MAX
;
2309 reg_costs
[j
] += cost
;
2310 if (min_cost
> reg_costs
[j
])
2311 min_cost
= reg_costs
[j
];
2314 if (min_cost
!= INT_MAX
)
2315 ALLOCNO_CLASS_COST (a
) = min_cost
;
2317 /* Some targets allow pseudos to be allocated to unaligned sequences
2318 of hard registers. However, selecting an unaligned sequence can
2319 unnecessarily restrict later allocations. So increase the cost of
2320 unaligned hard regs to encourage the use of aligned hard regs. */
2322 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2326 ira_allocate_and_set_costs
2327 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2328 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2329 for (j
= n
- 1; j
>= 0; j
--)
2331 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2332 if ((regno
% nregs
) != 0)
2334 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2335 ira_assert (index
!= -1);
2336 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2344 /* Add COST to the estimated gain for eliminating REGNO with its
2345 equivalence. If COST is zero, record that no such elimination is
2349 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2352 regno_equiv_gains
[regno
] = 0;
2354 regno_equiv_gains
[regno
] += cost
;
2358 ira_costs_c_finalize (void)
2360 this_target_ira_int
->free_ira_costs ();