1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx
*reg_last_reload_reg
;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload
;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload
;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx
*reg_equiv_constant
;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx
*reg_equiv_memory_loc
;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray
;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx
*reg_equiv_address
;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width
;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx
*reg_equiv_init
;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber
;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid
;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead
;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs
;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global
;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET
*pseudo_previous_regs
;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET
*pseudo_forbidden_regs
;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs
;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg
;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels
;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok
;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok
;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos
;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted
;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid
;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed
;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress
= 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
266 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 static struct obstack reload_obstack
;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj
;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj
;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj
;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain
*reload_insn_chain
;
289 /* List of all insns needing reloads. */
290 static struct insn_chain
*insns_need_reload
;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from
; /* Register number to be eliminated. */
300 int to
; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
302 int can_eliminate
; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
307 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx
; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx
; /* REG rtx for the replacement. */
316 static struct elim_table
*reg_eliminate
= 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1
[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset
;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable
;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants
;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num
;
359 static char *offsets_known_at
;
360 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
362 /* Number of labels in the current function. */
364 static int num_labels
;
366 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain
*);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain
*, int);
371 static void find_reload_regs (struct insn_chain
*);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx
, enum reg_class
);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx
);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx
, rtx
, int);
380 static void check_eliminable_occurrences (rtx
);
381 static void elimination_effects (rtx
, enum machine_mode
);
382 static int eliminate_regs_in_insn (rtx
, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx
, rtx
, void *);
385 static void set_initial_elim_offsets (void);
386 static bool verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx
);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET
*);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx
);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain
*);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx
, rtx
, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
406 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
408 static int function_invariant_p (rtx
);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
410 static int allocate_reload_reg (struct insn_chain
*, int, int);
411 static int conflicts_with_override (rtx
);
412 static void failed_reload (rtx
, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
415 static void choose_reload_regs (struct insn_chain
*);
416 static void merge_assigned_reloads (rtx
);
417 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
419 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
421 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
422 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain
*);
425 static void delete_output_reload (rtx
, int, int);
426 static void delete_address_reloads (rtx
, rtx
);
427 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
428 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
430 static void add_auto_inc_notes (rtx
, rtx
);
432 static void copy_eh_notes (rtx
, rtx
);
433 static int reloads_conflict (int, int);
434 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode
,
451 LAST_VIRTUAL_REGISTER
+ 1),
453 spill_indirect_levels
= 0;
455 while (memory_address_p (QImode
, tem
))
457 spill_indirect_levels
++;
458 tem
= gen_rtx_MEM (Pmode
, tem
);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
464 indirect_symref_ok
= memory_address_p (QImode
, tem
);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
470 tem
= gen_rtx_PLUS (Pmode
,
471 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
472 gen_rtx_REG (Pmode
, i
));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem
= plus_constant (tem
, 4);
477 if (memory_address_p (QImode
, tem
))
479 double_reg_address_ok
= 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack
);
486 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
488 INIT_REG_SET (&spilled_pseudos
);
489 INIT_REG_SET (&pseudos_counted
);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray
, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain
*unused_insn_chains
= 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain
*c
;
502 if (unused_insn_chains
== 0)
504 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
505 INIT_REG_SET (&c
->live_throughout
);
506 INIT_REG_SET (&c
->dead_or_set
);
510 c
= unused_insn_chains
;
511 unused_insn_chains
= c
->next
;
513 c
->is_caller_save_insn
= 0;
514 c
->need_operand_change
= 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
527 reg_set_iterator rsi
;
529 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
531 int r
= reg_renumber
[regno
];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed
);
544 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (regno
)];
546 SET_HARD_REG_BIT (*to
, r
+ nregs
);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
568 unsigned int regno
= REGNO (x
);
570 if (regno
< FIRST_PSEUDO_REGISTER
)
573 x
= eliminate_regs (x
, mem_mode
, usage
);
577 replace_pseudos_in (loc
, mem_mode
, usage
);
581 if (reg_equiv_constant
[regno
])
582 *loc
= reg_equiv_constant
[regno
];
583 else if (reg_equiv_mem
[regno
])
584 *loc
= reg_equiv_mem
[regno
];
585 else if (reg_equiv_address
[regno
])
586 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
589 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
590 || REGNO (regno_reg_rtx
[regno
]) != regno
);
591 *loc
= regno_reg_rtx
[regno
];
596 else if (code
== MEM
)
598 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
602 /* Process each of our operands recursively. */
603 fmt
= GET_RTX_FORMAT (code
);
604 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
606 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
607 else if (*fmt
== 'E')
608 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
609 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination
;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed
;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first
, int global
)
641 struct elim_table
*ep
;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED
);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid
= get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
665 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label
)
681 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
682 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
683 regs_ever_live
[i
] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant
= xcalloc (max_regno
, sizeof (rtx
));
696 reg_equiv_mem
= xcalloc (max_regno
, sizeof (rtx
));
697 reg_equiv_init
= xcalloc (max_regno
, sizeof (rtx
));
698 reg_equiv_address
= xcalloc (max_regno
, sizeof (rtx
));
699 reg_max_ref_width
= xcalloc (max_regno
, sizeof (int));
700 reg_old_renumber
= xcalloc (max_regno
, sizeof (short));
701 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
702 pseudo_forbidden_regs
= xmalloc (max_regno
* sizeof (HARD_REG_SET
));
703 pseudo_previous_regs
= xcalloc (max_regno
, sizeof (HARD_REG_SET
));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants
= 0;
712 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
714 rtx set
= single_set (insn
);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
720 && GET_MODE (insn
) != VOIDmode
)
721 PUT_MODE (insn
, VOIDmode
);
723 if (set
!= 0 && REG_P (SET_DEST (set
)))
725 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
727 && (! function_invariant_p (XEXP (note
, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note
, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))))
735 rtx x
= XEXP (note
, 0);
736 i
= REGNO (SET_DEST (set
));
737 if (i
> LAST_VIRTUAL_REGISTER
)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
744 It can also happen that a REG_EQUIV note contains a
745 readonly memory location. If the destination pseudo
746 is set from some other value (typically a different
747 pseudo), and the destination pseudo does not get a
748 hard reg, then reload will replace the destination
749 pseudo with its equivalent memory location. This
750 is horribly bad as it creates a store to a readonly
751 memory location and a runtime segfault. To avoid
752 this problem we reject readonly memory locations
753 for equivalences. This is overly conservative as
754 we could find all sets of the destination pseudo
755 and remove them as they should be redundant. */
756 if (memory_operand (x
, VOIDmode
) && ! MEM_READONLY_P (x
))
758 /* Always unshare the equivalence, so we can
759 substitute into this insn without touching the
761 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
763 else if (function_invariant_p (x
))
765 if (GET_CODE (x
) == PLUS
)
767 /* This is PLUS of frame pointer and a constant,
768 and might be shared. Unshare it. */
769 reg_equiv_constant
[i
] = copy_rtx (x
);
770 num_eliminable_invariants
++;
772 else if (x
== frame_pointer_rtx
773 || x
== arg_pointer_rtx
)
775 reg_equiv_constant
[i
] = x
;
776 num_eliminable_invariants
++;
778 else if (LEGITIMATE_CONSTANT_P (x
))
779 reg_equiv_constant
[i
] = x
;
782 reg_equiv_memory_loc
[i
]
783 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
784 if (!reg_equiv_memory_loc
[i
])
791 /* If this register is being made equivalent to a MEM
792 and the MEM is not SET_SRC, the equivalencing insn
793 is one with the MEM as a SET_DEST and it occurs later.
794 So don't mark this insn now. */
796 || rtx_equal_p (SET_SRC (set
), x
))
798 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
803 /* If this insn is setting a MEM from a register equivalent to it,
804 this is the equivalencing insn. */
805 else if (set
&& MEM_P (SET_DEST (set
))
806 && REG_P (SET_SRC (set
))
807 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
808 && rtx_equal_p (SET_DEST (set
),
809 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
810 reg_equiv_init
[REGNO (SET_SRC (set
))]
811 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
812 reg_equiv_init
[REGNO (SET_SRC (set
))]);
815 scan_paradoxical_subregs (PATTERN (insn
));
820 first_label_num
= get_first_label_num ();
821 num_labels
= max_label_num () - first_label_num
;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at
= xmalloc (num_labels
);
828 offsets_at
= xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
845 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
847 maybe_fix_stack_asms ();
849 insns_need_reload
= 0;
850 something_needs_elimination
= 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs
);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
863 int can_eliminate
= 0;
866 can_eliminate
|= ep
->can_eliminate
;
869 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
871 spill_hard_reg (from
, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed
)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
878 finish_spills (global
);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress
= 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed
;
892 HOST_WIDE_INT starting_frame_size
;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun
->stack_alignment_needed
)
899 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
901 starting_frame_size
= get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
931 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
933 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
937 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
938 else if (CONSTANT_P (XEXP (x
, 0))
939 || (REG_P (XEXP (x
, 0))
940 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
941 || (GET_CODE (XEXP (x
, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x
, 0), 0))
943 && (REGNO (XEXP (XEXP (x
, 0), 0))
944 < FIRST_PSEUDO_REGISTER
)
945 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
946 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc
[i
] = 0;
956 reg_equiv_init
[i
] = 0;
961 if (caller_save_needed
)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size
!= get_frame_size ())
968 if (caller_save_needed
)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
975 calculate_needs_all_insns (global
);
977 CLEAR_REG_SET (&spilled_pseudos
);
980 something_changed
= 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size
!= get_frame_size ())
985 something_changed
= 1;
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed
= 1;
995 HARD_REG_SET to_spill
;
996 CLEAR_HARD_REG_SET (to_spill
);
997 update_eliminables (&to_spill
);
998 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
999 if (TEST_HARD_REG_BIT (to_spill
, i
))
1001 spill_hard_reg (i
, 1);
1004 /* Regardless of the state of spills, if we previously had
1005 a register that we thought we could eliminate, but now can
1006 not eliminate, we must run another pass.
1008 Consider pseudos which have an entry in reg_equiv_* which
1009 reference an eliminable register. We must make another pass
1010 to update reg_equiv_* so that we do not substitute in the
1011 old value from when we thought the elimination could be
1013 something_changed
= 1;
1017 select_reload_regs ();
1021 if (insns_need_reload
!= 0 || did_spill
)
1022 something_changed
|= finish_spills (global
);
1024 if (! something_changed
)
1027 if (caller_save_needed
)
1028 delete_caller_save_insns ();
1030 obstack_free (&reload_obstack
, reload_firstobj
);
1033 /* If global-alloc was run, notify it of any register eliminations we have
1036 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1037 if (ep
->can_eliminate
)
1038 mark_elimination (ep
->from
, ep
->to
);
1040 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1041 If that insn didn't set the register (i.e., it copied the register to
1042 memory), just delete that insn instead of the equivalencing insn plus
1043 anything now dead. If we call delete_dead_insn on that insn, we may
1044 delete the insn that actually sets the register if the register dies
1045 there and that is incorrect. */
1047 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1049 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1052 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1054 rtx equiv_insn
= XEXP (list
, 0);
1056 /* If we already deleted the insn or if it may trap, we can't
1057 delete it. The latter case shouldn't happen, but can
1058 if an insn has a variable address, gets a REG_EH_REGION
1059 note added to it, and then gets converted into an load
1060 from a constant address. */
1061 if (NOTE_P (equiv_insn
)
1062 || can_throw_internal (equiv_insn
))
1064 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1065 delete_dead_insn (equiv_insn
);
1067 SET_INSN_DELETED (equiv_insn
);
1072 /* Use the reload registers where necessary
1073 by generating move instructions to move the must-be-register
1074 values into or out of the reload registers. */
1076 if (insns_need_reload
!= 0 || something_needs_elimination
1077 || something_needs_operands_changed
)
1079 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1081 reload_as_needed (global
);
1083 gcc_assert (old_frame_size
== get_frame_size ());
1085 gcc_assert (verify_initial_elim_offsets ());
1088 /* If we were able to eliminate the frame pointer, show that it is no
1089 longer live at the start of any basic block. If it ls live by
1090 virtue of being in a pseudo, that pseudo will be marked live
1091 and hence the frame pointer will be known to be live via that
1094 if (! frame_pointer_needed
)
1096 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
,
1097 HARD_FRAME_POINTER_REGNUM
);
1099 /* Come here (with failure set nonzero) if we can't get enough spill
1103 CLEAR_REG_SET (&spilled_pseudos
);
1104 reload_in_progress
= 0;
1106 /* Now eliminate all pseudo regs by modifying them into
1107 their equivalent memory references.
1108 The REG-rtx's for the pseudos are modified in place,
1109 so all insns that used to refer to them now refer to memory.
1111 For a reg that has a reg_equiv_address, all those insns
1112 were changed by reloading so that no insns refer to it any longer;
1113 but the DECL_RTL of a variable decl may refer to it,
1114 and if so this causes the debugging info to mention the variable. */
1116 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1120 if (reg_equiv_mem
[i
])
1121 addr
= XEXP (reg_equiv_mem
[i
], 0);
1123 if (reg_equiv_address
[i
])
1124 addr
= reg_equiv_address
[i
];
1128 if (reg_renumber
[i
] < 0)
1130 rtx reg
= regno_reg_rtx
[i
];
1132 REG_USERVAR_P (reg
) = 0;
1133 PUT_CODE (reg
, MEM
);
1134 XEXP (reg
, 0) = addr
;
1135 if (reg_equiv_memory_loc
[i
])
1136 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1139 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1140 MEM_ATTRS (reg
) = 0;
1143 else if (reg_equiv_mem
[i
])
1144 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1148 /* We must set reload_completed now since the cleanup_subreg_operands call
1149 below will re-recognize each insn and reload may have generated insns
1150 which are only valid during and after reload. */
1151 reload_completed
= 1;
1153 /* Make a pass over all the insns and delete all USEs which we inserted
1154 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1155 notes. Delete all CLOBBER insns, except those that refer to the return
1156 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1157 from misarranging variable-array code, and simplify (subreg (reg))
1158 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1159 are no longer useful or accurate. Strip and regenerate REG_INC notes
1160 that may have been moved around. */
1162 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1168 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1169 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1171 if ((GET_CODE (PATTERN (insn
)) == USE
1172 /* We mark with QImode USEs introduced by reload itself. */
1173 && (GET_MODE (insn
) == QImode
1174 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1175 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1176 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1177 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1178 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1179 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1180 != stack_pointer_rtx
))
1181 && (!REG_P (XEXP (PATTERN (insn
), 0))
1182 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1188 /* Some CLOBBERs may survive until here and still reference unassigned
1189 pseudos with const equivalent, which may in turn cause ICE in later
1190 passes if the reference remains in place. */
1191 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1192 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1193 VOIDmode
, PATTERN (insn
));
1195 /* Discard obvious no-ops, even without -O. This optimization
1196 is fast and doesn't interfere with debugging. */
1197 if (NONJUMP_INSN_P (insn
)
1198 && GET_CODE (PATTERN (insn
)) == SET
1199 && REG_P (SET_SRC (PATTERN (insn
)))
1200 && REG_P (SET_DEST (PATTERN (insn
)))
1201 && (REGNO (SET_SRC (PATTERN (insn
)))
1202 == REGNO (SET_DEST (PATTERN (insn
)))))
1208 pnote
= ®_NOTES (insn
);
1211 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1212 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1213 || REG_NOTE_KIND (*pnote
) == REG_INC
1214 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1215 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1216 *pnote
= XEXP (*pnote
, 1);
1218 pnote
= &XEXP (*pnote
, 1);
1222 add_auto_inc_notes (insn
, PATTERN (insn
));
1225 /* And simplify (subreg (reg)) if it appears as an operand. */
1226 cleanup_subreg_operands (insn
);
1229 /* If we are doing stack checking, give a warning if this function's
1230 frame size is larger than we expect. */
1231 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1233 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1234 static int verbose_warned
= 0;
1236 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1237 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1238 size
+= UNITS_PER_WORD
;
1240 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1242 warning (0, "frame size too large for reliable stack checking");
1243 if (! verbose_warned
)
1245 warning (0, "try reducing the number of local variables");
1251 /* Indicate that we no longer have known memory locations or constants. */
1252 if (reg_equiv_constant
)
1253 free (reg_equiv_constant
);
1254 reg_equiv_constant
= 0;
1255 VARRAY_GROW (reg_equiv_memory_loc_varray
, 0);
1256 reg_equiv_memory_loc
= 0;
1258 if (offsets_known_at
)
1259 free (offsets_known_at
);
1263 free (reg_equiv_mem
);
1264 free (reg_equiv_init
);
1265 free (reg_equiv_address
);
1266 free (reg_max_ref_width
);
1267 free (reg_old_renumber
);
1268 free (pseudo_previous_regs
);
1269 free (pseudo_forbidden_regs
);
1271 CLEAR_HARD_REG_SET (used_spill_regs
);
1272 for (i
= 0; i
< n_spills
; i
++)
1273 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1275 /* Free all the insn_chain structures at once. */
1276 obstack_free (&reload_obstack
, reload_startobj
);
1277 unused_insn_chains
= 0;
1278 fixup_abnormal_edges ();
1280 /* Replacing pseudos with their memory equivalents might have
1281 created shared rtx. Subsequent passes would get confused
1282 by this, so unshare everything here. */
1283 unshare_all_rtl_again (first
);
1285 #ifdef STACK_BOUNDARY
1286 /* init_emit has set the alignment of the hard frame pointer
1287 to STACK_BOUNDARY. It is very likely no longer valid if
1288 the hard frame pointer was used for register allocation. */
1289 if (!frame_pointer_needed
)
1290 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1296 /* Yet another special case. Unfortunately, reg-stack forces people to
1297 write incorrect clobbers in asm statements. These clobbers must not
1298 cause the register to appear in bad_spill_regs, otherwise we'll call
1299 fatal_insn later. We clear the corresponding regnos in the live
1300 register sets to avoid this.
1301 The whole thing is rather sick, I'm afraid. */
1304 maybe_fix_stack_asms (void)
1307 const char *constraints
[MAX_RECOG_OPERANDS
];
1308 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1309 struct insn_chain
*chain
;
1311 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1314 HARD_REG_SET clobbered
, allowed
;
1317 if (! INSN_P (chain
->insn
)
1318 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1320 pat
= PATTERN (chain
->insn
);
1321 if (GET_CODE (pat
) != PARALLEL
)
1324 CLEAR_HARD_REG_SET (clobbered
);
1325 CLEAR_HARD_REG_SET (allowed
);
1327 /* First, make a mask of all stack regs that are clobbered. */
1328 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1330 rtx t
= XVECEXP (pat
, 0, i
);
1331 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1332 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1335 /* Get the operand values and constraints out of the insn. */
1336 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1337 constraints
, operand_mode
);
1339 /* For every operand, see what registers are allowed. */
1340 for (i
= 0; i
< noperands
; i
++)
1342 const char *p
= constraints
[i
];
1343 /* For every alternative, we compute the class of registers allowed
1344 for reloading in CLS, and merge its contents into the reg set
1346 int cls
= (int) NO_REGS
;
1352 if (c
== '\0' || c
== ',' || c
== '#')
1354 /* End of one alternative - mark the regs in the current
1355 class, and reset the class. */
1356 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1362 } while (c
!= '\0' && c
!= ',');
1370 case '=': case '+': case '*': case '%': case '?': case '!':
1371 case '0': case '1': case '2': case '3': case '4': case 'm':
1372 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1373 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1374 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1379 cls
= (int) reg_class_subunion
[cls
]
1380 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1385 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1389 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1390 cls
= (int) reg_class_subunion
[cls
]
1391 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1393 cls
= (int) reg_class_subunion
[cls
]
1394 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1396 p
+= CONSTRAINT_LEN (c
, p
);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 AND_HARD_REG_SET (allowed
, clobbered
);
1403 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1404 if (TEST_HARD_REG_BIT (allowed
, i
))
1406 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1407 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (struct insn_chain
*chain
)
1419 chain
->n_reloads
= n_reloads
;
1420 chain
->rld
= obstack_alloc (&reload_obstack
,
1421 n_reloads
* sizeof (struct reload
));
1422 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1423 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1426 /* Walk the chain of insns, and determine for each whether it needs reloads
1427 and/or eliminations. Build the corresponding insns_need_reload list, and
1428 set something_needs_elimination as appropriate. */
1430 calculate_needs_all_insns (int global
)
1432 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1433 struct insn_chain
*chain
, *next
= 0;
1435 something_needs_elimination
= 0;
1437 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1438 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1440 rtx insn
= chain
->insn
;
1444 /* Clear out the shortcuts. */
1445 chain
->n_reloads
= 0;
1446 chain
->need_elim
= 0;
1447 chain
->need_reload
= 0;
1448 chain
->need_operand_change
= 0;
1450 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1451 include REG_LABEL), we need to see what effects this has on the
1452 known offsets at labels. */
1454 if (LABEL_P (insn
) || JUMP_P (insn
)
1455 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1456 set_label_offsets (insn
, insn
, 0);
1460 rtx old_body
= PATTERN (insn
);
1461 int old_code
= INSN_CODE (insn
);
1462 rtx old_notes
= REG_NOTES (insn
);
1463 int did_elimination
= 0;
1464 int operands_changed
= 0;
1465 rtx set
= single_set (insn
);
1467 /* Skip insns that only set an equivalence. */
1468 if (set
&& REG_P (SET_DEST (set
))
1469 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1470 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1473 /* If needed, eliminate any eliminable registers. */
1474 if (num_eliminable
|| num_eliminable_invariants
)
1475 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1477 /* Analyze the instruction. */
1478 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1479 global
, spill_reg_order
);
1481 /* If a no-op set needs more than one reload, this is likely
1482 to be something that needs input address reloads. We
1483 can't get rid of this cleanly later, and it is of no use
1484 anyway, so discard it now.
1485 We only do this when expensive_optimizations is enabled,
1486 since this complements reload inheritance / output
1487 reload deletion, and it can make debugging harder. */
1488 if (flag_expensive_optimizations
&& n_reloads
> 1)
1490 rtx set
= single_set (insn
);
1492 && SET_SRC (set
) == SET_DEST (set
)
1493 && REG_P (SET_SRC (set
))
1494 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1497 /* Delete it from the reload chain. */
1499 chain
->prev
->next
= next
;
1501 reload_insn_chain
= next
;
1503 next
->prev
= chain
->prev
;
1504 chain
->next
= unused_insn_chains
;
1505 unused_insn_chains
= chain
;
1510 update_eliminable_offsets ();
1512 /* Remember for later shortcuts which insns had any reloads or
1513 register eliminations. */
1514 chain
->need_elim
= did_elimination
;
1515 chain
->need_reload
= n_reloads
> 0;
1516 chain
->need_operand_change
= operands_changed
;
1518 /* Discard any register replacements done. */
1519 if (did_elimination
)
1521 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1522 PATTERN (insn
) = old_body
;
1523 INSN_CODE (insn
) = old_code
;
1524 REG_NOTES (insn
) = old_notes
;
1525 something_needs_elimination
= 1;
1528 something_needs_operands_changed
|= operands_changed
;
1532 copy_reloads (chain
);
1533 *pprev_reload
= chain
;
1534 pprev_reload
= &chain
->next_need_reload
;
1541 /* Comparison function for qsort to decide which of two reloads
1542 should be handled first. *P1 and *P2 are the reload numbers. */
1545 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1547 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1550 /* Consider required reloads before optional ones. */
1551 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1555 /* Count all solitary classes before non-solitary ones. */
1556 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1557 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1561 /* Aside from solitaires, consider all multi-reg groups first. */
1562 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1566 /* Consider reloads in order of increasing reg-class number. */
1567 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1571 /* If reloads are equally urgent, sort by reload number,
1572 so that the results of qsort leave nothing to chance. */
1576 /* The cost of spilling each hard reg. */
1577 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1579 /* When spilling multiple hard registers, we use SPILL_COST for the first
1580 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1581 only the first hard reg for a multi-reg pseudo. */
1582 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1584 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 count_pseudo (int reg
)
1589 int freq
= REG_FREQ (reg
);
1590 int r
= reg_renumber
[reg
];
1593 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1594 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1597 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1599 gcc_assert (r
>= 0);
1601 spill_add_cost
[r
] += freq
;
1603 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1605 spill_cost
[r
+ nregs
] += freq
;
1608 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1609 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1612 order_regs_for_reload (struct insn_chain
*chain
)
1615 HARD_REG_SET used_by_pseudos
;
1616 HARD_REG_SET used_by_pseudos2
;
1617 reg_set_iterator rsi
;
1619 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1621 memset (spill_cost
, 0, sizeof spill_cost
);
1622 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1624 /* Count number of uses of each hard reg by pseudo regs allocated to it
1625 and then order them by decreasing use. First exclude hard registers
1626 that are live in or across this insn. */
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1630 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1631 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1633 /* Now find out which pseudos are allocated to it, and update
1635 CLEAR_REG_SET (&pseudos_counted
);
1637 EXECUTE_IF_SET_IN_REG_SET
1638 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1642 EXECUTE_IF_SET_IN_REG_SET
1643 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1647 CLEAR_REG_SET (&pseudos_counted
);
1650 /* Vector of reload-numbers showing the order in which the reloads should
1652 static short reload_order
[MAX_RELOADS
];
1654 /* This is used to keep track of the spill regs used in one insn. */
1655 static HARD_REG_SET used_spill_regs_local
;
1657 /* We decided to spill hard register SPILLED, which has a size of
1658 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1659 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1660 update SPILL_COST/SPILL_ADD_COST. */
1663 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1665 int r
= reg_renumber
[reg
];
1666 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1668 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1669 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1672 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1674 spill_add_cost
[r
] -= REG_FREQ (reg
);
1676 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (struct insn_chain
*chain
, int order
)
1684 int rnum
= reload_order
[order
];
1685 struct reload
*rl
= rld
+ rnum
;
1686 int best_cost
= INT_MAX
;
1690 HARD_REG_SET not_usable
;
1691 HARD_REG_SET used_by_other_reload
;
1692 reg_set_iterator rsi
;
1694 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1695 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1696 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1698 CLEAR_HARD_REG_SET (used_by_other_reload
);
1699 for (k
= 0; k
< order
; k
++)
1701 int other
= reload_order
[k
];
1703 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1704 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1705 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1708 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1710 unsigned int regno
= i
;
1712 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1713 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1714 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1716 int this_cost
= spill_cost
[regno
];
1718 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1720 for (j
= 1; j
< this_nregs
; j
++)
1722 this_cost
+= spill_add_cost
[regno
+ j
];
1723 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1724 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1729 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1731 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1733 if (this_cost
< best_cost
1734 /* Among registers with equal cost, prefer caller-saved ones, or
1735 use REG_ALLOC_ORDER if it is defined. */
1736 || (this_cost
== best_cost
1737 #ifdef REG_ALLOC_ORDER
1738 && (inv_reg_alloc_order
[regno
]
1739 < inv_reg_alloc_order
[best_reg
])
1741 && call_used_regs
[regno
]
1742 && ! call_used_regs
[best_reg
]
1747 best_cost
= this_cost
;
1755 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1757 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1758 rl
->regno
= best_reg
;
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1763 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1766 EXECUTE_IF_SET_IN_REG_SET
1767 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1769 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1772 for (i
= 0; i
< rl
->nregs
; i
++)
1774 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1775 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1776 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1781 /* Find more reload regs to satisfy the remaining need of an insn, which
1783 Do it by ascending class number, since otherwise a reg
1784 might be spilled for a big class and might fail to count
1785 for a smaller class even though it belongs to that class. */
1788 find_reload_regs (struct insn_chain
*chain
)
1792 /* In order to be certain of getting the registers we need,
1793 we must sort the reloads into order of increasing register class.
1794 Then our grabbing of reload registers will parallel the process
1795 that provided the reload registers. */
1796 for (i
= 0; i
< chain
->n_reloads
; i
++)
1798 /* Show whether this reload already has a hard reg. */
1799 if (chain
->rld
[i
].reg_rtx
)
1801 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1802 chain
->rld
[i
].regno
= regno
;
1804 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1807 chain
->rld
[i
].regno
= -1;
1808 reload_order
[i
] = i
;
1811 n_reloads
= chain
->n_reloads
;
1812 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1814 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1817 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1819 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1821 /* Compute the order of preference for hard registers to spill. */
1823 order_regs_for_reload (chain
);
1825 for (i
= 0; i
< n_reloads
; i
++)
1827 int r
= reload_order
[i
];
1829 /* Ignore reloads that got marked inoperative. */
1830 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1831 && ! rld
[r
].optional
1832 && rld
[r
].regno
== -1)
1833 if (! find_reg (chain
, i
))
1835 spill_failure (chain
->insn
, rld
[r
].class);
1841 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1842 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1844 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1848 select_reload_regs (void)
1850 struct insn_chain
*chain
;
1852 /* Try to satisfy the needs for each insn. */
1853 for (chain
= insns_need_reload
; chain
!= 0;
1854 chain
= chain
->next_need_reload
)
1855 find_reload_regs (chain
);
1858 /* Delete all insns that were inserted by emit_caller_save_insns during
1861 delete_caller_save_insns (void)
1863 struct insn_chain
*c
= reload_insn_chain
;
1867 while (c
!= 0 && c
->is_caller_save_insn
)
1869 struct insn_chain
*next
= c
->next
;
1872 if (c
== reload_insn_chain
)
1873 reload_insn_chain
= next
;
1877 next
->prev
= c
->prev
;
1879 c
->prev
->next
= next
;
1880 c
->next
= unused_insn_chains
;
1881 unused_insn_chains
= c
;
1889 /* Handle the failure to find a register to spill.
1890 INSN should be one of the insns which needed this particular spill reg. */
1893 spill_failure (rtx insn
, enum reg_class
class)
1895 if (asm_noperands (PATTERN (insn
)) >= 0)
1896 error_for_asm (insn
, "can't find a register in class %qs while "
1897 "reloading %<asm%>",
1898 reg_class_names
[class]);
1901 error ("unable to find a register to spill in class %qs",
1902 reg_class_names
[class]);
1903 fatal_insn ("this is the insn:", insn
);
1907 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1908 data that is dead in INSN. */
1911 delete_dead_insn (rtx insn
)
1913 rtx prev
= prev_real_insn (insn
);
1916 /* If the previous insn sets a register that dies in our insn, delete it
1918 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1919 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
1920 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1921 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1922 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1923 delete_dead_insn (prev
);
1925 SET_INSN_DELETED (insn
);
1928 /* Modify the home of pseudo-reg I.
1929 The new home is present in reg_renumber[I].
1931 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1932 or it may be -1, meaning there is none or it is not relevant.
1933 This is used so that all pseudos spilled from a given hard reg
1934 can share one stack slot. */
1937 alter_reg (int i
, int from_reg
)
1939 /* When outputting an inline function, this can happen
1940 for a reg that isn't actually used. */
1941 if (regno_reg_rtx
[i
] == 0)
1944 /* If the reg got changed to a MEM at rtl-generation time,
1946 if (!REG_P (regno_reg_rtx
[i
]))
1949 /* Modify the reg-rtx to contain the new hard reg
1950 number or else to contain its pseudo reg number. */
1951 REGNO (regno_reg_rtx
[i
])
1952 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1954 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1955 allocate a stack slot for it. */
1957 if (reg_renumber
[i
] < 0
1958 && REG_N_REFS (i
) > 0
1959 && reg_equiv_constant
[i
] == 0
1960 && reg_equiv_memory_loc
[i
] == 0)
1963 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1964 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1979 inherent_size
== total_size
? 0 : -1);
1980 if (BYTES_BIG_ENDIAN
)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust
= inherent_size
- total_size
;
1987 /* Nothing can alias this slot except this pseudo. */
1988 set_mem_alias_set (x
, new_alias_set ());
1991 /* Reuse a stack slot if possible. */
1992 else if (spill_stack_slot
[from_reg
] != 0
1993 && spill_stack_slot_width
[from_reg
] >= total_size
1994 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1996 x
= spill_stack_slot
[from_reg
];
1998 /* Allocate a bigger slot. */
2001 /* Compute maximum size needed, both for inherent size
2002 and for total size. */
2003 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2006 if (spill_stack_slot
[from_reg
])
2008 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2010 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2011 if (spill_stack_slot_width
[from_reg
] > total_size
)
2012 total_size
= spill_stack_slot_width
[from_reg
];
2015 /* Make a slot with that size. */
2016 x
= assign_stack_local (mode
, total_size
,
2017 inherent_size
== total_size
? 0 : -1);
2020 /* All pseudos mapped to this slot can alias each other. */
2021 if (spill_stack_slot
[from_reg
])
2022 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2024 set_mem_alias_set (x
, new_alias_set ());
2026 if (BYTES_BIG_ENDIAN
)
2028 /* Cancel the big-endian correction done in assign_stack_local.
2029 Get the address of the beginning of the slot.
2030 This is so we can do a big-endian correction unconditionally
2032 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2035 = adjust_address_nv (x
, mode_for_size (total_size
2041 spill_stack_slot
[from_reg
] = stack_slot
;
2042 spill_stack_slot_width
[from_reg
] = total_size
;
2045 /* On a big endian machine, the "address" of the slot
2046 is the address of the low part that fits its inherent mode. */
2047 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2048 adjust
+= (total_size
- inherent_size
);
2050 /* If we have any adjustment to make, or if the stack slot is the
2051 wrong mode, make a new stack slot. */
2052 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2054 /* If we have a decl for the original register, set it for the
2055 memory. If this is a shared MEM, make a copy. */
2056 if (REG_EXPR (regno_reg_rtx
[i
])
2057 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2059 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2061 /* We can do this only for the DECLs home pseudo, not for
2062 any copies of it, since otherwise when the stack slot
2063 is reused, nonoverlapping_memrefs_p might think they
2065 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2067 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2070 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2074 /* Save the stack slot for later. */
2075 reg_equiv_memory_loc
[i
] = x
;
2079 /* Mark the slots in regs_ever_live for the hard regs
2080 used by pseudo-reg number REGNO. */
2083 mark_home_live (int regno
)
2087 i
= reg_renumber
[regno
];
2090 lim
= i
+ hard_regno_nregs
[i
][PSEUDO_REGNO_MODE (regno
)];
2092 regs_ever_live
[i
++] = 1;
2095 /* This function handles the tracking of elimination offsets around branches.
2097 X is a piece of RTL being scanned.
2099 INSN is the insn that it came from, if any.
2101 INITIAL_P is nonzero if we are to set the offset to be the initial
2102 offset and zero if we are setting the offset of the label to be the
2106 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2108 enum rtx_code code
= GET_CODE (x
);
2111 struct elim_table
*p
;
2116 if (LABEL_REF_NONLOCAL_P (x
))
2121 /* ... fall through ... */
2124 /* If we know nothing about this label, set the desired offsets. Note
2125 that this sets the offset at a label to be the offset before a label
2126 if we don't know anything about the label. This is not correct for
2127 the label after a BARRIER, but is the best guess we can make. If
2128 we guessed wrong, we will suppress an elimination that might have
2129 been possible had we been able to guess correctly. */
2131 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2133 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2134 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2135 = (initial_p
? reg_eliminate
[i
].initial_offset
2136 : reg_eliminate
[i
].offset
);
2137 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2140 /* Otherwise, if this is the definition of a label and it is
2141 preceded by a BARRIER, set our offsets to the known offset of
2145 && (tem
= prev_nonnote_insn (insn
)) != 0
2147 set_offsets_for_label (insn
);
2149 /* If neither of the above cases is true, compare each offset
2150 with those previously recorded and suppress any eliminations
2151 where the offsets disagree. */
2153 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2154 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2155 != (initial_p
? reg_eliminate
[i
].initial_offset
2156 : reg_eliminate
[i
].offset
))
2157 reg_eliminate
[i
].can_eliminate
= 0;
2162 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2164 /* ... fall through ... */
2168 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2169 and hence must have all eliminations at their initial offsets. */
2170 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2171 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2172 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2178 /* Each of the labels in the parallel or address vector must be
2179 at their initial offsets. We want the first field for PARALLEL
2180 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2182 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2183 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2188 /* We only care about setting PC. If the source is not RETURN,
2189 IF_THEN_ELSE, or a label, disable any eliminations not at
2190 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2191 isn't one of those possibilities. For branches to a label,
2192 call ourselves recursively.
2194 Note that this can disable elimination unnecessarily when we have
2195 a non-local goto since it will look like a non-constant jump to
2196 someplace in the current function. This isn't a significant
2197 problem since such jumps will normally be when all elimination
2198 pairs are back to their initial offsets. */
2200 if (SET_DEST (x
) != pc_rtx
)
2203 switch (GET_CODE (SET_SRC (x
)))
2210 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2214 tem
= XEXP (SET_SRC (x
), 1);
2215 if (GET_CODE (tem
) == LABEL_REF
)
2216 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2217 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2220 tem
= XEXP (SET_SRC (x
), 2);
2221 if (GET_CODE (tem
) == LABEL_REF
)
2222 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2223 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2231 /* If we reach here, all eliminations must be at their initial
2232 offset because we are doing a jump to a variable address. */
2233 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2234 if (p
->offset
!= p
->initial_offset
)
2235 p
->can_eliminate
= 0;
2243 /* Scan X and replace any eliminable registers (such as fp) with a
2244 replacement (such as sp), plus an offset.
2246 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2247 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2248 MEM, we are allowed to replace a sum of a register and the constant zero
2249 with the register, which we cannot do outside a MEM. In addition, we need
2250 to record the fact that a register is referenced outside a MEM.
2252 If INSN is an insn, it is the insn containing X. If we replace a REG
2253 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2254 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2255 the REG is being modified.
2257 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2258 That's used when we eliminate in expressions stored in notes.
2259 This means, do not set ref_outside_mem even if the reference
2262 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2263 replacements done assuming all offsets are at their initial values. If
2264 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2265 encounter, return the actual location so that find_reloads will do
2266 the proper thing. */
2269 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2271 enum rtx_code code
= GET_CODE (x
);
2272 struct elim_table
*ep
;
2279 if (! current_function_decl
)
2301 /* First handle the case where we encounter a bare register that
2302 is eliminable. Replace it with a PLUS. */
2303 if (regno
< FIRST_PSEUDO_REGISTER
)
2305 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2307 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2308 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2311 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2312 && reg_equiv_constant
&& reg_equiv_constant
[regno
]
2313 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2314 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2318 /* You might think handling MINUS in a manner similar to PLUS is a
2319 good idea. It is not. It has been tried multiple times and every
2320 time the change has had to have been reverted.
2322 Other parts of reload know a PLUS is special (gen_reload for example)
2323 and require special code to handle code a reloaded PLUS operand.
2325 Also consider backends where the flags register is clobbered by a
2326 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2327 lea instruction comes to mind). If we try to reload a MINUS, we
2328 may kill the flags register that was holding a useful value.
2330 So, please before trying to handle MINUS, consider reload as a
2331 whole instead of this little section as well as the backend issues. */
2333 /* If this is the sum of an eliminable register and a constant, rework
2335 if (REG_P (XEXP (x
, 0))
2336 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2337 && CONSTANT_P (XEXP (x
, 1)))
2339 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2341 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2343 /* The only time we want to replace a PLUS with a REG (this
2344 occurs when the constant operand of the PLUS is the negative
2345 of the offset) is when we are inside a MEM. We won't want
2346 to do so at other times because that would change the
2347 structure of the insn in a way that reload can't handle.
2348 We special-case the commonest situation in
2349 eliminate_regs_in_insn, so just replace a PLUS with a
2350 PLUS here, unless inside a MEM. */
2351 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2352 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2355 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2356 plus_constant (XEXP (x
, 1),
2357 ep
->previous_offset
));
2360 /* If the register is not eliminable, we are done since the other
2361 operand is a constant. */
2365 /* If this is part of an address, we want to bring any constant to the
2366 outermost PLUS. We will do this by doing register replacement in
2367 our operands and seeing if a constant shows up in one of them.
2369 Note that there is no risk of modifying the structure of the insn,
2370 since we only get called for its operands, thus we are either
2371 modifying the address inside a MEM, or something like an address
2372 operand of a load-address insn. */
2375 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2376 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2378 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2380 /* If one side is a PLUS and the other side is a pseudo that
2381 didn't get a hard register but has a reg_equiv_constant,
2382 we must replace the constant here since it may no longer
2383 be in the position of any operand. */
2384 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2385 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2386 && reg_renumber
[REGNO (new1
)] < 0
2387 && reg_equiv_constant
!= 0
2388 && reg_equiv_constant
[REGNO (new1
)] != 0)
2389 new1
= reg_equiv_constant
[REGNO (new1
)];
2390 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2391 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber
[REGNO (new0
)] < 0
2393 && reg_equiv_constant
[REGNO (new0
)] != 0)
2394 new0
= reg_equiv_constant
[REGNO (new0
)];
2396 new = form_sum (new0
, new1
);
2398 /* As above, if we are not inside a MEM we do not want to
2399 turn a PLUS into something else. We might try to do so here
2400 for an addition of 0 if we aren't optimizing. */
2401 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2402 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2410 /* If this is the product of an eliminable register and a
2411 constant, apply the distribute law and move the constant out
2412 so that we have (plus (mult ..) ..). This is needed in order
2413 to keep load-address insns valid. This case is pathological.
2414 We ignore the possibility of overflow here. */
2415 if (REG_P (XEXP (x
, 0))
2416 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2417 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2418 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2420 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2423 /* Refs inside notes don't count for this purpose. */
2424 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2425 || GET_CODE (insn
) == INSN_LIST
)))
2426 ep
->ref_outside_mem
= 1;
2429 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2430 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2433 /* ... fall through ... */
2437 /* See comments before PLUS about handling MINUS. */
2439 case DIV
: case UDIV
:
2440 case MOD
: case UMOD
:
2441 case AND
: case IOR
: case XOR
:
2442 case ROTATERT
: case ROTATE
:
2443 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2445 case GE
: case GT
: case GEU
: case GTU
:
2446 case LE
: case LT
: case LEU
: case LTU
:
2448 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2450 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2452 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2453 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2458 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2461 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2462 if (new != XEXP (x
, 0))
2464 /* If this is a REG_DEAD note, it is not valid anymore.
2465 Using the eliminated version could result in creating a
2466 REG_DEAD note for the stack or frame pointer. */
2467 if (GET_MODE (x
) == REG_DEAD
)
2469 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2472 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2476 /* ... fall through ... */
2479 /* Now do eliminations in the rest of the chain. If this was
2480 an EXPR_LIST, this might result in allocating more memory than is
2481 strictly needed, but it simplifies the code. */
2484 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2485 if (new != XEXP (x
, 1))
2487 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2495 case STRICT_LOW_PART
:
2497 case SIGN_EXTEND
: case ZERO_EXTEND
:
2498 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2499 case FLOAT
: case FIX
:
2500 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2508 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2509 if (new != XEXP (x
, 0))
2510 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2514 /* Similar to above processing, but preserve SUBREG_BYTE.
2515 Convert (subreg (mem)) to (mem) if not paradoxical.
2516 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2517 pseudo didn't get a hard reg, we must replace this with the
2518 eliminated version of the memory location because push_reload
2519 may do the replacement in certain circumstances. */
2520 if (REG_P (SUBREG_REG (x
))
2521 && (GET_MODE_SIZE (GET_MODE (x
))
2522 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2523 && reg_equiv_memory_loc
!= 0
2524 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2526 new = SUBREG_REG (x
);
2529 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2531 if (new != SUBREG_REG (x
))
2533 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2534 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2537 && ((x_size
< new_size
2538 #ifdef WORD_REGISTER_OPERATIONS
2539 /* On these machines, combine can create rtl of the form
2540 (set (subreg:m1 (reg:m2 R) 0) ...)
2541 where m1 < m2, and expects something interesting to
2542 happen to the entire word. Moreover, it will use the
2543 (reg:m2 R) later, expecting all bits to be preserved.
2544 So if the number of words is the same, preserve the
2545 subreg so that push_reload can see it. */
2546 && ! ((x_size
- 1) / UNITS_PER_WORD
2547 == (new_size
-1 ) / UNITS_PER_WORD
)
2550 || x_size
== new_size
)
2552 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2554 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2560 /* Our only special processing is to pass the mode of the MEM to our
2561 recursive call and copy the flags. While we are here, handle this
2562 case more efficiently. */
2564 replace_equiv_address_nv (x
,
2565 eliminate_regs (XEXP (x
, 0),
2566 GET_MODE (x
), insn
));
2569 /* Handle insn_list USE that a call to a pure function may generate. */
2570 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2571 if (new != XEXP (x
, 0))
2572 return gen_rtx_USE (GET_MODE (x
), new);
2584 /* Process each of our operands recursively. If any have changed, make a
2586 fmt
= GET_RTX_FORMAT (code
);
2587 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2591 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2592 if (new != XEXP (x
, i
) && ! copied
)
2594 rtx new_x
= rtx_alloc (code
);
2595 memcpy (new_x
, x
, RTX_SIZE (code
));
2601 else if (*fmt
== 'E')
2604 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2606 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2607 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2609 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2613 rtx new_x
= rtx_alloc (code
);
2614 memcpy (new_x
, x
, RTX_SIZE (code
));
2618 XVEC (x
, i
) = new_v
;
2621 XVECEXP (x
, i
, j
) = new;
2629 /* Scan rtx X for modifications of elimination target registers. Update
2630 the table of eliminables to reflect the changed state. MEM_MODE is
2631 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2634 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2636 enum rtx_code code
= GET_CODE (x
);
2637 struct elim_table
*ep
;
2661 /* First handle the case where we encounter a bare register that
2662 is eliminable. Replace it with a PLUS. */
2663 if (regno
< FIRST_PSEUDO_REGISTER
)
2665 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2667 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2670 ep
->ref_outside_mem
= 1;
2675 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2676 && reg_equiv_constant
[regno
]
2677 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2678 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2687 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2688 if (ep
->to_rtx
== XEXP (x
, 0))
2690 int size
= GET_MODE_SIZE (mem_mode
);
2692 /* If more bytes than MEM_MODE are pushed, account for them. */
2693 #ifdef PUSH_ROUNDING
2694 if (ep
->to_rtx
== stack_pointer_rtx
)
2695 size
= PUSH_ROUNDING (size
);
2697 if (code
== PRE_DEC
|| code
== POST_DEC
)
2699 else if (code
== PRE_INC
|| code
== POST_INC
)
2701 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2702 && GET_CODE (XEXP (x
, 1)) == PLUS
2703 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2704 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2705 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2708 /* These two aren't unary operators. */
2709 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2712 /* Fall through to generic unary operation case. */
2713 case STRICT_LOW_PART
:
2715 case SIGN_EXTEND
: case ZERO_EXTEND
:
2716 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2717 case FLOAT
: case FIX
:
2718 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2726 elimination_effects (XEXP (x
, 0), mem_mode
);
2730 if (REG_P (SUBREG_REG (x
))
2731 && (GET_MODE_SIZE (GET_MODE (x
))
2732 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2733 && reg_equiv_memory_loc
!= 0
2734 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2737 elimination_effects (SUBREG_REG (x
), mem_mode
);
2741 /* If using a register that is the source of an eliminate we still
2742 think can be performed, note it cannot be performed since we don't
2743 know how this register is used. */
2744 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2745 if (ep
->from_rtx
== XEXP (x
, 0))
2746 ep
->can_eliminate
= 0;
2748 elimination_effects (XEXP (x
, 0), mem_mode
);
2752 /* If clobbering a register that is the replacement register for an
2753 elimination we still think can be performed, note that it cannot
2754 be performed. Otherwise, we need not be concerned about it. */
2755 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2756 if (ep
->to_rtx
== XEXP (x
, 0))
2757 ep
->can_eliminate
= 0;
2759 elimination_effects (XEXP (x
, 0), mem_mode
);
2763 /* Check for setting a register that we know about. */
2764 if (REG_P (SET_DEST (x
)))
2766 /* See if this is setting the replacement register for an
2769 If DEST is the hard frame pointer, we do nothing because we
2770 assume that all assignments to the frame pointer are for
2771 non-local gotos and are being done at a time when they are valid
2772 and do not disturb anything else. Some machines want to
2773 eliminate a fake argument pointer (or even a fake frame pointer)
2774 with either the real frame or the stack pointer. Assignments to
2775 the hard frame pointer must not prevent this elimination. */
2777 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2779 if (ep
->to_rtx
== SET_DEST (x
)
2780 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2782 /* If it is being incremented, adjust the offset. Otherwise,
2783 this elimination can't be done. */
2784 rtx src
= SET_SRC (x
);
2786 if (GET_CODE (src
) == PLUS
2787 && XEXP (src
, 0) == SET_DEST (x
)
2788 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2789 ep
->offset
-= INTVAL (XEXP (src
, 1));
2791 ep
->can_eliminate
= 0;
2795 elimination_effects (SET_DEST (x
), 0);
2796 elimination_effects (SET_SRC (x
), 0);
2800 /* Our only special processing is to pass the mode of the MEM to our
2802 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2809 fmt
= GET_RTX_FORMAT (code
);
2810 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2813 elimination_effects (XEXP (x
, i
), mem_mode
);
2814 else if (*fmt
== 'E')
2815 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2816 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2820 /* Descend through rtx X and verify that no references to eliminable registers
2821 remain. If any do remain, mark the involved register as not
2825 check_eliminable_occurrences (rtx x
)
2834 code
= GET_CODE (x
);
2836 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2838 struct elim_table
*ep
;
2840 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2841 if (ep
->from_rtx
== x
)
2842 ep
->can_eliminate
= 0;
2846 fmt
= GET_RTX_FORMAT (code
);
2847 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2850 check_eliminable_occurrences (XEXP (x
, i
));
2851 else if (*fmt
== 'E')
2854 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2855 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2860 /* Scan INSN and eliminate all eliminable registers in it.
2862 If REPLACE is nonzero, do the replacement destructively. Also
2863 delete the insn as dead it if it is setting an eliminable register.
2865 If REPLACE is zero, do all our allocations in reload_obstack.
2867 If no eliminations were done and this insn doesn't require any elimination
2868 processing (these are not identical conditions: it might be updating sp,
2869 but not referencing fp; this needs to be seen during reload_as_needed so
2870 that the offset between fp and sp can be taken into consideration), zero
2871 is returned. Otherwise, 1 is returned. */
2874 eliminate_regs_in_insn (rtx insn
, int replace
)
2876 int icode
= recog_memoized (insn
);
2877 rtx old_body
= PATTERN (insn
);
2878 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2879 rtx old_set
= single_set (insn
);
2883 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2884 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2885 struct elim_table
*ep
;
2888 if (! insn_is_asm
&& icode
< 0)
2890 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
2891 || GET_CODE (PATTERN (insn
)) == CLOBBER
2892 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2893 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2894 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
2898 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
2899 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2901 /* Check for setting an eliminable register. */
2902 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2903 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2905 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2906 /* If this is setting the frame pointer register to the
2907 hardware frame pointer register and this is an elimination
2908 that will be done (tested above), this insn is really
2909 adjusting the frame pointer downward to compensate for
2910 the adjustment done before a nonlocal goto. */
2911 if (ep
->from
== FRAME_POINTER_REGNUM
2912 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2914 rtx base
= SET_SRC (old_set
);
2915 rtx base_insn
= insn
;
2916 HOST_WIDE_INT offset
= 0;
2918 while (base
!= ep
->to_rtx
)
2920 rtx prev_insn
, prev_set
;
2922 if (GET_CODE (base
) == PLUS
2923 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
2925 offset
+= INTVAL (XEXP (base
, 1));
2926 base
= XEXP (base
, 0);
2928 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
2929 && (prev_set
= single_set (prev_insn
)) != 0
2930 && rtx_equal_p (SET_DEST (prev_set
), base
))
2932 base
= SET_SRC (prev_set
);
2933 base_insn
= prev_insn
;
2939 if (base
== ep
->to_rtx
)
2942 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2944 new_body
= old_body
;
2947 new_body
= copy_insn (old_body
);
2948 if (REG_NOTES (insn
))
2949 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2951 PATTERN (insn
) = new_body
;
2952 old_set
= single_set (insn
);
2954 /* First see if this insn remains valid when we
2955 make the change. If not, keep the INSN_CODE
2956 the same and let reload fit it up. */
2957 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2958 validate_change (insn
, &SET_DEST (old_set
),
2960 if (! apply_change_group ())
2962 SET_SRC (old_set
) = src
;
2963 SET_DEST (old_set
) = ep
->to_rtx
;
2972 /* In this case this insn isn't serving a useful purpose. We
2973 will delete it in reload_as_needed once we know that this
2974 elimination is, in fact, being done.
2976 If REPLACE isn't set, we can't delete this insn, but needn't
2977 process it since it won't be used unless something changes. */
2980 delete_dead_insn (insn
);
2988 /* We allow one special case which happens to work on all machines we
2989 currently support: a single set with the source or a REG_EQUAL
2990 note being a PLUS of an eliminable register and a constant. */
2992 if (old_set
&& REG_P (SET_DEST (old_set
)))
2994 /* First see if the source is of the form (plus (reg) CST). */
2995 if (GET_CODE (SET_SRC (old_set
)) == PLUS
2996 && REG_P (XEXP (SET_SRC (old_set
), 0))
2997 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
2998 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
2999 plus_src
= SET_SRC (old_set
);
3000 else if (REG_P (SET_SRC (old_set
)))
3002 /* Otherwise, see if we have a REG_EQUAL note of the form
3003 (plus (reg) CST). */
3005 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3007 if (REG_NOTE_KIND (links
) == REG_EQUAL
3008 && GET_CODE (XEXP (links
, 0)) == PLUS
3009 && REG_P (XEXP (XEXP (links
, 0), 0))
3010 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
3011 && REGNO (XEXP (XEXP (links
, 0), 0)) < FIRST_PSEUDO_REGISTER
)
3013 plus_src
= XEXP (links
, 0);
3021 rtx reg
= XEXP (plus_src
, 0);
3022 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_src
, 1));
3024 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3025 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3027 offset
+= ep
->offset
;
3032 /* We assume here that if we need a PARALLEL with
3033 CLOBBERs for this assignment, we can do with the
3034 MATCH_SCRATCHes that add_clobbers allocates.
3035 There's not much we can do if that doesn't work. */
3036 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3040 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3043 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3045 vec
->elem
[0] = PATTERN (insn
);
3046 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3047 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3049 gcc_assert (INSN_CODE (insn
) >= 0);
3051 /* If we have a nonzero offset, and the source is already
3052 a simple REG, the following transformation would
3053 increase the cost of the insn by replacing a simple REG
3054 with (plus (reg sp) CST). So try only when plus_src
3055 comes from old_set proper, not REG_NOTES. */
3056 else if (SET_SRC (old_set
) == plus_src
)
3058 new_body
= old_body
;
3061 new_body
= copy_insn (old_body
);
3062 if (REG_NOTES (insn
))
3063 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3065 PATTERN (insn
) = new_body
;
3066 old_set
= single_set (insn
);
3068 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3069 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3075 /* This can't have an effect on elimination offsets, so skip right
3081 /* Determine the effects of this insn on elimination offsets. */
3082 elimination_effects (old_body
, 0);
3084 /* Eliminate all eliminable registers occurring in operands that
3085 can be handled by reload. */
3086 extract_insn (insn
);
3087 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3089 orig_operand
[i
] = recog_data
.operand
[i
];
3090 substed_operand
[i
] = recog_data
.operand
[i
];
3092 /* For an asm statement, every operand is eliminable. */
3093 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3095 /* Check for setting a register that we know about. */
3096 if (recog_data
.operand_type
[i
] != OP_IN
3097 && REG_P (orig_operand
[i
]))
3099 /* If we are assigning to a register that can be eliminated, it
3100 must be as part of a PARALLEL, since the code above handles
3101 single SETs. We must indicate that we can no longer
3102 eliminate this reg. */
3103 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3105 if (ep
->from_rtx
== orig_operand
[i
])
3106 ep
->can_eliminate
= 0;
3109 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3110 replace
? insn
: NULL_RTX
);
3111 if (substed_operand
[i
] != orig_operand
[i
])
3113 /* Terminate the search in check_eliminable_occurrences at
3115 *recog_data
.operand_loc
[i
] = 0;
3117 /* If an output operand changed from a REG to a MEM and INSN is an
3118 insn, write a CLOBBER insn. */
3119 if (recog_data
.operand_type
[i
] != OP_IN
3120 && REG_P (orig_operand
[i
])
3121 && MEM_P (substed_operand
[i
])
3123 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3128 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3129 *recog_data
.dup_loc
[i
]
3130 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3132 /* If any eliminable remain, they aren't eliminable anymore. */
3133 check_eliminable_occurrences (old_body
);
3135 /* Substitute the operands; the new values are in the substed_operand
3137 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3138 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3139 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3140 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3142 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3143 re-recognize the insn. We do this in case we had a simple addition
3144 but now can do this as a load-address. This saves an insn in this
3146 If re-recognition fails, the old insn code number will still be used,
3147 and some register operands may have changed into PLUS expressions.
3148 These will be handled by find_reloads by loading them into a register
3153 /* If we aren't replacing things permanently and we changed something,
3154 make another copy to ensure that all the RTL is new. Otherwise
3155 things can go wrong if find_reload swaps commutative operands
3156 and one is inside RTL that has been copied while the other is not. */
3157 new_body
= old_body
;
3160 new_body
= copy_insn (old_body
);
3161 if (REG_NOTES (insn
))
3162 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3164 PATTERN (insn
) = new_body
;
3166 /* If we had a move insn but now we don't, rerecognize it. This will
3167 cause spurious re-recognition if the old move had a PARALLEL since
3168 the new one still will, but we can't call single_set without
3169 having put NEW_BODY into the insn and the re-recognition won't
3170 hurt in this rare case. */
3171 /* ??? Why this huge if statement - why don't we just rerecognize the
3175 && ((REG_P (SET_SRC (old_set
))
3176 && (GET_CODE (new_body
) != SET
3177 || !REG_P (SET_SRC (new_body
))))
3178 /* If this was a load from or store to memory, compare
3179 the MEM in recog_data.operand to the one in the insn.
3180 If they are not equal, then rerecognize the insn. */
3182 && ((MEM_P (SET_SRC (old_set
))
3183 && SET_SRC (old_set
) != recog_data
.operand
[1])
3184 || (MEM_P (SET_DEST (old_set
))
3185 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3186 /* If this was an add insn before, rerecognize. */
3187 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3189 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3191 INSN_CODE (insn
) = icode
;
3195 /* Restore the old body. If there were any changes to it, we made a copy
3196 of it while the changes were still in place, so we'll correctly return
3197 a modified insn below. */
3200 /* Restore the old body. */
3201 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3202 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3203 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3204 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3207 /* Update all elimination pairs to reflect the status after the current
3208 insn. The changes we make were determined by the earlier call to
3209 elimination_effects.
3211 We also detect cases where register elimination cannot be done,
3212 namely, if a register would be both changed and referenced outside a MEM
3213 in the resulting insn since such an insn is often undefined and, even if
3214 not, we cannot know what meaning will be given to it. Note that it is
3215 valid to have a register used in an address in an insn that changes it
3216 (presumably with a pre- or post-increment or decrement).
3218 If anything changes, return nonzero. */
3220 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3222 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3223 ep
->can_eliminate
= 0;
3225 ep
->ref_outside_mem
= 0;
3227 if (ep
->previous_offset
!= ep
->offset
)
3232 /* If we changed something, perform elimination in REG_NOTES. This is
3233 needed even when REPLACE is zero because a REG_DEAD note might refer
3234 to a register that we eliminate and could cause a different number
3235 of spill registers to be needed in the final reload pass than in
3237 if (val
&& REG_NOTES (insn
) != 0)
3238 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3243 /* Loop through all elimination pairs.
3244 Recalculate the number not at initial offset.
3246 Compute the maximum offset (minimum offset if the stack does not
3247 grow downward) for each elimination pair. */
3250 update_eliminable_offsets (void)
3252 struct elim_table
*ep
;
3254 num_not_at_initial_offset
= 0;
3255 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3257 ep
->previous_offset
= ep
->offset
;
3258 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3259 num_not_at_initial_offset
++;
3263 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3264 replacement we currently believe is valid, mark it as not eliminable if X
3265 modifies DEST in any way other than by adding a constant integer to it.
3267 If DEST is the frame pointer, we do nothing because we assume that
3268 all assignments to the hard frame pointer are nonlocal gotos and are being
3269 done at a time when they are valid and do not disturb anything else.
3270 Some machines want to eliminate a fake argument pointer with either the
3271 frame or stack pointer. Assignments to the hard frame pointer must not
3272 prevent this elimination.
3274 Called via note_stores from reload before starting its passes to scan
3275 the insns of the function. */
3278 mark_not_eliminable (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
3282 /* A SUBREG of a hard register here is just changing its mode. We should
3283 not see a SUBREG of an eliminable hard register, but check just in
3285 if (GET_CODE (dest
) == SUBREG
)
3286 dest
= SUBREG_REG (dest
);
3288 if (dest
== hard_frame_pointer_rtx
)
3291 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3292 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3293 && (GET_CODE (x
) != SET
3294 || GET_CODE (SET_SRC (x
)) != PLUS
3295 || XEXP (SET_SRC (x
), 0) != dest
3296 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3298 reg_eliminate
[i
].can_eliminate_previous
3299 = reg_eliminate
[i
].can_eliminate
= 0;
3304 /* Verify that the initial elimination offsets did not change since the
3305 last call to set_initial_elim_offsets. This is used to catch cases
3306 where something illegal happened during reload_as_needed that could
3307 cause incorrect code to be generated if we did not check for it. */
3310 verify_initial_elim_offsets (void)
3314 if (!num_eliminable
)
3317 #ifdef ELIMINABLE_REGS
3318 struct elim_table
*ep
;
3320 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3322 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3323 if (t
!= ep
->initial_offset
)
3327 INITIAL_FRAME_POINTER_OFFSET (t
);
3328 if (t
!= reg_eliminate
[0].initial_offset
)
3335 /* Reset all offsets on eliminable registers to their initial values. */
3338 set_initial_elim_offsets (void)
3340 struct elim_table
*ep
= reg_eliminate
;
3342 #ifdef ELIMINABLE_REGS
3343 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3345 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3346 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3349 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3350 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3353 num_not_at_initial_offset
= 0;
3356 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3359 set_initial_eh_label_offset (rtx label
)
3361 set_label_offsets (label
, NULL_RTX
, 1);
3364 /* Initialize the known label offsets.
3365 Set a known offset for each forced label to be at the initial offset
3366 of each elimination. We do this because we assume that all
3367 computed jumps occur from a location where each elimination is
3368 at its initial offset.
3369 For all other labels, show that we don't know the offsets. */
3372 set_initial_label_offsets (void)
3375 memset (offsets_known_at
, 0, num_labels
);
3377 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3379 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3381 for_each_eh_label (set_initial_eh_label_offset
);
3384 /* Set all elimination offsets to the known values for the code label given
3388 set_offsets_for_label (rtx insn
)
3391 int label_nr
= CODE_LABEL_NUMBER (insn
);
3392 struct elim_table
*ep
;
3394 num_not_at_initial_offset
= 0;
3395 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3397 ep
->offset
= ep
->previous_offset
3398 = offsets_at
[label_nr
- first_label_num
][i
];
3399 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3400 num_not_at_initial_offset
++;
3404 /* See if anything that happened changes which eliminations are valid.
3405 For example, on the SPARC, whether or not the frame pointer can
3406 be eliminated can depend on what registers have been used. We need
3407 not check some conditions again (such as flag_omit_frame_pointer)
3408 since they can't have changed. */
3411 update_eliminables (HARD_REG_SET
*pset
)
3413 int previous_frame_pointer_needed
= frame_pointer_needed
;
3414 struct elim_table
*ep
;
3416 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3417 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3418 #ifdef ELIMINABLE_REGS
3419 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3422 ep
->can_eliminate
= 0;
3424 /* Look for the case where we have discovered that we can't replace
3425 register A with register B and that means that we will now be
3426 trying to replace register A with register C. This means we can
3427 no longer replace register C with register B and we need to disable
3428 such an elimination, if it exists. This occurs often with A == ap,
3429 B == sp, and C == fp. */
3431 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3433 struct elim_table
*op
;
3436 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3438 /* Find the current elimination for ep->from, if there is a
3440 for (op
= reg_eliminate
;
3441 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3442 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3448 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3450 for (op
= reg_eliminate
;
3451 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3452 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3453 op
->can_eliminate
= 0;
3457 /* See if any registers that we thought we could eliminate the previous
3458 time are no longer eliminable. If so, something has changed and we
3459 must spill the register. Also, recompute the number of eliminable
3460 registers and see if the frame pointer is needed; it is if there is
3461 no elimination of the frame pointer that we can perform. */
3463 frame_pointer_needed
= 1;
3464 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3466 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3467 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3468 frame_pointer_needed
= 0;
3470 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3472 ep
->can_eliminate_previous
= 0;
3473 SET_HARD_REG_BIT (*pset
, ep
->from
);
3478 /* If we didn't need a frame pointer last time, but we do now, spill
3479 the hard frame pointer. */
3480 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3481 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3484 /* Initialize the table of registers to eliminate. */
3487 init_elim_table (void)
3489 struct elim_table
*ep
;
3490 #ifdef ELIMINABLE_REGS
3491 const struct elim_table_1
*ep1
;
3495 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3497 /* Does this function require a frame pointer? */
3499 frame_pointer_needed
= (! flag_omit_frame_pointer
3500 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3501 and restore sp for alloca. So we can't eliminate
3502 the frame pointer in that case. At some point,
3503 we should improve this by emitting the
3504 sp-adjusting insns for this case. */
3505 || (current_function_calls_alloca
3506 && EXIT_IGNORE_STACK
)
3507 || FRAME_POINTER_REQUIRED
);
3511 #ifdef ELIMINABLE_REGS
3512 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3513 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3515 ep
->from
= ep1
->from
;
3517 ep
->can_eliminate
= ep
->can_eliminate_previous
3518 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3519 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3522 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3523 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3524 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3525 = ! frame_pointer_needed
;
3528 /* Count the number of eliminable registers and build the FROM and TO
3529 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3530 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3531 We depend on this. */
3532 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3534 num_eliminable
+= ep
->can_eliminate
;
3535 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3536 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3540 /* Kick all pseudos out of hard register REGNO.
3542 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3543 because we found we can't eliminate some register. In the case, no pseudos
3544 are allowed to be in the register, even if they are only in a block that
3545 doesn't require spill registers, unlike the case when we are spilling this
3546 hard reg to produce another spill register.
3548 Return nonzero if any pseudos needed to be kicked out. */
3551 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3557 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3558 regs_ever_live
[regno
] = 1;
3561 /* Spill every pseudo reg that was allocated to this reg
3562 or to something that overlaps this reg. */
3564 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3565 if (reg_renumber
[i
] >= 0
3566 && (unsigned int) reg_renumber
[i
] <= regno
3567 && ((unsigned int) reg_renumber
[i
]
3568 + hard_regno_nregs
[(unsigned int) reg_renumber
[i
]]
3569 [PSEUDO_REGNO_MODE (i
)]
3571 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3574 /* After find_reload_regs has been run for all insn that need reloads,
3575 and/or spill_hard_regs was called, this function is used to actually
3576 spill pseudo registers and try to reallocate them. It also sets up the
3577 spill_regs array for use by choose_reload_regs. */
3580 finish_spills (int global
)
3582 struct insn_chain
*chain
;
3583 int something_changed
= 0;
3585 reg_set_iterator rsi
;
3587 /* Build the spill_regs array for the function. */
3588 /* If there are some registers still to eliminate and one of the spill regs
3589 wasn't ever used before, additional stack space may have to be
3590 allocated to store this register. Thus, we may have changed the offset
3591 between the stack and frame pointers, so mark that something has changed.
3593 One might think that we need only set VAL to 1 if this is a call-used
3594 register. However, the set of registers that must be saved by the
3595 prologue is not identical to the call-used set. For example, the
3596 register used by the call insn for the return PC is a call-used register,
3597 but must be saved by the prologue. */
3600 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3601 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3603 spill_reg_order
[i
] = n_spills
;
3604 spill_regs
[n_spills
++] = i
;
3605 if (num_eliminable
&& ! regs_ever_live
[i
])
3606 something_changed
= 1;
3607 regs_ever_live
[i
] = 1;
3610 spill_reg_order
[i
] = -1;
3612 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3614 /* Record the current hard register the pseudo is allocated to in
3615 pseudo_previous_regs so we avoid reallocating it to the same
3616 hard reg in a later pass. */
3617 gcc_assert (reg_renumber
[i
] >= 0);
3619 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3620 /* Mark it as no longer having a hard register home. */
3621 reg_renumber
[i
] = -1;
3622 /* We will need to scan everything again. */
3623 something_changed
= 1;
3626 /* Retry global register allocation if possible. */
3629 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3630 /* For every insn that needs reloads, set the registers used as spill
3631 regs in pseudo_forbidden_regs for every pseudo live across the
3633 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3635 EXECUTE_IF_SET_IN_REG_SET
3636 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3638 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3639 chain
->used_spill_regs
);
3641 EXECUTE_IF_SET_IN_REG_SET
3642 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3644 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3645 chain
->used_spill_regs
);
3649 /* Retry allocating the spilled pseudos. For each reg, merge the
3650 various reg sets that indicate which hard regs can't be used,
3651 and call retry_global_alloc.
3652 We change spill_pseudos here to only contain pseudos that did not
3653 get a new hard register. */
3654 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3655 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3657 HARD_REG_SET forbidden
;
3658 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3659 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3660 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3661 retry_global_alloc (i
, forbidden
);
3662 if (reg_renumber
[i
] >= 0)
3663 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3667 /* Fix up the register information in the insn chain.
3668 This involves deleting those of the spilled pseudos which did not get
3669 a new hard register home from the live_{before,after} sets. */
3670 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3672 HARD_REG_SET used_by_pseudos
;
3673 HARD_REG_SET used_by_pseudos2
;
3675 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3676 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3678 /* Mark any unallocated hard regs as available for spills. That
3679 makes inheritance work somewhat better. */
3680 if (chain
->need_reload
)
3682 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3683 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3684 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3686 /* Save the old value for the sanity test below. */
3687 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3689 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3690 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3691 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3692 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3694 /* Make sure we only enlarge the set. */
3695 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3701 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3702 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3704 int regno
= reg_renumber
[i
];
3705 if (reg_old_renumber
[i
] == regno
)
3708 alter_reg (i
, reg_old_renumber
[i
]);
3709 reg_old_renumber
[i
] = regno
;
3713 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
3715 fprintf (dump_file
, " Register %d now in %d.\n\n",
3716 i
, reg_renumber
[i
]);
3720 return something_changed
;
3723 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3726 scan_paradoxical_subregs (rtx x
)
3730 enum rtx_code code
= GET_CODE (x
);
3740 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3748 if (REG_P (SUBREG_REG (x
))
3749 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3750 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3751 = GET_MODE_SIZE (GET_MODE (x
));
3758 fmt
= GET_RTX_FORMAT (code
);
3759 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3762 scan_paradoxical_subregs (XEXP (x
, i
));
3763 else if (fmt
[i
] == 'E')
3766 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3767 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3772 /* Reload pseudo-registers into hard regs around each insn as needed.
3773 Additional register load insns are output before the insn that needs it
3774 and perhaps store insns after insns that modify the reloaded pseudo reg.
3776 reg_last_reload_reg and reg_reloaded_contents keep track of
3777 which registers are already available in reload registers.
3778 We update these for the reloads that we perform,
3779 as the insns are scanned. */
3782 reload_as_needed (int live_known
)
3784 struct insn_chain
*chain
;
3785 #if defined (AUTO_INC_DEC)
3790 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3791 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
3792 reg_last_reload_reg
= xcalloc (max_regno
, sizeof (rtx
));
3793 reg_has_output_reload
= xmalloc (max_regno
);
3794 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3795 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
3797 set_initial_elim_offsets ();
3799 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3802 rtx insn
= chain
->insn
;
3803 rtx old_next
= NEXT_INSN (insn
);
3805 /* If we pass a label, copy the offsets from the label information
3806 into the current offsets of each elimination. */
3808 set_offsets_for_label (insn
);
3810 else if (INSN_P (insn
))
3812 rtx oldpat
= copy_rtx (PATTERN (insn
));
3814 /* If this is a USE and CLOBBER of a MEM, ensure that any
3815 references to eliminable registers have been removed. */
3817 if ((GET_CODE (PATTERN (insn
)) == USE
3818 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3819 && MEM_P (XEXP (PATTERN (insn
), 0)))
3820 XEXP (XEXP (PATTERN (insn
), 0), 0)
3821 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3822 GET_MODE (XEXP (PATTERN (insn
), 0)),
3825 /* If we need to do register elimination processing, do so.
3826 This might delete the insn, in which case we are done. */
3827 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3829 eliminate_regs_in_insn (insn
, 1);
3832 update_eliminable_offsets ();
3837 /* If need_elim is nonzero but need_reload is zero, one might think
3838 that we could simply set n_reloads to 0. However, find_reloads
3839 could have done some manipulation of the insn (such as swapping
3840 commutative operands), and these manipulations are lost during
3841 the first pass for every insn that needs register elimination.
3842 So the actions of find_reloads must be redone here. */
3844 if (! chain
->need_elim
&& ! chain
->need_reload
3845 && ! chain
->need_operand_change
)
3847 /* First find the pseudo regs that must be reloaded for this insn.
3848 This info is returned in the tables reload_... (see reload.h).
3849 Also modify the body of INSN by substituting RELOAD
3850 rtx's for those pseudo regs. */
3853 memset (reg_has_output_reload
, 0, max_regno
);
3854 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3856 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3862 rtx next
= NEXT_INSN (insn
);
3865 prev
= PREV_INSN (insn
);
3867 /* Now compute which reload regs to reload them into. Perhaps
3868 reusing reload regs from previous insns, or else output
3869 load insns to reload them. Maybe output store insns too.
3870 Record the choices of reload reg in reload_reg_rtx. */
3871 choose_reload_regs (chain
);
3873 /* Merge any reloads that we didn't combine for fear of
3874 increasing the number of spill registers needed but now
3875 discover can be safely merged. */
3876 if (SMALL_REGISTER_CLASSES
)
3877 merge_assigned_reloads (insn
);
3879 /* Generate the insns to reload operands into or out of
3880 their reload regs. */
3881 emit_reload_insns (chain
);
3883 /* Substitute the chosen reload regs from reload_reg_rtx
3884 into the insn's body (or perhaps into the bodies of other
3885 load and store insn that we just made for reloading
3886 and that we moved the structure into). */
3887 subst_reloads (insn
);
3889 /* If this was an ASM, make sure that all the reload insns
3890 we have generated are valid. If not, give an error
3893 if (asm_noperands (PATTERN (insn
)) >= 0)
3894 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3895 if (p
!= insn
&& INSN_P (p
)
3896 && GET_CODE (PATTERN (p
)) != USE
3897 && (recog_memoized (p
) < 0
3898 || (extract_insn (p
), ! constrain_operands (1))))
3900 error_for_asm (insn
,
3901 "%<asm%> operand requires "
3902 "impossible reload");
3907 if (num_eliminable
&& chain
->need_elim
)
3908 update_eliminable_offsets ();
3910 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3911 is no longer validly lying around to save a future reload.
3912 Note that this does not detect pseudos that were reloaded
3913 for this insn in order to be stored in
3914 (obeying register constraints). That is correct; such reload
3915 registers ARE still valid. */
3916 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3918 /* There may have been CLOBBER insns placed after INSN. So scan
3919 between INSN and NEXT and use them to forget old reloads. */
3920 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3921 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
3922 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3925 /* Likewise for regs altered by auto-increment in this insn.
3926 REG_INC notes have been changed by reloading:
3927 find_reloads_address_1 records substitutions for them,
3928 which have been performed by subst_reloads above. */
3929 for (i
= n_reloads
- 1; i
>= 0; i
--)
3931 rtx in_reg
= rld
[i
].in_reg
;
3934 enum rtx_code code
= GET_CODE (in_reg
);
3935 /* PRE_INC / PRE_DEC will have the reload register ending up
3936 with the same value as the stack slot, but that doesn't
3937 hold true for POST_INC / POST_DEC. Either we have to
3938 convert the memory access to a true POST_INC / POST_DEC,
3939 or we can't use the reload register for inheritance. */
3940 if ((code
== POST_INC
|| code
== POST_DEC
)
3941 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3942 REGNO (rld
[i
].reg_rtx
))
3943 /* Make sure it is the inc/dec pseudo, and not
3944 some other (e.g. output operand) pseudo. */
3945 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3946 == REGNO (XEXP (in_reg
, 0))))
3949 rtx reload_reg
= rld
[i
].reg_rtx
;
3950 enum machine_mode mode
= GET_MODE (reload_reg
);
3954 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3956 /* We really want to ignore REG_INC notes here, so
3957 use PATTERN (p) as argument to reg_set_p . */
3958 if (reg_set_p (reload_reg
, PATTERN (p
)))
3960 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
3965 n
= validate_replace_rtx (reload_reg
,
3966 gen_rtx_fmt_e (code
,
3971 /* We must also verify that the constraints
3972 are met after the replacement. */
3975 n
= constrain_operands (1);
3979 /* If the constraints were not met, then
3980 undo the replacement. */
3983 validate_replace_rtx (gen_rtx_fmt_e (code
,
3996 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
3998 /* Mark this as having an output reload so that the
3999 REG_INC processing code below won't invalidate
4000 the reload for inheritance. */
4001 SET_HARD_REG_BIT (reg_is_output_reload
,
4002 REGNO (reload_reg
));
4003 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4006 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4009 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4010 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4011 REGNO (rld
[i
].reg_rtx
))
4012 /* Make sure it is the inc/dec pseudo, and not
4013 some other (e.g. output operand) pseudo. */
4014 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4015 == REGNO (XEXP (in_reg
, 0))))
4017 SET_HARD_REG_BIT (reg_is_output_reload
,
4018 REGNO (rld
[i
].reg_rtx
));
4019 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4023 /* If a pseudo that got a hard register is auto-incremented,
4024 we must purge records of copying it into pseudos without
4026 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4027 if (REG_NOTE_KIND (x
) == REG_INC
)
4029 /* See if this pseudo reg was reloaded in this insn.
4030 If so, its last-reload info is still valid
4031 because it is based on this insn's reload. */
4032 for (i
= 0; i
< n_reloads
; i
++)
4033 if (rld
[i
].out
== XEXP (x
, 0))
4037 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4041 /* A reload reg's contents are unknown after a label. */
4043 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4045 /* Don't assume a reload reg is still good after a call insn
4046 if it is a call-used reg, or if it contains a value that will
4047 be partially clobbered by the call. */
4048 else if (CALL_P (insn
))
4050 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4051 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4056 free (reg_last_reload_reg
);
4057 free (reg_has_output_reload
);
4060 /* Discard all record of any value reloaded from X,
4061 or reloaded in X from someplace else;
4062 unless X is an output reload reg of the current insn.
4064 X may be a hard reg (the reload reg)
4065 or it may be a pseudo reg that was reloaded from. */
4068 forget_old_reloads_1 (rtx x
, rtx ignored ATTRIBUTE_UNUSED
,
4069 void *data ATTRIBUTE_UNUSED
)
4074 /* note_stores does give us subregs of hard regs,
4075 subreg_regno_offset requires a hard reg. */
4076 while (GET_CODE (x
) == SUBREG
)
4078 /* We ignore the subreg offset when calculating the regno,
4079 because we are using the entire underlying hard register
4089 if (regno
>= FIRST_PSEUDO_REGISTER
)
4095 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4096 /* Storing into a spilled-reg invalidates its contents.
4097 This can happen if a block-local pseudo is allocated to that reg
4098 and it wasn't spilled because this block's total need is 0.
4099 Then some insn might have an optional reload and use this reg. */
4100 for (i
= 0; i
< nr
; i
++)
4101 /* But don't do this if the reg actually serves as an output
4102 reload reg in the current instruction. */
4104 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4106 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4107 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, regno
+ i
);
4108 spill_reg_store
[regno
+ i
] = 0;
4112 /* Since value of X has changed,
4113 forget any value previously copied from it. */
4116 /* But don't forget a copy if this is the output reload
4117 that establishes the copy's validity. */
4118 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4119 reg_last_reload_reg
[regno
+ nr
] = 0;
4122 /* The following HARD_REG_SETs indicate when each hard register is
4123 used for a reload of various parts of the current insn. */
4125 /* If reg is unavailable for all reloads. */
4126 static HARD_REG_SET reload_reg_unavailable
;
4127 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4128 static HARD_REG_SET reload_reg_used
;
4129 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4130 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4131 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4132 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4133 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4135 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4137 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4139 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4141 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4142 static HARD_REG_SET reload_reg_used_in_op_addr
;
4143 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4144 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4145 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4146 static HARD_REG_SET reload_reg_used_in_insn
;
4147 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4148 static HARD_REG_SET reload_reg_used_in_other_addr
;
4150 /* If reg is in use as a reload reg for any sort of reload. */
4151 static HARD_REG_SET reload_reg_used_at_all
;
4153 /* If reg is use as an inherited reload. We just mark the first register
4155 static HARD_REG_SET reload_reg_used_for_inherit
;
4157 /* Records which hard regs are used in any way, either as explicit use or
4158 by being allocated to a pseudo during any point of the current insn. */
4159 static HARD_REG_SET reg_used_in_insn
;
4161 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4162 TYPE. MODE is used to indicate how many consecutive regs are
4166 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4167 enum machine_mode mode
)
4169 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4172 for (i
= regno
; i
< nregs
+ regno
; i
++)
4177 SET_HARD_REG_BIT (reload_reg_used
, i
);
4180 case RELOAD_FOR_INPUT_ADDRESS
:
4181 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4184 case RELOAD_FOR_INPADDR_ADDRESS
:
4185 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4188 case RELOAD_FOR_OUTPUT_ADDRESS
:
4189 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4192 case RELOAD_FOR_OUTADDR_ADDRESS
:
4193 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4196 case RELOAD_FOR_OPERAND_ADDRESS
:
4197 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4200 case RELOAD_FOR_OPADDR_ADDR
:
4201 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4204 case RELOAD_FOR_OTHER_ADDRESS
:
4205 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4208 case RELOAD_FOR_INPUT
:
4209 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4212 case RELOAD_FOR_OUTPUT
:
4213 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4216 case RELOAD_FOR_INSN
:
4217 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4221 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4225 /* Similarly, but show REGNO is no longer in use for a reload. */
4228 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4229 enum reload_type type
, enum machine_mode mode
)
4231 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4232 unsigned int start_regno
, end_regno
, r
;
4234 /* A complication is that for some reload types, inheritance might
4235 allow multiple reloads of the same types to share a reload register.
4236 We set check_opnum if we have to check only reloads with the same
4237 operand number, and check_any if we have to check all reloads. */
4238 int check_opnum
= 0;
4240 HARD_REG_SET
*used_in_set
;
4245 used_in_set
= &reload_reg_used
;
4248 case RELOAD_FOR_INPUT_ADDRESS
:
4249 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4252 case RELOAD_FOR_INPADDR_ADDRESS
:
4254 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4257 case RELOAD_FOR_OUTPUT_ADDRESS
:
4258 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4261 case RELOAD_FOR_OUTADDR_ADDRESS
:
4263 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4266 case RELOAD_FOR_OPERAND_ADDRESS
:
4267 used_in_set
= &reload_reg_used_in_op_addr
;
4270 case RELOAD_FOR_OPADDR_ADDR
:
4272 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4275 case RELOAD_FOR_OTHER_ADDRESS
:
4276 used_in_set
= &reload_reg_used_in_other_addr
;
4280 case RELOAD_FOR_INPUT
:
4281 used_in_set
= &reload_reg_used_in_input
[opnum
];
4284 case RELOAD_FOR_OUTPUT
:
4285 used_in_set
= &reload_reg_used_in_output
[opnum
];
4288 case RELOAD_FOR_INSN
:
4289 used_in_set
= &reload_reg_used_in_insn
;
4294 /* We resolve conflicts with remaining reloads of the same type by
4295 excluding the intervals of reload registers by them from the
4296 interval of freed reload registers. Since we only keep track of
4297 one set of interval bounds, we might have to exclude somewhat
4298 more than what would be necessary if we used a HARD_REG_SET here.
4299 But this should only happen very infrequently, so there should
4300 be no reason to worry about it. */
4302 start_regno
= regno
;
4303 end_regno
= regno
+ nregs
;
4304 if (check_opnum
|| check_any
)
4306 for (i
= n_reloads
- 1; i
>= 0; i
--)
4308 if (rld
[i
].when_needed
== type
4309 && (check_any
|| rld
[i
].opnum
== opnum
)
4312 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4313 unsigned int conflict_end
4315 + hard_regno_nregs
[conflict_start
][rld
[i
].mode
]);
4317 /* If there is an overlap with the first to-be-freed register,
4318 adjust the interval start. */
4319 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4320 start_regno
= conflict_end
;
4321 /* Otherwise, if there is a conflict with one of the other
4322 to-be-freed registers, adjust the interval end. */
4323 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4324 end_regno
= conflict_start
;
4329 for (r
= start_regno
; r
< end_regno
; r
++)
4330 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4333 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4334 specified by OPNUM and TYPE. */
4337 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4341 /* In use for a RELOAD_OTHER means it's not available for anything. */
4342 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4343 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4349 /* In use for anything means we can't use it for RELOAD_OTHER. */
4350 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4351 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4352 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4356 for (i
= 0; i
< reload_n_operands
; i
++)
4357 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4358 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4359 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4367 case RELOAD_FOR_INPUT
:
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4375 /* If it is used for some other input, can't use it. */
4376 for (i
= 0; i
< reload_n_operands
; i
++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4380 /* If it is used in a later operand's address, can't use it. */
4381 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4388 case RELOAD_FOR_INPUT_ADDRESS
:
4389 /* Can't use a register if it is used for an input address for this
4390 operand or used as an input in an earlier one. */
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4392 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4395 for (i
= 0; i
< opnum
; i
++)
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4401 case RELOAD_FOR_INPADDR_ADDRESS
:
4402 /* Can't use a register if it is used for an input address
4403 for this operand or used as an input in an earlier
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4408 for (i
= 0; i
< opnum
; i
++)
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4414 case RELOAD_FOR_OUTPUT_ADDRESS
:
4415 /* Can't use a register if it is used for an output address for this
4416 operand or used as an output in this or a later operand. Note
4417 that multiple output operands are emitted in reverse order, so
4418 the conflicting ones are those with lower indices. */
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4422 for (i
= 0; i
<= opnum
; i
++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4428 case RELOAD_FOR_OUTADDR_ADDRESS
:
4429 /* Can't use a register if it is used for an output address
4430 for this operand or used as an output in this or a
4431 later operand. Note that multiple output operands are
4432 emitted in reverse order, so the conflicting ones are
4433 those with lower indices. */
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4437 for (i
= 0; i
<= opnum
; i
++)
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4443 case RELOAD_FOR_OPERAND_ADDRESS
:
4444 for (i
= 0; i
< reload_n_operands
; i
++)
4445 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4448 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4449 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4451 case RELOAD_FOR_OPADDR_ADDR
:
4452 for (i
= 0; i
< reload_n_operands
; i
++)
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4456 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4458 case RELOAD_FOR_OUTPUT
:
4459 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4460 outputs, or an operand address for this or an earlier output.
4461 Note that multiple output operands are emitted in reverse order,
4462 so the conflicting ones are those with higher indices. */
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4466 for (i
= 0; i
< reload_n_operands
; i
++)
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4470 for (i
= opnum
; i
< reload_n_operands
; i
++)
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4472 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4477 case RELOAD_FOR_INSN
:
4478 for (i
= 0; i
< reload_n_operands
; i
++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4480 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4483 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4484 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4486 case RELOAD_FOR_OTHER_ADDRESS
:
4487 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4494 /* Return 1 if the value in reload reg REGNO, as used by a reload
4495 needed for the part of the insn specified by OPNUM and TYPE,
4496 is still available in REGNO at the end of the insn.
4498 We can assume that the reload reg was already tested for availability
4499 at the time it is needed, and we should not check this again,
4500 in case the reg has already been marked in use. */
4503 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4510 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4511 its value must reach the end. */
4514 /* If this use is for part of the insn,
4515 its value reaches if no subsequent part uses the same register.
4516 Just like the above function, don't try to do this with lots
4519 case RELOAD_FOR_OTHER_ADDRESS
:
4520 /* Here we check for everything else, since these don't conflict
4521 with anything else and everything comes later. */
4523 for (i
= 0; i
< reload_n_operands
; i
++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4532 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4533 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4534 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4535 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4537 case RELOAD_FOR_INPUT_ADDRESS
:
4538 case RELOAD_FOR_INPADDR_ADDRESS
:
4539 /* Similar, except that we check only for this and subsequent inputs
4540 and the address of only subsequent inputs and we do not need
4541 to check for RELOAD_OTHER objects since they are known not to
4544 for (i
= opnum
; i
< reload_n_operands
; i
++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4548 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4553 for (i
= 0; i
< reload_n_operands
; i
++)
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4562 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4563 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4564 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4566 case RELOAD_FOR_INPUT
:
4567 /* Similar to input address, except we start at the next operand for
4568 both input and input address and we do not check for
4569 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4572 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4578 /* ... fall through ... */
4580 case RELOAD_FOR_OPERAND_ADDRESS
:
4581 /* Check outputs and their addresses. */
4583 for (i
= 0; i
< reload_n_operands
; i
++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4585 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4586 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4589 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4591 case RELOAD_FOR_OPADDR_ADDR
:
4592 for (i
= 0; i
< reload_n_operands
; i
++)
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4598 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4599 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4600 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4602 case RELOAD_FOR_INSN
:
4603 /* These conflict with other outputs with RELOAD_OTHER. So
4604 we need only check for output addresses. */
4606 opnum
= reload_n_operands
;
4608 /* ... fall through ... */
4610 case RELOAD_FOR_OUTPUT
:
4611 case RELOAD_FOR_OUTPUT_ADDRESS
:
4612 case RELOAD_FOR_OUTADDR_ADDRESS
:
4613 /* We already know these can't conflict with a later output. So the
4614 only thing to check are later output addresses.
4615 Note that multiple output operands are emitted in reverse order,
4616 so the conflicting ones are those with lower indices. */
4617 for (i
= 0; i
< opnum
; i
++)
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4629 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4632 This function uses the same algorithm as reload_reg_free_p above. */
4635 reloads_conflict (int r1
, int r2
)
4637 enum reload_type r1_type
= rld
[r1
].when_needed
;
4638 enum reload_type r2_type
= rld
[r2
].when_needed
;
4639 int r1_opnum
= rld
[r1
].opnum
;
4640 int r2_opnum
= rld
[r2
].opnum
;
4642 /* RELOAD_OTHER conflicts with everything. */
4643 if (r2_type
== RELOAD_OTHER
)
4646 /* Otherwise, check conflicts differently for each type. */
4650 case RELOAD_FOR_INPUT
:
4651 return (r2_type
== RELOAD_FOR_INSN
4652 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4653 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4654 || r2_type
== RELOAD_FOR_INPUT
4655 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4656 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4657 && r2_opnum
> r1_opnum
));
4659 case RELOAD_FOR_INPUT_ADDRESS
:
4660 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4661 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4663 case RELOAD_FOR_INPADDR_ADDRESS
:
4664 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4665 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4667 case RELOAD_FOR_OUTPUT_ADDRESS
:
4668 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4669 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4671 case RELOAD_FOR_OUTADDR_ADDRESS
:
4672 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4673 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4675 case RELOAD_FOR_OPERAND_ADDRESS
:
4676 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4677 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4679 case RELOAD_FOR_OPADDR_ADDR
:
4680 return (r2_type
== RELOAD_FOR_INPUT
4681 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4683 case RELOAD_FOR_OUTPUT
:
4684 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4685 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4686 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4687 && r2_opnum
>= r1_opnum
));
4689 case RELOAD_FOR_INSN
:
4690 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4691 || r2_type
== RELOAD_FOR_INSN
4692 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4694 case RELOAD_FOR_OTHER_ADDRESS
:
4695 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4705 /* Indexed by reload number, 1 if incoming value
4706 inherited from previous insns. */
4707 static char reload_inherited
[MAX_RELOADS
];
4709 /* For an inherited reload, this is the insn the reload was inherited from,
4710 if we know it. Otherwise, this is 0. */
4711 static rtx reload_inheritance_insn
[MAX_RELOADS
];
4713 /* If nonzero, this is a place to get the value of the reload,
4714 rather than using reload_in. */
4715 static rtx reload_override_in
[MAX_RELOADS
];
4717 /* For each reload, the hard register number of the register used,
4718 or -1 if we did not need a register for this reload. */
4719 static int reload_spill_index
[MAX_RELOADS
];
4721 /* Subroutine of free_for_value_p, used to check a single register.
4722 START_REGNO is the starting regno of the full reload register
4723 (possibly comprising multiple hard registers) that we are considering. */
4726 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
4727 enum reload_type type
, rtx value
, rtx out
,
4728 int reloadnum
, int ignore_address_reloads
)
4731 /* Set if we see an input reload that must not share its reload register
4732 with any new earlyclobber, but might otherwise share the reload
4733 register with an output or input-output reload. */
4734 int check_earlyclobber
= 0;
4738 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4741 if (out
== const0_rtx
)
4747 /* We use some pseudo 'time' value to check if the lifetimes of the
4748 new register use would overlap with the one of a previous reload
4749 that is not read-only or uses a different value.
4750 The 'time' used doesn't have to be linear in any shape or form, just
4752 Some reload types use different 'buckets' for each operand.
4753 So there are MAX_RECOG_OPERANDS different time values for each
4755 We compute TIME1 as the time when the register for the prospective
4756 new reload ceases to be live, and TIME2 for each existing
4757 reload as the time when that the reload register of that reload
4759 Where there is little to be gained by exact lifetime calculations,
4760 we just make conservative assumptions, i.e. a longer lifetime;
4761 this is done in the 'default:' cases. */
4764 case RELOAD_FOR_OTHER_ADDRESS
:
4765 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4766 time1
= copy
? 0 : 1;
4769 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4771 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4772 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4773 respectively, to the time values for these, we get distinct time
4774 values. To get distinct time values for each operand, we have to
4775 multiply opnum by at least three. We round that up to four because
4776 multiply by four is often cheaper. */
4777 case RELOAD_FOR_INPADDR_ADDRESS
:
4778 time1
= opnum
* 4 + 2;
4780 case RELOAD_FOR_INPUT_ADDRESS
:
4781 time1
= opnum
* 4 + 3;
4783 case RELOAD_FOR_INPUT
:
4784 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4785 executes (inclusive). */
4786 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4788 case RELOAD_FOR_OPADDR_ADDR
:
4790 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4791 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4793 case RELOAD_FOR_OPERAND_ADDRESS
:
4794 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4796 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4798 case RELOAD_FOR_OUTADDR_ADDRESS
:
4799 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4801 case RELOAD_FOR_OUTPUT_ADDRESS
:
4802 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4805 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4808 for (i
= 0; i
< n_reloads
; i
++)
4810 rtx reg
= rld
[i
].reg_rtx
;
4811 if (reg
&& REG_P (reg
)
4812 && ((unsigned) regno
- true_regnum (reg
)
4813 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
4816 rtx other_input
= rld
[i
].in
;
4818 /* If the other reload loads the same input value, that
4819 will not cause a conflict only if it's loading it into
4820 the same register. */
4821 if (true_regnum (reg
) != start_regno
)
4822 other_input
= NULL_RTX
;
4823 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4824 || rld
[i
].out
|| out
)
4827 switch (rld
[i
].when_needed
)
4829 case RELOAD_FOR_OTHER_ADDRESS
:
4832 case RELOAD_FOR_INPADDR_ADDRESS
:
4833 /* find_reloads makes sure that a
4834 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4835 by at most one - the first -
4836 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4837 address reload is inherited, the address address reload
4838 goes away, so we can ignore this conflict. */
4839 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4840 && ignore_address_reloads
4841 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4842 Then the address address is still needed to store
4843 back the new address. */
4844 && ! rld
[reloadnum
].out
)
4846 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4847 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4849 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4850 && ignore_address_reloads
4851 /* Unless we are reloading an auto_inc expression. */
4852 && ! rld
[reloadnum
].out
)
4854 time2
= rld
[i
].opnum
* 4 + 2;
4856 case RELOAD_FOR_INPUT_ADDRESS
:
4857 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4858 && ignore_address_reloads
4859 && ! rld
[reloadnum
].out
)
4861 time2
= rld
[i
].opnum
* 4 + 3;
4863 case RELOAD_FOR_INPUT
:
4864 time2
= rld
[i
].opnum
* 4 + 4;
4865 check_earlyclobber
= 1;
4867 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4868 == MAX_RECOG_OPERAND * 4 */
4869 case RELOAD_FOR_OPADDR_ADDR
:
4870 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4871 && ignore_address_reloads
4872 && ! rld
[reloadnum
].out
)
4874 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4876 case RELOAD_FOR_OPERAND_ADDRESS
:
4877 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4878 check_earlyclobber
= 1;
4880 case RELOAD_FOR_INSN
:
4881 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4883 case RELOAD_FOR_OUTPUT
:
4884 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4885 instruction is executed. */
4886 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4888 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4889 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4891 case RELOAD_FOR_OUTADDR_ADDRESS
:
4892 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4893 && ignore_address_reloads
4894 && ! rld
[reloadnum
].out
)
4896 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4898 case RELOAD_FOR_OUTPUT_ADDRESS
:
4899 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4902 /* If there is no conflict in the input part, handle this
4903 like an output reload. */
4904 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4906 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4907 /* Earlyclobbered outputs must conflict with inputs. */
4908 if (earlyclobber_operand_p (rld
[i
].out
))
4909 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4914 /* RELOAD_OTHER might be live beyond instruction execution,
4915 but this is not obvious when we set time2 = 1. So check
4916 here if there might be a problem with the new reload
4917 clobbering the register used by the RELOAD_OTHER. */
4925 && (! rld
[i
].in
|| rld
[i
].out
4926 || ! rtx_equal_p (other_input
, value
)))
4927 || (out
&& rld
[reloadnum
].out_reg
4928 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4934 /* Earlyclobbered outputs must conflict with inputs. */
4935 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4941 /* Return 1 if the value in reload reg REGNO, as used by a reload
4942 needed for the part of the insn specified by OPNUM and TYPE,
4943 may be used to load VALUE into it.
4945 MODE is the mode in which the register is used, this is needed to
4946 determine how many hard regs to test.
4948 Other read-only reloads with the same value do not conflict
4949 unless OUT is nonzero and these other reloads have to live while
4950 output reloads live.
4951 If OUT is CONST0_RTX, this is a special case: it means that the
4952 test should not be for using register REGNO as reload register, but
4953 for copying from register REGNO into the reload register.
4955 RELOADNUM is the number of the reload we want to load this value for;
4956 a reload does not conflict with itself.
4958 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4959 reloads that load an address for the very reload we are considering.
4961 The caller has to make sure that there is no conflict with the return
4965 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
4966 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
4967 int ignore_address_reloads
)
4969 int nregs
= hard_regno_nregs
[regno
][mode
];
4971 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
4972 value
, out
, reloadnum
,
4973 ignore_address_reloads
))
4978 /* Return nonzero if the rtx X is invariant over the current function. */
4979 /* ??? Actually, the places where we use this expect exactly what is
4980 tested here, and not everything that is function invariant. In
4981 particular, the frame pointer and arg pointer are special cased;
4982 pic_offset_table_rtx is not, and we must not spill these things to
4986 function_invariant_p (rtx x
)
4990 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4992 if (GET_CODE (x
) == PLUS
4993 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
4994 && CONSTANT_P (XEXP (x
, 1)))
4999 /* Determine whether the reload reg X overlaps any rtx'es used for
5000 overriding inheritance. Return nonzero if so. */
5003 conflicts_with_override (rtx x
)
5006 for (i
= 0; i
< n_reloads
; i
++)
5007 if (reload_override_in
[i
]
5008 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5013 /* Give an error message saying we failed to find a reload for INSN,
5014 and clear out reload R. */
5016 failed_reload (rtx insn
, int r
)
5018 if (asm_noperands (PATTERN (insn
)) < 0)
5019 /* It's the compiler's fault. */
5020 fatal_insn ("could not find a spill register", insn
);
5022 /* It's the user's fault; the operand's mode and constraint
5023 don't match. Disable this reload so we don't crash in final. */
5024 error_for_asm (insn
,
5025 "%<asm%> operand constraint incompatible with operand size");
5029 rld
[r
].optional
= 1;
5030 rld
[r
].secondary_p
= 1;
5033 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5034 for reload R. If it's valid, get an rtx for it. Return nonzero if
5037 set_reload_reg (int i
, int r
)
5040 rtx reg
= spill_reg_rtx
[i
];
5042 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5043 spill_reg_rtx
[i
] = reg
5044 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5046 regno
= true_regnum (reg
);
5048 /* Detect when the reload reg can't hold the reload mode.
5049 This used to be one `if', but Sequent compiler can't handle that. */
5050 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5052 enum machine_mode test_mode
= VOIDmode
;
5054 test_mode
= GET_MODE (rld
[r
].in
);
5055 /* If rld[r].in has VOIDmode, it means we will load it
5056 in whatever mode the reload reg has: to wit, rld[r].mode.
5057 We have already tested that for validity. */
5058 /* Aside from that, we need to test that the expressions
5059 to reload from or into have modes which are valid for this
5060 reload register. Otherwise the reload insns would be invalid. */
5061 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5062 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5063 if (! (rld
[r
].out
!= 0
5064 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5066 /* The reg is OK. */
5069 /* Mark as in use for this insn the reload regs we use
5071 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5072 rld
[r
].when_needed
, rld
[r
].mode
);
5074 rld
[r
].reg_rtx
= reg
;
5075 reload_spill_index
[r
] = spill_regs
[i
];
5082 /* Find a spill register to use as a reload register for reload R.
5083 LAST_RELOAD is nonzero if this is the last reload for the insn being
5086 Set rld[R].reg_rtx to the register allocated.
5088 We return 1 if successful, or 0 if we couldn't find a spill reg and
5089 we didn't change anything. */
5092 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5097 /* If we put this reload ahead, thinking it is a group,
5098 then insist on finding a group. Otherwise we can grab a
5099 reg that some other reload needs.
5100 (That can happen when we have a 68000 DATA_OR_FP_REG
5101 which is a group of data regs or one fp reg.)
5102 We need not be so restrictive if there are no more reloads
5105 ??? Really it would be nicer to have smarter handling
5106 for that kind of reg class, where a problem like this is normal.
5107 Perhaps those classes should be avoided for reloading
5108 by use of more alternatives. */
5110 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5112 /* If we want a single register and haven't yet found one,
5113 take any reg in the right class and not in use.
5114 If we want a consecutive group, here is where we look for it.
5116 We use two passes so we can first look for reload regs to
5117 reuse, which are already in use for other reloads in this insn,
5118 and only then use additional registers.
5119 I think that maximizing reuse is needed to make sure we don't
5120 run out of reload regs. Suppose we have three reloads, and
5121 reloads A and B can share regs. These need two regs.
5122 Suppose A and B are given different regs.
5123 That leaves none for C. */
5124 for (pass
= 0; pass
< 2; pass
++)
5126 /* I is the index in spill_regs.
5127 We advance it round-robin between insns to use all spill regs
5128 equally, so that inherited reloads have a chance
5129 of leapfrogging each other. */
5133 for (count
= 0; count
< n_spills
; count
++)
5135 int class = (int) rld
[r
].class;
5141 regnum
= spill_regs
[i
];
5143 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5146 /* We check reload_reg_used to make sure we
5147 don't clobber the return register. */
5148 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5149 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5150 rld
[r
].when_needed
, rld
[r
].in
,
5152 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5153 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5154 /* Look first for regs to share, then for unshared. But
5155 don't share regs used for inherited reloads; they are
5156 the ones we want to preserve. */
5158 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5160 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5163 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5164 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5165 (on 68000) got us two FP regs. If NR is 1,
5166 we would reject both of them. */
5169 /* If we need only one reg, we have already won. */
5172 /* But reject a single reg if we demand a group. */
5177 /* Otherwise check that as many consecutive regs as we need
5178 are available here. */
5181 int regno
= regnum
+ nr
- 1;
5182 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5183 && spill_reg_order
[regno
] >= 0
5184 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5185 rld
[r
].when_needed
)))
5194 /* If we found something on pass 1, omit pass 2. */
5195 if (count
< n_spills
)
5199 /* We should have found a spill register by now. */
5200 if (count
>= n_spills
)
5203 /* I is the index in SPILL_REG_RTX of the reload register we are to
5204 allocate. Get an rtx for it and find its register number. */
5206 return set_reload_reg (i
, r
);
5209 /* Initialize all the tables needed to allocate reload registers.
5210 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5211 is the array we use to restore the reg_rtx field for every reload. */
5214 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5218 for (i
= 0; i
< n_reloads
; i
++)
5219 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5221 memset (reload_inherited
, 0, MAX_RELOADS
);
5222 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5223 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5225 CLEAR_HARD_REG_SET (reload_reg_used
);
5226 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5227 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5228 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5232 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5235 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5236 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5237 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5238 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5239 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5240 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5243 for (i
= 0; i
< reload_n_operands
; i
++)
5245 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5246 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5253 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5255 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5257 for (i
= 0; i
< n_reloads
; i
++)
5258 /* If we have already decided to use a certain register,
5259 don't use it in another way. */
5261 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5262 rld
[i
].when_needed
, rld
[i
].mode
);
5265 /* Assign hard reg targets for the pseudo-registers we must reload
5266 into hard regs for this insn.
5267 Also output the instructions to copy them in and out of the hard regs.
5269 For machines with register classes, we are responsible for
5270 finding a reload reg in the proper class. */
5273 choose_reload_regs (struct insn_chain
*chain
)
5275 rtx insn
= chain
->insn
;
5277 unsigned int max_group_size
= 1;
5278 enum reg_class group_class
= NO_REGS
;
5279 int pass
, win
, inheritance
;
5281 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5283 /* In order to be certain of getting the registers we need,
5284 we must sort the reloads into order of increasing register class.
5285 Then our grabbing of reload registers will parallel the process
5286 that provided the reload registers.
5288 Also note whether any of the reloads wants a consecutive group of regs.
5289 If so, record the maximum size of the group desired and what
5290 register class contains all the groups needed by this insn. */
5292 for (j
= 0; j
< n_reloads
; j
++)
5294 reload_order
[j
] = j
;
5295 reload_spill_index
[j
] = -1;
5297 if (rld
[j
].nregs
> 1)
5299 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5301 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5304 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5308 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5310 /* If -O, try first with inheritance, then turning it off.
5311 If not -O, don't do inheritance.
5312 Using inheritance when not optimizing leads to paradoxes
5313 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5314 because one side of the comparison might be inherited. */
5316 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5318 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5320 /* Process the reloads in order of preference just found.
5321 Beyond this point, subregs can be found in reload_reg_rtx.
5323 This used to look for an existing reloaded home for all of the
5324 reloads, and only then perform any new reloads. But that could lose
5325 if the reloads were done out of reg-class order because a later
5326 reload with a looser constraint might have an old home in a register
5327 needed by an earlier reload with a tighter constraint.
5329 To solve this, we make two passes over the reloads, in the order
5330 described above. In the first pass we try to inherit a reload
5331 from a previous insn. If there is a later reload that needs a
5332 class that is a proper subset of the class being processed, we must
5333 also allocate a spill register during the first pass.
5335 Then make a second pass over the reloads to allocate any reloads
5336 that haven't been given registers yet. */
5338 for (j
= 0; j
< n_reloads
; j
++)
5340 int r
= reload_order
[j
];
5341 rtx search_equiv
= NULL_RTX
;
5343 /* Ignore reloads that got marked inoperative. */
5344 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5345 && ! rld
[r
].secondary_p
)
5348 /* If find_reloads chose to use reload_in or reload_out as a reload
5349 register, we don't need to chose one. Otherwise, try even if it
5350 found one since we might save an insn if we find the value lying
5352 Try also when reload_in is a pseudo without a hard reg. */
5353 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5354 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5355 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5356 && !MEM_P (rld
[r
].in
)
5357 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5360 #if 0 /* No longer needed for correct operation.
5361 It might give better code, or might not; worth an experiment? */
5362 /* If this is an optional reload, we can't inherit from earlier insns
5363 until we are sure that any non-optional reloads have been allocated.
5364 The following code takes advantage of the fact that optional reloads
5365 are at the end of reload_order. */
5366 if (rld
[r
].optional
!= 0)
5367 for (i
= 0; i
< j
; i
++)
5368 if ((rld
[reload_order
[i
]].out
!= 0
5369 || rld
[reload_order
[i
]].in
!= 0
5370 || rld
[reload_order
[i
]].secondary_p
)
5371 && ! rld
[reload_order
[i
]].optional
5372 && rld
[reload_order
[i
]].reg_rtx
== 0)
5373 allocate_reload_reg (chain
, reload_order
[i
], 0);
5376 /* First see if this pseudo is already available as reloaded
5377 for a previous insn. We cannot try to inherit for reloads
5378 that are smaller than the maximum number of registers needed
5379 for groups unless the register we would allocate cannot be used
5382 We could check here to see if this is a secondary reload for
5383 an object that is already in a register of the desired class.
5384 This would avoid the need for the secondary reload register.
5385 But this is complex because we can't easily determine what
5386 objects might want to be loaded via this reload. So let a
5387 register be allocated here. In `emit_reload_insns' we suppress
5388 one of the loads in the case described above. */
5394 enum machine_mode mode
= VOIDmode
;
5398 else if (REG_P (rld
[r
].in
))
5400 regno
= REGNO (rld
[r
].in
);
5401 mode
= GET_MODE (rld
[r
].in
);
5403 else if (REG_P (rld
[r
].in_reg
))
5405 regno
= REGNO (rld
[r
].in_reg
);
5406 mode
= GET_MODE (rld
[r
].in_reg
);
5408 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5409 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
5411 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5412 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5413 if (regno
< FIRST_PSEUDO_REGISTER
)
5414 regno
= subreg_regno (rld
[r
].in_reg
);
5415 mode
= GET_MODE (rld
[r
].in_reg
);
5418 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5419 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5420 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5421 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5422 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
5424 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5425 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5426 rld
[r
].out
= rld
[r
].in
;
5430 /* This won't work, since REGNO can be a pseudo reg number.
5431 Also, it takes much more hair to keep track of all the things
5432 that can invalidate an inherited reload of part of a pseudoreg. */
5433 else if (GET_CODE (rld
[r
].in
) == SUBREG
5434 && REG_P (SUBREG_REG (rld
[r
].in
)))
5435 regno
= subreg_regno (rld
[r
].in
);
5438 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5440 enum reg_class
class = rld
[r
].class, last_class
;
5441 rtx last_reg
= reg_last_reload_reg
[regno
];
5442 enum machine_mode need_mode
;
5444 i
= REGNO (last_reg
);
5445 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5446 last_class
= REGNO_REG_CLASS (i
);
5452 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
5453 + byte
* BITS_PER_UNIT
,
5454 GET_MODE_CLASS (mode
));
5456 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5457 >= GET_MODE_SIZE (need_mode
))
5458 #ifdef CANNOT_CHANGE_MODE_CLASS
5459 /* Verify that the register in "i" can be obtained
5461 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg
),
5462 GET_MODE (last_reg
),
5465 && reg_reloaded_contents
[i
] == regno
5466 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5467 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5468 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5469 /* Even if we can't use this register as a reload
5470 register, we might use it for reload_override_in,
5471 if copying it to the desired class is cheap
5473 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5474 < MEMORY_MOVE_COST (mode
, class, 1))
5475 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5476 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5480 #ifdef SECONDARY_MEMORY_NEEDED
5481 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5486 && (rld
[r
].nregs
== max_group_size
5487 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5489 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5490 rld
[r
].when_needed
, rld
[r
].in
,
5493 /* If a group is needed, verify that all the subsequent
5494 registers still have their values intact. */
5495 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5498 for (k
= 1; k
< nr
; k
++)
5499 if (reg_reloaded_contents
[i
+ k
] != regno
5500 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5508 last_reg
= (GET_MODE (last_reg
) == mode
5509 ? last_reg
: gen_rtx_REG (mode
, i
));
5512 for (k
= 0; k
< nr
; k
++)
5513 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5516 /* We found a register that contains the
5517 value we need. If this register is the
5518 same as an `earlyclobber' operand of the
5519 current insn, just mark it as a place to
5520 reload from since we can't use it as the
5521 reload register itself. */
5523 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5524 if (reg_overlap_mentioned_for_reload_p
5525 (reg_last_reload_reg
[regno
],
5526 reload_earlyclobbers
[i1
]))
5529 if (i1
!= n_earlyclobbers
5530 || ! (free_for_value_p (i
, rld
[r
].mode
,
5532 rld
[r
].when_needed
, rld
[r
].in
,
5534 /* Don't use it if we'd clobber a pseudo reg. */
5535 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5537 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5538 /* Don't clobber the frame pointer. */
5539 || (i
== HARD_FRAME_POINTER_REGNUM
5540 && frame_pointer_needed
5542 /* Don't really use the inherited spill reg
5543 if we need it wider than we've got it. */
5544 || (GET_MODE_SIZE (rld
[r
].mode
)
5545 > GET_MODE_SIZE (mode
))
5548 /* If find_reloads chose reload_out as reload
5549 register, stay with it - that leaves the
5550 inherited register for subsequent reloads. */
5551 || (rld
[r
].out
&& rld
[r
].reg_rtx
5552 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5554 if (! rld
[r
].optional
)
5556 reload_override_in
[r
] = last_reg
;
5557 reload_inheritance_insn
[r
]
5558 = reg_reloaded_insn
[i
];
5564 /* We can use this as a reload reg. */
5565 /* Mark the register as in use for this part of
5567 mark_reload_reg_in_use (i
,
5571 rld
[r
].reg_rtx
= last_reg
;
5572 reload_inherited
[r
] = 1;
5573 reload_inheritance_insn
[r
]
5574 = reg_reloaded_insn
[i
];
5575 reload_spill_index
[r
] = i
;
5576 for (k
= 0; k
< nr
; k
++)
5577 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5585 /* Here's another way to see if the value is already lying around. */
5588 && ! reload_inherited
[r
]
5590 && (CONSTANT_P (rld
[r
].in
)
5591 || GET_CODE (rld
[r
].in
) == PLUS
5592 || REG_P (rld
[r
].in
)
5593 || MEM_P (rld
[r
].in
))
5594 && (rld
[r
].nregs
== max_group_size
5595 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5596 search_equiv
= rld
[r
].in
;
5597 /* If this is an output reload from a simple move insn, look
5598 if an equivalence for the input is available. */
5599 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5601 rtx set
= single_set (insn
);
5604 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5605 && CONSTANT_P (SET_SRC (set
)))
5606 search_equiv
= SET_SRC (set
);
5612 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5613 -1, NULL
, 0, rld
[r
].mode
);
5619 regno
= REGNO (equiv
);
5622 /* This must be a SUBREG of a hard register.
5623 Make a new REG since this might be used in an
5624 address and not all machines support SUBREGs
5626 gcc_assert (GET_CODE (equiv
) == SUBREG
);
5627 regno
= subreg_regno (equiv
);
5628 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5629 /* If we choose EQUIV as the reload register, but the
5630 loop below decides to cancel the inheritance, we'll
5631 end up reloading EQUIV in rld[r].mode, not the mode
5632 it had originally. That isn't safe when EQUIV isn't
5633 available as a spill register since its value might
5634 still be live at this point. */
5635 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
5636 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
5641 /* If we found a spill reg, reject it unless it is free
5642 and of the desired class. */
5646 int bad_for_class
= 0;
5647 int max_regno
= regno
+ rld
[r
].nregs
;
5649 for (i
= regno
; i
< max_regno
; i
++)
5651 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5653 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5658 && ! free_for_value_p (regno
, rld
[r
].mode
,
5659 rld
[r
].opnum
, rld
[r
].when_needed
,
5660 rld
[r
].in
, rld
[r
].out
, r
, 1))
5665 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5668 /* We found a register that contains the value we need.
5669 If this register is the same as an `earlyclobber' operand
5670 of the current insn, just mark it as a place to reload from
5671 since we can't use it as the reload register itself. */
5674 for (i
= 0; i
< n_earlyclobbers
; i
++)
5675 if (reg_overlap_mentioned_for_reload_p (equiv
,
5676 reload_earlyclobbers
[i
]))
5678 if (! rld
[r
].optional
)
5679 reload_override_in
[r
] = equiv
;
5684 /* If the equiv register we have found is explicitly clobbered
5685 in the current insn, it depends on the reload type if we
5686 can use it, use it for reload_override_in, or not at all.
5687 In particular, we then can't use EQUIV for a
5688 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5692 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5693 switch (rld
[r
].when_needed
)
5695 case RELOAD_FOR_OTHER_ADDRESS
:
5696 case RELOAD_FOR_INPADDR_ADDRESS
:
5697 case RELOAD_FOR_INPUT_ADDRESS
:
5698 case RELOAD_FOR_OPADDR_ADDR
:
5701 case RELOAD_FOR_INPUT
:
5702 case RELOAD_FOR_OPERAND_ADDRESS
:
5703 if (! rld
[r
].optional
)
5704 reload_override_in
[r
] = equiv
;
5710 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5711 switch (rld
[r
].when_needed
)
5713 case RELOAD_FOR_OTHER_ADDRESS
:
5714 case RELOAD_FOR_INPADDR_ADDRESS
:
5715 case RELOAD_FOR_INPUT_ADDRESS
:
5716 case RELOAD_FOR_OPADDR_ADDR
:
5717 case RELOAD_FOR_OPERAND_ADDRESS
:
5718 case RELOAD_FOR_INPUT
:
5721 if (! rld
[r
].optional
)
5722 reload_override_in
[r
] = equiv
;
5730 /* If we found an equivalent reg, say no code need be generated
5731 to load it, and use it as our reload reg. */
5733 && (regno
!= HARD_FRAME_POINTER_REGNUM
5734 || !frame_pointer_needed
))
5736 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
5738 rld
[r
].reg_rtx
= equiv
;
5739 reload_inherited
[r
] = 1;
5741 /* If reg_reloaded_valid is not set for this register,
5742 there might be a stale spill_reg_store lying around.
5743 We must clear it, since otherwise emit_reload_insns
5744 might delete the store. */
5745 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5746 spill_reg_store
[regno
] = NULL_RTX
;
5747 /* If any of the hard registers in EQUIV are spill
5748 registers, mark them as in use for this insn. */
5749 for (k
= 0; k
< nr
; k
++)
5751 i
= spill_reg_order
[regno
+ k
];
5754 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5757 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5764 /* If we found a register to use already, or if this is an optional
5765 reload, we are done. */
5766 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5770 /* No longer needed for correct operation. Might or might
5771 not give better code on the average. Want to experiment? */
5773 /* See if there is a later reload that has a class different from our
5774 class that intersects our class or that requires less register
5775 than our reload. If so, we must allocate a register to this
5776 reload now, since that reload might inherit a previous reload
5777 and take the only available register in our class. Don't do this
5778 for optional reloads since they will force all previous reloads
5779 to be allocated. Also don't do this for reloads that have been
5782 for (i
= j
+ 1; i
< n_reloads
; i
++)
5784 int s
= reload_order
[i
];
5786 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5787 && ! rld
[s
].secondary_p
)
5791 if ((rld
[s
].class != rld
[r
].class
5792 && reg_classes_intersect_p (rld
[r
].class,
5794 || rld
[s
].nregs
< rld
[r
].nregs
)
5801 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5805 /* Now allocate reload registers for anything non-optional that
5806 didn't get one yet. */
5807 for (j
= 0; j
< n_reloads
; j
++)
5809 int r
= reload_order
[j
];
5811 /* Ignore reloads that got marked inoperative. */
5812 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5815 /* Skip reloads that already have a register allocated or are
5817 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5820 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5824 /* If that loop got all the way, we have won. */
5831 /* Loop around and try without any inheritance. */
5836 /* First undo everything done by the failed attempt
5837 to allocate with inheritance. */
5838 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5840 /* Some sanity tests to verify that the reloads found in the first
5841 pass are identical to the ones we have now. */
5842 gcc_assert (chain
->n_reloads
== n_reloads
);
5844 for (i
= 0; i
< n_reloads
; i
++)
5846 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5848 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
5849 for (j
= 0; j
< n_spills
; j
++)
5850 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5851 if (! set_reload_reg (j
, i
))
5852 failed_reload (chain
->insn
, i
);
5856 /* If we thought we could inherit a reload, because it seemed that
5857 nothing else wanted the same reload register earlier in the insn,
5858 verify that assumption, now that all reloads have been assigned.
5859 Likewise for reloads where reload_override_in has been set. */
5861 /* If doing expensive optimizations, do one preliminary pass that doesn't
5862 cancel any inheritance, but removes reloads that have been needed only
5863 for reloads that we know can be inherited. */
5864 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5866 for (j
= 0; j
< n_reloads
; j
++)
5868 int r
= reload_order
[j
];
5870 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5871 check_reg
= rld
[r
].reg_rtx
;
5872 else if (reload_override_in
[r
]
5873 && (REG_P (reload_override_in
[r
])
5874 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5875 check_reg
= reload_override_in
[r
];
5878 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5879 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5880 (reload_inherited
[r
]
5881 ? rld
[r
].out
: const0_rtx
),
5886 reload_inherited
[r
] = 0;
5887 reload_override_in
[r
] = 0;
5889 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5890 reload_override_in, then we do not need its related
5891 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5892 likewise for other reload types.
5893 We handle this by removing a reload when its only replacement
5894 is mentioned in reload_in of the reload we are going to inherit.
5895 A special case are auto_inc expressions; even if the input is
5896 inherited, we still need the address for the output. We can
5897 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5898 If we succeeded removing some reload and we are doing a preliminary
5899 pass just to remove such reloads, make another pass, since the
5900 removal of one reload might allow us to inherit another one. */
5902 && rld
[r
].out
!= rld
[r
].in
5903 && remove_address_replacements (rld
[r
].in
) && pass
)
5908 /* Now that reload_override_in is known valid,
5909 actually override reload_in. */
5910 for (j
= 0; j
< n_reloads
; j
++)
5911 if (reload_override_in
[j
])
5912 rld
[j
].in
= reload_override_in
[j
];
5914 /* If this reload won't be done because it has been canceled or is
5915 optional and not inherited, clear reload_reg_rtx so other
5916 routines (such as subst_reloads) don't get confused. */
5917 for (j
= 0; j
< n_reloads
; j
++)
5918 if (rld
[j
].reg_rtx
!= 0
5919 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5920 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5921 && ! rld
[j
].secondary_p
)))
5923 int regno
= true_regnum (rld
[j
].reg_rtx
);
5925 if (spill_reg_order
[regno
] >= 0)
5926 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5927 rld
[j
].when_needed
, rld
[j
].mode
);
5929 reload_spill_index
[j
] = -1;
5932 /* Record which pseudos and which spill regs have output reloads. */
5933 for (j
= 0; j
< n_reloads
; j
++)
5935 int r
= reload_order
[j
];
5937 i
= reload_spill_index
[r
];
5939 /* I is nonneg if this reload uses a register.
5940 If rld[r].reg_rtx is 0, this is an optional reload
5941 that we opted to ignore. */
5942 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
5943 && rld
[r
].reg_rtx
!= 0)
5945 int nregno
= REGNO (rld
[r
].out_reg
);
5948 if (nregno
< FIRST_PSEUDO_REGISTER
)
5949 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
5952 reg_has_output_reload
[nregno
+ nr
] = 1;
5956 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5958 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5961 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
5962 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
5963 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
5968 /* Deallocate the reload register for reload R. This is called from
5969 remove_address_replacements. */
5972 deallocate_reload_reg (int r
)
5976 if (! rld
[r
].reg_rtx
)
5978 regno
= true_regnum (rld
[r
].reg_rtx
);
5980 if (spill_reg_order
[regno
] >= 0)
5981 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5983 reload_spill_index
[r
] = -1;
5986 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5987 reloads of the same item for fear that we might not have enough reload
5988 registers. However, normally they will get the same reload register
5989 and hence actually need not be loaded twice.
5991 Here we check for the most common case of this phenomenon: when we have
5992 a number of reloads for the same object, each of which were allocated
5993 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5994 reload, and is not modified in the insn itself. If we find such,
5995 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5996 This will not increase the number of spill registers needed and will
5997 prevent redundant code. */
6000 merge_assigned_reloads (rtx insn
)
6004 /* Scan all the reloads looking for ones that only load values and
6005 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6006 assigned and not modified by INSN. */
6008 for (i
= 0; i
< n_reloads
; i
++)
6010 int conflicting_input
= 0;
6011 int max_input_address_opnum
= -1;
6012 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6014 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6015 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6016 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6019 /* Look at all other reloads. Ensure that the only use of this
6020 reload_reg_rtx is in a reload that just loads the same value
6021 as we do. Note that any secondary reloads must be of the identical
6022 class since the values, modes, and result registers are the
6023 same, so we need not do anything with any secondary reloads. */
6025 for (j
= 0; j
< n_reloads
; j
++)
6027 if (i
== j
|| rld
[j
].reg_rtx
== 0
6028 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6032 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6033 && rld
[j
].opnum
> max_input_address_opnum
)
6034 max_input_address_opnum
= rld
[j
].opnum
;
6036 /* If the reload regs aren't exactly the same (e.g, different modes)
6037 or if the values are different, we can't merge this reload.
6038 But if it is an input reload, we might still merge
6039 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6041 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6042 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6043 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6045 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6046 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6047 || rld
[i
].opnum
> rld
[j
].opnum
)
6048 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6050 conflicting_input
= 1;
6051 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6052 min_conflicting_input_opnum
= rld
[j
].opnum
;
6056 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6057 we, in fact, found any matching reloads. */
6060 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6062 for (j
= 0; j
< n_reloads
; j
++)
6063 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6064 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6065 && (! conflicting_input
6066 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6067 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6069 rld
[i
].when_needed
= RELOAD_OTHER
;
6071 reload_spill_index
[j
] = -1;
6072 transfer_replacements (i
, j
);
6075 /* If this is now RELOAD_OTHER, look for any reloads that load
6076 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6077 if they were for inputs, RELOAD_OTHER for outputs. Note that
6078 this test is equivalent to looking for reloads for this operand
6080 /* We must take special care when there are two or more reloads to
6081 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6082 same value or a part of it; we must not change its type if there
6083 is a conflicting input. */
6085 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6086 for (j
= 0; j
< n_reloads
; j
++)
6088 && rld
[j
].when_needed
!= RELOAD_OTHER
6089 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6090 && (! conflicting_input
6091 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6092 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6093 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6099 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6100 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6101 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6103 /* Check to see if we accidentally converted two
6104 reloads that use the same reload register with
6105 different inputs to the same type. If so, the
6106 resulting code won't work. */
6108 for (k
= 0; k
< j
; k
++)
6109 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6110 || rld
[k
].when_needed
!= rld
[j
].when_needed
6111 || !rtx_equal_p (rld
[k
].reg_rtx
,
6113 || rtx_equal_p (rld
[k
].in
,
6120 /* These arrays are filled by emit_reload_insns and its subroutines. */
6121 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6122 static rtx other_input_address_reload_insns
= 0;
6123 static rtx other_input_reload_insns
= 0;
6124 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6125 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6126 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6127 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6128 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6129 static rtx operand_reload_insns
= 0;
6130 static rtx other_operand_reload_insns
= 0;
6131 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6133 /* Values to be put in spill_reg_store are put here first. */
6134 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6135 static HARD_REG_SET reg_reloaded_died
;
6137 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6138 has the number J. OLD contains the value to be used as input. */
6141 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6144 rtx insn
= chain
->insn
;
6145 rtx reloadreg
= rl
->reg_rtx
;
6146 rtx oldequiv_reg
= 0;
6149 enum machine_mode mode
;
6152 /* Determine the mode to reload in.
6153 This is very tricky because we have three to choose from.
6154 There is the mode the insn operand wants (rl->inmode).
6155 There is the mode of the reload register RELOADREG.
6156 There is the intrinsic mode of the operand, which we could find
6157 by stripping some SUBREGs.
6158 It turns out that RELOADREG's mode is irrelevant:
6159 we can change that arbitrarily.
6161 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6162 then the reload reg may not support QImode moves, so use SImode.
6163 If foo is in memory due to spilling a pseudo reg, this is safe,
6164 because the QImode value is in the least significant part of a
6165 slot big enough for a SImode. If foo is some other sort of
6166 memory reference, then it is impossible to reload this case,
6167 so previous passes had better make sure this never happens.
6169 Then consider a one-word union which has SImode and one of its
6170 members is a float, being fetched as (SUBREG:SF union:SI).
6171 We must fetch that as SFmode because we could be loading into
6172 a float-only register. In this case OLD's mode is correct.
6174 Consider an immediate integer: it has VOIDmode. Here we need
6175 to get a mode from something else.
6177 In some cases, there is a fourth mode, the operand's
6178 containing mode. If the insn specifies a containing mode for
6179 this operand, it overrides all others.
6181 I am not sure whether the algorithm here is always right,
6182 but it does the right things in those cases. */
6184 mode
= GET_MODE (old
);
6185 if (mode
== VOIDmode
)
6188 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6189 /* If we need a secondary register for this operation, see if
6190 the value is already in a register in that class. Don't
6191 do this if the secondary register will be used as a scratch
6194 if (rl
->secondary_in_reload
>= 0
6195 && rl
->secondary_in_icode
== CODE_FOR_nothing
6198 = find_equiv_reg (old
, insn
,
6199 rld
[rl
->secondary_in_reload
].class,
6203 /* If reloading from memory, see if there is a register
6204 that already holds the same value. If so, reload from there.
6205 We can pass 0 as the reload_reg_p argument because
6206 any other reload has either already been emitted,
6207 in which case find_equiv_reg will see the reload-insn,
6208 or has yet to be emitted, in which case it doesn't matter
6209 because we will use this equiv reg right away. */
6211 if (oldequiv
== 0 && optimize
6214 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6215 && reg_renumber
[REGNO (old
)] < 0)))
6216 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6220 unsigned int regno
= true_regnum (oldequiv
);
6222 /* Don't use OLDEQUIV if any other reload changes it at an
6223 earlier stage of this insn or at this stage. */
6224 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6225 rl
->in
, const0_rtx
, j
, 0))
6228 /* If it is no cheaper to copy from OLDEQUIV into the
6229 reload register than it would be to move from memory,
6230 don't use it. Likewise, if we need a secondary register
6234 && (((enum reg_class
) REGNO_REG_CLASS (regno
) != rl
->class
6235 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6237 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6238 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6239 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6243 #ifdef SECONDARY_MEMORY_NEEDED
6244 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6252 /* delete_output_reload is only invoked properly if old contains
6253 the original pseudo register. Since this is replaced with a
6254 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6255 find the pseudo in RELOAD_IN_REG. */
6257 && reload_override_in
[j
]
6258 && REG_P (rl
->in_reg
))
6265 else if (REG_P (oldequiv
))
6266 oldequiv_reg
= oldequiv
;
6267 else if (GET_CODE (oldequiv
) == SUBREG
)
6268 oldequiv_reg
= SUBREG_REG (oldequiv
);
6270 /* If we are reloading from a register that was recently stored in
6271 with an output-reload, see if we can prove there was
6272 actually no need to store the old value in it. */
6274 if (optimize
&& REG_P (oldequiv
)
6275 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6276 && spill_reg_store
[REGNO (oldequiv
)]
6278 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6279 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6281 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6283 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6284 then load RELOADREG from OLDEQUIV. Note that we cannot use
6285 gen_lowpart_common since it can do the wrong thing when
6286 RELOADREG has a multi-word mode. Note that RELOADREG
6287 must always be a REG here. */
6289 if (GET_MODE (reloadreg
) != mode
)
6290 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6291 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6292 oldequiv
= SUBREG_REG (oldequiv
);
6293 if (GET_MODE (oldequiv
) != VOIDmode
6294 && mode
!= GET_MODE (oldequiv
))
6295 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6297 /* Switch to the right place to emit the reload insns. */
6298 switch (rl
->when_needed
)
6301 where
= &other_input_reload_insns
;
6303 case RELOAD_FOR_INPUT
:
6304 where
= &input_reload_insns
[rl
->opnum
];
6306 case RELOAD_FOR_INPUT_ADDRESS
:
6307 where
= &input_address_reload_insns
[rl
->opnum
];
6309 case RELOAD_FOR_INPADDR_ADDRESS
:
6310 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6312 case RELOAD_FOR_OUTPUT_ADDRESS
:
6313 where
= &output_address_reload_insns
[rl
->opnum
];
6315 case RELOAD_FOR_OUTADDR_ADDRESS
:
6316 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6318 case RELOAD_FOR_OPERAND_ADDRESS
:
6319 where
= &operand_reload_insns
;
6321 case RELOAD_FOR_OPADDR_ADDR
:
6322 where
= &other_operand_reload_insns
;
6324 case RELOAD_FOR_OTHER_ADDRESS
:
6325 where
= &other_input_address_reload_insns
;
6331 push_to_sequence (*where
);
6333 /* Auto-increment addresses must be reloaded in a special way. */
6334 if (rl
->out
&& ! rl
->out_reg
)
6336 /* We are not going to bother supporting the case where a
6337 incremented register can't be copied directly from
6338 OLDEQUIV since this seems highly unlikely. */
6339 gcc_assert (rl
->secondary_in_reload
< 0);
6341 if (reload_inherited
[j
])
6342 oldequiv
= reloadreg
;
6344 old
= XEXP (rl
->in_reg
, 0);
6346 if (optimize
&& REG_P (oldequiv
)
6347 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6348 && spill_reg_store
[REGNO (oldequiv
)]
6350 && (dead_or_set_p (insn
,
6351 spill_reg_stored_to
[REGNO (oldequiv
)])
6352 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6354 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6356 /* Prevent normal processing of this reload. */
6358 /* Output a special code sequence for this case. */
6359 new_spill_reg_store
[REGNO (reloadreg
)]
6360 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6364 /* If we are reloading a pseudo-register that was set by the previous
6365 insn, see if we can get rid of that pseudo-register entirely
6366 by redirecting the previous insn into our reload register. */
6368 else if (optimize
&& REG_P (old
)
6369 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6370 && dead_or_set_p (insn
, old
)
6371 /* This is unsafe if some other reload
6372 uses the same reg first. */
6373 && ! conflicts_with_override (reloadreg
)
6374 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6375 rl
->when_needed
, old
, rl
->out
, j
, 0))
6377 rtx temp
= PREV_INSN (insn
);
6378 while (temp
&& NOTE_P (temp
))
6379 temp
= PREV_INSN (temp
);
6381 && NONJUMP_INSN_P (temp
)
6382 && GET_CODE (PATTERN (temp
)) == SET
6383 && SET_DEST (PATTERN (temp
)) == old
6384 /* Make sure we can access insn_operand_constraint. */
6385 && asm_noperands (PATTERN (temp
)) < 0
6386 /* This is unsafe if operand occurs more than once in current
6387 insn. Perhaps some occurrences aren't reloaded. */
6388 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6390 rtx old
= SET_DEST (PATTERN (temp
));
6391 /* Store into the reload register instead of the pseudo. */
6392 SET_DEST (PATTERN (temp
)) = reloadreg
;
6394 /* Verify that resulting insn is valid. */
6395 extract_insn (temp
);
6396 if (constrain_operands (1))
6398 /* If the previous insn is an output reload, the source is
6399 a reload register, and its spill_reg_store entry will
6400 contain the previous destination. This is now
6402 if (REG_P (SET_SRC (PATTERN (temp
)))
6403 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6405 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6406 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6409 /* If these are the only uses of the pseudo reg,
6410 pretend for GDB it lives in the reload reg we used. */
6411 if (REG_N_DEATHS (REGNO (old
)) == 1
6412 && REG_N_SETS (REGNO (old
)) == 1)
6414 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6415 alter_reg (REGNO (old
), -1);
6421 SET_DEST (PATTERN (temp
)) = old
;
6426 /* We can't do that, so output an insn to load RELOADREG. */
6428 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6429 /* If we have a secondary reload, pick up the secondary register
6430 and icode, if any. If OLDEQUIV and OLD are different or
6431 if this is an in-out reload, recompute whether or not we
6432 still need a secondary register and what the icode should
6433 be. If we still need a secondary register and the class or
6434 icode is different, go back to reloading from OLD if using
6435 OLDEQUIV means that we got the wrong type of register. We
6436 cannot have different class or icode due to an in-out reload
6437 because we don't make such reloads when both the input and
6438 output need secondary reload registers. */
6440 if (! special
&& rl
->secondary_in_reload
>= 0)
6442 rtx second_reload_reg
= 0;
6443 int secondary_reload
= rl
->secondary_in_reload
;
6444 rtx real_oldequiv
= oldequiv
;
6447 enum insn_code icode
;
6449 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6450 and similarly for OLD.
6451 See comments in get_secondary_reload in reload.c. */
6452 /* If it is a pseudo that cannot be replaced with its
6453 equivalent MEM, we must fall back to reload_in, which
6454 will have all the necessary substitutions registered.
6455 Likewise for a pseudo that can't be replaced with its
6456 equivalent constant.
6458 Take extra care for subregs of such pseudos. Note that
6459 we cannot use reg_equiv_mem in this case because it is
6460 not in the right mode. */
6463 if (GET_CODE (tmp
) == SUBREG
)
6464 tmp
= SUBREG_REG (tmp
);
6466 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6467 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6468 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6470 if (! reg_equiv_mem
[REGNO (tmp
)]
6471 || num_not_at_initial_offset
6472 || GET_CODE (oldequiv
) == SUBREG
)
6473 real_oldequiv
= rl
->in
;
6475 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6479 if (GET_CODE (tmp
) == SUBREG
)
6480 tmp
= SUBREG_REG (tmp
);
6482 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6483 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6484 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6486 if (! reg_equiv_mem
[REGNO (tmp
)]
6487 || num_not_at_initial_offset
6488 || GET_CODE (old
) == SUBREG
)
6491 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6494 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6495 icode
= rl
->secondary_in_icode
;
6497 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6498 || (rl
->in
!= 0 && rl
->out
!= 0))
6500 enum reg_class new_class
6501 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6502 mode
, real_oldequiv
);
6504 if (new_class
== NO_REGS
)
6505 second_reload_reg
= 0;
6508 enum insn_code new_icode
;
6509 enum machine_mode new_mode
;
6511 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6512 REGNO (second_reload_reg
)))
6513 oldequiv
= old
, real_oldequiv
= real_old
;
6516 new_icode
= reload_in_optab
[(int) mode
];
6517 if (new_icode
!= CODE_FOR_nothing
6518 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6519 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6521 || (insn_data
[(int) new_icode
].operand
[1].predicate
6522 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6523 (real_oldequiv
, mode
)))))
6524 new_icode
= CODE_FOR_nothing
;
6526 if (new_icode
== CODE_FOR_nothing
)
6529 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6531 if (GET_MODE (second_reload_reg
) != new_mode
)
6533 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6535 oldequiv
= old
, real_oldequiv
= real_old
;
6538 = reload_adjust_reg_for_mode (second_reload_reg
,
6545 /* If we still need a secondary reload register, check
6546 to see if it is being used as a scratch or intermediate
6547 register and generate code appropriately. If we need
6548 a scratch register, use REAL_OLDEQUIV since the form of
6549 the insn may depend on the actual address if it is
6552 if (second_reload_reg
)
6554 if (icode
!= CODE_FOR_nothing
)
6556 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6557 second_reload_reg
));
6562 /* See if we need a scratch register to load the
6563 intermediate register (a tertiary reload). */
6564 enum insn_code tertiary_icode
6565 = rld
[secondary_reload
].secondary_in_icode
;
6567 if (tertiary_icode
!= CODE_FOR_nothing
)
6569 rtx third_reload_reg
6570 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6572 emit_insn ((GEN_FCN (tertiary_icode
)
6573 (second_reload_reg
, real_oldequiv
,
6574 third_reload_reg
)));
6577 gen_reload (second_reload_reg
, real_oldequiv
,
6581 oldequiv
= second_reload_reg
;
6587 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6589 rtx real_oldequiv
= oldequiv
;
6591 if ((REG_P (oldequiv
)
6592 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6593 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6594 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6595 || (GET_CODE (oldequiv
) == SUBREG
6596 && REG_P (SUBREG_REG (oldequiv
))
6597 && (REGNO (SUBREG_REG (oldequiv
))
6598 >= FIRST_PSEUDO_REGISTER
)
6599 && ((reg_equiv_memory_loc
6600 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6601 || (reg_equiv_constant
6602 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6603 || (CONSTANT_P (oldequiv
)
6604 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6605 REGNO_REG_CLASS (REGNO (reloadreg
)))
6607 real_oldequiv
= rl
->in
;
6608 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6612 if (flag_non_call_exceptions
)
6613 copy_eh_notes (insn
, get_insns ());
6615 /* End this sequence. */
6616 *where
= get_insns ();
6619 /* Update reload_override_in so that delete_address_reloads_1
6620 can see the actual register usage. */
6622 reload_override_in
[j
] = oldequiv
;
6625 /* Generate insns to for the output reload RL, which is for the insn described
6626 by CHAIN and has the number J. */
6628 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6631 rtx reloadreg
= rl
->reg_rtx
;
6632 rtx insn
= chain
->insn
;
6635 enum machine_mode mode
= GET_MODE (old
);
6638 if (rl
->when_needed
== RELOAD_OTHER
)
6641 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6643 /* Determine the mode to reload in.
6644 See comments above (for input reloading). */
6646 if (mode
== VOIDmode
)
6648 /* VOIDmode should never happen for an output. */
6649 if (asm_noperands (PATTERN (insn
)) < 0)
6650 /* It's the compiler's fault. */
6651 fatal_insn ("VOIDmode on an output", insn
);
6652 error_for_asm (insn
, "output operand is constant in %<asm%>");
6653 /* Prevent crash--use something we know is valid. */
6655 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6658 if (GET_MODE (reloadreg
) != mode
)
6659 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6661 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6663 /* If we need two reload regs, set RELOADREG to the intermediate
6664 one, since it will be stored into OLD. We might need a secondary
6665 register only for an input reload, so check again here. */
6667 if (rl
->secondary_out_reload
>= 0)
6671 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6672 && reg_equiv_mem
[REGNO (old
)] != 0)
6673 real_old
= reg_equiv_mem
[REGNO (old
)];
6675 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6679 rtx second_reloadreg
= reloadreg
;
6680 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6682 /* See if RELOADREG is to be used as a scratch register
6683 or as an intermediate register. */
6684 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6686 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6687 (real_old
, second_reloadreg
, reloadreg
)));
6692 /* See if we need both a scratch and intermediate reload
6695 int secondary_reload
= rl
->secondary_out_reload
;
6696 enum insn_code tertiary_icode
6697 = rld
[secondary_reload
].secondary_out_icode
;
6699 if (GET_MODE (reloadreg
) != mode
)
6700 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6702 if (tertiary_icode
!= CODE_FOR_nothing
)
6705 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6708 /* Copy primary reload reg to secondary reload reg.
6709 (Note that these have been swapped above, then
6710 secondary reload reg to OLD using our insn.) */
6712 /* If REAL_OLD is a paradoxical SUBREG, remove it
6713 and try to put the opposite SUBREG on
6715 if (GET_CODE (real_old
) == SUBREG
6716 && (GET_MODE_SIZE (GET_MODE (real_old
))
6717 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6718 && 0 != (tem
= gen_lowpart_common
6719 (GET_MODE (SUBREG_REG (real_old
)),
6721 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6723 gen_reload (reloadreg
, second_reloadreg
,
6724 rl
->opnum
, rl
->when_needed
);
6725 emit_insn ((GEN_FCN (tertiary_icode
)
6726 (real_old
, reloadreg
, third_reloadreg
)));
6731 /* Copy between the reload regs here and then to
6734 gen_reload (reloadreg
, second_reloadreg
,
6735 rl
->opnum
, rl
->when_needed
);
6741 /* Output the last reload insn. */
6746 /* Don't output the last reload if OLD is not the dest of
6747 INSN and is in the src and is clobbered by INSN. */
6748 if (! flag_expensive_optimizations
6750 || !(set
= single_set (insn
))
6751 || rtx_equal_p (old
, SET_DEST (set
))
6752 || !reg_mentioned_p (old
, SET_SRC (set
))
6753 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
6754 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
6755 gen_reload (old
, reloadreg
, rl
->opnum
,
6759 /* Look at all insns we emitted, just to be safe. */
6760 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6763 rtx pat
= PATTERN (p
);
6765 /* If this output reload doesn't come from a spill reg,
6766 clear any memory of reloaded copies of the pseudo reg.
6767 If this output reload comes from a spill reg,
6768 reg_has_output_reload will make this do nothing. */
6769 note_stores (pat
, forget_old_reloads_1
, NULL
);
6771 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6773 rtx set
= single_set (insn
);
6774 if (reload_spill_index
[j
] < 0
6776 && SET_SRC (set
) == rl
->reg_rtx
)
6778 int src
= REGNO (SET_SRC (set
));
6780 reload_spill_index
[j
] = src
;
6781 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6782 if (find_regno_note (insn
, REG_DEAD
, src
))
6783 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6785 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6787 int s
= rl
->secondary_out_reload
;
6788 set
= single_set (p
);
6789 /* If this reload copies only to the secondary reload
6790 register, the secondary reload does the actual
6792 if (s
>= 0 && set
== NULL_RTX
)
6793 /* We can't tell what function the secondary reload
6794 has and where the actual store to the pseudo is
6795 made; leave new_spill_reg_store alone. */
6798 && SET_SRC (set
) == rl
->reg_rtx
6799 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6801 /* Usually the next instruction will be the
6802 secondary reload insn; if we can confirm
6803 that it is, setting new_spill_reg_store to
6804 that insn will allow an extra optimization. */
6805 rtx s_reg
= rld
[s
].reg_rtx
;
6806 rtx next
= NEXT_INSN (p
);
6807 rld
[s
].out
= rl
->out
;
6808 rld
[s
].out_reg
= rl
->out_reg
;
6809 set
= single_set (next
);
6810 if (set
&& SET_SRC (set
) == s_reg
6811 && ! new_spill_reg_store
[REGNO (s_reg
)])
6813 SET_HARD_REG_BIT (reg_is_output_reload
,
6815 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6819 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6824 if (rl
->when_needed
== RELOAD_OTHER
)
6826 emit_insn (other_output_reload_insns
[rl
->opnum
]);
6827 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6830 output_reload_insns
[rl
->opnum
] = get_insns ();
6832 if (flag_non_call_exceptions
)
6833 copy_eh_notes (insn
, get_insns ());
6838 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6839 and has the number J. */
6841 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6843 rtx insn
= chain
->insn
;
6844 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
6845 ? rl
->in_reg
: rl
->in
);
6848 /* AUTO_INC reloads need to be handled even if inherited. We got an
6849 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6850 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6851 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6852 && rl
->reg_rtx
!= 0)
6853 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6855 /* When inheriting a wider reload, we have a MEM in rl->in,
6856 e.g. inheriting a SImode output reload for
6857 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6858 if (optimize
&& reload_inherited
[j
] && rl
->in
6860 && MEM_P (rl
->in_reg
)
6861 && reload_spill_index
[j
] >= 0
6862 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6863 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6865 /* If we are reloading a register that was recently stored in with an
6866 output-reload, see if we can prove there was
6867 actually no need to store the old value in it. */
6870 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6871 that there may be multiple uses of the previous output reload.
6872 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6873 && rl
->when_needed
== RELOAD_FOR_INPUT
6874 && (reload_inherited
[j
] || reload_override_in
[j
])
6876 && REG_P (rl
->reg_rtx
)
6877 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6879 /* There doesn't seem to be any reason to restrict this to pseudos
6880 and doing so loses in the case where we are copying from a
6881 register of the wrong class. */
6882 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6883 >= FIRST_PSEUDO_REGISTER
)
6885 /* The insn might have already some references to stackslots
6886 replaced by MEMs, while reload_out_reg still names the
6888 && (dead_or_set_p (insn
,
6889 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6890 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6892 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6895 /* Do output reloading for reload RL, which is for the insn described by
6896 CHAIN and has the number J.
6897 ??? At some point we need to support handling output reloads of
6898 JUMP_INSNs or insns that set cc0. */
6900 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
6903 rtx insn
= chain
->insn
;
6904 /* If this is an output reload that stores something that is
6905 not loaded in this same reload, see if we can eliminate a previous
6907 rtx pseudo
= rl
->out_reg
;
6912 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6913 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6914 && reg_last_reload_reg
[REGNO (pseudo
)])
6916 int pseudo_no
= REGNO (pseudo
);
6917 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6919 /* We don't need to test full validity of last_regno for
6920 inherit here; we only want to know if the store actually
6921 matches the pseudo. */
6922 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6923 && reg_reloaded_contents
[last_regno
] == pseudo_no
6924 && spill_reg_store
[last_regno
]
6925 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6926 delete_output_reload (insn
, j
, last_regno
);
6931 || rl
->reg_rtx
== old
6932 || rl
->reg_rtx
== 0)
6935 /* An output operand that dies right away does need a reload,
6936 but need not be copied from it. Show the new location in the
6938 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
6939 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6941 XEXP (note
, 0) = rl
->reg_rtx
;
6944 /* Likewise for a SUBREG of an operand that dies. */
6945 else if (GET_CODE (old
) == SUBREG
6946 && REG_P (SUBREG_REG (old
))
6947 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6950 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6954 else if (GET_CODE (old
) == SCRATCH
)
6955 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6956 but we don't want to make an output reload. */
6959 /* If is a JUMP_INSN, we can't support output reloads yet. */
6960 gcc_assert (!JUMP_P (insn
));
6962 emit_output_reload_insns (chain
, rld
+ j
, j
);
6965 /* Reload number R reloads from or to a group of hard registers starting at
6966 register REGNO. Return true if it can be treated for inheritance purposes
6967 like a group of reloads, each one reloading a single hard register.
6968 The caller has already checked that the spill register and REGNO use
6969 the same number of registers to store the reload value. */
6972 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED
, int regno ATTRIBUTE_UNUSED
)
6974 #ifdef CANNOT_CHANGE_MODE_CLASS
6975 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index
[r
],
6976 GET_MODE (rld
[r
].reg_rtx
),
6977 reg_raw_mode
[reload_spill_index
[r
]])
6978 && !REG_CANNOT_CHANGE_MODE_P (regno
,
6979 GET_MODE (rld
[r
].reg_rtx
),
6980 reg_raw_mode
[regno
]));
6986 /* Output insns to reload values in and out of the chosen reload regs. */
6989 emit_reload_insns (struct insn_chain
*chain
)
6991 rtx insn
= chain
->insn
;
6995 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6997 for (j
= 0; j
< reload_n_operands
; j
++)
6998 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6999 = inpaddr_address_reload_insns
[j
]
7000 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7001 = outaddr_address_reload_insns
[j
]
7002 = other_output_reload_insns
[j
] = 0;
7003 other_input_address_reload_insns
= 0;
7004 other_input_reload_insns
= 0;
7005 operand_reload_insns
= 0;
7006 other_operand_reload_insns
= 0;
7008 /* Dump reloads into the dump file. */
7011 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7012 debug_reload_to_stream (dump_file
);
7015 /* Now output the instructions to copy the data into and out of the
7016 reload registers. Do these in the order that the reloads were reported,
7017 since reloads of base and index registers precede reloads of operands
7018 and the operands may need the base and index registers reloaded. */
7020 for (j
= 0; j
< n_reloads
; j
++)
7023 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7024 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
7026 do_input_reload (chain
, rld
+ j
, j
);
7027 do_output_reload (chain
, rld
+ j
, j
);
7030 /* Now write all the insns we made for reloads in the order expected by
7031 the allocation functions. Prior to the insn being reloaded, we write
7032 the following reloads:
7034 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7036 RELOAD_OTHER reloads.
7038 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7039 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7040 RELOAD_FOR_INPUT reload for the operand.
7042 RELOAD_FOR_OPADDR_ADDRS reloads.
7044 RELOAD_FOR_OPERAND_ADDRESS reloads.
7046 After the insn being reloaded, we write the following:
7048 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7049 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7050 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7051 reloads for the operand. The RELOAD_OTHER output reloads are
7052 output in descending order by reload number. */
7054 emit_insn_before (other_input_address_reload_insns
, insn
);
7055 emit_insn_before (other_input_reload_insns
, insn
);
7057 for (j
= 0; j
< reload_n_operands
; j
++)
7059 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7060 emit_insn_before (input_address_reload_insns
[j
], insn
);
7061 emit_insn_before (input_reload_insns
[j
], insn
);
7064 emit_insn_before (other_operand_reload_insns
, insn
);
7065 emit_insn_before (operand_reload_insns
, insn
);
7067 for (j
= 0; j
< reload_n_operands
; j
++)
7069 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7070 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7071 x
= emit_insn_after (output_reload_insns
[j
], x
);
7072 emit_insn_after (other_output_reload_insns
[j
], x
);
7075 /* For all the spill regs newly reloaded in this instruction,
7076 record what they were reloaded from, so subsequent instructions
7077 can inherit the reloads.
7079 Update spill_reg_store for the reloads of this insn.
7080 Copy the elements that were updated in the loop above. */
7082 for (j
= 0; j
< n_reloads
; j
++)
7084 int r
= reload_order
[j
];
7085 int i
= reload_spill_index
[r
];
7087 /* If this is a non-inherited input reload from a pseudo, we must
7088 clear any memory of a previous store to the same pseudo. Only do
7089 something if there will not be an output reload for the pseudo
7091 if (rld
[r
].in_reg
!= 0
7092 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7094 rtx reg
= rld
[r
].in_reg
;
7096 if (GET_CODE (reg
) == SUBREG
)
7097 reg
= SUBREG_REG (reg
);
7100 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7101 && ! reg_has_output_reload
[REGNO (reg
)])
7103 int nregno
= REGNO (reg
);
7105 if (reg_last_reload_reg
[nregno
])
7107 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7109 if (reg_reloaded_contents
[last_regno
] == nregno
)
7110 spill_reg_store
[last_regno
] = 0;
7115 /* I is nonneg if this reload used a register.
7116 If rld[r].reg_rtx is 0, this is an optional reload
7117 that we opted to ignore. */
7119 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7121 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7123 int part_reaches_end
= 0;
7124 int all_reaches_end
= 1;
7126 /* For a multi register reload, we need to check if all or part
7127 of the value lives to the end. */
7128 for (k
= 0; k
< nr
; k
++)
7130 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7131 rld
[r
].when_needed
))
7132 part_reaches_end
= 1;
7134 all_reaches_end
= 0;
7137 /* Ignore reloads that don't reach the end of the insn in
7139 if (all_reaches_end
)
7141 /* First, clear out memory of what used to be in this spill reg.
7142 If consecutive registers are used, clear them all. */
7144 for (k
= 0; k
< nr
; k
++)
7146 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7147 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7150 /* Maybe the spill reg contains a copy of reload_out. */
7152 && (REG_P (rld
[r
].out
)
7156 || REG_P (rld
[r
].out_reg
)))
7158 rtx out
= (REG_P (rld
[r
].out
)
7162 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7163 int nregno
= REGNO (out
);
7164 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7165 : hard_regno_nregs
[nregno
]
7166 [GET_MODE (rld
[r
].reg_rtx
)]);
7169 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7170 spill_reg_stored_to
[i
] = out
;
7171 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7173 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7175 && inherit_piecemeal_p (r
, nregno
));
7177 /* If NREGNO is a hard register, it may occupy more than
7178 one register. If it does, say what is in the
7179 rest of the registers assuming that both registers
7180 agree on how many words the object takes. If not,
7181 invalidate the subsequent registers. */
7183 if (nregno
< FIRST_PSEUDO_REGISTER
)
7184 for (k
= 1; k
< nnr
; k
++)
7185 reg_last_reload_reg
[nregno
+ k
]
7187 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7190 /* Now do the inverse operation. */
7191 for (k
= 0; k
< nr
; k
++)
7193 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7194 reg_reloaded_contents
[i
+ k
]
7195 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7198 reg_reloaded_insn
[i
+ k
] = insn
;
7199 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7200 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (out
)))
7201 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7205 /* Maybe the spill reg contains a copy of reload_in. Only do
7206 something if there will not be an output reload for
7207 the register being reloaded. */
7208 else if (rld
[r
].out_reg
== 0
7210 && ((REG_P (rld
[r
].in
)
7211 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7212 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7213 || (REG_P (rld
[r
].in_reg
)
7214 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7215 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7222 if (REG_P (rld
[r
].in
)
7223 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7225 else if (REG_P (rld
[r
].in_reg
))
7228 in
= XEXP (rld
[r
].in_reg
, 0);
7229 nregno
= REGNO (in
);
7231 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7232 : hard_regno_nregs
[nregno
]
7233 [GET_MODE (rld
[r
].reg_rtx
)]);
7235 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7237 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7239 && inherit_piecemeal_p (r
, nregno
));
7241 if (nregno
< FIRST_PSEUDO_REGISTER
)
7242 for (k
= 1; k
< nnr
; k
++)
7243 reg_last_reload_reg
[nregno
+ k
]
7245 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7248 /* Unless we inherited this reload, show we haven't
7249 recently done a store.
7250 Previous stores of inherited auto_inc expressions
7251 also have to be discarded. */
7252 if (! reload_inherited
[r
]
7253 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7254 spill_reg_store
[i
] = 0;
7256 for (k
= 0; k
< nr
; k
++)
7258 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7259 reg_reloaded_contents
[i
+ k
]
7260 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7263 reg_reloaded_insn
[i
+ k
] = insn
;
7264 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7265 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (in
)))
7266 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7271 /* However, if part of the reload reaches the end, then we must
7272 invalidate the old info for the part that survives to the end. */
7273 else if (part_reaches_end
)
7275 for (k
= 0; k
< nr
; k
++)
7276 if (reload_reg_reaches_end_p (i
+ k
,
7278 rld
[r
].when_needed
))
7279 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7283 /* The following if-statement was #if 0'd in 1.34 (or before...).
7284 It's reenabled in 1.35 because supposedly nothing else
7285 deals with this problem. */
7287 /* If a register gets output-reloaded from a non-spill register,
7288 that invalidates any previous reloaded copy of it.
7289 But forget_old_reloads_1 won't get to see it, because
7290 it thinks only about the original insn. So invalidate it here. */
7291 if (i
< 0 && rld
[r
].out
!= 0
7292 && (REG_P (rld
[r
].out
)
7293 || (MEM_P (rld
[r
].out
)
7294 && REG_P (rld
[r
].out_reg
))))
7296 rtx out
= (REG_P (rld
[r
].out
)
7297 ? rld
[r
].out
: rld
[r
].out_reg
);
7298 int nregno
= REGNO (out
);
7299 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7301 rtx src_reg
, store_insn
= NULL_RTX
;
7303 reg_last_reload_reg
[nregno
] = 0;
7305 /* If we can find a hard register that is stored, record
7306 the storing insn so that we may delete this insn with
7307 delete_output_reload. */
7308 src_reg
= rld
[r
].reg_rtx
;
7310 /* If this is an optional reload, try to find the source reg
7311 from an input reload. */
7314 rtx set
= single_set (insn
);
7315 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7319 src_reg
= SET_SRC (set
);
7321 for (k
= 0; k
< n_reloads
; k
++)
7323 if (rld
[k
].in
== src_reg
)
7325 src_reg
= rld
[k
].reg_rtx
;
7332 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7333 if (src_reg
&& REG_P (src_reg
)
7334 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7336 int src_regno
= REGNO (src_reg
);
7337 int nr
= hard_regno_nregs
[src_regno
][rld
[r
].mode
];
7338 /* The place where to find a death note varies with
7339 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7340 necessarily checked exactly in the code that moves
7341 notes, so just check both locations. */
7342 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7343 if (! note
&& store_insn
)
7344 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7347 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7348 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7349 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7350 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7351 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7352 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7353 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ nr
,
7354 GET_MODE (src_reg
)))
7355 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7357 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7359 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7361 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7363 reg_last_reload_reg
[nregno
] = src_reg
;
7364 /* We have to set reg_has_output_reload here, or else
7365 forget_old_reloads_1 will clear reg_last_reload_reg
7367 reg_has_output_reload
[nregno
] = 1;
7372 int num_regs
= hard_regno_nregs
[nregno
][GET_MODE (rld
[r
].out
)];
7374 while (num_regs
-- > 0)
7375 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7379 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7382 /* Emit code to perform a reload from IN (which may be a reload register) to
7383 OUT (which may also be a reload register). IN or OUT is from operand
7384 OPNUM with reload type TYPE.
7386 Returns first insn emitted. */
7389 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7391 rtx last
= get_last_insn ();
7394 /* If IN is a paradoxical SUBREG, remove it and try to put the
7395 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7396 if (GET_CODE (in
) == SUBREG
7397 && (GET_MODE_SIZE (GET_MODE (in
))
7398 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7399 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7400 in
= SUBREG_REG (in
), out
= tem
;
7401 else if (GET_CODE (out
) == SUBREG
7402 && (GET_MODE_SIZE (GET_MODE (out
))
7403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7404 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7405 out
= SUBREG_REG (out
), in
= tem
;
7407 /* How to do this reload can get quite tricky. Normally, we are being
7408 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7409 register that didn't get a hard register. In that case we can just
7410 call emit_move_insn.
7412 We can also be asked to reload a PLUS that adds a register or a MEM to
7413 another register, constant or MEM. This can occur during frame pointer
7414 elimination and while reloading addresses. This case is handled by
7415 trying to emit a single insn to perform the add. If it is not valid,
7416 we use a two insn sequence.
7418 Finally, we could be called to handle an 'o' constraint by putting
7419 an address into a register. In that case, we first try to do this
7420 with a named pattern of "reload_load_address". If no such pattern
7421 exists, we just emit a SET insn and hope for the best (it will normally
7422 be valid on machines that use 'o').
7424 This entire process is made complex because reload will never
7425 process the insns we generate here and so we must ensure that
7426 they will fit their constraints and also by the fact that parts of
7427 IN might be being reloaded separately and replaced with spill registers.
7428 Because of this, we are, in some sense, just guessing the right approach
7429 here. The one listed above seems to work.
7431 ??? At some point, this whole thing needs to be rethought. */
7433 if (GET_CODE (in
) == PLUS
7434 && (REG_P (XEXP (in
, 0))
7435 || GET_CODE (XEXP (in
, 0)) == SUBREG
7436 || MEM_P (XEXP (in
, 0)))
7437 && (REG_P (XEXP (in
, 1))
7438 || GET_CODE (XEXP (in
, 1)) == SUBREG
7439 || CONSTANT_P (XEXP (in
, 1))
7440 || MEM_P (XEXP (in
, 1))))
7442 /* We need to compute the sum of a register or a MEM and another
7443 register, constant, or MEM, and put it into the reload
7444 register. The best possible way of doing this is if the machine
7445 has a three-operand ADD insn that accepts the required operands.
7447 The simplest approach is to try to generate such an insn and see if it
7448 is recognized and matches its constraints. If so, it can be used.
7450 It might be better not to actually emit the insn unless it is valid,
7451 but we need to pass the insn as an operand to `recog' and
7452 `extract_insn' and it is simpler to emit and then delete the insn if
7453 not valid than to dummy things up. */
7455 rtx op0
, op1
, tem
, insn
;
7458 op0
= find_replacement (&XEXP (in
, 0));
7459 op1
= find_replacement (&XEXP (in
, 1));
7461 /* Since constraint checking is strict, commutativity won't be
7462 checked, so we need to do that here to avoid spurious failure
7463 if the add instruction is two-address and the second operand
7464 of the add is the same as the reload reg, which is frequently
7465 the case. If the insn would be A = B + A, rearrange it so
7466 it will be A = A + B as constrain_operands expects. */
7468 if (REG_P (XEXP (in
, 1))
7469 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7470 tem
= op0
, op0
= op1
, op1
= tem
;
7472 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7473 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7475 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7476 code
= recog_memoized (insn
);
7480 extract_insn (insn
);
7481 /* We want constrain operands to treat this insn strictly in
7482 its validity determination, i.e., the way it would after reload
7484 if (constrain_operands (1))
7488 delete_insns_since (last
);
7490 /* If that failed, we must use a conservative two-insn sequence.
7492 Use a move to copy one operand into the reload register. Prefer
7493 to reload a constant, MEM or pseudo since the move patterns can
7494 handle an arbitrary operand. If OP1 is not a constant, MEM or
7495 pseudo and OP1 is not a valid operand for an add instruction, then
7498 After reloading one of the operands into the reload register, add
7499 the reload register to the output register.
7501 If there is another way to do this for a specific machine, a
7502 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7505 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7507 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
7509 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7510 || (code
!= CODE_FOR_nothing
7511 && ! ((*insn_data
[code
].operand
[2].predicate
)
7512 (op1
, insn_data
[code
].operand
[2].mode
))))
7513 tem
= op0
, op0
= op1
, op1
= tem
;
7515 gen_reload (out
, op0
, opnum
, type
);
7517 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7518 This fixes a problem on the 32K where the stack pointer cannot
7519 be used as an operand of an add insn. */
7521 if (rtx_equal_p (op0
, op1
))
7524 insn
= emit_insn (gen_add2_insn (out
, op1
));
7526 /* If that failed, copy the address register to the reload register.
7527 Then add the constant to the reload register. */
7529 code
= recog_memoized (insn
);
7533 extract_insn (insn
);
7534 /* We want constrain operands to treat this insn strictly in
7535 its validity determination, i.e., the way it would after reload
7537 if (constrain_operands (1))
7539 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7541 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7546 delete_insns_since (last
);
7548 gen_reload (out
, op1
, opnum
, type
);
7549 insn
= emit_insn (gen_add2_insn (out
, op0
));
7550 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7553 #ifdef SECONDARY_MEMORY_NEEDED
7554 /* If we need a memory location to do the move, do it that way. */
7555 else if ((REG_P (in
) || GET_CODE (in
) == SUBREG
)
7556 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7557 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
7558 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7559 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7560 REGNO_REG_CLASS (reg_or_subregno (out
)),
7563 /* Get the memory to use and rewrite both registers to its mode. */
7564 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7566 if (GET_MODE (loc
) != GET_MODE (out
))
7567 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7569 if (GET_MODE (loc
) != GET_MODE (in
))
7570 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7572 gen_reload (loc
, in
, opnum
, type
);
7573 gen_reload (out
, loc
, opnum
, type
);
7577 /* If IN is a simple operand, use gen_move_insn. */
7578 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
7579 emit_insn (gen_move_insn (out
, in
));
7581 #ifdef HAVE_reload_load_address
7582 else if (HAVE_reload_load_address
)
7583 emit_insn (gen_reload_load_address (out
, in
));
7586 /* Otherwise, just write (set OUT IN) and hope for the best. */
7588 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7590 /* Return the first insn emitted.
7591 We can not just return get_last_insn, because there may have
7592 been multiple instructions emitted. Also note that gen_move_insn may
7593 emit more than one insn itself, so we can not assume that there is one
7594 insn emitted per emit_insn_before call. */
7596 return last
? NEXT_INSN (last
) : get_insns ();
7599 /* Delete a previously made output-reload whose result we now believe
7600 is not needed. First we double-check.
7602 INSN is the insn now being processed.
7603 LAST_RELOAD_REG is the hard register number for which we want to delete
7604 the last output reload.
7605 J is the reload-number that originally used REG. The caller has made
7606 certain that reload J doesn't use REG any longer for input. */
7609 delete_output_reload (rtx insn
, int j
, int last_reload_reg
)
7611 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7612 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7615 int n_inherited
= 0;
7619 /* It is possible that this reload has been only used to set another reload
7620 we eliminated earlier and thus deleted this instruction too. */
7621 if (INSN_DELETED_P (output_reload_insn
))
7624 /* Get the raw pseudo-register referred to. */
7626 while (GET_CODE (reg
) == SUBREG
)
7627 reg
= SUBREG_REG (reg
);
7628 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7630 /* This is unsafe if the operand occurs more often in the current
7631 insn than it is inherited. */
7632 for (k
= n_reloads
- 1; k
>= 0; k
--)
7634 rtx reg2
= rld
[k
].in
;
7637 if (MEM_P (reg2
) || reload_override_in
[k
])
7638 reg2
= rld
[k
].in_reg
;
7640 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7641 reg2
= XEXP (rld
[k
].in_reg
, 0);
7643 while (GET_CODE (reg2
) == SUBREG
)
7644 reg2
= SUBREG_REG (reg2
);
7645 if (rtx_equal_p (reg2
, reg
))
7647 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7650 reg2
= rld
[k
].out_reg
;
7653 while (GET_CODE (reg2
) == SUBREG
)
7654 reg2
= XEXP (reg2
, 0);
7655 if (rtx_equal_p (reg2
, reg
))
7662 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7664 n_occurrences
+= count_occurrences (PATTERN (insn
),
7665 eliminate_regs (substed
, 0,
7667 if (n_occurrences
> n_inherited
)
7670 /* If the pseudo-reg we are reloading is no longer referenced
7671 anywhere between the store into it and here,
7672 and we're within the same basic block, then the value can only
7673 pass through the reload reg and end up here.
7674 Otherwise, give up--return. */
7675 for (i1
= NEXT_INSN (output_reload_insn
);
7676 i1
!= insn
; i1
= NEXT_INSN (i1
))
7678 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
7680 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
7681 && reg_mentioned_p (reg
, PATTERN (i1
)))
7683 /* If this is USE in front of INSN, we only have to check that
7684 there are no more references than accounted for by inheritance. */
7685 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
7687 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7688 i1
= NEXT_INSN (i1
);
7690 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7696 /* We will be deleting the insn. Remove the spill reg information. */
7697 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
7699 spill_reg_store
[last_reload_reg
+ k
] = 0;
7700 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
7703 /* The caller has already checked that REG dies or is set in INSN.
7704 It has also checked that we are optimizing, and thus some
7705 inaccuracies in the debugging information are acceptable.
7706 So we could just delete output_reload_insn. But in some cases
7707 we can improve the debugging information without sacrificing
7708 optimization - maybe even improving the code: See if the pseudo
7709 reg has been completely replaced with reload regs. If so, delete
7710 the store insn and forget we had a stack slot for the pseudo. */
7711 if (rld
[j
].out
!= rld
[j
].in
7712 && REG_N_DEATHS (REGNO (reg
)) == 1
7713 && REG_N_SETS (REGNO (reg
)) == 1
7714 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7715 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7719 /* We know that it was used only between here and the beginning of
7720 the current basic block. (We also know that the last use before
7721 INSN was the output reload we are thinking of deleting, but never
7722 mind that.) Search that range; see if any ref remains. */
7723 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7725 rtx set
= single_set (i2
);
7727 /* Uses which just store in the pseudo don't count,
7728 since if they are the only uses, they are dead. */
7729 if (set
!= 0 && SET_DEST (set
) == reg
)
7734 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
7735 && reg_mentioned_p (reg
, PATTERN (i2
)))
7737 /* Some other ref remains; just delete the output reload we
7739 delete_address_reloads (output_reload_insn
, insn
);
7740 delete_insn (output_reload_insn
);
7745 /* Delete the now-dead stores into this pseudo. Note that this
7746 loop also takes care of deleting output_reload_insn. */
7747 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7749 rtx set
= single_set (i2
);
7751 if (set
!= 0 && SET_DEST (set
) == reg
)
7753 delete_address_reloads (i2
, insn
);
7761 /* For the debugging info, say the pseudo lives in this reload reg. */
7762 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7763 alter_reg (REGNO (reg
), -1);
7767 delete_address_reloads (output_reload_insn
, insn
);
7768 delete_insn (output_reload_insn
);
7772 /* We are going to delete DEAD_INSN. Recursively delete loads of
7773 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7774 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7776 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
7778 rtx set
= single_set (dead_insn
);
7779 rtx set2
, dst
, prev
, next
;
7782 rtx dst
= SET_DEST (set
);
7784 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7786 /* If we deleted the store from a reloaded post_{in,de}c expression,
7787 we can delete the matching adds. */
7788 prev
= PREV_INSN (dead_insn
);
7789 next
= NEXT_INSN (dead_insn
);
7790 if (! prev
|| ! next
)
7792 set
= single_set (next
);
7793 set2
= single_set (prev
);
7795 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7796 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7797 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7799 dst
= SET_DEST (set
);
7800 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7801 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7802 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7803 || (INTVAL (XEXP (SET_SRC (set
), 1))
7804 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7806 delete_related_insns (prev
);
7807 delete_related_insns (next
);
7810 /* Subfunction of delete_address_reloads: process registers found in X. */
7812 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
7814 rtx prev
, set
, dst
, i2
;
7816 enum rtx_code code
= GET_CODE (x
);
7820 const char *fmt
= GET_RTX_FORMAT (code
);
7821 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7824 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7825 else if (fmt
[i
] == 'E')
7827 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7828 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7835 if (spill_reg_order
[REGNO (x
)] < 0)
7838 /* Scan backwards for the insn that sets x. This might be a way back due
7840 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7842 code
= GET_CODE (prev
);
7843 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7847 if (reg_set_p (x
, PATTERN (prev
)))
7849 if (reg_referenced_p (x
, PATTERN (prev
)))
7852 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7854 /* Check that PREV only sets the reload register. */
7855 set
= single_set (prev
);
7858 dst
= SET_DEST (set
);
7860 || ! rtx_equal_p (dst
, x
))
7862 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7864 /* Check if DST was used in a later insn -
7865 it might have been inherited. */
7866 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7872 if (reg_referenced_p (dst
, PATTERN (i2
)))
7874 /* If there is a reference to the register in the current insn,
7875 it might be loaded in a non-inherited reload. If no other
7876 reload uses it, that means the register is set before
7878 if (i2
== current_insn
)
7880 for (j
= n_reloads
- 1; j
>= 0; j
--)
7881 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7882 || reload_override_in
[j
] == dst
)
7884 for (j
= n_reloads
- 1; j
>= 0; j
--)
7885 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7894 /* If DST is still live at CURRENT_INSN, check if it is used for
7895 any reload. Note that even if CURRENT_INSN sets DST, we still
7896 have to check the reloads. */
7897 if (i2
== current_insn
)
7899 for (j
= n_reloads
- 1; j
>= 0; j
--)
7900 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7901 || reload_override_in
[j
] == dst
)
7903 /* ??? We can't finish the loop here, because dst might be
7904 allocated to a pseudo in this block if no reload in this
7905 block needs any of the classes containing DST - see
7906 spill_hard_reg. There is no easy way to tell this, so we
7907 have to scan till the end of the basic block. */
7909 if (reg_set_p (dst
, PATTERN (i2
)))
7913 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7914 reg_reloaded_contents
[REGNO (dst
)] = -1;
7918 /* Output reload-insns to reload VALUE into RELOADREG.
7919 VALUE is an autoincrement or autodecrement RTX whose operand
7920 is a register or memory location;
7921 so reloading involves incrementing that location.
7922 IN is either identical to VALUE, or some cheaper place to reload from.
7924 INC_AMOUNT is the number to increment or decrement by (always positive).
7925 This cannot be deduced from VALUE.
7927 Return the instruction that stores into RELOADREG. */
7930 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
7932 /* REG or MEM to be copied and incremented. */
7933 rtx incloc
= XEXP (value
, 0);
7934 /* Nonzero if increment after copying. */
7935 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7941 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7943 /* No hard register is equivalent to this register after
7944 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7945 we could inc/dec that register as well (maybe even using it for
7946 the source), but I'm not sure it's worth worrying about. */
7948 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7950 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7951 inc_amount
= -inc_amount
;
7953 inc
= GEN_INT (inc_amount
);
7955 /* If this is post-increment, first copy the location to the reload reg. */
7956 if (post
&& real_in
!= reloadreg
)
7957 emit_insn (gen_move_insn (reloadreg
, real_in
));
7961 /* See if we can directly increment INCLOC. Use a method similar to
7962 that in gen_reload. */
7964 last
= get_last_insn ();
7965 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7966 gen_rtx_PLUS (GET_MODE (incloc
),
7969 code
= recog_memoized (add_insn
);
7972 extract_insn (add_insn
);
7973 if (constrain_operands (1))
7975 /* If this is a pre-increment and we have incremented the value
7976 where it lives, copy the incremented value to RELOADREG to
7977 be used as an address. */
7980 emit_insn (gen_move_insn (reloadreg
, incloc
));
7985 delete_insns_since (last
);
7988 /* If couldn't do the increment directly, must increment in RELOADREG.
7989 The way we do this depends on whether this is pre- or post-increment.
7990 For pre-increment, copy INCLOC to the reload register, increment it
7991 there, then save back. */
7995 if (in
!= reloadreg
)
7996 emit_insn (gen_move_insn (reloadreg
, real_in
));
7997 emit_insn (gen_add2_insn (reloadreg
, inc
));
7998 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8003 Because this might be a jump insn or a compare, and because RELOADREG
8004 may not be available after the insn in an input reload, we must do
8005 the incrementation before the insn being reloaded for.
8007 We have already copied IN to RELOADREG. Increment the copy in
8008 RELOADREG, save that back, then decrement RELOADREG so it has
8009 the original value. */
8011 emit_insn (gen_add2_insn (reloadreg
, inc
));
8012 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8013 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8021 add_auto_inc_notes (rtx insn
, rtx x
)
8023 enum rtx_code code
= GET_CODE (x
);
8027 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8030 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
8034 /* Scan all the operand sub-expressions. */
8035 fmt
= GET_RTX_FORMAT (code
);
8036 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8039 add_auto_inc_notes (insn
, XEXP (x
, i
));
8040 else if (fmt
[i
] == 'E')
8041 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8042 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8047 /* Copy EH notes from an insn to its reloads. */
8049 copy_eh_notes (rtx insn
, rtx x
)
8051 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8054 for (; x
!= 0; x
= NEXT_INSN (x
))
8056 if (may_trap_p (PATTERN (x
)))
8058 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
8064 /* This is used by reload pass, that does emit some instructions after
8065 abnormal calls moving basic block end, but in fact it wants to emit
8066 them on the edge. Looks for abnormal call edges, find backward the
8067 proper call and fix the damage.
8069 Similar handle instructions throwing exceptions internally. */
8071 fixup_abnormal_edges (void)
8073 bool inserted
= false;
8081 /* Look for cases we are interested in - calls or instructions causing
8083 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8085 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8087 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8088 == (EDGE_ABNORMAL
| EDGE_EH
))
8091 if (e
&& !CALL_P (BB_END (bb
))
8092 && !can_throw_internal (BB_END (bb
)))
8094 rtx insn
= BB_END (bb
), stop
= NEXT_INSN (BB_END (bb
));
8096 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8097 if (e
->flags
& EDGE_FALLTHRU
)
8099 /* Get past the new insns generated. Allow notes, as the insns may
8100 be already deleted. */
8101 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8102 && !can_throw_internal (insn
)
8103 && insn
!= BB_HEAD (bb
))
8104 insn
= PREV_INSN (insn
);
8105 gcc_assert (CALL_P (insn
) || can_throw_internal (insn
));
8108 insn
= NEXT_INSN (insn
);
8109 while (insn
&& insn
!= stop
)
8111 next
= NEXT_INSN (insn
);
8116 /* Sometimes there's still the return value USE.
8117 If it's placed after a trapping call (i.e. that
8118 call is the last insn anyway), we have no fallthru
8119 edge. Simply delete this use and don't try to insert
8120 on the non-existent edge. */
8121 if (GET_CODE (PATTERN (insn
)) != USE
)
8123 /* We're not deleting it, we're moving it. */
8124 INSN_DELETED_P (insn
) = 0;
8125 PREV_INSN (insn
) = NULL_RTX
;
8126 NEXT_INSN (insn
) = NULL_RTX
;
8128 insert_insn_on_edge (insn
, e
);
8135 /* We've possibly turned single trapping insn into multiple ones. */
8136 if (flag_non_call_exceptions
)
8139 blocks
= sbitmap_alloc (last_basic_block
);
8140 sbitmap_ones (blocks
);
8141 find_many_sub_basic_blocks (blocks
);
8144 commit_edge_insertions ();