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2018-11-09 Richard Biener <rguenther@suse.de>
[official-gcc.git] / gcc / config / arc / arc.h
blob58d66d74ebcc311074dab5bbd09dfd6cd4492dbe
1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #ifndef GCC_ARC_H
21 #define GCC_ARC_H
22
23 #include <stdbool.h>
24
25 /* Things to do:
26
27 - incscc, decscc?
28
29 */
30
31 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0)
32 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1)
33 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2)
34 #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3)
35
36 #ifndef TARGET_CPU_DEFAULT
37 #define TARGET_CPU_DEFAULT PROCESSOR_arc700
38 #endif
39
40 /* Check if this symbol has a long_call attribute in its declaration */
41 #define SYMBOL_REF_LONG_CALL_P(X) \
42 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
43
44 /* Check if this symbol has a medium_call attribute in its declaration */
45 #define SYMBOL_REF_MEDIUM_CALL_P(X) \
46 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0)
47
48 /* Check if this symbol has a short_call attribute in its declaration */
49 #define SYMBOL_REF_SHORT_CALL_P(X) \
50 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0)
51
52 /* Names to predefine in the preprocessor for this target machine. */
53 #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile)
54
55 /* Macros enabled by specific command line option. FIXME: to be
56 deprecatd. */
57 #define CPP_SPEC "\
58 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \
59 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \
60 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \
61 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \
62 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \
63 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \
64 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \
65 %(subtarget_cpp_spec)"
66
67 #undef CC1_SPEC
68 #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \
69 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
70 %{G*} \
71 "
72 extern const char *arc_cpu_to_as (int argc, const char **argv);
73
74 #define EXTRA_SPEC_FUNCTIONS \
75 { "cpu_to_as", arc_cpu_to_as },
76
77 /* This macro defines names of additional specifications to put in the specs
78 that can be used in various specifications like CC1_SPEC. Its definition
79 is an initializer with a subgrouping for each command option.
80
81 Each subgrouping contains a string constant, that defines the
82 specification name, and a string constant that used by the GCC driver
83 program.
84
85 Do not define this macro if it does not need to do anything. */
86 #define EXTRA_SPECS \
87 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
88 SUBTARGET_EXTRA_SPECS
89
90 #ifndef SUBTARGET_EXTRA_SPECS
91 #define SUBTARGET_EXTRA_SPECS
92 #endif
93
94 #ifndef SUBTARGET_CPP_SPEC
95 #define SUBTARGET_CPP_SPEC ""
96 #endif
97
98 #undef ASM_SPEC
99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \
100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}"
101
102 #define OPTION_DEFAULT_SPECS \
103 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" }
104
105 #ifndef DRIVER_ENDIAN_SELF_SPECS
106 #define DRIVER_ENDIAN_SELF_SPECS ""
107 #endif
108
109 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \
110 "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \
111 "%{mARC601: -mcpu=arc601 %<mARC601}" \
112 "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \
113 "%{mEA: -mea %<mEA}"
114
115 /* Run-time compilation parameters selecting different hardware subsets. */
116
117 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
118
119 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
120 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \
121 || TARGET_FP_DP_AX)
122
123 #define SUBTARGET_SWITCHES
124
125 /* Instruction set characteristics.
126 These are internal macros, set by the appropriate -m option. */
127
128 /* Non-zero means the cpu supports norm instruction. This flag is set by
129 default for A7, and only for pre A7 cores when -mnorm is given. */
130 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS)
131 /* Indicate if an optimized floating point emulation library is available. */
132 #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK)
133
134 /* Non-zero means the cpu supports swap instruction. This flag is set by
135 default for A7, and only for pre A7 cores when -mswap is given. */
136 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET)
137
138 /* Provide some macros for size / scheduling features of the ARC700, so
139 that we can pick & choose features if we get a new cpu family member. */
140
141 /* Should we try to unalign likely taken branches without a delay slot. */
142 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size)
143
144 /* Should we add padding before a return insn to avoid mispredict? */
145 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size)
146
147 /* For an anulled-true delay slot insn for a delayed branch, should we only
148 use conditional execution? */
149 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2)
150
151 #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \
152 == BASE_ARCH_6xx) \
153 && (TARGET_BARREL_SHIFTER))
154 #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \
155 == BASE_ARCH_6xx) \
156 && (!TARGET_BARREL_SHIFTER))
157 #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \
158 == BASE_ARCH_700)
159 /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400
160 TARGET_ARC700 is true, and TARGET_NPS400 is true. */
161 #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \
162 == BASE_ARCH_700) \
163 && (arc_selected_cpu->processor \
164 == PROCESSOR_nps400))
165 #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em)
166 #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs)
167 #define TARGET_V2 (TARGET_EM || TARGET_HS)
168
169 #ifndef UNALIGNED_ACCESS_DEFAULT
170 #define UNALIGNED_ACCESS_DEFAULT 0
171 #endif
172
173 #ifndef TARGET_NPS_BITOPS_DEFAULT
174 #define TARGET_NPS_BITOPS_DEFAULT 0
175 #endif
176
177 #ifndef TARGET_NPS_CMEM_DEFAULT
178 #define TARGET_NPS_CMEM_DEFAULT 0
179 #endif
180
181 /* Enable the RRQ instruction alternatives. */
182
183 #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS
184
185 /* Target machine storage layout. */
186
187 /* We want zero_extract to mean the same
188 no matter what the byte endianness is. */
189 #define BITS_BIG_ENDIAN 0
190
191 /* Define this if most significant byte of a word is the lowest numbered. */
192 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
193
194 /* Define this if most significant word of a multiword number is the lowest
195 numbered. */
196 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
197
198 /* Width in bits of a "word", which is the contents of a machine register.
199 Note that this is not necessarily the width of data type `int';
200 if using 16-bit ints on a 68000, this would still be 32.
201 But on a machine with 16-bit registers, this would be 16. */
202 #define BITS_PER_WORD 32
203
204 /* Width of a word, in units (bytes). */
205 #define UNITS_PER_WORD 4
206
207 /* Define this macro if it is advisable to hold scalars in registers
208 in a wider mode than that declared by the program. In such cases,
209 the value is constrained to be within the bounds of the declared
210 type, but kept valid in the wider mode. The signedness of the
211 extension may differ from that of the type. */
212 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
213 if (GET_MODE_CLASS (MODE) == MODE_INT \
214 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
215 { \
216 (MODE) = SImode; \
217 }
218
219 /* Width in bits of a pointer.
220 See also the macro `Pmode' defined below. */
221 #define POINTER_SIZE 32
222
223 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
224 #define PARM_BOUNDARY 32
225
226 /* Boundary (in *bits*) on which stack pointer should be aligned. */
227 /* TOCHECK: Changed from 64 to 32 */
228 #define STACK_BOUNDARY 32
229
230 /* ALIGN FRAMES on word boundaries. */
231 #define ARC_STACK_ALIGN(LOC) \
232 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT)
233
234 /* Allocation boundary (in *bits*) for the code of a function. */
235 #define FUNCTION_BOUNDARY 32
236
237 /* Alignment of field after `int : 0' in a structure. */
238 #define EMPTY_FIELD_BOUNDARY 32
239
240 /* Every structure's size must be a multiple of this. */
241 #define STRUCTURE_SIZE_BOUNDARY 8
242
243 /* A bitfield declared as `int' forces `int' alignment for the struct. */
244 #define PCC_BITFIELD_TYPE_MATTERS 1
245
246 /* An expression for the alignment of a structure field FIELD if the
247 alignment computed in the usual way (including applying of
248 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the
249 alignment) is COMPUTED. It overrides alignment only if the field
250 alignment has not been set by the `__attribute__ ((aligned (N)))'
251 construct.
252 */
253
254 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
255 (TYPE_MODE (strip_array_types (TYPE)) == DFmode \
256 ? MIN ((COMPUTED), 32) : (COMPUTED))
257
258
259
260 /* No data type wants to be aligned rounder than this. */
261 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
262 ever added it's not clear whether they'll need such alignment or not. For
263 now we assume they will. We can always relax it if necessary but the
264 reverse isn't true. */
265 /* TOCHECK: Changed from 64 to 32 */
266 #define BIGGEST_ALIGNMENT 32
267
268 /* The best alignment to use in cases where we have a choice. */
269 #define FASTEST_ALIGNMENT 32
270
271 /* Make arrays of chars word-aligned for the same reasons. */
272 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
273 (TREE_CODE (TYPE) == ARRAY_TYPE \
274 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
275 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
276
277 #define DATA_ALIGNMENT(TYPE, ALIGN) \
278 (TREE_CODE (TYPE) == ARRAY_TYPE \
279 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
280 && arc_size_opt_level < 3 \
281 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
282
283 /* Set this nonzero if move instructions will actually fail to work
284 when given unaligned data. */
285 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
286 won't croak when given an unaligned address, but the insn will still fail
287 to produce the correct result. */
288 #define STRICT_ALIGNMENT (!unaligned_access && !TARGET_HS)
289
290 /* Layout of source language data types. */
291
292 #define SHORT_TYPE_SIZE 16
293 #define INT_TYPE_SIZE 32
294 #define LONG_TYPE_SIZE 32
295 #define LONG_LONG_TYPE_SIZE 64
296 #define FLOAT_TYPE_SIZE 32
297 #define DOUBLE_TYPE_SIZE 64
298 #define LONG_DOUBLE_TYPE_SIZE 64
299
300 /* Define this as 1 if `char' should by default be signed; else as 0. */
301 #define DEFAULT_SIGNED_CHAR 0
302
303 #undef SIZE_TYPE
304 #define SIZE_TYPE "unsigned int"
305
306 #undef PTRDIFF_TYPE
307 #define PTRDIFF_TYPE "int"
308
309 #undef WCHAR_TYPE
310 #define WCHAR_TYPE "int"
311
312 #undef WCHAR_TYPE_SIZE
313 #define WCHAR_TYPE_SIZE 32
314
315 #define PROGRAM_COUNTER_REGNO 63
316
317 /* Standard register usage. */
318
319 /* Number of actual hardware registers.
320 The hardware registers are assigned numbers for the compiler
321 from 0 to just below FIRST_PSEUDO_REGISTER.
322 All registers that the compiler knows about must be given numbers,
323 even those that are not normally considered general registers.
324
325 Registers 61, 62, and 63 are not really registers and we needn't treat
326 them as such. We still need a register for the condition code and
327 argument pointer. */
328
329 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs
330 r144, r145 = lp_start, lp_end
331 and therefore the pseudo registers start from r146. */
332 #define FIRST_PSEUDO_REGISTER 146
333
334 /* 1 for registers that have pervasive standard uses
335 and are not available for the register allocator.
336
337 0-28 - general purpose registers
338 29 - ilink1 (interrupt link register)
339 30 - ilink2 (interrupt link register)
340 31 - blink (branch link register)
341 32-59 - reserved for extensions
342 60 - LP_COUNT
343 61 - condition code
344 62 - argument pointer
345 63 - program counter
346
347 FWIW, this is how the 61-63 encodings are used by the hardware:
348 61 - reserved
349 62 - long immediate data indicator
350 63 - PCL (program counter aligned to 32 bit, read-only)
351
352 The general purpose registers are further broken down into:
353
354 0-7 - arguments/results
355 8-12 - call used (r11 - static chain pointer)
356 13-25 - call saved
357 26 - global pointer
358 27 - frame pointer
359 28 - stack pointer
360 29 - ilink1
361 30 - ilink2
362 31 - return address register
363
364 By default, the extension registers are not available. */
365 /* Present implementations only have VR0-VR23 only. */
366 /* ??? FIXME: r27 and r31 should not be fixed registers. */
367 #define FIXED_REGISTERS \
368 { 0, 0, 0, 0, 0, 0, 0, 0, \
369 0, 0, 0, 0, 0, 0, 0, 0, \
370 0, 0, 0, 0, 0, 0, 0, 0, \
371 0, 0, 1, 1, 1, 1, 1, 1, \
372 \
373 1, 1, 1, 1, 1, 1, 1, 1, \
374 0, 0, 0, 0, 1, 1, 1, 1, \
375 1, 1, 1, 1, 1, 1, 1, 1, \
376 1, 1, 1, 1, 0, 1, 1, 1, \
377 \
378 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, \
381 1, 1, 1, 1, 1, 1, 1, 1, \
382 \
383 1, 1, 1, 1, 1, 1, 1, 1, \
384 1, 1, 1, 1, 1, 1, 1, 1, \
385 1, 1, 1, 1, 1, 1, 1, 1, \
386 1, 1, 1, 1, 1, 1, 1, 1, \
387 \
388 0, 0, 0, 0, 0, 0, 0, 0, \
389 0, 0, 0, 0, 0, 0, 0, 0, \
390 1, 1}
391
392 /* 1 for registers not available across function calls.
393 These must include the FIXED_REGISTERS and also any
394 registers that can be used without being saved.
395 The latter must include the registers where values are returned
396 and the register where structure-value addresses are passed.
397 Aside from that, you can include as many other registers as you like. */
398 #define CALL_USED_REGISTERS \
399 { \
400 1, 1, 1, 1, 1, 1, 1, 1, \
401 1, 1, 1, 1, 1, 0, 0, 0, \
402 0, 0, 0, 0, 0, 0, 0, 0, \
403 0, 0, 1, 1, 1, 1, 1, 1, \
404 \
405 1, 1, 1, 1, 1, 1, 1, 1, \
406 1, 1, 1, 1, 1, 1, 1, 1, \
407 1, 1, 1, 1, 1, 1, 1, 1, \
408 1, 1, 1, 1, 1, 1, 1, 1, \
409 \
410 0, 0, 0, 0, 0, 0, 0, 0, \
411 0, 0, 0, 0, 0, 0, 0, 0, \
412 0, 0, 0, 0, 0, 0, 0, 0, \
413 1, 1, 1, 1, 1, 1, 1, 1, \
414 \
415 1, 1, 1, 1, 1, 1, 1, 1, \
416 1, 1, 1, 1, 1, 1, 1, 1, \
417 1, 1, 1, 1, 1, 1, 1, 1, \
418 1, 1, 1, 1, 1, 1, 1, 1, \
419 \
420 0, 0, 0, 0, 0, 0, 0, 0, \
421 0, 0, 0, 0, 0, 0, 0, 0, \
422 1, 1}
423
424 /* If defined, an initializer for a vector of integers, containing the
425 numbers of hard registers in the order in which GCC should
426 prefer to use them (from most preferred to least). */
427 #define REG_ALLOC_ORDER \
428 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
429 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
430 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
431 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
432 27, 28, 29, 30, 31, 63}
433
434 /* Internal macros to classify a register number as to whether it's a
435 general purpose register for compact insns (r0-r3,r12-r15), or
436 stack pointer (r28). */
437
438 #define COMPACT_GP_REG_P(REGNO) \
439 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15))
440 #define SP_REG_P(REGNO) ((REGNO) == 28)
441
442
443
444 /* Register classes and constants. */
445
446 /* Define the classes of registers for register constraints in the
447 machine description. Also define ranges of constants.
448
449 One of the classes must always be named ALL_REGS and include all hard regs.
450 If there is more than one class, another class must be named NO_REGS
451 and contain no registers.
452
453 The name GENERAL_REGS must be the name of a class (or an alias for
454 another name such as ALL_REGS). This is the class of registers
455 that is allowed by "g" or "r" in a register constraint.
456 Also, registers outside this class are allocated only when
457 instructions express preferences for them.
458
459 The classes must be numbered in nondecreasing order; that is,
460 a larger-numbered class must never be contained completely
461 in a smaller-numbered class.
462
463 For any two classes, it is very desirable that there be another
464 class that represents their union.
465
466 It is important that any condition codes have class NO_REGS.
467 See `register_operand'. */
468
469 enum reg_class
470 {
471 NO_REGS,
472 R0_REGS, /* 'x' */
473 GP_REG, /* 'Rgp' */
474 FP_REG, /* 'f' */
475 SP_REGS, /* 'b' */
476 LPCOUNT_REG, /* 'l' */
477 LINK_REGS, /* 'k' */
478 DOUBLE_REGS, /* D0, D1 */
479 SIMD_VR_REGS, /* VR00-VR63 */
480 SIMD_DMA_CONFIG_REGS, /* DI0-DI7,DO0-DO7 */
481 ARCOMPACT16_REGS, /* 'q' */
482 AC16_BASE_REGS, /* 'e' */
483 SIBCALL_REGS, /* "Rsc" */
484 GENERAL_REGS, /* 'r' */
485 MPY_WRITABLE_CORE_REGS, /* 'W' */
486 WRITABLE_CORE_REGS, /* 'w' */
487 CHEAP_CORE_REGS, /* 'c' */
488 ALL_CORE_REGS, /* 'Rac' */
489 R0R3_CD_REGS, /* 'Rcd' */
490 R0R1_CD_REGS, /* 'Rsd' */
491 AC16_H_REGS, /* 'h' */
492 ALL_REGS,
493 LIM_REG_CLASSES
494 };
495
496 #define N_REG_CLASSES (int) LIM_REG_CLASSES
497
498 /* Give names of register classes as strings for dump file. */
499 #define REG_CLASS_NAMES \
500 { \
501 "NO_REGS", \
502 "R0_REGS", \
503 "GP_REG", \
504 "FP_REG", \
505 "SP_REGS", \
506 "LPCOUNT_REG", \
507 "LINK_REGS", \
508 "DOUBLE_REGS", \
509 "SIMD_VR_REGS", \
510 "SIMD_DMA_CONFIG_REGS", \
511 "ARCOMPACT16_REGS", \
512 "AC16_BASE_REGS", \
513 "SIBCALL_REGS", \
514 "GENERAL_REGS", \
515 "MPY_WRITABLE_CORE_REGS", \
516 "WRITABLE_CORE_REGS", \
517 "CHEAP_CORE_REGS", \
518 "R0R3_CD_REGS", \
519 "R0R1_CD_REGS", \
520 "AC16_H_REGS", \
521 "ALL_CORE_REGS", \
522 "ALL_REGS" \
523 }
524
525 /* Define which registers fit in which classes.
526 This is an initializer for a vector of HARD_REG_SET
527 of length N_REG_CLASSES. */
528
529 #define REG_CLASS_CONTENTS \
530 { \
531 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* No Registers */ \
532 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x', r0 register , r0 */ \
533 {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \
534 {0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'f', Frame Pointer, r27 */ \
535 {0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'b', Stack Pointer, r28 */ \
536 {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \
537 {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \
538 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D', D1, D2 Registers */ \
539 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'V', VR00-VR63 Registers */ \
540 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \
541 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q', r0-r3, r12-r15 */ \
542 {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'e', r0-r3, r12-r15, sp */ \
543 {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* "Rsc", r0-r12 */ \
544 {0x9fffffff, 0x80000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \
545 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'W', r0-r31 */ \
546 /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \
547 registers are fixed, it does not affect the literal meaning of the \
548 constraints, but it makes it a superset of GENERAL_REGS, thus \
549 enabling some operations that would otherwise not be possible. */ \
550 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \
551 {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \
552 {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \
553 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd', r0-r3 */ \
554 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd', r0-r1 */ \
555 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h', r0-28, r30 */ \
556 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \
557 }
558
559 /* Local macros to mark the first and last regs of different classes. */
560 #define ARC_FIRST_SIMD_VR_REG 64
561 #define ARC_LAST_SIMD_VR_REG 127
562
563 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128
564 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128
565 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136
566 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143
567
568 /* ARCv2 double-register accumulator. */
569 #define ACC_REG_FIRST 58
570 #define ACC_REG_LAST 59
571 #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST)
572 #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1)
573
574 /* The same information, inverted:
575 Return the class number of the smallest class containing
576 reg number REGNO. This could be a conditional expression
577 or could index an array. */
578
579 extern enum reg_class arc_regno_reg_class[];
580
581 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO])
582
583 /* The class value for valid index registers. An index register is
584 one used in an address where its value is either multiplied by
585 a scale factor or added to another register (as well as added to a
586 displacement). */
587
588 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
589
590 /* The class value for valid base registers. A base register is one used in
591 an address which is the register value plus a displacement. */
592
593 #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS)
594
595 /* These assume that REGNO is a hard or pseudo reg number.
596 They give nonzero only if REGNO is a hard reg of the suitable class
597 or a pseudo reg currently allocated to a suitable hard reg.
598 Since they use reg_renumber, they are safe only once reg_renumber
599 has been allocated, which happens in local-alloc.c. */
600 #define REGNO_OK_FOR_BASE_P(REGNO) \
601 ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \
602 || ((unsigned) reg_renumber[REGNO] < 29) \
603 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
604 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \
605 || ((REGNO) == 30 && fixed_regs[REGNO] == 0))
606
607 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
608
609 /* Given an rtx X being reloaded into a reg required to be
610 in class CLASS, return the class of reg to actually use.
611 In general this is just CLASS; but on some machines
612 in some cases it is preferable to use a more restrictive class. */
613
614 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
615 arc_preferred_reload_class((X), (CLASS))
616
617 extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class);
618
619 /* Return the maximum number of consecutive registers
620 needed to represent mode MODE in a register of class CLASS. */
621
622 #define CLASS_MAX_NREGS(CLASS, MODE) \
623 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \
624 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
625
626 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
627 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \
628 ((unsigned) (((X) >> (SHIFT)) + 0x100) \
629 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT)))
630 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000)
631 #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000)
632 #define LARGE_INT(X) \
633 (((X) < 0) \
634 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
635 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
636 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8)
637 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20)
638 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40)
639 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80)
640 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100)
641 #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800)
642 #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000)
643 #define IS_ONE(X) ((X) == 1)
644 #define IS_ZERO(X) ((X) == 0)
645
646 /* Stack layout and stack pointer usage. */
647
648 /* Define this macro if pushing a word onto the stack moves the stack
649 pointer to a smaller address. */
650 #define STACK_GROWS_DOWNWARD 1
651
652 /* Define this if the nominal address of the stack frame
653 is at the high-address end of the local variables;
654 that is, each additional local variable allocated
655 goes at a more negative offset in the frame. */
656 #define FRAME_GROWS_DOWNWARD 1
657
658 /* Offset from the stack pointer register to the first location at which
659 outgoing arguments are placed. */
660 #define STACK_POINTER_OFFSET (0)
661
662 /* Offset of first parameter from the argument pointer register value. */
663 #define FIRST_PARM_OFFSET(FNDECL) (0)
664
665 /* A C expression whose value is RTL representing the address in a
666 stack frame where the pointer to the caller's frame is stored.
667 Assume that FRAMEADDR is an RTL expression for the address of the
668 stack frame itself.
669
670 If you don't define this macro, the default is to return the value
671 of FRAMEADDR--that is, the stack frame address is also the address
672 of the stack word that points to the previous frame. */
673 /* ??? unfinished */
674 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
675
676 /* A C expression whose value is RTL representing the value of the
677 return address for the frame COUNT steps up from the current frame.
678 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
679 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
680 is defined. */
681 /* The current return address is in r31. The return address of anything
682 farther back is at [%fp,4]. */
683
684 #define RETURN_ADDR_RTX(COUNT, FRAME) \
685 arc_return_addr_rtx(COUNT,FRAME)
686
687 /* Register to use for pushing function arguments. */
688 #define STACK_POINTER_REGNUM 28
689
690 /* Base register for access to local variables of the function. */
691 #define FRAME_POINTER_REGNUM 27
692
693 /* Base register for access to arguments of the function. This register
694 will be eliminated into either fp or sp. */
695 #define ARG_POINTER_REGNUM 62
696
697 #define RETURN_ADDR_REGNUM 31
698
699 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */
700 /* Register in which static-chain is passed to a function. This must
701 not be a register used by the prologue. */
702 #define STATIC_CHAIN_REGNUM 11
703
704 /* Function argument passing. */
705
706 /* If defined, the maximum amount of space required for outgoing
707 arguments will be computed and placed into the variable
708 `crtl->outgoing_args_size'. No space will be pushed
709 onto the stack for each call; instead, the function prologue should
710 increase the stack frame size by this amount. */
711 #define ACCUMULATE_OUTGOING_ARGS 1
712
713 /* Define a data type for recording info about an argument list
714 during the scan of that argument list. This data type should
715 hold all necessary information about the function itself
716 and about the args processed so far, enough to enable macros
717 such as FUNCTION_ARG to determine where the next arg should go. */
718 #define CUMULATIVE_ARGS int
719
720 /* Initialize a variable CUM of type CUMULATIVE_ARGS
721 for a call to a function whose data type is FNTYPE.
722 For a library call, FNTYPE is 0. */
723 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
724 ((CUM) = 0)
725
726 /* The number of registers used for parameter passing. Local to this file. */
727 #define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8)
728
729 /* 1 if N is a possible register number for function argument passing. */
730 #define FUNCTION_ARG_REGNO_P(N) \
731 ((unsigned) (N) < MAX_ARC_PARM_REGS)
732
733 /* The ROUND_ADVANCE* macros are local to this file. */
734 /* Round SIZE up to a word boundary. */
735 #define ROUND_ADVANCE(SIZE) \
736 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
737
738 /* Round arg MODE/TYPE up to the next word boundary. */
739 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
740 ((MODE) == BLKmode \
741 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
742 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
743
744 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY
745 /* Round CUM up to the necessary point for argument MODE/TYPE. */
746 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT.
747 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */
748 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
749 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\
750 + 1)
751
752 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
753 a reg. This includes arguments that have to be passed by reference as the
754 pointer to them is passed in a reg if one is available (and that is what
755 we're given).
756 When passing arguments NAMED is always 1. When receiving arguments NAMED
757 is 1 for each argument except the last in a stdarg/varargs function. In
758 a stdarg function we want to treat the last named arg as named. In a
759 varargs function we want to treat the last named arg (which is
760 `__builtin_va_alist') as unnamed.
761 This macro is only used in this file. */
762 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
763 ((CUM) < MAX_ARC_PARM_REGS)
764
765
766 /* Function results. */
767
768 /* Define how to find the value returned by a library function
769 assuming the value has mode MODE. */
770 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
771
772 /* 1 if N is a possible register number for a function value
773 as seen by the caller. */
774 /* ??? What about r1 in DI/DF values. */
775 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
776
777 /* Tell GCC to use RETURN_IN_MEMORY. */
778 #define DEFAULT_PCC_STRUCT_RETURN 0
779
780 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
781 the stack pointer does not matter. The value is tested only in
782 functions that have frame pointers.
783 No definition is equivalent to always zero. */
784 #define EXIT_IGNORE_STACK 0
785
786 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO))
787
788 #define EH_USES(REGNO) arc_eh_uses((REGNO))
789
790 /* Definitions for register eliminations.
791
792 This is an array of structures. Each structure initializes one pair
793 of eliminable registers. The "from" register number is given first,
794 followed by "to". Eliminations of the same "from" register are listed
795 in order of preference.
796
797 We have two registers that can be eliminated on the ARC. First, the
798 argument pointer register can always be eliminated in favor of the stack
799 pointer register or frame pointer register. Secondly, the frame pointer
800 register can often be eliminated in favor of the stack pointer register.
801 */
802
803 #define ELIMINABLE_REGS \
804 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
805 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
806 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
807
808 /* Define the offset between two registers, one to be eliminated, and the other
809 its replacement, at the start of a routine. */
810 extern int arc_initial_elimination_offset(int from, int to);
811 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
812 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO))
813
814 /* Output assembler code to FILE to increment profiler label # LABELNO
815 for profiling a function entry. */
816 #define FUNCTION_PROFILER(FILE, LABELNO) \
817 do { \
818 if (flag_pic) \
819 fprintf (FILE, "\tbl\t__mcount@plt\n"); \
820 else \
821 fprintf (FILE, "\tbl\t__mcount\n"); \
822 } while (0)
823
824 #define NO_PROFILE_COUNTERS 1
825
826 /* Trampolines. */
827
828 /* Length in units of the trampoline for entering a nested function. */
829 #define TRAMPOLINE_SIZE 16
830
831 /* Alignment required for a trampoline in bits . */
832 /* For actual data alignment we just need 32, no more than the stack;
833 however, to reduce cache coherency issues, we want to make sure that
834 trampoline instructions always appear the same in any given cache line. */
835 #define TRAMPOLINE_ALIGNMENT 256
836
837 /* Library calls. */
838
839 /* Addressing modes, and classification of registers for them. */
840
841 /* Maximum number of registers that can appear in a valid memory address. */
842 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
843 #define MAX_REGS_PER_ADDRESS 1
844
845 /* We have pre inc/dec (load/store with update). */
846 #define HAVE_PRE_INCREMENT 1
847 #define HAVE_PRE_DECREMENT 1
848 #define HAVE_POST_INCREMENT 1
849 #define HAVE_POST_DECREMENT 1
850 #define HAVE_PRE_MODIFY_DISP 1
851 #define HAVE_POST_MODIFY_DISP 1
852 #define HAVE_PRE_MODIFY_REG 1
853 #define HAVE_POST_MODIFY_REG 1
854 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires
855 a special predicate for the memory operand of stores, like for the SH. */
856
857 /* Recognize any constant value that is a valid address. */
858 #define CONSTANT_ADDRESS_P(X) \
859 (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \
860 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
861 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
862
863 /* Is the argument a const_int rtx, containing an exact power of 2 */
864 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
865 #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1)))
866
867 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
868 and check its validity for a certain class.
869 We have two alternate definitions for each of them.
870 The *_NONSTRICT definition accepts all pseudo regs; the other rejects
871 them unless they have been allocated suitable hard regs.
872
873 Most source files want to accept pseudo regs in the hope that
874 they will get allocated to the class that the insn wants them to be in.
875 Source files for reload pass need to be strict.
876 After reload, it makes no difference, since pseudo regs have
877 been eliminated by then. */
878
879 /* Nonzero if X is a hard reg that can be used as an index
880 or if it is a pseudo reg. */
881 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
882 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
883 || REGNO_OK_FOR_BASE_P (REGNO (X)))
884
885 /* Nonzero if X is a hard reg that can be used as a base reg
886 or if it is a pseudo reg. */
887 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \
888 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \
889 || REGNO_OK_FOR_BASE_P (REGNO (X)))
890
891 /* Nonzero if X is a hard reg that can be used as an index. */
892 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
893 /* Nonzero if X is a hard reg that can be used as a base reg. */
894 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
895
896 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
897 that is a valid memory address for an instruction.
898 The MODE argument is the machine mode for the MEM expression
899 that wants to use this address. */
900 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
901 but the `st' insn only allows [reg],[reg+shimm],[limm].
902 The only thing we can do is only allow the most strict case `st' and hope
903 other parts optimize out the restrictions for `ld'. */
904
905 #define RTX_OK_FOR_BASE_P(X, STRICT) \
906 (REG_P (X) \
907 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X)))
908
909 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
910 (REG_P (X) \
911 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X)))
912
913 /* A C compound statement that attempts to replace X, which is an address
914 that needs reloading, with a valid memory address for an operand of
915 mode MODE. WIN is a C statement label elsewhere in the code.
916
917 We try to get a normal form
918 of the address. That will allow inheritance of the address reloads. */
919
920 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
921 do { \
922 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
923 goto WIN; \
924 } while (0)
925
926 /* Reading lp_count for anything but the lp instruction is very slow on the
927 ARC700. */
928 #define DONT_REALLOC(REGNO,MODE) \
929 (TARGET_ARC700 && (REGNO) == 60)
930
931
932 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
933 return the mode to be used for the comparison. */
934 /*extern machine_mode arc_select_cc_mode ();*/
935 #define SELECT_CC_MODE(OP, X, Y) \
936 arc_select_cc_mode (OP, X, Y)
937
938 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
939 floating point inequality comparison. */
940 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
941
942 /* Costs. */
943
944 /* Compute extra cost of moving data between one register class
945 and another. */
946 #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
947 arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
948
949 /* Compute the cost of moving data between registers and memory. */
950 /* Memory is 3 times as expensive as registers.
951 ??? Is that the right way to look at it? */
952 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
953 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
954
955 /* The cost of a branch insn. */
956 /* ??? What's the right value here? Branches are certainly more
957 expensive than reg->reg moves. */
958 #define BRANCH_COST(speed_p, predictable_p) 2
959
960 /* Scc sets the destination to 1 and then conditionally zeroes it.
961 Best case, ORed SCCs can be made into clear - condset - condset.
962 But it could also end up as five insns. So say it costs four on
963 average.
964 These extra instructions - and the second comparison - will also be
965 an extra cost if the first comparison would have been decisive.
966 So get an average saving, with a probability of the first branch
967 beging decisive of p0, we want:
968 p0 * (branch_cost - 4) > (1 - p0) * 5
969 ??? We don't get to see that probability to evaluate, so we can
970 only wildly guess that it might be 50%.
971 ??? The compiler also lacks the notion of branch predictability. */
972 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
973 (BRANCH_COST (optimize_function_for_speed_p (cfun), \
974 false) > 9)
975
976 /* Nonzero if access to memory by bytes is slow and undesirable.
977 For RISC chips, it means that access to memory by bytes is no
978 better than access by words when possible, so grab a whole word
979 and maybe make use of that. */
980 #define SLOW_BYTE_ACCESS 0
981
982 /* Define this macro if it is as good or better to call a constant
983 function address than to call an address kept in a register. */
984 /* On the ARC, calling through registers is slow. */
985 #define NO_FUNCTION_CSE 1
986
987 /* Section selection. */
988 /* WARNING: These section names also appear in dwarfout.c. */
989
990 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
991 #define DATA_SECTION_ASM_OP "\t.section\t.data"
992
993 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
994 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata"
995 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
996
997 /* Expression whose value is a string, including spacing, containing the
998 assembler operation to identify the following data as initialization/termination
999 code. If not defined, GCC will assume such a section does not exist. */
1000 #define INIT_SECTION_ASM_OP "\t.section\t.init"
1001 #define FINI_SECTION_ASM_OP "\t.section\t.fini"
1002
1003 /* Define this macro if jump tables (for tablejump insns) should be
1004 output in the text section, along with the assembler instructions.
1005 Otherwise, the readonly data section is used.
1006 This macro is irrelevant if there is no separate readonly data section. */
1007 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE)
1008
1009 /* For DWARF. Marginally different than default so output is "prettier"
1010 (and consistent with above). */
1011 #define PUSHSECTION_FORMAT "\t%s %s\n"
1012
1013 /* Tell crtstuff.c we're using ELF. */
1014 #define OBJECT_FORMAT_ELF
1015
1016 /* PIC */
1017
1018 /* The register number of the register used to address a table of static
1019 data addresses in memory. In some cases this register is defined by a
1020 processor's ``application binary interface'' (ABI). When this macro
1021 is defined, RTL is generated for this register once, as with the stack
1022 pointer and frame pointer registers. If this macro is not defined, it
1023 is up to the machine-dependent files to allocate such a register (if
1024 necessary). */
1025 #define PIC_OFFSET_TABLE_REGNUM 26
1026
1027 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1028 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1029 is not defined. */
1030 /* This register is call-saved on the ARC. */
1031 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1032
1033 /* A C expression that is nonzero if X is a legitimate immediate
1034 operand on the target machine when generating position independent code.
1035 You can assume that X satisfies CONSTANT_P, so you need not
1036 check this. You can also assume `flag_pic' is true, so you need not
1037 check it either. You need not define this macro if all constants
1038 (including SYMBOL_REF) can be immediate operands when generating
1039 position independent code. */
1040 #define LEGITIMATE_PIC_OPERAND_P(X) \
1041 (!arc_raw_symbolic_reference_mentioned_p ((X), true))
1042
1043 /* PIC and small data don't mix on ARC because they use the same register. */
1044 #define SDATA_BASE_REGNUM 26
1045
1046 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1047 (flag_pic \
1048 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1049 : DW_EH_PE_absptr)
1050
1051 /* Control the assembler format that we output. */
1052
1053 /* A C string constant describing how to begin a comment in the target
1054 assembler language. The compiler assumes that the comment will
1055 end at the end of the line. */
1056 /* Gas needs this to be "#" in order to recognize line directives. */
1057 #define ASM_COMMENT_START "#"
1058
1059 /* Output to assembler file text saying following lines
1060 may contain character constants, extra white space, comments, etc. */
1061 #undef ASM_APP_ON
1062 #define ASM_APP_ON ""
1063
1064 /* Output to assembler file text saying following lines
1065 no longer contain unusual constructs. */
1066 #undef ASM_APP_OFF
1067 #define ASM_APP_OFF ""
1068
1069 /* Globalizing directive for a label. */
1070 #define GLOBAL_ASM_OP "\t.global\t"
1071
1072 /* This is how to output an assembler line defining a `char' constant. */
1073 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1074 ( fprintf (FILE, "\t.byte\t"), \
1075 output_addr_const (FILE, (VALUE)), \
1076 fprintf (FILE, "\n"))
1077
1078 /* This is how to output an assembler line defining a `short' constant. */
1079 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1080 ( fprintf (FILE, "\t.hword\t"), \
1081 output_addr_const (FILE, (VALUE)), \
1082 fprintf (FILE, "\n"))
1083
1084 /* This is how to output an assembler line defining an `int' constant.
1085 We also handle symbol output here. Code addresses must be right shifted
1086 by 2 because that's how the jump instruction wants them. */
1087 #define ASM_OUTPUT_INT(FILE, VALUE) \
1088 do { \
1089 fprintf (FILE, "\t.word\t"); \
1090 if (GET_CODE (VALUE) == LABEL_REF) \
1091 { \
1092 fprintf (FILE, "%%st(@"); \
1093 output_addr_const (FILE, (VALUE)); \
1094 fprintf (FILE, ")"); \
1095 } \
1096 else \
1097 output_addr_const (FILE, (VALUE)); \
1098 fprintf (FILE, "\n"); \
1099 } while (0)
1100
1101 /* This is how to output an assembler line defining a `float' constant. */
1102 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
1103 { \
1104 long t; \
1105 char str[30]; \
1106 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1107 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1108 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \
1109 t, ASM_COMMENT_START, str); \
1110 }
1111
1112 /* This is how to output an assembler line defining a `double' constant. */
1113 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
1114 { \
1115 long t[2]; \
1116 char str[30]; \
1117 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1118 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1119 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
1120 t[0], ASM_COMMENT_START, str, t[1]); \
1121 }
1122
1123 /* This is how to output the definition of a user-level label named NAME,
1124 such as the label on a static function or variable NAME. */
1125 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1126 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1127
1128 #define ASM_NAME_P(NAME) ( NAME[0]=='*')
1129
1130 /* This is how to output a reference to a user-level label named NAME.
1131 `assemble_name' uses this. */
1132 /* We work around a dwarfout.c deficiency by watching for labels from it and
1133 not adding the '_' prefix. There is a comment in
1134 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */
1135 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \
1136 do { \
1137 const char *NAME; \
1138 NAME = (*targetm.strip_name_encoding)(NAME1); \
1139 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \
1140 fprintf (FILE, "%s", NAME); \
1141 else \
1142 { \
1143 if (!ASM_NAME_P (NAME1)) \
1144 fprintf (FILE, "%s", user_label_prefix); \
1145 fprintf (FILE, "%s", NAME); \
1146 } \
1147 } while (0)
1148
1149 /* This is how to output a reference to a symbol_ref / label_ref as
1150 (part of) an operand. To disambiguate from register names like
1151 a1 / a2 / status etc, symbols are preceded by '@'. */
1152 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
1153 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0))
1154 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \
1155 do \
1156 { \
1157 fputc ('@', file); \
1158 assemble_name ((FILE), (STR)); \
1159 } \
1160 while (0)
1161
1162 /* Store in OUTPUT a string (made with alloca) containing
1163 an assembler-name for a local static variable named NAME.
1164 LABELNO is an integer which is different for each call. */
1165 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1166 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1167 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1168
1169 /* The following macro defines the format used to output the second
1170 operand of the .type assembler directive. Different svr4 assemblers
1171 expect various different forms for this operand. The one given here
1172 is just a default. You may need to override it in your machine-
1173 specific tm.h file (depending upon the particulars of your assembler). */
1174
1175 #undef TYPE_OPERAND_FMT
1176 #define TYPE_OPERAND_FMT "@%s"
1177
1178 /* A C string containing the appropriate assembler directive to
1179 specify the size of a symbol, without any arguments. On systems
1180 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"';
1181 on other systems, the default is not to define this macro. */
1182 #undef SIZE_ASM_OP
1183 #define SIZE_ASM_OP "\t.size\t"
1184
1185 /* Assembler pseudo-op to equate one value with another. */
1186 /* ??? This is needed because dwarfout.c provides a default definition too
1187 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF
1188 that we use). */
1189 #ifdef SET_ASM_OP
1190 #undef SET_ASM_OP
1191 #endif
1192 #define SET_ASM_OP "\t.set\t"
1193
1194 extern char rname29[], rname30[];
1195 extern char rname56[], rname57[], rname58[], rname59[];
1196 /* How to refer to registers in assembler output.
1197 This sequence is indexed by compiler's hard-register-number (see above). */
1198 #define REGISTER_NAMES \
1199 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1200 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1201 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1202 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \
1203 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1204 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \
1205 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1206 rname56,rname57,rname58,rname59,"lp_count", "cc", "ap", "pcl", \
1207 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \
1208 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \
1209 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \
1210 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \
1211 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \
1212 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \
1213 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \
1214 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \
1215 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1216 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1217 "lp_start", "lp_end" \
1218 }
1219
1220 #define ADDITIONAL_REGISTER_NAMES \
1221 { \
1222 {"ilink", 29}, \
1223 {"r29", 29}, \
1224 {"r30", 30}, \
1225 {"r40", 40}, \
1226 {"r41", 41}, \
1227 {"r42", 42}, \
1228 {"r43", 43}, \
1229 {"r56", 56}, \
1230 {"r57", 57}, \
1231 {"r58", 58}, \
1232 {"r59", 59} \
1233 }
1234
1235 /* Entry to the insn conditionalizer. */
1236 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1237 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1238
1239 /* A C expression which evaluates to true if CODE is a valid
1240 punctuation character for use in the `PRINT_OPERAND' macro. */
1241 extern char arc_punct_chars[];
1242 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1243 arc_punct_chars[(unsigned char) (CHAR)]
1244
1245 /* Print operand X (an rtx) in assembler syntax to file FILE.
1246 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1247 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1248 #define PRINT_OPERAND(FILE, X, CODE) \
1249 arc_print_operand (FILE, X, CODE)
1250
1251 /* A C compound statement to output to stdio stream STREAM the
1252 assembler syntax for an instruction operand that is a memory
1253 reference whose address is ADDR. ADDR is an RTL expression.
1254
1255 On some machines, the syntax for a symbolic address depends on
1256 the section that the address refers to. On these machines,
1257 define the macro `ENCODE_SECTION_INFO' to store the information
1258 into the `symbol_ref', and then check for it here. */
1259 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1260 arc_print_operand_address (FILE, ADDR)
1261
1262 /* This is how to output an element of a case-vector that is absolute. */
1263 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1264 do { \
1265 char label[30]; \
1266 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1267 fprintf (FILE, "\t.word "); \
1268 assemble_name (FILE, label); \
1269 fprintf (FILE, "\n"); \
1270 } while (0)
1271
1272 /* This is how to output an element of a case-vector that is relative. */
1273 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1274 do { \
1275 char label[30]; \
1276 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1277 if (!TARGET_BI_BIH) \
1278 { \
1279 switch (GET_MODE (BODY)) \
1280 { \
1281 case E_QImode: fprintf (FILE, "\t.byte "); break; \
1282 case E_HImode: fprintf (FILE, "\t.hword "); break; \
1283 case E_SImode: fprintf (FILE, "\t.word "); break; \
1284 default: gcc_unreachable (); \
1285 } \
1286 assemble_name (FILE, label); \
1287 fprintf (FILE, "-"); \
1288 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1289 assemble_name (FILE, label); \
1290 fprintf (FILE, "\n"); \
1291 } \
1292 else \
1293 { \
1294 switch (GET_MODE (BODY)) \
1295 { \
1296 case E_SImode: fprintf (FILE, "\tb\t@"); break; \
1297 case E_HImode: \
1298 case E_QImode: fprintf (FILE, "\tb_s\t@"); break; \
1299 default: gcc_unreachable (); \
1300 } \
1301 assemble_name (FILE, label); \
1302 fprintf(FILE, "\n"); \
1303 } \
1304 } while (0)
1305
1306 /* Defined to also emit an .align in elfos.h. We don't want that. */
1307 #undef ASM_OUTPUT_CASE_LABEL
1308
1309 /* ADDR_DIFF_VECs are in the text section and thus can affect the
1310 current alignment. */
1311 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
1312 do \
1313 { \
1314 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \
1315 && ((GET_MODE_SIZE (as_a <scalar_int_mode> \
1316 (GET_MODE (PATTERN (JUMPTABLE)))) \
1317 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \
1318 & 2)) \
1319 arc_toggle_unalign (); \
1320 } \
1321 while (0)
1322
1323 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0)
1324 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
1325 (JUMP_ALIGN(LABEL) \
1326 ? JUMP_ALIGN(LABEL) \
1327 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
1328 ? 1 : 0)
1329 /* The desired alignment for the location counter at the beginning
1330 of a loop. */
1331 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size
1332 optimization. */
1333 #define LOOP_ALIGN(X) 0
1334
1335 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL))
1336
1337 /* This is how to output an assembler line
1338 that says to advance the location counter
1339 to a multiple of 2**LOG bytes. */
1340 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1341 do { \
1342 if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1343 if ((LOG) > 1) \
1344 arc_clear_unalign (); \
1345 } while (0)
1346
1347 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT)
1348 Define this macro when you need to see the variable's decl in order to
1349 chose what to output. */
1350 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
1351 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
1352
1353 /* Debugging information. */
1354
1355 /* Generate DBX and DWARF debugging information. */
1356 #ifdef DBX_DEBUGGING_INFO
1357 #undef DBX_DEBUGGING_INFO
1358 #endif
1359 #define DBX_DEBUGGING_INFO
1360
1361 #ifdef DWARF2_DEBUGGING_INFO
1362 #undef DWARF2_DEBUGGING_INFO
1363 #endif
1364 #define DWARF2_DEBUGGING_INFO
1365
1366 /* Prefer STABS (for now). */
1367 #undef PREFERRED_DEBUGGING_TYPE
1368 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1369
1370 /* How to renumber registers for dbx and gdb. */
1371 #define DBX_REGISTER_NUMBER(REGNO) \
1372 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1373 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1374 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \
1375 ? ((REGNO) == 57 \
1376 ? 58 /* MMED */ \
1377 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \
1378 ? 59 /* MHI */ \
1379 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1380 : (REGNO))
1381
1382 #define DWARF_FRAME_REGNUM(REG) (REG)
1383
1384 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
1385
1386 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
1387
1388 /* Frame info. */
1389
1390 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
1391
1392 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1393
1394 #define EH_RETURN_HANDLER_RTX arc_eh_return_address_location ()
1395
1396 /* Turn off splitting of long stabs. */
1397 #define DBX_CONTIN_LENGTH 0
1398
1399 /* Miscellaneous. */
1400
1401 /* Specify the machine mode that this machine uses
1402 for the index in the tablejump instruction.
1403 If we have pc relative case vectors, we start the case vector shortening
1404 with QImode. */
1405 #define CASE_VECTOR_MODE \
1406 (TARGET_BI_BIH ? SImode \
1407 : (optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode)
1408
1409 /* Define as C expression which evaluates to nonzero if the tablejump
1410 instruction expects the table to contain offsets from the address of the
1411 table.
1412 Do not define this if the table should contain absolute addresses. */
1413 #define CASE_VECTOR_PC_RELATIVE \
1414 (TARGET_CASE_VECTOR_PC_RELATIVE || TARGET_BI_BIH)
1415
1416 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1417 (TARGET_BI_BIH ? \
1418 ((MIN_OFFSET) >= -512 && (MAX_OFFSET) <= 508 ? HImode : SImode) \
1419 : ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1420 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1421 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \
1422 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1423 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \
1424 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \
1425 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \
1426 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
1427 : SImode))
1428
1429 #define ADDR_VEC_ALIGN(VEC_INSN) \
1430 (TARGET_BI_BIH ? 0 \
1431 : exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \
1432 (GET_MODE (PATTERN (VEC_INSN))))))
1433
1434 #define INSN_LENGTH_ALIGNMENT(INSN) \
1435 ((JUMP_TABLE_DATA_P (INSN) \
1436 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \
1437 && GET_MODE (PATTERN (INSN)) == QImode) \
1438 ? 0 : length_unit_log)
1439
1440 /* Define if operations between registers always perform the operation
1441 on the full register even if a narrower mode is specified. */
1442 #define WORD_REGISTER_OPERATIONS 1
1443
1444 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1445 will either zero-extend or sign-extend. The value of this macro should
1446 be the code that says which one of the two operations is implicitly
1447 done, NIL if none. */
1448 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1449
1450
1451 /* Max number of bytes we can move from memory to memory
1452 in one reasonably fast instruction. */
1453 #define MOVE_MAX 4
1454
1455 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */
1456 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
1457
1458 /* Define this to be nonzero if shift instructions ignore all but the
1459 low-order few bits.
1460 */
1461 #define SHIFT_COUNT_TRUNCATED 1
1462
1463 /* We assume that the store-condition-codes instructions store 0 for false
1464 and some other value for true. This is the value stored for true. */
1465 #define STORE_FLAG_VALUE 1
1466
1467 /* Specify the machine mode that pointers have.
1468 After generation of rtl, the compiler makes no further distinction
1469 between pointers and any other objects of this machine mode. */
1470 /* ARCompact has full 32-bit pointers. */
1471 #define Pmode SImode
1472
1473 /* A function address in a call instruction. */
1474 #define FUNCTION_MODE SImode
1475
1476 /* Define the information needed to generate branch and scc insns. This is
1477 stored from the compare operation. Note that we can't use "rtx" here
1478 since it hasn't been defined! */
1479 extern struct rtx_def *arc_compare_op0, *arc_compare_op1;
1480
1481 /* ARC function types. */
1482 enum arc_function_type {
1483 /* No function should have the unknown type. This value is used to
1484 indicate the that function type has not yet been computed. */
1485 ARC_FUNCTION_UNKNOWN = 0,
1486
1487 /* The normal function type indicates that the function has the
1488 standard prologue and epilogue. */
1489 ARC_FUNCTION_NORMAL = 1 << 0,
1490 /* These are interrupt handlers. The name corresponds to the register
1491 name that contains the return address. */
1492 ARC_FUNCTION_ILINK1 = 1 << 1,
1493 ARC_FUNCTION_ILINK2 = 1 << 2,
1494 /* Fast interrupt is only available on ARCv2 processors. */
1495 ARC_FUNCTION_FIRQ = 1 << 3,
1496 /* The naked function type indicates that the function does not have
1497 prologue or epilogue, and that no stack frame is available. */
1498 ARC_FUNCTION_NAKED = 1 << 4
1499 };
1500
1501 /* Check if a function is an interrupt function. */
1502 #define ARC_INTERRUPT_P(TYPE) \
1503 (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \
1504 | ARC_FUNCTION_FIRQ)) != 0)
1505
1506 /* Check if a function is a fast interrupt function. */
1507 #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0)
1508
1509 /* Check if a function is normal, that is, has standard prologue and
1510 epilogue. */
1511 #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0)
1512
1513 /* Check if a function is naked. */
1514 #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0)
1515
1516 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in
1517 SECTION_OP, and then to switch back to text section. */
1518 #undef CRT_CALL_STATIC_FUNCTION
1519 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1520 asm (SECTION_OP "\n\t" \
1521 "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \
1522 "jl [r12]\n" \
1523 TEXT_SECTION_ASM_OP);
1524
1525 /* This macro expands to the name of the scratch register r12, used for
1526 temporary calculations according to the ABI. */
1527 #define ARC_TEMP_SCRATCH_REG "r12"
1528
1529 /* The C++ compiler must use one bit to indicate whether the function
1530 that will be called through a pointer-to-member-function is
1531 virtual. Normally, we assume that the low-order bit of a function
1532 pointer must always be zero. Then, by ensuring that the
1533 vtable_index is odd, we can distinguish which variant of the union
1534 is in use. But, on some platforms function pointers can be odd,
1535 and so this doesn't work. In that case, we use the low-order bit
1536 of the `delta' field, and shift the remainder of the `delta' field
1537 to the left. We needed to do this for A4 because the address was always
1538 shifted and thus could be odd. */
1539 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
1540 (ptrmemfunc_vbit_in_pfn)
1541
1542 #define INSN_SETS_ARE_DELAYED(X) \
1543 (GET_CODE (X) == INSN \
1544 && GET_CODE (PATTERN (X)) != SEQUENCE \
1545 && GET_CODE (PATTERN (X)) != USE \
1546 && GET_CODE (PATTERN (X)) != CLOBBER \
1547 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC))
1548
1549 #define INSN_REFERENCES_ARE_DELAYED(insn) \
1550 (INSN_SETS_ARE_DELAYED (insn))
1551
1552 #define CALL_ATTR(X, NAME) \
1553 ((CALL_P (X) || NONJUMP_INSN_P (X)) \
1554 && GET_CODE (PATTERN (X)) != USE \
1555 && GET_CODE (PATTERN (X)) != CLOBBER \
1556 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \
1557
1558 #define REVERSE_CONDITION(CODE,MODE) \
1559 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
1560 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
1561 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \
1562 || (MODE) == CC_FPUmode) \
1563 ? reverse_condition_maybe_unordered ((CODE)) \
1564 : reverse_condition ((CODE)))
1565
1566 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1567 ((LENGTH) \
1568 = (GET_CODE (PATTERN (X)) == SEQUENCE \
1569 ? ((LENGTH) \
1570 + arc_adjust_insn_length ( \
1571 as_a <rtx_sequence *> (PATTERN (X))->insn (0), \
1572 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \
1573 true) \
1574 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \
1575 + arc_adjust_insn_length ( \
1576 as_a <rtx_sequence *> (PATTERN (X))->insn (1), \
1577 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \
1578 true) \
1579 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \
1580 : arc_adjust_insn_length ((X), (LENGTH), false)))
1581
1582 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`')
1583
1584 #define INIT_EXPANDERS arc_init_expanders ()
1585
1586 enum
1587 {
1588 ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT
1589 };
1590
1591 /* The define_cond_exec construct is rather crude, as we can't have
1592 different ones with different conditions apply to different sets
1593 of instructions. We can't use an attribute test inside the condition,
1594 because that would lead to infinite recursion as the attribute test
1595 needs to recognize the insn. So, instead we have a clause for
1596 the pattern condition of all sfunc patterns which is only relevant for
1597 the predicated varaint. */
1598 #define SFUNC_CHECK_PREDICABLE \
1599 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS)
1600
1601 /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */
1602 #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2)
1603 /* Full ARCv2 multiplication feature macro. */
1604 #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2)
1605 /* General MPY feature macro. */
1606 #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI)
1607 /* ARC700 MPY feature macro. */
1608 #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET))
1609 /* Any multiplication feature macro. */
1610 #define TARGET_ANY_MPY \
1611 (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET)
1612 /* PLUS_DMPY feature macro. */
1613 #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS)
1614 /* PLUS_MACD feature macro. */
1615 #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS)
1616 /* PLUS_QMACW feature macro. */
1617 #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS)
1618
1619 /* ARC600 and ARC601 feature macro. */
1620 #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601)
1621 /* ARC600, ARC601 and ARC700 feature macro. */
1622 #define TARGET_ARCOMPACT_FAMILY \
1623 (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700)
1624 /* Loop count register can be read in very next instruction after has
1625 been written to by an ordinary instruction. */
1626 #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY)
1627
1628 /* FPU defines. */
1629 /* Any FPU support. */
1630 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0)
1631 /* Single precision floating point support. */
1632 #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0)
1633 /* Double precision floating point support. */
1634 #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0)
1635 /* Single precision floating point support with fused operation. */
1636 #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0)
1637 /* Double precision floating point support with fused operation. */
1638 #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0)
1639 /* Single precision floating point conversion instruction support. */
1640 #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0)
1641 /* Double precision floating point conversion instruction support. */
1642 #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0)
1643 /* Single precision floating point SQRT/DIV instruction support. */
1644 #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0)
1645 /* Double precision floating point SQRT/DIV instruction support. */
1646 #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0)
1647 /* Double precision floating point assist instruction support. */
1648 #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0)
1649 /* Custom FP instructions used by QuarkSE EM cpu. */
1650 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \
1651 && (arc_fpu_build == FPX_QK))
1652 /* DBNZ support is available for ARCv2 core3 and newer cpus. */
1653 #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3))
1654
1655 /* BI/BIH feature macro. */
1656 #define TARGET_BI_BIH (TARGET_BRANCH_INDEX && TARGET_CODE_DENSITY)
1657
1658 /* The default option for BI/BIH instructions. */
1659 #define DEFAULT_BRANCH_INDEX 0
1660
1661 #endif /* GCC_ARC_H */
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