1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2023 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
119 #include "memmodel.h"
127 #include "addresses.h"
130 #include "rtl-error.h"
133 #include "print-rtl.h"
134 #include "function-abi.h"
135 #include "rtl-iter.h"
137 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
138 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
140 static int bb_reload_num
;
142 /* The current insn being processed and corresponding its single set
143 (NULL otherwise), its data (basic block, the insn data, the insn
144 static data, and the mode of each operand). */
145 static rtx_insn
*curr_insn
;
146 static rtx curr_insn_set
;
147 static basic_block curr_bb
;
148 static lra_insn_recog_data_t curr_id
;
149 static struct lra_static_insn_data
*curr_static_id
;
150 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
151 /* Mode of the register substituted by its equivalence with VOIDmode
152 (e.g. constant) and whose subreg is given operand of the current
153 insn. VOIDmode in all other cases. */
154 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
158 /* Start numbers for new registers and insns at the current constraints
160 static int new_regno_start
;
161 static int new_insn_uid_start
;
163 /* If LOC is nonnull, strip any outer subreg from it. */
165 strip_subreg (rtx
*loc
)
167 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
170 /* Return hard regno of REGNO or if it is was not assigned to a hard
171 register, use a hard register from its allocno class. */
173 get_try_hard_regno (int regno
)
176 enum reg_class rclass
;
178 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
179 hard_regno
= lra_get_regno_hard_regno (regno
);
182 rclass
= lra_get_allocno_class (regno
);
183 if (rclass
== NO_REGS
)
185 return ira_class_hard_regs
[rclass
][0];
188 /* Return the hard regno of X after removing its subreg. If X is not a
189 register or a subreg of a register, return -1. If X is a pseudo, use its
190 assignment. If X is a hard regno, return the final hard regno which will be
191 after elimination. */
193 get_hard_regno (rtx x
)
200 reg
= SUBREG_REG (x
);
203 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
204 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
207 if (HARD_REGISTER_NUM_P (REGNO (reg
)))
208 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
210 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
211 SUBREG_BYTE (x
), GET_MODE (x
));
215 /* If REGNO is a hard register or has been allocated a hard register,
216 return the class of that register. If REGNO is a reload pseudo
217 created by the current constraints pass, return its allocno class.
218 Return NO_REGS otherwise. */
219 static enum reg_class
220 get_reg_class (int regno
)
224 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
225 hard_regno
= lra_get_regno_hard_regno (regno
);
228 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
229 return REGNO_REG_CLASS (hard_regno
);
231 if (regno
>= new_regno_start
)
232 return lra_get_allocno_class (regno
);
236 /* Return true if REG_CLASS has enough allocatable hard regs to keep value of
239 enough_allocatable_hard_regs_p (enum reg_class reg_class
,
240 enum machine_mode reg_mode
)
242 int i
, j
, hard_regno
, class_size
, nregs
;
244 if (hard_reg_set_subset_p (reg_class_contents
[reg_class
], lra_no_alloc_regs
))
246 class_size
= ira_class_hard_regs_num
[reg_class
];
247 for (i
= 0; i
< class_size
; i
++)
249 hard_regno
= ira_class_hard_regs
[reg_class
][i
];
250 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
253 for (j
= 0; j
< nregs
; j
++)
254 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
255 || ! TEST_HARD_REG_BIT (reg_class_contents
[reg_class
],
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL and
271 - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
272 - the instruction we're processing is not a reload move.
274 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
275 REGNO (reg), or NO_REGS if no change in its class was needed. */
277 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
,
278 bool allow_all_reload_class_changes_p
= false)
280 enum reg_class rclass
, common_class
;
281 machine_mode reg_mode
;
283 int regno
= REGNO (reg
);
285 if (new_class
!= NULL
)
286 *new_class
= NO_REGS
;
287 if (regno
< FIRST_PSEUDO_REGISTER
)
290 rtx
*final_loc
= &final_reg
;
292 lra_eliminate_reg_if_possible (final_loc
);
293 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
295 reg_mode
= GET_MODE (reg
);
296 rclass
= get_reg_class (regno
);
297 src
= curr_insn_set
!= NULL
? SET_SRC (curr_insn_set
) : NULL
;
298 if (regno
< new_regno_start
299 /* Do not allow the constraints for reload instructions to
300 influence the classes of new pseudos. These reloads are
301 typically moves that have many alternatives, and restricting
302 reload pseudos for one alternative may lead to situations
303 where other reload pseudos are no longer allocatable. */
304 || (!allow_all_reload_class_changes_p
305 && INSN_UID (curr_insn
) >= new_insn_uid_start
307 && ((REG_P (src
) || MEM_P (src
))
308 || (GET_CODE (src
) == SUBREG
309 && (REG_P (SUBREG_REG (src
)) || MEM_P (SUBREG_REG (src
)))))))
310 /* When we don't know what class will be used finally for reload
311 pseudos, we use ALL_REGS. */
312 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
313 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
314 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
315 lra_no_alloc_regs
)));
318 common_class
= ira_reg_class_subset
[rclass
][cl
];
319 if (new_class
!= NULL
)
320 *new_class
= common_class
;
321 return enough_allocatable_hard_regs_p (common_class
, reg_mode
);
325 /* Return true if REGNO satisfies a memory constraint. */
329 return get_reg_class (regno
) == NO_REGS
;
332 /* Return true if ADDR is a valid memory address for mode MODE in address
333 space AS, and check that each pseudo has the proper kind of hard
336 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
337 rtx addr
, addr_space_t as
)
339 #ifdef GO_IF_LEGITIMATE_ADDRESS
340 lra_assert (ADDR_SPACE_GENERIC_P (as
));
341 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
347 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
,
353 /* Temporarily eliminates registers in an address (for the lifetime of
355 class address_eliminator
{
357 address_eliminator (struct address_info
*ad
);
358 ~address_eliminator ();
361 struct address_info
*m_ad
;
369 address_eliminator::address_eliminator (struct address_info
*ad
)
371 m_base_loc (strip_subreg (ad
->base_term
)),
372 m_base_reg (NULL_RTX
),
373 m_index_loc (strip_subreg (ad
->index_term
)),
374 m_index_reg (NULL_RTX
)
376 if (m_base_loc
!= NULL
)
378 m_base_reg
= *m_base_loc
;
379 /* If we have non-legitimate address which is decomposed not in
380 the way we expected, don't do elimination here. In such case
381 the address will be reloaded and elimination will be done in
382 reload insn finally. */
383 if (REG_P (m_base_reg
))
384 lra_eliminate_reg_if_possible (m_base_loc
);
385 if (m_ad
->base_term2
!= NULL
)
386 *m_ad
->base_term2
= *m_ad
->base_term
;
388 if (m_index_loc
!= NULL
)
390 m_index_reg
= *m_index_loc
;
391 if (REG_P (m_index_reg
))
392 lra_eliminate_reg_if_possible (m_index_loc
);
396 address_eliminator::~address_eliminator ()
398 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
400 *m_base_loc
= m_base_reg
;
401 if (m_ad
->base_term2
!= NULL
)
402 *m_ad
->base_term2
= *m_ad
->base_term
;
404 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
405 *m_index_loc
= m_index_reg
;
408 /* Return true if the eliminated form of AD is a legitimate target address.
409 If OP is a MEM, AD is the address within OP, otherwise OP should be
410 ignored. CONSTRAINT is one constraint that the operand may need
413 valid_address_p (rtx op
, struct address_info
*ad
,
414 enum constraint_num constraint
)
416 address_eliminator
eliminator (ad
);
418 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
420 Need to extract memory from op for special memory constraint,
421 i.e. bcst_mem_operand in i386 backend. */
422 if (MEM_P (extract_mem_from_operand (op
))
423 && insn_extra_relaxed_memory_constraint (constraint
)
424 && constraint_satisfied_p (op
, constraint
))
427 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
430 /* For special_memory_operand, it could be false for MEM_P (op),
431 i.e. bcst_mem_operand in i386 backend.
432 Extract and return real memory operand or op. */
434 extract_mem_from_operand (rtx op
)
436 for (rtx x
= op
;; x
= XEXP (x
, 0))
440 if (GET_RTX_LENGTH (GET_CODE (x
)) != 1
441 || GET_RTX_FORMAT (GET_CODE (x
))[0] != 'e')
447 /* Return true if the eliminated form of memory reference OP satisfies
448 extra (special) memory constraint CONSTRAINT. */
450 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
452 struct address_info ad
;
453 rtx mem
= extract_mem_from_operand (op
);
457 decompose_mem_address (&ad
, mem
);
458 address_eliminator
eliminator (&ad
);
459 return constraint_satisfied_p (op
, constraint
);
462 /* Return true if the eliminated form of address AD satisfies extra
463 address constraint CONSTRAINT. */
465 satisfies_address_constraint_p (struct address_info
*ad
,
466 enum constraint_num constraint
)
468 address_eliminator
eliminator (ad
);
469 return constraint_satisfied_p (*ad
->outer
, constraint
);
472 /* Return true if the eliminated form of address OP satisfies extra
473 address constraint CONSTRAINT. */
475 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
477 struct address_info ad
;
479 decompose_lea_address (&ad
, &op
);
480 return satisfies_address_constraint_p (&ad
, constraint
);
483 /* Initiate equivalences for LRA. As we keep original equivalences
484 before any elimination, we need to make copies otherwise any change
485 in insns might change the equivalences. */
487 lra_init_equiv (void)
489 ira_expand_reg_equiv ();
490 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
494 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
495 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
496 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
497 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
501 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
503 /* Update equivalence for REGNO. We need to this as the equivalence
504 might contain other pseudos which are changed by their
507 update_equiv (int regno
)
511 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
512 ira_reg_equiv
[regno
].memory
513 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
515 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
516 ira_reg_equiv
[regno
].invariant
517 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
521 /* If we have decided to substitute X with another value, return that
522 value, otherwise return X. */
529 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
530 || ! ira_reg_equiv
[regno
].defined_p
531 || ! ira_reg_equiv
[regno
].profitable_p
532 || lra_get_regno_hard_regno (regno
) >= 0)
534 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
536 if (targetm
.cannot_substitute_mem_equiv_p (res
))
540 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
542 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
547 /* If we have decided to substitute X with the equivalent value,
548 return that value after elimination for INSN, otherwise return
551 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
553 rtx res
= get_equiv (x
);
555 if (x
== res
|| CONSTANT_P (res
))
557 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
558 false, false, 0, true);
561 /* Set up curr_operand_mode. */
563 init_curr_operand_mode (void)
565 int nop
= curr_static_id
->n_operands
;
566 for (int i
= 0; i
< nop
; i
++)
568 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
569 if (mode
== VOIDmode
)
571 /* The .md mode for address operands is the mode of the
572 addressed value rather than the mode of the address itself. */
573 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
576 mode
= curr_static_id
->operand
[i
].mode
;
578 curr_operand_mode
[i
] = mode
;
584 /* The page contains code to reuse input reloads. */
586 /* Structure describes input reload of the current insns. */
589 /* True for input reload of matched operands. */
591 /* Reloaded value. */
593 /* Reload pseudo used. */
597 /* The number of elements in the following array. */
598 static int curr_insn_input_reloads_num
;
599 /* Array containing info about input reloads. It is used to find the
600 same input reload and reuse the reload pseudo in this case. */
601 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
603 /* Initiate data concerning reuse of input reloads for the current
606 init_curr_insn_input_reloads (void)
608 curr_insn_input_reloads_num
= 0;
611 /* The canonical form of an rtx inside a MEM is not necessarily the same as the
612 canonical form of the rtx outside the MEM. Fix this up in the case that
613 we're reloading an address (and therefore pulling it outside a MEM). */
615 canonicalize_reload_addr (rtx addr
)
617 subrtx_var_iterator::array_type array
;
618 FOR_EACH_SUBRTX_VAR (iter
, array
, addr
, NONCONST
)
621 if (GET_CODE (x
) == MULT
&& CONST_INT_P (XEXP (x
, 1)))
623 const HOST_WIDE_INT ci
= INTVAL (XEXP (x
, 1));
624 const int pwr2
= exact_log2 (ci
);
627 /* Rewrite this to use a shift instead, which is canonical when
629 PUT_CODE (x
, ASHIFT
);
630 XEXP (x
, 1) = GEN_INT (pwr2
);
638 /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or
639 reuse an existing reload pseudo. Don't reuse an existing reload pseudo if
640 IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG.
641 The result pseudo is returned through RESULT_REG. Return TRUE if we created
642 a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to
643 describe new registers for debug purposes. */
645 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
646 enum reg_class rclass
, HARD_REG_SET
*exclude_start_hard_regs
,
647 bool in_subreg_p
, const char *title
, rtx
*result_reg
)
650 enum reg_class new_class
;
651 bool unique_p
= false;
655 /* Output reload registers tend to start out with a conservative
656 choice of register class. Usually this is ALL_REGS, although
657 a target might narrow it (for performance reasons) through
658 targetm.preferred_reload_class. It's therefore quite common
659 for a reload instruction to require a more restrictive class
660 than the class that was originally assigned to the reload register.
662 In these situations, it's more efficient to refine the choice
663 of register class rather than create a second reload register.
664 This also helps to avoid cycling for registers that are only
665 used by reload instructions. */
667 && (int) REGNO (original
) >= new_regno_start
668 && INSN_UID (curr_insn
) >= new_insn_uid_start
669 && in_class_p (original
, rclass
, &new_class
, true))
671 unsigned int regno
= REGNO (original
);
672 if (lra_dump_file
!= NULL
)
674 fprintf (lra_dump_file
, " Reuse r%d for output ", regno
);
675 dump_value_slim (lra_dump_file
, original
, 1);
677 if (new_class
!= lra_get_allocno_class (regno
))
678 lra_change_class (regno
, new_class
, ", change to", false);
679 if (lra_dump_file
!= NULL
)
680 fprintf (lra_dump_file
, "\n");
681 *result_reg
= original
;
685 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
,
686 exclude_start_hard_regs
, title
);
689 /* Prevent reuse value of expression with side effects,
690 e.g. volatile memory. */
691 if (! side_effects_p (original
))
692 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
694 if (! curr_insn_input_reloads
[i
].match_p
695 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
696 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
698 rtx reg
= curr_insn_input_reloads
[i
].reg
;
700 /* If input is equal to original and both are VOIDmode,
701 GET_MODE (reg) might be still different from mode.
702 Ensure we don't return *result_reg with wrong mode. */
703 if (GET_MODE (reg
) != mode
)
707 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
708 GET_MODE_SIZE (mode
)))
710 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
711 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
715 if (lra_dump_file
!= NULL
)
717 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
718 dump_value_slim (lra_dump_file
, original
, 1);
720 if (new_class
!= lra_get_allocno_class (regno
))
721 lra_change_class (regno
, new_class
, ", change to", false);
722 if (lra_dump_file
!= NULL
)
723 fprintf (lra_dump_file
, "\n");
726 /* If we have an input reload with a different mode, make sure it
727 will get a different hard reg. */
728 else if (REG_P (original
)
729 && REG_P (curr_insn_input_reloads
[i
].input
)
730 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
731 && (GET_MODE (original
)
732 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
735 *result_reg
= (unique_p
736 ? lra_create_new_reg_with_unique_value
737 : lra_create_new_reg
) (mode
, original
, rclass
,
738 exclude_start_hard_regs
, title
);
739 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
740 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
741 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
742 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
747 /* The page contains major code to choose the current insn alternative
748 and generate reloads for it. */
750 /* Return the offset from REGNO of the least significant register
753 This function is used to tell whether two registers satisfy
754 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
756 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
757 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
759 lra_constraint_offset (int regno
, machine_mode mode
)
761 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
763 scalar_int_mode int_mode
;
765 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
766 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
767 return hard_regno_nregs (regno
, mode
) - 1;
771 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
772 if they are the same hard reg, and has special hacks for
773 auto-increment and auto-decrement. This is specifically intended for
774 process_alt_operands to use in determining whether two operands
775 match. X is the operand whose number is the lower of the two.
777 It is supposed that X is the output operand and Y is the input
778 operand. Y_HARD_REGNO is the final hard regno of register Y or
779 register in subreg Y as we know it now. Otherwise, it is a
782 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
785 RTX_CODE code
= GET_CODE (x
);
790 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
791 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
795 i
= get_hard_regno (x
);
799 if ((j
= y_hard_regno
) < 0)
802 i
+= lra_constraint_offset (i
, GET_MODE (x
));
803 j
+= lra_constraint_offset (j
, GET_MODE (y
));
808 /* If two operands must match, because they are really a single
809 operand of an assembler insn, then two post-increments are invalid
810 because the assembler insn would increment only once. On the
811 other hand, a post-increment matches ordinary indexing if the
812 post-increment is the output operand. */
813 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
814 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
816 /* Two pre-increments are invalid because the assembler insn would
817 increment only once. On the other hand, a pre-increment matches
818 ordinary indexing if the pre-increment is the input operand. */
819 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
820 || GET_CODE (y
) == PRE_MODIFY
)
821 return operands_match_p (x
, XEXP (y
, 0), -1);
825 if (code
== REG
&& REG_P (y
))
826 return REGNO (x
) == REGNO (y
);
828 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
829 && x
== SUBREG_REG (y
))
831 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
832 && SUBREG_REG (x
) == y
)
835 /* Now we have disposed of all the cases in which different rtx
837 if (code
!= GET_CODE (y
))
840 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
841 if (GET_MODE (x
) != GET_MODE (y
))
850 if (!same_vector_encodings_p (x
, y
))
855 return label_ref_label (x
) == label_ref_label (y
);
857 return XSTR (x
, 0) == XSTR (y
, 0);
863 /* Compare the elements. If any pair of corresponding elements fail
864 to match, return false for the whole things. */
866 fmt
= GET_RTX_FORMAT (code
);
867 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
873 if (XWINT (x
, i
) != XWINT (y
, i
))
878 if (XINT (x
, i
) != XINT (y
, i
))
883 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
888 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
897 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
899 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
901 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
907 /* It is believed that rtx's at this level will never
908 contain anything but integers and other rtx's, except for
909 within LABEL_REFs and SYMBOL_REFs. */
917 /* True if X is a constant that can be forced into the constant pool.
918 MODE is the mode of the operand, or VOIDmode if not known. */
919 #define CONST_POOL_OK_P(MODE, X) \
920 ((MODE) != VOIDmode \
922 && GET_CODE (X) != HIGH \
923 && GET_MODE_SIZE (MODE).is_constant () \
924 && !targetm.cannot_force_const_mem (MODE, X))
926 /* True if C is a non-empty register class that has too few registers
927 to be safely used as a reload target class. */
928 #define SMALL_REGISTER_CLASS_P(C) \
929 (ira_class_hard_regs_num [(C)] == 1 \
930 || (ira_class_hard_regs_num [(C)] >= 1 \
931 && targetm.class_likely_spilled_p (C)))
933 /* If REG is a reload pseudo, try to make its class satisfying CL. */
935 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
937 enum reg_class rclass
;
939 /* Do not make more accurate class from reloads generated. They are
940 mostly moves with a lot of constraints. Making more accurate
941 class may results in very narrow class and impossibility of find
942 registers for several reloads of one insn. */
943 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
945 if (GET_CODE (reg
) == SUBREG
)
946 reg
= SUBREG_REG (reg
);
947 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
949 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
950 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
953 /* Searches X for any reference to a reg with the same value as REGNO,
954 returning the rtx of the reference found if any. Otherwise,
957 regno_val_use_in (unsigned int regno
, rtx x
)
963 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
966 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
967 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
971 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
974 else if (fmt
[i
] == 'E')
975 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
976 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
983 /* Return true if all current insn non-output operands except INS (it
984 has a negaitve end marker) do not use pseudos with the same value
987 check_conflict_input_operands (int regno
, signed char *ins
)
990 int n_operands
= curr_static_id
->n_operands
;
992 for (int nop
= 0; nop
< n_operands
; nop
++)
993 if (! curr_static_id
->operand
[nop
].is_operator
994 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
996 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
1000 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
1006 /* Generate reloads for matching OUT and INS (array of input operand numbers
1007 with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS,
1008 considering output operands OUTS (similar array to INS) needing to be in
1009 different registers. Add input and output reloads correspondingly to the
1010 lists *BEFORE and *AFTER. OUT might be negative. In this case we generate
1011 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1012 that the output operand is early clobbered for chosen alternative. */
1014 match_reload (signed char out
, signed char *ins
, signed char *outs
,
1015 enum reg_class goal_class
, HARD_REG_SET
*exclude_start_hard_regs
,
1016 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
1020 rtx new_in_reg
, new_out_reg
, reg
;
1021 machine_mode inmode
, outmode
;
1022 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
1023 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
1025 inmode
= curr_operand_mode
[ins
[0]];
1026 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
1027 push_to_sequence (*before
);
1028 if (inmode
!= outmode
)
1030 /* process_alt_operands has already checked that the mode sizes
1032 if (partial_subreg_p (outmode
, inmode
))
1034 bool asm_p
= asm_noperands (PATTERN (curr_insn
)) >= 0;
1036 HARD_REG_SET temp_hard_reg_set
;
1038 if (asm_p
&& (hr
= get_hard_regno (out_rtx
)) >= 0
1039 && hard_regno_nregs (hr
, inmode
) > 1)
1041 /* See gcc.c-torture/execute/20030222-1.c.
1042 Consider the code for 32-bit (e.g. BE) target:
1043 int i, v; long x; x = v; asm ("" : "=r" (i) : "0" (x));
1044 We generate the following RTL with reload insns:
1045 1. subreg:si(x:di, 0) = 0;
1046 2. subreg:si(x:di, 4) = v:si;
1047 3. t:di = x:di, dead x;
1048 4. asm ("" : "=r" (subreg:si(t:di,4)) : "0" (t:di))
1049 5. i:si = subreg:si(t:di,4);
1050 If we assign hard reg of x to t, dead code elimination
1051 will remove insn #2 and we will use unitialized hard reg.
1052 So exclude the hard reg of x for t. We could ignore this
1053 problem for non-empty asm using all x value but it is hard to
1054 check that the asm are expanded into insn realy using x
1056 CLEAR_HARD_REG_SET (temp_hard_reg_set
);
1057 if (exclude_start_hard_regs
!= NULL
)
1058 temp_hard_reg_set
= *exclude_start_hard_regs
;
1059 SET_HARD_REG_BIT (temp_hard_reg_set
, hr
);
1060 exclude_start_hard_regs
= &temp_hard_reg_set
;
1063 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
, goal_class
,
1064 exclude_start_hard_regs
,
1066 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
1067 LRA_SUBREG_P (new_out_reg
) = 1;
1068 /* If the input reg is dying here, we can use the same hard
1069 register for REG and IN_RTX. We do it only for original
1070 pseudos as reload pseudos can die although original
1071 pseudos still live where reload pseudos dies. */
1072 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
1073 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1074 && (!early_clobber_p
1075 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
1076 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
1081 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1083 exclude_start_hard_regs
,
1085 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
1086 /* NEW_IN_REG is non-paradoxical subreg. We don't want
1087 NEW_OUT_REG living above. We add clobber clause for
1088 this. This is just a temporary clobber. We can remove
1089 it at the end of LRA work. */
1090 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
1091 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
1092 LRA_SUBREG_P (new_in_reg
) = 1;
1093 if (GET_CODE (in_rtx
) == SUBREG
)
1095 rtx subreg_reg
= SUBREG_REG (in_rtx
);
1097 /* If SUBREG_REG is dying here and sub-registers IN_RTX
1098 and NEW_IN_REG are similar, we can use the same hard
1099 register for REG and SUBREG_REG. */
1100 if (REG_P (subreg_reg
)
1101 && (int) REGNO (subreg_reg
) < lra_new_regno_start
1102 && GET_MODE (subreg_reg
) == outmode
1103 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
1104 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
1105 && (! early_clobber_p
1106 || check_conflict_input_operands (REGNO (subreg_reg
),
1108 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1114 /* Pseudos have values -- see comments for lra_reg_info.
1115 Different pseudos with the same value do not conflict even if
1116 they live in the same place. When we create a pseudo we
1117 assign value of original pseudo (if any) from which we
1118 created the new pseudo. If we create the pseudo from the
1119 input pseudo, the new pseudo will have no conflict with the
1120 input pseudo which is wrong when the input pseudo lives after
1121 the insn and as the new pseudo value is changed by the insn
1122 output. Therefore we create the new pseudo from the output
1123 except the case when we have single matched dying input
1126 We cannot reuse the current output register because we might
1127 have a situation like "a <- a op b", where the constraints
1128 force the second input operand ("b") to match the output
1129 operand ("a"). "b" must then be copied into a new register
1130 so that it doesn't clobber the current value of "a".
1132 We cannot use the same value if the output pseudo is
1133 early clobbered or the input pseudo is mentioned in the
1134 output, e.g. as an address part in memory, because
1135 output reload will actually extend the pseudo liveness.
1136 We don't care about eliminable hard regs here as we are
1137 interesting only in pseudos. */
1139 /* Matching input's register value is the same as one of the other
1140 output operand. Output operands in a parallel insn must be in
1141 different registers. */
1142 out_conflict
= false;
1145 for (i
= 0; outs
[i
] >= 0; i
++)
1147 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1148 if (outs
[i
] != out
&& REG_P (other_out_rtx
)
1149 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1152 out_conflict
= true;
1158 new_in_reg
= new_out_reg
1159 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1160 && (int) REGNO (in_rtx
) < lra_new_regno_start
1161 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1162 && (! early_clobber_p
1163 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1165 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1167 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
,
1168 exclude_start_hard_regs
, "")
1169 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
, goal_class
,
1170 exclude_start_hard_regs
,
1173 /* In operand can be got from transformations before processing insn
1174 constraints. One example of such transformations is subreg
1175 reloading (see function simplify_operand_subreg). The new
1176 pseudos created by the transformations might have inaccurate
1177 class (ALL_REGS) and we should make their classes more
1179 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1180 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1181 *before
= get_insns ();
1183 /* Add the new pseudo to consider values of subsequent input reload
1185 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1186 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1187 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1188 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1189 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1190 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1191 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1192 *curr_id
->operand_loc
[in
] = new_in_reg
;
1196 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1197 *curr_id
->operand_loc
[in
] = new_out_reg
;
1199 lra_update_dups (curr_id
, ins
);
1202 /* See a comment for the input operand above. */
1203 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1204 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1206 reg
= SUBREG_P (out_rtx
) ? SUBREG_REG (out_rtx
) : out_rtx
;
1208 /* If we had strict_low_part, use it also in reload to keep other
1209 parts unchanged but do it only for regs as strict_low_part
1210 has no sense for memory and probably there is no insn pattern
1211 to match the reload insn in memory case. */
1212 if (out
>= 0 && curr_static_id
->operand
[out
].strict_low
&& REG_P (reg
))
1213 out_rtx
= gen_rtx_STRICT_LOW_PART (VOIDmode
, out_rtx
);
1214 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1216 *after
= get_insns ();
1219 *curr_id
->operand_loc
[out
] = new_out_reg
;
1220 lra_update_dup (curr_id
, out
);
1223 /* Return register class which is union of all reg classes in insn
1224 constraint alternative string starting with P. */
1225 static enum reg_class
1226 reg_class_from_constraints (const char *p
)
1229 enum reg_class op_class
= NO_REGS
;
1232 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1239 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1243 enum constraint_num cn
= lookup_constraint (p
);
1244 enum reg_class cl
= reg_class_for_constraint (cn
);
1247 if (insn_extra_address_constraint (cn
))
1249 = (reg_class_subunion
1250 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1251 ADDRESS
, SCRATCH
)]);
1255 op_class
= reg_class_subunion
[op_class
][cl
];
1258 while ((p
+= len
), c
);
1262 /* If OP is a register, return the class of the register as per
1263 get_reg_class, otherwise return NO_REGS. */
1264 static inline enum reg_class
1265 get_op_class (rtx op
)
1267 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1270 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1271 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1272 SUBREG for VAL to make them equal. */
1274 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1276 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1278 /* Usually size of mem_pseudo is greater than val size but in
1279 rare cases it can be less as it can be defined by target
1280 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1283 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1284 GET_CODE (val
) == SUBREG
1285 ? SUBREG_REG (val
) : val
);
1286 LRA_SUBREG_P (val
) = 1;
1290 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1291 LRA_SUBREG_P (mem_pseudo
) = 1;
1294 return to_p
? gen_move_insn (mem_pseudo
, val
)
1295 : gen_move_insn (val
, mem_pseudo
);
1298 /* Process a special case insn (register move), return true if we
1299 don't need to process it anymore. INSN should be a single set
1300 insn. Set up that RTL was changed through CHANGE_P and that hook
1301 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1304 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1307 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1309 enum reg_class dclass
, sclass
, secondary_class
;
1310 secondary_reload_info sri
;
1312 lra_assert (curr_insn_set
!= NULL_RTX
);
1313 dreg
= dest
= SET_DEST (curr_insn_set
);
1314 sreg
= src
= SET_SRC (curr_insn_set
);
1315 if (GET_CODE (dest
) == SUBREG
)
1316 dreg
= SUBREG_REG (dest
);
1317 if (GET_CODE (src
) == SUBREG
)
1318 sreg
= SUBREG_REG (src
);
1319 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1321 sclass
= dclass
= NO_REGS
;
1323 dclass
= get_reg_class (REGNO (dreg
));
1324 gcc_assert (dclass
< LIM_REG_CLASSES
&& dclass
>= NO_REGS
);
1325 if (dclass
== ALL_REGS
)
1326 /* ALL_REGS is used for new pseudos created by transformations
1327 like reload of SUBREG_REG (see function
1328 simplify_operand_subreg). We don't know their class yet. We
1329 should figure out the class from processing the insn
1330 constraints not in this fast path function. Even if ALL_REGS
1331 were a right class for the pseudo, secondary_... hooks usually
1332 are not define for ALL_REGS. */
1335 sclass
= get_reg_class (REGNO (sreg
));
1336 gcc_assert (sclass
< LIM_REG_CLASSES
&& sclass
>= NO_REGS
);
1337 if (sclass
== ALL_REGS
)
1338 /* See comments above. */
1340 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1342 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1343 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1345 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1350 if (! REG_P (dreg
) || ! REG_P (sreg
))
1352 sri
.prev_sri
= NULL
;
1353 sri
.icode
= CODE_FOR_nothing
;
1355 secondary_class
= NO_REGS
;
1356 /* Set up hard register for a reload pseudo for hook
1357 secondary_reload because some targets just ignore unassigned
1358 pseudos in the hook. */
1359 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1361 dregno
= REGNO (dreg
);
1362 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1366 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1368 sregno
= REGNO (sreg
);
1369 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1373 if (sclass
!= NO_REGS
)
1375 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1376 (reg_class_t
) sclass
,
1377 GET_MODE (src
), &sri
);
1378 if (sclass
== NO_REGS
1379 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1380 && dclass
!= NO_REGS
))
1382 enum reg_class old_sclass
= secondary_class
;
1383 secondary_reload_info old_sri
= sri
;
1385 sri
.prev_sri
= NULL
;
1386 sri
.icode
= CODE_FOR_nothing
;
1389 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1390 (reg_class_t
) dclass
,
1391 GET_MODE (src
), &sri
);
1392 /* Check the target hook consistency. */
1394 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1395 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1396 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1399 reg_renumber
[sregno
] = -1;
1401 reg_renumber
[dregno
] = -1;
1402 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1406 if (secondary_class
!= NO_REGS
)
1407 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1408 secondary_class
, NULL
,
1411 if (sri
.icode
== CODE_FOR_nothing
)
1412 lra_emit_move (new_reg
, src
);
1415 enum reg_class scratch_class
;
1417 scratch_class
= (reg_class_from_constraints
1418 (insn_data
[sri
.icode
].operand
[2].constraint
));
1419 scratch_reg
= (lra_create_new_reg_with_unique_value
1420 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1421 scratch_class
, NULL
, "scratch"));
1422 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1425 before
= get_insns ();
1427 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1428 if (new_reg
!= NULL_RTX
)
1429 SET_SRC (curr_insn_set
) = new_reg
;
1432 if (lra_dump_file
!= NULL
)
1434 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1435 dump_insn_slim (lra_dump_file
, curr_insn
);
1437 lra_set_insn_deleted (curr_insn
);
1443 /* The following data describe the result of process_alt_operands.
1444 The data are used in curr_insn_transform to generate reloads. */
1446 /* The chosen reg classes which should be used for the corresponding
1448 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1449 /* Hard registers which cannot be a start hard register for the corresponding
1451 static HARD_REG_SET goal_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
1452 /* True if the operand should be the same as another operand and that
1453 other operand does not need a reload. */
1454 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1455 /* True if the operand does not need a reload. */
1456 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1457 /* True if the operand can be offsetable memory. */
1458 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1459 /* The number of an operand to which given operand can be matched to. */
1460 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1461 /* The number of elements in the following array. */
1462 static int goal_alt_dont_inherit_ops_num
;
1463 /* Numbers of operands whose reload pseudos should not be inherited. */
1464 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1465 /* True if we should try only this alternative for the next constraint sub-pass
1466 to speed up the sub-pass. */
1467 static bool goal_reuse_alt_p
;
1468 /* True if the insn commutative operands should be swapped. */
1469 static bool goal_alt_swapped
;
1470 /* The chosen insn alternative. */
1471 static int goal_alt_number
;
1472 /* True if output reload of the stack pointer should be generated. */
1473 static bool goal_alt_out_sp_reload_p
;
1475 /* True if the corresponding operand is the result of an equivalence
1477 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1479 /* The following five variables are used to choose the best insn
1480 alternative. They reflect final characteristics of the best
1483 /* Number of necessary reloads and overall cost reflecting the
1484 previous value and other unpleasantness of the best alternative. */
1485 static int best_losers
, best_overall
;
1486 /* Overall number hard registers used for reloads. For example, on
1487 some targets we need 2 general registers to reload DFmode and only
1488 one floating point register. */
1489 static int best_reload_nregs
;
1490 /* Overall number reflecting distances of previous reloading the same
1491 value. The distances are counted from the current BB start. It is
1492 used to improve inheritance chances. */
1493 static int best_reload_sum
;
1495 /* True if the current insn should have no correspondingly input or
1497 static bool no_input_reloads_p
, no_output_reloads_p
;
1499 /* True if we swapped the commutative operands in the current
1501 static int curr_swapped
;
1503 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1504 register of class CL. Add any input reloads to list BEFORE. AFTER
1505 is nonnull if *LOC is an automodified value; handle that case by
1506 adding the required output reloads to list AFTER. Return true if
1507 the RTL was changed.
1509 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1510 register. Return false if the address register is correct. */
1512 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1516 enum reg_class rclass
, new_class
;
1520 bool subreg_p
, before_p
= false;
1522 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1525 reg
= SUBREG_REG (*loc
);
1526 mode
= GET_MODE (reg
);
1528 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1529 between two registers with different classes, but there normally will
1530 be "mov" which transfers element of vector register into the general
1531 register, and this normally will be a subreg which should be reloaded
1532 as a whole. This is particularly likely to be triggered when
1533 -fno-split-wide-types specified. */
1535 || in_class_p (reg
, cl
, &new_class
)
1536 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1537 loc
= &SUBREG_REG (*loc
);
1541 mode
= GET_MODE (reg
);
1546 /* Always reload memory in an address even if the target supports
1548 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, NULL
,
1554 regno
= REGNO (reg
);
1555 rclass
= get_reg_class (regno
);
1557 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1559 if (lra_dump_file
!= NULL
)
1561 fprintf (lra_dump_file
,
1562 "Changing pseudo %d in address of insn %u on equiv ",
1563 REGNO (reg
), INSN_UID (curr_insn
));
1564 dump_value_slim (lra_dump_file
, *loc
, 1);
1565 fprintf (lra_dump_file
, "\n");
1567 *loc
= copy_rtx (*loc
);
1569 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1574 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1575 mode
, reg
, cl
, NULL
,
1576 subreg_p
, "address", &new_reg
))
1579 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1583 lra_change_class (regno
, new_class
, " Change to", true);
1591 push_to_sequence (*before
);
1592 lra_emit_move (new_reg
, reg
);
1593 *before
= get_insns ();
1600 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1602 *after
= get_insns ();
1608 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1609 the insn to be inserted before curr insn. AFTER returns the
1610 the insn to be inserted after curr insn. ORIGREG and NEWREG
1611 are the original reg and new reg for reload. */
1613 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1618 push_to_sequence (*before
);
1619 lra_emit_move (newreg
, origreg
);
1620 *before
= get_insns ();
1626 lra_emit_move (origreg
, newreg
);
1628 *after
= get_insns ();
1633 static bool valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1634 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1636 /* Make reloads for subreg in operand NOP with internal subreg mode
1637 REG_MODE, add new reloads for further processing. Return true if
1638 any change was done. */
1640 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1642 int hard_regno
, inner_hard_regno
;
1643 rtx_insn
*before
, *after
;
1644 machine_mode mode
, innermode
;
1646 rtx operand
= *curr_id
->operand_loc
[nop
];
1647 enum reg_class regclass
;
1650 before
= after
= NULL
;
1652 if (GET_CODE (operand
) != SUBREG
)
1655 mode
= GET_MODE (operand
);
1656 reg
= SUBREG_REG (operand
);
1657 innermode
= GET_MODE (reg
);
1658 type
= curr_static_id
->operand
[nop
].type
;
1661 const bool addr_was_valid
1662 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1663 alter_subreg (curr_id
->operand_loc
[nop
], false);
1664 rtx subst
= *curr_id
->operand_loc
[nop
];
1665 lra_assert (MEM_P (subst
));
1666 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1668 MEM_ADDR_SPACE (subst
));
1671 || ((get_constraint_type (lookup_constraint
1672 (curr_static_id
->operand
[nop
].constraint
))
1673 != CT_SPECIAL_MEMORY
)
1674 /* We still can reload address and if the address is
1675 valid, we can remove subreg without reloading its
1677 && valid_address_p (GET_MODE (subst
),
1679 [ira_class_hard_regs
1680 [base_reg_class (GET_MODE (subst
),
1681 MEM_ADDR_SPACE (subst
),
1682 ADDRESS
, SCRATCH
)][0]],
1683 MEM_ADDR_SPACE (subst
))))
1685 /* If we change the address for a paradoxical subreg of memory, the
1686 new address might violate the necessary alignment or the access
1687 might be slow; take this into consideration. We need not worry
1688 about accesses beyond allocated memory for paradoxical memory
1689 subregs as we don't substitute such equiv memory (see processing
1690 equivalences in function lra_constraints) and because for spilled
1691 pseudos we allocate stack memory enough for the biggest
1692 corresponding paradoxical subreg.
1694 However, do not blindly simplify a (subreg (mem ...)) for
1695 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1696 data into a register when the inner is narrower than outer or
1697 missing important data from memory when the inner is wider than
1698 outer. This rule only applies to modes that are no wider than
1701 If valid memory becomes invalid after subreg elimination
1702 and address might be different we still have to reload
1705 if ((! addr_was_valid
1707 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1708 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1709 GET_MODE_PRECISION (innermode
))
1710 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1711 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1712 && WORD_REGISTER_OPERATIONS
)
1713 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1714 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1715 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1716 && targetm
.slow_unaligned_access (innermode
,
1720 *curr_id
->operand_loc
[nop
] = operand
;
1722 /* But if the address was not valid, we cannot reload the MEM without
1723 reloading the address first. */
1724 if (!addr_was_valid
)
1725 process_address (nop
, false, &before
, &after
);
1727 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1728 enum reg_class rclass
1729 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1730 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1732 true, "slow/invalid mem", &new_reg
))
1734 bool insert_before
, insert_after
;
1735 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1737 insert_before
= (type
!= OP_OUT
1738 || partial_subreg_p (mode
, innermode
));
1739 insert_after
= type
!= OP_IN
;
1740 insert_move_for_subreg (insert_before
? &before
: NULL
,
1741 insert_after
? &after
: NULL
,
1744 SUBREG_REG (operand
) = new_reg
;
1746 /* Convert to MODE. */
1749 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1750 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1752 true, "slow/invalid mem", &new_reg
))
1754 bool insert_before
, insert_after
;
1755 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1757 insert_before
= type
!= OP_OUT
;
1758 insert_after
= type
!= OP_IN
;
1759 insert_move_for_subreg (insert_before
? &before
: NULL
,
1760 insert_after
? &after
: NULL
,
1763 *curr_id
->operand_loc
[nop
] = new_reg
;
1764 lra_process_new_insns (curr_insn
, before
, after
,
1765 "Inserting slow/invalid mem reload");
1769 /* If the address was valid and became invalid, prefer to reload
1770 the memory. Typical case is when the index scale should
1771 correspond the memory. */
1772 *curr_id
->operand_loc
[nop
] = operand
;
1773 /* Do not return false here as the MEM_P (reg) will be processed
1774 later in this function. */
1776 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1778 alter_subreg (curr_id
->operand_loc
[nop
], false);
1781 else if (CONSTANT_P (reg
))
1783 /* Try to simplify subreg of constant. It is usually result of
1784 equivalence substitution. */
1785 if (innermode
== VOIDmode
1786 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1787 innermode
= curr_static_id
->operand
[nop
].mode
;
1788 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1789 SUBREG_BYTE (operand
))) != NULL_RTX
)
1791 *curr_id
->operand_loc
[nop
] = new_reg
;
1795 /* Put constant into memory when we have mixed modes. It generates
1796 a better code in most cases as it does not need a secondary
1797 reload memory. It also prevents LRA looping when LRA is using
1798 secondary reload memory again and again. */
1799 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1800 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1802 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1803 alter_subreg (curr_id
->operand_loc
[nop
], false);
1806 auto fp_subreg_can_be_simplified_after_reload_p
= [] (machine_mode innermode
,
1808 machine_mode mode
) {
1809 reload_completed
= 1;
1810 bool res
= simplify_subreg_regno (FRAME_POINTER_REGNUM
,
1813 reload_completed
= 0;
1816 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1817 if there may be a problem accessing OPERAND in the outer
1820 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1821 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1822 /* Don't reload paradoxical subregs because we could be looping
1823 having repeatedly final regno out of hard regs range. */
1824 && (hard_regno_nregs (hard_regno
, innermode
)
1825 >= hard_regno_nregs (hard_regno
, mode
))
1826 && simplify_subreg_regno (hard_regno
, innermode
,
1827 SUBREG_BYTE (operand
), mode
) < 0
1828 /* Exclude reloading of frame pointer in subreg if frame pointer can not
1829 be simplified here only because the reload is not finished yet. */
1830 && (hard_regno
!= FRAME_POINTER_REGNUM
1831 || !fp_subreg_can_be_simplified_after_reload_p (innermode
,
1832 SUBREG_BYTE (operand
),
1834 /* Don't reload subreg for matching reload. It is actually
1835 valid subreg in LRA. */
1836 && ! LRA_SUBREG_P (operand
))
1837 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1839 enum reg_class rclass
;
1842 /* There is a big probability that we will get the same class
1843 for the new pseudo and we will get the same insn which
1844 means infinite looping. So spill the new pseudo. */
1847 /* The class will be defined later in curr_insn_transform. */
1849 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1851 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1853 true, "subreg reg", &new_reg
))
1855 bool insert_before
, insert_after
;
1856 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1858 insert_before
= (type
!= OP_OUT
1859 || read_modify_subreg_p (operand
));
1860 insert_after
= (type
!= OP_IN
);
1861 insert_move_for_subreg (insert_before
? &before
: NULL
,
1862 insert_after
? &after
: NULL
,
1865 SUBREG_REG (operand
) = new_reg
;
1866 lra_process_new_insns (curr_insn
, before
, after
,
1867 "Inserting subreg reload");
1870 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1871 IRA allocates hardreg to the inner pseudo reg according to its mode
1872 instead of the outermode, so the size of the hardreg may not be enough
1873 to contain the outermode operand, in that case we may need to insert
1874 reload for the reg. For the following two types of paradoxical subreg,
1875 we need to insert reload:
1876 1. If the op_type is OP_IN, and the hardreg could not be paired with
1877 other hardreg to contain the outermode operand
1878 (checked by in_hard_reg_set_p), we need to insert the reload.
1879 2. If the op_type is OP_OUT or OP_INOUT.
1881 Here is a paradoxical subreg example showing how the reload is generated:
1883 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1884 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1886 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1887 here, if reg107 is assigned to hardreg R15, because R15 is the last
1888 hardreg, compiler cannot find another hardreg to pair with R15 to
1889 contain TImode data. So we insert a TImode reload reg180 for it.
1890 After reload is inserted:
1892 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1893 (reg:DI 107 [ __comp ])) -1
1894 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1895 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1897 Two reload hard registers will be allocated to reg180 to save TImode data
1900 For LRA pseudos this should normally be handled by the biggest_mode
1901 mechanism. However, it's possible for new uses of an LRA pseudo
1902 to be introduced after we've allocated it, such as when undoing
1903 inheritance, and the allocated register might not then be appropriate
1904 for the new uses. */
1905 else if (REG_P (reg
)
1906 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1907 && paradoxical_subreg_p (operand
)
1908 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1910 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1911 SUBREG_BYTE (operand
), mode
)) < 0
1912 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1913 < hard_regno_nregs (hard_regno
, mode
))
1914 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1916 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1918 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1919 mode
, hard_regno
)))))
1921 /* The class will be defined later in curr_insn_transform. */
1922 enum reg_class rclass
1923 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1925 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1927 true, "paradoxical subreg", &new_reg
))
1930 bool insert_before
, insert_after
;
1932 PUT_MODE (new_reg
, mode
);
1933 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1934 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1936 insert_before
= (type
!= OP_OUT
);
1937 insert_after
= (type
!= OP_IN
);
1938 insert_move_for_subreg (insert_before
? &before
: NULL
,
1939 insert_after
? &after
: NULL
,
1942 SUBREG_REG (operand
) = new_reg
;
1943 lra_process_new_insns (curr_insn
, before
, after
,
1944 "Inserting paradoxical subreg reload");
1950 /* Return TRUE if X refers for a hard register from SET. */
1952 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1954 int i
, j
, x_hard_regno
;
1961 code
= GET_CODE (x
);
1962 mode
= GET_MODE (x
);
1966 /* For all SUBREGs we want to check whether the full multi-register
1967 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1968 the inner register, for paradoxical SUBREGs this means the
1969 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1970 fine. Use the wider mode for all cases. */
1971 rtx subreg
= SUBREG_REG (x
);
1972 mode
= wider_subreg_mode (x
);
1973 if (mode
== GET_MODE (subreg
))
1976 code
= GET_CODE (x
);
1980 if (REG_P (x
) || SUBREG_P (x
))
1982 x_hard_regno
= get_hard_regno (x
);
1983 return (x_hard_regno
>= 0
1984 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1986 fmt
= GET_RTX_FORMAT (code
);
1987 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1991 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1994 else if (fmt
[i
] == 'E')
1996 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1997 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
2004 /* Return true if OP is a spilled pseudo. */
2006 spilled_pseudo_p (rtx op
)
2009 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
2012 /* Return true if X is a general constant. */
2014 general_constant_p (rtx x
)
2016 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
2020 reg_in_class_p (rtx reg
, enum reg_class cl
)
2023 return get_reg_class (REGNO (reg
)) == NO_REGS
;
2024 return in_class_p (reg
, cl
, NULL
);
2027 /* Return true if SET of RCLASS contains no hard regs which can be
2030 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
2036 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
2037 temp
= set
& ~lra_no_alloc_regs
;
2038 return (hard_reg_set_subset_p
2039 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
2043 /* Used to check validity info about small class input operands. It
2044 should be incremented at start of processing an insn
2046 static unsigned int curr_small_class_check
= 0;
2048 /* Update number of used inputs of class OP_CLASS for operand NOP
2049 of alternative NALT. Return true if we have more such class operands
2050 than the number of available regs. */
2052 update_and_check_small_class_inputs (int nop
, int nalt
,
2053 enum reg_class op_class
)
2055 static unsigned int small_class_check
[LIM_REG_CLASSES
];
2056 static int small_class_input_nums
[LIM_REG_CLASSES
];
2058 if (SMALL_REGISTER_CLASS_P (op_class
)
2059 /* We are interesting in classes became small because of fixing
2060 some hard regs, e.g. by an user through GCC options. */
2061 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
2063 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
2064 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
2066 if (small_class_check
[op_class
] == curr_small_class_check
)
2067 small_class_input_nums
[op_class
]++;
2070 small_class_check
[op_class
] = curr_small_class_check
;
2071 small_class_input_nums
[op_class
] = 1;
2073 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
2079 /* Print operand constraints for alternative ALT_NUMBER of the current
2082 print_curr_insn_alt (int alt_number
)
2084 for (int i
= 0; i
< curr_static_id
->n_operands
; i
++)
2086 const char *p
= (curr_static_id
->operand_alternative
2087 [alt_number
* curr_static_id
->n_operands
+ i
].constraint
);
2090 fprintf (lra_dump_file
, " (%d) ", i
);
2091 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2092 fputc (*p
, lra_dump_file
);
2096 /* Major function to choose the current insn alternative and what
2097 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2098 negative we should consider only this alternative. Return false if
2099 we cannot choose the alternative or find how to reload the
2102 process_alt_operands (int only_alternative
)
2105 int nop
, overall
, nalt
;
2106 int n_alternatives
= curr_static_id
->n_alternatives
;
2107 int n_operands
= curr_static_id
->n_operands
;
2108 /* LOSERS counts the operands that don't fit this alternative and
2109 would require loading. */
2112 /* REJECT is a count of how undesirable this alternative says it is
2113 if any reloading is required. If the alternative matches exactly
2114 then REJECT is ignored, but otherwise it gets this much counted
2115 against it in addition to the reloading needed. */
2117 /* This is defined by '!' or '?' alternative constraint and added to
2118 reject. But in some cases it can be ignored. */
2121 /* The number of elements in the following array. */
2122 int early_clobbered_regs_num
;
2123 /* Numbers of operands which are early clobber registers. */
2124 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
2125 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
2126 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
2127 HARD_REG_SET curr_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
2128 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
2129 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
2130 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
2131 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
2132 /* The number of elements in the following array. */
2133 int curr_alt_dont_inherit_ops_num
;
2134 /* Numbers of operands whose reload pseudos should not be inherited. */
2135 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
2136 bool curr_reuse_alt_p
;
2137 /* True if output stack pointer reload should be generated for the current
2139 bool curr_alt_out_sp_reload_p
;
2141 /* The register when the operand is a subreg of register, otherwise the
2143 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
2144 /* The register if the operand is a register or subreg of register,
2146 rtx operand_reg
[MAX_RECOG_OPERANDS
];
2147 int hard_regno
[MAX_RECOG_OPERANDS
];
2148 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
2149 int reload_nregs
, reload_sum
;
2153 /* Calculate some data common for all alternatives to speed up the
2155 for (nop
= 0; nop
< n_operands
; nop
++)
2159 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
2160 /* The real hard regno of the operand after the allocation. */
2161 hard_regno
[nop
] = get_hard_regno (op
);
2163 operand_reg
[nop
] = reg
= op
;
2164 biggest_mode
[nop
] = GET_MODE (op
);
2165 if (GET_CODE (op
) == SUBREG
)
2167 biggest_mode
[nop
] = wider_subreg_mode (op
);
2168 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
2171 operand_reg
[nop
] = NULL_RTX
;
2172 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2173 || ((int) REGNO (reg
)
2174 == lra_get_elimination_hard_regno (REGNO (reg
))))
2175 no_subreg_reg_operand
[nop
] = reg
;
2177 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
2178 /* Just use natural mode for elimination result. It should
2179 be enough for extra constraints hooks. */
2180 = regno_reg_rtx
[hard_regno
[nop
]];
2183 /* The constraints are made of several alternatives. Each operand's
2184 constraint looks like foo,bar,... with commas separating the
2185 alternatives. The first alternatives for all operands go
2186 together, the second alternatives go together, etc.
2188 First loop over alternatives. */
2189 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2190 if (only_alternative
>= 0)
2191 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2193 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2195 /* Loop over operands for one constraint alternative. */
2196 if (!TEST_BIT (preferred
, nalt
))
2199 if (lra_dump_file
!= NULL
)
2201 fprintf (lra_dump_file
, " Considering alt=%d of insn %d: ",
2202 nalt
, INSN_UID (curr_insn
));
2203 print_curr_insn_alt (nalt
);
2204 fprintf (lra_dump_file
, "\n");
2207 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2208 curr_small_class_check
++;
2209 overall
= losers
= addr_losers
= 0;
2210 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2211 for (nop
= 0; nop
< n_operands
; nop
++)
2213 int inc
= (curr_static_id
2214 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2215 if (lra_dump_file
!= NULL
&& inc
!= 0)
2216 fprintf (lra_dump_file
,
2217 " Staticly defined alt reject+=%d\n", inc
);
2218 static_reject
+= inc
;
2219 matching_early_clobber
[nop
] = 0;
2221 reject
+= static_reject
;
2222 early_clobbered_regs_num
= 0;
2223 curr_alt_out_sp_reload_p
= false;
2224 curr_reuse_alt_p
= true;
2226 for (nop
= 0; nop
< n_operands
; nop
++)
2230 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2231 bool win
, did_match
, offmemok
, early_clobber_p
;
2232 /* false => this operand can be reloaded somehow for this
2235 /* true => this operand can be reloaded if the alternative
2238 /* True if a constant forced into memory would be OK for
2241 enum reg_class this_alternative
, this_costly_alternative
;
2242 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2243 HARD_REG_SET this_alternative_exclude_start_hard_regs
;
2244 bool this_alternative_match_win
, this_alternative_win
;
2245 bool this_alternative_offmemok
;
2248 enum constraint_num cn
;
2250 opalt_num
= nalt
* n_operands
+ nop
;
2251 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2253 /* Fast track for no constraints at all. */
2254 curr_alt
[nop
] = NO_REGS
;
2255 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2256 curr_alt_win
[nop
] = true;
2257 curr_alt_match_win
[nop
] = false;
2258 curr_alt_offmemok
[nop
] = false;
2259 curr_alt_matches
[nop
] = -1;
2263 op
= no_subreg_reg_operand
[nop
];
2264 mode
= curr_operand_mode
[nop
];
2266 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2269 early_clobber_p
= false;
2270 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2272 this_costly_alternative
= this_alternative
= NO_REGS
;
2273 /* We update set of possible hard regs besides its class
2274 because reg class might be inaccurate. For example,
2275 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2276 is translated in HI_REGS because classes are merged by
2277 pairs and there is no accurate intermediate class. */
2278 CLEAR_HARD_REG_SET (this_alternative_set
);
2279 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2280 CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs
);
2281 this_alternative_win
= false;
2282 this_alternative_match_win
= false;
2283 this_alternative_offmemok
= false;
2284 this_alternative_matches
= -1;
2286 /* An empty constraint should be excluded by the fast
2288 lra_assert (*p
!= 0 && *p
!= ',');
2291 /* Scan this alternative's specs for this operand; set WIN
2292 if the operand fits any letter in this alternative.
2293 Otherwise, clear BADOP if this operand could fit some
2294 letter after reloads, or set WINREG if this operand could
2295 fit after reloads provided the constraint allows some
2300 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2310 early_clobber_p
= true;
2314 op_reject
+= LRA_MAX_REJECT
;
2317 op_reject
+= LRA_LOSER_COST_FACTOR
;
2321 /* Ignore rest of this alternative. */
2325 case '0': case '1': case '2': case '3': case '4':
2326 case '5': case '6': case '7': case '8': case '9':
2331 m
= strtoul (p
, &end
, 10);
2334 lra_assert (nop
> m
);
2336 /* Reject matches if we don't know which operand is
2337 bigger. This situation would arguably be a bug in
2338 an .md pattern, but could also occur in a user asm. */
2339 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2340 GET_MODE_SIZE (biggest_mode
[nop
])))
2343 /* Don't match wrong asm insn operands for proper
2344 diagnostic later. */
2345 if (INSN_CODE (curr_insn
) < 0
2346 && (curr_operand_mode
[m
] == BLKmode
2347 || curr_operand_mode
[nop
] == BLKmode
)
2348 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2351 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
2352 /* We are supposed to match a previous operand.
2353 If we do, we win if that one did. If we do
2354 not, count both of the operands as losers.
2355 (This is too conservative, since most of the
2356 time only a single reload insn will be needed
2357 to make the two operands win. As a result,
2358 this alternative may be rejected when it is
2359 actually desirable.) */
2361 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2362 *curr_id
->operand_loc
[m
], m_hregno
))
2364 /* We should reject matching of an early
2365 clobber operand if the matching operand is
2366 not dying in the insn. */
2367 if (!TEST_BIT (curr_static_id
->operand
[m
]
2368 .early_clobber_alts
, nalt
)
2369 || operand_reg
[nop
] == NULL_RTX
2370 || (find_regno_note (curr_insn
, REG_DEAD
,
2372 || REGNO (op
) == REGNO (operand_reg
[m
])))
2377 /* If we are matching a non-offsettable
2378 address where an offsettable address was
2379 expected, then we must reject this
2380 combination, because we can't reload
2382 if (curr_alt_offmemok
[m
]
2383 && MEM_P (*curr_id
->operand_loc
[m
])
2384 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2389 /* If the operands do not match and one
2390 operand is INOUT, we can not match them.
2391 Try other possibilities, e.g. other
2392 alternatives or commutative operand
2394 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2395 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2397 /* Operands don't match. If the operands are
2398 different user defined explicit hard
2399 registers, then we cannot make them match
2400 when one is early clobber operand. */
2401 if ((REG_P (*curr_id
->operand_loc
[nop
])
2402 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2403 && (REG_P (*curr_id
->operand_loc
[m
])
2404 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2406 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2407 if (SUBREG_P (nop_reg
))
2408 nop_reg
= SUBREG_REG (nop_reg
);
2409 rtx m_reg
= *curr_id
->operand_loc
[m
];
2410 if (SUBREG_P (m_reg
))
2411 m_reg
= SUBREG_REG (m_reg
);
2414 && HARD_REGISTER_P (nop_reg
)
2415 && REG_USERVAR_P (nop_reg
)
2417 && HARD_REGISTER_P (m_reg
)
2418 && REG_USERVAR_P (m_reg
))
2422 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2423 if (m
== early_clobbered_nops
[i
])
2425 if (i
< early_clobbered_regs_num
2430 /* Both operands must allow a reload register,
2431 otherwise we cannot make them match. */
2432 if (curr_alt
[m
] == NO_REGS
)
2434 /* Retroactively mark the operand we had to
2435 match as a loser, if it wasn't already and
2436 it wasn't matched to a register constraint
2437 (e.g it might be matched by memory). */
2439 && (operand_reg
[m
] == NULL_RTX
2440 || hard_regno
[m
] < 0))
2444 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2445 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2448 /* Prefer matching earlyclobber alternative as
2449 it results in less hard regs required for
2450 the insn than a non-matching earlyclobber
2452 if (TEST_BIT (curr_static_id
->operand
[m
]
2453 .early_clobber_alts
, nalt
))
2455 if (lra_dump_file
!= NULL
)
2458 " %d Matching earlyclobber alt:"
2461 if (!matching_early_clobber
[m
])
2464 matching_early_clobber
[m
] = 1;
2467 /* Otherwise we prefer no matching
2468 alternatives because it gives more freedom
2470 else if (operand_reg
[nop
] == NULL_RTX
2471 || (find_regno_note (curr_insn
, REG_DEAD
,
2472 REGNO (operand_reg
[nop
]))
2475 if (lra_dump_file
!= NULL
)
2478 " %d Matching alt: reject+=2\n",
2483 /* If we have to reload this operand and some
2484 previous operand also had to match the same
2485 thing as this operand, we don't know how to do
2487 if (!match_p
|| !curr_alt_win
[m
])
2489 for (i
= 0; i
< nop
; i
++)
2490 if (curr_alt_matches
[i
] == m
)
2498 this_alternative_matches
= m
;
2499 /* This can be fixed with reloads if the operand
2500 we are supposed to match can be fixed with
2503 this_alternative
= curr_alt
[m
];
2504 this_alternative_set
= curr_alt_set
[m
];
2505 this_alternative_exclude_start_hard_regs
2506 = curr_alt_exclude_start_hard_regs
[m
];
2507 winreg
= this_alternative
!= NO_REGS
;
2513 || general_constant_p (op
)
2514 || spilled_pseudo_p (op
))
2520 cn
= lookup_constraint (p
);
2521 switch (get_constraint_type (cn
))
2524 cl
= reg_class_for_constraint (cn
);
2530 if (CONST_INT_P (op
)
2531 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2536 case CT_RELAXED_MEMORY
:
2538 && satisfies_memory_constraint_p (op
, cn
))
2540 else if (spilled_pseudo_p (op
))
2543 /* If we didn't already win, we can reload constants
2544 via force_const_mem or put the pseudo value into
2545 memory, or make other memory by reloading the
2546 address like for 'o'. */
2547 if (CONST_POOL_OK_P (mode
, op
)
2548 || MEM_P (op
) || REG_P (op
)
2549 /* We can restore the equiv insn by a
2551 || equiv_substition_p
[nop
])
2558 /* An asm operand with an address constraint
2559 that doesn't satisfy address_operand has
2560 is_address cleared, so that we don't try to
2561 make a non-address fit. */
2562 if (!curr_static_id
->operand
[nop
].is_address
)
2564 /* If we didn't already win, we can reload the address
2565 into a base register. */
2566 if (satisfies_address_constraint_p (op
, cn
))
2568 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2574 if (constraint_satisfied_p (op
, cn
))
2578 case CT_SPECIAL_MEMORY
:
2579 if (satisfies_memory_constraint_p (op
, cn
))
2581 else if (spilled_pseudo_p (op
))
2583 curr_reuse_alt_p
= false;
2591 if (mode
== BLKmode
)
2593 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2594 if (hard_reg_set_subset_p (this_alternative_set
,
2595 reg_class_contents
[cl
]))
2596 this_alternative_exclude_start_hard_regs
2597 = ira_exclude_class_mode_regs
[cl
][mode
];
2598 else if (!hard_reg_set_subset_p (reg_class_contents
[cl
],
2599 this_alternative_set
))
2600 this_alternative_exclude_start_hard_regs
2601 |= ira_exclude_class_mode_regs
[cl
][mode
];
2602 this_alternative_set
|= reg_class_contents
[cl
];
2605 this_costly_alternative
2606 = reg_class_subunion
[this_costly_alternative
][cl
];
2607 this_costly_alternative_set
|= reg_class_contents
[cl
];
2612 if (hard_regno
[nop
] >= 0
2613 && in_hard_reg_set_p (this_alternative_set
,
2614 mode
, hard_regno
[nop
])
2615 && !TEST_HARD_REG_BIT
2616 (this_alternative_exclude_start_hard_regs
,
2619 else if (hard_regno
[nop
] < 0
2620 && in_class_p (op
, this_alternative
, NULL
))
2625 if (c
!= ' ' && c
!= '\t')
2626 costly_p
= c
== '*';
2628 while ((p
+= len
), c
);
2630 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2631 && ira_former_scratch_p (REGNO (operand_reg
[nop
])));
2632 /* Record which operands fit this alternative. */
2635 this_alternative_win
= true;
2636 if (operand_reg
[nop
] != NULL_RTX
)
2638 if (hard_regno
[nop
] >= 0)
2640 if (in_hard_reg_set_p (this_costly_alternative_set
,
2641 mode
, hard_regno
[nop
]))
2643 if (lra_dump_file
!= NULL
)
2644 fprintf (lra_dump_file
,
2645 " %d Costly set: reject++\n",
2652 /* Prefer won reg to spilled pseudo under other
2653 equal conditions for possibe inheritance. */
2656 if (lra_dump_file
!= NULL
)
2659 " %d Non pseudo reload: reject++\n",
2663 if (in_class_p (operand_reg
[nop
],
2664 this_costly_alternative
, NULL
))
2666 if (lra_dump_file
!= NULL
)
2669 " %d Non pseudo costly reload:"
2675 /* We simulate the behavior of old reload here.
2676 Although scratches need hard registers and it
2677 might result in spilling other pseudos, no reload
2678 insns are generated for the scratches. So it
2679 might cost something but probably less than old
2680 reload pass believes. */
2683 if (lra_dump_file
!= NULL
)
2684 fprintf (lra_dump_file
,
2685 " %d Scratch win: reject+=2\n",
2692 this_alternative_match_win
= true;
2695 int const_to_mem
= 0;
2698 reject
+= op_reject
;
2699 /* Mark output reload of the stack pointer. */
2700 if (op
== stack_pointer_rtx
2701 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2702 curr_alt_out_sp_reload_p
= true;
2704 /* If this alternative asks for a specific reg class, see if there
2705 is at least one allocatable register in that class. */
2707 = (this_alternative
== NO_REGS
2708 || (hard_reg_set_subset_p
2709 (reg_class_contents
[this_alternative
],
2710 lra_no_alloc_regs
)));
2712 /* For asms, verify that the class for this alternative is possible
2713 for the mode that is specified. */
2714 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2717 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2718 if (targetm
.hard_regno_mode_ok (i
, mode
)
2719 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2722 if (i
== FIRST_PSEUDO_REGISTER
)
2726 /* If this operand accepts a register, and if the
2727 register class has at least one allocatable register,
2728 then this operand can be reloaded. */
2729 if (winreg
&& !no_regs_p
)
2734 if (lra_dump_file
!= NULL
)
2735 fprintf (lra_dump_file
,
2736 " Bad operand -- refuse\n");
2740 if (this_alternative
!= NO_REGS
)
2742 HARD_REG_SET available_regs
2743 = (reg_class_contents
[this_alternative
]
2744 & ~((ira_prohibited_class_mode_regs
2745 [this_alternative
][mode
])
2746 | lra_no_alloc_regs
));
2747 if (hard_reg_set_empty_p (available_regs
))
2749 /* There are no hard regs holding a value of given
2753 this_alternative
= NO_REGS
;
2754 if (lra_dump_file
!= NULL
)
2755 fprintf (lra_dump_file
,
2756 " %d Using memory because of"
2757 " a bad mode: reject+=2\n",
2763 if (lra_dump_file
!= NULL
)
2764 fprintf (lra_dump_file
,
2765 " Wrong mode -- refuse\n");
2771 /* If not assigned pseudo has a class which a subset of
2772 required reg class, it is a less costly alternative
2773 as the pseudo still can get a hard reg of necessary
2775 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2776 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2777 && ira_class_subset_p
[this_alternative
][cl
])
2779 if (lra_dump_file
!= NULL
)
2782 " %d Super set class reg: reject-=3\n", nop
);
2786 this_alternative_offmemok
= offmemok
;
2787 if (this_costly_alternative
!= NO_REGS
)
2789 if (lra_dump_file
!= NULL
)
2790 fprintf (lra_dump_file
,
2791 " %d Costly loser: reject++\n", nop
);
2794 /* If the operand is dying, has a matching constraint,
2795 and satisfies constraints of the matched operand
2796 which failed to satisfy the own constraints, most probably
2797 the reload for this operand will be gone. */
2798 if (this_alternative_matches
>= 0
2799 && !curr_alt_win
[this_alternative_matches
]
2801 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2802 && (hard_regno
[nop
] >= 0
2803 ? in_hard_reg_set_p (this_alternative_set
,
2804 mode
, hard_regno
[nop
])
2805 : in_class_p (op
, this_alternative
, NULL
)))
2807 if (lra_dump_file
!= NULL
)
2810 " %d Dying matched operand reload: reject++\n",
2816 /* Strict_low_part requires to reload the register
2817 not the sub-register. In this case we should
2818 check that a final reload hard reg can hold the
2820 if (curr_static_id
->operand
[nop
].strict_low
2822 && hard_regno
[nop
] < 0
2823 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2824 && ira_class_hard_regs_num
[this_alternative
] > 0
2825 && (!targetm
.hard_regno_mode_ok
2826 (ira_class_hard_regs
[this_alternative
][0],
2827 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2829 if (lra_dump_file
!= NULL
)
2832 " Strict low subreg reload -- refuse\n");
2837 if (operand_reg
[nop
] != NULL_RTX
2838 /* Output operands and matched input operands are
2839 not inherited. The following conditions do not
2840 exactly describe the previous statement but they
2841 are pretty close. */
2842 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2843 && (this_alternative_matches
< 0
2844 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2846 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2850 /* The value of reload_sum has sense only if we
2851 process insns in their order. It happens only on
2852 the first constraints sub-pass when we do most of
2854 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2855 reload_sum
+= last_reload
- bb_reload_num
;
2857 /* If this is a constant that is reloaded into the
2858 desired class by copying it to memory first, count
2859 that as another reload. This is consistent with
2860 other code and is required to avoid choosing another
2861 alternative when the constant is moved into memory.
2862 Note that the test here is precisely the same as in
2863 the code below that calls force_const_mem. */
2864 if (CONST_POOL_OK_P (mode
, op
)
2865 && ((targetm
.preferred_reload_class
2866 (op
, this_alternative
) == NO_REGS
)
2867 || no_input_reloads_p
))
2874 /* Alternative loses if it requires a type of reload not
2875 permitted for this insn. We can always reload
2876 objects with a REG_UNUSED note. */
2877 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2878 && no_output_reloads_p
2879 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2880 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2881 && no_input_reloads_p
&& ! const_to_mem
)
2882 || (this_alternative_matches
>= 0
2883 && (no_input_reloads_p
2884 || (no_output_reloads_p
2885 && (curr_static_id
->operand
2886 [this_alternative_matches
].type
!= OP_IN
)
2887 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2888 no_subreg_reg_operand
2889 [this_alternative_matches
])))))
2891 if (lra_dump_file
!= NULL
)
2894 " No input/output reload -- refuse\n");
2898 /* Alternative loses if it required class pseudo cannot
2899 hold value of required mode. Such insns can be
2900 described by insn definitions with mode iterators. */
2901 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2902 && ! hard_reg_set_empty_p (this_alternative_set
)
2903 /* It is common practice for constraints to use a
2904 class which does not have actually enough regs to
2905 hold the value (e.g. x86 AREG for mode requiring
2906 more one general reg). Therefore we have 2
2907 conditions to check that the reload pseudo cannot
2908 hold the mode value. */
2909 && (!targetm
.hard_regno_mode_ok
2910 (ira_class_hard_regs
[this_alternative
][0],
2911 GET_MODE (*curr_id
->operand_loc
[nop
])))
2912 /* The above condition is not enough as the first
2913 reg in ira_class_hard_regs can be not aligned for
2914 multi-words mode values. */
2915 && (prohibited_class_reg_set_mode_p
2916 (this_alternative
, this_alternative_set
,
2917 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2919 if (lra_dump_file
!= NULL
)
2920 fprintf (lra_dump_file
,
2921 " reload pseudo for op %d "
2922 "cannot hold the mode value -- refuse\n",
2927 /* Check strong discouragement of reload of non-constant
2928 into class THIS_ALTERNATIVE. */
2929 if (! CONSTANT_P (op
) && ! no_regs_p
2930 && (targetm
.preferred_reload_class
2931 (op
, this_alternative
) == NO_REGS
2932 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2933 && (targetm
.preferred_output_reload_class
2934 (op
, this_alternative
) == NO_REGS
))))
2936 if (offmemok
&& REG_P (op
))
2938 if (lra_dump_file
!= NULL
)
2941 " %d Spill pseudo into memory: reject+=3\n",
2947 if (lra_dump_file
!= NULL
)
2950 " %d Non-prefered reload: reject+=%d\n",
2951 nop
, LRA_MAX_REJECT
);
2952 reject
+= LRA_MAX_REJECT
;
2956 if (! (MEM_P (op
) && offmemok
)
2957 && ! (const_to_mem
&& constmemok
))
2959 /* We prefer to reload pseudos over reloading other
2960 things, since such reloads may be able to be
2961 eliminated later. So bump REJECT in other cases.
2962 Don't do this in the case where we are forcing a
2963 constant into memory and it will then win since
2964 we don't want to have a different alternative
2966 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2968 if (lra_dump_file
!= NULL
)
2971 " %d Non-pseudo reload: reject+=2\n",
2978 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2980 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2982 if (lra_dump_file
!= NULL
)
2985 " %d Small class reload: reject+=%d\n",
2986 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2987 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2991 /* We are trying to spill pseudo into memory. It is
2992 usually more costly than moving to a hard register
2993 although it might takes the same number of
2996 Non-pseudo spill may happen also. Suppose a target allows both
2997 register and memory in the operand constraint alternatives,
2998 then it's typical that an eliminable register has a substition
2999 of "base + offset" which can either be reloaded by a simple
3000 "new_reg <= base + offset" which will match the register
3001 constraint, or a similar reg addition followed by further spill
3002 to and reload from memory which will match the memory
3003 constraint, but this memory spill will be much more costly
3006 Code below increases the reject for both pseudo and non-pseudo
3009 && !(MEM_P (op
) && offmemok
)
3010 && !(REG_P (op
) && hard_regno
[nop
] < 0))
3012 if (lra_dump_file
!= NULL
)
3015 " %d Spill %spseudo into memory: reject+=3\n",
3016 nop
, REG_P (op
) ? "" : "Non-");
3018 if (VECTOR_MODE_P (mode
))
3020 /* Spilling vectors into memory is usually more
3021 costly as they contain big values. */
3022 if (lra_dump_file
!= NULL
)
3025 " %d Spill vector pseudo: reject+=2\n",
3031 /* When we use an operand requiring memory in given
3032 alternative, the insn should write *and* read the
3033 value to/from memory it is costly in comparison with
3034 an insn alternative which does not use memory
3035 (e.g. register or immediate operand). We exclude
3036 memory operand for such case as we can satisfy the
3037 memory constraints by reloading address. */
3038 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
3040 if (lra_dump_file
!= NULL
)
3043 " Using memory insn operand %d: reject+=3\n",
3048 /* If reload requires moving value through secondary
3049 memory, it will need one more insn at least. */
3050 if (this_alternative
!= NO_REGS
3051 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
3052 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
3053 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
3055 || (curr_static_id
->operand
[nop
].type
!= OP_IN
3056 && (targetm
.secondary_memory_needed
3057 (GET_MODE (op
), this_alternative
, cl
)))))
3060 if (MEM_P (op
) && offmemok
)
3064 /* Input reloads can be inherited more often than
3065 output reloads can be removed, so penalize output
3067 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
3069 if (lra_dump_file
!= NULL
)
3072 " %d Non input pseudo reload: reject++\n",
3077 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
3079 if (lra_dump_file
!= NULL
)
3082 " %d Input/Output reload: reject+=%d\n",
3083 nop
, LRA_LOSER_COST_FACTOR
);
3084 reject
+= LRA_LOSER_COST_FACTOR
;
3089 if (early_clobber_p
&& ! scratch_p
)
3091 if (lra_dump_file
!= NULL
)
3092 fprintf (lra_dump_file
,
3093 " %d Early clobber: reject++\n", nop
);
3096 /* ??? We check early clobbers after processing all operands
3097 (see loop below) and there we update the costs more.
3098 Should we update the cost (may be approximately) here
3099 because of early clobber register reloads or it is a rare
3100 or non-important thing to be worth to do it. */
3101 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
3102 - (addr_losers
== losers
? static_reject
: 0));
3103 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
3105 if (lra_dump_file
!= NULL
)
3106 fprintf (lra_dump_file
,
3107 " overall=%d,losers=%d -- refuse\n",
3112 if (update_and_check_small_class_inputs (nop
, nalt
,
3115 if (lra_dump_file
!= NULL
)
3116 fprintf (lra_dump_file
,
3117 " not enough small class regs -- refuse\n");
3120 curr_alt
[nop
] = this_alternative
;
3121 curr_alt_set
[nop
] = this_alternative_set
;
3122 curr_alt_exclude_start_hard_regs
[nop
]
3123 = this_alternative_exclude_start_hard_regs
;
3124 curr_alt_win
[nop
] = this_alternative_win
;
3125 curr_alt_match_win
[nop
] = this_alternative_match_win
;
3126 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
3127 curr_alt_matches
[nop
] = this_alternative_matches
;
3129 if (this_alternative_matches
>= 0
3130 && !did_match
&& !this_alternative_win
)
3131 curr_alt_win
[this_alternative_matches
] = false;
3133 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
3134 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
3137 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
3138 /* Prevent processing non-move insns. */
3139 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
3140 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
3141 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
3142 && REG_P (no_subreg_reg_operand
[0])
3143 && REG_P (no_subreg_reg_operand
[1])
3144 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3145 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
3146 || (! curr_alt_win
[0] && curr_alt_win
[1]
3147 && REG_P (no_subreg_reg_operand
[1])
3148 /* Check that we reload memory not the memory
3150 && ! (curr_alt_offmemok
[0]
3151 && MEM_P (no_subreg_reg_operand
[0]))
3152 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
3153 || (curr_alt_win
[0] && ! curr_alt_win
[1]
3154 && REG_P (no_subreg_reg_operand
[0])
3155 /* Check that we reload memory not the memory
3157 && ! (curr_alt_offmemok
[1]
3158 && MEM_P (no_subreg_reg_operand
[1]))
3159 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3160 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
3161 no_subreg_reg_operand
[1])
3162 || (targetm
.preferred_reload_class
3163 (no_subreg_reg_operand
[1],
3164 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
3165 /* If it is a result of recent elimination in move
3166 insn we can transform it into an add still by
3167 using this alternative. */
3168 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
3169 /* Likewise if the source has been replaced with an
3170 equivalent value. This only happens once -- the reload
3171 will use the equivalent value instead of the register it
3172 replaces -- so there should be no danger of cycling. */
3173 && !equiv_substition_p
[1])))
3175 /* We have a move insn and a new reload insn will be similar
3176 to the current insn. We should avoid such situation as
3177 it results in LRA cycling. */
3178 if (lra_dump_file
!= NULL
)
3179 fprintf (lra_dump_file
,
3180 " Cycle danger: overall += LRA_MAX_REJECT\n");
3181 overall
+= LRA_MAX_REJECT
;
3184 curr_alt_dont_inherit_ops_num
= 0;
3185 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
3187 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
3188 HARD_REG_SET temp_set
;
3190 i
= early_clobbered_nops
[nop
];
3191 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
3192 || hard_regno
[i
] < 0)
3194 lra_assert (operand_reg
[i
] != NULL_RTX
);
3195 clobbered_hard_regno
= hard_regno
[i
];
3196 CLEAR_HARD_REG_SET (temp_set
);
3197 add_to_hard_reg_set (&temp_set
, GET_MODE (*curr_id
->operand_loc
[i
]),
3198 clobbered_hard_regno
);
3199 first_conflict_j
= last_conflict_j
= -1;
3200 for (j
= 0; j
< n_operands
; j
++)
3202 /* We don't want process insides of match_operator and
3203 match_parallel because otherwise we would process
3204 their operands once again generating a wrong
3206 || curr_static_id
->operand
[j
].is_operator
)
3208 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3209 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3211 /* If we don't reload j-th operand, check conflicts. */
3212 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3213 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3215 if (first_conflict_j
< 0)
3216 first_conflict_j
= j
;
3217 last_conflict_j
= j
;
3218 /* Both the earlyclobber operand and conflicting operand
3219 cannot both be user defined hard registers. */
3220 if (HARD_REGISTER_P (operand_reg
[i
])
3221 && REG_USERVAR_P (operand_reg
[i
])
3222 && operand_reg
[j
] != NULL_RTX
3223 && HARD_REGISTER_P (operand_reg
[j
])
3224 && REG_USERVAR_P (operand_reg
[j
]))
3226 /* For asm, let curr_insn_transform diagnose it. */
3227 if (INSN_CODE (curr_insn
) < 0)
3229 fatal_insn ("unable to generate reloads for "
3230 "impossible constraints:", curr_insn
);
3233 if (last_conflict_j
< 0)
3236 /* If an earlyclobber operand conflicts with another non-matching
3237 operand (ie, they have been assigned the same hard register),
3238 then it is better to reload the other operand, as there may
3239 exist yet another operand with a matching constraint associated
3240 with the earlyclobber operand. However, if one of the operands
3241 is an explicit use of a hard register, then we must reload the
3242 other non-hard register operand. */
3243 if (HARD_REGISTER_P (operand_reg
[i
])
3244 || (first_conflict_j
== last_conflict_j
3245 && operand_reg
[last_conflict_j
] != NULL_RTX
3246 && !curr_alt_match_win
[last_conflict_j
]
3247 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3249 curr_alt_win
[last_conflict_j
] = false;
3250 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3253 if (lra_dump_file
!= NULL
)
3256 " %d Conflict early clobber reload: reject--\n",
3261 /* We need to reload early clobbered register and the
3262 matched registers. */
3263 for (j
= 0; j
< n_operands
; j
++)
3264 if (curr_alt_matches
[j
] == i
)
3266 curr_alt_match_win
[j
] = false;
3268 overall
+= LRA_LOSER_COST_FACTOR
;
3270 if (! curr_alt_match_win
[i
])
3271 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3274 /* Remember pseudos used for match reloads are never
3276 lra_assert (curr_alt_matches
[i
] >= 0);
3277 curr_alt_win
[curr_alt_matches
[i
]] = false;
3279 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3281 if (lra_dump_file
!= NULL
)
3284 " %d Matched conflict early clobber reloads: "
3288 /* Early clobber was already reflected in REJECT. */
3289 if (!matching_early_clobber
[i
])
3291 lra_assert (reject
> 0);
3293 matching_early_clobber
[i
] = 1;
3295 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3297 if (lra_dump_file
!= NULL
)
3298 fprintf (lra_dump_file
, " overall=%d,losers=%d,rld_nregs=%d\n",
3299 overall
, losers
, reload_nregs
);
3301 /* If this alternative can be made to work by reloading, and it
3302 needs less reloading than the others checked so far, record
3303 it as the chosen goal for reloading. */
3304 if ((best_losers
!= 0 && losers
== 0)
3305 || (((best_losers
== 0 && losers
== 0)
3306 || (best_losers
!= 0 && losers
!= 0))
3307 && (best_overall
> overall
3308 || (best_overall
== overall
3309 /* If the cost of the reloads is the same,
3310 prefer alternative which requires minimal
3311 number of reload regs. */
3312 && (reload_nregs
< best_reload_nregs
3313 || (reload_nregs
== best_reload_nregs
3314 && (best_reload_sum
< reload_sum
3315 || (best_reload_sum
== reload_sum
3316 && nalt
< goal_alt_number
))))))))
3318 for (nop
= 0; nop
< n_operands
; nop
++)
3320 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3321 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3322 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3323 goal_alt
[nop
] = curr_alt
[nop
];
3324 goal_alt_exclude_start_hard_regs
[nop
]
3325 = curr_alt_exclude_start_hard_regs
[nop
];
3326 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3328 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3329 goal_reuse_alt_p
= curr_reuse_alt_p
;
3330 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3331 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3332 goal_alt_swapped
= curr_swapped
;
3333 goal_alt_out_sp_reload_p
= curr_alt_out_sp_reload_p
;
3334 best_overall
= overall
;
3335 best_losers
= losers
;
3336 best_reload_nregs
= reload_nregs
;
3337 best_reload_sum
= reload_sum
;
3338 goal_alt_number
= nalt
;
3341 /* Everything is satisfied. Do not process alternatives
3350 /* Make reload base reg from address AD. */
3352 base_to_reg (struct address_info
*ad
)
3356 rtx new_inner
= NULL_RTX
;
3357 rtx new_reg
= NULL_RTX
;
3359 rtx_insn
*last_insn
= get_last_insn();
3361 lra_assert (ad
->disp
== ad
->disp_term
);
3362 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3363 get_index_code (ad
));
3364 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
, cl
, NULL
,
3366 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3367 ad
->disp_term
== NULL
3370 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3372 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3373 code
= recog_memoized (insn
);
3376 delete_insns_since (last_insn
);
3383 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3385 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3390 lra_assert (ad
->base
== ad
->base_term
);
3391 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3392 get_index_code (ad
));
3393 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
, cl
, NULL
,
3395 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3399 /* Make reload of index part of address AD. Return the new
3402 index_part_to_reg (struct address_info
*ad
)
3406 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3407 INDEX_REG_CLASS
, NULL
, "index term");
3408 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3409 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3413 /* Return true if we can add a displacement to address AD, even if that
3414 makes the address invalid. The fix-up code requires any new address
3415 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3417 can_add_disp_p (struct address_info
*ad
)
3419 return (!ad
->autoinc_p
3420 && ad
->segment
== NULL
3421 && ad
->base
== ad
->base_term
3422 && ad
->disp
== ad
->disp_term
);
3425 /* Make equiv substitution in address AD. Return true if a substitution
3428 equiv_address_substitution (struct address_info
*ad
)
3430 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3432 HOST_WIDE_INT scale
;
3435 base_term
= strip_subreg (ad
->base_term
);
3436 if (base_term
== NULL
)
3437 base_reg
= new_base_reg
= NULL_RTX
;
3440 base_reg
= *base_term
;
3441 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3443 index_term
= strip_subreg (ad
->index_term
);
3444 if (index_term
== NULL
)
3445 index_reg
= new_index_reg
= NULL_RTX
;
3448 index_reg
= *index_term
;
3449 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3451 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3455 if (lra_dump_file
!= NULL
)
3457 fprintf (lra_dump_file
, "Changing address in insn %d ",
3458 INSN_UID (curr_insn
));
3459 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3461 if (base_reg
!= new_base_reg
)
3464 if (REG_P (new_base_reg
))
3466 *base_term
= new_base_reg
;
3469 else if (GET_CODE (new_base_reg
) == PLUS
3470 && REG_P (XEXP (new_base_reg
, 0))
3471 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3472 && can_add_disp_p (ad
))
3475 *base_term
= XEXP (new_base_reg
, 0);
3478 if (ad
->base_term2
!= NULL
)
3479 *ad
->base_term2
= *ad
->base_term
;
3481 if (index_reg
!= new_index_reg
)
3484 if (REG_P (new_index_reg
))
3486 *index_term
= new_index_reg
;
3489 else if (GET_CODE (new_index_reg
) == PLUS
3490 && REG_P (XEXP (new_index_reg
, 0))
3491 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3492 && can_add_disp_p (ad
)
3493 && (scale
= get_index_scale (ad
)))
3495 disp
+= offset
* scale
;
3496 *index_term
= XEXP (new_index_reg
, 0);
3500 if (maybe_ne (disp
, 0))
3502 if (ad
->disp
!= NULL
)
3503 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3506 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3507 update_address (ad
);
3511 if (lra_dump_file
!= NULL
)
3514 fprintf (lra_dump_file
, " -- no change\n");
3517 fprintf (lra_dump_file
, " on equiv ");
3518 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3519 fprintf (lra_dump_file
, "\n");
3525 /* Skip all modifiers and whitespaces in constraint STR and return the
3528 skip_constraint_modifiers (const char *str
)
3533 case '+': case '&' : case '=': case '*': case ' ': case '\t':
3534 case '$': case '^' : case '%': case '?': case '!':
3536 default: return str
;
3540 /* Takes a string of 0 or more comma-separated constraints. When more
3541 than one constraint is present, evaluate whether they all correspond
3542 to a single, repeated constraint (e.g. "r,r") or whether we have
3543 more than one distinct constraints (e.g. "r,m"). */
3545 constraint_unique (const char *cstr
)
3547 enum constraint_num ca
, cb
;
3548 ca
= CONSTRAINT__UNKNOWN
;
3551 cstr
= skip_constraint_modifiers (cstr
);
3552 if (*cstr
== '\0' || *cstr
== ',')
3556 cb
= lookup_constraint (cstr
);
3557 if (cb
== CONSTRAINT__UNKNOWN
)
3559 cstr
+= CONSTRAINT_LEN (cstr
[0], cstr
);
3561 /* Handle the first iteration of the loop. */
3562 if (ca
== CONSTRAINT__UNKNOWN
)
3564 /* Handle the general case of comparing ca with subsequent
3575 /* Major function to make reloads for an address in operand NOP or
3576 check its correctness (If CHECK_ONLY_P is true). The supported
3579 1) an address that existed before LRA started, at which point it
3580 must have been valid. These addresses are subject to elimination
3581 and may have become invalid due to the elimination offset being out
3584 2) an address created by forcing a constant to memory
3585 (force_const_to_mem). The initial form of these addresses might
3586 not be valid, and it is this function's job to make them valid.
3588 3) a frame address formed from a register and a (possibly zero)
3589 constant offset. As above, these addresses might not be valid and
3590 this function must make them so.
3592 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3593 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3594 address. Return true for any RTL change.
3596 The function is a helper function which does not produce all
3597 transformations (when CHECK_ONLY_P is false) which can be
3598 necessary. It does just basic steps. To do all necessary
3599 transformations use function process_address. */
3601 process_address_1 (int nop
, bool check_only_p
,
3602 rtx_insn
**before
, rtx_insn
**after
)
3604 struct address_info ad
;
3606 HOST_WIDE_INT scale
;
3607 rtx op
= *curr_id
->operand_loc
[nop
];
3608 rtx mem
= extract_mem_from_operand (op
);
3609 const char *constraint
;
3610 enum constraint_num cn
;
3611 bool change_p
= false;
3614 && GET_MODE (mem
) == BLKmode
3615 && GET_CODE (XEXP (mem
, 0)) == SCRATCH
)
3619 = skip_constraint_modifiers (curr_static_id
->operand
[nop
].constraint
);
3620 if (IN_RANGE (constraint
[0], '0', '9'))
3623 unsigned long dup
= strtoul (constraint
, &end
, 10);
3625 = skip_constraint_modifiers (curr_static_id
->operand
[dup
].constraint
);
3627 cn
= lookup_constraint (*constraint
== '\0' ? "X" : constraint
);
3628 /* If we have several alternatives or/and several constraints in an
3629 alternative and we can not say at this stage what constraint will be used,
3630 use unknown constraint. The exception is an address constraint. If
3631 operand has one address constraint, probably all others constraints are
3633 if (constraint
[0] != '\0' && get_constraint_type (cn
) != CT_ADDRESS
3634 && !constraint_unique (constraint
))
3635 cn
= CONSTRAINT__UNKNOWN
;
3636 if (insn_extra_address_constraint (cn
)
3637 /* When we find an asm operand with an address constraint that
3638 doesn't satisfy address_operand to begin with, we clear
3639 is_address, so that we don't try to make a non-address fit.
3640 If the asm statement got this far, it's because other
3641 constraints are available, and we'll use them, disregarding
3642 the unsatisfiable address ones. */
3643 && curr_static_id
->operand
[nop
].is_address
)
3644 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3645 /* Do not attempt to decompose arbitrary addresses generated by combine
3646 for asm operands with loose constraints, e.g 'X'.
3647 Need to extract memory from op for special memory constraint,
3648 i.e. bcst_mem_operand in i386 backend. */
3649 else if (MEM_P (mem
)
3650 && !(INSN_CODE (curr_insn
) < 0
3651 && get_constraint_type (cn
) == CT_FIXED_FORM
3652 && constraint_satisfied_p (op
, cn
)))
3653 decompose_mem_address (&ad
, mem
);
3654 else if (GET_CODE (op
) == SUBREG
3655 && MEM_P (SUBREG_REG (op
)))
3656 decompose_mem_address (&ad
, SUBREG_REG (op
));
3659 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3660 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3661 when INDEX_REG_CLASS is a single register class. */
3662 if (ad
.base_term
!= NULL
3663 && ad
.index_term
!= NULL
3664 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3665 && REG_P (*ad
.base_term
)
3666 && REG_P (*ad
.index_term
)
3667 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3668 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3670 std::swap (ad
.base
, ad
.index
);
3671 std::swap (ad
.base_term
, ad
.index_term
);
3674 change_p
= equiv_address_substitution (&ad
);
3675 if (ad
.base_term
!= NULL
3676 && (process_addr_reg
3677 (ad
.base_term
, check_only_p
, before
,
3679 && !(REG_P (*ad
.base_term
)
3680 && find_regno_note (curr_insn
, REG_DEAD
,
3681 REGNO (*ad
.base_term
)) != NULL_RTX
)
3683 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3684 get_index_code (&ad
)))))
3687 if (ad
.base_term2
!= NULL
)
3688 *ad
.base_term2
= *ad
.base_term
;
3690 if (ad
.index_term
!= NULL
3691 && process_addr_reg (ad
.index_term
, check_only_p
,
3692 before
, NULL
, INDEX_REG_CLASS
))
3695 /* Target hooks sometimes don't treat extra-constraint addresses as
3696 legitimate address_operands, so handle them specially. */
3697 if (insn_extra_address_constraint (cn
)
3698 && satisfies_address_constraint_p (&ad
, cn
))
3704 /* There are three cases where the shape of *AD.INNER may now be invalid:
3706 1) the original address was valid, but either elimination or
3707 equiv_address_substitution was applied and that made
3708 the address invalid.
3710 2) the address is an invalid symbolic address created by
3713 3) the address is a frame address with an invalid offset.
3715 4) the address is a frame address with an invalid base.
3717 All these cases involve a non-autoinc address, so there is no
3718 point revalidating other types. */
3719 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3722 /* Any index existed before LRA started, so we can assume that the
3723 presence and shape of the index is valid. */
3724 push_to_sequence (*before
);
3725 lra_assert (ad
.disp
== ad
.disp_term
);
3726 if (ad
.base
== NULL
)
3728 if (ad
.index
== NULL
)
3731 rtx_insn
*last
= get_last_insn ();
3733 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3735 rtx addr
= *ad
.inner
;
3737 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3740 /* addr => lo_sum (new_base, addr), case (2) above. */
3741 insn
= emit_insn (gen_rtx_SET
3743 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3744 code
= recog_memoized (insn
);
3747 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3748 if (!valid_address_p (op
, &ad
, cn
))
3750 /* Try to put lo_sum into register. */
3751 insn
= emit_insn (gen_rtx_SET
3753 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3754 code
= recog_memoized (insn
);
3757 *ad
.inner
= new_reg
;
3758 if (!valid_address_p (op
, &ad
, cn
))
3768 delete_insns_since (last
);
3773 /* addr => new_base, case (2) above. */
3774 lra_emit_move (new_reg
, addr
);
3776 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3778 insn
= NEXT_INSN (insn
))
3779 if (recog_memoized (insn
) < 0)
3781 if (insn
!= NULL_RTX
)
3783 /* Do nothing if we cannot generate right insns.
3784 This is analogous to reload pass behavior. */
3785 delete_insns_since (last
);
3789 *ad
.inner
= new_reg
;
3794 /* index * scale + disp => new base + index * scale,
3796 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3797 GET_CODE (*ad
.index
));
3799 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3800 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "disp");
3801 lra_emit_move (new_reg
, *ad
.disp
);
3802 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3803 new_reg
, *ad
.index
);
3806 else if (ad
.index
== NULL
)
3811 rtx_insn
*insns
, *last_insn
;
3812 /* Try to reload base into register only if the base is invalid
3813 for the address but with valid offset, case (4) above. */
3815 new_reg
= base_to_reg (&ad
);
3817 /* base + disp => new base, cases (1) and (3) above. */
3818 /* Another option would be to reload the displacement into an
3819 index register. However, postreload has code to optimize
3820 address reloads that have the same base and different
3821 displacements, so reloading into an index register would
3822 not necessarily be a win. */
3823 if (new_reg
== NULL_RTX
)
3825 /* See if the target can split the displacement into a
3826 legitimate new displacement from a local anchor. */
3827 gcc_assert (ad
.disp
== ad
.disp_term
);
3828 poly_int64 orig_offset
;
3829 rtx offset1
, offset2
;
3830 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3831 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3835 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3836 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3839 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3841 insns
= get_insns ();
3842 last_insn
= get_last_insn ();
3843 /* If we generated at least two insns, try last insn source as
3844 an address. If we succeed, we generate one less insn. */
3846 && last_insn
!= insns
3847 && (set
= single_set (last_insn
)) != NULL_RTX
3848 && GET_CODE (SET_SRC (set
)) == PLUS
3849 && REG_P (XEXP (SET_SRC (set
), 0))
3850 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3852 *ad
.inner
= SET_SRC (set
);
3853 if (valid_address_p (op
, &ad
, cn
))
3855 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3856 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3857 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3858 get_index_code (&ad
));
3859 regno
= REGNO (*ad
.base_term
);
3860 if (regno
>= FIRST_PSEUDO_REGISTER
3861 && cl
!= lra_get_allocno_class (regno
))
3862 lra_change_class (regno
, cl
, " Change to", true);
3863 new_reg
= SET_SRC (set
);
3864 delete_insns_since (PREV_INSN (last_insn
));
3869 *ad
.inner
= new_reg
;
3871 else if (ad
.disp_term
!= NULL
)
3873 /* base + scale * index + disp => new base + scale * index,
3875 gcc_assert (ad
.disp
== ad
.disp_term
);
3876 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3877 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3878 new_reg
, *ad
.index
);
3880 else if ((scale
= get_index_scale (&ad
)) == 1)
3882 /* The last transformation to one reg will be made in
3883 curr_insn_transform function. */
3887 else if (scale
!= 0)
3889 /* base + scale * index => base + new_reg,
3891 Index part of address may become invalid. For example, we
3892 changed pseudo on the equivalent memory and a subreg of the
3893 pseudo onto the memory of different mode for which the scale is
3895 new_reg
= index_part_to_reg (&ad
);
3896 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3897 *ad
.base_term
, new_reg
);
3901 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3903 rtx addr
= *ad
.inner
;
3905 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3906 /* addr => new_base. */
3907 lra_emit_move (new_reg
, addr
);
3908 *ad
.inner
= new_reg
;
3910 *before
= get_insns ();
3915 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3916 Use process_address_1 as a helper function. Return true for any
3919 If CHECK_ONLY_P is true, just check address correctness. Return
3920 false if the address correct. */
3922 process_address (int nop
, bool check_only_p
,
3923 rtx_insn
**before
, rtx_insn
**after
)
3927 while (process_address_1 (nop
, check_only_p
, before
, after
))
3936 /* Emit insns to reload VALUE into a new register. VALUE is an
3937 auto-increment or auto-decrement RTX whose operand is a register or
3938 memory location; so reloading involves incrementing that location.
3939 IN is either identical to VALUE, or some cheaper place to reload
3940 value being incremented/decremented from.
3942 INC_AMOUNT is the number to increment or decrement by (always
3943 positive and ignored for POST_MODIFY/PRE_MODIFY).
3945 Return pseudo containing the result. */
3947 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3949 /* REG or MEM to be copied and incremented. */
3950 rtx incloc
= XEXP (value
, 0);
3951 /* Nonzero if increment after copying. */
3952 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3953 || GET_CODE (value
) == POST_MODIFY
);
3958 rtx real_in
= in
== value
? incloc
: in
;
3962 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3964 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3965 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3966 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3967 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3968 inc
= XEXP (XEXP (value
, 1), 1);
3972 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3973 inc_amount
= -inc_amount
;
3975 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3978 if (! post
&& REG_P (incloc
))
3981 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
, NULL
,
3984 if (real_in
!= result
)
3986 /* First copy the location to the result register. */
3987 lra_assert (REG_P (result
));
3988 emit_insn (gen_move_insn (result
, real_in
));
3991 /* We suppose that there are insns to add/sub with the constant
3992 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3993 old reload worked with this assumption. If the assumption
3994 becomes wrong, we should use approach in function
3995 base_plus_disp_to_reg. */
3998 /* See if we can directly increment INCLOC. */
3999 last
= get_last_insn ();
4000 add_insn
= emit_insn (plus_p
4001 ? gen_add2_insn (incloc
, inc
)
4002 : gen_sub2_insn (incloc
, inc
));
4004 code
= recog_memoized (add_insn
);
4007 if (! post
&& result
!= incloc
)
4008 emit_insn (gen_move_insn (result
, incloc
));
4011 delete_insns_since (last
);
4014 /* If couldn't do the increment directly, must increment in RESULT.
4015 The way we do this depends on whether this is pre- or
4016 post-increment. For pre-increment, copy INCLOC to the reload
4017 register, increment it there, then save back. */
4020 if (real_in
!= result
)
4021 emit_insn (gen_move_insn (result
, real_in
));
4023 emit_insn (gen_add2_insn (result
, inc
));
4025 emit_insn (gen_sub2_insn (result
, inc
));
4026 if (result
!= incloc
)
4027 emit_insn (gen_move_insn (incloc
, result
));
4033 Because this might be a jump insn or a compare, and because
4034 RESULT may not be available after the insn in an input
4035 reload, we must do the incrementing before the insn being
4038 We have already copied IN to RESULT. Increment the copy in
4039 RESULT, save that back, then decrement RESULT so it has
4040 the original value. */
4042 emit_insn (gen_add2_insn (result
, inc
));
4044 emit_insn (gen_sub2_insn (result
, inc
));
4045 emit_insn (gen_move_insn (incloc
, result
));
4046 /* Restore non-modified value for the result. We prefer this
4047 way because it does not require an additional hard
4052 if (poly_int_rtx_p (inc
, &offset
))
4053 emit_insn (gen_add2_insn (result
,
4054 gen_int_mode (-offset
,
4055 GET_MODE (result
))));
4057 emit_insn (gen_sub2_insn (result
, inc
));
4060 emit_insn (gen_add2_insn (result
, inc
));
4065 /* Return true if the current move insn does not need processing as we
4066 already know that it satisfies its constraints. */
4068 simple_move_p (void)
4071 enum reg_class dclass
, sclass
;
4073 lra_assert (curr_insn_set
!= NULL_RTX
);
4074 dest
= SET_DEST (curr_insn_set
);
4075 src
= SET_SRC (curr_insn_set
);
4077 /* If the instruction has multiple sets we need to process it even if it
4078 is single_set. This can happen if one or more of the SETs are dead.
4080 if (multiple_sets (curr_insn
))
4083 return ((dclass
= get_op_class (dest
)) != NO_REGS
4084 && (sclass
= get_op_class (src
)) != NO_REGS
4085 /* The backend guarantees that register moves of cost 2
4086 never need reloads. */
4087 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
4090 /* Swap operands NOP and NOP + 1. */
4092 swap_operands (int nop
)
4094 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
4095 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
4096 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
4097 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
4098 /* Swap the duplicates too. */
4099 lra_update_dup (curr_id
, nop
);
4100 lra_update_dup (curr_id
, nop
+ 1);
4103 /* Main entry point of the constraint code: search the body of the
4104 current insn to choose the best alternative. It is mimicking insn
4105 alternative cost calculation model of former reload pass. That is
4106 because machine descriptions were written to use this model. This
4107 model can be changed in future. Make commutative operand exchange
4110 if CHECK_ONLY_P is false, do RTL changes to satisfy the
4111 constraints. Return true if any change happened during function
4114 If CHECK_ONLY_P is true then don't do any transformation. Just
4115 check that the insn satisfies all constraints. If the insn does
4116 not satisfy any constraint, return true. */
4118 curr_insn_transform (bool check_only_p
)
4125 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
4126 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
4127 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
4128 rtx_insn
*before
, *after
;
4130 /* Flag that the insn has been changed through a transformation. */
4134 int max_regno_before
;
4135 int reused_alternative_num
;
4137 curr_insn_set
= single_set (curr_insn
);
4138 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
4140 /* We assume that the corresponding insn alternative has no
4141 earlier clobbers. If it is not the case, don't define move
4142 cost equal to 2 for the corresponding register classes. */
4143 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
4147 no_input_reloads_p
= no_output_reloads_p
= false;
4148 goal_alt_number
= -1;
4149 change_p
= sec_mem_p
= false;
4151 /* CALL_INSNs are not allowed to have any output reloads. */
4152 if (CALL_P (curr_insn
))
4153 no_output_reloads_p
= true;
4155 n_operands
= curr_static_id
->n_operands
;
4156 n_alternatives
= curr_static_id
->n_alternatives
;
4158 /* Just return "no reloads" if insn has no operands with
4160 if (n_operands
== 0 || n_alternatives
== 0)
4163 max_regno_before
= max_reg_num ();
4165 for (i
= 0; i
< n_operands
; i
++)
4167 goal_alt_matched
[i
][0] = -1;
4168 goal_alt_matches
[i
] = -1;
4171 commutative
= curr_static_id
->commutative
;
4173 /* Now see what we need for pseudos that didn't get hard regs or got
4174 the wrong kind of hard reg. For this, we must consider all the
4175 operands together against the register constraints. */
4177 best_losers
= best_overall
= INT_MAX
;
4178 best_reload_sum
= 0;
4180 curr_swapped
= false;
4181 goal_alt_swapped
= false;
4184 /* Make equivalence substitution and memory subreg elimination
4185 before address processing because an address legitimacy can
4186 depend on memory mode. */
4187 for (i
= 0; i
< n_operands
; i
++)
4190 bool op_change_p
= false;
4192 if (curr_static_id
->operand
[i
].is_operator
)
4195 old
= op
= *curr_id
->operand_loc
[i
];
4196 if (GET_CODE (old
) == SUBREG
)
4197 old
= SUBREG_REG (old
);
4198 subst
= get_equiv_with_elimination (old
, curr_insn
);
4199 original_subreg_reg_mode
[i
] = VOIDmode
;
4200 equiv_substition_p
[i
] = false;
4203 equiv_substition_p
[i
] = true;
4204 subst
= copy_rtx (subst
);
4205 lra_assert (REG_P (old
));
4206 if (GET_CODE (op
) != SUBREG
)
4207 *curr_id
->operand_loc
[i
] = subst
;
4210 SUBREG_REG (op
) = subst
;
4211 if (GET_MODE (subst
) == VOIDmode
)
4212 original_subreg_reg_mode
[i
] = GET_MODE (old
);
4214 if (lra_dump_file
!= NULL
)
4216 fprintf (lra_dump_file
,
4217 "Changing pseudo %d in operand %i of insn %u on equiv ",
4218 REGNO (old
), i
, INSN_UID (curr_insn
));
4219 dump_value_slim (lra_dump_file
, subst
, 1);
4220 fprintf (lra_dump_file
, "\n");
4222 op_change_p
= change_p
= true;
4224 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
4227 lra_update_dup (curr_id
, i
);
4231 /* Reload address registers and displacements. We do it before
4232 finding an alternative because of memory constraints. */
4233 before
= after
= NULL
;
4234 for (i
= 0; i
< n_operands
; i
++)
4235 if (! curr_static_id
->operand
[i
].is_operator
4236 && process_address (i
, check_only_p
, &before
, &after
))
4241 lra_update_dup (curr_id
, i
);
4245 /* If we've changed the instruction then any alternative that
4246 we chose previously may no longer be valid. */
4247 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
4249 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
4250 && check_and_process_move (&change_p
, &sec_mem_p
))
4255 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
4256 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
4257 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
4258 reused_alternative_num
, INSN_UID (curr_insn
));
4260 if (process_alt_operands (reused_alternative_num
))
4264 return ! alt_p
|| best_losers
!= 0;
4266 /* If insn is commutative (it's safe to exchange a certain pair of
4267 operands) then we need to try each alternative twice, the second
4268 time matching those two operands as if we had exchanged them. To
4269 do this, really exchange them in operands.
4271 If we have just tried the alternatives the second time, return
4272 operands to normal and drop through. */
4274 if (reused_alternative_num
< 0 && commutative
>= 0)
4276 curr_swapped
= !curr_swapped
;
4279 swap_operands (commutative
);
4283 swap_operands (commutative
);
4286 if (! alt_p
&& ! sec_mem_p
)
4288 /* No alternative works with reloads?? */
4289 if (INSN_CODE (curr_insn
) >= 0)
4290 fatal_insn ("unable to generate reloads for:", curr_insn
);
4291 error_for_asm (curr_insn
,
4292 "inconsistent operand constraints in an %<asm%>");
4293 lra_asm_error_p
= true;
4294 if (! JUMP_P (curr_insn
))
4296 /* Avoid further trouble with this insn. Don't generate use
4297 pattern here as we could use the insn SP offset. */
4298 lra_set_insn_deleted (curr_insn
);
4302 lra_invalidate_insn_data (curr_insn
);
4303 ira_nullify_asm_goto (curr_insn
);
4304 lra_update_insn_regno_info (curr_insn
);
4309 /* If the best alternative is with operands 1 and 2 swapped, swap
4310 them. Update the operand numbers of any reloads already
4313 if (goal_alt_swapped
)
4315 if (lra_dump_file
!= NULL
)
4316 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4317 INSN_UID (curr_insn
));
4319 /* Swap the duplicates too. */
4320 swap_operands (commutative
);
4324 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4325 too conservatively. So we use the secondary memory only if there
4326 is no any alternative without reloads. */
4327 use_sec_mem_p
= false;
4329 use_sec_mem_p
= true;
4332 for (i
= 0; i
< n_operands
; i
++)
4333 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4335 use_sec_mem_p
= i
< n_operands
;
4340 int in
= -1, out
= -1;
4341 rtx new_reg
, src
, dest
, rld
;
4342 machine_mode sec_mode
, rld_mode
;
4344 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4345 dest
= SET_DEST (curr_insn_set
);
4346 src
= SET_SRC (curr_insn_set
);
4347 for (i
= 0; i
< n_operands
; i
++)
4348 if (*curr_id
->operand_loc
[i
] == dest
)
4350 else if (*curr_id
->operand_loc
[i
] == src
)
4352 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4353 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4354 out
= curr_static_id
->dup_num
[i
];
4355 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4356 in
= curr_static_id
->dup_num
[i
];
4357 lra_assert (out
>= 0 && in
>= 0
4358 && curr_static_id
->operand
[out
].type
== OP_OUT
4359 && curr_static_id
->operand
[in
].type
== OP_IN
);
4360 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4361 rld_mode
= GET_MODE (rld
);
4362 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4363 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
, NO_REGS
, NULL
,
4365 /* If the mode is changed, it should be wider. */
4366 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4367 if (sec_mode
!= rld_mode
)
4369 /* If the target says specifically to use another mode for
4370 secondary memory moves we cannot reuse the original
4372 after
= emit_spill_move (false, new_reg
, dest
);
4373 lra_process_new_insns (curr_insn
, NULL
, after
,
4374 "Inserting the sec. move");
4375 /* We may have non null BEFORE here (e.g. after address
4377 push_to_sequence (before
);
4378 before
= emit_spill_move (true, new_reg
, src
);
4380 before
= get_insns ();
4382 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4383 lra_set_insn_deleted (curr_insn
);
4385 else if (dest
== rld
)
4387 *curr_id
->operand_loc
[out
] = new_reg
;
4388 lra_update_dup (curr_id
, out
);
4389 after
= emit_spill_move (false, new_reg
, dest
);
4390 lra_process_new_insns (curr_insn
, NULL
, after
,
4391 "Inserting the sec. move");
4395 *curr_id
->operand_loc
[in
] = new_reg
;
4396 lra_update_dup (curr_id
, in
);
4397 /* See comments above. */
4398 push_to_sequence (before
);
4399 before
= emit_spill_move (true, new_reg
, src
);
4401 before
= get_insns ();
4403 lra_process_new_insns (curr_insn
, before
, NULL
,
4404 "Inserting the sec. move");
4406 lra_update_insn_regno_info (curr_insn
);
4410 lra_assert (goal_alt_number
>= 0);
4411 lra_set_used_insn_alternative (curr_insn
, goal_reuse_alt_p
4412 ? goal_alt_number
: LRA_UNKNOWN_ALT
);
4414 if (lra_dump_file
!= NULL
)
4418 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4419 goal_alt_number
, INSN_UID (curr_insn
));
4420 print_curr_insn_alt (goal_alt_number
);
4421 if (INSN_CODE (curr_insn
) >= 0
4422 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4423 fprintf (lra_dump_file
, " {%s}", p
);
4424 if (maybe_ne (curr_id
->sp_offset
, 0))
4426 fprintf (lra_dump_file
, " (sp_off=");
4427 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4428 fprintf (lra_dump_file
, ")");
4430 fprintf (lra_dump_file
, "\n");
4433 /* Right now, for any pair of operands I and J that are required to
4434 match, with J < I, goal_alt_matches[I] is J. Add I to
4435 goal_alt_matched[J]. */
4437 for (i
= 0; i
< n_operands
; i
++)
4438 if ((j
= goal_alt_matches
[i
]) >= 0)
4440 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4442 /* We allow matching one output operand and several input
4445 || (curr_static_id
->operand
[j
].type
== OP_OUT
4446 && curr_static_id
->operand
[i
].type
== OP_IN
4447 && (curr_static_id
->operand
4448 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4449 goal_alt_matched
[j
][k
] = i
;
4450 goal_alt_matched
[j
][k
+ 1] = -1;
4453 for (i
= 0; i
< n_operands
; i
++)
4454 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4456 /* Any constants that aren't allowed and can't be reloaded into
4457 registers are here changed into memory references. */
4458 for (i
= 0; i
< n_operands
; i
++)
4459 if (goal_alt_win
[i
])
4462 enum reg_class new_class
;
4463 rtx reg
= *curr_id
->operand_loc
[i
];
4465 if (GET_CODE (reg
) == SUBREG
)
4466 reg
= SUBREG_REG (reg
);
4468 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4470 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4472 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4475 lra_change_class (regno
, new_class
, " Change to", true);
4481 const char *constraint
;
4483 rtx op
= *curr_id
->operand_loc
[i
];
4484 rtx subreg
= NULL_RTX
;
4485 machine_mode mode
= curr_operand_mode
[i
];
4487 if (GET_CODE (op
) == SUBREG
)
4490 op
= SUBREG_REG (op
);
4491 mode
= GET_MODE (op
);
4494 if (CONST_POOL_OK_P (mode
, op
)
4495 && ((targetm
.preferred_reload_class
4496 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4497 || no_input_reloads_p
))
4499 rtx tem
= force_const_mem (mode
, op
);
4502 if (subreg
!= NULL_RTX
)
4503 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4505 *curr_id
->operand_loc
[i
] = tem
;
4506 lra_update_dup (curr_id
, i
);
4507 process_address (i
, false, &before
, &after
);
4509 /* If the alternative accepts constant pool refs directly
4510 there will be no reload needed at all. */
4511 if (subreg
!= NULL_RTX
)
4513 /* Skip alternatives before the one requested. */
4514 constraint
= (curr_static_id
->operand_alternative
4515 [goal_alt_number
* n_operands
+ i
].constraint
);
4517 (c
= *constraint
) && c
!= ',' && c
!= '#';
4518 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4520 enum constraint_num cn
= lookup_constraint (constraint
);
4521 if ((insn_extra_memory_constraint (cn
)
4522 || insn_extra_special_memory_constraint (cn
)
4523 || insn_extra_relaxed_memory_constraint (cn
))
4524 && satisfies_memory_constraint_p (tem
, cn
))
4527 if (c
== '\0' || c
== ',' || c
== '#')
4530 goal_alt_win
[i
] = true;
4535 for (i
= 0; i
< n_operands
; i
++)
4536 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4537 outputs
[n_outputs
++] = i
;
4538 outputs
[n_outputs
] = -1;
4539 for (i
= 0; i
< n_operands
; i
++)
4542 bool optional_p
= false;
4544 rtx op
= *curr_id
->operand_loc
[i
];
4546 if (goal_alt_win
[i
])
4548 if (goal_alt
[i
] == NO_REGS
4550 /* When we assign NO_REGS it means that we will not
4551 assign a hard register to the scratch pseudo by
4552 assigment pass and the scratch pseudo will be
4553 spilled. Spilled scratch pseudos are transformed
4554 back to scratches at the LRA end. */
4555 && ira_former_scratch_operand_p (curr_insn
, i
)
4556 && ira_former_scratch_p (REGNO (op
)))
4558 int regno
= REGNO (op
);
4559 lra_change_class (regno
, NO_REGS
, " Change to", true);
4560 if (lra_get_regno_hard_regno (regno
) >= 0)
4561 /* We don't have to mark all insn affected by the
4562 spilled pseudo as there is only one such insn, the
4564 reg_renumber
[regno
] = -1;
4565 lra_assert (bitmap_single_bit_set_p
4566 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4568 /* We can do an optional reload. If the pseudo got a hard
4569 reg, we might improve the code through inheritance. If
4570 it does not get a hard register we coalesce memory/memory
4571 moves later. Ignore move insns to avoid cycling. */
4573 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4574 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4575 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4576 && regno
< new_regno_start
4577 && ! ira_former_scratch_p (regno
)
4578 && reg_renumber
[regno
] < 0
4579 /* Check that the optional reload pseudo will be able to
4580 hold given mode value. */
4581 && ! (prohibited_class_reg_set_mode_p
4582 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4583 PSEUDO_REGNO_MODE (regno
)))
4584 && (curr_insn_set
== NULL_RTX
4585 || !((REG_P (SET_SRC (curr_insn_set
))
4586 || MEM_P (SET_SRC (curr_insn_set
))
4587 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4588 && (REG_P (SET_DEST (curr_insn_set
))
4589 || MEM_P (SET_DEST (curr_insn_set
))
4590 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4592 else if (goal_alt_matched
[i
][0] != -1
4593 && curr_static_id
->operand
[i
].type
== OP_OUT
4594 && (curr_static_id
->operand_alternative
4595 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4598 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4600 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4602 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4605 if (goal_alt_matched
[i
][j
] != -1)
4607 /* Generate reloads for different output and matched
4608 input registers. This is the easiest way to avoid
4609 creation of non-existing register conflicts in
4611 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4612 &goal_alt_exclude_start_hard_regs
[i
], &before
,
4619 enum reg_class rclass
, common_class
;
4621 if (REG_P (op
) && goal_alt
[i
] != NO_REGS
4622 && (regno
= REGNO (op
)) >= new_regno_start
4623 && (rclass
= get_reg_class (regno
)) == ALL_REGS
4624 && ((common_class
= ira_reg_class_subset
[rclass
][goal_alt
[i
]])
4626 && common_class
!= ALL_REGS
4627 && enough_allocatable_hard_regs_p (common_class
,
4629 /* Refine reload pseudo class from chosen alternative
4631 lra_change_class (regno
, common_class
, " Change to", true);
4636 /* Operands that match previous ones have already been handled. */
4637 if (goal_alt_matches
[i
] >= 0)
4640 /* We should not have an operand with a non-offsettable address
4641 appearing where an offsettable address will do. It also may
4642 be a case when the address should be special in other words
4643 not a general one (e.g. it needs no index reg). */
4644 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4646 enum reg_class rclass
;
4647 rtx
*loc
= &XEXP (op
, 0);
4648 enum rtx_code code
= GET_CODE (*loc
);
4650 push_to_sequence (before
);
4651 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4653 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4654 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4655 /* This value does not matter for MODIFY. */
4656 GET_MODE_SIZE (GET_MODE (op
)));
4657 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
4659 "offsetable address", &new_reg
))
4662 enum rtx_code code
= GET_CODE (addr
);
4663 bool align_p
= false;
4665 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4667 /* (and ... (const_int -X)) is used to align to X bytes. */
4669 addr
= XEXP (*loc
, 0);
4672 addr
= canonicalize_reload_addr (addr
);
4674 lra_emit_move (new_reg
, addr
);
4676 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4678 before
= get_insns ();
4681 lra_update_dup (curr_id
, i
);
4683 else if (goal_alt_matched
[i
][0] == -1)
4688 enum op_type type
= curr_static_id
->operand
[i
].type
;
4690 loc
= curr_id
->operand_loc
[i
];
4691 mode
= curr_operand_mode
[i
];
4692 if (GET_CODE (*loc
) == SUBREG
)
4694 reg
= SUBREG_REG (*loc
);
4695 poly_int64 byte
= SUBREG_BYTE (*loc
);
4697 /* Strict_low_part requires reloading the register and not
4698 just the subreg. Likewise for a strict subreg no wider
4699 than a word for WORD_REGISTER_OPERATIONS targets. */
4700 && (curr_static_id
->operand
[i
].strict_low
4701 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4703 = get_try_hard_regno (REGNO (reg
))) >= 0
4704 && (simplify_subreg_regno
4706 GET_MODE (reg
), byte
, mode
) < 0)
4707 && (goal_alt
[i
] == NO_REGS
4708 || (simplify_subreg_regno
4709 (ira_class_hard_regs
[goal_alt
[i
]][0],
4710 GET_MODE (reg
), byte
, mode
) >= 0)))
4711 || (partial_subreg_p (mode
, GET_MODE (reg
))
4712 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4714 && WORD_REGISTER_OPERATIONS
))
4715 /* Avoid the situation when there are no available hard regs
4716 for the pseudo mode but there are ones for the subreg
4718 && !(goal_alt
[i
] != NO_REGS
4719 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
4720 && (prohibited_class_reg_set_mode_p
4721 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4723 && !(prohibited_class_reg_set_mode_p
4724 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4727 /* An OP_INOUT is required when reloading a subreg of a
4728 mode wider than a word to ensure that data beyond the
4729 word being reloaded is preserved. Also automatically
4730 ensure that strict_low_part reloads are made into
4731 OP_INOUT which should already be true from the backend
4734 && (curr_static_id
->operand
[i
].strict_low
4735 || read_modify_subreg_p (*loc
)))
4737 loc
= &SUBREG_REG (*loc
);
4738 mode
= GET_MODE (*loc
);
4742 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4743 &goal_alt_exclude_start_hard_regs
[i
],
4744 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4747 push_to_sequence (before
);
4748 lra_emit_move (new_reg
, old
);
4749 before
= get_insns ();
4754 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4757 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4759 after
= get_insns ();
4763 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4764 if (goal_alt_dont_inherit_ops
[j
] == i
)
4766 lra_set_regno_unique_value (REGNO (new_reg
));
4769 lra_update_dup (curr_id
, i
);
4771 else if (curr_static_id
->operand
[i
].type
== OP_IN
4772 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4774 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4776 && (operands_match_p
4777 (*curr_id
->operand_loc
[i
],
4778 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4781 /* generate reloads for input and matched outputs. */
4782 match_inputs
[0] = i
;
4783 match_inputs
[1] = -1;
4784 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4785 goal_alt
[i
], &goal_alt_exclude_start_hard_regs
[i
],
4787 curr_static_id
->operand_alternative
4788 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4791 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4792 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4793 && (operands_match_p
4794 (*curr_id
->operand_loc
[i
],
4795 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4797 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4799 /* Generate reloads for output and matched inputs. */
4800 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4801 &goal_alt_exclude_start_hard_regs
[i
], &before
, &after
,
4802 curr_static_id
->operand_alternative
4803 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4804 else if (curr_static_id
->operand
[i
].type
== OP_IN
4805 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4808 /* Generate reloads for matched inputs. */
4809 match_inputs
[0] = i
;
4810 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4811 match_inputs
[j
+ 1] = k
;
4812 match_inputs
[j
+ 1] = -1;
4813 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
],
4814 &goal_alt_exclude_start_hard_regs
[i
],
4815 &before
, &after
, false);
4818 /* We must generate code in any case when function
4819 process_alt_operands decides that it is possible. */
4826 lra_assert (REG_P (reg
));
4827 regno
= REGNO (reg
);
4828 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4829 if (GET_CODE (op
) == SUBREG
)
4830 op
= SUBREG_REG (op
);
4831 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4832 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4833 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4834 if (lra_dump_file
!= NULL
)
4835 fprintf (lra_dump_file
,
4836 " Making reload reg %d for reg %d optional\n",
4840 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4841 || max_regno_before
!= max_reg_num ())
4845 lra_update_operator_dups (curr_id
);
4846 /* Something changes -- process the insn. */
4847 lra_update_insn_regno_info (curr_insn
);
4848 if (asm_noperands (PATTERN (curr_insn
)) >= 0
4849 && ++curr_id
->asm_reloads_num
>= FIRST_PSEUDO_REGISTER
)
4850 /* Most probably there are no enough registers to satisfy asm insn: */
4851 lra_asm_insn_error (curr_insn
);
4853 if (goal_alt_out_sp_reload_p
)
4855 /* We have an output stack pointer reload -- update sp offset: */
4857 bool done_p
= false;
4858 poly_int64 sp_offset
= curr_id
->sp_offset
;
4859 for (rtx_insn
*insn
= after
; insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
4860 if ((set
= single_set (insn
)) != NULL_RTX
4861 && SET_DEST (set
) == stack_pointer_rtx
)
4863 lra_assert (!done_p
);
4865 curr_id
->sp_offset
= 0;
4866 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
4867 id
->sp_offset
= sp_offset
;
4868 if (lra_dump_file
!= NULL
)
4869 fprintf (lra_dump_file
,
4870 " Moving sp offset from insn %u to %u\n",
4871 INSN_UID (curr_insn
), INSN_UID (insn
));
4873 lra_assert (done_p
);
4875 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4879 /* Return true if INSN satisfies all constraints. In other words, no
4880 reload insns are needed. */
4882 lra_constrain_insn (rtx_insn
*insn
)
4884 int saved_new_regno_start
= new_regno_start
;
4885 int saved_new_insn_uid_start
= new_insn_uid_start
;
4889 curr_id
= lra_get_insn_recog_data (curr_insn
);
4890 curr_static_id
= curr_id
->insn_static_data
;
4891 new_insn_uid_start
= get_max_uid ();
4892 new_regno_start
= max_reg_num ();
4893 change_p
= curr_insn_transform (true);
4894 new_regno_start
= saved_new_regno_start
;
4895 new_insn_uid_start
= saved_new_insn_uid_start
;
4899 /* Return true if X is in LIST. */
4901 in_list_p (rtx x
, rtx list
)
4903 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4904 if (XEXP (list
, 0) == x
)
4909 /* Return true if X contains an allocatable hard register (if
4910 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4912 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4918 code
= GET_CODE (x
);
4921 int regno
= REGNO (x
);
4922 HARD_REG_SET alloc_regs
;
4926 if (regno
>= FIRST_PSEUDO_REGISTER
)
4927 regno
= lra_get_regno_hard_regno (regno
);
4930 alloc_regs
= ~lra_no_alloc_regs
;
4931 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4935 if (regno
< FIRST_PSEUDO_REGISTER
)
4939 return lra_get_regno_hard_regno (regno
) < 0;
4942 fmt
= GET_RTX_FORMAT (code
);
4943 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4947 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4950 else if (fmt
[i
] == 'E')
4952 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4953 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4960 /* Process all regs in location *LOC and change them on equivalent
4961 substitution. Return true if any change was done. */
4963 loc_equivalence_change_p (rtx
*loc
)
4965 rtx subst
, reg
, x
= *loc
;
4966 bool result
= false;
4967 enum rtx_code code
= GET_CODE (x
);
4973 reg
= SUBREG_REG (x
);
4974 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4975 && GET_MODE (subst
) == VOIDmode
)
4977 /* We cannot reload debug location. Simplify subreg here
4978 while we know the inner mode. */
4979 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4980 GET_MODE (reg
), SUBREG_BYTE (x
));
4984 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4990 /* Scan all the operand sub-expressions. */
4991 fmt
= GET_RTX_FORMAT (code
);
4992 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4995 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4996 else if (fmt
[i
] == 'E')
4997 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4999 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
5004 /* Similar to loc_equivalence_change_p, but for use as
5005 simplify_replace_fn_rtx callback. DATA is insn for which the
5006 elimination is done. If it null we don't do the elimination. */
5008 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
5013 rtx subst
= (data
== NULL
5014 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
5021 /* Maximum number of generated reload insns per an insn. It is for
5022 preventing this pass cycling in a bug case. */
5023 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
5025 /* The current iteration number of this LRA pass. */
5026 int lra_constraint_iter
;
5028 /* True if we should during assignment sub-pass check assignment
5029 correctness for all pseudos and spill some of them to correct
5030 conflicts. It can be necessary when we substitute equiv which
5031 needs checking register allocation correctness because the
5032 equivalent value contains allocatable hard registers, or when we
5033 restore multi-register pseudo, or when we change the insn code and
5034 its operand became INOUT operand when it was IN one before. */
5035 bool check_and_force_assignment_correctness_p
;
5037 /* Return true if REGNO is referenced in more than one block. */
5039 multi_block_pseudo_p (int regno
)
5041 basic_block bb
= NULL
;
5045 if (regno
< FIRST_PSEUDO_REGISTER
)
5048 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
5050 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
5051 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
5056 /* Return true if LIST contains a deleted insn. */
5058 contains_deleted_insn_p (rtx_insn_list
*list
)
5060 for (; list
!= NULL_RTX
; list
= list
->next ())
5061 if (NOTE_P (list
->insn ())
5062 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
5067 /* Return true if X contains a pseudo dying in INSN. */
5069 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
5076 return (insn
!= NULL_RTX
5077 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
5078 code
= GET_CODE (x
);
5079 fmt
= GET_RTX_FORMAT (code
);
5080 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5084 if (dead_pseudo_p (XEXP (x
, i
), insn
))
5087 else if (fmt
[i
] == 'E')
5089 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5090 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
5097 /* Return true if INSN contains a dying pseudo in INSN right hand
5100 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
5102 rtx set
= single_set (insn
);
5104 gcc_assert (set
!= NULL
);
5105 return dead_pseudo_p (SET_SRC (set
), insn
);
5108 /* Return true if any init insn of REGNO contains a dying pseudo in
5109 insn right hand side. */
5111 init_insn_rhs_dead_pseudo_p (int regno
)
5113 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5117 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
5118 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
5123 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
5124 reverse only if we have one init insn with given REGNO as a
5127 reverse_equiv_p (int regno
)
5129 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5134 if (! INSN_P (insns
->insn ())
5135 || insns
->next () != NULL
)
5137 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
5139 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
5142 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
5143 call this function only for non-reverse equivalence. */
5145 contains_reloaded_insn_p (int regno
)
5148 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
5150 for (; list
!= NULL
; list
= list
->next ())
5151 if ((set
= single_set (list
->insn ())) == NULL_RTX
5152 || ! REG_P (SET_DEST (set
))
5153 || (int) REGNO (SET_DEST (set
)) != regno
)
5158 /* Try combine secondary memory reload insn FROM for insn TO into TO insn.
5159 FROM should be a load insn (usually a secondary memory reload insn). Return
5160 TRUE in case of success. */
5162 combine_reload_insn (rtx_insn
*from
, rtx_insn
*to
)
5165 rtx_insn
*saved_insn
;
5166 rtx set
, from_reg
, to_reg
, op
;
5167 enum reg_class to_class
, from_class
;
5169 signed char changed_nops
[MAX_RECOG_OPERANDS
+ 1];
5171 /* Check conditions for second memory reload and original insn: */
5172 if ((targetm
.secondary_memory_needed
5173 == hook_bool_mode_reg_class_t_reg_class_t_false
)
5174 || NEXT_INSN (from
) != to
5175 || !NONDEBUG_INSN_P (to
)
5179 lra_insn_recog_data_t id
= lra_get_insn_recog_data (to
);
5180 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5182 if (id
->used_insn_alternative
== LRA_UNKNOWN_ALT
5183 || (set
= single_set (from
)) == NULL_RTX
)
5185 from_reg
= SET_DEST (set
);
5186 to_reg
= SET_SRC (set
);
5187 /* Ignore optional reloads: */
5188 if (! REG_P (from_reg
) || ! REG_P (to_reg
)
5189 || bitmap_bit_p (&lra_optional_reload_pseudos
, REGNO (from_reg
)))
5191 to_class
= lra_get_allocno_class (REGNO (to_reg
));
5192 from_class
= lra_get_allocno_class (REGNO (from_reg
));
5193 /* Check that reload insn is a load: */
5194 if (to_class
!= NO_REGS
|| from_class
== NO_REGS
)
5196 for (n
= nop
= 0; nop
< static_id
->n_operands
; nop
++)
5198 if (static_id
->operand
[nop
].type
!= OP_IN
)
5200 op
= *id
->operand_loc
[nop
];
5201 if (!REG_P (op
) || REGNO (op
) != REGNO (from_reg
))
5203 *id
->operand_loc
[nop
] = to_reg
;
5204 changed_nops
[n
++] = nop
;
5206 changed_nops
[n
] = -1;
5207 lra_update_dups (id
, changed_nops
);
5208 lra_update_insn_regno_info (to
);
5209 ok_p
= recog_memoized (to
) >= 0;
5212 /* Check that combined insn does not need any reloads: */
5213 saved_insn
= curr_insn
;
5215 curr_id
= lra_get_insn_recog_data (curr_insn
);
5216 curr_static_id
= curr_id
->insn_static_data
;
5217 for (bool swapped_p
= false;;)
5219 ok_p
= !curr_insn_transform (true);
5220 if (ok_p
|| curr_static_id
->commutative
< 0)
5222 swap_operands (curr_static_id
->commutative
);
5223 if (lra_dump_file
!= NULL
)
5225 fprintf (lra_dump_file
,
5226 " Swapping %scombined insn operands:\n",
5227 swapped_p
? "back " : "");
5228 dump_insn_slim (lra_dump_file
, to
);
5234 curr_insn
= saved_insn
;
5235 curr_id
= lra_get_insn_recog_data (curr_insn
);
5236 curr_static_id
= curr_id
->insn_static_data
;
5240 id
->used_insn_alternative
= -1;
5241 lra_push_insn_and_update_insn_regno_info (to
);
5242 if (lra_dump_file
!= NULL
)
5244 fprintf (lra_dump_file
, " Use combined insn:\n");
5245 dump_insn_slim (lra_dump_file
, to
);
5249 if (lra_dump_file
!= NULL
)
5251 fprintf (lra_dump_file
, " Failed combined insn:\n");
5252 dump_insn_slim (lra_dump_file
, to
);
5254 for (int i
= 0; i
< n
; i
++)
5256 nop
= changed_nops
[i
];
5257 *id
->operand_loc
[nop
] = from_reg
;
5259 lra_update_dups (id
, changed_nops
);
5260 lra_update_insn_regno_info (to
);
5261 if (lra_dump_file
!= NULL
)
5263 fprintf (lra_dump_file
, " Restoring insn after failed combining:\n");
5264 dump_insn_slim (lra_dump_file
, to
);
5269 /* Entry function of LRA constraint pass. Return true if the
5270 constraint pass did change the code. */
5272 lra_constraints (bool first_p
)
5275 int i
, hard_regno
, new_insns_num
;
5276 unsigned int min_len
, new_min_len
, uid
;
5277 rtx set
, x
, reg
, dest_reg
;
5278 rtx_insn
*original_insn
;
5279 basic_block last_bb
;
5282 lra_constraint_iter
++;
5283 if (lra_dump_file
!= NULL
)
5284 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
5285 lra_constraint_iter
);
5287 if (pic_offset_table_rtx
5288 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5289 check_and_force_assignment_correctness_p
= true;
5291 /* On the first iteration we should check IRA assignment
5292 correctness. In rare cases, the assignments can be wrong as
5293 early clobbers operands are ignored in IRA or usages of
5294 paradoxical sub-registers are not taken into account by
5296 check_and_force_assignment_correctness_p
= true;
5297 new_insn_uid_start
= get_max_uid ();
5298 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
5299 /* Mark used hard regs for target stack size calulations. */
5300 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5301 if (lra_reg_info
[i
].nrefs
!= 0
5302 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5306 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
5307 for (j
= 0; j
< nregs
; j
++)
5308 df_set_regs_ever_live (hard_regno
+ j
, true);
5310 /* Do elimination before the equivalence processing as we can spill
5311 some pseudos during elimination. */
5312 lra_eliminate (false, first_p
);
5313 auto_bitmap
equiv_insn_bitmap (®_obstack
);
5314 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5315 if (lra_reg_info
[i
].nrefs
!= 0)
5317 ira_reg_equiv
[i
].profitable_p
= true;
5318 reg
= regno_reg_rtx
[i
];
5319 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
5321 bool pseudo_p
= contains_reg_p (x
, false, false);
5323 /* After RTL transformation, we cannot guarantee that
5324 pseudo in the substitution was not reloaded which might
5325 make equivalence invalid. For example, in reverse
5332 the memory address register was reloaded before the 2nd
5334 if ((! first_p
&& pseudo_p
)
5335 /* We don't use DF for compilation speed sake. So it
5336 is problematic to update live info when we use an
5337 equivalence containing pseudos in more than one
5339 || (pseudo_p
&& multi_block_pseudo_p (i
))
5340 /* If an init insn was deleted for some reason, cancel
5341 the equiv. We could update the equiv insns after
5342 transformations including an equiv insn deletion
5343 but it is not worthy as such cases are extremely
5345 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
5346 /* If it is not a reverse equivalence, we check that a
5347 pseudo in rhs of the init insn is not dying in the
5348 insn. Otherwise, the live info at the beginning of
5349 the corresponding BB might be wrong after we
5350 removed the insn. When the equiv can be a
5351 constant, the right hand side of the init insn can
5353 || (! reverse_equiv_p (i
)
5354 && (init_insn_rhs_dead_pseudo_p (i
)
5355 /* If we reloaded the pseudo in an equivalence
5356 init insn, we cannot remove the equiv init
5357 insns and the init insns might write into
5358 const memory in this case. */
5359 || contains_reloaded_insn_p (i
)))
5360 /* Prevent access beyond equivalent memory for
5361 paradoxical subregs. */
5363 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
5364 GET_MODE_SIZE (GET_MODE (x
))))
5365 || (pic_offset_table_rtx
5366 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
5367 && (targetm
.preferred_reload_class
5368 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
5369 || contains_symbol_ref_p (x
))))
5370 ira_reg_equiv
[i
].defined_p
5371 = ira_reg_equiv
[i
].caller_save_p
= false;
5372 if (contains_reg_p (x
, false, true))
5373 ira_reg_equiv
[i
].profitable_p
= false;
5374 if (get_equiv (reg
) != reg
)
5375 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
5378 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5380 /* We should add all insns containing pseudos which should be
5381 substituted by their equivalences. */
5382 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
5383 lra_push_insn_by_uid (uid
);
5384 min_len
= lra_insn_stack_length ();
5388 original_insn
= NULL
;
5389 while ((new_min_len
= lra_insn_stack_length ()) != 0)
5391 curr_insn
= lra_pop_insn ();
5393 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5394 if (curr_bb
!= last_bb
)
5397 bb_reload_num
= lra_curr_reload_num
;
5399 if (min_len
> new_min_len
)
5401 min_len
= new_min_len
;
5403 original_insn
= curr_insn
;
5405 else if (combine_reload_insn (curr_insn
, original_insn
))
5409 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
5411 ("maximum number of generated reload insns per insn achieved (%d)",
5412 MAX_RELOAD_INSNS_NUMBER
);
5414 if (DEBUG_INSN_P (curr_insn
))
5416 /* We need to check equivalence in debug insn and change
5417 pseudo to the equivalent value if necessary. */
5418 curr_id
= lra_get_insn_recog_data (curr_insn
);
5419 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
5421 rtx old
= *curr_id
->operand_loc
[0];
5422 *curr_id
->operand_loc
[0]
5423 = simplify_replace_fn_rtx (old
, NULL_RTX
,
5424 loc_equivalence_callback
, curr_insn
);
5425 if (old
!= *curr_id
->operand_loc
[0])
5427 /* If we substitute pseudo by shared equivalence, we can fail
5428 to update LRA reg info and this can result in many
5429 unexpected consequences. So keep rtl unshared: */
5430 *curr_id
->operand_loc
[0]
5431 = copy_rtx (*curr_id
->operand_loc
[0]);
5432 lra_update_insn_regno_info (curr_insn
);
5437 else if (INSN_P (curr_insn
))
5439 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
5441 dest_reg
= SET_DEST (set
);
5442 /* The equivalence pseudo could be set up as SUBREG in a
5443 case when it is a call restore insn in a mode
5444 different from the pseudo mode. */
5445 if (GET_CODE (dest_reg
) == SUBREG
)
5446 dest_reg
= SUBREG_REG (dest_reg
);
5447 if ((REG_P (dest_reg
)
5448 && (x
= get_equiv (dest_reg
)) != dest_reg
5449 /* Remove insns which set up a pseudo whose value
5450 cannot be changed. Such insns might be not in
5451 init_insns because we don't update equiv data
5452 during insn transformations.
5454 As an example, let suppose that a pseudo got
5455 hard register and on the 1st pass was not
5456 changed to equivalent constant. We generate an
5457 additional insn setting up the pseudo because of
5458 secondary memory movement. Then the pseudo is
5459 spilled and we use the equiv constant. In this
5460 case we should remove the additional insn and
5461 this insn is not init_insns list. */
5462 && (! MEM_P (x
) || MEM_READONLY_P (x
)
5463 /* Check that this is actually an insn setting
5464 up the equivalence. */
5465 || in_list_p (curr_insn
,
5467 [REGNO (dest_reg
)].init_insns
)))
5468 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5469 && in_list_p (curr_insn
,
5471 [REGNO (SET_SRC (set
))].init_insns
)))
5473 /* This is equiv init insn of pseudo which did not get a
5474 hard register -- remove the insn. */
5475 if (lra_dump_file
!= NULL
)
5477 fprintf (lra_dump_file
,
5478 " Removing equiv init insn %i (freq=%d)\n",
5479 INSN_UID (curr_insn
),
5480 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5481 dump_insn_slim (lra_dump_file
, curr_insn
);
5483 if (contains_reg_p (x
, true, false))
5484 check_and_force_assignment_correctness_p
= true;
5485 lra_set_insn_deleted (curr_insn
);
5489 curr_id
= lra_get_insn_recog_data (curr_insn
);
5490 curr_static_id
= curr_id
->insn_static_data
;
5491 init_curr_insn_input_reloads ();
5492 init_curr_operand_mode ();
5493 if (curr_insn_transform (false))
5495 /* Check non-transformed insns too for equiv change as USE
5496 or CLOBBER don't need reloads but can contain pseudos
5497 being changed on their equivalences. */
5498 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5499 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5501 lra_update_insn_regno_info (curr_insn
);
5507 /* If we used a new hard regno, changed_p should be true because the
5508 hard reg is assigned to a new pseudo. */
5509 if (flag_checking
&& !changed_p
)
5511 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5512 if (lra_reg_info
[i
].nrefs
!= 0
5513 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5515 int j
, nregs
= hard_regno_nregs (hard_regno
,
5516 PSEUDO_REGNO_MODE (i
));
5518 for (j
= 0; j
< nregs
; j
++)
5519 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5525 static void initiate_invariants (void);
5526 static void finish_invariants (void);
5528 /* Initiate the LRA constraint pass. It is done once per
5531 lra_constraints_init (void)
5533 initiate_invariants ();
5536 /* Finalize the LRA constraint pass. It is done once per
5539 lra_constraints_finish (void)
5541 finish_invariants ();
5546 /* Structure describes invariants for ineheritance. */
5547 struct lra_invariant
5549 /* The order number of the invariant. */
5551 /* The invariant RTX. */
5553 /* The origin insn of the invariant. */
5557 typedef lra_invariant invariant_t
;
5558 typedef invariant_t
*invariant_ptr_t
;
5559 typedef const invariant_t
*const_invariant_ptr_t
;
5561 /* Pointer to the inheritance invariants. */
5562 static vec
<invariant_ptr_t
> invariants
;
5564 /* Allocation pool for the invariants. */
5565 static object_allocator
<lra_invariant
> *invariants_pool
;
5567 /* Hash table for the invariants. */
5568 static htab_t invariant_table
;
5570 /* Hash function for INVARIANT. */
5572 invariant_hash (const void *invariant
)
5574 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5575 return lra_rtx_hash (inv
);
5578 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5580 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5582 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5583 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5585 return rtx_equal_p (inv1
, inv2
);
5588 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5589 invariant which is in the table. */
5590 static invariant_ptr_t
5591 insert_invariant (rtx invariant_rtx
)
5594 invariant_t invariant
;
5595 invariant_ptr_t invariant_ptr
;
5597 invariant
.invariant_rtx
= invariant_rtx
;
5598 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5599 if (*entry_ptr
== NULL
)
5601 invariant_ptr
= invariants_pool
->allocate ();
5602 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5603 invariant_ptr
->insn
= NULL
;
5604 invariants
.safe_push (invariant_ptr
);
5605 *entry_ptr
= (void *) invariant_ptr
;
5607 return (invariant_ptr_t
) *entry_ptr
;
5610 /* Initiate the invariant table. */
5612 initiate_invariants (void)
5614 invariants
.create (100);
5616 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5617 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5620 /* Finish the invariant table. */
5622 finish_invariants (void)
5624 htab_delete (invariant_table
);
5625 delete invariants_pool
;
5626 invariants
.release ();
5629 /* Make the invariant table empty. */
5631 clear_invariants (void)
5633 htab_empty (invariant_table
);
5634 invariants_pool
->release ();
5635 invariants
.truncate (0);
5640 /* This page contains code to do inheritance/split
5643 /* Number of reloads passed so far in current EBB. */
5644 static int reloads_num
;
5646 /* Number of calls passed so far in current EBB. */
5647 static int calls_num
;
5649 /* Index ID is the CALLS_NUM associated the last call we saw with
5650 ABI identifier ID. */
5651 static int last_call_for_abi
[NUM_ABI_IDS
];
5653 /* Which registers have been fully or partially clobbered by a call
5654 since they were last used. */
5655 static HARD_REG_SET full_and_partial_call_clobbers
;
5657 /* Current reload pseudo check for validity of elements in
5659 static int curr_usage_insns_check
;
5661 /* Info about last usage of registers in EBB to do inheritance/split
5662 transformation. Inheritance transformation is done from a spilled
5663 pseudo and split transformations from a hard register or a pseudo
5664 assigned to a hard register. */
5667 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5668 value INSNS is valid. The insns is chain of optional debug insns
5669 and a finishing non-debug insn using the corresponding reg. The
5670 value is also used to mark the registers which are set up in the
5671 current insn. The negated insn uid is used for this. */
5673 /* Value of global reloads_num at the last insn in INSNS. */
5675 /* Value of global reloads_nums at the last insn in INSNS. */
5677 /* It can be true only for splitting. And it means that the restore
5678 insn should be put after insn given by the following member. */
5680 /* Next insns in the current EBB which use the original reg and the
5681 original reg value is not changed between the current insn and
5682 the next insns. In order words, e.g. for inheritance, if we need
5683 to use the original reg value again in the next insns we can try
5684 to use the value in a hard register from a reload insn of the
5689 /* Map: regno -> corresponding pseudo usage insns. */
5690 static struct usage_insns
*usage_insns
;
5693 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5695 usage_insns
[regno
].check
= curr_usage_insns_check
;
5696 usage_insns
[regno
].insns
= insn
;
5697 usage_insns
[regno
].reloads_num
= reloads_num
;
5698 usage_insns
[regno
].calls_num
= calls_num
;
5699 usage_insns
[regno
].after_p
= after_p
;
5700 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5701 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5702 PSEUDO_REGNO_MODE (regno
),
5703 reg_renumber
[regno
]);
5706 /* The function is used to form list REGNO usages which consists of
5707 optional debug insns finished by a non-debug insn using REGNO.
5708 RELOADS_NUM is current number of reload insns processed so far. */
5710 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5712 rtx next_usage_insns
;
5714 if (usage_insns
[regno
].check
== curr_usage_insns_check
5715 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5716 && DEBUG_INSN_P (insn
))
5718 /* Check that we did not add the debug insn yet. */
5719 if (next_usage_insns
!= insn
5720 && (GET_CODE (next_usage_insns
) != INSN_LIST
5721 || XEXP (next_usage_insns
, 0) != insn
))
5722 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5725 else if (NONDEBUG_INSN_P (insn
))
5726 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5728 usage_insns
[regno
].check
= 0;
5731 /* Return first non-debug insn in list USAGE_INSNS. */
5733 skip_usage_debug_insns (rtx usage_insns
)
5737 /* Skip debug insns. */
5738 for (insn
= usage_insns
;
5739 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5740 insn
= XEXP (insn
, 1))
5742 return safe_as_a
<rtx_insn
*> (insn
);
5745 /* Return true if we need secondary memory moves for insn in
5746 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5749 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5750 rtx usage_insns ATTRIBUTE_UNUSED
)
5756 if (inher_cl
== ALL_REGS
5757 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5759 lra_assert (INSN_P (insn
));
5760 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5762 dest
= SET_DEST (set
);
5765 lra_assert (inher_cl
!= NO_REGS
);
5766 cl
= get_reg_class (REGNO (dest
));
5767 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5768 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5771 /* Registers involved in inheritance/split in the current EBB
5772 (inheritance/split pseudos and original registers). */
5773 static bitmap_head check_only_regs
;
5775 /* Reload pseudos cannot be involded in invariant inheritance in the
5777 static bitmap_head invalid_invariant_regs
;
5779 /* Do inheritance transformations for insn INSN, which defines (if
5780 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5781 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5782 form as the "insns" field of usage_insns. Return true if we
5783 succeed in such transformation.
5785 The transformations look like:
5788 ... p <- i (new insn)
5790 <- ... p ... <- ... i ...
5792 ... i <- p (new insn)
5793 <- ... p ... <- ... i ...
5795 <- ... p ... <- ... i ...
5796 where p is a spilled original pseudo and i is a new inheritance pseudo.
5799 The inheritance pseudo has the smallest class of two classes CL and
5800 class of ORIGINAL REGNO. */
5802 inherit_reload_reg (bool def_p
, int original_regno
,
5803 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5805 if (optimize_function_for_size_p (cfun
))
5808 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5809 rtx original_reg
= regno_reg_rtx
[original_regno
];
5810 rtx new_reg
, usage_insn
;
5811 rtx_insn
*new_insns
;
5813 lra_assert (! usage_insns
[original_regno
].after_p
);
5814 if (lra_dump_file
!= NULL
)
5815 fprintf (lra_dump_file
,
5816 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5817 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5819 if (lra_dump_file
!= NULL
)
5821 fprintf (lra_dump_file
,
5822 " Rejecting inheritance for %d "
5823 "because of disjoint classes %s and %s\n",
5824 original_regno
, reg_class_names
[cl
],
5825 reg_class_names
[rclass
]);
5826 fprintf (lra_dump_file
,
5827 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5831 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5832 /* We don't use a subset of two classes because it can be
5833 NO_REGS. This transformation is still profitable in most
5834 cases even if the classes are not intersected as register
5835 move is probably cheaper than a memory load. */
5836 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5838 if (lra_dump_file
!= NULL
)
5839 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5840 reg_class_names
[cl
], reg_class_names
[rclass
]);
5844 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5846 /* Reject inheritance resulting in secondary memory moves.
5847 Otherwise, there is a danger in LRA cycling. Also such
5848 transformation will be unprofitable. */
5849 if (lra_dump_file
!= NULL
)
5851 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5852 rtx set
= single_set (insn
);
5854 lra_assert (set
!= NULL_RTX
);
5856 rtx dest
= SET_DEST (set
);
5858 lra_assert (REG_P (dest
));
5859 fprintf (lra_dump_file
,
5860 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5861 "as secondary mem is needed\n",
5862 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5863 original_regno
, reg_class_names
[rclass
]);
5864 fprintf (lra_dump_file
,
5865 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5869 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5870 rclass
, NULL
, "inheritance");
5873 lra_emit_move (original_reg
, new_reg
);
5875 lra_emit_move (new_reg
, original_reg
);
5876 new_insns
= get_insns ();
5878 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5880 if (lra_dump_file
!= NULL
)
5882 fprintf (lra_dump_file
,
5883 " Rejecting inheritance %d->%d "
5884 "as it results in 2 or more insns:\n",
5885 original_regno
, REGNO (new_reg
));
5886 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5887 fprintf (lra_dump_file
,
5888 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5892 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5893 lra_update_insn_regno_info (insn
);
5895 /* We now have a new usage insn for original regno. */
5896 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5897 if (lra_dump_file
!= NULL
)
5898 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5899 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5900 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5901 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5902 bitmap_set_bit (&check_only_regs
, original_regno
);
5903 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5905 lra_process_new_insns (insn
, NULL
, new_insns
,
5906 "Add original<-inheritance");
5908 lra_process_new_insns (insn
, new_insns
, NULL
,
5909 "Add inheritance<-original");
5910 while (next_usage_insns
!= NULL_RTX
)
5912 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5914 usage_insn
= next_usage_insns
;
5915 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5916 next_usage_insns
= NULL
;
5920 usage_insn
= XEXP (next_usage_insns
, 0);
5921 lra_assert (DEBUG_INSN_P (usage_insn
));
5922 next_usage_insns
= XEXP (next_usage_insns
, 1);
5924 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5925 DEBUG_INSN_P (usage_insn
));
5926 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5927 if (lra_dump_file
!= NULL
)
5929 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5930 fprintf (lra_dump_file
,
5931 " Inheritance reuse change %d->%d (bb%d):\n",
5932 original_regno
, REGNO (new_reg
),
5933 bb
? bb
->index
: -1);
5934 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5937 if (lra_dump_file
!= NULL
)
5938 fprintf (lra_dump_file
,
5939 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5943 /* Return true if we need a caller save/restore for pseudo REGNO which
5944 was assigned to a hard register. */
5946 need_for_call_save_p (int regno
)
5948 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5949 if (usage_insns
[regno
].calls_num
< calls_num
)
5951 unsigned int abis
= 0;
5952 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5953 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5956 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5957 PSEUDO_REGNO_MODE (regno
),
5958 reg_renumber
[regno
]))
5964 /* Global registers occurring in the current EBB. */
5965 static bitmap_head ebb_global_regs
;
5967 /* Return true if we need a split for hard register REGNO or pseudo
5968 REGNO which was assigned to a hard register.
5969 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5970 used for reloads since the EBB end. It is an approximation of the
5971 used hard registers in the split range. The exact value would
5972 require expensive calculations. If we were aggressive with
5973 splitting because of the approximation, the split pseudo will save
5974 the same hard register assignment and will be removed in the undo
5975 pass. We still need the approximation because too aggressive
5976 splitting would result in too inaccurate cost calculation in the
5977 assignment pass because of too many generated moves which will be
5978 probably removed in the undo pass. */
5980 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5982 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5984 lra_assert (hard_regno
>= 0);
5985 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5986 /* Don't split eliminable hard registers, otherwise we can
5987 split hard registers like hard frame pointer, which
5988 lives on BB start/end according to DF-infrastructure,
5989 when there is a pseudo assigned to the register and
5990 living in the same BB. */
5991 && (regno
>= FIRST_PSEUDO_REGISTER
5992 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5993 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5994 /* Don't split call clobbered hard regs living through
5995 calls, otherwise we might have a check problem in the
5996 assign sub-pass as in the most cases (exception is a
5997 situation when check_and_force_assignment_correctness_p value is
5998 true) the assign pass assumes that all pseudos living
5999 through calls are assigned to call saved hard regs. */
6000 && (regno
>= FIRST_PSEUDO_REGISTER
6001 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
6002 /* We need at least 2 reloads to make pseudo splitting
6003 profitable. We should provide hard regno splitting in
6004 any case to solve 1st insn scheduling problem when
6005 moving hard register definition up might result in
6006 impossibility to find hard register for reload pseudo of
6007 small register class. */
6008 && (usage_insns
[regno
].reloads_num
6009 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
6010 && (regno
< FIRST_PSEUDO_REGISTER
6011 /* For short living pseudos, spilling + inheritance can
6012 be considered a substitution for splitting.
6013 Therefore we do not splitting for local pseudos. It
6014 decreases also aggressiveness of splitting. The
6015 minimal number of references is chosen taking into
6016 account that for 2 references splitting has no sense
6017 as we can just spill the pseudo. */
6018 || (regno
>= FIRST_PSEUDO_REGISTER
6019 && lra_reg_info
[regno
].nrefs
> 3
6020 && bitmap_bit_p (&ebb_global_regs
, regno
))))
6021 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
6024 /* Return class for the split pseudo created from original pseudo with
6025 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
6026 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
6027 results in no secondary memory movements. */
6028 static enum reg_class
6029 choose_split_class (enum reg_class allocno_class
,
6030 int hard_regno ATTRIBUTE_UNUSED
,
6031 machine_mode mode ATTRIBUTE_UNUSED
)
6034 enum reg_class cl
, best_cl
= NO_REGS
;
6035 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
6036 = REGNO_REG_CLASS (hard_regno
);
6038 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
6039 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
6040 return allocno_class
;
6042 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
6044 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
6045 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
6046 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
6047 && (best_cl
== NO_REGS
6048 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
6053 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. It only
6054 makes sense to call this function if NEW_REGNO is always equal to
6055 ORIGINAL_REGNO. Set up defined_p flag when caller_save_p flag is set up and
6056 CALL_SAVE_P is true. */
6059 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
,
6062 if (!ira_reg_equiv
[original_regno
].defined_p
6063 && !(call_save_p
&& ira_reg_equiv
[original_regno
].caller_save_p
))
6066 ira_expand_reg_equiv ();
6067 ira_reg_equiv
[new_regno
].defined_p
= true;
6068 if (ira_reg_equiv
[original_regno
].memory
)
6069 ira_reg_equiv
[new_regno
].memory
6070 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
6071 if (ira_reg_equiv
[original_regno
].constant
)
6072 ira_reg_equiv
[new_regno
].constant
6073 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
6074 if (ira_reg_equiv
[original_regno
].invariant
)
6075 ira_reg_equiv
[new_regno
].invariant
6076 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
6079 /* Do split transformations for insn INSN, which defines or uses
6080 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
6081 the EBB next uses ORIGINAL_REGNO; it has the same form as the
6082 "insns" field of usage_insns. If TO is not NULL, we don't use
6083 usage_insns, we put restore insns after TO insn. It is a case when
6084 we call it from lra_split_hard_reg_for, outside the inheritance
6087 The transformations look like:
6090 ... s <- p (new insn -- save)
6092 ... p <- s (new insn -- restore)
6093 <- ... p ... <- ... p ...
6095 <- ... p ... <- ... p ...
6096 ... s <- p (new insn -- save)
6098 ... p <- s (new insn -- restore)
6099 <- ... p ... <- ... p ...
6101 where p is an original pseudo got a hard register or a hard
6102 register and s is a new split pseudo. The save is put before INSN
6103 if BEFORE_P is true. Return true if we succeed in such
6106 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
6107 rtx next_usage_insns
, rtx_insn
*to
)
6109 enum reg_class rclass
;
6111 int hard_regno
, nregs
;
6112 rtx new_reg
, usage_insn
;
6113 rtx_insn
*restore
, *save
;
6118 if (original_regno
< FIRST_PSEUDO_REGISTER
)
6120 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
6121 hard_regno
= original_regno
;
6122 call_save_p
= false;
6124 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
6125 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
6126 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
6127 part of a multi-word register. In that case, just use the reg_rtx
6128 mode. Do the same also if the biggest mode was larger than a register
6129 or we can not compare the modes. Otherwise, limit the size to that of
6130 the biggest access in the function or to the natural mode at least. */
6131 if (mode
== VOIDmode
6132 || !ordered_p (GET_MODE_PRECISION (mode
),
6133 GET_MODE_PRECISION (reg_rtx_mode
))
6134 || paradoxical_subreg_p (mode
, reg_rtx_mode
)
6135 || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode
), GET_MODE_PRECISION (mode
)))
6137 original_reg
= regno_reg_rtx
[hard_regno
];
6138 mode
= reg_rtx_mode
;
6141 original_reg
= gen_rtx_REG (mode
, hard_regno
);
6145 mode
= PSEUDO_REGNO_MODE (original_regno
);
6146 hard_regno
= reg_renumber
[original_regno
];
6147 nregs
= hard_regno_nregs (hard_regno
, mode
);
6148 rclass
= lra_get_allocno_class (original_regno
);
6149 original_reg
= regno_reg_rtx
[original_regno
];
6150 call_save_p
= need_for_call_save_p (original_regno
);
6152 lra_assert (hard_regno
>= 0);
6153 if (lra_dump_file
!= NULL
)
6154 fprintf (lra_dump_file
,
6155 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
6159 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
6160 hard_regno_nregs (hard_regno
, mode
),
6162 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, NULL
, "save");
6166 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
6167 if (rclass
== NO_REGS
)
6169 if (lra_dump_file
!= NULL
)
6171 fprintf (lra_dump_file
,
6172 " Rejecting split of %d(%s): "
6173 "no good reg class for %d(%s)\n",
6175 reg_class_names
[lra_get_allocno_class (original_regno
)],
6177 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
6180 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6184 /* Split_if_necessary can split hard registers used as part of a
6185 multi-register mode but splits each register individually. The
6186 mode used for each independent register may not be supported
6187 so reject the split. Splitting the wider mode should theoretically
6188 be possible but is not implemented. */
6189 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
6191 if (lra_dump_file
!= NULL
)
6193 fprintf (lra_dump_file
,
6194 " Rejecting split of %d(%s): unsuitable mode %s\n",
6196 reg_class_names
[lra_get_allocno_class (original_regno
)],
6197 GET_MODE_NAME (mode
));
6200 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6204 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, NULL
, "split");
6205 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
6207 int new_regno
= REGNO (new_reg
);
6208 save
= emit_spill_move (true, new_reg
, original_reg
);
6209 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
6211 if (lra_dump_file
!= NULL
)
6215 " Rejecting split %d->%d resulting in > 2 save insns:\n",
6216 original_regno
, new_regno
);
6217 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
6218 fprintf (lra_dump_file
,
6219 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6223 restore
= emit_spill_move (false, new_reg
, original_reg
);
6224 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
6226 if (lra_dump_file
!= NULL
)
6228 fprintf (lra_dump_file
,
6229 " Rejecting split %d->%d "
6230 "resulting in > 2 restore insns:\n",
6231 original_regno
, new_regno
);
6232 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
6233 fprintf (lra_dump_file
,
6234 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6238 /* Transfer equivalence information to the spill register, so that
6239 if we fail to allocate the spill register, we have the option of
6240 rematerializing the original value instead of spilling to the stack. */
6241 if (!HARD_REGISTER_NUM_P (original_regno
)
6242 && mode
== PSEUDO_REGNO_MODE (original_regno
))
6243 lra_copy_reg_equiv (new_regno
, original_regno
, call_save_p
);
6244 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
6245 bitmap_set_bit (&lra_split_regs
, new_regno
);
6248 lra_assert (next_usage_insns
== NULL
);
6254 /* We need check_only_regs only inside the inheritance pass. */
6255 bitmap_set_bit (&check_only_regs
, new_regno
);
6256 bitmap_set_bit (&check_only_regs
, original_regno
);
6257 after_p
= usage_insns
[original_regno
].after_p
;
6260 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
6262 usage_insn
= next_usage_insns
;
6265 usage_insn
= XEXP (next_usage_insns
, 0);
6266 lra_assert (DEBUG_INSN_P (usage_insn
));
6267 next_usage_insns
= XEXP (next_usage_insns
, 1);
6268 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
6270 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
6271 if (lra_dump_file
!= NULL
)
6273 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
6274 original_regno
, new_regno
);
6275 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
6279 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
6280 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
6281 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
6282 after_p
? NULL
: restore
,
6283 after_p
? restore
: NULL
,
6285 ? "Add reg<-save" : "Add reg<-split");
6286 lra_process_new_insns (insn
, before_p
? save
: NULL
,
6287 before_p
? NULL
: save
,
6289 ? "Add save<-reg" : "Add split<-reg");
6290 if (nregs
> 1 || original_regno
< FIRST_PSEUDO_REGISTER
)
6291 /* If we are trying to split multi-register. We should check
6292 conflicts on the next assignment sub-pass. IRA can allocate on
6293 sub-register levels, LRA do this on pseudos level right now and
6294 this discrepancy may create allocation conflicts after
6297 If we are trying to split hard register we should also check conflicts
6298 as such splitting can create artificial conflict of the hard register
6299 with another pseudo because of simplified conflict calculation in
6301 check_and_force_assignment_correctness_p
= true;
6302 if (lra_dump_file
!= NULL
)
6303 fprintf (lra_dump_file
,
6304 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6308 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
6309 in the range [FROM, TO]. Return true if did a split. Otherwise,
6312 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
6319 HARD_REG_SET ignore
;
6321 lra_assert (from
!= NULL
&& to
!= NULL
);
6322 ignore
= lra_no_alloc_regs
;
6323 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
6325 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
6326 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
6327 struct lra_insn_reg
*reg
;
6329 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6330 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
6331 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6332 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6333 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6335 rclass_size
= ira_class_hard_regs_num
[rclass
];
6336 for (i
= 0; i
< rclass_size
; i
++)
6338 hard_regno
= ira_class_hard_regs
[rclass
][i
];
6339 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
6340 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
6342 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
6344 struct lra_static_insn_data
*static_id
;
6345 struct lra_insn_reg
*reg
;
6349 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
6352 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
6353 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6354 if (reg
->regno
== hard_regno
)
6359 if (insn
!= NEXT_INSN (to
))
6361 if (split_reg (true, hard_regno
, from
, NULL
, to
))
6367 /* Recognize that we need a split transformation for insn INSN, which
6368 defines or uses REGNO in its insn biggest MODE (we use it only if
6369 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
6370 hard registers which might be used for reloads since the EBB end.
6371 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
6372 uid before starting INSN processing. Return true if we succeed in
6373 such transformation. */
6375 split_if_necessary (int regno
, machine_mode mode
,
6376 HARD_REG_SET potential_reload_hard_regs
,
6377 bool before_p
, rtx_insn
*insn
, int max_uid
)
6381 rtx next_usage_insns
;
6383 if (regno
< FIRST_PSEUDO_REGISTER
)
6384 nregs
= hard_regno_nregs (regno
, mode
);
6385 for (i
= 0; i
< nregs
; i
++)
6386 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
6387 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
6388 /* To avoid processing the register twice or more. */
6389 && ((GET_CODE (next_usage_insns
) != INSN_LIST
6390 && INSN_UID (next_usage_insns
) < max_uid
)
6391 || (GET_CODE (next_usage_insns
) == INSN_LIST
6392 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
6393 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
6394 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
6399 /* Return TRUE if rtx X is considered as an invariant for
6402 invariant_p (const_rtx x
)
6409 if (side_effects_p (x
))
6412 code
= GET_CODE (x
);
6413 mode
= GET_MODE (x
);
6417 code
= GET_CODE (x
);
6418 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
6426 int i
, nregs
, regno
= REGNO (x
);
6428 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
6429 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
6430 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
6432 nregs
= hard_regno_nregs (regno
, mode
);
6433 for (i
= 0; i
< nregs
; i
++)
6434 if (! fixed_regs
[regno
+ i
]
6435 /* A hard register may be clobbered in the current insn
6436 but we can ignore this case because if the hard
6437 register is used it should be set somewhere after the
6439 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
6442 fmt
= GET_RTX_FORMAT (code
);
6443 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6447 if (! invariant_p (XEXP (x
, i
)))
6450 else if (fmt
[i
] == 'E')
6452 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6453 if (! invariant_p (XVECEXP (x
, i
, j
)))
6460 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6461 inheritance transformation (using dest_reg instead invariant in a
6462 subsequent insn). */
6464 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
6466 invariant_ptr_t invariant_ptr
;
6467 rtx_insn
*insn
, *new_insns
;
6468 rtx insn_set
, insn_reg
, new_reg
;
6470 bool succ_p
= false;
6471 int dst_regno
= REGNO (dst_reg
);
6472 machine_mode dst_mode
= GET_MODE (dst_reg
);
6473 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
6475 invariant_ptr
= insert_invariant (invariant_rtx
);
6476 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6478 /* We have a subsequent insn using the invariant. */
6479 insn_set
= single_set (insn
);
6480 lra_assert (insn_set
!= NULL
);
6481 insn_reg
= SET_DEST (insn_set
);
6482 lra_assert (REG_P (insn_reg
));
6483 insn_regno
= REGNO (insn_reg
);
6484 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6486 if (dst_mode
== GET_MODE (insn_reg
)
6487 /* We should consider only result move reg insns which are
6489 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6490 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6492 if (lra_dump_file
!= NULL
)
6493 fprintf (lra_dump_file
,
6494 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6495 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
, cl
, NULL
,
6496 "invariant inheritance");
6497 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6498 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6499 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6501 lra_emit_move (new_reg
, dst_reg
);
6502 new_insns
= get_insns ();
6504 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6505 "Add invariant inheritance<-original");
6507 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6508 new_insns
= get_insns ();
6510 lra_process_new_insns (insn
, NULL
, new_insns
,
6511 "Changing reload<-inheritance");
6512 lra_set_insn_deleted (insn
);
6514 if (lra_dump_file
!= NULL
)
6516 fprintf (lra_dump_file
,
6517 " Invariant inheritance reuse change %d (bb%d):\n",
6518 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6519 dump_insn_slim (lra_dump_file
, insn
);
6520 fprintf (lra_dump_file
,
6521 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6525 invariant_ptr
->insn
= curr_insn
;
6529 /* Check only registers living at the current program point in the
6531 static bitmap_head live_regs
;
6533 /* Update live info in EBB given by its HEAD and TAIL insns after
6534 inheritance/split transformation. The function removes dead moves
6537 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6542 rtx_insn
*prev_insn
;
6545 basic_block last_bb
, prev_bb
, curr_bb
;
6547 struct lra_insn_reg
*reg
;
6551 last_bb
= BLOCK_FOR_INSN (tail
);
6553 for (curr_insn
= tail
;
6554 curr_insn
!= PREV_INSN (head
);
6555 curr_insn
= prev_insn
)
6557 prev_insn
= PREV_INSN (curr_insn
);
6558 /* We need to process empty blocks too. They contain
6559 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6560 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6562 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6563 if (curr_bb
!= prev_bb
)
6565 if (prev_bb
!= NULL
)
6567 /* Update df_get_live_in (prev_bb): */
6568 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6569 if (bitmap_bit_p (&live_regs
, j
))
6570 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6572 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6574 if (curr_bb
!= last_bb
)
6576 /* Update df_get_live_out (curr_bb): */
6577 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6579 live_p
= bitmap_bit_p (&live_regs
, j
);
6581 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6582 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6588 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6590 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6594 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6596 if (! NONDEBUG_INSN_P (curr_insn
))
6598 curr_id
= lra_get_insn_recog_data (curr_insn
);
6599 curr_static_id
= curr_id
->insn_static_data
;
6601 if ((set
= single_set (curr_insn
)) != NULL_RTX
6602 && REG_P (SET_DEST (set
))
6603 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6604 && SET_DEST (set
) != pic_offset_table_rtx
6605 && bitmap_bit_p (&check_only_regs
, regno
)
6606 && ! bitmap_bit_p (&live_regs
, regno
))
6608 /* See which defined values die here. */
6609 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6610 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6611 bitmap_clear_bit (&live_regs
, reg
->regno
);
6612 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6613 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6614 bitmap_clear_bit (&live_regs
, reg
->regno
);
6615 if (curr_id
->arg_hard_regs
!= NULL
)
6616 /* Make clobbered argument hard registers die. */
6617 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6618 if (regno
>= FIRST_PSEUDO_REGISTER
)
6619 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6620 /* Mark each used value as live. */
6621 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6622 if (reg
->type
!= OP_OUT
6623 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6624 bitmap_set_bit (&live_regs
, reg
->regno
);
6625 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6626 if (reg
->type
!= OP_OUT
6627 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6628 bitmap_set_bit (&live_regs
, reg
->regno
);
6629 if (curr_id
->arg_hard_regs
!= NULL
)
6630 /* Make used argument hard registers live. */
6631 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6632 if (regno
< FIRST_PSEUDO_REGISTER
6633 && bitmap_bit_p (&check_only_regs
, regno
))
6634 bitmap_set_bit (&live_regs
, regno
);
6635 /* It is quite important to remove dead move insns because it
6636 means removing dead store. We don't need to process them for
6640 if (lra_dump_file
!= NULL
)
6642 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6643 dump_insn_slim (lra_dump_file
, curr_insn
);
6645 lra_set_insn_deleted (curr_insn
);
6650 /* The structure describes info to do an inheritance for the current
6651 insn. We need to collect such info first before doing the
6652 transformations because the transformations change the insn
6653 internal representation. */
6656 /* Original regno. */
6658 /* Subsequent insns which can inherit original reg value. */
6662 /* Array containing all info for doing inheritance from the current
6664 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6666 /* Number elements in the previous array. */
6667 static int to_inherit_num
;
6669 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6670 structure to_inherit. */
6672 add_to_inherit (int regno
, rtx insns
)
6676 for (i
= 0; i
< to_inherit_num
; i
++)
6677 if (to_inherit
[i
].regno
== regno
)
6679 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6680 to_inherit
[to_inherit_num
].regno
= regno
;
6681 to_inherit
[to_inherit_num
++].insns
= insns
;
6684 /* Return the last non-debug insn in basic block BB, or the block begin
6687 get_last_insertion_point (basic_block bb
)
6691 FOR_BB_INSNS_REVERSE (bb
, insn
)
6692 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6697 /* Set up RES by registers living on edges FROM except the edge (FROM,
6698 TO) or by registers set up in a jump insn in BB FROM. */
6700 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6703 struct lra_insn_reg
*reg
;
6707 lra_assert (to
!= NULL
);
6709 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6711 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6712 last
= get_last_insertion_point (from
);
6713 if (! JUMP_P (last
))
6715 curr_id
= lra_get_insn_recog_data (last
);
6716 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6717 if (reg
->type
!= OP_IN
)
6718 bitmap_set_bit (res
, reg
->regno
);
6721 /* Used as a temporary results of some bitmap calculations. */
6722 static bitmap_head temp_bitmap
;
6724 /* We split for reloads of small class of hard regs. The following
6725 defines how many hard regs the class should have to be qualified as
6726 small. The code is mostly oriented to x86/x86-64 architecture
6727 where some insns need to use only specific register or pair of
6728 registers and these register can live in RTL explicitly, e.g. for
6729 parameter passing. */
6730 static const int max_small_class_regs_num
= 2;
6732 /* Do inheritance/split transformations in EBB starting with HEAD and
6733 finishing on TAIL. We process EBB insns in the reverse order.
6734 Return true if we did any inheritance/split transformation in the
6737 We should avoid excessive splitting which results in worse code
6738 because of inaccurate cost calculations for spilling new split
6739 pseudos in such case. To achieve this we do splitting only if
6740 register pressure is high in given basic block and there are reload
6741 pseudos requiring hard registers. We could do more register
6742 pressure calculations at any given program point to avoid necessary
6743 splitting even more but it is to expensive and the current approach
6744 works well enough. */
6746 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6748 int i
, src_regno
, dst_regno
, nregs
;
6749 bool change_p
, succ_p
, update_reloads_num_p
;
6750 rtx_insn
*prev_insn
, *last_insn
;
6751 rtx next_usage_insns
, curr_set
;
6753 struct lra_insn_reg
*reg
;
6754 basic_block last_processed_bb
, curr_bb
= NULL
;
6755 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6759 bool head_p
, after_p
;
6762 curr_usage_insns_check
++;
6763 clear_invariants ();
6764 reloads_num
= calls_num
= 0;
6765 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6766 last_call_for_abi
[i
] = 0;
6767 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6768 bitmap_clear (&check_only_regs
);
6769 bitmap_clear (&invalid_invariant_regs
);
6770 last_processed_bb
= NULL
;
6771 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6772 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6773 /* We don't process new insns generated in the loop. */
6774 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6776 prev_insn
= PREV_INSN (curr_insn
);
6777 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6778 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6779 if (last_processed_bb
!= curr_bb
)
6781 /* We are at the end of BB. Add qualified living
6782 pseudos for potential splitting. */
6783 to_process
= df_get_live_out (curr_bb
);
6784 if (last_processed_bb
!= NULL
)
6786 /* We are somewhere in the middle of EBB. */
6787 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6789 to_process
= &temp_bitmap
;
6791 last_processed_bb
= curr_bb
;
6792 last_insn
= get_last_insertion_point (curr_bb
);
6793 after_p
= (! JUMP_P (last_insn
)
6794 && (! CALL_P (last_insn
)
6795 || (find_reg_note (last_insn
,
6796 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6797 && ! SIBLING_CALL_P (last_insn
))));
6798 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6799 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6801 if ((int) j
>= lra_constraint_new_regno_start
)
6803 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6805 if (j
< FIRST_PSEUDO_REGISTER
)
6806 SET_HARD_REG_BIT (live_hard_regs
, j
);
6808 add_to_hard_reg_set (&live_hard_regs
,
6809 PSEUDO_REGNO_MODE (j
),
6811 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6815 src_regno
= dst_regno
= -1;
6816 curr_set
= single_set (curr_insn
);
6817 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6818 dst_regno
= REGNO (SET_DEST (curr_set
));
6819 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6820 src_regno
= REGNO (SET_SRC (curr_set
));
6821 update_reloads_num_p
= true;
6822 if (src_regno
< lra_constraint_new_regno_start
6823 && src_regno
>= FIRST_PSEUDO_REGISTER
6824 && reg_renumber
[src_regno
] < 0
6825 && dst_regno
>= lra_constraint_new_regno_start
6826 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6828 /* 'reload_pseudo <- original_pseudo'. */
6829 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6831 update_reloads_num_p
= false;
6833 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6834 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6835 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6836 curr_insn
, next_usage_insns
);
6840 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6841 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6842 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6844 else if (src_regno
< 0
6845 && dst_regno
>= lra_constraint_new_regno_start
6846 && invariant_p (SET_SRC (curr_set
))
6847 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6848 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6849 && ! bitmap_bit_p (&invalid_invariant_regs
,
6850 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6852 /* 'reload_pseudo <- invariant'. */
6853 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6855 update_reloads_num_p
= false;
6856 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6858 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6859 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6861 else if (src_regno
>= lra_constraint_new_regno_start
6862 && dst_regno
< lra_constraint_new_regno_start
6863 && dst_regno
>= FIRST_PSEUDO_REGISTER
6864 && reg_renumber
[dst_regno
] < 0
6865 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6866 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6867 && (next_usage_insns
6868 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6870 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6872 update_reloads_num_p
= false;
6873 /* 'original_pseudo <- reload_pseudo'. */
6874 if (! JUMP_P (curr_insn
)
6875 && inherit_reload_reg (true, dst_regno
, cl
,
6876 curr_insn
, next_usage_insns
))
6879 usage_insns
[dst_regno
].check
= 0;
6880 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6881 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6883 else if (INSN_P (curr_insn
))
6886 int max_uid
= get_max_uid ();
6888 curr_id
= lra_get_insn_recog_data (curr_insn
);
6889 curr_static_id
= curr_id
->insn_static_data
;
6891 /* Process insn definitions. */
6892 for (iter
= 0; iter
< 2; iter
++)
6893 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6896 if (reg
->type
!= OP_IN
6897 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6899 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6900 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6901 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6902 && (next_usage_insns
6903 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6905 struct lra_insn_reg
*r
;
6907 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6908 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6910 /* Don't do inheritance if the pseudo is also
6911 used in the insn. */
6913 /* We cannot do inheritance right now
6914 because the current insn reg info (chain
6915 regs) can change after that. */
6916 add_to_inherit (dst_regno
, next_usage_insns
);
6918 /* We cannot process one reg twice here because of
6919 usage_insns invalidation. */
6920 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6921 || reg_renumber
[dst_regno
] >= 0)
6922 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6926 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6927 potential_reload_hard_regs
,
6928 false, curr_insn
, max_uid
))
6930 CLEAR_HARD_REG_SET (s
);
6931 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6932 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6934 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6935 reg_renumber
[dst_regno
]);
6936 live_hard_regs
&= ~s
;
6937 potential_reload_hard_regs
&= ~s
;
6939 /* We should invalidate potential inheritance or
6940 splitting for the current insn usages to the next
6941 usage insns (see code below) as the output pseudo
6943 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6944 && reg_renumber
[dst_regno
] < 0)
6945 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6946 && (dst_regno
< FIRST_PSEUDO_REGISTER
6947 || reg_renumber
[dst_regno
] >= 0)))
6949 /* Invalidate and mark definitions. */
6950 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6951 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6954 nregs
= hard_regno_nregs (dst_regno
,
6956 for (i
= 0; i
< nregs
; i
++)
6957 usage_insns
[dst_regno
+ i
].check
6958 = -(int) INSN_UID (curr_insn
);
6962 /* Process clobbered call regs. */
6963 if (curr_id
->arg_hard_regs
!= NULL
)
6964 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6965 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6966 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6967 = -(int) INSN_UID (curr_insn
);
6968 if (! JUMP_P (curr_insn
))
6969 for (i
= 0; i
< to_inherit_num
; i
++)
6970 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6971 ALL_REGS
, curr_insn
,
6972 to_inherit
[i
].insns
))
6974 if (CALL_P (curr_insn
))
6976 rtx cheap
, pat
, dest
;
6978 int regno
, hard_regno
;
6981 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6982 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6983 full_and_partial_call_clobbers
6984 |= callee_abi
.full_and_partial_reg_clobbers ();
6985 if ((cheap
= find_reg_note (curr_insn
,
6986 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6987 && ((cheap
= XEXP (cheap
, 0)), true)
6988 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6989 && (hard_regno
= reg_renumber
[regno
]) >= 0
6990 && usage_insns
[regno
].check
== curr_usage_insns_check
6991 /* If there are pending saves/restores, the
6992 optimization is not worth. */
6993 && usage_insns
[regno
].calls_num
== calls_num
- 1
6994 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6996 /* Restore the pseudo from the call result as
6997 REG_RETURNED note says that the pseudo value is
6998 in the call result and the pseudo is an argument
7000 pat
= PATTERN (curr_insn
);
7001 if (GET_CODE (pat
) == PARALLEL
)
7002 pat
= XVECEXP (pat
, 0, 0);
7003 dest
= SET_DEST (pat
);
7004 /* For multiple return values dest is PARALLEL.
7005 Currently we handle only single return value case. */
7009 emit_move_insn (cheap
, copy_rtx (dest
));
7010 restore
= get_insns ();
7012 lra_process_new_insns (curr_insn
, NULL
, restore
,
7013 "Inserting call parameter restore");
7014 /* We don't need to save/restore of the pseudo from
7016 usage_insns
[regno
].calls_num
= calls_num
;
7017 remove_from_hard_reg_set
7018 (&full_and_partial_call_clobbers
,
7019 GET_MODE (cheap
), hard_regno
);
7020 bitmap_set_bit (&check_only_regs
, regno
);
7025 /* Process insn usages. */
7026 for (iter
= 0; iter
< 2; iter
++)
7027 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
7030 if ((reg
->type
!= OP_OUT
7031 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
7032 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
7034 if (src_regno
>= FIRST_PSEUDO_REGISTER
7035 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
7037 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
7038 && (next_usage_insns
7039 = usage_insns
[src_regno
].insns
) != NULL_RTX
7040 && NONDEBUG_INSN_P (curr_insn
))
7041 add_to_inherit (src_regno
, next_usage_insns
);
7042 else if (usage_insns
[src_regno
].check
7043 != -(int) INSN_UID (curr_insn
))
7044 /* Add usages but only if the reg is not set up
7045 in the same insn. */
7046 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
7048 else if (src_regno
< FIRST_PSEUDO_REGISTER
7049 || reg_renumber
[src_regno
] >= 0)
7052 rtx_insn
*use_insn
= curr_insn
;
7054 before_p
= (JUMP_P (curr_insn
)
7055 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
7056 if (NONDEBUG_INSN_P (curr_insn
)
7057 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
7058 && split_if_necessary (src_regno
, reg
->biggest_mode
,
7059 potential_reload_hard_regs
,
7060 before_p
, curr_insn
, max_uid
))
7063 check_and_force_assignment_correctness_p
= true;
7066 usage_insns
[src_regno
].check
= 0;
7068 use_insn
= PREV_INSN (curr_insn
);
7070 if (NONDEBUG_INSN_P (curr_insn
))
7072 if (src_regno
< FIRST_PSEUDO_REGISTER
)
7073 add_to_hard_reg_set (&live_hard_regs
,
7074 reg
->biggest_mode
, src_regno
);
7076 add_to_hard_reg_set (&live_hard_regs
,
7077 PSEUDO_REGNO_MODE (src_regno
),
7078 reg_renumber
[src_regno
]);
7080 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
7081 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
7084 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
7085 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
7089 /* Process used call regs. */
7090 if (curr_id
->arg_hard_regs
!= NULL
)
7091 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7092 if (src_regno
< FIRST_PSEUDO_REGISTER
)
7094 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
7095 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
7097 for (i
= 0; i
< to_inherit_num
; i
++)
7099 src_regno
= to_inherit
[i
].regno
;
7100 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
7101 curr_insn
, to_inherit
[i
].insns
))
7104 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
7107 if (update_reloads_num_p
7108 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
7111 if ((REG_P (SET_DEST (curr_set
))
7112 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
7113 && reg_renumber
[regno
] < 0
7114 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
7115 || (REG_P (SET_SRC (curr_set
))
7116 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
7117 && reg_renumber
[regno
] < 0
7118 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
7120 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
7122 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
7123 potential_reload_hard_regs
|= reg_class_contents
[cl
];
7126 if (NONDEBUG_INSN_P (curr_insn
))
7130 /* Invalidate invariants with changed regs. */
7131 curr_id
= lra_get_insn_recog_data (curr_insn
);
7132 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7133 if (reg
->type
!= OP_IN
)
7135 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7136 bitmap_set_bit (&invalid_invariant_regs
,
7137 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
7139 curr_static_id
= curr_id
->insn_static_data
;
7140 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
7141 if (reg
->type
!= OP_IN
)
7142 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7143 if (curr_id
->arg_hard_regs
!= NULL
)
7144 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7145 if (regno
>= FIRST_PSEUDO_REGISTER
)
7146 bitmap_set_bit (&invalid_invariant_regs
,
7147 regno
- FIRST_PSEUDO_REGISTER
);
7149 /* We reached the start of the current basic block. */
7150 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
7151 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
7153 /* We reached the beginning of the current block -- do
7154 rest of spliting in the current BB. */
7155 to_process
= df_get_live_in (curr_bb
);
7156 if (BLOCK_FOR_INSN (head
) != curr_bb
)
7158 /* We are somewhere in the middle of EBB. */
7159 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
7160 curr_bb
, &temp_bitmap
);
7161 to_process
= &temp_bitmap
;
7164 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
7166 if ((int) j
>= lra_constraint_new_regno_start
)
7168 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
7169 && usage_insns
[j
].check
== curr_usage_insns_check
7170 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
7172 if (need_for_split_p (potential_reload_hard_regs
, j
))
7174 if (lra_dump_file
!= NULL
&& head_p
)
7176 fprintf (lra_dump_file
,
7177 " ----------------------------------\n");
7180 if (split_reg (false, j
, bb_note (curr_bb
),
7181 next_usage_insns
, NULL
))
7184 usage_insns
[j
].check
= 0;
7192 /* This value affects EBB forming. If probability of edge from EBB to
7193 a BB is not greater than the following value, we don't add the BB
7195 #define EBB_PROBABILITY_CUTOFF \
7196 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
7198 /* Current number of inheritance/split iteration. */
7199 int lra_inheritance_iter
;
7201 /* Entry function for inheritance/split pass. */
7203 lra_inheritance (void)
7206 basic_block bb
, start_bb
;
7209 lra_inheritance_iter
++;
7210 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7212 timevar_push (TV_LRA_INHERITANCE
);
7213 if (lra_dump_file
!= NULL
)
7214 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
7215 lra_inheritance_iter
);
7216 curr_usage_insns_check
= 0;
7217 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
7218 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
7219 usage_insns
[i
].check
= 0;
7220 bitmap_initialize (&check_only_regs
, ®_obstack
);
7221 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
7222 bitmap_initialize (&live_regs
, ®_obstack
);
7223 bitmap_initialize (&temp_bitmap
, ®_obstack
);
7224 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
7225 FOR_EACH_BB_FN (bb
, cfun
)
7228 if (lra_dump_file
!= NULL
)
7229 fprintf (lra_dump_file
, "EBB");
7230 /* Form a EBB starting with BB. */
7231 bitmap_clear (&ebb_global_regs
);
7232 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
7235 if (lra_dump_file
!= NULL
)
7236 fprintf (lra_dump_file
, " %d", bb
->index
);
7237 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
7238 || LABEL_P (BB_HEAD (bb
->next_bb
)))
7240 e
= find_fallthru_edge (bb
->succs
);
7243 if (e
->probability
.initialized_p ()
7244 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
7248 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
7249 if (lra_dump_file
!= NULL
)
7250 fprintf (lra_dump_file
, "\n");
7251 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
7252 /* Remember that the EBB head and tail can change in
7254 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
7256 bitmap_release (&ebb_global_regs
);
7257 bitmap_release (&temp_bitmap
);
7258 bitmap_release (&live_regs
);
7259 bitmap_release (&invalid_invariant_regs
);
7260 bitmap_release (&check_only_regs
);
7263 timevar_pop (TV_LRA_INHERITANCE
);
7268 /* This page contains code to undo failed inheritance/split
7271 /* Current number of iteration undoing inheritance/split. */
7272 int lra_undo_inheritance_iter
;
7274 /* Fix BB live info LIVE after removing pseudos created on pass doing
7275 inheritance/split which are REMOVED_PSEUDOS. */
7277 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
7282 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
7283 if (bitmap_clear_bit (live
, regno
)
7284 && REG_P (lra_reg_info
[regno
].restore_rtx
))
7285 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
7288 /* Return regno of the (subreg of) REG. Otherwise, return a negative
7293 if (GET_CODE (reg
) == SUBREG
)
7294 reg
= SUBREG_REG (reg
);
7300 /* Delete a move INSN with destination reg DREGNO and a previous
7301 clobber insn with the same regno. The inheritance/split code can
7302 generate moves with preceding clobber and when we delete such moves
7303 we should delete the clobber insn too to keep the correct life
7306 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
7308 rtx_insn
*prev_insn
= PREV_INSN (insn
);
7310 lra_set_insn_deleted (insn
);
7311 lra_assert (dregno
>= 0);
7312 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
7313 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
7314 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
7315 lra_set_insn_deleted (prev_insn
);
7318 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
7319 return true if we did any change. The undo transformations for
7320 inheritance looks like
7324 p <- i, i <- p, and i <- i3
7325 where p is original pseudo from which inheritance pseudo i was
7326 created, i and i3 are removed inheritance pseudos, i2 is another
7327 not removed inheritance pseudo. All split pseudos or other
7328 occurrences of removed inheritance pseudos are changed on the
7329 corresponding original pseudos.
7331 The function also schedules insns changed and created during
7332 inheritance/split pass for processing by the subsequent constraint
7335 remove_inheritance_pseudos (bitmap remove_pseudos
)
7338 int regno
, sregno
, prev_sregno
, dregno
;
7341 rtx_insn
*prev_insn
;
7342 bool change_p
, done_p
;
7344 change_p
= ! bitmap_empty_p (remove_pseudos
);
7345 /* We cannot finish the function right away if CHANGE_P is true
7346 because we need to marks insns affected by previous
7347 inheritance/split pass for processing by the subsequent
7349 FOR_EACH_BB_FN (bb
, cfun
)
7351 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
7352 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
7353 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
7355 if (! INSN_P (curr_insn
))
7358 sregno
= dregno
= -1;
7359 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
7360 && (set
= single_set (curr_insn
)) != NULL_RTX
)
7362 dregno
= get_regno (SET_DEST (set
));
7363 sregno
= get_regno (SET_SRC (set
));
7366 if (sregno
>= 0 && dregno
>= 0)
7368 if (bitmap_bit_p (remove_pseudos
, dregno
)
7369 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
7371 /* invariant inheritance pseudo <- original pseudo */
7372 if (lra_dump_file
!= NULL
)
7374 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
7375 dump_insn_slim (lra_dump_file
, curr_insn
);
7376 fprintf (lra_dump_file
, "\n");
7378 delete_move_and_clobber (curr_insn
, dregno
);
7381 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7382 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
7384 /* reload pseudo <- invariant inheritance pseudo */
7386 /* We cannot just change the source. It might be
7387 an insn different from the move. */
7388 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
7389 rtx_insn
*new_insns
= get_insns ();
7391 lra_assert (single_set (new_insns
) != NULL
7392 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
7393 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
7394 "Changing reload<-invariant inheritance");
7395 delete_move_and_clobber (curr_insn
, dregno
);
7398 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
7399 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
7400 || (bitmap_bit_p (remove_pseudos
, dregno
)
7401 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7402 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7403 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
7404 || (bitmap_bit_p (remove_pseudos
, dregno
)
7405 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
7406 /* One of the following cases:
7407 original <- removed inheritance pseudo
7408 removed inherit pseudo <- another removed inherit pseudo
7409 removed inherit pseudo <- original pseudo
7411 removed_split_pseudo <- original_reg
7412 original_reg <- removed_split_pseudo */
7414 if (lra_dump_file
!= NULL
)
7416 fprintf (lra_dump_file
, " Removing %s:\n",
7417 bitmap_bit_p (&lra_split_regs
, sregno
)
7418 || bitmap_bit_p (&lra_split_regs
, dregno
)
7419 ? "split" : "inheritance");
7420 dump_insn_slim (lra_dump_file
, curr_insn
);
7422 delete_move_and_clobber (curr_insn
, dregno
);
7425 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7426 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
7428 /* Search the following pattern:
7429 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
7430 original_pseudo <- inherit_or_split_pseudo1
7431 where the 2nd insn is the current insn and
7432 inherit_or_split_pseudo2 is not removed. If it is found,
7433 change the current insn onto:
7434 original_pseudo <- inherit_or_split_pseudo2. */
7435 for (prev_insn
= PREV_INSN (curr_insn
);
7436 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
7437 prev_insn
= PREV_INSN (prev_insn
))
7439 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
7440 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
7441 /* There should be no subregs in insn we are
7442 searching because only the original reg might
7443 be in subreg when we changed the mode of
7444 load/store for splitting. */
7445 && REG_P (SET_DEST (prev_set
))
7446 && REG_P (SET_SRC (prev_set
))
7447 && (int) REGNO (SET_DEST (prev_set
)) == sregno
7448 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
7449 >= FIRST_PSEUDO_REGISTER
)
7450 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
7452 /* As we consider chain of inheritance or
7453 splitting described in above comment we should
7454 check that sregno and prev_sregno were
7455 inheritance/split pseudos created from the
7456 same original regno. */
7457 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7458 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7459 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
7460 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
7462 lra_assert (GET_MODE (SET_SRC (prev_set
))
7463 == GET_MODE (regno_reg_rtx
[sregno
]));
7464 /* Although we have a single set, the insn can
7465 contain more one sregno register occurrence
7466 as a source. Change all occurrences. */
7467 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
7470 /* As we are finishing with processing the insn
7471 here, check the destination too as it might
7472 inheritance pseudo for another pseudo. */
7473 if (bitmap_bit_p (remove_pseudos
, dregno
)
7474 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7476 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7478 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7479 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7481 SET_DEST (set
) = restore_rtx
;
7483 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7484 lra_set_used_insn_alternative_by_uid
7485 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7487 if (lra_dump_file
!= NULL
)
7489 fprintf (lra_dump_file
, " Change reload insn:\n");
7490 dump_insn_slim (lra_dump_file
, curr_insn
);
7497 struct lra_insn_reg
*reg
;
7498 bool restored_regs_p
= false;
7499 bool kept_regs_p
= false;
7501 curr_id
= lra_get_insn_recog_data (curr_insn
);
7502 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7505 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7506 if (restore_rtx
!= NULL_RTX
)
7508 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7510 lra_substitute_pseudo_within_insn
7511 (curr_insn
, regno
, restore_rtx
, false);
7512 restored_regs_p
= true;
7518 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7520 /* The instruction has changed since the previous
7521 constraints pass. */
7522 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7523 lra_set_used_insn_alternative_by_uid
7524 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7526 else if (restored_regs_p
)
7527 /* The instruction has been restored to the form that
7528 it had during the previous constraints pass. */
7529 lra_update_insn_regno_info (curr_insn
);
7530 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7532 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7533 dump_insn_slim (lra_dump_file
, curr_insn
);
7541 /* If optional reload pseudos failed to get a hard register or was not
7542 inherited, it is better to remove optional reloads. We do this
7543 transformation after undoing inheritance to figure out necessity to
7544 remove optional reloads easier. Return true if we do any
7547 undo_optional_reloads (void)
7549 bool change_p
, keep_p
;
7550 unsigned int regno
, uid
;
7551 bitmap_iterator bi
, bi2
;
7554 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7556 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7557 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7560 /* Keep optional reloads from previous subpasses. */
7561 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7562 /* If the original pseudo changed its allocation, just
7563 removing the optional pseudo is dangerous as the original
7564 pseudo will have longer live range. */
7565 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7567 else if (reg_renumber
[regno
] >= 0)
7568 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7570 insn
= lra_insn_recog_data
[uid
]->insn
;
7571 if ((set
= single_set (insn
)) == NULL_RTX
)
7573 src
= SET_SRC (set
);
7574 dest
= SET_DEST (set
);
7575 if ((! REG_P (src
) && ! SUBREG_P (src
))
7576 || (! REG_P (dest
) && ! SUBREG_P (dest
)))
7578 if (get_regno (dest
) == (int) regno
7579 /* Ignore insn for optional reloads itself. */
7580 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7582 /* Check only inheritance on last inheritance pass. */
7583 && get_regno (src
) >= new_regno_start
7584 /* Check that the optional reload was inherited. */
7585 && bitmap_bit_p (&lra_inheritance_pseudos
, get_regno (src
)))
7593 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7594 if (lra_dump_file
!= NULL
)
7595 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7598 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7599 auto_bitmap
insn_bitmap (®_obstack
);
7600 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7602 if (lra_dump_file
!= NULL
)
7603 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7604 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7605 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7607 /* We may have already removed a clobber. */
7608 if (!lra_insn_recog_data
[uid
])
7610 insn
= lra_insn_recog_data
[uid
]->insn
;
7611 if ((set
= single_set (insn
)) != NULL_RTX
)
7613 src
= SET_SRC (set
);
7614 dest
= SET_DEST (set
);
7615 if ((REG_P (src
) || SUBREG_P (src
))
7616 && (REG_P (dest
) || SUBREG_P (dest
))
7617 && ((get_regno (src
) == (int) regno
7618 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7619 == get_regno (dest
)))
7620 || (get_regno (dest
) == (int) regno
7621 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7622 == get_regno (src
)))))
7624 if (lra_dump_file
!= NULL
)
7626 fprintf (lra_dump_file
, " Deleting move %u\n",
7628 dump_insn_slim (lra_dump_file
, insn
);
7630 delete_move_and_clobber (insn
, get_regno (dest
));
7633 /* We should not worry about generation memory-memory
7634 moves here as if the corresponding inheritance did
7635 not work (inheritance pseudo did not get a hard reg),
7636 we remove the inheritance pseudo and the optional
7639 if (GET_CODE (PATTERN (insn
)) == CLOBBER
7640 && REG_P (SET_DEST (insn
))
7641 && get_regno (SET_DEST (insn
)) == (int) regno
)
7642 /* Refuse to remap clobbers to preexisting pseudos. */
7644 lra_substitute_pseudo_within_insn
7645 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7646 lra_update_insn_regno_info (insn
);
7647 if (lra_dump_file
!= NULL
)
7649 fprintf (lra_dump_file
,
7650 " Restoring original insn:\n");
7651 dump_insn_slim (lra_dump_file
, insn
);
7655 /* Clear restore_regnos. */
7656 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7657 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7661 /* Entry function for undoing inheritance/split transformation. Return true
7662 if we did any RTL change in this pass. */
7664 lra_undo_inheritance (void)
7668 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7673 lra_undo_inheritance_iter
++;
7674 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7676 if (lra_dump_file
!= NULL
)
7677 fprintf (lra_dump_file
,
7678 "\n********** Undoing inheritance #%d: **********\n\n",
7679 lra_undo_inheritance_iter
);
7680 auto_bitmap
remove_pseudos (®_obstack
);
7681 n_inherit
= n_all_inherit
= 0;
7682 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7683 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7686 if (reg_renumber
[regno
] < 0
7687 /* If the original pseudo changed its allocation, just
7688 removing inheritance is dangerous as for changing
7689 allocation we used shorter live-ranges. */
7690 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7691 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7692 bitmap_set_bit (remove_pseudos
, regno
);
7696 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7697 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7698 n_inherit
, n_all_inherit
,
7699 (double) n_inherit
/ n_all_inherit
* 100);
7700 n_split
= n_all_split
= 0;
7701 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7702 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7704 int restore_regno
= REGNO (restore_rtx
);
7707 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7708 ? reg_renumber
[restore_regno
] : restore_regno
);
7709 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7710 bitmap_set_bit (remove_pseudos
, regno
);
7714 if (lra_dump_file
!= NULL
)
7715 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7716 regno
, restore_regno
);
7719 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7720 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7721 n_split
, n_all_split
,
7722 (double) n_split
/ n_all_split
* 100);
7723 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7724 /* Clear restore_regnos. */
7725 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7726 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7727 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7728 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7729 change_p
= undo_optional_reloads () || change_p
;