gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 143    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 144
 145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 146   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 147
 148 /* Maximum register number, which is the size of the tables below.  */
 149
 150 static unsigned int combine_max_regno;
 151
 152 struct reg_stat {
 153   /* Record last point of death of (hard or pseudo) register n.  */
 154   rtx                           last_death;
 155
 156   /* Record last point of modification of (hard or pseudo) register n.  */
 157   rtx                           last_set;
 158
 159   /* The next group of fields allows the recording of the last value assigned
 160      to (hard or pseudo) register n.  We use this information to see if an
 161      operation being processed is redundant given a prior operation performed
 162      on the register.  For example, an `and' with a constant is redundant if
 163      all the zero bits are already known to be turned off.
 164
 165      We use an approach similar to that used by cse, but change it in the
 166      following ways:
 167
 168      (1) We do not want to reinitialize at each label.
 169      (2) It is useful, but not critical, to know the actual value assigned
 170          to a register.  Often just its form is helpful.
 171
 172      Therefore, we maintain the following fields:
 173
 174      last_set_value             the last value assigned
 175      last_set_label             records the value of label_tick when the
 176                                 register was assigned
 177      last_set_table_tick        records the value of label_tick when a
 178                                 value using the register is assigned
 179      last_set_invalid           set to nonzero when it is not valid
 180                                 to use the value of this register in some
 181                                 register's value
 182
 183      To understand the usage of these tables, it is important to understand
 184      the distinction between the value in last_set_value being valid and
 185      the register being validly contained in some other expression in the
 186      table.
 187
 188      (The next two parameters are out of date).
 189
 190      reg_stat[i].last_set_value is valid if it is nonzero, and either
 191      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 192
 193      Register I may validly appear in any expression returned for the value
 194      of another register if reg_n_sets[i] is 1.  It may also appear in the
 195      value for register J if reg_stat[j].last_set_invalid is zero, or
 196      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 197
 198      If an expression is found in the table containing a register which may
 199      not validly appear in an expression, the register is replaced by
 200      something that won't match, (clobber (const_int 0)).  */
 201
 202   /* Record last value assigned to (hard or pseudo) register n.  */
 203
 204   rtx                           last_set_value;
 205
 206   /* Record the value of label_tick when an expression involving register n
 207      is placed in last_set_value.  */
 208
 209   int                           last_set_table_tick;
 210
 211   /* Record the value of label_tick when the value for register n is placed in
 212      last_set_value.  */
 213
 214   int                           last_set_label;
 215
 216   /* These fields are maintained in parallel with last_set_value and are
 217      used to store the mode in which the register was last set, the bits
 218      that were known to be zero when it was last set, and the number of
 219      sign bits copies it was known to have when it was last set.  */
 220
 221   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 222   char                          last_set_sign_bit_copies;
 223   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 224
 225   /* Set nonzero if references to register n in expressions should not be
 226      used.  last_set_invalid is set nonzero when this register is being
 227      assigned to and last_set_table_tick == label_tick.  */
 228
 229   char                          last_set_invalid;
 230
 231   /* Some registers that are set more than once and used in more than one
 232      basic block are nevertheless always set in similar ways.  For example,
 233      a QImode register may be loaded from memory in two places on a machine
 234      where byte loads zero extend.
 235
 236      We record in the following fields if a register has some leading bits
 237      that are always equal to the sign bit, and what we know about the
 238      nonzero bits of a register, specifically which bits are known to be
 239      zero.
 240
 241      If an entry is zero, it means that we don't know anything special.  */
 242
 243   unsigned char                 sign_bit_copies;
 244
 245   unsigned HOST_WIDE_INT        nonzero_bits;
 246
 247   /* Record the value of the label_tick when the last truncation
 248      happened.  The field truncated_to_mode is only valid if
 249      truncation_label == label_tick.  */
 250
 251   int                           truncation_label;
 252
 253   /* Record the last truncation seen for this register.  If truncation
 254      is not a nop to this mode we might be able to save an explicit
 255      truncation if we know that value already contains a truncated
 256      value.  */
 257
 258   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 259 };
 260
 261 static struct reg_stat *reg_stat;
 262
 263 /* Record the cuid of the last insn that invalidated memory
 264    (anything that writes memory, and subroutine calls, but not pushes).  */
 265
 266 static int mem_last_set;
 267
 268 /* Record the cuid of the last CALL_INSN
 269    so we can tell whether a potential combination crosses any calls.  */
 270
 271 static int last_call_cuid;
 272
 273 /* When `subst' is called, this is the insn that is being modified
 274    (by combining in a previous insn).  The PATTERN of this insn
 275    is still the old pattern partially modified and it should not be
 276    looked at, but this may be used to examine the successors of the insn
 277    to judge whether a simplification is valid.  */
 278
 279 static rtx subst_insn;
 280
 281 /* This is the lowest CUID that `subst' is currently dealing with.
 282    get_last_value will not return a value if the register was set at or
 283    after this CUID.  If not for this mechanism, we could get confused if
 284    I2 or I1 in try_combine were an insn that used the old value of a register
 285    to obtain a new value.  In that case, we might erroneously get the
 286    new value of the register when we wanted the old one.  */
 287
 288 static int subst_low_cuid;
 289
 290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 291    must consider all these registers to be always live.  */
 292
 293 static HARD_REG_SET newpat_used_regs;
 294
 295 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 296    insn is the earlier than I2 or I3, combine should rescan starting at
 297    that location.  */
 298
 299 static rtx added_links_insn;
 300
 301 /* Basic block in which we are performing combines.  */
 302 static basic_block this_basic_block;
 303
 304 /* A bitmap indicating which blocks had registers go dead at entry.
 305    After combine, we'll need to re-do global life analysis with
 306    those blocks as starting points.  */
 307 static sbitmap refresh_blocks;
 308 \f
 309 /* The following array records the insn_rtx_cost for every insn
 310    in the instruction stream.  */
 311
 312 static int *uid_insn_cost;
 313
 314 /* Length of the currently allocated uid_insn_cost array.  */
 315
 316 static int last_insn_cost;
 317
 318 /* Incremented for each label.  */
 319
 320 static int label_tick;
 321
 322 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 323    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 324
 325 static enum machine_mode nonzero_bits_mode;
 326
 327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 328    be safely used.  It is zero while computing them and after combine has
 329    completed.  This former test prevents propagating values based on
 330    previously set values, which can be incorrect if a variable is modified
 331    in a loop.  */
 332
 333 static int nonzero_sign_valid;
 334
 335 \f
 336 /* Record one modification to rtl structure
 337    to be undone by storing old_contents into *where.  */
 338
 339 struct undo
 340 {
 341   struct undo *next;
 342   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 343   union { rtx r; int i; enum machine_mode m; } old_contents;
 344   union { rtx *r; int *i; } where;
 345 };
 346
 347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 348    num_undo says how many are currently recorded.
 349
 350    other_insn is nonzero if we have modified some other insn in the process
 351    of working on subst_insn.  It must be verified too.  */
 352
 353 struct undobuf
 354 {
 355   struct undo *undos;
 356   struct undo *frees;
 357   rtx other_insn;
 358 };
 359
 360 static struct undobuf undobuf;
 361
 362 /* Number of times the pseudo being substituted for
 363    was found and replaced.  */
 364
 365 static int n_occurrences;
 366
 367 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 368                                          enum machine_mode,
 369                                          unsigned HOST_WIDE_INT,
 370                                          unsigned HOST_WIDE_INT *);
 371 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 372                                                 enum machine_mode,
 373                                                 unsigned int, unsigned int *);
 374 static void do_SUBST (rtx *, rtx);
 375 static void do_SUBST_INT (int *, int);
 376 static void init_reg_last (void);
 377 static void setup_incoming_promotions (void);
 378 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 379 static int cant_combine_insn_p (rtx);
 380 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 381 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 382 static int contains_muldiv (rtx);
 383 static rtx try_combine (rtx, rtx, rtx, int *);
 384 static void undo_all (void);
 385 static void undo_commit (void);
 386 static rtx *find_split_point (rtx *, rtx);
 387 static rtx subst (rtx, rtx, rtx, int, int);
 388 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 389 static rtx simplify_if_then_else (rtx);
 390 static rtx simplify_set (rtx);
 391 static rtx simplify_logical (rtx);
 392 static rtx expand_compound_operation (rtx);
 393 static rtx expand_field_assignment (rtx);
 394 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 395                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 396 static rtx extract_left_shift (rtx, int);
 397 static rtx make_compound_operation (rtx, enum rtx_code);
 398 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 399                               unsigned HOST_WIDE_INT *);
 400 static rtx canon_reg_for_combine (rtx, rtx);
 401 static rtx force_to_mode (rtx, enum machine_mode,
 402                           unsigned HOST_WIDE_INT, int);
 403 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 404 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 405 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 406 static rtx make_field_assignment (rtx);
 407 static rtx apply_distributive_law (rtx);
 408 static rtx distribute_and_simplify_rtx (rtx, int);
 409 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 410                                      unsigned HOST_WIDE_INT);
 411 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 412                                    unsigned HOST_WIDE_INT);
 413 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 414                             HOST_WIDE_INT, enum machine_mode, int *);
 415 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 417                                  int);
 418 static int recog_for_combine (rtx *, rtx, rtx *);
 419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 421 static void update_table_tick (rtx);
 422 static void record_value_for_reg (rtx, rtx, rtx);
 423 static void check_conversions (rtx, rtx);
 424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 425 static void record_dead_and_set_regs (rtx);
 426 static int get_last_value_validate (rtx *, rtx, int, int);
 427 static rtx get_last_value (rtx);
 428 static int use_crosses_set_p (rtx, int);
 429 static void reg_dead_at_p_1 (rtx, rtx, void *);
 430 static int reg_dead_at_p (rtx, rtx);
 431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 432 static int reg_bitfield_target_p (rtx, rtx);
 433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 434 static void distribute_links (rtx);
 435 static void mark_used_regs_combine (rtx);
 436 static int insn_cuid (rtx);
 437 static void record_promoted_value (rtx, rtx);
 438 static int unmentioned_reg_p_1 (rtx *, void *);
 439 static bool unmentioned_reg_p (rtx, rtx);
 440 static void record_truncated_value (rtx);
 441 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 442 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 443 \f
 444
 445 /* It is not safe to use ordinary gen_lowpart in combine.
 446    See comments in gen_lowpart_for_combine.  */
 447 #undef RTL_HOOKS_GEN_LOWPART
 448 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 449
 450 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 453
 454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 455 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 456
 457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 459
 460 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 461
 462 \f
 463 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 464    insn.  The substitution can be undone by undo_all.  If INTO is already
 465    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 466    also call SUBST, we have to compute it before we put anything into
 467    the undo table.  */
 468
 469 static void
 470 do_SUBST (rtx *into, rtx newval)
 471 {
 472   struct undo *buf;
 473   rtx oldval = *into;
 474
 475   if (oldval == newval)
 476     return;
 477
 478   /* We'd like to catch as many invalid transformations here as
 479      possible.  Unfortunately, there are way too many mode changes
 480      that are perfectly valid, so we'd waste too much effort for
 481      little gain doing the checks here.  Focus on catching invalid
 482      transformations involving integer constants.  */
 483   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 484       && GET_CODE (newval) == CONST_INT)
 485     {
 486       /* Sanity check that we're replacing oldval with a CONST_INT
 487          that is a valid sign-extension for the original mode.  */
 488       gcc_assert (INTVAL (newval)
 489                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 490
 491       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 492          CONST_INT is not valid, because after the replacement, the
 493          original mode would be gone.  Unfortunately, we can't tell
 494          when do_SUBST is called to replace the operand thereof, so we
 495          perform this test on oldval instead, checking whether an
 496          invalid replacement took place before we got here.  */
 497       gcc_assert (!(GET_CODE (oldval) == SUBREG
 498                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 499       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 500                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 501     }
 502
 503   if (undobuf.frees)
 504     buf = undobuf.frees, undobuf.frees = buf->next;
 505   else
 506     buf = xmalloc (sizeof (struct undo));
 507
 508   buf->kind = UNDO_RTX;
 509   buf->where.r = into;
 510   buf->old_contents.r = oldval;
 511   *into = newval;
 512
 513   buf->next = undobuf.undos, undobuf.undos = buf;
 514 }
 515
 516 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 517
 518 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 519    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 520    not safe.  */
 521
 522 static void
 523 do_SUBST_INT (int *into, int newval)
 524 {
 525   struct undo *buf;
 526   int oldval = *into;
 527
 528   if (oldval == newval)
 529     return;
 530
 531   if (undobuf.frees)
 532     buf = undobuf.frees, undobuf.frees = buf->next;
 533   else
 534     buf = xmalloc (sizeof (struct undo));
 535
 536   buf->kind = UNDO_INT;
 537   buf->where.i = into;
 538   buf->old_contents.i = oldval;
 539   *into = newval;
 540
 541   buf->next = undobuf.undos, undobuf.undos = buf;
 542 }
 543
 544 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 545
 546 /* Similar to SUBST, but just substitute the mode.  This is used when
 547    changing the mode of a pseudo-register, so that any other
 548    references to the entry in the regno_reg_rtx array will change as
 549    well.  */
 550
 551 static void
 552 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 553 {
 554   struct undo *buf;
 555   enum machine_mode oldval = GET_MODE (*into);
 556
 557   if (oldval == newval)
 558     return;
 559
 560   if (undobuf.frees)
 561     buf = undobuf.frees, undobuf.frees = buf->next;
 562   else
 563     buf = xmalloc (sizeof (struct undo));
 564
 565   buf->kind = UNDO_MODE;
 566   buf->where.r = into;
 567   buf->old_contents.m = oldval;
 568   PUT_MODE (*into, newval);
 569
 570   buf->next = undobuf.undos, undobuf.undos = buf;
 571 }
 572
 573 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 574 \f
 575 /* Subroutine of try_combine.  Determine whether the combine replacement
 576    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 577    that the original instruction sequence I1, I2 and I3.  Note that I1
 578    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 579    costs of all instructions can be estimated, and the replacements are
 580    more expensive than the original sequence.  */
 581
 582 static bool
 583 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 584 {
 585   int i1_cost, i2_cost, i3_cost;
 586   int new_i2_cost, new_i3_cost;
 587   int old_cost, new_cost;
 588
 589   /* Lookup the original insn_rtx_costs.  */
 590   i2_cost = INSN_UID (i2) <= last_insn_cost
 591             ? uid_insn_cost[INSN_UID (i2)] : 0;
 592   i3_cost = INSN_UID (i3) <= last_insn_cost
 593             ? uid_insn_cost[INSN_UID (i3)] : 0;
 594
 595   if (i1)
 596     {
 597       i1_cost = INSN_UID (i1) <= last_insn_cost
 598                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 599       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 600                  ? i1_cost + i2_cost + i3_cost : 0;
 601     }
 602   else
 603     {
 604       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 605       i1_cost = 0;
 606     }
 607
 608   /* Calculate the replacement insn_rtx_costs.  */
 609   new_i3_cost = insn_rtx_cost (newpat);
 610   if (newi2pat)
 611     {
 612       new_i2_cost = insn_rtx_cost (newi2pat);
 613       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 614                  ? new_i2_cost + new_i3_cost : 0;
 615     }
 616   else
 617     {
 618       new_cost = new_i3_cost;
 619       new_i2_cost = 0;
 620     }
 621
 622   if (undobuf.other_insn)
 623     {
 624       int old_other_cost, new_other_cost;
 625
 626       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 627                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 628       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 629       if (old_other_cost > 0 && new_other_cost > 0)
 630         {
 631           old_cost += old_other_cost;
 632           new_cost += new_other_cost;
 633         }
 634       else
 635         old_cost = 0;
 636     }
 637
 638   /* Disallow this recombination if both new_cost and old_cost are
 639      greater than zero, and new_cost is greater than old cost.  */
 640   if (old_cost > 0
 641       && new_cost > old_cost)
 642     {
 643       if (dump_file)
 644         {
 645           if (i1)
 646             {
 647               fprintf (dump_file,
 648                        "rejecting combination of insns %d, %d and %d\n",
 649                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 650               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 651                        i1_cost, i2_cost, i3_cost, old_cost);
 652             }
 653           else
 654             {
 655               fprintf (dump_file,
 656                        "rejecting combination of insns %d and %d\n",
 657                        INSN_UID (i2), INSN_UID (i3));
 658               fprintf (dump_file, "original costs %d + %d = %d\n",
 659                        i2_cost, i3_cost, old_cost);
 660             }
 661
 662           if (newi2pat)
 663             {
 664               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 665                        new_i2_cost, new_i3_cost, new_cost);
 666             }
 667           else
 668             fprintf (dump_file, "replacement cost %d\n", new_cost);
 669         }
 670
 671       return false;
 672     }
 673
 674   /* Update the uid_insn_cost array with the replacement costs.  */
 675   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 676   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 677   if (i1)
 678     uid_insn_cost[INSN_UID (i1)] = 0;
 679
 680   return true;
 681 }
 682 \f
 683 /* Main entry point for combiner.  F is the first insn of the function.
 684    NREGS is the first unused pseudo-reg number.
 685
 686    Return nonzero if the combiner has turned an indirect jump
 687    instruction into a direct jump.  */
 688 int
 689 combine_instructions (rtx f, unsigned int nregs)
 690 {
 691   rtx insn, next;
 692 #ifdef HAVE_cc0
 693   rtx prev;
 694 #endif
 695   int i;
 696   unsigned int j = 0;
 697   rtx links, nextlinks;
 698   sbitmap_iterator sbi;
 699
 700   int new_direct_jump_p = 0;
 701
 702   combine_attempts = 0;
 703   combine_merges = 0;
 704   combine_extras = 0;
 705   combine_successes = 0;
 706
 707   combine_max_regno = nregs;
 708
 709   rtl_hooks = combine_rtl_hooks;
 710
 711   reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
 712
 713   init_recog_no_volatile ();
 714
 715   /* Compute maximum uid value so uid_cuid can be allocated.  */
 716
 717   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 718     if (INSN_UID (insn) > i)
 719       i = INSN_UID (insn);
 720
 721   uid_cuid = xmalloc ((i + 1) * sizeof (int));
 722   max_uid_cuid = i;
 723
 724   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 725
 726   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 727      problems when, for example, we have j <<= 1 in a loop.  */
 728
 729   nonzero_sign_valid = 0;
 730
 731   /* Compute the mapping from uids to cuids.
 732      Cuids are numbers assigned to insns, like uids,
 733      except that cuids increase monotonically through the code.
 734
 735      Scan all SETs and see if we can deduce anything about what
 736      bits are known to be zero for some registers and how many copies
 737      of the sign bit are known to exist for those registers.
 738
 739      Also set any known values so that we can use it while searching
 740      for what bits are known to be set.  */
 741
 742   label_tick = 1;
 743
 744   setup_incoming_promotions ();
 745
 746   refresh_blocks = sbitmap_alloc (last_basic_block);
 747   sbitmap_zero (refresh_blocks);
 748
 749   /* Allocate array of current insn_rtx_costs.  */
 750   uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
 751   last_insn_cost = max_uid_cuid;
 752
 753   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 754     {
 755       uid_cuid[INSN_UID (insn)] = ++i;
 756       subst_low_cuid = i;
 757       subst_insn = insn;
 758
 759       if (INSN_P (insn))
 760         {
 761           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 762                        NULL);
 763           record_dead_and_set_regs (insn);
 764
 765 #ifdef AUTO_INC_DEC
 766           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 767             if (REG_NOTE_KIND (links) == REG_INC)
 768               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 769                                                 NULL);
 770 #endif
 771
 772           /* Record the current insn_rtx_cost of this instruction.  */
 773           if (NONJUMP_INSN_P (insn))
 774             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 775           if (dump_file)
 776             fprintf(dump_file, "insn_cost %d: %d\n",
 777                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 778         }
 779
 780       if (LABEL_P (insn))
 781         label_tick++;
 782     }
 783
 784   nonzero_sign_valid = 1;
 785
 786   /* Now scan all the insns in forward order.  */
 787
 788   label_tick = 1;
 789   last_call_cuid = 0;
 790   mem_last_set = 0;
 791   init_reg_last ();
 792   setup_incoming_promotions ();
 793
 794   FOR_EACH_BB (this_basic_block)
 795     {
 796       for (insn = BB_HEAD (this_basic_block);
 797            insn != NEXT_INSN (BB_END (this_basic_block));
 798            insn = next ? next : NEXT_INSN (insn))
 799         {
 800           next = 0;
 801
 802           if (LABEL_P (insn))
 803             label_tick++;
 804
 805           else if (INSN_P (insn))
 806             {
 807               /* See if we know about function return values before this
 808                  insn based upon SUBREG flags.  */
 809               check_conversions (insn, PATTERN (insn));
 810
 811               /* Try this insn with each insn it links back to.  */
 812
 813               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 814                 if ((next = try_combine (insn, XEXP (links, 0),
 815                                          NULL_RTX, &new_direct_jump_p)) != 0)
 816                   goto retry;
 817
 818               /* Try each sequence of three linked insns ending with this one.  */
 819
 820               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 821                 {
 822                   rtx link = XEXP (links, 0);
 823
 824                   /* If the linked insn has been replaced by a note, then there
 825                      is no point in pursuing this chain any further.  */
 826                   if (NOTE_P (link))
 827                     continue;
 828
 829                   for (nextlinks = LOG_LINKS (link);
 830                        nextlinks;
 831                        nextlinks = XEXP (nextlinks, 1))
 832                     if ((next = try_combine (insn, link,
 833                                              XEXP (nextlinks, 0),
 834                                              &new_direct_jump_p)) != 0)
 835                       goto retry;
 836                 }
 837
 838 #ifdef HAVE_cc0
 839               /* Try to combine a jump insn that uses CC0
 840                  with a preceding insn that sets CC0, and maybe with its
 841                  logical predecessor as well.
 842                  This is how we make decrement-and-branch insns.
 843                  We need this special code because data flow connections
 844                  via CC0 do not get entered in LOG_LINKS.  */
 845
 846               if (JUMP_P (insn)
 847                   && (prev = prev_nonnote_insn (insn)) != 0
 848                   && NONJUMP_INSN_P (prev)
 849                   && sets_cc0_p (PATTERN (prev)))
 850                 {
 851                   if ((next = try_combine (insn, prev,
 852                                            NULL_RTX, &new_direct_jump_p)) != 0)
 853                     goto retry;
 854
 855                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 856                        nextlinks = XEXP (nextlinks, 1))
 857                     if ((next = try_combine (insn, prev,
 858                                              XEXP (nextlinks, 0),
 859                                              &new_direct_jump_p)) != 0)
 860                       goto retry;
 861                 }
 862
 863               /* Do the same for an insn that explicitly references CC0.  */
 864               if (NONJUMP_INSN_P (insn)
 865                   && (prev = prev_nonnote_insn (insn)) != 0
 866                   && NONJUMP_INSN_P (prev)
 867                   && sets_cc0_p (PATTERN (prev))
 868                   && GET_CODE (PATTERN (insn)) == SET
 869                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 870                 {
 871                   if ((next = try_combine (insn, prev,
 872                                            NULL_RTX, &new_direct_jump_p)) != 0)
 873                     goto retry;
 874
 875                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 876                        nextlinks = XEXP (nextlinks, 1))
 877                     if ((next = try_combine (insn, prev,
 878                                              XEXP (nextlinks, 0),
 879                                              &new_direct_jump_p)) != 0)
 880                       goto retry;
 881                 }
 882
 883               /* Finally, see if any of the insns that this insn links to
 884                  explicitly references CC0.  If so, try this insn, that insn,
 885                  and its predecessor if it sets CC0.  */
 886               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 887                 if (NONJUMP_INSN_P (XEXP (links, 0))
 888                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 889                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 890                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 891                     && NONJUMP_INSN_P (prev)
 892                     && sets_cc0_p (PATTERN (prev))
 893                     && (next = try_combine (insn, XEXP (links, 0),
 894                                             prev, &new_direct_jump_p)) != 0)
 895                   goto retry;
 896 #endif
 897
 898               /* Try combining an insn with two different insns whose results it
 899                  uses.  */
 900               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 901                 for (nextlinks = XEXP (links, 1); nextlinks;
 902                      nextlinks = XEXP (nextlinks, 1))
 903                   if ((next = try_combine (insn, XEXP (links, 0),
 904                                            XEXP (nextlinks, 0),
 905                                            &new_direct_jump_p)) != 0)
 906                     goto retry;
 907
 908               /* Try this insn with each REG_EQUAL note it links back to.  */
 909               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 910                 {
 911                   rtx set, note;
 912                   rtx temp = XEXP (links, 0);
 913                   if ((set = single_set (temp)) != 0
 914                       && (note = find_reg_equal_equiv_note (temp)) != 0
 915                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 916                       /* Avoid using a register that may already been marked
 917                          dead by an earlier instruction.  */
 918                       && ! unmentioned_reg_p (note, SET_SRC (set))
 919                       && (GET_MODE (note) == VOIDmode
 920                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 921                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 922                     {
 923                       /* Temporarily replace the set's source with the
 924                          contents of the REG_EQUAL note.  The insn will
 925                          be deleted or recognized by try_combine.  */
 926                       rtx orig = SET_SRC (set);
 927                       SET_SRC (set) = note;
 928                       next = try_combine (insn, temp, NULL_RTX,
 929                                           &new_direct_jump_p);
 930                       if (next)
 931                         goto retry;
 932                       SET_SRC (set) = orig;
 933                     }
 934                 }
 935
 936               if (!NOTE_P (insn))
 937                 record_dead_and_set_regs (insn);
 938
 939             retry:
 940               ;
 941             }
 942         }
 943     }
 944   clear_bb_flags ();
 945
 946   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 947     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 948   new_direct_jump_p |= purge_all_dead_edges ();
 949   delete_noop_moves ();
 950
 951   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 952                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 953                                     | PROP_KILL_DEAD_CODE);
 954
 955   /* Clean up.  */
 956   sbitmap_free (refresh_blocks);
 957   free (uid_insn_cost);
 958   free (reg_stat);
 959   free (uid_cuid);
 960
 961   {
 962     struct undo *undo, *next;
 963     for (undo = undobuf.frees; undo; undo = next)
 964       {
 965         next = undo->next;
 966         free (undo);
 967       }
 968     undobuf.frees = 0;
 969   }
 970
 971   total_attempts += combine_attempts;
 972   total_merges += combine_merges;
 973   total_extras += combine_extras;
 974   total_successes += combine_successes;
 975
 976   nonzero_sign_valid = 0;
 977   rtl_hooks = general_rtl_hooks;
 978
 979   /* Make recognizer allow volatile MEMs again.  */
 980   init_recog ();
 981
 982   return new_direct_jump_p;
 983 }
 984
 985 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 986
 987 static void
 988 init_reg_last (void)
 989 {
 990   unsigned int i;
 991   for (i = 0; i < combine_max_regno; i++)
 992     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 993 }
 994 \f
 995 /* Set up any promoted values for incoming argument registers.  */
 996
 997 static void
 998 setup_incoming_promotions (void)
 999 {
1000   unsigned int regno;
1001   rtx reg;
1002   enum machine_mode mode;
1003   int unsignedp;
1004   rtx first = get_insns ();
1005
1006   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1007     {
1008       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1009         /* Check whether this register can hold an incoming pointer
1010            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1011            numbers, so translate if necessary due to register windows.  */
1012         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1013             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1014           {
1015             record_value_for_reg
1016               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1017                                            : SIGN_EXTEND),
1018                                           GET_MODE (reg),
1019                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1020           }
1021     }
1022 }
1023 \f
1024 /* Called via note_stores.  If X is a pseudo that is narrower than
1025    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1026
1027    If we are setting only a portion of X and we can't figure out what
1028    portion, assume all bits will be used since we don't know what will
1029    be happening.
1030
1031    Similarly, set how many bits of X are known to be copies of the sign bit
1032    at all locations in the function.  This is the smallest number implied
1033    by any set of X.  */
1034
1035 static void
1036 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1037                                   void *data ATTRIBUTE_UNUSED)
1038 {
1039   unsigned int num;
1040
1041   if (REG_P (x)
1042       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1043       /* If this register is undefined at the start of the file, we can't
1044          say what its contents were.  */
1045       && ! REGNO_REG_SET_P
1046          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1047       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1048     {
1049       if (set == 0 || GET_CODE (set) == CLOBBER)
1050         {
1051           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1052           reg_stat[REGNO (x)].sign_bit_copies = 1;
1053           return;
1054         }
1055
1056       /* If this is a complex assignment, see if we can convert it into a
1057          simple assignment.  */
1058       set = expand_field_assignment (set);
1059
1060       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1061          set what we know about X.  */
1062
1063       if (SET_DEST (set) == x
1064           || (GET_CODE (SET_DEST (set)) == SUBREG
1065               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1066                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1067               && SUBREG_REG (SET_DEST (set)) == x))
1068         {
1069           rtx src = SET_SRC (set);
1070
1071 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1072           /* If X is narrower than a word and SRC is a non-negative
1073              constant that would appear negative in the mode of X,
1074              sign-extend it for use in reg_stat[].nonzero_bits because some
1075              machines (maybe most) will actually do the sign-extension
1076              and this is the conservative approach.
1077
1078              ??? For 2.5, try to tighten up the MD files in this regard
1079              instead of this kludge.  */
1080
1081           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1082               && GET_CODE (src) == CONST_INT
1083               && INTVAL (src) > 0
1084               && 0 != (INTVAL (src)
1085                        & ((HOST_WIDE_INT) 1
1086                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1087             src = GEN_INT (INTVAL (src)
1088                            | ((HOST_WIDE_INT) (-1)
1089                               << GET_MODE_BITSIZE (GET_MODE (x))));
1090 #endif
1091
1092           /* Don't call nonzero_bits if it cannot change anything.  */
1093           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1094             reg_stat[REGNO (x)].nonzero_bits
1095               |= nonzero_bits (src, nonzero_bits_mode);
1096           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1097           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1098               || reg_stat[REGNO (x)].sign_bit_copies > num)
1099             reg_stat[REGNO (x)].sign_bit_copies = num;
1100         }
1101       else
1102         {
1103           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1104           reg_stat[REGNO (x)].sign_bit_copies = 1;
1105         }
1106     }
1107 }
1108 \f
1109 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1110    insns that were previously combined into I3 or that will be combined
1111    into the merger of INSN and I3.
1112
1113    Return 0 if the combination is not allowed for any reason.
1114
1115    If the combination is allowed, *PDEST will be set to the single
1116    destination of INSN and *PSRC to the single source, and this function
1117    will return 1.  */
1118
1119 static int
1120 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1121                rtx *pdest, rtx *psrc)
1122 {
1123   int i;
1124   rtx set = 0, src, dest;
1125   rtx p;
1126 #ifdef AUTO_INC_DEC
1127   rtx link;
1128 #endif
1129   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1130                               && next_active_insn (succ) == i3)
1131                       : next_active_insn (insn) == i3);
1132
1133   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1134      or a PARALLEL consisting of such a SET and CLOBBERs.
1135
1136      If INSN has CLOBBER parallel parts, ignore them for our processing.
1137      By definition, these happen during the execution of the insn.  When it
1138      is merged with another insn, all bets are off.  If they are, in fact,
1139      needed and aren't also supplied in I3, they may be added by
1140      recog_for_combine.  Otherwise, it won't match.
1141
1142      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1143      note.
1144
1145      Get the source and destination of INSN.  If more than one, can't
1146      combine.  */
1147
1148   if (GET_CODE (PATTERN (insn)) == SET)
1149     set = PATTERN (insn);
1150   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1151            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1152     {
1153       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1154         {
1155           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1156           rtx note;
1157
1158           switch (GET_CODE (elt))
1159             {
1160             /* This is important to combine floating point insns
1161                for the SH4 port.  */
1162             case USE:
1163               /* Combining an isolated USE doesn't make sense.
1164                  We depend here on combinable_i3pat to reject them.  */
1165               /* The code below this loop only verifies that the inputs of
1166                  the SET in INSN do not change.  We call reg_set_between_p
1167                  to verify that the REG in the USE does not change between
1168                  I3 and INSN.
1169                  If the USE in INSN was for a pseudo register, the matching
1170                  insn pattern will likely match any register; combining this
1171                  with any other USE would only be safe if we knew that the
1172                  used registers have identical values, or if there was
1173                  something to tell them apart, e.g. different modes.  For
1174                  now, we forgo such complicated tests and simply disallow
1175                  combining of USES of pseudo registers with any other USE.  */
1176               if (REG_P (XEXP (elt, 0))
1177                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1178                 {
1179                   rtx i3pat = PATTERN (i3);
1180                   int i = XVECLEN (i3pat, 0) - 1;
1181                   unsigned int regno = REGNO (XEXP (elt, 0));
1182
1183                   do
1184                     {
1185                       rtx i3elt = XVECEXP (i3pat, 0, i);
1186
1187                       if (GET_CODE (i3elt) == USE
1188                           && REG_P (XEXP (i3elt, 0))
1189                           && (REGNO (XEXP (i3elt, 0)) == regno
1190                               ? reg_set_between_p (XEXP (elt, 0),
1191                                                    PREV_INSN (insn), i3)
1192                               : regno >= FIRST_PSEUDO_REGISTER))
1193                         return 0;
1194                     }
1195                   while (--i >= 0);
1196                 }
1197               break;
1198
1199               /* We can ignore CLOBBERs.  */
1200             case CLOBBER:
1201               break;
1202
1203             case SET:
1204               /* Ignore SETs whose result isn't used but not those that
1205                  have side-effects.  */
1206               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1207                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1208                       || INTVAL (XEXP (note, 0)) <= 0)
1209                   && ! side_effects_p (elt))
1210                 break;
1211
1212               /* If we have already found a SET, this is a second one and
1213                  so we cannot combine with this insn.  */
1214               if (set)
1215                 return 0;
1216
1217               set = elt;
1218               break;
1219
1220             default:
1221               /* Anything else means we can't combine.  */
1222               return 0;
1223             }
1224         }
1225
1226       if (set == 0
1227           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1228              so don't do anything with it.  */
1229           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1230         return 0;
1231     }
1232   else
1233     return 0;
1234
1235   if (set == 0)
1236     return 0;
1237
1238   set = expand_field_assignment (set);
1239   src = SET_SRC (set), dest = SET_DEST (set);
1240
1241   /* Don't eliminate a store in the stack pointer.  */
1242   if (dest == stack_pointer_rtx
1243       /* Don't combine with an insn that sets a register to itself if it has
1244          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1245       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1246       /* Can't merge an ASM_OPERANDS.  */
1247       || GET_CODE (src) == ASM_OPERANDS
1248       /* Can't merge a function call.  */
1249       || GET_CODE (src) == CALL
1250       /* Don't eliminate a function call argument.  */
1251       || (CALL_P (i3)
1252           && (find_reg_fusage (i3, USE, dest)
1253               || (REG_P (dest)
1254                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1255                   && global_regs[REGNO (dest)])))
1256       /* Don't substitute into an incremented register.  */
1257       || FIND_REG_INC_NOTE (i3, dest)
1258       || (succ && FIND_REG_INC_NOTE (succ, dest))
1259       /* Don't substitute into a non-local goto, this confuses CFG.  */
1260       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1261 #if 0
1262       /* Don't combine the end of a libcall into anything.  */
1263       /* ??? This gives worse code, and appears to be unnecessary, since no
1264          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1265          use REG_RETVAL notes for noconflict blocks, but other code here
1266          makes sure that those insns don't disappear.  */
1267       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1268 #endif
1269       /* Make sure that DEST is not used after SUCC but before I3.  */
1270       || (succ && ! all_adjacent
1271           && reg_used_between_p (dest, succ, i3))
1272       /* Make sure that the value that is to be substituted for the register
1273          does not use any registers whose values alter in between.  However,
1274          If the insns are adjacent, a use can't cross a set even though we
1275          think it might (this can happen for a sequence of insns each setting
1276          the same destination; last_set of that register might point to
1277          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1278          equivalent to the memory so the substitution is valid even if there
1279          are intervening stores.  Also, don't move a volatile asm or
1280          UNSPEC_VOLATILE across any other insns.  */
1281       || (! all_adjacent
1282           && (((!MEM_P (src)
1283                 || ! find_reg_note (insn, REG_EQUIV, src))
1284                && use_crosses_set_p (src, INSN_CUID (insn)))
1285               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1286               || GET_CODE (src) == UNSPEC_VOLATILE))
1287       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1288          better register allocation by not doing the combine.  */
1289       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1290       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1291       /* Don't combine across a CALL_INSN, because that would possibly
1292          change whether the life span of some REGs crosses calls or not,
1293          and it is a pain to update that information.
1294          Exception: if source is a constant, moving it later can't hurt.
1295          Accept that special case, because it helps -fforce-addr a lot.  */
1296       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1297     return 0;
1298
1299   /* DEST must either be a REG or CC0.  */
1300   if (REG_P (dest))
1301     {
1302       /* If register alignment is being enforced for multi-word items in all
1303          cases except for parameters, it is possible to have a register copy
1304          insn referencing a hard register that is not allowed to contain the
1305          mode being copied and which would not be valid as an operand of most
1306          insns.  Eliminate this problem by not combining with such an insn.
1307
1308          Also, on some machines we don't want to extend the life of a hard
1309          register.  */
1310
1311       if (REG_P (src)
1312           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1313                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1314               /* Don't extend the life of a hard register unless it is
1315                  user variable (if we have few registers) or it can't
1316                  fit into the desired register (meaning something special
1317                  is going on).
1318                  Also avoid substituting a return register into I3, because
1319                  reload can't handle a conflict with constraints of other
1320                  inputs.  */
1321               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1322                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1323         return 0;
1324     }
1325   else if (GET_CODE (dest) != CC0)
1326     return 0;
1327
1328
1329   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1330     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1331       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1332         {
1333           /* Don't substitute for a register intended as a clobberable
1334              operand.  */
1335           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1336           if (rtx_equal_p (reg, dest))
1337             return 0;
1338
1339           /* If the clobber represents an earlyclobber operand, we must not
1340              substitute an expression containing the clobbered register.
1341              As we do not analyze the constraint strings here, we have to
1342              make the conservative assumption.  However, if the register is
1343              a fixed hard reg, the clobber cannot represent any operand;
1344              we leave it up to the machine description to either accept or
1345              reject use-and-clobber patterns.  */
1346           if (!REG_P (reg)
1347               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1348               || !fixed_regs[REGNO (reg)])
1349             if (reg_overlap_mentioned_p (reg, src))
1350               return 0;
1351         }
1352
1353   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1354      or not), reject, unless nothing volatile comes between it and I3 */
1355
1356   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1357     {
1358       /* Make sure succ doesn't contain a volatile reference.  */
1359       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1360         return 0;
1361
1362       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1363         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1364           return 0;
1365     }
1366
1367   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1368      to be an explicit register variable, and was chosen for a reason.  */
1369
1370   if (GET_CODE (src) == ASM_OPERANDS
1371       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1372     return 0;
1373
1374   /* If there are any volatile insns between INSN and I3, reject, because
1375      they might affect machine state.  */
1376
1377   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1378     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1379       return 0;
1380
1381   /* If INSN contains an autoincrement or autodecrement, make sure that
1382      register is not used between there and I3, and not already used in
1383      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1384      Also insist that I3 not be a jump; if it were one
1385      and the incremented register were spilled, we would lose.  */
1386
1387 #ifdef AUTO_INC_DEC
1388   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1389     if (REG_NOTE_KIND (link) == REG_INC
1390         && (JUMP_P (i3)
1391             || reg_used_between_p (XEXP (link, 0), insn, i3)
1392             || (pred != NULL_RTX
1393                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1394             || (succ != NULL_RTX
1395                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1396             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1397       return 0;
1398 #endif
1399
1400 #ifdef HAVE_cc0
1401   /* Don't combine an insn that follows a CC0-setting insn.
1402      An insn that uses CC0 must not be separated from the one that sets it.
1403      We do, however, allow I2 to follow a CC0-setting insn if that insn
1404      is passed as I1; in that case it will be deleted also.
1405      We also allow combining in this case if all the insns are adjacent
1406      because that would leave the two CC0 insns adjacent as well.
1407      It would be more logical to test whether CC0 occurs inside I1 or I2,
1408      but that would be much slower, and this ought to be equivalent.  */
1409
1410   p = prev_nonnote_insn (insn);
1411   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1412       && ! all_adjacent)
1413     return 0;
1414 #endif
1415
1416   /* If we get here, we have passed all the tests and the combination is
1417      to be allowed.  */
1418
1419   *pdest = dest;
1420   *psrc = src;
1421
1422   return 1;
1423 }
1424 \f
1425 /* LOC is the location within I3 that contains its pattern or the component
1426    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1427
1428    One problem is if I3 modifies its output, as opposed to replacing it
1429    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1430    so would produce an insn that is not equivalent to the original insns.
1431
1432    Consider:
1433
1434          (set (reg:DI 101) (reg:DI 100))
1435          (set (subreg:SI (reg:DI 101) 0) <foo>)
1436
1437    This is NOT equivalent to:
1438
1439          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1440                     (set (reg:DI 101) (reg:DI 100))])
1441
1442    Not only does this modify 100 (in which case it might still be valid
1443    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1444
1445    We can also run into a problem if I2 sets a register that I1
1446    uses and I1 gets directly substituted into I3 (not via I2).  In that
1447    case, we would be getting the wrong value of I2DEST into I3, so we
1448    must reject the combination.  This case occurs when I2 and I1 both
1449    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1450    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1451    of a SET must prevent combination from occurring.
1452
1453    Before doing the above check, we first try to expand a field assignment
1454    into a set of logical operations.
1455
1456    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1457    we place a register that is both set and used within I3.  If more than one
1458    such register is detected, we fail.
1459
1460    Return 1 if the combination is valid, zero otherwise.  */
1461
1462 static int
1463 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1464                   int i1_not_in_src, rtx *pi3dest_killed)
1465 {
1466   rtx x = *loc;
1467
1468   if (GET_CODE (x) == SET)
1469     {
1470       rtx set = x ;
1471       rtx dest = SET_DEST (set);
1472       rtx src = SET_SRC (set);
1473       rtx inner_dest = dest;
1474       rtx subdest;
1475
1476       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1477              || GET_CODE (inner_dest) == SUBREG
1478              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1479         inner_dest = XEXP (inner_dest, 0);
1480
1481       /* Check for the case where I3 modifies its output, as discussed
1482          above.  We don't want to prevent pseudos from being combined
1483          into the address of a MEM, so only prevent the combination if
1484          i1 or i2 set the same MEM.  */
1485       if ((inner_dest != dest &&
1486            (!MEM_P (inner_dest)
1487             || rtx_equal_p (i2dest, inner_dest)
1488             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1489            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1490                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1491
1492           /* This is the same test done in can_combine_p except we can't test
1493              all_adjacent; we don't have to, since this instruction will stay
1494              in place, thus we are not considering increasing the lifetime of
1495              INNER_DEST.
1496
1497              Also, if this insn sets a function argument, combining it with
1498              something that might need a spill could clobber a previous
1499              function argument; the all_adjacent test in can_combine_p also
1500              checks this; here, we do a more specific test for this case.  */
1501
1502           || (REG_P (inner_dest)
1503               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1504               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1505                                         GET_MODE (inner_dest))))
1506           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1507         return 0;
1508
1509       /* If DEST is used in I3, it is being killed in this insn, so
1510          record that for later.  We have to consider paradoxical
1511          subregs here, since they kill the whole register, but we
1512          ignore partial subregs, STRICT_LOW_PART, etc.
1513          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1514          STACK_POINTER_REGNUM, since these are always considered to be
1515          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1516       subdest = dest;
1517       if (GET_CODE (subdest) == SUBREG
1518           && (GET_MODE_SIZE (GET_MODE (subdest))
1519               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1520         subdest = SUBREG_REG (subdest);
1521       if (pi3dest_killed
1522           && REG_P (subdest)
1523           && reg_referenced_p (subdest, PATTERN (i3))
1524           && REGNO (subdest) != FRAME_POINTER_REGNUM
1525 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1527 #endif
1528 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529           && (REGNO (subdest) != ARG_POINTER_REGNUM
1530               || ! fixed_regs [REGNO (subdest)])
1531 #endif
1532           && REGNO (subdest) != STACK_POINTER_REGNUM)
1533         {
1534           if (*pi3dest_killed)
1535             return 0;
1536
1537           *pi3dest_killed = subdest;
1538         }
1539     }
1540
1541   else if (GET_CODE (x) == PARALLEL)
1542     {
1543       int i;
1544
1545       for (i = 0; i < XVECLEN (x, 0); i++)
1546         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1547                                 i1_not_in_src, pi3dest_killed))
1548           return 0;
1549     }
1550
1551   return 1;
1552 }
1553 \f
1554 /* Return 1 if X is an arithmetic expression that contains a multiplication
1555    and division.  We don't count multiplications by powers of two here.  */
1556
1557 static int
1558 contains_muldiv (rtx x)
1559 {
1560   switch (GET_CODE (x))
1561     {
1562     case MOD:  case DIV:  case UMOD:  case UDIV:
1563       return 1;
1564
1565     case MULT:
1566       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1567                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1568     default:
1569       if (BINARY_P (x))
1570         return contains_muldiv (XEXP (x, 0))
1571             || contains_muldiv (XEXP (x, 1));
1572
1573       if (UNARY_P (x))
1574         return contains_muldiv (XEXP (x, 0));
1575
1576       return 0;
1577     }
1578 }
1579 \f
1580 /* Determine whether INSN can be used in a combination.  Return nonzero if
1581    not.  This is used in try_combine to detect early some cases where we
1582    can't perform combinations.  */
1583
1584 static int
1585 cant_combine_insn_p (rtx insn)
1586 {
1587   rtx set;
1588   rtx src, dest;
1589
1590   /* If this isn't really an insn, we can't do anything.
1591      This can occur when flow deletes an insn that it has merged into an
1592      auto-increment address.  */
1593   if (! INSN_P (insn))
1594     return 1;
1595
1596   /* Never combine loads and stores involving hard regs that are likely
1597      to be spilled.  The register allocator can usually handle such
1598      reg-reg moves by tying.  If we allow the combiner to make
1599      substitutions of likely-spilled regs, reload might die.
1600      As an exception, we allow combinations involving fixed regs; these are
1601      not available to the register allocator so there's no risk involved.  */
1602
1603   set = single_set (insn);
1604   if (! set)
1605     return 0;
1606   src = SET_SRC (set);
1607   dest = SET_DEST (set);
1608   if (GET_CODE (src) == SUBREG)
1609     src = SUBREG_REG (src);
1610   if (GET_CODE (dest) == SUBREG)
1611     dest = SUBREG_REG (dest);
1612   if (REG_P (src) && REG_P (dest)
1613       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1614            && ! fixed_regs[REGNO (src)]
1615            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1616           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1617               && ! fixed_regs[REGNO (dest)]
1618               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1619     return 1;
1620
1621   return 0;
1622 }
1623
1624 struct likely_spilled_retval_info
1625 {
1626   unsigned regno, nregs;
1627   unsigned mask;
1628 };
1629
1630 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1631    hard registers that are known to be written to / clobbered in full.  */
1632 static void
1633 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1634 {
1635   struct likely_spilled_retval_info *info = data;
1636   unsigned regno, nregs;
1637   unsigned new_mask;
1638
1639   if (!REG_P (XEXP (set, 0)))
1640     return;
1641   regno = REGNO (x);
1642   if (regno >= info->regno + info->nregs)
1643     return;
1644   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1645   if (regno + nregs <= info->regno)
1646     return;
1647   new_mask = (2U << (nregs - 1)) - 1;
1648   if (regno < info->regno)
1649     new_mask >>= info->regno - regno;
1650   else
1651     new_mask <<= regno - info->regno;
1652   info->mask &= new_mask;
1653 }
1654
1655 /* Return nonzero iff part of the return value is live during INSN, and
1656    it is likely spilled.  This can happen when more than one insn is needed
1657    to copy the return value, e.g. when we consider to combine into the
1658    second copy insn for a complex value.  */
1659
1660 static int
1661 likely_spilled_retval_p (rtx insn)
1662 {
1663   rtx use = BB_END (this_basic_block);
1664   rtx reg, p;
1665   unsigned regno, nregs;
1666   /* We assume here that no machine mode needs more than
1667      32 hard registers when the value overlaps with a register
1668      for which FUNCTION_VALUE_REGNO_P is true.  */
1669   unsigned mask;
1670   struct likely_spilled_retval_info info;
1671
1672   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1673     return 0;
1674   reg = XEXP (PATTERN (use), 0);
1675   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1676     return 0;
1677   regno = REGNO (reg);
1678   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1679   if (nregs == 1)
1680     return 0;
1681   mask = (2U << (nregs - 1)) - 1;
1682
1683   /* Disregard parts of the return value that are set later.  */
1684   info.regno = regno;
1685   info.nregs = nregs;
1686   info.mask = mask;
1687   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1688     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1689   mask = info.mask;
1690
1691   /* Check if any of the (probably) live return value registers is
1692      likely spilled.  */
1693   nregs --;
1694   do
1695     {
1696       if ((mask & 1 << nregs)
1697           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1698         return 1;
1699     } while (nregs--);
1700   return 0;
1701 }
1702
1703 /* Adjust INSN after we made a change to its destination.
1704
1705    Changing the destination can invalidate notes that say something about
1706    the results of the insn and a LOG_LINK pointing to the insn.  */
1707
1708 static void
1709 adjust_for_new_dest (rtx insn)
1710 {
1711   rtx *loc;
1712
1713   /* For notes, be conservative and simply remove them.  */
1714   loc = &REG_NOTES (insn);
1715   while (*loc)
1716     {
1717       enum reg_note kind = REG_NOTE_KIND (*loc);
1718       if (kind == REG_EQUAL || kind == REG_EQUIV)
1719         *loc = XEXP (*loc, 1);
1720       else
1721         loc = &XEXP (*loc, 1);
1722     }
1723
1724   /* The new insn will have a destination that was previously the destination
1725      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1726      the next use of that destination.  */
1727   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1728 }
1729
1730 /* Return TRUE if combine can reuse reg X in mode MODE.
1731    ADDED_SETS is nonzero if the original set is still required.  */
1732 static bool
1733 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1734 {
1735   unsigned int regno;
1736
1737   if (!REG_P(x))
1738     return false;
1739
1740   regno = REGNO (x);
1741   /* Allow hard registers if the new mode is legal, and occupies no more
1742      registers than the old mode.  */
1743   if (regno < FIRST_PSEUDO_REGISTER)
1744     return (HARD_REGNO_MODE_OK (regno, mode)
1745             && (hard_regno_nregs[regno][GET_MODE (x)]
1746                 >= hard_regno_nregs[regno][mode]));
1747
1748   /* Or a pseudo that is only used once.  */
1749   return (REG_N_SETS (regno) == 1 && !added_sets
1750           && !REG_USERVAR_P (x));
1751 }
1752
1753
1754 /* Check whether X, the destination of a set, refers to part of
1755    the register specified by REG.  */
1756
1757 static bool
1758 reg_subword_p (rtx x, rtx reg)
1759 {
1760   /* Check that reg is an integer mode register.  */
1761   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1762     return false;
1763
1764   if (GET_CODE (x) == STRICT_LOW_PART
1765       || GET_CODE (x) == ZERO_EXTRACT)
1766     x = XEXP (x, 0);
1767
1768   return GET_CODE (x) == SUBREG
1769          && SUBREG_REG (x) == reg
1770          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1771 }
1772
1773
1774 /* Try to combine the insns I1 and I2 into I3.
1775    Here I1 and I2 appear earlier than I3.
1776    I1 can be zero; then we combine just I2 into I3.
1777
1778    If we are combining three insns and the resulting insn is not recognized,
1779    try splitting it into two insns.  If that happens, I2 and I3 are retained
1780    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1781    are pseudo-deleted.
1782
1783    Return 0 if the combination does not work.  Then nothing is changed.
1784    If we did the combination, return the insn at which combine should
1785    resume scanning.
1786
1787    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1788    new direct jump instruction.  */
1789
1790 static rtx
1791 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1792 {
1793   /* New patterns for I3 and I2, respectively.  */
1794   rtx newpat, newi2pat = 0;
1795   rtvec newpat_vec_with_clobbers = 0;
1796   int substed_i2 = 0, substed_i1 = 0;
1797   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1798   int added_sets_1, added_sets_2;
1799   /* Total number of SETs to put into I3.  */
1800   int total_sets;
1801   /* Nonzero if I2's body now appears in I3.  */
1802   int i2_is_used;
1803   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1804   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1805   /* Contains I3 if the destination of I3 is used in its source, which means
1806      that the old life of I3 is being killed.  If that usage is placed into
1807      I2 and not in I3, a REG_DEAD note must be made.  */
1808   rtx i3dest_killed = 0;
1809   /* SET_DEST and SET_SRC of I2 and I1.  */
1810   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1811   /* PATTERN (I2), or a copy of it in certain cases.  */
1812   rtx i2pat;
1813   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1814   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1815   int i2dest_killed = 0, i1dest_killed = 0;
1816   int i1_feeds_i3 = 0;
1817   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1818   rtx new_i3_notes, new_i2_notes;
1819   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1820   int i3_subst_into_i2 = 0;
1821   /* Notes that I1, I2 or I3 is a MULT operation.  */
1822   int have_mult = 0;
1823   int swap_i2i3 = 0;
1824
1825   int maxreg;
1826   rtx temp;
1827   rtx link;
1828   int i;
1829
1830   /* Exit early if one of the insns involved can't be used for
1831      combinations.  */
1832   if (cant_combine_insn_p (i3)
1833       || cant_combine_insn_p (i2)
1834       || (i1 && cant_combine_insn_p (i1))
1835       || likely_spilled_retval_p (i3)
1836       /* We also can't do anything if I3 has a
1837          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1838          libcall.  */
1839 #if 0
1840       /* ??? This gives worse code, and appears to be unnecessary, since no
1841          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1842       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1843 #endif
1844       )
1845     return 0;
1846
1847   combine_attempts++;
1848   undobuf.other_insn = 0;
1849
1850   /* Reset the hard register usage information.  */
1851   CLEAR_HARD_REG_SET (newpat_used_regs);
1852
1853   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1854      code below, set I1 to be the earlier of the two insns.  */
1855   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1856     temp = i1, i1 = i2, i2 = temp;
1857
1858   added_links_insn = 0;
1859
1860   /* First check for one important special-case that the code below will
1861      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1862      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1863      we may be able to replace that destination with the destination of I3.
1864      This occurs in the common code where we compute both a quotient and
1865      remainder into a structure, in which case we want to do the computation
1866      directly into the structure to avoid register-register copies.
1867
1868      Note that this case handles both multiple sets in I2 and also
1869      cases where I2 has a number of CLOBBER or PARALLELs.
1870
1871      We make very conservative checks below and only try to handle the
1872      most common cases of this.  For example, we only handle the case
1873      where I2 and I3 are adjacent to avoid making difficult register
1874      usage tests.  */
1875
1876   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1877       && REG_P (SET_SRC (PATTERN (i3)))
1878       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1879       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1880       && GET_CODE (PATTERN (i2)) == PARALLEL
1881       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1882       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1883          below would need to check what is inside (and reg_overlap_mentioned_p
1884          doesn't support those codes anyway).  Don't allow those destinations;
1885          the resulting insn isn't likely to be recognized anyway.  */
1886       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1887       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1888       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1889                                     SET_DEST (PATTERN (i3)))
1890       && next_real_insn (i2) == i3)
1891     {
1892       rtx p2 = PATTERN (i2);
1893
1894       /* Make sure that the destination of I3,
1895          which we are going to substitute into one output of I2,
1896          is not used within another output of I2.  We must avoid making this:
1897          (parallel [(set (mem (reg 69)) ...)
1898                     (set (reg 69) ...)])
1899          which is not well-defined as to order of actions.
1900          (Besides, reload can't handle output reloads for this.)
1901
1902          The problem can also happen if the dest of I3 is a memory ref,
1903          if another dest in I2 is an indirect memory ref.  */
1904       for (i = 0; i < XVECLEN (p2, 0); i++)
1905         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1906              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1907             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1908                                         SET_DEST (XVECEXP (p2, 0, i))))
1909           break;
1910
1911       if (i == XVECLEN (p2, 0))
1912         for (i = 0; i < XVECLEN (p2, 0); i++)
1913           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1914                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1915               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1916             {
1917               combine_merges++;
1918
1919               subst_insn = i3;
1920               subst_low_cuid = INSN_CUID (i2);
1921
1922               added_sets_2 = added_sets_1 = 0;
1923               i2dest = SET_SRC (PATTERN (i3));
1924               i2dest_killed = dead_or_set_p (i2, i2dest);
1925
1926               /* Replace the dest in I2 with our dest and make the resulting
1927                  insn the new pattern for I3.  Then skip to where we
1928                  validate the pattern.  Everything was set up above.  */
1929               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1930                      SET_DEST (PATTERN (i3)));
1931
1932               newpat = p2;
1933               i3_subst_into_i2 = 1;
1934               goto validate_replacement;
1935             }
1936     }
1937
1938   /* If I2 is setting a pseudo to a constant and I3 is setting some
1939      sub-part of it to another constant, merge them by making a new
1940      constant.  */
1941   if (i1 == 0
1942       && (temp = single_set (i2)) != 0
1943       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1944           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1945       && GET_CODE (PATTERN (i3)) == SET
1946       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1947           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1948       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1949     {
1950       rtx dest = SET_DEST (PATTERN (i3));
1951       int offset = -1;
1952       int width = 0;
1953
1954       if (GET_CODE (dest) == STRICT_LOW_PART)
1955         {
1956           width = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)));
1957           offset = 0;
1958         }
1959       else if (GET_CODE (dest) == ZERO_EXTRACT)
1960         {
1961           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1962               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1963             {
1964               width = INTVAL (XEXP (dest, 1));
1965               offset = INTVAL (XEXP (dest, 2));
1966
1967               if (BITS_BIG_ENDIAN)
1968                 offset = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)))
1969                          - width - offset;
1970             }
1971         }
1972       else if (subreg_lowpart_p (dest))
1973         {
1974           width = GET_MODE_BITSIZE (GET_MODE (dest));
1975           offset = 0;
1976         }
1977       /* ??? Preserve the original logic to handle setting the high word
1978          of double-word pseudos, where inner is half the size of outer
1979          but not the lowpart.  This could be generalized by handling
1980          SUBREG_BYTE, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN ourselves.
1981          Unfortunately this logic is tricky to get right and probably
1982          not worth the effort.  */
1983       else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1984                == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1985         {
1986           width = GET_MODE_BITSIZE (GET_MODE (dest));
1987           offset = width;
1988         }
1989
1990       if (offset >= 0)
1991         {
1992           HOST_WIDE_INT mhi, ohi, ihi;
1993           HOST_WIDE_INT mlo, olo, ilo;
1994           rtx inner = SET_SRC (PATTERN (i3));
1995           rtx outer = SET_SRC (temp);
1996
1997           if (GET_CODE (outer) == CONST_INT)
1998             {
1999               olo = INTVAL (outer);
2000               ohi = olo < 0 ? -1 : 0;
2001             }
2002           else
2003             {
2004               olo = CONST_DOUBLE_LOW (outer);
2005               ohi = CONST_DOUBLE_HIGH (outer);
2006             }
2007
2008           if (GET_CODE (inner) == CONST_INT)
2009             {
2010               ilo = INTVAL (inner);
2011               ihi = ilo < 0 ? -1 : 0;
2012             }
2013           else
2014             {
2015               ilo = CONST_DOUBLE_LOW (inner);
2016               ihi = CONST_DOUBLE_HIGH (inner);
2017             }
2018
2019           if (width < HOST_BITS_PER_WIDE_INT)
2020             {
2021               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2022               mhi = 0;
2023             }
2024           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2025             {
2026               mhi = ((unsigned HOST_WIDE_INT) 1
2027                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2028               mlo = -1;
2029             }
2030           else
2031             {
2032               mlo = -1;
2033               mhi = -1;
2034             }
2035
2036           ilo &= mlo;
2037           ihi &= mhi;
2038
2039           if (offset >= HOST_BITS_PER_WIDE_INT)
2040             {
2041               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2042               mlo = 0;
2043               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2044               ilo = 0;
2045             }
2046           else if (offset > 0)
2047             {
2048               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2049                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2050               mlo = mlo << offset;
2051               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2052                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2053               ilo = ilo << offset;
2054             }
2055
2056           olo = (olo & ~mlo) | ilo;
2057           ohi = (ohi & ~mhi) | ihi;
2058
2059           combine_merges++;
2060           subst_insn = i3;
2061           subst_low_cuid = INSN_CUID (i2);
2062           added_sets_2 = added_sets_1 = 0;
2063           i2dest = SET_DEST (temp);
2064           i2dest_killed = dead_or_set_p (i2, i2dest);
2065
2066           SUBST (SET_SRC (temp),
2067                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2068
2069           newpat = PATTERN (i2);
2070           goto validate_replacement;
2071         }
2072     }
2073
2074 #ifndef HAVE_cc0
2075   /* If we have no I1 and I2 looks like:
2076         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2077                    (set Y OP)])
2078      make up a dummy I1 that is
2079         (set Y OP)
2080      and change I2 to be
2081         (set (reg:CC X) (compare:CC Y (const_int 0)))
2082
2083      (We can ignore any trailing CLOBBERs.)
2084
2085      This undoes a previous combination and allows us to match a branch-and-
2086      decrement insn.  */
2087
2088   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2089       && XVECLEN (PATTERN (i2), 0) >= 2
2090       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2091       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2092           == MODE_CC)
2093       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2094       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2095       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2096       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2097       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2098                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2099     {
2100       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2101         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2102           break;
2103
2104       if (i == 1)
2105         {
2106           /* We make I1 with the same INSN_UID as I2.  This gives it
2107              the same INSN_CUID for value tracking.  Our fake I1 will
2108              never appear in the insn stream so giving it the same INSN_UID
2109              as I2 will not cause a problem.  */
2110
2111           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2112                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2113                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2114                              NULL_RTX);
2115
2116           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2117           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2118                  SET_DEST (PATTERN (i1)));
2119         }
2120     }
2121 #endif
2122
2123   /* Verify that I2 and I1 are valid for combining.  */
2124   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2125       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2126     {
2127       undo_all ();
2128       return 0;
2129     }
2130
2131   /* Record whether I2DEST is used in I2SRC and similarly for the other
2132      cases.  Knowing this will help in register status updating below.  */
2133   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2134   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2135   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2136   i2dest_killed = dead_or_set_p (i2, i2dest);
2137   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2138
2139   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2140      in I2SRC.  */
2141   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2142
2143   /* Ensure that I3's pattern can be the destination of combines.  */
2144   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2145                           i1 && i2dest_in_i1src && i1_feeds_i3,
2146                           &i3dest_killed))
2147     {
2148       undo_all ();
2149       return 0;
2150     }
2151
2152   /* See if any of the insns is a MULT operation.  Unless one is, we will
2153      reject a combination that is, since it must be slower.  Be conservative
2154      here.  */
2155   if (GET_CODE (i2src) == MULT
2156       || (i1 != 0 && GET_CODE (i1src) == MULT)
2157       || (GET_CODE (PATTERN (i3)) == SET
2158           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2159     have_mult = 1;
2160
2161   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2162      We used to do this EXCEPT in one case: I3 has a post-inc in an
2163      output operand.  However, that exception can give rise to insns like
2164         mov r3,(r3)+
2165      which is a famous insn on the PDP-11 where the value of r3 used as the
2166      source was model-dependent.  Avoid this sort of thing.  */
2167
2168 #if 0
2169   if (!(GET_CODE (PATTERN (i3)) == SET
2170         && REG_P (SET_SRC (PATTERN (i3)))
2171         && MEM_P (SET_DEST (PATTERN (i3)))
2172         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2173             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2174     /* It's not the exception.  */
2175 #endif
2176 #ifdef AUTO_INC_DEC
2177     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2178       if (REG_NOTE_KIND (link) == REG_INC
2179           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2180               || (i1 != 0
2181                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2182         {
2183           undo_all ();
2184           return 0;
2185         }
2186 #endif
2187
2188   /* See if the SETs in I1 or I2 need to be kept around in the merged
2189      instruction: whenever the value set there is still needed past I3.
2190      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2191
2192      For the SET in I1, we have two cases:  If I1 and I2 independently
2193      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2194      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2195      in I1 needs to be kept around unless I1DEST dies or is set in either
2196      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2197      I1DEST.  If so, we know I1 feeds into I2.  */
2198
2199   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2200
2201   added_sets_1
2202     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2203                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2204
2205   /* If the set in I2 needs to be kept around, we must make a copy of
2206      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2207      PATTERN (I2), we are only substituting for the original I1DEST, not into
2208      an already-substituted copy.  This also prevents making self-referential
2209      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2210      I2DEST.  */
2211
2212   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2213            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2214            : PATTERN (i2));
2215
2216   if (added_sets_2)
2217     i2pat = copy_rtx (i2pat);
2218
2219   combine_merges++;
2220
2221   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2222
2223   maxreg = max_reg_num ();
2224
2225   subst_insn = i3;
2226
2227 #ifndef HAVE_cc0
2228   /* Many machines that don't use CC0 have insns that can both perform an
2229      arithmetic operation and set the condition code.  These operations will
2230      be represented as a PARALLEL with the first element of the vector
2231      being a COMPARE of an arithmetic operation with the constant zero.
2232      The second element of the vector will set some pseudo to the result
2233      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2234      match such a pattern and so will generate an extra insn.   Here we test
2235      for this case, where both the comparison and the operation result are
2236      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2237      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2238
2239   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2240       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2241       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2242       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2243     {
2244 #ifdef SELECT_CC_MODE
2245       rtx *cc_use;
2246       enum machine_mode compare_mode;
2247 #endif
2248
2249       newpat = PATTERN (i3);
2250       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2251
2252       i2_is_used = 1;
2253
2254 #ifdef SELECT_CC_MODE
2255       /* See if a COMPARE with the operand we substituted in should be done
2256          with the mode that is currently being used.  If not, do the same
2257          processing we do in `subst' for a SET; namely, if the destination
2258          is used only once, try to replace it with a register of the proper
2259          mode and also replace the COMPARE.  */
2260       if (undobuf.other_insn == 0
2261           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2262                                         &undobuf.other_insn))
2263           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2264                                               i2src, const0_rtx))
2265               != GET_MODE (SET_DEST (newpat))))
2266         {
2267           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2268                                    compare_mode))
2269             {
2270               unsigned int regno = REGNO (SET_DEST (newpat));
2271               rtx new_dest;
2272
2273               if (regno < FIRST_PSEUDO_REGISTER)
2274                 new_dest = gen_rtx_REG (compare_mode, regno);
2275               else
2276                 {
2277                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2278                   new_dest = regno_reg_rtx[regno];
2279                 }
2280
2281               SUBST (SET_DEST (newpat), new_dest);
2282               SUBST (XEXP (*cc_use, 0), new_dest);
2283               SUBST (SET_SRC (newpat),
2284                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2285             }
2286           else
2287             undobuf.other_insn = 0;
2288         }
2289 #endif
2290     }
2291   else
2292 #endif
2293     {
2294       /* It is possible that the source of I2 or I1 may be performing
2295          an unneeded operation, such as a ZERO_EXTEND of something
2296          that is known to have the high part zero.  Handle that case
2297          by letting subst look at the innermost one of them.
2298
2299          Another way to do this would be to have a function that tries
2300          to simplify a single insn instead of merging two or more
2301          insns.  We don't do this because of the potential of infinite
2302          loops and because of the potential extra memory required.
2303          However, doing it the way we are is a bit of a kludge and
2304          doesn't catch all cases.
2305
2306          But only do this if -fexpensive-optimizations since it slows
2307          things down and doesn't usually win.
2308
2309          This is not done in the COMPARE case above because the
2310          unmodified I2PAT is used in the PARALLEL and so a pattern
2311          with a modified I2SRC would not match.  */
2312
2313       if (flag_expensive_optimizations)
2314         {
2315           /* Pass pc_rtx so no substitutions are done, just
2316              simplifications.  */
2317           if (i1)
2318             {
2319               subst_low_cuid = INSN_CUID (i1);
2320               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2321             }
2322           else
2323             {
2324               subst_low_cuid = INSN_CUID (i2);
2325               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2326             }
2327         }
2328
2329       n_occurrences = 0;                /* `subst' counts here */
2330
2331       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2332          need to make a unique copy of I2SRC each time we substitute it
2333          to avoid self-referential rtl.  */
2334
2335       subst_low_cuid = INSN_CUID (i2);
2336       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2337                       ! i1_feeds_i3 && i1dest_in_i1src);
2338       substed_i2 = 1;
2339
2340       /* Record whether i2's body now appears within i3's body.  */
2341       i2_is_used = n_occurrences;
2342     }
2343
2344   /* If we already got a failure, don't try to do more.  Otherwise,
2345      try to substitute in I1 if we have it.  */
2346
2347   if (i1 && GET_CODE (newpat) != CLOBBER)
2348     {
2349       /* Before we can do this substitution, we must redo the test done
2350          above (see detailed comments there) that ensures  that I1DEST
2351          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2352
2353       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2354                               0, (rtx*) 0))
2355         {
2356           undo_all ();
2357           return 0;
2358         }
2359
2360       n_occurrences = 0;
2361       subst_low_cuid = INSN_CUID (i1);
2362       newpat = subst (newpat, i1dest, i1src, 0, 0);
2363       substed_i1 = 1;
2364     }
2365
2366   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2367      to count all the ways that I2SRC and I1SRC can be used.  */
2368   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2369        && i2_is_used + added_sets_2 > 1)
2370       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2371           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2372               > 1))
2373       /* Fail if we tried to make a new register.  */
2374       || max_reg_num () != maxreg
2375       /* Fail if we couldn't do something and have a CLOBBER.  */
2376       || GET_CODE (newpat) == CLOBBER
2377       /* Fail if this new pattern is a MULT and we didn't have one before
2378          at the outer level.  */
2379       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2380           && ! have_mult))
2381     {
2382       undo_all ();
2383       return 0;
2384     }
2385
2386   /* If the actions of the earlier insns must be kept
2387      in addition to substituting them into the latest one,
2388      we must make a new PARALLEL for the latest insn
2389      to hold additional the SETs.  */
2390
2391   if (added_sets_1 || added_sets_2)
2392     {
2393       combine_extras++;
2394
2395       if (GET_CODE (newpat) == PARALLEL)
2396         {
2397           rtvec old = XVEC (newpat, 0);
2398           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2399           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2400           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2401                   sizeof (old->elem[0]) * old->num_elem);
2402         }
2403       else
2404         {
2405           rtx old = newpat;
2406           total_sets = 1 + added_sets_1 + added_sets_2;
2407           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2408           XVECEXP (newpat, 0, 0) = old;
2409         }
2410
2411       if (added_sets_1)
2412         XVECEXP (newpat, 0, --total_sets)
2413           = (GET_CODE (PATTERN (i1)) == PARALLEL
2414              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2415
2416       if (added_sets_2)
2417         {
2418           /* If there is no I1, use I2's body as is.  We used to also not do
2419              the subst call below if I2 was substituted into I3,
2420              but that could lose a simplification.  */
2421           if (i1 == 0)
2422             XVECEXP (newpat, 0, --total_sets) = i2pat;
2423           else
2424             /* See comment where i2pat is assigned.  */
2425             XVECEXP (newpat, 0, --total_sets)
2426               = subst (i2pat, i1dest, i1src, 0, 0);
2427         }
2428     }
2429
2430   /* We come here when we are replacing a destination in I2 with the
2431      destination of I3.  */
2432  validate_replacement:
2433
2434   /* Note which hard regs this insn has as inputs.  */
2435   mark_used_regs_combine (newpat);
2436
2437   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2438      consider splitting this pattern, we might need these clobbers.  */
2439   if (i1 && GET_CODE (newpat) == PARALLEL
2440       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2441     {
2442       int len = XVECLEN (newpat, 0);
2443
2444       newpat_vec_with_clobbers = rtvec_alloc (len);
2445       for (i = 0; i < len; i++)
2446         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2447     }
2448
2449   /* Is the result of combination a valid instruction?  */
2450   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2451
2452   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2453      the second SET's destination is a register that is unused and isn't
2454      marked as an instruction that might trap in an EH region.  In that case,
2455      we just need the first SET.   This can occur when simplifying a divmod
2456      insn.  We *must* test for this case here because the code below that
2457      splits two independent SETs doesn't handle this case correctly when it
2458      updates the register status.
2459
2460      It's pointless doing this if we originally had two sets, one from
2461      i3, and one from i2.  Combining then splitting the parallel results
2462      in the original i2 again plus an invalid insn (which we delete).
2463      The net effect is only to move instructions around, which makes
2464      debug info less accurate.
2465
2466      Also check the case where the first SET's destination is unused.
2467      That would not cause incorrect code, but does cause an unneeded
2468      insn to remain.  */
2469
2470   if (insn_code_number < 0
2471       && !(added_sets_2 && i1 == 0)
2472       && GET_CODE (newpat) == PARALLEL
2473       && XVECLEN (newpat, 0) == 2
2474       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2475       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2476       && asm_noperands (newpat) < 0)
2477     {
2478       rtx set0 = XVECEXP (newpat, 0, 0);
2479       rtx set1 = XVECEXP (newpat, 0, 1);
2480       rtx note;
2481
2482       if (((REG_P (SET_DEST (set1))
2483             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2484            || (GET_CODE (SET_DEST (set1)) == SUBREG
2485                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2486           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2487               || INTVAL (XEXP (note, 0)) <= 0)
2488           && ! side_effects_p (SET_SRC (set1)))
2489         {
2490           newpat = set0;
2491           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2492         }
2493
2494       else if (((REG_P (SET_DEST (set0))
2495                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2496                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2497                     && find_reg_note (i3, REG_UNUSED,
2498                                       SUBREG_REG (SET_DEST (set0)))))
2499                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2500                    || INTVAL (XEXP (note, 0)) <= 0)
2501                && ! side_effects_p (SET_SRC (set0)))
2502         {
2503           newpat = set1;
2504           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2505
2506           if (insn_code_number >= 0)
2507             {
2508               /* If we will be able to accept this, we have made a
2509                  change to the destination of I3.  This requires us to
2510                  do a few adjustments.  */
2511
2512               PATTERN (i3) = newpat;
2513               adjust_for_new_dest (i3);
2514             }
2515         }
2516     }
2517
2518   /* If we were combining three insns and the result is a simple SET
2519      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2520      insns.  There are two ways to do this.  It can be split using a
2521      machine-specific method (like when you have an addition of a large
2522      constant) or by combine in the function find_split_point.  */
2523
2524   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2525       && asm_noperands (newpat) < 0)
2526     {
2527       rtx m_split, *split;
2528
2529       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2530          use I2DEST as a scratch register will help.  In the latter case,
2531          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2532
2533       m_split = split_insns (newpat, i3);
2534
2535       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2536          inputs of NEWPAT.  */
2537
2538       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2539          possible to try that as a scratch reg.  This would require adding
2540          more code to make it work though.  */
2541
2542       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2543         {
2544           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2545
2546           /* First try to split using the original register as a
2547              scratch register.  */
2548           m_split = split_insns (gen_rtx_PARALLEL
2549                                  (VOIDmode,
2550                                   gen_rtvec (2, newpat,
2551                                              gen_rtx_CLOBBER (VOIDmode,
2552                                                               i2dest))),
2553                                  i3);
2554
2555           /* If that didn't work, try changing the mode of I2DEST if
2556              we can.  */
2557           if (m_split == 0
2558               && new_mode != GET_MODE (i2dest)
2559               && new_mode != VOIDmode
2560               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2561             {
2562               enum machine_mode old_mode = GET_MODE (i2dest);
2563               rtx ni2dest;
2564
2565               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2566                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2567               else
2568                 {
2569                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2570                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2571                 }
2572
2573               m_split = split_insns (gen_rtx_PARALLEL
2574                                      (VOIDmode,
2575                                       gen_rtvec (2, newpat,
2576                                                  gen_rtx_CLOBBER (VOIDmode,
2577                                                                   ni2dest))),
2578                                      i3);
2579
2580               if (m_split == 0
2581                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2582                 {
2583                   struct undo *buf;
2584
2585                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2586                   buf = undobuf.undos;
2587                   undobuf.undos = buf->next;
2588                   buf->next = undobuf.frees;
2589                   undobuf.frees = buf;
2590                 }
2591             }
2592         }
2593
2594       /* If recog_for_combine has discarded clobbers, try to use them
2595          again for the split.  */
2596       if (m_split == 0 && newpat_vec_with_clobbers)
2597         m_split
2598           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2599                                            newpat_vec_with_clobbers), i3);
2600
2601       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2602         {
2603           m_split = PATTERN (m_split);
2604           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2605           if (insn_code_number >= 0)
2606             newpat = m_split;
2607         }
2608       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2609                && (next_real_insn (i2) == i3
2610                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2611         {
2612           rtx i2set, i3set;
2613           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2614           newi2pat = PATTERN (m_split);
2615
2616           i3set = single_set (NEXT_INSN (m_split));
2617           i2set = single_set (m_split);
2618
2619           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2620
2621           /* If I2 or I3 has multiple SETs, we won't know how to track
2622              register status, so don't use these insns.  If I2's destination
2623              is used between I2 and I3, we also can't use these insns.  */
2624
2625           if (i2_code_number >= 0 && i2set && i3set
2626               && (next_real_insn (i2) == i3
2627                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2628             insn_code_number = recog_for_combine (&newi3pat, i3,
2629                                                   &new_i3_notes);
2630           if (insn_code_number >= 0)
2631             newpat = newi3pat;
2632
2633           /* It is possible that both insns now set the destination of I3.
2634              If so, we must show an extra use of it.  */
2635
2636           if (insn_code_number >= 0)
2637             {
2638               rtx new_i3_dest = SET_DEST (i3set);
2639               rtx new_i2_dest = SET_DEST (i2set);
2640
2641               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2642                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2643                      || GET_CODE (new_i3_dest) == SUBREG)
2644                 new_i3_dest = XEXP (new_i3_dest, 0);
2645
2646               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2647                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2648                      || GET_CODE (new_i2_dest) == SUBREG)
2649                 new_i2_dest = XEXP (new_i2_dest, 0);
2650
2651               if (REG_P (new_i3_dest)
2652                   && REG_P (new_i2_dest)
2653                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2654                 REG_N_SETS (REGNO (new_i2_dest))++;
2655             }
2656         }
2657
2658       /* If we can split it and use I2DEST, go ahead and see if that
2659          helps things be recognized.  Verify that none of the registers
2660          are set between I2 and I3.  */
2661       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2662 #ifdef HAVE_cc0
2663           && REG_P (i2dest)
2664 #endif
2665           /* We need I2DEST in the proper mode.  If it is a hard register
2666              or the only use of a pseudo, we can change its mode.
2667              Make sure we don't change a hard register to have a mode that
2668              isn't valid for it, or change the number of registers.  */
2669           && (GET_MODE (*split) == GET_MODE (i2dest)
2670               || GET_MODE (*split) == VOIDmode
2671               || can_change_dest_mode (i2dest, added_sets_2,
2672                                        GET_MODE (*split)))
2673           && (next_real_insn (i2) == i3
2674               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2675           /* We can't overwrite I2DEST if its value is still used by
2676              NEWPAT.  */
2677           && ! reg_referenced_p (i2dest, newpat))
2678         {
2679           rtx newdest = i2dest;
2680           enum rtx_code split_code = GET_CODE (*split);
2681           enum machine_mode split_mode = GET_MODE (*split);
2682           bool subst_done = false;
2683           newi2pat = NULL_RTX;
2684
2685           /* Get NEWDEST as a register in the proper mode.  We have already
2686              validated that we can do this.  */
2687           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2688             {
2689               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2690                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2691               else
2692                 {
2693                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2694                   newdest = regno_reg_rtx[REGNO (i2dest)];
2695                 }
2696             }
2697
2698           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2699              an ASHIFT.  This can occur if it was inside a PLUS and hence
2700              appeared to be a memory address.  This is a kludge.  */
2701           if (split_code == MULT
2702               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2703               && INTVAL (XEXP (*split, 1)) > 0
2704               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2705             {
2706               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2707                                              XEXP (*split, 0), GEN_INT (i)));
2708               /* Update split_code because we may not have a multiply
2709                  anymore.  */
2710               split_code = GET_CODE (*split);
2711             }
2712
2713 #ifdef INSN_SCHEDULING
2714           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2715              be written as a ZERO_EXTEND.  */
2716           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2717             {
2718 #ifdef LOAD_EXTEND_OP
2719               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2720                  what it really is.  */
2721               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2722                   == SIGN_EXTEND)
2723                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2724                                                     SUBREG_REG (*split)));
2725               else
2726 #endif
2727                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2728                                                     SUBREG_REG (*split)));
2729             }
2730 #endif
2731
2732           /* Attempt to split binary operators using arithmetic identities.  */
2733           if (BINARY_P (SET_SRC (newpat))
2734               && split_mode == GET_MODE (SET_SRC (newpat))
2735               && ! side_effects_p (SET_SRC (newpat)))
2736             {
2737               rtx setsrc = SET_SRC (newpat);
2738               enum machine_mode mode = GET_MODE (setsrc);
2739               enum rtx_code code = GET_CODE (setsrc);
2740               rtx src_op0 = XEXP (setsrc, 0);
2741               rtx src_op1 = XEXP (setsrc, 1);
2742
2743               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2744               if (rtx_equal_p (src_op0, src_op1))
2745                 {
2746                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2747                   SUBST (XEXP (setsrc, 0), newdest);
2748                   SUBST (XEXP (setsrc, 1), newdest);
2749                   subst_done = true;
2750                 }
2751               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2752               else if ((code == PLUS || code == MULT)
2753                        && GET_CODE (src_op0) == code
2754                        && GET_CODE (XEXP (src_op0, 0)) == code
2755                        && (INTEGRAL_MODE_P (mode)
2756                            || (FLOAT_MODE_P (mode)
2757                                && flag_unsafe_math_optimizations)))
2758                 {
2759                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2760                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2761                   rtx r = XEXP (src_op0, 1);
2762                   rtx s = src_op1;
2763
2764                   /* Split both "((X op Y) op X) op Y" and
2765                      "((X op Y) op Y) op X" as "T op T" where T is
2766                      "X op Y".  */
2767                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2768                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2769                     {
2770                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2771                                               XEXP (src_op0, 0));
2772                       SUBST (XEXP (setsrc, 0), newdest);
2773                       SUBST (XEXP (setsrc, 1), newdest);
2774                       subst_done = true;
2775                     }
2776                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2777                      T is "X op Y".  */
2778                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2779                     {
2780                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2781                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2782                       SUBST (XEXP (setsrc, 0), newdest);
2783                       SUBST (XEXP (setsrc, 1), newdest);
2784                       subst_done = true;
2785                     }
2786                 }
2787             }
2788
2789           if (!subst_done)
2790             {
2791               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2792               SUBST (*split, newdest);
2793             }
2794
2795           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2796
2797           /* recog_for_combine might have added CLOBBERs to newi2pat.
2798              Make sure NEWPAT does not depend on the clobbered regs.  */
2799           if (GET_CODE (newi2pat) == PARALLEL)
2800             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2801               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2802                 {
2803                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2804                   if (reg_overlap_mentioned_p (reg, newpat))
2805                     {
2806                       undo_all ();
2807                       return 0;
2808                     }
2809                 }
2810
2811           /* If the split point was a MULT and we didn't have one before,
2812              don't use one now.  */
2813           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2814             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2815         }
2816     }
2817
2818   /* Check for a case where we loaded from memory in a narrow mode and
2819      then sign extended it, but we need both registers.  In that case,
2820      we have a PARALLEL with both loads from the same memory location.
2821      We can split this into a load from memory followed by a register-register
2822      copy.  This saves at least one insn, more if register allocation can
2823      eliminate the copy.
2824
2825      We cannot do this if the destination of the first assignment is a
2826      condition code register or cc0.  We eliminate this case by making sure
2827      the SET_DEST and SET_SRC have the same mode.
2828
2829      We cannot do this if the destination of the second assignment is
2830      a register that we have already assumed is zero-extended.  Similarly
2831      for a SUBREG of such a register.  */
2832
2833   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2834            && GET_CODE (newpat) == PARALLEL
2835            && XVECLEN (newpat, 0) == 2
2836            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2837            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2838            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2839                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2840            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2841            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2842                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2843            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2844                                    INSN_CUID (i2))
2845            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2846            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2847            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2848                  (REG_P (temp)
2849                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2850                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2851                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2852                   && (reg_stat[REGNO (temp)].nonzero_bits
2853                       != GET_MODE_MASK (word_mode))))
2854            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2855                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2856                      (REG_P (temp)
2857                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2858                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2859                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2860                       && (reg_stat[REGNO (temp)].nonzero_bits
2861                           != GET_MODE_MASK (word_mode)))))
2862            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2863                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2864            && ! find_reg_note (i3, REG_UNUSED,
2865                                SET_DEST (XVECEXP (newpat, 0, 0))))
2866     {
2867       rtx ni2dest;
2868
2869       newi2pat = XVECEXP (newpat, 0, 0);
2870       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2871       newpat = XVECEXP (newpat, 0, 1);
2872       SUBST (SET_SRC (newpat),
2873              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2874       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2875
2876       if (i2_code_number >= 0)
2877         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2878
2879       if (insn_code_number >= 0)
2880         swap_i2i3 = 1;
2881     }
2882
2883   /* Similarly, check for a case where we have a PARALLEL of two independent
2884      SETs but we started with three insns.  In this case, we can do the sets
2885      as two separate insns.  This case occurs when some SET allows two
2886      other insns to combine, but the destination of that SET is still live.  */
2887
2888   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2889            && GET_CODE (newpat) == PARALLEL
2890            && XVECLEN (newpat, 0) == 2
2891            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2892            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2893            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2894            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2895            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2896            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2897            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2898                                    INSN_CUID (i2))
2899            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2900            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2901            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2902            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2903                                   XVECEXP (newpat, 0, 0))
2904            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2905                                   XVECEXP (newpat, 0, 1))
2906            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2907                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2908     {
2909       /* Normally, it doesn't matter which of the two is done first,
2910          but it does if one references cc0.  In that case, it has to
2911          be first.  */
2912 #ifdef HAVE_cc0
2913       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2914         {
2915           newi2pat = XVECEXP (newpat, 0, 0);
2916           newpat = XVECEXP (newpat, 0, 1);
2917         }
2918       else
2919 #endif
2920         {
2921           newi2pat = XVECEXP (newpat, 0, 1);
2922           newpat = XVECEXP (newpat, 0, 0);
2923         }
2924
2925       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2926
2927       if (i2_code_number >= 0)
2928         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2929     }
2930
2931   /* If it still isn't recognized, fail and change things back the way they
2932      were.  */
2933   if ((insn_code_number < 0
2934        /* Is the result a reasonable ASM_OPERANDS?  */
2935        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2936     {
2937       undo_all ();
2938       return 0;
2939     }
2940
2941   /* If we had to change another insn, make sure it is valid also.  */
2942   if (undobuf.other_insn)
2943     {
2944       rtx other_pat = PATTERN (undobuf.other_insn);
2945       rtx new_other_notes;
2946       rtx note, next;
2947
2948       CLEAR_HARD_REG_SET (newpat_used_regs);
2949
2950       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2951                                              &new_other_notes);
2952
2953       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2954         {
2955           undo_all ();
2956           return 0;
2957         }
2958
2959       PATTERN (undobuf.other_insn) = other_pat;
2960
2961       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2962          are still valid.  Then add any non-duplicate notes added by
2963          recog_for_combine.  */
2964       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2965         {
2966           next = XEXP (note, 1);
2967
2968           if (REG_NOTE_KIND (note) == REG_UNUSED
2969               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2970             {
2971               if (REG_P (XEXP (note, 0)))
2972                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2973
2974               remove_note (undobuf.other_insn, note);
2975             }
2976         }
2977
2978       for (note = new_other_notes; note; note = XEXP (note, 1))
2979         if (REG_P (XEXP (note, 0)))
2980           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2981
2982       distribute_notes (new_other_notes, undobuf.other_insn,
2983                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2984     }
2985 #ifdef HAVE_cc0
2986   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2987      they are adjacent to each other or not.  */
2988   {
2989     rtx p = prev_nonnote_insn (i3);
2990     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2991         && sets_cc0_p (newi2pat))
2992       {
2993         undo_all ();
2994         return 0;
2995       }
2996   }
2997 #endif
2998
2999   /* Only allow this combination if insn_rtx_costs reports that the
3000      replacement instructions are cheaper than the originals.  */
3001   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3002     {
3003       undo_all ();
3004       return 0;
3005     }
3006
3007   /* We now know that we can do this combination.  Merge the insns and
3008      update the status of registers and LOG_LINKS.  */
3009
3010   if (swap_i2i3)
3011     {
3012       rtx insn;
3013       rtx link;
3014       rtx ni2dest;
3015
3016       /* I3 now uses what used to be its destination and which is now
3017          I2's destination.  This requires us to do a few adjustments.  */
3018       PATTERN (i3) = newpat;
3019       adjust_for_new_dest (i3);
3020
3021       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3022          so we still will.
3023
3024          However, some later insn might be using I2's dest and have
3025          a LOG_LINK pointing at I3.  We must remove this link.
3026          The simplest way to remove the link is to point it at I1,
3027          which we know will be a NOTE.  */
3028
3029       /* newi2pat is usually a SET here; however, recog_for_combine might
3030          have added some clobbers.  */
3031       if (GET_CODE (newi2pat) == PARALLEL)
3032         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3033       else
3034         ni2dest = SET_DEST (newi2pat);
3035
3036       for (insn = NEXT_INSN (i3);
3037            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3038                     || insn != BB_HEAD (this_basic_block->next_bb));
3039            insn = NEXT_INSN (insn))
3040         {
3041           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3042             {
3043               for (link = LOG_LINKS (insn); link;
3044                    link = XEXP (link, 1))
3045                 if (XEXP (link, 0) == i3)
3046                   XEXP (link, 0) = i1;
3047
3048               break;
3049             }
3050         }
3051     }
3052
3053   {
3054     rtx i3notes, i2notes, i1notes = 0;
3055     rtx i3links, i2links, i1links = 0;
3056     rtx midnotes = 0;
3057     unsigned int regno;
3058     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3059        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3060        same as i3dest, in which case newi2pat may be setting i1dest.  */
3061     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3062                    || i2dest_in_i2src || i2dest_in_i1src
3063                    || !i2dest_killed
3064                    ? 0 : i2dest);
3065     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3066                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3067                    || !i1dest_killed
3068                    ? 0 : i1dest);
3069
3070     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3071        clear them.  */
3072     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3073     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3074     if (i1)
3075       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3076
3077     /* Ensure that we do not have something that should not be shared but
3078        occurs multiple times in the new insns.  Check this by first
3079        resetting all the `used' flags and then copying anything is shared.  */
3080
3081     reset_used_flags (i3notes);
3082     reset_used_flags (i2notes);
3083     reset_used_flags (i1notes);
3084     reset_used_flags (newpat);
3085     reset_used_flags (newi2pat);
3086     if (undobuf.other_insn)
3087       reset_used_flags (PATTERN (undobuf.other_insn));
3088
3089     i3notes = copy_rtx_if_shared (i3notes);
3090     i2notes = copy_rtx_if_shared (i2notes);
3091     i1notes = copy_rtx_if_shared (i1notes);
3092     newpat = copy_rtx_if_shared (newpat);
3093     newi2pat = copy_rtx_if_shared (newi2pat);
3094     if (undobuf.other_insn)
3095       reset_used_flags (PATTERN (undobuf.other_insn));
3096
3097     INSN_CODE (i3) = insn_code_number;
3098     PATTERN (i3) = newpat;
3099
3100     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3101       {
3102         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3103
3104         reset_used_flags (call_usage);
3105         call_usage = copy_rtx (call_usage);
3106
3107         if (substed_i2)
3108           replace_rtx (call_usage, i2dest, i2src);
3109
3110         if (substed_i1)
3111           replace_rtx (call_usage, i1dest, i1src);
3112
3113         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3114       }
3115
3116     if (undobuf.other_insn)
3117       INSN_CODE (undobuf.other_insn) = other_code_number;
3118
3119     /* We had one special case above where I2 had more than one set and
3120        we replaced a destination of one of those sets with the destination
3121        of I3.  In that case, we have to update LOG_LINKS of insns later
3122        in this basic block.  Note that this (expensive) case is rare.
3123
3124        Also, in this case, we must pretend that all REG_NOTEs for I2
3125        actually came from I3, so that REG_UNUSED notes from I2 will be
3126        properly handled.  */
3127
3128     if (i3_subst_into_i2)
3129       {
3130         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3131           if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
3132               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3133               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3134               && ! find_reg_note (i2, REG_UNUSED,
3135                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3136             for (temp = NEXT_INSN (i2);
3137                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3138                           || BB_HEAD (this_basic_block) != temp);
3139                  temp = NEXT_INSN (temp))
3140               if (temp != i3 && INSN_P (temp))
3141                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3142                   if (XEXP (link, 0) == i2)
3143                     XEXP (link, 0) = i3;
3144
3145         if (i3notes)
3146           {
3147             rtx link = i3notes;
3148             while (XEXP (link, 1))
3149               link = XEXP (link, 1);
3150             XEXP (link, 1) = i2notes;
3151           }
3152         else
3153           i3notes = i2notes;
3154         i2notes = 0;
3155       }
3156
3157     LOG_LINKS (i3) = 0;
3158     REG_NOTES (i3) = 0;
3159     LOG_LINKS (i2) = 0;
3160     REG_NOTES (i2) = 0;
3161
3162     if (newi2pat)
3163       {
3164         INSN_CODE (i2) = i2_code_number;
3165         PATTERN (i2) = newi2pat;
3166       }
3167     else
3168       SET_INSN_DELETED (i2);
3169
3170     if (i1)
3171       {
3172         LOG_LINKS (i1) = 0;
3173         REG_NOTES (i1) = 0;
3174         SET_INSN_DELETED (i1);
3175       }
3176
3177     /* Get death notes for everything that is now used in either I3 or
3178        I2 and used to die in a previous insn.  If we built two new
3179        patterns, move from I1 to I2 then I2 to I3 so that we get the
3180        proper movement on registers that I2 modifies.  */
3181
3182     if (newi2pat)
3183       {
3184         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3185         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3186       }
3187     else
3188       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3189                    i3, &midnotes);
3190
3191     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3192     if (i3notes)
3193       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3194                         elim_i2, elim_i1);
3195     if (i2notes)
3196       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3197                         elim_i2, elim_i1);
3198     if (i1notes)
3199       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3200                         elim_i2, elim_i1);
3201     if (midnotes)
3202       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3203                         elim_i2, elim_i1);
3204
3205     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3206        know these are REG_UNUSED and want them to go to the desired insn,
3207        so we always pass it as i3.  We have not counted the notes in
3208        reg_n_deaths yet, so we need to do so now.  */
3209
3210     if (newi2pat && new_i2_notes)
3211       {
3212         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3213           if (REG_P (XEXP (temp, 0)))
3214             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3215
3216         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3217       }
3218
3219     if (new_i3_notes)
3220       {
3221         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3222           if (REG_P (XEXP (temp, 0)))
3223             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3224
3225         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3226       }
3227
3228     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3229        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3230        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3231        in that case, it might delete I2.  Similarly for I2 and I1.
3232        Show an additional death due to the REG_DEAD note we make here.  If
3233        we discard it in distribute_notes, we will decrement it again.  */
3234
3235     if (i3dest_killed)
3236       {
3237         if (REG_P (i3dest_killed))
3238           REG_N_DEATHS (REGNO (i3dest_killed))++;
3239
3240         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3241           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3242                                                NULL_RTX),
3243                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3244         else
3245           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3246                                                NULL_RTX),
3247                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3248                             elim_i2, elim_i1);
3249       }
3250
3251     if (i2dest_in_i2src)
3252       {
3253         if (REG_P (i2dest))
3254           REG_N_DEATHS (REGNO (i2dest))++;
3255
3256         if (newi2pat && reg_set_p (i2dest, newi2pat))
3257           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3258                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3259         else
3260           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3261                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3262                             NULL_RTX, NULL_RTX);
3263       }
3264
3265     if (i1dest_in_i1src)
3266       {
3267         if (REG_P (i1dest))
3268           REG_N_DEATHS (REGNO (i1dest))++;
3269
3270         if (newi2pat && reg_set_p (i1dest, newi2pat))
3271           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3272                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3273         else
3274           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3275                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3276                             NULL_RTX, NULL_RTX);
3277       }
3278
3279     distribute_links (i3links);
3280     distribute_links (i2links);
3281     distribute_links (i1links);
3282
3283     if (REG_P (i2dest))
3284       {
3285         rtx link;
3286         rtx i2_insn = 0, i2_val = 0, set;
3287
3288         /* The insn that used to set this register doesn't exist, and
3289            this life of the register may not exist either.  See if one of
3290            I3's links points to an insn that sets I2DEST.  If it does,
3291            that is now the last known value for I2DEST. If we don't update
3292            this and I2 set the register to a value that depended on its old
3293            contents, we will get confused.  If this insn is used, thing
3294            will be set correctly in combine_instructions.  */
3295
3296         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3297           if ((set = single_set (XEXP (link, 0))) != 0
3298               && rtx_equal_p (i2dest, SET_DEST (set)))
3299             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3300
3301         record_value_for_reg (i2dest, i2_insn, i2_val);
3302
3303         /* If the reg formerly set in I2 died only once and that was in I3,
3304            zero its use count so it won't make `reload' do any work.  */
3305         if (! added_sets_2
3306             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3307             && ! i2dest_in_i2src)
3308           {
3309             regno = REGNO (i2dest);
3310             REG_N_SETS (regno)--;
3311           }
3312       }
3313
3314     if (i1 && REG_P (i1dest))
3315       {
3316         rtx link;
3317         rtx i1_insn = 0, i1_val = 0, set;
3318
3319         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3320           if ((set = single_set (XEXP (link, 0))) != 0
3321               && rtx_equal_p (i1dest, SET_DEST (set)))
3322             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3323
3324         record_value_for_reg (i1dest, i1_insn, i1_val);
3325
3326         regno = REGNO (i1dest);
3327         if (! added_sets_1 && ! i1dest_in_i1src)
3328           REG_N_SETS (regno)--;
3329       }
3330
3331     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3332        been made to this insn.  The order of
3333        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3334        can affect nonzero_bits of newpat */
3335     if (newi2pat)
3336       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3337     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3338
3339     /* Set new_direct_jump_p if a new return or simple jump instruction
3340        has been created.
3341
3342        If I3 is now an unconditional jump, ensure that it has a
3343        BARRIER following it since it may have initially been a
3344        conditional jump.  It may also be the last nonnote insn.  */
3345
3346     if (returnjump_p (i3) || any_uncondjump_p (i3))
3347       {
3348         *new_direct_jump_p = 1;
3349         mark_jump_label (PATTERN (i3), i3, 0);
3350
3351         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3352             || !BARRIER_P (temp))
3353           emit_barrier_after (i3);
3354       }
3355
3356     if (undobuf.other_insn != NULL_RTX
3357         && (returnjump_p (undobuf.other_insn)
3358             || any_uncondjump_p (undobuf.other_insn)))
3359       {
3360         *new_direct_jump_p = 1;
3361
3362         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3363             || !BARRIER_P (temp))
3364           emit_barrier_after (undobuf.other_insn);
3365       }
3366
3367     /* An NOOP jump does not need barrier, but it does need cleaning up
3368        of CFG.  */
3369     if (GET_CODE (newpat) == SET
3370         && SET_SRC (newpat) == pc_rtx
3371         && SET_DEST (newpat) == pc_rtx)
3372       *new_direct_jump_p = 1;
3373   }
3374
3375   combine_successes++;
3376   undo_commit ();
3377
3378   if (added_links_insn
3379       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3380       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3381     return added_links_insn;
3382   else
3383     return newi2pat ? i2 : i3;
3384 }
3385 \f
3386 /* Undo all the modifications recorded in undobuf.  */
3387
3388 static void
3389 undo_all (void)
3390 {
3391   struct undo *undo, *next;
3392
3393   for (undo = undobuf.undos; undo; undo = next)
3394     {
3395       next = undo->next;
3396       switch (undo->kind)
3397         {
3398         case UNDO_RTX:
3399           *undo->where.r = undo->old_contents.r;
3400           break;
3401         case UNDO_INT:
3402           *undo->where.i = undo->old_contents.i;
3403           break;
3404         case UNDO_MODE:
3405           PUT_MODE (*undo->where.r, undo->old_contents.m);
3406           break;
3407         default:
3408           gcc_unreachable ();
3409         }
3410
3411       undo->next = undobuf.frees;
3412       undobuf.frees = undo;
3413     }
3414
3415   undobuf.undos = 0;
3416 }
3417
3418 /* We've committed to accepting the changes we made.  Move all
3419    of the undos to the free list.  */
3420
3421 static void
3422 undo_commit (void)
3423 {
3424   struct undo *undo, *next;
3425
3426   for (undo = undobuf.undos; undo; undo = next)
3427     {
3428       next = undo->next;
3429       undo->next = undobuf.frees;
3430       undobuf.frees = undo;
3431     }
3432   undobuf.undos = 0;
3433 }
3434
3435 \f
3436 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3437    where we have an arithmetic expression and return that point.  LOC will
3438    be inside INSN.
3439
3440    try_combine will call this function to see if an insn can be split into
3441    two insns.  */
3442
3443 static rtx *
3444 find_split_point (rtx *loc, rtx insn)
3445 {
3446   rtx x = *loc;
3447   enum rtx_code code = GET_CODE (x);
3448   rtx *split;
3449   unsigned HOST_WIDE_INT len = 0;
3450   HOST_WIDE_INT pos = 0;
3451   int unsignedp = 0;
3452   rtx inner = NULL_RTX;
3453
3454   /* First special-case some codes.  */
3455   switch (code)
3456     {
3457     case SUBREG:
3458 #ifdef INSN_SCHEDULING
3459       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3460          point.  */
3461       if (MEM_P (SUBREG_REG (x)))
3462         return loc;
3463 #endif
3464       return find_split_point (&SUBREG_REG (x), insn);
3465
3466     case MEM:
3467 #ifdef HAVE_lo_sum
3468       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3469          using LO_SUM and HIGH.  */
3470       if (GET_CODE (XEXP (x, 0)) == CONST
3471           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3472         {
3473           SUBST (XEXP (x, 0),
3474                  gen_rtx_LO_SUM (Pmode,
3475                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3476                                  XEXP (x, 0)));
3477           return &XEXP (XEXP (x, 0), 0);
3478         }
3479 #endif
3480
3481       /* If we have a PLUS whose second operand is a constant and the
3482          address is not valid, perhaps will can split it up using
3483          the machine-specific way to split large constants.  We use
3484          the first pseudo-reg (one of the virtual regs) as a placeholder;
3485          it will not remain in the result.  */
3486       if (GET_CODE (XEXP (x, 0)) == PLUS
3487           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3488           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3489         {
3490           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3491           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3492                                  subst_insn);
3493
3494           /* This should have produced two insns, each of which sets our
3495              placeholder.  If the source of the second is a valid address,
3496              we can make put both sources together and make a split point
3497              in the middle.  */
3498
3499           if (seq
3500               && NEXT_INSN (seq) != NULL_RTX
3501               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3502               && NONJUMP_INSN_P (seq)
3503               && GET_CODE (PATTERN (seq)) == SET
3504               && SET_DEST (PATTERN (seq)) == reg
3505               && ! reg_mentioned_p (reg,
3506                                     SET_SRC (PATTERN (seq)))
3507               && NONJUMP_INSN_P (NEXT_INSN (seq))
3508               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3509               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3510               && memory_address_p (GET_MODE (x),
3511                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3512             {
3513               rtx src1 = SET_SRC (PATTERN (seq));
3514               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3515
3516               /* Replace the placeholder in SRC2 with SRC1.  If we can
3517                  find where in SRC2 it was placed, that can become our
3518                  split point and we can replace this address with SRC2.
3519                  Just try two obvious places.  */
3520
3521               src2 = replace_rtx (src2, reg, src1);
3522               split = 0;
3523               if (XEXP (src2, 0) == src1)
3524                 split = &XEXP (src2, 0);
3525               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3526                        && XEXP (XEXP (src2, 0), 0) == src1)
3527                 split = &XEXP (XEXP (src2, 0), 0);
3528
3529               if (split)
3530                 {
3531                   SUBST (XEXP (x, 0), src2);
3532                   return split;
3533                 }
3534             }
3535
3536           /* If that didn't work, perhaps the first operand is complex and
3537              needs to be computed separately, so make a split point there.
3538              This will occur on machines that just support REG + CONST
3539              and have a constant moved through some previous computation.  */
3540
3541           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3542                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3543                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3544             return &XEXP (XEXP (x, 0), 0);
3545         }
3546       break;
3547
3548     case SET:
3549 #ifdef HAVE_cc0
3550       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3551          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3552          we need to put the operand into a register.  So split at that
3553          point.  */
3554
3555       if (SET_DEST (x) == cc0_rtx
3556           && GET_CODE (SET_SRC (x)) != COMPARE
3557           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3558           && !OBJECT_P (SET_SRC (x))
3559           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3560                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3561         return &SET_SRC (x);
3562 #endif
3563
3564       /* See if we can split SET_SRC as it stands.  */
3565       split = find_split_point (&SET_SRC (x), insn);
3566       if (split && split != &SET_SRC (x))
3567         return split;
3568
3569       /* See if we can split SET_DEST as it stands.  */
3570       split = find_split_point (&SET_DEST (x), insn);
3571       if (split && split != &SET_DEST (x))
3572         return split;
3573
3574       /* See if this is a bitfield assignment with everything constant.  If
3575          so, this is an IOR of an AND, so split it into that.  */
3576       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3577           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3578               <= HOST_BITS_PER_WIDE_INT)
3579           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3580           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3581           && GET_CODE (SET_SRC (x)) == CONST_INT
3582           && ((INTVAL (XEXP (SET_DEST (x), 1))
3583                + INTVAL (XEXP (SET_DEST (x), 2)))
3584               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3585           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3586         {
3587           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3588           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3589           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3590           rtx dest = XEXP (SET_DEST (x), 0);
3591           enum machine_mode mode = GET_MODE (dest);
3592           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3593           rtx or_mask;
3594
3595           if (BITS_BIG_ENDIAN)
3596             pos = GET_MODE_BITSIZE (mode) - len - pos;
3597
3598           or_mask = gen_int_mode (src << pos, mode);
3599           if (src == mask)
3600             SUBST (SET_SRC (x),
3601                    simplify_gen_binary (IOR, mode, dest, or_mask));
3602           else
3603             {
3604               rtx negmask = gen_int_mode (~(mask << pos), mode);
3605               SUBST (SET_SRC (x),
3606                      simplify_gen_binary (IOR, mode,
3607                                           simplify_gen_binary (AND, mode,
3608                                                                dest, negmask),
3609                                           or_mask));
3610             }
3611
3612           SUBST (SET_DEST (x), dest);
3613
3614           split = find_split_point (&SET_SRC (x), insn);
3615           if (split && split != &SET_SRC (x))
3616             return split;
3617         }
3618
3619       /* Otherwise, see if this is an operation that we can split into two.
3620          If so, try to split that.  */
3621       code = GET_CODE (SET_SRC (x));
3622
3623       switch (code)
3624         {
3625         case AND:
3626           /* If we are AND'ing with a large constant that is only a single
3627              bit and the result is only being used in a context where we
3628              need to know if it is zero or nonzero, replace it with a bit
3629              extraction.  This will avoid the large constant, which might
3630              have taken more than one insn to make.  If the constant were
3631              not a valid argument to the AND but took only one insn to make,
3632              this is no worse, but if it took more than one insn, it will
3633              be better.  */
3634
3635           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3636               && REG_P (XEXP (SET_SRC (x), 0))
3637               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3638               && REG_P (SET_DEST (x))
3639               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3640               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3641               && XEXP (*split, 0) == SET_DEST (x)
3642               && XEXP (*split, 1) == const0_rtx)
3643             {
3644               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3645                                                 XEXP (SET_SRC (x), 0),
3646                                                 pos, NULL_RTX, 1, 1, 0, 0);
3647               if (extraction != 0)
3648                 {
3649                   SUBST (SET_SRC (x), extraction);
3650                   return find_split_point (loc, insn);
3651                 }
3652             }
3653           break;
3654
3655         case NE:
3656           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3657              is known to be on, this can be converted into a NEG of a shift.  */
3658           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3659               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3660               && 1 <= (pos = exact_log2
3661                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3662                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3663             {
3664               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3665
3666               SUBST (SET_SRC (x),
3667                      gen_rtx_NEG (mode,
3668                                   gen_rtx_LSHIFTRT (mode,
3669                                                     XEXP (SET_SRC (x), 0),
3670                                                     GEN_INT (pos))));
3671
3672               split = find_split_point (&SET_SRC (x), insn);
3673               if (split && split != &SET_SRC (x))
3674                 return split;
3675             }
3676           break;
3677
3678         case SIGN_EXTEND:
3679           inner = XEXP (SET_SRC (x), 0);
3680
3681           /* We can't optimize if either mode is a partial integer
3682              mode as we don't know how many bits are significant
3683              in those modes.  */
3684           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3685               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3686             break;
3687
3688           pos = 0;
3689           len = GET_MODE_BITSIZE (GET_MODE (inner));
3690           unsignedp = 0;
3691           break;
3692
3693         case SIGN_EXTRACT:
3694         case ZERO_EXTRACT:
3695           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3696               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3697             {
3698               inner = XEXP (SET_SRC (x), 0);
3699               len = INTVAL (XEXP (SET_SRC (x), 1));
3700               pos = INTVAL (XEXP (SET_SRC (x), 2));
3701
3702               if (BITS_BIG_ENDIAN)
3703                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3704               unsignedp = (code == ZERO_EXTRACT);
3705             }
3706           break;
3707
3708         default:
3709           break;
3710         }
3711
3712       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3713         {
3714           enum machine_mode mode = GET_MODE (SET_SRC (x));
3715
3716           /* For unsigned, we have a choice of a shift followed by an
3717              AND or two shifts.  Use two shifts for field sizes where the
3718              constant might be too large.  We assume here that we can
3719              always at least get 8-bit constants in an AND insn, which is
3720              true for every current RISC.  */
3721
3722           if (unsignedp && len <= 8)
3723             {
3724               SUBST (SET_SRC (x),
3725                      gen_rtx_AND (mode,
3726                                   gen_rtx_LSHIFTRT
3727                                   (mode, gen_lowpart (mode, inner),
3728                                    GEN_INT (pos)),
3729                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3730
3731               split = find_split_point (&SET_SRC (x), insn);
3732               if (split && split != &SET_SRC (x))
3733                 return split;
3734             }
3735           else
3736             {
3737               SUBST (SET_SRC (x),
3738                      gen_rtx_fmt_ee
3739                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3740                       gen_rtx_ASHIFT (mode,
3741                                       gen_lowpart (mode, inner),
3742                                       GEN_INT (GET_MODE_BITSIZE (mode)
3743                                                - len - pos)),
3744                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3745
3746               split = find_split_point (&SET_SRC (x), insn);
3747               if (split && split != &SET_SRC (x))
3748                 return split;
3749             }
3750         }
3751
3752       /* See if this is a simple operation with a constant as the second
3753          operand.  It might be that this constant is out of range and hence
3754          could be used as a split point.  */
3755       if (BINARY_P (SET_SRC (x))
3756           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3757           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3758               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3759                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3760         return &XEXP (SET_SRC (x), 1);
3761
3762       /* Finally, see if this is a simple operation with its first operand
3763          not in a register.  The operation might require this operand in a
3764          register, so return it as a split point.  We can always do this
3765          because if the first operand were another operation, we would have
3766          already found it as a split point.  */
3767       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3768           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3769         return &XEXP (SET_SRC (x), 0);
3770
3771       return 0;
3772
3773     case AND:
3774     case IOR:
3775       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3776          it is better to write this as (not (ior A B)) so we can split it.
3777          Similarly for IOR.  */
3778       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3779         {
3780           SUBST (*loc,
3781                  gen_rtx_NOT (GET_MODE (x),
3782                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3783                                               GET_MODE (x),
3784                                               XEXP (XEXP (x, 0), 0),
3785                                               XEXP (XEXP (x, 1), 0))));
3786           return find_split_point (loc, insn);
3787         }
3788
3789       /* Many RISC machines have a large set of logical insns.  If the
3790          second operand is a NOT, put it first so we will try to split the
3791          other operand first.  */
3792       if (GET_CODE (XEXP (x, 1)) == NOT)
3793         {
3794           rtx tem = XEXP (x, 0);
3795           SUBST (XEXP (x, 0), XEXP (x, 1));
3796           SUBST (XEXP (x, 1), tem);
3797         }
3798       break;
3799
3800     default:
3801       break;
3802     }
3803
3804   /* Otherwise, select our actions depending on our rtx class.  */
3805   switch (GET_RTX_CLASS (code))
3806     {
3807     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3808     case RTX_TERNARY:
3809       split = find_split_point (&XEXP (x, 2), insn);
3810       if (split)
3811         return split;
3812       /* ... fall through ...  */
3813     case RTX_BIN_ARITH:
3814     case RTX_COMM_ARITH:
3815     case RTX_COMPARE:
3816     case RTX_COMM_COMPARE:
3817       split = find_split_point (&XEXP (x, 1), insn);
3818       if (split)
3819         return split;
3820       /* ... fall through ...  */
3821     case RTX_UNARY:
3822       /* Some machines have (and (shift ...) ...) insns.  If X is not
3823          an AND, but XEXP (X, 0) is, use it as our split point.  */
3824       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3825         return &XEXP (x, 0);
3826
3827       split = find_split_point (&XEXP (x, 0), insn);
3828       if (split)
3829         return split;
3830       return loc;
3831
3832     default:
3833       /* Otherwise, we don't have a split point.  */
3834       return 0;
3835     }
3836 }
3837 \f
3838 /* Throughout X, replace FROM with TO, and return the result.
3839    The result is TO if X is FROM;
3840    otherwise the result is X, but its contents may have been modified.
3841    If they were modified, a record was made in undobuf so that
3842    undo_all will (among other things) return X to its original state.
3843
3844    If the number of changes necessary is too much to record to undo,
3845    the excess changes are not made, so the result is invalid.
3846    The changes already made can still be undone.
3847    undobuf.num_undo is incremented for such changes, so by testing that
3848    the caller can tell whether the result is valid.
3849
3850    `n_occurrences' is incremented each time FROM is replaced.
3851
3852    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3853
3854    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3855    by copying if `n_occurrences' is nonzero.  */
3856
3857 static rtx
3858 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3859 {
3860   enum rtx_code code = GET_CODE (x);
3861   enum machine_mode op0_mode = VOIDmode;
3862   const char *fmt;
3863   int len, i;
3864   rtx new;
3865
3866 /* Two expressions are equal if they are identical copies of a shared
3867    RTX or if they are both registers with the same register number
3868    and mode.  */
3869
3870 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3871   ((X) == (Y)                                           \
3872    || (REG_P (X) && REG_P (Y)   \
3873        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3874
3875   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3876     {
3877       n_occurrences++;
3878       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3879     }
3880
3881   /* If X and FROM are the same register but different modes, they will
3882      not have been seen as equal above.  However, flow.c will make a
3883      LOG_LINKS entry for that case.  If we do nothing, we will try to
3884      rerecognize our original insn and, when it succeeds, we will
3885      delete the feeding insn, which is incorrect.
3886
3887      So force this insn not to match in this (rare) case.  */
3888   if (! in_dest && code == REG && REG_P (from)
3889       && REGNO (x) == REGNO (from))
3890     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3891
3892   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3893      of which may contain things that can be combined.  */
3894   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3895     return x;
3896
3897   /* It is possible to have a subexpression appear twice in the insn.
3898      Suppose that FROM is a register that appears within TO.
3899      Then, after that subexpression has been scanned once by `subst',
3900      the second time it is scanned, TO may be found.  If we were
3901      to scan TO here, we would find FROM within it and create a
3902      self-referent rtl structure which is completely wrong.  */
3903   if (COMBINE_RTX_EQUAL_P (x, to))
3904     return to;
3905
3906   /* Parallel asm_operands need special attention because all of the
3907      inputs are shared across the arms.  Furthermore, unsharing the
3908      rtl results in recognition failures.  Failure to handle this case
3909      specially can result in circular rtl.
3910
3911      Solve this by doing a normal pass across the first entry of the
3912      parallel, and only processing the SET_DESTs of the subsequent
3913      entries.  Ug.  */
3914
3915   if (code == PARALLEL
3916       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3917       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3918     {
3919       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3920
3921       /* If this substitution failed, this whole thing fails.  */
3922       if (GET_CODE (new) == CLOBBER
3923           && XEXP (new, 0) == const0_rtx)
3924         return new;
3925
3926       SUBST (XVECEXP (x, 0, 0), new);
3927
3928       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3929         {
3930           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3931
3932           if (!REG_P (dest)
3933               && GET_CODE (dest) != CC0
3934               && GET_CODE (dest) != PC)
3935             {
3936               new = subst (dest, from, to, 0, unique_copy);
3937
3938               /* If this substitution failed, this whole thing fails.  */
3939               if (GET_CODE (new) == CLOBBER
3940                   && XEXP (new, 0) == const0_rtx)
3941                 return new;
3942
3943               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3944             }
3945         }
3946     }
3947   else
3948     {
3949       len = GET_RTX_LENGTH (code);
3950       fmt = GET_RTX_FORMAT (code);
3951
3952       /* We don't need to process a SET_DEST that is a register, CC0,
3953          or PC, so set up to skip this common case.  All other cases
3954          where we want to suppress replacing something inside a
3955          SET_SRC are handled via the IN_DEST operand.  */
3956       if (code == SET
3957           && (REG_P (SET_DEST (x))
3958               || GET_CODE (SET_DEST (x)) == CC0
3959               || GET_CODE (SET_DEST (x)) == PC))
3960         fmt = "ie";
3961
3962       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3963          constant.  */
3964       if (fmt[0] == 'e')
3965         op0_mode = GET_MODE (XEXP (x, 0));
3966
3967       for (i = 0; i < len; i++)
3968         {
3969           if (fmt[i] == 'E')
3970             {
3971               int j;
3972               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3973                 {
3974                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3975                     {
3976                       new = (unique_copy && n_occurrences
3977                              ? copy_rtx (to) : to);
3978                       n_occurrences++;
3979                     }
3980                   else
3981                     {
3982                       new = subst (XVECEXP (x, i, j), from, to, 0,
3983                                    unique_copy);
3984
3985                       /* If this substitution failed, this whole thing
3986                          fails.  */
3987                       if (GET_CODE (new) == CLOBBER
3988                           && XEXP (new, 0) == const0_rtx)
3989                         return new;
3990                     }
3991
3992                   SUBST (XVECEXP (x, i, j), new);
3993                 }
3994             }
3995           else if (fmt[i] == 'e')
3996             {
3997               /* If this is a register being set, ignore it.  */
3998               new = XEXP (x, i);
3999               if (in_dest
4000                   && i == 0
4001                   && (((code == SUBREG || code == ZERO_EXTRACT)
4002                        && REG_P (new))
4003                       || code == STRICT_LOW_PART))
4004                 ;
4005
4006               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4007                 {
4008                   /* In general, don't install a subreg involving two
4009                      modes not tieable.  It can worsen register
4010                      allocation, and can even make invalid reload
4011                      insns, since the reg inside may need to be copied
4012                      from in the outside mode, and that may be invalid
4013                      if it is an fp reg copied in integer mode.
4014
4015                      We allow two exceptions to this: It is valid if
4016                      it is inside another SUBREG and the mode of that
4017                      SUBREG and the mode of the inside of TO is
4018                      tieable and it is valid if X is a SET that copies
4019                      FROM to CC0.  */
4020
4021                   if (GET_CODE (to) == SUBREG
4022                       && ! MODES_TIEABLE_P (GET_MODE (to),
4023                                             GET_MODE (SUBREG_REG (to)))
4024                       && ! (code == SUBREG
4025                             && MODES_TIEABLE_P (GET_MODE (x),
4026                                                 GET_MODE (SUBREG_REG (to))))
4027 #ifdef HAVE_cc0
4028                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4029 #endif
4030                       )
4031                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4032
4033 #ifdef CANNOT_CHANGE_MODE_CLASS
4034                   if (code == SUBREG
4035                       && REG_P (to)
4036                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4037                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4038                                                    GET_MODE (to),
4039                                                    GET_MODE (x)))
4040                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4041 #endif
4042
4043                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4044                   n_occurrences++;
4045                 }
4046               else
4047                 /* If we are in a SET_DEST, suppress most cases unless we
4048                    have gone inside a MEM, in which case we want to
4049                    simplify the address.  We assume here that things that
4050                    are actually part of the destination have their inner
4051                    parts in the first expression.  This is true for SUBREG,
4052                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4053                    things aside from REG and MEM that should appear in a
4054                    SET_DEST.  */
4055                 new = subst (XEXP (x, i), from, to,
4056                              (((in_dest
4057                                 && (code == SUBREG || code == STRICT_LOW_PART
4058                                     || code == ZERO_EXTRACT))
4059                                || code == SET)
4060                               && i == 0), unique_copy);
4061
4062               /* If we found that we will have to reject this combination,
4063                  indicate that by returning the CLOBBER ourselves, rather than
4064                  an expression containing it.  This will speed things up as
4065                  well as prevent accidents where two CLOBBERs are considered
4066                  to be equal, thus producing an incorrect simplification.  */
4067
4068               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4069                 return new;
4070
4071               if (GET_CODE (x) == SUBREG
4072                   && (GET_CODE (new) == CONST_INT
4073                       || GET_CODE (new) == CONST_DOUBLE))
4074                 {
4075                   enum machine_mode mode = GET_MODE (x);
4076
4077                   x = simplify_subreg (GET_MODE (x), new,
4078                                        GET_MODE (SUBREG_REG (x)),
4079                                        SUBREG_BYTE (x));
4080                   if (! x)
4081                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4082                 }
4083               else if (GET_CODE (new) == CONST_INT
4084                        && GET_CODE (x) == ZERO_EXTEND)
4085                 {
4086                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4087                                                 new, GET_MODE (XEXP (x, 0)));
4088                   gcc_assert (x);
4089                 }
4090               else
4091                 SUBST (XEXP (x, i), new);
4092             }
4093         }
4094     }
4095
4096   /* Try to simplify X.  If the simplification changed the code, it is likely
4097      that further simplification will help, so loop, but limit the number
4098      of repetitions that will be performed.  */
4099
4100   for (i = 0; i < 4; i++)
4101     {
4102       /* If X is sufficiently simple, don't bother trying to do anything
4103          with it.  */
4104       if (code != CONST_INT && code != REG && code != CLOBBER)
4105         x = combine_simplify_rtx (x, op0_mode, in_dest);
4106
4107       if (GET_CODE (x) == code)
4108         break;
4109
4110       code = GET_CODE (x);
4111
4112       /* We no longer know the original mode of operand 0 since we
4113          have changed the form of X)  */
4114       op0_mode = VOIDmode;
4115     }
4116
4117   return x;
4118 }
4119 \f
4120 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4121    outer level; call `subst' to simplify recursively.  Return the new
4122    expression.
4123
4124    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4125    if we are inside a SET_DEST.  */
4126
4127 static rtx
4128 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4129 {
4130   enum rtx_code code = GET_CODE (x);
4131   enum machine_mode mode = GET_MODE (x);
4132   rtx temp;
4133   int i;
4134
4135   /* If this is a commutative operation, put a constant last and a complex
4136      expression first.  We don't need to do this for comparisons here.  */
4137   if (COMMUTATIVE_ARITH_P (x)
4138       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4139     {
4140       temp = XEXP (x, 0);
4141       SUBST (XEXP (x, 0), XEXP (x, 1));
4142       SUBST (XEXP (x, 1), temp);
4143     }
4144
4145   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4146      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4147      things.  Check for cases where both arms are testing the same
4148      condition.
4149
4150      Don't do anything if all operands are very simple.  */
4151
4152   if ((BINARY_P (x)
4153        && ((!OBJECT_P (XEXP (x, 0))
4154             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4155                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4156            || (!OBJECT_P (XEXP (x, 1))
4157                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4158                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4159       || (UNARY_P (x)
4160           && (!OBJECT_P (XEXP (x, 0))
4161                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4162                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4163     {
4164       rtx cond, true_rtx, false_rtx;
4165
4166       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4167       if (cond != 0
4168           /* If everything is a comparison, what we have is highly unlikely
4169              to be simpler, so don't use it.  */
4170           && ! (COMPARISON_P (x)
4171                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4172         {
4173           rtx cop1 = const0_rtx;
4174           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4175
4176           if (cond_code == NE && COMPARISON_P (cond))
4177             return x;
4178
4179           /* Simplify the alternative arms; this may collapse the true and
4180              false arms to store-flag values.  Be careful to use copy_rtx
4181              here since true_rtx or false_rtx might share RTL with x as a
4182              result of the if_then_else_cond call above.  */
4183           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4184           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4185
4186           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4187              is unlikely to be simpler.  */
4188           if (general_operand (true_rtx, VOIDmode)
4189               && general_operand (false_rtx, VOIDmode))
4190             {
4191               enum rtx_code reversed;
4192
4193               /* Restarting if we generate a store-flag expression will cause
4194                  us to loop.  Just drop through in this case.  */
4195
4196               /* If the result values are STORE_FLAG_VALUE and zero, we can
4197                  just make the comparison operation.  */
4198               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4199                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4200                                              cond, cop1);
4201               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4202                        && ((reversed = reversed_comparison_code_parts
4203                                         (cond_code, cond, cop1, NULL))
4204                            != UNKNOWN))
4205                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4206                                              cond, cop1);
4207
4208               /* Likewise, we can make the negate of a comparison operation
4209                  if the result values are - STORE_FLAG_VALUE and zero.  */
4210               else if (GET_CODE (true_rtx) == CONST_INT
4211                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4212                        && false_rtx == const0_rtx)
4213                 x = simplify_gen_unary (NEG, mode,
4214                                         simplify_gen_relational (cond_code,
4215                                                                  mode, VOIDmode,
4216                                                                  cond, cop1),
4217                                         mode);
4218               else if (GET_CODE (false_rtx) == CONST_INT
4219                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4220                        && true_rtx == const0_rtx
4221                        && ((reversed = reversed_comparison_code_parts
4222                                         (cond_code, cond, cop1, NULL))
4223                            != UNKNOWN))
4224                 x = simplify_gen_unary (NEG, mode,
4225                                         simplify_gen_relational (reversed,
4226                                                                  mode, VOIDmode,
4227                                                                  cond, cop1),
4228                                         mode);
4229               else
4230                 return gen_rtx_IF_THEN_ELSE (mode,
4231                                              simplify_gen_relational (cond_code,
4232                                                                       mode,
4233                                                                       VOIDmode,
4234                                                                       cond,
4235                                                                       cop1),
4236                                              true_rtx, false_rtx);
4237
4238               code = GET_CODE (x);
4239               op0_mode = VOIDmode;
4240             }
4241         }
4242     }
4243
4244   /* Try to fold this expression in case we have constants that weren't
4245      present before.  */
4246   temp = 0;
4247   switch (GET_RTX_CLASS (code))
4248     {
4249     case RTX_UNARY:
4250       if (op0_mode == VOIDmode)
4251         op0_mode = GET_MODE (XEXP (x, 0));
4252       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4253       break;
4254     case RTX_COMPARE:
4255     case RTX_COMM_COMPARE:
4256       {
4257         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4258         if (cmp_mode == VOIDmode)
4259           {
4260             cmp_mode = GET_MODE (XEXP (x, 1));
4261             if (cmp_mode == VOIDmode)
4262               cmp_mode = op0_mode;
4263           }
4264         temp = simplify_relational_operation (code, mode, cmp_mode,
4265                                               XEXP (x, 0), XEXP (x, 1));
4266       }
4267       break;
4268     case RTX_COMM_ARITH:
4269     case RTX_BIN_ARITH:
4270       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4271       break;
4272     case RTX_BITFIELD_OPS:
4273     case RTX_TERNARY:
4274       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4275                                          XEXP (x, 1), XEXP (x, 2));
4276       break;
4277     default:
4278       break;
4279     }
4280
4281   if (temp)
4282     {
4283       x = temp;
4284       code = GET_CODE (temp);
4285       op0_mode = VOIDmode;
4286       mode = GET_MODE (temp);
4287     }
4288
4289   /* First see if we can apply the inverse distributive law.  */
4290   if (code == PLUS || code == MINUS
4291       || code == AND || code == IOR || code == XOR)
4292     {
4293       x = apply_distributive_law (x);
4294       code = GET_CODE (x);
4295       op0_mode = VOIDmode;
4296     }
4297
4298   /* If CODE is an associative operation not otherwise handled, see if we
4299      can associate some operands.  This can win if they are constants or
4300      if they are logically related (i.e. (a & b) & a).  */
4301   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4302        || code == AND || code == IOR || code == XOR
4303        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4304       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4305           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4306     {
4307       if (GET_CODE (XEXP (x, 0)) == code)
4308         {
4309           rtx other = XEXP (XEXP (x, 0), 0);
4310           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4311           rtx inner_op1 = XEXP (x, 1);
4312           rtx inner;
4313
4314           /* Make sure we pass the constant operand if any as the second
4315              one if this is a commutative operation.  */
4316           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4317             {
4318               rtx tem = inner_op0;
4319               inner_op0 = inner_op1;
4320               inner_op1 = tem;
4321             }
4322           inner = simplify_binary_operation (code == MINUS ? PLUS
4323                                              : code == DIV ? MULT
4324                                              : code,
4325                                              mode, inner_op0, inner_op1);
4326
4327           /* For commutative operations, try the other pair if that one
4328              didn't simplify.  */
4329           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4330             {
4331               other = XEXP (XEXP (x, 0), 1);
4332               inner = simplify_binary_operation (code, mode,
4333                                                  XEXP (XEXP (x, 0), 0),
4334                                                  XEXP (x, 1));
4335             }
4336
4337           if (inner)
4338             return simplify_gen_binary (code, mode, other, inner);
4339         }
4340     }
4341
4342   /* A little bit of algebraic simplification here.  */
4343   switch (code)
4344     {
4345     case MEM:
4346       /* Ensure that our address has any ASHIFTs converted to MULT in case
4347          address-recognizing predicates are called later.  */
4348       temp = make_compound_operation (XEXP (x, 0), MEM);
4349       SUBST (XEXP (x, 0), temp);
4350       break;
4351
4352     case SUBREG:
4353       if (op0_mode == VOIDmode)
4354         op0_mode = GET_MODE (SUBREG_REG (x));
4355
4356       /* See if this can be moved to simplify_subreg.  */
4357       if (CONSTANT_P (SUBREG_REG (x))
4358           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4359              /* Don't call gen_lowpart if the inner mode
4360                 is VOIDmode and we cannot simplify it, as SUBREG without
4361                 inner mode is invalid.  */
4362           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4363               || gen_lowpart_common (mode, SUBREG_REG (x))))
4364         return gen_lowpart (mode, SUBREG_REG (x));
4365
4366       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4367         break;
4368       {
4369         rtx temp;
4370         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4371                                 SUBREG_BYTE (x));
4372         if (temp)
4373           return temp;
4374       }
4375
4376       /* Don't change the mode of the MEM if that would change the meaning
4377          of the address.  */
4378       if (MEM_P (SUBREG_REG (x))
4379           && (MEM_VOLATILE_P (SUBREG_REG (x))
4380               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4381         return gen_rtx_CLOBBER (mode, const0_rtx);
4382
4383       /* Note that we cannot do any narrowing for non-constants since
4384          we might have been counting on using the fact that some bits were
4385          zero.  We now do this in the SET.  */
4386
4387       break;
4388
4389     case NEG:
4390       temp = expand_compound_operation (XEXP (x, 0));
4391
4392       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4393          replaced by (lshiftrt X C).  This will convert
4394          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4395
4396       if (GET_CODE (temp) == ASHIFTRT
4397           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4398           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4399         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4400                                      INTVAL (XEXP (temp, 1)));
4401
4402       /* If X has only a single bit that might be nonzero, say, bit I, convert
4403          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4404          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4405          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4406          or a SUBREG of one since we'd be making the expression more
4407          complex if it was just a register.  */
4408
4409       if (!REG_P (temp)
4410           && ! (GET_CODE (temp) == SUBREG
4411                 && REG_P (SUBREG_REG (temp)))
4412           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4413         {
4414           rtx temp1 = simplify_shift_const
4415             (NULL_RTX, ASHIFTRT, mode,
4416              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4417                                    GET_MODE_BITSIZE (mode) - 1 - i),
4418              GET_MODE_BITSIZE (mode) - 1 - i);
4419
4420           /* If all we did was surround TEMP with the two shifts, we
4421              haven't improved anything, so don't use it.  Otherwise,
4422              we are better off with TEMP1.  */
4423           if (GET_CODE (temp1) != ASHIFTRT
4424               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4425               || XEXP (XEXP (temp1, 0), 0) != temp)
4426             return temp1;
4427         }
4428       break;
4429
4430     case TRUNCATE:
4431       /* We can't handle truncation to a partial integer mode here
4432          because we don't know the real bitsize of the partial
4433          integer mode.  */
4434       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4435         break;
4436
4437       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4438           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4439                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4440         SUBST (XEXP (x, 0),
4441                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4442                               GET_MODE_MASK (mode), 0));
4443
4444       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4445          whose value is a comparison can be replaced with a subreg if
4446          STORE_FLAG_VALUE permits.  */
4447       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4448           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4449           && (temp = get_last_value (XEXP (x, 0)))
4450           && COMPARISON_P (temp))
4451         return gen_lowpart (mode, XEXP (x, 0));
4452       break;
4453
4454 #ifdef HAVE_cc0
4455     case COMPARE:
4456       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4457          using cc0, in which case we want to leave it as a COMPARE
4458          so we can distinguish it from a register-register-copy.  */
4459       if (XEXP (x, 1) == const0_rtx)
4460         return XEXP (x, 0);
4461
4462       /* x - 0 is the same as x unless x's mode has signed zeros and
4463          allows rounding towards -infinity.  Under those conditions,
4464          0 - 0 is -0.  */
4465       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4466             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4467           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4468         return XEXP (x, 0);
4469       break;
4470 #endif
4471
4472     case CONST:
4473       /* (const (const X)) can become (const X).  Do it this way rather than
4474          returning the inner CONST since CONST can be shared with a
4475          REG_EQUAL note.  */
4476       if (GET_CODE (XEXP (x, 0)) == CONST)
4477         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4478       break;
4479
4480 #ifdef HAVE_lo_sum
4481     case LO_SUM:
4482       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4483          can add in an offset.  find_split_point will split this address up
4484          again if it doesn't match.  */
4485       if (GET_CODE (XEXP (x, 0)) == HIGH
4486           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4487         return XEXP (x, 1);
4488       break;
4489 #endif
4490
4491     case PLUS:
4492       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4493          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4494          bit-field and can be replaced by either a sign_extend or a
4495          sign_extract.  The `and' may be a zero_extend and the two
4496          <c>, -<c> constants may be reversed.  */
4497       if (GET_CODE (XEXP (x, 0)) == XOR
4498           && GET_CODE (XEXP (x, 1)) == CONST_INT
4499           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4500           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4501           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4502               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4503           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4504           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4505                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4506                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4507                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4508               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4509                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4510                       == (unsigned int) i + 1))))
4511         return simplify_shift_const
4512           (NULL_RTX, ASHIFTRT, mode,
4513            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4514                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4515                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4516            GET_MODE_BITSIZE (mode) - (i + 1));
4517
4518       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4519          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4520          the bitsize of the mode - 1.  This allows simplification of
4521          "a = (b & 8) == 0;"  */
4522       if (XEXP (x, 1) == constm1_rtx
4523           && !REG_P (XEXP (x, 0))
4524           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4525                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4526           && nonzero_bits (XEXP (x, 0), mode) == 1)
4527         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4528            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4529                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4530                                  GET_MODE_BITSIZE (mode) - 1),
4531            GET_MODE_BITSIZE (mode) - 1);
4532
4533       /* If we are adding two things that have no bits in common, convert
4534          the addition into an IOR.  This will often be further simplified,
4535          for example in cases like ((a & 1) + (a & 2)), which can
4536          become a & 3.  */
4537
4538       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4539           && (nonzero_bits (XEXP (x, 0), mode)
4540               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4541         {
4542           /* Try to simplify the expression further.  */
4543           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4544           temp = combine_simplify_rtx (tor, mode, in_dest);
4545
4546           /* If we could, great.  If not, do not go ahead with the IOR
4547              replacement, since PLUS appears in many special purpose
4548              address arithmetic instructions.  */
4549           if (GET_CODE (temp) != CLOBBER && temp != tor)
4550             return temp;
4551         }
4552       break;
4553
4554     case MINUS:
4555       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4556          (and <foo> (const_int pow2-1))  */
4557       if (GET_CODE (XEXP (x, 1)) == AND
4558           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4559           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4560           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4561         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4562                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4563       break;
4564
4565     case MULT:
4566       /* If we have (mult (plus A B) C), apply the distributive law and then
4567          the inverse distributive law to see if things simplify.  This
4568          occurs mostly in addresses, often when unrolling loops.  */
4569
4570       if (GET_CODE (XEXP (x, 0)) == PLUS)
4571         {
4572           rtx result = distribute_and_simplify_rtx (x, 0);
4573           if (result)
4574             return result;
4575         }
4576
4577       /* Try simplify a*(b/c) as (a*b)/c.  */
4578       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4579           && GET_CODE (XEXP (x, 0)) == DIV)
4580         {
4581           rtx tem = simplify_binary_operation (MULT, mode,
4582                                                XEXP (XEXP (x, 0), 0),
4583                                                XEXP (x, 1));
4584           if (tem)
4585             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4586         }
4587       break;
4588
4589     case UDIV:
4590       /* If this is a divide by a power of two, treat it as a shift if
4591          its first operand is a shift.  */
4592       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4593           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4594           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4595               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4596               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4597               || GET_CODE (XEXP (x, 0)) == ROTATE
4598               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4599         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4600       break;
4601
4602     case EQ:  case NE:
4603     case GT:  case GTU:  case GE:  case GEU:
4604     case LT:  case LTU:  case LE:  case LEU:
4605     case UNEQ:  case LTGT:
4606     case UNGT:  case UNGE:
4607     case UNLT:  case UNLE:
4608     case UNORDERED: case ORDERED:
4609       /* If the first operand is a condition code, we can't do anything
4610          with it.  */
4611       if (GET_CODE (XEXP (x, 0)) == COMPARE
4612           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4613               && ! CC0_P (XEXP (x, 0))))
4614         {
4615           rtx op0 = XEXP (x, 0);
4616           rtx op1 = XEXP (x, 1);
4617           enum rtx_code new_code;
4618
4619           if (GET_CODE (op0) == COMPARE)
4620             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4621
4622           /* Simplify our comparison, if possible.  */
4623           new_code = simplify_comparison (code, &op0, &op1);
4624
4625           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4626              if only the low-order bit is possibly nonzero in X (such as when
4627              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4628              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4629              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4630              (plus X 1).
4631
4632              Remove any ZERO_EXTRACT we made when thinking this was a
4633              comparison.  It may now be simpler to use, e.g., an AND.  If a
4634              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4635              the call to make_compound_operation in the SET case.  */
4636
4637           if (STORE_FLAG_VALUE == 1
4638               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4639               && op1 == const0_rtx
4640               && mode == GET_MODE (op0)
4641               && nonzero_bits (op0, mode) == 1)
4642             return gen_lowpart (mode,
4643                                 expand_compound_operation (op0));
4644
4645           else if (STORE_FLAG_VALUE == 1
4646                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4647                    && op1 == const0_rtx
4648                    && mode == GET_MODE (op0)
4649                    && (num_sign_bit_copies (op0, mode)
4650                        == GET_MODE_BITSIZE (mode)))
4651             {
4652               op0 = expand_compound_operation (op0);
4653               return simplify_gen_unary (NEG, mode,
4654                                          gen_lowpart (mode, op0),
4655                                          mode);
4656             }
4657
4658           else if (STORE_FLAG_VALUE == 1
4659                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4660                    && op1 == const0_rtx
4661                    && mode == GET_MODE (op0)
4662                    && nonzero_bits (op0, mode) == 1)
4663             {
4664               op0 = expand_compound_operation (op0);
4665               return simplify_gen_binary (XOR, mode,
4666                                           gen_lowpart (mode, op0),
4667                                           const1_rtx);
4668             }
4669
4670           else if (STORE_FLAG_VALUE == 1
4671                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4672                    && op1 == const0_rtx
4673                    && mode == GET_MODE (op0)
4674                    && (num_sign_bit_copies (op0, mode)
4675                        == GET_MODE_BITSIZE (mode)))
4676             {
4677               op0 = expand_compound_operation (op0);
4678               return plus_constant (gen_lowpart (mode, op0), 1);
4679             }
4680
4681           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4682              those above.  */
4683           if (STORE_FLAG_VALUE == -1
4684               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4685               && op1 == const0_rtx
4686               && (num_sign_bit_copies (op0, mode)
4687                   == GET_MODE_BITSIZE (mode)))
4688             return gen_lowpart (mode,
4689                                 expand_compound_operation (op0));
4690
4691           else if (STORE_FLAG_VALUE == -1
4692                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4693                    && op1 == const0_rtx
4694                    && mode == GET_MODE (op0)
4695                    && nonzero_bits (op0, mode) == 1)
4696             {
4697               op0 = expand_compound_operation (op0);
4698               return simplify_gen_unary (NEG, mode,
4699                                          gen_lowpart (mode, op0),
4700                                          mode);
4701             }
4702
4703           else if (STORE_FLAG_VALUE == -1
4704                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4705                    && op1 == const0_rtx
4706                    && mode == GET_MODE (op0)
4707                    && (num_sign_bit_copies (op0, mode)
4708                        == GET_MODE_BITSIZE (mode)))
4709             {
4710               op0 = expand_compound_operation (op0);
4711               return simplify_gen_unary (NOT, mode,
4712                                          gen_lowpart (mode, op0),
4713                                          mode);
4714             }
4715
4716           /* If X is 0/1, (eq X 0) is X-1.  */
4717           else if (STORE_FLAG_VALUE == -1
4718                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4719                    && op1 == const0_rtx
4720                    && mode == GET_MODE (op0)
4721                    && nonzero_bits (op0, mode) == 1)
4722             {
4723               op0 = expand_compound_operation (op0);
4724               return plus_constant (gen_lowpart (mode, op0), -1);
4725             }
4726
4727           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4728              one bit that might be nonzero, we can convert (ne x 0) to
4729              (ashift x c) where C puts the bit in the sign bit.  Remove any
4730              AND with STORE_FLAG_VALUE when we are done, since we are only
4731              going to test the sign bit.  */
4732           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4733               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4734               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4735                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4736               && op1 == const0_rtx
4737               && mode == GET_MODE (op0)
4738               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4739             {
4740               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4741                                         expand_compound_operation (op0),
4742                                         GET_MODE_BITSIZE (mode) - 1 - i);
4743               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4744                 return XEXP (x, 0);
4745               else
4746                 return x;
4747             }
4748
4749           /* If the code changed, return a whole new comparison.  */
4750           if (new_code != code)
4751             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4752
4753           /* Otherwise, keep this operation, but maybe change its operands.
4754              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4755           SUBST (XEXP (x, 0), op0);
4756           SUBST (XEXP (x, 1), op1);
4757         }
4758       break;
4759
4760     case IF_THEN_ELSE:
4761       return simplify_if_then_else (x);
4762
4763     case ZERO_EXTRACT:
4764     case SIGN_EXTRACT:
4765     case ZERO_EXTEND:
4766     case SIGN_EXTEND:
4767       /* If we are processing SET_DEST, we are done.  */
4768       if (in_dest)
4769         return x;
4770
4771       return expand_compound_operation (x);
4772
4773     case SET:
4774       return simplify_set (x);
4775
4776     case AND:
4777     case IOR:
4778       return simplify_logical (x);
4779
4780     case ASHIFT:
4781     case LSHIFTRT:
4782     case ASHIFTRT:
4783     case ROTATE:
4784     case ROTATERT:
4785       /* If this is a shift by a constant amount, simplify it.  */
4786       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4787         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4788                                      INTVAL (XEXP (x, 1)));
4789
4790       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4791         SUBST (XEXP (x, 1),
4792                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4793                               ((HOST_WIDE_INT) 1
4794                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4795                               - 1,
4796                               0));
4797       break;
4798
4799     default:
4800       break;
4801     }
4802
4803   return x;
4804 }
4805 \f
4806 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4807
4808 static rtx
4809 simplify_if_then_else (rtx x)
4810 {
4811   enum machine_mode mode = GET_MODE (x);
4812   rtx cond = XEXP (x, 0);
4813   rtx true_rtx = XEXP (x, 1);
4814   rtx false_rtx = XEXP (x, 2);
4815   enum rtx_code true_code = GET_CODE (cond);
4816   int comparison_p = COMPARISON_P (cond);
4817   rtx temp;
4818   int i;
4819   enum rtx_code false_code;
4820   rtx reversed;
4821
4822   /* Simplify storing of the truth value.  */
4823   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4824     return simplify_gen_relational (true_code, mode, VOIDmode,
4825                                     XEXP (cond, 0), XEXP (cond, 1));
4826
4827   /* Also when the truth value has to be reversed.  */
4828   if (comparison_p
4829       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4830       && (reversed = reversed_comparison (cond, mode)))
4831     return reversed;
4832
4833   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4834      in it is being compared against certain values.  Get the true and false
4835      comparisons and see if that says anything about the value of each arm.  */
4836
4837   if (comparison_p
4838       && ((false_code = reversed_comparison_code (cond, NULL))
4839           != UNKNOWN)
4840       && REG_P (XEXP (cond, 0)))
4841     {
4842       HOST_WIDE_INT nzb;
4843       rtx from = XEXP (cond, 0);
4844       rtx true_val = XEXP (cond, 1);
4845       rtx false_val = true_val;
4846       int swapped = 0;
4847
4848       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4849
4850       if (false_code == EQ)
4851         {
4852           swapped = 1, true_code = EQ, false_code = NE;
4853           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4854         }
4855
4856       /* If we are comparing against zero and the expression being tested has
4857          only a single bit that might be nonzero, that is its value when it is
4858          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4859
4860       if (true_code == EQ && true_val == const0_rtx
4861           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4862         false_code = EQ, false_val = GEN_INT (nzb);
4863       else if (true_code == EQ && true_val == const0_rtx
4864                && (num_sign_bit_copies (from, GET_MODE (from))
4865                    == GET_MODE_BITSIZE (GET_MODE (from))))
4866         false_code = EQ, false_val = constm1_rtx;
4867
4868       /* Now simplify an arm if we know the value of the register in the
4869          branch and it is used in the arm.  Be careful due to the potential
4870          of locally-shared RTL.  */
4871
4872       if (reg_mentioned_p (from, true_rtx))
4873         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4874                                       from, true_val),
4875                       pc_rtx, pc_rtx, 0, 0);
4876       if (reg_mentioned_p (from, false_rtx))
4877         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4878                                    from, false_val),
4879                        pc_rtx, pc_rtx, 0, 0);
4880
4881       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4882       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4883
4884       true_rtx = XEXP (x, 1);
4885       false_rtx = XEXP (x, 2);
4886       true_code = GET_CODE (cond);
4887     }
4888
4889   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4890      reversed, do so to avoid needing two sets of patterns for
4891      subtract-and-branch insns.  Similarly if we have a constant in the true
4892      arm, the false arm is the same as the first operand of the comparison, or
4893      the false arm is more complicated than the true arm.  */
4894
4895   if (comparison_p
4896       && reversed_comparison_code (cond, NULL) != UNKNOWN
4897       && (true_rtx == pc_rtx
4898           || (CONSTANT_P (true_rtx)
4899               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4900           || true_rtx == const0_rtx
4901           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4902           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4903               && !OBJECT_P (false_rtx))
4904           || reg_mentioned_p (true_rtx, false_rtx)
4905           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4906     {
4907       true_code = reversed_comparison_code (cond, NULL);
4908       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4909       SUBST (XEXP (x, 1), false_rtx);
4910       SUBST (XEXP (x, 2), true_rtx);
4911
4912       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4913       cond = XEXP (x, 0);
4914
4915       /* It is possible that the conditional has been simplified out.  */
4916       true_code = GET_CODE (cond);
4917       comparison_p = COMPARISON_P (cond);
4918     }
4919
4920   /* If the two arms are identical, we don't need the comparison.  */
4921
4922   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4923     return true_rtx;
4924
4925   /* Convert a == b ? b : a to "a".  */
4926   if (true_code == EQ && ! side_effects_p (cond)
4927       && !HONOR_NANS (mode)
4928       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4929       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4930     return false_rtx;
4931   else if (true_code == NE && ! side_effects_p (cond)
4932            && !HONOR_NANS (mode)
4933            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4934            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4935     return true_rtx;
4936
4937   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4938
4939   if (GET_MODE_CLASS (mode) == MODE_INT
4940       && GET_CODE (false_rtx) == NEG
4941       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4942       && comparison_p
4943       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4944       && ! side_effects_p (true_rtx))
4945     switch (true_code)
4946       {
4947       case GT:
4948       case GE:
4949         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4950       case LT:
4951       case LE:
4952         return
4953           simplify_gen_unary (NEG, mode,
4954                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4955                               mode);
4956       default:
4957         break;
4958       }
4959
4960   /* Look for MIN or MAX.  */
4961
4962   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4963       && comparison_p
4964       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4965       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4966       && ! side_effects_p (cond))
4967     switch (true_code)
4968       {
4969       case GE:
4970       case GT:
4971         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4972       case LE:
4973       case LT:
4974         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4975       case GEU:
4976       case GTU:
4977         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4978       case LEU:
4979       case LTU:
4980         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4981       default:
4982         break;
4983       }
4984
4985   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4986      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4987      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4988      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4989      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4990      neither 1 or -1, but it isn't worth checking for.  */
4991
4992   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4993       && comparison_p
4994       && GET_MODE_CLASS (mode) == MODE_INT
4995       && ! side_effects_p (x))
4996     {
4997       rtx t = make_compound_operation (true_rtx, SET);
4998       rtx f = make_compound_operation (false_rtx, SET);
4999       rtx cond_op0 = XEXP (cond, 0);
5000       rtx cond_op1 = XEXP (cond, 1);
5001       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5002       enum machine_mode m = mode;
5003       rtx z = 0, c1 = NULL_RTX;
5004
5005       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5006            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5007            || GET_CODE (t) == ASHIFT
5008            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5009           && rtx_equal_p (XEXP (t, 0), f))
5010         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5011
5012       /* If an identity-zero op is commutative, check whether there
5013          would be a match if we swapped the operands.  */
5014       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5015                 || GET_CODE (t) == XOR)
5016                && rtx_equal_p (XEXP (t, 1), f))
5017         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5018       else if (GET_CODE (t) == SIGN_EXTEND
5019                && (GET_CODE (XEXP (t, 0)) == PLUS
5020                    || GET_CODE (XEXP (t, 0)) == MINUS
5021                    || GET_CODE (XEXP (t, 0)) == IOR
5022                    || GET_CODE (XEXP (t, 0)) == XOR
5023                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5024                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5025                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5026                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5027                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5028                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5029                && (num_sign_bit_copies (f, GET_MODE (f))
5030                    > (unsigned int)
5031                      (GET_MODE_BITSIZE (mode)
5032                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5033         {
5034           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5035           extend_op = SIGN_EXTEND;
5036           m = GET_MODE (XEXP (t, 0));
5037         }
5038       else if (GET_CODE (t) == SIGN_EXTEND
5039                && (GET_CODE (XEXP (t, 0)) == PLUS
5040                    || GET_CODE (XEXP (t, 0)) == IOR
5041                    || GET_CODE (XEXP (t, 0)) == XOR)
5042                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5043                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5044                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5045                && (num_sign_bit_copies (f, GET_MODE (f))
5046                    > (unsigned int)
5047                      (GET_MODE_BITSIZE (mode)
5048                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5049         {
5050           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5051           extend_op = SIGN_EXTEND;
5052           m = GET_MODE (XEXP (t, 0));
5053         }
5054       else if (GET_CODE (t) == ZERO_EXTEND
5055                && (GET_CODE (XEXP (t, 0)) == PLUS
5056                    || GET_CODE (XEXP (t, 0)) == MINUS
5057                    || GET_CODE (XEXP (t, 0)) == IOR
5058                    || GET_CODE (XEXP (t, 0)) == XOR
5059                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5060                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5061                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5062                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5063                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5064                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5065                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5066                && ((nonzero_bits (f, GET_MODE (f))
5067                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5068                    == 0))
5069         {
5070           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5071           extend_op = ZERO_EXTEND;
5072           m = GET_MODE (XEXP (t, 0));
5073         }
5074       else if (GET_CODE (t) == ZERO_EXTEND
5075                && (GET_CODE (XEXP (t, 0)) == PLUS
5076                    || GET_CODE (XEXP (t, 0)) == IOR
5077                    || GET_CODE (XEXP (t, 0)) == XOR)
5078                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5079                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5080                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5081                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5082                && ((nonzero_bits (f, GET_MODE (f))
5083                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5084                    == 0))
5085         {
5086           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5087           extend_op = ZERO_EXTEND;
5088           m = GET_MODE (XEXP (t, 0));
5089         }
5090
5091       if (z)
5092         {
5093           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5094                                                  cond_op0, cond_op1),
5095                         pc_rtx, pc_rtx, 0, 0);
5096           temp = simplify_gen_binary (MULT, m, temp,
5097                                       simplify_gen_binary (MULT, m, c1,
5098                                                            const_true_rtx));
5099           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5100           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5101
5102           if (extend_op != UNKNOWN)
5103             temp = simplify_gen_unary (extend_op, mode, temp, m);
5104
5105           return temp;
5106         }
5107     }
5108
5109   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5110      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5111      negation of a single bit, we can convert this operation to a shift.  We
5112      can actually do this more generally, but it doesn't seem worth it.  */
5113
5114   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5115       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5116       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5117            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5118           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5119                == GET_MODE_BITSIZE (mode))
5120               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5121     return
5122       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5123                             gen_lowpart (mode, XEXP (cond, 0)), i);
5124
5125   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5126   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5127       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5128       && GET_MODE (XEXP (cond, 0)) == mode
5129       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5130           == nonzero_bits (XEXP (cond, 0), mode)
5131       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5132     return XEXP (cond, 0);
5133
5134   return x;
5135 }
5136 \f
5137 /* Simplify X, a SET expression.  Return the new expression.  */
5138
5139 static rtx
5140 simplify_set (rtx x)
5141 {
5142   rtx src = SET_SRC (x);
5143   rtx dest = SET_DEST (x);
5144   enum machine_mode mode
5145     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5146   rtx other_insn;
5147   rtx *cc_use;
5148
5149   /* (set (pc) (return)) gets written as (return).  */
5150   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5151     return src;
5152
5153   /* Now that we know for sure which bits of SRC we are using, see if we can
5154      simplify the expression for the object knowing that we only need the
5155      low-order bits.  */
5156
5157   if (GET_MODE_CLASS (mode) == MODE_INT
5158       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5159     {
5160       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5161       SUBST (SET_SRC (x), src);
5162     }
5163
5164   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5165      the comparison result and try to simplify it unless we already have used
5166      undobuf.other_insn.  */
5167   if ((GET_MODE_CLASS (mode) == MODE_CC
5168        || GET_CODE (src) == COMPARE
5169        || CC0_P (dest))
5170       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5171       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5172       && COMPARISON_P (*cc_use)
5173       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5174     {
5175       enum rtx_code old_code = GET_CODE (*cc_use);
5176       enum rtx_code new_code;
5177       rtx op0, op1, tmp;
5178       int other_changed = 0;
5179       enum machine_mode compare_mode = GET_MODE (dest);
5180
5181       if (GET_CODE (src) == COMPARE)
5182         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5183       else
5184         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5185
5186       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5187                                            op0, op1);
5188       if (!tmp)
5189         new_code = old_code;
5190       else if (!CONSTANT_P (tmp))
5191         {
5192           new_code = GET_CODE (tmp);
5193           op0 = XEXP (tmp, 0);
5194           op1 = XEXP (tmp, 1);
5195         }
5196       else
5197         {
5198           rtx pat = PATTERN (other_insn);
5199           undobuf.other_insn = other_insn;
5200           SUBST (*cc_use, tmp);
5201
5202           /* Attempt to simplify CC user.  */
5203           if (GET_CODE (pat) == SET)
5204             {
5205               rtx new = simplify_rtx (SET_SRC (pat));
5206               if (new != NULL_RTX)
5207                 SUBST (SET_SRC (pat), new);
5208             }
5209
5210           /* Convert X into a no-op move.  */
5211           SUBST (SET_DEST (x), pc_rtx);
5212           SUBST (SET_SRC (x), pc_rtx);
5213           return x;
5214         }
5215
5216       /* Simplify our comparison, if possible.  */
5217       new_code = simplify_comparison (new_code, &op0, &op1);
5218
5219 #ifdef SELECT_CC_MODE
5220       /* If this machine has CC modes other than CCmode, check to see if we
5221          need to use a different CC mode here.  */
5222       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5223         compare_mode = GET_MODE (op0);
5224       else
5225         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5226
5227 #ifndef HAVE_cc0
5228       /* If the mode changed, we have to change SET_DEST, the mode in the
5229          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5230          a hard register, just build new versions with the proper mode.  If it
5231          is a pseudo, we lose unless it is only time we set the pseudo, in
5232          which case we can safely change its mode.  */
5233       if (compare_mode != GET_MODE (dest))
5234         {
5235           if (can_change_dest_mode (dest, 0, compare_mode))
5236             {
5237               unsigned int regno = REGNO (dest);
5238               rtx new_dest;
5239
5240               if (regno < FIRST_PSEUDO_REGISTER)
5241                 new_dest = gen_rtx_REG (compare_mode, regno);
5242               else
5243                 {
5244                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5245                   new_dest = regno_reg_rtx[regno];
5246                 }
5247
5248               SUBST (SET_DEST (x), new_dest);
5249               SUBST (XEXP (*cc_use, 0), new_dest);
5250               other_changed = 1;
5251
5252               dest = new_dest;
5253             }
5254         }
5255 #endif  /* cc0 */
5256 #endif  /* SELECT_CC_MODE */
5257
5258       /* If the code changed, we have to build a new comparison in
5259          undobuf.other_insn.  */
5260       if (new_code != old_code)
5261         {
5262           int other_changed_previously = other_changed;
5263           unsigned HOST_WIDE_INT mask;
5264
5265           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5266                                           dest, const0_rtx));
5267           other_changed = 1;
5268
5269           /* If the only change we made was to change an EQ into an NE or
5270              vice versa, OP0 has only one bit that might be nonzero, and OP1
5271              is zero, check if changing the user of the condition code will
5272              produce a valid insn.  If it won't, we can keep the original code
5273              in that insn by surrounding our operation with an XOR.  */
5274
5275           if (((old_code == NE && new_code == EQ)
5276                || (old_code == EQ && new_code == NE))
5277               && ! other_changed_previously && op1 == const0_rtx
5278               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5279               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5280             {
5281               rtx pat = PATTERN (other_insn), note = 0;
5282
5283               if ((recog_for_combine (&pat, other_insn, &note) < 0
5284                    && ! check_asm_operands (pat)))
5285                 {
5286                   PUT_CODE (*cc_use, old_code);
5287                   other_changed = 0;
5288
5289                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5290                                              op0, GEN_INT (mask));
5291                 }
5292             }
5293         }
5294
5295       if (other_changed)
5296         undobuf.other_insn = other_insn;
5297
5298 #ifdef HAVE_cc0
5299       /* If we are now comparing against zero, change our source if
5300          needed.  If we do not use cc0, we always have a COMPARE.  */
5301       if (op1 == const0_rtx && dest == cc0_rtx)
5302         {
5303           SUBST (SET_SRC (x), op0);
5304           src = op0;
5305         }
5306       else
5307 #endif
5308
5309       /* Otherwise, if we didn't previously have a COMPARE in the
5310          correct mode, we need one.  */
5311       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5312         {
5313           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5314           src = SET_SRC (x);
5315         }
5316       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5317         {
5318           SUBST(SET_SRC (x), op0);
5319           src = SET_SRC (x);
5320         }
5321       else
5322         {
5323           /* Otherwise, update the COMPARE if needed.  */
5324           SUBST (XEXP (src, 0), op0);
5325           SUBST (XEXP (src, 1), op1);
5326         }
5327     }
5328   else
5329     {
5330       /* Get SET_SRC in a form where we have placed back any
5331          compound expressions.  Then do the checks below.  */
5332       src = make_compound_operation (src, SET);
5333       SUBST (SET_SRC (x), src);
5334     }
5335
5336   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5337      and X being a REG or (subreg (reg)), we may be able to convert this to
5338      (set (subreg:m2 x) (op)).
5339
5340      We can always do this if M1 is narrower than M2 because that means that
5341      we only care about the low bits of the result.
5342
5343      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5344      perform a narrower operation than requested since the high-order bits will
5345      be undefined.  On machine where it is defined, this transformation is safe
5346      as long as M1 and M2 have the same number of words.  */
5347
5348   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5349       && !OBJECT_P (SUBREG_REG (src))
5350       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5351            / UNITS_PER_WORD)
5352           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5353                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5354 #ifndef WORD_REGISTER_OPERATIONS
5355       && (GET_MODE_SIZE (GET_MODE (src))
5356         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5357 #endif
5358 #ifdef CANNOT_CHANGE_MODE_CLASS
5359       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5360             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5361                                          GET_MODE (SUBREG_REG (src)),
5362                                          GET_MODE (src)))
5363 #endif
5364       && (REG_P (dest)
5365           || (GET_CODE (dest) == SUBREG
5366               && REG_P (SUBREG_REG (dest)))))
5367     {
5368       SUBST (SET_DEST (x),
5369              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5370                                       dest));
5371       SUBST (SET_SRC (x), SUBREG_REG (src));
5372
5373       src = SET_SRC (x), dest = SET_DEST (x);
5374     }
5375
5376 #ifdef HAVE_cc0
5377   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5378      in SRC.  */
5379   if (dest == cc0_rtx
5380       && GET_CODE (src) == SUBREG
5381       && subreg_lowpart_p (src)
5382       && (GET_MODE_BITSIZE (GET_MODE (src))
5383           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5384     {
5385       rtx inner = SUBREG_REG (src);
5386       enum machine_mode inner_mode = GET_MODE (inner);
5387
5388       /* Here we make sure that we don't have a sign bit on.  */
5389       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5390           && (nonzero_bits (inner, inner_mode)
5391               < ((unsigned HOST_WIDE_INT) 1
5392                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5393         {
5394           SUBST (SET_SRC (x), inner);
5395           src = SET_SRC (x);
5396         }
5397     }
5398 #endif
5399
5400 #ifdef LOAD_EXTEND_OP
5401   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5402      would require a paradoxical subreg.  Replace the subreg with a
5403      zero_extend to avoid the reload that would otherwise be required.  */
5404
5405   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5406       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5407       && SUBREG_BYTE (src) == 0
5408       && (GET_MODE_SIZE (GET_MODE (src))
5409           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5410       && MEM_P (SUBREG_REG (src)))
5411     {
5412       SUBST (SET_SRC (x),
5413              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5414                             GET_MODE (src), SUBREG_REG (src)));
5415
5416       src = SET_SRC (x);
5417     }
5418 #endif
5419
5420   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5421      are comparing an item known to be 0 or -1 against 0, use a logical
5422      operation instead. Check for one of the arms being an IOR of the other
5423      arm with some value.  We compute three terms to be IOR'ed together.  In
5424      practice, at most two will be nonzero.  Then we do the IOR's.  */
5425
5426   if (GET_CODE (dest) != PC
5427       && GET_CODE (src) == IF_THEN_ELSE
5428       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5429       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5430       && XEXP (XEXP (src, 0), 1) == const0_rtx
5431       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5432 #ifdef HAVE_conditional_move
5433       && ! can_conditionally_move_p (GET_MODE (src))
5434 #endif
5435       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5436                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5437           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5438       && ! side_effects_p (src))
5439     {
5440       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5441                       ? XEXP (src, 1) : XEXP (src, 2));
5442       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5443                    ? XEXP (src, 2) : XEXP (src, 1));
5444       rtx term1 = const0_rtx, term2, term3;
5445
5446       if (GET_CODE (true_rtx) == IOR
5447           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5448         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5449       else if (GET_CODE (true_rtx) == IOR
5450                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5451         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5452       else if (GET_CODE (false_rtx) == IOR
5453                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5454         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5455       else if (GET_CODE (false_rtx) == IOR
5456                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5457         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5458
5459       term2 = simplify_gen_binary (AND, GET_MODE (src),
5460                                    XEXP (XEXP (src, 0), 0), true_rtx);
5461       term3 = simplify_gen_binary (AND, GET_MODE (src),
5462                                    simplify_gen_unary (NOT, GET_MODE (src),
5463                                                        XEXP (XEXP (src, 0), 0),
5464                                                        GET_MODE (src)),
5465                                    false_rtx);
5466
5467       SUBST (SET_SRC (x),
5468              simplify_gen_binary (IOR, GET_MODE (src),
5469                                   simplify_gen_binary (IOR, GET_MODE (src),
5470                                                        term1, term2),
5471                                   term3));
5472
5473       src = SET_SRC (x);
5474     }
5475
5476   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5477      whole thing fail.  */
5478   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5479     return src;
5480   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5481     return dest;
5482   else
5483     /* Convert this into a field assignment operation, if possible.  */
5484     return make_field_assignment (x);
5485 }
5486 \f
5487 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5488    result.  */
5489
5490 static rtx
5491 simplify_logical (rtx x)
5492 {
5493   enum machine_mode mode = GET_MODE (x);
5494   rtx op0 = XEXP (x, 0);
5495   rtx op1 = XEXP (x, 1);
5496
5497   switch (GET_CODE (x))
5498     {
5499     case AND:
5500       /* We can call simplify_and_const_int only if we don't lose
5501          any (sign) bits when converting INTVAL (op1) to
5502          "unsigned HOST_WIDE_INT".  */
5503       if (GET_CODE (op1) == CONST_INT
5504           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5505               || INTVAL (op1) > 0))
5506         {
5507           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5508           if (GET_CODE (x) != AND)
5509             return x;
5510
5511           op0 = XEXP (x, 0);
5512           op1 = XEXP (x, 1);
5513         }
5514
5515       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5516          apply the distributive law and then the inverse distributive
5517          law to see if things simplify.  */
5518       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5519         {
5520           rtx result = distribute_and_simplify_rtx (x, 0);
5521           if (result)
5522             return result;
5523         }
5524       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5525         {
5526           rtx result = distribute_and_simplify_rtx (x, 1);
5527           if (result)
5528             return result;
5529         }
5530       break;
5531
5532     case IOR:
5533       /* If we have (ior (and A B) C), apply the distributive law and then
5534          the inverse distributive law to see if things simplify.  */
5535
5536       if (GET_CODE (op0) == AND)
5537         {
5538           rtx result = distribute_and_simplify_rtx (x, 0);
5539           if (result)
5540             return result;
5541         }
5542
5543       if (GET_CODE (op1) == AND)
5544         {
5545           rtx result = distribute_and_simplify_rtx (x, 1);
5546           if (result)
5547             return result;
5548         }
5549       break;
5550
5551     default:
5552       gcc_unreachable ();
5553     }
5554
5555   return x;
5556 }
5557 \f
5558 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5559    operations" because they can be replaced with two more basic operations.
5560    ZERO_EXTEND is also considered "compound" because it can be replaced with
5561    an AND operation, which is simpler, though only one operation.
5562
5563    The function expand_compound_operation is called with an rtx expression
5564    and will convert it to the appropriate shifts and AND operations,
5565    simplifying at each stage.
5566
5567    The function make_compound_operation is called to convert an expression
5568    consisting of shifts and ANDs into the equivalent compound expression.
5569    It is the inverse of this function, loosely speaking.  */
5570
5571 static rtx
5572 expand_compound_operation (rtx x)
5573 {
5574   unsigned HOST_WIDE_INT pos = 0, len;
5575   int unsignedp = 0;
5576   unsigned int modewidth;
5577   rtx tem;
5578
5579   switch (GET_CODE (x))
5580     {
5581     case ZERO_EXTEND:
5582       unsignedp = 1;
5583     case SIGN_EXTEND:
5584       /* We can't necessarily use a const_int for a multiword mode;
5585          it depends on implicitly extending the value.
5586          Since we don't know the right way to extend it,
5587          we can't tell whether the implicit way is right.
5588
5589          Even for a mode that is no wider than a const_int,
5590          we can't win, because we need to sign extend one of its bits through
5591          the rest of it, and we don't know which bit.  */
5592       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5593         return x;
5594
5595       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5596          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5597          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5598          reloaded. If not for that, MEM's would very rarely be safe.
5599
5600          Reject MODEs bigger than a word, because we might not be able
5601          to reference a two-register group starting with an arbitrary register
5602          (and currently gen_lowpart might crash for a SUBREG).  */
5603
5604       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5605         return x;
5606
5607       /* Reject MODEs that aren't scalar integers because turning vector
5608          or complex modes into shifts causes problems.  */
5609
5610       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5611         return x;
5612
5613       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5614       /* If the inner object has VOIDmode (the only way this can happen
5615          is if it is an ASM_OPERANDS), we can't do anything since we don't
5616          know how much masking to do.  */
5617       if (len == 0)
5618         return x;
5619
5620       break;
5621
5622     case ZERO_EXTRACT:
5623       unsignedp = 1;
5624
5625       /* ... fall through ...  */
5626
5627     case SIGN_EXTRACT:
5628       /* If the operand is a CLOBBER, just return it.  */
5629       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5630         return XEXP (x, 0);
5631
5632       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5633           || GET_CODE (XEXP (x, 2)) != CONST_INT
5634           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5635         return x;
5636
5637       /* Reject MODEs that aren't scalar integers because turning vector
5638          or complex modes into shifts causes problems.  */
5639
5640       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5641         return x;
5642
5643       len = INTVAL (XEXP (x, 1));
5644       pos = INTVAL (XEXP (x, 2));
5645
5646       /* If this goes outside the object being extracted, replace the object
5647          with a (use (mem ...)) construct that only combine understands
5648          and is used only for this purpose.  */
5649       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5650         SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5651
5652       if (BITS_BIG_ENDIAN)
5653         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5654
5655       break;
5656
5657     default:
5658       return x;
5659     }
5660   /* Convert sign extension to zero extension, if we know that the high
5661      bit is not set, as this is easier to optimize.  It will be converted
5662      back to cheaper alternative in make_extraction.  */
5663   if (GET_CODE (x) == SIGN_EXTEND
5664       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5665           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5666                 & ~(((unsigned HOST_WIDE_INT)
5667                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5668                      >> 1))
5669                == 0)))
5670     {
5671       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5672       rtx temp2 = expand_compound_operation (temp);
5673
5674       /* Make sure this is a profitable operation.  */
5675       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5676        return temp2;
5677       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5678        return temp;
5679       else
5680        return x;
5681     }
5682
5683   /* We can optimize some special cases of ZERO_EXTEND.  */
5684   if (GET_CODE (x) == ZERO_EXTEND)
5685     {
5686       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5687          know that the last value didn't have any inappropriate bits
5688          set.  */
5689       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5690           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5691           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5692           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5693               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5694         return XEXP (XEXP (x, 0), 0);
5695
5696       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5697       if (GET_CODE (XEXP (x, 0)) == SUBREG
5698           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5699           && subreg_lowpart_p (XEXP (x, 0))
5700           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5701           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5702               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5703         return SUBREG_REG (XEXP (x, 0));
5704
5705       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5706          is a comparison and STORE_FLAG_VALUE permits.  This is like
5707          the first case, but it works even when GET_MODE (x) is larger
5708          than HOST_WIDE_INT.  */
5709       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5710           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5711           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5712           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5713               <= HOST_BITS_PER_WIDE_INT)
5714           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5715               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5716         return XEXP (XEXP (x, 0), 0);
5717
5718       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5719       if (GET_CODE (XEXP (x, 0)) == SUBREG
5720           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5721           && subreg_lowpart_p (XEXP (x, 0))
5722           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5723           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5724               <= HOST_BITS_PER_WIDE_INT)
5725           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5726               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5727         return SUBREG_REG (XEXP (x, 0));
5728
5729     }
5730
5731   /* If we reach here, we want to return a pair of shifts.  The inner
5732      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5733      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5734      logical depending on the value of UNSIGNEDP.
5735
5736      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5737      converted into an AND of a shift.
5738
5739      We must check for the case where the left shift would have a negative
5740      count.  This can happen in a case like (x >> 31) & 255 on machines
5741      that can't shift by a constant.  On those machines, we would first
5742      combine the shift with the AND to produce a variable-position
5743      extraction.  Then the constant of 31 would be substituted in to produce
5744      a such a position.  */
5745
5746   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5747   if (modewidth + len >= pos)
5748     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5749                                 GET_MODE (x),
5750                                 simplify_shift_const (NULL_RTX, ASHIFT,
5751                                                       GET_MODE (x),
5752                                                       XEXP (x, 0),
5753                                                       modewidth - pos - len),
5754                                 modewidth - len);
5755
5756   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5757     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5758                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5759                                                         GET_MODE (x),
5760                                                         XEXP (x, 0), pos),
5761                                   ((HOST_WIDE_INT) 1 << len) - 1);
5762   else
5763     /* Any other cases we can't handle.  */
5764     return x;
5765
5766   /* If we couldn't do this for some reason, return the original
5767      expression.  */
5768   if (GET_CODE (tem) == CLOBBER)
5769     return x;
5770
5771   return tem;
5772 }
5773 \f
5774 /* X is a SET which contains an assignment of one object into
5775    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5776    or certain SUBREGS). If possible, convert it into a series of
5777    logical operations.
5778
5779    We half-heartedly support variable positions, but do not at all
5780    support variable lengths.  */
5781
5782 static rtx
5783 expand_field_assignment (rtx x)
5784 {
5785   rtx inner;
5786   rtx pos;                      /* Always counts from low bit.  */
5787   int len;
5788   rtx mask, cleared, masked;
5789   enum machine_mode compute_mode;
5790
5791   /* Loop until we find something we can't simplify.  */
5792   while (1)
5793     {
5794       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5795           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5796         {
5797           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5798           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5799           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5800         }
5801       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5802                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5803         {
5804           inner = XEXP (SET_DEST (x), 0);
5805           len = INTVAL (XEXP (SET_DEST (x), 1));
5806           pos = XEXP (SET_DEST (x), 2);
5807
5808           /* If the position is constant and spans the width of INNER,
5809              surround INNER  with a USE to indicate this.  */
5810           if (GET_CODE (pos) == CONST_INT
5811               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5812             inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5813
5814           if (BITS_BIG_ENDIAN)
5815             {
5816               if (GET_CODE (pos) == CONST_INT)
5817                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5818                                - INTVAL (pos));
5819               else if (GET_CODE (pos) == MINUS
5820                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5821                        && (INTVAL (XEXP (pos, 1))
5822                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5823                 /* If position is ADJUST - X, new position is X.  */
5824                 pos = XEXP (pos, 0);
5825               else
5826                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5827                                            GEN_INT (GET_MODE_BITSIZE (
5828                                                     GET_MODE (inner))
5829                                                     - len),
5830                                            pos);
5831             }
5832         }
5833
5834       /* A SUBREG between two modes that occupy the same numbers of words
5835          can be done by moving the SUBREG to the source.  */
5836       else if (GET_CODE (SET_DEST (x)) == SUBREG
5837                /* We need SUBREGs to compute nonzero_bits properly.  */
5838                && nonzero_sign_valid
5839                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5840                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5841                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5842                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5843         {
5844           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5845                            gen_lowpart
5846                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5847                             SET_SRC (x)));
5848           continue;
5849         }
5850       else
5851         break;
5852
5853       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5854         inner = SUBREG_REG (inner);
5855
5856       compute_mode = GET_MODE (inner);
5857
5858       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5859       if (! SCALAR_INT_MODE_P (compute_mode))
5860         {
5861           enum machine_mode imode;
5862
5863           /* Don't do anything for vector or complex integral types.  */
5864           if (! FLOAT_MODE_P (compute_mode))
5865             break;
5866
5867           /* Try to find an integral mode to pun with.  */
5868           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5869           if (imode == BLKmode)
5870             break;
5871
5872           compute_mode = imode;
5873           inner = gen_lowpart (imode, inner);
5874         }
5875
5876       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5877       if (len >= HOST_BITS_PER_WIDE_INT)
5878         break;
5879
5880       /* Now compute the equivalent expression.  Make a copy of INNER
5881          for the SET_DEST in case it is a MEM into which we will substitute;
5882          we don't want shared RTL in that case.  */
5883       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5884       cleared = simplify_gen_binary (AND, compute_mode,
5885                                      simplify_gen_unary (NOT, compute_mode,
5886                                        simplify_gen_binary (ASHIFT,
5887                                                             compute_mode,
5888                                                             mask, pos),
5889                                        compute_mode),
5890                                      inner);
5891       masked = simplify_gen_binary (ASHIFT, compute_mode,
5892                                     simplify_gen_binary (
5893                                       AND, compute_mode,
5894                                       gen_lowpart (compute_mode, SET_SRC (x)),
5895                                       mask),
5896                                     pos);
5897
5898       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5899                        simplify_gen_binary (IOR, compute_mode,
5900                                             cleared, masked));
5901     }
5902
5903   return x;
5904 }
5905 \f
5906 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5907    it is an RTX that represents a variable starting position; otherwise,
5908    POS is the (constant) starting bit position (counted from the LSB).
5909
5910    INNER may be a USE.  This will occur when we started with a bitfield
5911    that went outside the boundary of the object in memory, which is
5912    allowed on most machines.  To isolate this case, we produce a USE
5913    whose mode is wide enough and surround the MEM with it.  The only
5914    code that understands the USE is this routine.  If it is not removed,
5915    it will cause the resulting insn not to match.
5916
5917    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5918    signed reference.
5919
5920    IN_DEST is nonzero if this is a reference in the destination of a
5921    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5922    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5923    be used.
5924
5925    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5926    ZERO_EXTRACT should be built even for bits starting at bit 0.
5927
5928    MODE is the desired mode of the result (if IN_DEST == 0).
5929
5930    The result is an RTX for the extraction or NULL_RTX if the target
5931    can't handle it.  */
5932
5933 static rtx
5934 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5935                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5936                  int in_dest, int in_compare)
5937 {
5938   /* This mode describes the size of the storage area
5939      to fetch the overall value from.  Within that, we
5940      ignore the POS lowest bits, etc.  */
5941   enum machine_mode is_mode = GET_MODE (inner);
5942   enum machine_mode inner_mode;
5943   enum machine_mode wanted_inner_mode = byte_mode;
5944   enum machine_mode wanted_inner_reg_mode = word_mode;
5945   enum machine_mode pos_mode = word_mode;
5946   enum machine_mode extraction_mode = word_mode;
5947   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5948   int spans_byte = 0;
5949   rtx new = 0;
5950   rtx orig_pos_rtx = pos_rtx;
5951   HOST_WIDE_INT orig_pos;
5952
5953   /* Get some information about INNER and get the innermost object.  */
5954   if (GET_CODE (inner) == USE)
5955     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5956     /* We don't need to adjust the position because we set up the USE
5957        to pretend that it was a full-word object.  */
5958     spans_byte = 1, inner = XEXP (inner, 0);
5959   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5960     {
5961       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5962          consider just the QI as the memory to extract from.
5963          The subreg adds or removes high bits; its mode is
5964          irrelevant to the meaning of this extraction,
5965          since POS and LEN count from the lsb.  */
5966       if (MEM_P (SUBREG_REG (inner)))
5967         is_mode = GET_MODE (SUBREG_REG (inner));
5968       inner = SUBREG_REG (inner);
5969     }
5970   else if (GET_CODE (inner) == ASHIFT
5971            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5972            && pos_rtx == 0 && pos == 0
5973            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5974     {
5975       /* We're extracting the least significant bits of an rtx
5976          (ashift X (const_int C)), where LEN > C.  Extract the
5977          least significant (LEN - C) bits of X, giving an rtx
5978          whose mode is MODE, then shift it left C times.  */
5979       new = make_extraction (mode, XEXP (inner, 0),
5980                              0, 0, len - INTVAL (XEXP (inner, 1)),
5981                              unsignedp, in_dest, in_compare);
5982       if (new != 0)
5983         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5984     }
5985
5986   inner_mode = GET_MODE (inner);
5987
5988   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5989     pos = INTVAL (pos_rtx), pos_rtx = 0;
5990
5991   /* See if this can be done without an extraction.  We never can if the
5992      width of the field is not the same as that of some integer mode. For
5993      registers, we can only avoid the extraction if the position is at the
5994      low-order bit and this is either not in the destination or we have the
5995      appropriate STRICT_LOW_PART operation available.
5996
5997      For MEM, we can avoid an extract if the field starts on an appropriate
5998      boundary and we can change the mode of the memory reference.  However,
5999      we cannot directly access the MEM if we have a USE and the underlying
6000      MEM is not TMODE.  This combination means that MEM was being used in a
6001      context where bits outside its mode were being referenced; that is only
6002      valid in bit-field insns.  */
6003
6004   if (tmode != BLKmode
6005       && ! (spans_byte && inner_mode != tmode)
6006       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6007            && !MEM_P (inner)
6008            && (inner_mode == tmode
6009                || !REG_P (inner)
6010                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6011                                          GET_MODE_BITSIZE (inner_mode))
6012                || reg_truncated_to_mode (tmode, inner))
6013            && (! in_dest
6014                || (REG_P (inner)
6015                    && have_insn_for (STRICT_LOW_PART, tmode))))
6016           || (MEM_P (inner) && pos_rtx == 0
6017               && (pos
6018                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6019                      : BITS_PER_UNIT)) == 0
6020               /* We can't do this if we are widening INNER_MODE (it
6021                  may not be aligned, for one thing).  */
6022               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6023               && (inner_mode == tmode
6024                   || (! mode_dependent_address_p (XEXP (inner, 0))
6025                       && ! MEM_VOLATILE_P (inner))))))
6026     {
6027       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6028          field.  If the original and current mode are the same, we need not
6029          adjust the offset.  Otherwise, we do if bytes big endian.
6030
6031          If INNER is not a MEM, get a piece consisting of just the field
6032          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6033
6034       if (MEM_P (inner))
6035         {
6036           HOST_WIDE_INT offset;
6037
6038           /* POS counts from lsb, but make OFFSET count in memory order.  */
6039           if (BYTES_BIG_ENDIAN)
6040             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6041           else
6042             offset = pos / BITS_PER_UNIT;
6043
6044           new = adjust_address_nv (inner, tmode, offset);
6045         }
6046       else if (REG_P (inner))
6047         {
6048           if (tmode != inner_mode)
6049             {
6050               /* We can't call gen_lowpart in a DEST since we
6051                  always want a SUBREG (see below) and it would sometimes
6052                  return a new hard register.  */
6053               if (pos || in_dest)
6054                 {
6055                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6056
6057                   if (WORDS_BIG_ENDIAN
6058                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6059                     final_word = ((GET_MODE_SIZE (inner_mode)
6060                                    - GET_MODE_SIZE (tmode))
6061                                   / UNITS_PER_WORD) - final_word;
6062
6063                   final_word *= UNITS_PER_WORD;
6064                   if (BYTES_BIG_ENDIAN &&
6065                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6066                     final_word += (GET_MODE_SIZE (inner_mode)
6067                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6068
6069                   /* Avoid creating invalid subregs, for example when
6070                      simplifying (x>>32)&255.  */
6071                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6072                     return NULL_RTX;
6073
6074                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6075                 }
6076               else
6077                 new = gen_lowpart (tmode, inner);
6078             }
6079           else
6080             new = inner;
6081         }
6082       else
6083         new = force_to_mode (inner, tmode,
6084                              len >= HOST_BITS_PER_WIDE_INT
6085                              ? ~(unsigned HOST_WIDE_INT) 0
6086                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6087                              0);
6088
6089       /* If this extraction is going into the destination of a SET,
6090          make a STRICT_LOW_PART unless we made a MEM.  */
6091
6092       if (in_dest)
6093         return (MEM_P (new) ? new
6094                 : (GET_CODE (new) != SUBREG
6095                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6096                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6097
6098       if (mode == tmode)
6099         return new;
6100
6101       if (GET_CODE (new) == CONST_INT)
6102         return gen_int_mode (INTVAL (new), mode);
6103
6104       /* If we know that no extraneous bits are set, and that the high
6105          bit is not set, convert the extraction to the cheaper of
6106          sign and zero extension, that are equivalent in these cases.  */
6107       if (flag_expensive_optimizations
6108           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6109               && ((nonzero_bits (new, tmode)
6110                    & ~(((unsigned HOST_WIDE_INT)
6111                         GET_MODE_MASK (tmode))
6112                        >> 1))
6113                   == 0)))
6114         {
6115           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6116           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6117
6118           /* Prefer ZERO_EXTENSION, since it gives more information to
6119              backends.  */
6120           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6121             return temp;
6122           return temp1;
6123         }
6124
6125       /* Otherwise, sign- or zero-extend unless we already are in the
6126          proper mode.  */
6127
6128       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6129                              mode, new));
6130     }
6131
6132   /* Unless this is a COMPARE or we have a funny memory reference,
6133      don't do anything with zero-extending field extracts starting at
6134      the low-order bit since they are simple AND operations.  */
6135   if (pos_rtx == 0 && pos == 0 && ! in_dest
6136       && ! in_compare && ! spans_byte && unsignedp)
6137     return 0;
6138
6139   /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6140      we would be spanning bytes or if the position is not a constant and the
6141      length is not 1.  In all other cases, we would only be going outside
6142      our object in cases when an original shift would have been
6143      undefined.  */
6144   if (! spans_byte && MEM_P (inner)
6145       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6146           || (pos_rtx != 0 && len != 1)))
6147     return 0;
6148
6149   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6150      and the mode for the result.  */
6151   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6152     {
6153       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6154       pos_mode = mode_for_extraction (EP_insv, 2);
6155       extraction_mode = mode_for_extraction (EP_insv, 3);
6156     }
6157
6158   if (! in_dest && unsignedp
6159       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6160     {
6161       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6162       pos_mode = mode_for_extraction (EP_extzv, 3);
6163       extraction_mode = mode_for_extraction (EP_extzv, 0);
6164     }
6165
6166   if (! in_dest && ! unsignedp
6167       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6168     {
6169       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6170       pos_mode = mode_for_extraction (EP_extv, 3);
6171       extraction_mode = mode_for_extraction (EP_extv, 0);
6172     }
6173
6174   /* Never narrow an object, since that might not be safe.  */
6175
6176   if (mode != VOIDmode
6177       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6178     extraction_mode = mode;
6179
6180   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6181       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6182     pos_mode = GET_MODE (pos_rtx);
6183
6184   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6185      if we have to change the mode of memory and cannot, the desired mode is
6186      EXTRACTION_MODE.  */
6187   if (!MEM_P (inner))
6188     wanted_inner_mode = wanted_inner_reg_mode;
6189   else if (inner_mode != wanted_inner_mode
6190            && (mode_dependent_address_p (XEXP (inner, 0))
6191                || MEM_VOLATILE_P (inner)))
6192     wanted_inner_mode = extraction_mode;
6193
6194   orig_pos = pos;
6195
6196   if (BITS_BIG_ENDIAN)
6197     {
6198       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6199          BITS_BIG_ENDIAN style.  If position is constant, compute new
6200          position.  Otherwise, build subtraction.
6201          Note that POS is relative to the mode of the original argument.
6202          If it's a MEM we need to recompute POS relative to that.
6203          However, if we're extracting from (or inserting into) a register,
6204          we want to recompute POS relative to wanted_inner_mode.  */
6205       int width = (MEM_P (inner)
6206                    ? GET_MODE_BITSIZE (is_mode)
6207                    : GET_MODE_BITSIZE (wanted_inner_mode));
6208
6209       if (pos_rtx == 0)
6210         pos = width - len - pos;
6211       else
6212         pos_rtx
6213           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6214       /* POS may be less than 0 now, but we check for that below.
6215          Note that it can only be less than 0 if !MEM_P (inner).  */
6216     }
6217
6218   /* If INNER has a wider mode, make it smaller.  If this is a constant
6219      extract, try to adjust the byte to point to the byte containing
6220      the value.  */
6221   if (wanted_inner_mode != VOIDmode
6222       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6223       && ((MEM_P (inner)
6224            && (inner_mode == wanted_inner_mode
6225                || (! mode_dependent_address_p (XEXP (inner, 0))
6226                    && ! MEM_VOLATILE_P (inner))))))
6227     {
6228       int offset = 0;
6229
6230       /* The computations below will be correct if the machine is big
6231          endian in both bits and bytes or little endian in bits and bytes.
6232          If it is mixed, we must adjust.  */
6233
6234       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6235          adjust OFFSET to compensate.  */
6236       if (BYTES_BIG_ENDIAN
6237           && ! spans_byte
6238           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6239         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6240
6241       /* If this is a constant position, we can move to the desired byte.
6242          Be careful not to go beyond the original object and maintain the
6243          natural alignment of the memory.  */
6244       if (pos_rtx == 0)
6245         {
6246           enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6247           offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6248           pos %= GET_MODE_BITSIZE (bfmode);
6249         }
6250
6251       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6252           && ! spans_byte
6253           && is_mode != wanted_inner_mode)
6254         offset = (GET_MODE_SIZE (is_mode)
6255                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6256
6257       if (offset != 0 || inner_mode != wanted_inner_mode)
6258         inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6259     }
6260
6261   /* If INNER is not memory, we can always get it into the proper mode.  If we
6262      are changing its mode, POS must be a constant and smaller than the size
6263      of the new mode.  */
6264   else if (!MEM_P (inner))
6265     {
6266       if (GET_MODE (inner) != wanted_inner_mode
6267           && (pos_rtx != 0
6268               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6269         return 0;
6270
6271       inner = force_to_mode (inner, wanted_inner_mode,
6272                              pos_rtx
6273                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6274                              ? ~(unsigned HOST_WIDE_INT) 0
6275                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6276                                 << orig_pos),
6277                              0);
6278     }
6279
6280   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6281      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6282   if (pos_rtx != 0
6283       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6284     {
6285       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6286
6287       /* If we know that no extraneous bits are set, and that the high
6288          bit is not set, convert extraction to cheaper one - either
6289          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6290          cases.  */
6291       if (flag_expensive_optimizations
6292           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6293               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6294                    & ~(((unsigned HOST_WIDE_INT)
6295                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6296                        >> 1))
6297                   == 0)))
6298         {
6299           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6300
6301           /* Prefer ZERO_EXTENSION, since it gives more information to
6302              backends.  */
6303           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6304             temp = temp1;
6305         }
6306       pos_rtx = temp;
6307     }
6308   else if (pos_rtx != 0
6309            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6310     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6311
6312   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6313      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6314      be a CONST_INT.  */
6315   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6316     pos_rtx = orig_pos_rtx;
6317
6318   else if (pos_rtx == 0)
6319     pos_rtx = GEN_INT (pos);
6320
6321   /* Make the required operation.  See if we can use existing rtx.  */
6322   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6323                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6324   if (! in_dest)
6325     new = gen_lowpart (mode, new);
6326
6327   return new;
6328 }
6329 \f
6330 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6331    with any other operations in X.  Return X without that shift if so.  */
6332
6333 static rtx
6334 extract_left_shift (rtx x, int count)
6335 {
6336   enum rtx_code code = GET_CODE (x);
6337   enum machine_mode mode = GET_MODE (x);
6338   rtx tem;
6339
6340   switch (code)
6341     {
6342     case ASHIFT:
6343       /* This is the shift itself.  If it is wide enough, we will return
6344          either the value being shifted if the shift count is equal to
6345          COUNT or a shift for the difference.  */
6346       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6347           && INTVAL (XEXP (x, 1)) >= count)
6348         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6349                                      INTVAL (XEXP (x, 1)) - count);
6350       break;
6351
6352     case NEG:  case NOT:
6353       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6354         return simplify_gen_unary (code, mode, tem, mode);
6355
6356       break;
6357
6358     case PLUS:  case IOR:  case XOR:  case AND:
6359       /* If we can safely shift this constant and we find the inner shift,
6360          make a new operation.  */
6361       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6362           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6363           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6364         return simplify_gen_binary (code, mode, tem,
6365                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6366
6367       break;
6368
6369     default:
6370       break;
6371     }
6372
6373   return 0;
6374 }
6375 \f
6376 /* Look at the expression rooted at X.  Look for expressions
6377    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6378    Form these expressions.
6379
6380    Return the new rtx, usually just X.
6381
6382    Also, for machines like the VAX that don't have logical shift insns,
6383    try to convert logical to arithmetic shift operations in cases where
6384    they are equivalent.  This undoes the canonicalizations to logical
6385    shifts done elsewhere.
6386
6387    We try, as much as possible, to re-use rtl expressions to save memory.
6388
6389    IN_CODE says what kind of expression we are processing.  Normally, it is
6390    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6391    being kludges), it is MEM.  When processing the arguments of a comparison
6392    or a COMPARE against zero, it is COMPARE.  */
6393
6394 static rtx
6395 make_compound_operation (rtx x, enum rtx_code in_code)
6396 {
6397   enum rtx_code code = GET_CODE (x);
6398   enum machine_mode mode = GET_MODE (x);
6399   int mode_width = GET_MODE_BITSIZE (mode);
6400   rtx rhs, lhs;
6401   enum rtx_code next_code;
6402   int i;
6403   rtx new = 0;
6404   rtx tem;
6405   const char *fmt;
6406
6407   /* Select the code to be used in recursive calls.  Once we are inside an
6408      address, we stay there.  If we have a comparison, set to COMPARE,
6409      but once inside, go back to our default of SET.  */
6410
6411   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6412                : ((code == COMPARE || COMPARISON_P (x))
6413                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6414                : in_code == COMPARE ? SET : in_code);
6415
6416   /* Process depending on the code of this operation.  If NEW is set
6417      nonzero, it will be returned.  */
6418
6419   switch (code)
6420     {
6421     case ASHIFT:
6422       /* Convert shifts by constants into multiplications if inside
6423          an address.  */
6424       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6425           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6426           && INTVAL (XEXP (x, 1)) >= 0)
6427         {
6428           new = make_compound_operation (XEXP (x, 0), next_code);
6429           new = gen_rtx_MULT (mode, new,
6430                               GEN_INT ((HOST_WIDE_INT) 1
6431                                        << INTVAL (XEXP (x, 1))));
6432         }
6433       break;
6434
6435     case AND:
6436       /* If the second operand is not a constant, we can't do anything
6437          with it.  */
6438       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6439         break;
6440
6441       /* If the constant is a power of two minus one and the first operand
6442          is a logical right shift, make an extraction.  */
6443       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6444           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6445         {
6446           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6447           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6448                                  0, in_code == COMPARE);
6449         }
6450
6451       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6452       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6453                && subreg_lowpart_p (XEXP (x, 0))
6454                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6455                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6456         {
6457           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6458                                          next_code);
6459           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6460                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6461                                  0, in_code == COMPARE);
6462         }
6463       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6464       else if ((GET_CODE (XEXP (x, 0)) == XOR
6465                 || GET_CODE (XEXP (x, 0)) == IOR)
6466                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6467                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6468                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6469         {
6470           /* Apply the distributive law, and then try to make extractions.  */
6471           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6472                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6473                                              XEXP (x, 1)),
6474                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6475                                              XEXP (x, 1)));
6476           new = make_compound_operation (new, in_code);
6477         }
6478
6479       /* If we are have (and (rotate X C) M) and C is larger than the number
6480          of bits in M, this is an extraction.  */
6481
6482       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6483                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6484                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6485                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6486         {
6487           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6488           new = make_extraction (mode, new,
6489                                  (GET_MODE_BITSIZE (mode)
6490                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6491                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6492         }
6493
6494       /* On machines without logical shifts, if the operand of the AND is
6495          a logical shift and our mask turns off all the propagated sign
6496          bits, we can replace the logical shift with an arithmetic shift.  */
6497       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6498                && !have_insn_for (LSHIFTRT, mode)
6499                && have_insn_for (ASHIFTRT, mode)
6500                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6501                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6502                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6503                && mode_width <= HOST_BITS_PER_WIDE_INT)
6504         {
6505           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6506
6507           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6508           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6509             SUBST (XEXP (x, 0),
6510                    gen_rtx_ASHIFTRT (mode,
6511                                      make_compound_operation
6512                                      (XEXP (XEXP (x, 0), 0), next_code),
6513                                      XEXP (XEXP (x, 0), 1)));
6514         }
6515
6516       /* If the constant is one less than a power of two, this might be
6517          representable by an extraction even if no shift is present.
6518          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6519          we are in a COMPARE.  */
6520       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6521         new = make_extraction (mode,
6522                                make_compound_operation (XEXP (x, 0),
6523                                                         next_code),
6524                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6525
6526       /* If we are in a comparison and this is an AND with a power of two,
6527          convert this into the appropriate bit extract.  */
6528       else if (in_code == COMPARE
6529                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6530         new = make_extraction (mode,
6531                                make_compound_operation (XEXP (x, 0),
6532                                                         next_code),
6533                                i, NULL_RTX, 1, 1, 0, 1);
6534
6535       break;
6536
6537     case LSHIFTRT:
6538       /* If the sign bit is known to be zero, replace this with an
6539          arithmetic shift.  */
6540       if (have_insn_for (ASHIFTRT, mode)
6541           && ! have_insn_for (LSHIFTRT, mode)
6542           && mode_width <= HOST_BITS_PER_WIDE_INT
6543           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6544         {
6545           new = gen_rtx_ASHIFTRT (mode,
6546                                   make_compound_operation (XEXP (x, 0),
6547                                                            next_code),
6548                                   XEXP (x, 1));
6549           break;
6550         }
6551
6552       /* ... fall through ...  */
6553
6554     case ASHIFTRT:
6555       lhs = XEXP (x, 0);
6556       rhs = XEXP (x, 1);
6557
6558       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6559          this is a SIGN_EXTRACT.  */
6560       if (GET_CODE (rhs) == CONST_INT
6561           && GET_CODE (lhs) == ASHIFT
6562           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6563           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6564         {
6565           new = make_compound_operation (XEXP (lhs, 0), next_code);
6566           new = make_extraction (mode, new,
6567                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6568                                  NULL_RTX, mode_width - INTVAL (rhs),
6569                                  code == LSHIFTRT, 0, in_code == COMPARE);
6570           break;
6571         }
6572
6573       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6574          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6575          also do this for some cases of SIGN_EXTRACT, but it doesn't
6576          seem worth the effort; the case checked for occurs on Alpha.  */
6577
6578       if (!OBJECT_P (lhs)
6579           && ! (GET_CODE (lhs) == SUBREG
6580                 && (OBJECT_P (SUBREG_REG (lhs))))
6581           && GET_CODE (rhs) == CONST_INT
6582           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6583           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6584         new = make_extraction (mode, make_compound_operation (new, next_code),
6585                                0, NULL_RTX, mode_width - INTVAL (rhs),
6586                                code == LSHIFTRT, 0, in_code == COMPARE);
6587
6588       break;
6589
6590     case SUBREG:
6591       /* Call ourselves recursively on the inner expression.  If we are
6592          narrowing the object and it has a different RTL code from
6593          what it originally did, do this SUBREG as a force_to_mode.  */
6594
6595       tem = make_compound_operation (SUBREG_REG (x), in_code);
6596
6597       {
6598         rtx simplified;
6599         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6600                                       SUBREG_BYTE (x));
6601
6602         if (simplified)
6603           tem = simplified;
6604
6605         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6606             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6607             && subreg_lowpart_p (x))
6608           {
6609             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6610                                        0);
6611
6612             /* If we have something other than a SUBREG, we might have
6613                done an expansion, so rerun ourselves.  */
6614             if (GET_CODE (newer) != SUBREG)
6615               newer = make_compound_operation (newer, in_code);
6616
6617             return newer;
6618           }
6619
6620         if (simplified)
6621           return tem;
6622       }
6623       break;
6624
6625     default:
6626       break;
6627     }
6628
6629   if (new)
6630     {
6631       x = gen_lowpart (mode, new);
6632       code = GET_CODE (x);
6633     }
6634
6635   /* Now recursively process each operand of this operation.  */
6636   fmt = GET_RTX_FORMAT (code);
6637   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6638     if (fmt[i] == 'e')
6639       {
6640         new = make_compound_operation (XEXP (x, i), next_code);
6641         SUBST (XEXP (x, i), new);
6642       }
6643
6644   /* If this is a commutative operation, the changes to the operands
6645      may have made it noncanonical.  */
6646   if (COMMUTATIVE_ARITH_P (x)
6647       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6648     {
6649       tem = XEXP (x, 0);
6650       SUBST (XEXP (x, 0), XEXP (x, 1));
6651       SUBST (XEXP (x, 1), tem);
6652     }
6653
6654   return x;
6655 }
6656 \f
6657 /* Given M see if it is a value that would select a field of bits
6658    within an item, but not the entire word.  Return -1 if not.
6659    Otherwise, return the starting position of the field, where 0 is the
6660    low-order bit.
6661
6662    *PLEN is set to the length of the field.  */
6663
6664 static int
6665 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6666 {
6667   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6668   int pos = exact_log2 (m & -m);
6669   int len = 0;
6670
6671   if (pos >= 0)
6672     /* Now shift off the low-order zero bits and see if we have a
6673        power of two minus 1.  */
6674     len = exact_log2 ((m >> pos) + 1);
6675
6676   if (len <= 0)
6677     pos = -1;
6678
6679   *plen = len;
6680   return pos;
6681 }
6682 \f
6683 /* If X refers to a register that equals REG in value, replace these
6684    references with REG.  */
6685 static rtx
6686 canon_reg_for_combine (rtx x, rtx reg)
6687 {
6688   rtx op0, op1, op2;
6689   const char *fmt;
6690   int i;
6691   bool copied;
6692
6693   enum rtx_code code = GET_CODE (x);
6694   switch (GET_RTX_CLASS (code))
6695     {
6696     case RTX_UNARY:
6697       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6698       if (op0 != XEXP (x, 0))
6699         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6700                                    GET_MODE (reg));
6701       break;
6702
6703     case RTX_BIN_ARITH:
6704     case RTX_COMM_ARITH:
6705       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6706       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6707       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6708         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6709       break;
6710
6711     case RTX_COMPARE:
6712     case RTX_COMM_COMPARE:
6713       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6714       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6715       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6716         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6717                                         GET_MODE (op0), op0, op1);
6718       break;
6719
6720     case RTX_TERNARY:
6721     case RTX_BITFIELD_OPS:
6722       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6723       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6724       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6725       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6726         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6727                                      GET_MODE (op0), op0, op1, op2);
6728
6729     case RTX_OBJ:
6730       if (REG_P (x))
6731         {
6732           if (rtx_equal_p (get_last_value (reg), x)
6733               || rtx_equal_p (reg, get_last_value (x)))
6734             return reg;
6735           else
6736             break;
6737         }
6738
6739       /* fall through */
6740
6741     default:
6742       fmt = GET_RTX_FORMAT (code);
6743       copied = false;
6744       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6745         if (fmt[i] == 'e')
6746           {
6747             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6748             if (op != XEXP (x, i))
6749               {
6750                 if (!copied)
6751                   {
6752                     copied = true;
6753                     x = copy_rtx (x);
6754                   }
6755                 XEXP (x, i) = op;
6756               }
6757           }
6758         else if (fmt[i] == 'E')
6759           {
6760             int j;
6761             for (j = 0; j < XVECLEN (x, i); j++)
6762               {
6763                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6764                 if (op != XVECEXP (x, i, j))
6765                   {
6766                     if (!copied)
6767                       {
6768                         copied = true;
6769                         x = copy_rtx (x);
6770                       }
6771                     XVECEXP (x, i, j) = op;
6772                   }
6773               }
6774           }
6775
6776       break;
6777     }
6778
6779   return x;
6780 }
6781
6782 /* Return X converted to MODE.  If the value is already truncated to
6783    MODE we can just return a subreg even though in the general case we
6784    would need an explicit truncation.  */
6785
6786 static rtx
6787 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6788 {
6789   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6790       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6791                                 GET_MODE_BITSIZE (GET_MODE (x)))
6792       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6793     return gen_lowpart (mode, x);
6794   else
6795     return gen_rtx_TRUNCATE (mode, x);
6796 }
6797
6798 /* See if X can be simplified knowing that we will only refer to it in
6799    MODE and will only refer to those bits that are nonzero in MASK.
6800    If other bits are being computed or if masking operations are done
6801    that select a superset of the bits in MASK, they can sometimes be
6802    ignored.
6803
6804    Return a possibly simplified expression, but always convert X to
6805    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6806
6807    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6808    are all off in X.  This is used when X will be complemented, by either
6809    NOT, NEG, or XOR.  */
6810
6811 static rtx
6812 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6813                int just_select)
6814 {
6815   enum rtx_code code = GET_CODE (x);
6816   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6817   enum machine_mode op_mode;
6818   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6819   rtx op0, op1, temp;
6820
6821   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6822      code below will do the wrong thing since the mode of such an
6823      expression is VOIDmode.
6824
6825      Also do nothing if X is a CLOBBER; this can happen if X was
6826      the return value from a call to gen_lowpart.  */
6827   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6828     return x;
6829
6830   /* We want to perform the operation is its present mode unless we know
6831      that the operation is valid in MODE, in which case we do the operation
6832      in MODE.  */
6833   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6834               && have_insn_for (code, mode))
6835              ? mode : GET_MODE (x));
6836
6837   /* It is not valid to do a right-shift in a narrower mode
6838      than the one it came in with.  */
6839   if ((code == LSHIFTRT || code == ASHIFTRT)
6840       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6841     op_mode = GET_MODE (x);
6842
6843   /* Truncate MASK to fit OP_MODE.  */
6844   if (op_mode)
6845     mask &= GET_MODE_MASK (op_mode);
6846
6847   /* When we have an arithmetic operation, or a shift whose count we
6848      do not know, we need to assume that all bits up to the highest-order
6849      bit in MASK will be needed.  This is how we form such a mask.  */
6850   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6851     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6852   else
6853     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6854                    - 1);
6855
6856   /* Determine what bits of X are guaranteed to be (non)zero.  */
6857   nonzero = nonzero_bits (x, mode);
6858
6859   /* If none of the bits in X are needed, return a zero.  */
6860   if (! just_select && (nonzero & mask) == 0)
6861     x = const0_rtx;
6862
6863   /* If X is a CONST_INT, return a new one.  Do this here since the
6864      test below will fail.  */
6865   if (GET_CODE (x) == CONST_INT)
6866     {
6867       if (SCALAR_INT_MODE_P (mode))
6868         return gen_int_mode (INTVAL (x) & mask, mode);
6869       else
6870         {
6871           x = GEN_INT (INTVAL (x) & mask);
6872           return gen_lowpart_common (mode, x);
6873         }
6874     }
6875
6876   /* If X is narrower than MODE and we want all the bits in X's mode, just
6877      get X in the proper mode.  */
6878   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6879       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6880     return gen_lowpart (mode, x);
6881
6882   switch (code)
6883     {
6884     case CLOBBER:
6885       /* If X is a (clobber (const_int)), return it since we know we are
6886          generating something that won't match.  */
6887       return x;
6888
6889     case USE:
6890       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6891          spanned the boundary of the MEM.  If we are now masking so it is
6892          within that boundary, we don't need the USE any more.  */
6893       if (! BITS_BIG_ENDIAN
6894           && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6895         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6896       break;
6897
6898     case SIGN_EXTEND:
6899     case ZERO_EXTEND:
6900     case ZERO_EXTRACT:
6901     case SIGN_EXTRACT:
6902       x = expand_compound_operation (x);
6903       if (GET_CODE (x) != code)
6904         return force_to_mode (x, mode, mask, next_select);
6905       break;
6906
6907     case SUBREG:
6908       if (subreg_lowpart_p (x)
6909           /* We can ignore the effect of this SUBREG if it narrows the mode or
6910              if the constant masks to zero all the bits the mode doesn't
6911              have.  */
6912           && ((GET_MODE_SIZE (GET_MODE (x))
6913                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6914               || (0 == (mask
6915                         & GET_MODE_MASK (GET_MODE (x))
6916                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6917         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6918       break;
6919
6920     case AND:
6921       /* If this is an AND with a constant, convert it into an AND
6922          whose constant is the AND of that constant with MASK.  If it
6923          remains an AND of MASK, delete it since it is redundant.  */
6924
6925       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6926         {
6927           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6928                                       mask & INTVAL (XEXP (x, 1)));
6929
6930           /* If X is still an AND, see if it is an AND with a mask that
6931              is just some low-order bits.  If so, and it is MASK, we don't
6932              need it.  */
6933
6934           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6935               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6936                   == mask))
6937             x = XEXP (x, 0);
6938
6939           /* If it remains an AND, try making another AND with the bits
6940              in the mode mask that aren't in MASK turned on.  If the
6941              constant in the AND is wide enough, this might make a
6942              cheaper constant.  */
6943
6944           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6945               && GET_MODE_MASK (GET_MODE (x)) != mask
6946               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6947             {
6948               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6949                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6950               int width = GET_MODE_BITSIZE (GET_MODE (x));
6951               rtx y;
6952
6953               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6954                  number, sign extend it.  */
6955               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6956                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6957                 cval |= (HOST_WIDE_INT) -1 << width;
6958
6959               y = simplify_gen_binary (AND, GET_MODE (x),
6960                                        XEXP (x, 0), GEN_INT (cval));
6961               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6962                 x = y;
6963             }
6964
6965           break;
6966         }
6967
6968       goto binop;
6969
6970     case PLUS:
6971       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6972          low-order bits (as in an alignment operation) and FOO is already
6973          aligned to that boundary, mask C1 to that boundary as well.
6974          This may eliminate that PLUS and, later, the AND.  */
6975
6976       {
6977         unsigned int width = GET_MODE_BITSIZE (mode);
6978         unsigned HOST_WIDE_INT smask = mask;
6979
6980         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6981            number, sign extend it.  */
6982
6983         if (width < HOST_BITS_PER_WIDE_INT
6984             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6985           smask |= (HOST_WIDE_INT) -1 << width;
6986
6987         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6988             && exact_log2 (- smask) >= 0
6989             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6990             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6991           return force_to_mode (plus_constant (XEXP (x, 0),
6992                                                (INTVAL (XEXP (x, 1)) & smask)),
6993                                 mode, smask, next_select);
6994       }
6995
6996       /* ... fall through ...  */
6997
6998     case MULT:
6999       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7000          most significant bit in MASK since carries from those bits will
7001          affect the bits we are interested in.  */
7002       mask = fuller_mask;
7003       goto binop;
7004
7005     case MINUS:
7006       /* If X is (minus C Y) where C's least set bit is larger than any bit
7007          in the mask, then we may replace with (neg Y).  */
7008       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7009           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7010                                         & -INTVAL (XEXP (x, 0))))
7011               > mask))
7012         {
7013           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7014                                   GET_MODE (x));
7015           return force_to_mode (x, mode, mask, next_select);
7016         }
7017
7018       /* Similarly, if C contains every bit in the fuller_mask, then we may
7019          replace with (not Y).  */
7020       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7021           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7022               == INTVAL (XEXP (x, 0))))
7023         {
7024           x = simplify_gen_unary (NOT, GET_MODE (x),
7025                                   XEXP (x, 1), GET_MODE (x));
7026           return force_to_mode (x, mode, mask, next_select);
7027         }
7028
7029       mask = fuller_mask;
7030       goto binop;
7031
7032     case IOR:
7033     case XOR:
7034       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7035          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7036          operation which may be a bitfield extraction.  Ensure that the
7037          constant we form is not wider than the mode of X.  */
7038
7039       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7040           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7041           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7042           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7043           && GET_CODE (XEXP (x, 1)) == CONST_INT
7044           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7045                + floor_log2 (INTVAL (XEXP (x, 1))))
7046               < GET_MODE_BITSIZE (GET_MODE (x)))
7047           && (INTVAL (XEXP (x, 1))
7048               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7049         {
7050           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7051                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7052           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7053                                       XEXP (XEXP (x, 0), 0), temp);
7054           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7055                                    XEXP (XEXP (x, 0), 1));
7056           return force_to_mode (x, mode, mask, next_select);
7057         }
7058
7059     binop:
7060       /* For most binary operations, just propagate into the operation and
7061          change the mode if we have an operation of that mode.  */
7062
7063       op0 = gen_lowpart_or_truncate (op_mode,
7064                                      force_to_mode (XEXP (x, 0), mode, mask,
7065                                                     next_select));
7066       op1 = gen_lowpart_or_truncate (op_mode,
7067                                      force_to_mode (XEXP (x, 1), mode, mask,
7068                                         next_select));
7069
7070       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7071         x = simplify_gen_binary (code, op_mode, op0, op1);
7072       break;
7073
7074     case ASHIFT:
7075       /* For left shifts, do the same, but just for the first operand.
7076          However, we cannot do anything with shifts where we cannot
7077          guarantee that the counts are smaller than the size of the mode
7078          because such a count will have a different meaning in a
7079          wider mode.  */
7080
7081       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7082              && INTVAL (XEXP (x, 1)) >= 0
7083              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7084           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7085                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7086                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7087         break;
7088
7089       /* If the shift count is a constant and we can do arithmetic in
7090          the mode of the shift, refine which bits we need.  Otherwise, use the
7091          conservative form of the mask.  */
7092       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7093           && INTVAL (XEXP (x, 1)) >= 0
7094           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7095           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7096         mask >>= INTVAL (XEXP (x, 1));
7097       else
7098         mask = fuller_mask;
7099
7100       op0 = gen_lowpart_or_truncate (op_mode,
7101                                      force_to_mode (XEXP (x, 0), op_mode,
7102                                                     mask, next_select));
7103
7104       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7105         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7106       break;
7107
7108     case LSHIFTRT:
7109       /* Here we can only do something if the shift count is a constant,
7110          this shift constant is valid for the host, and we can do arithmetic
7111          in OP_MODE.  */
7112
7113       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7114           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7115           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7116         {
7117           rtx inner = XEXP (x, 0);
7118           unsigned HOST_WIDE_INT inner_mask;
7119
7120           /* Select the mask of the bits we need for the shift operand.  */
7121           inner_mask = mask << INTVAL (XEXP (x, 1));
7122
7123           /* We can only change the mode of the shift if we can do arithmetic
7124              in the mode of the shift and INNER_MASK is no wider than the
7125              width of X's mode.  */
7126           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7127             op_mode = GET_MODE (x);
7128
7129           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7130
7131           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7132             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7133         }
7134
7135       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7136          shift and AND produces only copies of the sign bit (C2 is one less
7137          than a power of two), we can do this with just a shift.  */
7138
7139       if (GET_CODE (x) == LSHIFTRT
7140           && GET_CODE (XEXP (x, 1)) == CONST_INT
7141           /* The shift puts one of the sign bit copies in the least significant
7142              bit.  */
7143           && ((INTVAL (XEXP (x, 1))
7144                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7145               >= GET_MODE_BITSIZE (GET_MODE (x)))
7146           && exact_log2 (mask + 1) >= 0
7147           /* Number of bits left after the shift must be more than the mask
7148              needs.  */
7149           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7150               <= GET_MODE_BITSIZE (GET_MODE (x)))
7151           /* Must be more sign bit copies than the mask needs.  */
7152           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7153               >= exact_log2 (mask + 1)))
7154         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7155                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7156                                           - exact_log2 (mask + 1)));
7157
7158       goto shiftrt;
7159
7160     case ASHIFTRT:
7161       /* If we are just looking for the sign bit, we don't need this shift at
7162          all, even if it has a variable count.  */
7163       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7164           && (mask == ((unsigned HOST_WIDE_INT) 1
7165                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7166         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7167
7168       /* If this is a shift by a constant, get a mask that contains those bits
7169          that are not copies of the sign bit.  We then have two cases:  If
7170          MASK only includes those bits, this can be a logical shift, which may
7171          allow simplifications.  If MASK is a single-bit field not within
7172          those bits, we are requesting a copy of the sign bit and hence can
7173          shift the sign bit to the appropriate location.  */
7174
7175       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7176           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7177         {
7178           int i;
7179
7180           /* If the considered data is wider than HOST_WIDE_INT, we can't
7181              represent a mask for all its bits in a single scalar.
7182              But we only care about the lower bits, so calculate these.  */
7183
7184           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7185             {
7186               nonzero = ~(HOST_WIDE_INT) 0;
7187
7188               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7189                  is the number of bits a full-width mask would have set.
7190                  We need only shift if these are fewer than nonzero can
7191                  hold.  If not, we must keep all bits set in nonzero.  */
7192
7193               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7194                   < HOST_BITS_PER_WIDE_INT)
7195                 nonzero >>= INTVAL (XEXP (x, 1))
7196                             + HOST_BITS_PER_WIDE_INT
7197                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7198             }
7199           else
7200             {
7201               nonzero = GET_MODE_MASK (GET_MODE (x));
7202               nonzero >>= INTVAL (XEXP (x, 1));
7203             }
7204
7205           if ((mask & ~nonzero) == 0)
7206             {
7207               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7208                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7209               if (GET_CODE (x) != ASHIFTRT)
7210                 return force_to_mode (x, mode, mask, next_select);
7211             }
7212
7213           else if ((i = exact_log2 (mask)) >= 0)
7214             {
7215               x = simplify_shift_const
7216                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7217                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7218
7219               if (GET_CODE (x) != ASHIFTRT)
7220                 return force_to_mode (x, mode, mask, next_select);
7221             }
7222         }
7223
7224       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7225          even if the shift count isn't a constant.  */
7226       if (mask == 1)
7227         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7228                                  XEXP (x, 0), XEXP (x, 1));
7229
7230     shiftrt:
7231
7232       /* If this is a zero- or sign-extension operation that just affects bits
7233          we don't care about, remove it.  Be sure the call above returned
7234          something that is still a shift.  */
7235
7236       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7237           && GET_CODE (XEXP (x, 1)) == CONST_INT
7238           && INTVAL (XEXP (x, 1)) >= 0
7239           && (INTVAL (XEXP (x, 1))
7240               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7241           && GET_CODE (XEXP (x, 0)) == ASHIFT
7242           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7243         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7244                               next_select);
7245
7246       break;
7247
7248     case ROTATE:
7249     case ROTATERT:
7250       /* If the shift count is constant and we can do computations
7251          in the mode of X, compute where the bits we care about are.
7252          Otherwise, we can't do anything.  Don't change the mode of
7253          the shift or propagate MODE into the shift, though.  */
7254       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7255           && INTVAL (XEXP (x, 1)) >= 0)
7256         {
7257           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7258                                             GET_MODE (x), GEN_INT (mask),
7259                                             XEXP (x, 1));
7260           if (temp && GET_CODE (temp) == CONST_INT)
7261             SUBST (XEXP (x, 0),
7262                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7263                                   INTVAL (temp), next_select));
7264         }
7265       break;
7266
7267     case NEG:
7268       /* If we just want the low-order bit, the NEG isn't needed since it
7269          won't change the low-order bit.  */
7270       if (mask == 1)
7271         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7272
7273       /* We need any bits less significant than the most significant bit in
7274          MASK since carries from those bits will affect the bits we are
7275          interested in.  */
7276       mask = fuller_mask;
7277       goto unop;
7278
7279     case NOT:
7280       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7281          same as the XOR case above.  Ensure that the constant we form is not
7282          wider than the mode of X.  */
7283
7284       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7285           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7286           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7287           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7288               < GET_MODE_BITSIZE (GET_MODE (x)))
7289           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7290         {
7291           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7292                                GET_MODE (x));
7293           temp = simplify_gen_binary (XOR, GET_MODE (x),
7294                                       XEXP (XEXP (x, 0), 0), temp);
7295           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7296                                    temp, XEXP (XEXP (x, 0), 1));
7297
7298           return force_to_mode (x, mode, mask, next_select);
7299         }
7300
7301       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7302          use the full mask inside the NOT.  */
7303       mask = fuller_mask;
7304
7305     unop:
7306       op0 = gen_lowpart_or_truncate (op_mode,
7307                                      force_to_mode (XEXP (x, 0), mode, mask,
7308                                                     next_select));
7309       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7310         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7311       break;
7312
7313     case NE:
7314       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7315          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7316          which is equal to STORE_FLAG_VALUE.  */
7317       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7318           && GET_MODE (XEXP (x, 0)) == mode
7319           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7320           && (nonzero_bits (XEXP (x, 0), mode)
7321               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7322         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7323
7324       break;
7325
7326     case IF_THEN_ELSE:
7327       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7328          written in a narrower mode.  We play it safe and do not do so.  */
7329
7330       SUBST (XEXP (x, 1),
7331              gen_lowpart_or_truncate (GET_MODE (x),
7332                                       force_to_mode (XEXP (x, 1), mode,
7333                                                      mask, next_select)));
7334       SUBST (XEXP (x, 2),
7335              gen_lowpart_or_truncate (GET_MODE (x),
7336                                       force_to_mode (XEXP (x, 2), mode,
7337                                                      mask, next_select)));
7338       break;
7339
7340     default:
7341       break;
7342     }
7343
7344   /* Ensure we return a value of the proper mode.  */
7345   return gen_lowpart_or_truncate (mode, x);
7346 }
7347 \f
7348 /* Return nonzero if X is an expression that has one of two values depending on
7349    whether some other value is zero or nonzero.  In that case, we return the
7350    value that is being tested, *PTRUE is set to the value if the rtx being
7351    returned has a nonzero value, and *PFALSE is set to the other alternative.
7352
7353    If we return zero, we set *PTRUE and *PFALSE to X.  */
7354
7355 static rtx
7356 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7357 {
7358   enum machine_mode mode = GET_MODE (x);
7359   enum rtx_code code = GET_CODE (x);
7360   rtx cond0, cond1, true0, true1, false0, false1;
7361   unsigned HOST_WIDE_INT nz;
7362
7363   /* If we are comparing a value against zero, we are done.  */
7364   if ((code == NE || code == EQ)
7365       && XEXP (x, 1) == const0_rtx)
7366     {
7367       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7368       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7369       return XEXP (x, 0);
7370     }
7371
7372   /* If this is a unary operation whose operand has one of two values, apply
7373      our opcode to compute those values.  */
7374   else if (UNARY_P (x)
7375            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7376     {
7377       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7378       *pfalse = simplify_gen_unary (code, mode, false0,
7379                                     GET_MODE (XEXP (x, 0)));
7380       return cond0;
7381     }
7382
7383   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7384      make can't possibly match and would suppress other optimizations.  */
7385   else if (code == COMPARE)
7386     ;
7387
7388   /* If this is a binary operation, see if either side has only one of two
7389      values.  If either one does or if both do and they are conditional on
7390      the same value, compute the new true and false values.  */
7391   else if (BINARY_P (x))
7392     {
7393       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7394       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7395
7396       if ((cond0 != 0 || cond1 != 0)
7397           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7398         {
7399           /* If if_then_else_cond returned zero, then true/false are the
7400              same rtl.  We must copy one of them to prevent invalid rtl
7401              sharing.  */
7402           if (cond0 == 0)
7403             true0 = copy_rtx (true0);
7404           else if (cond1 == 0)
7405             true1 = copy_rtx (true1);
7406
7407           if (COMPARISON_P (x))
7408             {
7409               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7410                                                 true0, true1);
7411               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7412                                                  false0, false1);
7413              }
7414           else
7415             {
7416               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7417               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7418             }
7419
7420           return cond0 ? cond0 : cond1;
7421         }
7422
7423       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7424          operands is zero when the other is nonzero, and vice-versa,
7425          and STORE_FLAG_VALUE is 1 or -1.  */
7426
7427       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7428           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7429               || code == UMAX)
7430           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7431         {
7432           rtx op0 = XEXP (XEXP (x, 0), 1);
7433           rtx op1 = XEXP (XEXP (x, 1), 1);
7434
7435           cond0 = XEXP (XEXP (x, 0), 0);
7436           cond1 = XEXP (XEXP (x, 1), 0);
7437
7438           if (COMPARISON_P (cond0)
7439               && COMPARISON_P (cond1)
7440               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7441                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7442                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7443                   || ((swap_condition (GET_CODE (cond0))
7444                        == reversed_comparison_code (cond1, NULL))
7445                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7446                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7447               && ! side_effects_p (x))
7448             {
7449               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7450               *pfalse = simplify_gen_binary (MULT, mode,
7451                                              (code == MINUS
7452                                               ? simplify_gen_unary (NEG, mode,
7453                                                                     op1, mode)
7454                                               : op1),
7455                                               const_true_rtx);
7456               return cond0;
7457             }
7458         }
7459
7460       /* Similarly for MULT, AND and UMIN, except that for these the result
7461          is always zero.  */
7462       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7463           && (code == MULT || code == AND || code == UMIN)
7464           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7465         {
7466           cond0 = XEXP (XEXP (x, 0), 0);
7467           cond1 = XEXP (XEXP (x, 1), 0);
7468
7469           if (COMPARISON_P (cond0)
7470               && COMPARISON_P (cond1)
7471               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7472                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7473                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7474                   || ((swap_condition (GET_CODE (cond0))
7475                        == reversed_comparison_code (cond1, NULL))
7476                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7477                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7478               && ! side_effects_p (x))
7479             {
7480               *ptrue = *pfalse = const0_rtx;
7481               return cond0;
7482             }
7483         }
7484     }
7485
7486   else if (code == IF_THEN_ELSE)
7487     {
7488       /* If we have IF_THEN_ELSE already, extract the condition and
7489          canonicalize it if it is NE or EQ.  */
7490       cond0 = XEXP (x, 0);
7491       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7492       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7493         return XEXP (cond0, 0);
7494       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7495         {
7496           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7497           return XEXP (cond0, 0);
7498         }
7499       else
7500         return cond0;
7501     }
7502
7503   /* If X is a SUBREG, we can narrow both the true and false values
7504      if the inner expression, if there is a condition.  */
7505   else if (code == SUBREG
7506            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7507                                                &true0, &false0)))
7508     {
7509       true0 = simplify_gen_subreg (mode, true0,
7510                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7511       false0 = simplify_gen_subreg (mode, false0,
7512                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7513       if (true0 && false0)
7514         {
7515           *ptrue = true0;
7516           *pfalse = false0;
7517           return cond0;
7518         }
7519     }
7520
7521   /* If X is a constant, this isn't special and will cause confusions
7522      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7523   else if (CONSTANT_P (x)
7524            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7525     ;
7526
7527   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7528      will be least confusing to the rest of the compiler.  */
7529   else if (mode == BImode)
7530     {
7531       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7532       return x;
7533     }
7534
7535   /* If X is known to be either 0 or -1, those are the true and
7536      false values when testing X.  */
7537   else if (x == constm1_rtx || x == const0_rtx
7538            || (mode != VOIDmode
7539                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7540     {
7541       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7542       return x;
7543     }
7544
7545   /* Likewise for 0 or a single bit.  */
7546   else if (SCALAR_INT_MODE_P (mode)
7547            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7548            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7549     {
7550       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7551       return x;
7552     }
7553
7554   /* Otherwise fail; show no condition with true and false values the same.  */
7555   *ptrue = *pfalse = x;
7556   return 0;
7557 }
7558 \f
7559 /* Return the value of expression X given the fact that condition COND
7560    is known to be true when applied to REG as its first operand and VAL
7561    as its second.  X is known to not be shared and so can be modified in
7562    place.
7563
7564    We only handle the simplest cases, and specifically those cases that
7565    arise with IF_THEN_ELSE expressions.  */
7566
7567 static rtx
7568 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7569 {
7570   enum rtx_code code = GET_CODE (x);
7571   rtx temp;
7572   const char *fmt;
7573   int i, j;
7574
7575   if (side_effects_p (x))
7576     return x;
7577
7578   /* If either operand of the condition is a floating point value,
7579      then we have to avoid collapsing an EQ comparison.  */
7580   if (cond == EQ
7581       && rtx_equal_p (x, reg)
7582       && ! FLOAT_MODE_P (GET_MODE (x))
7583       && ! FLOAT_MODE_P (GET_MODE (val)))
7584     return val;
7585
7586   if (cond == UNEQ && rtx_equal_p (x, reg))
7587     return val;
7588
7589   /* If X is (abs REG) and we know something about REG's relationship
7590      with zero, we may be able to simplify this.  */
7591
7592   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7593     switch (cond)
7594       {
7595       case GE:  case GT:  case EQ:
7596         return XEXP (x, 0);
7597       case LT:  case LE:
7598         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7599                                    XEXP (x, 0),
7600                                    GET_MODE (XEXP (x, 0)));
7601       default:
7602         break;
7603       }
7604
7605   /* The only other cases we handle are MIN, MAX, and comparisons if the
7606      operands are the same as REG and VAL.  */
7607
7608   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7609     {
7610       if (rtx_equal_p (XEXP (x, 0), val))
7611         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7612
7613       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7614         {
7615           if (COMPARISON_P (x))
7616             {
7617               if (comparison_dominates_p (cond, code))
7618                 return const_true_rtx;
7619
7620               code = reversed_comparison_code (x, NULL);
7621               if (code != UNKNOWN
7622                   && comparison_dominates_p (cond, code))
7623                 return const0_rtx;
7624               else
7625                 return x;
7626             }
7627           else if (code == SMAX || code == SMIN
7628                    || code == UMIN || code == UMAX)
7629             {
7630               int unsignedp = (code == UMIN || code == UMAX);
7631
7632               /* Do not reverse the condition when it is NE or EQ.
7633                  This is because we cannot conclude anything about
7634                  the value of 'SMAX (x, y)' when x is not equal to y,
7635                  but we can when x equals y.  */
7636               if ((code == SMAX || code == UMAX)
7637                   && ! (cond == EQ || cond == NE))
7638                 cond = reverse_condition (cond);
7639
7640               switch (cond)
7641                 {
7642                 case GE:   case GT:
7643                   return unsignedp ? x : XEXP (x, 1);
7644                 case LE:   case LT:
7645                   return unsignedp ? x : XEXP (x, 0);
7646                 case GEU:  case GTU:
7647                   return unsignedp ? XEXP (x, 1) : x;
7648                 case LEU:  case LTU:
7649                   return unsignedp ? XEXP (x, 0) : x;
7650                 default:
7651                   break;
7652                 }
7653             }
7654         }
7655     }
7656   else if (code == SUBREG)
7657     {
7658       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7659       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7660
7661       if (SUBREG_REG (x) != r)
7662         {
7663           /* We must simplify subreg here, before we lose track of the
7664              original inner_mode.  */
7665           new = simplify_subreg (GET_MODE (x), r,
7666                                  inner_mode, SUBREG_BYTE (x));
7667           if (new)
7668             return new;
7669           else
7670             SUBST (SUBREG_REG (x), r);
7671         }
7672
7673       return x;
7674     }
7675   /* We don't have to handle SIGN_EXTEND here, because even in the
7676      case of replacing something with a modeless CONST_INT, a
7677      CONST_INT is already (supposed to be) a valid sign extension for
7678      its narrower mode, which implies it's already properly
7679      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7680      story is different.  */
7681   else if (code == ZERO_EXTEND)
7682     {
7683       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7684       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7685
7686       if (XEXP (x, 0) != r)
7687         {
7688           /* We must simplify the zero_extend here, before we lose
7689              track of the original inner_mode.  */
7690           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7691                                           r, inner_mode);
7692           if (new)
7693             return new;
7694           else
7695             SUBST (XEXP (x, 0), r);
7696         }
7697
7698       return x;
7699     }
7700
7701   fmt = GET_RTX_FORMAT (code);
7702   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7703     {
7704       if (fmt[i] == 'e')
7705         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7706       else if (fmt[i] == 'E')
7707         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7708           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7709                                                 cond, reg, val));
7710     }
7711
7712   return x;
7713 }
7714 \f
7715 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7716    assignment as a field assignment.  */
7717
7718 static int
7719 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7720 {
7721   if (x == y || rtx_equal_p (x, y))
7722     return 1;
7723
7724   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7725     return 0;
7726
7727   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7728      Note that all SUBREGs of MEM are paradoxical; otherwise they
7729      would have been rewritten.  */
7730   if (MEM_P (x) && GET_CODE (y) == SUBREG
7731       && MEM_P (SUBREG_REG (y))
7732       && rtx_equal_p (SUBREG_REG (y),
7733                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7734     return 1;
7735
7736   if (MEM_P (y) && GET_CODE (x) == SUBREG
7737       && MEM_P (SUBREG_REG (x))
7738       && rtx_equal_p (SUBREG_REG (x),
7739                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7740     return 1;
7741
7742   /* We used to see if get_last_value of X and Y were the same but that's
7743      not correct.  In one direction, we'll cause the assignment to have
7744      the wrong destination and in the case, we'll import a register into this
7745      insn that might have already have been dead.   So fail if none of the
7746      above cases are true.  */
7747   return 0;
7748 }
7749 \f
7750 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7751    Return that assignment if so.
7752
7753    We only handle the most common cases.  */
7754
7755 static rtx
7756 make_field_assignment (rtx x)
7757 {
7758   rtx dest = SET_DEST (x);
7759   rtx src = SET_SRC (x);
7760   rtx assign;
7761   rtx rhs, lhs;
7762   HOST_WIDE_INT c1;
7763   HOST_WIDE_INT pos;
7764   unsigned HOST_WIDE_INT len;
7765   rtx other;
7766   enum machine_mode mode;
7767
7768   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7769      a clear of a one-bit field.  We will have changed it to
7770      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7771      for a SUBREG.  */
7772
7773   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7774       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7775       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7776       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7777     {
7778       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7779                                 1, 1, 1, 0);
7780       if (assign != 0)
7781         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7782       return x;
7783     }
7784
7785   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7786       && subreg_lowpart_p (XEXP (src, 0))
7787       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7788           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7789       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7790       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7791       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7792       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7793     {
7794       assign = make_extraction (VOIDmode, dest, 0,
7795                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7796                                 1, 1, 1, 0);
7797       if (assign != 0)
7798         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7799       return x;
7800     }
7801
7802   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7803      one-bit field.  */
7804   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7805       && XEXP (XEXP (src, 0), 0) == const1_rtx
7806       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7807     {
7808       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7809                                 1, 1, 1, 0);
7810       if (assign != 0)
7811         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7812       return x;
7813     }
7814
7815   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7816      SRC is an AND with all bits of that field set, then we can discard
7817      the AND.  */
7818   if (GET_CODE (dest) == ZERO_EXTRACT
7819       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7820       && GET_CODE (src) == AND
7821       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7822     {
7823       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7824       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7825       unsigned HOST_WIDE_INT ze_mask;
7826
7827       if (width >= HOST_BITS_PER_WIDE_INT)
7828         ze_mask = -1;
7829       else
7830         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7831
7832       /* Complete overlap.  We can remove the source AND.  */
7833       if ((and_mask & ze_mask) == ze_mask)
7834         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7835
7836       /* Partial overlap.  We can reduce the source AND.  */
7837       if ((and_mask & ze_mask) != and_mask)
7838         {
7839           mode = GET_MODE (src);
7840           src = gen_rtx_AND (mode, XEXP (src, 0),
7841                              gen_int_mode (and_mask & ze_mask, mode));
7842           return gen_rtx_SET (VOIDmode, dest, src);
7843         }
7844     }
7845
7846   /* The other case we handle is assignments into a constant-position
7847      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7848      a mask that has all one bits except for a group of zero bits and
7849      OTHER is known to have zeros where C1 has ones, this is such an
7850      assignment.  Compute the position and length from C1.  Shift OTHER
7851      to the appropriate position, force it to the required mode, and
7852      make the extraction.  Check for the AND in both operands.  */
7853
7854   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7855     return x;
7856
7857   rhs = expand_compound_operation (XEXP (src, 0));
7858   lhs = expand_compound_operation (XEXP (src, 1));
7859
7860   if (GET_CODE (rhs) == AND
7861       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7862       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7863     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7864   else if (GET_CODE (lhs) == AND
7865            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7866            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7867     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7868   else
7869     return x;
7870
7871   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7872   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7873       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7874       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7875     return x;
7876
7877   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7878   if (assign == 0)
7879     return x;
7880
7881   /* The mode to use for the source is the mode of the assignment, or of
7882      what is inside a possible STRICT_LOW_PART.  */
7883   mode = (GET_CODE (assign) == STRICT_LOW_PART
7884           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7885
7886   /* Shift OTHER right POS places and make it the source, restricting it
7887      to the proper length and mode.  */
7888
7889   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7890                                                      GET_MODE (src),
7891                                                      other, pos),
7892                                dest);
7893   src = force_to_mode (src, mode,
7894                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7895                        ? ~(unsigned HOST_WIDE_INT) 0
7896                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7897                        0);
7898
7899   /* If SRC is masked by an AND that does not make a difference in
7900      the value being stored, strip it.  */
7901   if (GET_CODE (assign) == ZERO_EXTRACT
7902       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7903       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7904       && GET_CODE (src) == AND
7905       && GET_CODE (XEXP (src, 1)) == CONST_INT
7906       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7907           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7908     src = XEXP (src, 0);
7909
7910   return gen_rtx_SET (VOIDmode, assign, src);
7911 }
7912 \f
7913 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7914    if so.  */
7915
7916 static rtx
7917 apply_distributive_law (rtx x)
7918 {
7919   enum rtx_code code = GET_CODE (x);
7920   enum rtx_code inner_code;
7921   rtx lhs, rhs, other;
7922   rtx tem;
7923
7924   /* Distributivity is not true for floating point as it can change the
7925      value.  So we don't do it unless -funsafe-math-optimizations.  */
7926   if (FLOAT_MODE_P (GET_MODE (x))
7927       && ! flag_unsafe_math_optimizations)
7928     return x;
7929
7930   /* The outer operation can only be one of the following:  */
7931   if (code != IOR && code != AND && code != XOR
7932       && code != PLUS && code != MINUS)
7933     return x;
7934
7935   lhs = XEXP (x, 0);
7936   rhs = XEXP (x, 1);
7937
7938   /* If either operand is a primitive we can't do anything, so get out
7939      fast.  */
7940   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7941     return x;
7942
7943   lhs = expand_compound_operation (lhs);
7944   rhs = expand_compound_operation (rhs);
7945   inner_code = GET_CODE (lhs);
7946   if (inner_code != GET_CODE (rhs))
7947     return x;
7948
7949   /* See if the inner and outer operations distribute.  */
7950   switch (inner_code)
7951     {
7952     case LSHIFTRT:
7953     case ASHIFTRT:
7954     case AND:
7955     case IOR:
7956       /* These all distribute except over PLUS.  */
7957       if (code == PLUS || code == MINUS)
7958         return x;
7959       break;
7960
7961     case MULT:
7962       if (code != PLUS && code != MINUS)
7963         return x;
7964       break;
7965
7966     case ASHIFT:
7967       /* This is also a multiply, so it distributes over everything.  */
7968       break;
7969
7970     case SUBREG:
7971       /* Non-paradoxical SUBREGs distributes over all operations,
7972          provided the inner modes and byte offsets are the same, this
7973          is an extraction of a low-order part, we don't convert an fp
7974          operation to int or vice versa, this is not a vector mode,
7975          and we would not be converting a single-word operation into a
7976          multi-word operation.  The latter test is not required, but
7977          it prevents generating unneeded multi-word operations.  Some
7978          of the previous tests are redundant given the latter test,
7979          but are retained because they are required for correctness.
7980
7981          We produce the result slightly differently in this case.  */
7982
7983       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7984           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7985           || ! subreg_lowpart_p (lhs)
7986           || (GET_MODE_CLASS (GET_MODE (lhs))
7987               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7988           || (GET_MODE_SIZE (GET_MODE (lhs))
7989               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7990           || VECTOR_MODE_P (GET_MODE (lhs))
7991           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7992           /* Result might need to be truncated.  Don't change mode if
7993              explicit truncation is needed.  */
7994           || !TRULY_NOOP_TRUNCATION
7995                (GET_MODE_BITSIZE (GET_MODE (x)),
7996                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7997         return x;
7998
7999       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8000                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8001       return gen_lowpart (GET_MODE (x), tem);
8002
8003     default:
8004       return x;
8005     }
8006
8007   /* Set LHS and RHS to the inner operands (A and B in the example
8008      above) and set OTHER to the common operand (C in the example).
8009      There is only one way to do this unless the inner operation is
8010      commutative.  */
8011   if (COMMUTATIVE_ARITH_P (lhs)
8012       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8013     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8014   else if (COMMUTATIVE_ARITH_P (lhs)
8015            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8016     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8017   else if (COMMUTATIVE_ARITH_P (lhs)
8018            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8019     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8020   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8021     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8022   else
8023     return x;
8024
8025   /* Form the new inner operation, seeing if it simplifies first.  */
8026   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8027
8028   /* There is one exception to the general way of distributing:
8029      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8030   if (code == XOR && inner_code == IOR)
8031     {
8032       inner_code = AND;
8033       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8034     }
8035
8036   /* We may be able to continuing distributing the result, so call
8037      ourselves recursively on the inner operation before forming the
8038      outer operation, which we return.  */
8039   return simplify_gen_binary (inner_code, GET_MODE (x),
8040                               apply_distributive_law (tem), other);
8041 }
8042
8043 /* See if X is of the form (* (+ A B) C), and if so convert to
8044    (+ (* A C) (* B C)) and try to simplify.
8045
8046    Most of the time, this results in no change.  However, if some of
8047    the operands are the same or inverses of each other, simplifications
8048    will result.
8049
8050    For example, (and (ior A B) (not B)) can occur as the result of
8051    expanding a bit field assignment.  When we apply the distributive
8052    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8053    which then simplifies to (and (A (not B))).
8054
8055    Note that no checks happen on the validity of applying the inverse
8056    distributive law.  This is pointless since we can do it in the
8057    few places where this routine is called.
8058
8059    N is the index of the term that is decomposed (the arithmetic operation,
8060    i.e. (+ A B) in the first example above).  !N is the index of the term that
8061    is distributed, i.e. of C in the first example above.  */
8062 static rtx
8063 distribute_and_simplify_rtx (rtx x, int n)
8064 {
8065   enum machine_mode mode;
8066   enum rtx_code outer_code, inner_code;
8067   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8068
8069   decomposed = XEXP (x, n);
8070   if (!ARITHMETIC_P (decomposed))
8071     return NULL_RTX;
8072
8073   mode = GET_MODE (x);
8074   outer_code = GET_CODE (x);
8075   distributed = XEXP (x, !n);
8076
8077   inner_code = GET_CODE (decomposed);
8078   inner_op0 = XEXP (decomposed, 0);
8079   inner_op1 = XEXP (decomposed, 1);
8080
8081   /* Special case (and (xor B C) (not A)), which is equivalent to
8082      (xor (ior A B) (ior A C))  */
8083   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8084     {
8085       distributed = XEXP (distributed, 0);
8086       outer_code = IOR;
8087     }
8088
8089   if (n == 0)
8090     {
8091       /* Distribute the second term.  */
8092       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8093       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8094     }
8095   else
8096     {
8097       /* Distribute the first term.  */
8098       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8099       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8100     }
8101
8102   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8103                                                      new_op0, new_op1));
8104   if (GET_CODE (tmp) != outer_code
8105       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8106     return tmp;
8107
8108   return NULL_RTX;
8109 }
8110 \f
8111 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8112    in MODE.  Return an equivalent form, if different from (and VAROP
8113    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8114
8115 static rtx
8116 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8117                           unsigned HOST_WIDE_INT constop)
8118 {
8119   unsigned HOST_WIDE_INT nonzero;
8120   unsigned HOST_WIDE_INT orig_constop;
8121   rtx orig_varop;
8122   int i;
8123
8124   orig_varop = varop;
8125   orig_constop = constop;
8126   if (GET_CODE (varop) == CLOBBER)
8127     return NULL_RTX;
8128
8129   /* Simplify VAROP knowing that we will be only looking at some of the
8130      bits in it.
8131
8132      Note by passing in CONSTOP, we guarantee that the bits not set in
8133      CONSTOP are not significant and will never be examined.  We must
8134      ensure that is the case by explicitly masking out those bits
8135      before returning.  */
8136   varop = force_to_mode (varop, mode, constop, 0);
8137
8138   /* If VAROP is a CLOBBER, we will fail so return it.  */
8139   if (GET_CODE (varop) == CLOBBER)
8140     return varop;
8141
8142   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8143      to VAROP and return the new constant.  */
8144   if (GET_CODE (varop) == CONST_INT)
8145     return gen_int_mode (INTVAL (varop) & constop, mode);
8146
8147   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8148      a call to nonzero_bits, here we don't care about bits outside
8149      MODE.  */
8150
8151   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8152
8153   /* Turn off all bits in the constant that are known to already be zero.
8154      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8155      which is tested below.  */
8156
8157   constop &= nonzero;
8158
8159   /* If we don't have any bits left, return zero.  */
8160   if (constop == 0)
8161     return const0_rtx;
8162
8163   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8164      a power of two, we can replace this with an ASHIFT.  */
8165   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8166       && (i = exact_log2 (constop)) >= 0)
8167     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8168
8169   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8170      or XOR, then try to apply the distributive law.  This may eliminate
8171      operations if either branch can be simplified because of the AND.
8172      It may also make some cases more complex, but those cases probably
8173      won't match a pattern either with or without this.  */
8174
8175   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8176     return
8177       gen_lowpart
8178         (mode,
8179          apply_distributive_law
8180          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8181                                simplify_and_const_int (NULL_RTX,
8182                                                        GET_MODE (varop),
8183                                                        XEXP (varop, 0),
8184                                                        constop),
8185                                simplify_and_const_int (NULL_RTX,
8186                                                        GET_MODE (varop),
8187                                                        XEXP (varop, 1),
8188                                                        constop))));
8189
8190   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8191      the AND and see if one of the operands simplifies to zero.  If so, we
8192      may eliminate it.  */
8193
8194   if (GET_CODE (varop) == PLUS
8195       && exact_log2 (constop + 1) >= 0)
8196     {
8197       rtx o0, o1;
8198
8199       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8200       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8201       if (o0 == const0_rtx)
8202         return o1;
8203       if (o1 == const0_rtx)
8204         return o0;
8205     }
8206
8207   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8208   varop = gen_lowpart (mode, varop);
8209   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8210     return NULL_RTX;
8211
8212   /* If we are only masking insignificant bits, return VAROP.  */
8213   if (constop == nonzero)
8214     return varop;
8215
8216   if (varop == orig_varop && constop == orig_constop)
8217     return NULL_RTX;
8218
8219   /* Otherwise, return an AND.  */
8220   constop = trunc_int_for_mode (constop, mode);
8221   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8222 }
8223
8224
8225 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8226    in MODE.
8227
8228    Return an equivalent form, if different from X.  Otherwise, return X.  If
8229    X is zero, we are to always construct the equivalent form.  */
8230
8231 static rtx
8232 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8233                         unsigned HOST_WIDE_INT constop)
8234 {
8235   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8236   if (tem)
8237     return tem;
8238
8239   if (!x)
8240     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8241   if (GET_MODE (x) != mode)
8242     x = gen_lowpart (mode, x);
8243   return x;
8244 }
8245 \f
8246 /* Given a REG, X, compute which bits in X can be nonzero.
8247    We don't care about bits outside of those defined in MODE.
8248
8249    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8250    a shift, AND, or zero_extract, we can do better.  */
8251
8252 static rtx
8253 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8254                               rtx known_x ATTRIBUTE_UNUSED,
8255                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8256                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8257                               unsigned HOST_WIDE_INT *nonzero)
8258 {
8259   rtx tem;
8260
8261   /* If X is a register whose nonzero bits value is current, use it.
8262      Otherwise, if X is a register whose value we can find, use that
8263      value.  Otherwise, use the previously-computed global nonzero bits
8264      for this register.  */
8265
8266   if (reg_stat[REGNO (x)].last_set_value != 0
8267       && (reg_stat[REGNO (x)].last_set_mode == mode
8268           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8269               && GET_MODE_CLASS (mode) == MODE_INT))
8270       && (reg_stat[REGNO (x)].last_set_label == label_tick
8271           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8272               && REG_N_SETS (REGNO (x)) == 1
8273               && ! REGNO_REG_SET_P
8274                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8275                   REGNO (x))))
8276       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8277     {
8278       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8279       return NULL;
8280     }
8281
8282   tem = get_last_value (x);
8283
8284   if (tem)
8285     {
8286 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8287       /* If X is narrower than MODE and TEM is a non-negative
8288          constant that would appear negative in the mode of X,
8289          sign-extend it for use in reg_nonzero_bits because some
8290          machines (maybe most) will actually do the sign-extension
8291          and this is the conservative approach.
8292
8293          ??? For 2.5, try to tighten up the MD files in this regard
8294          instead of this kludge.  */
8295
8296       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8297           && GET_CODE (tem) == CONST_INT
8298           && INTVAL (tem) > 0
8299           && 0 != (INTVAL (tem)
8300                    & ((HOST_WIDE_INT) 1
8301                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8302         tem = GEN_INT (INTVAL (tem)
8303                        | ((HOST_WIDE_INT) (-1)
8304                           << GET_MODE_BITSIZE (GET_MODE (x))));
8305 #endif
8306       return tem;
8307     }
8308   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8309     {
8310       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8311
8312       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8313         /* We don't know anything about the upper bits.  */
8314         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8315       *nonzero &= mask;
8316     }
8317
8318   return NULL;
8319 }
8320
8321 /* Return the number of bits at the high-order end of X that are known to
8322    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8323    VOIDmode, X will be used in its own mode.  The returned value  will always
8324    be between 1 and the number of bits in MODE.  */
8325
8326 static rtx
8327 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8328                                      rtx known_x ATTRIBUTE_UNUSED,
8329                                      enum machine_mode known_mode
8330                                      ATTRIBUTE_UNUSED,
8331                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8332                                      unsigned int *result)
8333 {
8334   rtx tem;
8335
8336   if (reg_stat[REGNO (x)].last_set_value != 0
8337       && reg_stat[REGNO (x)].last_set_mode == mode
8338       && (reg_stat[REGNO (x)].last_set_label == label_tick
8339           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8340               && REG_N_SETS (REGNO (x)) == 1
8341               && ! REGNO_REG_SET_P
8342                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8343                   REGNO (x))))
8344       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8345     {
8346       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8347       return NULL;
8348     }
8349
8350   tem = get_last_value (x);
8351   if (tem != 0)
8352     return tem;
8353
8354   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8355       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8356     *result = reg_stat[REGNO (x)].sign_bit_copies;
8357
8358   return NULL;
8359 }
8360 \f
8361 /* Return the number of "extended" bits there are in X, when interpreted
8362    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8363    unsigned quantities, this is the number of high-order zero bits.
8364    For signed quantities, this is the number of copies of the sign bit
8365    minus 1.  In both case, this function returns the number of "spare"
8366    bits.  For example, if two quantities for which this function returns
8367    at least 1 are added, the addition is known not to overflow.
8368
8369    This function will always return 0 unless called during combine, which
8370    implies that it must be called from a define_split.  */
8371
8372 unsigned int
8373 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8374 {
8375   if (nonzero_sign_valid == 0)
8376     return 0;
8377
8378   return (unsignedp
8379           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8380              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8381                                - floor_log2 (nonzero_bits (x, mode)))
8382              : 0)
8383           : num_sign_bit_copies (x, mode) - 1);
8384 }
8385 \f
8386 /* This function is called from `simplify_shift_const' to merge two
8387    outer operations.  Specifically, we have already found that we need
8388    to perform operation *POP0 with constant *PCONST0 at the outermost
8389    position.  We would now like to also perform OP1 with constant CONST1
8390    (with *POP0 being done last).
8391
8392    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8393    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8394    complement the innermost operand, otherwise it is unchanged.
8395
8396    MODE is the mode in which the operation will be done.  No bits outside
8397    the width of this mode matter.  It is assumed that the width of this mode
8398    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8399
8400    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8401    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8402    result is simply *PCONST0.
8403
8404    If the resulting operation cannot be expressed as one operation, we
8405    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8406
8407 static int
8408 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8409 {
8410   enum rtx_code op0 = *pop0;
8411   HOST_WIDE_INT const0 = *pconst0;
8412
8413   const0 &= GET_MODE_MASK (mode);
8414   const1 &= GET_MODE_MASK (mode);
8415
8416   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8417   if (op0 == AND)
8418     const1 &= const0;
8419
8420   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8421      if OP0 is SET.  */
8422
8423   if (op1 == UNKNOWN || op0 == SET)
8424     return 1;
8425
8426   else if (op0 == UNKNOWN)
8427     op0 = op1, const0 = const1;
8428
8429   else if (op0 == op1)
8430     {
8431       switch (op0)
8432         {
8433         case AND:
8434           const0 &= const1;
8435           break;
8436         case IOR:
8437           const0 |= const1;
8438           break;
8439         case XOR:
8440           const0 ^= const1;
8441           break;
8442         case PLUS:
8443           const0 += const1;
8444           break;
8445         case NEG:
8446           op0 = UNKNOWN;
8447           break;
8448         default:
8449           break;
8450         }
8451     }
8452
8453   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8454   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8455     return 0;
8456
8457   /* If the two constants aren't the same, we can't do anything.  The
8458      remaining six cases can all be done.  */
8459   else if (const0 != const1)
8460     return 0;
8461
8462   else
8463     switch (op0)
8464       {
8465       case IOR:
8466         if (op1 == AND)
8467           /* (a & b) | b == b */
8468           op0 = SET;
8469         else /* op1 == XOR */
8470           /* (a ^ b) | b == a | b */
8471           {;}
8472         break;
8473
8474       case XOR:
8475         if (op1 == AND)
8476           /* (a & b) ^ b == (~a) & b */
8477           op0 = AND, *pcomp_p = 1;
8478         else /* op1 == IOR */
8479           /* (a | b) ^ b == a & ~b */
8480           op0 = AND, const0 = ~const0;
8481         break;
8482
8483       case AND:
8484         if (op1 == IOR)
8485           /* (a | b) & b == b */
8486         op0 = SET;
8487         else /* op1 == XOR */
8488           /* (a ^ b) & b) == (~a) & b */
8489           *pcomp_p = 1;
8490         break;
8491       default:
8492         break;
8493       }
8494
8495   /* Check for NO-OP cases.  */
8496   const0 &= GET_MODE_MASK (mode);
8497   if (const0 == 0
8498       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8499     op0 = UNKNOWN;
8500   else if (const0 == 0 && op0 == AND)
8501     op0 = SET;
8502   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8503            && op0 == AND)
8504     op0 = UNKNOWN;
8505
8506   /* ??? Slightly redundant with the above mask, but not entirely.
8507      Moving this above means we'd have to sign-extend the mode mask
8508      for the final test.  */
8509   const0 = trunc_int_for_mode (const0, mode);
8510
8511   *pop0 = op0;
8512   *pconst0 = const0;
8513
8514   return 1;
8515 }
8516 \f
8517 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8518    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8519    simplify it.  Otherwise, return a simplified value.
8520
8521    The shift is normally computed in the widest mode we find in VAROP, as
8522    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8523    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8524
8525 static rtx
8526 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8527                         rtx varop, int orig_count)
8528 {
8529   enum rtx_code orig_code = code;
8530   rtx orig_varop = varop;
8531   int count;
8532   enum machine_mode mode = result_mode;
8533   enum machine_mode shift_mode, tmode;
8534   unsigned int mode_words
8535     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8536   /* We form (outer_op (code varop count) (outer_const)).  */
8537   enum rtx_code outer_op = UNKNOWN;
8538   HOST_WIDE_INT outer_const = 0;
8539   int complement_p = 0;
8540   rtx new, x;
8541
8542   /* Make sure and truncate the "natural" shift on the way in.  We don't
8543      want to do this inside the loop as it makes it more difficult to
8544      combine shifts.  */
8545   if (SHIFT_COUNT_TRUNCATED)
8546     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8547
8548   /* If we were given an invalid count, don't do anything except exactly
8549      what was requested.  */
8550
8551   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8552     return NULL_RTX;
8553
8554   count = orig_count;
8555
8556   /* Unless one of the branches of the `if' in this loop does a `continue',
8557      we will `break' the loop after the `if'.  */
8558
8559   while (count != 0)
8560     {
8561       /* If we have an operand of (clobber (const_int 0)), fail.  */
8562       if (GET_CODE (varop) == CLOBBER)
8563         return NULL_RTX;
8564
8565       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8566          here would cause an infinite loop.  */
8567       if (complement_p)
8568         break;
8569
8570       /* Convert ROTATERT to ROTATE.  */
8571       if (code == ROTATERT)
8572         {
8573           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8574           code = ROTATE;
8575           if (VECTOR_MODE_P (result_mode))
8576             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8577           else
8578             count = bitsize - count;
8579         }
8580
8581       /* We need to determine what mode we will do the shift in.  If the
8582          shift is a right shift or a ROTATE, we must always do it in the mode
8583          it was originally done in.  Otherwise, we can do it in MODE, the
8584          widest mode encountered.  */
8585       shift_mode
8586         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8587            ? result_mode : mode);
8588
8589       /* Handle cases where the count is greater than the size of the mode
8590          minus 1.  For ASHIFT, use the size minus one as the count (this can
8591          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8592          take the count modulo the size.  For other shifts, the result is
8593          zero.
8594
8595          Since these shifts are being produced by the compiler by combining
8596          multiple operations, each of which are defined, we know what the
8597          result is supposed to be.  */
8598
8599       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8600         {
8601           if (code == ASHIFTRT)
8602             count = GET_MODE_BITSIZE (shift_mode) - 1;
8603           else if (code == ROTATE || code == ROTATERT)
8604             count %= GET_MODE_BITSIZE (shift_mode);
8605           else
8606             {
8607               /* We can't simply return zero because there may be an
8608                  outer op.  */
8609               varop = const0_rtx;
8610               count = 0;
8611               break;
8612             }
8613         }
8614
8615       /* An arithmetic right shift of a quantity known to be -1 or 0
8616          is a no-op.  */
8617       if (code == ASHIFTRT
8618           && (num_sign_bit_copies (varop, shift_mode)
8619               == GET_MODE_BITSIZE (shift_mode)))
8620         {
8621           count = 0;
8622           break;
8623         }
8624
8625       /* If we are doing an arithmetic right shift and discarding all but
8626          the sign bit copies, this is equivalent to doing a shift by the
8627          bitsize minus one.  Convert it into that shift because it will often
8628          allow other simplifications.  */
8629
8630       if (code == ASHIFTRT
8631           && (count + num_sign_bit_copies (varop, shift_mode)
8632               >= GET_MODE_BITSIZE (shift_mode)))
8633         count = GET_MODE_BITSIZE (shift_mode) - 1;
8634
8635       /* We simplify the tests below and elsewhere by converting
8636          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8637          `make_compound_operation' will convert it to an ASHIFTRT for
8638          those machines (such as VAX) that don't have an LSHIFTRT.  */
8639       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8640           && code == ASHIFTRT
8641           && ((nonzero_bits (varop, shift_mode)
8642                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8643               == 0))
8644         code = LSHIFTRT;
8645
8646       if (code == LSHIFTRT
8647           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8648           && !(nonzero_bits (varop, shift_mode) >> count))
8649         varop = const0_rtx;
8650       if (code == ASHIFT
8651           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8652           && !((nonzero_bits (varop, shift_mode) << count)
8653                & GET_MODE_MASK (shift_mode)))
8654         varop = const0_rtx;
8655
8656       switch (GET_CODE (varop))
8657         {
8658         case SIGN_EXTEND:
8659         case ZERO_EXTEND:
8660         case SIGN_EXTRACT:
8661         case ZERO_EXTRACT:
8662           new = expand_compound_operation (varop);
8663           if (new != varop)
8664             {
8665               varop = new;
8666               continue;
8667             }
8668           break;
8669
8670         case MEM:
8671           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8672              minus the width of a smaller mode, we can do this with a
8673              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8674           if ((code == ASHIFTRT || code == LSHIFTRT)
8675               && ! mode_dependent_address_p (XEXP (varop, 0))
8676               && ! MEM_VOLATILE_P (varop)
8677               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8678                                          MODE_INT, 1)) != BLKmode)
8679             {
8680               new = adjust_address_nv (varop, tmode,
8681                                        BYTES_BIG_ENDIAN ? 0
8682                                        : count / BITS_PER_UNIT);
8683
8684               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8685                                      : ZERO_EXTEND, mode, new);
8686               count = 0;
8687               continue;
8688             }
8689           break;
8690
8691         case USE:
8692           /* Similar to the case above, except that we can only do this if
8693              the resulting mode is the same as that of the underlying
8694              MEM and adjust the address depending on the *bits* endianness
8695              because of the way that bit-field extract insns are defined.  */
8696           if ((code == ASHIFTRT || code == LSHIFTRT)
8697               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8698                                          MODE_INT, 1)) != BLKmode
8699               && tmode == GET_MODE (XEXP (varop, 0)))
8700             {
8701               if (BITS_BIG_ENDIAN)
8702                 new = XEXP (varop, 0);
8703               else
8704                 {
8705                   new = copy_rtx (XEXP (varop, 0));
8706                   SUBST (XEXP (new, 0),
8707                          plus_constant (XEXP (new, 0),
8708                                         count / BITS_PER_UNIT));
8709                 }
8710
8711               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8712                                      : ZERO_EXTEND, mode, new);
8713               count = 0;
8714               continue;
8715             }
8716           break;
8717
8718         case SUBREG:
8719           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8720              the same number of words as what we've seen so far.  Then store
8721              the widest mode in MODE.  */
8722           if (subreg_lowpart_p (varop)
8723               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8724                   > GET_MODE_SIZE (GET_MODE (varop)))
8725               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8726                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8727                  == mode_words)
8728             {
8729               varop = SUBREG_REG (varop);
8730               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8731                 mode = GET_MODE (varop);
8732               continue;
8733             }
8734           break;
8735
8736         case MULT:
8737           /* Some machines use MULT instead of ASHIFT because MULT
8738              is cheaper.  But it is still better on those machines to
8739              merge two shifts into one.  */
8740           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8741               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8742             {
8743               varop
8744                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8745                                        XEXP (varop, 0),
8746                                        GEN_INT (exact_log2 (
8747                                                 INTVAL (XEXP (varop, 1)))));
8748               continue;
8749             }
8750           break;
8751
8752         case UDIV:
8753           /* Similar, for when divides are cheaper.  */
8754           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8755               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8756             {
8757               varop
8758                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8759                                        XEXP (varop, 0),
8760                                        GEN_INT (exact_log2 (
8761                                                 INTVAL (XEXP (varop, 1)))));
8762               continue;
8763             }
8764           break;
8765
8766         case ASHIFTRT:
8767           /* If we are extracting just the sign bit of an arithmetic
8768              right shift, that shift is not needed.  However, the sign
8769              bit of a wider mode may be different from what would be
8770              interpreted as the sign bit in a narrower mode, so, if
8771              the result is narrower, don't discard the shift.  */
8772           if (code == LSHIFTRT
8773               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8774               && (GET_MODE_BITSIZE (result_mode)
8775                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8776             {
8777               varop = XEXP (varop, 0);
8778               continue;
8779             }
8780
8781           /* ... fall through ...  */
8782
8783         case LSHIFTRT:
8784         case ASHIFT:
8785         case ROTATE:
8786           /* Here we have two nested shifts.  The result is usually the
8787              AND of a new shift with a mask.  We compute the result below.  */
8788           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8789               && INTVAL (XEXP (varop, 1)) >= 0
8790               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8791               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8792               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8793             {
8794               enum rtx_code first_code = GET_CODE (varop);
8795               unsigned int first_count = INTVAL (XEXP (varop, 1));
8796               unsigned HOST_WIDE_INT mask;
8797               rtx mask_rtx;
8798
8799               /* We have one common special case.  We can't do any merging if
8800                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8801                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8802                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8803                  we can convert it to
8804                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8805                  This simplifies certain SIGN_EXTEND operations.  */
8806               if (code == ASHIFT && first_code == ASHIFTRT
8807                   && count == (GET_MODE_BITSIZE (result_mode)
8808                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8809                 {
8810                   /* C3 has the low-order C1 bits zero.  */
8811
8812                   mask = (GET_MODE_MASK (mode)
8813                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8814
8815                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8816                                                   XEXP (varop, 0), mask);
8817                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8818                                                 varop, count);
8819                   count = first_count;
8820                   code = ASHIFTRT;
8821                   continue;
8822                 }
8823
8824               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8825                  than C1 high-order bits equal to the sign bit, we can convert
8826                  this to either an ASHIFT or an ASHIFTRT depending on the
8827                  two counts.
8828
8829                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8830
8831               if (code == ASHIFTRT && first_code == ASHIFT
8832                   && GET_MODE (varop) == shift_mode
8833                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8834                       > first_count))
8835                 {
8836                   varop = XEXP (varop, 0);
8837                   count -= first_count;
8838                   if (count < 0)
8839                     {
8840                       count = -count;
8841                       code = ASHIFT;
8842                     }
8843
8844                   continue;
8845                 }
8846
8847               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8848                  we can only do this if FIRST_CODE is also ASHIFTRT.
8849
8850                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8851                  ASHIFTRT.
8852
8853                  If the mode of this shift is not the mode of the outer shift,
8854                  we can't do this if either shift is a right shift or ROTATE.
8855
8856                  Finally, we can't do any of these if the mode is too wide
8857                  unless the codes are the same.
8858
8859                  Handle the case where the shift codes are the same
8860                  first.  */
8861
8862               if (code == first_code)
8863                 {
8864                   if (GET_MODE (varop) != result_mode
8865                       && (code == ASHIFTRT || code == LSHIFTRT
8866                           || code == ROTATE))
8867                     break;
8868
8869                   count += first_count;
8870                   varop = XEXP (varop, 0);
8871                   continue;
8872                 }
8873
8874               if (code == ASHIFTRT
8875                   || (code == ROTATE && first_code == ASHIFTRT)
8876                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8877                   || (GET_MODE (varop) != result_mode
8878                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8879                           || first_code == ROTATE
8880                           || code == ROTATE)))
8881                 break;
8882
8883               /* To compute the mask to apply after the shift, shift the
8884                  nonzero bits of the inner shift the same way the
8885                  outer shift will.  */
8886
8887               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8888
8889               mask_rtx
8890                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8891                                                    GEN_INT (count));
8892
8893               /* Give up if we can't compute an outer operation to use.  */
8894               if (mask_rtx == 0
8895                   || GET_CODE (mask_rtx) != CONST_INT
8896                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8897                                         INTVAL (mask_rtx),
8898                                         result_mode, &complement_p))
8899                 break;
8900
8901               /* If the shifts are in the same direction, we add the
8902                  counts.  Otherwise, we subtract them.  */
8903               if ((code == ASHIFTRT || code == LSHIFTRT)
8904                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8905                 count += first_count;
8906               else
8907                 count -= first_count;
8908
8909               /* If COUNT is positive, the new shift is usually CODE,
8910                  except for the two exceptions below, in which case it is
8911                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8912                  always be used  */
8913               if (count > 0
8914                   && ((first_code == ROTATE && code == ASHIFT)
8915                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8916                 code = first_code;
8917               else if (count < 0)
8918                 code = first_code, count = -count;
8919
8920               varop = XEXP (varop, 0);
8921               continue;
8922             }
8923
8924           /* If we have (A << B << C) for any shift, we can convert this to
8925              (A << C << B).  This wins if A is a constant.  Only try this if
8926              B is not a constant.  */
8927
8928           else if (GET_CODE (varop) == code
8929                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8930                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8931             {
8932               rtx new = simplify_const_binary_operation (code, mode,
8933                                                          XEXP (varop, 0),
8934                                                          GEN_INT (count));
8935               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8936               count = 0;
8937               continue;
8938             }
8939           break;
8940
8941         case NOT:
8942           /* Make this fit the case below.  */
8943           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8944                                GEN_INT (GET_MODE_MASK (mode)));
8945           continue;
8946
8947         case IOR:
8948         case AND:
8949         case XOR:
8950           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8951              with C the size of VAROP - 1 and the shift is logical if
8952              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8953              we have an (le X 0) operation.   If we have an arithmetic shift
8954              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8955              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8956
8957           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8958               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8959               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8960               && (code == LSHIFTRT || code == ASHIFTRT)
8961               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8962               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8963             {
8964               count = 0;
8965               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8966                                   const0_rtx);
8967
8968               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8969                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8970
8971               continue;
8972             }
8973
8974           /* If we have (shift (logical)), move the logical to the outside
8975              to allow it to possibly combine with another logical and the
8976              shift to combine with another shift.  This also canonicalizes to
8977              what a ZERO_EXTRACT looks like.  Also, some machines have
8978              (and (shift)) insns.  */
8979
8980           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8981               /* We can't do this if we have (ashiftrt (xor))  and the
8982                  constant has its sign bit set in shift_mode.  */
8983               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8984                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8985                                               shift_mode))
8986               && (new = simplify_const_binary_operation (code, result_mode,
8987                                                          XEXP (varop, 1),
8988                                                          GEN_INT (count))) != 0
8989               && GET_CODE (new) == CONST_INT
8990               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8991                                   INTVAL (new), result_mode, &complement_p))
8992             {
8993               varop = XEXP (varop, 0);
8994               continue;
8995             }
8996
8997           /* If we can't do that, try to simplify the shift in each arm of the
8998              logical expression, make a new logical expression, and apply
8999              the inverse distributive law.  This also can't be done
9000              for some (ashiftrt (xor)).  */
9001           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9002              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9003                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9004                                              shift_mode)))
9005             {
9006               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9007                                               XEXP (varop, 0), count);
9008               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9009                                               XEXP (varop, 1), count);
9010
9011               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9012                                            lhs, rhs);
9013               varop = apply_distributive_law (varop);
9014
9015               count = 0;
9016               continue;
9017             }
9018           break;
9019
9020         case EQ:
9021           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9022              says that the sign bit can be tested, FOO has mode MODE, C is
9023              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9024              that may be nonzero.  */
9025           if (code == LSHIFTRT
9026               && XEXP (varop, 1) == const0_rtx
9027               && GET_MODE (XEXP (varop, 0)) == result_mode
9028               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9029               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9030               && STORE_FLAG_VALUE == -1
9031               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9032               && merge_outer_ops (&outer_op, &outer_const, XOR,
9033                                   (HOST_WIDE_INT) 1, result_mode,
9034                                   &complement_p))
9035             {
9036               varop = XEXP (varop, 0);
9037               count = 0;
9038               continue;
9039             }
9040           break;
9041
9042         case NEG:
9043           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9044              than the number of bits in the mode is equivalent to A.  */
9045           if (code == LSHIFTRT
9046               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9047               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9048             {
9049               varop = XEXP (varop, 0);
9050               count = 0;
9051               continue;
9052             }
9053
9054           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9055              NEG outside to allow shifts to combine.  */
9056           if (code == ASHIFT
9057               && merge_outer_ops (&outer_op, &outer_const, NEG,
9058                                   (HOST_WIDE_INT) 0, result_mode,
9059                                   &complement_p))
9060             {
9061               varop = XEXP (varop, 0);
9062               continue;
9063             }
9064           break;
9065
9066         case PLUS:
9067           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9068              is one less than the number of bits in the mode is
9069              equivalent to (xor A 1).  */
9070           if (code == LSHIFTRT
9071               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9072               && XEXP (varop, 1) == constm1_rtx
9073               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9074               && merge_outer_ops (&outer_op, &outer_const, XOR,
9075                                   (HOST_WIDE_INT) 1, result_mode,
9076                                   &complement_p))
9077             {
9078               count = 0;
9079               varop = XEXP (varop, 0);
9080               continue;
9081             }
9082
9083           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9084              that might be nonzero in BAR are those being shifted out and those
9085              bits are known zero in FOO, we can replace the PLUS with FOO.
9086              Similarly in the other operand order.  This code occurs when
9087              we are computing the size of a variable-size array.  */
9088
9089           if ((code == ASHIFTRT || code == LSHIFTRT)
9090               && count < HOST_BITS_PER_WIDE_INT
9091               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9092               && (nonzero_bits (XEXP (varop, 1), result_mode)
9093                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9094             {
9095               varop = XEXP (varop, 0);
9096               continue;
9097             }
9098           else if ((code == ASHIFTRT || code == LSHIFTRT)
9099                    && count < HOST_BITS_PER_WIDE_INT
9100                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9101                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9102                             >> count)
9103                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9104                             & nonzero_bits (XEXP (varop, 1),
9105                                                  result_mode)))
9106             {
9107               varop = XEXP (varop, 1);
9108               continue;
9109             }
9110
9111           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9112           if (code == ASHIFT
9113               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9114               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9115                                                          XEXP (varop, 1),
9116                                                          GEN_INT (count))) != 0
9117               && GET_CODE (new) == CONST_INT
9118               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9119                                   INTVAL (new), result_mode, &complement_p))
9120             {
9121               varop = XEXP (varop, 0);
9122               continue;
9123             }
9124
9125           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9126              signbit', and attempt to change the PLUS to an XOR and move it to
9127              the outer operation as is done above in the AND/IOR/XOR case
9128              leg for shift(logical). See details in logical handling above
9129              for reasoning in doing so.  */
9130           if (code == LSHIFTRT
9131               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9132               && mode_signbit_p (result_mode, XEXP (varop, 1))
9133               && (new = simplify_const_binary_operation (code, result_mode,
9134                                                          XEXP (varop, 1),
9135                                                          GEN_INT (count))) != 0
9136               && GET_CODE (new) == CONST_INT
9137               && merge_outer_ops (&outer_op, &outer_const, XOR,
9138                                   INTVAL (new), result_mode, &complement_p))
9139             {
9140               varop = XEXP (varop, 0);
9141               continue;
9142             }
9143
9144           break;
9145
9146         case MINUS:
9147           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9148              with C the size of VAROP - 1 and the shift is logical if
9149              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9150              we have a (gt X 0) operation.  If the shift is arithmetic with
9151              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9152              we have a (neg (gt X 0)) operation.  */
9153
9154           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9155               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9156               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9157               && (code == LSHIFTRT || code == ASHIFTRT)
9158               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9159               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9160               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9161             {
9162               count = 0;
9163               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9164                                   const0_rtx);
9165
9166               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9167                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9168
9169               continue;
9170             }
9171           break;
9172
9173         case TRUNCATE:
9174           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9175              if the truncate does not affect the value.  */
9176           if (code == LSHIFTRT
9177               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9178               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9179               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9180                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9181                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9182             {
9183               rtx varop_inner = XEXP (varop, 0);
9184
9185               varop_inner
9186                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9187                                     XEXP (varop_inner, 0),
9188                                     GEN_INT
9189                                     (count + INTVAL (XEXP (varop_inner, 1))));
9190               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9191               count = 0;
9192               continue;
9193             }
9194           break;
9195
9196         default:
9197           break;
9198         }
9199
9200       break;
9201     }
9202
9203   /* We need to determine what mode to do the shift in.  If the shift is
9204      a right shift or ROTATE, we must always do it in the mode it was
9205      originally done in.  Otherwise, we can do it in MODE, the widest mode
9206      encountered.  The code we care about is that of the shift that will
9207      actually be done, not the shift that was originally requested.  */
9208   shift_mode
9209     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9210        ? result_mode : mode);
9211
9212   /* We have now finished analyzing the shift.  The result should be
9213      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9214      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9215      to the result of the shift.  OUTER_CONST is the relevant constant,
9216      but we must turn off all bits turned off in the shift.  */
9217
9218   if (outer_op == UNKNOWN
9219       && orig_code == code && orig_count == count
9220       && varop == orig_varop
9221       && shift_mode == GET_MODE (varop))
9222     return NULL_RTX;
9223
9224   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9225   varop = gen_lowpart (shift_mode, varop);
9226   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9227     return NULL_RTX;
9228
9229   /* If we have an outer operation and we just made a shift, it is
9230      possible that we could have simplified the shift were it not
9231      for the outer operation.  So try to do the simplification
9232      recursively.  */
9233
9234   if (outer_op != UNKNOWN)
9235     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9236   else
9237     x = NULL_RTX;
9238
9239   if (x == NULL_RTX)
9240     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9241
9242   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9243      turn off all the bits that the shift would have turned off.  */
9244   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9245     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9246                                 GET_MODE_MASK (result_mode) >> orig_count);
9247
9248   /* Do the remainder of the processing in RESULT_MODE.  */
9249   x = gen_lowpart (result_mode, x);
9250
9251   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9252      operation.  */
9253   if (complement_p)
9254     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9255
9256   if (outer_op != UNKNOWN)
9257     {
9258       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9259         outer_const = trunc_int_for_mode (outer_const, result_mode);
9260
9261       if (outer_op == AND)
9262         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9263       else if (outer_op == SET)
9264         /* This means that we have determined that the result is
9265            equivalent to a constant.  This should be rare.  */
9266         x = GEN_INT (outer_const);
9267       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9268         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9269       else
9270         x = simplify_gen_binary (outer_op, result_mode, x,
9271                                  GEN_INT (outer_const));
9272     }
9273
9274   return x;
9275 }
9276
9277 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9278    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9279    return X or, if it is NULL, synthesize the expression with
9280    simplify_gen_binary.  Otherwise, return a simplified value.
9281
9282    The shift is normally computed in the widest mode we find in VAROP, as
9283    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9284    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9285
9286 static rtx
9287 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9288                       rtx varop, int count)
9289 {
9290   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9291   if (tem)
9292     return tem;
9293
9294   if (!x)
9295     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9296   if (GET_MODE (x) != result_mode)
9297     x = gen_lowpart (result_mode, x);
9298   return x;
9299 }
9300
9301 \f
9302 /* Like recog, but we receive the address of a pointer to a new pattern.
9303    We try to match the rtx that the pointer points to.
9304    If that fails, we may try to modify or replace the pattern,
9305    storing the replacement into the same pointer object.
9306
9307    Modifications include deletion or addition of CLOBBERs.
9308
9309    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9310    the CLOBBERs are placed.
9311
9312    The value is the final insn code from the pattern ultimately matched,
9313    or -1.  */
9314
9315 static int
9316 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9317 {
9318   rtx pat = *pnewpat;
9319   int insn_code_number;
9320   int num_clobbers_to_add = 0;
9321   int i;
9322   rtx notes = 0;
9323   rtx old_notes, old_pat;
9324
9325   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9326      we use to indicate that something didn't match.  If we find such a
9327      thing, force rejection.  */
9328   if (GET_CODE (pat) == PARALLEL)
9329     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9330       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9331           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9332         return -1;
9333
9334   old_pat = PATTERN (insn);
9335   old_notes = REG_NOTES (insn);
9336   PATTERN (insn) = pat;
9337   REG_NOTES (insn) = 0;
9338
9339   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9340
9341   /* If it isn't, there is the possibility that we previously had an insn
9342      that clobbered some register as a side effect, but the combined
9343      insn doesn't need to do that.  So try once more without the clobbers
9344      unless this represents an ASM insn.  */
9345
9346   if (insn_code_number < 0 && ! check_asm_operands (pat)
9347       && GET_CODE (pat) == PARALLEL)
9348     {
9349       int pos;
9350
9351       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9352         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9353           {
9354             if (i != pos)
9355               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9356             pos++;
9357           }
9358
9359       SUBST_INT (XVECLEN (pat, 0), pos);
9360
9361       if (pos == 1)
9362         pat = XVECEXP (pat, 0, 0);
9363
9364       PATTERN (insn) = pat;
9365       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9366     }
9367   PATTERN (insn) = old_pat;
9368   REG_NOTES (insn) = old_notes;
9369
9370   /* Recognize all noop sets, these will be killed by followup pass.  */
9371   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9372     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9373
9374   /* If we had any clobbers to add, make a new pattern than contains
9375      them.  Then check to make sure that all of them are dead.  */
9376   if (num_clobbers_to_add)
9377     {
9378       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9379                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9380                                                   ? (XVECLEN (pat, 0)
9381                                                      + num_clobbers_to_add)
9382                                                   : num_clobbers_to_add + 1));
9383
9384       if (GET_CODE (pat) == PARALLEL)
9385         for (i = 0; i < XVECLEN (pat, 0); i++)
9386           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9387       else
9388         XVECEXP (newpat, 0, 0) = pat;
9389
9390       add_clobbers (newpat, insn_code_number);
9391
9392       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9393            i < XVECLEN (newpat, 0); i++)
9394         {
9395           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9396               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9397             return -1;
9398           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9399                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9400         }
9401       pat = newpat;
9402     }
9403
9404   *pnewpat = pat;
9405   *pnotes = notes;
9406
9407   return insn_code_number;
9408 }
9409 \f
9410 /* Like gen_lowpart_general but for use by combine.  In combine it
9411    is not possible to create any new pseudoregs.  However, it is
9412    safe to create invalid memory addresses, because combine will
9413    try to recognize them and all they will do is make the combine
9414    attempt fail.
9415
9416    If for some reason this cannot do its job, an rtx
9417    (clobber (const_int 0)) is returned.
9418    An insn containing that will not be recognized.  */
9419
9420 static rtx
9421 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9422 {
9423   enum machine_mode imode = GET_MODE (x);
9424   unsigned int osize = GET_MODE_SIZE (omode);
9425   unsigned int isize = GET_MODE_SIZE (imode);
9426   rtx result;
9427
9428   if (omode == imode)
9429     return x;
9430
9431   /* Return identity if this is a CONST or symbolic reference.  */
9432   if (omode == Pmode
9433       && (GET_CODE (x) == CONST
9434           || GET_CODE (x) == SYMBOL_REF
9435           || GET_CODE (x) == LABEL_REF))
9436     return x;
9437
9438   /* We can only support MODE being wider than a word if X is a
9439      constant integer or has a mode the same size.  */
9440   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9441       && ! ((imode == VOIDmode
9442              && (GET_CODE (x) == CONST_INT
9443                  || GET_CODE (x) == CONST_DOUBLE))
9444             || isize == osize))
9445     goto fail;
9446
9447   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9448      won't know what to do.  So we will strip off the SUBREG here and
9449      process normally.  */
9450   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9451     {
9452       x = SUBREG_REG (x);
9453
9454       /* For use in case we fall down into the address adjustments
9455          further below, we need to adjust the known mode and size of
9456          x; imode and isize, since we just adjusted x.  */
9457       imode = GET_MODE (x);
9458
9459       if (imode == omode)
9460         return x;
9461
9462       isize = GET_MODE_SIZE (imode);
9463     }
9464
9465   result = gen_lowpart_common (omode, x);
9466
9467 #ifdef CANNOT_CHANGE_MODE_CLASS
9468   if (result != 0 && GET_CODE (result) == SUBREG)
9469     record_subregs_of_mode (result);
9470 #endif
9471
9472   if (result)
9473     return result;
9474
9475   if (MEM_P (x))
9476     {
9477       int offset = 0;
9478
9479       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9480          address.  */
9481       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9482         goto fail;
9483
9484       /* If we want to refer to something bigger than the original memref,
9485          generate a paradoxical subreg instead.  That will force a reload
9486          of the original memref X.  */
9487       if (isize < osize)
9488         return gen_rtx_SUBREG (omode, x, 0);
9489
9490       if (WORDS_BIG_ENDIAN)
9491         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9492
9493       /* Adjust the address so that the address-after-the-data is
9494          unchanged.  */
9495       if (BYTES_BIG_ENDIAN)
9496         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9497
9498       return adjust_address_nv (x, omode, offset);
9499     }
9500
9501   /* If X is a comparison operator, rewrite it in a new mode.  This
9502      probably won't match, but may allow further simplifications.  */
9503   else if (COMPARISON_P (x))
9504     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9505
9506   /* If we couldn't simplify X any other way, just enclose it in a
9507      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9508      include an explicit SUBREG or we may simplify it further in combine.  */
9509   else
9510     {
9511       int offset = 0;
9512       rtx res;
9513
9514       offset = subreg_lowpart_offset (omode, imode);
9515       if (imode == VOIDmode)
9516         {
9517           imode = int_mode_for_mode (omode);
9518           x = gen_lowpart_common (imode, x);
9519           if (x == NULL)
9520             goto fail;
9521         }
9522       res = simplify_gen_subreg (omode, x, imode, offset);
9523       if (res)
9524         return res;
9525     }
9526
9527  fail:
9528   return gen_rtx_CLOBBER (imode, const0_rtx);
9529 }
9530 \f
9531 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9532    comparison code that will be tested.
9533
9534    The result is a possibly different comparison code to use.  *POP0 and
9535    *POP1 may be updated.
9536
9537    It is possible that we might detect that a comparison is either always
9538    true or always false.  However, we do not perform general constant
9539    folding in combine, so this knowledge isn't useful.  Such tautologies
9540    should have been detected earlier.  Hence we ignore all such cases.  */
9541
9542 static enum rtx_code
9543 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9544 {
9545   rtx op0 = *pop0;
9546   rtx op1 = *pop1;
9547   rtx tem, tem1;
9548   int i;
9549   enum machine_mode mode, tmode;
9550
9551   /* Try a few ways of applying the same transformation to both operands.  */
9552   while (1)
9553     {
9554 #ifndef WORD_REGISTER_OPERATIONS
9555       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9556          so check specially.  */
9557       if (code != GTU && code != GEU && code != LTU && code != LEU
9558           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9559           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9560           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9561           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9562           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9563           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9564               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9565           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9566           && XEXP (op0, 1) == XEXP (op1, 1)
9567           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9568           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9569           && (INTVAL (XEXP (op0, 1))
9570               == (GET_MODE_BITSIZE (GET_MODE (op0))
9571                   - (GET_MODE_BITSIZE
9572                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9573         {
9574           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9575           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9576         }
9577 #endif
9578
9579       /* If both operands are the same constant shift, see if we can ignore the
9580          shift.  We can if the shift is a rotate or if the bits shifted out of
9581          this shift are known to be zero for both inputs and if the type of
9582          comparison is compatible with the shift.  */
9583       if (GET_CODE (op0) == GET_CODE (op1)
9584           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9585           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9586               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9587                   && (code != GT && code != LT && code != GE && code != LE))
9588               || (GET_CODE (op0) == ASHIFTRT
9589                   && (code != GTU && code != LTU
9590                       && code != GEU && code != LEU)))
9591           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9592           && INTVAL (XEXP (op0, 1)) >= 0
9593           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9594           && XEXP (op0, 1) == XEXP (op1, 1))
9595         {
9596           enum machine_mode mode = GET_MODE (op0);
9597           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9598           int shift_count = INTVAL (XEXP (op0, 1));
9599
9600           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9601             mask &= (mask >> shift_count) << shift_count;
9602           else if (GET_CODE (op0) == ASHIFT)
9603             mask = (mask & (mask << shift_count)) >> shift_count;
9604
9605           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9606               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9607             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9608           else
9609             break;
9610         }
9611
9612       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9613          SUBREGs are of the same mode, and, in both cases, the AND would
9614          be redundant if the comparison was done in the narrower mode,
9615          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9616          and the operand's possibly nonzero bits are 0xffffff01; in that case
9617          if we only care about QImode, we don't need the AND).  This case
9618          occurs if the output mode of an scc insn is not SImode and
9619          STORE_FLAG_VALUE == 1 (e.g., the 386).
9620
9621          Similarly, check for a case where the AND's are ZERO_EXTEND
9622          operations from some narrower mode even though a SUBREG is not
9623          present.  */
9624
9625       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9626                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9627                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9628         {
9629           rtx inner_op0 = XEXP (op0, 0);
9630           rtx inner_op1 = XEXP (op1, 0);
9631           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9632           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9633           int changed = 0;
9634
9635           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9636               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9637                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9638               && (GET_MODE (SUBREG_REG (inner_op0))
9639                   == GET_MODE (SUBREG_REG (inner_op1)))
9640               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9641                   <= HOST_BITS_PER_WIDE_INT)
9642               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9643                                              GET_MODE (SUBREG_REG (inner_op0)))))
9644               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9645                                              GET_MODE (SUBREG_REG (inner_op1))))))
9646             {
9647               op0 = SUBREG_REG (inner_op0);
9648               op1 = SUBREG_REG (inner_op1);
9649
9650               /* The resulting comparison is always unsigned since we masked
9651                  off the original sign bit.  */
9652               code = unsigned_condition (code);
9653
9654               changed = 1;
9655             }
9656
9657           else if (c0 == c1)
9658             for (tmode = GET_CLASS_NARROWEST_MODE
9659                  (GET_MODE_CLASS (GET_MODE (op0)));
9660                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9661               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9662                 {
9663                   op0 = gen_lowpart (tmode, inner_op0);
9664                   op1 = gen_lowpart (tmode, inner_op1);
9665                   code = unsigned_condition (code);
9666                   changed = 1;
9667                   break;
9668                 }
9669
9670           if (! changed)
9671             break;
9672         }
9673
9674       /* If both operands are NOT, we can strip off the outer operation
9675          and adjust the comparison code for swapped operands; similarly for
9676          NEG, except that this must be an equality comparison.  */
9677       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9678                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9679                    && (code == EQ || code == NE)))
9680         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9681
9682       else
9683         break;
9684     }
9685
9686   /* If the first operand is a constant, swap the operands and adjust the
9687      comparison code appropriately, but don't do this if the second operand
9688      is already a constant integer.  */
9689   if (swap_commutative_operands_p (op0, op1))
9690     {
9691       tem = op0, op0 = op1, op1 = tem;
9692       code = swap_condition (code);
9693     }
9694
9695   /* We now enter a loop during which we will try to simplify the comparison.
9696      For the most part, we only are concerned with comparisons with zero,
9697      but some things may really be comparisons with zero but not start
9698      out looking that way.  */
9699
9700   while (GET_CODE (op1) == CONST_INT)
9701     {
9702       enum machine_mode mode = GET_MODE (op0);
9703       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9704       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9705       int equality_comparison_p;
9706       int sign_bit_comparison_p;
9707       int unsigned_comparison_p;
9708       HOST_WIDE_INT const_op;
9709
9710       /* We only want to handle integral modes.  This catches VOIDmode,
9711          CCmode, and the floating-point modes.  An exception is that we
9712          can handle VOIDmode if OP0 is a COMPARE or a comparison
9713          operation.  */
9714
9715       if (GET_MODE_CLASS (mode) != MODE_INT
9716           && ! (mode == VOIDmode
9717                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9718         break;
9719
9720       /* Get the constant we are comparing against and turn off all bits
9721          not on in our mode.  */
9722       const_op = INTVAL (op1);
9723       if (mode != VOIDmode)
9724         const_op = trunc_int_for_mode (const_op, mode);
9725       op1 = GEN_INT (const_op);
9726
9727       /* If we are comparing against a constant power of two and the value
9728          being compared can only have that single bit nonzero (e.g., it was
9729          `and'ed with that bit), we can replace this with a comparison
9730          with zero.  */
9731       if (const_op
9732           && (code == EQ || code == NE || code == GE || code == GEU
9733               || code == LT || code == LTU)
9734           && mode_width <= HOST_BITS_PER_WIDE_INT
9735           && exact_log2 (const_op) >= 0
9736           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9737         {
9738           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9739           op1 = const0_rtx, const_op = 0;
9740         }
9741
9742       /* Similarly, if we are comparing a value known to be either -1 or
9743          0 with -1, change it to the opposite comparison against zero.  */
9744
9745       if (const_op == -1
9746           && (code == EQ || code == NE || code == GT || code == LE
9747               || code == GEU || code == LTU)
9748           && num_sign_bit_copies (op0, mode) == mode_width)
9749         {
9750           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9751           op1 = const0_rtx, const_op = 0;
9752         }
9753
9754       /* Do some canonicalizations based on the comparison code.  We prefer
9755          comparisons against zero and then prefer equality comparisons.
9756          If we can reduce the size of a constant, we will do that too.  */
9757
9758       switch (code)
9759         {
9760         case LT:
9761           /* < C is equivalent to <= (C - 1) */
9762           if (const_op > 0)
9763             {
9764               const_op -= 1;
9765               op1 = GEN_INT (const_op);
9766               code = LE;
9767               /* ... fall through to LE case below.  */
9768             }
9769           else
9770             break;
9771
9772         case LE:
9773           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9774           if (const_op < 0)
9775             {
9776               const_op += 1;
9777               op1 = GEN_INT (const_op);
9778               code = LT;
9779             }
9780
9781           /* If we are doing a <= 0 comparison on a value known to have
9782              a zero sign bit, we can replace this with == 0.  */
9783           else if (const_op == 0
9784                    && mode_width <= HOST_BITS_PER_WIDE_INT
9785                    && (nonzero_bits (op0, mode)
9786                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9787             code = EQ;
9788           break;
9789
9790         case GE:
9791           /* >= C is equivalent to > (C - 1).  */
9792           if (const_op > 0)
9793             {
9794               const_op -= 1;
9795               op1 = GEN_INT (const_op);
9796               code = GT;
9797               /* ... fall through to GT below.  */
9798             }
9799           else
9800             break;
9801
9802         case GT:
9803           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9804           if (const_op < 0)
9805             {
9806               const_op += 1;
9807               op1 = GEN_INT (const_op);
9808               code = GE;
9809             }
9810
9811           /* If we are doing a > 0 comparison on a value known to have
9812              a zero sign bit, we can replace this with != 0.  */
9813           else if (const_op == 0
9814                    && mode_width <= HOST_BITS_PER_WIDE_INT
9815                    && (nonzero_bits (op0, mode)
9816                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9817             code = NE;
9818           break;
9819
9820         case LTU:
9821           /* < C is equivalent to <= (C - 1).  */
9822           if (const_op > 0)
9823             {
9824               const_op -= 1;
9825               op1 = GEN_INT (const_op);
9826               code = LEU;
9827               /* ... fall through ...  */
9828             }
9829
9830           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9831           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9832                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9833             {
9834               const_op = 0, op1 = const0_rtx;
9835               code = GE;
9836               break;
9837             }
9838           else
9839             break;
9840
9841         case LEU:
9842           /* unsigned <= 0 is equivalent to == 0 */
9843           if (const_op == 0)
9844             code = EQ;
9845
9846           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9847           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9848                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9849             {
9850               const_op = 0, op1 = const0_rtx;
9851               code = GE;
9852             }
9853           break;
9854
9855         case GEU:
9856           /* >= C is equivalent to > (C - 1).  */
9857           if (const_op > 1)
9858             {
9859               const_op -= 1;
9860               op1 = GEN_INT (const_op);
9861               code = GTU;
9862               /* ... fall through ...  */
9863             }
9864
9865           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9866           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9867                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9868             {
9869               const_op = 0, op1 = const0_rtx;
9870               code = LT;
9871               break;
9872             }
9873           else
9874             break;
9875
9876         case GTU:
9877           /* unsigned > 0 is equivalent to != 0 */
9878           if (const_op == 0)
9879             code = NE;
9880
9881           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9882           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9883                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9884             {
9885               const_op = 0, op1 = const0_rtx;
9886               code = LT;
9887             }
9888           break;
9889
9890         default:
9891           break;
9892         }
9893
9894       /* Compute some predicates to simplify code below.  */
9895
9896       equality_comparison_p = (code == EQ || code == NE);
9897       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9898       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9899                                || code == GEU);
9900
9901       /* If this is a sign bit comparison and we can do arithmetic in
9902          MODE, say that we will only be needing the sign bit of OP0.  */
9903       if (sign_bit_comparison_p
9904           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9905         op0 = force_to_mode (op0, mode,
9906                              ((HOST_WIDE_INT) 1
9907                               << (GET_MODE_BITSIZE (mode) - 1)),
9908                              0);
9909
9910       /* Now try cases based on the opcode of OP0.  If none of the cases
9911          does a "continue", we exit this loop immediately after the
9912          switch.  */
9913
9914       switch (GET_CODE (op0))
9915         {
9916         case ZERO_EXTRACT:
9917           /* If we are extracting a single bit from a variable position in
9918              a constant that has only a single bit set and are comparing it
9919              with zero, we can convert this into an equality comparison
9920              between the position and the location of the single bit.  */
9921           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9922              have already reduced the shift count modulo the word size.  */
9923           if (!SHIFT_COUNT_TRUNCATED
9924               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9925               && XEXP (op0, 1) == const1_rtx
9926               && equality_comparison_p && const_op == 0
9927               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9928             {
9929               if (BITS_BIG_ENDIAN)
9930                 {
9931                   enum machine_mode new_mode
9932                     = mode_for_extraction (EP_extzv, 1);
9933                   if (new_mode == MAX_MACHINE_MODE)
9934                     i = BITS_PER_WORD - 1 - i;
9935                   else
9936                     {
9937                       mode = new_mode;
9938                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9939                     }
9940                 }
9941
9942               op0 = XEXP (op0, 2);
9943               op1 = GEN_INT (i);
9944               const_op = i;
9945
9946               /* Result is nonzero iff shift count is equal to I.  */
9947               code = reverse_condition (code);
9948               continue;
9949             }
9950
9951           /* ... fall through ...  */
9952
9953         case SIGN_EXTRACT:
9954           tem = expand_compound_operation (op0);
9955           if (tem != op0)
9956             {
9957               op0 = tem;
9958               continue;
9959             }
9960           break;
9961
9962         case NOT:
9963           /* If testing for equality, we can take the NOT of the constant.  */
9964           if (equality_comparison_p
9965               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9966             {
9967               op0 = XEXP (op0, 0);
9968               op1 = tem;
9969               continue;
9970             }
9971
9972           /* If just looking at the sign bit, reverse the sense of the
9973              comparison.  */
9974           if (sign_bit_comparison_p)
9975             {
9976               op0 = XEXP (op0, 0);
9977               code = (code == GE ? LT : GE);
9978               continue;
9979             }
9980           break;
9981
9982         case NEG:
9983           /* If testing for equality, we can take the NEG of the constant.  */
9984           if (equality_comparison_p
9985               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9986             {
9987               op0 = XEXP (op0, 0);
9988               op1 = tem;
9989               continue;
9990             }
9991
9992           /* The remaining cases only apply to comparisons with zero.  */
9993           if (const_op != 0)
9994             break;
9995
9996           /* When X is ABS or is known positive,
9997              (neg X) is < 0 if and only if X != 0.  */
9998
9999           if (sign_bit_comparison_p
10000               && (GET_CODE (XEXP (op0, 0)) == ABS
10001                   || (mode_width <= HOST_BITS_PER_WIDE_INT
10002                       && (nonzero_bits (XEXP (op0, 0), mode)
10003                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10004             {
10005               op0 = XEXP (op0, 0);
10006               code = (code == LT ? NE : EQ);
10007               continue;
10008             }
10009
10010           /* If we have NEG of something whose two high-order bits are the
10011              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10012           if (num_sign_bit_copies (op0, mode) >= 2)
10013             {
10014               op0 = XEXP (op0, 0);
10015               code = swap_condition (code);
10016               continue;
10017             }
10018           break;
10019
10020         case ROTATE:
10021           /* If we are testing equality and our count is a constant, we
10022              can perform the inverse operation on our RHS.  */
10023           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10024               && (tem = simplify_binary_operation (ROTATERT, mode,
10025                                                    op1, XEXP (op0, 1))) != 0)
10026             {
10027               op0 = XEXP (op0, 0);
10028               op1 = tem;
10029               continue;
10030             }
10031
10032           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10033              a particular bit.  Convert it to an AND of a constant of that
10034              bit.  This will be converted into a ZERO_EXTRACT.  */
10035           if (const_op == 0 && sign_bit_comparison_p
10036               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10037               && mode_width <= HOST_BITS_PER_WIDE_INT)
10038             {
10039               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10040                                             ((HOST_WIDE_INT) 1
10041                                              << (mode_width - 1
10042                                                  - INTVAL (XEXP (op0, 1)))));
10043               code = (code == LT ? NE : EQ);
10044               continue;
10045             }
10046
10047           /* Fall through.  */
10048
10049         case ABS:
10050           /* ABS is ignorable inside an equality comparison with zero.  */
10051           if (const_op == 0 && equality_comparison_p)
10052             {
10053               op0 = XEXP (op0, 0);
10054               continue;
10055             }
10056           break;
10057
10058         case SIGN_EXTEND:
10059           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10060              (compare FOO CONST) if CONST fits in FOO's mode and we
10061              are either testing inequality or have an unsigned
10062              comparison with ZERO_EXTEND or a signed comparison with
10063              SIGN_EXTEND.  But don't do it if we don't have a compare
10064              insn of the given mode, since we'd have to revert it
10065              later on, and then we wouldn't know whether to sign- or
10066              zero-extend.  */
10067           mode = GET_MODE (XEXP (op0, 0));
10068           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10069               && ! unsigned_comparison_p
10070               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10071               && ((unsigned HOST_WIDE_INT) const_op
10072                   < (((unsigned HOST_WIDE_INT) 1
10073                       << (GET_MODE_BITSIZE (mode) - 1))))
10074               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10075             {
10076               op0 = XEXP (op0, 0);
10077               continue;
10078             }
10079           break;
10080
10081         case SUBREG:
10082           /* Check for the case where we are comparing A - C1 with C2, that is
10083
10084                (subreg:MODE (plus (A) (-C1))) op (C2)
10085
10086              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10087              comparison in the wider mode.  One of the following two conditions
10088              must be true in order for this to be valid:
10089
10090                1. The mode extension results in the same bit pattern being added
10091                   on both sides and the comparison is equality or unsigned.  As
10092                   C2 has been truncated to fit in MODE, the pattern can only be
10093                   all 0s or all 1s.
10094
10095                2. The mode extension results in the sign bit being copied on
10096                   each side.
10097
10098              The difficulty here is that we have predicates for A but not for
10099              (A - C1) so we need to check that C1 is within proper bounds so
10100              as to perturbate A as little as possible.  */
10101
10102           if (mode_width <= HOST_BITS_PER_WIDE_INT
10103               && subreg_lowpart_p (op0)
10104               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10105               && GET_CODE (SUBREG_REG (op0)) == PLUS
10106               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10107             {
10108               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10109               rtx a = XEXP (SUBREG_REG (op0), 0);
10110               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10111
10112               if ((c1 > 0
10113                    && (unsigned HOST_WIDE_INT) c1
10114                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10115                    && (equality_comparison_p || unsigned_comparison_p)
10116                    /* (A - C1) zero-extends if it is positive and sign-extends
10117                       if it is negative, C2 both zero- and sign-extends.  */
10118                    && ((0 == (nonzero_bits (a, inner_mode)
10119                               & ~GET_MODE_MASK (mode))
10120                         && const_op >= 0)
10121                        /* (A - C1) sign-extends if it is positive and 1-extends
10122                           if it is negative, C2 both sign- and 1-extends.  */
10123                        || (num_sign_bit_copies (a, inner_mode)
10124                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10125                                              - mode_width)
10126                            && const_op < 0)))
10127                   || ((unsigned HOST_WIDE_INT) c1
10128                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10129                       /* (A - C1) always sign-extends, like C2.  */
10130                       && num_sign_bit_copies (a, inner_mode)
10131                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10132                                            - (mode_width - 1))))
10133                 {
10134                   op0 = SUBREG_REG (op0);
10135                   continue;
10136                 }
10137             }
10138
10139           /* If the inner mode is narrower and we are extracting the low part,
10140              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10141           if (subreg_lowpart_p (op0)
10142               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10143             /* Fall through */ ;
10144           else
10145             break;
10146
10147           /* ... fall through ...  */
10148
10149         case ZERO_EXTEND:
10150           mode = GET_MODE (XEXP (op0, 0));
10151           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10152               && (unsigned_comparison_p || equality_comparison_p)
10153               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10154               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10155               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10156             {
10157               op0 = XEXP (op0, 0);
10158               continue;
10159             }
10160           break;
10161
10162         case PLUS:
10163           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10164              this for equality comparisons due to pathological cases involving
10165              overflows.  */
10166           if (equality_comparison_p
10167               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10168                                                         op1, XEXP (op0, 1))))
10169             {
10170               op0 = XEXP (op0, 0);
10171               op1 = tem;
10172               continue;
10173             }
10174
10175           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10176           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10177               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10178             {
10179               op0 = XEXP (XEXP (op0, 0), 0);
10180               code = (code == LT ? EQ : NE);
10181               continue;
10182             }
10183           break;
10184
10185         case MINUS:
10186           /* We used to optimize signed comparisons against zero, but that
10187              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10188              arrive here as equality comparisons, or (GEU, LTU) are
10189              optimized away.  No need to special-case them.  */
10190
10191           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10192              (eq B (minus A C)), whichever simplifies.  We can only do
10193              this for equality comparisons due to pathological cases involving
10194              overflows.  */
10195           if (equality_comparison_p
10196               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10197                                                         XEXP (op0, 1), op1)))
10198             {
10199               op0 = XEXP (op0, 0);
10200               op1 = tem;
10201               continue;
10202             }
10203
10204           if (equality_comparison_p
10205               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10206                                                         XEXP (op0, 0), op1)))
10207             {
10208               op0 = XEXP (op0, 1);
10209               op1 = tem;
10210               continue;
10211             }
10212
10213           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10214              of bits in X minus 1, is one iff X > 0.  */
10215           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10216               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10217               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10218                  == mode_width - 1
10219               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10220             {
10221               op0 = XEXP (op0, 1);
10222               code = (code == GE ? LE : GT);
10223               continue;
10224             }
10225           break;
10226
10227         case XOR:
10228           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10229              if C is zero or B is a constant.  */
10230           if (equality_comparison_p
10231               && 0 != (tem = simplify_binary_operation (XOR, mode,
10232                                                         XEXP (op0, 1), op1)))
10233             {
10234               op0 = XEXP (op0, 0);
10235               op1 = tem;
10236               continue;
10237             }
10238           break;
10239
10240         case EQ:  case NE:
10241         case UNEQ:  case LTGT:
10242         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10243         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10244         case UNORDERED: case ORDERED:
10245           /* We can't do anything if OP0 is a condition code value, rather
10246              than an actual data value.  */
10247           if (const_op != 0
10248               || CC0_P (XEXP (op0, 0))
10249               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10250             break;
10251
10252           /* Get the two operands being compared.  */
10253           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10254             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10255           else
10256             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10257
10258           /* Check for the cases where we simply want the result of the
10259              earlier test or the opposite of that result.  */
10260           if (code == NE || code == EQ
10261               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10262                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10263                   && (STORE_FLAG_VALUE
10264                       & (((HOST_WIDE_INT) 1
10265                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10266                   && (code == LT || code == GE)))
10267             {
10268               enum rtx_code new_code;
10269               if (code == LT || code == NE)
10270                 new_code = GET_CODE (op0);
10271               else
10272                 new_code = reversed_comparison_code (op0, NULL);
10273
10274               if (new_code != UNKNOWN)
10275                 {
10276                   code = new_code;
10277                   op0 = tem;
10278                   op1 = tem1;
10279                   continue;
10280                 }
10281             }
10282           break;
10283
10284         case IOR:
10285           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10286              iff X <= 0.  */
10287           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10288               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10289               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10290             {
10291               op0 = XEXP (op0, 1);
10292               code = (code == GE ? GT : LE);
10293               continue;
10294             }
10295           break;
10296
10297         case AND:
10298           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10299              will be converted to a ZERO_EXTRACT later.  */
10300           if (const_op == 0 && equality_comparison_p
10301               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10302               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10303             {
10304               op0 = simplify_and_const_int
10305                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10306                                                    XEXP (op0, 1),
10307                                                    XEXP (XEXP (op0, 0), 1)),
10308                  (HOST_WIDE_INT) 1);
10309               continue;
10310             }
10311
10312           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10313              zero and X is a comparison and C1 and C2 describe only bits set
10314              in STORE_FLAG_VALUE, we can compare with X.  */
10315           if (const_op == 0 && equality_comparison_p
10316               && mode_width <= HOST_BITS_PER_WIDE_INT
10317               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10318               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10319               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10320               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10321               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10322             {
10323               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10324                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10325               if ((~STORE_FLAG_VALUE & mask) == 0
10326                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10327                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10328                           && COMPARISON_P (tem))))
10329                 {
10330                   op0 = XEXP (XEXP (op0, 0), 0);
10331                   continue;
10332                 }
10333             }
10334
10335           /* If we are doing an equality comparison of an AND of a bit equal
10336              to the sign bit, replace this with a LT or GE comparison of
10337              the underlying value.  */
10338           if (equality_comparison_p
10339               && const_op == 0
10340               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10341               && mode_width <= HOST_BITS_PER_WIDE_INT
10342               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10343                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10344             {
10345               op0 = XEXP (op0, 0);
10346               code = (code == EQ ? GE : LT);
10347               continue;
10348             }
10349
10350           /* If this AND operation is really a ZERO_EXTEND from a narrower
10351              mode, the constant fits within that mode, and this is either an
10352              equality or unsigned comparison, try to do this comparison in
10353              the narrower mode.  */
10354           if ((equality_comparison_p || unsigned_comparison_p)
10355               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10356               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10357                                    & GET_MODE_MASK (mode))
10358                                   + 1)) >= 0
10359               && const_op >> i == 0
10360               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10361             {
10362               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10363               continue;
10364             }
10365
10366           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10367              fits in both M1 and M2 and the SUBREG is either paradoxical
10368              or represents the low part, permute the SUBREG and the AND
10369              and try again.  */
10370           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10371             {
10372               unsigned HOST_WIDE_INT c1;
10373               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10374               /* Require an integral mode, to avoid creating something like
10375                  (AND:SF ...).  */
10376               if (SCALAR_INT_MODE_P (tmode)
10377                   /* It is unsafe to commute the AND into the SUBREG if the
10378                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10379                      not defined.  As originally written the upper bits
10380                      have a defined value due to the AND operation.
10381                      However, if we commute the AND inside the SUBREG then
10382                      they no longer have defined values and the meaning of
10383                      the code has been changed.  */
10384                   && (0
10385 #ifdef WORD_REGISTER_OPERATIONS
10386                       || (mode_width > GET_MODE_BITSIZE (tmode)
10387                           && mode_width <= BITS_PER_WORD)
10388 #endif
10389                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10390                           && subreg_lowpart_p (XEXP (op0, 0))))
10391                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10392                   && mode_width <= HOST_BITS_PER_WIDE_INT
10393                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10394                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10395                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10396                   && c1 != mask
10397                   && c1 != GET_MODE_MASK (tmode))
10398                 {
10399                   op0 = simplify_gen_binary (AND, tmode,
10400                                              SUBREG_REG (XEXP (op0, 0)),
10401                                              gen_int_mode (c1, tmode));
10402                   op0 = gen_lowpart (mode, op0);
10403                   continue;
10404                 }
10405             }
10406
10407           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10408           if (const_op == 0 && equality_comparison_p
10409               && XEXP (op0, 1) == const1_rtx
10410               && GET_CODE (XEXP (op0, 0)) == NOT)
10411             {
10412               op0 = simplify_and_const_int
10413                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10414               code = (code == NE ? EQ : NE);
10415               continue;
10416             }
10417
10418           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10419              (eq (and (lshiftrt X) 1) 0).
10420              Also handle the case where (not X) is expressed using xor.  */
10421           if (const_op == 0 && equality_comparison_p
10422               && XEXP (op0, 1) == const1_rtx
10423               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10424             {
10425               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10426               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10427
10428               if (GET_CODE (shift_op) == NOT
10429                   || (GET_CODE (shift_op) == XOR
10430                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10431                       && GET_CODE (shift_count) == CONST_INT
10432                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10433                       && (INTVAL (XEXP (shift_op, 1))
10434                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10435                 {
10436                   op0 = simplify_and_const_int
10437                     (NULL_RTX, mode,
10438                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10439                      (HOST_WIDE_INT) 1);
10440                   code = (code == NE ? EQ : NE);
10441                   continue;
10442                 }
10443             }
10444           break;
10445
10446         case ASHIFT:
10447           /* If we have (compare (ashift FOO N) (const_int C)) and
10448              the high order N bits of FOO (N+1 if an inequality comparison)
10449              are known to be zero, we can do this by comparing FOO with C
10450              shifted right N bits so long as the low-order N bits of C are
10451              zero.  */
10452           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10453               && INTVAL (XEXP (op0, 1)) >= 0
10454               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10455                   < HOST_BITS_PER_WIDE_INT)
10456               && ((const_op
10457                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10458               && mode_width <= HOST_BITS_PER_WIDE_INT
10459               && (nonzero_bits (XEXP (op0, 0), mode)
10460                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10461                                + ! equality_comparison_p))) == 0)
10462             {
10463               /* We must perform a logical shift, not an arithmetic one,
10464                  as we want the top N bits of C to be zero.  */
10465               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10466
10467               temp >>= INTVAL (XEXP (op0, 1));
10468               op1 = gen_int_mode (temp, mode);
10469               op0 = XEXP (op0, 0);
10470               continue;
10471             }
10472
10473           /* If we are doing a sign bit comparison, it means we are testing
10474              a particular bit.  Convert it to the appropriate AND.  */
10475           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476               && mode_width <= HOST_BITS_PER_WIDE_INT)
10477             {
10478               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10479                                             ((HOST_WIDE_INT) 1
10480                                              << (mode_width - 1
10481                                                  - INTVAL (XEXP (op0, 1)))));
10482               code = (code == LT ? NE : EQ);
10483               continue;
10484             }
10485
10486           /* If this an equality comparison with zero and we are shifting
10487              the low bit to the sign bit, we can convert this to an AND of the
10488              low-order bit.  */
10489           if (const_op == 0 && equality_comparison_p
10490               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10491               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10492                  == mode_width - 1)
10493             {
10494               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10495                                             (HOST_WIDE_INT) 1);
10496               continue;
10497             }
10498           break;
10499
10500         case ASHIFTRT:
10501           /* If this is an equality comparison with zero, we can do this
10502              as a logical shift, which might be much simpler.  */
10503           if (equality_comparison_p && const_op == 0
10504               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10505             {
10506               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10507                                           XEXP (op0, 0),
10508                                           INTVAL (XEXP (op0, 1)));
10509               continue;
10510             }
10511
10512           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10513              do the comparison in a narrower mode.  */
10514           if (! unsigned_comparison_p
10515               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10516               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10517               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10518               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10519                                          MODE_INT, 1)) != BLKmode
10520               && (((unsigned HOST_WIDE_INT) const_op
10521                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10522                   <= GET_MODE_MASK (tmode)))
10523             {
10524               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10525               continue;
10526             }
10527
10528           /* Likewise if OP0 is a PLUS of a sign extension with a
10529              constant, which is usually represented with the PLUS
10530              between the shifts.  */
10531           if (! unsigned_comparison_p
10532               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10533               && GET_CODE (XEXP (op0, 0)) == PLUS
10534               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10535               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10536               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10537               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10538                                          MODE_INT, 1)) != BLKmode
10539               && (((unsigned HOST_WIDE_INT) const_op
10540                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10541                   <= GET_MODE_MASK (tmode)))
10542             {
10543               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10544               rtx add_const = XEXP (XEXP (op0, 0), 1);
10545               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10546                                                    add_const, XEXP (op0, 1));
10547
10548               op0 = simplify_gen_binary (PLUS, tmode,
10549                                          gen_lowpart (tmode, inner),
10550                                          new_const);
10551               continue;
10552             }
10553
10554           /* ... fall through ...  */
10555         case LSHIFTRT:
10556           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10557              the low order N bits of FOO are known to be zero, we can do this
10558              by comparing FOO with C shifted left N bits so long as no
10559              overflow occurs.  */
10560           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10561               && INTVAL (XEXP (op0, 1)) >= 0
10562               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10563               && mode_width <= HOST_BITS_PER_WIDE_INT
10564               && (nonzero_bits (XEXP (op0, 0), mode)
10565                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10566               && (((unsigned HOST_WIDE_INT) const_op
10567                    + (GET_CODE (op0) != LSHIFTRT
10568                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10569                          + 1)
10570                       : 0))
10571                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10572             {
10573               /* If the shift was logical, then we must make the condition
10574                  unsigned.  */
10575               if (GET_CODE (op0) == LSHIFTRT)
10576                 code = unsigned_condition (code);
10577
10578               const_op <<= INTVAL (XEXP (op0, 1));
10579               op1 = GEN_INT (const_op);
10580               op0 = XEXP (op0, 0);
10581               continue;
10582             }
10583
10584           /* If we are using this shift to extract just the sign bit, we
10585              can replace this with an LT or GE comparison.  */
10586           if (const_op == 0
10587               && (equality_comparison_p || sign_bit_comparison_p)
10588               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10589               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10590                  == mode_width - 1)
10591             {
10592               op0 = XEXP (op0, 0);
10593               code = (code == NE || code == GT ? LT : GE);
10594               continue;
10595             }
10596           break;
10597
10598         default:
10599           break;
10600         }
10601
10602       break;
10603     }
10604
10605   /* Now make any compound operations involved in this comparison.  Then,
10606      check for an outmost SUBREG on OP0 that is not doing anything or is
10607      paradoxical.  The latter transformation must only be performed when
10608      it is known that the "extra" bits will be the same in op0 and op1 or
10609      that they don't matter.  There are three cases to consider:
10610
10611      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10612      care bits and we can assume they have any convenient value.  So
10613      making the transformation is safe.
10614
10615      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10616      In this case the upper bits of op0 are undefined.  We should not make
10617      the simplification in that case as we do not know the contents of
10618      those bits.
10619
10620      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10621      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10622      also be sure that they are the same as the upper bits of op1.
10623
10624      We can never remove a SUBREG for a non-equality comparison because
10625      the sign bit is in a different place in the underlying object.  */
10626
10627   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10628   op1 = make_compound_operation (op1, SET);
10629
10630   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10631       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10632       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10633       && (code == NE || code == EQ))
10634     {
10635       if (GET_MODE_SIZE (GET_MODE (op0))
10636           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10637         {
10638           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10639              implemented.  */
10640           if (REG_P (SUBREG_REG (op0)))
10641             {
10642               op0 = SUBREG_REG (op0);
10643               op1 = gen_lowpart (GET_MODE (op0), op1);
10644             }
10645         }
10646       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10647                 <= HOST_BITS_PER_WIDE_INT)
10648                && (nonzero_bits (SUBREG_REG (op0),
10649                                  GET_MODE (SUBREG_REG (op0)))
10650                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10651         {
10652           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10653
10654           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10655                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10656             op0 = SUBREG_REG (op0), op1 = tem;
10657         }
10658     }
10659
10660   /* We now do the opposite procedure: Some machines don't have compare
10661      insns in all modes.  If OP0's mode is an integer mode smaller than a
10662      word and we can't do a compare in that mode, see if there is a larger
10663      mode for which we can do the compare.  There are a number of cases in
10664      which we can use the wider mode.  */
10665
10666   mode = GET_MODE (op0);
10667   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10668       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10669       && ! have_insn_for (COMPARE, mode))
10670     for (tmode = GET_MODE_WIDER_MODE (mode);
10671          (tmode != VOIDmode
10672           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10673          tmode = GET_MODE_WIDER_MODE (tmode))
10674       if (have_insn_for (COMPARE, tmode))
10675         {
10676           int zero_extended;
10677
10678           /* If the only nonzero bits in OP0 and OP1 are those in the
10679              narrower mode and this is an equality or unsigned comparison,
10680              we can use the wider mode.  Similarly for sign-extended
10681              values, in which case it is true for all comparisons.  */
10682           zero_extended = ((code == EQ || code == NE
10683                             || code == GEU || code == GTU
10684                             || code == LEU || code == LTU)
10685                            && (nonzero_bits (op0, tmode)
10686                                & ~GET_MODE_MASK (mode)) == 0
10687                            && ((GET_CODE (op1) == CONST_INT
10688                                 || (nonzero_bits (op1, tmode)
10689                                     & ~GET_MODE_MASK (mode)) == 0)));
10690
10691           if (zero_extended
10692               || ((num_sign_bit_copies (op0, tmode)
10693                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10694                                      - GET_MODE_BITSIZE (mode)))
10695                   && (num_sign_bit_copies (op1, tmode)
10696                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10697                                         - GET_MODE_BITSIZE (mode)))))
10698             {
10699               /* If OP0 is an AND and we don't have an AND in MODE either,
10700                  make a new AND in the proper mode.  */
10701               if (GET_CODE (op0) == AND
10702                   && !have_insn_for (AND, mode))
10703                 op0 = simplify_gen_binary (AND, tmode,
10704                                            gen_lowpart (tmode,
10705                                                         XEXP (op0, 0)),
10706                                            gen_lowpart (tmode,
10707                                                         XEXP (op0, 1)));
10708
10709               op0 = gen_lowpart (tmode, op0);
10710               if (zero_extended && GET_CODE (op1) == CONST_INT)
10711                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10712               op1 = gen_lowpart (tmode, op1);
10713               break;
10714             }
10715
10716           /* If this is a test for negative, we can make an explicit
10717              test of the sign bit.  */
10718
10719           if (op1 == const0_rtx && (code == LT || code == GE)
10720               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10721             {
10722               op0 = simplify_gen_binary (AND, tmode,
10723                                          gen_lowpart (tmode, op0),
10724                                          GEN_INT ((HOST_WIDE_INT) 1
10725                                                   << (GET_MODE_BITSIZE (mode)
10726                                                       - 1)));
10727               code = (code == LT) ? NE : EQ;
10728               break;
10729             }
10730         }
10731
10732 #ifdef CANONICALIZE_COMPARISON
10733   /* If this machine only supports a subset of valid comparisons, see if we
10734      can convert an unsupported one into a supported one.  */
10735   CANONICALIZE_COMPARISON (code, op0, op1);
10736 #endif
10737
10738   *pop0 = op0;
10739   *pop1 = op1;
10740
10741   return code;
10742 }
10743 \f
10744 /* Utility function for record_value_for_reg.  Count number of
10745    rtxs in X.  */
10746 static int
10747 count_rtxs (rtx x)
10748 {
10749   enum rtx_code code = GET_CODE (x);
10750   const char *fmt;
10751   int i, ret = 1;
10752
10753   if (GET_RTX_CLASS (code) == '2'
10754       || GET_RTX_CLASS (code) == 'c')
10755     {
10756       rtx x0 = XEXP (x, 0);
10757       rtx x1 = XEXP (x, 1);
10758
10759       if (x0 == x1)
10760         return 1 + 2 * count_rtxs (x0);
10761
10762       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10763            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10764           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10765         return 2 + 2 * count_rtxs (x0)
10766                + count_rtxs (x == XEXP (x1, 0)
10767                              ? XEXP (x1, 1) : XEXP (x1, 0));
10768
10769       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10770            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10771           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10772         return 2 + 2 * count_rtxs (x1)
10773                + count_rtxs (x == XEXP (x0, 0)
10774                              ? XEXP (x0, 1) : XEXP (x0, 0));
10775     }
10776
10777   fmt = GET_RTX_FORMAT (code);
10778   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10779     if (fmt[i] == 'e')
10780       ret += count_rtxs (XEXP (x, i));
10781
10782   return ret;
10783 }
10784 \f
10785 /* Utility function for following routine.  Called when X is part of a value
10786    being stored into last_set_value.  Sets last_set_table_tick
10787    for each register mentioned.  Similar to mention_regs in cse.c  */
10788
10789 static void
10790 update_table_tick (rtx x)
10791 {
10792   enum rtx_code code = GET_CODE (x);
10793   const char *fmt = GET_RTX_FORMAT (code);
10794   int i;
10795
10796   if (code == REG)
10797     {
10798       unsigned int regno = REGNO (x);
10799       unsigned int endregno
10800         = regno + (regno < FIRST_PSEUDO_REGISTER
10801                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10802       unsigned int r;
10803
10804       for (r = regno; r < endregno; r++)
10805         reg_stat[r].last_set_table_tick = label_tick;
10806
10807       return;
10808     }
10809
10810   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10811     /* Note that we can't have an "E" in values stored; see
10812        get_last_value_validate.  */
10813     if (fmt[i] == 'e')
10814       {
10815         /* Check for identical subexpressions.  If x contains
10816            identical subexpression we only have to traverse one of
10817            them.  */
10818         if (i == 0 && ARITHMETIC_P (x))
10819           {
10820             /* Note that at this point x1 has already been
10821                processed.  */
10822             rtx x0 = XEXP (x, 0);
10823             rtx x1 = XEXP (x, 1);
10824
10825             /* If x0 and x1 are identical then there is no need to
10826                process x0.  */
10827             if (x0 == x1)
10828               break;
10829
10830             /* If x0 is identical to a subexpression of x1 then while
10831                processing x1, x0 has already been processed.  Thus we
10832                are done with x.  */
10833             if (ARITHMETIC_P (x1)
10834                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10835               break;
10836
10837             /* If x1 is identical to a subexpression of x0 then we
10838                still have to process the rest of x0.  */
10839             if (ARITHMETIC_P (x0)
10840                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10841               {
10842                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10843                 break;
10844               }
10845           }
10846
10847         update_table_tick (XEXP (x, i));
10848       }
10849 }
10850
10851 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10852    are saying that the register is clobbered and we no longer know its
10853    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10854    only permitted with VALUE also zero and is used to invalidate the
10855    register.  */
10856
10857 static void
10858 record_value_for_reg (rtx reg, rtx insn, rtx value)
10859 {
10860   unsigned int regno = REGNO (reg);
10861   unsigned int endregno
10862     = regno + (regno < FIRST_PSEUDO_REGISTER
10863                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10864   unsigned int i;
10865
10866   /* If VALUE contains REG and we have a previous value for REG, substitute
10867      the previous value.  */
10868   if (value && insn && reg_overlap_mentioned_p (reg, value))
10869     {
10870       rtx tem;
10871
10872       /* Set things up so get_last_value is allowed to see anything set up to
10873          our insn.  */
10874       subst_low_cuid = INSN_CUID (insn);
10875       tem = get_last_value (reg);
10876
10877       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10878          it isn't going to be useful and will take a lot of time to process,
10879          so just use the CLOBBER.  */
10880
10881       if (tem)
10882         {
10883           if (ARITHMETIC_P (tem)
10884               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10885               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10886             tem = XEXP (tem, 0);
10887           else if (count_occurrences (value, reg, 1) >= 2)
10888             {
10889               /* If there are two or more occurrences of REG in VALUE,
10890                  prevent the value from growing too much.  */
10891               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10892                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10893             }
10894
10895           value = replace_rtx (copy_rtx (value), reg, tem);
10896         }
10897     }
10898
10899   /* For each register modified, show we don't know its value, that
10900      we don't know about its bitwise content, that its value has been
10901      updated, and that we don't know the location of the death of the
10902      register.  */
10903   for (i = regno; i < endregno; i++)
10904     {
10905       if (insn)
10906         reg_stat[i].last_set = insn;
10907
10908       reg_stat[i].last_set_value = 0;
10909       reg_stat[i].last_set_mode = 0;
10910       reg_stat[i].last_set_nonzero_bits = 0;
10911       reg_stat[i].last_set_sign_bit_copies = 0;
10912       reg_stat[i].last_death = 0;
10913       reg_stat[i].truncated_to_mode = 0;
10914     }
10915
10916   /* Mark registers that are being referenced in this value.  */
10917   if (value)
10918     update_table_tick (value);
10919
10920   /* Now update the status of each register being set.
10921      If someone is using this register in this block, set this register
10922      to invalid since we will get confused between the two lives in this
10923      basic block.  This makes using this register always invalid.  In cse, we
10924      scan the table to invalidate all entries using this register, but this
10925      is too much work for us.  */
10926
10927   for (i = regno; i < endregno; i++)
10928     {
10929       reg_stat[i].last_set_label = label_tick;
10930       if (value && reg_stat[i].last_set_table_tick == label_tick)
10931         reg_stat[i].last_set_invalid = 1;
10932       else
10933         reg_stat[i].last_set_invalid = 0;
10934     }
10935
10936   /* The value being assigned might refer to X (like in "x++;").  In that
10937      case, we must replace it with (clobber (const_int 0)) to prevent
10938      infinite loops.  */
10939   if (value && ! get_last_value_validate (&value, insn,
10940                                           reg_stat[regno].last_set_label, 0))
10941     {
10942       value = copy_rtx (value);
10943       if (! get_last_value_validate (&value, insn,
10944                                      reg_stat[regno].last_set_label, 1))
10945         value = 0;
10946     }
10947
10948   /* For the main register being modified, update the value, the mode, the
10949      nonzero bits, and the number of sign bit copies.  */
10950
10951   reg_stat[regno].last_set_value = value;
10952
10953   if (value)
10954     {
10955       enum machine_mode mode = GET_MODE (reg);
10956       subst_low_cuid = INSN_CUID (insn);
10957       reg_stat[regno].last_set_mode = mode;
10958       if (GET_MODE_CLASS (mode) == MODE_INT
10959           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10960         mode = nonzero_bits_mode;
10961       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10962       reg_stat[regno].last_set_sign_bit_copies
10963         = num_sign_bit_copies (value, GET_MODE (reg));
10964     }
10965 }
10966
10967 /* Called via note_stores from record_dead_and_set_regs to handle one
10968    SET or CLOBBER in an insn.  DATA is the instruction in which the
10969    set is occurring.  */
10970
10971 static void
10972 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10973 {
10974   rtx record_dead_insn = (rtx) data;
10975
10976   if (GET_CODE (dest) == SUBREG)
10977     dest = SUBREG_REG (dest);
10978
10979   if (REG_P (dest))
10980     {
10981       /* If we are setting the whole register, we know its value.  Otherwise
10982          show that we don't know the value.  We can handle SUBREG in
10983          some cases.  */
10984       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10985         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10986       else if (GET_CODE (setter) == SET
10987                && GET_CODE (SET_DEST (setter)) == SUBREG
10988                && SUBREG_REG (SET_DEST (setter)) == dest
10989                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10990                && subreg_lowpart_p (SET_DEST (setter)))
10991         record_value_for_reg (dest, record_dead_insn,
10992                               gen_lowpart (GET_MODE (dest),
10993                                                        SET_SRC (setter)));
10994       else
10995         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10996     }
10997   else if (MEM_P (dest)
10998            /* Ignore pushes, they clobber nothing.  */
10999            && ! push_operand (dest, GET_MODE (dest)))
11000     mem_last_set = INSN_CUID (record_dead_insn);
11001 }
11002
11003 /* Update the records of when each REG was most recently set or killed
11004    for the things done by INSN.  This is the last thing done in processing
11005    INSN in the combiner loop.
11006
11007    We update reg_stat[], in particular fields last_set, last_set_value,
11008    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11009    last_death, and also the similar information mem_last_set (which insn
11010    most recently modified memory) and last_call_cuid (which insn was the
11011    most recent subroutine call).  */
11012
11013 static void
11014 record_dead_and_set_regs (rtx insn)
11015 {
11016   rtx link;
11017   unsigned int i;
11018
11019   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11020     {
11021       if (REG_NOTE_KIND (link) == REG_DEAD
11022           && REG_P (XEXP (link, 0)))
11023         {
11024           unsigned int regno = REGNO (XEXP (link, 0));
11025           unsigned int endregno
11026             = regno + (regno < FIRST_PSEUDO_REGISTER
11027                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11028                        : 1);
11029
11030           for (i = regno; i < endregno; i++)
11031             reg_stat[i].last_death = insn;
11032         }
11033       else if (REG_NOTE_KIND (link) == REG_INC)
11034         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11035     }
11036
11037   if (CALL_P (insn))
11038     {
11039       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11040         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11041           {
11042             reg_stat[i].last_set_value = 0;
11043             reg_stat[i].last_set_mode = 0;
11044             reg_stat[i].last_set_nonzero_bits = 0;
11045             reg_stat[i].last_set_sign_bit_copies = 0;
11046             reg_stat[i].last_death = 0;
11047             reg_stat[i].truncated_to_mode = 0;
11048           }
11049
11050       last_call_cuid = mem_last_set = INSN_CUID (insn);
11051
11052       /* Don't bother recording what this insn does.  It might set the
11053          return value register, but we can't combine into a call
11054          pattern anyway, so there's no point trying (and it may cause
11055          a crash, if e.g. we wind up asking for last_set_value of a
11056          SUBREG of the return value register).  */
11057       return;
11058     }
11059
11060   note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11061 }
11062
11063 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11064    register present in the SUBREG, so for each such SUBREG go back and
11065    adjust nonzero and sign bit information of the registers that are
11066    known to have some zero/sign bits set.
11067
11068    This is needed because when combine blows the SUBREGs away, the
11069    information on zero/sign bits is lost and further combines can be
11070    missed because of that.  */
11071
11072 static void
11073 record_promoted_value (rtx insn, rtx subreg)
11074 {
11075   rtx links, set;
11076   unsigned int regno = REGNO (SUBREG_REG (subreg));
11077   enum machine_mode mode = GET_MODE (subreg);
11078
11079   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11080     return;
11081
11082   for (links = LOG_LINKS (insn); links;)
11083     {
11084       insn = XEXP (links, 0);
11085       set = single_set (insn);
11086
11087       if (! set || !REG_P (SET_DEST (set))
11088           || REGNO (SET_DEST (set)) != regno
11089           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11090         {
11091           links = XEXP (links, 1);
11092           continue;
11093         }
11094
11095       if (reg_stat[regno].last_set == insn)
11096         {
11097           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11098             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11099         }
11100
11101       if (REG_P (SET_SRC (set)))
11102         {
11103           regno = REGNO (SET_SRC (set));
11104           links = LOG_LINKS (insn);
11105         }
11106       else
11107         break;
11108     }
11109 }
11110
11111 /* Check if X, a register, is known to contain a value already
11112    truncated to MODE.  In this case we can use a subreg to refer to
11113    the truncated value even though in the generic case we would need
11114    an explicit truncation.  */
11115
11116 static bool
11117 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11118 {
11119   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11120
11121   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11122     return false;
11123   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11124     return true;
11125   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11126                              GET_MODE_BITSIZE (truncated)))
11127     return true;
11128   return false;
11129 }
11130
11131 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11132    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11133    a truncate into a subreg using this information.  */
11134
11135 static void
11136 record_truncated_value (rtx x)
11137 {
11138   enum machine_mode truncated_mode;
11139
11140   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11141     {
11142       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11143       truncated_mode = GET_MODE (x);
11144
11145       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11146         return;
11147
11148       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11149                                  GET_MODE_BITSIZE (original_mode)))
11150         return;
11151
11152       x = SUBREG_REG (x);
11153     }
11154   /* ??? For hard-regs we now record everthing.  We might be able to
11155      optimize this using last_set_mode.  */
11156   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11157     truncated_mode = GET_MODE (x);
11158   else
11159     return;
11160
11161   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11162       || reg_stat[REGNO (x)].truncation_label < label_tick
11163       || (GET_MODE_SIZE (truncated_mode)
11164           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11165     {
11166       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11167       reg_stat[REGNO (x)].truncation_label = label_tick;
11168     }
11169 }
11170
11171 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11172    found, note what it implies to the registers used in it.  */
11173
11174 static void
11175 check_conversions (rtx insn, rtx x)
11176 {
11177   if (GET_CODE (x) == SUBREG || REG_P (x))
11178     {
11179       if (GET_CODE (x) == SUBREG
11180           && SUBREG_PROMOTED_VAR_P (x)
11181           && REG_P (SUBREG_REG (x)))
11182         record_promoted_value (insn, x);
11183
11184       record_truncated_value (x);
11185     }
11186   else
11187     {
11188       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11189       int i, j;
11190
11191       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11192         switch (format[i])
11193           {
11194           case 'e':
11195             check_conversions (insn, XEXP (x, i));
11196             break;
11197           case 'V':
11198           case 'E':
11199             if (XVEC (x, i) != 0)
11200               for (j = 0; j < XVECLEN (x, i); j++)
11201                 check_conversions (insn, XVECEXP (x, i, j));
11202             break;
11203           }
11204     }
11205 }
11206 \f
11207 /* Utility routine for the following function.  Verify that all the registers
11208    mentioned in *LOC are valid when *LOC was part of a value set when
11209    label_tick == TICK.  Return 0 if some are not.
11210
11211    If REPLACE is nonzero, replace the invalid reference with
11212    (clobber (const_int 0)) and return 1.  This replacement is useful because
11213    we often can get useful information about the form of a value (e.g., if
11214    it was produced by a shift that always produces -1 or 0) even though
11215    we don't know exactly what registers it was produced from.  */
11216
11217 static int
11218 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11219 {
11220   rtx x = *loc;
11221   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11222   int len = GET_RTX_LENGTH (GET_CODE (x));
11223   int i;
11224
11225   if (REG_P (x))
11226     {
11227       unsigned int regno = REGNO (x);
11228       unsigned int endregno
11229         = regno + (regno < FIRST_PSEUDO_REGISTER
11230                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11231       unsigned int j;
11232
11233       for (j = regno; j < endregno; j++)
11234         if (reg_stat[j].last_set_invalid
11235             /* If this is a pseudo-register that was only set once and not
11236                live at the beginning of the function, it is always valid.  */
11237             || (! (regno >= FIRST_PSEUDO_REGISTER
11238                    && REG_N_SETS (regno) == 1
11239                    && (! REGNO_REG_SET_P
11240                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11241                         regno)))
11242                 && reg_stat[j].last_set_label > tick))
11243           {
11244             if (replace)
11245               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11246             return replace;
11247           }
11248
11249       return 1;
11250     }
11251   /* If this is a memory reference, make sure that there were
11252      no stores after it that might have clobbered the value.  We don't
11253      have alias info, so we assume any store invalidates it.  */
11254   else if (MEM_P (x) && !MEM_READONLY_P (x)
11255            && INSN_CUID (insn) <= mem_last_set)
11256     {
11257       if (replace)
11258         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11259       return replace;
11260     }
11261
11262   for (i = 0; i < len; i++)
11263     {
11264       if (fmt[i] == 'e')
11265         {
11266           /* Check for identical subexpressions.  If x contains
11267              identical subexpression we only have to traverse one of
11268              them.  */
11269           if (i == 1 && ARITHMETIC_P (x))
11270             {
11271               /* Note that at this point x0 has already been checked
11272                  and found valid.  */
11273               rtx x0 = XEXP (x, 0);
11274               rtx x1 = XEXP (x, 1);
11275
11276               /* If x0 and x1 are identical then x is also valid.  */
11277               if (x0 == x1)
11278                 return 1;
11279
11280               /* If x1 is identical to a subexpression of x0 then
11281                  while checking x0, x1 has already been checked.  Thus
11282                  it is valid and so as x.  */
11283               if (ARITHMETIC_P (x0)
11284                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11285                 return 1;
11286
11287               /* If x0 is identical to a subexpression of x1 then x is
11288                  valid iff the rest of x1 is valid.  */
11289               if (ARITHMETIC_P (x1)
11290                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11291                 return
11292                   get_last_value_validate (&XEXP (x1,
11293                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11294                                            insn, tick, replace);
11295             }
11296
11297           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11298                                        replace) == 0)
11299             return 0;
11300         }
11301       /* Don't bother with these.  They shouldn't occur anyway.  */
11302       else if (fmt[i] == 'E')
11303         return 0;
11304     }
11305
11306   /* If we haven't found a reason for it to be invalid, it is valid.  */
11307   return 1;
11308 }
11309
11310 /* Get the last value assigned to X, if known.  Some registers
11311    in the value may be replaced with (clobber (const_int 0)) if their value
11312    is known longer known reliably.  */
11313
11314 static rtx
11315 get_last_value (rtx x)
11316 {
11317   unsigned int regno;
11318   rtx value;
11319
11320   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11321      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11322      we cannot predict what values the "extra" bits might have.  */
11323   if (GET_CODE (x) == SUBREG
11324       && subreg_lowpart_p (x)
11325       && (GET_MODE_SIZE (GET_MODE (x))
11326           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11327       && (value = get_last_value (SUBREG_REG (x))) != 0)
11328     return gen_lowpart (GET_MODE (x), value);
11329
11330   if (!REG_P (x))
11331     return 0;
11332
11333   regno = REGNO (x);
11334   value = reg_stat[regno].last_set_value;
11335
11336   /* If we don't have a value, or if it isn't for this basic block and
11337      it's either a hard register, set more than once, or it's a live
11338      at the beginning of the function, return 0.
11339
11340      Because if it's not live at the beginning of the function then the reg
11341      is always set before being used (is never used without being set).
11342      And, if it's set only once, and it's always set before use, then all
11343      uses must have the same last value, even if it's not from this basic
11344      block.  */
11345
11346   if (value == 0
11347       || (reg_stat[regno].last_set_label != label_tick
11348           && (regno < FIRST_PSEUDO_REGISTER
11349               || REG_N_SETS (regno) != 1
11350               || (REGNO_REG_SET_P
11351                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11352                    regno)))))
11353     return 0;
11354
11355   /* If the value was set in a later insn than the ones we are processing,
11356      we can't use it even if the register was only set once.  */
11357   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11358     return 0;
11359
11360   /* If the value has all its registers valid, return it.  */
11361   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11362                                reg_stat[regno].last_set_label, 0))
11363     return value;
11364
11365   /* Otherwise, make a copy and replace any invalid register with
11366      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11367
11368   value = copy_rtx (value);
11369   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11370                                reg_stat[regno].last_set_label, 1))
11371     return value;
11372
11373   return 0;
11374 }
11375 \f
11376 /* Return nonzero if expression X refers to a REG or to memory
11377    that is set in an instruction more recent than FROM_CUID.  */
11378
11379 static int
11380 use_crosses_set_p (rtx x, int from_cuid)
11381 {
11382   const char *fmt;
11383   int i;
11384   enum rtx_code code = GET_CODE (x);
11385
11386   if (code == REG)
11387     {
11388       unsigned int regno = REGNO (x);
11389       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11390                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11391
11392 #ifdef PUSH_ROUNDING
11393       /* Don't allow uses of the stack pointer to be moved,
11394          because we don't know whether the move crosses a push insn.  */
11395       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11396         return 1;
11397 #endif
11398       for (; regno < endreg; regno++)
11399         if (reg_stat[regno].last_set
11400             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11401           return 1;
11402       return 0;
11403     }
11404
11405   if (code == MEM && mem_last_set > from_cuid)
11406     return 1;
11407
11408   fmt = GET_RTX_FORMAT (code);
11409
11410   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11411     {
11412       if (fmt[i] == 'E')
11413         {
11414           int j;
11415           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11416             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11417               return 1;
11418         }
11419       else if (fmt[i] == 'e'
11420                && use_crosses_set_p (XEXP (x, i), from_cuid))
11421         return 1;
11422     }
11423   return 0;
11424 }
11425 \f
11426 /* Define three variables used for communication between the following
11427    routines.  */
11428
11429 static unsigned int reg_dead_regno, reg_dead_endregno;
11430 static int reg_dead_flag;
11431
11432 /* Function called via note_stores from reg_dead_at_p.
11433
11434    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11435    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11436
11437 static void
11438 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11439 {
11440   unsigned int regno, endregno;
11441
11442   if (!REG_P (dest))
11443     return;
11444
11445   regno = REGNO (dest);
11446   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11447                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11448
11449   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11450     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11451 }
11452
11453 /* Return nonzero if REG is known to be dead at INSN.
11454
11455    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11456    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11457    live.  Otherwise, see if it is live or dead at the start of the basic
11458    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11459    must be assumed to be always live.  */
11460
11461 static int
11462 reg_dead_at_p (rtx reg, rtx insn)
11463 {
11464   basic_block block;
11465   unsigned int i;
11466
11467   /* Set variables for reg_dead_at_p_1.  */
11468   reg_dead_regno = REGNO (reg);
11469   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11470                                         ? hard_regno_nregs[reg_dead_regno]
11471                                                           [GET_MODE (reg)]
11472                                         : 1);
11473
11474   reg_dead_flag = 0;
11475
11476   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11477      we allow the machine description to decide whether use-and-clobber
11478      patterns are OK.  */
11479   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11480     {
11481       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11482         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11483           return 0;
11484     }
11485
11486   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11487      beginning of function.  */
11488   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11489        insn = prev_nonnote_insn (insn))
11490     {
11491       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11492       if (reg_dead_flag)
11493         return reg_dead_flag == 1 ? 1 : 0;
11494
11495       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11496         return 1;
11497     }
11498
11499   /* Get the basic block that we were in.  */
11500   if (insn == 0)
11501     block = ENTRY_BLOCK_PTR->next_bb;
11502   else
11503     {
11504       FOR_EACH_BB (block)
11505         if (insn == BB_HEAD (block))
11506           break;
11507
11508       if (block == EXIT_BLOCK_PTR)
11509         return 0;
11510     }
11511
11512   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11513     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11514       return 0;
11515
11516   return 1;
11517 }
11518 \f
11519 /* Note hard registers in X that are used.  This code is similar to
11520    that in flow.c, but much simpler since we don't care about pseudos.  */
11521
11522 static void
11523 mark_used_regs_combine (rtx x)
11524 {
11525   RTX_CODE code = GET_CODE (x);
11526   unsigned int regno;
11527   int i;
11528
11529   switch (code)
11530     {
11531     case LABEL_REF:
11532     case SYMBOL_REF:
11533     case CONST_INT:
11534     case CONST:
11535     case CONST_DOUBLE:
11536     case CONST_VECTOR:
11537     case PC:
11538     case ADDR_VEC:
11539     case ADDR_DIFF_VEC:
11540     case ASM_INPUT:
11541 #ifdef HAVE_cc0
11542     /* CC0 must die in the insn after it is set, so we don't need to take
11543        special note of it here.  */
11544     case CC0:
11545 #endif
11546       return;
11547
11548     case CLOBBER:
11549       /* If we are clobbering a MEM, mark any hard registers inside the
11550          address as used.  */
11551       if (MEM_P (XEXP (x, 0)))
11552         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11553       return;
11554
11555     case REG:
11556       regno = REGNO (x);
11557       /* A hard reg in a wide mode may really be multiple registers.
11558          If so, mark all of them just like the first.  */
11559       if (regno < FIRST_PSEUDO_REGISTER)
11560         {
11561           unsigned int endregno, r;
11562
11563           /* None of this applies to the stack, frame or arg pointers.  */
11564           if (regno == STACK_POINTER_REGNUM
11565 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11566               || regno == HARD_FRAME_POINTER_REGNUM
11567 #endif
11568 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11569               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11570 #endif
11571               || regno == FRAME_POINTER_REGNUM)
11572             return;
11573
11574           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11575           for (r = regno; r < endregno; r++)
11576             SET_HARD_REG_BIT (newpat_used_regs, r);
11577         }
11578       return;
11579
11580     case SET:
11581       {
11582         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11583            the address.  */
11584         rtx testreg = SET_DEST (x);
11585
11586         while (GET_CODE (testreg) == SUBREG
11587                || GET_CODE (testreg) == ZERO_EXTRACT
11588                || GET_CODE (testreg) == STRICT_LOW_PART)
11589           testreg = XEXP (testreg, 0);
11590
11591         if (MEM_P (testreg))
11592           mark_used_regs_combine (XEXP (testreg, 0));
11593
11594         mark_used_regs_combine (SET_SRC (x));
11595       }
11596       return;
11597
11598     default:
11599       break;
11600     }
11601
11602   /* Recursively scan the operands of this expression.  */
11603
11604   {
11605     const char *fmt = GET_RTX_FORMAT (code);
11606
11607     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11608       {
11609         if (fmt[i] == 'e')
11610           mark_used_regs_combine (XEXP (x, i));
11611         else if (fmt[i] == 'E')
11612           {
11613             int j;
11614
11615             for (j = 0; j < XVECLEN (x, i); j++)
11616               mark_used_regs_combine (XVECEXP (x, i, j));
11617           }
11618       }
11619   }
11620 }
11621 \f
11622 /* Remove register number REGNO from the dead registers list of INSN.
11623
11624    Return the note used to record the death, if there was one.  */
11625
11626 rtx
11627 remove_death (unsigned int regno, rtx insn)
11628 {
11629   rtx note = find_regno_note (insn, REG_DEAD, regno);
11630
11631   if (note)
11632     {
11633       REG_N_DEATHS (regno)--;
11634       remove_note (insn, note);
11635     }
11636
11637   return note;
11638 }
11639
11640 /* For each register (hardware or pseudo) used within expression X, if its
11641    death is in an instruction with cuid between FROM_CUID (inclusive) and
11642    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11643    list headed by PNOTES.
11644
11645    That said, don't move registers killed by maybe_kill_insn.
11646
11647    This is done when X is being merged by combination into TO_INSN.  These
11648    notes will then be distributed as needed.  */
11649
11650 static void
11651 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11652              rtx *pnotes)
11653 {
11654   const char *fmt;
11655   int len, i;
11656   enum rtx_code code = GET_CODE (x);
11657
11658   if (code == REG)
11659     {
11660       unsigned int regno = REGNO (x);
11661       rtx where_dead = reg_stat[regno].last_death;
11662       rtx before_dead, after_dead;
11663
11664       /* Don't move the register if it gets killed in between from and to.  */
11665       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11666           && ! reg_referenced_p (x, maybe_kill_insn))
11667         return;
11668
11669       /* WHERE_DEAD could be a USE insn made by combine, so first we
11670          make sure that we have insns with valid INSN_CUID values.  */
11671       before_dead = where_dead;
11672       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11673         before_dead = PREV_INSN (before_dead);
11674
11675       after_dead = where_dead;
11676       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11677         after_dead = NEXT_INSN (after_dead);
11678
11679       if (before_dead && after_dead
11680           && INSN_CUID (before_dead) >= from_cuid
11681           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11682               || (where_dead != after_dead
11683                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11684         {
11685           rtx note = remove_death (regno, where_dead);
11686
11687           /* It is possible for the call above to return 0.  This can occur
11688              when last_death points to I2 or I1 that we combined with.
11689              In that case make a new note.
11690
11691              We must also check for the case where X is a hard register
11692              and NOTE is a death note for a range of hard registers
11693              including X.  In that case, we must put REG_DEAD notes for
11694              the remaining registers in place of NOTE.  */
11695
11696           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11697               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11698                   > GET_MODE_SIZE (GET_MODE (x))))
11699             {
11700               unsigned int deadregno = REGNO (XEXP (note, 0));
11701               unsigned int deadend
11702                 = (deadregno + hard_regno_nregs[deadregno]
11703                                                [GET_MODE (XEXP (note, 0))]);
11704               unsigned int ourend
11705                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11706               unsigned int i;
11707
11708               for (i = deadregno; i < deadend; i++)
11709                 if (i < regno || i >= ourend)
11710                   REG_NOTES (where_dead)
11711                     = gen_rtx_EXPR_LIST (REG_DEAD,
11712                                          regno_reg_rtx[i],
11713                                          REG_NOTES (where_dead));
11714             }
11715
11716           /* If we didn't find any note, or if we found a REG_DEAD note that
11717              covers only part of the given reg, and we have a multi-reg hard
11718              register, then to be safe we must check for REG_DEAD notes
11719              for each register other than the first.  They could have
11720              their own REG_DEAD notes lying around.  */
11721           else if ((note == 0
11722                     || (note != 0
11723                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11724                             < GET_MODE_SIZE (GET_MODE (x)))))
11725                    && regno < FIRST_PSEUDO_REGISTER
11726                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11727             {
11728               unsigned int ourend
11729                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11730               unsigned int i, offset;
11731               rtx oldnotes = 0;
11732
11733               if (note)
11734                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11735               else
11736                 offset = 1;
11737
11738               for (i = regno + offset; i < ourend; i++)
11739                 move_deaths (regno_reg_rtx[i],
11740                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11741             }
11742
11743           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11744             {
11745               XEXP (note, 1) = *pnotes;
11746               *pnotes = note;
11747             }
11748           else
11749             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11750
11751           REG_N_DEATHS (regno)++;
11752         }
11753
11754       return;
11755     }
11756
11757   else if (GET_CODE (x) == SET)
11758     {
11759       rtx dest = SET_DEST (x);
11760
11761       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11762
11763       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11764          that accesses one word of a multi-word item, some
11765          piece of everything register in the expression is used by
11766          this insn, so remove any old death.  */
11767       /* ??? So why do we test for equality of the sizes?  */
11768
11769       if (GET_CODE (dest) == ZERO_EXTRACT
11770           || GET_CODE (dest) == STRICT_LOW_PART
11771           || (GET_CODE (dest) == SUBREG
11772               && (((GET_MODE_SIZE (GET_MODE (dest))
11773                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11774                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11775                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11776         {
11777           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11778           return;
11779         }
11780
11781       /* If this is some other SUBREG, we know it replaces the entire
11782          value, so use that as the destination.  */
11783       if (GET_CODE (dest) == SUBREG)
11784         dest = SUBREG_REG (dest);
11785
11786       /* If this is a MEM, adjust deaths of anything used in the address.
11787          For a REG (the only other possibility), the entire value is
11788          being replaced so the old value is not used in this insn.  */
11789
11790       if (MEM_P (dest))
11791         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11792                      to_insn, pnotes);
11793       return;
11794     }
11795
11796   else if (GET_CODE (x) == CLOBBER)
11797     return;
11798
11799   len = GET_RTX_LENGTH (code);
11800   fmt = GET_RTX_FORMAT (code);
11801
11802   for (i = 0; i < len; i++)
11803     {
11804       if (fmt[i] == 'E')
11805         {
11806           int j;
11807           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11808             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11809                          to_insn, pnotes);
11810         }
11811       else if (fmt[i] == 'e')
11812         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11813     }
11814 }
11815 \f
11816 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11817    pattern of an insn.  X must be a REG.  */
11818
11819 static int
11820 reg_bitfield_target_p (rtx x, rtx body)
11821 {
11822   int i;
11823
11824   if (GET_CODE (body) == SET)
11825     {
11826       rtx dest = SET_DEST (body);
11827       rtx target;
11828       unsigned int regno, tregno, endregno, endtregno;
11829
11830       if (GET_CODE (dest) == ZERO_EXTRACT)
11831         target = XEXP (dest, 0);
11832       else if (GET_CODE (dest) == STRICT_LOW_PART)
11833         target = SUBREG_REG (XEXP (dest, 0));
11834       else
11835         return 0;
11836
11837       if (GET_CODE (target) == SUBREG)
11838         target = SUBREG_REG (target);
11839
11840       if (!REG_P (target))
11841         return 0;
11842
11843       tregno = REGNO (target), regno = REGNO (x);
11844       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11845         return target == x;
11846
11847       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11848       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11849
11850       return endregno > tregno && regno < endtregno;
11851     }
11852
11853   else if (GET_CODE (body) == PARALLEL)
11854     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11855       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11856         return 1;
11857
11858   return 0;
11859 }
11860 \f
11861 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11862    as appropriate.  I3 and I2 are the insns resulting from the combination
11863    insns including FROM (I2 may be zero).
11864
11865    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11866    not need REG_DEAD notes because they are being substituted for.  This
11867    saves searching in the most common cases.
11868
11869    Each note in the list is either ignored or placed on some insns, depending
11870    on the type of note.  */
11871
11872 static void
11873 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11874                   rtx elim_i1)
11875 {
11876   rtx note, next_note;
11877   rtx tem;
11878
11879   for (note = notes; note; note = next_note)
11880     {
11881       rtx place = 0, place2 = 0;
11882
11883       next_note = XEXP (note, 1);
11884       switch (REG_NOTE_KIND (note))
11885         {
11886         case REG_BR_PROB:
11887         case REG_BR_PRED:
11888           /* Doesn't matter much where we put this, as long as it's somewhere.
11889              It is preferable to keep these notes on branches, which is most
11890              likely to be i3.  */
11891           place = i3;
11892           break;
11893
11894         case REG_VALUE_PROFILE:
11895           /* Just get rid of this note, as it is unused later anyway.  */
11896           break;
11897
11898         case REG_NON_LOCAL_GOTO:
11899           if (JUMP_P (i3))
11900             place = i3;
11901           else
11902             {
11903               gcc_assert (i2 && JUMP_P (i2));
11904               place = i2;
11905             }
11906           break;
11907
11908         case REG_EH_REGION:
11909           /* These notes must remain with the call or trapping instruction.  */
11910           if (CALL_P (i3))
11911             place = i3;
11912           else if (i2 && CALL_P (i2))
11913             place = i2;
11914           else
11915             {
11916               gcc_assert (flag_non_call_exceptions);
11917               if (may_trap_p (i3))
11918                 place = i3;
11919               else if (i2 && may_trap_p (i2))
11920                 place = i2;
11921               /* ??? Otherwise assume we've combined things such that we
11922                  can now prove that the instructions can't trap.  Drop the
11923                  note in this case.  */
11924             }
11925           break;
11926
11927         case REG_NORETURN:
11928         case REG_SETJMP:
11929           /* These notes must remain with the call.  It should not be
11930              possible for both I2 and I3 to be a call.  */
11931           if (CALL_P (i3))
11932             place = i3;
11933           else
11934             {
11935               gcc_assert (i2 && CALL_P (i2));
11936               place = i2;
11937             }
11938           break;
11939
11940         case REG_UNUSED:
11941           /* Any clobbers for i3 may still exist, and so we must process
11942              REG_UNUSED notes from that insn.
11943
11944              Any clobbers from i2 or i1 can only exist if they were added by
11945              recog_for_combine.  In that case, recog_for_combine created the
11946              necessary REG_UNUSED notes.  Trying to keep any original
11947              REG_UNUSED notes from these insns can cause incorrect output
11948              if it is for the same register as the original i3 dest.
11949              In that case, we will notice that the register is set in i3,
11950              and then add a REG_UNUSED note for the destination of i3, which
11951              is wrong.  However, it is possible to have REG_UNUSED notes from
11952              i2 or i1 for register which were both used and clobbered, so
11953              we keep notes from i2 or i1 if they will turn into REG_DEAD
11954              notes.  */
11955
11956           /* If this register is set or clobbered in I3, put the note there
11957              unless there is one already.  */
11958           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11959             {
11960               if (from_insn != i3)
11961                 break;
11962
11963               if (! (REG_P (XEXP (note, 0))
11964                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11965                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11966                 place = i3;
11967             }
11968           /* Otherwise, if this register is used by I3, then this register
11969              now dies here, so we must put a REG_DEAD note here unless there
11970              is one already.  */
11971           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11972                    && ! (REG_P (XEXP (note, 0))
11973                          ? find_regno_note (i3, REG_DEAD,
11974                                             REGNO (XEXP (note, 0)))
11975                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11976             {
11977               PUT_REG_NOTE_KIND (note, REG_DEAD);
11978               place = i3;
11979             }
11980           break;
11981
11982         case REG_EQUAL:
11983         case REG_EQUIV:
11984         case REG_NOALIAS:
11985           /* These notes say something about results of an insn.  We can
11986              only support them if they used to be on I3 in which case they
11987              remain on I3.  Otherwise they are ignored.
11988
11989              If the note refers to an expression that is not a constant, we
11990              must also ignore the note since we cannot tell whether the
11991              equivalence is still true.  It might be possible to do
11992              slightly better than this (we only have a problem if I2DEST
11993              or I1DEST is present in the expression), but it doesn't
11994              seem worth the trouble.  */
11995
11996           if (from_insn == i3
11997               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11998             place = i3;
11999           break;
12000
12001         case REG_INC:
12002         case REG_NO_CONFLICT:
12003           /* These notes say something about how a register is used.  They must
12004              be present on any use of the register in I2 or I3.  */
12005           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12006             place = i3;
12007
12008           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12009             {
12010               if (place)
12011                 place2 = i2;
12012               else
12013                 place = i2;
12014             }
12015           break;
12016
12017         case REG_LABEL:
12018           /* This can show up in several ways -- either directly in the
12019              pattern, or hidden off in the constant pool with (or without?)
12020              a REG_EQUAL note.  */
12021           /* ??? Ignore the without-reg_equal-note problem for now.  */
12022           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12023               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12024                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12025                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12026             place = i3;
12027
12028           if (i2
12029               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12030                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12031                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12032                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12033             {
12034               if (place)
12035                 place2 = i2;
12036               else
12037                 place = i2;
12038             }
12039
12040           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12041              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12042           if (place && JUMP_P (place))
12043             {
12044               rtx label = JUMP_LABEL (place);
12045
12046               if (!label)
12047                 JUMP_LABEL (place) = XEXP (note, 0);
12048               else
12049                 {
12050                   gcc_assert (label == XEXP (note, 0));
12051                   if (LABEL_P (label))
12052                     LABEL_NUSES (label)--;
12053                 }
12054               place = 0;
12055             }
12056           if (place2 && JUMP_P (place2))
12057             {
12058               rtx label = JUMP_LABEL (place2);
12059
12060               if (!label)
12061                 JUMP_LABEL (place2) = XEXP (note, 0);
12062               else
12063                 {
12064                   gcc_assert (label == XEXP (note, 0));
12065                   if (LABEL_P (label))
12066                     LABEL_NUSES (label)--;
12067                 }
12068               place2 = 0;
12069             }
12070           break;
12071
12072         case REG_NONNEG:
12073           /* This note says something about the value of a register prior
12074              to the execution of an insn.  It is too much trouble to see
12075              if the note is still correct in all situations.  It is better
12076              to simply delete it.  */
12077           break;
12078
12079         case REG_RETVAL:
12080           /* If the insn previously containing this note still exists,
12081              put it back where it was.  Otherwise move it to the previous
12082              insn.  Adjust the corresponding REG_LIBCALL note.  */
12083           if (!NOTE_P (from_insn))
12084             place = from_insn;
12085           else
12086             {
12087               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12088               place = prev_real_insn (from_insn);
12089               if (tem && place)
12090                 XEXP (tem, 0) = place;
12091               /* If we're deleting the last remaining instruction of a
12092                  libcall sequence, don't add the notes.  */
12093               else if (XEXP (note, 0) == from_insn)
12094                 tem = place = 0;
12095               /* Don't add the dangling REG_RETVAL note.  */
12096               else if (! tem)
12097                 place = 0;
12098             }
12099           break;
12100
12101         case REG_LIBCALL:
12102           /* This is handled similarly to REG_RETVAL.  */
12103           if (!NOTE_P (from_insn))
12104             place = from_insn;
12105           else
12106             {
12107               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12108               place = next_real_insn (from_insn);
12109               if (tem && place)
12110                 XEXP (tem, 0) = place;
12111               /* If we're deleting the last remaining instruction of a
12112                  libcall sequence, don't add the notes.  */
12113               else if (XEXP (note, 0) == from_insn)
12114                 tem = place = 0;
12115               /* Don't add the dangling REG_LIBCALL note.  */
12116               else if (! tem)
12117                 place = 0;
12118             }
12119           break;
12120
12121         case REG_DEAD:
12122           /* If the register is used as an input in I3, it dies there.
12123              Similarly for I2, if it is nonzero and adjacent to I3.
12124
12125              If the register is not used as an input in either I3 or I2
12126              and it is not one of the registers we were supposed to eliminate,
12127              there are two possibilities.  We might have a non-adjacent I2
12128              or we might have somehow eliminated an additional register
12129              from a computation.  For example, we might have had A & B where
12130              we discover that B will always be zero.  In this case we will
12131              eliminate the reference to A.
12132
12133              In both cases, we must search to see if we can find a previous
12134              use of A and put the death note there.  */
12135
12136           if (from_insn
12137               && CALL_P (from_insn)
12138               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12139             place = from_insn;
12140           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12141             place = i3;
12142           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12143                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12144             place = i2;
12145
12146           if (place == 0
12147               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12148                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12149             break;
12150
12151           if (place == 0)
12152             {
12153               basic_block bb = this_basic_block;
12154
12155               /* You might think you could search back from FROM_INSN
12156                  rather than from I3, but combine tries to split invalid
12157                  combined instructions.  This can result in the old I2
12158                  or I1 moving later in the insn sequence.  */
12159               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12160                 {
12161                   if (! INSN_P (tem))
12162                     {
12163                       if (tem == BB_HEAD (bb))
12164                         break;
12165                       continue;
12166                     }
12167
12168                   /* If the register is being set at TEM, see if that is all
12169                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12170                      into a REG_UNUSED note instead. Don't delete sets to
12171                      global register vars.  */
12172                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12173                        || !global_regs[REGNO (XEXP (note, 0))])
12174                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12175                     {
12176                       rtx set = single_set (tem);
12177                       rtx inner_dest = 0;
12178 #ifdef HAVE_cc0
12179                       rtx cc0_setter = NULL_RTX;
12180 #endif
12181
12182                       if (set != 0)
12183                         for (inner_dest = SET_DEST (set);
12184                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12185                               || GET_CODE (inner_dest) == SUBREG
12186                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12187                              inner_dest = XEXP (inner_dest, 0))
12188                           ;
12189
12190                       /* Verify that it was the set, and not a clobber that
12191                          modified the register.
12192
12193                          CC0 targets must be careful to maintain setter/user
12194                          pairs.  If we cannot delete the setter due to side
12195                          effects, mark the user with an UNUSED note instead
12196                          of deleting it.  */
12197
12198                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12199                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12200 #ifdef HAVE_cc0
12201                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12202                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12203                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12204 #endif
12205                           )
12206                         {
12207                           /* Move the notes and links of TEM elsewhere.
12208                              This might delete other dead insns recursively.
12209                              First set the pattern to something that won't use
12210                              any register.  */
12211                           rtx old_notes = REG_NOTES (tem);
12212
12213                           PATTERN (tem) = pc_rtx;
12214                           REG_NOTES (tem) = NULL;
12215
12216                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12217                                             NULL_RTX, NULL_RTX);
12218                           distribute_links (LOG_LINKS (tem));
12219
12220                           SET_INSN_DELETED (tem);
12221
12222 #ifdef HAVE_cc0
12223                           /* Delete the setter too.  */
12224                           if (cc0_setter)
12225                             {
12226                               PATTERN (cc0_setter) = pc_rtx;
12227                               old_notes = REG_NOTES (cc0_setter);
12228                               REG_NOTES (cc0_setter) = NULL;
12229
12230                               distribute_notes (old_notes, cc0_setter,
12231                                                 cc0_setter, NULL_RTX,
12232                                                 NULL_RTX, NULL_RTX);
12233                               distribute_links (LOG_LINKS (cc0_setter));
12234
12235                               SET_INSN_DELETED (cc0_setter);
12236                             }
12237 #endif
12238                         }
12239                       else
12240                         {
12241                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12242
12243                           /*  If there isn't already a REG_UNUSED note, put one
12244                               here.  Do not place a REG_DEAD note, even if
12245                               the register is also used here; that would not
12246                               match the algorithm used in lifetime analysis
12247                               and can cause the consistency check in the
12248                               scheduler to fail.  */
12249                           if (! find_regno_note (tem, REG_UNUSED,
12250                                                  REGNO (XEXP (note, 0))))
12251                             place = tem;
12252                           break;
12253                         }
12254                     }
12255                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12256                            || (CALL_P (tem)
12257                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12258                     {
12259                       /* This may not be the correct place for the death
12260                          note if FROM_INSN is before TEM, and the reg is
12261                          set between FROM_INSN and TEM.  The reg might
12262                          die two or more times.  An existing death note
12263                          means we are looking at the wrong live range.  */
12264                       if (from_insn
12265                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12266                           && find_regno_note (tem, REG_DEAD,
12267                                               REGNO (XEXP (note, 0))))
12268                         {
12269                           tem = from_insn;
12270                           if (tem == BB_HEAD (bb))
12271                             break;
12272                           continue;
12273                         }
12274
12275                       place = tem;
12276
12277                       /* If we are doing a 3->2 combination, and we have a
12278                          register which formerly died in i3 and was not used
12279                          by i2, which now no longer dies in i3 and is used in
12280                          i2 but does not die in i2, and place is between i2
12281                          and i3, then we may need to move a link from place to
12282                          i2.  */
12283                       if (i2 && INSN_UID (place) <= max_uid_cuid
12284                           && INSN_CUID (place) > INSN_CUID (i2)
12285                           && from_insn
12286                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12287                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12288                         {
12289                           rtx links = LOG_LINKS (place);
12290                           LOG_LINKS (place) = 0;
12291                           distribute_links (links);
12292                         }
12293                       break;
12294                     }
12295
12296                   if (tem == BB_HEAD (bb))
12297                     break;
12298                 }
12299
12300               /* We haven't found an insn for the death note and it
12301                  is still a REG_DEAD note, but we have hit the beginning
12302                  of the block.  If the existing life info says the reg
12303                  was dead, there's nothing left to do.  Otherwise, we'll
12304                  need to do a global life update after combine.  */
12305               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12306                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12307                                       REGNO (XEXP (note, 0))))
12308                 SET_BIT (refresh_blocks, this_basic_block->index);
12309             }
12310
12311           /* If the register is set or already dead at PLACE, we needn't do
12312              anything with this note if it is still a REG_DEAD note.
12313              We check here if it is set at all, not if is it totally replaced,
12314              which is what `dead_or_set_p' checks, so also check for it being
12315              set partially.  */
12316
12317           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12318             {
12319               unsigned int regno = REGNO (XEXP (note, 0));
12320
12321               /* Similarly, if the instruction on which we want to place
12322                  the note is a noop, we'll need do a global live update
12323                  after we remove them in delete_noop_moves.  */
12324               if (noop_move_p (place))
12325                 SET_BIT (refresh_blocks, this_basic_block->index);
12326
12327               if (dead_or_set_p (place, XEXP (note, 0))
12328                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12329                 {
12330                   /* Unless the register previously died in PLACE, clear
12331                      last_death.  [I no longer understand why this is
12332                      being done.] */
12333                   if (reg_stat[regno].last_death != place)
12334                     reg_stat[regno].last_death = 0;
12335                   place = 0;
12336                 }
12337               else
12338                 reg_stat[regno].last_death = place;
12339
12340               /* If this is a death note for a hard reg that is occupying
12341                  multiple registers, ensure that we are still using all
12342                  parts of the object.  If we find a piece of the object
12343                  that is unused, we must arrange for an appropriate REG_DEAD
12344                  note to be added for it.  However, we can't just emit a USE
12345                  and tag the note to it, since the register might actually
12346                  be dead; so we recourse, and the recursive call then finds
12347                  the previous insn that used this register.  */
12348
12349               if (place && regno < FIRST_PSEUDO_REGISTER
12350                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12351                 {
12352                   unsigned int endregno
12353                     = regno + hard_regno_nregs[regno]
12354                                               [GET_MODE (XEXP (note, 0))];
12355                   int all_used = 1;
12356                   unsigned int i;
12357
12358                   for (i = regno; i < endregno; i++)
12359                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12360                          && ! find_regno_fusage (place, USE, i))
12361                         || dead_or_set_regno_p (place, i))
12362                       all_used = 0;
12363
12364                   if (! all_used)
12365                     {
12366                       /* Put only REG_DEAD notes for pieces that are
12367                          not already dead or set.  */
12368
12369                       for (i = regno; i < endregno;
12370                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12371                         {
12372                           rtx piece = regno_reg_rtx[i];
12373                           basic_block bb = this_basic_block;
12374
12375                           if (! dead_or_set_p (place, piece)
12376                               && ! reg_bitfield_target_p (piece,
12377                                                           PATTERN (place)))
12378                             {
12379                               rtx new_note
12380                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12381
12382                               distribute_notes (new_note, place, place,
12383                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12384                             }
12385                           else if (! refers_to_regno_p (i, i + 1,
12386                                                         PATTERN (place), 0)
12387                                    && ! find_regno_fusage (place, USE, i))
12388                             for (tem = PREV_INSN (place); ;
12389                                  tem = PREV_INSN (tem))
12390                               {
12391                                 if (! INSN_P (tem))
12392                                   {
12393                                     if (tem == BB_HEAD (bb))
12394                                       {
12395                                         SET_BIT (refresh_blocks,
12396                                                  this_basic_block->index);
12397                                         break;
12398                                       }
12399                                     continue;
12400                                   }
12401                                 if (dead_or_set_p (tem, piece)
12402                                     || reg_bitfield_target_p (piece,
12403                                                               PATTERN (tem)))
12404                                   {
12405                                     REG_NOTES (tem)
12406                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12407                                                            REG_NOTES (tem));
12408                                     break;
12409                                   }
12410                               }
12411
12412                         }
12413
12414                       place = 0;
12415                     }
12416                 }
12417             }
12418           break;
12419
12420         default:
12421           /* Any other notes should not be present at this point in the
12422              compilation.  */
12423           gcc_unreachable ();
12424         }
12425
12426       if (place)
12427         {
12428           XEXP (note, 1) = REG_NOTES (place);
12429           REG_NOTES (place) = note;
12430         }
12431       else if ((REG_NOTE_KIND (note) == REG_DEAD
12432                 || REG_NOTE_KIND (note) == REG_UNUSED)
12433                && REG_P (XEXP (note, 0)))
12434         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12435
12436       if (place2)
12437         {
12438           if ((REG_NOTE_KIND (note) == REG_DEAD
12439                || REG_NOTE_KIND (note) == REG_UNUSED)
12440               && REG_P (XEXP (note, 0)))
12441             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12442
12443           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12444                                                REG_NOTE_KIND (note),
12445                                                XEXP (note, 0),
12446                                                REG_NOTES (place2));
12447         }
12448     }
12449 }
12450 \f
12451 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12452    I3, I2, and I1 to new locations.  This is also called to add a link
12453    pointing at I3 when I3's destination is changed.  */
12454
12455 static void
12456 distribute_links (rtx links)
12457 {
12458   rtx link, next_link;
12459
12460   for (link = links; link; link = next_link)
12461     {
12462       rtx place = 0;
12463       rtx insn;
12464       rtx set, reg;
12465
12466       next_link = XEXP (link, 1);
12467
12468       /* If the insn that this link points to is a NOTE or isn't a single
12469          set, ignore it.  In the latter case, it isn't clear what we
12470          can do other than ignore the link, since we can't tell which
12471          register it was for.  Such links wouldn't be used by combine
12472          anyway.
12473
12474          It is not possible for the destination of the target of the link to
12475          have been changed by combine.  The only potential of this is if we
12476          replace I3, I2, and I1 by I3 and I2.  But in that case the
12477          destination of I2 also remains unchanged.  */
12478
12479       if (NOTE_P (XEXP (link, 0))
12480           || (set = single_set (XEXP (link, 0))) == 0)
12481         continue;
12482
12483       reg = SET_DEST (set);
12484       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12485              || GET_CODE (reg) == STRICT_LOW_PART)
12486         reg = XEXP (reg, 0);
12487
12488       /* A LOG_LINK is defined as being placed on the first insn that uses
12489          a register and points to the insn that sets the register.  Start
12490          searching at the next insn after the target of the link and stop
12491          when we reach a set of the register or the end of the basic block.
12492
12493          Note that this correctly handles the link that used to point from
12494          I3 to I2.  Also note that not much searching is typically done here
12495          since most links don't point very far away.  */
12496
12497       for (insn = NEXT_INSN (XEXP (link, 0));
12498            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12499                      || BB_HEAD (this_basic_block->next_bb) != insn));
12500            insn = NEXT_INSN (insn))
12501         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12502           {
12503             if (reg_referenced_p (reg, PATTERN (insn)))
12504               place = insn;
12505             break;
12506           }
12507         else if (CALL_P (insn)
12508                  && find_reg_fusage (insn, USE, reg))
12509           {
12510             place = insn;
12511             break;
12512           }
12513         else if (INSN_P (insn) && reg_set_p (reg, insn))
12514           break;
12515
12516       /* If we found a place to put the link, place it there unless there
12517          is already a link to the same insn as LINK at that point.  */
12518
12519       if (place)
12520         {
12521           rtx link2;
12522
12523           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12524             if (XEXP (link2, 0) == XEXP (link, 0))
12525               break;
12526
12527           if (link2 == 0)
12528             {
12529               XEXP (link, 1) = LOG_LINKS (place);
12530               LOG_LINKS (place) = link;
12531
12532               /* Set added_links_insn to the earliest insn we added a
12533                  link to.  */
12534               if (added_links_insn == 0
12535                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12536                 added_links_insn = place;
12537             }
12538         }
12539     }
12540 }
12541 \f
12542 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12543    Check whether the expression pointer to by LOC is a register or
12544    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12545    Otherwise return zero.  */
12546
12547 static int
12548 unmentioned_reg_p_1 (rtx *loc, void *expr)
12549 {
12550   rtx x = *loc;
12551
12552   if (x != NULL_RTX
12553       && (REG_P (x) || MEM_P (x))
12554       && ! reg_mentioned_p (x, (rtx) expr))
12555     return 1;
12556   return 0;
12557 }
12558
12559 /* Check for any register or memory mentioned in EQUIV that is not
12560    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12561    of EXPR where some registers may have been replaced by constants.  */
12562
12563 static bool
12564 unmentioned_reg_p (rtx equiv, rtx expr)
12565 {
12566   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12567 }
12568 \f
12569 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12570
12571 static int
12572 insn_cuid (rtx insn)
12573 {
12574   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12575          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12576     insn = NEXT_INSN (insn);
12577
12578   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12579
12580   return INSN_CUID (insn);
12581 }
12582 \f
12583 void
12584 dump_combine_stats (FILE *file)
12585 {
12586   fprintf
12587     (file,
12588      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12589      combine_attempts, combine_merges, combine_extras, combine_successes);
12590 }
12591
12592 void
12593 dump_combine_total_stats (FILE *file)
12594 {
12595   fprintf
12596     (file,
12597      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12598      total_attempts, total_merges, total_extras, total_successes);
12599 }
12600 \f
12601
12602 static bool
12603 gate_handle_combine (void)
12604 {
12605   return (optimize > 0);
12606 }
12607
12608 /* Try combining insns through substitution.  */
12609 static void
12610 rest_of_handle_combine (void)
12611 {
12612   int rebuild_jump_labels_after_combine
12613     = combine_instructions (get_insns (), max_reg_num ());
12614
12615   /* Combining insns may have turned an indirect jump into a
12616      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12617      instructions.  */
12618   if (rebuild_jump_labels_after_combine)
12619     {
12620       timevar_push (TV_JUMP);
12621       rebuild_jump_labels (get_insns ());
12622       timevar_pop (TV_JUMP);
12623
12624       delete_dead_jumptables ();
12625       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12626     }
12627 }
12628
12629 struct tree_opt_pass pass_combine =
12630 {
12631   "combine",                            /* name */
12632   gate_handle_combine,                  /* gate */
12633   rest_of_handle_combine,               /* execute */
12634   NULL,                                 /* sub */
12635   NULL,                                 /* next */
12636   0,                                    /* static_pass_number */
12637   TV_COMBINE,                           /* tv_id */
12638   0,                                    /* properties_required */
12639   0,                                    /* properties_provided */
12640   0,                                    /* properties_destroyed */
12641   0,                                    /* todo_flags_start */
12642   TODO_dump_func |
12643   TODO_ggc_collect,                     /* todo_flags_finish */
12644   'c'                                   /* letter */
12645 };
12646