1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2013 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
35 ;; for a str* inline function.
37 ;; BSR is not generated by the compiler proper, but when relaxing, it
38 ;; generates .uses pseudo-ops that allow linker relaxation to create
39 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
41 ;; Special constraints for SH machine description:
48 ;; Special formats used for outputting SH instructions:
50 ;; %. -- print a .s if insn needs delay slot
51 ;; %@ -- print rte/rts if is/isn't an interrupt function
52 ;; %# -- output a nop if there is nothing to put in the delay slot
53 ;; %O -- print a constant without the #
54 ;; %R -- print the lsw reg of a double
55 ;; %S -- print the msw reg of a double
56 ;; %T -- print next word of a double REG or MEM
58 ;; Special predicates:
60 ;; arith_operand -- operand is valid source for arithmetic op
61 ;; arith_reg_operand -- operand is valid register for arithmetic op
62 ;; general_movdst_operand -- operand is valid move destination
63 ;; general_movsrc_operand -- operand is valid move source
64 ;; logical_operand -- operand is valid source for logical op
66 ;; -------------------------------------------------------------------------
68 ;; -------------------------------------------------------------------------
116 ;; These are used with unspec.
117 (UNSPEC_COMPACT_ARGS 0)
130 (UNSPEC_INIT_TRAMP 13)
143 (UNSPEC_DIV_INV_M0 30)
144 (UNSPEC_DIV_INV_M1 31)
145 (UNSPEC_DIV_INV_M2 32)
146 (UNSPEC_DIV_INV_M3 33)
147 (UNSPEC_DIV_INV20 34)
148 (UNSPEC_DIV_INV_TABLE 37)
156 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
157 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
158 (UNSPEC_EXTRACT_S16 43)
159 (UNSPEC_EXTRACT_U16 44)
161 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
164 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
165 (UNSPEC_PCREL_SYMOFF 46)
167 ;; These are used with unspec_volatile.
173 (UNSPECV_WINDOW_END 10)
174 (UNSPECV_CONST_END 11)
175 (UNSPECV_EH_RETURN 12)
177 (UNSPECV_SP_SWITCH_B 14)
178 (UNSPECV_SP_SWITCH_E 15)
181 ;; -------------------------------------------------------------------------
183 ;; -------------------------------------------------------------------------
188 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
189 (const (symbol_ref "sh_cpu_attr")))
191 (define_attr "endian" "big,little"
192 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
193 (const_string "little") (const_string "big"))))
195 ;; Indicate if the default fpu mode is single precision.
196 (define_attr "fpu_single" "yes,no"
197 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
198 (const_string "yes") (const_string "no"))))
200 (define_attr "fmovd" "yes,no"
201 (const (if_then_else (symbol_ref "TARGET_FMOVD")
202 (const_string "yes") (const_string "no"))))
204 (define_attr "pipe_model" "sh1,sh4,sh5media"
206 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
207 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
208 (const_string "sh1"))))
210 ;; cbranch conditional branch instructions
211 ;; jump unconditional jumps
212 ;; arith ordinary arithmetic
213 ;; arith3 a compound insn that behaves similarly to a sequence of
214 ;; three insns of type arith
215 ;; arith3b like above, but might end with a redirected branch
217 ;; load_si Likewise, SImode variant for general register.
218 ;; fload Likewise, but load to fp register.
220 ;; fstore floating point register to memory
221 ;; move general purpose register to register
222 ;; movi8 8-bit immediate to general purpose register
223 ;; mt_group other sh4 mt instructions
224 ;; fmove register to register, floating point
225 ;; smpy word precision integer multiply
226 ;; dmpy longword or doublelongword precision integer multiply
228 ;; pload load of pr reg, which can't be put into delay slot of rts
229 ;; prset copy register to pr reg, ditto
230 ;; pstore store of pr reg, which can't be put into delay slot of jsr
231 ;; prget copy pr to register, ditto
232 ;; pcload pc relative load of constant value
233 ;; pcfload Likewise, but load to fp register.
234 ;; pcload_si Likewise, SImode variant for general register.
235 ;; rte return from exception
236 ;; sfunc special function call with known used registers
237 ;; call function call
239 ;; fpscr_toggle toggle a bit in the fpscr
240 ;; fdiv floating point divide (or square root)
241 ;; gp_fpul move from general purpose register to fpul
242 ;; fpul_gp move from fpul to general purpose register
243 ;; mac_gp move from mac[lh] to general purpose register
244 ;; gp_mac move from general purpose register to mac[lh]
245 ;; mac_mem move from mac[lh] to memory
246 ;; mem_mac move from memory to mac[lh]
247 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
248 ;; ftrc_s fix_truncsfsi2_i4
249 ;; dfdiv double precision floating point divide (or square root)
250 ;; cwb ic_invalidate_line_i
251 ;; movua SH4a unaligned load
252 ;; fsrra square root reciprocal approximate
253 ;; fsca sine and cosine approximate
254 ;; tls_load load TLS related address
255 ;; arith_media SHmedia arithmetic, logical, and shift instructions
256 ;; cbranch_media SHmedia conditional branch instructions
257 ;; cmp_media SHmedia compare instructions
258 ;; dfdiv_media SHmedia double precision divide and square root
259 ;; dfmul_media SHmedia double precision multiply instruction
260 ;; dfparith_media SHmedia double precision floating point arithmetic
261 ;; dfpconv_media SHmedia double precision floating point conversions
262 ;; dmpy_media SHmedia longword multiply
263 ;; fcmp_media SHmedia floating point compare instructions
264 ;; fdiv_media SHmedia single precision divide and square root
265 ;; fload_media SHmedia floating point register load instructions
266 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
267 ;; fparith_media SHmedia single precision floating point arithmetic
268 ;; fpconv_media SHmedia single precision floating point conversions
269 ;; fstore_media SHmedia floating point register store instructions
270 ;; gettr_media SHmedia gettr instruction
271 ;; invalidate_line_media SHmedia invalidate_line sequence
272 ;; jump_media SHmedia unconditional branch instructions
273 ;; load_media SHmedia general register load instructions
274 ;; pt_media SHmedia pt instruction (expanded by assembler)
275 ;; ptabs_media SHmedia ptabs instruction
276 ;; store_media SHmedia general register store instructions
277 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
278 ;; mac_media SHmedia mac-style fixed point operations
279 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
280 ;; atrans_media SHmedia approximate transcendental functions
281 ;; ustore_media SHmedia unaligned stores
282 ;; nil no-op move, will be deleted.
285 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
286 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
287 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
288 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
289 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
290 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
291 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
292 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
293 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
294 d2mpy_media,atrans_media,ustore_media,nil,other"
295 (const_string "other"))
297 ;; We define a new attribute namely "insn_class".We use
298 ;; this for the DFA based pipeline description.
300 ;; mt_group SH4 "mt" group instructions.
302 ;; ex_group SH4 "ex" group instructions.
304 ;; ls_group SH4 "ls" group instructions.
306 (define_attr "insn_class"
307 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
308 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
309 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
310 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
311 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
312 (eq_attr "type" "cbranch,jump") (const_string "br_group")
313 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
314 (const_string "fe_group")
315 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
316 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
317 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
318 (const_string "none")))
320 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
321 ;; so these do not belong in an insn group, although they are modeled
322 ;; with their own define_insn_reservations.
324 ;; Indicate what precision must be selected in fpscr for this insn, if any.
325 (define_attr "fp_mode" "single,double,none" (const_string "none"))
327 ;; Indicate if the fpu mode is set by this instruction
328 ;; "unknown" must have the value as "none" in fp_mode, and means
329 ;; that the instruction/abi has left the processor in an unknown
331 ;; "none" means that nothing has changed and no mode is set.
332 ;; This attribute is only used for the Renesas ABI.
333 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
335 ; If a conditional branch destination is within -252..258 bytes away
336 ; from the instruction it can be 2 bytes long. Something in the
337 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
338 ; branches are initially assumed to be 16 bytes long.
339 ; In machine_dependent_reorg, we split all branches that are longer than
342 ;; The maximum range used for SImode constant pool entries is 1018. A final
343 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
344 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
345 ;; instruction around the pool table, 2 bytes of alignment before the table,
346 ;; and 30 bytes of alignment after the table. That gives a maximum total
347 ;; pool size of 1058 bytes.
348 ;; Worst case code/pool content size ratio is 1:2 (using asms).
349 ;; Thus, in the worst case, there is one instruction in front of a maximum
350 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
351 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
352 ;; If we have a forward branch, the initial table will be put after the
353 ;; unconditional branch.
355 ;; ??? We could do much better by keeping track of the actual pcloads within
356 ;; the branch range and in the pcload range in front of the branch range.
358 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
360 (define_attr "short_cbranch_p" "no,yes"
361 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
365 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
367 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
369 ] (const_string "no")))
371 (define_attr "med_branch_p" "no,yes"
372 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
375 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
377 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
380 ] (const_string "no")))
382 (define_attr "med_cbranch_p" "no,yes"
383 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
386 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
388 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
391 ] (const_string "no")))
393 (define_attr "braf_branch_p" "no,yes"
394 (cond [(match_test "! TARGET_SH2")
396 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
404 ] (const_string "no")))
406 (define_attr "braf_cbranch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
417 ] (const_string "no")))
419 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
420 ;; For wider ranges, we need a combination of a code and a data part.
421 ;; If we can get a scratch register for a long range jump, the code
422 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
423 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
424 ;; long; otherwise, it must be 6 bytes long.
426 ;; All other instructions are two bytes long by default.
428 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
429 ;; but getattrtab doesn't understand this.
430 (define_attr "length" ""
431 (cond [(eq_attr "type" "cbranch")
432 (cond [(eq_attr "short_cbranch_p" "yes")
434 (eq_attr "med_cbranch_p" "yes")
436 (eq_attr "braf_cbranch_p" "yes")
438 ;; ??? using pc is not computed transitively.
439 (ne (match_dup 0) (match_dup 0))
441 (match_test "flag_pic")
444 (eq_attr "type" "jump")
445 (cond [(eq_attr "med_branch_p" "yes")
447 (and (match_test "prev_nonnote_insn (insn)")
448 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
450 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
451 (symbol_ref "code_for_indirect_jump_scratch"))))
452 (cond [(eq_attr "braf_branch_p" "yes")
454 (not (match_test "flag_pic"))
456 (match_test "TARGET_SH2")
457 (const_int 10)] (const_int 18))
458 (eq_attr "braf_branch_p" "yes")
460 ;; ??? using pc is not computed transitively.
461 (ne (match_dup 0) (match_dup 0))
463 (match_test "flag_pic")
466 (eq_attr "type" "pt_media")
467 (if_then_else (match_test "TARGET_SHMEDIA64")
468 (const_int 20) (const_int 12))
469 (and (eq_attr "type" "jump_media")
470 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
472 ] (if_then_else (match_test "TARGET_SHMEDIA")
476 ;; DFA descriptions for the pipelines
479 (include "shmedia.md")
482 (include "iterators.md")
483 (include "predicates.md")
484 (include "constraints.md")
486 ;; Definitions for filling delay slots
488 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
490 (define_attr "banked" "yes,no"
491 (cond [(match_test "sh_loads_bankedreg_p (insn)")
492 (const_string "yes")]
493 (const_string "no")))
495 ;; ??? This should be (nil) instead of (const_int 0)
496 (define_attr "hit_stack" "yes,no"
497 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
499 (const_string "yes")))
501 (define_attr "interrupt_function" "no,yes"
502 (const (symbol_ref "current_function_interrupt")))
504 (define_attr "in_delay_slot" "yes,no"
505 (cond [(eq_attr "type" "cbranch") (const_string "no")
506 (eq_attr "type" "pcload,pcload_si") (const_string "no")
507 (eq_attr "needs_delay_slot" "yes") (const_string "no")
508 (eq_attr "length" "2") (const_string "yes")
509 ] (const_string "no")))
511 (define_attr "cond_delay_slot" "yes,no"
512 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
513 ] (const_string "no")))
515 (define_attr "is_sfunc" ""
516 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
518 (define_attr "is_mac_media" ""
519 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
521 (define_attr "branch_zero" "yes,no"
522 (cond [(eq_attr "type" "!cbranch") (const_string "no")
523 (ne (symbol_ref "(next_active_insn (insn)\
524 == (prev_active_insn\
525 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
526 && get_attr_length (next_active_insn (insn)) == 2")
528 (const_string "yes")]
529 (const_string "no")))
531 ;; SH4 Double-precision computation with double-precision result -
532 ;; the two halves are ready at different times.
533 (define_attr "dfp_comp" "yes,no"
534 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
535 (const_string "no")))
537 ;; Insns for which the latency of a preceding fp insn is decreased by one.
538 (define_attr "late_fp_use" "yes,no" (const_string "no"))
539 ;; And feeding insns for which this relevant.
540 (define_attr "any_fp_comp" "yes,no"
541 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
542 (const_string "yes")]
543 (const_string "no")))
545 (define_attr "any_int_load" "yes,no"
546 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
547 (const_string "yes")]
548 (const_string "no")))
550 (define_attr "highpart" "user, ignore, extend, depend, must_split"
551 (const_string "user"))
554 (eq_attr "needs_delay_slot" "yes")
555 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
557 ;; Since a normal return (rts) implicitly uses the PR register,
558 ;; we can't allow PR register loads in an rts delay slot.
559 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
560 ;; stack, and thus we can't put a pop instruction in its delay slot.
561 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
562 ;; pop instruction can go in the delay slot, unless it references a banked
563 ;; register (the register bank is switched by rte).
565 (eq_attr "type" "return")
566 [(and (eq_attr "in_delay_slot" "yes")
567 (ior (and (eq_attr "interrupt_function" "no")
568 (eq_attr "type" "!pload,prset"))
569 (and (eq_attr "interrupt_function" "yes")
570 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
571 (eq_attr "banked" "no"))))
574 ;; Since a call implicitly uses the PR register, we can't allow
575 ;; a PR register store in a jsr delay slot.
578 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
579 [(and (eq_attr "in_delay_slot" "yes")
580 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
582 ;; Say that we have annulled true branches, since this gives smaller and
583 ;; faster code when branches are predicted as not taken.
585 ;; ??? The non-annulled condition should really be "in_delay_slot",
586 ;; but insns that can be filled in non-annulled get priority over insns
587 ;; that can only be filled in anulled.
590 (and (eq_attr "type" "cbranch")
591 (match_test "TARGET_SH2"))
592 ;; SH2e has a hardware bug that pretty much prohibits the use of
593 ;; annulled delay slots.
594 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
595 (not (eq_attr "cpu" "sh2e"))) (nil)])
597 ;; -------------------------------------------------------------------------
598 ;; SImode signed integer comparisons
599 ;; -------------------------------------------------------------------------
601 ;; Various patterns to generate the TST #imm, R0 instruction.
602 ;; Although this adds some pressure on the R0 register, it can potentially
603 ;; result in faster code, even if the operand has to be moved to R0 first.
604 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
605 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
606 ;; is an EX group instruction but still can be executed in parallel with the
607 ;; MT group MOV Rm, Rn instruction.
609 ;; Usual TST #imm, R0 patterns for SI, HI and QI
610 ;; This is usually used for bit patterns other than contiguous bits
612 (define_insn "tstsi_t"
614 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
615 (match_operand:SI 1 "logical_operand" "K08,r"))
619 [(set_attr "type" "mt_group")])
621 (define_insn "tsthi_t"
623 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
624 (match_operand 1 "const_int_operand")) 0)
627 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
629 [(set_attr "type" "mt_group")])
631 (define_insn "tstqi_t"
633 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
634 (match_operand 1 "const_int_operand")) 0)
637 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
638 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
640 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
643 [(set_attr "type" "mt_group")])
645 ;; Test low QI subreg against zero.
646 ;; This avoids unnecessary zero extension before the test.
647 (define_insn "*tstqi_t_zero"
649 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
652 [(set_attr "type" "mt_group")])
654 ;; This pattern might be risky because it also tests the upper bits and not
655 ;; only the subreg. However, it seems that combine will get to this only
656 ;; when testing sign/zero extended values. In this case the extended upper
657 ;; bits do not matter.
658 (define_insn "*tst<mode>_t_zero"
662 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
663 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_le>)
665 "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
667 [(set_attr "type" "mt_group")])
669 (define_insn "*tst<mode>_t_zero"
673 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
674 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
676 "TARGET_SH1 && !TARGET_LITTLE_ENDIAN"
678 [(set_attr "type" "mt_group")])
680 ;; Extract LSB, negate and store in T bit.
681 (define_insn "tstsi_t_and_not"
683 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
687 [(set_attr "type" "mt_group")])
689 ;; Extract contiguous bits and compare them against zero.
690 (define_insn "tst<mode>_t_zero_extract_eq"
692 (eq:SI (zero_extract:SI (match_operand:QIHISIDI 0 "logical_operand" "z")
693 (match_operand:SI 1 "const_int_operand")
694 (match_operand:SI 2 "const_int_operand"))
697 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
699 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
702 [(set_attr "type" "mt_group")])
704 ;; This split is required when testing bits in a QI subreg.
709 (zero_extract:SI (match_operand 0 "logical_operand")
710 (match_operand 1 "const_int_operand")
711 (match_operand 2 "const_int_operand"))
712 (match_operand 3 "const_int_operand")
716 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
717 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
718 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
721 if (GET_MODE (operands[0]) == QImode)
722 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
725 ;; Extract single bit, negate and store it in the T bit.
726 ;; Not used for SH4A.
727 (define_insn "tstsi_t_zero_extract_xor"
729 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
730 (match_operand:SI 3 "const_int_operand"))
731 (match_operand:SI 1 "const_int_operand")
732 (match_operand:SI 2 "const_int_operand")))]
734 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
735 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
737 [(set_attr "type" "mt_group")])
739 ;; Extract single bit, negate and store it in the T bit.
740 ;; Used for SH4A little endian.
741 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
744 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
745 (match_operand:SI 3 "const_int_operand")) 0)
746 (match_operand:SI 1 "const_int_operand")
747 (match_operand:SI 2 "const_int_operand")))]
748 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
749 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
750 == (INTVAL (operands[3]) & 255)
751 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
753 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
756 [(set_attr "type" "mt_group")])
758 ;; Extract single bit, negate and store it in the T bit.
759 ;; Used for SH4A big endian.
760 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
763 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
764 (match_operand:SI 3 "const_int_operand")) 3)
765 (match_operand:SI 1 "const_int_operand")
766 (match_operand:SI 2 "const_int_operand")))]
767 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN
768 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
769 == (INTVAL (operands[3]) & 255)
770 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
772 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
775 [(set_attr "type" "mt_group")])
777 (define_insn "cmpeqsi_t"
779 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
780 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
786 [(set_attr "type" "mt_group")])
788 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
789 ;; pattern by itself. What this actually does is:
790 ;; x == 0: (1 >> 0-0) & 1 = 1
791 ;; x != 0: (1 >> 0-x) & 1 = 0
792 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
793 (define_insn_and_split "*cmpeqsi_t"
797 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
802 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
804 (define_insn "cmpgtsi_t"
806 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
807 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
812 [(set_attr "type" "mt_group")])
814 (define_insn "cmpgesi_t"
816 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
817 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
822 [(set_attr "type" "mt_group")])
824 ;; FIXME: This is actually wrong. There is no way to literally move a
825 ;; general reg to t reg. Luckily, it seems that this pattern will be only
826 ;; used when the general reg is known be either '0' or '1' during combine.
827 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
828 ;; Due to interactions with other patterns, combine fails to pick the latter
829 ;; and invert the dependent logic.
830 (define_insn "*negtstsi"
831 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
834 [(set_attr "type" "mt_group")])
836 ;; Some integer sign comparison patterns can be realized with the div0s insn.
837 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
838 (define_insn "cmp_div0s_0"
840 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
841 (match_operand:SI 1 "arith_reg_operand" "r"))
845 [(set_attr "type" "arith")])
847 (define_insn "cmp_div0s_1"
849 (lt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
850 (match_operand:SI 1 "arith_reg_operand" "r"))
854 [(set_attr "type" "arith")])
856 (define_insn_and_split "*cmp_div0s_0"
857 [(set (match_operand:SI 0 "arith_reg_dest" "")
858 (lshiftrt:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
859 (match_operand:SI 2 "arith_reg_operand" ""))
861 (clobber (reg:SI T_REG))]
866 (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31)))
867 (set (match_dup 0) (reg:SI T_REG))])
869 (define_insn "*cmp_div0s_0"
871 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
873 (ge:SI (match_operand:SI 1 "arith_reg_operand")
877 [(set_attr "type" "arith")])
879 (define_insn_and_split "*cmp_div0s_1"
880 [(set (match_operand:SI 0 "arith_reg_dest" "")
881 (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
882 (match_operand:SI 2 "arith_reg_operand" ""))
884 (clobber (reg:SI T_REG))]
887 "&& can_create_pseudo_p ()"
889 ;; We have to go through the movnegt expander here which will handle the
890 ;; SH2A vs non-SH2A cases.
892 emit_insn (gen_cmp_div0s_1 (operands[1], operands[2]));
893 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
897 (define_insn_and_split "*cmp_div0s_1"
899 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
900 (match_operand:SI 1 "arith_reg_operand" ""))
904 "&& can_create_pseudo_p ()"
905 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
907 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
909 (define_insn_and_split "*cmp_div0s_1"
911 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
913 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
917 "&& can_create_pseudo_p ()"
918 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
920 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
922 ;; -------------------------------------------------------------------------
923 ;; SImode compare and branch
924 ;; -------------------------------------------------------------------------
926 (define_expand "cbranchsi4"
928 (if_then_else (match_operator 0 "comparison_operator"
929 [(match_operand:SI 1 "arith_operand" "")
930 (match_operand:SI 2 "arith_operand" "")])
931 (label_ref (match_operand 3 "" ""))
933 (clobber (reg:SI T_REG))]
937 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
938 operands[2], operands[3]));
940 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
945 ;; Combine patterns to invert compare and branch operations for which we
946 ;; don't have actual comparison insns. These patterns are used in cases
947 ;; which appear after the initial cbranchsi expansion, which also does
948 ;; some condition inversion.
951 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
952 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
953 (label_ref (match_operand 2))
955 (clobber (reg:SI T_REG))]
957 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
958 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
959 (label_ref (match_dup 2))
962 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
963 ;; and SH2A combine fails to simplify this pattern by itself.
964 ;; What this actually does is:
965 ;; x == 0: (1 >> 0-0) & 1 = 1
966 ;; x != 0: (1 >> 0-x) & 1 = 0
967 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
971 (eq (and:SI (lshiftrt:SI
973 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
976 (label_ref (match_operand 2))
978 (clobber (reg:SI T_REG))]
980 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
981 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
982 (label_ref (match_dup 2))
985 ;; FIXME: These could probably use code iterators for the compare op.
988 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
989 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
990 (label_ref (match_operand 2))
992 (clobber (reg:SI T_REG))]
994 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
995 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
996 (label_ref (match_dup 2))
1001 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1002 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1003 (label_ref (match_operand 2))
1005 (clobber (reg:SI T_REG))]
1007 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1008 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1009 (label_ref (match_dup 2))
1014 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1015 (match_operand:SI 1 "arith_reg_operand" ""))
1016 (label_ref (match_operand 2))
1018 (clobber (reg:SI T_REG))]
1020 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1021 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1022 (label_ref (match_dup 2))
1027 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1028 (match_operand:SI 1 "arith_reg_operand" ""))
1029 (label_ref (match_operand 2))
1031 (clobber (reg:SI T_REG))]
1033 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1034 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1035 (label_ref (match_dup 2))
1038 ;; Compare and branch combine patterns for div0s comparisons.
1039 (define_insn_and_split "*cbranch_div0s"
1041 (if_then_else (lt (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1042 (match_operand:SI 1 "arith_reg_operand" ""))
1044 (label_ref (match_operand 2))
1046 (clobber (reg:SI T_REG))]
1050 [(set (reg:SI T_REG)
1051 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1053 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1054 (label_ref (match_dup 2))
1057 (define_insn_and_split "*cbranch_div0s"
1059 (if_then_else (ge (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1060 (match_operand:SI 1 "arith_reg_operand" ""))
1062 (label_ref (match_operand 2))
1064 (clobber (reg:SI T_REG))]
1068 [(set (reg:SI T_REG)
1069 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1071 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1072 (label_ref (match_dup 2))
1075 ;; Conditional move combine pattern for div0s comparisons.
1076 ;; This is used when TARGET_PRETEND_CMOVE is in effect.
1077 (define_insn_and_split "*movsicc_div0s"
1078 [(set (match_operand:SI 0 "arith_reg_dest" "")
1079 (if_then_else:SI (ge (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
1080 (match_operand:SI 2 "arith_reg_operand" ""))
1082 (match_operand:SI 3 "arith_reg_operand" "")
1083 (match_operand:SI 4 "general_movsrc_operand" "")))
1084 (clobber (reg:SI T_REG))]
1085 "TARGET_PRETEND_CMOVE"
1088 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1091 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1095 (define_insn_and_split "*movsicc_div0s"
1096 [(set (match_operand:SI 0 "arith_reg_dest")
1097 (if_then_else:SI (eq (lshiftrt:SI
1098 (match_operand:SI 1 "arith_reg_operand")
1101 (match_operand:SI 2 "arith_reg_operand")
1103 (match_operand:SI 3 "arith_reg_operand")
1104 (match_operand:SI 4 "general_movsrc_operand")))
1105 (clobber (reg:SI T_REG))]
1106 "TARGET_PRETEND_CMOVE"
1109 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1112 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1116 ;; -------------------------------------------------------------------------
1117 ;; SImode unsigned integer comparisons
1118 ;; -------------------------------------------------------------------------
1120 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1121 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1122 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1123 ;; handled here, something else would just load a '0' into the second operand
1124 ;; and do the comparison. We can do slightly better by just setting the
1126 (define_insn_and_split "cmpgeusi_t"
1127 [(set (reg:SI T_REG)
1128 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1129 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1132 "&& satisfies_constraint_Z (operands[1])"
1133 [(set (reg:SI T_REG) (const_int 1))]
1135 [(set_attr "type" "mt_group")])
1137 (define_insn "cmpgtusi_t"
1138 [(set (reg:SI T_REG)
1139 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1140 (match_operand:SI 1 "arith_reg_operand" "r")))]
1143 [(set_attr "type" "mt_group")])
1145 ;; -------------------------------------------------------------------------
1146 ;; DImode compare and branch
1147 ;; -------------------------------------------------------------------------
1149 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1150 ;; Therefore, we aim to have a set of three branches that go straight to the
1151 ;; destination, i.e. only one of them is taken at any one time.
1152 ;; This mechanism should also be slightly better for the sh4-200.
1154 (define_expand "cbranchdi4"
1156 (if_then_else (match_operator 0 "comparison_operator"
1157 [(match_operand:DI 1 "arith_operand" "")
1158 (match_operand:DI 2 "arith_operand" "")])
1159 (label_ref (match_operand 3 "" ""))
1161 (clobber (match_dup 4))
1162 (clobber (reg:SI T_REG))]
1163 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1165 enum rtx_code comparison;
1169 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1170 operands[2], operands[3]));
1173 else if (!TARGET_CBRANCHDI4)
1175 sh_emit_compare_and_branch (operands, DImode);
1180 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1183 comparison = prepare_cbranch_operands (operands, DImode,
1184 LAST_AND_UNUSED_RTX_CODE);
1185 if (comparison != GET_CODE (operands[0]))
1187 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1188 operands[4] = gen_rtx_SCRATCH (SImode);
1192 (define_insn_and_split "cbranchdi4_i"
1194 (if_then_else (match_operator 0 "comparison_operator"
1195 [(match_operand:DI 1 "arith_operand" "r,r")
1196 (match_operand:DI 2 "arith_operand" "rN,I08")])
1197 (label_ref (match_operand 3 "" ""))
1199 (clobber (match_scratch:SI 4 "=X,&r"))
1200 (clobber (reg:SI T_REG))]
1203 "&& reload_completed"
1206 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1211 ;; -------------------------------------------------------------------------
1212 ;; DImode signed integer comparisons
1213 ;; -------------------------------------------------------------------------
1216 [(set (reg:SI T_REG)
1217 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1218 (match_operand:DI 1 "arith_operand" "r"))
1222 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1225 [(set_attr "length" "6")
1226 (set_attr "type" "arith3b")])
1228 (define_insn "cmpeqdi_t"
1229 [(set (reg:SI T_REG)
1230 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1231 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1234 static const char* alt[] =
1241 "cmp/eq %S1,%S0" "\n"
1243 " cmp/eq %R1,%R0" "\n"
1246 return alt[which_alternative];
1248 [(set_attr "length" "6")
1249 (set_attr "type" "arith3b")])
1252 [(set (reg:SI T_REG)
1253 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1254 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1255 ;; If we applied this split when not optimizing, it would only be
1256 ;; applied during the machine-dependent reorg, when no new basic blocks
1258 "TARGET_SH1 && reload_completed && optimize"
1259 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1260 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1261 (label_ref (match_dup 6))
1263 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1266 operands[2] = gen_highpart (SImode, operands[0]);
1267 operands[3] = operands[1] == const0_rtx
1269 : gen_highpart (SImode, operands[1]);
1270 operands[4] = gen_lowpart (SImode, operands[0]);
1271 operands[5] = gen_lowpart (SImode, operands[1]);
1272 operands[6] = gen_label_rtx ();
1275 (define_insn "cmpgtdi_t"
1276 [(set (reg:SI T_REG)
1277 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1278 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1281 static const char* alt[] =
1283 "cmp/eq %S1,%S0" "\n"
1285 " cmp/gt %S1,%S0" "\n"
1286 " cmp/hi %R1,%R0" "\n"
1292 " cmp/hi %S0,%R0" "\n"
1295 return alt[which_alternative];
1297 [(set_attr "length" "8")
1298 (set_attr "type" "arith3")])
1300 (define_insn "cmpgedi_t"
1301 [(set (reg:SI T_REG)
1302 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1303 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1306 static const char* alt[] =
1308 "cmp/eq %S1,%S0" "\n"
1310 " cmp/ge %S1,%S0" "\n"
1311 " cmp/hs %R1,%R0" "\n"
1316 return alt[which_alternative];
1318 [(set_attr "length" "8,2")
1319 (set_attr "type" "arith3,mt_group")])
1321 ;; -------------------------------------------------------------------------
1322 ;; DImode unsigned integer comparisons
1323 ;; -------------------------------------------------------------------------
1325 (define_insn "cmpgeudi_t"
1326 [(set (reg:SI T_REG)
1327 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1328 (match_operand:DI 1 "arith_reg_operand" "r")))]
1331 return "cmp/eq %S1,%S0" "\n"
1333 " cmp/hs %S1,%S0" "\n"
1334 " cmp/hs %R1,%R0" "\n"
1337 [(set_attr "length" "8")
1338 (set_attr "type" "arith3")])
1340 (define_insn "cmpgtudi_t"
1341 [(set (reg:SI T_REG)
1342 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1343 (match_operand:DI 1 "arith_reg_operand" "r")))]
1346 return "cmp/eq %S1,%S0" "\n"
1348 " cmp/hi %S1,%S0" "\n"
1349 " cmp/hi %R1,%R0" "\n"
1352 [(set_attr "length" "8")
1353 (set_attr "type" "arith3")])
1355 (define_insn "cmpeqsi_media"
1356 [(set (match_operand:SI 0 "register_operand" "=r")
1357 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1358 (match_operand:SI 2 "cmp_operand" "Nr")))]
1361 [(set_attr "type" "cmp_media")])
1363 (define_insn "cmpeqdi_media"
1364 [(set (match_operand:SI 0 "register_operand" "=r")
1365 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1366 (match_operand:DI 2 "cmp_operand" "Nr")))]
1369 [(set_attr "type" "cmp_media")])
1371 (define_insn "cmpgtsi_media"
1372 [(set (match_operand:SI 0 "register_operand" "=r")
1373 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1374 (match_operand:SI 2 "cmp_operand" "rN")))]
1376 "cmpgt %N1, %N2, %0"
1377 [(set_attr "type" "cmp_media")])
1379 (define_insn "cmpgtdi_media"
1380 [(set (match_operand:SI 0 "register_operand" "=r")
1381 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1382 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1384 "cmpgt %N1, %N2, %0"
1385 [(set_attr "type" "cmp_media")])
1387 (define_insn "cmpgtusi_media"
1388 [(set (match_operand:SI 0 "register_operand" "=r")
1389 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1390 (match_operand:SI 2 "cmp_operand" "rN")))]
1392 "cmpgtu %N1, %N2, %0"
1393 [(set_attr "type" "cmp_media")])
1395 (define_insn "cmpgtudi_media"
1396 [(set (match_operand:SI 0 "register_operand" "=r")
1397 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1398 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1400 "cmpgtu %N1, %N2, %0"
1401 [(set_attr "type" "cmp_media")])
1403 ; This pattern is for combine.
1404 (define_insn "*cmpne0sisi_media"
1405 [(set (match_operand:SI 0 "register_operand" "=r")
1406 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1409 [(set_attr "type" "cmp_media")])
1411 ;; -------------------------------------------------------------------------
1412 ;; Conditional move instructions
1413 ;; -------------------------------------------------------------------------
1415 ;; The insn names may seem reversed, but note that cmveq performs the move
1416 ;; if op1 == 0, and cmvne does it if op1 != 0.
1418 (define_insn "movdicc_false"
1419 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1420 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1422 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1423 (match_operand:DI 3 "arith_reg_operand" "0")))]
1426 [(set_attr "type" "arith_media")])
1428 (define_insn "movdicc_true"
1429 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1430 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1432 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1433 (match_operand:DI 3 "arith_reg_operand" "0")))]
1436 [(set_attr "type" "arith_media")])
1439 [(set (match_operand:DI 0 "arith_reg_dest" "")
1440 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1441 [(match_operand:DI 1 "arith_reg_operand" "")
1443 (match_operand:DI 2 "arith_reg_dest" "")
1445 (set (match_dup 2) (match_dup 0))]
1446 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1448 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1450 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1451 VOIDmode, operands[1], CONST0_RTX (DImode));
1455 [(set (match_operand:DI 0 "general_movdst_operand" "")
1456 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1457 (set (match_operand:DI 2 "arith_reg_dest" "")
1458 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1459 [(match_operand:DI 3 "arith_reg_operand" "")
1463 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1465 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1468 (define_expand "movdicc"
1469 [(set (match_operand:DI 0 "register_operand" "")
1470 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1471 (match_operand:DI 2 "register_operand" "")
1472 (match_operand:DI 3 "register_operand" "")))]
1475 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1476 && GET_MODE (XEXP (operands[1], 0)) == DImode
1477 && XEXP (operands[1], 1) == const0_rtx)
1481 if (!can_create_pseudo_p ())
1484 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1485 GET_CODE (operands[1]),
1486 XEXP (operands[1], 0),
1487 XEXP (operands[1], 1));
1493 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1494 ;; SImode to DImode.
1495 (define_insn "movsicc_false"
1496 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1497 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1499 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1500 (match_operand:SI 3 "arith_reg_operand" "0")))]
1503 [(set_attr "type" "arith_media")])
1505 (define_insn "movsicc_true"
1506 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1507 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1509 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1510 (match_operand:SI 3 "arith_reg_operand" "0")))]
1513 [(set_attr "type" "arith_media")])
1516 [(set (match_operand:SI 0 "arith_reg_dest" "")
1517 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1518 [(match_operand:SI 1 "arith_reg_operand" "")
1520 (match_operand:SI 2 "arith_reg_dest" "")
1522 (set (match_dup 2) (match_dup 0))]
1523 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1525 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1527 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1528 VOIDmode, operands[1], CONST0_RTX (SImode));
1532 [(set (match_operand:SI 0 "general_movdst_operand" "")
1533 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1534 (set (match_operand:SI 2 "arith_reg_dest" "")
1535 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1536 [(match_operand:SI 3 "arith_reg_operand" "")
1540 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1541 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1543 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1545 replace_rtx (operands[4], operands[0], operands[1]);
1549 [(set (match_operand 0 "any_register_operand" "")
1550 (match_operand 1 "any_register_operand" ""))
1551 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1552 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1553 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1554 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1555 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1556 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1557 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1558 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1559 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1560 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1561 && (REGNO_REG_CLASS (REGNO (operands[0]))
1562 == REGNO_REG_CLASS (REGNO (operands[2])))
1563 && (REGNO_REG_CLASS (REGNO (operands[1]))
1564 == REGNO_REG_CLASS (REGNO (operands[0])))"
1565 [(set (match_dup 0) (match_dup 3))
1566 (set (match_dup 4) (match_dup 5))]
1568 rtx set1, set2, insn2;
1569 rtx replacements[4];
1571 /* We want to replace occurrences of operands[0] with operands[1] and
1572 operands[2] with operands[0] in operands[4]/operands[5].
1573 Doing just two replace_rtx calls naively would result in the second
1574 replacement undoing all that the first did if operands[1] and operands[2]
1575 are identical, so we must do this simultaneously. */
1576 replacements[0] = operands[0];
1577 replacements[1] = operands[1];
1578 replacements[2] = operands[2];
1579 replacements[3] = operands[0];
1580 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1581 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1582 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1585 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1586 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1587 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1588 /* The operands array is aliased to recog_data.operand, which gets
1589 clobbered by extract_insn, so finish with it now. */
1590 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1591 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1592 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1593 always uses emit_insn. */
1594 /* Check that we don't violate matching constraints or earlyclobbers. */
1595 extract_insn (emit_insn (set1));
1596 if (! constrain_operands (1))
1598 insn2 = emit (set2);
1599 if (GET_CODE (insn2) == BARRIER)
1601 extract_insn (insn2);
1602 if (! constrain_operands (1))
1606 tmp = replacements[0];
1607 replacements[0] = replacements[1];
1608 replacements[1] = tmp;
1609 tmp = replacements[2];
1610 replacements[2] = replacements[3];
1611 replacements[3] = tmp;
1612 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1613 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1614 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1620 ;; The register allocator is rather clumsy in handling multi-way conditional
1621 ;; moves, so allow the combiner to make them, and we split them up after
1623 (define_insn_and_split "*movsicc_umin"
1624 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1625 (umin:SI (if_then_else:SI
1626 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1628 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1629 (match_operand:SI 3 "register_operand" "0"))
1630 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1631 (clobber (match_scratch:SI 5 "=&r"))]
1632 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1634 "TARGET_SHMEDIA && reload_completed"
1637 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1639 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1640 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1645 (define_insn "*movsicc_t_false"
1646 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1647 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1648 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1649 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1650 "TARGET_PRETEND_CMOVE
1651 && (arith_reg_operand (operands[1], SImode)
1652 || (immediate_operand (operands[1], SImode)
1653 && satisfies_constraint_I08 (operands[1])))"
1659 [(set_attr "type" "mt_group,arith") ;; poor approximation
1660 (set_attr "length" "4")])
1662 (define_insn "*movsicc_t_true"
1663 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1664 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1665 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1666 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1667 "TARGET_PRETEND_CMOVE
1668 && (arith_reg_operand (operands[1], SImode)
1669 || (immediate_operand (operands[1], SImode)
1670 && satisfies_constraint_I08 (operands[1])))"
1676 [(set_attr "type" "mt_group,arith") ;; poor approximation
1677 (set_attr "length" "4")])
1679 (define_expand "movsicc"
1680 [(set (match_operand:SI 0 "arith_reg_dest" "")
1681 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1682 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1683 (match_operand:SI 3 "arith_reg_operand" "")))]
1684 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1686 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1687 && GET_MODE (XEXP (operands[1], 0)) == SImode
1689 || (REG_P (XEXP (operands[1], 0))
1690 && REGNO (XEXP (operands[1], 0)) == T_REG))
1691 && XEXP (operands[1], 1) == const0_rtx)
1694 else if (TARGET_PRETEND_CMOVE)
1696 enum rtx_code code = GET_CODE (operands[1]);
1697 enum rtx_code new_code = code;
1698 rtx op0 = XEXP (operands[1], 0);
1699 rtx op1 = XEXP (operands[1], 1);
1701 if (! currently_expanding_to_rtl)
1705 case LT: case LE: case LEU: case LTU:
1706 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1709 new_code = reverse_condition (code);
1711 case EQ: case GT: case GE: case GEU: case GTU:
1716 sh_emit_scc_to_t (new_code, op0, op1);
1717 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1718 gen_rtx_REG (SImode, T_REG), const0_rtx);
1722 if (!can_create_pseudo_p ())
1725 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1726 GET_CODE (operands[1]),
1727 XEXP (operands[1], 0),
1728 XEXP (operands[1], 1));
1734 (define_expand "movqicc"
1735 [(set (match_operand:QI 0 "register_operand" "")
1736 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1737 (match_operand:QI 2 "register_operand" "")
1738 (match_operand:QI 3 "register_operand" "")))]
1741 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1742 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1743 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1744 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1748 ;; -------------------------------------------------------------------------
1749 ;; Addition instructions
1750 ;; -------------------------------------------------------------------------
1752 (define_expand "adddi3"
1753 [(set (match_operand:DI 0 "arith_reg_operand" "")
1754 (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
1755 (match_operand:DI 2 "arith_operand" "")))]
1760 if (!can_create_pseudo_p () && ! arith_reg_operand (operands[2], DImode))
1762 operands[2] = force_reg (DImode, operands[2]);
1763 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1768 (define_insn "*adddi3_media"
1769 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1770 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1771 (match_operand:DI 2 "arith_operand" "r,I10")))]
1776 [(set_attr "type" "arith_media")])
1778 (define_insn "*adddisi3_media"
1779 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1780 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1781 (match_operand:DI 2 "arith_operand" "r,I10")))]
1786 [(set_attr "type" "arith_media")
1787 (set_attr "highpart" "ignore")])
1789 (define_insn "adddi3z_media"
1790 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1792 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1793 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1795 "addz.l %1, %N2, %0"
1796 [(set_attr "type" "arith_media")
1797 (set_attr "highpart" "ignore")])
1799 (define_insn_and_split "adddi3_compact"
1800 [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
1801 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
1802 (match_operand:DI 2 "arith_reg_operand" "r")))
1803 (clobber (reg:SI T_REG))]
1806 "&& reload_completed"
1809 rtx high0 = gen_highpart (SImode, operands[0]);
1810 rtx high2 = gen_highpart (SImode, operands[2]);
1811 rtx low0 = gen_lowpart (SImode, operands[0]);
1813 emit_insn (gen_clrt ());
1814 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
1815 emit_insn (gen_addc (high0, high0, high2));
1820 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1821 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1822 (match_operand:SI 2 "arith_reg_operand" "r"))
1825 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1828 [(set_attr "type" "arith")])
1830 ;; A simplified version of the addc insn, where the exact value of the
1831 ;; T bit doesn't matter. This is easier for combine to pick up.
1832 ;; We allow a reg or 0 for one of the operands in order to be able to
1833 ;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
1835 (define_insn "*addc"
1836 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1837 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1838 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
1839 (match_operand:SI 3 "t_reg_operand" "")))
1840 (clobber (reg:SI T_REG))]
1843 [(set_attr "type" "arith")])
1845 ;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
1846 ;; better, if the sett insn can be done early.
1847 (define_insn_and_split "*addc"
1848 [(set (match_operand:SI 0 "arith_reg_dest" "")
1849 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
1850 (match_operand:SI 2 "arith_reg_operand" ""))
1852 (clobber (reg:SI T_REG))]
1856 [(set (reg:SI T_REG) (const_int 1))
1857 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1859 (clobber (reg:SI T_REG))])])
1861 ;; Left shifts by one are usually done with an add insn to avoid T_REG
1862 ;; clobbers. Thus addc can also be used to do something like '(x << 1) + 1'.
1863 (define_insn_and_split "*addc"
1864 [(set (match_operand:SI 0 "arith_reg_dest")
1865 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
1868 (clobber (reg:SI T_REG))]
1872 [(set (reg:SI T_REG) (const_int 1))
1873 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1875 (clobber (reg:SI T_REG))])])
1877 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1878 ;; matched. Split this up into a simple sub add sequence, as this will save
1879 ;; us one sett insn.
1880 (define_insn_and_split "*minus_plus_one"
1881 [(set (match_operand:SI 0 "arith_reg_dest" "")
1882 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1883 (match_operand:SI 2 "arith_reg_operand" ""))
1888 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1889 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1891 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1892 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1893 ;; operation, as opposed to sequences such as
1897 ;; Even if the constant is not CSE-ed, a sequence such as
1900 ;; can be scheduled much better since the load of the constant can be
1901 ;; done earlier, before any comparison insns that store the result in
1903 (define_insn_and_split "*addc"
1904 [(set (match_operand:SI 0 "arith_reg_dest" "")
1905 (plus:SI (match_operand:SI 1 "t_reg_operand" "")
1906 (match_operand:SI 2 "arith_reg_operand" "")))
1907 (clobber (reg:SI T_REG))]
1911 [(parallel [(set (match_dup 0)
1912 (plus:SI (plus:SI (match_dup 2) (const_int 0))
1914 (clobber (reg:SI T_REG))])])
1916 (define_expand "addsi3"
1917 [(set (match_operand:SI 0 "arith_reg_operand" "")
1918 (plus:SI (match_operand:SI 1 "arith_operand" "")
1919 (match_operand:SI 2 "arith_operand" "")))]
1923 operands[1] = force_reg (SImode, operands[1]);
1926 (define_insn "addsi3_media"
1927 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1928 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
1929 (match_operand:SI 2 "arith_operand" "r,I10")))]
1934 [(set_attr "type" "arith_media")
1935 (set_attr "highpart" "ignore")])
1937 (define_insn "addsidi3_media"
1938 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1939 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
1941 (match_operand:SI 2 "arith_operand"
1947 [(set_attr "type" "arith_media")
1948 (set_attr "highpart" "ignore")])
1950 (define_insn "*addsi3_compact"
1951 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1952 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
1953 (match_operand:SI 2 "arith_operand" "rI08")))]
1956 [(set_attr "type" "arith")])
1958 ;; -------------------------------------------------------------------------
1959 ;; Subtraction instructions
1960 ;; -------------------------------------------------------------------------
1962 (define_expand "subdi3"
1963 [(set (match_operand:DI 0 "arith_reg_operand" "")
1964 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
1965 (match_operand:DI 2 "arith_reg_operand" "")))]
1970 operands[1] = force_reg (DImode, operands[1]);
1971 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
1976 (define_insn "*subdi3_media"
1977 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1978 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1979 (match_operand:DI 2 "arith_reg_operand" "r")))]
1982 [(set_attr "type" "arith_media")])
1984 (define_insn "subdisi3_media"
1985 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
1986 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
1987 (match_operand:DI 2 "arith_reg_operand" "r")))]
1990 [(set_attr "type" "arith_media")
1991 (set_attr "highpart" "ignore")])
1993 (define_insn_and_split "subdi3_compact"
1994 [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
1995 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
1996 (match_operand:DI 2 "arith_reg_operand" "r")))
1997 (clobber (reg:SI T_REG))]
2000 "&& reload_completed"
2003 rtx high0 = gen_highpart (SImode, operands[0]);
2004 rtx high2 = gen_highpart (SImode, operands[2]);
2005 rtx low0 = gen_lowpart (SImode, operands[0]);
2007 emit_insn (gen_clrt ());
2008 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
2009 emit_insn (gen_subc (high0, high0, high2));
2014 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2015 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2016 (match_operand:SI 2 "arith_reg_operand" "r"))
2019 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2024 [(set_attr "type" "arith")])
2026 ;; A simplified version of the subc insn, where the exact value of the
2027 ;; T bit doesn't matter. This is easier for combine to pick up.
2028 ;; We allow a reg or 0 for one of the operands in order to be able to
2029 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2031 (define_insn "*subc"
2032 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2033 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2034 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
2035 (match_operand:SI 3 "t_reg_operand" "")))
2036 (clobber (reg:SI T_REG))]
2039 [(set_attr "type" "arith")])
2041 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2042 ;; better, if the sett insn can be done early.
2043 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2044 (define_insn_and_split "*subc"
2045 [(set (match_operand:SI 0 "arith_reg_dest" "")
2046 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2047 (match_operand:SI 2 "arith_reg_operand" "")))
2048 (clobber (reg:SI T_REG))]
2052 [(set (reg:SI T_REG) (const_int 1))
2053 (parallel [(set (match_dup 0)
2054 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2056 (clobber (reg:SI T_REG))])])
2058 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2059 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2060 ;; operation, as opposed to sequences such as
2064 ;; Even if the constant is not CSE-ed, a sequence such as
2067 ;; can be scheduled much better since the load of the constant can be
2068 ;; done earlier, before any comparison insns that store the result in
2070 (define_insn_and_split "*subc"
2071 [(set (match_operand:SI 0 "arith_reg_dest" "")
2072 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2073 (match_operand:SI 2 "t_reg_operand" "")))
2074 (clobber (reg:SI T_REG))]
2078 [(parallel [(set (match_dup 0)
2079 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2081 (clobber (reg:SI T_REG))])])
2083 (define_insn "*subsi3_internal"
2084 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2085 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2086 (match_operand:SI 2 "arith_reg_operand" "r")))]
2089 [(set_attr "type" "arith")])
2091 (define_insn_and_split "*subsi3_media"
2092 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2093 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2094 (match_operand:SI 2 "extend_reg_operand" "r")))]
2096 && (operands[1] != constm1_rtx
2097 || (GET_CODE (operands[2]) != TRUNCATE
2098 && GET_CODE (operands[2]) != SUBREG))"
2100 "operands[1] == constm1_rtx"
2101 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2103 [(set_attr "type" "arith_media")
2104 (set_attr "highpart" "ignore")])
2107 [(set (match_operand:SI 0 "arith_reg_dest" "")
2108 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2109 "general_extend_operand"
2111 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2112 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2113 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2117 [(set (match_operand:SI 0 "arith_reg_dest" "")
2118 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2119 "general_extend_operand"
2121 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
2122 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2123 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2131 ;; since this will sometimes save one instruction.
2132 ;; Otherwise we might get a sequence like
2136 ;; if the source and dest regs are the same.
2137 (define_expand "subsi3"
2138 [(set (match_operand:SI 0 "arith_reg_operand" "")
2139 (minus:SI (match_operand:SI 1 "arith_operand" "")
2140 (match_operand:SI 2 "arith_reg_operand" "")))]
2143 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2145 emit_insn (gen_negsi2 (operands[0], operands[2]));
2146 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2151 if (!can_create_pseudo_p ()
2152 && ! arith_reg_or_0_operand (operands[1], SImode))
2154 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2155 operands[1] = force_reg (SImode, operands[1]);
2159 ;; -------------------------------------------------------------------------
2160 ;; Division instructions
2161 ;; -------------------------------------------------------------------------
2163 ;; We take advantage of the library routines which don't clobber as many
2164 ;; registers as a normal function call would.
2166 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2167 ;; also has an effect on the register that holds the address of the sfunc.
2168 ;; To make this work, we have an extra dummy insn that shows the use
2169 ;; of this register for reorg.
2171 (define_insn "use_sfunc_addr"
2172 [(set (reg:SI PR_REG)
2173 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2174 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2176 [(set_attr "length" "0")])
2178 (define_insn "udivsi3_sh2a"
2179 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2180 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2181 (match_operand:SI 2 "arith_reg_operand" "z")))]
2184 [(set_attr "type" "arith")
2185 (set_attr "in_delay_slot" "no")])
2187 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2188 ;; hard register 0. If we used hard register 0, then the next instruction
2189 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2190 ;; gets allocated to a stack slot that needs its address reloaded, then
2191 ;; there is nothing to prevent reload from using r0 to reload the address.
2192 ;; This reload would clobber the value in r0 we are trying to store.
2193 ;; If we let reload allocate r0, then this problem can never happen.
2194 (define_insn "udivsi3_i1"
2195 [(set (match_operand:SI 0 "register_operand" "=z")
2196 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2197 (clobber (reg:SI T_REG))
2198 (clobber (reg:SI PR_REG))
2199 (clobber (reg:SI R4_REG))
2200 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2201 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2203 [(set_attr "type" "sfunc")
2204 (set_attr "needs_delay_slot" "yes")])
2206 ; Since shmedia-nofpu code could be linked against shcompact code, and
2207 ; the udivsi3 libcall has the same name, we must consider all registers
2208 ; clobbered that are in the union of the registers clobbered by the
2209 ; shmedia and the shcompact implementation. Note, if the shcompact
2210 ; implementation actually used shcompact code, we'd need to clobber
2211 ; also r23 and fr23.
2212 (define_insn "udivsi3_i1_media"
2213 [(set (match_operand:SI 0 "register_operand" "=z")
2214 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2215 (clobber (reg:SI T_MEDIA_REG))
2216 (clobber (reg:SI PR_MEDIA_REG))
2217 (clobber (reg:SI R20_REG))
2218 (clobber (reg:SI R21_REG))
2219 (clobber (reg:SI R22_REG))
2220 (clobber (reg:DI TR0_REG))
2221 (clobber (reg:DI TR1_REG))
2222 (clobber (reg:DI TR2_REG))
2223 (use (match_operand 1 "target_reg_operand" "b"))]
2224 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2226 [(set_attr "type" "sfunc")
2227 (set_attr "needs_delay_slot" "yes")])
2229 (define_expand "udivsi3_i4_media"
2231 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2233 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2234 (set (match_dup 5) (float:DF (match_dup 3)))
2235 (set (match_dup 6) (float:DF (match_dup 4)))
2236 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2237 (set (match_dup 8) (fix:DI (match_dup 7)))
2238 (set (match_operand:SI 0 "register_operand" "")
2239 (truncate:SI (match_dup 8)))]
2240 "TARGET_SHMEDIA_FPU"
2242 operands[3] = gen_reg_rtx (DImode);
2243 operands[4] = gen_reg_rtx (DImode);
2244 operands[5] = gen_reg_rtx (DFmode);
2245 operands[6] = gen_reg_rtx (DFmode);
2246 operands[7] = gen_reg_rtx (DFmode);
2247 operands[8] = gen_reg_rtx (DImode);
2250 (define_insn "udivsi3_i4"
2251 [(set (match_operand:SI 0 "register_operand" "=y")
2252 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2253 (clobber (reg:SI T_REG))
2254 (clobber (reg:SI PR_REG))
2255 (clobber (reg:DF DR0_REG))
2256 (clobber (reg:DF DR2_REG))
2257 (clobber (reg:DF DR4_REG))
2258 (clobber (reg:SI R0_REG))
2259 (clobber (reg:SI R1_REG))
2260 (clobber (reg:SI R4_REG))
2261 (clobber (reg:SI R5_REG))
2262 (use (reg:PSI FPSCR_REG))
2263 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2264 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2266 [(set_attr "type" "sfunc")
2267 (set_attr "fp_mode" "double")
2268 (set_attr "needs_delay_slot" "yes")])
2270 (define_insn "udivsi3_i4_single"
2271 [(set (match_operand:SI 0 "register_operand" "=y")
2272 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2273 (clobber (reg:SI T_REG))
2274 (clobber (reg:SI PR_REG))
2275 (clobber (reg:DF DR0_REG))
2276 (clobber (reg:DF DR2_REG))
2277 (clobber (reg:DF DR4_REG))
2278 (clobber (reg:SI R0_REG))
2279 (clobber (reg:SI R1_REG))
2280 (clobber (reg:SI R4_REG))
2281 (clobber (reg:SI R5_REG))
2282 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2283 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2284 && TARGET_FPU_SINGLE"
2286 [(set_attr "type" "sfunc")
2287 (set_attr "needs_delay_slot" "yes")])
2289 (define_insn "udivsi3_i4_int"
2290 [(set (match_operand:SI 0 "register_operand" "=z")
2291 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2292 (clobber (reg:SI T_REG))
2293 (clobber (reg:SI R1_REG))
2294 (clobber (reg:SI PR_REG))
2295 (clobber (reg:SI MACH_REG))
2296 (clobber (reg:SI MACL_REG))
2297 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2300 [(set_attr "type" "sfunc")
2301 (set_attr "needs_delay_slot" "yes")])
2304 (define_expand "udivsi3"
2305 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2306 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2307 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2308 (parallel [(set (match_operand:SI 0 "register_operand" "")
2309 (udiv:SI (reg:SI R4_REG)
2311 (clobber (reg:SI T_REG))
2312 (clobber (reg:SI PR_REG))
2313 (clobber (reg:SI R4_REG))
2314 (use (match_dup 3))])]
2319 operands[3] = gen_reg_rtx (Pmode);
2320 /* Emit the move of the address to a pseudo outside of the libcall. */
2321 if (TARGET_DIVIDE_CALL_TABLE)
2323 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2324 that causes problems when the divide code is supposed to come from a
2325 separate library. Division by zero is undefined, so dividing 1 can be
2326 implemented by comparing with the divisor. */
2327 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2329 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2330 emit_insn (gen_cstoresi4 (operands[0], test,
2331 operands[1], operands[2]));
2334 else if (operands[2] == const0_rtx)
2336 emit_move_insn (operands[0], operands[2]);
2339 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2340 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2342 else if (TARGET_DIVIDE_CALL_FP)
2344 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2345 if (TARGET_FPU_SINGLE)
2346 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2348 last = gen_udivsi3_i4 (operands[0], operands[3]);
2350 else if (TARGET_SHMEDIA_FPU)
2352 operands[1] = force_reg (SImode, operands[1]);
2353 operands[2] = force_reg (SImode, operands[2]);
2354 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2357 else if (TARGET_SH2A)
2359 operands[1] = force_reg (SImode, operands[1]);
2360 operands[2] = force_reg (SImode, operands[2]);
2361 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2364 else if (TARGET_SH5)
2366 function_symbol (operands[3],
2367 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2371 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2372 else if (TARGET_FPU_ANY)
2373 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2375 last = gen_udivsi3_i1 (operands[0], operands[3]);
2379 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2380 last = gen_udivsi3_i1 (operands[0], operands[3]);
2382 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2383 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2388 (define_insn "divsi3_sh2a"
2389 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2390 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2391 (match_operand:SI 2 "arith_reg_operand" "z")))]
2394 [(set_attr "type" "arith")
2395 (set_attr "in_delay_slot" "no")])
2397 (define_insn "divsi3_i1"
2398 [(set (match_operand:SI 0 "register_operand" "=z")
2399 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2400 (clobber (reg:SI T_REG))
2401 (clobber (reg:SI PR_REG))
2402 (clobber (reg:SI R1_REG))
2403 (clobber (reg:SI R2_REG))
2404 (clobber (reg:SI R3_REG))
2405 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2406 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2408 [(set_attr "type" "sfunc")
2409 (set_attr "needs_delay_slot" "yes")])
2411 (define_insn "divsi3_i1_media"
2412 [(set (match_operand:SI 0 "register_operand" "=z")
2413 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2414 (clobber (reg:SI T_MEDIA_REG))
2415 (clobber (reg:SI PR_MEDIA_REG))
2416 (clobber (reg:SI R1_REG))
2417 (clobber (reg:SI R20_REG))
2418 (clobber (reg:SI R21_REG))
2419 (clobber (reg:SI TR0_REG))
2420 (use (match_operand 1 "target_reg_operand" "b"))]
2421 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2423 [(set_attr "type" "sfunc")])
2425 (define_insn "divsi3_media_2"
2426 [(set (match_operand:SI 0 "register_operand" "=z")
2427 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2428 (clobber (reg:SI T_MEDIA_REG))
2429 (clobber (reg:SI PR_MEDIA_REG))
2430 (clobber (reg:SI R1_REG))
2431 (clobber (reg:SI R21_REG))
2432 (clobber (reg:SI TR0_REG))
2433 (use (reg:SI R20_REG))
2434 (use (match_operand 1 "target_reg_operand" "b"))]
2435 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2437 [(set_attr "type" "sfunc")])
2439 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2440 ;; hard reg clobbers and data dependencies that we need when we want
2441 ;; to rematerialize the division into a call.
2442 (define_insn_and_split "divsi_inv_call"
2443 [(set (match_operand:SI 0 "register_operand" "=r")
2444 (div:SI (match_operand:SI 1 "register_operand" "r")
2445 (match_operand:SI 2 "register_operand" "r")))
2446 (clobber (reg:SI R4_REG))
2447 (clobber (reg:SI R5_REG))
2448 (clobber (reg:SI T_MEDIA_REG))
2449 (clobber (reg:SI PR_MEDIA_REG))
2450 (clobber (reg:SI R1_REG))
2451 (clobber (reg:SI R21_REG))
2452 (clobber (reg:SI TR0_REG))
2453 (clobber (reg:SI R20_REG))
2454 (use (match_operand:SI 3 "register_operand" "r"))]
2457 "&& (reload_in_progress || reload_completed)"
2458 [(set (match_dup 0) (match_dup 3))]
2460 [(set_attr "highpart" "must_split")])
2462 ;; This is the combiner pattern for -mdiv=inv:call .
2463 (define_insn_and_split "*divsi_inv_call_combine"
2464 [(set (match_operand:SI 0 "register_operand" "=z")
2465 (div:SI (match_operand:SI 1 "register_operand" "r")
2466 (match_operand:SI 2 "register_operand" "r")))
2467 (clobber (reg:SI R4_REG))
2468 (clobber (reg:SI R5_REG))
2469 (clobber (reg:SI T_MEDIA_REG))
2470 (clobber (reg:SI PR_MEDIA_REG))
2471 (clobber (reg:SI R1_REG))
2472 (clobber (reg:SI R21_REG))
2473 (clobber (reg:SI TR0_REG))
2474 (clobber (reg:SI R20_REG))
2475 (use (unspec:SI [(match_dup 1)
2476 (match_operand:SI 3 "" "")
2477 (unspec:SI [(match_operand:SI 4 "" "")
2479 (match_operand:DI 5 "" "")]
2481 (match_operand:DI 6 "" "")
2484 UNSPEC_DIV_INV_M3))]
2487 "&& (reload_in_progress || reload_completed)"
2490 const char *name = sh_divsi3_libfunc;
2491 enum sh_function_kind kind = SFUNC_GOT;
2494 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2495 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2496 while (TARGET_DIVIDE_INV_CALL2)
2498 rtx x = operands[3];
2500 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2502 x = XVECEXP (x, 0, 0);
2503 name = "__sdivsi3_2";
2504 kind = SFUNC_STATIC;
2505 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2508 sym = function_symbol (NULL, name, kind);
2509 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2512 [(set_attr "highpart" "must_split")])
2514 (define_expand "divsi3_i4_media"
2515 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2516 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2517 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2518 (set (match_operand:SI 0 "register_operand" "=r")
2519 (fix:SI (match_dup 5)))]
2520 "TARGET_SHMEDIA_FPU"
2522 operands[3] = gen_reg_rtx (DFmode);
2523 operands[4] = gen_reg_rtx (DFmode);
2524 operands[5] = gen_reg_rtx (DFmode);
2527 (define_insn "divsi3_i4"
2528 [(set (match_operand:SI 0 "register_operand" "=y")
2529 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2530 (clobber (reg:SI PR_REG))
2531 (clobber (reg:DF DR0_REG))
2532 (clobber (reg:DF DR2_REG))
2533 (use (reg:PSI FPSCR_REG))
2534 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2535 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2537 [(set_attr "type" "sfunc")
2538 (set_attr "fp_mode" "double")
2539 (set_attr "needs_delay_slot" "yes")])
2541 (define_insn "divsi3_i4_single"
2542 [(set (match_operand:SI 0 "register_operand" "=y")
2543 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2544 (clobber (reg:SI PR_REG))
2545 (clobber (reg:DF DR0_REG))
2546 (clobber (reg:DF DR2_REG))
2547 (clobber (reg:SI R2_REG))
2548 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2549 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2550 && TARGET_FPU_SINGLE"
2552 [(set_attr "type" "sfunc")
2553 (set_attr "needs_delay_slot" "yes")])
2555 (define_insn "divsi3_i4_int"
2556 [(set (match_operand:SI 0 "register_operand" "=z")
2557 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2558 (clobber (reg:SI T_REG))
2559 (clobber (reg:SI PR_REG))
2560 (clobber (reg:SI R1_REG))
2561 (clobber (reg:SI MACH_REG))
2562 (clobber (reg:SI MACL_REG))
2563 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2566 [(set_attr "type" "sfunc")
2567 (set_attr "needs_delay_slot" "yes")])
2569 (define_expand "divsi3"
2570 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2571 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2572 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2573 (parallel [(set (match_operand:SI 0 "register_operand" "")
2574 (div:SI (reg:SI R4_REG)
2576 (clobber (reg:SI T_REG))
2577 (clobber (reg:SI PR_REG))
2578 (clobber (reg:SI R1_REG))
2579 (clobber (reg:SI R2_REG))
2580 (clobber (reg:SI R3_REG))
2581 (use (match_dup 3))])]
2586 operands[3] = gen_reg_rtx (Pmode);
2587 /* Emit the move of the address to a pseudo outside of the libcall. */
2588 if (TARGET_DIVIDE_CALL_TABLE)
2590 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2591 last = gen_divsi3_i4_int (operands[0], operands[3]);
2593 else if (TARGET_DIVIDE_CALL_FP)
2595 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2596 if (TARGET_FPU_SINGLE)
2597 last = gen_divsi3_i4_single (operands[0], operands[3]);
2599 last = gen_divsi3_i4 (operands[0], operands[3]);
2601 else if (TARGET_SH2A)
2603 operands[1] = force_reg (SImode, operands[1]);
2604 operands[2] = force_reg (SImode, operands[2]);
2605 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2608 else if (TARGET_DIVIDE_INV)
2610 rtx dividend = operands[1];
2611 rtx divisor = operands[2];
2613 rtx nsb_res = gen_reg_rtx (DImode);
2614 rtx norm64 = gen_reg_rtx (DImode);
2615 rtx tab_ix = gen_reg_rtx (DImode);
2616 rtx norm32 = gen_reg_rtx (SImode);
2617 rtx i92 = force_reg (DImode, GEN_INT (92));
2618 rtx scratch0a = gen_reg_rtx (DImode);
2619 rtx scratch0b = gen_reg_rtx (DImode);
2620 rtx inv0 = gen_reg_rtx (SImode);
2621 rtx scratch1a = gen_reg_rtx (DImode);
2622 rtx scratch1b = gen_reg_rtx (DImode);
2623 rtx shift = gen_reg_rtx (DImode);
2625 rtx inv1 = gen_reg_rtx (SImode);
2626 rtx scratch2a = gen_reg_rtx (DImode);
2627 rtx scratch2b = gen_reg_rtx (SImode);
2628 rtx inv2 = gen_reg_rtx (SImode);
2629 rtx scratch3a = gen_reg_rtx (DImode);
2630 rtx scratch3b = gen_reg_rtx (DImode);
2631 rtx scratch3c = gen_reg_rtx (DImode);
2632 rtx scratch3d = gen_reg_rtx (SImode);
2633 rtx scratch3e = gen_reg_rtx (DImode);
2634 rtx result = gen_reg_rtx (SImode);
2636 if (! arith_reg_or_0_operand (dividend, SImode))
2637 dividend = force_reg (SImode, dividend);
2638 if (! arith_reg_operand (divisor, SImode))
2639 divisor = force_reg (SImode, divisor);
2640 if (flag_pic && Pmode != DImode)
2642 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2643 tab_base = gen_datalabel_ref (tab_base);
2644 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2648 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2649 tab_base = gen_datalabel_ref (tab_base);
2650 tab_base = force_reg (DImode, tab_base);
2652 if (TARGET_DIVIDE_INV20U)
2653 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2655 i2p27 = GEN_INT (0);
2656 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2657 i43 = force_reg (DImode, GEN_INT (43));
2660 emit_insn (gen_nsbdi (nsb_res,
2661 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2662 emit_insn (gen_ashldi3_media (norm64,
2663 gen_rtx_SUBREG (DImode, divisor, 0),
2665 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2666 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2667 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2668 inv0, scratch0a, scratch0b,
2669 scratch1a, scratch1b));
2670 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2671 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2673 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2675 scratch3a, scratch3b, scratch3c,
2676 scratch2a, scratch2b, scratch3d, scratch3e));
2677 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2678 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2679 else if (TARGET_DIVIDE_INV_FP)
2680 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2681 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2682 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2683 gen_reg_rtx (DFmode)));
2685 emit_move_insn (operands[0], result);
2688 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2690 operands[1] = force_reg (SImode, operands[1]);
2691 operands[2] = force_reg (SImode, operands[2]);
2692 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2695 else if (TARGET_SH5)
2697 if (TARGET_DIVIDE_CALL2)
2699 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2700 tab_base = gen_datalabel_ref (tab_base);
2701 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2703 if (TARGET_FPU_ANY && TARGET_SH1)
2704 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2705 else if (TARGET_DIVIDE_CALL2)
2706 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
2708 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2711 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2712 (operands[0], operands[3]));
2713 else if (TARGET_FPU_ANY)
2714 last = gen_divsi3_i4_single (operands[0], operands[3]);
2716 last = gen_divsi3_i1 (operands[0], operands[3]);
2720 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2721 last = gen_divsi3_i1 (operands[0], operands[3]);
2723 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2724 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2729 ;; operands: scratch, tab_base, tab_ix
2730 ;; These are unspecs because we could generate an indexed addressing mode
2731 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2732 ;; confuse reload. See PR27117.
2733 (define_insn "divsi_inv_qitable"
2734 [(set (match_operand:DI 0 "register_operand" "=r")
2735 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2736 (match_operand:DI 2 "register_operand" "r")]
2737 UNSPEC_DIV_INV_TABLE)))]
2740 [(set_attr "type" "load_media")
2741 (set_attr "highpart" "user")])
2743 ;; operands: scratch, tab_base, tab_ix
2744 (define_insn "divsi_inv_hitable"
2745 [(set (match_operand:DI 0 "register_operand" "=r")
2746 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2747 (match_operand:DI 2 "register_operand" "r")]
2748 UNSPEC_DIV_INV_TABLE)))]
2751 [(set_attr "type" "load_media")
2752 (set_attr "highpart" "user")])
2754 ;; operands: inv0, tab_base, tab_ix, norm32
2755 ;; scratch equiv in sdivsi3_2: r19, r21
2756 (define_expand "divsi_inv_m0"
2757 [(set (match_operand:SI 0 "register_operand" "=r")
2758 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2759 (match_operand:DI 2 "register_operand" "r")
2760 (match_operand:SI 3 "register_operand" "r")]
2762 (clobber (match_operand:DI 4 "register_operand" "=r"))
2763 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2770 ldx.ub r20, r21, r19 // u0.8
2772 muls.l r25, r19, r19 // s2.38
2773 ldx.w r20, r21, r21 // s2.14
2774 shari r19, 24, r19 // truncate to s2.14
2775 sub r21, r19, r19 // some 11 bit inverse in s1.14
2778 rtx inv0 = operands[0];
2779 rtx tab_base = operands[1];
2780 rtx tab_ix = operands[2];
2781 rtx norm32 = operands[3];
2782 rtx scratch0 = operands[4];
2783 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2784 rtx scratch1 = operands[5];
2786 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2787 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2788 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2789 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2790 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2791 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2795 ;; operands: inv1, tab_base, tab_ix, norm32
2796 (define_insn_and_split "divsi_inv_m1"
2797 [(set (match_operand:SI 0 "register_operand" "=r")
2798 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2799 (match_operand:DI 2 "register_operand" "r")
2800 (match_operand:SI 3 "register_operand" "r")]
2802 (clobber (match_operand:SI 4 "register_operand" "=r"))
2803 (clobber (match_operand:DI 5 "register_operand" "=r"))
2804 (clobber (match_operand:DI 6 "register_operand" "=r"))
2805 (clobber (match_operand:DI 7 "register_operand" "=r"))
2806 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2809 "&& !can_create_pseudo_p ()"
2813 muls.l r19, r19, r18 // u0.28
2814 muls.l r25, r18, r18 // s2.58
2815 shlli r19, 45, r0 // multiply by two and convert to s2.58
2817 shari r18, 28, r18 // some 18 bit inverse in s1.30
2820 rtx inv1 = operands[0];
2821 rtx tab_base = operands[1];
2822 rtx tab_ix = operands[2];
2823 rtx norm32 = operands[3];
2824 rtx inv0 = operands[4];
2825 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2826 rtx scratch0a = operands[5];
2827 rtx scratch0b = operands[6];
2828 rtx scratch0 = operands[7];
2829 rtx scratch1 = operands[8];
2830 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2832 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2833 scratch0a, scratch0b));
2834 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2835 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2836 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2837 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2838 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2842 ;; operands: inv2, norm32, inv1, i92
2843 (define_insn_and_split "divsi_inv_m2"
2844 [(set (match_operand:SI 0 "register_operand" "=r")
2845 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2846 (match_operand:SI 2 "register_operand" "r")
2847 (match_operand:DI 3 "register_operand" "r")]
2849 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2852 "&& !can_create_pseudo_p ()"
2856 muls.l r18, r25, r0 // s2.60
2857 shari r0, 16, r0 // s-16.44
2859 muls.l r0, r18, r19 // s-16.74
2860 shari r19, 30, r19 // s-16.44
2862 rtx inv2 = operands[0];
2863 rtx norm32 = operands[1];
2864 rtx inv1 = operands[2];
2865 rtx i92 = operands[3];
2866 rtx scratch0 = operands[4];
2867 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2869 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
2870 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
2871 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
2872 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
2873 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
2877 (define_insn_and_split "divsi_inv_m3"
2878 [(set (match_operand:SI 0 "register_operand" "=r")
2879 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
2880 (match_operand:SI 2 "register_operand" "r")
2881 (match_operand:SI 3 "register_operand" "r")
2882 (match_operand:DI 4 "register_operand" "r")
2883 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
2884 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
2886 (clobber (match_operand:DI 7 "register_operand" "=r"))
2887 (clobber (match_operand:DI 8 "register_operand" "=r"))
2888 (clobber (match_operand:DI 9 "register_operand" "=r"))
2889 (clobber (match_operand:DI 10 "register_operand" "=r"))
2890 (clobber (match_operand:SI 11 "register_operand" "=r"))
2891 (clobber (match_operand:SI 12 "register_operand" "=r"))
2892 (clobber (match_operand:DI 13 "register_operand" "=r"))]
2895 "&& !can_create_pseudo_p ()"
2899 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
2900 r0: scratch0 r19: scratch1 r21: scratch2
2902 muls.l r18, r4, r25 // s32.30
2903 muls.l r19, r4, r19 // s15.30
2905 shari r19, 14, r19 // s18.-14
2911 rtx result = operands[0];
2912 rtx dividend = operands[1];
2913 rtx inv1 = operands[2];
2914 rtx inv2 = operands[3];
2915 rtx shift = operands[4];
2916 rtx scratch0 = operands[7];
2917 rtx scratch1 = operands[8];
2918 rtx scratch2 = operands[9];
2920 if (satisfies_constraint_N (dividend))
2922 emit_move_insn (result, dividend);
2926 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
2927 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
2928 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
2929 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
2930 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
2931 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
2932 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
2936 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
2937 ;; inv1: tab_base, tab_ix, norm32
2938 ;; inv2: norm32, inv1, i92
2939 (define_insn_and_split "divsi_inv_m1_3"
2940 [(set (match_operand:SI 0 "register_operand" "=r")
2941 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
2942 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
2943 (match_operand:DI 3 "register_operand" "r")
2944 (match_operand:SI 4 "register_operand" "r")]
2946 (unspec:SI [(match_dup 4)
2947 (unspec:SI [(match_dup 2)
2949 (match_dup 4)] UNSPEC_DIV_INV_M1)
2950 (match_operand:SI 5 "" "")]
2952 (match_operand:DI 6 "register_operand" "r")
2953 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
2954 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
2956 (clobber (match_operand:DI 9 "register_operand" "=r"))
2957 (clobber (match_operand:DI 10 "register_operand" "=r"))
2958 (clobber (match_operand:DI 11 "register_operand" "=r"))
2959 (clobber (match_operand:DI 12 "register_operand" "=r"))
2960 (clobber (match_operand:SI 13 "register_operand" "=r"))
2961 (clobber (match_operand:SI 14 "register_operand" "=r"))
2962 (clobber (match_operand:DI 15 "register_operand" "=r"))]
2964 && (TARGET_DIVIDE_INV_MINLAT
2965 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
2967 "&& !can_create_pseudo_p ()"
2970 rtx result = operands[0];
2971 rtx dividend = operands[1];
2972 rtx tab_base = operands[2];
2973 rtx tab_ix = operands[3];
2974 rtx norm32 = operands[4];
2975 /* rtx i92 = operands[5]; */
2976 rtx shift = operands[6];
2977 rtx i2p27 = operands[7];
2978 rtx i43 = operands[8];
2979 rtx scratch0 = operands[9];
2980 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2981 rtx scratch1 = operands[10];
2982 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2983 rtx scratch2 = operands[11];
2984 rtx scratch3 = operands[12];
2985 rtx scratch4 = operands[13];
2986 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
2987 rtx scratch5 = operands[14];
2988 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
2989 rtx scratch6 = operands[15];
2991 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
2992 scratch0, scratch1));
2993 /* inv0 == scratch4 */
2994 if (! TARGET_DIVIDE_INV20U)
2996 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
2998 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3002 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3003 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3005 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3006 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3007 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3008 /* inv1 == scratch4 */
3010 if (TARGET_DIVIDE_INV_MINLAT)
3012 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3013 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3014 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3015 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3016 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3017 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3018 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3019 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3020 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3021 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3022 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3026 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3027 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3028 emit_insn (gen_nsbdi (scratch6,
3029 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3030 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3031 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3032 emit_insn (gen_divsi_inv20 (scratch2,
3033 norm32, scratch4, dividend,
3034 scratch6, scratch3, i43,
3035 /* scratch0 may be shared with i2p27. */
3036 scratch0, scratch1, scratch5,
3037 label, label, i2p27));
3039 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3040 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3044 (define_insn "divsi_inv20"
3045 [(set (match_operand:DI 0 "register_operand" "=&r")
3046 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3047 (match_operand:SI 2 "register_operand" "r")
3048 (match_operand:SI 3 "register_operand" "r")
3049 (match_operand:DI 4 "register_operand" "r")
3050 (match_operand:DI 5 "register_operand" "r")
3051 (match_operand:DI 6 "register_operand" "r")
3052 (match_operand:DI 12 "register_operand" "r")
3053 (match_operand 10 "target_operand" "b")
3054 (match_operand 11 "immediate_operand" "i")]
3056 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3057 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3058 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3060 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3062 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3063 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3064 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3065 %10 label (tr), %11 label (imm)
3067 muls.l inv1, norm32, scratch0 // s2.60
3068 muls.l inv1, dividend, result // s32.30
3069 xor i2p27, result_sign, round_scratch
3070 bge/u dividend_nsb, i43, tr.. (label)
3071 shari scratch0, 16, scratch0 // s-16.44
3072 muls.l sratch0_si, inv1, scratch0 // s-16.74
3073 sub result, round_scratch, result
3074 shari dividend, 14, scratch1 // s19.-14
3075 shari scratch0, 30, scratch0 // s-16.44
3076 muls.l scratch0, scratch1, round_scratch // s15.30
3078 sub result, round_scratch, result */
3080 const bool likely = TARGET_DIVIDE_INV20L;
3083 "muls.l %2, %3, %0" "\n"
3084 " xor %12, %5, %7" "\n"
3085 " bge/l %4, %6, %10" "\n"
3086 " muls.l %2, %1, %8" "\n"
3087 " shari %8, 16, %8" "\n"
3088 " muls.l %8, %2, %8" "\n"
3089 " shari %3, 14, %9" "\n"
3090 " shari %8, 30, %8" "\n"
3091 " muls.l %8, %9, %8" "\n"
3092 " sub %0, %8, %0" "\n"
3093 "%11: add %0, %7, %0";
3096 "muls.l %2, %1, %8" "\n"
3097 " muls.l %2, %3, %0" "\n"
3098 " xor %12, %5, %7" "\n"
3099 " bge/u %4, %6, %10" "\n"
3100 " shari %8, 16, %8" "\n"
3101 " muls.l %8, %2, %8" "\n"
3102 " sub %0, %7, %0" "\n"
3103 " shari %3, 14, %9" "\n"
3104 " shari %8, 30, %8" "\n"
3105 " muls.l %8, %9, %7" "\n"
3106 "%11: sub %0, %7, %0";
3109 (define_insn_and_split "divsi_inv_fp"
3110 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3111 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3112 (match_operand:SI 2 "register_operand" "rf")))
3113 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3114 (clobber (match_operand:SI 4 "register_operand" "=r"))
3115 (clobber (match_operand:SI 5 "register_operand" "=r"))
3116 (clobber (match_operand:DF 6 "register_operand" "=r"))
3117 (clobber (match_operand:DF 7 "register_operand" "=r"))
3118 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3119 "TARGET_SHMEDIA_FPU"
3121 "&& (reload_in_progress || reload_completed)"
3122 [(set (match_dup 0) (match_dup 3))]
3124 [(set_attr "highpart" "must_split")])
3126 ;; If a matching group of divide-by-inverse instructions is in the same
3127 ;; basic block after gcse & loop optimizations, we want to transform them
3128 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3129 (define_insn_and_split "*divsi_inv_fp_combine"
3130 [(set (match_operand:SI 0 "register_operand" "=f")
3131 (div:SI (match_operand:SI 1 "register_operand" "f")
3132 (match_operand:SI 2 "register_operand" "f")))
3133 (use (unspec:SI [(match_dup 1)
3134 (match_operand:SI 3 "" "")
3135 (unspec:SI [(match_operand:SI 4 "" "")
3137 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3138 (match_operand:DI 6 "" "")
3140 (const_int 0)] UNSPEC_DIV_INV_M3))
3141 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3142 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3143 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3144 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3145 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3146 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3149 [(set (match_dup 9) (float:DF (match_dup 1)))
3150 (set (match_dup 10) (float:DF (match_dup 2)))
3151 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3153 (fix:SI (match_dup 11)))
3154 (set (match_dup 0) (match_dup 8))]
3156 if (! fp_arith_reg_operand (operands[1], SImode))
3158 emit_move_insn (operands[7], operands[1]);
3159 operands[1] = operands[7];
3161 if (! fp_arith_reg_operand (operands[2], SImode))
3163 emit_move_insn (operands[8], operands[2]);
3164 operands[2] = operands[8];
3167 [(set_attr "highpart" "must_split")])
3169 ;; -------------------------------------------------------------------------
3170 ;; Multiplication instructions
3171 ;; -------------------------------------------------------------------------
3173 (define_insn "umulhisi3_i"
3174 [(set (reg:SI MACL_REG)
3175 (mult:SI (zero_extend:SI
3176 (match_operand:HI 0 "arith_reg_operand" "r"))
3178 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3181 [(set_attr "type" "smpy")])
3183 (define_insn "mulhisi3_i"
3184 [(set (reg:SI MACL_REG)
3185 (mult:SI (sign_extend:SI
3186 (match_operand:HI 0 "arith_reg_operand" "r"))
3188 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3191 [(set_attr "type" "smpy")])
3193 (define_expand "mulhisi3"
3194 [(set (reg:SI MACL_REG)
3195 (mult:SI (sign_extend:SI
3196 (match_operand:HI 1 "arith_reg_operand" ""))
3198 (match_operand:HI 2 "arith_reg_operand" ""))))
3199 (set (match_operand:SI 0 "arith_reg_operand" "")
3205 macl = gen_rtx_REG (SImode, MACL_REG);
3207 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3208 insn = get_insns ();
3210 /* expand_binop can't find a suitable code in umul_widen_optab to
3211 make a REG_EQUAL note from, so make one here.
3212 See also smulsi3_highpart.
3213 ??? Alternatively, we could put this at the calling site of expand_binop,
3214 i.e. expand_expr. */
3215 /* Use emit_libcall_block for loop invariant code motion and to make
3216 a REG_EQUAL note. */
3217 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3222 (define_expand "umulhisi3"
3223 [(set (reg:SI MACL_REG)
3224 (mult:SI (zero_extend:SI
3225 (match_operand:HI 1 "arith_reg_operand" ""))
3227 (match_operand:HI 2 "arith_reg_operand" ""))))
3228 (set (match_operand:SI 0 "arith_reg_operand" "")
3234 macl = gen_rtx_REG (SImode, MACL_REG);
3236 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3237 insn = get_insns ();
3239 /* expand_binop can't find a suitable code in umul_widen_optab to
3240 make a REG_EQUAL note from, so make one here.
3241 See also smulsi3_highpart.
3242 ??? Alternatively, we could put this at the calling site of expand_binop,
3243 i.e. expand_expr. */
3244 /* Use emit_libcall_block for loop invariant code motion and to make
3245 a REG_EQUAL note. */
3246 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3251 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3252 ;; a call to a routine which clobbers known registers.
3254 [(set (match_operand:SI 1 "register_operand" "=z")
3255 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3256 (clobber (reg:SI MACL_REG))
3257 (clobber (reg:SI T_REG))
3258 (clobber (reg:SI PR_REG))
3259 (clobber (reg:SI R3_REG))
3260 (clobber (reg:SI R2_REG))
3261 (clobber (reg:SI R1_REG))
3262 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3265 [(set_attr "type" "sfunc")
3266 (set_attr "needs_delay_slot" "yes")])
3268 (define_expand "mulsi3_call"
3269 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3270 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3271 (parallel[(set (match_operand:SI 0 "register_operand" "")
3272 (mult:SI (reg:SI R4_REG)
3274 (clobber (reg:SI MACL_REG))
3275 (clobber (reg:SI T_REG))
3276 (clobber (reg:SI PR_REG))
3277 (clobber (reg:SI R3_REG))
3278 (clobber (reg:SI R2_REG))
3279 (clobber (reg:SI R1_REG))
3280 (use (match_operand:SI 3 "register_operand" ""))])]
3284 (define_insn "mul_r"
3285 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3286 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3287 (match_operand:SI 2 "arith_reg_operand" "z")))]
3290 [(set_attr "type" "dmpy")])
3292 (define_insn "mul_l"
3293 [(set (reg:SI MACL_REG)
3294 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3295 (match_operand:SI 1 "arith_reg_operand" "r")))]
3298 [(set_attr "type" "dmpy")])
3300 (define_expand "mulsi3"
3301 [(set (reg:SI MACL_REG)
3302 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3303 (match_operand:SI 2 "arith_reg_operand" "")))
3304 (set (match_operand:SI 0 "arith_reg_operand" "")
3310 /* The address must be set outside the libcall,
3311 since it goes into a pseudo. */
3312 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3313 rtx addr = force_reg (SImode, sym);
3314 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3320 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3322 emit_insn (gen_mul_l (operands[1], operands[2]));
3323 /* consec_sets_giv can only recognize the first insn that sets a
3324 giv as the giv insn. So we must tag this also with a REG_EQUAL
3326 emit_insn (gen_movsi_i ((operands[0]), macl));
3331 (define_insn "mulsidi3_i"
3332 [(set (reg:SI MACH_REG)
3336 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3337 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3339 (set (reg:SI MACL_REG)
3340 (mult:SI (match_dup 0)
3344 [(set_attr "type" "dmpy")])
3346 (define_expand "mulsidi3"
3347 [(set (match_operand:DI 0 "arith_reg_dest" "")
3348 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3349 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3350 "TARGET_SH2 || TARGET_SHMEDIA"
3354 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3359 (define_insn "mulsidi3_media"
3360 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3361 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3362 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3365 [(set_attr "type" "dmpy_media")
3366 (set_attr "highpart" "ignore")])
3368 (define_insn_and_split "mulsidi3_compact"
3369 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3371 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3372 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3373 (clobber (reg:SI MACH_REG))
3374 (clobber (reg:SI MACL_REG))]
3380 rtx low_dst = gen_lowpart (SImode, operands[0]);
3381 rtx high_dst = gen_highpart (SImode, operands[0]);
3383 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3385 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3386 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3387 /* We need something to tag the possible REG_EQUAL notes on to. */
3388 emit_move_insn (operands[0], operands[0]);
3392 (define_insn "umulsidi3_i"
3393 [(set (reg:SI MACH_REG)
3397 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3398 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3400 (set (reg:SI MACL_REG)
3401 (mult:SI (match_dup 0)
3405 [(set_attr "type" "dmpy")])
3407 (define_expand "umulsidi3"
3408 [(set (match_operand:DI 0 "arith_reg_dest" "")
3409 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3410 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3411 "TARGET_SH2 || TARGET_SHMEDIA"
3415 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3420 (define_insn "umulsidi3_media"
3421 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3422 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3423 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3426 [(set_attr "type" "dmpy_media")
3427 (set_attr "highpart" "ignore")])
3429 (define_insn_and_split "umulsidi3_compact"
3430 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3432 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3433 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3434 (clobber (reg:SI MACH_REG))
3435 (clobber (reg:SI MACL_REG))]
3441 rtx low_dst = gen_lowpart (SImode, operands[0]);
3442 rtx high_dst = gen_highpart (SImode, operands[0]);
3444 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3446 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3447 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3448 /* We need something to tag the possible REG_EQUAL notes on to. */
3449 emit_move_insn (operands[0], operands[0]);
3453 (define_insn "smulsi3_highpart_i"
3454 [(set (reg:SI MACH_REG)
3458 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3459 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3461 (clobber (reg:SI MACL_REG))]
3464 [(set_attr "type" "dmpy")])
3466 (define_expand "smulsi3_highpart"
3468 [(set (reg:SI MACH_REG)
3472 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3473 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3475 (clobber (reg:SI MACL_REG))])
3476 (set (match_operand:SI 0 "arith_reg_operand" "")
3482 mach = gen_rtx_REG (SImode, MACH_REG);
3484 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3485 insn = get_insns ();
3487 /* expand_binop can't find a suitable code in mul_highpart_optab to
3488 make a REG_EQUAL note from, so make one here.
3489 See also {,u}mulhisi.
3490 ??? Alternatively, we could put this at the calling site of expand_binop,
3491 i.e. expand_mult_highpart. */
3492 /* Use emit_libcall_block for loop invariant code motion and to make
3493 a REG_EQUAL note. */
3494 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3499 (define_insn "umulsi3_highpart_i"
3500 [(set (reg:SI MACH_REG)
3504 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3505 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3507 (clobber (reg:SI MACL_REG))]
3510 [(set_attr "type" "dmpy")])
3512 (define_expand "umulsi3_highpart"
3514 [(set (reg:SI MACH_REG)
3518 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3519 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3521 (clobber (reg:SI MACL_REG))])
3522 (set (match_operand:SI 0 "arith_reg_operand" "")
3528 mach = gen_rtx_REG (SImode, MACH_REG);
3530 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3531 insn = get_insns ();
3533 /* Use emit_libcall_block for loop invariant code motion and to make
3534 a REG_EQUAL note. */
3535 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3540 (define_insn_and_split "muldi3"
3541 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3542 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3543 (match_operand:DI 2 "arith_reg_operand" "r")))
3544 (clobber (match_scratch:DI 3 "=&r"))
3545 (clobber (match_scratch:DI 4 "=r"))]
3551 rtx op3_v2si, op2_v2si;
3553 op3_v2si = operands[3];
3554 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3556 op3_v2si = XEXP (op3_v2si, 0);
3557 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3559 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3560 op2_v2si = operands[2];
3561 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3563 op2_v2si = XEXP (op2_v2si, 0);
3564 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3566 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3567 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3568 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3569 emit_insn (gen_umulsidi3_media (operands[4],
3570 sh_gen_truncate (SImode, operands[1], 0),
3571 sh_gen_truncate (SImode, operands[2], 0)));
3572 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3573 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3574 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3575 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3579 ;; -------------------------------------------------------------------------
3580 ;; Logical operations
3581 ;; -------------------------------------------------------------------------
3583 (define_expand "andsi3"
3584 [(set (match_operand:SI 0 "arith_reg_operand" "")
3585 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3586 (match_operand:SI 2 "logical_and_operand" "")))]
3589 /* If it is possible to turn the and insn into a zero extension
3590 already, redundant zero extensions will be folded, which results
3592 Ideally the splitter of *andsi_compact would be enough, if redundant
3593 zero extensions were detected after the combine pass, which does not
3594 happen at the moment. */
3597 if (satisfies_constraint_Jmb (operands[2]))
3599 emit_insn (gen_zero_extendqisi2 (operands[0],
3600 gen_lowpart (QImode, operands[1])));
3603 else if (satisfies_constraint_Jmw (operands[2]))
3605 emit_insn (gen_zero_extendhisi2 (operands[0],
3606 gen_lowpart (HImode, operands[1])));
3612 (define_insn_and_split "*andsi_compact"
3613 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3614 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3615 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3623 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3625 if (satisfies_constraint_Jmb (operands[2]))
3626 operands[1] = gen_lowpart (QImode, operands[1]);
3627 else if (satisfies_constraint_Jmw (operands[2]))
3628 operands[1] = gen_lowpart (HImode, operands[1]);
3632 [(set_attr "type" "arith")])
3634 (define_insn "*andsi3_media"
3635 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3636 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3637 (match_operand:SI 2 "logical_operand" "r,I10")))]
3642 [(set_attr "type" "arith_media")])
3644 (define_insn "*andsi3_bclr"
3645 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3646 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3647 (match_operand:SI 2 "const_int_operand" "Psz")))]
3648 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3650 [(set_attr "type" "arith")])
3652 (define_insn_and_split "anddi3"
3653 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3654 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3655 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3662 && ! logical_operand (operands[2], DImode)"
3665 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3666 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3668 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3671 [(set_attr "type" "arith_media")])
3673 (define_insn "andcsi3"
3674 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3675 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3676 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3679 [(set_attr "type" "arith_media")])
3681 (define_insn "andcdi3"
3682 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3683 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3684 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3687 [(set_attr "type" "arith_media")])
3689 (define_expand "iorsi3"
3690 [(set (match_operand:SI 0 "arith_reg_operand" "")
3691 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3692 (match_operand:SI 2 "logical_operand" "")))]
3696 (define_insn "*iorsi3_compact"
3697 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3698 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3699 (match_operand:SI 2 "logical_operand" "r,K08")))]
3701 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3703 [(set_attr "type" "arith")])
3705 (define_insn "*iorsi3_media"
3706 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3707 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3708 (match_operand:SI 2 "logical_operand" "r,I10")))]
3713 [(set_attr "type" "arith_media")])
3715 (define_insn "*iorsi3_bset"
3716 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3717 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3718 (match_operand:SI 2 "const_int_operand" "Pso")))]
3719 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3721 [(set_attr "type" "arith")])
3723 (define_insn "iordi3"
3724 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3725 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3726 (match_operand:DI 2 "logical_operand" "r,I10")))]
3731 [(set_attr "type" "arith_media")])
3733 (define_insn_and_split "*logical_sidi3"
3734 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3735 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3736 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3737 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3740 "&& reload_completed"
3741 [(set (match_dup 0) (match_dup 3))]
3744 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3745 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3746 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3749 (define_insn_and_split "*logical_sidisi3"
3750 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3751 (truncate:SI (sign_extend:DI
3752 (match_operator:SI 3 "logical_operator"
3753 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3754 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3758 [(set (match_dup 0) (match_dup 3))])
3760 (define_insn_and_split "*logical_sidi3_2"
3761 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3762 (sign_extend:DI (truncate:SI (sign_extend:DI
3763 (match_operator:SI 3 "logical_operator"
3764 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3765 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3769 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3771 (define_expand "xorsi3"
3772 [(set (match_operand:SI 0 "arith_reg_operand" "")
3773 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3774 (match_operand:SI 2 "xor_operand" "")))]
3778 (define_insn "*xorsi3_compact"
3779 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3780 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3781 (match_operand:SI 2 "logical_operand" "K08,r")))]
3784 [(set_attr "type" "arith")])
3786 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
3787 ;; of results where one of the inputs is a T bit store. Notice that this
3788 ;; pattern must not match during reload. If reload picks this pattern it
3789 ;; will be impossible to split it afterwards.
3790 (define_insn_and_split "*logical_op_t"
3791 [(set (match_operand:SI 0 "arith_reg_dest")
3792 (match_operator:SI 3 "logical_operator"
3793 [(match_operand:SI 1 "arith_reg_operand")
3794 (match_operand:SI 2 "t_reg_operand")]))]
3795 "TARGET_SH1 && can_create_pseudo_p ()"
3798 [(set (match_dup 4) (reg:SI T_REG))
3799 (set (match_dup 0) (match_dup 3))]
3801 operands[4] = gen_reg_rtx (SImode);
3802 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3803 operands[1], operands[4]);
3806 (define_insn "*xorsi3_media"
3807 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3808 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3809 (match_operand:SI 2 "xor_operand" "r,I06")))]
3814 [(set_attr "type" "arith_media")])
3816 (define_insn "xordi3"
3817 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3818 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3819 (match_operand:DI 2 "xor_operand" "r,I06")))]
3824 [(set_attr "type" "arith_media")])
3826 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3827 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3829 [(set (match_operand:DI 0 "arith_reg_dest" "")
3830 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3831 [(match_operand 1 "any_register_operand" "")
3832 (match_operand 2 "any_register_operand" "")])))]
3834 [(set (match_dup 5) (match_dup 4))
3835 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3837 enum machine_mode inmode = GET_MODE (operands[1]);
3840 if (GET_CODE (operands[0]) == SUBREG)
3842 offset = SUBREG_BYTE (operands[0]);
3843 operands[0] = SUBREG_REG (operands[0]);
3845 gcc_assert (REG_P (operands[0]));
3846 if (! TARGET_LITTLE_ENDIAN)
3847 offset += 8 - GET_MODE_SIZE (inmode);
3848 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3851 ;; -------------------------------------------------------------------------
3852 ;; Shifts and rotates
3853 ;; -------------------------------------------------------------------------
3855 (define_expand "rotldi3"
3856 [(set (match_operand:DI 0 "arith_reg_dest" "")
3857 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
3858 (match_operand:HI 2 "mextr_bit_offset" "")))]
3861 if (! mextr_bit_offset (operands[2], HImode))
3865 (define_insn "rotldi3_mextr"
3866 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3867 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
3868 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3871 static char templ[16];
3872 sprintf (templ, "mextr%d %%1,%%1,%%0",
3873 8 - (int) (INTVAL (operands[2]) >> 3));
3876 [(set_attr "type" "arith_media")])
3878 (define_expand "rotrdi3"
3879 [(set (match_operand:DI 0 "arith_reg_dest" "")
3880 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
3881 (match_operand:HI 2 "mextr_bit_offset" "")))]
3884 if (! mextr_bit_offset (operands[2], HImode))
3888 (define_insn "rotrdi3_mextr"
3889 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3890 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
3891 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3894 static char templ[16];
3895 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
3898 [(set_attr "type" "arith_media")])
3901 [(set (match_operand:DI 0 "arith_reg_dest" "")
3902 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
3903 "ua_address_operand" "")))
3904 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
3906 (clobber (match_operand:DI 3 "register_operand" ""))]
3908 [(match_dup 4) (match_dup 5)]
3910 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
3911 (operands[3], operands[1]));
3912 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
3913 GEN_INT (56), GEN_INT (8));
3916 (define_expand "rotrsi3"
3917 [(set (match_operand:SI 0 "arith_reg_dest")
3918 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
3919 (match_operand:SI 2 "const_int_operand")))]
3922 HOST_WIDE_INT ival = INTVAL (operands[2]);
3925 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
3932 (define_insn "rotrsi3_1"
3933 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3934 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
3937 (and:SI (match_dup 1) (const_int 1)))]
3940 [(set_attr "type" "arith")])
3942 ;; A slimplified version of rotr for combine.
3943 (define_insn "*rotrsi3_1"
3944 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3945 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
3947 (clobber (reg:SI T_REG))]
3950 [(set_attr "type" "arith")])
3952 (define_insn "rotlsi3_1"
3953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3954 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
3957 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3960 [(set_attr "type" "arith")])
3962 ;; A simplified version of rotl for combine.
3963 (define_insn "*rotlsi3_1"
3964 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3965 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
3967 (clobber (reg:SI T_REG))]
3970 [(set_attr "type" "arith")])
3972 (define_insn "rotlsi3_31"
3973 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3974 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
3976 (clobber (reg:SI T_REG))]
3979 [(set_attr "type" "arith")])
3981 (define_insn "rotlsi3_16"
3982 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3983 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
3987 [(set_attr "type" "arith")])
3989 (define_expand "rotlsi3"
3990 [(set (match_operand:SI 0 "arith_reg_dest")
3991 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
3992 (match_operand:SI 2 "const_int_operand")))]
3995 static const char rot_tab[] = {
3996 000, 000, 000, 000, 000, 000, 010, 001,
3997 001, 001, 011, 013, 003, 003, 003, 003,
3998 003, 003, 003, 003, 003, 013, 012, 002,
3999 002, 002, 010, 000, 000, 000, 000, 000,
4002 int count = INTVAL (operands[2]);
4003 int choice = rot_tab[count];
4004 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4010 emit_move_insn (operands[0], operands[1]);
4011 count -= (count & 16) * 2;
4014 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4021 parts[0] = gen_reg_rtx (SImode);
4022 parts[1] = gen_reg_rtx (SImode);
4023 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4024 emit_move_insn (parts[choice-1], operands[1]);
4025 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4026 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4027 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4028 count = (count & ~16) - 8;
4032 for (; count > 0; count--)
4033 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4034 for (; count < 0; count++)
4035 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4040 (define_insn "*rotlhi3_8"
4041 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4042 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4046 [(set_attr "type" "arith")])
4048 (define_expand "rotlhi3"
4049 [(set (match_operand:HI 0 "arith_reg_operand")
4050 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4051 (match_operand:HI 2 "const_int_operand")))]
4054 if (INTVAL (operands[2]) != 8)
4058 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4059 ;; They can also be used to implement things like
4061 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4062 ;; int x1 = (y << 1) | t; // rotcl
4063 (define_insn "rotcr"
4064 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4065 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4067 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4070 (and:SI (match_dup 1) (const_int 1)))]
4073 [(set_attr "type" "arith")])
4075 (define_insn "rotcl"
4076 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4077 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4079 (match_operand:SI 2 "t_reg_operand")))
4081 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4084 [(set_attr "type" "arith")])
4086 ;; Simplified rotcr version for combine, which allows arbitrary shift
4087 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4088 ;; directly. Otherwise we have to insert a shift in between.
4089 (define_insn_and_split "*rotcr"
4090 [(set (match_operand:SI 0 "arith_reg_dest")
4091 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4092 (match_operand:SI 2 "const_int_operand"))
4093 (ashift:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4095 (clobber (reg:SI T_REG))]
4098 "&& can_create_pseudo_p ()"
4101 if (INTVAL (operands[2]) > 1)
4103 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4104 rtx prev_set_t_insn = NULL_RTX;
4105 rtx tmp_t_reg = NULL_RTX;
4107 /* If we're going to emit a shift sequence that clobbers the T_REG,
4108 try to find the previous insn that sets the T_REG and emit the
4109 shift insn before that insn, to remove the T_REG dependency.
4110 If the insn that sets the T_REG cannot be found, store the T_REG
4111 in a temporary reg and restore it after the shift. */
4112 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4113 && ! sh_dynamicalize_shift_p (shift_count))
4115 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4117 /* Skip the nott insn, which was probably inserted by the splitter
4118 of *rotcr_neg_t. Don't use one of the recog functions
4119 here during insn splitting, since that causes problems in later
4121 if (prev_set_t_insn != NULL_RTX)
4123 rtx pat = PATTERN (prev_set_t_insn);
4124 if (GET_CODE (pat) == SET
4125 && t_reg_operand (XEXP (pat, 0), SImode)
4126 && negt_reg_operand (XEXP (pat, 1), SImode))
4127 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4130 if (! (prev_set_t_insn != NULL_RTX
4131 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4132 && ! reg_referenced_p (get_t_reg_rtx (),
4133 PATTERN (prev_set_t_insn))))
4135 prev_set_t_insn = NULL_RTX;
4136 tmp_t_reg = gen_reg_rtx (SImode);
4137 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4141 rtx shift_result = gen_reg_rtx (SImode);
4142 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4143 operands[1] = shift_result;
4145 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4146 if (prev_set_t_insn != NULL_RTX)
4147 emit_insn_before (shift_insn, prev_set_t_insn);
4149 emit_insn (shift_insn);
4151 /* Restore T_REG if it has been saved before. */
4152 if (tmp_t_reg != NULL_RTX)
4153 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4156 /* For the rotcr insn to work, operands[3] must be in T_REG.
4157 If it is not we can get it there by shifting it right one bit.
4158 In this case T_REG is not an input for this insn, thus we don't have to
4159 pay attention as of where to insert the shlr insn. */
4160 if (! t_reg_operand (operands[3], SImode))
4162 /* We don't care about the shifted result here, only the T_REG. */
4163 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4164 operands[3] = get_t_reg_rtx ();
4167 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4171 ;; If combine tries the same as above but with swapped operands, split
4172 ;; it so that it will try the pattern above.
4174 [(set (match_operand:SI 0 "arith_reg_dest")
4175 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4177 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4178 (match_operand:SI 3 "const_int_operand"))))]
4179 "TARGET_SH1 && can_create_pseudo_p ()"
4180 [(parallel [(set (match_dup 0)
4181 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4182 (ashift:SI (match_dup 1) (const_int 31))))
4183 (clobber (reg:SI T_REG))])])
4185 ;; Basically the same as the rotcr pattern above, but for rotcl.
4186 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4187 (define_insn_and_split "*rotcl"
4188 [(set (match_operand:SI 0 "arith_reg_dest")
4189 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4190 (match_operand:SI 2 "const_int_operand"))
4191 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4193 (clobber (reg:SI T_REG))]
4196 "&& can_create_pseudo_p ()"
4199 gcc_assert (INTVAL (operands[2]) > 0);
4201 if (INTVAL (operands[2]) > 1)
4203 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4204 rtx prev_set_t_insn = NULL_RTX;
4205 rtx tmp_t_reg = NULL_RTX;
4207 /* If we're going to emit a shift sequence that clobbers the T_REG,
4208 try to find the previous insn that sets the T_REG and emit the
4209 shift insn before that insn, to remove the T_REG dependency.
4210 If the insn that sets the T_REG cannot be found, store the T_REG
4211 in a temporary reg and restore it after the shift. */
4212 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4213 && ! sh_dynamicalize_shift_p (shift_count))
4215 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4217 /* Skip the nott insn, which was probably inserted by the splitter
4218 of *rotcl_neg_t. Don't use one of the recog functions
4219 here during insn splitting, since that causes problems in later
4221 if (prev_set_t_insn != NULL_RTX)
4223 rtx pat = PATTERN (prev_set_t_insn);
4224 if (GET_CODE (pat) == SET
4225 && t_reg_operand (XEXP (pat, 0), SImode)
4226 && negt_reg_operand (XEXP (pat, 1), SImode))
4227 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4230 if (! (prev_set_t_insn != NULL_RTX
4231 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4232 && ! reg_referenced_p (get_t_reg_rtx (),
4233 PATTERN (prev_set_t_insn))))
4235 prev_set_t_insn = NULL_RTX;
4236 tmp_t_reg = gen_reg_rtx (SImode);
4237 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4241 rtx shift_result = gen_reg_rtx (SImode);
4242 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4243 operands[1] = shift_result;
4245 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4246 if (prev_set_t_insn != NULL_RTX)
4247 emit_insn_before (shift_insn, prev_set_t_insn);
4249 emit_insn (shift_insn);
4251 /* Restore T_REG if it has been saved before. */
4252 if (tmp_t_reg != NULL_RTX)
4253 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4256 /* For the rotcl insn to work, operands[3] must be in T_REG.
4257 If it is not we can get it there by shifting it right one bit.
4258 In this case T_REG is not an input for this insn, thus we don't have to
4259 pay attention as of where to insert the shlr insn. */
4260 if (! t_reg_operand (operands[3], SImode))
4262 /* We don't care about the shifted result here, only the T_REG. */
4263 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4264 operands[3] = get_t_reg_rtx ();
4267 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4271 ;; rotcl combine pattern variations
4272 (define_insn_and_split "*rotcl"
4273 [(set (match_operand:SI 0 "arith_reg_dest")
4274 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4275 (match_operand:SI 2 "const_int_operand"))
4276 (match_operand:SI 3 "t_reg_operand")))
4277 (clobber (reg:SI T_REG))]
4280 "&& can_create_pseudo_p ()"
4281 [(parallel [(set (match_dup 0)
4282 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4283 (and:SI (match_dup 3) (const_int 1))))
4284 (clobber (reg:SI T_REG))])])
4286 (define_insn_and_split "*rotcl"
4287 [(set (match_operand:SI 0 "arith_reg_dest")
4288 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4290 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4291 (match_operand:SI 3 "const_int_operand"))))
4292 (clobber (reg:SI T_REG))]
4295 "&& can_create_pseudo_p ()"
4296 [(parallel [(set (match_dup 0)
4297 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4298 (and:SI (match_dup 1) (const_int 1))))
4299 (clobber (reg:SI T_REG))])])
4301 (define_insn_and_split "*rotcl"
4302 [(set (match_operand:SI 0 "arith_reg_dest")
4303 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4304 (match_operand:SI 2 "const_int_operand"))
4305 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4307 (clobber (reg:SI T_REG))]
4310 "&& can_create_pseudo_p ()"
4311 [(parallel [(set (match_dup 0)
4312 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4313 (and:SI (reg:SI T_REG) (const_int 1))))
4314 (clobber (reg:SI T_REG))])]
4316 /* We don't care about the result of the left shift, only the T_REG. */
4317 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4320 (define_insn_and_split "*rotcl"
4321 [(set (match_operand:SI 0 "arith_reg_dest")
4322 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4324 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4325 (match_operand:SI 2 "const_int_operand"))))
4326 (clobber (reg:SI T_REG))]
4329 "&& can_create_pseudo_p ()"
4330 [(parallel [(set (match_dup 0)
4331 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4332 (and:SI (reg:SI T_REG) (const_int 1))))
4333 (clobber (reg:SI T_REG))])]
4335 /* We don't care about the result of the left shift, only the T_REG. */
4336 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4339 ;; rotcr combine bridge pattern which will make combine try out more
4340 ;; complex patterns.
4341 (define_insn_and_split "*rotcr"
4342 [(set (match_operand:SI 0 "arith_reg_dest")
4343 (ashift:SI (match_operand:SI 1 "t_reg_operand") (const_int 31)))]
4347 [(set (match_dup 0) (match_dup 1))
4348 (parallel [(set (match_dup 0)
4349 (ior:SI (lshiftrt:SI (match_dup 0) (const_int 1))
4350 (ashift:SI (match_dup 1) (const_int 31))))
4352 (and:SI (match_dup 0) (const_int 1)))])])
4354 (define_insn_and_split "*rotcr"
4355 [(set (match_operand:SI 0 "arith_reg_dest")
4356 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4357 (const_int -2147483648)) ;; 0xffffffff80000000
4358 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4360 (clobber (reg:SI T_REG))]
4363 "&& can_create_pseudo_p ()"
4366 rtx tmp = gen_reg_rtx (SImode);
4367 emit_insn (gen_shll (tmp, operands[1]));
4368 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4372 ;; rotcr combine patterns for rotating in the negated T_REG value.
4373 (define_insn_and_split "*rotcr_neg_t"
4374 [(set (match_operand:SI 0 "arith_reg_dest")
4375 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4376 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4377 (match_operand:SI 3 "const_int_operand"))))
4378 (clobber (reg:SI T_REG))]
4381 "&& can_create_pseudo_p ()"
4382 [(parallel [(set (match_dup 0)
4383 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4384 (ashift:SI (reg:SI T_REG) (const_int 31))))
4385 (clobber (reg:SI T_REG))])]
4387 emit_insn (gen_nott (get_t_reg_rtx ()));
4390 (define_insn_and_split "*rotcr_neg_t"
4391 [(set (match_operand:SI 0 "arith_reg_dest")
4392 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4393 (match_operand:SI 2 "const_int_operand"))
4394 (match_operand:SI 3 "negt_reg_shl31_operand")))
4395 (clobber (reg:SI T_REG))]
4398 "&& can_create_pseudo_p ()"
4399 [(parallel [(set (match_dup 0)
4400 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4401 (ashift:SI (reg:SI T_REG) (const_int 31))))
4402 (clobber (reg:SI T_REG))])]
4404 emit_insn (gen_nott (get_t_reg_rtx ()));
4407 ;; rotcl combine patterns for rotating in the negated T_REG value.
4408 ;; For some strange reason these have to be specified as splits which combine
4409 ;; will pick up. If they are specified as insn_and_split like the
4410 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4411 ;; but not emit them on non-SH2A targets.
4413 [(set (match_operand:SI 0 "arith_reg_dest")
4414 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4415 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4416 (match_operand:SI 3 "const_int_operand"))))]
4418 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4419 (parallel [(set (match_dup 0)
4420 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4421 (and:SI (reg:SI T_REG) (const_int 1))))
4422 (clobber (reg:SI T_REG))])])
4425 [(set (match_operand:SI 0 "arith_reg_dest")
4426 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4427 (match_operand:SI 3 "const_int_operand"))
4428 (match_operand:SI 1 "negt_reg_operand")))]
4430 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4431 (parallel [(set (match_dup 0)
4432 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4433 (and:SI (reg:SI T_REG) (const_int 1))))
4434 (clobber (reg:SI T_REG))])])
4436 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4437 ;; SImode shift left
4439 (define_expand "ashlsi3"
4440 [(set (match_operand:SI 0 "arith_reg_operand" "")
4441 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4442 (match_operand:SI 2 "shift_count_operand" "")))]
4447 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4451 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4452 operands[2] = force_reg (SImode, operands[2]);
4454 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4456 if (CONST_INT_P (operands[2])
4457 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4458 && ! sh_dynamicalize_shift_p (operands[2]))
4460 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4465 /* Expand a library call for the dynamic shift. */
4466 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4468 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4469 rtx funcaddr = gen_reg_rtx (Pmode);
4470 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4471 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4477 (define_insn "ashlsi3_k"
4478 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4479 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4480 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4485 [(set_attr "type" "arith")])
4487 (define_insn_and_split "ashlsi3_d"
4488 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4489 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4490 (match_operand:SI 2 "shift_count_operand" "r")))]
4493 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4494 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4497 if (satisfies_constraint_P27 (operands[2]))
4499 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4502 else if (! satisfies_constraint_P27 (operands[2]))
4504 /* This must happen before reload, otherwise the constant will be moved
4505 into a register due to the "r" constraint, after which this split
4506 cannot be done anymore.
4507 Unfortunately the move insn will not always be eliminated.
4508 Also, here we must not create a shift sequence that clobbers the
4510 emit_move_insn (operands[0], operands[1]);
4511 gen_shifty_op (ASHIFT, operands);
4517 [(set_attr "type" "dyn_shift")])
4519 ;; If dynamic shifts are not available use a library function.
4520 ;; By specifying the pattern we reduce the number of call clobbered regs.
4521 ;; In order to make combine understand the truncation of the shift amount
4522 ;; operand we have to allow it to use pseudo regs for the shift operands.
4523 (define_insn "ashlsi3_d_call"
4524 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4525 (ashift:SI (reg:SI R4_REG)
4526 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4528 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4529 (clobber (reg:SI T_REG))
4530 (clobber (reg:SI PR_REG))]
4531 "TARGET_SH1 && !TARGET_DYNSHIFT"
4533 [(set_attr "type" "sfunc")
4534 (set_attr "needs_delay_slot" "yes")])
4536 (define_insn_and_split "ashlsi3_n"
4537 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4538 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4539 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4540 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4542 "&& (reload_completed
4543 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4546 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4548 /* If this pattern was picked and dynamic shifts are supported, switch
4549 to dynamic shift pattern before reload. */
4550 operands[2] = force_reg (SImode, operands[2]);
4551 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4554 gen_shifty_op (ASHIFT, operands);
4559 (define_insn_and_split "ashlsi3_n_clobbers_t"
4560 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4561 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4562 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
4563 (clobber (reg:SI T_REG))]
4564 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
4566 "&& (reload_completed || INTVAL (operands[2]) == 31
4567 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4570 if (INTVAL (operands[2]) == 31)
4572 /* If the shift amount is 31 we split into a different sequence before
4573 reload so that it gets a chance to allocate R0 for the sequence.
4574 If it fails to do so (due to pressure on R0), it will take one insn
4575 more for the and. */
4576 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
4577 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4579 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4581 /* If this pattern was picked and dynamic shifts are supported, switch
4582 to dynamic shift pattern before reload. */
4583 operands[2] = force_reg (SImode, operands[2]);
4584 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4587 gen_shifty_op (ASHIFT, operands);
4593 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4594 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
4596 (lt:SI (match_dup 1) (const_int 0)))]
4599 [(set_attr "type" "arith")])
4601 (define_insn "*ashlsi_c_void"
4602 [(set (reg:SI T_REG)
4603 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
4604 (clobber (match_scratch:SI 1 "=0"))]
4605 "TARGET_SH1 && cse_not_expected"
4607 [(set_attr "type" "arith")])
4610 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
4612 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
4614 && peep2_reg_dead_p (2, operands[0])
4615 && peep2_reg_dead_p (2, operands[1])"
4618 emit_insn (gen_shll (operands[1], operands[1]));
4622 (define_insn "ashlsi3_media"
4623 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4624 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4625 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4630 [(set_attr "type" "arith_media")
4631 (set_attr "highpart" "ignore")])
4633 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4634 ;; HImode shift left
4636 (define_expand "ashlhi3"
4637 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
4638 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
4639 (match_operand:SI 2 "nonmemory_operand" "")))
4640 (clobber (reg:SI T_REG))])]
4643 if (!CONST_INT_P (operands[2]))
4645 /* It may be possible to call gen_ashlhi3 directly with more generic
4646 operands. Make sure operands[1] is a HImode register here. */
4647 if (!arith_reg_operand (operands[1], HImode))
4648 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4651 (define_insn "ashlhi3_k"
4652 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
4653 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
4654 (match_operand:HI 2 "const_int_operand" "M,P27")))]
4655 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
4659 [(set_attr "type" "arith")])
4661 (define_insn_and_split "*ashlhi3_n"
4662 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4663 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
4664 (match_operand:HI 2 "const_int_operand" "n")))
4665 (clobber (reg:SI T_REG))]
4668 "&& reload_completed"
4669 [(use (reg:SI R0_REG))]
4671 gen_shifty_hi_op (ASHIFT, operands);
4675 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4676 ;; DImode shift left
4678 (define_expand "ashldi3"
4679 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4680 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4681 (match_operand:DI 2 "immediate_operand" "")))
4682 (clobber (reg:SI T_REG))])]
4687 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4690 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
4692 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4695 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
4697 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4704 ;; Expander for DImode shift left with SImode operations.
4705 (define_expand "ashldi3_std"
4706 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4707 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4708 (match_operand:DI 2 "const_int_operand" "n")))]
4709 "TARGET_SH1 && INTVAL (operands[2]) < 32"
4711 rtx low_src = gen_lowpart (SImode, operands[1]);
4712 rtx high_src = gen_highpart (SImode, operands[1]);
4713 rtx dst = gen_reg_rtx (DImode);
4714 rtx low_dst = gen_lowpart (SImode, dst);
4715 rtx high_dst = gen_highpart (SImode, dst);
4716 rtx tmp0 = gen_reg_rtx (SImode);
4717 rtx tmp1 = gen_reg_rtx (SImode);
4719 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
4720 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
4721 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
4722 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
4723 emit_move_insn (operands[0], dst);
4727 (define_insn_and_split "ashldi3_k"
4728 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4729 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
4731 (clobber (reg:SI T_REG))]
4734 "&& reload_completed"
4737 rtx high = gen_highpart (SImode, operands[0]);
4738 rtx low = gen_lowpart (SImode, operands[0]);
4739 emit_insn (gen_shll (low, low));
4740 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
4744 (define_insn "ashldi3_media"
4745 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4746 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4747 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4752 [(set_attr "type" "arith_media")])
4754 (define_insn "*ashldisi3_media"
4755 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4756 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4757 (match_operand:DI 2 "const_int_operand" "n")))]
4758 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4759 "shlli.l %1, %2, %0"
4760 [(set_attr "type" "arith_media")
4761 (set_attr "highpart" "ignore")])
4763 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4764 ;; SImode arithmetic shift right
4766 ;; We can't do HImode right shifts correctly unless we start out with an
4767 ;; explicit zero / sign extension; doing that would result in worse overall
4768 ;; code, so just let the machine independent code widen the mode.
4769 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
4771 (define_expand "ashrsi3"
4772 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4773 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4774 (match_operand:SI 2 "nonmemory_operand" "")))
4775 (clobber (reg:SI T_REG))])]
4780 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4783 if (expand_ashiftrt (operands))
4790 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4791 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4794 (and:SI (match_dup 1) (const_int 1)))]
4797 [(set_attr "type" "arith")])
4799 (define_insn "ashrsi3_k"
4800 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4801 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4802 (match_operand:SI 2 "const_int_operand" "M")))
4803 (clobber (reg:SI T_REG))]
4804 "TARGET_SH1 && INTVAL (operands[2]) == 1"
4806 [(set_attr "type" "arith")])
4808 (define_insn_and_split "ashrsi2_16"
4809 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4810 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
4815 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
4816 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
4818 operands[2] = gen_lowpart (HImode, operands[0]);
4821 (define_insn_and_split "ashrsi2_31"
4822 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4823 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4825 (clobber (reg:SI T_REG))]
4831 emit_insn (gen_shll (operands[0], operands[1]));
4832 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
4836 (define_insn "ashrsi3_d"
4837 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4838 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4839 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4842 [(set_attr "type" "dyn_shift")])
4844 (define_insn "ashrsi3_n"
4845 [(set (reg:SI R4_REG)
4846 (ashiftrt:SI (reg:SI R4_REG)
4847 (match_operand:SI 0 "const_int_operand" "i")))
4848 (clobber (reg:SI T_REG))
4849 (clobber (reg:SI PR_REG))
4850 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
4853 [(set_attr "type" "sfunc")
4854 (set_attr "needs_delay_slot" "yes")])
4856 (define_insn "ashrsi3_media"
4857 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4858 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4859 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4864 [(set_attr "type" "arith_media")
4865 (set_attr "highpart" "ignore")])
4867 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4868 ;; DImode arithmetic shift right
4870 (define_expand "ashrdi3"
4871 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4872 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4873 (match_operand:DI 2 "immediate_operand" "")))
4874 (clobber (reg:SI T_REG))])]
4879 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
4882 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4886 (define_insn_and_split "ashrdi3_k"
4887 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4888 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4890 (clobber (reg:SI T_REG))]
4893 "&& reload_completed"
4896 rtx high = gen_highpart (SImode, operands[0]);
4897 rtx low = gen_lowpart (SImode, operands[0]);
4898 emit_insn (gen_shar (high, high));
4899 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4903 (define_insn "ashrdi3_media"
4904 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
4905 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4906 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4908 && (arith_reg_dest (operands[0], DImode)
4909 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
4913 [(set_attr "type" "arith_media")])
4915 (define_insn "*ashrdisi3_media"
4916 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4917 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
4918 (match_operand:DI 2 "const_int_operand" "n")))]
4919 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4920 "shari.l %1, %2, %0"
4921 [(set_attr "type" "arith_media")
4922 (set_attr "highpart" "ignore")])
4924 (define_insn "ashrdisi3_media_high"
4925 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4927 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
4928 (match_operand:DI 2 "const_int_operand" "n"))))]
4929 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
4931 [(set_attr "type" "arith_media")])
4933 (define_insn "ashrdisi3_media_opaque"
4934 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4935 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
4936 (match_operand:DI 2 "const_int_operand" "n")]
4940 [(set_attr "type" "arith_media")])
4942 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4943 ;; SImode logical shift right
4945 (define_expand "lshrsi3"
4946 [(set (match_operand:SI 0 "arith_reg_dest" "")
4947 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4948 (match_operand:SI 2 "shift_count_operand" "")))]
4953 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
4957 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
4958 here, otherwise the pattern will never match due to the shift amount reg
4961 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4963 rtx neg_count = force_reg (SImode,
4964 gen_int_mode (- INTVAL (operands[2]), SImode));
4965 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
4969 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
4971 rtx neg_count = gen_reg_rtx (SImode);
4972 emit_insn (gen_negsi2 (neg_count, operands[2]));
4973 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
4977 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
4979 if (CONST_INT_P (operands[2])
4980 && sh_lshrsi_clobbers_t_reg_p (operands[2])
4981 && ! sh_dynamicalize_shift_p (operands[2]))
4983 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
4988 /* Expand a library call for the dynamic shift. */
4989 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4991 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4992 rtx funcaddr = gen_reg_rtx (Pmode);
4993 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
4994 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
4999 (define_insn "lshrsi3_k"
5000 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5001 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5002 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5005 [(set_attr "type" "arith")])
5007 (define_insn_and_split "lshrsi3_d"
5008 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5009 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5010 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5013 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5014 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5017 if (satisfies_constraint_P27 (operands[2]))
5019 /* This will not be done for a shift amount of 1, because it would
5020 clobber the T_REG. */
5021 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5024 else if (! satisfies_constraint_P27 (operands[2]))
5026 /* This must happen before reload, otherwise the constant will be moved
5027 into a register due to the "r" constraint, after which this split
5028 cannot be done anymore.
5029 Unfortunately the move insn will not always be eliminated.
5030 Also, here we must not create a shift sequence that clobbers the
5032 emit_move_insn (operands[0], operands[1]);
5033 gen_shifty_op (LSHIFTRT, operands);
5039 [(set_attr "type" "dyn_shift")])
5041 ;; If dynamic shifts are not available use a library function.
5042 ;; By specifying the pattern we reduce the number of call clobbered regs.
5043 ;; In order to make combine understand the truncation of the shift amount
5044 ;; operand we have to allow it to use pseudo regs for the shift operands.
5045 (define_insn "lshrsi3_d_call"
5046 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5047 (lshiftrt:SI (reg:SI R4_REG)
5048 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5050 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5051 (clobber (reg:SI T_REG))
5052 (clobber (reg:SI PR_REG))]
5053 "TARGET_SH1 && !TARGET_DYNSHIFT"
5055 [(set_attr "type" "sfunc")
5056 (set_attr "needs_delay_slot" "yes")])
5058 (define_insn_and_split "lshrsi3_n"
5059 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5060 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5061 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5062 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5064 "&& (reload_completed
5065 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5068 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5070 /* If this pattern was picked and dynamic shifts are supported, switch
5071 to dynamic shift pattern before reload. */
5072 operands[2] = force_reg (SImode,
5073 gen_int_mode (- INTVAL (operands[2]), SImode));
5074 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5077 gen_shifty_op (LSHIFTRT, operands);
5082 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5083 ;; the shlr pattern.
5084 (define_insn_and_split "lshrsi3_n_clobbers_t"
5085 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5086 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5087 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5088 (clobber (reg:SI T_REG))]
5089 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5091 "&& (reload_completed || INTVAL (operands[2]) == 31
5092 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5095 if (INTVAL (operands[2]) == 31)
5097 emit_insn (gen_shll (operands[0], operands[1]));
5098 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5100 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5102 /* If this pattern was picked and dynamic shifts are supported, switch
5103 to dynamic shift pattern before reload. */
5104 operands[2] = force_reg (SImode,
5105 gen_int_mode (- INTVAL (operands[2]), SImode));
5106 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5109 gen_shifty_op (LSHIFTRT, operands);
5115 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5116 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5119 (and:SI (match_dup 1) (const_int 1)))]
5122 [(set_attr "type" "arith")])
5124 (define_insn "lshrsi3_media"
5125 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5126 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5127 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5132 [(set_attr "type" "arith_media")
5133 (set_attr "highpart" "ignore")])
5135 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5136 ;; DImode logical shift right
5138 (define_expand "lshrdi3"
5139 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5140 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5141 (match_operand:DI 2 "immediate_operand" "")))
5142 (clobber (reg:SI T_REG))])]
5147 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5150 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5154 (define_insn_and_split "lshrdi3_k"
5155 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5156 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5158 (clobber (reg:SI T_REG))]
5161 "&& reload_completed"
5164 rtx high = gen_highpart (SImode, operands[0]);
5165 rtx low = gen_lowpart (SImode, operands[0]);
5166 emit_insn (gen_shlr (high, high));
5167 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5171 (define_insn "lshrdi3_media"
5172 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5173 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5174 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5176 && (arith_reg_dest (operands[0], DImode)
5177 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5181 [(set_attr "type" "arith_media")])
5183 (define_insn "*lshrdisi3_media"
5184 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5185 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5186 (match_operand:DI 2 "const_int_operand" "n")))]
5187 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5188 "shlri.l %1, %2, %0"
5189 [(set_attr "type" "arith_media")
5190 (set_attr "highpart" "ignore")])
5192 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5193 ;; Combined left/right shifts
5196 [(set (match_operand:SI 0 "register_operand" "")
5197 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5198 (match_operand:SI 2 "const_int_operand" ""))
5199 (match_operand:SI 3 "const_int_operand" "")))]
5200 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5201 [(use (reg:SI R0_REG))]
5203 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5209 [(set (match_operand:SI 0 "register_operand" "")
5210 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5211 (match_operand:SI 2 "const_int_operand" ""))
5212 (match_operand:SI 3 "const_int_operand" "")))
5213 (clobber (reg:SI T_REG))]
5214 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5215 [(use (reg:SI R0_REG))]
5217 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5223 [(set (match_operand:SI 0 "register_operand" "=r")
5224 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5225 (match_operand:SI 2 "const_int_operand" "n"))
5226 (match_operand:SI 3 "const_int_operand" "n")))
5227 (clobber (reg:SI T_REG))]
5228 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5230 [(set (attr "length")
5231 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5233 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5235 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5237 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5239 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5241 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5243 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5244 (const_string "16")]
5245 (const_string "18")))
5246 (set_attr "type" "arith")])
5249 [(set (match_operand:SI 0 "register_operand" "=z")
5250 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5251 (match_operand:SI 2 "const_int_operand" "n"))
5252 (match_operand:SI 3 "const_int_operand" "n")))
5253 (clobber (reg:SI T_REG))]
5254 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5256 [(set (attr "length")
5257 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5259 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5261 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5263 (const_string "10")))
5264 (set_attr "type" "arith")])
5266 ;; shift left / and combination with a scratch register: The combine pass
5267 ;; does not accept the individual instructions, even though they are
5268 ;; cheap. But it needs a precise description so that it is usable after
5270 (define_insn "and_shl_scratch"
5271 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5275 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5276 (match_operand:SI 2 "const_int_operand" "N,n"))
5277 (match_operand:SI 3 "" "0,r"))
5278 (match_operand:SI 4 "const_int_operand" "n,n"))
5279 (match_operand:SI 5 "const_int_operand" "n,n")))
5280 (clobber (reg:SI T_REG))]
5283 [(set (attr "length")
5284 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5286 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5288 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5290 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5291 (const_string "10")]
5292 (const_string "12")))
5293 (set_attr "type" "arith")])
5296 [(set (match_operand:SI 0 "register_operand" "")
5300 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5301 (match_operand:SI 2 "const_int_operand" ""))
5302 (match_operand:SI 3 "register_operand" ""))
5303 (match_operand:SI 4 "const_int_operand" ""))
5304 (match_operand:SI 5 "const_int_operand" "")))
5305 (clobber (reg:SI T_REG))]
5307 [(use (reg:SI R0_REG))]
5309 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5311 if (INTVAL (operands[2]))
5313 gen_shifty_op (LSHIFTRT, operands);
5315 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5316 operands[2] = operands[4];
5317 gen_shifty_op (ASHIFT, operands);
5318 if (INTVAL (operands[5]))
5320 operands[2] = operands[5];
5321 gen_shifty_op (LSHIFTRT, operands);
5326 ;; signed left/right shift combination.
5328 [(set (match_operand:SI 0 "register_operand" "")
5330 (ashift:SI (match_operand:SI 1 "register_operand" "")
5331 (match_operand:SI 2 "const_int_operand" ""))
5332 (match_operand:SI 3 "const_int_operand" "")
5334 (clobber (reg:SI T_REG))]
5336 [(use (reg:SI R0_REG))]
5338 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5343 (define_insn "shl_sext_ext"
5344 [(set (match_operand:SI 0 "register_operand" "=r")
5346 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5347 (match_operand:SI 2 "const_int_operand" "n"))
5348 (match_operand:SI 3 "const_int_operand" "n")
5350 (clobber (reg:SI T_REG))]
5351 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5353 [(set (attr "length")
5354 (cond [(match_test "shl_sext_length (insn)")
5356 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5358 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5360 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5362 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5364 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5366 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5368 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5369 (const_string "16")]
5370 (const_string "18")))
5371 (set_attr "type" "arith")])
5373 (define_insn "shl_sext_sub"
5374 [(set (match_operand:SI 0 "register_operand" "=z")
5376 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5377 (match_operand:SI 2 "const_int_operand" "n"))
5378 (match_operand:SI 3 "const_int_operand" "n")
5380 (clobber (reg:SI T_REG))]
5381 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5383 [(set (attr "length")
5384 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5386 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5388 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5390 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5391 (const_string "12")]
5392 (const_string "14")))
5393 (set_attr "type" "arith")])
5395 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5396 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5398 (define_insn "xtrct_left"
5399 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5400 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5402 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5406 [(set_attr "type" "arith")])
5408 (define_insn "xtrct_right"
5409 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5410 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5412 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5416 [(set_attr "type" "arith")])
5418 ;; -------------------------------------------------------------------------
5420 ;; -------------------------------------------------------------------------
5423 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5424 (neg:SI (plus:SI (reg:SI T_REG)
5425 (match_operand:SI 1 "arith_reg_operand" "r"))))
5427 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5431 [(set_attr "type" "arith")])
5433 ;; A simplified version of the negc insn, where the exact value of the
5434 ;; T bit doesn't matter. This is easier for combine to pick up.
5435 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5436 ;; extra patterns for this case.
5437 (define_insn "*negc"
5438 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5439 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5440 (match_operand:SI 2 "t_reg_operand" "")))
5441 (clobber (reg:SI T_REG))]
5444 [(set_attr "type" "arith")])
5446 (define_insn "*negdi_media"
5447 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5448 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5451 [(set_attr "type" "arith_media")])
5453 ;; Don't expand immediately because otherwise neg:DI (abs:DI) will not be
5455 (define_expand "negdi2"
5456 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5457 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5458 (clobber (reg:SI T_REG))])]
5461 (define_insn_and_split "*negdi2"
5462 [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
5463 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))
5464 (clobber (reg:SI T_REG))]
5467 "&& reload_completed"
5470 emit_insn (gen_clrt ());
5471 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5472 gen_lowpart (SImode, operands[1])));
5473 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5474 gen_highpart (SImode, operands[1])));
5478 (define_insn "negsi2"
5479 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5480 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5483 [(set_attr "type" "arith")])
5485 (define_insn_and_split "one_cmplsi2"
5486 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5487 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5490 "&& can_create_pseudo_p ()"
5491 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5492 (set (match_dup 0) (reg:SI T_REG))]
5495 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5498 (set (reg0) (not:SI (reg0) (reg1)))
5499 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5500 (clobber (reg:SI T_REG))])
5502 ... match and combine the sequence manually in the split pass after the
5503 combine pass. Notice that combine does try the target pattern of this
5504 split, but if the pattern is added it interferes with other patterns, in
5505 particular with the div0s comparisons.
5506 This could also be done with a peephole but doing it here before register
5507 allocation can save one temporary.
5508 When we're here, the not:SI pattern obviously has been matched already
5509 and we only have to see whether the following insn is the left shift. */
5511 rtx i = next_nonnote_insn_bb (curr_insn);
5512 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
5515 rtx p = PATTERN (i);
5516 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
5519 rtx p0 = XVECEXP (p, 0, 0);
5520 rtx p1 = XVECEXP (p, 0, 1);
5522 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
5523 GET_CODE (p0) == SET
5524 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
5525 && REG_P (XEXP (XEXP (p0, 1), 0))
5526 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
5527 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
5528 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
5530 /* (clobber (reg:SI T_REG)) */
5531 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
5532 && REGNO (XEXP (p1, 0)) == T_REG)
5534 operands[0] = XEXP (p0, 0);
5535 set_insn_deleted (i);
5540 [(set_attr "type" "arith")])
5542 (define_expand "one_cmpldi2"
5543 [(set (match_operand:DI 0 "arith_reg_dest" "")
5544 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
5546 "TARGET_SHMEDIA" "")
5548 (define_expand "abs<mode>2"
5549 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
5550 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5551 (clobber (reg:SI T_REG))])]
5554 (define_insn_and_split "*abs<mode>2"
5555 [(set (match_operand:SIDI 0 "arith_reg_dest")
5556 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5557 (clobber (reg:SI T_REG))]
5560 "&& can_create_pseudo_p ()"
5563 if (<MODE>mode == SImode)
5564 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5567 rtx high_src = gen_highpart (SImode, operands[1]);
5568 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5571 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5576 (define_insn_and_split "*negabs<mode>2"
5577 [(set (match_operand:SIDI 0 "arith_reg_dest")
5578 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
5579 (clobber (reg:SI T_REG))]
5582 "&& can_create_pseudo_p ()"
5585 if (<MODE>mode == SImode)
5586 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5589 rtx high_src = gen_highpart (SImode, operands[1]);
5590 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5593 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5598 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
5599 ;; This can be used as some kind of conditional execution, which is useful
5601 ;; Actually the instruction scheduling should decide whether to use a
5602 ;; zero-offset branch or not for any generic case involving a single
5603 ;; instruction on SH4 202.
5604 (define_insn_and_split "negsi_cond"
5605 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5607 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
5608 (match_operand:SI 1 "arith_reg_operand" "0,0")
5609 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
5610 "TARGET_SH1 && TARGET_ZDCBRANCH"
5612 static const char* alt[] =
5622 return alt[which_alternative];
5624 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
5627 rtx skip_neg_label = gen_label_rtx ();
5629 emit_move_insn (operands[0], operands[1]);
5631 emit_jump_insn (INTVAL (operands[3])
5632 ? gen_branch_true (skip_neg_label)
5633 : gen_branch_false (skip_neg_label));
5635 emit_label_after (skip_neg_label,
5636 emit_insn (gen_negsi2 (operands[0], operands[1])));
5639 [(set_attr "type" "arith") ;; poor approximation
5640 (set_attr "length" "4")])
5642 (define_insn_and_split "negdi_cond"
5643 [(set (match_operand:DI 0 "arith_reg_dest")
5645 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
5646 (match_operand:DI 1 "arith_reg_operand")
5647 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
5648 (clobber (reg:SI T_REG))]
5651 "&& can_create_pseudo_p ()"
5654 rtx skip_neg_label = gen_label_rtx ();
5656 emit_move_insn (operands[0], operands[1]);
5658 emit_jump_insn (INTVAL (operands[3])
5659 ? gen_branch_true (skip_neg_label)
5660 : gen_branch_false (skip_neg_label));
5662 if (!INTVAL (operands[3]))
5663 emit_insn (gen_clrt ());
5665 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5666 gen_lowpart (SImode, operands[1])));
5667 emit_label_after (skip_neg_label,
5668 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5669 gen_highpart (SImode, operands[1]))));
5673 (define_expand "bswapsi2"
5674 [(set (match_operand:SI 0 "arith_reg_dest" "")
5675 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
5678 if (! can_create_pseudo_p ())
5682 rtx tmp0 = gen_reg_rtx (SImode);
5683 rtx tmp1 = gen_reg_rtx (SImode);
5685 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
5686 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
5687 emit_insn (gen_swapbsi2 (operands[0], tmp1));
5692 (define_insn "swapbsi2"
5693 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5694 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
5695 (const_int 4294901760))
5696 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5698 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5699 (const_int 255)))))]
5702 [(set_attr "type" "arith")])
5704 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
5705 ;; partial byte swap expressions such as...
5706 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
5707 ;; ...which are currently not handled by the tree optimizers.
5708 ;; The combine pass will not initially try to combine the full expression,
5709 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
5710 ;; pattern acts as an intermediate pattern that will eventually lead combine
5711 ;; to the swapbsi2 pattern above.
5712 ;; As a side effect this also improves code that does (x & 0xFF) << 8
5713 ;; or (x << 8) & 0xFF00.
5714 (define_insn_and_split "*swapbisi2_and_shl8"
5715 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5716 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5719 (match_operand:SI 2 "arith_reg_operand" "r")))]
5720 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5722 "&& can_create_pseudo_p ()"
5725 rtx tmp0 = gen_reg_rtx (SImode);
5726 rtx tmp1 = gen_reg_rtx (SImode);
5728 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
5729 emit_insn (gen_swapbsi2 (tmp1, tmp0));
5730 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
5734 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
5735 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
5736 (define_insn_and_split "*swapbhisi2"
5737 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5738 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5741 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
5742 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5744 "&& can_create_pseudo_p ()"
5747 rtx tmp = gen_reg_rtx (SImode);
5749 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
5750 emit_insn (gen_swapbsi2 (operands[0], tmp));
5754 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
5758 ;; which can be simplified to...
5761 [(set (match_operand:SI 0 "arith_reg_dest" "")
5762 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5763 (const_int 4294901760))
5764 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5766 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5768 (set (match_operand:SI 2 "arith_reg_dest" "")
5770 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
5772 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5773 (const_int 4294901760))
5774 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5776 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5777 (const_int 255)))))])
5779 ;; -------------------------------------------------------------------------
5780 ;; Zero extension instructions
5781 ;; -------------------------------------------------------------------------
5783 (define_insn "zero_extendsidi2"
5784 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5785 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
5787 "addz.l %1, r63, %0"
5788 [(set_attr "type" "arith_media")
5789 (set_attr "highpart" "extend")])
5791 (define_insn "zero_extendhidi2"
5792 [(set (match_operand:DI 0 "register_operand" "=r,r")
5793 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5798 [(set_attr "type" "*,load_media")
5799 (set (attr "highpart")
5800 (cond [(match_test "sh_contains_memref_p (insn)")
5801 (const_string "user")]
5802 (const_string "ignore")))])
5805 [(set (match_operand:DI 0 "register_operand" "")
5806 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
5807 "TARGET_SHMEDIA && reload_completed"
5808 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
5809 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
5811 if (GET_CODE (operands[1]) == TRUNCATE)
5812 operands[1] = XEXP (operands[1], 0);
5815 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
5816 ;; reload the entire truncate expression.
5817 (define_insn_and_split "*loaddi_trunc"
5818 [(set (match_operand 0 "any_register_operand" "=r")
5819 (truncate (match_operand:DI 1 "memory_operand" "m")))]
5820 "TARGET_SHMEDIA && reload_completed"
5822 "TARGET_SHMEDIA && reload_completed"
5823 [(set (match_dup 0) (match_dup 1))]
5825 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
5828 (define_insn "zero_extendqidi2"
5829 [(set (match_operand:DI 0 "register_operand" "=r,r")
5830 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
5835 [(set_attr "type" "arith_media,load_media")
5836 (set (attr "highpart")
5837 (cond [(match_test "sh_contains_memref_p (insn)")
5838 (const_string "user")]
5839 (const_string "ignore")))])
5841 (define_expand "zero_extend<mode>si2"
5842 [(set (match_operand:SI 0 "arith_reg_dest")
5843 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
5845 (define_insn_and_split "*zero_extend<mode>si2_compact"
5846 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5847 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
5850 "&& can_create_pseudo_p ()"
5851 [(set (match_dup 0) (match_dup 2))]
5853 /* Sometimes combine fails to combine a T bit or negated T bit store to a
5854 reg with a following zero extension. In the split pass after combine,
5855 try to figure out how the extended reg was set. If it originated from
5856 the T bit we can replace the zero extension with a reg move, which will
5857 be eliminated. Notice that this also helps the *cbranch_t splitter when
5858 it tries to post-combine tests and conditional branches, as it does not
5859 check for zero extensions. */
5860 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
5861 if (operands[2] == NULL_RTX)
5864 [(set_attr "type" "arith")])
5866 (define_insn "*zero_extendhisi2_media"
5867 [(set (match_operand:SI 0 "register_operand" "=r,r")
5868 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5873 [(set_attr "type" "arith_media,load_media")
5874 (set (attr "highpart")
5875 (cond [(match_test "sh_contains_memref_p (insn)")
5876 (const_string "user")]
5877 (const_string "ignore")))])
5880 [(set (match_operand:SI 0 "register_operand" "")
5881 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
5882 "TARGET_SHMEDIA && reload_completed"
5883 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
5884 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
5886 rtx op1 = operands[1];
5888 if (GET_CODE (op1) == TRUNCATE)
5889 op1 = XEXP (op1, 0);
5891 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
5892 subreg_lowpart_offset (SImode, GET_MODE (op1)));
5895 (define_insn "*zero_extendqisi2_media"
5896 [(set (match_operand:SI 0 "register_operand" "=r,r")
5897 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
5902 [(set_attr "type" "arith_media,load_media")
5903 (set (attr "highpart")
5904 (cond [(match_test "sh_contains_memref_p (insn)")
5905 (const_string "user")]
5906 (const_string "ignore")))])
5908 (define_insn "zero_extendqihi2"
5909 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
5910 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
5913 [(set_attr "type" "arith")])
5915 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
5916 ;; They could also be used for simple memory addresses like @Rn by setting
5917 ;; the displacement value to zero. However, doing so too early results in
5918 ;; missed opportunities for other optimizations such as post-inc or index
5919 ;; addressing loads.
5920 ;; Although the 'zero_extend_movu_operand' predicate does not allow simple
5921 ;; register addresses (an address without a displacement, index, post-inc),
5922 ;; zero-displacement addresses might be generated during reload, wich are
5923 ;; simplified to simple register addresses in turn. Thus, we have to
5924 ;; provide the Sdd and Sra alternatives in the patterns.
5925 (define_insn "*zero_extend<mode>si2_disp_mem"
5926 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5928 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
5932 movu.<bw> @(0,%t1),%0"
5933 [(set_attr "type" "load")
5934 (set_attr "length" "4")])
5936 ;; Convert the zero extending loads in sequences such as:
5937 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
5938 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
5940 ;; back to sign extending loads like:
5941 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
5942 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
5944 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
5945 ;; is only 2 bytes in size if the displacement is {K04|K05}.
5946 ;; If the displacement is greater it doesn't matter, so we convert anyways.
5948 [(set (match_operand:SI 0 "arith_reg_dest" "")
5949 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
5950 (set (match_operand 2 "general_operand" "")
5951 (match_operand 3 "arith_reg_operand" ""))]
5953 && REGNO (operands[0]) == REGNO (operands[3])
5954 && peep2_reg_dead_p (2, operands[0])
5955 && GET_MODE_SIZE (GET_MODE (operands[2]))
5956 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
5957 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
5958 (set (match_dup 2) (match_dup 3))])
5960 ;; Fold sequences such as
5964 ;; movu.b @(0,r3),r7
5965 ;; This does not reduce the code size but the number of instructions is
5966 ;; halved, which results in faster code.
5968 [(set (match_operand:SI 0 "arith_reg_dest" "")
5969 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
5970 (set (match_operand:SI 2 "arith_reg_dest" "")
5971 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
5973 && GET_MODE (operands[1]) == GET_MODE (operands[3])
5974 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
5975 && REGNO (operands[0]) == REGNO (operands[3])
5976 && (REGNO (operands[2]) == REGNO (operands[0])
5977 || peep2_reg_dead_p (2, operands[0]))"
5978 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
5981 = replace_equiv_address (operands[1],
5982 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
5986 ;; -------------------------------------------------------------------------
5987 ;; Sign extension instructions
5988 ;; -------------------------------------------------------------------------
5990 ;; ??? This should be a define expand.
5991 ;; ??? Or perhaps it should be dropped?
5993 ;; convert_move generates good code for SH[1-4].
5994 (define_insn "extendsidi2"
5995 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5996 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6002 [(set_attr "type" "arith_media,load_media,fpconv_media")
6003 (set (attr "highpart")
6004 (cond [(match_test "sh_contains_memref_p (insn)")
6005 (const_string "user")]
6006 (const_string "extend")))])
6008 (define_insn "extendhidi2"
6009 [(set (match_operand:DI 0 "register_operand" "=r,r")
6010 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6015 [(set_attr "type" "*,load_media")
6016 (set (attr "highpart")
6017 (cond [(match_test "sh_contains_memref_p (insn)")
6018 (const_string "user")]
6019 (const_string "ignore")))])
6022 [(set (match_operand:DI 0 "register_operand" "")
6023 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6024 "TARGET_SHMEDIA && reload_completed"
6025 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6026 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6028 if (GET_CODE (operands[1]) == TRUNCATE)
6029 operands[1] = XEXP (operands[1], 0);
6032 (define_insn "extendqidi2"
6033 [(set (match_operand:DI 0 "register_operand" "=r,r")
6034 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6039 [(set_attr "type" "*,load_media")
6040 (set (attr "highpart")
6041 (cond [(match_test "sh_contains_memref_p (insn)")
6042 (const_string "user")]
6043 (const_string "ignore")))])
6046 [(set (match_operand:DI 0 "register_operand" "")
6047 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6048 "TARGET_SHMEDIA && reload_completed"
6049 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6050 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6052 if (GET_CODE (operands[1]) == TRUNCATE)
6053 operands[1] = XEXP (operands[1], 0);
6056 (define_expand "extend<mode>si2"
6057 [(set (match_operand:SI 0 "arith_reg_dest")
6058 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6060 (define_insn "*extendhisi2_media"
6061 [(set (match_operand:SI 0 "register_operand" "=r,r")
6062 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6067 [(set_attr "type" "arith_media,load_media")
6068 (set (attr "highpart")
6069 (cond [(match_test "sh_contains_memref_p (insn)")
6070 (const_string "user")]
6071 (const_string "ignore")))])
6074 [(set (match_operand:SI 0 "register_operand" "")
6075 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6076 "TARGET_SHMEDIA && reload_completed"
6077 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6078 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6080 rtx op1 = operands[1];
6081 if (GET_CODE (op1) == TRUNCATE)
6082 op1 = XEXP (op1, 0);
6084 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6085 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6088 (define_insn_and_split "*extend<mode>si2_compact_reg"
6089 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6090 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6093 "&& can_create_pseudo_p ()"
6094 [(set (match_dup 0) (match_dup 2))]
6096 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6097 reg with a following sign extension. In the split pass after combine,
6098 try to figure the extended reg was set. If it originated from the T
6099 bit we can replace the sign extension with a reg move, which will be
6101 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6102 if (operands[2] == NULL_RTX)
6105 [(set_attr "type" "arith")])
6107 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6109 (define_insn "*extend<mode>si2_compact_mem_disp"
6110 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6114 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6115 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6116 "TARGET_SH1 && ! TARGET_SH2A
6117 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6119 mov.<bw> @(%O2,%1),%0
6121 [(set_attr "type" "load")])
6123 (define_insn "*extend<mode>si2_compact_mem_disp"
6124 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6128 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6129 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6130 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6132 mov.<bw> @(%O2,%1),%0
6134 mov.<bw> @(%O2,%1),%0"
6135 [(set_attr "type" "load")
6136 (set_attr "length" "2,2,4")])
6138 ;; The *_snd patterns will take care of other QImode/HImode addressing
6139 ;; modes than displacement addressing. They must be defined _after_ the
6140 ;; displacement addressing patterns. Otherwise the displacement addressing
6141 ;; patterns will not be picked.
6142 (define_insn "*extend<mode>si2_compact_snd"
6143 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6145 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6148 [(set_attr "type" "load")])
6150 (define_insn "*extendqisi2_media"
6151 [(set (match_operand:SI 0 "register_operand" "=r,r")
6152 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6157 [(set_attr "type" "arith_media,load_media")
6158 (set (attr "highpart")
6159 (cond [(match_test "sh_contains_memref_p (insn)")
6160 (const_string "user")]
6161 (const_string "ignore")))])
6164 [(set (match_operand:SI 0 "register_operand" "")
6165 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6166 "TARGET_SHMEDIA && reload_completed"
6167 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6168 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6170 rtx op1 = operands[1];
6171 if (GET_CODE (op1) == TRUNCATE)
6172 op1 = XEXP (op1, 0);
6174 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6175 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6178 (define_expand "extendqihi2"
6179 [(set (match_operand:HI 0 "arith_reg_dest" "")
6180 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))]
6184 (define_insn "*extendqihi2_compact_reg"
6185 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6186 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6189 [(set_attr "type" "arith")])
6191 ;; It would seem useful to combine the truncXi patterns into the movXi
6192 ;; patterns, but unary operators are ignored when matching constraints,
6193 ;; so we need separate patterns.
6194 (define_insn "truncdisi2"
6195 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6196 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6205 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6206 fpconv_media,fmove_media")
6207 (set (attr "highpart")
6208 (cond [(match_test "sh_contains_memref_p (insn)")
6209 (const_string "user")]
6210 (const_string "extend")))])
6212 (define_insn "truncdihi2"
6213 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6214 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6217 static const char* alt[] =
6219 "shlli %1,48,%0" "\n"
6224 return alt[which_alternative];
6226 [(set_attr "type" "arith_media,store_media")
6227 (set_attr "length" "8,4")
6228 (set (attr "highpart")
6229 (cond [(match_test "sh_contains_memref_p (insn)")
6230 (const_string "user")]
6231 (const_string "extend")))])
6233 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6234 ; Because we use zero extension, we can't provide signed QImode compares
6235 ; using a simple compare or conditional branch insn.
6236 (define_insn "truncdiqi2"
6237 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6238 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6243 [(set_attr "type" "arith_media,store")
6244 (set (attr "highpart")
6245 (cond [(match_test "sh_contains_memref_p (insn)")
6246 (const_string "user")]
6247 (const_string "extend")))])
6249 ;; -------------------------------------------------------------------------
6250 ;; Move instructions
6251 ;; -------------------------------------------------------------------------
6253 ;; define push and pop so it is easy for sh.c
6254 ;; We can't use push and pop on SHcompact because the stack must always
6255 ;; be 8-byte aligned.
6256 (define_expand "push"
6257 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6258 (match_operand:SI 0 "register_operand" "r,l,x"))]
6259 "TARGET_SH1 && ! TARGET_SH5"
6262 (define_expand "pop"
6263 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6264 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6265 "TARGET_SH1 && ! TARGET_SH5"
6268 (define_expand "push_e"
6269 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6270 (match_operand:SF 0 "" ""))
6271 (use (reg:PSI FPSCR_REG))
6272 (clobber (scratch:SI))])]
6273 "TARGET_SH1 && ! TARGET_SH5"
6276 (define_insn "push_fpul"
6277 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6278 "TARGET_SH2E && ! TARGET_SH5"
6280 [(set_attr "type" "fstore")
6281 (set_attr "late_fp_use" "yes")
6282 (set_attr "hit_stack" "yes")])
6284 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6286 (define_expand "push_4"
6287 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6288 (match_operand:DF 0 "" ""))
6289 (use (reg:PSI FPSCR_REG))
6290 (clobber (scratch:SI))])]
6291 "TARGET_SH1 && ! TARGET_SH5"
6294 (define_expand "pop_e"
6295 [(parallel [(set (match_operand:SF 0 "" "")
6296 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6297 (use (reg:PSI FPSCR_REG))
6298 (clobber (scratch:SI))])]
6299 "TARGET_SH1 && ! TARGET_SH5"
6302 (define_insn "pop_fpul"
6303 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6304 "TARGET_SH2E && ! TARGET_SH5"
6306 [(set_attr "type" "load")
6307 (set_attr "hit_stack" "yes")])
6309 (define_expand "pop_4"
6310 [(parallel [(set (match_operand:DF 0 "" "")
6311 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6312 (use (reg:PSI FPSCR_REG))
6313 (clobber (scratch:SI))])]
6314 "TARGET_SH1 && ! TARGET_SH5"
6317 (define_expand "push_fpscr"
6321 rtx insn = emit_insn (gen_fpu_switch (gen_frame_mem (PSImode,
6322 gen_rtx_PRE_DEC (Pmode,
6323 stack_pointer_rtx)),
6325 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6329 (define_expand "pop_fpscr"
6333 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
6334 gen_frame_mem (PSImode,
6335 gen_rtx_POST_INC (Pmode,
6336 stack_pointer_rtx))));
6337 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6341 ;; The clrt and sett patterns can happen as the result of optimization and
6343 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6344 ;; In this case they might not disappear completely, because the T reg is
6345 ;; a fixed hard reg.
6346 ;; When DImode operations that use the T reg as carry/borrow are split into
6347 ;; individual SImode operations, the T reg is usually cleared before the
6348 ;; first SImode insn.
6350 [(set (reg:SI T_REG) (const_int 0))]
6353 [(set_attr "type" "mt_group")])
6356 [(set (reg:SI T_REG) (const_int 1))]
6359 [(set_attr "type" "mt_group")])
6361 ;; Use the combine pass to transform sequences such as
6365 ;; mov.l @(r0,r4),r0
6371 ;; See also PR 39423.
6372 ;; Notice that these patterns have a T_REG clobber, because the shift
6373 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6374 ;; clobber would be added conditionally, depending on the result of
6375 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6376 ;; through the ashlsi3 expander in order to get the right shift insn --
6377 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6378 ;; FIXME: Combine never tries this kind of patterns for DImode.
6379 (define_insn_and_split "*movsi_index_disp_load"
6380 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6381 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6382 (clobber (reg:SI T_REG))]
6385 "&& can_create_pseudo_p ()"
6386 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6387 (set (match_dup 0) (match_dup 7))]
6389 rtx mem = operands[1];
6390 rtx plus0_rtx = XEXP (mem, 0);
6391 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6392 rtx mult_rtx = XEXP (plus1_rtx, 0);
6394 operands[1] = XEXP (mult_rtx, 0);
6395 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6396 operands[3] = XEXP (plus1_rtx, 1);
6397 operands[4] = XEXP (plus0_rtx, 1);
6398 operands[5] = gen_reg_rtx (SImode);
6399 operands[6] = gen_reg_rtx (SImode);
6401 replace_equiv_address (mem,
6402 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6404 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6407 (define_insn_and_split "*movhi_index_disp_load"
6408 [(set (match_operand:SI 0 "arith_reg_dest")
6409 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6410 (clobber (reg:SI T_REG))]
6413 "&& can_create_pseudo_p ()"
6416 rtx mem = operands[1];
6417 rtx plus0_rtx = XEXP (mem, 0);
6418 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6419 rtx mult_rtx = XEXP (plus1_rtx, 0);
6421 rtx op_1 = XEXP (mult_rtx, 0);
6422 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6423 rtx op_3 = XEXP (plus1_rtx, 1);
6424 rtx op_4 = XEXP (plus0_rtx, 1);
6425 rtx op_5 = gen_reg_rtx (SImode);
6426 rtx op_6 = gen_reg_rtx (SImode);
6427 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6429 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6430 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6432 if (<CODE> == SIGN_EXTEND)
6434 emit_insn (gen_extendhisi2 (operands[0], op_7));
6437 else if (<CODE> == ZERO_EXTEND)
6439 /* On SH2A the movu.w insn can be used for zero extending loads. */
6441 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6444 emit_insn (gen_extendhisi2 (operands[0], op_7));
6445 emit_insn (gen_zero_extendhisi2 (operands[0],
6446 gen_lowpart (HImode, operands[0])));
6454 (define_insn_and_split "*mov<mode>_index_disp_store"
6455 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6456 (match_operand:HISI 1 "arith_reg_operand" "r"))
6457 (clobber (reg:SI T_REG))]
6460 "&& can_create_pseudo_p ()"
6461 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6462 (set (match_dup 7) (match_dup 1))]
6464 rtx mem = operands[0];
6465 rtx plus0_rtx = XEXP (mem, 0);
6466 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6467 rtx mult_rtx = XEXP (plus1_rtx, 0);
6469 operands[0] = XEXP (mult_rtx, 0);
6470 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6471 operands[3] = XEXP (plus1_rtx, 1);
6472 operands[4] = XEXP (plus0_rtx, 1);
6473 operands[5] = gen_reg_rtx (SImode);
6474 operands[6] = gen_reg_rtx (SImode);
6476 replace_equiv_address (mem,
6477 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6479 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6482 ;; t/r must come after r/r, lest reload will try to reload stuff like
6483 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6484 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6485 (define_insn "movsi_i"
6486 [(set (match_operand:SI 0 "general_movdst_operand"
6487 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6488 (match_operand:SI 1 "general_movsrc_operand"
6489 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6493 && (register_operand (operands[0], SImode)
6494 || register_operand (operands[1], SImode))"
6510 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
6511 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
6512 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
6514 ;; t/r must come after r/r, lest reload will try to reload stuff like
6515 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
6516 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
6517 ;; will require a reload.
6518 ;; ??? We can't include f/f because we need the proper FPSCR setting when
6519 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
6520 (define_insn "movsi_ie"
6521 [(set (match_operand:SI 0 "general_movdst_operand"
6522 "=r,r,r,r,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
6523 (match_operand:SI 1 "general_movsrc_operand"
6524 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
6525 "(TARGET_SH2E || TARGET_SH2A)
6526 && (register_operand (operands[0], SImode)
6527 || register_operand (operands[1], SImode))"
6552 ! move optimized away"
6553 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
6554 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
6555 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
6556 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
6557 (set_attr_alternative "length"
6564 (match_test "TARGET_SH2A")
6565 (const_int 4) (const_int 2))
6569 (match_test "TARGET_SH2A")
6570 (const_int 4) (const_int 2))
6587 (define_insn "movsi_i_lowpart"
6588 [(set (strict_low_part
6589 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
6590 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
6592 && (register_operand (operands[0], SImode)
6593 || register_operand (operands[1], SImode))"
6603 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
6605 (define_insn_and_split "load_ra"
6606 [(set (match_operand:SI 0 "general_movdst_operand" "")
6607 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
6610 "&& ! currently_expanding_to_rtl"
6611 [(set (match_dup 0) (match_dup 1))]
6613 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
6614 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
6617 ;; The '?'s in the following constraints may not reflect the time taken
6618 ;; to perform the move. They are there to discourage the use of floating-
6619 ;; point registers for storing integer values.
6620 (define_insn "*movsi_media"
6621 [(set (match_operand:SI 0 "general_movdst_operand"
6622 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
6623 (match_operand:SI 1 "general_movsrc_operand"
6624 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
6626 && (register_operand (operands[0], SImode)
6627 || sh_register_operand (operands[1], SImode)
6628 || GET_CODE (operands[1]) == TRUNCATE)"
6643 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6644 fload_media,fstore_media,fload_media,fpconv_media,
6645 fmove_media,ptabs_media,gettr_media,pt_media")
6646 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
6647 (set (attr "highpart")
6648 (cond [(match_test "sh_contains_memref_p (insn)")
6649 (const_string "user")]
6650 (const_string "ignore")))])
6652 (define_insn "*movsi_media_nofpu"
6653 [(set (match_operand:SI 0 "general_movdst_operand"
6654 "=r,r,r,r,m,*b,r,*b")
6655 (match_operand:SI 1 "general_movsrc_operand"
6656 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
6658 && (register_operand (operands[0], SImode)
6659 || sh_register_operand (operands[1], SImode)
6660 || GET_CODE (operands[1]) == TRUNCATE)"
6670 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6671 ptabs_media,gettr_media,pt_media")
6672 (set_attr "length" "4,4,8,4,4,4,4,12")
6673 (set (attr "highpart")
6674 (cond [(match_test "sh_contains_memref_p (insn)")
6675 (const_string "user")]
6676 (const_string "ignore")))])
6678 (define_expand "movsi_const"
6679 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6680 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6681 (const_int 16)] UNSPEC_EXTRACT_S16)))
6683 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
6684 (const:SI (unspec:SI [(match_dup 1)
6685 (const_int 0)] UNSPEC_EXTRACT_U16))))]
6686 "TARGET_SHMEDIA && reload_completed
6687 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6689 if (GET_CODE (operands[1]) == LABEL_REF
6690 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
6691 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
6692 else if (GOTOFF_P (operands[1]))
6694 rtx unspec = XEXP (operands[1], 0);
6696 if (! UNSPEC_GOTOFF_P (unspec))
6698 unspec = XEXP (unspec, 0);
6699 if (! UNSPEC_GOTOFF_P (unspec))
6702 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
6703 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
6704 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
6708 (define_expand "movsi_const_16bit"
6709 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6710 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6711 (const_int 0)] UNSPEC_EXTRACT_S16)))]
6712 "TARGET_SHMEDIA && flag_pic && reload_completed
6713 && GET_CODE (operands[1]) == SYMBOL_REF"
6717 [(set (match_operand:SI 0 "arith_reg_dest" "")
6718 (match_operand:SI 1 "immediate_operand" ""))]
6719 "TARGET_SHMEDIA && reload_completed
6720 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6723 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
6725 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
6731 [(set (match_operand:SI 0 "register_operand" "")
6732 (match_operand:SI 1 "immediate_operand" ""))]
6733 "TARGET_SHMEDIA && reload_completed
6734 && ((CONST_INT_P (operands[1])
6735 && ! satisfies_constraint_I16 (operands[1]))
6736 || GET_CODE (operands[1]) == CONST_DOUBLE)"
6737 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
6739 (define_expand "movsi"
6740 [(set (match_operand:SI 0 "general_movdst_operand" "")
6741 (match_operand:SI 1 "general_movsrc_operand" ""))]
6744 prepare_move_operands (operands, SImode);
6747 (define_expand "ic_invalidate_line"
6748 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
6749 (match_dup 1)] UNSPEC_ICACHE)
6750 (clobber (scratch:SI))])]
6751 "TARGET_HARD_SH4 || TARGET_SH5"
6755 emit_insn (gen_ic_invalidate_line_media (operands[0]));
6758 else if (TARGET_SHCOMPACT)
6760 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
6761 operands[1] = force_reg (Pmode, operands[1]);
6762 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
6765 else if (TARGET_SH4A_ARCH || TARGET_SH4_300)
6767 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
6770 operands[0] = force_reg (Pmode, operands[0]);
6771 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
6775 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
6776 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
6777 ;; the requirement *1*00 for associative address writes. The alignment of
6778 ;; %0 implies that its least significant bit is cleared,
6779 ;; thus we clear the V bit of a matching entry if there is one.
6780 (define_insn "ic_invalidate_line_i"
6781 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
6782 (match_operand:SI 1 "register_operand" "r")]
6784 (clobber (match_scratch:SI 2 "=&r"))]
6787 return "ocbwb @%0" "\n"
6788 " extu.w %0,%2" "\n"
6792 [(set_attr "length" "8")
6793 (set_attr "type" "cwb")])
6795 (define_insn "ic_invalidate_line_sh4a"
6796 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
6798 "TARGET_SH4A_ARCH || TARGET_SH4_300"
6800 return "ocbwb @%0" "\n"
6804 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
6805 (set_attr "type" "cwb")])
6807 ;; ??? could make arg 0 an offsettable memory operand to allow to save
6808 ;; an add in the code that calculates the address.
6809 (define_insn "ic_invalidate_line_media"
6810 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
6814 return "ocbwb %0,0" "\n"
6819 [(set_attr "length" "16")
6820 (set_attr "type" "invalidate_line_media")])
6822 (define_insn "ic_invalidate_line_compact"
6823 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6824 (match_operand:SI 1 "register_operand" "r")]
6826 (clobber (reg:SI PR_REG))]
6829 [(set_attr "type" "sfunc")
6830 (set_attr "needs_delay_slot" "yes")])
6832 (define_expand "initialize_trampoline"
6833 [(match_operand:SI 0 "" "")
6834 (match_operand:SI 1 "" "")
6835 (match_operand:SI 2 "" "")]
6840 tramp = force_reg (Pmode, operands[0]);
6841 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
6843 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
6844 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
6846 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
6850 (define_insn "initialize_trampoline_compact"
6851 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6852 (match_operand:SI 1 "register_operand" "r")
6853 (reg:SI R2_REG) (reg:SI R3_REG)]
6856 (clobber (reg:SI PR_REG))]
6859 [(set_attr "type" "sfunc")
6860 (set_attr "needs_delay_slot" "yes")])
6862 (define_expand "movhi"
6863 [(set (match_operand:HI 0 "general_movdst_operand" "")
6864 (match_operand:HI 1 "general_movsrc_operand" ""))]
6867 prepare_move_operands (operands, HImode);
6870 (define_expand "movqi"
6871 [(set (match_operand:QI 0 "general_operand" "")
6872 (match_operand:QI 1 "general_operand" ""))]
6875 prepare_move_operands (operands, QImode);
6878 ;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be
6879 ;; selected to copy QImode regs. If one of them happens to be allocated
6880 ;; on the stack, reload will stick to movqi insn and generate wrong
6881 ;; displacement addressing because of the generic m alternatives.
6882 ;; With the movqi_reg_reg being specified before movqi it will be initially
6883 ;; picked to load/store regs. If the regs regs are on the stack reload
6884 ;; try other insns and not stick to movqi_reg_reg, unless there were spilled
6885 ;; pseudos in which case 'm' constraints pertain.
6886 ;; The same applies to the movhi variants.
6888 ;; Notice, that T bit is not allowed as a mov src operand here. This is to
6889 ;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which
6890 ;; introduces zero extensions after T bit stores and redundant reg copies.
6892 ;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a
6893 ;; predicate for the mov src operand because reload will have trouble
6894 ;; reloading MAC subregs otherwise. For that probably special patterns
6895 ;; would be required.
6896 (define_insn "*mov<mode>_reg_reg"
6897 [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z")
6898 (match_operand:QIHI 1 "register_operand" "r,*z,m"))]
6899 "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)"
6904 [(set_attr "type" "move,store,load")])
6906 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
6907 ;; "enabled" attribute as it is done in other targets.
6908 (define_insn "*mov<mode>_store_mem_disp04"
6910 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
6911 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
6912 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
6913 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
6915 mov.<bw> %2,@(%O1,%0)
6917 [(set_attr "type" "store")])
6919 (define_insn "*mov<mode>_store_mem_disp12"
6921 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
6922 (match_operand:SI 1 "const_int_operand" "<disp12>")))
6923 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
6924 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
6925 "mov.<bw> %2,@(%O1,%0)"
6926 [(set_attr "type" "store")
6927 (set_attr "length" "4")])
6929 (define_insn "*mov<mode>_load_mem_disp04"
6930 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
6932 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
6933 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
6934 "TARGET_SH1 && ! TARGET_SH2A
6935 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6937 mov.<bw> @(%O2,%1),%0
6939 [(set_attr "type" "load")])
6941 (define_insn "*mov<mode>_load_mem_disp12"
6942 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
6945 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6946 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
6947 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6949 mov.<bw> @(%O2,%1),%0
6951 mov.<bw> @(%O2,%1),%0"
6952 [(set_attr "type" "load")
6953 (set_attr "length" "2,2,4")])
6955 ;; The m constraints basically allow any kind of addresses to be used with any
6956 ;; source/target register as the other operand. This is not true for
6957 ;; displacement addressing modes on anything but SH2A. That's why the
6958 ;; specialized load/store insns are specified above.
6959 (define_insn "*movqi"
6960 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")
6961 (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]
6963 && (arith_reg_operand (operands[0], QImode)
6964 || arith_reg_operand (operands[1], QImode))"
6971 [(set_attr "type" "movi8,load,store,prget,prset")])
6973 (define_insn "*movhi"
6974 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l")
6975 (match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))]
6977 && (arith_reg_operand (operands[0], HImode)
6978 || arith_reg_operand (operands[1], HImode))"
6986 [(set_attr "type" "pcload,movi8,load,store,prget,prset")])
6988 (define_insn "*movqi_media"
6989 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
6990 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
6992 && (arith_reg_operand (operands[0], QImode)
6993 || extend_reg_or_0_operand (operands[1], QImode))"
6999 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7000 (set (attr "highpart")
7001 (cond [(match_test "sh_contains_memref_p (insn)")
7002 (const_string "user")]
7003 (const_string "ignore")))])
7005 (define_expand "reload_inqi"
7006 [(set (match_operand:SI 2 "" "=&r")
7007 (match_operand:QI 1 "inqhi_operand" ""))
7008 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7009 (truncate:QI (match_dup 3)))]
7012 rtx inner = XEXP (operands[1], 0);
7013 int regno = REGNO (inner);
7015 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7016 operands[1] = gen_rtx_REG (SImode, regno);
7017 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7020 (define_insn "*movhi_media"
7021 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7022 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7024 && (arith_reg_operand (operands[0], HImode)
7025 || arith_reg_or_0_operand (operands[1], HImode))"
7032 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7033 (set (attr "highpart")
7034 (cond [(match_test "sh_contains_memref_p (insn)")
7035 (const_string "user")]
7036 (const_string "ignore")))])
7039 [(set (match_operand:HI 0 "register_operand" "")
7040 (match_operand:HI 1 "immediate_operand" ""))]
7041 "TARGET_SHMEDIA && reload_completed
7042 && ! satisfies_constraint_I16 (operands[1])"
7043 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7045 (define_expand "reload_inhi"
7046 [(set (match_operand:SI 2 "" "=&r")
7047 (match_operand:HI 1 "inqhi_operand" ""))
7048 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7049 (truncate:HI (match_dup 3)))]
7052 rtx inner = XEXP (operands[1], 0);
7053 int regno = REGNO (inner);
7055 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7056 operands[1] = gen_rtx_REG (SImode, regno);
7057 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7060 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7061 ;; compiled with -m2 -ml -O3 -funroll-loops
7062 (define_insn "*movdi_i"
7063 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7064 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7066 && (arith_reg_operand (operands[0], DImode)
7067 || arith_reg_operand (operands[1], DImode))"
7069 return output_movedouble (insn, operands, DImode);
7071 [(set_attr "length" "4")
7072 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7074 ;; If the output is a register and the input is memory or a register, we have
7075 ;; to be careful and see which word needs to be loaded first.
7077 [(set (match_operand:DI 0 "general_movdst_operand" "")
7078 (match_operand:DI 1 "general_movsrc_operand" ""))]
7079 "TARGET_SH1 && reload_completed"
7080 [(set (match_dup 2) (match_dup 3))
7081 (set (match_dup 4) (match_dup 5))]
7085 if ((MEM_P (operands[0])
7086 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7087 || (MEM_P (operands[1])
7088 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7091 switch (GET_CODE (operands[0]))
7094 regno = REGNO (operands[0]);
7097 regno = subreg_regno (operands[0]);
7107 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7109 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7110 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7111 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7112 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7116 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7117 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7118 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7119 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7122 if (operands[2] == 0 || operands[3] == 0
7123 || operands[4] == 0 || operands[5] == 0)
7127 ;; The '?'s in the following constraints may not reflect the time taken
7128 ;; to perform the move. They are there to discourage the use of floating-
7129 ;; point registers for storing integer values.
7130 (define_insn "*movdi_media"
7131 [(set (match_operand:DI 0 "general_movdst_operand"
7132 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7133 (match_operand:DI 1 "general_movsrc_operand"
7134 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7136 && (register_operand (operands[0], DImode)
7137 || sh_register_operand (operands[1], DImode))"
7152 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7153 fload_media,fstore_media,fload_media,dfpconv_media,
7154 fmove_media,ptabs_media,gettr_media,pt_media")
7155 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7157 (define_insn "*movdi_media_nofpu"
7158 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7159 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7161 && (register_operand (operands[0], DImode)
7162 || sh_register_operand (operands[1], DImode))"
7172 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7173 ptabs_media,gettr_media,pt_media")
7174 (set_attr "length" "4,4,16,4,4,4,4,*")])
7176 (define_insn "*movdi_media_I16"
7177 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7178 (match_operand:DI 1 "const_int_operand" "I16"))]
7179 "TARGET_SHMEDIA && reload_completed"
7181 [(set_attr "type" "arith_media")
7182 (set_attr "length" "4")])
7185 [(set (match_operand:DI 0 "arith_reg_dest" "")
7186 (match_operand:DI 1 "immediate_operand" ""))]
7187 "TARGET_SHMEDIA && reload_completed
7188 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7189 [(set (match_dup 0) (match_dup 1))]
7193 if (TARGET_SHMEDIA64)
7194 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7196 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7198 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7203 (define_expand "movdi_const"
7204 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7205 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7206 (const_int 48)] UNSPEC_EXTRACT_S16)))
7208 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7209 (const:DI (unspec:DI [(match_dup 1)
7210 (const_int 32)] UNSPEC_EXTRACT_U16))))
7212 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7213 (const:DI (unspec:DI [(match_dup 1)
7214 (const_int 16)] UNSPEC_EXTRACT_U16))))
7216 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7217 (const:DI (unspec:DI [(match_dup 1)
7218 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7219 "TARGET_SHMEDIA64 && reload_completed
7220 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7222 sh_mark_label (operands[1], 4);
7225 (define_expand "movdi_const_32bit"
7226 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7227 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7228 (const_int 16)] UNSPEC_EXTRACT_S16)))
7230 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7231 (const:DI (unspec:DI [(match_dup 1)
7232 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7233 "TARGET_SHMEDIA32 && reload_completed
7234 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7236 sh_mark_label (operands[1], 2);
7239 (define_expand "movdi_const_16bit"
7240 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7241 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7242 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7243 "TARGET_SHMEDIA && flag_pic && reload_completed
7244 && GET_CODE (operands[1]) == SYMBOL_REF"
7248 [(set (match_operand:DI 0 "ext_dest_operand" "")
7249 (match_operand:DI 1 "immediate_operand" ""))]
7250 "TARGET_SHMEDIA && reload_completed
7251 && CONST_INT_P (operands[1])
7252 && ! satisfies_constraint_I16 (operands[1])"
7253 [(set (match_dup 0) (match_dup 2))
7256 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7257 unsigned HOST_WIDE_INT low = val;
7258 unsigned HOST_WIDE_INT high = val;
7259 unsigned HOST_WIDE_INT sign;
7260 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7262 /* Zero-extend the 16 least-significant bits. */
7265 /* Arithmetic shift right the word by 16 bits. */
7267 if (GET_CODE (operands[0]) == SUBREG
7268 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7277 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7283 /* If we can't generate the constant with a two-insn movi / shori
7284 sequence, try some other strategies. */
7285 if (! CONST_OK_FOR_I16 (high))
7287 /* Try constant load / left shift. We know VAL != 0. */
7288 val2 = val ^ (val-1);
7291 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7293 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7294 || (! CONST_OK_FOR_I16 (high >> 16)
7295 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7297 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7298 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7299 GEN_INT (trailing_zeroes));
7303 /* Try constant load / right shift. */
7304 val2 = (val >> 15) + 1;
7305 if (val2 == (val2 & -val2))
7307 int shift = 49 - exact_log2 (val2);
7309 val2 = trunc_int_for_mode (val << shift, DImode);
7310 if (CONST_OK_FOR_I16 (val2))
7312 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7318 val2 = val & 0xffff;
7319 if ((val >> 16 & 0xffff) == val2
7320 && (val >> 32 & 0xffff) == val2
7321 && (val >> 48 & 0xffff) == val2)
7323 val2 = (HOST_WIDE_INT) val >> 48;
7324 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7325 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7328 /* Try movi / mshflo.l */
7329 val2 = (HOST_WIDE_INT) val >> 32;
7330 if (val2 == ((unsigned HOST_WIDE_INT)
7331 trunc_int_for_mode (val, SImode)))
7333 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7337 /* Try movi / mshflo.l w/ r63. */
7338 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7339 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7341 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7347 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7350 operands[2] = GEN_INT (val2);
7354 [(set (match_operand:DI 0 "ext_dest_operand" "")
7355 (match_operand:DI 1 "immediate_operand" ""))]
7356 "TARGET_SHMEDIA && reload_completed
7357 && GET_CODE (operands[1]) == CONST_DOUBLE"
7358 [(set (match_dup 0) (match_dup 2))
7360 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7362 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7363 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7364 unsigned HOST_WIDE_INT val = low;
7365 unsigned HOST_WIDE_INT sign;
7367 /* Zero-extend the 16 least-significant bits. */
7369 operands[1] = GEN_INT (val);
7371 /* Arithmetic shift right the double-word by 16 bits. */
7373 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7376 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7380 /* This will only be true if high is a sign-extension of low, i.e.,
7381 it must be either 0 or (unsigned)-1, and be zero iff the
7382 most-significant bit of low is set. */
7383 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7384 operands[2] = GEN_INT (low);
7386 operands[2] = immed_double_const (low, high, DImode);
7389 (define_insn "shori_media"
7390 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7391 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7393 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7394 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7398 [(set_attr "type" "arith_media,*")])
7400 (define_insn "*shori_media_si"
7401 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7402 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7404 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7408 (define_expand "movdi"
7409 [(set (match_operand:DI 0 "general_movdst_operand" "")
7410 (match_operand:DI 1 "general_movsrc_operand" ""))]
7413 prepare_move_operands (operands, DImode);
7416 (define_insn "movdf_media"
7417 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7418 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7420 && (register_operand (operands[0], DFmode)
7421 || sh_register_operand (operands[1], DFmode))"
7432 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7433 fload_media,fstore_media,load_media,store_media")])
7435 (define_insn "movdf_media_nofpu"
7436 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7437 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7439 && (register_operand (operands[0], DFmode)
7440 || sh_register_operand (operands[1], DFmode))"
7446 [(set_attr "type" "arith_media,*,load_media,store_media")])
7449 [(set (match_operand:DF 0 "arith_reg_dest" "")
7450 (match_operand:DF 1 "immediate_operand" ""))]
7451 "TARGET_SHMEDIA && reload_completed"
7452 [(set (match_dup 3) (match_dup 2))]
7454 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7456 REAL_VALUE_TYPE value;
7458 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7459 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7461 if (HOST_BITS_PER_WIDE_INT >= 64)
7462 operands[2] = immed_double_const ((unsigned long) values[endian]
7463 | ((HOST_WIDE_INT) values[1 - endian]
7467 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7468 operands[2] = immed_double_const (values[endian], values[1 - endian],
7472 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7475 ;; FIXME: This should be a define_insn_and_split.
7476 (define_insn "movdf_k"
7477 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7478 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7480 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7481 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7482 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7483 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7484 && (arith_reg_operand (operands[0], DFmode)
7485 || arith_reg_operand (operands[1], DFmode))"
7487 return output_movedouble (insn, operands, DFmode);
7489 [(set_attr "length" "4")
7490 (set_attr "type" "move,pcload,load,store")])
7492 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7493 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7494 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7495 ;; the d/m/c/X alternative, which is split later into single-precision
7496 ;; instructions. And when not optimizing, no splits are done before fixing
7497 ;; up pcloads, so we need usable length information for that.
7498 (define_insn "movdf_i4"
7499 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7500 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7501 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
7502 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
7503 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7504 && (arith_reg_operand (operands[0], DFmode)
7505 || arith_reg_operand (operands[1], DFmode))"
7507 switch (which_alternative)
7511 return "fmov %1,%0";
7512 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7513 return "fmov %R1,%R0" "\n"
7516 return "fmov %S1,%S0" "\n"
7520 return "fmov.d %1,%0";
7525 [(set_attr_alternative "length"
7526 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
7528 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7529 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7530 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7532 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
7533 ;; We can't use 4-byte push/pop on SHcompact, so we have to
7534 ;; increment or decrement r15 explicitly.
7536 (match_test "TARGET_SHCOMPACT")
7537 (const_int 10) (const_int 8))
7539 (match_test "TARGET_SHCOMPACT")
7540 (const_int 10) (const_int 8))])
7541 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
7542 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
7543 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
7544 (const_string "double")
7545 (const_string "none")))])
7547 ;; Moving DFmode between fp/general registers through memory
7548 ;; (the top of the stack) is faster than moving through fpul even for
7549 ;; little endian. Because the type of an instruction is important for its
7550 ;; scheduling, it is beneficial to split these operations, rather than
7551 ;; emitting them in one single chunk, even if this will expose a stack
7552 ;; use that will prevent scheduling of other stack accesses beyond this
7555 [(set (match_operand:DF 0 "register_operand" "")
7556 (match_operand:DF 1 "register_operand" ""))
7557 (use (match_operand:PSI 2 "fpscr_operand" ""))
7558 (clobber (match_scratch:SI 3 "=X"))]
7559 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
7560 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
7565 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
7567 emit_move_insn (stack_pointer_rtx,
7568 plus_constant (Pmode, stack_pointer_rtx, -8));
7569 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7572 tos = gen_tmp_stack_mem (DFmode,
7573 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
7574 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
7575 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
7576 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7577 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7578 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7580 tos = gen_tmp_stack_mem (DFmode,
7581 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
7582 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
7583 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7584 emit_move_insn (stack_pointer_rtx,
7585 plus_constant (Pmode, stack_pointer_rtx, 8));
7587 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7591 ;; local-alloc sometimes allocates scratch registers even when not required,
7592 ;; so we must be prepared to handle these.
7594 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
7596 [(set (match_operand:DF 0 "general_movdst_operand" "")
7597 (match_operand:DF 1 "general_movsrc_operand" ""))
7598 (use (match_operand:PSI 2 "fpscr_operand" ""))
7599 (clobber (match_scratch:SI 3 ""))]
7600 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7602 && true_regnum (operands[0]) < 16
7603 && true_regnum (operands[1]) < 16"
7604 [(set (match_dup 0) (match_dup 1))]
7606 /* If this was a reg <-> mem operation with base + index reg addressing,
7607 we have to handle this in a special way. */
7608 rtx mem = operands[0];
7610 if (! memory_operand (mem, DFmode))
7615 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
7616 mem = SUBREG_REG (mem);
7619 rtx addr = XEXP (mem, 0);
7620 if (GET_CODE (addr) == PLUS
7621 && REG_P (XEXP (addr, 0))
7622 && REG_P (XEXP (addr, 1)))
7625 rtx reg0 = gen_rtx_REG (Pmode, 0);
7626 rtx regop = operands[store_p], word0 ,word1;
7628 if (GET_CODE (regop) == SUBREG)
7629 alter_subreg (®op, true);
7630 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
7634 mem = copy_rtx (mem);
7635 PUT_MODE (mem, SImode);
7636 word0 = gen_rtx_SUBREG (SImode, regop, 0);
7637 alter_subreg (&word0, true);
7638 word1 = gen_rtx_SUBREG (SImode, regop, 4);
7639 alter_subreg (&word1, true);
7640 if (store_p || ! refers_to_regno_p (REGNO (word0),
7641 REGNO (word0) + 1, addr, 0))
7644 ? gen_movsi_ie (mem, word0)
7645 : gen_movsi_ie (word0, mem));
7646 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7647 mem = copy_rtx (mem);
7649 ? gen_movsi_ie (mem, word1)
7650 : gen_movsi_ie (word1, mem));
7651 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7655 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7656 emit_insn (gen_movsi_ie (word1, mem));
7657 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7658 mem = copy_rtx (mem);
7659 emit_insn (gen_movsi_ie (word0, mem));
7666 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
7668 [(set (match_operand:DF 0 "register_operand" "")
7669 (match_operand:DF 1 "memory_operand" ""))
7670 (use (match_operand:PSI 2 "fpscr_operand" ""))
7671 (clobber (reg:SI R0_REG))]
7672 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
7673 [(parallel [(set (match_dup 0) (match_dup 1))
7675 (clobber (scratch:SI))])]
7678 (define_expand "reload_indf__frn"
7679 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
7680 (match_operand:DF 1 "immediate_operand" "FQ"))
7681 (use (reg:PSI FPSCR_REG))
7682 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7686 (define_expand "reload_outdf__RnFRm"
7687 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
7688 (match_operand:DF 1 "register_operand" "af,r"))
7689 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
7693 ;; Simplify no-op moves.
7695 [(set (match_operand:SF 0 "register_operand" "")
7696 (match_operand:SF 1 "register_operand" ""))
7697 (use (match_operand:PSI 2 "fpscr_operand" ""))
7698 (clobber (match_scratch:SI 3 ""))]
7699 "TARGET_SH2E && reload_completed
7700 && true_regnum (operands[0]) == true_regnum (operands[1])"
7701 [(set (match_dup 0) (match_dup 0))]
7704 ;; fmovd substitute post-reload splits
7706 [(set (match_operand:DF 0 "register_operand" "")
7707 (match_operand:DF 1 "register_operand" ""))
7708 (use (match_operand:PSI 2 "fpscr_operand" ""))
7709 (clobber (match_scratch:SI 3 ""))]
7710 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
7711 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7712 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7715 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
7716 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
7717 gen_rtx_REG (SFmode, src), operands[2]));
7718 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
7719 gen_rtx_REG (SFmode, src + 1), operands[2]));
7724 [(set (match_operand:DF 0 "register_operand" "")
7725 (mem:DF (match_operand:SI 1 "register_operand" "")))
7726 (use (match_operand:PSI 2 "fpscr_operand" ""))
7727 (clobber (match_scratch:SI 3 ""))]
7728 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7729 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7730 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
7733 int regno = true_regnum (operands[0]);
7735 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
7737 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
7738 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7739 regno + !! TARGET_LITTLE_ENDIAN),
7740 mem2, operands[2]));
7741 add_reg_note (insn, REG_INC, operands[1]);
7742 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7743 regno + ! TARGET_LITTLE_ENDIAN),
7744 change_address (mem, SFmode, NULL_RTX),
7750 [(set (match_operand:DF 0 "register_operand" "")
7751 (match_operand:DF 1 "memory_operand" ""))
7752 (use (match_operand:PSI 2 "fpscr_operand" ""))
7753 (clobber (match_scratch:SI 3 ""))]
7754 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7755 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
7758 int regno = true_regnum (operands[0]);
7760 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
7761 rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
7762 rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
7764 operands[1] = copy_rtx (mem2);
7765 addr = XEXP (mem2, 0);
7767 switch (GET_CODE (addr))
7770 /* This is complicated. If the register is an arithmetic register
7771 we can just fall through to the REG+DISP case below. Otherwise
7772 we have to use a combination of POST_INC and REG addressing... */
7773 if (! arith_reg_operand (operands[1], SFmode))
7775 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
7776 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
7777 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7779 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7781 /* If we have modified the stack pointer, the value that we have
7782 read with post-increment might be modified by an interrupt,
7783 so write it back. */
7784 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
7785 emit_insn (gen_push_e (reg0));
7787 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
7794 emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7795 operands[1] = copy_rtx (operands[1]);
7796 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
7797 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7801 insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7802 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7804 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7805 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7817 [(set (match_operand:DF 0 "memory_operand" "")
7818 (match_operand:DF 1 "register_operand" ""))
7819 (use (match_operand:PSI 2 "fpscr_operand" ""))
7820 (clobber (match_scratch:SI 3 ""))]
7821 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7822 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7825 int regno = true_regnum (operands[1]);
7827 rtx reg0 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 1 : 0));
7828 rtx reg1 = gen_rtx_REG (SFmode, regno + (TARGET_LITTLE_ENDIAN ? 0 : 1));
7830 operands[0] = copy_rtx (operands[0]);
7831 PUT_MODE (operands[0], SFmode);
7832 addr = XEXP (operands[0], 0);
7834 switch (GET_CODE (addr))
7837 /* This is complicated. If the register is an arithmetic register
7838 we can just fall through to the REG+DISP case below. Otherwise
7839 we have to use a combination of REG and PRE_DEC addressing... */
7840 if (! arith_reg_operand (operands[0], SFmode))
7842 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
7843 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7845 operands[0] = copy_rtx (operands[0]);
7846 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
7848 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7849 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7855 /* Since REG+DISP addressing has already been decided upon by gcc
7856 we can rely upon it having chosen an arithmetic register as the
7857 register component of the address. Just emit the lower numbered
7858 register first, to the lower address, then the higher numbered
7859 register to the higher address. */
7860 emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7862 operands[0] = copy_rtx (operands[0]);
7863 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
7865 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7869 /* This is easy. Output the word to go to the higher address
7870 first (ie the word in the higher numbered register) then the
7871 word to go to the lower address. */
7873 insn = emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7874 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7876 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
7877 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7889 ;; If the output is a register and the input is memory or a register, we have
7890 ;; to be careful and see which word needs to be loaded first.
7892 [(set (match_operand:DF 0 "general_movdst_operand" "")
7893 (match_operand:DF 1 "general_movsrc_operand" ""))]
7894 "TARGET_SH1 && reload_completed"
7895 [(set (match_dup 2) (match_dup 3))
7896 (set (match_dup 4) (match_dup 5))]
7900 if ((MEM_P (operands[0])
7901 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7902 || (MEM_P (operands[1])
7903 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7906 switch (GET_CODE (operands[0]))
7909 regno = REGNO (operands[0]);
7912 regno = subreg_regno (operands[0]);
7922 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7924 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
7925 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
7926 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
7927 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
7931 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
7932 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
7933 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
7934 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
7937 if (operands[2] == 0 || operands[3] == 0
7938 || operands[4] == 0 || operands[5] == 0)
7942 (define_expand "movdf"
7943 [(set (match_operand:DF 0 "general_movdst_operand" "")
7944 (match_operand:DF 1 "general_movsrc_operand" ""))]
7947 prepare_move_operands (operands, DFmode);
7950 if (TARGET_SHMEDIA_FPU)
7951 emit_insn (gen_movdf_media (operands[0], operands[1]));
7953 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
7956 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
7958 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
7963 ;;This is incompatible with the way gcc uses subregs.
7964 ;;(define_insn "movv2sf_i"
7965 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
7966 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
7967 ;; "TARGET_SHMEDIA_FPU
7968 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
7969 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
7973 ;; fst%M0.p %m0, %1"
7974 ;; [(set_attr "type" "*,fload_media,fstore_media")])
7975 (define_insn_and_split "movv2sf_i"
7976 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
7977 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
7978 "TARGET_SHMEDIA_FPU"
7980 "TARGET_SHMEDIA_FPU && reload_completed"
7981 [(set (match_dup 0) (match_dup 1))]
7983 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
7984 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
7987 (define_expand "movv2sf"
7988 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
7989 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
7990 "TARGET_SHMEDIA_FPU"
7992 prepare_move_operands (operands, V2SFmode);
7995 (define_expand "addv2sf3"
7996 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
7997 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
7998 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
7999 "TARGET_SHMEDIA_FPU"
8001 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8005 (define_expand "subv2sf3"
8006 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8007 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8008 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8009 "TARGET_SHMEDIA_FPU"
8011 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8015 (define_expand "mulv2sf3"
8016 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8017 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8018 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8019 "TARGET_SHMEDIA_FPU"
8021 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8025 (define_expand "divv2sf3"
8026 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8027 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8028 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8029 "TARGET_SHMEDIA_FPU"
8031 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8035 (define_insn_and_split "*movv4sf_i"
8036 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8037 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8038 "TARGET_SHMEDIA_FPU"
8040 "&& reload_completed"
8043 for (int i = 0; i < 4/2; i++)
8047 if (MEM_P (operands[0]))
8048 x = adjust_address (operands[0], V2SFmode,
8049 i * GET_MODE_SIZE (V2SFmode));
8051 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8053 if (MEM_P (operands[1]))
8054 y = adjust_address (operands[1], V2SFmode,
8055 i * GET_MODE_SIZE (V2SFmode));
8057 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8059 emit_insn (gen_movv2sf_i (x, y));
8064 [(set_attr "length" "8")])
8066 (define_expand "movv4sf"
8067 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8068 (match_operand:V4SF 1 "general_operand" ""))]
8069 "TARGET_SHMEDIA_FPU"
8071 prepare_move_operands (operands, V4SFmode);
8074 (define_insn_and_split "*movv16sf_i"
8075 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8076 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8077 "TARGET_SHMEDIA_FPU"
8079 "&& reload_completed"
8082 for (int i = 0; i < 16/2; i++)
8086 if (MEM_P (operands[0]))
8087 x = adjust_address (operands[0], V2SFmode,
8088 i * GET_MODE_SIZE (V2SFmode));
8091 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8092 alter_subreg (&x, true);
8095 if (MEM_P (operands[1]))
8096 y = adjust_address (operands[1], V2SFmode,
8097 i * GET_MODE_SIZE (V2SFmode));
8100 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8101 alter_subreg (&y, true);
8104 emit_insn (gen_movv2sf_i (x, y));
8109 [(set_attr "length" "32")])
8111 (define_expand "movv16sf"
8112 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8113 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8114 "TARGET_SHMEDIA_FPU"
8116 prepare_move_operands (operands, V16SFmode);
8119 (define_insn "movsf_media"
8120 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8121 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8123 && (register_operand (operands[0], SFmode)
8124 || sh_register_operand (operands[1], SFmode))"
8135 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8136 (set (attr "highpart")
8137 (cond [(match_test "sh_contains_memref_p (insn)")
8138 (const_string "user")]
8139 (const_string "ignore")))])
8141 (define_insn "movsf_media_nofpu"
8142 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8143 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8145 && (register_operand (operands[0], SFmode)
8146 || sh_register_operand (operands[1], SFmode))"
8152 [(set_attr "type" "arith_media,*,load_media,store_media")
8153 (set (attr "highpart")
8154 (cond [(match_test "sh_contains_memref_p (insn)")
8155 (const_string "user")]
8156 (const_string "ignore")))])
8159 [(set (match_operand:SF 0 "arith_reg_dest" "")
8160 (match_operand:SF 1 "immediate_operand" ""))]
8161 "TARGET_SHMEDIA && reload_completed
8162 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8163 [(set (match_dup 3) (match_dup 2))]
8166 REAL_VALUE_TYPE value;
8168 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8169 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8170 operands[2] = GEN_INT (values);
8172 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8175 (define_insn "movsf_i"
8176 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8177 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8180 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8181 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8182 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8183 && (arith_reg_operand (operands[0], SFmode)
8184 || arith_reg_operand (operands[1], SFmode))"
8193 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8195 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8196 ;; update_flow_info would not know where to put REG_EQUAL notes
8197 ;; when the destination changes mode.
8198 (define_insn "movsf_ie"
8199 [(set (match_operand:SF 0 "general_movdst_operand"
8200 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8201 (match_operand:SF 1 "general_movsrc_operand"
8202 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8203 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
8204 (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8206 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8207 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8208 || arith_reg_operand (operands[3], SImode))"
8228 ! move optimized away"
8229 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8230 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8231 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8232 (set_attr_alternative "length"
8239 (match_test "TARGET_SH2A")
8240 (const_int 4) (const_int 2))
8242 (match_test "TARGET_SH2A")
8243 (const_int 4) (const_int 2))
8246 (match_test "TARGET_SH2A")
8247 (const_int 4) (const_int 2))
8249 (match_test "TARGET_SH2A")
8250 (const_int 4) (const_int 2))
8260 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
8261 (const_string "single")
8262 (const_string "single")))])
8265 [(set (match_operand:SF 0 "register_operand" "")
8266 (match_operand:SF 1 "register_operand" ""))
8267 (use (match_operand:PSI 2 "fpscr_operand" ""))
8268 (clobber (reg:SI FPUL_REG))]
8270 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8272 (clobber (scratch:SI))])
8273 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8275 (clobber (scratch:SI))])]
8278 (define_expand "movsf"
8279 [(set (match_operand:SF 0 "general_movdst_operand" "")
8280 (match_operand:SF 1 "general_movsrc_operand" ""))]
8283 prepare_move_operands (operands, SFmode);
8286 if (TARGET_SHMEDIA_FPU)
8287 emit_insn (gen_movsf_media (operands[0], operands[1]));
8289 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8294 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
8299 (define_insn "mov_nop"
8300 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8303 [(set_attr "length" "0")
8304 (set_attr "type" "nil")])
8306 (define_expand "reload_insf__frn"
8307 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8308 (match_operand:SF 1 "immediate_operand" "FQ"))
8309 (use (reg:PSI FPSCR_REG))
8310 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8314 (define_expand "reload_insi__i_fpul"
8315 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8316 (match_operand:SI 1 "immediate_operand" "i"))
8317 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8321 (define_expand "ptabs"
8322 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8325 if (!TARGET_PT_FIXED)
8327 rtx eq = operands[1];
8329 /* ??? For canonical RTL we really should remove any CONST from EQ
8330 before wrapping it in the AND, and finally wrap the EQ into a
8331 const if is constant. However, for reload we must expose the
8332 input register or symbolic constant, and we can't have
8333 different insn structures outside of the operands for different
8334 alternatives of the same pattern. */
8335 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8338 = (gen_rtx_IF_THEN_ELSE
8341 gen_rtx_MEM (PDImode, operands[1]),
8342 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8343 PDImode, operands[1])));
8347 ;; expanded by ptabs expander.
8348 (define_insn "*extendsipdi_media"
8349 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8350 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8354 (mem:PDI (match_dup 1))
8355 (sign_extend:PDI (match_dup 1))))]
8356 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8360 [(set_attr "type" "ptabs_media,pt_media")
8361 (set_attr "length" "4,*")])
8363 (define_insn "*truncdipdi_media"
8364 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8365 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8369 (mem:PDI (match_dup 1))
8370 (truncate:PDI (match_dup 1))))]
8371 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8375 [(set_attr "type" "ptabs_media,pt_media")
8376 (set_attr "length" "4,*")])
8378 (define_insn "*movsi_y"
8379 [(set (match_operand:SI 0 "register_operand" "=y,y")
8380 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8381 (clobber (match_scratch:SI 2 "=&z,r"))]
8383 && (reload_in_progress || reload_completed)"
8385 [(set_attr "length" "4")
8386 (set_attr "type" "pcload,move")])
8389 [(set (match_operand:SI 0 "register_operand" "")
8390 (match_operand:SI 1 "immediate_operand" ""))
8391 (clobber (match_operand:SI 2 "register_operand" ""))]
8393 [(set (match_dup 2) (match_dup 1))
8394 (set (match_dup 0) (match_dup 2))]
8397 ;; ------------------------------------------------------------------------
8398 ;; Define the real conditional branch instructions.
8399 ;; ------------------------------------------------------------------------
8401 (define_expand "branch_true"
8402 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
8403 (label_ref (match_operand 0))
8407 (define_expand "branch_false"
8408 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8409 (label_ref (match_operand 0))
8413 (define_insn_and_split "*cbranch_t"
8414 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
8415 (label_ref (match_operand 0))
8419 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
8422 [(set (pc) (if_then_else (eq (reg:SI T_REG) (match_dup 2))
8423 (label_ref (match_dup 0))
8426 /* Try to find missed test and branch combine opportunities which result
8427 in redundant T bit tests before conditional branches.
8428 This is done not only after combine (and before reload) but in every
8429 split pass, because some opportunities are formed also after combine.
8430 FIXME: Probably this would not be needed if CCmode was used
8431 together with TARGET_FIXED_CONDITION_CODE_REGS. */
8433 const int treg_value = sh_eval_treg_value (operands[1]);
8434 operands[2] = NULL_RTX;
8436 /* Scan the insns backwards for an insn that sets the T bit by testing a
8437 reg against zero like:
8438 (set (reg T_REG) (eq (reg) (const_int 0))) */
8439 rtx testing_insn = NULL_RTX;
8440 rtx tested_reg = NULL_RTX;
8442 set_of_reg s0 = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn,
8443 prev_nonnote_insn_bb);
8444 if (s0.set_src != NULL_RTX
8445 && GET_CODE (s0.set_src) == EQ
8446 && REG_P (XEXP (s0.set_src, 0))
8447 && satisfies_constraint_Z (XEXP (s0.set_src, 1)))
8449 testing_insn = s0.insn;
8450 tested_reg = XEXP (s0.set_src, 0);
8455 /* Continue scanning the insns backwards and try to find the insn that
8456 sets the tested reg which we found above. If the reg is set by storing
8457 the T bit or the negated T bit we can eliminate the test insn before
8458 the branch. Notice that the branch condition has to be inverted if the
8459 test is eliminated. */
8461 /* If the T bit is used between the testing insn and the brach insn
8463 if (reg_used_between_p (get_t_reg_rtx (), testing_insn, curr_insn))
8468 /* It's not safe to go beyond the current basic block after reload. */
8469 set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn,
8471 ? prev_nonnote_insn_bb
8472 : prev_nonnote_insn);
8473 if (s1.set_src == NULL_RTX)
8476 if (t_reg_operand (s1.set_src, VOIDmode))
8477 operands[2] = GEN_INT (treg_value ^ 1);
8478 else if (negt_reg_operand (s1.set_src, VOIDmode))
8479 operands[2] = GEN_INT (treg_value);
8480 else if (REG_P (s1.set_src))
8482 /* If it's a reg-reg copy follow the copied reg. This can
8483 happen e.g. when T bit store zero-extensions are
8485 tested_reg = s1.set_src;
8490 /* It's only safe to remove the testing insn if the T bit is not
8491 modified between the testing insn and the insn that stores the
8492 T bit. Notice that some T bit stores such as negc also modify
8494 if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)
8495 || modified_in_p (get_t_reg_rtx (), s1.insn))
8496 operands[2] = NULL_RTX;
8501 if (operands[2] == NULL_RTX)
8504 set_insn_deleted (testing_insn);
8506 [(set_attr "type" "cbranch")])
8508 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
8509 ;; which destination is too far away.
8510 ;; The const_int_operand is distinct for each branch target; it avoids
8511 ;; unwanted matches with redundant_insn.
8512 (define_insn "block_branch_redirect"
8513 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
8516 [(set_attr "length" "0")])
8518 ;; This one has the additional purpose to record a possible scratch register
8519 ;; for the following branch.
8520 ;; ??? Unfortunately, just setting the scratch register is not good enough,
8521 ;; because the insn then might be deemed dead and deleted. And we can't
8522 ;; make the use in the jump insn explicit because that would disable
8523 ;; delay slot scheduling from the target.
8524 (define_insn "indirect_jump_scratch"
8525 [(set (match_operand:SI 0 "register_operand" "=r")
8526 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
8527 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
8530 [(set_attr "length" "0")])
8532 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
8533 ;; being pulled into the delay slot of a condbranch that has been made to
8534 ;; jump around the unconditional jump because it was out of range.
8535 (define_insn "stuff_delay_slot"
8537 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
8538 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
8541 [(set_attr "length" "0")
8542 (set_attr "cond_delay_slot" "yes")])
8544 ;; Conditional branch insns
8546 (define_expand "cbranchint4_media"
8548 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
8549 [(match_operand 1 "" "")
8550 (match_operand 2 "" "")])
8551 (match_operand 3 "" "")
8555 enum machine_mode mode = GET_MODE (operands[1]);
8556 if (mode == VOIDmode)
8557 mode = GET_MODE (operands[2]);
8558 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
8560 operands[1] = force_reg (mode, operands[1]);
8561 if (CONSTANT_P (operands[2])
8562 && (! satisfies_constraint_I06 (operands[2])))
8563 operands[2] = force_reg (mode, operands[2]);
8567 if (operands[1] != const0_rtx)
8568 operands[1] = force_reg (mode, operands[1]);
8569 if (operands[2] != const0_rtx)
8570 operands[2] = force_reg (mode, operands[2]);
8572 switch (GET_CODE (operands[0]))
8578 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
8579 VOIDmode, operands[2], operands[1]);
8580 operands[1] = XEXP (operands[0], 0);
8581 operands[2] = XEXP (operands[0], 1);
8584 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
8585 VOIDmode, operands[1], operands[2]);
8588 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8591 (define_expand "cbranchfp4_media"
8593 (if_then_else (match_operator 0 "sh_float_comparison_operator"
8594 [(match_operand 1 "" "")
8595 (match_operand 2 "" "")])
8596 (match_operand 3 "" "")
8600 rtx tmp = gen_reg_rtx (SImode);
8602 if (GET_CODE (operands[0]) == NE)
8603 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
8605 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
8606 operands[1], operands[2]);
8608 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
8610 if (GET_CODE (cmp) == GET_CODE (operands[0]))
8611 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
8613 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8615 operands[2] = const0_rtx;
8616 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8619 (define_insn "*beq_media_i"
8621 (if_then_else (match_operator 3 "equality_comparison_operator"
8622 [(match_operand:DI 1 "arith_reg_operand" "r,r")
8623 (match_operand:DI 2 "arith_operand" "r,I06")])
8624 (match_operand 0 "target_operand" "b,b")
8629 b%o3i%' %1, %2, %0%>"
8630 [(set_attr "type" "cbranch_media")])
8632 (define_insn "*beq_media_i32"
8634 (if_then_else (match_operator 3 "equality_comparison_operator"
8635 [(match_operand:SI 1 "arith_reg_operand" "r,r")
8636 (match_operand:SI 2 "arith_operand" "r,I06")])
8637 (match_operand 0 "target_operand" "b,b")
8642 b%o3i%' %1, %2, %0%>"
8643 [(set_attr "type" "cbranch_media")])
8645 (define_insn "*bgt_media_i"
8647 (if_then_else (match_operator 3 "greater_comparison_operator"
8648 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8649 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8650 (match_operand 0 "target_operand" "b")
8653 "b%o3%' %N1, %N2, %0%>"
8654 [(set_attr "type" "cbranch_media")])
8656 (define_insn "*bgt_media_i32"
8658 (if_then_else (match_operator 3 "greater_comparison_operator"
8659 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8660 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8661 (match_operand 0 "target_operand" "b")
8664 "b%o3%' %N1, %N2, %0%>"
8665 [(set_attr "type" "cbranch_media")])
8667 ;; These are only needed to make invert_jump() happy - otherwise, jump
8668 ;; optimization will be silently disabled.
8669 (define_insn "*blt_media_i"
8671 (if_then_else (match_operator 3 "less_comparison_operator"
8672 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8673 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8674 (match_operand 0 "target_operand" "b")
8677 "b%o3%' %N2, %N1, %0%>"
8678 [(set_attr "type" "cbranch_media")])
8680 (define_insn "*blt_media_i32"
8682 (if_then_else (match_operator 3 "less_comparison_operator"
8683 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8684 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8685 (match_operand 0 "target_operand" "b")
8688 "b%o3%' %N2, %N1, %0%>"
8689 [(set_attr "type" "cbranch_media")])
8691 ;; combiner splitter for test-and-branch on single bit in register. This
8692 ;; is endian dependent because the non-paradoxical subreg looks different
8697 (match_operator 3 "equality_comparison_operator"
8700 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
8702 (match_operand 2 "const_int_operand" "")) 0)
8704 (match_operand 0 "target_operand" "")
8706 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
8707 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
8708 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
8709 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
8711 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
8712 operands[6] = (GET_CODE (operands[3]) == EQ
8713 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
8714 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
8717 ; operand 0 is the loop count pseudo register
8718 ; operand 1 is the number of loop iterations or 0 if it is unknown
8719 ; operand 2 is the maximum number of loop iterations
8720 ; operand 3 is the number of levels of enclosed loops
8721 ; operand 4 is the label to jump to at the top of the loop
8722 (define_expand "doloop_end"
8723 [(parallel [(set (pc)
8724 (if_then_else (ne:SI (match_operand:SI 0 "" "")
8726 (label_ref (match_operand 4 "" ""))
8729 (plus:SI (match_dup 0) (const_int -1)))
8730 (clobber (reg:SI T_REG))])
8731 (match_operand 5 "" "")]
8734 if (GET_MODE (operands[0]) != SImode)
8736 emit_jump_insn (gen_doloop_end_split (operands[0], operands[4], operands[0]));
8740 (define_insn_and_split "doloop_end_split"
8742 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
8744 (label_ref (match_operand 1 "" ""))
8746 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8747 (plus (match_dup 2) (const_int -1)))
8748 (clobber (reg:SI T_REG))]
8752 [(parallel [(set (reg:SI T_REG)
8753 (eq:SI (match_dup 2) (const_int 1)))
8754 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
8755 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8756 (label_ref (match_dup 1))
8759 [(set_attr "type" "cbranch")])
8761 ;; ------------------------------------------------------------------------
8762 ;; Jump and linkage insns
8763 ;; ------------------------------------------------------------------------
8765 (define_insn "jump_compact"
8767 (label_ref (match_operand 0 "" "")))]
8768 "TARGET_SH1 && !find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)"
8770 /* The length is 16 if the delay slot is unfilled. */
8771 if (get_attr_length(insn) > 4)
8772 return output_far_jump(insn, operands[0]);
8776 [(set_attr "type" "jump")
8777 (set_attr "needs_delay_slot" "yes")])
8779 ;; ??? It would be much saner to explicitly use the scratch register
8780 ;; in the jump insn, and have indirect_jump_scratch only set it,
8781 ;; but fill_simple_delay_slots would refuse to do delay slot filling
8782 ;; from the target then, as it uses simplejump_p.
8783 ;;(define_insn "jump_compact_far"
8785 ;; (label_ref (match_operand 0 "" "")))
8786 ;; (use (match_operand 1 "register_operand" "r")]
8788 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
8789 ;; [(set_attr "type" "jump")
8790 ;; (set_attr "needs_delay_slot" "yes")])
8792 (define_insn "jump_media"
8794 (match_operand 0 "target_operand" "b"))]
8797 [(set_attr "type" "jump_media")])
8799 (define_expand "jump"
8801 (label_ref (match_operand 0 "" "")))]
8805 emit_jump_insn (gen_jump_compact (operands[0]));
8806 else if (TARGET_SHMEDIA)
8808 if (reload_in_progress || reload_completed)
8810 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
8815 (define_insn "force_mode_for_call"
8816 [(use (reg:PSI FPSCR_REG))]
8819 [(set_attr "length" "0")
8820 (set (attr "fp_mode")
8821 (if_then_else (eq_attr "fpu_single" "yes")
8822 (const_string "single") (const_string "double")))])
8824 (define_insn "calli"
8825 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8826 (match_operand 1 "" ""))
8827 (use (reg:PSI FPSCR_REG))
8828 (clobber (reg:SI PR_REG))]
8831 if (TARGET_SH2A && (dbr_sequence_length () == 0))
8836 [(set_attr "type" "call")
8837 (set (attr "fp_mode")
8838 (if_then_else (eq_attr "fpu_single" "yes")
8839 (const_string "single") (const_string "double")))
8840 (set_attr "needs_delay_slot" "yes")
8841 (set_attr "fp_set" "unknown")])
8843 ;; This is TBR relative jump instruction for SH2A architecture.
8844 ;; Its use is enabled by assigning an attribute "function_vector"
8845 ;; and the vector number to a function during its declaration.
8846 (define_insn "calli_tbr_rel"
8847 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
8848 (match_operand 1 "" ""))
8849 (use (reg:PSI FPSCR_REG))
8850 (clobber (reg:SI PR_REG))]
8851 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
8853 unsigned HOST_WIDE_INT vect_num;
8854 vect_num = sh2a_get_function_vector_number (operands[0]);
8855 operands[2] = GEN_INT (vect_num * 4);
8857 return "jsr/n @@(%O2,tbr)";
8859 [(set_attr "type" "call")
8860 (set (attr "fp_mode")
8861 (if_then_else (eq_attr "fpu_single" "yes")
8862 (const_string "single") (const_string "double")))
8863 (set_attr "needs_delay_slot" "no")
8864 (set_attr "fp_set" "unknown")])
8866 ;; This is a pc-rel call, using bsrf, for use with PIC.
8867 (define_insn "calli_pcrel"
8868 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8869 (match_operand 1 "" ""))
8870 (use (reg:PSI FPSCR_REG))
8871 (use (reg:SI PIC_REG))
8872 (use (match_operand 2 "" ""))
8873 (clobber (reg:SI PR_REG))]
8876 return "bsrf %0" "\n"
8879 [(set_attr "type" "call")
8880 (set (attr "fp_mode")
8881 (if_then_else (eq_attr "fpu_single" "yes")
8882 (const_string "single") (const_string "double")))
8883 (set_attr "needs_delay_slot" "yes")
8884 (set_attr "fp_set" "unknown")])
8886 (define_insn_and_split "call_pcrel"
8887 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
8888 (match_operand 1 "" ""))
8889 (use (reg:PSI FPSCR_REG))
8890 (use (reg:SI PIC_REG))
8891 (clobber (reg:SI PR_REG))
8892 (clobber (match_scratch:SI 2 "=r"))]
8898 rtx lab = PATTERN (gen_call_site ());
8900 if (SYMBOL_REF_LOCAL_P (operands[0]))
8901 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
8903 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
8904 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
8907 [(set_attr "type" "call")
8908 (set (attr "fp_mode")
8909 (if_then_else (eq_attr "fpu_single" "yes")
8910 (const_string "single") (const_string "double")))
8911 (set_attr "needs_delay_slot" "yes")
8912 (set_attr "fp_set" "unknown")])
8914 (define_insn "call_compact"
8915 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8916 (match_operand 1 "" ""))
8917 (match_operand 2 "immediate_operand" "n")
8918 (use (reg:SI R0_REG))
8919 (use (reg:SI R1_REG))
8920 (use (reg:PSI FPSCR_REG))
8921 (clobber (reg:SI PR_REG))]
8922 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
8924 [(set_attr "type" "call")
8925 (set (attr "fp_mode")
8926 (if_then_else (eq_attr "fpu_single" "yes")
8927 (const_string "single") (const_string "double")))
8928 (set_attr "needs_delay_slot" "yes")])
8930 (define_insn "call_compact_rettramp"
8931 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8932 (match_operand 1 "" ""))
8933 (match_operand 2 "immediate_operand" "n")
8934 (use (reg:SI R0_REG))
8935 (use (reg:SI R1_REG))
8936 (use (reg:PSI FPSCR_REG))
8937 (clobber (reg:SI R10_REG))
8938 (clobber (reg:SI PR_REG))]
8939 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
8941 [(set_attr "type" "call")
8942 (set (attr "fp_mode")
8943 (if_then_else (eq_attr "fpu_single" "yes")
8944 (const_string "single") (const_string "double")))
8945 (set_attr "needs_delay_slot" "yes")])
8947 (define_insn "call_media"
8948 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
8949 (match_operand 1 "" ""))
8950 (clobber (reg:DI PR_MEDIA_REG))]
8953 [(set_attr "type" "jump_media")])
8955 (define_insn "call_valuei"
8956 [(set (match_operand 0 "" "=rf")
8957 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
8958 (match_operand 2 "" "")))
8959 (use (reg:PSI FPSCR_REG))
8960 (clobber (reg:SI PR_REG))]
8963 if (TARGET_SH2A && (dbr_sequence_length () == 0))
8968 [(set_attr "type" "call")
8969 (set (attr "fp_mode")
8970 (if_then_else (eq_attr "fpu_single" "yes")
8971 (const_string "single") (const_string "double")))
8972 (set_attr "needs_delay_slot" "yes")
8973 (set_attr "fp_set" "unknown")])
8975 ;; This is TBR relative jump instruction for SH2A architecture.
8976 ;; Its use is enabled by assigning an attribute "function_vector"
8977 ;; and the vector number to a function during its declaration.
8978 (define_insn "call_valuei_tbr_rel"
8979 [(set (match_operand 0 "" "=rf")
8980 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
8981 (match_operand 2 "" "")))
8982 (use (reg:PSI FPSCR_REG))
8983 (clobber (reg:SI PR_REG))]
8984 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
8986 unsigned HOST_WIDE_INT vect_num;
8987 vect_num = sh2a_get_function_vector_number (operands[1]);
8988 operands[3] = GEN_INT (vect_num * 4);
8990 return "jsr/n @@(%O3,tbr)";
8992 [(set_attr "type" "call")
8993 (set (attr "fp_mode")
8994 (if_then_else (eq_attr "fpu_single" "yes")
8995 (const_string "single") (const_string "double")))
8996 (set_attr "needs_delay_slot" "no")
8997 (set_attr "fp_set" "unknown")])
8999 (define_insn "call_valuei_pcrel"
9000 [(set (match_operand 0 "" "=rf")
9001 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9002 (match_operand 2 "" "")))
9003 (use (reg:PSI FPSCR_REG))
9004 (use (reg:SI PIC_REG))
9005 (use (match_operand 3 "" ""))
9006 (clobber (reg:SI PR_REG))]
9009 return "bsrf %1" "\n"
9012 [(set_attr "type" "call")
9013 (set (attr "fp_mode")
9014 (if_then_else (eq_attr "fpu_single" "yes")
9015 (const_string "single") (const_string "double")))
9016 (set_attr "needs_delay_slot" "yes")
9017 (set_attr "fp_set" "unknown")])
9019 (define_insn_and_split "call_value_pcrel"
9020 [(set (match_operand 0 "" "=rf")
9021 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9022 (match_operand 2 "" "")))
9023 (use (reg:PSI FPSCR_REG))
9024 (use (reg:SI PIC_REG))
9025 (clobber (reg:SI PR_REG))
9026 (clobber (match_scratch:SI 3 "=r"))]
9032 rtx lab = PATTERN (gen_call_site ());
9034 if (SYMBOL_REF_LOCAL_P (operands[1]))
9035 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9037 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9038 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9039 operands[2], copy_rtx (lab)));
9042 [(set_attr "type" "call")
9043 (set (attr "fp_mode")
9044 (if_then_else (eq_attr "fpu_single" "yes")
9045 (const_string "single") (const_string "double")))
9046 (set_attr "needs_delay_slot" "yes")
9047 (set_attr "fp_set" "unknown")])
9049 (define_insn "call_value_compact"
9050 [(set (match_operand 0 "" "=rf")
9051 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9052 (match_operand 2 "" "")))
9053 (match_operand 3 "immediate_operand" "n")
9054 (use (reg:SI R0_REG))
9055 (use (reg:SI R1_REG))
9056 (use (reg:PSI FPSCR_REG))
9057 (clobber (reg:SI PR_REG))]
9058 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9060 [(set_attr "type" "call")
9061 (set (attr "fp_mode")
9062 (if_then_else (eq_attr "fpu_single" "yes")
9063 (const_string "single") (const_string "double")))
9064 (set_attr "needs_delay_slot" "yes")])
9066 (define_insn "call_value_compact_rettramp"
9067 [(set (match_operand 0 "" "=rf")
9068 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9069 (match_operand 2 "" "")))
9070 (match_operand 3 "immediate_operand" "n")
9071 (use (reg:SI R0_REG))
9072 (use (reg:SI R1_REG))
9073 (use (reg:PSI FPSCR_REG))
9074 (clobber (reg:SI R10_REG))
9075 (clobber (reg:SI PR_REG))]
9076 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9078 [(set_attr "type" "call")
9079 (set (attr "fp_mode")
9080 (if_then_else (eq_attr "fpu_single" "yes")
9081 (const_string "single") (const_string "double")))
9082 (set_attr "needs_delay_slot" "yes")])
9084 (define_insn "call_value_media"
9085 [(set (match_operand 0 "" "=rf")
9086 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9087 (match_operand 2 "" "")))
9088 (clobber (reg:DI PR_MEDIA_REG))]
9091 [(set_attr "type" "jump_media")])
9093 (define_expand "call"
9094 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9095 (match_operand 1 "" ""))
9096 (match_operand 2 "" "")
9097 (use (reg:PSI FPSCR_REG))
9098 (clobber (reg:SI PR_REG))])]
9103 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9104 emit_call_insn (gen_call_media (operands[0], operands[1]));
9107 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9109 rtx cookie_rtx = operands[2];
9110 long cookie = INTVAL (cookie_rtx);
9111 rtx func = XEXP (operands[0], 0);
9116 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9118 rtx reg = gen_reg_rtx (Pmode);
9120 emit_insn (gen_symGOTPLT2reg (reg, func));
9124 func = legitimize_pic_address (func, Pmode, 0);
9127 r0 = gen_rtx_REG (SImode, R0_REG);
9128 r1 = gen_rtx_REG (SImode, R1_REG);
9130 /* Since such a call function may use all call-clobbered
9131 registers, we force a mode switch earlier, so that we don't
9132 run out of registers when adjusting fpscr for the call. */
9133 emit_insn (gen_force_mode_for_call ());
9136 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9137 operands[0] = force_reg (SImode, operands[0]);
9139 emit_move_insn (r0, func);
9140 emit_move_insn (r1, cookie_rtx);
9142 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9143 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9146 emit_call_insn (gen_call_compact (operands[0], operands[1],
9151 else if (TARGET_SHCOMPACT && flag_pic
9152 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9153 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9155 rtx reg = gen_reg_rtx (Pmode);
9157 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9158 XEXP (operands[0], 0) = reg;
9160 if (!flag_pic && TARGET_SH2A
9161 && MEM_P (operands[0])
9162 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9164 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9166 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9171 if (flag_pic && TARGET_SH2
9172 && MEM_P (operands[0])
9173 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9175 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9180 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9181 operands[1] = operands[2];
9184 emit_call_insn (gen_calli (operands[0], operands[1]));
9188 (define_insn "call_pop_compact"
9189 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9190 (match_operand 1 "" ""))
9191 (match_operand 2 "immediate_operand" "n")
9192 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9193 (match_operand 3 "immediate_operand" "n")))
9194 (use (reg:SI R0_REG))
9195 (use (reg:SI R1_REG))
9196 (use (reg:PSI FPSCR_REG))
9197 (clobber (reg:SI PR_REG))]
9198 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9200 [(set_attr "type" "call")
9201 (set (attr "fp_mode")
9202 (if_then_else (eq_attr "fpu_single" "yes")
9203 (const_string "single") (const_string "double")))
9204 (set_attr "needs_delay_slot" "yes")])
9206 (define_insn "call_pop_compact_rettramp"
9207 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9208 (match_operand 1 "" ""))
9209 (match_operand 2 "immediate_operand" "n")
9210 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9211 (match_operand 3 "immediate_operand" "n")))
9212 (use (reg:SI R0_REG))
9213 (use (reg:SI R1_REG))
9214 (use (reg:PSI FPSCR_REG))
9215 (clobber (reg:SI R10_REG))
9216 (clobber (reg:SI PR_REG))]
9217 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9219 [(set_attr "type" "call")
9220 (set (attr "fp_mode")
9221 (if_then_else (eq_attr "fpu_single" "yes")
9222 (const_string "single") (const_string "double")))
9223 (set_attr "needs_delay_slot" "yes")])
9225 (define_expand "call_pop"
9226 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9227 (match_operand 1 "" ""))
9228 (match_operand 2 "" "")
9229 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9230 (match_operand 3 "" "")))])]
9238 gcc_assert (operands[2] && INTVAL (operands[2]));
9239 cookie_rtx = operands[2];
9240 cookie = INTVAL (cookie_rtx);
9241 func = XEXP (operands[0], 0);
9245 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9247 rtx reg = gen_reg_rtx (Pmode);
9248 emit_insn (gen_symGOTPLT2reg (reg, func));
9252 func = legitimize_pic_address (func, Pmode, 0);
9255 r0 = gen_rtx_REG (SImode, R0_REG);
9256 r1 = gen_rtx_REG (SImode, R1_REG);
9258 /* Since such a call function may use all call-clobbered
9259 registers, we force a mode switch earlier, so that we don't
9260 run out of registers when adjusting fpscr for the call. */
9261 emit_insn (gen_force_mode_for_call ());
9263 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9265 operands[0] = force_reg (SImode, operands[0]);
9267 emit_move_insn (r0, func);
9268 emit_move_insn (r1, cookie_rtx);
9270 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9271 emit_call_insn (gen_call_pop_compact_rettramp
9272 (operands[0], operands[1], operands[2], operands[3]));
9274 emit_call_insn (gen_call_pop_compact
9275 (operands[0], operands[1], operands[2], operands[3]));
9280 (define_expand "call_value"
9281 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9282 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9283 (match_operand 2 "" "")))
9284 (match_operand 3 "" "")
9285 (use (reg:PSI FPSCR_REG))
9286 (clobber (reg:SI PR_REG))])]
9291 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9292 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9296 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9298 rtx cookie_rtx = operands[3];
9299 long cookie = INTVAL (cookie_rtx);
9300 rtx func = XEXP (operands[1], 0);
9305 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9307 rtx reg = gen_reg_rtx (Pmode);
9309 emit_insn (gen_symGOTPLT2reg (reg, func));
9313 func = legitimize_pic_address (func, Pmode, 0);
9316 r0 = gen_rtx_REG (SImode, R0_REG);
9317 r1 = gen_rtx_REG (SImode, R1_REG);
9319 /* Since such a call function may use all call-clobbered
9320 registers, we force a mode switch earlier, so that we don't
9321 run out of registers when adjusting fpscr for the call. */
9322 emit_insn (gen_force_mode_for_call ());
9325 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9326 operands[1] = force_reg (SImode, operands[1]);
9328 emit_move_insn (r0, func);
9329 emit_move_insn (r1, cookie_rtx);
9331 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9332 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9337 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9338 operands[2], operands[3]));
9342 else if (TARGET_SHCOMPACT && flag_pic
9343 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9344 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9346 rtx reg = gen_reg_rtx (Pmode);
9348 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9349 XEXP (operands[1], 0) = reg;
9351 if (!flag_pic && TARGET_SH2A
9352 && MEM_P (operands[1])
9353 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9355 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9357 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9358 XEXP (operands[1], 0), operands[2]));
9362 if (flag_pic && TARGET_SH2
9363 && MEM_P (operands[1])
9364 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9366 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9371 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9373 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9377 (define_insn "sibcalli"
9378 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9379 (match_operand 1 "" ""))
9380 (use (reg:PSI FPSCR_REG))
9384 [(set_attr "needs_delay_slot" "yes")
9385 (set (attr "fp_mode")
9386 (if_then_else (eq_attr "fpu_single" "yes")
9387 (const_string "single") (const_string "double")))
9388 (set_attr "type" "jump_ind")])
9390 (define_insn "sibcalli_pcrel"
9391 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9392 (match_operand 1 "" ""))
9393 (use (match_operand 2 "" ""))
9394 (use (reg:PSI FPSCR_REG))
9398 return "braf %0" "\n"
9401 [(set_attr "needs_delay_slot" "yes")
9402 (set (attr "fp_mode")
9403 (if_then_else (eq_attr "fpu_single" "yes")
9404 (const_string "single") (const_string "double")))
9405 (set_attr "type" "jump_ind")])
9407 ;; This uses an unspec to describe that the symbol_ref is very close.
9408 (define_insn "sibcalli_thunk"
9409 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9411 (match_operand 1 "" ""))
9412 (use (reg:PSI FPSCR_REG))
9416 [(set_attr "needs_delay_slot" "yes")
9417 (set (attr "fp_mode")
9418 (if_then_else (eq_attr "fpu_single" "yes")
9419 (const_string "single") (const_string "double")))
9420 (set_attr "type" "jump")
9421 (set_attr "length" "2")])
9423 (define_insn_and_split "sibcall_pcrel"
9424 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9425 (match_operand 1 "" ""))
9426 (use (reg:PSI FPSCR_REG))
9427 (clobber (match_scratch:SI 2 "=k"))
9434 rtx lab = PATTERN (gen_call_site ());
9437 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9438 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9440 SIBLING_CALL_P (call_insn) = 1;
9443 [(set_attr "needs_delay_slot" "yes")
9444 (set (attr "fp_mode")
9445 (if_then_else (eq_attr "fpu_single" "yes")
9446 (const_string "single") (const_string "double")))
9447 (set_attr "type" "jump_ind")])
9449 (define_insn "sibcall_compact"
9450 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
9451 (match_operand 1 "" ""))
9453 (use (match_operand:SI 2 "register_operand" "z,x"))
9454 (use (reg:SI R1_REG))
9455 (use (reg:PSI FPSCR_REG))
9456 ;; We want to make sure the `x' above will only match MACH_REG
9457 ;; because sibcall_epilogue may clobber MACL_REG.
9458 (clobber (reg:SI MACL_REG))]
9461 static const char* alt[] =
9468 return alt[which_alternative];
9470 [(set_attr "needs_delay_slot" "yes,no")
9471 (set_attr "length" "2,4")
9472 (set (attr "fp_mode") (const_string "single"))
9473 (set_attr "type" "jump_ind")])
9475 (define_insn "sibcall_media"
9476 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
9477 (match_operand 1 "" ""))
9478 (use (reg:SI PR_MEDIA_REG))
9482 [(set_attr "type" "jump_media")])
9484 (define_expand "sibcall"
9486 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9487 (match_operand 1 "" ""))
9488 (match_operand 2 "" "")
9489 (use (reg:PSI FPSCR_REG))
9495 operands[0] = shmedia_prepare_call_address (operands[0], 1);
9496 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
9499 else if (TARGET_SHCOMPACT && operands[2]
9500 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9502 rtx cookie_rtx = operands[2];
9503 long cookie = INTVAL (cookie_rtx);
9504 rtx func = XEXP (operands[0], 0);
9509 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9511 rtx reg = gen_reg_rtx (Pmode);
9513 emit_insn (gen_symGOT2reg (reg, func));
9517 func = legitimize_pic_address (func, Pmode, 0);
9520 /* FIXME: if we could tell whether all argument registers are
9521 already taken, we could decide whether to force the use of
9522 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9523 simple way to tell. We could use the CALL_COOKIE, but we
9524 can't currently tell a register used for regular argument
9525 passing from one that is unused. If we leave it up to reload
9526 to decide which register to use, it seems to always choose
9527 R0_REG, which leaves no available registers in SIBCALL_REGS
9528 to hold the address of the trampoline. */
9529 mach = gen_rtx_REG (SImode, MACH_REG);
9530 r1 = gen_rtx_REG (SImode, R1_REG);
9532 /* Since such a call function may use all call-clobbered
9533 registers, we force a mode switch earlier, so that we don't
9534 run out of registers when adjusting fpscr for the call. */
9535 emit_insn (gen_force_mode_for_call ());
9538 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9539 operands[0] = force_reg (SImode, operands[0]);
9541 /* We don't need a return trampoline, since the callee will
9542 return directly to the upper caller. */
9543 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9545 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9546 cookie_rtx = GEN_INT (cookie);
9549 emit_move_insn (mach, func);
9550 emit_move_insn (r1, cookie_rtx);
9552 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
9555 else if (TARGET_SHCOMPACT && flag_pic
9556 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9557 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9559 rtx reg = gen_reg_rtx (Pmode);
9561 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
9562 XEXP (operands[0], 0) = reg;
9564 if (flag_pic && TARGET_SH2
9565 && MEM_P (operands[0])
9566 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9567 /* The PLT needs the PIC register, but the epilogue would have
9568 to restore it, so we can only use PC-relative PIC calls for
9569 static functions. */
9570 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9572 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
9576 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9578 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
9582 (define_insn "sibcall_valuei"
9583 [(set (match_operand 0 "" "=rf")
9584 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
9585 (match_operand 2 "" "")))
9586 (use (reg:PSI FPSCR_REG))
9590 [(set_attr "needs_delay_slot" "yes")
9591 (set (attr "fp_mode")
9592 (if_then_else (eq_attr "fpu_single" "yes")
9593 (const_string "single") (const_string "double")))
9594 (set_attr "type" "jump_ind")])
9596 (define_insn "sibcall_valuei_pcrel"
9597 [(set (match_operand 0 "" "=rf")
9598 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
9599 (match_operand 2 "" "")))
9600 (use (match_operand 3 "" ""))
9601 (use (reg:PSI FPSCR_REG))
9605 return "braf %1" "\n"
9608 [(set_attr "needs_delay_slot" "yes")
9609 (set (attr "fp_mode")
9610 (if_then_else (eq_attr "fpu_single" "yes")
9611 (const_string "single") (const_string "double")))
9612 (set_attr "type" "jump_ind")])
9614 (define_insn_and_split "sibcall_value_pcrel"
9615 [(set (match_operand 0 "" "=rf")
9616 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9617 (match_operand 2 "" "")))
9618 (use (reg:PSI FPSCR_REG))
9619 (clobber (match_scratch:SI 3 "=k"))
9626 rtx lab = PATTERN (gen_call_site ());
9629 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9630 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
9634 SIBLING_CALL_P (call_insn) = 1;
9637 [(set_attr "needs_delay_slot" "yes")
9638 (set (attr "fp_mode")
9639 (if_then_else (eq_attr "fpu_single" "yes")
9640 (const_string "single") (const_string "double")))
9641 (set_attr "type" "jump_ind")])
9643 (define_insn "sibcall_value_compact"
9644 [(set (match_operand 0 "" "=rf,rf")
9645 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
9646 (match_operand 2 "" "")))
9648 (use (match_operand:SI 3 "register_operand" "z,x"))
9649 (use (reg:SI R1_REG))
9650 (use (reg:PSI FPSCR_REG))
9651 ;; We want to make sure the `x' above will only match MACH_REG
9652 ;; because sibcall_epilogue may clobber MACL_REG.
9653 (clobber (reg:SI MACL_REG))]
9656 static const char* alt[] =
9663 return alt[which_alternative];
9665 [(set_attr "needs_delay_slot" "yes,no")
9666 (set_attr "length" "2,4")
9667 (set (attr "fp_mode") (const_string "single"))
9668 (set_attr "type" "jump_ind")])
9670 (define_insn "sibcall_value_media"
9671 [(set (match_operand 0 "" "=rf")
9672 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
9673 (match_operand 2 "" "")))
9674 (use (reg:SI PR_MEDIA_REG))
9678 [(set_attr "type" "jump_media")])
9680 (define_expand "sibcall_value"
9682 [(set (match_operand 0 "arith_reg_operand" "")
9683 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9684 (match_operand 2 "" "")))
9685 (match_operand 3 "" "")
9686 (use (reg:PSI FPSCR_REG))
9692 operands[1] = shmedia_prepare_call_address (operands[1], 1);
9693 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
9697 else if (TARGET_SHCOMPACT && operands[3]
9698 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9700 rtx cookie_rtx = operands[3];
9701 long cookie = INTVAL (cookie_rtx);
9702 rtx func = XEXP (operands[1], 0);
9707 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9709 rtx reg = gen_reg_rtx (Pmode);
9711 emit_insn (gen_symGOT2reg (reg, func));
9715 func = legitimize_pic_address (func, Pmode, 0);
9718 /* FIXME: if we could tell whether all argument registers are
9719 already taken, we could decide whether to force the use of
9720 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9721 simple way to tell. We could use the CALL_COOKIE, but we
9722 can't currently tell a register used for regular argument
9723 passing from one that is unused. If we leave it up to reload
9724 to decide which register to use, it seems to always choose
9725 R0_REG, which leaves no available registers in SIBCALL_REGS
9726 to hold the address of the trampoline. */
9727 mach = gen_rtx_REG (SImode, MACH_REG);
9728 r1 = gen_rtx_REG (SImode, R1_REG);
9730 /* Since such a call function may use all call-clobbered
9731 registers, we force a mode switch earlier, so that we don't
9732 run out of registers when adjusting fpscr for the call. */
9733 emit_insn (gen_force_mode_for_call ());
9736 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9737 operands[1] = force_reg (SImode, operands[1]);
9739 /* We don't need a return trampoline, since the callee will
9740 return directly to the upper caller. */
9741 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9743 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9744 cookie_rtx = GEN_INT (cookie);
9747 emit_move_insn (mach, func);
9748 emit_move_insn (r1, cookie_rtx);
9750 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
9751 operands[2], mach));
9754 else if (TARGET_SHCOMPACT && flag_pic
9755 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9756 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9758 rtx reg = gen_reg_rtx (Pmode);
9760 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
9761 XEXP (operands[1], 0) = reg;
9763 if (flag_pic && TARGET_SH2
9764 && MEM_P (operands[1])
9765 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9766 /* The PLT needs the PIC register, but the epilogue would have
9767 to restore it, so we can only use PC-relative PIC calls for
9768 static functions. */
9769 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9771 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
9772 XEXP (operands[1], 0),
9777 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9779 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
9783 (define_insn "call_value_pop_compact"
9784 [(set (match_operand 0 "" "=rf")
9785 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9786 (match_operand 2 "" "")))
9787 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9788 (match_operand 4 "immediate_operand" "n")))
9789 (match_operand 3 "immediate_operand" "n")
9790 (use (reg:SI R0_REG))
9791 (use (reg:SI R1_REG))
9792 (use (reg:PSI FPSCR_REG))
9793 (clobber (reg:SI PR_REG))]
9794 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9796 [(set_attr "type" "call")
9797 (set (attr "fp_mode")
9798 (if_then_else (eq_attr "fpu_single" "yes")
9799 (const_string "single") (const_string "double")))
9800 (set_attr "needs_delay_slot" "yes")])
9802 (define_insn "call_value_pop_compact_rettramp"
9803 [(set (match_operand 0 "" "=rf")
9804 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9805 (match_operand 2 "" "")))
9806 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9807 (match_operand 4 "immediate_operand" "n")))
9808 (match_operand 3 "immediate_operand" "n")
9809 (use (reg:SI R0_REG))
9810 (use (reg:SI R1_REG))
9811 (use (reg:PSI FPSCR_REG))
9812 (clobber (reg:SI R10_REG))
9813 (clobber (reg:SI PR_REG))]
9814 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9816 [(set_attr "type" "call")
9817 (set (attr "fp_mode")
9818 (if_then_else (eq_attr "fpu_single" "yes")
9819 (const_string "single") (const_string "double")))
9820 (set_attr "needs_delay_slot" "yes")])
9822 (define_expand "call_value_pop"
9823 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9824 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9825 (match_operand 2 "" "")))
9826 (match_operand 3 "" "")
9827 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9828 (match_operand 4 "" "")))])]
9836 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
9837 cookie_rtx = operands[3];
9838 cookie = INTVAL (cookie_rtx);
9839 func = XEXP (operands[1], 0);
9843 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9845 rtx reg = gen_reg_rtx (Pmode);
9847 emit_insn (gen_symGOTPLT2reg (reg, func));
9851 func = legitimize_pic_address (func, Pmode, 0);
9854 r0 = gen_rtx_REG (SImode, R0_REG);
9855 r1 = gen_rtx_REG (SImode, R1_REG);
9857 /* Since such a call function may use all call-clobbered
9858 registers, we force a mode switch earlier, so that we don't
9859 run out of registers when adjusting fpscr for the call. */
9860 emit_insn (gen_force_mode_for_call ());
9862 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9864 operands[1] = force_reg (SImode, operands[1]);
9866 emit_move_insn (r0, func);
9867 emit_move_insn (r1, cookie_rtx);
9869 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9870 emit_call_insn (gen_call_value_pop_compact_rettramp
9871 (operands[0], operands[1], operands[2],
9872 operands[3], operands[4]));
9874 emit_call_insn (gen_call_value_pop_compact
9875 (operands[0], operands[1], operands[2],
9876 operands[3], operands[4]));
9881 (define_expand "sibcall_epilogue"
9885 sh_expand_epilogue (true);
9886 if (TARGET_SHCOMPACT)
9890 /* If epilogue clobbers r0, preserve it in macl. */
9891 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9892 if ((set = single_set (insn))
9893 && REG_P (SET_DEST (set))
9894 && REGNO (SET_DEST (set)) == R0_REG)
9896 rtx r0 = gen_rtx_REG (SImode, R0_REG);
9897 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
9899 /* We can't tell at this point whether the sibcall is a
9900 sibcall_compact and, if it is, whether it uses r0 or
9901 mach as operand 2, so let the instructions that
9902 preserve r0 be optimized away if r0 turns out to be
9904 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
9905 emit_move_insn (r0, tmp);
9912 (define_insn "indirect_jump_compact"
9914 (match_operand:SI 0 "arith_reg_operand" "r"))]
9917 [(set_attr "needs_delay_slot" "yes")
9918 (set_attr "type" "jump_ind")])
9920 (define_expand "indirect_jump"
9922 (match_operand 0 "register_operand" ""))]
9925 if (GET_MODE (operands[0]) != Pmode)
9926 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
9929 ;; The use of operand 1 / 2 helps us distinguish case table jumps
9930 ;; which can be present in structured code from indirect jumps which can not
9931 ;; be present in structured code. This allows -fprofile-arcs to work.
9933 ;; For SH1 processors.
9934 (define_insn "casesi_jump_1"
9936 (match_operand:SI 0 "register_operand" "r"))
9937 (use (label_ref (match_operand 1 "" "")))]
9940 [(set_attr "needs_delay_slot" "yes")
9941 (set_attr "type" "jump_ind")])
9943 ;; For all later processors.
9944 (define_insn "casesi_jump_2"
9945 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
9946 (label_ref (match_operand 1 "" ""))))
9947 (use (label_ref (match_operand 2 "" "")))]
9949 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
9951 [(set_attr "needs_delay_slot" "yes")
9952 (set_attr "type" "jump_ind")])
9954 (define_insn "casesi_jump_media"
9955 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
9956 (use (label_ref (match_operand 1 "" "")))]
9959 [(set_attr "type" "jump_media")])
9961 ;; Call subroutine returning any type.
9962 ;; ??? This probably doesn't work.
9963 (define_expand "untyped_call"
9964 [(parallel [(call (match_operand 0 "" "")
9966 (match_operand 1 "" "")
9967 (match_operand 2 "" "")])]
9968 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
9970 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9972 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
9974 rtx set = XVECEXP (operands[2], 0, i);
9975 emit_move_insn (SET_DEST (set), SET_SRC (set));
9978 /* The optimizer does not know that the call sets the function value
9979 registers we stored in the result block. We avoid problems by
9980 claiming that all hard registers are used and clobbered at this
9982 emit_insn (gen_blockage ());
9987 ;; ------------------------------------------------------------------------
9989 ;; ------------------------------------------------------------------------
9992 [(set (reg:SI T_REG)
9993 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
9994 (set (match_operand:SI 0 "arith_reg_dest" "=r")
9995 (plus:SI (match_dup 1) (const_int -1)))]
9998 [(set_attr "type" "arith")])
10005 ;; Load address of a label. This is only generated by the casesi expand,
10006 ;; and by machine_dependent_reorg (fixing up fp moves).
10007 ;; This must use unspec, because this only works for labels that are
10009 (define_insn "mova"
10010 [(set (reg:SI R0_REG)
10011 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10014 [(set_attr "in_delay_slot" "no")
10015 (set_attr "type" "arith")])
10017 ;; machine_dependent_reorg will make this a `mova'.
10018 (define_insn "mova_const"
10019 [(set (reg:SI R0_REG)
10020 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10023 [(set_attr "in_delay_slot" "no")
10024 (set_attr "type" "arith")])
10026 (define_expand "GOTaddr2picreg"
10027 [(set (reg:SI R0_REG)
10028 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10030 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10031 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10034 if (TARGET_VXWORKS_RTP)
10036 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10037 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10038 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10042 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10043 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10045 if (TARGET_SHMEDIA)
10047 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10048 rtx pic = operands[0];
10049 rtx lab = PATTERN (gen_call_site ());
10052 equiv = operands[1];
10053 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10054 UNSPEC_PCREL_SYMOFF);
10055 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10057 if (Pmode == SImode)
10059 emit_insn (gen_movsi_const (pic, operands[1]));
10060 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10064 emit_insn (gen_movdi_const (pic, operands[1]));
10065 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10068 insn = emit_move_insn (operands[0], tr);
10070 set_unique_reg_note (insn, REG_EQUAL, equiv);
10076 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10078 (define_expand "vxworks_picreg"
10079 [(set (reg:SI PIC_REG)
10080 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10081 (set (reg:SI R0_REG)
10082 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10083 (set (reg:SI PIC_REG)
10084 (mem:SI (reg:SI PIC_REG)))
10085 (set (reg:SI PIC_REG)
10086 (mem:SI (plus:SI (reg:SI PIC_REG)
10087 (reg:SI R0_REG))))]
10088 "TARGET_VXWORKS_RTP")
10090 (define_insn "*ptb"
10091 [(set (match_operand 0 "target_reg_operand" "=b")
10092 (const (unspec [(match_operand 1 "" "Csy")]
10093 UNSPEC_DATALABEL)))]
10094 "TARGET_SHMEDIA && flag_pic
10095 && satisfies_constraint_Csy (operands[1])"
10096 "ptb/u datalabel %1, %0"
10097 [(set_attr "type" "ptabs_media")
10098 (set_attr "length" "*")])
10100 (define_insn "ptrel_si"
10101 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10102 (plus:SI (match_operand:SI 1 "register_operand" "r")
10104 (match_operand:SI 2 "" "")]
10106 "%O2: ptrel/u %1, %0"
10107 [(set_attr "type" "ptabs_media")])
10109 (define_insn "ptrel_di"
10110 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10111 (plus:DI (match_operand:DI 1 "register_operand" "r")
10113 (match_operand:DI 2 "" "")]
10115 "%O2: ptrel/u %1, %0"
10116 [(set_attr "type" "ptabs_media")])
10118 (define_expand "builtin_setjmp_receiver"
10119 [(match_operand 0 "" "")]
10122 emit_insn (gen_GOTaddr2picreg ());
10126 (define_expand "call_site"
10127 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10130 static HOST_WIDE_INT i = 0;
10131 operands[0] = GEN_INT (i);
10135 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10136 ;; in symGOT_load expand.
10137 (define_insn_and_split "chk_guard_add"
10138 [(set (match_operand:SI 0 "register_operand" "=&r")
10139 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10144 "TARGET_SH1 && reload_completed"
10145 [(set (match_dup 0) (reg:SI PIC_REG))
10146 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10148 [(set_attr "type" "arith")])
10150 (define_expand "sym_label2reg"
10151 [(set (match_operand:SI 0 "" "")
10152 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10153 (const (plus:SI (match_operand:SI 2 "" "")
10158 (define_expand "symGOT_load"
10159 [(set (match_dup 2) (match_operand 1 "" ""))
10160 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10161 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10166 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10167 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10169 if (TARGET_SHMEDIA)
10171 rtx reg = operands[2];
10173 if (Pmode == DImode)
10176 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10178 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10183 emit_insn (gen_movsi_const (reg, operands[1]));
10185 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10189 emit_move_insn (operands[2], operands[1]);
10191 /* When stack protector inserts codes after the result is set to
10192 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10193 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10194 when rX is a GOT address for the guard symbol. Ugly but doesn't
10195 matter because this is a rare situation. */
10196 if (!TARGET_SHMEDIA
10197 && flag_stack_protect
10198 && GET_CODE (operands[1]) == CONST
10199 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10200 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10201 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10202 "__stack_chk_guard") == 0)
10203 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10205 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10206 gen_rtx_REG (Pmode, PIC_REG)));
10208 /* N.B. This is not constant for a GOTPLT relocation. */
10209 mem = gen_rtx_MEM (Pmode, operands[3]);
10210 MEM_NOTRAP_P (mem) = 1;
10211 /* ??? Should we have a special alias set for the GOT? */
10212 emit_move_insn (operands[0], mem);
10217 (define_expand "sym2GOT"
10218 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10222 (define_expand "symGOT2reg"
10223 [(match_operand 0 "" "") (match_operand 1 "" "")]
10228 gotsym = gen_sym2GOT (operands[1]);
10229 PUT_MODE (gotsym, Pmode);
10230 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10232 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10237 (define_expand "symGOTPLT2reg"
10238 [(match_operand 0 "" "") (match_operand 1 "" "")]
10241 rtx pltsym = gen_rtx_CONST (Pmode,
10242 gen_rtx_UNSPEC (Pmode,
10243 gen_rtvec (1, operands[1]),
10245 emit_insn (gen_symGOT_load (operands[0], pltsym));
10249 (define_expand "sym2GOTOFF"
10250 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10254 (define_expand "symGOTOFF2reg"
10255 [(match_operand 0 "" "") (match_operand 1 "" "")]
10258 rtx gotoffsym, insn;
10259 rtx t = (!can_create_pseudo_p ()
10261 : gen_reg_rtx (GET_MODE (operands[0])));
10263 gotoffsym = gen_sym2GOTOFF (operands[1]);
10264 PUT_MODE (gotoffsym, Pmode);
10265 emit_move_insn (t, gotoffsym);
10266 insn = emit_move_insn (operands[0],
10267 gen_rtx_PLUS (Pmode, t,
10268 gen_rtx_REG (Pmode, PIC_REG)));
10270 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10275 (define_expand "symPLT_label2reg"
10276 [(set (match_operand:SI 0 "" "")
10279 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10280 (const:SI (plus:SI (match_operand:SI 2 "" "")
10281 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10282 ;; Even though the PIC register is not really used by the call
10283 ;; sequence in which this is expanded, the PLT code assumes the PIC
10284 ;; register is set, so we must not skip its initialization. Since
10285 ;; we only use this expand as part of calling sequences, and never
10286 ;; to take the address of a function, this is the best point to
10287 ;; insert the (use). Using the PLT to take the address of a
10288 ;; function would be wrong, not only because the PLT entry could
10289 ;; then be called from a function that doesn't initialize the PIC
10290 ;; register to the proper GOT, but also because pointers to the
10291 ;; same function might not compare equal, should they be set by
10292 ;; different shared libraries.
10293 (use (reg:SI PIC_REG))]
10297 (define_expand "sym2PIC"
10298 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10302 ;; -------------------------------------------------------------------------
10303 ;; TLS code generation.
10305 ;; FIXME: The multi-insn asm blocks should be converted to use
10306 ;; define_insn_and_split.
10307 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10308 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10311 (define_insn "tls_global_dynamic"
10312 [(set (match_operand:SI 0 "register_operand" "=&z")
10313 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10316 (use (reg:PSI FPSCR_REG))
10317 (use (reg:SI PIC_REG))
10318 (clobber (reg:SI PR_REG))
10319 (clobber (scratch:SI))]
10322 return "mov.l 1f,r4" "\n"
10324 " mov.l 2f,r1" "\n"
10331 "1: .long %a1@TLSGD" "\n"
10332 "2: .long __tls_get_addr@PLT" "\n"
10335 [(set_attr "type" "tls_load")
10336 (set_attr "length" "26")])
10338 (define_insn "tls_local_dynamic"
10339 [(set (match_operand:SI 0 "register_operand" "=&z")
10340 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10343 (use (reg:PSI FPSCR_REG))
10344 (use (reg:SI PIC_REG))
10345 (clobber (reg:SI PR_REG))
10346 (clobber (scratch:SI))]
10349 return "mov.l 1f,r4" "\n"
10351 " mov.l 2f,r1" "\n"
10358 "1: .long %a1@TLSLDM" "\n"
10359 "2: .long __tls_get_addr@PLT" "\n"
10362 [(set_attr "type" "tls_load")
10363 (set_attr "length" "26")])
10365 (define_expand "sym2DTPOFF"
10366 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10370 (define_expand "symDTPOFF2reg"
10371 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10375 rtx t = (!can_create_pseudo_p ()
10377 : gen_reg_rtx (GET_MODE (operands[0])));
10379 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10380 PUT_MODE (dtpoffsym, Pmode);
10381 emit_move_insn (t, dtpoffsym);
10382 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10386 (define_expand "sym2GOTTPOFF"
10387 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10391 (define_insn "tls_initial_exec"
10392 [(set (match_operand:SI 0 "register_operand" "=&r")
10393 (unspec:SI [(match_operand:SI 1 "" "")]
10395 (use (reg:SI GBR_REG))
10396 (use (reg:SI PIC_REG))
10397 (clobber (reg:SI R0_REG))]
10400 return "mov.l 1f,r0" "\n"
10402 " mov.l @(r0,r12),r0" "\n"
10406 "1: .long %a1" "\n"
10409 [(set_attr "type" "tls_load")
10410 (set_attr "length" "16")])
10412 (define_expand "sym2TPOFF"
10413 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10417 (define_expand "symTPOFF2reg"
10418 [(match_operand 0 "" "") (match_operand 1 "" "")]
10423 tpoffsym = gen_sym2TPOFF (operands[1]);
10424 PUT_MODE (tpoffsym, Pmode);
10425 emit_move_insn (operands[0], tpoffsym);
10429 ;;------------------------------------------------------------------------------
10430 ;; Thread pointer getter and setter.
10432 ;; On SH the thread pointer is kept in the GBR.
10433 ;; These patterns are usually expanded from the respective built-in functions.
10434 (define_expand "get_thread_pointersi"
10435 [(set (match_operand:SI 0 "register_operand") (reg:SI GBR_REG))]
10438 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
10439 (define_insn "store_gbr"
10440 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))]
10443 [(set_attr "type" "tls_load")])
10445 (define_expand "set_thread_pointersi"
10446 [(set (reg:SI GBR_REG)
10447 (unspec_volatile:SI [(match_operand:SI 0 "register_operand")]
10451 (define_insn "load_gbr"
10452 [(set (reg:SI GBR_REG)
10453 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10457 [(set_attr "type" "move")])
10459 ;;------------------------------------------------------------------------------
10460 ;; Thread pointer relative memory loads and stores.
10462 ;; On SH there are GBR displacement address modes which can be utilized to
10463 ;; access memory behind the thread pointer.
10464 ;; Since we do not allow using GBR for general purpose memory accesses, these
10465 ;; GBR addressing modes are formed by the combine pass.
10466 ;; This could be done with fewer patterns than below by using a mem predicate
10467 ;; for the GBR mem, but then reload would try to reload addresses with a
10468 ;; zero displacement for some strange reason.
10470 (define_insn "*mov<mode>_gbr_load"
10471 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10472 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10473 (match_operand:QIHISI 1 "gbr_displacement"))))]
10475 "mov.<bwl> @(%O1,gbr),%0"
10476 [(set_attr "type" "load")])
10478 (define_insn "*mov<mode>_gbr_load"
10479 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10480 (mem:QIHISI (reg:SI GBR_REG)))]
10482 "mov.<bwl> @(0,gbr),%0"
10483 [(set_attr "type" "load")])
10485 (define_insn "*mov<mode>_gbr_load"
10486 [(set (match_operand:SI 0 "register_operand" "=z")
10488 (mem:QIHI (plus:SI (reg:SI GBR_REG)
10489 (match_operand:QIHI 1 "gbr_displacement")))))]
10491 "mov.<bw> @(%O1,gbr),%0"
10492 [(set_attr "type" "load")])
10494 (define_insn "*mov<mode>_gbr_load"
10495 [(set (match_operand:SI 0 "register_operand" "=z")
10496 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
10498 "mov.<bw> @(0,gbr),%0"
10499 [(set_attr "type" "load")])
10501 (define_insn "*mov<mode>_gbr_store"
10502 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10503 (match_operand:QIHISI 0 "gbr_displacement")))
10504 (match_operand:QIHISI 1 "register_operand" "z"))]
10506 "mov.<bwl> %1,@(%O0,gbr)"
10507 [(set_attr "type" "store")])
10509 (define_insn "*mov<mode>_gbr_store"
10510 [(set (mem:QIHISI (reg:SI GBR_REG))
10511 (match_operand:QIHISI 0 "register_operand" "z"))]
10513 "mov.<bwl> %0,@(0,gbr)"
10514 [(set_attr "type" "store")])
10516 ;; DImode memory accesses have to be split in two SImode accesses.
10517 ;; Split them before reload, so that it gets a better chance to figure out
10518 ;; how to deal with the R0 restriction for the individual SImode accesses.
10519 ;; Do not match this insn during or after reload because it can't be split
10521 (define_insn_and_split "*movdi_gbr_load"
10522 [(set (match_operand:DI 0 "register_operand")
10523 (match_operand:DI 1 "gbr_address_mem"))]
10524 "TARGET_SH1 && can_create_pseudo_p ()"
10527 [(set (match_dup 3) (match_dup 5))
10528 (set (match_dup 4) (match_dup 6))]
10530 /* Swap low/high part load order on little endian, so that the result reg
10531 of the second load can be used better. */
10532 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
10533 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10534 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10535 operands[4 - off] = gen_highpart (SImode, operands[0]);
10536 operands[6 - off] = gen_highpart (SImode, operands[1]);
10539 (define_insn_and_split "*movdi_gbr_store"
10540 [(set (match_operand:DI 0 "gbr_address_mem")
10541 (match_operand:DI 1 "register_operand"))]
10542 "TARGET_SH1 && can_create_pseudo_p ()"
10545 [(set (match_dup 3) (match_dup 5))
10546 (set (match_dup 4) (match_dup 6))]
10548 /* Swap low/high part store order on big endian, so that stores of function
10549 call results can save a reg copy. */
10550 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
10551 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10552 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10553 operands[4 - off] = gen_highpart (SImode, operands[0]);
10554 operands[6 - off] = gen_highpart (SImode, operands[1]);
10557 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
10558 ;; in particular when the displacements are in the range of the regular move
10559 ;; insns. Thus, in the first split pass after the combine pass we search
10560 ;; for missed opportunities and try to fix them up ourselves.
10561 ;; If an equivalent GBR address can be determined the load / store is split
10562 ;; into one of the GBR load / store patterns.
10563 ;; All of that must happen before reload (GBR address modes use R0 as the
10564 ;; other operand) and there's no point of doing it if the GBR is not
10565 ;; referenced in a function at all.
10567 [(set (match_operand:QIHISIDI 0 "register_operand")
10568 (match_operand:QIHISIDI 1 "memory_operand"))]
10569 "TARGET_SH1 && !reload_in_progress && !reload_completed
10570 && df_regs_ever_live_p (GBR_REG)"
10571 [(set (match_dup 0) (match_dup 1))]
10573 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10574 if (gbr_mem != NULL_RTX)
10575 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10581 [(set (match_operand:SI 0 "register_operand")
10582 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10583 "TARGET_SH1 && !reload_in_progress && !reload_completed
10584 && df_regs_ever_live_p (GBR_REG)"
10585 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
10587 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10588 if (gbr_mem != NULL_RTX)
10589 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10594 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
10595 ;; Split those so that a GBR load can be used.
10597 [(set (match_operand:SI 0 "register_operand")
10598 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10599 "TARGET_SH2A && !reload_in_progress && !reload_completed
10600 && df_regs_ever_live_p (GBR_REG)"
10601 [(set (match_dup 2) (match_dup 1))
10602 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10604 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10605 if (gbr_mem != NULL_RTX)
10607 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
10608 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10615 [(set (match_operand:QIHISIDI 0 "memory_operand")
10616 (match_operand:QIHISIDI 1 "register_operand"))]
10617 "TARGET_SH1 && !reload_in_progress && !reload_completed
10618 && df_regs_ever_live_p (GBR_REG)"
10619 [(set (match_dup 0) (match_dup 1))]
10621 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
10622 if (gbr_mem != NULL_RTX)
10623 operands[0] = replace_equiv_address (operands[0], gbr_mem);
10628 ;;------------------------------------------------------------------------------
10629 ;; case instruction for switch statements.
10631 ;; operand 0 is index
10632 ;; operand 1 is the minimum bound
10633 ;; operand 2 is the maximum bound - minimum bound + 1
10634 ;; operand 3 is CODE_LABEL for the table;
10635 ;; operand 4 is the CODE_LABEL to go to if index out of range.
10636 (define_expand "casesi"
10637 [(match_operand:SI 0 "arith_reg_operand" "")
10638 (match_operand:SI 1 "arith_reg_operand" "")
10639 (match_operand:SI 2 "arith_reg_operand" "")
10640 (match_operand 3 "" "") (match_operand 4 "" "")]
10643 rtx reg = gen_reg_rtx (SImode);
10644 rtx reg2 = gen_reg_rtx (SImode);
10645 if (TARGET_SHMEDIA)
10647 rtx reg = gen_reg_rtx (DImode);
10648 rtx reg2 = gen_reg_rtx (DImode);
10649 rtx reg3 = gen_reg_rtx (Pmode);
10650 rtx reg4 = gen_reg_rtx (Pmode);
10651 rtx reg5 = gen_reg_rtx (Pmode);
10654 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
10655 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
10656 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
10658 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
10659 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
10661 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
10662 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
10663 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
10664 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
10665 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
10666 (Pmode, operands[3])));
10667 /* Messy: can we subreg to clean this up? */
10668 if (Pmode == DImode)
10669 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
10671 load = gen_casesi_load_media (reg4,
10672 gen_rtx_SUBREG (DImode, reg3, 0),
10673 reg2, operands[3]);
10674 PUT_MODE (SET_SRC (load), Pmode);
10676 /* ??? The following add could be eliminated if we used ptrel. */
10677 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
10678 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
10682 operands[1] = copy_to_mode_reg (SImode, operands[1]);
10683 operands[2] = copy_to_mode_reg (SImode, operands[2]);
10684 /* If optimizing, casesi_worker depends on the mode of the instruction
10685 before label it 'uses' - operands[3]. */
10686 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
10688 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
10690 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
10692 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
10693 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
10694 operands[3], but to lab. We will fix this up in
10695 machine_dependent_reorg. */
10700 (define_expand "casesi_0"
10701 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
10702 (set (match_dup 4) (minus:SI (match_dup 4)
10703 (match_operand:SI 1 "arith_operand" "")))
10704 (set (reg:SI T_REG)
10705 (gtu:SI (match_dup 4)
10706 (match_operand:SI 2 "arith_reg_operand" "")))
10708 (if_then_else (ne (reg:SI T_REG)
10710 (label_ref (match_operand 3 "" ""))
10715 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
10716 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
10717 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
10718 (define_insn "casesi_worker_0"
10719 [(set (match_operand:SI 0 "register_operand" "=r,r")
10720 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
10721 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10722 (clobber (match_scratch:SI 3 "=X,1"))
10723 (clobber (match_scratch:SI 4 "=&z,z"))]
10728 [(set (match_operand:SI 0 "register_operand" "")
10729 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10730 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10731 (clobber (match_scratch:SI 3 ""))
10732 (clobber (match_scratch:SI 4 ""))]
10733 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
10734 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10735 (parallel [(set (match_dup 0)
10736 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10737 (label_ref (match_dup 2))] UNSPEC_CASESI))
10738 (clobber (match_dup 3))])
10739 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10741 if (GET_CODE (operands[2]) == CODE_LABEL)
10742 LABEL_NUSES (operands[2])++;
10746 [(set (match_operand:SI 0 "register_operand" "")
10747 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10748 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10749 (clobber (match_scratch:SI 3 ""))
10750 (clobber (match_scratch:SI 4 ""))]
10751 "TARGET_SH2 && reload_completed"
10752 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10753 (parallel [(set (match_dup 0)
10754 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10755 (label_ref (match_dup 2))] UNSPEC_CASESI))
10756 (clobber (match_dup 3))])]
10758 if (GET_CODE (operands[2]) == CODE_LABEL)
10759 LABEL_NUSES (operands[2])++;
10762 (define_insn "casesi_worker_1"
10763 [(set (match_operand:SI 0 "register_operand" "=r,r")
10764 (unspec:SI [(reg:SI R0_REG)
10765 (match_operand:SI 1 "register_operand" "0,r")
10766 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10767 (clobber (match_scratch:SI 3 "=X,1"))]
10770 rtx diff_vec = PATTERN (next_active_insn (operands[2]));
10772 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10774 switch (GET_MODE (diff_vec))
10777 return "shll2 %1" "\n"
10778 " mov.l @(r0,%1),%0";
10780 return "add %1,%1" "\n"
10781 " mov.w @(r0,%1),%0";
10783 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10784 return "mov.b @(r0,%1),%0" "\n"
10787 return "mov.b @(r0,%1),%0";
10790 gcc_unreachable ();
10793 [(set_attr "length" "4")])
10795 (define_insn "casesi_worker_2"
10796 [(set (match_operand:SI 0 "register_operand" "=r,r")
10797 (unspec:SI [(reg:SI R0_REG)
10798 (match_operand:SI 1 "register_operand" "0,r")
10799 (label_ref (match_operand 2 "" ""))
10800 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
10801 (clobber (match_operand:SI 4 "" "=X,1"))]
10802 "TARGET_SH2 && reload_completed && flag_pic"
10804 rtx diff_vec = PATTERN (next_active_insn (operands[2]));
10805 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10807 switch (GET_MODE (diff_vec))
10810 return "shll2 %1" "\n"
10812 " mova %O3,r0" "\n"
10813 " mov.l @(r0,%1),%0";
10815 return "add %1,%1" "\n"
10817 " mova %O3,r0" "\n"
10818 " mov.w @(r0,%1),%0";
10820 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10821 return "add r0,%1" "\n"
10822 " mova %O3,r0" "\n"
10823 " mov.b @(r0,%1),%0" "\n"
10826 return "add r0,%1" "\n"
10827 " mova %O3,r0" "\n"
10828 " mov.b @(r0,%1),%0";
10830 gcc_unreachable ();
10833 [(set_attr "length" "8")])
10835 (define_insn "casesi_shift_media"
10836 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10837 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
10838 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
10842 rtx diff_vec = PATTERN (next_active_insn (operands[2]));
10844 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10846 switch (GET_MODE (diff_vec))
10849 return "shlli %1, 2, %0";
10851 return "shlli %1, 1, %0";
10853 if (rtx_equal_p (operands[0], operands[1]))
10855 return "add %1, r63, %0";
10857 gcc_unreachable ();
10860 [(set_attr "type" "arith_media")])
10862 (define_insn "casesi_load_media"
10863 [(set (match_operand 0 "any_arith_reg_dest" "=r")
10864 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
10865 (match_operand:DI 2 "arith_reg_operand" "r")
10866 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
10869 rtx diff_vec = PATTERN (next_active_insn (operands[3]));
10871 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10873 switch (GET_MODE (diff_vec))
10876 return "ldx.l %1, %2, %0";
10879 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10880 return "ldx.uw %1, %2, %0";
10882 return "ldx.w %1, %2, %0";
10884 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10885 return "ldx.ub %1, %2, %0";
10886 return "ldx.b %1, %2, %0";
10888 gcc_unreachable ();
10891 [(set_attr "type" "load_media")])
10893 (define_expand "simple_return"
10895 "sh_can_use_simple_return_p ()")
10897 (define_expand "return"
10899 "reload_completed && epilogue_completed"
10901 if (TARGET_SHMEDIA)
10903 emit_jump_insn (gen_return_media ());
10907 if (TARGET_SHCOMPACT
10908 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
10910 emit_jump_insn (gen_shcompact_return_tramp ());
10915 (define_insn "*<code>_i"
10917 "TARGET_SH1 && ! (TARGET_SHCOMPACT
10918 && (crtl->args.info.call_cookie
10919 & CALL_COOKIE_RET_TRAMP (1)))
10920 && reload_completed
10921 && ! sh_cfun_trap_exit_p ()"
10923 if (TARGET_SH2A && (dbr_sequence_length () == 0)
10924 && !current_function_interrupt)
10929 [(set_attr "type" "return")
10930 (set_attr "needs_delay_slot" "yes")])
10932 ;; trapa has no delay slot.
10933 (define_insn "*return_trapa"
10935 "TARGET_SH1 && !TARGET_SHCOMPACT
10936 && reload_completed"
10938 [(set_attr "type" "return")])
10940 (define_expand "shcompact_return_tramp"
10943 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
10945 rtx reg = gen_rtx_REG (Pmode, R0_REG);
10947 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
10948 emit_jump_insn (gen_shcompact_return_tramp_i ());
10952 (define_insn "shcompact_return_tramp_i"
10953 [(parallel [(return) (use (reg:SI R0_REG))])]
10955 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
10957 [(set_attr "type" "jump_ind")
10958 (set_attr "needs_delay_slot" "yes")])
10960 (define_insn "return_media_i"
10961 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
10962 "TARGET_SHMEDIA && reload_completed"
10964 [(set_attr "type" "jump_media")])
10966 (define_insn "return_media_rte"
10968 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
10970 [(set_attr "type" "jump_media")])
10972 (define_expand "return_media"
10974 "TARGET_SHMEDIA && reload_completed"
10976 int tr_regno = sh_media_register_for_return ();
10979 if (current_function_interrupt)
10981 emit_jump_insn (gen_return_media_rte ());
10986 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
10988 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
10989 tr_regno = TR0_REG;
10990 tr = gen_rtx_REG (Pmode, tr_regno);
10991 emit_move_insn (tr, r18);
10994 tr = gen_rtx_REG (Pmode, tr_regno);
10996 emit_jump_insn (gen_return_media_i (tr));
11000 (define_insn "shcompact_preserve_incoming_args"
11001 [(set (match_operand:SI 0 "register_operand" "+r")
11002 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11005 [(set_attr "length" "0")])
11007 (define_insn "shcompact_incoming_args"
11008 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11009 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11010 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11011 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11012 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11013 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11014 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11015 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11016 (set (mem:BLK (reg:SI MACL_REG))
11017 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11018 (use (reg:SI R0_REG))
11019 (clobber (reg:SI R0_REG))
11020 (clobber (reg:SI MACL_REG))
11021 (clobber (reg:SI MACH_REG))
11022 (clobber (reg:SI PR_REG))]
11025 [(set_attr "needs_delay_slot" "yes")])
11027 (define_insn "shmedia_save_restore_regs_compact"
11028 [(set (reg:SI SP_REG)
11029 (plus:SI (reg:SI SP_REG)
11030 (match_operand:SI 0 "immediate_operand" "i")))
11031 (use (reg:SI R0_REG))
11032 (clobber (reg:SI PR_REG))]
11034 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11035 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11037 [(set_attr "needs_delay_slot" "yes")])
11039 (define_expand "prologue"
11043 sh_expand_prologue ();
11047 (define_expand "epilogue"
11051 sh_expand_epilogue (false);
11053 || (TARGET_SHCOMPACT
11054 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11056 emit_jump_insn (gen_return ());
11061 (define_expand "eh_return"
11062 [(use (match_operand 0 "register_operand" ""))]
11065 rtx ra = operands[0];
11067 if (TARGET_SHMEDIA64)
11068 emit_insn (gen_eh_set_ra_di (ra));
11070 emit_insn (gen_eh_set_ra_si (ra));
11075 ;; Clobber the return address on the stack. We can't expand this
11076 ;; until we know where it will be put in the stack frame.
11078 (define_insn "eh_set_ra_si"
11079 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11081 (clobber (match_scratch:SI 1 "=&r"))]
11082 "! TARGET_SHMEDIA64"
11085 (define_insn "eh_set_ra_di"
11086 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11088 (clobber (match_scratch:DI 1 "=&r"))]
11093 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11095 (clobber (match_scratch 1 ""))]
11099 sh_set_return_address (operands[0], operands[1]);
11103 (define_insn "blockage"
11104 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11107 [(set_attr "length" "0")])
11109 ;; Define movml instructions for SH2A target. Currently they are
11110 ;; used to push and pop all banked registers only.
11112 (define_insn "movml_push_banked"
11113 [(set (match_operand:SI 0 "register_operand" "=r")
11114 (plus (match_dup 0) (const_int -32)))
11115 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11116 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11117 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11118 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11119 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11120 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11121 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11122 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11123 "TARGET_SH2A && REGNO (operands[0]) == 15"
11125 [(set_attr "in_delay_slot" "no")])
11127 (define_insn "movml_pop_banked"
11128 [(set (match_operand:SI 0 "register_operand" "=r")
11129 (plus (match_dup 0) (const_int 32)))
11130 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11131 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11132 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11133 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11134 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11135 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11136 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11137 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11138 "TARGET_SH2A && REGNO (operands[0]) == 15"
11140 [(set_attr "in_delay_slot" "no")])
11142 ;; ------------------------------------------------------------------------
11143 ;; Scc instructions
11144 ;; ------------------------------------------------------------------------
11146 (define_insn "movt"
11147 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11148 (match_operand:SI 1 "t_reg_operand"))]
11151 [(set_attr "type" "arith")])
11153 (define_insn "movrt"
11154 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11155 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11158 [(set_attr "type" "arith")])
11160 (define_expand "cstore4_media"
11161 [(set (match_operand:SI 0 "register_operand" "=r")
11162 (match_operator:SI 1 "sh_float_comparison_operator"
11163 [(match_operand 2 "logical_operand" "")
11164 (match_operand 3 "cmp_operand" "")]))]
11167 enum machine_mode mode = GET_MODE (operands[2]);
11168 enum rtx_code code = GET_CODE (operands[1]);
11170 if (mode == VOIDmode)
11171 mode = GET_MODE (operands[3]);
11172 if (operands[2] == const0_rtx)
11174 if (code == EQ || code == NE)
11175 operands[2] = operands[3], operands[3] = const0_rtx;
11178 operands[2] = force_reg (mode, operands[2]);
11179 if (operands[3] != const0_rtx)
11180 operands[3] = force_reg (mode, operands[3]);
11186 swap = invert = !FLOAT_MODE_P (mode);
11191 swap = FLOAT_MODE_P (mode), invert = !swap;
11196 swap = true, invert = false;
11203 swap = invert = false;
11207 swap = invert = true;
11211 gcc_unreachable ();
11216 rtx tem = operands[2];
11217 operands[2] = operands[3];
11219 code = swap_condition (code);
11224 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11225 code = reverse_condition (code);
11226 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11227 emit_insn (gen_cstore4_media (tem, operands[1],
11228 operands[2], operands[3]));
11231 operands[3] = const0_rtx;
11234 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11237 (define_expand "cstoresi4"
11238 [(set (match_operand:SI 0 "register_operand" "=r")
11239 (match_operator:SI 1 "comparison_operator"
11240 [(match_operand:SI 2 "cmpsi_operand" "")
11241 (match_operand:SI 3 "arith_operand" "")]))]
11242 "TARGET_SH1 || TARGET_SHMEDIA"
11244 if (TARGET_SHMEDIA)
11246 emit_insn (gen_cstore4_media (operands[0], operands[1],
11247 operands[2], operands[3]));
11251 if (sh_expand_t_scc (operands))
11254 if (! currently_expanding_to_rtl)
11257 sh_emit_compare_and_set (operands, SImode);
11261 (define_expand "cstoredi4"
11262 [(set (match_operand:SI 0 "register_operand" "=r")
11263 (match_operator:SI 1 "comparison_operator"
11264 [(match_operand:DI 2 "arith_operand" "")
11265 (match_operand:DI 3 "arith_operand" "")]))]
11266 "TARGET_SH2 || TARGET_SHMEDIA"
11268 if (TARGET_SHMEDIA)
11270 emit_insn (gen_cstore4_media (operands[0], operands[1],
11271 operands[2], operands[3]));
11275 if (sh_expand_t_scc (operands))
11278 if (! currently_expanding_to_rtl)
11281 sh_emit_compare_and_set (operands, DImode);
11285 ;; Move the complement of the T reg to a reg.
11286 ;; On SH2A the movrt insn can be used.
11287 ;; On anything else than SH2A this has to be done with multiple instructions.
11288 ;; One obvious way would be:
11293 ;; However, this puts pressure on r0 in most cases and thus the following is
11299 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11300 ;; becomes a one instruction operation. Moreover, care must be taken that
11301 ;; the insn can still be combined with inverted compare and branch code
11302 ;; around it. On the other hand, if a function returns the complement of
11303 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11304 ;; lead to better code.
11305 (define_expand "movnegt"
11306 [(set (match_operand:SI 0 "arith_reg_dest" "")
11307 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11311 emit_insn (gen_movrt (operands[0], operands[1]));
11314 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11315 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11320 (define_insn "movrt_negc"
11321 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11322 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11323 (set (reg:SI T_REG) (const_int 1))
11324 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11327 [(set_attr "type" "arith")])
11329 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11330 ;; pattern can be used by the combine pass. Using a scratch reg for the
11331 ;; -1 constant results in slightly better register allocations compared to
11332 ;; generating a pseudo reg before reload.
11333 (define_insn_and_split "*movrt_negc"
11334 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11335 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11336 (clobber (match_scratch:SI 2 "=r"))
11337 (clobber (reg:SI T_REG))]
11338 "TARGET_SH1 && ! TARGET_SH2A"
11340 "&& reload_completed"
11341 [(set (match_dup 2) (const_int -1))
11343 [(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
11344 (set (reg:SI T_REG) (const_int 1))
11345 (use (match_dup 2))])])
11347 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11348 ;; clobber the T bit, which is useful when storing the T bit and the
11349 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11350 ;; Usually we don't want this insn to be matched, except for cases where the
11351 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11352 (define_insn_and_split "movrt_xor"
11353 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11354 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11355 (use (reg:SI T_REG))]
11356 "TARGET_SH1 && !TARGET_SH2A"
11358 "&& reload_completed"
11359 [(set (match_dup 0) (reg:SI T_REG))
11360 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11362 ;; Store the T bit and the negated T bit in two regs in parallel. There is
11363 ;; no real insn to do that, but specifying this pattern will give combine
11364 ;; some opportunities.
11365 (define_insn_and_split "*movt_movrt"
11366 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11367 (match_operand:SI 1 "negt_reg_operand"))
11368 (set (match_operand:SI 2 "arith_reg_dest")
11369 (match_operand:SI 3 "t_reg_operand"))])]
11375 rtx i = TARGET_SH2A
11376 ? gen_movrt (operands[0], get_t_reg_rtx ())
11377 : gen_movrt_xor (operands[0], get_t_reg_rtx ());
11380 emit_insn (gen_movt (operands[2], get_t_reg_rtx ()));
11384 (define_insn_and_split "*movt_movrt"
11385 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11386 (match_operand:SI 1 "t_reg_operand"))
11387 (set (match_operand:SI 2 "arith_reg_dest")
11388 (match_operand:SI 3 "negt_reg_operand"))])]
11392 [(parallel [(set (match_dup 2) (match_dup 3))
11393 (set (match_dup 0) (match_dup 1))])])
11395 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11396 ;; T = 1: 0x80000000 -> reg
11397 ;; T = 0: 0x7FFFFFFF -> reg
11398 ;; This works because 0 - 0x80000000 = 0x80000000.
11399 (define_insn_and_split "*mov_t_msb_neg"
11400 [(set (match_operand:SI 0 "arith_reg_dest")
11401 (minus:SI (const_int -2147483648) ;; 0x80000000
11402 (match_operand 1 "t_reg_operand")))
11403 (clobber (reg:SI T_REG))]
11406 "&& can_create_pseudo_p ()"
11407 [(set (match_dup 2) (const_int -2147483648))
11408 (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2))
11410 (clobber (reg:SI T_REG))])]
11412 operands[2] = gen_reg_rtx (SImode);
11415 ;; These are essentially the same as above, but with the inverted T bit.
11416 ;; Combine recognizes the split patterns, but does not take them sometimes
11417 ;; if the T_REG clobber is specified. Instead it tries to split out the
11418 ;; T bit negation. Since these splits are supposed to be taken only by
11419 ;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this
11422 [(set (match_operand:SI 0 "arith_reg_dest")
11423 (plus:SI (match_operand 1 "negt_reg_operand")
11424 (const_int 2147483647)))] ;; 0x7fffffff
11425 "TARGET_SH1 && can_create_pseudo_p ()"
11426 [(parallel [(set (match_dup 0)
11427 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11428 (clobber (reg:SI T_REG))])])
11431 [(set (match_operand:SI 0 "arith_reg_dest")
11432 (if_then_else:SI (match_operand 1 "t_reg_operand")
11433 (const_int 2147483647) ;; 0x7fffffff
11434 (const_int -2147483648)))] ;; 0x80000000
11435 "TARGET_SH1 && can_create_pseudo_p ()"
11436 [(parallel [(set (match_dup 0)
11437 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11438 (clobber (reg:SI T_REG))])])
11440 ;; The *negnegt pattern helps the combine pass to figure out how to fold
11441 ;; an explicit double T bit negation.
11442 (define_insn_and_split "*negnegt"
11443 [(set (reg:SI T_REG)
11444 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
11450 ;; Store T bit as all zeros or ones in a reg.
11451 (define_insn "mov_neg_si_t"
11452 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11453 (neg:SI (match_operand 1 "t_reg_operand" "")))]
11456 [(set_attr "type" "arith")])
11458 ;; Store negated T bit as all zeros or ones in a reg.
11459 ;; Use the following sequence:
11460 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
11461 ;; not Rn,Rn ! Rn = 0 - Rn
11463 [(set (match_operand:SI 0 "arith_reg_dest" "")
11464 (neg:SI (match_operand 1 "negt_reg_operand" "")))]
11466 [(set (match_dup 0) (neg:SI (reg:SI T_REG)))
11467 (set (match_dup 0) (not:SI (match_dup 0)))])
11469 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
11470 (define_insn_and_split "*movtt"
11471 [(set (reg:SI T_REG)
11472 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
11478 ;; Invert the T bit.
11479 ;; On SH2A we can use the nott insn. On anything else this must be done with
11480 ;; multiple insns like:
11483 (define_insn_and_split "nott"
11484 [(set (reg:SI T_REG)
11485 (xor:SI (match_operand:SI 0 "t_reg_operand" "") (const_int 1)))]
11488 gcc_assert (TARGET_SH2A);
11491 "! TARGET_SH2A && can_create_pseudo_p ()"
11492 [(set (match_dup 0) (reg:SI T_REG))
11493 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
11495 operands[0] = gen_reg_rtx (SImode);
11498 ;; Store T bit as MSB in a reg.
11499 ;; T = 0: 0x00000000 -> reg
11500 ;; T = 1: 0x80000000 -> reg
11501 (define_insn_and_split "*movt_msb"
11502 [(set (match_operand:SI 0 "arith_reg_dest")
11503 (mult:SI (match_operand:SI 1 "t_reg_operand")
11504 (const_int -2147483648))) ;; 0xffffffff80000000
11505 (clobber (reg:SI T_REG))]
11509 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
11511 ;; Store inverted T bit as MSB in a reg.
11512 ;; T = 0: 0x80000000 -> reg
11513 ;; T = 1: 0x00000000 -> reg
11514 ;; On SH2A we can get away without clobbering the T_REG.
11515 (define_insn_and_split "*negt_msb"
11516 [(set (match_operand:SI 0 "arith_reg_dest")
11517 (match_operand:SI 1 "negt_reg_shl31_operand"))]
11520 "&& can_create_pseudo_p ()"
11523 rtx tmp = gen_reg_rtx (SImode);
11524 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
11525 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
11529 (define_insn_and_split "*negt_msb"
11530 [(set (match_operand:SI 0 "arith_reg_dest")
11531 (match_operand:SI 1 "negt_reg_shl31_operand"))
11532 (clobber (reg:SI T_REG))]
11533 "TARGET_SH1 && !TARGET_SH2A"
11535 "&& can_create_pseudo_p ()"
11538 rtx tmp = gen_reg_rtx (SImode);
11539 emit_move_insn (tmp, get_t_reg_rtx ());
11540 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
11541 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
11545 ;; The *cset_zero patterns convert optimizations such as
11546 ;; "if (test) x = 0;"
11548 ;; "x &= -(test == 0);"
11549 ;; back to conditional branch sequences if zero-displacement branches
11551 ;; FIXME: These patterns can be removed when conditional execution patterns
11552 ;; are implemented, since ifcvt will not perform these optimizations if
11553 ;; conditional execution is supported.
11554 (define_insn "*cset_zero"
11555 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11556 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
11558 (match_operand:SI 2 "arith_reg_operand" "0")))]
11559 "TARGET_SH1 && TARGET_ZDCBRANCH"
11561 return "bf 0f" "\n"
11565 [(set_attr "type" "arith") ;; poor approximation
11566 (set_attr "length" "4")])
11568 (define_insn "*cset_zero"
11569 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11570 (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
11571 (match_operand:SI 2 "arith_reg_operand" "0")
11573 "TARGET_SH1 && TARGET_ZDCBRANCH"
11575 return "bt 0f" "\n"
11579 [(set_attr "type" "arith") ;; poor approximation
11580 (set_attr "length" "4")])
11582 (define_expand "cstoresf4"
11583 [(set (match_operand:SI 0 "register_operand" "=r")
11584 (match_operator:SI 1 "sh_float_comparison_operator"
11585 [(match_operand:SF 2 "arith_operand" "")
11586 (match_operand:SF 3 "arith_operand" "")]))]
11587 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
11589 if (TARGET_SHMEDIA)
11591 emit_insn (gen_cstore4_media (operands[0], operands[1],
11592 operands[2], operands[3]));
11596 if (! currently_expanding_to_rtl)
11599 sh_emit_compare_and_set (operands, SFmode);
11603 (define_expand "cstoredf4"
11604 [(set (match_operand:SI 0 "register_operand" "=r")
11605 (match_operator:SI 1 "sh_float_comparison_operator"
11606 [(match_operand:DF 2 "arith_operand" "")
11607 (match_operand:DF 3 "arith_operand" "")]))]
11608 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11610 if (TARGET_SHMEDIA)
11612 emit_insn (gen_cstore4_media (operands[0], operands[1],
11613 operands[2], operands[3]));
11617 if (! currently_expanding_to_rtl)
11620 sh_emit_compare_and_set (operands, DFmode);
11624 ;; -------------------------------------------------------------------------
11625 ;; Instructions to cope with inline literal tables
11626 ;; -------------------------------------------------------------------------
11628 ;; 2 byte integer in line
11629 (define_insn "consttable_2"
11630 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11631 (match_operand 1 "" "")]
11635 if (operands[1] != const0_rtx)
11636 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
11639 [(set_attr "length" "2")
11640 (set_attr "in_delay_slot" "no")])
11642 ;; 4 byte integer in line
11643 (define_insn "consttable_4"
11644 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11645 (match_operand 1 "" "")]
11649 if (operands[1] != const0_rtx)
11651 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
11652 mark_symbol_refs_as_used (operands[0]);
11656 [(set_attr "length" "4")
11657 (set_attr "in_delay_slot" "no")])
11659 ;; 8 byte integer in line
11660 (define_insn "consttable_8"
11661 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11662 (match_operand 1 "" "")]
11666 if (operands[1] != const0_rtx)
11667 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
11670 [(set_attr "length" "8")
11671 (set_attr "in_delay_slot" "no")])
11673 ;; 4 byte floating point
11674 (define_insn "consttable_sf"
11675 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
11676 (match_operand 1 "" "")]
11680 if (operands[1] != const0_rtx)
11683 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11684 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
11688 [(set_attr "length" "4")
11689 (set_attr "in_delay_slot" "no")])
11691 ;; 8 byte floating point
11692 (define_insn "consttable_df"
11693 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
11694 (match_operand 1 "" "")]
11698 if (operands[1] != const0_rtx)
11701 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11702 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
11706 [(set_attr "length" "8")
11707 (set_attr "in_delay_slot" "no")])
11709 ;; Alignment is needed for some constant tables; it may also be added for
11710 ;; Instructions at the start of loops, or after unconditional branches.
11711 ;; ??? We would get more accurate lengths if we did instruction
11712 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
11713 ;; here is too conservative.
11715 ;; align to a two byte boundary
11716 (define_expand "align_2"
11717 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
11721 ;; Align to a four byte boundary.
11722 ;; align_4 and align_log are instructions for the starts of loops, or
11723 ;; after unconditional branches, which may take up extra room.
11724 (define_expand "align_4"
11725 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
11729 ;; Align to a cache line boundary.
11730 (define_insn "align_log"
11731 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
11734 [(set_attr "length" "0")
11735 (set_attr "in_delay_slot" "no")])
11737 ;; Emitted at the end of the literal table, used to emit the
11738 ;; 32bit branch labels if needed.
11739 (define_insn "consttable_end"
11740 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
11743 return output_jump_label_table ();
11745 [(set_attr "in_delay_slot" "no")])
11747 ;; Emitted at the end of the window in the literal table.
11748 (define_insn "consttable_window_end"
11749 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
11752 [(set_attr "length" "0")
11753 (set_attr "in_delay_slot" "no")])
11755 ;; -------------------------------------------------------------------------
11756 ;; Minimum / maximum operations.
11757 ;; -------------------------------------------------------------------------
11759 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
11760 ;; and smax standard name patterns are defined, they will be used during
11761 ;; initial expansion and combine will then be able to form the actual min-max
11763 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
11764 ;; clipped, but there is currently no way of making use of this information.
11765 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11766 (define_expand "<code>si3"
11767 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11768 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11769 (match_operand 2 "const_int_operand")))
11770 (clobber (reg:SI T_REG))])]
11773 /* Force the comparison value into a register, because greater-than
11774 comparisons can work only on registers. Combine will be able to pick up
11775 the constant value from the REG_EQUAL note when trying to form a min-max
11777 operands[2] = force_reg (SImode, operands[2]);
11781 ;; smax (smin (...))
11783 ;; smin (smax (...))
11784 (define_insn_and_split "*clips"
11785 [(set (match_operand:SI 0 "arith_reg_dest")
11786 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
11787 (match_operand 2 "clips_max_const_int"))
11788 (match_operand 3 "clips_min_const_int")))]
11792 [(set (match_dup 0)
11793 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
11795 (define_insn "*clips"
11796 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11797 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
11798 (match_operand 2 "clips_min_const_int"))
11799 (match_operand 3 "clips_max_const_int")))]
11802 if (INTVAL (operands[3]) == 127)
11803 return "clips.b %0";
11804 else if (INTVAL (operands[3]) == 32767)
11805 return "clips.w %0";
11807 gcc_unreachable ();
11809 [(set_attr "type" "arith")])
11811 ;; If the expanded smin or smax patterns were not combined, split them into
11812 ;; a compare and branch sequence, because there are no real smin or smax
11814 (define_insn_and_split "*<code>si3"
11815 [(set (match_operand:SI 0 "arith_reg_dest")
11816 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11817 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
11818 (clobber (reg:SI T_REG))]
11819 "TARGET_SH2A && can_create_pseudo_p ()"
11824 rtx skip_label = gen_label_rtx ();
11825 emit_move_insn (operands[0], operands[1]);
11827 rtx cmp_val = operands[2];
11828 if (satisfies_constraint_M (cmp_val))
11829 cmp_val = const0_rtx;
11831 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
11832 emit_jump_insn (<CODE> == SMIN
11833 ? gen_branch_false (skip_label)
11834 : gen_branch_true (skip_label));
11836 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
11840 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
11841 ;; with a register and a constant.
11842 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
11843 ;; clipped, but there is currently no way of making use of this information.
11844 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11845 (define_expand "uminsi3"
11846 [(set (match_operand:SI 0 "arith_reg_dest")
11847 (umin:SI (match_operand:SI 1 "arith_reg_operand")
11848 (match_operand 2 "const_int_operand")))]
11851 if (INTVAL (operands[2]) == 1)
11853 emit_insn (gen_clipu_one (operands[0], operands[1]));
11856 else if (! clipu_max_const_int (operands[2], VOIDmode))
11860 (define_insn "*clipu"
11861 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11862 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
11863 (match_operand 2 "clipu_max_const_int")))]
11866 if (INTVAL (operands[2]) == 255)
11867 return "clipu.b %0";
11868 else if (INTVAL (operands[2]) == 65535)
11869 return "clipu.w %0";
11871 gcc_unreachable ();
11873 [(set_attr "type" "arith")])
11875 (define_insn_and_split "clipu_one"
11876 [(set (match_operand:SI 0 "arith_reg_dest")
11877 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
11878 (clobber (reg:SI T_REG))]
11881 "&& can_create_pseudo_p ()"
11884 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
11885 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
11889 ;; -------------------------------------------------------------------------
11891 ;; -------------------------------------------------------------------------
11893 ;; String/block move insn.
11895 (define_expand "movmemsi"
11896 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
11897 (mem:BLK (match_operand:BLK 1 "" "")))
11898 (use (match_operand:SI 2 "nonmemory_operand" ""))
11899 (use (match_operand:SI 3 "immediate_operand" ""))
11900 (clobber (reg:SI PR_REG))
11901 (clobber (reg:SI R4_REG))
11902 (clobber (reg:SI R5_REG))
11903 (clobber (reg:SI R0_REG))])]
11904 "TARGET_SH1 && ! TARGET_SH5"
11906 if(expand_block_move (operands))
11911 (define_insn "block_move_real"
11912 [(parallel [(set (mem:BLK (reg:SI R4_REG))
11913 (mem:BLK (reg:SI R5_REG)))
11914 (use (match_operand:SI 0 "arith_reg_operand" "r"))
11915 (clobber (reg:SI PR_REG))
11916 (clobber (reg:SI R0_REG))])]
11917 "TARGET_SH1 && ! TARGET_HARD_SH4"
11919 [(set_attr "type" "sfunc")
11920 (set_attr "needs_delay_slot" "yes")])
11922 (define_insn "block_lump_real"
11923 [(parallel [(set (mem:BLK (reg:SI R4_REG))
11924 (mem:BLK (reg:SI R5_REG)))
11925 (use (match_operand:SI 0 "arith_reg_operand" "r"))
11926 (use (reg:SI R6_REG))
11927 (clobber (reg:SI PR_REG))
11928 (clobber (reg:SI T_REG))
11929 (clobber (reg:SI R4_REG))
11930 (clobber (reg:SI R5_REG))
11931 (clobber (reg:SI R6_REG))
11932 (clobber (reg:SI R0_REG))])]
11933 "TARGET_SH1 && ! TARGET_HARD_SH4"
11935 [(set_attr "type" "sfunc")
11936 (set_attr "needs_delay_slot" "yes")])
11938 (define_insn "block_move_real_i4"
11939 [(parallel [(set (mem:BLK (reg:SI R4_REG))
11940 (mem:BLK (reg:SI R5_REG)))
11941 (use (match_operand:SI 0 "arith_reg_operand" "r"))
11942 (clobber (reg:SI PR_REG))
11943 (clobber (reg:SI R0_REG))
11944 (clobber (reg:SI R1_REG))
11945 (clobber (reg:SI R2_REG))])]
11948 [(set_attr "type" "sfunc")
11949 (set_attr "needs_delay_slot" "yes")])
11951 (define_insn "block_lump_real_i4"
11952 [(parallel [(set (mem:BLK (reg:SI R4_REG))
11953 (mem:BLK (reg:SI R5_REG)))
11954 (use (match_operand:SI 0 "arith_reg_operand" "r"))
11955 (use (reg:SI R6_REG))
11956 (clobber (reg:SI PR_REG))
11957 (clobber (reg:SI T_REG))
11958 (clobber (reg:SI R4_REG))
11959 (clobber (reg:SI R5_REG))
11960 (clobber (reg:SI R6_REG))
11961 (clobber (reg:SI R0_REG))
11962 (clobber (reg:SI R1_REG))
11963 (clobber (reg:SI R2_REG))
11964 (clobber (reg:SI R3_REG))])]
11967 [(set_attr "type" "sfunc")
11968 (set_attr "needs_delay_slot" "yes")])
11970 ;; -------------------------------------------------------------------------
11971 ;; Floating point instructions.
11972 ;; -------------------------------------------------------------------------
11974 ;; ??? All patterns should have a type attribute.
11976 (define_expand "movpsi"
11977 [(set (match_operand:PSI 0 "register_operand" "")
11978 (match_operand:PSI 1 "general_movsrc_operand" ""))]
11979 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
11982 ;; The c / m alternative is a fake to guide reload to load directly into
11983 ;; fpscr, since reload doesn't know how to use post-increment.
11984 ;; TARGET_LEGITIMATE_ADDRESS_P guards about bogus addresses before reload,
11985 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
11986 ;; predicate after reload.
11987 ;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
11988 ;; like a mac -> gpr move.
11989 (define_insn "fpu_switch"
11990 [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
11991 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
11993 && (! reload_completed
11994 || true_regnum (operands[0]) != FPSCR_REG
11995 || !MEM_P (operands[1])
11996 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
11998 ! precision stays the same
12007 [(set_attr "length" "0,2,2,4,2,2,2,2,2")
12008 (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,
12012 [(set (reg:PSI FPSCR_REG)
12013 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12014 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && peep2_reg_dead_p (1, operands[0])"
12017 rtx fpscr, mem, new_insn;
12019 fpscr = SET_DEST (PATTERN (curr_insn));
12020 mem = SET_SRC (PATTERN (curr_insn));
12021 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12023 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12024 add_reg_note (new_insn, REG_INC, operands[0]);
12029 [(set (reg:PSI FPSCR_REG)
12030 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12031 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
12032 && (flag_peephole2 ? epilogue_completed : reload_completed)"
12035 rtx fpscr, mem, new_insn;
12037 fpscr = SET_DEST (PATTERN (curr_insn));
12038 mem = SET_SRC (PATTERN (curr_insn));
12039 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12041 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12042 add_reg_note (new_insn, REG_INC, operands[0]);
12044 if (!find_regno_note (curr_insn, REG_DEAD, true_regnum (operands[0])))
12045 emit_insn (gen_addsi3 (operands[0], operands[0], GEN_INT (-4)));
12049 ;; ??? This uses the fp unit, but has no type indicating that.
12050 ;; If we did that, this would either give a bogus latency or introduce
12051 ;; a bogus FIFO constraint.
12052 ;; Since this insn is currently only used for prologues/epilogues,
12053 ;; it is probably best to claim no function unit, which matches the
12054 ;; current setting.
12055 (define_insn "toggle_sz"
12056 [(set (reg:PSI FPSCR_REG)
12057 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
12058 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12060 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12062 ;; There's no way we can use it today, since optimize mode switching
12063 ;; doesn't enable us to know from which mode we're switching to the
12064 ;; mode it requests, to tell whether we can use a relative mode switch
12065 ;; (like toggle_pr) or an absolute switch (like loading fpscr from
12067 (define_insn "toggle_pr"
12068 [(set (reg:PSI FPSCR_REG)
12069 (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
12070 "TARGET_SH4A_FP && ! TARGET_FPU_SINGLE"
12072 [(set_attr "type" "fpscr_toggle")])
12074 (define_expand "addsf3"
12075 [(set (match_operand:SF 0 "arith_reg_operand" "")
12076 (plus:SF (match_operand:SF 1 "arith_reg_operand" "")
12077 (match_operand:SF 2 "arith_reg_operand" "")))]
12078 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12082 expand_sf_binop (&gen_addsf3_i, operands);
12087 (define_insn "*addsf3_media"
12088 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12089 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12090 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12091 "TARGET_SHMEDIA_FPU"
12092 "fadd.s %1, %2, %0"
12093 [(set_attr "type" "fparith_media")])
12095 (define_insn_and_split "unary_sf_op"
12096 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12101 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12102 (match_operator:SF 2 "unary_float_operator"
12103 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12104 (parallel [(match_operand 4
12105 "const_int_operand" "n")]))]))
12106 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12107 "TARGET_SHMEDIA_FPU"
12109 "TARGET_SHMEDIA_FPU && reload_completed"
12110 [(set (match_dup 5) (match_dup 6))]
12112 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12113 rtx op1 = gen_rtx_REG (SFmode,
12114 (true_regnum (operands[1])
12115 + (INTVAL (operands[4]) ^ endian)));
12117 operands[7] = gen_rtx_REG (SFmode,
12118 (true_regnum (operands[0])
12119 + (INTVAL (operands[3]) ^ endian)));
12120 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12122 [(set_attr "type" "fparith_media")])
12124 (define_insn_and_split "binary_sf_op0"
12125 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12127 (match_operator:SF 3 "binary_float_operator"
12128 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12129 (parallel [(const_int 0)]))
12130 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12131 (parallel [(const_int 0)]))])
12134 (parallel [(const_int 1)]))))]
12135 "TARGET_SHMEDIA_FPU"
12137 "&& reload_completed"
12138 [(set (match_dup 4) (match_dup 5))]
12140 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12141 rtx op1 = gen_rtx_REG (SFmode,
12142 true_regnum (operands[1]) + endian);
12143 rtx op2 = gen_rtx_REG (SFmode,
12144 true_regnum (operands[2]) + endian);
12146 operands[4] = gen_rtx_REG (SFmode,
12147 true_regnum (operands[0]) + endian);
12148 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12150 [(set_attr "type" "fparith_media")])
12152 (define_insn_and_split "binary_sf_op1"
12153 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12157 (parallel [(const_int 0)]))
12158 (match_operator:SF 3 "binary_float_operator"
12159 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12160 (parallel [(const_int 1)]))
12161 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12162 (parallel [(const_int 1)]))])))]
12163 "TARGET_SHMEDIA_FPU"
12165 "&& reload_completed"
12166 [(set (match_dup 4) (match_dup 5))]
12168 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12169 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12170 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12172 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12173 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12175 [(set_attr "type" "fparith_media")])
12177 (define_insn "addsf3_i"
12178 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12179 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12180 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12181 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12184 [(set_attr "type" "fp")
12185 (set_attr "fp_mode" "single")])
12187 (define_expand "subsf3"
12188 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12189 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12190 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12191 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12195 expand_sf_binop (&gen_subsf3_i, operands);
12200 (define_insn "*subsf3_media"
12201 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12202 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12203 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12204 "TARGET_SHMEDIA_FPU"
12205 "fsub.s %1, %2, %0"
12206 [(set_attr "type" "fparith_media")])
12208 (define_insn "subsf3_i"
12209 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12210 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12211 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12212 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12215 [(set_attr "type" "fp")
12216 (set_attr "fp_mode" "single")])
12218 (define_expand "mulsf3"
12219 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12220 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12221 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12222 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12226 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2],
12227 get_fpscr_rtx ()));
12232 (define_insn "*mulsf3_media"
12233 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12234 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12235 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12236 "TARGET_SHMEDIA_FPU"
12237 "fmul.s %1, %2, %0"
12238 [(set_attr "type" "fparith_media")])
12240 (define_insn "mulsf3_i"
12241 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12242 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12243 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12244 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12247 [(set_attr "type" "fp")
12248 (set_attr "fp_mode" "single")])
12250 ;; FMA (fused multiply-add) patterns
12251 (define_expand "fmasf4"
12252 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12253 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
12254 (match_operand:SF 2 "fp_arith_reg_operand")
12255 (match_operand:SF 3 "fp_arith_reg_operand")))]
12256 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12260 emit_sf_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
12261 operands[3], get_fpscr_rtx ()));
12266 (define_insn "fmasf4_i"
12267 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12268 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
12269 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12270 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
12271 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
12274 [(set_attr "type" "fp")
12275 (set_attr "fp_mode" "single")])
12277 (define_insn "fmasf4_media"
12278 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12279 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12280 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12281 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12282 "TARGET_SHMEDIA_FPU"
12283 "fmac.s %1, %2, %0"
12284 [(set_attr "type" "fparith_media")])
12286 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
12287 ;; previous transformations. If FMA is generally allowed, let the combine
12288 ;; pass utilize it.
12289 (define_insn_and_split "*fmasf4"
12290 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12291 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
12292 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12293 (match_operand:SF 3 "arith_reg_operand" "0")))
12294 (use (match_operand:PSI 4 "fpscr_operand"))]
12295 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
12297 "&& can_create_pseudo_p ()"
12298 [(parallel [(set (match_dup 0)
12299 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
12300 (use (match_dup 4))])]
12302 /* Change 'b * a + a' into 'a * b + a'.
12303 This is better for register allocation. */
12304 if (REGNO (operands[2]) == REGNO (operands[3]))
12306 rtx tmp = operands[1];
12307 operands[1] = operands[2];
12311 [(set_attr "type" "fp")
12312 (set_attr "fp_mode" "single")])
12314 (define_insn "*fmasf4_media"
12315 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12316 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12317 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12318 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12319 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
12320 "fmac.s %1, %2, %0"
12321 [(set_attr "type" "fparith_media")])
12323 (define_expand "divsf3"
12324 [(set (match_operand:SF 0 "arith_reg_operand" "")
12325 (div:SF (match_operand:SF 1 "arith_reg_operand" "")
12326 (match_operand:SF 2 "arith_reg_operand" "")))]
12327 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12331 expand_sf_binop (&gen_divsf3_i, operands);
12336 (define_insn "*divsf3_media"
12337 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12338 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12339 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12340 "TARGET_SHMEDIA_FPU"
12341 "fdiv.s %1, %2, %0"
12342 [(set_attr "type" "fdiv_media")])
12344 (define_insn "divsf3_i"
12345 [(set (match_operand:SF 0 "arith_reg_dest" "=f")
12346 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
12347 (match_operand:SF 2 "arith_reg_operand" "f")))
12348 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12351 [(set_attr "type" "fdiv")
12352 (set_attr "fp_mode" "single")])
12354 (define_insn "floatdisf2"
12355 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12356 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12357 "TARGET_SHMEDIA_FPU"
12359 [(set_attr "type" "fpconv_media")])
12361 (define_expand "floatsisf2"
12362 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12363 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
12364 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12366 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12368 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1],
12369 get_fpscr_rtx ()));
12374 (define_insn "*floatsisf2_media"
12375 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12376 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12377 "TARGET_SHMEDIA_FPU"
12379 [(set_attr "type" "fpconv_media")])
12381 (define_insn "floatsisf2_i4"
12382 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12383 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
12384 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12385 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12387 [(set_attr "type" "fp")
12388 (set_attr "fp_mode" "single")])
12390 (define_insn "*floatsisf2_ie"
12391 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12392 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
12393 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12395 [(set_attr "type" "fp")])
12397 (define_insn "fix_truncsfdi2"
12398 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12399 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12400 "TARGET_SHMEDIA_FPU"
12402 [(set_attr "type" "fpconv_media")])
12404 (define_expand "fix_truncsfsi2"
12405 [(set (match_operand:SI 0 "fpul_operand" "=y")
12406 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12407 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12409 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12411 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1],
12412 get_fpscr_rtx ()));
12417 (define_insn "*fix_truncsfsi2_media"
12418 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12419 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12420 "TARGET_SHMEDIA_FPU"
12422 [(set_attr "type" "fpconv_media")])
12424 (define_insn "fix_truncsfsi2_i4"
12425 [(set (match_operand:SI 0 "fpul_operand" "=y")
12426 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12427 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12428 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12430 [(set_attr "type" "ftrc_s")
12431 (set_attr "fp_mode" "single")])
12433 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
12434 ;; fix_truncsfsi2_i4.
12435 ;; (define_insn "fix_truncsfsi2_i4_2"
12436 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12437 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12438 ;; (use (reg:PSI FPSCR_REG))
12439 ;; (clobber (reg:SI FPUL_REG))]
12442 ;; [(set_attr "length" "4")
12443 ;; (set_attr "fp_mode" "single")])
12446 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12447 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12448 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
12449 ;; (clobber (reg:SI FPUL_REG))]
12451 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
12452 ;; (use (match_dup 2))])
12453 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
12455 (define_insn "*fixsfsi"
12456 [(set (match_operand:SI 0 "fpul_operand" "=y")
12457 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12458 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12460 [(set_attr "type" "fp")])
12462 (define_insn "cmpgtsf_t"
12463 [(set (reg:SI T_REG)
12464 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12465 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12466 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12468 [(set_attr "type" "fp_cmp")
12469 (set_attr "fp_mode" "single")])
12471 (define_insn "cmpeqsf_t"
12472 [(set (reg:SI T_REG)
12473 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12474 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12475 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12477 [(set_attr "type" "fp_cmp")
12478 (set_attr "fp_mode" "single")])
12480 (define_insn "ieee_ccmpeqsf_t"
12481 [(set (reg:SI T_REG)
12482 (ior:SI (reg:SI T_REG)
12483 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12484 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
12485 "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12487 return output_ieee_ccmpeq (insn, operands);
12489 [(set_attr "length" "4")])
12492 (define_insn "cmpgtsf_t_i4"
12493 [(set (reg:SI T_REG)
12494 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12495 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12496 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12497 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12499 [(set_attr "type" "fp_cmp")
12500 (set_attr "fp_mode" "single")])
12502 (define_insn "cmpeqsf_t_i4"
12503 [(set (reg:SI T_REG)
12504 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12505 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12506 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12507 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12509 [(set_attr "type" "fp_cmp")
12510 (set_attr "fp_mode" "single")])
12512 (define_insn "*ieee_ccmpeqsf_t_4"
12513 [(set (reg:SI T_REG)
12514 (ior:SI (reg:SI T_REG)
12515 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12516 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
12517 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12518 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12520 return output_ieee_ccmpeq (insn, operands);
12522 [(set_attr "length" "4")
12523 (set_attr "fp_mode" "single")])
12525 (define_insn "cmpeqsf_media"
12526 [(set (match_operand:SI 0 "register_operand" "=r")
12527 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12528 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12529 "TARGET_SHMEDIA_FPU"
12530 "fcmpeq.s %1, %2, %0"
12531 [(set_attr "type" "fcmp_media")])
12533 (define_insn "cmpgtsf_media"
12534 [(set (match_operand:SI 0 "register_operand" "=r")
12535 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12536 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12537 "TARGET_SHMEDIA_FPU"
12538 "fcmpgt.s %1, %2, %0"
12539 [(set_attr "type" "fcmp_media")])
12541 (define_insn "cmpgesf_media"
12542 [(set (match_operand:SI 0 "register_operand" "=r")
12543 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12544 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12545 "TARGET_SHMEDIA_FPU"
12546 "fcmpge.s %1, %2, %0"
12547 [(set_attr "type" "fcmp_media")])
12549 (define_insn "cmpunsf_media"
12550 [(set (match_operand:SI 0 "register_operand" "=r")
12551 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12552 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12553 "TARGET_SHMEDIA_FPU"
12554 "fcmpun.s %1, %2, %0"
12555 [(set_attr "type" "fcmp_media")])
12557 (define_expand "cbranchsf4"
12559 (if_then_else (match_operator 0 "sh_float_comparison_operator"
12560 [(match_operand:SF 1 "arith_operand" "")
12561 (match_operand:SF 2 "arith_operand" "")])
12562 (match_operand 3 "" "")
12564 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12566 if (TARGET_SHMEDIA)
12567 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
12570 sh_emit_compare_and_branch (operands, SFmode);
12574 (define_expand "negsf2"
12575 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12576 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12577 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12581 expand_sf_unop (&gen_negsf2_i, operands);
12586 (define_insn "*negsf2_media"
12587 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12588 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12589 "TARGET_SHMEDIA_FPU"
12591 [(set_attr "type" "fmove_media")])
12593 (define_insn "negsf2_i"
12594 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12595 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12596 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12599 [(set_attr "type" "fmove")
12600 (set_attr "fp_mode" "single")])
12602 (define_expand "sqrtsf2"
12603 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12604 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12605 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
12609 expand_sf_unop (&gen_sqrtsf2_i, operands);
12614 (define_insn "*sqrtsf2_media"
12615 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12616 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12617 "TARGET_SHMEDIA_FPU"
12619 [(set_attr "type" "fdiv_media")])
12621 (define_insn "sqrtsf2_i"
12622 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12623 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12624 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12627 [(set_attr "type" "fdiv")
12628 (set_attr "fp_mode" "single")])
12630 (define_insn "rsqrtsf2"
12631 [(set (match_operand:SF 0 "register_operand" "=f")
12632 (div:SF (match_operand:SF 1 "immediate_operand" "i")
12633 (sqrt:SF (match_operand:SF 2 "register_operand" "0"))))
12634 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12635 "TARGET_FPU_ANY && TARGET_FSRRA
12636 && operands[1] == CONST1_RTX (SFmode)"
12638 [(set_attr "type" "fsrra")
12639 (set_attr "fp_mode" "single")])
12641 ;; When the sincos pattern is defined, the builtin functions sin and cos
12642 ;; will be expanded to the sincos pattern and one of the output values will
12644 (define_expand "sincossf3"
12645 [(set (match_operand:SF 0 "nonimmediate_operand")
12646 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
12647 (set (match_operand:SF 1 "nonimmediate_operand")
12648 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
12649 "TARGET_FPU_ANY && TARGET_FSCA"
12651 rtx scaled = gen_reg_rtx (SFmode);
12652 rtx truncated = gen_reg_rtx (SImode);
12653 rtx fsca = gen_reg_rtx (V2SFmode);
12654 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
12656 emit_sf_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
12657 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
12658 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
12659 get_fpscr_rtx ()));
12661 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
12662 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
12666 (define_insn_and_split "fsca"
12667 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12669 (unspec:SF [(mult:SF
12670 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
12671 (match_operand:SF 2 "fsca_scale_factor" "i"))
12673 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
12675 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12676 "TARGET_FPU_ANY && TARGET_FSCA"
12678 "&& !fpul_operand (operands[1], SImode)"
12681 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
12682 to a simple reg, otherwise reload will have trouble reloading the
12683 pseudo into fpul. */
12684 rtx x = XEXP (operands[1], 0);
12685 while (x != NULL_RTX && !fpul_operand (x, SImode))
12687 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
12691 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
12692 emit_insn (gen_fsca (operands[0], x, operands[2], operands[3]));
12695 [(set_attr "type" "fsca")
12696 (set_attr "fp_mode" "single")])
12698 (define_expand "abssf2"
12699 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12700 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12701 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12705 expand_sf_unop (&gen_abssf2_i, operands);
12710 (define_insn "*abssf2_media"
12711 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12712 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12713 "TARGET_SHMEDIA_FPU"
12715 [(set_attr "type" "fmove_media")])
12717 (define_insn "abssf2_i"
12718 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12719 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12720 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12723 [(set_attr "type" "fmove")
12724 (set_attr "fp_mode" "single")])
12726 (define_expand "adddf3"
12727 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12728 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12729 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12730 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12732 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12734 expand_df_binop (&gen_adddf3_i, operands);
12739 (define_insn "*adddf3_media"
12740 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12741 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12742 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12743 "TARGET_SHMEDIA_FPU"
12744 "fadd.d %1, %2, %0"
12745 [(set_attr "type" "dfparith_media")])
12747 (define_insn "adddf3_i"
12748 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12749 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12750 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12751 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12752 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12754 [(set_attr "type" "dfp_arith")
12755 (set_attr "fp_mode" "double")])
12757 (define_expand "subdf3"
12758 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12759 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12760 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12761 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12763 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12765 expand_df_binop (&gen_subdf3_i, operands);
12770 (define_insn "*subdf3_media"
12771 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12772 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12773 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12774 "TARGET_SHMEDIA_FPU"
12775 "fsub.d %1, %2, %0"
12776 [(set_attr "type" "dfparith_media")])
12778 (define_insn "subdf3_i"
12779 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12780 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12781 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12782 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12783 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12785 [(set_attr "type" "dfp_arith")
12786 (set_attr "fp_mode" "double")])
12788 (define_expand "muldf3"
12789 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12790 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12791 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12792 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12794 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12796 expand_df_binop (&gen_muldf3_i, operands);
12801 (define_insn "*muldf3_media"
12802 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12803 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12804 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12805 "TARGET_SHMEDIA_FPU"
12806 "fmul.d %1, %2, %0"
12807 [(set_attr "type" "dfmul_media")])
12809 (define_insn "muldf3_i"
12810 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12811 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12812 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12813 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12814 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12816 [(set_attr "type" "dfp_mul")
12817 (set_attr "fp_mode" "double")])
12819 (define_expand "divdf3"
12820 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12821 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12822 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12823 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12825 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12827 expand_df_binop (&gen_divdf3_i, operands);
12832 (define_insn "*divdf3_media"
12833 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12834 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12835 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12836 "TARGET_SHMEDIA_FPU"
12837 "fdiv.d %1, %2, %0"
12838 [(set_attr "type" "dfdiv_media")])
12840 (define_insn "divdf3_i"
12841 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12842 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12843 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12844 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12845 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12847 [(set_attr "type" "dfdiv")
12848 (set_attr "fp_mode" "double")])
12850 (define_insn "floatdidf2"
12851 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12852 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12853 "TARGET_SHMEDIA_FPU"
12855 [(set_attr "type" "dfpconv_media")])
12857 (define_expand "floatsidf2"
12858 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12859 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
12860 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12862 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12864 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
12865 get_fpscr_rtx ()));
12870 (define_insn "*floatsidf2_media"
12871 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12872 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12873 "TARGET_SHMEDIA_FPU"
12875 [(set_attr "type" "dfpconv_media")])
12877 (define_insn "floatsidf2_i"
12878 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12879 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
12880 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12881 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12883 [(set_attr "type" "dfp_conv")
12884 (set_attr "fp_mode" "double")])
12886 (define_insn "fix_truncdfdi2"
12887 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12888 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
12889 "TARGET_SHMEDIA_FPU"
12891 [(set_attr "type" "dfpconv_media")])
12893 (define_expand "fix_truncdfsi2"
12894 [(set (match_operand:SI 0 "fpul_operand" "")
12895 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
12896 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12898 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12900 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
12901 get_fpscr_rtx ()));
12906 (define_insn "*fix_truncdfsi2_media"
12907 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12908 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
12909 "TARGET_SHMEDIA_FPU"
12911 [(set_attr "type" "dfpconv_media")])
12913 (define_insn "fix_truncdfsi2_i"
12914 [(set (match_operand:SI 0 "fpul_operand" "=y")
12915 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
12916 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12917 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12919 [(set_attr "type" "dfp_conv")
12920 (set_attr "dfp_comp" "no")
12921 (set_attr "fp_mode" "double")])
12923 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
12924 ;; fix_truncdfsi2_i.
12925 ;; (define_insn "fix_truncdfsi2_i4"
12926 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12927 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
12928 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
12929 ;; (clobber (reg:SI FPUL_REG))]
12932 ;; [(set_attr "length" "4")
12933 ;; (set_attr "fp_mode" "double")])
12936 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12937 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
12938 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
12939 ;; (clobber (reg:SI FPUL_REG))]
12941 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
12942 ;; (use (match_dup 2))])
12943 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
12945 (define_insn "cmpgtdf_t"
12946 [(set (reg:SI T_REG)
12947 (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
12948 (match_operand:DF 1 "arith_reg_operand" "f")))
12949 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12950 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12952 [(set_attr "type" "dfp_cmp")
12953 (set_attr "fp_mode" "double")])
12955 (define_insn "cmpeqdf_t"
12956 [(set (reg:SI T_REG)
12957 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
12958 (match_operand:DF 1 "arith_reg_operand" "f")))
12959 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12960 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12962 [(set_attr "type" "dfp_cmp")
12963 (set_attr "fp_mode" "double")])
12965 (define_insn "*ieee_ccmpeqdf_t"
12966 [(set (reg:SI T_REG)
12967 (ior:SI (reg:SI T_REG)
12968 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
12969 (match_operand:DF 1 "arith_reg_operand" "f"))))
12970 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12971 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12973 return output_ieee_ccmpeq (insn, operands);
12975 [(set_attr "length" "4")
12976 (set_attr "fp_mode" "double")])
12978 (define_insn "cmpeqdf_media"
12979 [(set (match_operand:SI 0 "register_operand" "=r")
12980 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
12981 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12982 "TARGET_SHMEDIA_FPU"
12983 "fcmpeq.d %1,%2,%0"
12984 [(set_attr "type" "fcmp_media")])
12986 (define_insn "cmpgtdf_media"
12987 [(set (match_operand:SI 0 "register_operand" "=r")
12988 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
12989 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12990 "TARGET_SHMEDIA_FPU"
12991 "fcmpgt.d %1,%2,%0"
12992 [(set_attr "type" "fcmp_media")])
12994 (define_insn "cmpgedf_media"
12995 [(set (match_operand:SI 0 "register_operand" "=r")
12996 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
12997 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12998 "TARGET_SHMEDIA_FPU"
12999 "fcmpge.d %1,%2,%0"
13000 [(set_attr "type" "fcmp_media")])
13002 (define_insn "cmpundf_media"
13003 [(set (match_operand:SI 0 "register_operand" "=r")
13004 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13005 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13006 "TARGET_SHMEDIA_FPU"
13007 "fcmpun.d %1,%2,%0"
13008 [(set_attr "type" "fcmp_media")])
13010 (define_expand "cbranchdf4"
13012 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13013 [(match_operand:DF 1 "arith_operand" "")
13014 (match_operand:DF 2 "arith_operand" "")])
13015 (match_operand 3 "" "")
13017 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13019 if (TARGET_SHMEDIA)
13020 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13023 sh_emit_compare_and_branch (operands, DFmode);
13028 (define_expand "negdf2"
13029 [(set (match_operand:DF 0 "arith_reg_operand" "")
13030 (neg:DF (match_operand:DF 1 "arith_reg_operand" "")))]
13031 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13033 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13035 expand_df_unop (&gen_negdf2_i, operands);
13040 (define_insn "*negdf2_media"
13041 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13042 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13043 "TARGET_SHMEDIA_FPU"
13045 [(set_attr "type" "fmove_media")])
13047 (define_insn "negdf2_i"
13048 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13049 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13050 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13051 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13053 [(set_attr "type" "fmove")
13054 (set_attr "fp_mode" "double")])
13056 (define_expand "sqrtdf2"
13057 [(set (match_operand:DF 0 "arith_reg_operand" "")
13058 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "")))]
13059 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13061 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13063 expand_df_unop (&gen_sqrtdf2_i, operands);
13068 (define_insn "*sqrtdf2_media"
13069 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13070 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13071 "TARGET_SHMEDIA_FPU"
13073 [(set_attr "type" "dfdiv_media")])
13075 (define_insn "sqrtdf2_i"
13076 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13077 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13078 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13079 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13081 [(set_attr "type" "dfdiv")
13082 (set_attr "fp_mode" "double")])
13084 (define_expand "absdf2"
13085 [(set (match_operand:DF 0 "arith_reg_operand" "")
13086 (abs:DF (match_operand:DF 1 "arith_reg_operand" "")))]
13087 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13089 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13091 expand_df_unop (&gen_absdf2_i, operands);
13096 (define_insn "*absdf2_media"
13097 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13098 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13099 "TARGET_SHMEDIA_FPU"
13101 [(set_attr "type" "fmove_media")])
13103 (define_insn "absdf2_i"
13104 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13105 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13106 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13107 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13109 [(set_attr "type" "fmove")
13110 (set_attr "fp_mode" "double")])
13112 (define_expand "extendsfdf2"
13113 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13114 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13115 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13117 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13119 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
13120 get_fpscr_rtx ()));
13125 (define_insn "*extendsfdf2_media"
13126 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13127 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13128 "TARGET_SHMEDIA_FPU"
13130 [(set_attr "type" "dfpconv_media")])
13132 (define_insn "extendsfdf2_i4"
13133 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13134 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13135 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13136 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13138 [(set_attr "type" "fp")
13139 (set_attr "fp_mode" "double")])
13141 (define_expand "truncdfsf2"
13142 [(set (match_operand:SF 0 "fpul_operand" "")
13143 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13144 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13146 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13148 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
13149 get_fpscr_rtx ()));
13154 (define_insn "*truncdfsf2_media"
13155 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13156 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13157 "TARGET_SHMEDIA_FPU"
13159 [(set_attr "type" "dfpconv_media")])
13161 (define_insn "truncdfsf2_i4"
13162 [(set (match_operand:SF 0 "fpul_operand" "=y")
13163 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13164 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13165 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13167 [(set_attr "type" "fp")
13168 (set_attr "fp_mode" "double")])
13170 ;; -------------------------------------------------------------------------
13171 ;; Bit field extract patterns.
13172 ;; -------------------------------------------------------------------------
13174 ;; These give better code for packed bitfields, because they allow
13175 ;; auto-increment addresses to be generated.
13177 (define_expand "insv"
13178 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13179 (match_operand:SI 1 "immediate_operand" "")
13180 (match_operand:SI 2 "immediate_operand" ""))
13181 (match_operand:SI 3 "general_operand" ""))]
13182 "TARGET_SH1 && ! TARGET_LITTLE_ENDIAN"
13184 rtx addr_target, orig_address, shift_reg, qi_val;
13185 HOST_WIDE_INT bitsize, size, v = 0;
13186 rtx x = operands[3];
13188 if (TARGET_SH2A && TARGET_BITOPS
13189 && (satisfies_constraint_Sbw (operands[0])
13190 || satisfies_constraint_Sbv (operands[0]))
13191 && satisfies_constraint_M (operands[1])
13192 && satisfies_constraint_K03 (operands[2]))
13194 if (satisfies_constraint_N (operands[3]))
13196 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13199 else if (satisfies_constraint_M (operands[3]))
13201 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13204 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13205 && satisfies_constraint_M (operands[1]))
13207 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13210 else if (REG_P (operands[3])
13211 && satisfies_constraint_M (operands[1]))
13213 emit_insn (gen_bld_reg (operands[3], const0_rtx));
13214 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13218 /* ??? expmed doesn't care for non-register predicates. */
13219 if (! memory_operand (operands[0], VOIDmode)
13220 || ! immediate_operand (operands[1], VOIDmode)
13221 || ! immediate_operand (operands[2], VOIDmode)
13222 || ! general_operand (x, VOIDmode))
13224 /* If this isn't a 16 / 24 / 32 bit field, or if
13225 it doesn't start on a byte boundary, then fail. */
13226 bitsize = INTVAL (operands[1]);
13227 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13228 || (INTVAL (operands[2]) % 8) != 0)
13231 size = bitsize / 8;
13232 orig_address = XEXP (operands[0], 0);
13233 shift_reg = gen_reg_rtx (SImode);
13234 if (CONST_INT_P (x))
13237 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13241 emit_insn (gen_movsi (shift_reg, operands[3]));
13242 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13244 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13245 orig_address, size - 1));
13247 operands[0] = replace_equiv_address (operands[0], addr_target);
13248 emit_insn (gen_movqi (operands[0], qi_val));
13252 if (CONST_INT_P (x))
13254 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13257 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13258 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13260 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13261 emit_insn (gen_movqi (operands[0], qi_val));
13267 (define_insn "movua"
13268 [(set (match_operand:SI 0 "register_operand" "=z")
13269 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13273 [(set_attr "type" "movua")])
13275 ;; We shouldn't need this, but cse replaces increments with references
13276 ;; to other regs before flow has a chance to create post_inc
13277 ;; addressing modes, and only postreload's cse_move2add brings the
13278 ;; increments back to a usable form.
13280 [(set (match_operand:SI 0 "register_operand" "")
13281 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13282 (const_int 32) (const_int 0)))
13283 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13284 "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
13285 [(set (match_operand:SI 0 "register_operand" "")
13286 (sign_extract:SI (mem:SI (post_inc:SI
13287 (match_operand:SI 1 "register_operand" "")))
13288 (const_int 32) (const_int 0)))]
13291 (define_expand "extv"
13292 [(set (match_operand:SI 0 "register_operand" "")
13293 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13294 (match_operand 2 "const_int_operand" "")
13295 (match_operand 3 "const_int_operand" "")))]
13296 "TARGET_SH4A_ARCH || TARGET_SH2A"
13298 if (TARGET_SH2A && TARGET_BITOPS
13299 && (satisfies_constraint_Sbw (operands[1])
13300 || satisfies_constraint_Sbv (operands[1]))
13301 && satisfies_constraint_M (operands[2])
13302 && satisfies_constraint_K03 (operands[3]))
13304 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13305 if (REGNO (operands[0]) != T_REG)
13306 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13309 if (TARGET_SH4A_ARCH
13310 && INTVAL (operands[2]) == 32
13311 && INTVAL (operands[3]) == 0
13312 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13314 rtx src = adjust_address (operands[1], BLKmode, 0);
13315 set_mem_size (src, 4);
13316 emit_insn (gen_movua (operands[0], src));
13323 (define_expand "extzv"
13324 [(set (match_operand:SI 0 "register_operand" "")
13325 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13326 (match_operand 2 "const_int_operand" "")
13327 (match_operand 3 "const_int_operand" "")))]
13328 "TARGET_SH4A_ARCH || TARGET_SH2A"
13330 if (TARGET_SH2A && TARGET_BITOPS
13331 && (satisfies_constraint_Sbw (operands[1])
13332 || satisfies_constraint_Sbv (operands[1]))
13333 && satisfies_constraint_M (operands[2])
13334 && satisfies_constraint_K03 (operands[3]))
13336 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13337 if (REGNO (operands[0]) != T_REG)
13338 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13341 if (TARGET_SH4A_ARCH
13342 && INTVAL (operands[2]) == 32
13343 && INTVAL (operands[3]) == 0
13344 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13346 rtx src = adjust_address (operands[1], BLKmode, 0);
13347 set_mem_size (src, 4);
13348 emit_insn (gen_movua (operands[0], src));
13355 ;; SH2A instructions for bitwise operations.
13356 ;; FIXME: Convert multiple instruction insns to insn_and_split.
13357 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
13359 ;; Clear a bit in a memory location.
13360 (define_insn "bclr_m2a"
13361 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13363 (not:QI (ashift:QI (const_int 1)
13364 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13366 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13369 bclr.b %1,@(0,%t0)"
13370 [(set_attr "length" "4,4")])
13372 (define_insn "bclrmem_m2a"
13373 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13374 (and:QI (match_dup 0)
13375 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
13376 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
13379 bclr.b %W1,@(0,%t0)"
13380 [(set_attr "length" "4,4")])
13382 ;; Set a bit in a memory location.
13383 (define_insn "bset_m2a"
13384 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13386 (ashift:QI (const_int 1)
13387 (match_operand:QI 1 "const_int_operand" "K03,K03"))
13389 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13392 bset.b %1,@(0,%t0)"
13393 [(set_attr "length" "4,4")])
13395 (define_insn "bsetmem_m2a"
13396 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13397 (ior:QI (match_dup 0)
13398 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
13399 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
13402 bset.b %V1,@(0,%t0)"
13403 [(set_attr "length" "4,4")])
13405 ;;; Transfer the contents of the T bit to a specified bit of memory.
13406 (define_insn "bst_m2a"
13407 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
13408 (if_then_else (eq (reg:SI T_REG) (const_int 0))
13410 (not:QI (ashift:QI (const_int 1)
13411 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13414 (ashift:QI (const_int 1) (match_dup 1))
13416 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13420 [(set_attr "length" "4")])
13422 ;; Store a specified bit of memory in the T bit.
13423 (define_insn "bld_m2a"
13424 [(set (reg:SI T_REG)
13426 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
13428 (match_operand 1 "const_int_operand" "K03,K03")))]
13429 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13433 [(set_attr "length" "4,4")])
13435 ;; Store a specified bit of memory in the T bit.
13436 (define_insn "bldsign_m2a"
13437 [(set (reg:SI T_REG)
13439 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13441 (match_operand 1 "const_int_operand" "K03,K03")))]
13442 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13446 [(set_attr "length" "4,4")])
13448 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
13449 (define_insn "bld_reg"
13450 [(set (reg:SI T_REG)
13451 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
13453 (match_operand 1 "const_int_operand" "K03")))]
13454 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13457 (define_insn "*bld_regqi"
13458 [(set (reg:SI T_REG)
13459 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
13461 (match_operand 1 "const_int_operand" "K03")))]
13462 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13465 ;; Take logical and of a specified bit of memory with the T bit and
13466 ;; store its result in the T bit.
13467 (define_insn "band_m2a"
13468 [(set (reg:SI T_REG)
13469 (and:SI (reg:SI T_REG)
13471 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13473 (match_operand 1 "const_int_operand" "K03,K03"))))]
13474 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13477 band.b %1,@(0,%t0)"
13478 [(set_attr "length" "4,4")])
13480 (define_insn "bandreg_m2a"
13481 [(set (match_operand:SI 0 "register_operand" "=r,r")
13482 (and:SI (zero_extract:SI
13483 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13485 (match_operand 2 "const_int_operand" "K03,K03"))
13486 (match_operand:SI 3 "register_operand" "r,r")))]
13487 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13489 static const char* alt[] =
13491 "band.b %2,%1" "\n"
13494 "band.b %2,@(0,%t1)" "\n"
13497 return alt[which_alternative];
13499 [(set_attr "length" "6,6")])
13501 ;; Take logical or of a specified bit of memory with the T bit and
13502 ;; store its result in the T bit.
13503 (define_insn "bor_m2a"
13504 [(set (reg:SI T_REG)
13505 (ior:SI (reg:SI T_REG)
13507 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13509 (match_operand 1 "const_int_operand" "K03,K03"))))]
13510 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13514 [(set_attr "length" "4,4")])
13516 (define_insn "borreg_m2a"
13517 [(set (match_operand:SI 0 "register_operand" "=r,r")
13518 (ior:SI (zero_extract:SI
13519 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13521 (match_operand 2 "const_int_operand" "K03,K03"))
13522 (match_operand:SI 3 "register_operand" "=r,r")))]
13523 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13525 static const char* alt[] =
13530 "bor.b %2,@(0,%t1)" "\n"
13533 return alt[which_alternative];
13535 [(set_attr "length" "6,6")])
13537 ;; Take exclusive or of a specified bit of memory with the T bit and
13538 ;; store its result in the T bit.
13539 (define_insn "bxor_m2a"
13540 [(set (reg:SI T_REG)
13541 (xor:SI (reg:SI T_REG)
13543 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13545 (match_operand 1 "const_int_operand" "K03,K03"))))]
13546 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13549 bxor.b %1,@(0,%t0)"
13550 [(set_attr "length" "4,4")])
13552 (define_insn "bxorreg_m2a"
13553 [(set (match_operand:SI 0 "register_operand" "=r,r")
13554 (xor:SI (zero_extract:SI
13555 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13557 (match_operand 2 "const_int_operand" "K03,K03"))
13558 (match_operand:SI 3 "register_operand" "=r,r")))]
13559 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13561 static const char* alt[] =
13563 "bxor.b %2,%1" "\n"
13566 "bxor.b %2,@(0,%t1)" "\n"
13569 return alt[which_alternative];
13571 [(set_attr "length" "6,6")])
13573 ;; -------------------------------------------------------------------------
13575 ;; -------------------------------------------------------------------------
13576 ;; This matches cases where the bit in a memory location is set.
13578 [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
13579 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
13581 (ior:SI (match_dup 0)
13582 (match_operand:SI 2 "const_int_operand" "Pso,Pso")))
13584 (match_operand 3 "arith_reg_operand" "r,r"))]
13585 "TARGET_SH2A && TARGET_BITOPS
13586 && satisfies_constraint_Pso (operands[2])
13587 && REGNO (operands[0]) == REGNO (operands[3])"
13588 [(set (match_dup 1)
13589 (ior:QI (match_dup 1) (match_dup 2)))]
13592 ;; This matches cases where the bit in a memory location is cleared.
13594 [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
13595 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
13597 (and:SI (match_dup 0)
13598 (match_operand:SI 2 "const_int_operand" "Psz,Psz")))
13600 (match_operand 3 "arith_reg_operand" "r,r"))]
13601 "TARGET_SH2A && TARGET_BITOPS
13602 && satisfies_constraint_Psz (operands[2])
13603 && REGNO (operands[0]) == REGNO (operands[3])"
13604 [(set (match_dup 1)
13605 (and:QI (match_dup 1) (match_dup 2)))]
13608 ;; This matches cases where a stack pointer increment at the start of the
13609 ;; epilogue combines with a stack slot read loading the return value.
13611 [(set (match_operand:SI 0 "arith_reg_operand" "")
13612 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
13613 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13614 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
13617 ;; See the comment on the dt combiner pattern above.
13619 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13620 (plus:SI (match_dup 0)
13622 (set (reg:SI T_REG)
13623 (eq:SI (match_dup 0) (const_int 0)))]
13627 ;; The following peepholes fold load sequences for which reload was not
13628 ;; able to generate a displacement addressing move insn.
13629 ;; This can happen when reload has to transform a move insn
13630 ;; without displacement into one with displacement. Or when reload can't
13631 ;; fit a displacement into the insn's constraints. In the latter case, the
13632 ;; load destination reg remains at r0, which reload compensates by inserting
13633 ;; another mov insn.
13637 ;; mov.{b,w} @(r0,r15),r0
13640 ;; mov.{b,w} @(54,r15),r3
13643 [(set (match_operand:SI 0 "arith_reg_dest" "")
13644 (match_operand:SI 1 "const_int_operand" ""))
13645 (set (match_operand:SI 2 "arith_reg_dest" "")
13647 (mem:QI (plus:SI (match_dup 0)
13648 (match_operand:SI 3 "arith_reg_operand" "")))))
13649 (set (match_operand:QI 4 "arith_reg_dest" "")
13650 (match_operand:QI 5 "arith_reg_operand" ""))]
13652 && sh_legitimate_index_p (QImode, operands[1], true, true)
13653 && REGNO (operands[2]) == REGNO (operands[5])
13654 && peep2_reg_dead_p (3, operands[5])"
13655 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
13659 [(set (match_operand:SI 0 "arith_reg_dest" "")
13660 (match_operand:SI 1 "const_int_operand" ""))
13661 (set (match_operand:SI 2 "arith_reg_dest" "")
13663 (mem:HI (plus:SI (match_dup 0)
13664 (match_operand:SI 3 "arith_reg_operand" "")))))
13665 (set (match_operand:HI 4 "arith_reg_dest" "")
13666 (match_operand:HI 5 "arith_reg_operand" ""))]
13668 && sh_legitimate_index_p (HImode, operands[1], true, true)
13669 && REGNO (operands[2]) == REGNO (operands[5])
13670 && peep2_reg_dead_p (3, operands[5])"
13671 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
13676 ;; mov.{b,w} @(r0,r15),r1
13678 ;; mov.{b,w} @(54,r15),r1
13681 [(set (match_operand:SI 0 "arith_reg_dest" "")
13682 (match_operand:SI 1 "const_int_operand" ""))
13683 (set (match_operand:SI 2 "arith_reg_dest" "")
13685 (mem:QI (plus:SI (match_dup 0)
13686 (match_operand:SI 3 "arith_reg_operand" "")))))]
13688 && sh_legitimate_index_p (QImode, operands[1], true, true)
13689 && (peep2_reg_dead_p (2, operands[0])
13690 || REGNO (operands[0]) == REGNO (operands[2]))"
13691 [(set (match_dup 2)
13692 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
13696 [(set (match_operand:SI 0 "arith_reg_dest" "")
13697 (match_operand:SI 1 "const_int_operand" ""))
13698 (set (match_operand:SI 2 "arith_reg_dest" "")
13700 (mem:HI (plus:SI (match_dup 0)
13701 (match_operand:SI 3 "arith_reg_operand" "")))))]
13703 && sh_legitimate_index_p (HImode, operands[1], true, true)
13704 && (peep2_reg_dead_p (2, operands[0])
13705 || REGNO (operands[0]) == REGNO (operands[2]))"
13706 [(set (match_dup 2)
13707 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
13711 ;; mov.{b,w} @(r0,r15),r0
13714 ;; mov.{b,w} @(r0,r15),r3
13716 ;; This can happen when initially a displacement address is picked, where
13717 ;; the destination reg is fixed to r0, and then the address is transformed
13718 ;; into 'r0 + reg'.
13720 [(set (match_operand:SI 0 "arith_reg_dest" "")
13722 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13723 (match_operand:SI 2 "arith_reg_operand" "")))))
13724 (set (match_operand:QI 3 "arith_reg_dest" "")
13725 (match_operand:QI 4 "arith_reg_operand" ""))]
13727 && REGNO (operands[0]) == REGNO (operands[4])
13728 && peep2_reg_dead_p (2, operands[0])"
13729 [(set (match_dup 3)
13730 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
13734 [(set (match_operand:SI 0 "arith_reg_dest" "")
13736 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13737 (match_operand:SI 2 "arith_reg_operand" "")))))
13738 (set (match_operand:HI 3 "arith_reg_dest" "")
13739 (match_operand:HI 4 "arith_reg_operand" ""))]
13741 && REGNO (operands[0]) == REGNO (operands[4])
13742 && peep2_reg_dead_p (2, operands[0])"
13743 [(set (match_dup 3)
13744 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
13748 [(set (match_operand:SI 0 "register_operand" "=r")
13749 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13750 (set (mem:SF (match_dup 0))
13751 (match_operand:SF 2 "general_movsrc_operand" ""))]
13752 "TARGET_SH1 && REGNO (operands[0]) == 0
13753 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13754 || (GET_CODE (operands[2]) == SUBREG
13755 && REGNO (SUBREG_REG (operands[2])) < 16))
13756 && reg_unused_after (operands[0], insn)"
13757 "mov.l %2,@(%0,%1)")
13760 [(set (match_operand:SI 0 "register_operand" "=r")
13761 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13762 (set (match_operand:SF 2 "general_movdst_operand" "")
13764 (mem:SF (match_dup 0)))]
13765 "TARGET_SH1 && REGNO (operands[0]) == 0
13766 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13767 || (GET_CODE (operands[2]) == SUBREG
13768 && REGNO (SUBREG_REG (operands[2])) < 16))
13769 && reg_unused_after (operands[0], insn)"
13770 "mov.l @(%0,%1),%2")
13773 [(set (match_operand:SI 0 "register_operand" "=r")
13774 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13775 (set (mem:SF (match_dup 0))
13776 (match_operand:SF 2 "general_movsrc_operand" ""))]
13777 "TARGET_SH2E && REGNO (operands[0]) == 0
13778 && ((REG_P (operands[2])
13779 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13780 || (GET_CODE (operands[2]) == SUBREG
13781 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13782 && reg_unused_after (operands[0], insn)"
13783 "fmov{.s|} %2,@(%0,%1)")
13786 [(set (match_operand:SI 0 "register_operand" "=r")
13787 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13788 (set (match_operand:SF 2 "general_movdst_operand" "")
13790 (mem:SF (match_dup 0)))]
13791 "TARGET_SH2E && REGNO (operands[0]) == 0
13792 && ((REG_P (operands[2])
13793 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13794 || (GET_CODE (operands[2]) == SUBREG
13795 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13796 && reg_unused_after (operands[0], insn)"
13797 "fmov{.s|} @(%0,%1),%2")
13799 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
13800 (define_insn "sp_switch_1"
13801 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
13802 UNSPECV_SP_SWITCH_B))]
13805 return "mov.l r0,@-r15" "\n"
13806 " mov.l %0,r0" "\n"
13807 " mov.l @r0,r0" "\n"
13808 " mov.l r15,@-r0" "\n"
13811 [(set_attr "length" "10")])
13813 ;; Switch back to the original stack for interrupt functions with the
13814 ;; sp_switch attribute.
13815 (define_insn "sp_switch_2"
13816 [(unspec_volatile [(const_int 0)]
13817 UNSPECV_SP_SWITCH_E)]
13820 return "mov.l @r15,r15" "\n"
13823 [(set_attr "length" "4")])
13825 ;; -------------------------------------------------------------------------
13826 ;; Integer vector moves
13827 ;; -------------------------------------------------------------------------
13829 (define_expand "movv8qi"
13830 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
13831 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
13834 prepare_move_operands (operands, V8QImode);
13837 (define_insn "movv8qi_i"
13838 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
13839 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13841 && (register_operand (operands[0], V8QImode)
13842 || sh_register_operand (operands[1], V8QImode))"
13849 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
13850 (set_attr "length" "4,4,16,4,4")])
13853 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
13854 (subreg:V8QI (const_int 0) 0))]
13856 [(set (match_dup 0)
13857 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
13858 (const_int 0) (const_int 0) (const_int 0)
13859 (const_int 0) (const_int 0)]))])
13862 [(set (match_operand 0 "arith_reg_dest" "")
13863 (match_operand 1 "sh_rep_vec" ""))]
13864 "TARGET_SHMEDIA && reload_completed
13865 && GET_MODE (operands[0]) == GET_MODE (operands[1])
13866 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
13867 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
13868 && (XVECEXP (operands[1], 0, 0) != const0_rtx
13869 || XVECEXP (operands[1], 0, 1) != const0_rtx)
13870 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
13871 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
13872 [(set (match_dup 0) (match_dup 1))
13875 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
13876 rtx elt1 = XVECEXP (operands[1], 0, 1);
13879 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
13883 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
13884 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
13886 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
13887 operands[1] = XVECEXP (operands[1], 0, 0);
13890 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
13892 = GEN_INT (TARGET_LITTLE_ENDIAN
13893 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
13894 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
13897 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
13899 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
13905 [(set (match_operand 0 "arith_reg_dest" "")
13906 (match_operand 1 "sh_const_vec" ""))]
13907 "TARGET_SHMEDIA && reload_completed
13908 && GET_MODE (operands[0]) == GET_MODE (operands[1])
13909 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
13910 [(set (match_dup 0) (match_dup 1))]
13912 rtx v = operands[1];
13913 enum machine_mode new_mode
13914 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
13916 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
13918 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
13921 (define_expand "movv2hi"
13922 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
13923 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
13926 prepare_move_operands (operands, V2HImode);
13929 (define_insn "movv2hi_i"
13930 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
13931 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13933 && (register_operand (operands[0], V2HImode)
13934 || sh_register_operand (operands[1], V2HImode))"
13941 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
13942 (set_attr "length" "4,4,16,4,4")
13943 (set (attr "highpart")
13944 (cond [(match_test "sh_contains_memref_p (insn)")
13945 (const_string "user")]
13946 (const_string "ignore")))])
13948 (define_expand "movv4hi"
13949 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
13950 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
13953 prepare_move_operands (operands, V4HImode);
13956 (define_insn "movv4hi_i"
13957 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
13958 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13960 && (register_operand (operands[0], V4HImode)
13961 || sh_register_operand (operands[1], V4HImode))"
13968 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
13969 (set_attr "length" "4,4,16,4,4")
13970 (set_attr "highpart" "depend")])
13972 (define_expand "movv2si"
13973 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
13974 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
13977 prepare_move_operands (operands, V2SImode);
13980 (define_insn "movv2si_i"
13981 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
13982 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13984 && (register_operand (operands[0], V2SImode)
13985 || sh_register_operand (operands[1], V2SImode))"
13992 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
13993 (set_attr "length" "4,4,16,4,4")
13994 (set_attr "highpart" "depend")])
13996 ;; -------------------------------------------------------------------------
13997 ;; Multimedia Intrinsics
13998 ;; -------------------------------------------------------------------------
14000 (define_insn "absv2si2"
14001 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14002 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
14005 [(set_attr "type" "mcmp_media")
14006 (set_attr "highpart" "depend")])
14008 (define_insn "absv4hi2"
14009 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14010 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
14013 [(set_attr "type" "mcmp_media")
14014 (set_attr "highpart" "depend")])
14016 (define_insn "addv2si3"
14017 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14018 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14019 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14021 "madd.l %1, %2, %0"
14022 [(set_attr "type" "arith_media")
14023 (set_attr "highpart" "depend")])
14025 (define_insn "addv4hi3"
14026 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14027 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14028 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14030 "madd.w %1, %2, %0"
14031 [(set_attr "type" "arith_media")
14032 (set_attr "highpart" "depend")])
14034 (define_insn_and_split "addv2hi3"
14035 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
14036 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
14037 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
14043 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
14044 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
14045 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
14046 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
14047 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
14049 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
14050 emit_insn (gen_truncdisi2 (si_dst, di_dst));
14053 [(set_attr "highpart" "must_split")])
14055 (define_insn "ssaddv2si3"
14056 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14057 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14058 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14060 "madds.l %1, %2, %0"
14061 [(set_attr "type" "mcmp_media")
14062 (set_attr "highpart" "depend")])
14064 (define_insn "usaddv8qi3"
14065 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14066 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
14067 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
14069 "madds.ub %1, %2, %0"
14070 [(set_attr "type" "mcmp_media")
14071 (set_attr "highpart" "depend")])
14073 (define_insn "ssaddv4hi3"
14074 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14075 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14076 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14078 "madds.w %1, %2, %0"
14079 [(set_attr "type" "mcmp_media")
14080 (set_attr "highpart" "depend")])
14082 (define_insn "negcmpeqv8qi"
14083 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14085 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14086 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14088 "mcmpeq.b %N1, %N2, %0"
14089 [(set_attr "type" "mcmp_media")
14090 (set_attr "highpart" "depend")])
14092 (define_insn "negcmpeqv2si"
14093 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14095 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14096 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14098 "mcmpeq.l %N1, %N2, %0"
14099 [(set_attr "type" "mcmp_media")
14100 (set_attr "highpart" "depend")])
14102 (define_insn "negcmpeqv4hi"
14103 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14105 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14106 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14108 "mcmpeq.w %N1, %N2, %0"
14109 [(set_attr "type" "mcmp_media")
14110 (set_attr "highpart" "depend")])
14112 (define_insn "negcmpgtuv8qi"
14113 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14114 (neg:V8QI (gtu:V8QI
14115 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14116 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14118 "mcmpgt.ub %N1, %N2, %0"
14119 [(set_attr "type" "mcmp_media")
14120 (set_attr "highpart" "depend")])
14122 (define_insn "negcmpgtv2si"
14123 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14125 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14126 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14128 "mcmpgt.l %N1, %N2, %0"
14129 [(set_attr "type" "mcmp_media")
14130 (set_attr "highpart" "depend")])
14132 (define_insn "negcmpgtv4hi"
14133 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14135 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14136 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14138 "mcmpgt.w %N1, %N2, %0"
14139 [(set_attr "type" "mcmp_media")
14140 (set_attr "highpart" "depend")])
14142 (define_insn "mcmv"
14143 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14144 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14145 (match_operand:DI 2 "arith_reg_operand" "r"))
14146 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
14147 (not:DI (match_dup 2)))))]
14150 [(set_attr "type" "arith_media")
14151 (set_attr "highpart" "depend")])
14153 (define_insn "mcnvs_lw"
14154 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14156 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
14158 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14160 "mcnvs.lw %N1, %N2, %0"
14161 [(set_attr "type" "mcmp_media")])
14163 (define_insn "mcnvs_wb"
14164 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14166 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14168 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14170 "mcnvs.wb %N1, %N2, %0"
14171 [(set_attr "type" "mcmp_media")])
14173 (define_insn "mcnvs_wub"
14174 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14176 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14178 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14180 "mcnvs.wub %N1, %N2, %0"
14181 [(set_attr "type" "mcmp_media")])
14183 (define_insn "mextr_rl"
14184 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14185 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14186 (match_operand:HI 3 "mextr_bit_offset" "i"))
14187 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14188 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14189 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14191 static char templ[21];
14192 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
14193 (int) INTVAL (operands[3]) >> 3);
14196 [(set_attr "type" "arith_media")])
14198 (define_insn "*mextr_lr"
14199 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14200 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14201 (match_operand:HI 3 "mextr_bit_offset" "i"))
14202 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14203 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14204 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14206 static char templ[21];
14207 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
14208 (int) INTVAL (operands[4]) >> 3);
14211 [(set_attr "type" "arith_media")])
14213 ; mextrN can be modelled with vec_select / vec_concat, but the selection
14214 ; vector then varies depending on endianness.
14215 (define_expand "mextr1"
14216 [(match_operand:DI 0 "arith_reg_dest" "")
14217 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14218 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14221 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14222 GEN_INT (1 * 8), GEN_INT (7 * 8)));
14226 (define_expand "mextr2"
14227 [(match_operand:DI 0 "arith_reg_dest" "")
14228 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14229 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14232 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14233 GEN_INT (2 * 8), GEN_INT (6 * 8)));
14237 (define_expand "mextr3"
14238 [(match_operand:DI 0 "arith_reg_dest" "")
14239 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14240 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14243 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14244 GEN_INT (3 * 8), GEN_INT (5 * 8)));
14248 (define_expand "mextr4"
14249 [(match_operand:DI 0 "arith_reg_dest" "")
14250 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14251 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14254 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14255 GEN_INT (4 * 8), GEN_INT (4 * 8)));
14259 (define_expand "mextr5"
14260 [(match_operand:DI 0 "arith_reg_dest" "")
14261 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14262 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14265 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14266 GEN_INT (5 * 8), GEN_INT (3 * 8)));
14270 (define_expand "mextr6"
14271 [(match_operand:DI 0 "arith_reg_dest" "")
14272 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14273 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14276 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14277 GEN_INT (6 * 8), GEN_INT (2 * 8)));
14281 (define_expand "mextr7"
14282 [(match_operand:DI 0 "arith_reg_dest" "")
14283 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14284 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14287 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14288 GEN_INT (7 * 8), GEN_INT (1 * 8)));
14292 (define_expand "mmacfx_wl"
14293 [(match_operand:V2SI 0 "arith_reg_dest" "")
14294 (match_operand:V2HI 1 "extend_reg_operand" "")
14295 (match_operand:V2HI 2 "extend_reg_operand" "")
14296 (match_operand:V2SI 3 "arith_reg_operand" "")]
14299 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
14300 operands[1], operands[2]));
14304 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
14306 (define_insn "mmacfx_wl_i"
14307 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14309 (match_operand:V2SI 1 "arith_reg_operand" "0")
14314 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14315 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14318 "mmacfx.wl %2, %3, %0"
14319 [(set_attr "type" "mac_media")
14320 (set_attr "highpart" "depend")])
14322 (define_expand "mmacnfx_wl"
14323 [(match_operand:V2SI 0 "arith_reg_dest" "")
14324 (match_operand:V2HI 1 "extend_reg_operand" "")
14325 (match_operand:V2HI 2 "extend_reg_operand" "")
14326 (match_operand:V2SI 3 "arith_reg_operand" "")]
14329 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
14330 operands[1], operands[2]));
14334 (define_insn "mmacnfx_wl_i"
14335 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14337 (match_operand:V2SI 1 "arith_reg_operand" "0")
14342 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14343 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14346 "mmacnfx.wl %2, %3, %0"
14347 [(set_attr "type" "mac_media")
14348 (set_attr "highpart" "depend")])
14350 (define_insn "mulv2si3"
14351 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14352 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14353 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14355 "mmul.l %1, %2, %0"
14356 [(set_attr "type" "d2mpy_media")
14357 (set_attr "highpart" "depend")])
14359 (define_insn "mulv4hi3"
14360 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14361 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14362 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14364 "mmul.w %1, %2, %0"
14365 [(set_attr "type" "dmpy_media")
14366 (set_attr "highpart" "depend")])
14368 (define_insn "mmulfx_l"
14369 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14373 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14374 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
14377 "mmulfx.l %1, %2, %0"
14378 [(set_attr "type" "d2mpy_media")
14379 (set_attr "highpart" "depend")])
14381 (define_insn "mmulfx_w"
14382 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14386 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14387 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14390 "mmulfx.w %1, %2, %0"
14391 [(set_attr "type" "dmpy_media")
14392 (set_attr "highpart" "depend")])
14394 (define_insn "mmulfxrp_w"
14395 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14400 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14401 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14405 "mmulfxrp.w %1, %2, %0"
14406 [(set_attr "type" "dmpy_media")
14407 (set_attr "highpart" "depend")])
14410 (define_expand "mmulhi_wl"
14411 [(match_operand:V2SI 0 "arith_reg_dest" "")
14412 (match_operand:V4HI 1 "arith_reg_operand" "")
14413 (match_operand:V4HI 2 "arith_reg_operand" "")]
14416 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
14417 (operands[0], operands[1], operands[2]));
14421 (define_expand "mmullo_wl"
14422 [(match_operand:V2SI 0 "arith_reg_dest" "")
14423 (match_operand:V4HI 1 "arith_reg_operand" "")
14424 (match_operand:V4HI 2 "arith_reg_operand" "")]
14427 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
14428 (operands[0], operands[1], operands[2]));
14432 (define_insn "mmul23_wl"
14433 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14436 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14437 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14438 (parallel [(const_int 2) (const_int 3)])))]
14441 return (TARGET_LITTLE_ENDIAN
14442 ? "mmulhi.wl %1, %2, %0"
14443 : "mmullo.wl %1, %2, %0");
14445 [(set_attr "type" "dmpy_media")
14446 (set (attr "highpart")
14447 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14448 (const_string "user")))])
14450 (define_insn "mmul01_wl"
14451 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14454 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14455 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14456 (parallel [(const_int 0) (const_int 1)])))]
14459 return (TARGET_LITTLE_ENDIAN
14460 ? "mmullo.wl %1, %2, %0"
14461 : "mmulhi.wl %1, %2, %0");
14463 [(set_attr "type" "dmpy_media")
14464 (set (attr "highpart")
14465 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14466 (const_string "user")))])
14469 (define_expand "mmulsum_wq"
14470 [(match_operand:DI 0 "arith_reg_dest" "")
14471 (match_operand:V4HI 1 "arith_reg_operand" "")
14472 (match_operand:V4HI 2 "arith_reg_operand" "")
14473 (match_operand:DI 3 "arith_reg_operand" "")]
14476 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
14477 operands[1], operands[2]));
14481 (define_insn "mmulsum_wq_i"
14482 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14483 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
14488 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
14489 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
14490 (parallel [(const_int 0)]))
14491 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14492 (sign_extend:V4DI (match_dup 3)))
14493 (parallel [(const_int 1)])))
14495 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14496 (sign_extend:V4DI (match_dup 3)))
14497 (parallel [(const_int 2)]))
14498 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14499 (sign_extend:V4DI (match_dup 3)))
14500 (parallel [(const_int 3)]))))))]
14502 "mmulsum.wq %2, %3, %0"
14503 [(set_attr "type" "mac_media")])
14505 (define_expand "mperm_w"
14506 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
14507 (match_operand:V4HI 1 "arith_reg_operand" "r")
14508 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
14511 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
14512 (operands[0], operands[1], operands[2]));
14516 ; This use of vec_select isn't exactly correct according to rtl.texi
14517 ; (because not constant), but it seems a straightforward extension.
14518 (define_insn "mperm_w_little"
14519 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14521 (match_operand:V4HI 1 "arith_reg_operand" "r")
14523 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
14524 (const_int 2) (const_int 0))
14525 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
14526 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
14527 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
14528 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
14529 "mperm.w %1, %N2, %0"
14530 [(set_attr "type" "arith_media")])
14532 (define_insn "mperm_w_big"
14533 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14535 (match_operand:V4HI 1 "arith_reg_operand" "r")
14537 [(zero_extract:QI (not:QI (match_operand:QI 2
14538 "extend_reg_or_0_operand" "rZ"))
14539 (const_int 2) (const_int 0))
14540 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
14541 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
14542 (zero_extract:QI (not:QI (match_dup 2))
14543 (const_int 2) (const_int 6))])))]
14544 "TARGET_SHMEDIA && ! TARGET_LITTLE_ENDIAN"
14545 "mperm.w %1, %N2, %0"
14546 [(set_attr "type" "arith_media")])
14548 (define_insn "mperm_w0"
14549 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14550 (vec_duplicate:V4HI (truncate:HI (match_operand 1
14551 "trunc_hi_operand" "r"))))]
14553 "mperm.w %1, r63, %0"
14554 [(set_attr "type" "arith_media")
14555 (set_attr "highpart" "ignore")])
14557 (define_expand "msad_ubq"
14558 [(match_operand:DI 0 "arith_reg_dest" "")
14559 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
14560 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
14561 (match_operand:DI 3 "arith_reg_operand" "")]
14564 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
14565 operands[1], operands[2]));
14569 (define_insn "msad_ubq_i"
14570 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14575 (match_operand:DI 1 "arith_reg_operand" "0")
14576 (abs:DI (vec_select:DI
14579 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14581 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
14582 (parallel [(const_int 0)]))))
14583 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14584 (zero_extend:V8DI (match_dup 3)))
14585 (parallel [(const_int 1)]))))
14587 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14588 (zero_extend:V8DI (match_dup 3)))
14589 (parallel [(const_int 2)])))
14590 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14591 (zero_extend:V8DI (match_dup 3)))
14592 (parallel [(const_int 3)])))))
14595 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14596 (zero_extend:V8DI (match_dup 3)))
14597 (parallel [(const_int 4)])))
14598 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14599 (zero_extend:V8DI (match_dup 3)))
14600 (parallel [(const_int 5)]))))
14602 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14603 (zero_extend:V8DI (match_dup 3)))
14604 (parallel [(const_int 6)])))
14605 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14606 (zero_extend:V8DI (match_dup 3)))
14607 (parallel [(const_int 7)])))))))]
14609 "msad.ubq %N2, %N3, %0"
14610 [(set_attr "type" "mac_media")])
14612 (define_insn "mshalds_l"
14613 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14616 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14617 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14618 (const_int 31)))))]
14620 "mshalds.l %1, %2, %0"
14621 [(set_attr "type" "mcmp_media")
14622 (set_attr "highpart" "depend")])
14624 (define_insn "mshalds_w"
14625 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14628 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14629 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14630 (const_int 15)))))]
14632 "mshalds.w %1, %2, %0"
14633 [(set_attr "type" "mcmp_media")
14634 (set_attr "highpart" "depend")])
14636 (define_insn "ashrv2si3"
14637 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14638 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14639 (match_operand:DI 2 "arith_reg_operand" "r")))]
14641 "mshard.l %1, %2, %0"
14642 [(set_attr "type" "arith_media")
14643 (set_attr "highpart" "depend")])
14645 (define_insn "ashrv4hi3"
14646 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14647 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14648 (match_operand:DI 2 "arith_reg_operand" "r")))]
14650 "mshard.w %1, %2, %0"
14651 [(set_attr "type" "arith_media")
14652 (set_attr "highpart" "depend")])
14654 (define_insn "mshards_q"
14655 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
14657 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
14658 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
14660 "mshards.q %1, %N2, %0"
14661 [(set_attr "type" "mcmp_media")])
14663 (define_expand "mshfhi_b"
14664 [(match_operand:V8QI 0 "arith_reg_dest" "")
14665 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14666 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14669 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
14670 (operands[0], operands[1], operands[2]));
14674 (define_expand "mshflo_b"
14675 [(match_operand:V8QI 0 "arith_reg_dest" "")
14676 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14677 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14680 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
14681 (operands[0], operands[1], operands[2]));
14685 (define_insn "mshf4_b"
14687 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14689 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14690 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14691 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
14692 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
14695 return (TARGET_LITTLE_ENDIAN
14696 ? "mshfhi.b %N1, %N2, %0"
14697 : "mshflo.b %N1, %N2, %0");
14699 [(set_attr "type" "arith_media")
14700 (set (attr "highpart")
14701 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14702 (const_string "user")))])
14704 (define_insn "mshf0_b"
14706 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14708 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14709 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14710 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
14711 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
14714 return (TARGET_LITTLE_ENDIAN
14715 ? "mshflo.b %N1, %N2, %0"
14716 : "mshfhi.b %N1, %N2, %0");
14718 [(set_attr "type" "arith_media")
14719 (set (attr "highpart")
14720 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14721 (const_string "user")))])
14723 (define_expand "mshfhi_l"
14724 [(match_operand:V2SI 0 "arith_reg_dest" "")
14725 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14726 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14729 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
14730 (operands[0], operands[1], operands[2]));
14734 (define_expand "mshflo_l"
14735 [(match_operand:V2SI 0 "arith_reg_dest" "")
14736 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14737 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14740 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
14741 (operands[0], operands[1], operands[2]));
14745 (define_insn "mshf4_l"
14746 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14748 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14749 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14750 (parallel [(const_int 1) (const_int 3)])))]
14753 return (TARGET_LITTLE_ENDIAN
14754 ? "mshfhi.l %N1, %N2, %0"
14755 : "mshflo.l %N1, %N2, %0");
14757 [(set_attr "type" "arith_media")
14758 (set (attr "highpart")
14759 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14760 (const_string "user")))])
14762 (define_insn "mshf0_l"
14763 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14765 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14766 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14767 (parallel [(const_int 0) (const_int 2)])))]
14770 return (TARGET_LITTLE_ENDIAN
14771 ? "mshflo.l %N1, %N2, %0"
14772 : "mshfhi.l %N1, %N2, %0");
14774 [(set_attr "type" "arith_media")
14775 (set (attr "highpart")
14776 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14777 (const_string "user")))])
14779 (define_expand "mshfhi_w"
14780 [(match_operand:V4HI 0 "arith_reg_dest" "")
14781 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14782 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14785 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
14786 (operands[0], operands[1], operands[2]));
14790 (define_expand "mshflo_w"
14791 [(match_operand:V4HI 0 "arith_reg_dest" "")
14792 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14793 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14796 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
14797 (operands[0], operands[1], operands[2]));
14801 (define_insn "mshf4_w"
14802 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14804 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14805 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14806 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
14809 return (TARGET_LITTLE_ENDIAN
14810 ? "mshfhi.w %N1, %N2, %0"
14811 : "mshflo.w %N1, %N2, %0");
14813 [(set_attr "type" "arith_media")
14814 (set (attr "highpart")
14815 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14816 (const_string "user")))])
14818 (define_insn "mshf0_w"
14819 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14821 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14822 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14823 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
14826 return (TARGET_LITTLE_ENDIAN
14827 ? "mshflo.w %N1, %N2, %0"
14828 : "mshfhi.w %N1, %N2, %0");
14830 [(set_attr "type" "arith_media")
14831 (set (attr "highpart")
14832 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14833 (const_string "user")))])
14835 (define_insn "mshflo_w_x"
14836 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14838 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
14839 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
14840 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
14842 "mshflo.w %N1, %N2, %0"
14843 [(set_attr "type" "arith_media")
14844 (set_attr "highpart" "ignore")])
14846 ;; These are useful to expand ANDs and as combiner patterns.
14847 (define_insn_and_split "mshfhi_l_di"
14848 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
14849 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
14851 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
14852 (const_int -4294967296))))]
14855 mshfhi.l %N1, %N2, %0
14857 "TARGET_SHMEDIA && reload_completed
14858 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
14859 [(set (match_dup 3) (match_dup 4))
14860 (set (match_dup 5) (match_dup 6))]
14862 operands[3] = gen_lowpart (SImode, operands[0]);
14863 operands[4] = gen_highpart (SImode, operands[1]);
14864 operands[5] = gen_highpart (SImode, operands[0]);
14865 operands[6] = gen_highpart (SImode, operands[2]);
14867 [(set_attr "type" "arith_media")])
14869 (define_insn "*mshfhi_l_di_rev"
14870 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14871 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14872 (const_int -4294967296))
14873 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14876 "mshfhi.l %N2, %N1, %0"
14877 [(set_attr "type" "arith_media")])
14880 [(set (match_operand:DI 0 "arith_reg_dest" "")
14881 (ior:DI (zero_extend:DI (match_operand:SI 1
14882 "extend_reg_or_0_operand" ""))
14883 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
14884 (const_int -4294967296))))
14885 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
14889 emit_insn (gen_ashldi3_media (operands[3],
14890 simplify_gen_subreg (DImode, operands[1],
14893 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
14897 (define_insn "mshflo_l_di"
14898 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14899 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14900 (const_int 4294967295))
14901 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14905 "mshflo.l %N1, %N2, %0"
14906 [(set_attr "type" "arith_media")
14907 (set_attr "highpart" "ignore")])
14909 (define_insn "*mshflo_l_di_rev"
14910 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14911 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14913 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14914 (const_int 4294967295))))]
14917 "mshflo.l %N2, %N1, %0"
14918 [(set_attr "type" "arith_media")
14919 (set_attr "highpart" "ignore")])
14921 ;; Combiner pattern for trampoline initialization.
14922 (define_insn_and_split "*double_shori"
14923 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14924 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
14926 (match_operand:DI 2 "const_int_operand" "n")))]
14928 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
14930 "rtx_equal_p (operands[0], operands[1])"
14933 HOST_WIDE_INT v = INTVAL (operands[2]);
14935 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
14936 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
14939 [(set_attr "highpart" "ignore")])
14941 (define_insn "*mshflo_l_di_x"
14942 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14943 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
14945 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14948 "mshflo.l %N1, %N2, %0"
14949 [(set_attr "type" "arith_media")
14950 (set_attr "highpart" "ignore")])
14952 (define_insn_and_split "concat_v2sf"
14953 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
14954 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
14955 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
14956 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
14959 mshflo.l %N1, %N2, %0
14962 "TARGET_SHMEDIA && reload_completed
14963 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
14964 [(set (match_dup 3) (match_dup 1))
14965 (set (match_dup 4) (match_dup 2))]
14967 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
14968 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
14970 [(set_attr "type" "arith_media")
14971 (set_attr "highpart" "ignore")])
14973 (define_insn "*mshflo_l_di_x_rev"
14974 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14975 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14978 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
14980 "mshflo.l %N2, %N1, %0"
14981 [(set_attr "type" "arith_media")
14982 (set_attr "highpart" "ignore")])
14984 (define_insn "ashlv2si3"
14985 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14986 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14987 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
14989 "mshlld.l %1, %2, %0"
14990 [(set_attr "type" "arith_media")
14991 (set_attr "highpart" "depend")])
14994 [(set (match_operand 0 "any_register_operand" "")
14995 (match_operator 3 "shift_operator"
14996 [(match_operand 1 "any_register_operand" "")
14997 (match_operand 2 "shift_count_reg_operand" "")]))]
14998 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
14999 [(set (match_dup 0) (match_dup 3))]
15001 rtx count = operands[2];
15002 enum machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
15004 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
15005 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
15006 || GET_CODE (count) == TRUNCATE)
15007 count = XEXP (count, 0);
15008 inner_mode = GET_MODE (count);
15009 count = simplify_gen_subreg (outer_mode, count, inner_mode,
15010 subreg_lowpart_offset (outer_mode, inner_mode));
15011 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
15012 operands[1], count);
15015 (define_insn "ashlv4hi3"
15016 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15017 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15018 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15020 "mshlld.w %1, %2, %0"
15021 [(set_attr "type" "arith_media")
15022 (set_attr "highpart" "depend")])
15024 (define_insn "lshrv2si3"
15025 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15026 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15027 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15029 "mshlrd.l %1, %2, %0"
15030 [(set_attr "type" "arith_media")
15031 (set_attr "highpart" "depend")])
15033 (define_insn "lshrv4hi3"
15034 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15035 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15036 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15038 "mshlrd.w %1, %2, %0"
15039 [(set_attr "type" "arith_media")
15040 (set_attr "highpart" "depend")])
15042 (define_insn "subv2si3"
15043 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15044 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15045 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15047 "msub.l %N1, %2, %0"
15048 [(set_attr "type" "arith_media")
15049 (set_attr "highpart" "depend")])
15051 (define_insn "subv4hi3"
15052 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15053 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15054 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15056 "msub.w %N1, %2, %0"
15057 [(set_attr "type" "arith_media")
15058 (set_attr "highpart" "depend")])
15060 (define_insn_and_split "subv2hi3"
15061 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15062 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
15063 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
15069 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15070 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15071 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15072 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15073 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15075 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
15076 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15079 [(set_attr "highpart" "must_split")])
15081 (define_insn "sssubv2si3"
15082 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15083 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15084 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15086 "msubs.l %N1, %2, %0"
15087 [(set_attr "type" "mcmp_media")
15088 (set_attr "highpart" "depend")])
15090 (define_insn "ussubv8qi3"
15091 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15092 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15093 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15095 "msubs.ub %N1, %2, %0"
15096 [(set_attr "type" "mcmp_media")
15097 (set_attr "highpart" "depend")])
15099 (define_insn "sssubv4hi3"
15100 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15101 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15102 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15104 "msubs.w %N1, %2, %0"
15105 [(set_attr "type" "mcmp_media")
15106 (set_attr "highpart" "depend")])
15108 ;; -------------------------------------------------------------------------
15109 ;; Floating Point Intrinsics
15110 ;; -------------------------------------------------------------------------
15112 (define_insn "fcosa_s"
15113 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15114 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15118 [(set_attr "type" "atrans_media")])
15120 (define_insn "fsina_s"
15121 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15122 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15126 [(set_attr "type" "atrans_media")])
15128 (define_insn "fipr"
15129 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15130 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
15131 "fp_arith_reg_operand" "f")
15132 (match_operand:V4SF 2
15133 "fp_arith_reg_operand" "f"))
15134 (parallel [(const_int 0)]))
15135 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15136 (parallel [(const_int 1)])))
15137 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15138 (parallel [(const_int 2)]))
15139 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15140 (parallel [(const_int 3)])))))]
15142 "fipr.s %1, %2, %0"
15143 [(set_attr "type" "fparith_media")])
15145 (define_insn "fsrra_s"
15146 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15147 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
15151 [(set_attr "type" "atrans_media")])
15153 (define_insn "ftrv"
15154 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
15158 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
15159 (parallel [(const_int 0) (const_int 5)
15160 (const_int 10) (const_int 15)]))
15161 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
15163 (vec_select:V4SF (match_dup 1)
15164 (parallel [(const_int 4) (const_int 9)
15165 (const_int 14) (const_int 3)]))
15166 (vec_select:V4SF (match_dup 2)
15167 (parallel [(const_int 1) (const_int 2)
15168 (const_int 3) (const_int 0)]))))
15171 (vec_select:V4SF (match_dup 1)
15172 (parallel [(const_int 8) (const_int 13)
15173 (const_int 2) (const_int 7)]))
15174 (vec_select:V4SF (match_dup 2)
15175 (parallel [(const_int 2) (const_int 3)
15176 (const_int 0) (const_int 1)])))
15178 (vec_select:V4SF (match_dup 1)
15179 (parallel [(const_int 12) (const_int 1)
15180 (const_int 6) (const_int 11)]))
15181 (vec_select:V4SF (match_dup 2)
15182 (parallel [(const_int 3) (const_int 0)
15183 (const_int 1) (const_int 2)]))))))]
15185 "ftrv.s %1, %2, %0"
15186 [(set_attr "type" "fparith_media")])
15188 (define_insn "ldhi_l"
15189 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15191 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15194 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
15198 [(set_attr "type" "load_media")])
15200 (define_insn "ldhi_q"
15201 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15203 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15206 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
15210 [(set_attr "type" "load_media")])
15212 (define_insn_and_split "*ldhi_q_comb0"
15213 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15215 (mem:DI (plus:SI (ior:SI (plus:SI
15216 (match_operand:SI 1 "register_operand" "r")
15217 (match_operand:SI 2 "ua_offset" "I06"))
15220 (plus:SI (and:SI (match_dup 1) (const_int 7))
15223 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15228 emit_insn (gen_ldhi_q (operands[0],
15229 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15233 (define_insn_and_split "*ldhi_q_comb1"
15234 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15236 (mem:DI (plus:SI (ior:SI (plus:SI
15237 (match_operand:SI 1 "register_operand" "r")
15238 (match_operand:SI 2 "ua_offset" "I06"))
15241 (plus:SI (and:SI (plus:SI (match_dup 1)
15242 (match_operand:SI 3 "ua_offset" "I06"))
15246 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15247 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15252 emit_insn (gen_ldhi_q (operands[0],
15253 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15257 (define_insn "ldlo_l"
15258 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15260 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15262 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
15263 (and:SI (match_dup 1) (const_int 3))))]
15266 [(set_attr "type" "load_media")])
15268 (define_insn "ldlo_q"
15269 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15271 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15273 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15274 (and:SI (match_dup 1) (const_int 7))))]
15277 [(set_attr "type" "load_media")])
15279 (define_insn_and_split "*ldlo_q_comb0"
15280 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15282 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15283 (match_operand:SI 2 "ua_offset" "I06"))
15285 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15286 (and:SI (match_dup 1) (const_int 7))))]
15287 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15292 emit_insn (gen_ldlo_q (operands[0],
15293 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15297 (define_insn_and_split "*ldlo_q_comb1"
15298 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15300 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15301 (match_operand:SI 2 "ua_offset" "I06"))
15303 (minus:SI (const_int 8)
15304 (and:SI (plus:SI (match_dup 1)
15305 (match_operand:SI 3 "ua_offset" "I06"))
15307 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
15308 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15309 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15314 emit_insn (gen_ldlo_q (operands[0],
15315 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15319 (define_insn "sthi_l"
15320 [(set (zero_extract:SI
15321 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15324 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
15326 (match_operand:SI 1 "arith_reg_operand" "r"))]
15329 [(set_attr "type" "ustore_media")])
15331 ;; All unaligned stores are considered to be 'narrow' because they typically
15332 ;; operate on less that a quadword, and when they operate on a full quadword,
15333 ;; the vanilla store high / store low sequence will cause a stall if not
15334 ;; scheduled apart.
15335 (define_insn "sthi_q"
15336 [(set (zero_extract:DI
15337 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15340 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15342 (match_operand:DI 1 "arith_reg_operand" "r"))]
15345 [(set_attr "type" "ustore_media")])
15347 (define_insn_and_split "*sthi_q_comb0"
15348 [(set (zero_extract:DI
15349 (mem:DI (plus:SI (ior:SI (plus:SI
15350 (match_operand:SI 0 "register_operand" "r")
15351 (match_operand:SI 1 "ua_offset" "I06"))
15354 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15356 (match_operand:DI 2 "arith_reg_operand" "r"))]
15357 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15362 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15367 (define_insn_and_split "*sthi_q_comb1"
15368 [(set (zero_extract:DI
15369 (mem:DI (plus:SI (ior:SI (plus:SI
15370 (match_operand:SI 0 "register_operand" "r")
15371 (match_operand:SI 1 "ua_offset" "I06"))
15374 (plus:SI (and:SI (plus:SI (match_dup 0)
15375 (match_operand:SI 2 "ua_offset" "I06"))
15379 (match_operand:DI 3 "arith_reg_operand" "r"))]
15380 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
15381 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15386 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15391 ;; This is highpart user because the address is used as full 64 bit.
15392 (define_insn "stlo_l"
15393 [(set (zero_extract:SI
15394 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15396 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
15397 (and:SI (match_dup 0) (const_int 3)))
15398 (match_operand:SI 1 "arith_reg_operand" "r"))]
15401 [(set_attr "type" "ustore_media")])
15403 (define_insn "stlo_q"
15404 [(set (zero_extract:DI
15405 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15407 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15408 (and:SI (match_dup 0) (const_int 7)))
15409 (match_operand:DI 1 "arith_reg_operand" "r"))]
15412 [(set_attr "type" "ustore_media")])
15414 (define_insn_and_split "*stlo_q_comb0"
15415 [(set (zero_extract:DI
15416 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15417 (match_operand:SI 1 "ua_offset" "I06"))
15419 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15420 (and:SI (match_dup 0) (const_int 7)))
15421 (match_operand:DI 2 "arith_reg_operand" "r"))]
15422 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15427 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15432 (define_insn_and_split "*stlo_q_comb1"
15433 [(set (zero_extract:DI
15434 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15435 (match_operand:SI 1 "ua_offset" "I06"))
15437 (minus:SI (const_int 8)
15438 (and:SI (plus:SI (match_dup 0)
15439 (match_operand:SI 2 "ua_offset" "I06"))
15441 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
15442 (match_operand:DI 3 "arith_reg_operand" "r"))]
15443 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15448 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15453 (define_insn "ldhi_l64"
15454 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15456 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15459 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
15463 [(set_attr "type" "load_media")])
15465 (define_insn "ldhi_q64"
15466 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15468 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15471 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
15475 [(set_attr "type" "load_media")])
15477 (define_insn "ldlo_l64"
15478 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15480 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15482 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
15483 (and:DI (match_dup 1) (const_int 3))))]
15486 [(set_attr "type" "load_media")])
15488 (define_insn "ldlo_q64"
15489 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15491 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15493 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
15494 (and:DI (match_dup 1) (const_int 7))))]
15497 [(set_attr "type" "load_media")])
15499 (define_insn "sthi_l64"
15500 [(set (zero_extract:SI
15501 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15504 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
15506 (match_operand:SI 1 "arith_reg_operand" "r"))]
15509 [(set_attr "type" "ustore_media")])
15511 (define_insn "sthi_q64"
15512 [(set (zero_extract:DI
15513 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15516 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
15518 (match_operand:DI 1 "arith_reg_operand" "r"))]
15521 [(set_attr "type" "ustore_media")])
15523 (define_insn "stlo_l64"
15524 [(set (zero_extract:SI
15525 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15527 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
15528 (and:DI (match_dup 0) (const_int 3)))
15529 (match_operand:SI 1 "arith_reg_operand" "r"))]
15532 [(set_attr "type" "ustore_media")])
15534 (define_insn "stlo_q64"
15535 [(set (zero_extract:DI
15536 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15538 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
15539 (and:DI (match_dup 0) (const_int 7)))
15540 (match_operand:DI 1 "arith_reg_operand" "r"))]
15543 [(set_attr "type" "ustore_media")])
15546 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
15547 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15551 [(set_attr "type" "arith_media")])
15553 (define_insn "nsbsi"
15554 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15556 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15560 [(set_attr "type" "arith_media")])
15562 (define_insn "nsbdi"
15563 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15565 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15569 [(set_attr "type" "arith_media")])
15571 (define_expand "ffsdi2"
15572 [(set (match_operand:DI 0 "arith_reg_dest" "")
15573 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
15576 rtx scratch = gen_reg_rtx (DImode);
15579 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
15580 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
15581 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
15582 emit_insn (gen_nsbdi (scratch, scratch));
15583 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
15584 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
15585 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
15586 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
15591 (define_expand "ffssi2"
15592 [(set (match_operand:SI 0 "arith_reg_dest" "")
15593 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
15596 rtx scratch = gen_reg_rtx (SImode);
15597 rtx discratch = gen_reg_rtx (DImode);
15600 emit_insn (gen_adddi3 (discratch,
15601 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15603 emit_insn (gen_andcdi3 (discratch,
15604 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15606 emit_insn (gen_nsbsi (scratch, discratch));
15607 last = emit_insn (gen_subsi3 (operands[0],
15608 force_reg (SImode, GEN_INT (63)), scratch));
15609 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
15614 (define_insn "byterev"
15615 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15616 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
15617 (parallel [(const_int 7) (const_int 6) (const_int 5)
15618 (const_int 4) (const_int 3) (const_int 2)
15619 (const_int 1) (const_int 0)])))]
15622 [(set_attr "type" "arith_media")])
15624 ;; In user mode, the "pref" instruction will raise a RADDERR exception
15625 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
15626 ;; implementation of __builtin_prefetch for VxWorks RTPs.
15627 (define_expand "prefetch"
15628 [(prefetch (match_operand 0 "address_operand" "")
15629 (match_operand:SI 1 "const_int_operand" "")
15630 (match_operand:SI 2 "const_int_operand" ""))]
15631 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
15632 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
15634 (define_insn "*prefetch"
15635 [(prefetch (match_operand:SI 0 "register_operand" "r")
15636 (match_operand:SI 1 "const_int_operand" "n")
15637 (match_operand:SI 2 "const_int_operand" "n"))]
15638 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
15640 [(set_attr "type" "other")])
15642 (define_insn "*prefetch_media"
15643 [(prefetch (match_operand:QI 0 "address_operand" "p")
15644 (match_operand:SI 1 "const_int_operand" "n")
15645 (match_operand:SI 2 "const_int_operand" "n"))]
15648 operands[0] = gen_rtx_MEM (QImode, operands[0]);
15649 output_asm_insn ("ld%M0.b %m0,r63", operands);
15652 [(set_attr "type" "other")])
15654 (define_insn "alloco_i"
15655 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
15656 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
15661 if (GET_CODE (operands[0]) == PLUS)
15663 xops[0] = XEXP (operands[0], 0);
15664 xops[1] = XEXP (operands[0], 1);
15668 xops[0] = operands[0];
15669 xops[1] = const0_rtx;
15671 output_asm_insn ("alloco %0, %1", xops);
15674 [(set_attr "type" "other")])
15677 [(set (match_operand 0 "any_register_operand" "")
15678 (match_operand 1 "" ""))]
15679 "TARGET_SHMEDIA && reload_completed"
15680 [(set (match_dup 0) (match_dup 1))]
15684 for_each_rtx (&operands[1], shmedia_cleanup_truncate, &n_changes);
15689 ;; -------------------------------------------------------------------------
15690 ;; Stack Protector Patterns
15691 ;; -------------------------------------------------------------------------
15693 (define_expand "stack_protect_set"
15694 [(set (match_operand 0 "memory_operand" "")
15695 (match_operand 1 "memory_operand" ""))]
15698 if (TARGET_SHMEDIA)
15700 if (TARGET_SHMEDIA64)
15701 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
15703 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
15706 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
15711 (define_insn "stack_protect_set_si"
15712 [(set (match_operand:SI 0 "memory_operand" "=m")
15713 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15714 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15717 return "mov.l %1,%2" "\n"
15718 " mov.l %2,%0" "\n"
15721 [(set_attr "type" "other")
15722 (set_attr "length" "6")])
15724 (define_insn "stack_protect_set_si_media"
15725 [(set (match_operand:SI 0 "memory_operand" "=m")
15726 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15727 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15730 return "ld%M1.l %m1,%2" "\n"
15731 " st%M0.l %m0,%2" "\n"
15734 [(set_attr "type" "other")
15735 (set_attr "length" "12")])
15737 (define_insn "stack_protect_set_di_media"
15738 [(set (match_operand:DI 0 "memory_operand" "=m")
15739 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15740 (set (match_scratch:DI 2 "=&r") (const_int 0))]
15743 return "ld%M1.q %m1,%2" "\n"
15744 " st%M0.q %m0,%2" "\n"
15747 [(set_attr "type" "other")
15748 (set_attr "length" "12")])
15750 (define_expand "stack_protect_test"
15751 [(match_operand 0 "memory_operand" "")
15752 (match_operand 1 "memory_operand" "")
15753 (match_operand 2 "" "")]
15756 if (TARGET_SHMEDIA)
15758 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
15761 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15762 if (TARGET_SHMEDIA64)
15764 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
15766 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
15770 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
15772 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
15777 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
15778 emit_jump_insn (gen_branch_true (operands[2]));
15784 (define_insn "stack_protect_test_si"
15785 [(set (reg:SI T_REG)
15786 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
15787 (match_operand:SI 1 "memory_operand" "m")]
15789 (set (match_scratch:SI 2 "=&r") (const_int 0))
15790 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15793 return "mov.l %0,%2" "\n"
15794 " mov.l %1,%3" "\n"
15795 " cmp/eq %2,%3" "\n"
15799 [(set_attr "type" "other")
15800 (set_attr "length" "10")])
15802 (define_insn "stack_protect_test_si_media"
15803 [(set (match_operand:SI 0 "register_operand" "=&r")
15804 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
15805 (match_operand:SI 2 "memory_operand" "m")]
15807 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15810 return "ld%M1.l %m1,%0" "\n"
15811 " ld%M2.l %m2,%3" "\n"
15812 " cmpeq %0,%3,%0" "\n"
15815 [(set_attr "type" "other")
15816 (set_attr "length" "16")])
15818 (define_insn "stack_protect_test_di_media"
15819 [(set (match_operand:DI 0 "register_operand" "=&r")
15820 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
15821 (match_operand:DI 2 "memory_operand" "m")]
15823 (set (match_scratch:DI 3 "=&r") (const_int 0))]
15826 return "ld%M1.q %m1,%0" "\n"
15827 " ld%M2.q %m2,%3" "\n"
15828 " cmpeq %0,%3,%0" "\n"
15831 [(set_attr "type" "other")
15832 (set_attr "length" "16")])
15834 ;; -------------------------------------------------------------------------
15835 ;; Atomic operations
15836 ;; -------------------------------------------------------------------------
15838 (include "sync.md")