1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
38 /* Needed for use_return_insn. */
41 #ifdef SUPPORT_SUN_FPA
43 /* Index into this array by (register number >> 3) to find the
44 smallest class which contains that register. */
45 enum reg_class regno_reg_class
[]
46 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
47 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
49 #endif /* defined SUPPORT_SUN_FPA */
51 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
52 if SGS_SWITCH_TABLE. */
53 int switch_table_difference_label_flag
;
55 static rtx
find_addr_reg ();
56 rtx
legitimize_pic_address ();
57 void print_operand_address ();
60 /* Alignment to use for loops and jumps */
61 /* Specify power of two alignment used for loops. */
62 const char *m68k_align_loops_string
;
63 /* Specify power of two alignment used for non-loop jumps. */
64 const char *m68k_align_jumps_string
;
65 /* Specify power of two alignment used for functions. */
66 const char *m68k_align_funcs_string
;
68 /* Specify power of two alignment used for loops. */
70 /* Specify power of two alignment used for non-loop jumps. */
72 /* Specify power of two alignment used for functions. */
75 /* Nonzero if the last compare/test insn had FP operands. The
76 sCC expanders peek at this to determine what to do for the
77 68060, which has no fsCC instructions. */
78 int m68k_last_compare_had_fp_operands
;
80 /* Sometimes certain combinations of command options do not make
81 sense on a particular target machine. You can define a macro
82 `OVERRIDE_OPTIONS' to take account of this. This macro, if
83 defined, is executed once just after all the command options have
86 Don't use this macro to turn on various extra optimizations for
87 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
96 /* Validate -malign-loops= value, or provide default */
97 if (m68k_align_loops_string
)
99 m68k_align_loops
= atoi (m68k_align_loops_string
);
100 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
101 fatal ("-malign-loops=%d is not between 1 and %d",
102 m68k_align_loops
, MAX_CODE_ALIGN
);
105 m68k_align_loops
= def_align
;
107 /* Validate -malign-jumps= value, or provide default */
108 if (m68k_align_jumps_string
)
110 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
111 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
112 fatal ("-malign-jumps=%d is not between 1 and %d",
113 m68k_align_jumps
, MAX_CODE_ALIGN
);
116 m68k_align_jumps
= def_align
;
118 /* Validate -malign-functions= value, or provide default */
119 if (m68k_align_funcs_string
)
121 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
122 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
123 fatal ("-malign-functions=%d is not between 1 and %d",
124 m68k_align_funcs
, MAX_CODE_ALIGN
);
127 m68k_align_funcs
= def_align
;
130 /* This function generates the assembly code for function entry.
131 STREAM is a stdio stream to output the code to.
132 SIZE is an int: how many units of temporary storage to allocate.
133 Refer to the array `regs_ever_live' to determine which registers
134 to save; `regs_ever_live[I]' is nonzero if register number I
135 is ever used in the function. This function is responsible for
136 knowing which registers should not be saved even if used. */
139 /* Note that the order of the bit mask for fmovem is the opposite
140 of the order for movem! */
144 output_function_prologue (stream
, size
)
149 register int mask
= 0;
150 int num_saved_regs
= 0;
151 extern char call_used_regs
[];
152 int fsize
= (size
+ 3) & -4;
153 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
156 if (frame_pointer_needed
)
158 if (fsize
== 0 && TARGET_68040
)
160 /* on the 68040, pea + move is faster than link.w 0 */
162 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
163 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
164 reg_names
[FRAME_POINTER_REGNUM
]);
166 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
167 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
168 reg_names
[FRAME_POINTER_REGNUM
]);
171 else if (fsize
< 0x8000)
174 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
175 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
177 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
178 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
181 else if (TARGET_68020
)
184 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
185 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
187 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
188 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
193 /* Adding negative number is faster on the 68040. */
195 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
196 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
198 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
199 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 if (dwarf2out_do_frame ())
205 l
= (char *) dwarf2out_cfi_label ();
206 cfa_store_offset
+= 4;
207 cfa_offset
= cfa_store_offset
;
208 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
209 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
210 cfa_store_offset
+= fsize
;
215 if (fsize
+ 4 < 0x8000)
222 /* asm_fprintf() cannot handle %. */
224 asm_fprintf (stream
, "\tsubq.w %0I%d,%Rsp\n", fsize
+ 4);
226 asm_fprintf (stream
, "\tsubqw %0I%d,%Rsp\n", fsize
+ 4);
231 /* asm_fprintf() cannot handle %. */
233 asm_fprintf (stream
, "\tsubq.l %0I%d,%Rsp\n", fsize
+ 4);
235 asm_fprintf (stream
, "\tsubql %0I%d,%Rsp\n", fsize
+ 4);
239 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
241 /* On the CPU32 it is faster to use two subqw instructions to
242 subtract a small integer (8 < N <= 16) to a register. */
243 /* asm_fprintf() cannot handle %. */
245 asm_fprintf (stream
, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
248 asm_fprintf (stream
, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
253 #endif /* not NO_ADDSUB_Q */
256 /* Adding negative number is faster on the 68040. */
257 /* asm_fprintf() cannot handle %. */
259 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
261 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
267 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
269 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
275 /* asm_fprintf() cannot handle %. */
277 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
279 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
282 if (dwarf2out_do_frame ())
284 cfa_store_offset
+= fsize
;
285 cfa_offset
= cfa_store_offset
;
286 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
289 #ifdef SUPPORT_SUN_FPA
290 for (regno
= 24; regno
< 56; regno
++)
291 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
294 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
297 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
300 if (dwarf2out_do_frame ())
302 char *l
= dwarf2out_cfi_label ();
304 cfa_store_offset
+= 8;
305 if (! frame_pointer_needed
)
307 cfa_offset
= cfa_store_offset
;
308 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
310 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
316 for (regno
= 16; regno
< 24; regno
++)
317 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
319 mask
|= 1 << (regno
- 16);
322 if ((mask
& 0xff) != 0)
325 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
327 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
329 if (dwarf2out_do_frame ())
331 char *l
= (char *) dwarf2out_cfi_label ();
334 cfa_store_offset
+= num_saved_regs
* 12;
335 if (! frame_pointer_needed
)
337 cfa_offset
= cfa_store_offset
;
338 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
340 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
341 if (mask
& (1 << (regno
- 16)))
342 dwarf2out_reg_save (l
, regno
,
343 -cfa_store_offset
+ n_regs
++ * 12);
349 for (regno
= 0; regno
< 16; regno
++)
350 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
352 mask
|= 1 << (15 - regno
);
355 if (frame_pointer_needed
)
357 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
360 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
361 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
366 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
368 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
371 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
375 if (num_saved_regs
<= 2)
377 /* Store each separately in the same order moveml uses.
378 Using two movel instructions instead of a single moveml
379 is about 15% faster for the 68020 and 68030 at no expense
384 /* Undo the work from above. */
385 for (i
= 0; i
< 16; i
++)
390 "\t%Omove.l %s,-(%Rsp)\n",
392 "\tmovel %s,%Rsp@-\n",
395 if (dwarf2out_do_frame ())
397 char *l
= (char *) dwarf2out_cfi_label ();
399 cfa_store_offset
+= 4;
400 if (! frame_pointer_needed
)
402 cfa_offset
= cfa_store_offset
;
403 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
405 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
413 /* The coldfire does not support the predecrement form of the
414 movml instruction, so we must adjust the stack pointer and
415 then use the plain address register indirect mode. We also
416 have to invert the register save mask to use the new mode.
418 FIXME: if num_saved_regs was calculated earlier, we could
419 combine the stack pointer adjustment with any adjustment
420 done when the initial stack frame is created. This would
421 save an instruction */
426 for (i
= 0; i
< 16; i
++)
428 newmask
|= (1 << (15-i
));
431 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
432 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
434 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
435 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
441 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
443 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
446 if (dwarf2out_do_frame ())
448 char *l
= (char *) dwarf2out_cfi_label ();
451 cfa_store_offset
+= num_saved_regs
* 4;
452 if (! frame_pointer_needed
)
454 cfa_offset
= cfa_store_offset
;
455 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
457 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
458 if (mask
& (1 << (15 - regno
)))
459 dwarf2out_reg_save (l
, regno
,
460 -cfa_store_offset
+ n_regs
++ * 4);
463 if (flag_pic
&& current_function_uses_pic_offset_table
)
466 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
467 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
469 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
470 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
471 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
472 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
473 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
478 /* Return true if this function's epilogue can be output as RTL. */
485 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
488 /* Copied from output_function_epilogue (). We should probably create a
489 separate layout routine to perform the common work. */
491 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
492 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
498 /* This function generates the assembly code for function exit,
499 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
501 The function epilogue should not depend on the current stack pointer!
502 It should use the frame pointer only, if there is a frame pointer.
503 This is mandatory because of alloca; we also take advantage of it to
504 omit stack adjustments before returning. */
507 output_function_epilogue (stream
, size
)
512 register int mask
, fmask
;
514 int offset
, foffset
, fpoffset
;
515 extern char call_used_regs
[];
516 int fsize
= (size
+ 3) & -4;
518 rtx insn
= get_last_insn ();
519 int restore_from_sp
= 0;
521 /* If the last insn was a BARRIER, we don't have to write any code. */
522 if (GET_CODE (insn
) == NOTE
)
523 insn
= prev_nonnote_insn (insn
);
524 if (insn
&& GET_CODE (insn
) == BARRIER
)
526 /* Output just a no-op so that debuggers don't get confused
527 about which function the pc is in at this address. */
528 asm_fprintf (stream
, "\tnop\n");
532 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
533 if (profile_block_flag
== 2)
535 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
539 #ifdef FUNCTION_EXTRA_EPILOGUE
540 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
542 nregs
= 0; fmask
= 0; fpoffset
= 0;
543 #ifdef SUPPORT_SUN_FPA
544 for (regno
= 24 ; regno
< 56 ; regno
++)
545 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
547 fpoffset
= nregs
* 8;
552 for (regno
= 16; regno
< 24; regno
++)
553 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
556 fmask
|= 1 << (23 - regno
);
559 foffset
= fpoffset
+ nregs
* 12;
561 if (frame_pointer_needed
)
562 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
563 for (regno
= 0; regno
< 16; regno
++)
564 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
569 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
572 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
574 offset
= foffset
+ nregs
* 4;
575 /* FIXME : leaf_function_p below is too strong.
576 What we really need to know there is if there could be pending
577 stack adjustment needed at that point. */
578 restore_from_sp
= ! frame_pointer_needed
579 || (! current_function_calls_alloca
&& leaf_function_p ());
580 if (offset
+ fsize
>= 0x8000
582 && (mask
|| fmask
|| fpoffset
))
585 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
587 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
591 if (TARGET_5200
|| nregs
<= 2)
593 /* Restore each separately in the same order moveml does.
594 Using two movel instructions instead of a single moveml
595 is about 15% faster for the 68020 and 68030 at no expense
600 /* Undo the work from above. */
601 for (i
= 0; i
< 16; i
++)
607 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
609 reg_names
[FRAME_POINTER_REGNUM
],
612 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
613 reg_names
[FRAME_POINTER_REGNUM
],
614 offset
+ fsize
, reg_names
[i
]);
617 else if (restore_from_sp
)
620 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
623 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
630 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
632 reg_names
[FRAME_POINTER_REGNUM
],
635 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
636 reg_names
[FRAME_POINTER_REGNUM
],
637 offset
+ fsize
, reg_names
[i
]);
648 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
650 reg_names
[FRAME_POINTER_REGNUM
],
653 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
654 reg_names
[FRAME_POINTER_REGNUM
],
655 offset
+ fsize
, mask
);
658 else if (restore_from_sp
)
661 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
663 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
669 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
671 reg_names
[FRAME_POINTER_REGNUM
],
674 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
675 reg_names
[FRAME_POINTER_REGNUM
],
676 offset
+ fsize
, mask
);
685 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
687 reg_names
[FRAME_POINTER_REGNUM
],
690 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
691 reg_names
[FRAME_POINTER_REGNUM
],
692 foffset
+ fsize
, fmask
);
695 else if (restore_from_sp
)
698 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
700 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
706 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
708 reg_names
[FRAME_POINTER_REGNUM
],
711 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
712 reg_names
[FRAME_POINTER_REGNUM
],
713 foffset
+ fsize
, fmask
);
718 for (regno
= 55; regno
>= 24; regno
--)
719 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
724 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
726 reg_names
[FRAME_POINTER_REGNUM
],
729 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
730 reg_names
[FRAME_POINTER_REGNUM
],
731 fpoffset
+ fsize
, reg_names
[regno
]);
734 else if (restore_from_sp
)
737 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
740 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
747 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
749 reg_names
[FRAME_POINTER_REGNUM
],
752 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
753 reg_names
[FRAME_POINTER_REGNUM
],
754 fpoffset
+ fsize
, reg_names
[regno
]);
759 if (frame_pointer_needed
)
760 fprintf (stream
, "\tunlk %s\n",
761 reg_names
[FRAME_POINTER_REGNUM
]);
770 asm_fprintf (stream
, "\taddq.w %0I%d,%Rsp\n", fsize
+ 4);
772 asm_fprintf (stream
, "\taddqw %0I%d,%Rsp\n", fsize
+ 4);
778 asm_fprintf (stream
, "\taddq.l %0I%d,%Rsp\n", fsize
+ 4);
780 asm_fprintf (stream
, "\taddql %0I%d,%Rsp\n", fsize
+ 4);
784 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
786 /* On the CPU32 it is faster to use two addqw instructions to
787 add a small integer (8 < N <= 16) to a register. */
788 /* asm_fprintf() cannot handle %. */
790 asm_fprintf (stream
, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
793 asm_fprintf (stream
, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
798 #endif /* not NO_ADDSUB_Q */
799 if (fsize
+ 4 < 0x8000)
803 /* asm_fprintf() cannot handle %. */
805 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
807 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
813 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
815 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
821 /* asm_fprintf() cannot handle %. */
823 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
825 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
829 if (current_function_pops_args
)
830 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
832 fprintf (stream
, "\trts\n");
835 /* Similar to general_operand, but exclude stack_pointer_rtx. */
838 not_sp_operand (op
, mode
)
840 enum machine_mode mode
;
842 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
845 /* Return TRUE if X is a valid comparison operator for the dbcc
848 Note it rejects floating point comparison operators.
849 (In the future we could use Fdbcc).
851 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
854 valid_dbcc_comparison_p (x
, mode
)
856 enum machine_mode mode ATTRIBUTE_UNUSED
;
858 switch (GET_CODE (x
))
860 case EQ
: case NE
: case GTU
: case LTU
:
864 /* Reject some when CC_NO_OVERFLOW is set. This may be over
866 case GT
: case LT
: case GE
: case LE
:
867 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
873 /* Return non-zero if flags are currently in the 68881 flag register. */
877 /* We could add support for these in the future */
878 return cc_status
.flags
& CC_IN_68881
;
881 /* Output a dbCC; jCC sequence. Note we do not handle the
882 floating point version of this sequence (Fdbcc). We also
883 do not handle alternative conditions when CC_NO_OVERFLOW is
884 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
885 kick those out before we get here. */
888 output_dbcc_and_branch (operands
)
891 switch (GET_CODE (operands
[3]))
895 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
897 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
903 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
905 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
911 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
913 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
919 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
921 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
927 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
929 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
935 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
937 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
943 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
945 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
951 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
953 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
959 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
961 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
967 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
969 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
977 /* If the decrement is to be done in SImode, then we have
978 to compensate for the fact that dbcc decrements in HImode. */
979 switch (GET_MODE (operands
[0]))
983 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
985 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
998 output_scc_di(op
, operand1
, operand2
, dest
)
1005 enum rtx_code op_code
= GET_CODE (op
);
1007 /* This does not produce a usefull cc. */
1010 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1011 below. Swap the operands and change the op if these requirements
1012 are not fulfilled. */
1013 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1017 operand1
= operand2
;
1019 op_code
= swap_condition (op_code
);
1021 loperands
[0] = operand1
;
1022 if (GET_CODE (operand1
) == REG
)
1023 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1025 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1026 if (operand2
!= const0_rtx
)
1028 loperands
[2] = operand2
;
1029 if (GET_CODE (operand2
) == REG
)
1030 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1032 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1034 loperands
[4] = gen_label_rtx();
1035 if (operand2
!= const0_rtx
)
1038 #ifdef SGS_CMP_ORDER
1039 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1041 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1044 #ifdef SGS_CMP_ORDER
1045 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1047 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1053 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1054 output_asm_insn ("tst%.l %0", loperands
);
1057 #ifdef SGS_CMP_ORDER
1058 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1060 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1065 output_asm_insn ("jbne %l4", loperands
);
1067 output_asm_insn ("jne %l4", loperands
);
1070 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1071 output_asm_insn ("tst%.l %1", loperands
);
1074 #ifdef SGS_CMP_ORDER
1075 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1077 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1082 loperands
[5] = dest
;
1087 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1088 CODE_LABEL_NUMBER (loperands
[4]));
1089 output_asm_insn ("seq %5", loperands
);
1093 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1094 CODE_LABEL_NUMBER (loperands
[4]));
1095 output_asm_insn ("sne %5", loperands
);
1099 loperands
[6] = gen_label_rtx();
1101 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1103 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1105 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1106 CODE_LABEL_NUMBER (loperands
[4]));
1107 output_asm_insn ("sgt %5", loperands
);
1108 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1109 CODE_LABEL_NUMBER (loperands
[6]));
1113 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1114 CODE_LABEL_NUMBER (loperands
[4]));
1115 output_asm_insn ("shi %5", loperands
);
1119 loperands
[6] = gen_label_rtx();
1121 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1123 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1125 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1126 CODE_LABEL_NUMBER (loperands
[4]));
1127 output_asm_insn ("slt %5", loperands
);
1128 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1129 CODE_LABEL_NUMBER (loperands
[6]));
1133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1134 CODE_LABEL_NUMBER (loperands
[4]));
1135 output_asm_insn ("scs %5", loperands
);
1139 loperands
[6] = gen_label_rtx();
1141 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1143 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1145 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1146 CODE_LABEL_NUMBER (loperands
[4]));
1147 output_asm_insn ("sge %5", loperands
);
1148 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1149 CODE_LABEL_NUMBER (loperands
[6]));
1153 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1154 CODE_LABEL_NUMBER (loperands
[4]));
1155 output_asm_insn ("scc %5", loperands
);
1159 loperands
[6] = gen_label_rtx();
1161 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1163 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1165 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1166 CODE_LABEL_NUMBER (loperands
[4]));
1167 output_asm_insn ("sle %5", loperands
);
1168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1169 CODE_LABEL_NUMBER (loperands
[6]));
1173 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1174 CODE_LABEL_NUMBER (loperands
[4]));
1175 output_asm_insn ("sls %5", loperands
);
1185 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1187 rtx countop
, dataop
;
1191 operands
[0] = countop
;
1192 operands
[1] = dataop
;
1194 if (GET_CODE (countop
) == CONST_INT
)
1196 register int count
= INTVAL (countop
);
1197 /* If COUNT is bigger than size of storage unit in use,
1198 advance to the containing unit of same size. */
1199 if (count
> signpos
)
1201 int offset
= (count
& ~signpos
) / 8;
1202 count
= count
& signpos
;
1203 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1205 if (count
== signpos
)
1206 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1208 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1210 /* These three statements used to use next_insns_test_no...
1211 but it appears that this should do the same job. */
1213 && next_insn_tests_no_inequality (insn
))
1216 && next_insn_tests_no_inequality (insn
))
1219 && next_insn_tests_no_inequality (insn
))
1222 cc_status
.flags
= CC_NOT_NEGATIVE
;
1224 return "btst %0,%1";
1227 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1228 reference and a constant. */
1231 symbolic_operand (op
, mode
)
1233 enum machine_mode mode ATTRIBUTE_UNUSED
;
1235 switch (GET_CODE (op
))
1243 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1244 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1245 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1247 #if 0 /* Deleted, with corresponding change in m68k.h,
1248 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1250 return GET_MODE (op
) == mode
;
1258 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1261 extend_operator(x
, mode
)
1263 enum machine_mode mode
;
1265 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1267 switch (GET_CODE(x
))
1278 /* Legitimize PIC addresses. If the address is already
1279 position-independent, we return ORIG. Newly generated
1280 position-independent addresses go to REG. If we need more
1281 than one register, we lose.
1283 An address is legitimized by making an indirect reference
1284 through the Global Offset Table with the name of the symbol
1287 The assembler and linker are responsible for placing the
1288 address of the symbol in the GOT. The function prologue
1289 is responsible for initializing a5 to the starting address
1292 The assembler is also responsible for translating a symbol name
1293 into a constant displacement from the start of the GOT.
1295 A quick example may make things a little clearer:
1297 When not generating PIC code to store the value 12345 into _foo
1298 we would generate the following code:
1302 When generating PIC two transformations are made. First, the compiler
1303 loads the address of foo into a register. So the first transformation makes:
1308 The code in movsi will intercept the lea instruction and call this
1309 routine which will transform the instructions into:
1311 movel a5@(_foo:w), a0
1315 That (in a nutshell) is how *all* symbol and label references are
1319 legitimize_pic_address (orig
, mode
, reg
)
1321 enum machine_mode mode ATTRIBUTE_UNUSED
;
1325 /* First handle a simple SYMBOL_REF or LABEL_REF */
1326 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1331 pic_ref
= gen_rtx_MEM (Pmode
,
1332 gen_rtx_PLUS (Pmode
,
1333 pic_offset_table_rtx
, orig
));
1334 current_function_uses_pic_offset_table
= 1;
1335 if (reload_in_progress
)
1336 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1337 RTX_UNCHANGING_P (pic_ref
) = 1;
1338 emit_move_insn (reg
, pic_ref
);
1341 else if (GET_CODE (orig
) == CONST
)
1345 /* Make sure this is CONST has not already been legitimized */
1346 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1347 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1353 /* legitimize both operands of the PLUS */
1354 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1356 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1357 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1358 base
== reg
? 0 : reg
);
1362 if (GET_CODE (orig
) == CONST_INT
)
1363 return plus_constant_for_output (base
, INTVAL (orig
));
1364 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1365 /* Likewise, should we set special REG_NOTEs here? */
1371 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1373 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1376 const_method (constant
)
1382 i
= INTVAL (constant
);
1386 /* The Coldfire doesn't have byte or word operations. */
1387 /* FIXME: This may not be useful for the m68060 either */
1390 /* if -256 < N < 256 but N is not in range for a moveq
1391 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1392 if (USE_MOVQ (i
^ 0xff))
1394 /* Likewise, try with not.w */
1395 if (USE_MOVQ (i
^ 0xffff))
1397 /* This is the only value where neg.w is useful */
1400 /* Try also with swap */
1402 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1405 /* Otherwise, use move.l */
1410 const_int_cost (constant
)
1413 switch (const_method (constant
))
1416 /* Constants between -128 and 127 are cheap due to moveq */
1422 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1432 output_move_const_into_data_reg (operands
)
1437 i
= INTVAL (operands
[1]);
1438 switch (const_method (operands
[1]))
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %1,%0";
1444 return "moveq %1,%0";
1447 operands
[1] = GEN_INT (i
^ 0xff);
1448 #if defined (MOTOROLA) && !defined (CRDS)
1449 return "moveq%.l %1,%0\n\tnot%.b %0";
1451 return "moveq %1,%0\n\tnot%.b %0";
1454 operands
[1] = GEN_INT (i
^ 0xffff);
1455 #if defined (MOTOROLA) && !defined (CRDS)
1456 return "moveq%.l %1,%0\n\tnot%.w %0";
1458 return "moveq %1,%0\n\tnot%.w %0";
1461 #if defined (MOTOROLA) && !defined (CRDS)
1462 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1464 return "moveq %#-128,%0\n\tneg%.w %0";
1470 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1471 #if defined (MOTOROLA) && !defined (CRDS)
1472 return "moveq%.l %1,%0\n\tswap %0";
1474 return "moveq %1,%0\n\tswap %0";
1478 return "move%.l %1,%0";
1485 output_move_simode_const (operands
)
1488 if (operands
[1] == const0_rtx
1489 && (DATA_REG_P (operands
[0])
1490 || GET_CODE (operands
[0]) == MEM
)
1491 /* clr insns on 68000 read before writing.
1492 This isn't so on the 68010, but we have no TARGET_68010. */
1493 && ((TARGET_68020
|| TARGET_5200
)
1494 || !(GET_CODE (operands
[0]) == MEM
1495 && MEM_VOLATILE_P (operands
[0]))))
1497 else if (operands
[1] == const0_rtx
1498 && ADDRESS_REG_P (operands
[0]))
1499 return "sub%.l %0,%0";
1500 else if (DATA_REG_P (operands
[0]))
1501 return output_move_const_into_data_reg (operands
);
1502 else if (ADDRESS_REG_P (operands
[0])
1503 && INTVAL (operands
[1]) < 0x8000
1504 && INTVAL (operands
[1]) >= -0x8000)
1505 return "move%.w %1,%0";
1506 else if (GET_CODE (operands
[0]) == MEM
1507 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1508 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1509 && INTVAL (operands
[1]) < 0x8000
1510 && INTVAL (operands
[1]) >= -0x8000)
1512 return "move%.l %1,%0";
1516 output_move_simode (operands
)
1519 if (GET_CODE (operands
[1]) == CONST_INT
)
1520 return output_move_simode_const (operands
);
1521 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1522 || GET_CODE (operands
[1]) == CONST
)
1523 && push_operand (operands
[0], SImode
))
1525 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1526 || GET_CODE (operands
[1]) == CONST
)
1527 && ADDRESS_REG_P (operands
[0]))
1528 return "lea %a1,%0";
1529 return "move%.l %1,%0";
1533 output_move_himode (operands
)
1536 if (GET_CODE (operands
[1]) == CONST_INT
)
1538 if (operands
[1] == const0_rtx
1539 && (DATA_REG_P (operands
[0])
1540 || GET_CODE (operands
[0]) == MEM
)
1541 /* clr insns on 68000 read before writing.
1542 This isn't so on the 68010, but we have no TARGET_68010. */
1543 && ((TARGET_68020
|| TARGET_5200
)
1544 || !(GET_CODE (operands
[0]) == MEM
1545 && MEM_VOLATILE_P (operands
[0]))))
1547 else if (operands
[1] == const0_rtx
1548 && ADDRESS_REG_P (operands
[0]))
1549 return "sub%.l %0,%0";
1550 else if (DATA_REG_P (operands
[0])
1551 && INTVAL (operands
[1]) < 128
1552 && INTVAL (operands
[1]) >= -128)
1554 #if defined(MOTOROLA) && !defined(CRDS)
1555 return "moveq%.l %1,%0";
1557 return "moveq %1,%0";
1560 else if (INTVAL (operands
[1]) < 0x8000
1561 && INTVAL (operands
[1]) >= -0x8000)
1562 return "move%.w %1,%0";
1564 else if (CONSTANT_P (operands
[1]))
1565 return "move%.l %1,%0";
1567 /* Recognize the insn before a tablejump, one that refers
1568 to a table of offsets. Such an insn will need to refer
1569 to a label on the insn. So output one. Use the label-number
1570 of the table of offsets to generate this label. This code,
1571 and similar code below, assumes that there will be at most one
1572 reference to each table. */
1573 if (GET_CODE (operands
[1]) == MEM
1574 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1575 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1576 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1578 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1579 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1581 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1582 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1584 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1585 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1586 #endif /* not SGS */
1587 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1588 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1589 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1590 #ifdef SGS_SWITCH_TABLES
1591 /* Set flag saying we need to define the symbol
1592 LD%n (with value L%n-LI%n) at the end of the switch table. */
1593 switch_table_difference_label_flag
= 1;
1594 #endif /* SGS_SWITCH_TABLES */
1595 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1597 #endif /* SGS_NO_LI */
1598 return "move%.w %1,%0";
1602 output_move_qimode (operands
)
1607 /* This is probably useless, since it loses for pushing a struct
1608 of several bytes a byte at a time. */
1609 /* 68k family always modifies the stack pointer by at least 2, even for
1610 byte pushes. The 5200 (coldfire) does not do this. */
1611 if (GET_CODE (operands
[0]) == MEM
1612 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1613 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1614 && ! ADDRESS_REG_P (operands
[1])
1617 xoperands
[1] = operands
[1];
1619 = gen_rtx_MEM (QImode
,
1620 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1621 /* Just pushing a byte puts it in the high byte of the halfword. */
1622 /* We must put it in the low-order, high-numbered byte. */
1623 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1625 xoperands
[3] = stack_pointer_rtx
;
1627 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1629 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1633 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1637 /* clr and st insns on 68000 read before writing.
1638 This isn't so on the 68010, but we have no TARGET_68010. */
1639 if (!ADDRESS_REG_P (operands
[0])
1640 && ((TARGET_68020
|| TARGET_5200
)
1641 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1643 if (operands
[1] == const0_rtx
)
1645 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1646 && GET_CODE (operands
[1]) == CONST_INT
1647 && (INTVAL (operands
[1]) & 255) == 255)
1653 if (GET_CODE (operands
[1]) == CONST_INT
1654 && DATA_REG_P (operands
[0])
1655 && INTVAL (operands
[1]) < 128
1656 && INTVAL (operands
[1]) >= -128)
1658 #if defined(MOTOROLA) && !defined(CRDS)
1659 return "moveq%.l %1,%0";
1661 return "moveq %1,%0";
1664 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1665 return "sub%.l %0,%0";
1666 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1667 return "move%.l %1,%0";
1668 /* 68k family (including the 5200 coldfire) does not support byte moves to
1669 from address registers. */
1670 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1671 return "move%.w %1,%0";
1672 return "move%.b %1,%0";
1676 output_move_stricthi (operands
)
1679 if (operands
[1] == const0_rtx
1680 /* clr insns on 68000 read before writing.
1681 This isn't so on the 68010, but we have no TARGET_68010. */
1682 && ((TARGET_68020
|| TARGET_5200
)
1683 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1685 return "move%.w %1,%0";
1689 output_move_strictqi (operands
)
1692 if (operands
[1] == const0_rtx
1693 /* clr insns on 68000 read before writing.
1694 This isn't so on the 68010, but we have no TARGET_68010. */
1695 && ((TARGET_68020
|| TARGET_5200
)
1696 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1698 return "move%.b %1,%0";
1701 /* Return the best assembler insn template
1702 for moving operands[1] into operands[0] as a fullword. */
1705 singlemove_string (operands
)
1708 #ifdef SUPPORT_SUN_FPA
1709 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1710 return "fpmoves %1,%0";
1712 if (GET_CODE (operands
[1]) == CONST_INT
)
1713 return output_move_simode_const (operands
);
1714 return "move%.l %1,%0";
1718 /* Output assembler code to perform a doubleword move insn
1719 with operands OPERANDS. */
1722 output_move_double (operands
)
1727 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1732 rtx addreg0
= 0, addreg1
= 0;
1733 int dest_overlapped_low
= 0;
1734 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1739 /* First classify both operands. */
1741 if (REG_P (operands
[0]))
1743 else if (offsettable_memref_p (operands
[0]))
1745 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1747 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1749 else if (GET_CODE (operands
[0]) == MEM
)
1754 if (REG_P (operands
[1]))
1756 else if (CONSTANT_P (operands
[1]))
1758 else if (offsettable_memref_p (operands
[1]))
1760 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1762 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1764 else if (GET_CODE (operands
[1]) == MEM
)
1769 /* Check for the cases that the operand constraints are not
1770 supposed to allow to happen. Abort if we get one,
1771 because generating code for these cases is painful. */
1773 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1776 /* If one operand is decrementing and one is incrementing
1777 decrement the former register explicitly
1778 and change that operand into ordinary indexing. */
1780 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1782 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1784 output_asm_insn ("sub%.l %#12,%0", operands
);
1786 output_asm_insn ("subq%.l %#8,%0", operands
);
1787 if (GET_MODE (operands
[1]) == XFmode
)
1788 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1789 else if (GET_MODE (operands
[0]) == DFmode
)
1790 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1792 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1795 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1797 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1799 output_asm_insn ("sub%.l %#12,%1", operands
);
1801 output_asm_insn ("subq%.l %#8,%1", operands
);
1802 if (GET_MODE (operands
[1]) == XFmode
)
1803 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1804 else if (GET_MODE (operands
[1]) == DFmode
)
1805 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1807 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1811 /* If an operand is an unoffsettable memory ref, find a register
1812 we can increment temporarily to make it refer to the second word. */
1814 if (optype0
== MEMOP
)
1815 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1817 if (optype1
== MEMOP
)
1818 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1820 /* Ok, we can do one word at a time.
1821 Normally we do the low-numbered word first,
1822 but if either operand is autodecrementing then we
1823 do the high-numbered word first.
1825 In either case, set up in LATEHALF the operands to use
1826 for the high-numbered word and in some cases alter the
1827 operands in OPERANDS to be suitable for the low-numbered word. */
1831 if (optype0
== REGOP
)
1833 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1834 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1836 else if (optype0
== OFFSOP
)
1838 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1839 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1843 middlehalf
[0] = operands
[0];
1844 latehalf
[0] = operands
[0];
1847 if (optype1
== REGOP
)
1849 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1850 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1852 else if (optype1
== OFFSOP
)
1854 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1855 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1857 else if (optype1
== CNSTOP
)
1859 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1864 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1865 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1866 operands
[1] = GEN_INT (l
[0]);
1867 middlehalf
[1] = GEN_INT (l
[1]);
1868 latehalf
[1] = GEN_INT (l
[2]);
1870 else if (CONSTANT_P (operands
[1]))
1872 /* actually, no non-CONST_DOUBLE constant should ever
1875 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1876 latehalf
[1] = constm1_rtx
;
1878 latehalf
[1] = const0_rtx
;
1883 middlehalf
[1] = operands
[1];
1884 latehalf
[1] = operands
[1];
1888 /* size is not 12: */
1890 if (optype0
== REGOP
)
1891 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1892 else if (optype0
== OFFSOP
)
1893 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1895 latehalf
[0] = operands
[0];
1897 if (optype1
== REGOP
)
1898 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1899 else if (optype1
== OFFSOP
)
1900 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1901 else if (optype1
== CNSTOP
)
1902 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1904 latehalf
[1] = operands
[1];
1907 /* If insn is effectively movd N(sp),-(sp) then we will do the
1908 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1909 for the low word as well, to compensate for the first decrement of sp. */
1910 if (optype0
== PUSHOP
1911 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1912 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1913 operands
[1] = middlehalf
[1] = latehalf
[1];
1915 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1916 if the upper part of reg N does not appear in the MEM, arrange to
1917 emit the move late-half first. Otherwise, compute the MEM address
1918 into the upper part of N and use that as a pointer to the memory
1920 if (optype0
== REGOP
1921 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1923 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1925 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1926 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1928 /* If both halves of dest are used in the src memory address,
1929 compute the address into latehalf of dest.
1930 Note that this can't happen if the dest is two data regs. */
1932 xops
[0] = latehalf
[0];
1933 xops
[1] = XEXP (operands
[1], 0);
1934 output_asm_insn ("lea %a1,%0", xops
);
1935 if( GET_MODE (operands
[1]) == XFmode
)
1937 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1938 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1939 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1943 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1944 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1948 && reg_overlap_mentioned_p (middlehalf
[0],
1949 XEXP (operands
[1], 0)))
1951 /* Check for two regs used by both source and dest.
1952 Note that this can't happen if the dest is all data regs.
1953 It can happen if the dest is d6, d7, a0.
1954 But in that case, latehalf is an addr reg, so
1955 the code at compadr does ok. */
1957 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1958 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1961 /* JRV says this can't happen: */
1962 if (addreg0
|| addreg1
)
1965 /* Only the middle reg conflicts; simply put it last. */
1966 output_asm_insn (singlemove_string (operands
), operands
);
1967 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1968 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1971 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1972 /* If the low half of dest is mentioned in the source memory
1973 address, the arrange to emit the move late half first. */
1974 dest_overlapped_low
= 1;
1977 /* If one or both operands autodecrementing,
1978 do the two words, high-numbered first. */
1980 /* Likewise, the first move would clobber the source of the second one,
1981 do them in the other order. This happens only for registers;
1982 such overlap can't happen in memory unless the user explicitly
1983 sets it up, and that is an undefined circumstance. */
1985 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1986 || (optype0
== REGOP
&& optype1
== REGOP
1987 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1988 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1989 || dest_overlapped_low
)
1991 /* Make any unoffsettable addresses point at high-numbered word. */
1995 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1997 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2002 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2004 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2008 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2010 /* Undo the adds we just did. */
2012 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2014 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2018 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2020 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2022 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2025 /* Do low-numbered word. */
2026 return singlemove_string (operands
);
2029 /* Normal case: do the two words, low-numbered first. */
2031 output_asm_insn (singlemove_string (operands
), operands
);
2033 /* Do the middle one of the three words for long double */
2037 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2039 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2041 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2044 /* Make any unoffsettable addresses point at high-numbered word. */
2046 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2048 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2051 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2053 /* Undo the adds we just did. */
2057 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2059 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2064 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2066 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2072 /* Return a REG that occurs in ADDR with coefficient 1.
2073 ADDR can be effectively incremented by incrementing REG. */
2076 find_addr_reg (addr
)
2079 while (GET_CODE (addr
) == PLUS
)
2081 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2082 addr
= XEXP (addr
, 0);
2083 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2084 addr
= XEXP (addr
, 1);
2085 else if (CONSTANT_P (XEXP (addr
, 0)))
2086 addr
= XEXP (addr
, 1);
2087 else if (CONSTANT_P (XEXP (addr
, 1)))
2088 addr
= XEXP (addr
, 0);
2092 if (GET_CODE (addr
) == REG
)
2097 /* Output assembler code to perform a 32 bit 3 operand add. */
2100 output_addsi3 (operands
)
2103 if (! operands_match_p (operands
[0], operands
[1]))
2105 if (!ADDRESS_REG_P (operands
[1]))
2107 rtx tmp
= operands
[1];
2109 operands
[1] = operands
[2];
2113 /* These insns can result from reloads to access
2114 stack slots over 64k from the frame pointer. */
2115 if (GET_CODE (operands
[2]) == CONST_INT
2116 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2117 return "move%.l %2,%0\n\tadd%.l %1,%0";
2119 if (GET_CODE (operands
[2]) == REG
)
2120 return "lea 0(%1,%2.l),%0";
2122 return "lea %c2(%1),%0";
2125 if (GET_CODE (operands
[2]) == REG
)
2126 return "lea (%1,%2.l),%0";
2128 return "lea (%c2,%1),%0";
2129 #else /* not MOTOROLA (MIT syntax) */
2130 if (GET_CODE (operands
[2]) == REG
)
2131 return "lea %1@(0,%2:l),%0";
2133 return "lea %1@(%c2),%0";
2134 #endif /* not MOTOROLA */
2135 #endif /* not SGS */
2137 if (GET_CODE (operands
[2]) == CONST_INT
)
2140 if (INTVAL (operands
[2]) > 0
2141 && INTVAL (operands
[2]) <= 8)
2142 return "addq%.l %2,%0";
2143 if (INTVAL (operands
[2]) < 0
2144 && INTVAL (operands
[2]) >= -8)
2146 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2147 return "subq%.l %2,%0";
2149 /* On the CPU32 it is faster to use two addql instructions to
2150 add a small integer (8 < N <= 16) to a register.
2151 Likewise for subql. */
2152 if (TARGET_CPU32
&& REG_P (operands
[0]))
2154 if (INTVAL (operands
[2]) > 8
2155 && INTVAL (operands
[2]) <= 16)
2157 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2158 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2160 if (INTVAL (operands
[2]) < -8
2161 && INTVAL (operands
[2]) >= -16)
2163 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2164 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2168 if (ADDRESS_REG_P (operands
[0])
2169 && INTVAL (operands
[2]) >= -0x8000
2170 && INTVAL (operands
[2]) < 0x8000)
2173 return "add%.w %2,%0";
2176 return "lea (%c2,%0),%0";
2178 return "lea %0@(%c2),%0";
2182 return "add%.l %2,%0";
2185 /* Store in cc_status the expressions that the condition codes will
2186 describe after execution of an instruction whose pattern is EXP.
2187 Do not alter them if the instruction would not alter the cc's. */
2189 /* On the 68000, all the insns to store in an address register fail to
2190 set the cc's. However, in some cases these instructions can make it
2191 possibly invalid to use the saved cc's. In those cases we clear out
2192 some or all of the saved cc's so they won't be used. */
2195 notice_update_cc (exp
, insn
)
2199 /* If the cc is being set from the fpa and the expression is not an
2200 explicit floating point test instruction (which has code to deal with
2201 this), reinit the CC. */
2202 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2203 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2204 && !(GET_CODE (exp
) == PARALLEL
2205 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2206 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2210 else if (GET_CODE (exp
) == SET
)
2212 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2216 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2218 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2219 cc_status
.value1
= 0;
2220 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2221 cc_status
.value2
= 0;
2223 else if (!FP_REG_P (SET_DEST (exp
))
2224 && SET_DEST (exp
) != cc0_rtx
2225 && (FP_REG_P (SET_SRC (exp
))
2226 || GET_CODE (SET_SRC (exp
)) == FIX
2227 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2228 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2232 /* A pair of move insns doesn't produce a useful overall cc. */
2233 else if (!FP_REG_P (SET_DEST (exp
))
2234 && !FP_REG_P (SET_SRC (exp
))
2235 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2236 && (GET_CODE (SET_SRC (exp
)) == REG
2237 || GET_CODE (SET_SRC (exp
)) == MEM
2238 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2242 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2246 else if (XEXP (exp
, 0) != pc_rtx
)
2248 cc_status
.flags
= 0;
2249 cc_status
.value1
= XEXP (exp
, 0);
2250 cc_status
.value2
= XEXP (exp
, 1);
2253 else if (GET_CODE (exp
) == PARALLEL
2254 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2256 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2258 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2260 cc_status
.flags
= 0;
2261 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2262 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2267 if (cc_status
.value2
!= 0
2268 && ADDRESS_REG_P (cc_status
.value2
)
2269 && GET_MODE (cc_status
.value2
) == QImode
)
2271 if (cc_status
.value2
!= 0
2272 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2273 switch (GET_CODE (cc_status
.value2
))
2275 case PLUS
: case MINUS
: case MULT
:
2276 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2277 #if 0 /* These instructions always clear the overflow bit */
2278 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2279 case ROTATE
: case ROTATERT
:
2281 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2282 cc_status
.flags
|= CC_NO_OVERFLOW
;
2285 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2286 ends with a move insn moving r2 in r2's mode.
2287 Thus, the cc's are set for r2.
2288 This can set N bit spuriously. */
2289 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2294 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2296 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2297 cc_status
.value2
= 0;
2298 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2299 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2300 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2301 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2302 cc_status
.flags
= CC_IN_68881
;
2306 output_move_const_double (operands
)
2309 #ifdef SUPPORT_SUN_FPA
2310 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2312 int code
= standard_sun_fpa_constant_p (operands
[1]);
2316 static char buf
[40];
2318 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2321 return "fpmove%.d %1,%0";
2326 int code
= standard_68881_constant_p (operands
[1]);
2330 static char buf
[40];
2332 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2335 return "fmove%.d %1,%0";
2340 output_move_const_single (operands
)
2343 #ifdef SUPPORT_SUN_FPA
2346 int code
= standard_sun_fpa_constant_p (operands
[1]);
2350 static char buf
[40];
2352 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2355 return "fpmove%.s %1,%0";
2358 #endif /* defined SUPPORT_SUN_FPA */
2360 int code
= standard_68881_constant_p (operands
[1]);
2364 static char buf
[40];
2366 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2369 return "fmove%.s %f1,%0";
2373 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2374 from the "fmovecr" instruction.
2375 The value, anded with 0xff, gives the code to use in fmovecr
2376 to get the desired constant. */
2378 /* This code has been fixed for cross-compilation. */
2380 static int inited_68881_table
= 0;
2382 char *strings_68881
[7] = {
2392 int codes_68881
[7] = {
2402 REAL_VALUE_TYPE values_68881
[7];
2404 /* Set up values_68881 array by converting the decimal values
2405 strings_68881 to binary. */
2412 enum machine_mode mode
;
2415 for (i
= 0; i
< 7; i
++)
2419 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2420 values_68881
[i
] = r
;
2422 inited_68881_table
= 1;
2426 standard_68881_constant_p (x
)
2432 #ifdef NO_ASM_FMOVECR
2436 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2437 used at all on those chips. */
2438 if (TARGET_68040
|| TARGET_68060
)
2441 #ifndef REAL_ARITHMETIC
2442 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2443 if (! flag_pretend_float
)
2448 if (! inited_68881_table
)
2449 init_68881_table ();
2451 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2453 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2455 for (i
= 0; i
< 6; i
++)
2457 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2458 return (codes_68881
[i
]);
2461 if (GET_MODE (x
) == SFmode
)
2464 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2465 return (codes_68881
[6]);
2467 /* larger powers of ten in the constants ram are not used
2468 because they are not equal to a `double' C constant. */
2472 /* If X is a floating-point constant, return the logarithm of X base 2,
2473 or 0 if X is not a power of 2. */
2476 floating_exact_log2 (x
)
2479 REAL_VALUE_TYPE r
, r1
;
2482 #ifndef REAL_ARITHMETIC
2483 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2484 if (! flag_pretend_float
)
2489 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2491 if (REAL_VALUES_LESS (r
, dconst0
))
2496 while (REAL_VALUES_LESS (r1
, r
))
2498 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2499 if (REAL_VALUES_EQUAL (r1
, r
))
2506 #ifdef SUPPORT_SUN_FPA
2507 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2508 from the Sun FPA's constant RAM.
2509 The value returned, anded with 0x1ff, gives the code to use in fpmove
2510 to get the desired constant. */
2512 static int inited_FPA_table
= 0;
2514 char *strings_FPA
[38] = {
2515 /* small rationals */
2528 /* Decimal equivalents of double precision values */
2529 "2.718281828459045091", /* D_E */
2530 "6.283185307179586477", /* 2 pi */
2531 "3.141592653589793116", /* D_PI */
2532 "1.570796326794896619", /* pi/2 */
2533 "1.414213562373095145", /* D_SQRT2 */
2534 "0.7071067811865475244", /* 1/sqrt(2) */
2535 "-1.570796326794896619", /* -pi/2 */
2536 "1.442695040888963387", /* D_LOG2ofE */
2537 "3.321928024887362182", /* D_LOG2of10 */
2538 "0.6931471805599452862", /* D_LOGEof2 */
2539 "2.302585092994045901", /* D_LOGEof10 */
2540 "0.3010299956639811980", /* D_LOG10of2 */
2541 "0.4342944819032518167", /* D_LOG10ofE */
2542 /* Decimal equivalents of single precision values */
2543 "2.718281745910644531", /* S_E */
2544 "6.283185307179586477", /* 2 pi */
2545 "3.141592741012573242", /* S_PI */
2546 "1.570796326794896619", /* pi/2 */
2547 "1.414213538169860840", /* S_SQRT2 */
2548 "0.7071067811865475244", /* 1/sqrt(2) */
2549 "-1.570796326794896619", /* -pi/2 */
2550 "1.442695021629333496", /* S_LOG2ofE */
2551 "3.321928024291992188", /* S_LOG2of10 */
2552 "0.6931471824645996094", /* S_LOGEof2 */
2553 "2.302585124969482442", /* S_LOGEof10 */
2554 "0.3010300099849700928", /* S_LOG10of2 */
2555 "0.4342944920063018799", /* S_LOG10ofE */
2559 int codes_FPA
[38] = {
2560 /* small rationals */
2573 /* double precision */
2587 /* single precision */
2603 REAL_VALUE_TYPE values_FPA
[38];
2605 /* This code has been fixed for cross-compilation. */
2610 enum machine_mode mode
;
2615 for (i
= 0; i
< 38; i
++)
2619 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2622 inited_FPA_table
= 1;
2627 standard_sun_fpa_constant_p (x
)
2633 #ifndef REAL_ARITHMETIC
2634 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2635 if (! flag_pretend_float
)
2640 if (! inited_FPA_table
)
2643 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2645 for (i
=0; i
<12; i
++)
2647 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2648 return (codes_FPA
[i
]);
2651 if (GET_MODE (x
) == SFmode
)
2653 for (i
=25; i
<38; i
++)
2655 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2656 return (codes_FPA
[i
]);
2661 for (i
=12; i
<25; i
++)
2663 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2664 return (codes_FPA
[i
]);
2669 #endif /* define SUPPORT_SUN_FPA */
2671 /* A C compound statement to output to stdio stream STREAM the
2672 assembler syntax for an instruction operand X. X is an RTL
2675 CODE is a value that can be used to specify one of several ways
2676 of printing the operand. It is used when identical operands
2677 must be printed differently depending on the context. CODE
2678 comes from the `%' specification that was used to request
2679 printing of the operand. If the specification was just `%DIGIT'
2680 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2681 is the ASCII code for LTR.
2683 If X is a register, this macro should print the register's name.
2684 The names can be found in an array `reg_names' whose type is
2685 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2687 When the machine description has a specification `%PUNCT' (a `%'
2688 followed by a punctuation character), this macro is called with
2689 a null pointer for X and the punctuation character for CODE.
2691 The m68k specific codes are:
2693 '.' for dot needed in Motorola-style opcode names.
2694 '-' for an operand pushing on the stack:
2695 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2696 '+' for an operand pushing on the stack:
2697 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2698 '@' for a reference to the top word on the stack:
2699 sp@, (sp) or (%sp) depending on the style of syntax.
2700 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2701 but & in SGS syntax, $ in CRDS/UNOS syntax).
2702 '!' for the cc register (used in an `and to cc' insn).
2703 '$' for the letter `s' in an op code, but only on the 68040.
2704 '&' for the letter `d' in an op code, but only on the 68040.
2705 '/' for register prefix needed by longlong.h.
2707 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2708 'd' to force memory addressing to be absolute, not relative.
2709 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2710 'o' for operands to go directly to output_operand_address (bypassing
2711 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2712 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2713 than directly). Second part of 'y' below.
2714 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2715 or print pair of registers as rx:ry.
2716 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2717 CONST_DOUBLE's as SunFPA constant RAM registers if
2718 possible, so it should not be used except for the SunFPA.
2723 print_operand (file
, op
, letter
)
2724 FILE *file
; /* file to write to */
2725 rtx op
; /* operand to print */
2726 int letter
; /* %<letter> or 0 */
2728 #ifdef SUPPORT_SUN_FPA
2734 #if defined (MOTOROLA) && !defined (CRDS)
2735 asm_fprintf (file
, ".");
2738 else if (letter
== '#')
2740 asm_fprintf (file
, "%0I");
2742 else if (letter
== '-')
2745 asm_fprintf (file
, "-(%Rsp)");
2747 asm_fprintf (file
, "%Rsp@-");
2750 else if (letter
== '+')
2753 asm_fprintf (file
, "(%Rsp)+");
2755 asm_fprintf (file
, "%Rsp@+");
2758 else if (letter
== '@')
2761 asm_fprintf (file
, "(%Rsp)");
2763 asm_fprintf (file
, "%Rsp@");
2766 else if (letter
== '!')
2768 asm_fprintf (file
, "%Rfpcr");
2770 else if (letter
== '$')
2772 if (TARGET_68040_ONLY
)
2774 fprintf (file
, "s");
2777 else if (letter
== '&')
2779 if (TARGET_68040_ONLY
)
2781 fprintf (file
, "d");
2784 else if (letter
== '/')
2786 asm_fprintf (file
, "%R");
2788 else if (letter
== 'o')
2790 /* This is only for direct addresses with TARGET_PCREL */
2791 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2794 output_addr_const (file
, XEXP (op
, 0));
2796 else if (GET_CODE (op
) == REG
)
2798 #ifdef SUPPORT_SUN_FPA
2800 && (letter
== 'y' || letter
== 'x')
2801 && GET_MODE (op
) == DFmode
)
2803 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2804 reg_names
[REGNO (op
)+1]);
2810 /* Print out the second register name of a register pair.
2811 I.e., R (6) => 7. */
2812 fputs (reg_names
[REGNO (op
) + 1], file
);
2814 fputs (reg_names
[REGNO (op
)], file
);
2817 else if (GET_CODE (op
) == MEM
)
2819 output_address (XEXP (op
, 0));
2820 if (letter
== 'd' && ! TARGET_68020
2821 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2822 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2823 && INTVAL (XEXP (op
, 0)) < 0x8000
2824 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2827 fprintf (file
, ".l");
2829 fprintf (file
, ":l");
2833 #ifdef SUPPORT_SUN_FPA
2834 else if ((letter
== 'y' || letter
== 'w')
2835 && GET_CODE (op
) == CONST_DOUBLE
2836 && (i
= standard_sun_fpa_constant_p (op
)))
2838 fprintf (file
, "%%%d", i
& 0x1ff);
2841 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2844 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2845 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2847 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2850 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2851 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2853 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2856 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2857 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2861 /* Use `print_operand_address' instead of `output_addr_const'
2862 to ensure that we print relevant PIC stuff. */
2863 asm_fprintf (file
, "%0I");
2865 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2866 print_operand_address (file
, op
);
2868 output_addr_const (file
, op
);
2873 /* A C compound statement to output to stdio stream STREAM the
2874 assembler syntax for an instruction operand that is a memory
2875 reference whose address is ADDR. ADDR is an RTL expression.
2877 Note that this contains a kludge that knows that the only reason
2878 we have an address (plus (label_ref...) (reg...)) when not generating
2879 PIC code is in the insn before a tablejump, and we know that m68k.md
2880 generates a label LInnn: on such an insn.
2882 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2883 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2885 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2886 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2887 we want. This difference can be accommodated by using an assembler
2888 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2889 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2890 macro. See m68k/sgs.h for an example; for versions without the bug.
2891 Some assemblers refuse all the above solutions. The workaround is to
2892 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2895 They also do not like things like "pea 1.w", so we simple leave off
2896 the .w on small constants.
2898 This routine is responsible for distinguishing between -fpic and -fPIC
2899 style relocations in an address. When generating -fpic code the
2900 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2901 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2903 #ifndef ASM_OUTPUT_CASE_FETCH
2906 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2907 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2909 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2910 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2913 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2914 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2916 #endif /* ASM_OUTPUT_CASE_FETCH */
2919 print_operand_address (file
, addr
)
2923 register rtx reg1
, reg2
, breg
, ireg
;
2926 switch (GET_CODE (addr
))
2930 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2932 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2937 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2939 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2944 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2946 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2950 reg1
= reg2
= ireg
= breg
= offset
= 0;
2951 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2953 offset
= XEXP (addr
, 0);
2954 addr
= XEXP (addr
, 1);
2956 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2958 offset
= XEXP (addr
, 1);
2959 addr
= XEXP (addr
, 0);
2961 if (GET_CODE (addr
) != PLUS
)
2965 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2967 reg1
= XEXP (addr
, 0);
2968 addr
= XEXP (addr
, 1);
2970 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2972 reg1
= XEXP (addr
, 1);
2973 addr
= XEXP (addr
, 0);
2975 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2977 reg1
= XEXP (addr
, 0);
2978 addr
= XEXP (addr
, 1);
2980 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2982 reg1
= XEXP (addr
, 1);
2983 addr
= XEXP (addr
, 0);
2985 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2987 reg1
= XEXP (addr
, 0);
2988 addr
= XEXP (addr
, 1);
2990 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2992 reg1
= XEXP (addr
, 1);
2993 addr
= XEXP (addr
, 0);
2995 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2996 || GET_CODE (addr
) == SIGN_EXTEND
)
3008 #if 0 /* for OLD_INDEXING */
3009 else if (GET_CODE (addr
) == PLUS
)
3011 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3013 reg2
= XEXP (addr
, 0);
3014 addr
= XEXP (addr
, 1);
3016 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3018 reg2
= XEXP (addr
, 1);
3019 addr
= XEXP (addr
, 0);
3031 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3032 || GET_CODE (reg1
) == MULT
))
3033 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3038 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3043 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3044 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3047 if (GET_CODE (ireg
) == MULT
)
3049 scale
= INTVAL (XEXP (ireg
, 1));
3050 ireg
= XEXP (ireg
, 0);
3052 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3054 ASM_OUTPUT_CASE_FETCH (file
,
3055 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3056 reg_names
[REGNO (XEXP (ireg
, 0))]);
3057 fprintf (file
, "w");
3061 ASM_OUTPUT_CASE_FETCH (file
,
3062 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3063 reg_names
[REGNO (ireg
)]);
3064 fprintf (file
, "l");
3069 fprintf (file
, "*%d", scale
);
3071 fprintf (file
, ":%d", scale
);
3077 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3078 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3080 ASM_OUTPUT_CASE_FETCH (file
,
3081 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3082 reg_names
[REGNO (breg
)]);
3083 fprintf (file
, "l)");
3086 if (ireg
!= 0 || breg
!= 0)
3093 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3100 output_addr_const (file
, addr
);
3101 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3103 fprintf (file
, "@GOT");
3105 fprintf (file
, ".w");
3108 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3114 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3117 output_addr_const (file
, addr
);
3118 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3119 fprintf (file
, ":w");
3120 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3121 fprintf (file
, ":l");
3123 if (addr
!= 0 && ireg
!= 0)
3128 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3130 scale
= INTVAL (XEXP (ireg
, 1));
3131 ireg
= XEXP (ireg
, 0);
3133 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3136 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3138 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3144 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3146 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3152 fprintf (file
, "*%d", scale
);
3154 fprintf (file
, ":%d", scale
);
3160 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3161 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3163 ASM_OUTPUT_CASE_FETCH (file
,
3164 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3165 reg_names
[REGNO (reg1
)]);
3166 fprintf (file
, "l)");
3169 /* FALL-THROUGH (is this really what we want?) */
3171 if (GET_CODE (addr
) == CONST_INT
3172 && INTVAL (addr
) < 0x8000
3173 && INTVAL (addr
) >= -0x8000)
3177 /* Many SGS assemblers croak on size specifiers for constants. */
3178 fprintf (file
, "%d", INTVAL (addr
));
3180 fprintf (file
, "%d.w", INTVAL (addr
));
3183 fprintf (file
, "%d:w", INTVAL (addr
));
3186 else if (GET_CODE (addr
) == CONST_INT
)
3189 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
3196 else if (TARGET_PCREL
)
3199 output_addr_const (file
, addr
);
3201 asm_fprintf (file
, ":w,%Rpc)");
3203 asm_fprintf (file
, ":l,%Rpc)");
3207 /* Special case for SYMBOL_REF if the symbol name ends in
3208 `.<letter>', this can be mistaken as a size suffix. Put
3209 the name in parentheses. */
3210 if (GET_CODE (addr
) == SYMBOL_REF
3211 && strlen (XSTR (addr
, 0)) > 2
3212 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3215 output_addr_const (file
, addr
);
3219 output_addr_const (file
, addr
);
3225 /* Check for cases where a clr insns can be omitted from code using
3226 strict_low_part sets. For example, the second clrl here is not needed:
3227 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3229 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3230 insn we are checking for redundancy. TARGET is the register set by the
3234 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3235 enum machine_mode mode
;
3241 p
= prev_nonnote_insn (first_insn
);
3245 /* If it isn't an insn, then give up. */
3246 if (GET_CODE (p
) != INSN
)
3249 if (reg_set_p (target
, p
))
3251 rtx set
= single_set (p
);
3254 /* If it isn't an easy to recognize insn, then give up. */
3258 dest
= SET_DEST (set
);
3260 /* If this sets the entire target register to zero, then our
3261 first_insn is redundant. */
3262 if (rtx_equal_p (dest
, target
)
3263 && SET_SRC (set
) == const0_rtx
)
3265 else if (GET_CODE (dest
) == STRICT_LOW_PART
3266 && GET_CODE (XEXP (dest
, 0)) == REG
3267 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3268 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3269 <= GET_MODE_SIZE (mode
)))
3270 /* This is a strict low part set which modifies less than
3271 we are using, so it is safe. */
3277 p
= prev_nonnote_insn (p
);
3284 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3285 range carefully since this predicate is used in DImode contexts. Also, we
3286 need some extra crud to make it work when hosted on 64-bit machines. */
3289 const_uint32_operand (op
, mode
)
3291 enum machine_mode mode ATTRIBUTE_UNUSED
;
3293 #if HOST_BITS_PER_WIDE_INT > 32
3294 /* All allowed constants will fit a CONST_INT. */
3295 return (GET_CODE (op
) == CONST_INT
3296 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3298 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3299 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3303 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3304 to check the range carefully since this predicate is used in DImode
3308 const_sint32_operand (op
, mode
)
3310 enum machine_mode mode ATTRIBUTE_UNUSED
;
3312 /* All allowed constants will fit a CONST_INT. */
3313 return (GET_CODE (op
) == CONST_INT
3314 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3317 /* Operand predicates for implementing asymmetric pc-relative addressing
3318 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3319 when used as a source operand, but not as a destintation operand.
3321 We model this by restricting the meaning of the basic predicates
3322 (general_operand, memory_operand, etc) to forbid the use of this
3323 addressing mode, and then define the following predicates that permit
3324 this addressing mode. These predicates can then be used for the
3325 source operands of the appropriate instructions.
3327 n.b. While it is theoretically possible to change all machine patterns
3328 to use this addressing more where permitted by the architecture,
3329 it has only been implemented for "common" cases: SImode, HImode, and
3330 QImode operands, and only for the principle operations that would
3331 require this addressing mode: data movement and simple integer operations.
3333 In parallel with these new predicates, two new constraint letters
3334 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3335 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3336 In the pcrel case 's' is only valid in combination with 'a' registers.
3337 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3338 of how these constraints are used.
3340 The use of these predicates is strictly optional, though patterns that
3341 don't will cause an extra reload register to be allocated where one
3344 lea (abc:w,%pc),%a0 ; need to reload address
3345 moveq &1,%d1 ; since write to pc-relative space
3346 movel %d1,%a0@ ; is not allowed
3348 lea (abc:w,%pc),%a1 ; no need to reload address here
3349 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3351 For more info, consult tiemann@cygnus.com.
3354 All of the ugliness with predicates and constraints is due to the
3355 simple fact that the m68k does not allow a pc-relative addressing
3356 mode as a destination. gcc does not distinguish between source and
3357 destination addresses. Hence, if we claim that pc-relative address
3358 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3359 end up with invalid code. To get around this problem, we left
3360 pc-relative modes as invalid addresses, and then added special
3361 predicates and constraints to accept them.
3363 A cleaner way to handle this is to modify gcc to distinguish
3364 between source and destination addresses. We can then say that
3365 pc-relative is a valid source address but not a valid destination
3366 address, and hopefully avoid a lot of the predicate and constraint
3367 hackery. Unfortunately, this would be a pretty big change. It would
3368 be a useful change for a number of ports, but there aren't any current
3369 plans to undertake this.
3371 ***************************************************************************/
3374 /* Special case of a general operand that's used as a source operand.
3375 Use this to permit reads from PC-relative memory when -mpcrel
3379 general_src_operand (op
, mode
)
3381 enum machine_mode mode
;
3384 && GET_CODE (op
) == MEM
3385 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3386 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3387 || GET_CODE (XEXP (op
, 0)) == CONST
))
3389 return general_operand (op
, mode
);
3392 /* Special case of a nonimmediate operand that's used as a source.
3393 Use this to permit reads from PC-relative memory when -mpcrel
3397 nonimmediate_src_operand (op
, mode
)
3399 enum machine_mode mode
;
3401 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3402 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3403 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3404 || GET_CODE (XEXP (op
, 0)) == CONST
))
3406 return nonimmediate_operand (op
, mode
);
3409 /* Special case of a memory operand that's used as a source.
3410 Use this to permit reads from PC-relative memory when -mpcrel
3414 memory_src_operand (op
, mode
)
3416 enum machine_mode mode
;
3418 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3419 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3420 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3421 || GET_CODE (XEXP (op
, 0)) == CONST
))
3423 return memory_operand (op
, mode
);
3426 /* Predicate that accepts only a pc-relative address. This is needed
3427 because pc-relative addresses don't satisfy the predicate
3428 "general_src_operand". */
3431 pcrel_address (op
, mode
)
3433 enum machine_mode mode
;
3435 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3436 || GET_CODE (op
) == CONST
);
3440 output_andsi3 (operands
)
3444 if (GET_CODE (operands
[2]) == CONST_INT
3445 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3446 && (DATA_REG_P (operands
[0])
3447 || offsettable_memref_p (operands
[0]))
3450 if (GET_CODE (operands
[0]) != REG
)
3451 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3452 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3453 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3455 if (operands
[2] == const0_rtx
)
3457 return "and%.w %2,%0";
3459 if (GET_CODE (operands
[2]) == CONST_INT
3460 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3461 && (DATA_REG_P (operands
[0])
3462 || offsettable_memref_p (operands
[0])))
3464 if (DATA_REG_P (operands
[0]))
3466 operands
[1] = GEN_INT (logval
);
3470 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3471 operands
[1] = GEN_INT (logval
% 8);
3473 /* This does not set condition codes in a standard way. */
3475 return "bclr %1,%0";
3477 return "and%.l %2,%0";
3481 output_iorsi3 (operands
)
3484 register int logval
;
3485 if (GET_CODE (operands
[2]) == CONST_INT
3486 && INTVAL (operands
[2]) >> 16 == 0
3487 && (DATA_REG_P (operands
[0])
3488 || offsettable_memref_p (operands
[0]))
3491 if (GET_CODE (operands
[0]) != REG
)
3492 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3493 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3495 if (INTVAL (operands
[2]) == 0xffff)
3496 return "mov%.w %2,%0";
3497 return "or%.w %2,%0";
3499 if (GET_CODE (operands
[2]) == CONST_INT
3500 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3501 && (DATA_REG_P (operands
[0])
3502 || offsettable_memref_p (operands
[0])))
3504 if (DATA_REG_P (operands
[0]))
3506 operands
[1] = GEN_INT (logval
);
3510 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3511 operands
[1] = GEN_INT (logval
% 8);
3514 return "bset %1,%0";
3516 return "or%.l %2,%0";
3520 output_xorsi3 (operands
)
3523 register int logval
;
3524 if (GET_CODE (operands
[2]) == CONST_INT
3525 && INTVAL (operands
[2]) >> 16 == 0
3526 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3529 if (! DATA_REG_P (operands
[0]))
3530 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3531 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3533 if (INTVAL (operands
[2]) == 0xffff)
3535 return "eor%.w %2,%0";
3537 if (GET_CODE (operands
[2]) == CONST_INT
3538 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3539 && (DATA_REG_P (operands
[0])
3540 || offsettable_memref_p (operands
[0])))
3542 if (DATA_REG_P (operands
[0]))
3544 operands
[1] = GEN_INT (logval
);
3548 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3549 operands
[1] = GEN_INT (logval
% 8);
3552 return "bchg %1,%0";
3554 return "eor%.l %2,%0";