1 ;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
3 ;; This file is part of GCC.
5 ;; GCC is free software; you can redistribute it and/or modify it
6 ;; under the terms of the GNU General Public License as published
7 ;; by the Free Software Foundation; either version 3, or (at your
8 ;; option) any later version.
10 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
11 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
13 ;; License for more details.
15 ;; You should have received a copy of the GNU General Public License
16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>.
19 ;; This file contains ARM instructions that support fixed-point operations.
21 (define_insn "add<mode>3"
22 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
23 (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
24 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
27 [(set_attr "predicable" "yes")
28 (set_attr "predicable_short_it" "yes,no")
29 (set_attr "type" "alu_reg")])
31 (define_insn "add<mode>3"
32 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
34 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
36 "sadd<qaddsub_suf>%?\\t%0, %1, %2"
37 [(set_attr "predicable" "yes")
38 (set_attr "predicable_short_it" "no")
39 (set_attr "type" "alu_reg")])
41 (define_insn "usadd<mode>3"
42 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
43 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r")
44 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
46 "uqadd<qaddsub_suf>%?\\t%0, %1, %2"
47 [(set_attr "predicable" "yes")
48 (set_attr "predicable_short_it" "no")
49 (set_attr "type" "alu_reg")])
51 (define_insn "ssadd<mode>3"
52 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
53 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
54 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
56 "qadd<qaddsub_suf>%?\\t%0, %1, %2"
57 [(set_attr "predicable" "yes")
58 (set_attr "predicable_short_it" "no")
59 (set_attr "type" "alu_reg")])
61 (define_insn "sub<mode>3"
62 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
63 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r")
64 (match_operand:FIXED 2 "s_register_operand" "l,r")))]
67 [(set_attr "predicable" "yes")
68 (set_attr "predicable_short_it" "yes,no")
69 (set_attr "type" "alu_reg")])
71 (define_insn "sub<mode>3"
72 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
73 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r")
74 (match_operand:ADDSUB 2 "s_register_operand" "r")))]
76 "ssub<qaddsub_suf>%?\\t%0, %1, %2"
77 [(set_attr "predicable" "yes")
78 (set_attr "predicable_short_it" "no")
79 (set_attr "type" "alu_reg")])
81 (define_insn "ussub<mode>3"
82 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
84 (match_operand:UQADDSUB 1 "s_register_operand" "r")
85 (match_operand:UQADDSUB 2 "s_register_operand" "r")))]
87 "uqsub<qaddsub_suf>%?\\t%0, %1, %2"
88 [(set_attr "predicable" "yes")
89 (set_attr "predicable_short_it" "no")
90 (set_attr "type" "alu_reg")])
92 (define_insn "sssub<mode>3"
93 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
94 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r")
95 (match_operand:QADDSUB 2 "s_register_operand" "r")))]
97 "qsub<qaddsub_suf>%?\\t%0, %1, %2"
98 [(set_attr "predicable" "yes")
99 (set_attr "predicable_short_it" "no")
100 (set_attr "type" "alu_reg")])
102 ;; Fractional multiplies.
104 ; Note: none of these do any rounding.
106 (define_expand "mulqq3"
107 [(set (match_operand:QQ 0 "s_register_operand" "")
108 (mult:QQ (match_operand:QQ 1 "s_register_operand" "")
109 (match_operand:QQ 2 "s_register_operand" "")))]
110 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
112 rtx tmp1 = gen_reg_rtx (HImode);
113 rtx tmp2 = gen_reg_rtx (HImode);
114 rtx tmp3 = gen_reg_rtx (SImode);
116 emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1])));
117 emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2])));
118 emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2));
119 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp3, GEN_INT (8),
124 (define_expand "mulhq3"
125 [(set (match_operand:HQ 0 "s_register_operand" "")
126 (mult:HQ (match_operand:HQ 1 "s_register_operand" "")
127 (match_operand:HQ 2 "s_register_operand" "")))]
128 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
130 rtx tmp = gen_reg_rtx (SImode);
132 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
133 gen_lowpart (HImode, operands[2])));
134 /* We're doing a s.15 * s.15 multiplication, getting an s.30 result. Extract
135 an s.15 value from that. This won't overflow/saturate for _Fract
137 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp,
138 GEN_INT (16), GEN_INT (15)));
142 (define_expand "mulsq3"
143 [(set (match_operand:SQ 0 "s_register_operand" "")
144 (mult:SQ (match_operand:SQ 1 "s_register_operand" "")
145 (match_operand:SQ 2 "s_register_operand" "")))]
146 "TARGET_32BIT && arm_arch3m"
148 rtx tmp1 = gen_reg_rtx (DImode);
149 rtx tmp2 = gen_reg_rtx (SImode);
150 rtx tmp3 = gen_reg_rtx (SImode);
152 /* s.31 * s.31 -> s.62 multiplication. */
153 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
154 gen_lowpart (SImode, operands[2])));
155 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (31)));
156 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (1)));
157 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
162 ;; Accumulator multiplies.
164 (define_expand "mulsa3"
165 [(set (match_operand:SA 0 "s_register_operand" "")
166 (mult:SA (match_operand:SA 1 "s_register_operand" "")
167 (match_operand:SA 2 "s_register_operand" "")))]
168 "TARGET_32BIT && arm_arch3m"
170 rtx tmp1 = gen_reg_rtx (DImode);
171 rtx tmp2 = gen_reg_rtx (SImode);
172 rtx tmp3 = gen_reg_rtx (SImode);
174 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
175 gen_lowpart (SImode, operands[2])));
176 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15)));
177 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (17)));
178 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
183 (define_expand "mulusa3"
184 [(set (match_operand:USA 0 "s_register_operand" "")
185 (mult:USA (match_operand:USA 1 "s_register_operand" "")
186 (match_operand:USA 2 "s_register_operand" "")))]
187 "TARGET_32BIT && arm_arch3m"
189 rtx tmp1 = gen_reg_rtx (DImode);
190 rtx tmp2 = gen_reg_rtx (SImode);
191 rtx tmp3 = gen_reg_rtx (SImode);
193 emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]),
194 gen_lowpart (SImode, operands[2])));
195 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16)));
196 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16)));
197 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3));
202 ;; The code sequence emitted by this insn pattern uses the Q flag, which GCC
203 ;; doesn't generally know about, so we don't bother expanding to individual
204 ;; instructions. It may be better to just use an out-of-line asm libcall for
207 (define_insn "ssmulsa3"
208 [(set (match_operand:SA 0 "s_register_operand" "=r")
209 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r")
210 (match_operand:SA 2 "s_register_operand" "r")))
211 (clobber (match_scratch:DI 3 "=r"))
212 (clobber (match_scratch:SI 4 "=r"))
213 (clobber (reg:CC CC_REGNUM))]
214 "TARGET_32BIT && arm_arch6"
216 /* s16.15 * s16.15 -> s32.30. */
217 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands);
220 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
223 output_asm_insn ("mov\\t%4, #0", operands);
224 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
228 31 high word 0 31 low word 0
230 [ S i i .... i i i ] [ i f f f ... f f ]
233 [ S i ... i f ... f f ]
235 Need 16 integral bits, so saturate at 15th bit of high word. */
237 output_asm_insn ("ssat\\t%R3, #15, %R3", operands);
238 output_asm_insn ("mrs\\t%4, APSR", operands);
239 output_asm_insn ("tst\\t%4, #1<<27", operands);
242 output_asm_insn ("mvn\\t%4, %R3, asr #32", operands);
243 output_asm_insn ("it\\tne", operands);
244 output_asm_insn ("movne\\t%Q3, %4", operands);
249 output_asm_insn ("it\\tne", operands);
250 output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands);
252 output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands);
253 output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands);
256 [(set_attr "conds" "clob")
257 (set_attr "type" "multiple")
259 (if_then_else (eq_attr "is_thumb" "yes")
260 (if_then_else (match_test "arm_restrict_it")
265 ;; Same goes for this.
267 (define_insn "usmulusa3"
268 [(set (match_operand:USA 0 "s_register_operand" "=r")
269 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r")
270 (match_operand:USA 2 "s_register_operand" "r")))
271 (clobber (match_scratch:DI 3 "=r"))
272 (clobber (match_scratch:SI 4 "=r"))
273 (clobber (reg:CC CC_REGNUM))]
274 "TARGET_32BIT && arm_arch6"
276 /* 16.16 * 16.16 -> 32.32. */
277 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands);
280 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands);
283 output_asm_insn ("mov\\t%4, #0", operands);
284 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands);
288 31 high word 0 31 low word 0
290 [ i i i .... i i i ] [ f f f f ... f f ]
293 [ i i ... i f ... f f ]
295 Need 16 integral bits, so saturate at 16th bit of high word. */
297 output_asm_insn ("usat\\t%R3, #16, %R3", operands);
298 output_asm_insn ("mrs\\t%4, APSR", operands);
299 output_asm_insn ("tst\\t%4, #1<<27", operands);
302 output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands);
303 output_asm_insn ("it\\tne", operands);
304 output_asm_insn ("movne\\t%Q3, %4", operands);
309 output_asm_insn ("it\\tne", operands);
310 output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands);
312 output_asm_insn ("lsr\\t%0, %Q3, #16", operands);
313 output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands);
316 [(set_attr "conds" "clob")
317 (set_attr "type" "multiple")
319 (if_then_else (eq_attr "is_thumb" "yes")
320 (if_then_else (match_test "arm_restrict_it")
325 (define_expand "mulha3"
326 [(set (match_operand:HA 0 "s_register_operand" "")
327 (mult:HA (match_operand:HA 1 "s_register_operand" "")
328 (match_operand:HA 2 "s_register_operand" "")))]
329 "TARGET_DSP_MULTIPLY && arm_arch_thumb2"
331 rtx tmp = gen_reg_rtx (SImode);
333 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
334 gen_lowpart (HImode, operands[2])));
335 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16),
341 (define_expand "muluha3"
342 [(set (match_operand:UHA 0 "s_register_operand" "")
343 (mult:UHA (match_operand:UHA 1 "s_register_operand" "")
344 (match_operand:UHA 2 "s_register_operand" "")))]
345 "TARGET_DSP_MULTIPLY"
347 rtx tmp1 = gen_reg_rtx (SImode);
348 rtx tmp2 = gen_reg_rtx (SImode);
349 rtx tmp3 = gen_reg_rtx (SImode);
351 /* 8.8 * 8.8 -> 16.16 multiply. */
352 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
353 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
354 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
355 emit_insn (gen_extzv (gen_lowpart (SImode, operands[0]), tmp3,
356 GEN_INT (16), GEN_INT (8)));
361 (define_expand "ssmulha3"
362 [(set (match_operand:HA 0 "s_register_operand" "")
363 (ss_mult:HA (match_operand:HA 1 "s_register_operand" "")
364 (match_operand:HA 2 "s_register_operand" "")))]
365 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6"
367 rtx tmp = gen_reg_rtx (SImode);
370 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]),
371 gen_lowpart (HImode, operands[2])));
373 rshift = gen_rtx_ASHIFTRT (SImode, tmp, GEN_INT (7));
375 emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (HImode, operands[0]),
376 gen_rtx_SS_TRUNCATE (HImode, rshift)));
381 (define_expand "usmuluha3"
382 [(set (match_operand:UHA 0 "s_register_operand" "")
383 (us_mult:UHA (match_operand:UHA 1 "s_register_operand" "")
384 (match_operand:UHA 2 "s_register_operand" "")))]
387 rtx tmp1 = gen_reg_rtx (SImode);
388 rtx tmp2 = gen_reg_rtx (SImode);
389 rtx tmp3 = gen_reg_rtx (SImode);
390 rtx rshift_tmp = gen_reg_rtx (SImode);
392 /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a
393 normal 32x32->32-bit multiply instead. */
394 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1])));
395 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2])));
397 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2));
399 /* The operand to "usat" is signed, so we cannot use the "..., asr #8"
400 form of that instruction since the multiplication result TMP3 may have the
401 top bit set, thus be negative and saturate to zero. Use a separate
402 logical right-shift instead. */
403 emit_insn (gen_lshrsi3 (rshift_tmp, tmp3, GEN_INT (8)));
404 emit_insn (gen_arm_usatsihi (gen_lowpart (HImode, operands[0]), rshift_tmp));
409 (define_insn "arm_ssatsihi_shift"
410 [(set (match_operand:HI 0 "s_register_operand" "=r")
411 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator"
412 [(match_operand:SI 2 "s_register_operand" "r")
413 (match_operand:SI 3 "immediate_operand" "I")])))]
414 "TARGET_32BIT && arm_arch6"
415 "ssat%?\\t%0, #16, %2%S1"
416 [(set_attr "predicable" "yes")
417 (set_attr "predicable_short_it" "no")
418 (set_attr "shift" "1")
419 (set_attr "type" "alu_shift_imm")])
421 (define_insn "arm_usatsihi"
422 [(set (match_operand:HI 0 "s_register_operand" "=r")
423 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))]
425 "usat%?\\t%0, #16, %1"
426 [(set_attr "predicable" "yes")
427 (set_attr "predicable_short_it" "no")
428 (set_attr "type" "alu_imm")]