| blob | 3f5c1b4b0dd941f7bbe09f0482b1ea8bc927ea72 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
54 (UNSPEC_STFIWX 32)
55 (UNSPEC_SYNC 33)
56 (UNSPEC_SYNC_OP 34)
57 (UNSPEC_SYNC_SWAP 35)
58 (UNSPEC_LWSYNC 36)
59 (UNSPEC_ISYNC 37)
60 (UNSPEC_POPCNTB 38)
61 (UNSPEC_FRES 39)
62 (UNSPEC_SP_SET 40)
63 (UNSPEC_SP_TEST 41)
64 ])
66 ;;
67 ;; UNSPEC_VOLATILE usage
68 ;;
70 (define_constants
71 [(UNSPECV_BLOCK 0)
72 (UNSPECV_EH_RR 9) ; eh_reg_restore
73 ])
74 \f
75 ;; Define an insn type attribute. This is used in function unit delay
76 ;; computations.
77 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
78 (const_string "integer"))
80 ;; Length (in bytes).
81 ; '(pc)' in the following doesn't include the instruction itself; it is
82 ; calculated as if the instruction had zero size.
83 (define_attr "length" ""
84 (if_then_else (eq_attr "type" "branch")
85 (if_then_else (and (ge (minus (match_dup 0) (pc))
86 (const_int -32768))
87 (lt (minus (match_dup 0) (pc))
88 (const_int 32764)))
89 (const_int 4)
90 (const_int 8))
91 (const_int 4)))
93 ;; Processor type -- this attribute must exactly match the processor_type
94 ;; enumeration in rs6000.h.
96 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
97 (const (symbol_ref "rs6000_cpu_attr")))
99 (automata_option "ndfa")
101 (include "rios1.md")
102 (include "rios2.md")
103 (include "rs64.md")
104 (include "mpc.md")
105 (include "40x.md")
106 (include "440.md")
107 (include "603.md")
108 (include "6xx.md")
109 (include "7xx.md")
110 (include "7450.md")
111 (include "8540.md")
112 (include "power4.md")
113 (include "power5.md")
115 (include "predicates.md")
117 (include "darwin.md")
119 \f
120 ;; Mode macros
122 ; This mode macro allows :GPR to be used to indicate the allowable size
123 ; of whole values in GPRs.
124 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
126 ; Any supported integer mode.
127 (define_mode_macro INT [QI HI SI DI TI])
129 ; Any supported integer mode that fits in one register.
130 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
132 ; SImode or DImode, even if DImode doesn't fit in GPRs.
133 (define_mode_macro SDI [SI DI])
135 ; The size of a pointer. Also, the size of the value that a record-condition
136 ; (one with a '.') will compare.
137 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
139 ; Any hardware-supported floating-point mode
140 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
141 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
142 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
143 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
145 ; Various instructions that come in SI and DI forms.
146 ; A generic w/d attribute, for things like cmpw/cmpd.
147 (define_mode_attr wd [(SI "w") (DI "d")])
149 \f
150 ;; Start with fixed-point load and store insns. Here we put only the more
151 ;; complex forms. Basic data transfer is done later.
153 (define_expand "zero_extendqidi2"
154 [(set (match_operand:DI 0 "gpc_reg_operand" "")
155 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
156 "TARGET_POWERPC64"
157 "")
159 (define_insn ""
160 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
161 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
162 "TARGET_POWERPC64"
163 "@
164 lbz%U1%X1 %0,%1
165 rldicl %0,%1,0,56"
166 [(set_attr "type" "load,*")])
168 (define_insn ""
169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
170 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
171 (const_int 0)))
172 (clobber (match_scratch:DI 2 "=r,r"))]
173 "TARGET_64BIT"
174 "@
175 rldicl. %2,%1,0,56
176 #"
177 [(set_attr "type" "compare")
178 (set_attr "length" "4,8")])
180 (define_split
181 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
182 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
183 (const_int 0)))
184 (clobber (match_scratch:DI 2 ""))]
185 "TARGET_POWERPC64 && reload_completed"
186 [(set (match_dup 2)
187 (zero_extend:DI (match_dup 1)))
188 (set (match_dup 0)
189 (compare:CC (match_dup 2)
190 (const_int 0)))]
191 "")
193 (define_insn ""
194 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
195 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
196 (const_int 0)))
197 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
198 (zero_extend:DI (match_dup 1)))]
199 "TARGET_64BIT"
200 "@
201 rldicl. %0,%1,0,56
202 #"
203 [(set_attr "type" "compare")
204 (set_attr "length" "4,8")])
206 (define_split
207 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
208 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
209 (const_int 0)))
210 (set (match_operand:DI 0 "gpc_reg_operand" "")
211 (zero_extend:DI (match_dup 1)))]
212 "TARGET_POWERPC64 && reload_completed"
213 [(set (match_dup 0)
214 (zero_extend:DI (match_dup 1)))
215 (set (match_dup 2)
216 (compare:CC (match_dup 0)
217 (const_int 0)))]
218 "")
220 (define_insn "extendqidi2"
221 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
222 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
223 "TARGET_POWERPC64"
224 "extsb %0,%1")
226 (define_insn ""
227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
228 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
229 (const_int 0)))
230 (clobber (match_scratch:DI 2 "=r,r"))]
231 "TARGET_64BIT"
232 "@
233 extsb. %2,%1
234 #"
235 [(set_attr "type" "compare")
236 (set_attr "length" "4,8")])
238 (define_split
239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
240 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
241 (const_int 0)))
242 (clobber (match_scratch:DI 2 ""))]
243 "TARGET_POWERPC64 && reload_completed"
244 [(set (match_dup 2)
245 (sign_extend:DI (match_dup 1)))
246 (set (match_dup 0)
247 (compare:CC (match_dup 2)
248 (const_int 0)))]
249 "")
251 (define_insn ""
252 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
253 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
254 (const_int 0)))
255 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
256 (sign_extend:DI (match_dup 1)))]
257 "TARGET_64BIT"
258 "@
259 extsb. %0,%1
260 #"
261 [(set_attr "type" "compare")
262 (set_attr "length" "4,8")])
264 (define_split
265 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
266 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
267 (const_int 0)))
268 (set (match_operand:DI 0 "gpc_reg_operand" "")
269 (sign_extend:DI (match_dup 1)))]
270 "TARGET_POWERPC64 && reload_completed"
271 [(set (match_dup 0)
272 (sign_extend:DI (match_dup 1)))
273 (set (match_dup 2)
274 (compare:CC (match_dup 0)
275 (const_int 0)))]
276 "")
278 (define_expand "zero_extendhidi2"
279 [(set (match_operand:DI 0 "gpc_reg_operand" "")
280 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
281 "TARGET_POWERPC64"
282 "")
284 (define_insn ""
285 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
286 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
287 "TARGET_POWERPC64"
288 "@
289 lhz%U1%X1 %0,%1
290 rldicl %0,%1,0,48"
291 [(set_attr "type" "load,*")])
293 (define_insn ""
294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
295 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
296 (const_int 0)))
297 (clobber (match_scratch:DI 2 "=r,r"))]
298 "TARGET_64BIT"
299 "@
300 rldicl. %2,%1,0,48
301 #"
302 [(set_attr "type" "compare")
303 (set_attr "length" "4,8")])
305 (define_split
306 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
307 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
308 (const_int 0)))
309 (clobber (match_scratch:DI 2 ""))]
310 "TARGET_POWERPC64 && reload_completed"
311 [(set (match_dup 2)
312 (zero_extend:DI (match_dup 1)))
313 (set (match_dup 0)
314 (compare:CC (match_dup 2)
315 (const_int 0)))]
316 "")
318 (define_insn ""
319 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
320 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
321 (const_int 0)))
322 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_dup 1)))]
324 "TARGET_64BIT"
325 "@
326 rldicl. %0,%1,0,48
327 #"
328 [(set_attr "type" "compare")
329 (set_attr "length" "4,8")])
331 (define_split
332 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
333 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
334 (const_int 0)))
335 (set (match_operand:DI 0 "gpc_reg_operand" "")
336 (zero_extend:DI (match_dup 1)))]
337 "TARGET_POWERPC64 && reload_completed"
338 [(set (match_dup 0)
339 (zero_extend:DI (match_dup 1)))
340 (set (match_dup 2)
341 (compare:CC (match_dup 0)
342 (const_int 0)))]
343 "")
345 (define_expand "extendhidi2"
346 [(set (match_operand:DI 0 "gpc_reg_operand" "")
347 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
348 "TARGET_POWERPC64"
349 "")
351 (define_insn ""
352 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
353 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
354 "TARGET_POWERPC64"
355 "@
356 lha%U1%X1 %0,%1
357 extsh %0,%1"
358 [(set_attr "type" "load_ext,*")])
360 (define_insn ""
361 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
362 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
363 (const_int 0)))
364 (clobber (match_scratch:DI 2 "=r,r"))]
365 "TARGET_64BIT"
366 "@
367 extsh. %2,%1
368 #"
369 [(set_attr "type" "compare")
370 (set_attr "length" "4,8")])
372 (define_split
373 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
374 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
375 (const_int 0)))
376 (clobber (match_scratch:DI 2 ""))]
377 "TARGET_POWERPC64 && reload_completed"
378 [(set (match_dup 2)
379 (sign_extend:DI (match_dup 1)))
380 (set (match_dup 0)
381 (compare:CC (match_dup 2)
382 (const_int 0)))]
383 "")
385 (define_insn ""
386 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
387 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
388 (const_int 0)))
389 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
390 (sign_extend:DI (match_dup 1)))]
391 "TARGET_64BIT"
392 "@
393 extsh. %0,%1
394 #"
395 [(set_attr "type" "compare")
396 (set_attr "length" "4,8")])
398 (define_split
399 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
401 (const_int 0)))
402 (set (match_operand:DI 0 "gpc_reg_operand" "")
403 (sign_extend:DI (match_dup 1)))]
404 "TARGET_POWERPC64 && reload_completed"
405 [(set (match_dup 0)
406 (sign_extend:DI (match_dup 1)))
407 (set (match_dup 2)
408 (compare:CC (match_dup 0)
409 (const_int 0)))]
410 "")
412 (define_expand "zero_extendsidi2"
413 [(set (match_operand:DI 0 "gpc_reg_operand" "")
414 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
415 "TARGET_POWERPC64"
416 "")
418 (define_insn ""
419 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
420 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
421 "TARGET_POWERPC64"
422 "@
423 lwz%U1%X1 %0,%1
424 rldicl %0,%1,0,32"
425 [(set_attr "type" "load,*")])
427 (define_insn ""
428 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
429 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
430 (const_int 0)))
431 (clobber (match_scratch:DI 2 "=r,r"))]
432 "TARGET_64BIT"
433 "@
434 rldicl. %2,%1,0,32
435 #"
436 [(set_attr "type" "compare")
437 (set_attr "length" "4,8")])
439 (define_split
440 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
441 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
442 (const_int 0)))
443 (clobber (match_scratch:DI 2 ""))]
444 "TARGET_POWERPC64 && reload_completed"
445 [(set (match_dup 2)
446 (zero_extend:DI (match_dup 1)))
447 (set (match_dup 0)
448 (compare:CC (match_dup 2)
449 (const_int 0)))]
450 "")
452 (define_insn ""
453 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
454 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
455 (const_int 0)))
456 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
457 (zero_extend:DI (match_dup 1)))]
458 "TARGET_64BIT"
459 "@
460 rldicl. %0,%1,0,32
461 #"
462 [(set_attr "type" "compare")
463 (set_attr "length" "4,8")])
465 (define_split
466 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
467 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
468 (const_int 0)))
469 (set (match_operand:DI 0 "gpc_reg_operand" "")
470 (zero_extend:DI (match_dup 1)))]
471 "TARGET_POWERPC64 && reload_completed"
472 [(set (match_dup 0)
473 (zero_extend:DI (match_dup 1)))
474 (set (match_dup 2)
475 (compare:CC (match_dup 0)
476 (const_int 0)))]
477 "")
479 (define_expand "extendsidi2"
480 [(set (match_operand:DI 0 "gpc_reg_operand" "")
481 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
482 "TARGET_POWERPC64"
483 "")
485 (define_insn ""
486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
487 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
488 "TARGET_POWERPC64"
489 "@
490 lwa%U1%X1 %0,%1
491 extsw %0,%1"
492 [(set_attr "type" "load_ext,*")])
494 (define_insn ""
495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
496 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
497 (const_int 0)))
498 (clobber (match_scratch:DI 2 "=r,r"))]
499 "TARGET_64BIT"
500 "@
501 extsw. %2,%1
502 #"
503 [(set_attr "type" "compare")
504 (set_attr "length" "4,8")])
506 (define_split
507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
508 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
509 (const_int 0)))
510 (clobber (match_scratch:DI 2 ""))]
511 "TARGET_POWERPC64 && reload_completed"
512 [(set (match_dup 2)
513 (sign_extend:DI (match_dup 1)))
514 (set (match_dup 0)
515 (compare:CC (match_dup 2)
516 (const_int 0)))]
517 "")
519 (define_insn ""
520 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
521 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
522 (const_int 0)))
523 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
524 (sign_extend:DI (match_dup 1)))]
525 "TARGET_64BIT"
526 "@
527 extsw. %0,%1
528 #"
529 [(set_attr "type" "compare")
530 (set_attr "length" "4,8")])
532 (define_split
533 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
534 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
535 (const_int 0)))
536 (set (match_operand:DI 0 "gpc_reg_operand" "")
537 (sign_extend:DI (match_dup 1)))]
538 "TARGET_POWERPC64 && reload_completed"
539 [(set (match_dup 0)
540 (sign_extend:DI (match_dup 1)))
541 (set (match_dup 2)
542 (compare:CC (match_dup 0)
543 (const_int 0)))]
544 "")
546 (define_expand "zero_extendqisi2"
547 [(set (match_operand:SI 0 "gpc_reg_operand" "")
548 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
549 ""
550 "")
552 (define_insn ""
553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
554 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
555 ""
556 "@
557 lbz%U1%X1 %0,%1
558 {rlinm|rlwinm} %0,%1,0,0xff"
559 [(set_attr "type" "load,*")])
561 (define_insn ""
562 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
563 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
564 (const_int 0)))
565 (clobber (match_scratch:SI 2 "=r,r"))]
566 ""
567 "@
568 {andil.|andi.} %2,%1,0xff
569 #"
570 [(set_attr "type" "compare")
571 (set_attr "length" "4,8")])
573 (define_split
574 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
575 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
576 (const_int 0)))
577 (clobber (match_scratch:SI 2 ""))]
578 "reload_completed"
579 [(set (match_dup 2)
580 (zero_extend:SI (match_dup 1)))
581 (set (match_dup 0)
582 (compare:CC (match_dup 2)
583 (const_int 0)))]
584 "")
586 (define_insn ""
587 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
588 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
589 (const_int 0)))
590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
591 (zero_extend:SI (match_dup 1)))]
592 ""
593 "@
594 {andil.|andi.} %0,%1,0xff
595 #"
596 [(set_attr "type" "compare")
597 (set_attr "length" "4,8")])
599 (define_split
600 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
601 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
602 (const_int 0)))
603 (set (match_operand:SI 0 "gpc_reg_operand" "")
604 (zero_extend:SI (match_dup 1)))]
605 "reload_completed"
606 [(set (match_dup 0)
607 (zero_extend:SI (match_dup 1)))
608 (set (match_dup 2)
609 (compare:CC (match_dup 0)
610 (const_int 0)))]
611 "")
613 (define_expand "extendqisi2"
614 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
615 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
616 ""
617 "
618 {
619 if (TARGET_POWERPC)
620 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
621 else if (TARGET_POWER)
622 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
623 else
624 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
625 DONE;
626 }")
628 (define_insn "extendqisi2_ppc"
629 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
630 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
631 "TARGET_POWERPC"
632 "extsb %0,%1")
634 (define_insn ""
635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
636 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
637 (const_int 0)))
638 (clobber (match_scratch:SI 2 "=r,r"))]
639 "TARGET_POWERPC"
640 "@
641 extsb. %2,%1
642 #"
643 [(set_attr "type" "compare")
644 (set_attr "length" "4,8")])
646 (define_split
647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
648 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
649 (const_int 0)))
650 (clobber (match_scratch:SI 2 ""))]
651 "TARGET_POWERPC && reload_completed"
652 [(set (match_dup 2)
653 (sign_extend:SI (match_dup 1)))
654 (set (match_dup 0)
655 (compare:CC (match_dup 2)
656 (const_int 0)))]
657 "")
659 (define_insn ""
660 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
661 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
662 (const_int 0)))
663 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
664 (sign_extend:SI (match_dup 1)))]
665 "TARGET_POWERPC"
666 "@
667 extsb. %0,%1
668 #"
669 [(set_attr "type" "compare")
670 (set_attr "length" "4,8")])
672 (define_split
673 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
674 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
675 (const_int 0)))
676 (set (match_operand:SI 0 "gpc_reg_operand" "")
677 (sign_extend:SI (match_dup 1)))]
678 "TARGET_POWERPC && reload_completed"
679 [(set (match_dup 0)
680 (sign_extend:SI (match_dup 1)))
681 (set (match_dup 2)
682 (compare:CC (match_dup 0)
683 (const_int 0)))]
684 "")
686 (define_expand "extendqisi2_power"
687 [(parallel [(set (match_dup 2)
688 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
689 (const_int 24)))
690 (clobber (scratch:SI))])
691 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
692 (ashiftrt:SI (match_dup 2)
693 (const_int 24)))
694 (clobber (scratch:SI))])]
695 "TARGET_POWER"
696 "
697 { operands[1] = gen_lowpart (SImode, operands[1]);
698 operands[2] = gen_reg_rtx (SImode); }")
700 (define_expand "extendqisi2_no_power"
701 [(set (match_dup 2)
702 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
703 (const_int 24)))
704 (set (match_operand:SI 0 "gpc_reg_operand" "")
705 (ashiftrt:SI (match_dup 2)
706 (const_int 24)))]
707 "! TARGET_POWER && ! TARGET_POWERPC"
708 "
709 { operands[1] = gen_lowpart (SImode, operands[1]);
710 operands[2] = gen_reg_rtx (SImode); }")
712 (define_expand "zero_extendqihi2"
713 [(set (match_operand:HI 0 "gpc_reg_operand" "")
714 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
715 ""
716 "")
718 (define_insn ""
719 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
720 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
721 ""
722 "@
723 lbz%U1%X1 %0,%1
724 {rlinm|rlwinm} %0,%1,0,0xff"
725 [(set_attr "type" "load,*")])
727 (define_insn ""
728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
729 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
730 (const_int 0)))
731 (clobber (match_scratch:HI 2 "=r,r"))]
732 ""
733 "@
734 {andil.|andi.} %2,%1,0xff
735 #"
736 [(set_attr "type" "compare")
737 (set_attr "length" "4,8")])
739 (define_split
740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
741 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
742 (const_int 0)))
743 (clobber (match_scratch:HI 2 ""))]
744 "reload_completed"
745 [(set (match_dup 2)
746 (zero_extend:HI (match_dup 1)))
747 (set (match_dup 0)
748 (compare:CC (match_dup 2)
749 (const_int 0)))]
750 "")
752 (define_insn ""
753 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
754 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
755 (const_int 0)))
756 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
757 (zero_extend:HI (match_dup 1)))]
758 ""
759 "@
760 {andil.|andi.} %0,%1,0xff
761 #"
762 [(set_attr "type" "compare")
763 (set_attr "length" "4,8")])
765 (define_split
766 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
767 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
768 (const_int 0)))
769 (set (match_operand:HI 0 "gpc_reg_operand" "")
770 (zero_extend:HI (match_dup 1)))]
771 "reload_completed"
772 [(set (match_dup 0)
773 (zero_extend:HI (match_dup 1)))
774 (set (match_dup 2)
775 (compare:CC (match_dup 0)
776 (const_int 0)))]
777 "")
779 (define_expand "extendqihi2"
780 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
781 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
782 ""
783 "
784 {
785 if (TARGET_POWERPC)
786 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
787 else if (TARGET_POWER)
788 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
789 else
790 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
791 DONE;
792 }")
794 (define_insn "extendqihi2_ppc"
795 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
796 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
797 "TARGET_POWERPC"
798 "extsb %0,%1")
800 (define_insn ""
801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
802 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
803 (const_int 0)))
804 (clobber (match_scratch:HI 2 "=r,r"))]
805 "TARGET_POWERPC"
806 "@
807 extsb. %2,%1
808 #"
809 [(set_attr "type" "compare")
810 (set_attr "length" "4,8")])
812 (define_split
813 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
814 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
815 (const_int 0)))
816 (clobber (match_scratch:HI 2 ""))]
817 "TARGET_POWERPC && reload_completed"
818 [(set (match_dup 2)
819 (sign_extend:HI (match_dup 1)))
820 (set (match_dup 0)
821 (compare:CC (match_dup 2)
822 (const_int 0)))]
823 "")
825 (define_insn ""
826 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
827 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
828 (const_int 0)))
829 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
830 (sign_extend:HI (match_dup 1)))]
831 "TARGET_POWERPC"
832 "@
833 extsb. %0,%1
834 #"
835 [(set_attr "type" "compare")
836 (set_attr "length" "4,8")])
838 (define_split
839 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
840 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
841 (const_int 0)))
842 (set (match_operand:HI 0 "gpc_reg_operand" "")
843 (sign_extend:HI (match_dup 1)))]
844 "TARGET_POWERPC && reload_completed"
845 [(set (match_dup 0)
846 (sign_extend:HI (match_dup 1)))
847 (set (match_dup 2)
848 (compare:CC (match_dup 0)
849 (const_int 0)))]
850 "")
852 (define_expand "extendqihi2_power"
853 [(parallel [(set (match_dup 2)
854 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
855 (const_int 24)))
856 (clobber (scratch:SI))])
857 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
858 (ashiftrt:SI (match_dup 2)
859 (const_int 24)))
860 (clobber (scratch:SI))])]
861 "TARGET_POWER"
862 "
863 { operands[0] = gen_lowpart (SImode, operands[0]);
864 operands[1] = gen_lowpart (SImode, operands[1]);
865 operands[2] = gen_reg_rtx (SImode); }")
867 (define_expand "extendqihi2_no_power"
868 [(set (match_dup 2)
869 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
870 (const_int 24)))
871 (set (match_operand:HI 0 "gpc_reg_operand" "")
872 (ashiftrt:SI (match_dup 2)
873 (const_int 24)))]
874 "! TARGET_POWER && ! TARGET_POWERPC"
875 "
876 { operands[0] = gen_lowpart (SImode, operands[0]);
877 operands[1] = gen_lowpart (SImode, operands[1]);
878 operands[2] = gen_reg_rtx (SImode); }")
880 (define_expand "zero_extendhisi2"
881 [(set (match_operand:SI 0 "gpc_reg_operand" "")
882 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
883 ""
884 "")
886 (define_insn ""
887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
888 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
889 ""
890 "@
891 lhz%U1%X1 %0,%1
892 {rlinm|rlwinm} %0,%1,0,0xffff"
893 [(set_attr "type" "load,*")])
895 (define_insn ""
896 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
897 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
898 (const_int 0)))
899 (clobber (match_scratch:SI 2 "=r,r"))]
900 ""
901 "@
902 {andil.|andi.} %2,%1,0xffff
903 #"
904 [(set_attr "type" "compare")
905 (set_attr "length" "4,8")])
907 (define_split
908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
909 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
910 (const_int 0)))
911 (clobber (match_scratch:SI 2 ""))]
912 "reload_completed"
913 [(set (match_dup 2)
914 (zero_extend:SI (match_dup 1)))
915 (set (match_dup 0)
916 (compare:CC (match_dup 2)
917 (const_int 0)))]
918 "")
920 (define_insn ""
921 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
922 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
923 (const_int 0)))
924 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
925 (zero_extend:SI (match_dup 1)))]
926 ""
927 "@
928 {andil.|andi.} %0,%1,0xffff
929 #"
930 [(set_attr "type" "compare")
931 (set_attr "length" "4,8")])
933 (define_split
934 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
935 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
936 (const_int 0)))
937 (set (match_operand:SI 0 "gpc_reg_operand" "")
938 (zero_extend:SI (match_dup 1)))]
939 "reload_completed"
940 [(set (match_dup 0)
941 (zero_extend:SI (match_dup 1)))
942 (set (match_dup 2)
943 (compare:CC (match_dup 0)
944 (const_int 0)))]
945 "")
947 (define_expand "extendhisi2"
948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
949 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
950 ""
951 "")
953 (define_insn ""
954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
955 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
956 ""
957 "@
958 lha%U1%X1 %0,%1
959 {exts|extsh} %0,%1"
960 [(set_attr "type" "load_ext,*")])
962 (define_insn ""
963 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
965 (const_int 0)))
966 (clobber (match_scratch:SI 2 "=r,r"))]
967 ""
968 "@
969 {exts.|extsh.} %2,%1
970 #"
971 [(set_attr "type" "compare")
972 (set_attr "length" "4,8")])
974 (define_split
975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
976 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
977 (const_int 0)))
978 (clobber (match_scratch:SI 2 ""))]
979 "reload_completed"
980 [(set (match_dup 2)
981 (sign_extend:SI (match_dup 1)))
982 (set (match_dup 0)
983 (compare:CC (match_dup 2)
984 (const_int 0)))]
985 "")
987 (define_insn ""
988 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
989 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
990 (const_int 0)))
991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
992 (sign_extend:SI (match_dup 1)))]
993 ""
994 "@
995 {exts.|extsh.} %0,%1
996 #"
997 [(set_attr "type" "compare")
998 (set_attr "length" "4,8")])
999 \f
1000 (define_split
1001 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1002 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1003 (const_int 0)))
1004 (set (match_operand:SI 0 "gpc_reg_operand" "")
1005 (sign_extend:SI (match_dup 1)))]
1006 "reload_completed"
1007 [(set (match_dup 0)
1008 (sign_extend:SI (match_dup 1)))
1009 (set (match_dup 2)
1010 (compare:CC (match_dup 0)
1011 (const_int 0)))]
1012 "")
1014 ;; Fixed-point arithmetic insns.
1016 (define_expand "add<mode>3"
1017 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1018 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1019 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1020 ""
1021 "
1022 {
1023 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1024 {
1025 if (non_short_cint_operand (operands[2], DImode))
1026 FAIL;
1027 }
1028 else if (GET_CODE (operands[2]) == CONST_INT
1029 && ! add_operand (operands[2], <MODE>mode))
1030 {
1031 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1032 ? operands[0] : gen_reg_rtx (<MODE>mode));
1034 HOST_WIDE_INT val = INTVAL (operands[2]);
1035 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1036 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1038 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1039 FAIL;
1041 /* The ordering here is important for the prolog expander.
1042 When space is allocated from the stack, adding 'low' first may
1043 produce a temporary deallocation (which would be bad). */
1044 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1045 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1046 DONE;
1047 }
1048 }")
1050 ;; Discourage ai/addic because of carry but provide it in an alternative
1051 ;; allowing register zero as source.
1052 (define_insn "*add<mode>3_internal1"
1053 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1054 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1055 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1056 ""
1057 "@
1058 {cax|add} %0,%1,%2
1059 {cal %0,%2(%1)|addi %0,%1,%2}
1060 {ai|addic} %0,%1,%2
1061 {cau|addis} %0,%1,%v2"
1062 [(set_attr "length" "4,4,4,4")])
1064 (define_insn "addsi3_high"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1066 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1067 (high:SI (match_operand 2 "" ""))))]
1068 "TARGET_MACHO && !TARGET_64BIT"
1069 "{cau|addis} %0,%1,ha16(%2)"
1070 [(set_attr "length" "4")])
1072 (define_insn "*add<mode>3_internal2"
1073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1074 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1075 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1076 (const_int 0)))
1077 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1078 ""
1079 "@
1080 {cax.|add.} %3,%1,%2
1081 {ai.|addic.} %3,%1,%2
1082 #
1083 #"
1084 [(set_attr "type" "fast_compare,compare,compare,compare")
1085 (set_attr "length" "4,4,8,8")])
1087 (define_split
1088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1089 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1090 (match_operand:GPR 2 "reg_or_short_operand" ""))
1091 (const_int 0)))
1092 (clobber (match_scratch:GPR 3 ""))]
1093 "reload_completed"
1094 [(set (match_dup 3)
1095 (plus:GPR (match_dup 1)
1096 (match_dup 2)))
1097 (set (match_dup 0)
1098 (compare:CC (match_dup 3)
1099 (const_int 0)))]
1100 "")
1102 (define_insn "*add<mode>3_internal3"
1103 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1104 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1105 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1106 (const_int 0)))
1107 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1108 (plus:P (match_dup 1)
1109 (match_dup 2)))]
1110 ""
1111 "@
1112 {cax.|add.} %0,%1,%2
1113 {ai.|addic.} %0,%1,%2
1114 #
1115 #"
1116 [(set_attr "type" "fast_compare,compare,compare,compare")
1117 (set_attr "length" "4,4,8,8")])
1119 (define_split
1120 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1121 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1122 (match_operand:P 2 "reg_or_short_operand" ""))
1123 (const_int 0)))
1124 (set (match_operand:P 0 "gpc_reg_operand" "")
1125 (plus:P (match_dup 1) (match_dup 2)))]
1126 "reload_completed"
1127 [(set (match_dup 0)
1128 (plus:P (match_dup 1)
1129 (match_dup 2)))
1130 (set (match_dup 3)
1131 (compare:CC (match_dup 0)
1132 (const_int 0)))]
1133 "")
1135 ;; Split an add that we can't do in one insn into two insns, each of which
1136 ;; does one 16-bit part. This is used by combine. Note that the low-order
1137 ;; add should be last in case the result gets used in an address.
1139 (define_split
1140 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1141 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1142 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1143 ""
1144 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1145 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1146 "
1147 {
1148 HOST_WIDE_INT val = INTVAL (operands[2]);
1149 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1150 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1152 operands[4] = GEN_INT (low);
1153 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1154 operands[3] = GEN_INT (rest);
1155 else if (! no_new_pseudos)
1156 {
1157 operands[3] = gen_reg_rtx (DImode);
1158 emit_move_insn (operands[3], operands[2]);
1159 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1160 DONE;
1161 }
1162 else
1163 FAIL;
1164 }")
1166 (define_insn "one_cmpl<mode>2"
1167 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1168 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1169 ""
1170 "nor %0,%1,%1")
1172 (define_insn ""
1173 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1174 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1175 (const_int 0)))
1176 (clobber (match_scratch:P 2 "=r,r"))]
1177 ""
1178 "@
1179 nor. %2,%1,%1
1180 #"
1181 [(set_attr "type" "compare")
1182 (set_attr "length" "4,8")])
1184 (define_split
1185 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1186 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1187 (const_int 0)))
1188 (clobber (match_scratch:P 2 ""))]
1189 "reload_completed"
1190 [(set (match_dup 2)
1191 (not:P (match_dup 1)))
1192 (set (match_dup 0)
1193 (compare:CC (match_dup 2)
1194 (const_int 0)))]
1195 "")
1197 (define_insn ""
1198 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1199 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1200 (const_int 0)))
1201 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1202 (not:P (match_dup 1)))]
1203 ""
1204 "@
1205 nor. %0,%1,%1
1206 #"
1207 [(set_attr "type" "compare")
1208 (set_attr "length" "4,8")])
1210 (define_split
1211 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1212 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1213 (const_int 0)))
1214 (set (match_operand:P 0 "gpc_reg_operand" "")
1215 (not:P (match_dup 1)))]
1216 "reload_completed"
1217 [(set (match_dup 0)
1218 (not:P (match_dup 1)))
1219 (set (match_dup 2)
1220 (compare:CC (match_dup 0)
1221 (const_int 0)))]
1222 "")
1224 (define_insn ""
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1227 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1228 "! TARGET_POWERPC"
1229 "{sf%I1|subf%I1c} %0,%2,%1")
1231 (define_insn ""
1232 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1233 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1234 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1235 "TARGET_POWERPC"
1236 "@
1237 subf %0,%2,%1
1238 subfic %0,%2,%1")
1240 (define_insn ""
1241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1242 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1243 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1244 (const_int 0)))
1245 (clobber (match_scratch:SI 3 "=r,r"))]
1246 "! TARGET_POWERPC"
1247 "@
1248 {sf.|subfc.} %3,%2,%1
1249 #"
1250 [(set_attr "type" "compare")
1251 (set_attr "length" "4,8")])
1253 (define_insn ""
1254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1255 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1256 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1257 (const_int 0)))
1258 (clobber (match_scratch:P 3 "=r,r"))]
1259 "TARGET_POWERPC"
1260 "@
1261 subf. %3,%2,%1
1262 #"
1263 [(set_attr "type" "fast_compare")
1264 (set_attr "length" "4,8")])
1266 (define_split
1267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1268 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1269 (match_operand:P 2 "gpc_reg_operand" ""))
1270 (const_int 0)))
1271 (clobber (match_scratch:P 3 ""))]
1272 "reload_completed"
1273 [(set (match_dup 3)
1274 (minus:P (match_dup 1)
1275 (match_dup 2)))
1276 (set (match_dup 0)
1277 (compare:CC (match_dup 3)
1278 (const_int 0)))]
1279 "")
1281 (define_insn ""
1282 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1283 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1284 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1285 (const_int 0)))
1286 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1287 (minus:SI (match_dup 1) (match_dup 2)))]
1288 "! TARGET_POWERPC"
1289 "@
1290 {sf.|subfc.} %0,%2,%1
1291 #"
1292 [(set_attr "type" "compare")
1293 (set_attr "length" "4,8")])
1295 (define_insn ""
1296 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1297 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1298 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1299 (const_int 0)))
1300 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1301 (minus:P (match_dup 1)
1302 (match_dup 2)))]
1303 "TARGET_POWERPC"
1304 "@
1305 subf. %0,%2,%1
1306 #"
1307 [(set_attr "type" "fast_compare")
1308 (set_attr "length" "4,8")])
1310 (define_split
1311 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1312 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1313 (match_operand:P 2 "gpc_reg_operand" ""))
1314 (const_int 0)))
1315 (set (match_operand:P 0 "gpc_reg_operand" "")
1316 (minus:P (match_dup 1)
1317 (match_dup 2)))]
1318 "reload_completed"
1319 [(set (match_dup 0)
1320 (minus:P (match_dup 1)
1321 (match_dup 2)))
1322 (set (match_dup 3)
1323 (compare:CC (match_dup 0)
1324 (const_int 0)))]
1325 "")
1327 (define_expand "sub<mode>3"
1328 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1329 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1330 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1331 ""
1332 "
1333 {
1334 if (GET_CODE (operands[2]) == CONST_INT)
1335 {
1336 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1337 negate_rtx (<MODE>mode, operands[2])));
1338 DONE;
1339 }
1340 }")
1342 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1343 ;; instruction and some auxiliary computations. Then we just have a single
1344 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1345 ;; combine.
1347 (define_expand "sminsi3"
1348 [(set (match_dup 3)
1349 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1350 (match_operand:SI 2 "reg_or_short_operand" ""))
1351 (const_int 0)
1352 (minus:SI (match_dup 2) (match_dup 1))))
1353 (set (match_operand:SI 0 "gpc_reg_operand" "")
1354 (minus:SI (match_dup 2) (match_dup 3)))]
1355 "TARGET_POWER || TARGET_ISEL"
1356 "
1357 {
1358 if (TARGET_ISEL)
1359 {
1360 operands[2] = force_reg (SImode, operands[2]);
1361 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1362 DONE;
1363 }
1365 operands[3] = gen_reg_rtx (SImode);
1366 }")
1368 (define_split
1369 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1370 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1371 (match_operand:SI 2 "reg_or_short_operand" "")))
1372 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1373 "TARGET_POWER"
1374 [(set (match_dup 3)
1375 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1376 (const_int 0)
1377 (minus:SI (match_dup 2) (match_dup 1))))
1378 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1379 "")
1381 (define_expand "smaxsi3"
1382 [(set (match_dup 3)
1383 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1384 (match_operand:SI 2 "reg_or_short_operand" ""))
1385 (const_int 0)
1386 (minus:SI (match_dup 2) (match_dup 1))))
1387 (set (match_operand:SI 0 "gpc_reg_operand" "")
1388 (plus:SI (match_dup 3) (match_dup 1)))]
1389 "TARGET_POWER || TARGET_ISEL"
1390 "
1391 {
1392 if (TARGET_ISEL)
1393 {
1394 operands[2] = force_reg (SImode, operands[2]);
1395 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1396 DONE;
1397 }
1398 operands[3] = gen_reg_rtx (SImode);
1399 }")
1401 (define_split
1402 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1403 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" "")))
1405 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1406 "TARGET_POWER"
1407 [(set (match_dup 3)
1408 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1409 (const_int 0)
1410 (minus:SI (match_dup 2) (match_dup 1))))
1411 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1412 "")
1414 (define_expand "uminsi3"
1415 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1416 (match_dup 5)))
1417 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1418 (match_dup 5)))
1419 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1420 (const_int 0)
1421 (minus:SI (match_dup 4) (match_dup 3))))
1422 (set (match_operand:SI 0 "gpc_reg_operand" "")
1423 (minus:SI (match_dup 2) (match_dup 3)))]
1424 "TARGET_POWER || TARGET_ISEL"
1425 "
1426 {
1427 if (TARGET_ISEL)
1428 {
1429 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1430 DONE;
1431 }
1432 operands[3] = gen_reg_rtx (SImode);
1433 operands[4] = gen_reg_rtx (SImode);
1434 operands[5] = GEN_INT (-2147483647 - 1);
1435 }")
1437 (define_expand "umaxsi3"
1438 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1439 (match_dup 5)))
1440 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1441 (match_dup 5)))
1442 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1443 (const_int 0)
1444 (minus:SI (match_dup 4) (match_dup 3))))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "")
1446 (plus:SI (match_dup 3) (match_dup 1)))]
1447 "TARGET_POWER || TARGET_ISEL"
1448 "
1449 {
1450 if (TARGET_ISEL)
1451 {
1452 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1453 DONE;
1454 }
1455 operands[3] = gen_reg_rtx (SImode);
1456 operands[4] = gen_reg_rtx (SImode);
1457 operands[5] = GEN_INT (-2147483647 - 1);
1458 }")
1460 (define_insn ""
1461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1462 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1463 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1464 (const_int 0)
1465 (minus:SI (match_dup 2) (match_dup 1))))]
1466 "TARGET_POWER"
1467 "doz%I2 %0,%1,%2")
1469 (define_insn ""
1470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1471 (compare:CC
1472 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1473 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1474 (const_int 0)
1475 (minus:SI (match_dup 2) (match_dup 1)))
1476 (const_int 0)))
1477 (clobber (match_scratch:SI 3 "=r,r"))]
1478 "TARGET_POWER"
1479 "@
1480 doz%I2. %3,%1,%2
1481 #"
1482 [(set_attr "type" "delayed_compare")
1483 (set_attr "length" "4,8")])
1485 (define_split
1486 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1487 (compare:CC
1488 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1489 (match_operand:SI 2 "reg_or_short_operand" ""))
1490 (const_int 0)
1491 (minus:SI (match_dup 2) (match_dup 1)))
1492 (const_int 0)))
1493 (clobber (match_scratch:SI 3 ""))]
1494 "TARGET_POWER && reload_completed"
1495 [(set (match_dup 3)
1496 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1497 (const_int 0)
1498 (minus:SI (match_dup 2) (match_dup 1))))
1499 (set (match_dup 0)
1500 (compare:CC (match_dup 3)
1501 (const_int 0)))]
1502 "")
1504 (define_insn ""
1505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1506 (compare:CC
1507 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1508 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1509 (const_int 0)
1510 (minus:SI (match_dup 2) (match_dup 1)))
1511 (const_int 0)))
1512 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1513 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1514 (const_int 0)
1515 (minus:SI (match_dup 2) (match_dup 1))))]
1516 "TARGET_POWER"
1517 "@
1518 doz%I2. %0,%1,%2
1519 #"
1520 [(set_attr "type" "delayed_compare")
1521 (set_attr "length" "4,8")])
1523 (define_split
1524 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1525 (compare:CC
1526 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1527 (match_operand:SI 2 "reg_or_short_operand" ""))
1528 (const_int 0)
1529 (minus:SI (match_dup 2) (match_dup 1)))
1530 (const_int 0)))
1531 (set (match_operand:SI 0 "gpc_reg_operand" "")
1532 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1533 (const_int 0)
1534 (minus:SI (match_dup 2) (match_dup 1))))]
1535 "TARGET_POWER && reload_completed"
1536 [(set (match_dup 0)
1537 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1538 (const_int 0)
1539 (minus:SI (match_dup 2) (match_dup 1))))
1540 (set (match_dup 3)
1541 (compare:CC (match_dup 0)
1542 (const_int 0)))]
1543 "")
1545 ;; We don't need abs with condition code because such comparisons should
1546 ;; never be done.
1547 (define_expand "abssi2"
1548 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1549 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1550 ""
1551 "
1552 {
1553 if (TARGET_ISEL)
1554 {
1555 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1556 DONE;
1557 }
1558 else if (! TARGET_POWER)
1559 {
1560 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1561 DONE;
1562 }
1563 }")
1565 (define_insn "*abssi2_power"
1566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1567 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1568 "TARGET_POWER"
1569 "abs %0,%1")
1571 (define_insn_and_split "abssi2_isel"
1572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1573 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1574 (clobber (match_scratch:SI 2 "=&b"))
1575 (clobber (match_scratch:CC 3 "=y"))]
1576 "TARGET_ISEL"
1577 "#"
1578 "&& reload_completed"
1579 [(set (match_dup 2) (neg:SI (match_dup 1)))
1580 (set (match_dup 3)
1581 (compare:CC (match_dup 1)
1582 (const_int 0)))
1583 (set (match_dup 0)
1584 (if_then_else:SI (ge (match_dup 3)
1585 (const_int 0))
1586 (match_dup 1)
1587 (match_dup 2)))]
1588 "")
1590 (define_insn_and_split "abssi2_nopower"
1591 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1592 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1593 (clobber (match_scratch:SI 2 "=&r,&r"))]
1594 "! TARGET_POWER && ! TARGET_ISEL"
1595 "#"
1596 "&& reload_completed"
1597 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1598 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1599 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1600 "")
1602 (define_insn "*nabs_power"
1603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1604 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1605 "TARGET_POWER"
1606 "nabs %0,%1")
1608 (define_insn_and_split "*nabs_nopower"
1609 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1610 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1611 (clobber (match_scratch:SI 2 "=&r,&r"))]
1612 "! TARGET_POWER"
1613 "#"
1614 "&& reload_completed"
1615 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1616 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1617 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1618 "")
1620 (define_expand "neg<mode>2"
1621 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1622 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1623 ""
1624 "")
1626 (define_insn "*neg<mode>2_internal"
1627 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1628 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1629 ""
1630 "neg %0,%1")
1632 (define_insn ""
1633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1634 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1635 (const_int 0)))
1636 (clobber (match_scratch:P 2 "=r,r"))]
1637 ""
1638 "@
1639 neg. %2,%1
1640 #"
1641 [(set_attr "type" "fast_compare")
1642 (set_attr "length" "4,8")])
1644 (define_split
1645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1646 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1647 (const_int 0)))
1648 (clobber (match_scratch:P 2 ""))]
1649 "reload_completed"
1650 [(set (match_dup 2)
1651 (neg:P (match_dup 1)))
1652 (set (match_dup 0)
1653 (compare:CC (match_dup 2)
1654 (const_int 0)))]
1655 "")
1657 (define_insn ""
1658 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1659 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1660 (const_int 0)))
1661 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1662 (neg:P (match_dup 1)))]
1663 ""
1664 "@
1665 neg. %0,%1
1666 #"
1667 [(set_attr "type" "fast_compare")
1668 (set_attr "length" "4,8")])
1670 (define_split
1671 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1672 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1673 (const_int 0)))
1674 (set (match_operand:P 0 "gpc_reg_operand" "")
1675 (neg:P (match_dup 1)))]
1676 "reload_completed"
1677 [(set (match_dup 0)
1678 (neg:P (match_dup 1)))
1679 (set (match_dup 2)
1680 (compare:CC (match_dup 0)
1681 (const_int 0)))]
1682 "")
1684 (define_insn "clz<mode>2"
1685 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1686 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1687 ""
1688 "{cntlz|cntlz<wd>} %0,%1")
1690 (define_expand "ctz<mode>2"
1691 [(set (match_dup 2)
1692 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1693 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1694 (match_dup 2)))
1695 (clobber (scratch:CC))])
1696 (set (match_dup 4) (clz:GPR (match_dup 3)))
1697 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1698 (minus:GPR (match_dup 5) (match_dup 4)))]
1699 ""
1700 {
1701 operands[2] = gen_reg_rtx (<MODE>mode);
1702 operands[3] = gen_reg_rtx (<MODE>mode);
1703 operands[4] = gen_reg_rtx (<MODE>mode);
1704 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1705 })
1707 (define_expand "ffs<mode>2"
1708 [(set (match_dup 2)
1709 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1710 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1711 (match_dup 2)))
1712 (clobber (scratch:CC))])
1713 (set (match_dup 4) (clz:GPR (match_dup 3)))
1714 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1715 (minus:GPR (match_dup 5) (match_dup 4)))]
1716 ""
1717 {
1718 operands[2] = gen_reg_rtx (<MODE>mode);
1719 operands[3] = gen_reg_rtx (<MODE>mode);
1720 operands[4] = gen_reg_rtx (<MODE>mode);
1721 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1722 })
1724 (define_expand "popcount<mode>2"
1725 [(set (match_dup 2)
1726 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1727 UNSPEC_POPCNTB))
1728 (set (match_dup 3)
1729 (mult:GPR (match_dup 2) (match_dup 4)))
1730 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1731 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1732 "TARGET_POPCNTB"
1733 {
1734 operands[2] = gen_reg_rtx (<MODE>mode);
1735 operands[3] = gen_reg_rtx (<MODE>mode);
1736 operands[4] = force_reg (<MODE>mode,
1737 <MODE>mode == SImode
1738 ? GEN_INT (0x01010101)
1739 : GEN_INT ((HOST_WIDE_INT)
1740 0x01010101 << 32 | 0x01010101));
1741 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1742 })
1744 (define_insn "popcntb<mode>2"
1745 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1746 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1747 UNSPEC_POPCNTB))]
1748 "TARGET_POPCNTB"
1749 "popcntb %0,%1")
1751 (define_expand "mulsi3"
1752 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1753 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1754 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1755 ""
1756 "
1757 {
1758 if (TARGET_POWER)
1759 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1760 else
1761 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1762 DONE;
1763 }")
1765 (define_insn "mulsi3_mq"
1766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1768 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1769 (clobber (match_scratch:SI 3 "=q,q"))]
1770 "TARGET_POWER"
1771 "@
1772 {muls|mullw} %0,%1,%2
1773 {muli|mulli} %0,%1,%2"
1774 [(set (attr "type")
1775 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1776 (const_string "imul3")
1777 (match_operand:SI 2 "short_cint_operand" "")
1778 (const_string "imul2")]
1779 (const_string "imul")))])
1781 (define_insn "mulsi3_no_mq"
1782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1783 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1784 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1785 "! TARGET_POWER"
1786 "@
1787 {muls|mullw} %0,%1,%2
1788 {muli|mulli} %0,%1,%2"
1789 [(set (attr "type")
1790 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1791 (const_string "imul3")
1792 (match_operand:SI 2 "short_cint_operand" "")
1793 (const_string "imul2")]
1794 (const_string "imul")))])
1796 (define_insn "*mulsi3_mq_internal1"
1797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1798 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1799 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1800 (const_int 0)))
1801 (clobber (match_scratch:SI 3 "=r,r"))
1802 (clobber (match_scratch:SI 4 "=q,q"))]
1803 "TARGET_POWER"
1804 "@
1805 {muls.|mullw.} %3,%1,%2
1806 #"
1807 [(set_attr "type" "imul_compare")
1808 (set_attr "length" "4,8")])
1810 (define_split
1811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1812 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1813 (match_operand:SI 2 "gpc_reg_operand" ""))
1814 (const_int 0)))
1815 (clobber (match_scratch:SI 3 ""))
1816 (clobber (match_scratch:SI 4 ""))]
1817 "TARGET_POWER && reload_completed"
1818 [(parallel [(set (match_dup 3)
1819 (mult:SI (match_dup 1) (match_dup 2)))
1820 (clobber (match_dup 4))])
1821 (set (match_dup 0)
1822 (compare:CC (match_dup 3)
1823 (const_int 0)))]
1824 "")
1826 (define_insn "*mulsi3_no_mq_internal1"
1827 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1828 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1829 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1830 (const_int 0)))
1831 (clobber (match_scratch:SI 3 "=r,r"))]
1832 "! TARGET_POWER"
1833 "@
1834 {muls.|mullw.} %3,%1,%2
1835 #"
1836 [(set_attr "type" "imul_compare")
1837 (set_attr "length" "4,8")])
1839 (define_split
1840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1841 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "gpc_reg_operand" ""))
1843 (const_int 0)))
1844 (clobber (match_scratch:SI 3 ""))]
1845 "! TARGET_POWER && reload_completed"
1846 [(set (match_dup 3)
1847 (mult:SI (match_dup 1) (match_dup 2)))
1848 (set (match_dup 0)
1849 (compare:CC (match_dup 3)
1850 (const_int 0)))]
1851 "")
1853 (define_insn "*mulsi3_mq_internal2"
1854 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1855 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1856 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1857 (const_int 0)))
1858 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1859 (mult:SI (match_dup 1) (match_dup 2)))
1860 (clobber (match_scratch:SI 4 "=q,q"))]
1861 "TARGET_POWER"
1862 "@
1863 {muls.|mullw.} %0,%1,%2
1864 #"
1865 [(set_attr "type" "imul_compare")
1866 (set_attr "length" "4,8")])
1868 (define_split
1869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1870 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1871 (match_operand:SI 2 "gpc_reg_operand" ""))
1872 (const_int 0)))
1873 (set (match_operand:SI 0 "gpc_reg_operand" "")
1874 (mult:SI (match_dup 1) (match_dup 2)))
1875 (clobber (match_scratch:SI 4 ""))]
1876 "TARGET_POWER && reload_completed"
1877 [(parallel [(set (match_dup 0)
1878 (mult:SI (match_dup 1) (match_dup 2)))
1879 (clobber (match_dup 4))])
1880 (set (match_dup 3)
1881 (compare:CC (match_dup 0)
1882 (const_int 0)))]
1883 "")
1885 (define_insn "*mulsi3_no_mq_internal2"
1886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1887 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1888 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1889 (const_int 0)))
1890 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1891 (mult:SI (match_dup 1) (match_dup 2)))]
1892 "! TARGET_POWER"
1893 "@
1894 {muls.|mullw.} %0,%1,%2
1895 #"
1896 [(set_attr "type" "imul_compare")
1897 (set_attr "length" "4,8")])
1899 (define_split
1900 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1901 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1902 (match_operand:SI 2 "gpc_reg_operand" ""))
1903 (const_int 0)))
1904 (set (match_operand:SI 0 "gpc_reg_operand" "")
1905 (mult:SI (match_dup 1) (match_dup 2)))]
1906 "! TARGET_POWER && reload_completed"
1907 [(set (match_dup 0)
1908 (mult:SI (match_dup 1) (match_dup 2)))
1909 (set (match_dup 3)
1910 (compare:CC (match_dup 0)
1911 (const_int 0)))]
1912 "")
1914 ;; Operand 1 is divided by operand 2; quotient goes to operand
1915 ;; 0 and remainder to operand 3.
1916 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1918 (define_expand "divmodsi4"
1919 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1920 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1921 (match_operand:SI 2 "gpc_reg_operand" "")))
1922 (set (match_operand:SI 3 "register_operand" "")
1923 (mod:SI (match_dup 1) (match_dup 2)))])]
1924 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1925 "
1926 {
1927 if (! TARGET_POWER && ! TARGET_POWERPC)
1928 {
1929 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1930 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1931 emit_insn (gen_divss_call ());
1932 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1933 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1934 DONE;
1935 }
1936 }")
1938 (define_insn "*divmodsi4_internal"
1939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1940 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1941 (match_operand:SI 2 "gpc_reg_operand" "r")))
1942 (set (match_operand:SI 3 "register_operand" "=q")
1943 (mod:SI (match_dup 1) (match_dup 2)))]
1944 "TARGET_POWER"
1945 "divs %0,%1,%2"
1946 [(set_attr "type" "idiv")])
1948 (define_expand "udiv<mode>3"
1949 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1950 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1951 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1952 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1953 "
1954 {
1955 if (! TARGET_POWER && ! TARGET_POWERPC)
1956 {
1957 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1958 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1959 emit_insn (gen_quous_call ());
1960 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1961 DONE;
1962 }
1963 else if (TARGET_POWER)
1964 {
1965 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1966 DONE;
1967 }
1968 }")
1970 (define_insn "udivsi3_mq"
1971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1972 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1973 (match_operand:SI 2 "gpc_reg_operand" "r")))
1974 (clobber (match_scratch:SI 3 "=q"))]
1975 "TARGET_POWERPC && TARGET_POWER"
1976 "divwu %0,%1,%2"
1977 [(set_attr "type" "idiv")])
1979 (define_insn "*udivsi3_no_mq"
1980 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1981 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1982 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1983 "TARGET_POWERPC && ! TARGET_POWER"
1984 "div<wd>u %0,%1,%2"
1985 [(set_attr "type" "idiv")])
1987 ;; For powers of two we can do srai/aze for divide and then adjust for
1988 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1989 ;; used; for PowerPC, force operands into register and do a normal divide;
1990 ;; for AIX common-mode, use quoss call on register operands.
1991 (define_expand "div<mode>3"
1992 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1993 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1994 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1995 ""
1996 "
1997 {
1998 if (GET_CODE (operands[2]) == CONST_INT
1999 && INTVAL (operands[2]) > 0
2000 && exact_log2 (INTVAL (operands[2])) >= 0)
2001 ;
2002 else if (TARGET_POWERPC)
2003 {
2004 operands[2] = force_reg (SImode, operands[2]);
2005 if (TARGET_POWER)
2006 {
2007 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2008 DONE;
2009 }
2010 }
2011 else if (TARGET_POWER)
2012 FAIL;
2013 else
2014 {
2015 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2016 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2017 emit_insn (gen_quoss_call ());
2018 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2019 DONE;
2020 }
2021 }")
2023 (define_insn "divsi3_mq"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2025 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2026 (match_operand:SI 2 "gpc_reg_operand" "r")))
2027 (clobber (match_scratch:SI 3 "=q"))]
2028 "TARGET_POWERPC && TARGET_POWER"
2029 "divw %0,%1,%2"
2030 [(set_attr "type" "idiv")])
2032 (define_insn "*div<mode>3_no_mq"
2033 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2034 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2035 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2036 "TARGET_POWERPC && ! TARGET_POWER"
2037 "div<wd> %0,%1,%2"
2038 [(set_attr "type" "idiv")])
2040 (define_expand "mod<mode>3"
2041 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2042 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2043 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2044 ""
2045 "
2046 {
2047 int i;
2048 rtx temp1;
2049 rtx temp2;
2051 if (GET_CODE (operands[2]) != CONST_INT
2052 || INTVAL (operands[2]) <= 0
2053 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2054 FAIL;
2056 temp1 = gen_reg_rtx (<MODE>mode);
2057 temp2 = gen_reg_rtx (<MODE>mode);
2059 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2060 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2061 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2062 DONE;
2063 }")
2065 (define_insn ""
2066 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2067 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2068 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2069 ""
2070 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2071 [(set_attr "type" "two")
2072 (set_attr "length" "8")])
2074 (define_insn ""
2075 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2076 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2077 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2078 (const_int 0)))
2079 (clobber (match_scratch:P 3 "=r,r"))]
2080 ""
2081 "@
2082 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2083 #"
2084 [(set_attr "type" "compare")
2085 (set_attr "length" "8,12")])
2087 (define_split
2088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2089 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2090 (match_operand:GPR 2 "exact_log2_cint_operand"
2091 ""))
2092 (const_int 0)))
2093 (clobber (match_scratch:GPR 3 ""))]
2094 "reload_completed"
2095 [(set (match_dup 3)
2096 (div:<MODE> (match_dup 1) (match_dup 2)))
2097 (set (match_dup 0)
2098 (compare:CC (match_dup 3)
2099 (const_int 0)))]
2100 "")
2102 (define_insn ""
2103 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2104 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2105 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2106 (const_int 0)))
2107 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2108 (div:P (match_dup 1) (match_dup 2)))]
2109 ""
2110 "@
2111 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2112 #"
2113 [(set_attr "type" "compare")
2114 (set_attr "length" "8,12")])
2116 (define_split
2117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2118 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2119 (match_operand:GPR 2 "exact_log2_cint_operand"
2120 ""))
2121 (const_int 0)))
2122 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2123 (div:GPR (match_dup 1) (match_dup 2)))]
2124 "reload_completed"
2125 [(set (match_dup 0)
2126 (div:<MODE> (match_dup 1) (match_dup 2)))
2127 (set (match_dup 3)
2128 (compare:CC (match_dup 0)
2129 (const_int 0)))]
2130 "")
2132 (define_insn ""
2133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2134 (udiv:SI
2135 (plus:DI (ashift:DI
2136 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2137 (const_int 32))
2138 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2139 (match_operand:SI 3 "gpc_reg_operand" "r")))
2140 (set (match_operand:SI 2 "register_operand" "=*q")
2141 (umod:SI
2142 (plus:DI (ashift:DI
2143 (zero_extend:DI (match_dup 1)) (const_int 32))
2144 (zero_extend:DI (match_dup 4)))
2145 (match_dup 3)))]
2146 "TARGET_POWER"
2147 "div %0,%1,%3"
2148 [(set_attr "type" "idiv")])
2150 ;; To do unsigned divide we handle the cases of the divisor looking like a
2151 ;; negative number. If it is a constant that is less than 2**31, we don't
2152 ;; have to worry about the branches. So make a few subroutines here.
2153 ;;
2154 ;; First comes the normal case.
2155 (define_expand "udivmodsi4_normal"
2156 [(set (match_dup 4) (const_int 0))
2157 (parallel [(set (match_operand:SI 0 "" "")
2158 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2159 (const_int 32))
2160 (zero_extend:DI (match_operand:SI 1 "" "")))
2161 (match_operand:SI 2 "" "")))
2162 (set (match_operand:SI 3 "" "")
2163 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2164 (const_int 32))
2165 (zero_extend:DI (match_dup 1)))
2166 (match_dup 2)))])]
2167 "TARGET_POWER"
2168 "
2169 { operands[4] = gen_reg_rtx (SImode); }")
2171 ;; This handles the branches.
2172 (define_expand "udivmodsi4_tests"
2173 [(set (match_operand:SI 0 "" "") (const_int 0))
2174 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2175 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2176 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2177 (label_ref (match_operand:SI 4 "" "")) (pc)))
2178 (set (match_dup 0) (const_int 1))
2179 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2180 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2181 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2182 (label_ref (match_dup 4)) (pc)))]
2183 "TARGET_POWER"
2184 "
2185 { operands[5] = gen_reg_rtx (CCUNSmode);
2186 operands[6] = gen_reg_rtx (CCmode);
2187 }")
2189 (define_expand "udivmodsi4"
2190 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2191 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2192 (match_operand:SI 2 "reg_or_cint_operand" "")))
2193 (set (match_operand:SI 3 "gpc_reg_operand" "")
2194 (umod:SI (match_dup 1) (match_dup 2)))])]
2195 ""
2196 "
2197 {
2198 rtx label = 0;
2200 if (! TARGET_POWER)
2201 {
2202 if (! TARGET_POWERPC)
2203 {
2204 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2205 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2206 emit_insn (gen_divus_call ());
2207 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2208 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2209 DONE;
2210 }
2211 else
2212 FAIL;
2213 }
2215 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2216 {
2217 operands[2] = force_reg (SImode, operands[2]);
2218 label = gen_label_rtx ();
2219 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2220 operands[3], label));
2221 }
2222 else
2223 operands[2] = force_reg (SImode, operands[2]);
2225 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2226 operands[3]));
2227 if (label)
2228 emit_label (label);
2230 DONE;
2231 }")
2233 ;; AIX architecture-independent common-mode multiply (DImode),
2234 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2235 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2236 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2237 ;; assumed unused if generating common-mode, so ignore.
2238 (define_insn "mulh_call"
2239 [(set (reg:SI 3)
2240 (truncate:SI
2241 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2242 (sign_extend:DI (reg:SI 4)))
2243 (const_int 32))))
2244 (clobber (match_scratch:SI 0 "=l"))]
2245 "! TARGET_POWER && ! TARGET_POWERPC"
2246 "bla __mulh"
2247 [(set_attr "type" "imul")])
2249 (define_insn "mull_call"
2250 [(set (reg:DI 3)
2251 (mult:DI (sign_extend:DI (reg:SI 3))
2252 (sign_extend:DI (reg:SI 4))))
2253 (clobber (match_scratch:SI 0 "=l"))
2254 (clobber (reg:SI 0))]
2255 "! TARGET_POWER && ! TARGET_POWERPC"
2256 "bla __mull"
2257 [(set_attr "type" "imul")])
2259 (define_insn "divss_call"
2260 [(set (reg:SI 3)
2261 (div:SI (reg:SI 3) (reg:SI 4)))
2262 (set (reg:SI 4)
2263 (mod:SI (reg:SI 3) (reg:SI 4)))
2264 (clobber (match_scratch:SI 0 "=l"))
2265 (clobber (reg:SI 0))]
2266 "! TARGET_POWER && ! TARGET_POWERPC"
2267 "bla __divss"
2268 [(set_attr "type" "idiv")])
2270 (define_insn "divus_call"
2271 [(set (reg:SI 3)
2272 (udiv:SI (reg:SI 3) (reg:SI 4)))
2273 (set (reg:SI 4)
2274 (umod:SI (reg:SI 3) (reg:SI 4)))
2275 (clobber (match_scratch:SI 0 "=l"))
2276 (clobber (reg:SI 0))
2277 (clobber (match_scratch:CC 1 "=x"))
2278 (clobber (reg:CC 69))]
2279 "! TARGET_POWER && ! TARGET_POWERPC"
2280 "bla __divus"
2281 [(set_attr "type" "idiv")])
2283 (define_insn "quoss_call"
2284 [(set (reg:SI 3)
2285 (div:SI (reg:SI 3) (reg:SI 4)))
2286 (clobber (match_scratch:SI 0 "=l"))]
2287 "! TARGET_POWER && ! TARGET_POWERPC"
2288 "bla __quoss"
2289 [(set_attr "type" "idiv")])
2291 (define_insn "quous_call"
2292 [(set (reg:SI 3)
2293 (udiv:SI (reg:SI 3) (reg:SI 4)))
2294 (clobber (match_scratch:SI 0 "=l"))
2295 (clobber (reg:SI 0))
2296 (clobber (match_scratch:CC 1 "=x"))
2297 (clobber (reg:CC 69))]
2298 "! TARGET_POWER && ! TARGET_POWERPC"
2299 "bla __quous"
2300 [(set_attr "type" "idiv")])
2301 \f
2302 ;; Logical instructions
2303 ;; The logical instructions are mostly combined by using match_operator,
2304 ;; but the plain AND insns are somewhat different because there is no
2305 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2306 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2308 (define_insn "andsi3"
2309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2310 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2311 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2312 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2313 ""
2314 "@
2315 and %0,%1,%2
2316 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2317 {andil.|andi.} %0,%1,%b2
2318 {andiu.|andis.} %0,%1,%u2"
2319 [(set_attr "type" "*,*,compare,compare")])
2321 ;; Note to set cr's other than cr0 we do the and immediate and then
2322 ;; the test again -- this avoids a mfcr which on the higher end
2323 ;; machines causes an execution serialization
2325 (define_insn "*andsi3_internal2"
2326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2327 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2328 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2329 (const_int 0)))
2330 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2332 "TARGET_32BIT"
2333 "@
2334 and. %3,%1,%2
2335 {andil.|andi.} %3,%1,%b2
2336 {andiu.|andis.} %3,%1,%u2
2337 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2338 #
2339 #
2340 #
2341 #"
2342 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2343 (set_attr "length" "4,4,4,4,8,8,8,8")])
2345 (define_insn "*andsi3_internal3"
2346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2348 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2349 (const_int 0)))
2350 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2351 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2352 "TARGET_64BIT"
2353 "@
2354 #
2355 {andil.|andi.} %3,%1,%b2
2356 {andiu.|andis.} %3,%1,%u2
2357 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2358 #
2359 #
2360 #
2361 #"
2362 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2363 (set_attr "length" "8,4,4,4,8,8,8,8")])
2365 (define_split
2366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2367 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2368 (match_operand:GPR 2 "and_operand" ""))
2369 (const_int 0)))
2370 (clobber (match_scratch:GPR 3 ""))
2371 (clobber (match_scratch:CC 4 ""))]
2372 "reload_completed"
2373 [(parallel [(set (match_dup 3)
2374 (and:<MODE> (match_dup 1)
2375 (match_dup 2)))
2376 (clobber (match_dup 4))])
2377 (set (match_dup 0)
2378 (compare:CC (match_dup 3)
2379 (const_int 0)))]
2380 "")
2382 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2383 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2385 (define_split
2386 [(set (match_operand:CC 0 "cc_reg_operand" "")
2387 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2388 (match_operand:SI 2 "gpc_reg_operand" ""))
2389 (const_int 0)))
2390 (clobber (match_scratch:SI 3 ""))
2391 (clobber (match_scratch:CC 4 ""))]
2392 "TARGET_POWERPC64 && reload_completed"
2393 [(parallel [(set (match_dup 3)
2394 (and:SI (match_dup 1)
2395 (match_dup 2)))
2396 (clobber (match_dup 4))])
2397 (set (match_dup 0)
2398 (compare:CC (match_dup 3)
2399 (const_int 0)))]
2400 "")
2402 (define_insn "*andsi3_internal4"
2403 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2404 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2405 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2406 (const_int 0)))
2407 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2408 (and:SI (match_dup 1)
2409 (match_dup 2)))
2410 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2411 "TARGET_32BIT"
2412 "@
2413 and. %0,%1,%2
2414 {andil.|andi.} %0,%1,%b2
2415 {andiu.|andis.} %0,%1,%u2
2416 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2417 #
2418 #
2419 #
2420 #"
2421 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2422 (set_attr "length" "4,4,4,4,8,8,8,8")])
2424 (define_insn "*andsi3_internal5"
2425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2426 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2427 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2428 (const_int 0)))
2429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2430 (and:SI (match_dup 1)
2431 (match_dup 2)))
2432 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2433 "TARGET_64BIT"
2434 "@
2435 #
2436 {andil.|andi.} %0,%1,%b2
2437 {andiu.|andis.} %0,%1,%u2
2438 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2439 #
2440 #
2441 #
2442 #"
2443 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2444 (set_attr "length" "8,4,4,4,8,8,8,8")])
2446 (define_split
2447 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2448 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2449 (match_operand:SI 2 "and_operand" ""))
2450 (const_int 0)))
2451 (set (match_operand:SI 0 "gpc_reg_operand" "")
2452 (and:SI (match_dup 1)
2453 (match_dup 2)))
2454 (clobber (match_scratch:CC 4 ""))]
2455 "reload_completed"
2456 [(parallel [(set (match_dup 0)
2457 (and:SI (match_dup 1)
2458 (match_dup 2)))
2459 (clobber (match_dup 4))])
2460 (set (match_dup 3)
2461 (compare:CC (match_dup 0)
2462 (const_int 0)))]
2463 "")
2465 (define_split
2466 [(set (match_operand:CC 3 "cc_reg_operand" "")
2467 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2468 (match_operand:SI 2 "gpc_reg_operand" ""))
2469 (const_int 0)))
2470 (set (match_operand:SI 0 "gpc_reg_operand" "")
2471 (and:SI (match_dup 1)
2472 (match_dup 2)))
2473 (clobber (match_scratch:CC 4 ""))]
2474 "TARGET_POWERPC64 && reload_completed"
2475 [(parallel [(set (match_dup 0)
2476 (and:SI (match_dup 1)
2477 (match_dup 2)))
2478 (clobber (match_dup 4))])
2479 (set (match_dup 3)
2480 (compare:CC (match_dup 0)
2481 (const_int 0)))]
2482 "")
2484 ;; Handle the PowerPC64 rlwinm corner case
2486 (define_insn_and_split "*andsi3_internal6"
2487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2488 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2489 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2490 "TARGET_POWERPC64"
2491 "#"
2492 "TARGET_POWERPC64"
2493 [(set (match_dup 0)
2494 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2495 (match_dup 4)))
2496 (set (match_dup 0)
2497 (rotate:SI (match_dup 0) (match_dup 5)))]
2498 "
2499 {
2500 int mb = extract_MB (operands[2]);
2501 int me = extract_ME (operands[2]);
2502 operands[3] = GEN_INT (me + 1);
2503 operands[5] = GEN_INT (32 - (me + 1));
2504 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2505 }"
2506 [(set_attr "length" "8")])
2508 (define_expand "iorsi3"
2509 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2510 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2511 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2512 ""
2513 "
2514 {
2515 if (GET_CODE (operands[2]) == CONST_INT
2516 && ! logical_operand (operands[2], SImode))
2517 {
2518 HOST_WIDE_INT value = INTVAL (operands[2]);
2519 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2520 ? operands[0] : gen_reg_rtx (SImode));
2522 emit_insn (gen_iorsi3 (tmp, operands[1],
2523 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2524 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2525 DONE;
2526 }
2527 }")
2529 (define_expand "xorsi3"
2530 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2531 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2532 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2533 ""
2534 "
2535 {
2536 if (GET_CODE (operands[2]) == CONST_INT
2537 && ! logical_operand (operands[2], SImode))
2538 {
2539 HOST_WIDE_INT value = INTVAL (operands[2]);
2540 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2541 ? operands[0] : gen_reg_rtx (SImode));
2543 emit_insn (gen_xorsi3 (tmp, operands[1],
2544 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2545 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2546 DONE;
2547 }
2548 }")
2550 (define_insn "*boolsi3_internal1"
2551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2552 (match_operator:SI 3 "boolean_or_operator"
2553 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2554 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2555 ""
2556 "@
2557 %q3 %0,%1,%2
2558 {%q3il|%q3i} %0,%1,%b2
2559 {%q3iu|%q3is} %0,%1,%u2")
2561 (define_insn "*boolsi3_internal2"
2562 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2563 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2564 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2565 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2566 (const_int 0)))
2567 (clobber (match_scratch:SI 3 "=r,r"))]
2568 "TARGET_32BIT"
2569 "@
2570 %q4. %3,%1,%2
2571 #"
2572 [(set_attr "type" "compare")
2573 (set_attr "length" "4,8")])
2575 (define_split
2576 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2577 (compare:CC (match_operator:SI 4 "boolean_operator"
2578 [(match_operand:SI 1 "gpc_reg_operand" "")
2579 (match_operand:SI 2 "gpc_reg_operand" "")])
2580 (const_int 0)))
2581 (clobber (match_scratch:SI 3 ""))]
2582 "TARGET_32BIT && reload_completed"
2583 [(set (match_dup 3) (match_dup 4))
2584 (set (match_dup 0)
2585 (compare:CC (match_dup 3)
2586 (const_int 0)))]
2587 "")
2589 (define_insn "*boolsi3_internal3"
2590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2591 (compare:CC (match_operator:SI 4 "boolean_operator"
2592 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2593 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2594 (const_int 0)))
2595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2596 (match_dup 4))]
2597 "TARGET_32BIT"
2598 "@
2599 %q4. %0,%1,%2
2600 #"
2601 [(set_attr "type" "compare")
2602 (set_attr "length" "4,8")])
2604 (define_split
2605 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2606 (compare:CC (match_operator:SI 4 "boolean_operator"
2607 [(match_operand:SI 1 "gpc_reg_operand" "")
2608 (match_operand:SI 2 "gpc_reg_operand" "")])
2609 (const_int 0)))
2610 (set (match_operand:SI 0 "gpc_reg_operand" "")
2611 (match_dup 4))]
2612 "TARGET_32BIT && reload_completed"
2613 [(set (match_dup 0) (match_dup 4))
2614 (set (match_dup 3)
2615 (compare:CC (match_dup 0)
2616 (const_int 0)))]
2617 "")
2619 ;; Split a logical operation that we can't do in one insn into two insns,
2620 ;; each of which does one 16-bit part. This is used by combine.
2622 (define_split
2623 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2624 (match_operator:SI 3 "boolean_or_operator"
2625 [(match_operand:SI 1 "gpc_reg_operand" "")
2626 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2627 ""
2628 [(set (match_dup 0) (match_dup 4))
2629 (set (match_dup 0) (match_dup 5))]
2630 "
2631 {
2632 rtx i;
2633 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2634 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2635 operands[1], i);
2636 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2637 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2638 operands[0], i);
2639 }")
2641 (define_insn "*boolcsi3_internal1"
2642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2643 (match_operator:SI 3 "boolean_operator"
2644 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2645 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2646 ""
2647 "%q3 %0,%2,%1")
2649 (define_insn "*boolcsi3_internal2"
2650 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2651 (compare:CC (match_operator:SI 4 "boolean_operator"
2652 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2653 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2654 (const_int 0)))
2655 (clobber (match_scratch:SI 3 "=r,r"))]
2656 "TARGET_32BIT"
2657 "@
2658 %q4. %3,%2,%1
2659 #"
2660 [(set_attr "type" "compare")
2661 (set_attr "length" "4,8")])
2663 (define_split
2664 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2665 (compare:CC (match_operator:SI 4 "boolean_operator"
2666 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2667 (match_operand:SI 2 "gpc_reg_operand" "")])
2668 (const_int 0)))
2669 (clobber (match_scratch:SI 3 ""))]
2670 "TARGET_32BIT && reload_completed"
2671 [(set (match_dup 3) (match_dup 4))
2672 (set (match_dup 0)
2673 (compare:CC (match_dup 3)
2674 (const_int 0)))]
2675 "")
2677 (define_insn "*boolcsi3_internal3"
2678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2679 (compare:CC (match_operator:SI 4 "boolean_operator"
2680 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2681 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2682 (const_int 0)))
2683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2684 (match_dup 4))]
2685 "TARGET_32BIT"
2686 "@
2687 %q4. %0,%2,%1
2688 #"
2689 [(set_attr "type" "compare")
2690 (set_attr "length" "4,8")])
2692 (define_split
2693 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2694 (compare:CC (match_operator:SI 4 "boolean_operator"
2695 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2696 (match_operand:SI 2 "gpc_reg_operand" "")])
2697 (const_int 0)))
2698 (set (match_operand:SI 0 "gpc_reg_operand" "")
2699 (match_dup 4))]
2700 "TARGET_32BIT && reload_completed"
2701 [(set (match_dup 0) (match_dup 4))
2702 (set (match_dup 3)
2703 (compare:CC (match_dup 0)
2704 (const_int 0)))]
2705 "")
2707 (define_insn "*boolccsi3_internal1"
2708 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2709 (match_operator:SI 3 "boolean_operator"
2710 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2711 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2712 ""
2713 "%q3 %0,%1,%2")
2715 (define_insn "*boolccsi3_internal2"
2716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2717 (compare:CC (match_operator:SI 4 "boolean_operator"
2718 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2719 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2720 (const_int 0)))
2721 (clobber (match_scratch:SI 3 "=r,r"))]
2722 "TARGET_32BIT"
2723 "@
2724 %q4. %3,%1,%2
2725 #"
2726 [(set_attr "type" "compare")
2727 (set_attr "length" "4,8")])
2729 (define_split
2730 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2731 (compare:CC (match_operator:SI 4 "boolean_operator"
2732 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2733 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2734 (const_int 0)))
2735 (clobber (match_scratch:SI 3 ""))]
2736 "TARGET_32BIT && reload_completed"
2737 [(set (match_dup 3) (match_dup 4))
2738 (set (match_dup 0)
2739 (compare:CC (match_dup 3)
2740 (const_int 0)))]
2741 "")
2743 (define_insn "*boolccsi3_internal3"
2744 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2745 (compare:CC (match_operator:SI 4 "boolean_operator"
2746 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2747 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2748 (const_int 0)))
2749 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2750 (match_dup 4))]
2751 "TARGET_32BIT"
2752 "@
2753 %q4. %0,%1,%2
2754 #"
2755 [(set_attr "type" "compare")
2756 (set_attr "length" "4,8")])
2758 (define_split
2759 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2760 (compare:CC (match_operator:SI 4 "boolean_operator"
2761 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2762 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2763 (const_int 0)))
2764 (set (match_operand:SI 0 "gpc_reg_operand" "")
2765 (match_dup 4))]
2766 "TARGET_32BIT && reload_completed"
2767 [(set (match_dup 0) (match_dup 4))
2768 (set (match_dup 3)
2769 (compare:CC (match_dup 0)
2770 (const_int 0)))]
2771 "")
2773 ;; maskir insn. We need four forms because things might be in arbitrary
2774 ;; orders. Don't define forms that only set CR fields because these
2775 ;; would modify an input register.
2777 (define_insn "*maskir_internal1"
2778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2779 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2780 (match_operand:SI 1 "gpc_reg_operand" "0"))
2781 (and:SI (match_dup 2)
2782 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2783 "TARGET_POWER"
2784 "maskir %0,%3,%2")
2786 (define_insn "*maskir_internal2"
2787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2788 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2789 (match_operand:SI 1 "gpc_reg_operand" "0"))
2790 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2791 (match_dup 2))))]
2792 "TARGET_POWER"
2793 "maskir %0,%3,%2")
2795 (define_insn "*maskir_internal3"
2796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2797 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2798 (match_operand:SI 3 "gpc_reg_operand" "r"))
2799 (and:SI (not:SI (match_dup 2))
2800 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2801 "TARGET_POWER"
2802 "maskir %0,%3,%2")
2804 (define_insn "*maskir_internal4"
2805 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2806 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2807 (match_operand:SI 2 "gpc_reg_operand" "r"))
2808 (and:SI (not:SI (match_dup 2))
2809 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2810 "TARGET_POWER"
2811 "maskir %0,%3,%2")
2813 (define_insn "*maskir_internal5"
2814 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2815 (compare:CC
2816 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2817 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2818 (and:SI (match_dup 2)
2819 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2820 (const_int 0)))
2821 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2822 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2823 (and:SI (match_dup 2) (match_dup 3))))]
2824 "TARGET_POWER"
2825 "@
2826 maskir. %0,%3,%2
2827 #"
2828 [(set_attr "type" "compare")
2829 (set_attr "length" "4,8")])
2831 (define_split
2832 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2833 (compare:CC
2834 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2835 (match_operand:SI 1 "gpc_reg_operand" ""))
2836 (and:SI (match_dup 2)
2837 (match_operand:SI 3 "gpc_reg_operand" "")))
2838 (const_int 0)))
2839 (set (match_operand:SI 0 "gpc_reg_operand" "")
2840 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2841 (and:SI (match_dup 2) (match_dup 3))))]
2842 "TARGET_POWER && reload_completed"
2843 [(set (match_dup 0)
2844 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2845 (and:SI (match_dup 2) (match_dup 3))))
2846 (set (match_dup 4)
2847 (compare:CC (match_dup 0)
2848 (const_int 0)))]
2849 "")
2851 (define_insn "*maskir_internal6"
2852 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2853 (compare:CC
2854 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2855 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2856 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2857 (match_dup 2)))
2858 (const_int 0)))
2859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2860 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2861 (and:SI (match_dup 3) (match_dup 2))))]
2862 "TARGET_POWER"
2863 "@
2864 maskir. %0,%3,%2
2865 #"
2866 [(set_attr "type" "compare")
2867 (set_attr "length" "4,8")])
2869 (define_split
2870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2871 (compare:CC
2872 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2873 (match_operand:SI 1 "gpc_reg_operand" ""))
2874 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2875 (match_dup 2)))
2876 (const_int 0)))
2877 (set (match_operand:SI 0 "gpc_reg_operand" "")
2878 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2879 (and:SI (match_dup 3) (match_dup 2))))]
2880 "TARGET_POWER && reload_completed"
2881 [(set (match_dup 0)
2882 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2883 (and:SI (match_dup 3) (match_dup 2))))
2884 (set (match_dup 4)
2885 (compare:CC (match_dup 0)
2886 (const_int 0)))]
2887 "")
2889 (define_insn "*maskir_internal7"
2890 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2891 (compare:CC
2892 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2893 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2894 (and:SI (not:SI (match_dup 2))
2895 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2896 (const_int 0)))
2897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2898 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2899 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2900 "TARGET_POWER"
2901 "@
2902 maskir. %0,%3,%2
2903 #"
2904 [(set_attr "type" "compare")
2905 (set_attr "length" "4,8")])
2907 (define_split
2908 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2909 (compare:CC
2910 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2911 (match_operand:SI 3 "gpc_reg_operand" ""))
2912 (and:SI (not:SI (match_dup 2))
2913 (match_operand:SI 1 "gpc_reg_operand" "")))
2914 (const_int 0)))
2915 (set (match_operand:SI 0 "gpc_reg_operand" "")
2916 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2917 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2918 "TARGET_POWER && reload_completed"
2919 [(set (match_dup 0)
2920 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2921 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2922 (set (match_dup 4)
2923 (compare:CC (match_dup 0)
2924 (const_int 0)))]
2925 "")
2927 (define_insn "*maskir_internal8"
2928 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2929 (compare:CC
2930 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2931 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2932 (and:SI (not:SI (match_dup 2))
2933 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2934 (const_int 0)))
2935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2936 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2937 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2938 "TARGET_POWER"
2939 "@
2940 maskir. %0,%3,%2
2941 #"
2942 [(set_attr "type" "compare")
2943 (set_attr "length" "4,8")])
2945 (define_split
2946 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2947 (compare:CC
2948 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2949 (match_operand:SI 2 "gpc_reg_operand" ""))
2950 (and:SI (not:SI (match_dup 2))
2951 (match_operand:SI 1 "gpc_reg_operand" "")))
2952 (const_int 0)))
2953 (set (match_operand:SI 0 "gpc_reg_operand" "")
2954 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2955 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2956 "TARGET_POWER && reload_completed"
2957 [(set (match_dup 0)
2958 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2959 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2960 (set (match_dup 4)
2961 (compare:CC (match_dup 0)
2962 (const_int 0)))]
2963 "")
2964 \f
2965 ;; Rotate and shift insns, in all their variants. These support shifts,
2966 ;; field inserts and extracts, and various combinations thereof.
2967 (define_expand "insv"
2968 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2969 (match_operand:SI 1 "const_int_operand" "")
2970 (match_operand:SI 2 "const_int_operand" ""))
2971 (match_operand 3 "gpc_reg_operand" ""))]
2972 ""
2973 "
2974 {
2975 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2976 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2977 compiler if the address of the structure is taken later. */
2978 if (GET_CODE (operands[0]) == SUBREG
2979 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2980 FAIL;
2982 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2983 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2984 else
2985 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2986 DONE;
2987 }")
2989 (define_insn "insvsi"
2990 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2991 (match_operand:SI 1 "const_int_operand" "i")
2992 (match_operand:SI 2 "const_int_operand" "i"))
2993 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2994 ""
2995 "*
2996 {
2997 int start = INTVAL (operands[2]) & 31;
2998 int size = INTVAL (operands[1]) & 31;
3000 operands[4] = GEN_INT (32 - start - size);
3001 operands[1] = GEN_INT (start + size - 1);
3002 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3003 }"
3004 [(set_attr "type" "insert_word")])
3006 (define_insn "*insvsi_internal1"
3007 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3008 (match_operand:SI 1 "const_int_operand" "i")
3009 (match_operand:SI 2 "const_int_operand" "i"))
3010 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3011 (match_operand:SI 4 "const_int_operand" "i")))]
3012 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3013 "*
3014 {
3015 int shift = INTVAL (operands[4]) & 31;
3016 int start = INTVAL (operands[2]) & 31;
3017 int size = INTVAL (operands[1]) & 31;
3019 operands[4] = GEN_INT (shift - start - size);
3020 operands[1] = GEN_INT (start + size - 1);
3021 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3022 }"
3023 [(set_attr "type" "insert_word")])
3025 (define_insn "*insvsi_internal2"
3026 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3027 (match_operand:SI 1 "const_int_operand" "i")
3028 (match_operand:SI 2 "const_int_operand" "i"))
3029 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3030 (match_operand:SI 4 "const_int_operand" "i")))]
3031 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3032 "*
3033 {
3034 int shift = INTVAL (operands[4]) & 31;
3035 int start = INTVAL (operands[2]) & 31;
3036 int size = INTVAL (operands[1]) & 31;
3038 operands[4] = GEN_INT (32 - shift - start - size);
3039 operands[1] = GEN_INT (start + size - 1);
3040 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3041 }"
3042 [(set_attr "type" "insert_word")])
3044 (define_insn "*insvsi_internal3"
3045 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3046 (match_operand:SI 1 "const_int_operand" "i")
3047 (match_operand:SI 2 "const_int_operand" "i"))
3048 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3049 (match_operand:SI 4 "const_int_operand" "i")))]
3050 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3051 "*
3052 {
3053 int shift = INTVAL (operands[4]) & 31;
3054 int start = INTVAL (operands[2]) & 31;
3055 int size = INTVAL (operands[1]) & 31;
3057 operands[4] = GEN_INT (32 - shift - start - size);
3058 operands[1] = GEN_INT (start + size - 1);
3059 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3060 }"
3061 [(set_attr "type" "insert_word")])
3063 (define_insn "*insvsi_internal4"
3064 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3065 (match_operand:SI 1 "const_int_operand" "i")
3066 (match_operand:SI 2 "const_int_operand" "i"))
3067 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3068 (match_operand:SI 4 "const_int_operand" "i")
3069 (match_operand:SI 5 "const_int_operand" "i")))]
3070 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3071 "*
3072 {
3073 int extract_start = INTVAL (operands[5]) & 31;
3074 int extract_size = INTVAL (operands[4]) & 31;
3075 int insert_start = INTVAL (operands[2]) & 31;
3076 int insert_size = INTVAL (operands[1]) & 31;
3078 /* Align extract field with insert field */
3079 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3080 operands[1] = GEN_INT (insert_start + insert_size - 1);
3081 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3082 }"
3083 [(set_attr "type" "insert_word")])
3085 ;; combine patterns for rlwimi
3086 (define_insn "*insvsi_internal5"
3087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3088 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3089 (match_operand:SI 1 "mask_operand" "i"))
3090 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3091 (match_operand:SI 2 "const_int_operand" "i"))
3092 (match_operand:SI 5 "mask_operand" "i"))))]
3093 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3094 "*
3095 {
3096 int me = extract_ME(operands[5]);
3097 int mb = extract_MB(operands[5]);
3098 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3099 operands[2] = GEN_INT(mb);
3100 operands[1] = GEN_INT(me);
3101 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3102 }"
3103 [(set_attr "type" "insert_word")])
3105 (define_insn "*insvsi_internal6"
3106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3107 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3108 (match_operand:SI 2 "const_int_operand" "i"))
3109 (match_operand:SI 5 "mask_operand" "i"))
3110 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3111 (match_operand:SI 1 "mask_operand" "i"))))]
3112 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3113 "*
3114 {
3115 int me = extract_ME(operands[5]);
3116 int mb = extract_MB(operands[5]);
3117 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3118 operands[2] = GEN_INT(mb);
3119 operands[1] = GEN_INT(me);
3120 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3121 }"
3122 [(set_attr "type" "insert_word")])
3124 (define_insn "insvdi"
3125 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3126 (match_operand:SI 1 "const_int_operand" "i")
3127 (match_operand:SI 2 "const_int_operand" "i"))
3128 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3129 "TARGET_POWERPC64"
3130 "*
3131 {
3132 int start = INTVAL (operands[2]) & 63;
3133 int size = INTVAL (operands[1]) & 63;
3135 operands[1] = GEN_INT (64 - start - size);
3136 return \"rldimi %0,%3,%H1,%H2\";
3137 }")
3139 (define_insn "*insvdi_internal2"
3140 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3141 (match_operand:SI 1 "const_int_operand" "i")
3142 (match_operand:SI 2 "const_int_operand" "i"))
3143 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3144 (match_operand:SI 4 "const_int_operand" "i")))]
3145 "TARGET_POWERPC64
3146 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3147 "*
3148 {
3149 int shift = INTVAL (operands[4]) & 63;
3150 int start = (INTVAL (operands[2]) & 63) - 32;
3151 int size = INTVAL (operands[1]) & 63;
3153 operands[4] = GEN_INT (64 - shift - start - size);
3154 operands[2] = GEN_INT (start);
3155 operands[1] = GEN_INT (start + size - 1);
3156 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3157 }")
3159 (define_insn "*insvdi_internal3"
3160 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3161 (match_operand:SI 1 "const_int_operand" "i")
3162 (match_operand:SI 2 "const_int_operand" "i"))
3163 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3164 (match_operand:SI 4 "const_int_operand" "i")))]
3165 "TARGET_POWERPC64
3166 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3167 "*
3168 {
3169 int shift = INTVAL (operands[4]) & 63;
3170 int start = (INTVAL (operands[2]) & 63) - 32;
3171 int size = INTVAL (operands[1]) & 63;
3173 operands[4] = GEN_INT (64 - shift - start - size);
3174 operands[2] = GEN_INT (start);
3175 operands[1] = GEN_INT (start + size - 1);
3176 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3177 }")
3179 (define_expand "extzv"
3180 [(set (match_operand 0 "gpc_reg_operand" "")
3181 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3182 (match_operand:SI 2 "const_int_operand" "")
3183 (match_operand:SI 3 "const_int_operand" "")))]
3184 ""
3185 "
3186 {
3187 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3188 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3189 compiler if the address of the structure is taken later. */
3190 if (GET_CODE (operands[0]) == SUBREG
3191 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3192 FAIL;
3194 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3195 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3196 else
3197 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3198 DONE;
3199 }")
3201 (define_insn "extzvsi"
3202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3203 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3204 (match_operand:SI 2 "const_int_operand" "i")
3205 (match_operand:SI 3 "const_int_operand" "i")))]
3206 ""
3207 "*
3208 {
3209 int start = INTVAL (operands[3]) & 31;
3210 int size = INTVAL (operands[2]) & 31;
3212 if (start + size >= 32)
3213 operands[3] = const0_rtx;
3214 else
3215 operands[3] = GEN_INT (start + size);
3216 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3217 }")
3219 (define_insn "*extzvsi_internal1"
3220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3221 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3222 (match_operand:SI 2 "const_int_operand" "i,i")
3223 (match_operand:SI 3 "const_int_operand" "i,i"))
3224 (const_int 0)))
3225 (clobber (match_scratch:SI 4 "=r,r"))]
3226 ""
3227 "*
3228 {
3229 int start = INTVAL (operands[3]) & 31;
3230 int size = INTVAL (operands[2]) & 31;
3232 /* Force split for non-cc0 compare. */
3233 if (which_alternative == 1)
3234 return \"#\";
3236 /* If the bit-field being tested fits in the upper or lower half of a
3237 word, it is possible to use andiu. or andil. to test it. This is
3238 useful because the condition register set-use delay is smaller for
3239 andi[ul]. than for rlinm. This doesn't work when the starting bit
3240 position is 0 because the LT and GT bits may be set wrong. */
3242 if ((start > 0 && start + size <= 16) || start >= 16)
3243 {
3244 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3245 - (1 << (16 - (start & 15) - size))));
3246 if (start < 16)
3247 return \"{andiu.|andis.} %4,%1,%3\";
3248 else
3249 return \"{andil.|andi.} %4,%1,%3\";
3250 }
3252 if (start + size >= 32)
3253 operands[3] = const0_rtx;
3254 else
3255 operands[3] = GEN_INT (start + size);
3256 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3257 }"
3258 [(set_attr "type" "compare")
3259 (set_attr "length" "4,8")])
3261 (define_split
3262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3263 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3264 (match_operand:SI 2 "const_int_operand" "")
3265 (match_operand:SI 3 "const_int_operand" ""))
3266 (const_int 0)))
3267 (clobber (match_scratch:SI 4 ""))]
3268 "reload_completed"
3269 [(set (match_dup 4)
3270 (zero_extract:SI (match_dup 1) (match_dup 2)
3271 (match_dup 3)))
3272 (set (match_dup 0)
3273 (compare:CC (match_dup 4)
3274 (const_int 0)))]
3275 "")
3277 (define_insn "*extzvsi_internal2"
3278 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3279 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3280 (match_operand:SI 2 "const_int_operand" "i,i")
3281 (match_operand:SI 3 "const_int_operand" "i,i"))
3282 (const_int 0)))
3283 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3284 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3285 ""
3286 "*
3287 {
3288 int start = INTVAL (operands[3]) & 31;
3289 int size = INTVAL (operands[2]) & 31;
3291 /* Force split for non-cc0 compare. */
3292 if (which_alternative == 1)
3293 return \"#\";
3295 /* Since we are using the output value, we can't ignore any need for
3296 a shift. The bit-field must end at the LSB. */
3297 if (start >= 16 && start + size == 32)
3298 {
3299 operands[3] = GEN_INT ((1 << size) - 1);
3300 return \"{andil.|andi.} %0,%1,%3\";
3301 }
3303 if (start + size >= 32)
3304 operands[3] = const0_rtx;
3305 else
3306 operands[3] = GEN_INT (start + size);
3307 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3308 }"
3309 [(set_attr "type" "compare")
3310 (set_attr "length" "4,8")])
3312 (define_split
3313 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3314 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3315 (match_operand:SI 2 "const_int_operand" "")
3316 (match_operand:SI 3 "const_int_operand" ""))
3317 (const_int 0)))
3318 (set (match_operand:SI 0 "gpc_reg_operand" "")
3319 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3320 "reload_completed"
3321 [(set (match_dup 0)
3322 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3323 (set (match_dup 4)
3324 (compare:CC (match_dup 0)
3325 (const_int 0)))]
3326 "")
3328 (define_insn "extzvdi"
3329 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3330 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3331 (match_operand:SI 2 "const_int_operand" "i")
3332 (match_operand:SI 3 "const_int_operand" "i")))]
3333 "TARGET_POWERPC64"
3334 "*
3335 {
3336 int start = INTVAL (operands[3]) & 63;
3337 int size = INTVAL (operands[2]) & 63;
3339 if (start + size >= 64)
3340 operands[3] = const0_rtx;
3341 else
3342 operands[3] = GEN_INT (start + size);
3343 operands[2] = GEN_INT (64 - size);
3344 return \"rldicl %0,%1,%3,%2\";
3345 }")
3347 (define_insn "*extzvdi_internal1"
3348 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3349 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3350 (match_operand:SI 2 "const_int_operand" "i")
3351 (match_operand:SI 3 "const_int_operand" "i"))
3352 (const_int 0)))
3353 (clobber (match_scratch:DI 4 "=r"))]
3354 "TARGET_64BIT"
3355 "*
3356 {
3357 int start = INTVAL (operands[3]) & 63;
3358 int size = INTVAL (operands[2]) & 63;
3360 if (start + size >= 64)
3361 operands[3] = const0_rtx;
3362 else
3363 operands[3] = GEN_INT (start + size);
3364 operands[2] = GEN_INT (64 - size);
3365 return \"rldicl. %4,%1,%3,%2\";
3366 }"
3367 [(set_attr "type" "compare")])
3369 (define_insn "*extzvdi_internal2"
3370 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3371 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3372 (match_operand:SI 2 "const_int_operand" "i")
3373 (match_operand:SI 3 "const_int_operand" "i"))
3374 (const_int 0)))
3375 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3376 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3377 "TARGET_64BIT"
3378 "*
3379 {
3380 int start = INTVAL (operands[3]) & 63;
3381 int size = INTVAL (operands[2]) & 63;
3383 if (start + size >= 64)
3384 operands[3] = const0_rtx;
3385 else
3386 operands[3] = GEN_INT (start + size);
3387 operands[2] = GEN_INT (64 - size);
3388 return \"rldicl. %0,%1,%3,%2\";
3389 }"
3390 [(set_attr "type" "compare")])
3392 (define_insn "rotlsi3"
3393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3394 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3395 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3396 ""
3397 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3399 (define_insn "*rotlsi3_internal2"
3400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3401 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3402 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3403 (const_int 0)))
3404 (clobber (match_scratch:SI 3 "=r,r"))]
3405 ""
3406 "@
3407 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3408 #"
3409 [(set_attr "type" "delayed_compare")
3410 (set_attr "length" "4,8")])
3412 (define_split
3413 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3414 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "reg_or_cint_operand" ""))
3416 (const_int 0)))
3417 (clobber (match_scratch:SI 3 ""))]
3418 "reload_completed"
3419 [(set (match_dup 3)
3420 (rotate:SI (match_dup 1) (match_dup 2)))
3421 (set (match_dup 0)
3422 (compare:CC (match_dup 3)
3423 (const_int 0)))]
3424 "")
3426 (define_insn "*rotlsi3_internal3"
3427 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3428 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3429 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3430 (const_int 0)))
3431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3432 (rotate:SI (match_dup 1) (match_dup 2)))]
3433 ""
3434 "@
3435 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3436 #"
3437 [(set_attr "type" "delayed_compare")
3438 (set_attr "length" "4,8")])
3440 (define_split
3441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3442 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3443 (match_operand:SI 2 "reg_or_cint_operand" ""))
3444 (const_int 0)))
3445 (set (match_operand:SI 0 "gpc_reg_operand" "")
3446 (rotate:SI (match_dup 1) (match_dup 2)))]
3447 "reload_completed"
3448 [(set (match_dup 0)
3449 (rotate:SI (match_dup 1) (match_dup 2)))
3450 (set (match_dup 3)
3451 (compare:CC (match_dup 0)
3452 (const_int 0)))]
3453 "")
3455 (define_insn "*rotlsi3_internal4"
3456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3457 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3458 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3459 (match_operand:SI 3 "mask_operand" "n")))]
3460 ""
3461 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3463 (define_insn "*rotlsi3_internal5"
3464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3465 (compare:CC (and:SI
3466 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3467 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3468 (match_operand:SI 3 "mask_operand" "n,n"))
3469 (const_int 0)))
3470 (clobber (match_scratch:SI 4 "=r,r"))]
3471 ""
3472 "@
3473 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3474 #"
3475 [(set_attr "type" "delayed_compare")
3476 (set_attr "length" "4,8")])
3478 (define_split
3479 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3480 (compare:CC (and:SI
3481 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3482 (match_operand:SI 2 "reg_or_cint_operand" ""))
3483 (match_operand:SI 3 "mask_operand" ""))
3484 (const_int 0)))
3485 (clobber (match_scratch:SI 4 ""))]
3486 "reload_completed"
3487 [(set (match_dup 4)
3488 (and:SI (rotate:SI (match_dup 1)
3489 (match_dup 2))
3490 (match_dup 3)))
3491 (set (match_dup 0)
3492 (compare:CC (match_dup 4)
3493 (const_int 0)))]
3494 "")
3496 (define_insn "*rotlsi3_internal6"
3497 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3498 (compare:CC (and:SI
3499 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3500 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3501 (match_operand:SI 3 "mask_operand" "n,n"))
3502 (const_int 0)))
3503 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3504 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3505 ""
3506 "@
3507 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3508 #"
3509 [(set_attr "type" "delayed_compare")
3510 (set_attr "length" "4,8")])
3512 (define_split
3513 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3514 (compare:CC (and:SI
3515 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3516 (match_operand:SI 2 "reg_or_cint_operand" ""))
3517 (match_operand:SI 3 "mask_operand" ""))
3518 (const_int 0)))
3519 (set (match_operand:SI 0 "gpc_reg_operand" "")
3520 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3521 "reload_completed"
3522 [(set (match_dup 0)
3523 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3524 (set (match_dup 4)
3525 (compare:CC (match_dup 0)
3526 (const_int 0)))]
3527 "")
3529 (define_insn "*rotlsi3_internal7"
3530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3531 (zero_extend:SI
3532 (subreg:QI
3533 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3534 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3535 ""
3536 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3538 (define_insn "*rotlsi3_internal8"
3539 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3540 (compare:CC (zero_extend:SI
3541 (subreg:QI
3542 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3543 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3544 (const_int 0)))
3545 (clobber (match_scratch:SI 3 "=r,r"))]
3546 ""
3547 "@
3548 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3549 #"
3550 [(set_attr "type" "delayed_compare")
3551 (set_attr "length" "4,8")])
3553 (define_split
3554 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3555 (compare:CC (zero_extend:SI
3556 (subreg:QI
3557 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3558 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3559 (const_int 0)))
3560 (clobber (match_scratch:SI 3 ""))]
3561 "reload_completed"
3562 [(set (match_dup 3)
3563 (zero_extend:SI (subreg:QI
3564 (rotate:SI (match_dup 1)
3565 (match_dup 2)) 0)))
3566 (set (match_dup 0)
3567 (compare:CC (match_dup 3)
3568 (const_int 0)))]
3569 "")
3571 (define_insn "*rotlsi3_internal9"
3572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3573 (compare:CC (zero_extend:SI
3574 (subreg:QI
3575 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3577 (const_int 0)))
3578 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3579 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3580 ""
3581 "@
3582 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3583 #"
3584 [(set_attr "type" "delayed_compare")
3585 (set_attr "length" "4,8")])
3587 (define_split
3588 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3589 (compare:CC (zero_extend:SI
3590 (subreg:QI
3591 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3592 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3593 (const_int 0)))
3594 (set (match_operand:SI 0 "gpc_reg_operand" "")
3595 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3596 "reload_completed"
3597 [(set (match_dup 0)
3598 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3599 (set (match_dup 3)
3600 (compare:CC (match_dup 0)
3601 (const_int 0)))]
3602 "")
3604 (define_insn "*rotlsi3_internal10"
3605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3606 (zero_extend:SI
3607 (subreg:HI
3608 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3609 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3610 ""
3611 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3613 (define_insn "*rotlsi3_internal11"
3614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3615 (compare:CC (zero_extend:SI
3616 (subreg:HI
3617 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3618 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3619 (const_int 0)))
3620 (clobber (match_scratch:SI 3 "=r,r"))]
3621 ""
3622 "@
3623 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3624 #"
3625 [(set_attr "type" "delayed_compare")
3626 (set_attr "length" "4,8")])
3628 (define_split
3629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3630 (compare:CC (zero_extend:SI
3631 (subreg:HI
3632 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3633 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3634 (const_int 0)))
3635 (clobber (match_scratch:SI 3 ""))]
3636 "reload_completed"
3637 [(set (match_dup 3)
3638 (zero_extend:SI (subreg:HI
3639 (rotate:SI (match_dup 1)
3640 (match_dup 2)) 0)))
3641 (set (match_dup 0)
3642 (compare:CC (match_dup 3)
3643 (const_int 0)))]
3644 "")
3646 (define_insn "*rotlsi3_internal12"
3647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3648 (compare:CC (zero_extend:SI
3649 (subreg:HI
3650 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3651 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3652 (const_int 0)))
3653 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3654 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3655 ""
3656 "@
3657 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3658 #"
3659 [(set_attr "type" "delayed_compare")
3660 (set_attr "length" "4,8")])
3662 (define_split
3663 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3664 (compare:CC (zero_extend:SI
3665 (subreg:HI
3666 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3667 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3668 (const_int 0)))
3669 (set (match_operand:SI 0 "gpc_reg_operand" "")
3670 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3671 "reload_completed"
3672 [(set (match_dup 0)
3673 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3674 (set (match_dup 3)
3675 (compare:CC (match_dup 0)
3676 (const_int 0)))]
3677 "")
3679 ;; Note that we use "sle." instead of "sl." so that we can set
3680 ;; SHIFT_COUNT_TRUNCATED.
3682 (define_expand "ashlsi3"
3683 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3684 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3685 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3686 ""
3687 "
3688 {
3689 if (TARGET_POWER)
3690 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3691 else
3692 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3693 DONE;
3694 }")
3696 (define_insn "ashlsi3_power"
3697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3698 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3699 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3700 (clobber (match_scratch:SI 3 "=q,X"))]
3701 "TARGET_POWER"
3702 "@
3703 sle %0,%1,%2
3704 {sli|slwi} %0,%1,%h2")
3706 (define_insn "ashlsi3_no_power"
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3709 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3710 "! TARGET_POWER"
3711 "{sl|slw}%I2 %0,%1,%h2")
3713 (define_insn ""
3714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3715 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3716 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3717 (const_int 0)))
3718 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3719 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3720 "TARGET_POWER"
3721 "@
3722 sle. %3,%1,%2
3723 {sli.|slwi.} %3,%1,%h2
3724 #
3725 #"
3726 [(set_attr "type" "delayed_compare")
3727 (set_attr "length" "4,4,8,8")])
3729 (define_split
3730 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3731 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3732 (match_operand:SI 2 "reg_or_cint_operand" ""))
3733 (const_int 0)))
3734 (clobber (match_scratch:SI 3 ""))
3735 (clobber (match_scratch:SI 4 ""))]
3736 "TARGET_POWER && reload_completed"
3737 [(parallel [(set (match_dup 3)
3738 (ashift:SI (match_dup 1) (match_dup 2)))
3739 (clobber (match_dup 4))])
3740 (set (match_dup 0)
3741 (compare:CC (match_dup 3)
3742 (const_int 0)))]
3743 "")
3745 (define_insn ""
3746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3747 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3748 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3749 (const_int 0)))
3750 (clobber (match_scratch:SI 3 "=r,r"))]
3751 "! TARGET_POWER && TARGET_32BIT"
3752 "@
3753 {sl|slw}%I2. %3,%1,%h2
3754 #"
3755 [(set_attr "type" "delayed_compare")
3756 (set_attr "length" "4,8")])
3758 (define_split
3759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3760 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3761 (match_operand:SI 2 "reg_or_cint_operand" ""))
3762 (const_int 0)))
3763 (clobber (match_scratch:SI 3 ""))]
3764 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3765 [(set (match_dup 3)
3766 (ashift:SI (match_dup 1) (match_dup 2)))
3767 (set (match_dup 0)
3768 (compare:CC (match_dup 3)
3769 (const_int 0)))]
3770 "")
3772 (define_insn ""
3773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3774 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3775 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3776 (const_int 0)))
3777 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3778 (ashift:SI (match_dup 1) (match_dup 2)))
3779 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3780 "TARGET_POWER"
3781 "@
3782 sle. %0,%1,%2
3783 {sli.|slwi.} %0,%1,%h2
3784 #
3785 #"
3786 [(set_attr "type" "delayed_compare")
3787 (set_attr "length" "4,4,8,8")])
3789 (define_split
3790 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3791 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3792 (match_operand:SI 2 "reg_or_cint_operand" ""))
3793 (const_int 0)))
3794 (set (match_operand:SI 0 "gpc_reg_operand" "")
3795 (ashift:SI (match_dup 1) (match_dup 2)))
3796 (clobber (match_scratch:SI 4 ""))]
3797 "TARGET_POWER && reload_completed"
3798 [(parallel [(set (match_dup 0)
3799 (ashift:SI (match_dup 1) (match_dup 2)))
3800 (clobber (match_dup 4))])
3801 (set (match_dup 3)
3802 (compare:CC (match_dup 0)
3803 (const_int 0)))]
3804 "")
3806 (define_insn ""
3807 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3808 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3810 (const_int 0)))
3811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3812 (ashift:SI (match_dup 1) (match_dup 2)))]
3813 "! TARGET_POWER && TARGET_32BIT"
3814 "@
3815 {sl|slw}%I2. %0,%1,%h2
3816 #"
3817 [(set_attr "type" "delayed_compare")
3818 (set_attr "length" "4,8")])
3820 (define_split
3821 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3822 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "reg_or_cint_operand" ""))
3824 (const_int 0)))
3825 (set (match_operand:SI 0 "gpc_reg_operand" "")
3826 (ashift:SI (match_dup 1) (match_dup 2)))]
3827 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3828 [(set (match_dup 0)
3829 (ashift:SI (match_dup 1) (match_dup 2)))
3830 (set (match_dup 3)
3831 (compare:CC (match_dup 0)
3832 (const_int 0)))]
3833 "")
3835 (define_insn "rlwinm"
3836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3837 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3838 (match_operand:SI 2 "const_int_operand" "i"))
3839 (match_operand:SI 3 "mask_operand" "n")))]
3840 "includes_lshift_p (operands[2], operands[3])"
3841 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3843 (define_insn ""
3844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3845 (compare:CC
3846 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3847 (match_operand:SI 2 "const_int_operand" "i,i"))
3848 (match_operand:SI 3 "mask_operand" "n,n"))
3849 (const_int 0)))
3850 (clobber (match_scratch:SI 4 "=r,r"))]
3851 "includes_lshift_p (operands[2], operands[3])"
3852 "@
3853 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3854 #"
3855 [(set_attr "type" "delayed_compare")
3856 (set_attr "length" "4,8")])
3858 (define_split
3859 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3860 (compare:CC
3861 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3862 (match_operand:SI 2 "const_int_operand" ""))
3863 (match_operand:SI 3 "mask_operand" ""))
3864 (const_int 0)))
3865 (clobber (match_scratch:SI 4 ""))]
3866 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3867 [(set (match_dup 4)
3868 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3869 (match_dup 3)))
3870 (set (match_dup 0)
3871 (compare:CC (match_dup 4)
3872 (const_int 0)))]
3873 "")
3875 (define_insn ""
3876 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3877 (compare:CC
3878 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3879 (match_operand:SI 2 "const_int_operand" "i,i"))
3880 (match_operand:SI 3 "mask_operand" "n,n"))
3881 (const_int 0)))
3882 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3883 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3884 "includes_lshift_p (operands[2], operands[3])"
3885 "@
3886 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3887 #"
3888 [(set_attr "type" "delayed_compare")
3889 (set_attr "length" "4,8")])
3891 (define_split
3892 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3893 (compare:CC
3894 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3895 (match_operand:SI 2 "const_int_operand" ""))
3896 (match_operand:SI 3 "mask_operand" ""))
3897 (const_int 0)))
3898 (set (match_operand:SI 0 "gpc_reg_operand" "")
3899 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3900 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3901 [(set (match_dup 0)
3902 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3903 (set (match_dup 4)
3904 (compare:CC (match_dup 0)
3905 (const_int 0)))]
3906 "")
3908 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3909 ;; "sli x,x,0".
3910 (define_expand "lshrsi3"
3911 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3912 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3913 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3914 ""
3915 "
3916 {
3917 if (TARGET_POWER)
3918 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3919 else
3920 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3921 DONE;
3922 }")
3924 (define_insn "lshrsi3_power"
3925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3926 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3927 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3928 (clobber (match_scratch:SI 3 "=q,X,X"))]
3929 "TARGET_POWER"
3930 "@
3931 sre %0,%1,%2
3932 mr %0,%1
3933 {s%A2i|s%A2wi} %0,%1,%h2")
3935 (define_insn "lshrsi3_no_power"
3936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3937 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3938 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3939 "! TARGET_POWER"
3940 "@
3941 mr %0,%1
3942 {sr|srw}%I2 %0,%1,%h2")
3944 (define_insn ""
3945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3946 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3947 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3948 (const_int 0)))
3949 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3950 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3951 "TARGET_POWER"
3952 "@
3953 sre. %3,%1,%2
3954 mr. %1,%1
3955 {s%A2i.|s%A2wi.} %3,%1,%h2
3956 #
3957 #
3958 #"
3959 [(set_attr "type" "delayed_compare")
3960 (set_attr "length" "4,4,4,8,8,8")])
3962 (define_split
3963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3964 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3965 (match_operand:SI 2 "reg_or_cint_operand" ""))
3966 (const_int 0)))
3967 (clobber (match_scratch:SI 3 ""))
3968 (clobber (match_scratch:SI 4 ""))]
3969 "TARGET_POWER && reload_completed"
3970 [(parallel [(set (match_dup 3)
3971 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3972 (clobber (match_dup 4))])
3973 (set (match_dup 0)
3974 (compare:CC (match_dup 3)
3975 (const_int 0)))]
3976 "")
3978 (define_insn ""
3979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3980 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3981 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3982 (const_int 0)))
3983 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3984 "! TARGET_POWER && TARGET_32BIT"
3985 "@
3986 mr. %1,%1
3987 {sr|srw}%I2. %3,%1,%h2
3988 #
3989 #"
3990 [(set_attr "type" "delayed_compare")
3991 (set_attr "length" "4,4,8,8")])
3993 (define_split
3994 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3995 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3996 (match_operand:SI 2 "reg_or_cint_operand" ""))
3997 (const_int 0)))
3998 (clobber (match_scratch:SI 3 ""))]
3999 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4000 [(set (match_dup 3)
4001 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4002 (set (match_dup 0)
4003 (compare:CC (match_dup 3)
4004 (const_int 0)))]
4005 "")
4007 (define_insn ""
4008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4009 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4010 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4011 (const_int 0)))
4012 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4013 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4014 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4015 "TARGET_POWER"
4016 "@
4017 sre. %0,%1,%2
4018 mr. %0,%1
4019 {s%A2i.|s%A2wi.} %0,%1,%h2
4020 #
4021 #
4022 #"
4023 [(set_attr "type" "delayed_compare")
4024 (set_attr "length" "4,4,4,8,8,8")])
4026 (define_split
4027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4028 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4029 (match_operand:SI 2 "reg_or_cint_operand" ""))
4030 (const_int 0)))
4031 (set (match_operand:SI 0 "gpc_reg_operand" "")
4032 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4033 (clobber (match_scratch:SI 4 ""))]
4034 "TARGET_POWER && reload_completed"
4035 [(parallel [(set (match_dup 0)
4036 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4037 (clobber (match_dup 4))])
4038 (set (match_dup 3)
4039 (compare:CC (match_dup 0)
4040 (const_int 0)))]
4041 "")
4043 (define_insn ""
4044 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4045 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4046 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4047 (const_int 0)))
4048 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4049 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4050 "! TARGET_POWER && TARGET_32BIT"
4051 "@
4052 mr. %0,%1
4053 {sr|srw}%I2. %0,%1,%h2
4054 #
4055 #"
4056 [(set_attr "type" "delayed_compare")
4057 (set_attr "length" "4,4,8,8")])
4059 (define_split
4060 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4061 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4062 (match_operand:SI 2 "reg_or_cint_operand" ""))
4063 (const_int 0)))
4064 (set (match_operand:SI 0 "gpc_reg_operand" "")
4065 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4066 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4067 [(set (match_dup 0)
4068 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4069 (set (match_dup 3)
4070 (compare:CC (match_dup 0)
4071 (const_int 0)))]
4072 "")
4074 (define_insn ""
4075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4076 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4077 (match_operand:SI 2 "const_int_operand" "i"))
4078 (match_operand:SI 3 "mask_operand" "n")))]
4079 "includes_rshift_p (operands[2], operands[3])"
4080 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4082 (define_insn ""
4083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4084 (compare:CC
4085 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4086 (match_operand:SI 2 "const_int_operand" "i,i"))
4087 (match_operand:SI 3 "mask_operand" "n,n"))
4088 (const_int 0)))
4089 (clobber (match_scratch:SI 4 "=r,r"))]
4090 "includes_rshift_p (operands[2], operands[3])"
4091 "@
4092 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4093 #"
4094 [(set_attr "type" "delayed_compare")
4095 (set_attr "length" "4,8")])
4097 (define_split
4098 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4099 (compare:CC
4100 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4101 (match_operand:SI 2 "const_int_operand" ""))
4102 (match_operand:SI 3 "mask_operand" ""))
4103 (const_int 0)))
4104 (clobber (match_scratch:SI 4 ""))]
4105 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4106 [(set (match_dup 4)
4107 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4108 (match_dup 3)))
4109 (set (match_dup 0)
4110 (compare:CC (match_dup 4)
4111 (const_int 0)))]
4112 "")
4114 (define_insn ""
4115 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4116 (compare:CC
4117 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i"))
4119 (match_operand:SI 3 "mask_operand" "n,n"))
4120 (const_int 0)))
4121 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4122 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4123 "includes_rshift_p (operands[2], operands[3])"
4124 "@
4125 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4126 #"
4127 [(set_attr "type" "delayed_compare")
4128 (set_attr "length" "4,8")])
4130 (define_split
4131 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4132 (compare:CC
4133 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" ""))
4135 (match_operand:SI 3 "mask_operand" ""))
4136 (const_int 0)))
4137 (set (match_operand:SI 0 "gpc_reg_operand" "")
4138 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4139 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4140 [(set (match_dup 0)
4141 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4142 (set (match_dup 4)
4143 (compare:CC (match_dup 0)
4144 (const_int 0)))]
4145 "")
4147 (define_insn ""
4148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4149 (zero_extend:SI
4150 (subreg:QI
4151 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4152 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4153 "includes_rshift_p (operands[2], GEN_INT (255))"
4154 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4156 (define_insn ""
4157 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4158 (compare:CC
4159 (zero_extend:SI
4160 (subreg:QI
4161 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4162 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4163 (const_int 0)))
4164 (clobber (match_scratch:SI 3 "=r,r"))]
4165 "includes_rshift_p (operands[2], GEN_INT (255))"
4166 "@
4167 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4168 #"
4169 [(set_attr "type" "delayed_compare")
4170 (set_attr "length" "4,8")])
4172 (define_split
4173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4174 (compare:CC
4175 (zero_extend:SI
4176 (subreg:QI
4177 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4178 (match_operand:SI 2 "const_int_operand" "")) 0))
4179 (const_int 0)))
4180 (clobber (match_scratch:SI 3 ""))]
4181 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4182 [(set (match_dup 3)
4183 (zero_extend:SI (subreg:QI
4184 (lshiftrt:SI (match_dup 1)
4185 (match_dup 2)) 0)))
4186 (set (match_dup 0)
4187 (compare:CC (match_dup 3)
4188 (const_int 0)))]
4189 "")
4191 (define_insn ""
4192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4193 (compare:CC
4194 (zero_extend:SI
4195 (subreg:QI
4196 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4197 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4198 (const_int 0)))
4199 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4200 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4201 "includes_rshift_p (operands[2], GEN_INT (255))"
4202 "@
4203 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4204 #"
4205 [(set_attr "type" "delayed_compare")
4206 (set_attr "length" "4,8")])
4208 (define_split
4209 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4210 (compare:CC
4211 (zero_extend:SI
4212 (subreg:QI
4213 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4214 (match_operand:SI 2 "const_int_operand" "")) 0))
4215 (const_int 0)))
4216 (set (match_operand:SI 0 "gpc_reg_operand" "")
4217 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4218 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4219 [(set (match_dup 0)
4220 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4221 (set (match_dup 3)
4222 (compare:CC (match_dup 0)
4223 (const_int 0)))]
4224 "")
4226 (define_insn ""
4227 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4228 (zero_extend:SI
4229 (subreg:HI
4230 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4231 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4232 "includes_rshift_p (operands[2], GEN_INT (65535))"
4233 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4235 (define_insn ""
4236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4237 (compare:CC
4238 (zero_extend:SI
4239 (subreg:HI
4240 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4241 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4242 (const_int 0)))
4243 (clobber (match_scratch:SI 3 "=r,r"))]
4244 "includes_rshift_p (operands[2], GEN_INT (65535))"
4245 "@
4246 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4247 #"
4248 [(set_attr "type" "delayed_compare")
4249 (set_attr "length" "4,8")])
4251 (define_split
4252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4253 (compare:CC
4254 (zero_extend:SI
4255 (subreg:HI
4256 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4257 (match_operand:SI 2 "const_int_operand" "")) 0))
4258 (const_int 0)))
4259 (clobber (match_scratch:SI 3 ""))]
4260 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4261 [(set (match_dup 3)
4262 (zero_extend:SI (subreg:HI
4263 (lshiftrt:SI (match_dup 1)
4264 (match_dup 2)) 0)))
4265 (set (match_dup 0)
4266 (compare:CC (match_dup 3)
4267 (const_int 0)))]
4268 "")
4270 (define_insn ""
4271 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4272 (compare:CC
4273 (zero_extend:SI
4274 (subreg:HI
4275 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4276 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4277 (const_int 0)))
4278 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4279 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4280 "includes_rshift_p (operands[2], GEN_INT (65535))"
4281 "@
4282 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4283 #"
4284 [(set_attr "type" "delayed_compare")
4285 (set_attr "length" "4,8")])
4287 (define_split
4288 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4289 (compare:CC
4290 (zero_extend:SI
4291 (subreg:HI
4292 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4293 (match_operand:SI 2 "const_int_operand" "")) 0))
4294 (const_int 0)))
4295 (set (match_operand:SI 0 "gpc_reg_operand" "")
4296 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4297 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4298 [(set (match_dup 0)
4299 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4300 (set (match_dup 3)
4301 (compare:CC (match_dup 0)
4302 (const_int 0)))]
4303 "")
4305 (define_insn ""
4306 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4307 (const_int 1)
4308 (match_operand:SI 1 "gpc_reg_operand" "r"))
4309 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4310 (const_int 31)))]
4311 "TARGET_POWER"
4312 "rrib %0,%1,%2")
4314 (define_insn ""
4315 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4316 (const_int 1)
4317 (match_operand:SI 1 "gpc_reg_operand" "r"))
4318 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4319 (const_int 31)))]
4320 "TARGET_POWER"
4321 "rrib %0,%1,%2")
4323 (define_insn ""
4324 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4325 (const_int 1)
4326 (match_operand:SI 1 "gpc_reg_operand" "r"))
4327 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4328 (const_int 1)
4329 (const_int 0)))]
4330 "TARGET_POWER"
4331 "rrib %0,%1,%2")
4333 (define_expand "ashrsi3"
4334 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4335 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4336 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4337 ""
4338 "
4339 {
4340 if (TARGET_POWER)
4341 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4342 else
4343 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4344 DONE;
4345 }")
4347 (define_insn "ashrsi3_power"
4348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4349 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4350 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4351 (clobber (match_scratch:SI 3 "=q,X"))]
4352 "TARGET_POWER"
4353 "@
4354 srea %0,%1,%2
4355 {srai|srawi} %0,%1,%h2")
4357 (define_insn "ashrsi3_no_power"
4358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4359 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4360 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4361 "! TARGET_POWER"
4362 "{sra|sraw}%I2 %0,%1,%h2")
4364 (define_insn ""
4365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4366 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4367 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4368 (const_int 0)))
4369 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4370 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4371 "TARGET_POWER"
4372 "@
4373 srea. %3,%1,%2
4374 {srai.|srawi.} %3,%1,%h2
4375 #
4376 #"
4377 [(set_attr "type" "delayed_compare")
4378 (set_attr "length" "4,4,8,8")])
4380 (define_split
4381 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4382 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4383 (match_operand:SI 2 "reg_or_cint_operand" ""))
4384 (const_int 0)))
4385 (clobber (match_scratch:SI 3 ""))
4386 (clobber (match_scratch:SI 4 ""))]
4387 "TARGET_POWER && reload_completed"
4388 [(parallel [(set (match_dup 3)
4389 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4390 (clobber (match_dup 4))])
4391 (set (match_dup 0)
4392 (compare:CC (match_dup 3)
4393 (const_int 0)))]
4394 "")
4396 (define_insn ""
4397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4398 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4399 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4400 (const_int 0)))
4401 (clobber (match_scratch:SI 3 "=r,r"))]
4402 "! TARGET_POWER"
4403 "@
4404 {sra|sraw}%I2. %3,%1,%h2
4405 #"
4406 [(set_attr "type" "delayed_compare")
4407 (set_attr "length" "4,8")])
4409 (define_split
4410 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4411 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4412 (match_operand:SI 2 "reg_or_cint_operand" ""))
4413 (const_int 0)))
4414 (clobber (match_scratch:SI 3 ""))]
4415 "! TARGET_POWER && reload_completed"
4416 [(set (match_dup 3)
4417 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4418 (set (match_dup 0)
4419 (compare:CC (match_dup 3)
4420 (const_int 0)))]
4421 "")
4423 (define_insn ""
4424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4425 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4426 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4427 (const_int 0)))
4428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4429 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4430 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4431 "TARGET_POWER"
4432 "@
4433 srea. %0,%1,%2
4434 {srai.|srawi.} %0,%1,%h2
4435 #
4436 #"
4437 [(set_attr "type" "delayed_compare")
4438 (set_attr "length" "4,4,8,8")])
4440 (define_split
4441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4442 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4443 (match_operand:SI 2 "reg_or_cint_operand" ""))
4444 (const_int 0)))
4445 (set (match_operand:SI 0 "gpc_reg_operand" "")
4446 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4447 (clobber (match_scratch:SI 4 ""))]
4448 "TARGET_POWER && reload_completed"
4449 [(parallel [(set (match_dup 0)
4450 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4451 (clobber (match_dup 4))])
4452 (set (match_dup 3)
4453 (compare:CC (match_dup 0)
4454 (const_int 0)))]
4455 "")
4457 (define_insn ""
4458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4459 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4460 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4461 (const_int 0)))
4462 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4463 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4464 "! TARGET_POWER"
4465 "@
4466 {sra|sraw}%I2. %0,%1,%h2
4467 #"
4468 [(set_attr "type" "delayed_compare")
4469 (set_attr "length" "4,8")])
4470 \f
4471 (define_split
4472 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4473 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4474 (match_operand:SI 2 "reg_or_cint_operand" ""))
4475 (const_int 0)))
4476 (set (match_operand:SI 0 "gpc_reg_operand" "")
4477 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4478 "! TARGET_POWER && reload_completed"
4479 [(set (match_dup 0)
4480 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4481 (set (match_dup 3)
4482 (compare:CC (match_dup 0)
4483 (const_int 0)))]
4484 "")
4486 ;; Floating-point insns, excluding normal data motion.
4487 ;;
4488 ;; PowerPC has a full set of single-precision floating point instructions.
4489 ;;
4490 ;; For the POWER architecture, we pretend that we have both SFmode and
4491 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4492 ;; The only conversions we will do will be when storing to memory. In that
4493 ;; case, we will use the "frsp" instruction before storing.
4494 ;;
4495 ;; Note that when we store into a single-precision memory location, we need to
4496 ;; use the frsp insn first. If the register being stored isn't dead, we
4497 ;; need a scratch register for the frsp. But this is difficult when the store
4498 ;; is done by reload. It is not incorrect to do the frsp on the register in
4499 ;; this case, we just lose precision that we would have otherwise gotten but
4500 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4502 (define_expand "extendsfdf2"
4503 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4504 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4505 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4506 "")
4508 (define_insn_and_split "*extendsfdf2_fpr"
4509 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4510 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4511 "TARGET_HARD_FLOAT && TARGET_FPRS"
4512 "@
4513 #
4514 fmr %0,%1
4515 lfs%U1%X1 %0,%1"
4516 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4517 [(const_int 0)]
4518 {
4519 emit_note (NOTE_INSN_DELETED);
4520 DONE;
4521 }
4522 [(set_attr "type" "fp,fp,fpload")])
4524 (define_expand "truncdfsf2"
4525 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4526 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4527 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4528 "")
4530 (define_insn "*truncdfsf2_fpr"
4531 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4532 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4533 "TARGET_HARD_FLOAT && TARGET_FPRS"
4534 "frsp %0,%1"
4535 [(set_attr "type" "fp")])
4537 (define_insn "aux_truncdfsf2"
4538 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4539 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4540 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4541 "frsp %0,%1"
4542 [(set_attr "type" "fp")])
4544 (define_expand "negsf2"
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4546 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4547 "TARGET_HARD_FLOAT"
4548 "")
4550 (define_insn "*negsf2"
4551 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4552 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4553 "TARGET_HARD_FLOAT && TARGET_FPRS"
4554 "fneg %0,%1"
4555 [(set_attr "type" "fp")])
4557 (define_expand "abssf2"
4558 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4559 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4560 "TARGET_HARD_FLOAT"
4561 "")
4563 (define_insn "*abssf2"
4564 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4565 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4566 "TARGET_HARD_FLOAT && TARGET_FPRS"
4567 "fabs %0,%1"
4568 [(set_attr "type" "fp")])
4570 (define_insn ""
4571 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4572 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4573 "TARGET_HARD_FLOAT && TARGET_FPRS"
4574 "fnabs %0,%1"
4575 [(set_attr "type" "fp")])
4577 (define_expand "addsf3"
4578 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4579 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4580 (match_operand:SF 2 "gpc_reg_operand" "")))]
4581 "TARGET_HARD_FLOAT"
4582 "")
4584 (define_insn ""
4585 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4586 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4587 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4588 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4589 "fadds %0,%1,%2"
4590 [(set_attr "type" "fp")])
4592 (define_insn ""
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4595 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4596 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4597 "{fa|fadd} %0,%1,%2"
4598 [(set_attr "type" "fp")])
4600 (define_expand "subsf3"
4601 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4602 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4603 (match_operand:SF 2 "gpc_reg_operand" "")))]
4604 "TARGET_HARD_FLOAT"
4605 "")
4607 (define_insn ""
4608 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4609 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4610 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4611 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4612 "fsubs %0,%1,%2"
4613 [(set_attr "type" "fp")])
4615 (define_insn ""
4616 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4617 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4618 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4619 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4620 "{fs|fsub} %0,%1,%2"
4621 [(set_attr "type" "fp")])
4623 (define_expand "mulsf3"
4624 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4625 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4626 (match_operand:SF 2 "gpc_reg_operand" "")))]
4627 "TARGET_HARD_FLOAT"
4628 "")
4630 (define_insn ""
4631 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4632 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4634 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4635 "fmuls %0,%1,%2"
4636 [(set_attr "type" "fp")])
4638 (define_insn ""
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4640 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4641 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4642 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4643 "{fm|fmul} %0,%1,%2"
4644 [(set_attr "type" "dmul")])
4646 (define_insn "fres"
4647 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4648 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4649 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4650 "fres %0,%1"
4651 [(set_attr "type" "fp")])
4653 (define_expand "divsf3"
4654 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4655 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4656 (match_operand:SF 2 "gpc_reg_operand" "")))]
4657 "TARGET_HARD_FLOAT"
4658 {
4659 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4660 && flag_finite_math_only && !flag_trapping_math)
4661 {
4662 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4663 DONE;
4664 }
4665 })
4667 (define_insn ""
4668 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4669 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4670 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4671 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4672 "fdivs %0,%1,%2"
4673 [(set_attr "type" "sdiv")])
4675 (define_insn ""
4676 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4677 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4678 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4679 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4680 "{fd|fdiv} %0,%1,%2"
4681 [(set_attr "type" "ddiv")])
4683 (define_insn ""
4684 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4685 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4686 (match_operand:SF 2 "gpc_reg_operand" "f"))
4687 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4688 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4689 "fmadds %0,%1,%2,%3"
4690 [(set_attr "type" "fp")])
4692 (define_insn ""
4693 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4694 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4695 (match_operand:SF 2 "gpc_reg_operand" "f"))
4696 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4697 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4698 "{fma|fmadd} %0,%1,%2,%3"
4699 [(set_attr "type" "dmul")])
4701 (define_insn ""
4702 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4703 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4704 (match_operand:SF 2 "gpc_reg_operand" "f"))
4705 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4706 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4707 "fmsubs %0,%1,%2,%3"
4708 [(set_attr "type" "fp")])
4710 (define_insn ""
4711 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4712 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4713 (match_operand:SF 2 "gpc_reg_operand" "f"))
4714 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4715 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4716 "{fms|fmsub} %0,%1,%2,%3"
4717 [(set_attr "type" "dmul")])
4719 (define_insn ""
4720 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4721 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4722 (match_operand:SF 2 "gpc_reg_operand" "f"))
4723 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4724 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4725 && HONOR_SIGNED_ZEROS (SFmode)"
4726 "fnmadds %0,%1,%2,%3"
4727 [(set_attr "type" "fp")])
4729 (define_insn ""
4730 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4731 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4732 (match_operand:SF 2 "gpc_reg_operand" "f"))
4733 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4734 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4735 && ! HONOR_SIGNED_ZEROS (SFmode)"
4736 "fnmadds %0,%1,%2,%3"
4737 [(set_attr "type" "fp")])
4739 (define_insn ""
4740 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4741 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4742 (match_operand:SF 2 "gpc_reg_operand" "f"))
4743 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4744 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4745 "{fnma|fnmadd} %0,%1,%2,%3"
4746 [(set_attr "type" "dmul")])
4748 (define_insn ""
4749 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4750 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4751 (match_operand:SF 2 "gpc_reg_operand" "f"))
4752 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4753 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4754 && ! HONOR_SIGNED_ZEROS (SFmode)"
4755 "{fnma|fnmadd} %0,%1,%2,%3"
4756 [(set_attr "type" "dmul")])
4758 (define_insn ""
4759 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4760 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4761 (match_operand:SF 2 "gpc_reg_operand" "f"))
4762 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4763 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4764 && HONOR_SIGNED_ZEROS (SFmode)"
4765 "fnmsubs %0,%1,%2,%3"
4766 [(set_attr "type" "fp")])
4768 (define_insn ""
4769 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4770 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4771 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4772 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4773 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4774 && ! HONOR_SIGNED_ZEROS (SFmode)"
4775 "fnmsubs %0,%1,%2,%3"
4776 [(set_attr "type" "fp")])
4778 (define_insn ""
4779 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4780 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4781 (match_operand:SF 2 "gpc_reg_operand" "f"))
4782 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4783 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4784 "{fnms|fnmsub} %0,%1,%2,%3"
4785 [(set_attr "type" "dmul")])
4787 (define_insn ""
4788 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4789 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4790 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4791 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4792 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4793 && ! HONOR_SIGNED_ZEROS (SFmode)"
4794 "{fnms|fnmsub} %0,%1,%2,%3"
4795 [(set_attr "type" "fp")])
4797 (define_expand "sqrtsf2"
4798 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4799 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4800 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4801 "")
4803 (define_insn ""
4804 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4805 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4806 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4807 "fsqrts %0,%1"
4808 [(set_attr "type" "ssqrt")])
4810 (define_insn ""
4811 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4812 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4813 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4814 "fsqrt %0,%1"
4815 [(set_attr "type" "dsqrt")])
4817 (define_expand "copysignsf3"
4818 [(set (match_dup 3)
4819 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4820 (set (match_dup 4)
4821 (neg:SF (abs:SF (match_dup 1))))
4822 (set (match_operand:SF 0 "gpc_reg_operand" "")
4823 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4824 (match_dup 5))
4825 (match_dup 3)
4826 (match_dup 4)))]
4827 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4828 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4829 {
4830 operands[3] = gen_reg_rtx (SFmode);
4831 operands[4] = gen_reg_rtx (SFmode);
4832 operands[5] = CONST0_RTX (SFmode);
4833 })
4835 (define_expand "copysigndf3"
4836 [(set (match_dup 3)
4837 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4838 (set (match_dup 4)
4839 (neg:DF (abs:DF (match_dup 1))))
4840 (set (match_operand:DF 0 "gpc_reg_operand" "")
4841 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4842 (match_dup 5))
4843 (match_dup 3)
4844 (match_dup 4)))]
4845 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4846 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4847 {
4848 operands[3] = gen_reg_rtx (DFmode);
4849 operands[4] = gen_reg_rtx (DFmode);
4850 operands[5] = CONST0_RTX (DFmode);
4851 })
4853 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4854 ;; fsel instruction and some auxiliary computations. Then we just have a
4855 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4856 ;; combine.
4857 (define_expand "smaxsf3"
4858 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4859 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4860 (match_operand:SF 2 "gpc_reg_operand" ""))
4861 (match_dup 1)
4862 (match_dup 2)))]
4863 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4864 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4866 (define_expand "sminsf3"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4868 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4869 (match_operand:SF 2 "gpc_reg_operand" ""))
4870 (match_dup 2)
4871 (match_dup 1)))]
4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4873 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4875 (define_split
4876 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4877 (match_operator:SF 3 "min_max_operator"
4878 [(match_operand:SF 1 "gpc_reg_operand" "")
4879 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4880 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4881 [(const_int 0)]
4882 "
4883 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4884 operands[1], operands[2]);
4885 DONE;
4886 }")
4888 (define_expand "movsicc"
4889 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4890 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4891 (match_operand:SI 2 "gpc_reg_operand" "")
4892 (match_operand:SI 3 "gpc_reg_operand" "")))]
4893 "TARGET_ISEL"
4894 "
4895 {
4896 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4897 DONE;
4898 else
4899 FAIL;
4900 }")
4902 ;; We use the BASE_REGS for the isel input operands because, if rA is
4903 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4904 ;; because we may switch the operands and rB may end up being rA.
4905 ;;
4906 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4907 ;; leave out the mode in operand 4 and use one pattern, but reload can
4908 ;; change the mode underneath our feet and then gets confused trying
4909 ;; to reload the value.
4910 (define_insn "isel_signed"
4911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4912 (if_then_else:SI
4913 (match_operator 1 "comparison_operator"
4914 [(match_operand:CC 4 "cc_reg_operand" "y")
4915 (const_int 0)])
4916 (match_operand:SI 2 "gpc_reg_operand" "b")
4917 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4918 "TARGET_ISEL"
4919 "*
4920 { return output_isel (operands); }"
4921 [(set_attr "length" "4")])
4923 (define_insn "isel_unsigned"
4924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4925 (if_then_else:SI
4926 (match_operator 1 "comparison_operator"
4927 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4928 (const_int 0)])
4929 (match_operand:SI 2 "gpc_reg_operand" "b")
4930 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4931 "TARGET_ISEL"
4932 "*
4933 { return output_isel (operands); }"
4934 [(set_attr "length" "4")])
4936 (define_expand "movsfcc"
4937 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4938 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4939 (match_operand:SF 2 "gpc_reg_operand" "")
4940 (match_operand:SF 3 "gpc_reg_operand" "")))]
4941 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4942 "
4943 {
4944 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4945 DONE;
4946 else
4947 FAIL;
4948 }")
4950 (define_insn "*fselsfsf4"
4951 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4952 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4953 (match_operand:SF 4 "zero_fp_constant" "F"))
4954 (match_operand:SF 2 "gpc_reg_operand" "f")
4955 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4956 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4957 "fsel %0,%1,%2,%3"
4958 [(set_attr "type" "fp")])
4960 (define_insn "*fseldfsf4"
4961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4962 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4963 (match_operand:DF 4 "zero_fp_constant" "F"))
4964 (match_operand:SF 2 "gpc_reg_operand" "f")
4965 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4966 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4967 "fsel %0,%1,%2,%3"
4968 [(set_attr "type" "fp")])
4970 (define_expand "negdf2"
4971 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4972 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4973 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4974 "")
4976 (define_insn "*negdf2_fpr"
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4978 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4979 "TARGET_HARD_FLOAT && TARGET_FPRS"
4980 "fneg %0,%1"
4981 [(set_attr "type" "fp")])
4983 (define_expand "absdf2"
4984 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4985 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4986 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4987 "")
4989 (define_insn "*absdf2_fpr"
4990 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4991 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4992 "TARGET_HARD_FLOAT && TARGET_FPRS"
4993 "fabs %0,%1"
4994 [(set_attr "type" "fp")])
4996 (define_insn "*nabsdf2_fpr"
4997 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4998 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4999 "TARGET_HARD_FLOAT && TARGET_FPRS"
5000 "fnabs %0,%1"
5001 [(set_attr "type" "fp")])
5003 (define_expand "adddf3"
5004 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5005 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5006 (match_operand:DF 2 "gpc_reg_operand" "")))]
5007 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5008 "")
5010 (define_insn "*adddf3_fpr"
5011 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5012 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5013 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5014 "TARGET_HARD_FLOAT && TARGET_FPRS"
5015 "{fa|fadd} %0,%1,%2"
5016 [(set_attr "type" "fp")])
5018 (define_expand "subdf3"
5019 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5020 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5021 (match_operand:DF 2 "gpc_reg_operand" "")))]
5022 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5023 "")
5025 (define_insn "*subdf3_fpr"
5026 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5027 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5028 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5029 "TARGET_HARD_FLOAT && TARGET_FPRS"
5030 "{fs|fsub} %0,%1,%2"
5031 [(set_attr "type" "fp")])
5033 (define_expand "muldf3"
5034 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5035 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5036 (match_operand:DF 2 "gpc_reg_operand" "")))]
5037 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5038 "")
5040 (define_insn "*muldf3_fpr"
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5042 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5043 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5044 "TARGET_HARD_FLOAT && TARGET_FPRS"
5045 "{fm|fmul} %0,%1,%2"
5046 [(set_attr "type" "dmul")])
5048 (define_insn "fred"
5049 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5050 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5051 "TARGET_POPCNTB && flag_finite_math_only"
5052 "fre %0,%1"
5053 [(set_attr "type" "fp")])
5055 (define_expand "divdf3"
5056 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5057 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5058 (match_operand:DF 2 "gpc_reg_operand" "")))]
5059 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5060 {
5061 if (swdiv && !optimize_size && TARGET_POPCNTB
5062 && flag_finite_math_only && !flag_trapping_math)
5063 {
5064 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5065 DONE;
5066 }
5067 })
5069 (define_insn "*divdf3_fpr"
5070 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5071 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5072 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5073 "TARGET_HARD_FLOAT && TARGET_FPRS"
5074 "{fd|fdiv} %0,%1,%2"
5075 [(set_attr "type" "ddiv")])
5077 (define_insn ""
5078 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5079 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5080 (match_operand:DF 2 "gpc_reg_operand" "f"))
5081 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5082 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5083 "{fma|fmadd} %0,%1,%2,%3"
5084 [(set_attr "type" "dmul")])
5086 (define_insn ""
5087 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5088 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5089 (match_operand:DF 2 "gpc_reg_operand" "f"))
5090 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5091 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5092 "{fms|fmsub} %0,%1,%2,%3"
5093 [(set_attr "type" "dmul")])
5095 (define_insn ""
5096 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5097 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5098 (match_operand:DF 2 "gpc_reg_operand" "f"))
5099 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5100 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5101 && HONOR_SIGNED_ZEROS (DFmode)"
5102 "{fnma|fnmadd} %0,%1,%2,%3"
5103 [(set_attr "type" "dmul")])
5105 (define_insn ""
5106 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5107 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5108 (match_operand:DF 2 "gpc_reg_operand" "f"))
5109 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5110 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5111 && ! HONOR_SIGNED_ZEROS (DFmode)"
5112 "{fnma|fnmadd} %0,%1,%2,%3"
5113 [(set_attr "type" "dmul")])
5115 (define_insn ""
5116 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5117 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5118 (match_operand:DF 2 "gpc_reg_operand" "f"))
5119 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5120 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5121 && HONOR_SIGNED_ZEROS (DFmode)"
5122 "{fnms|fnmsub} %0,%1,%2,%3"
5123 [(set_attr "type" "dmul")])
5125 (define_insn ""
5126 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5127 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5128 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5129 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5130 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5131 && ! HONOR_SIGNED_ZEROS (DFmode)"
5132 "{fnms|fnmsub} %0,%1,%2,%3"
5133 [(set_attr "type" "dmul")])
5135 (define_insn "sqrtdf2"
5136 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5137 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5138 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5139 "fsqrt %0,%1"
5140 [(set_attr "type" "dsqrt")])
5142 ;; The conditional move instructions allow us to perform max and min
5143 ;; operations even when
5145 (define_expand "smaxdf3"
5146 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5147 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5148 (match_operand:DF 2 "gpc_reg_operand" ""))
5149 (match_dup 1)
5150 (match_dup 2)))]
5151 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5152 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5154 (define_expand "smindf3"
5155 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5156 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5157 (match_operand:DF 2 "gpc_reg_operand" ""))
5158 (match_dup 2)
5159 (match_dup 1)))]
5160 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5161 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5163 (define_split
5164 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5165 (match_operator:DF 3 "min_max_operator"
5166 [(match_operand:DF 1 "gpc_reg_operand" "")
5167 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5168 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5169 [(const_int 0)]
5170 "
5171 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5172 operands[1], operands[2]);
5173 DONE;
5174 }")
5176 (define_expand "movdfcc"
5177 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5178 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5179 (match_operand:DF 2 "gpc_reg_operand" "")
5180 (match_operand:DF 3 "gpc_reg_operand" "")))]
5181 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5182 "
5183 {
5184 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5185 DONE;
5186 else
5187 FAIL;
5188 }")
5190 (define_insn "*fseldfdf4"
5191 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5192 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5193 (match_operand:DF 4 "zero_fp_constant" "F"))
5194 (match_operand:DF 2 "gpc_reg_operand" "f")
5195 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5196 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5197 "fsel %0,%1,%2,%3"
5198 [(set_attr "type" "fp")])
5200 (define_insn "*fselsfdf4"
5201 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5202 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5203 (match_operand:SF 4 "zero_fp_constant" "F"))
5204 (match_operand:DF 2 "gpc_reg_operand" "f")
5205 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5206 "TARGET_PPC_GFXOPT"
5207 "fsel %0,%1,%2,%3"
5208 [(set_attr "type" "fp")])
5209 \f
5210 ;; Conversions to and from floating-point.
5212 (define_expand "fixuns_truncsfsi2"
5213 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5214 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5215 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5216 "")
5218 (define_expand "fix_truncsfsi2"
5219 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5220 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5221 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5222 "")
5224 ; For each of these conversions, there is a define_expand, a define_insn
5225 ; with a '#' template, and a define_split (with C code). The idea is
5226 ; to allow constant folding with the template of the define_insn,
5227 ; then to have the insns split later (between sched1 and final).
5229 (define_expand "floatsidf2"
5230 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5231 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5232 (use (match_dup 2))
5233 (use (match_dup 3))
5234 (clobber (match_dup 4))
5235 (clobber (match_dup 5))
5236 (clobber (match_dup 6))])]
5237 "TARGET_HARD_FLOAT && TARGET_FPRS"
5238 "
5239 {
5240 if (TARGET_E500_DOUBLE)
5241 {
5242 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5243 DONE;
5244 }
5245 if (TARGET_POWERPC64)
5246 {
5247 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5248 rtx t1 = gen_reg_rtx (DImode);
5249 rtx t2 = gen_reg_rtx (DImode);
5250 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5251 DONE;
5252 }
5254 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5255 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5256 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5257 operands[5] = gen_reg_rtx (DFmode);
5258 operands[6] = gen_reg_rtx (SImode);
5259 }")
5261 (define_insn_and_split "*floatsidf2_internal"
5262 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5263 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5264 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5265 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5266 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5267 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5268 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5269 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5270 "#"
5271 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5272 [(pc)]
5273 "
5274 {
5275 rtx lowword, highword;
5276 gcc_assert (MEM_P (operands[4]));
5277 highword = adjust_address (operands[4], SImode, 0);
5278 lowword = adjust_address (operands[4], SImode, 4);
5279 if (! WORDS_BIG_ENDIAN)
5280 {
5281 rtx tmp;
5282 tmp = highword; highword = lowword; lowword = tmp;
5283 }
5285 emit_insn (gen_xorsi3 (operands[6], operands[1],
5286 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5287 emit_move_insn (lowword, operands[6]);
5288 emit_move_insn (highword, operands[2]);
5289 emit_move_insn (operands[5], operands[4]);
5290 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5291 DONE;
5292 }"
5293 [(set_attr "length" "24")])
5295 (define_expand "floatunssisf2"
5296 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5297 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5298 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5299 "")
5301 (define_expand "floatunssidf2"
5302 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5303 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5304 (use (match_dup 2))
5305 (use (match_dup 3))
5306 (clobber (match_dup 4))
5307 (clobber (match_dup 5))])]
5308 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5309 "
5310 {
5311 if (TARGET_E500_DOUBLE)
5312 {
5313 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5314 DONE;
5315 }
5316 if (TARGET_POWERPC64)
5317 {
5318 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5319 rtx t1 = gen_reg_rtx (DImode);
5320 rtx t2 = gen_reg_rtx (DImode);
5321 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5322 t1, t2));
5323 DONE;
5324 }
5326 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5327 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5328 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5329 operands[5] = gen_reg_rtx (DFmode);
5330 }")
5332 (define_insn_and_split "*floatunssidf2_internal"
5333 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5334 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5335 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5336 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5337 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5338 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5339 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5340 "#"
5341 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5342 [(pc)]
5343 "
5344 {
5345 rtx lowword, highword;
5346 gcc_assert (MEM_P (operands[4]));
5347 highword = adjust_address (operands[4], SImode, 0);
5348 lowword = adjust_address (operands[4], SImode, 4);
5349 if (! WORDS_BIG_ENDIAN)
5350 {
5351 rtx tmp;
5352 tmp = highword; highword = lowword; lowword = tmp;
5353 }
5355 emit_move_insn (lowword, operands[1]);
5356 emit_move_insn (highword, operands[2]);
5357 emit_move_insn (operands[5], operands[4]);
5358 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5359 DONE;
5360 }"
5361 [(set_attr "length" "20")])
5363 (define_expand "fix_truncdfsi2"
5364 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5365 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5366 (clobber (match_dup 2))
5367 (clobber (match_dup 3))])]
5368 "(TARGET_POWER2 || TARGET_POWERPC)
5369 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5370 "
5371 {
5372 if (TARGET_E500_DOUBLE)
5373 {
5374 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5375 DONE;
5376 }
5377 operands[2] = gen_reg_rtx (DImode);
5378 if (TARGET_PPC_GFXOPT)
5379 {
5380 rtx orig_dest = operands[0];
5381 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5382 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5383 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5384 operands[2]));
5385 if (operands[0] != orig_dest)
5386 emit_move_insn (orig_dest, operands[0]);
5387 DONE;
5388 }
5389 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5390 }")
5392 (define_insn_and_split "*fix_truncdfsi2_internal"
5393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5394 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5395 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5396 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5397 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5398 "#"
5399 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5400 [(pc)]
5401 "
5402 {
5403 rtx lowword;
5404 gcc_assert (MEM_P (operands[3]));
5405 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5407 emit_insn (gen_fctiwz (operands[2], operands[1]));
5408 emit_move_insn (operands[3], operands[2]);
5409 emit_move_insn (operands[0], lowword);
5410 DONE;
5411 }"
5412 [(set_attr "length" "16")])
5414 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5415 [(set (match_operand:SI 0 "memory_operand" "=Z")
5416 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5417 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5418 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5419 && TARGET_PPC_GFXOPT"
5420 "#"
5421 "&& 1"
5422 [(pc)]
5423 "
5424 {
5425 emit_insn (gen_fctiwz (operands[2], operands[1]));
5426 emit_insn (gen_stfiwx (operands[0], operands[2]));
5427 DONE;
5428 }"
5429 [(set_attr "length" "16")])
5431 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5432 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5433 ; because the first makes it clear that operand 0 is not live
5434 ; before the instruction.
5435 (define_insn "fctiwz"
5436 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5437 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5438 UNSPEC_FCTIWZ))]
5439 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5440 "{fcirz|fctiwz} %0,%1"
5441 [(set_attr "type" "fp")])
5443 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5444 (define_insn "stfiwx"
5445 [(set (match_operand:SI 0 "memory_operand" "=Z")
5446 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5447 UNSPEC_STFIWX))]
5448 "TARGET_PPC_GFXOPT"
5449 "stfiwx %1,%y0"
5450 [(set_attr "type" "fpstore")])
5452 (define_expand "floatsisf2"
5453 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5454 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5455 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5456 "")
5458 (define_insn "floatdidf2"
5459 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5460 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5461 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5462 "fcfid %0,%1"
5463 [(set_attr "type" "fp")])
5465 (define_insn_and_split "floatsidf_ppc64"
5466 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5467 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5468 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5469 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5470 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5471 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5472 "#"
5473 "&& 1"
5474 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5475 (set (match_dup 2) (match_dup 3))
5476 (set (match_dup 4) (match_dup 2))
5477 (set (match_dup 0) (float:DF (match_dup 4)))]
5478 "")
5480 (define_insn_and_split "floatunssidf_ppc64"
5481 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5482 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5483 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5484 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5485 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5486 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5487 "#"
5488 "&& 1"
5489 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5490 (set (match_dup 2) (match_dup 3))
5491 (set (match_dup 4) (match_dup 2))
5492 (set (match_dup 0) (float:DF (match_dup 4)))]
5493 "")
5495 (define_insn "fix_truncdfdi2"
5496 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5497 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5498 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5499 "fctidz %0,%1"
5500 [(set_attr "type" "fp")])
5502 (define_expand "floatdisf2"
5503 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5504 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5505 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5506 "
5507 {
5508 rtx val = operands[1];
5509 if (!flag_unsafe_math_optimizations)
5510 {
5511 rtx label = gen_label_rtx ();
5512 val = gen_reg_rtx (DImode);
5513 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5514 emit_label (label);
5515 }
5516 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5517 DONE;
5518 }")
5520 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5521 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5522 ;; from double rounding.
5523 (define_insn_and_split "floatdisf2_internal1"
5524 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5525 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5526 (clobber (match_scratch:DF 2 "=f"))]
5527 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5528 "#"
5529 "&& reload_completed"
5530 [(set (match_dup 2)
5531 (float:DF (match_dup 1)))
5532 (set (match_dup 0)
5533 (float_truncate:SF (match_dup 2)))]
5534 "")
5536 ;; Twiddles bits to avoid double rounding.
5537 ;; Bits that might be truncated when converting to DFmode are replaced
5538 ;; by a bit that won't be lost at that stage, but is below the SFmode
5539 ;; rounding position.
5540 (define_expand "floatdisf2_internal2"
5541 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5542 (const_int 53)))
5543 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5544 (const_int 2047)))
5545 (clobber (scratch:CC))])
5546 (set (match_dup 3) (plus:DI (match_dup 3)
5547 (const_int 1)))
5548 (set (match_dup 0) (plus:DI (match_dup 0)
5549 (const_int 2047)))
5550 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5551 (const_int 3)))
5552 (set (match_dup 0) (ior:DI (match_dup 0)
5553 (match_dup 1)))
5554 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5555 (const_int -2048)))
5556 (clobber (scratch:CC))])
5557 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5558 (label_ref (match_operand:DI 2 "" ""))
5559 (pc)))
5560 (set (match_dup 0) (match_dup 1))]
5561 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5562 "
5563 {
5564 operands[3] = gen_reg_rtx (DImode);
5565 operands[4] = gen_reg_rtx (CCUNSmode);
5566 }")
5567 \f
5568 ;; Define the DImode operations that can be done in a small number
5569 ;; of instructions. The & constraints are to prevent the register
5570 ;; allocator from allocating registers that overlap with the inputs
5571 ;; (for example, having an input in 7,8 and an output in 6,7). We
5572 ;; also allow for the output being the same as one of the inputs.
5574 (define_insn "*adddi3_noppc64"
5575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5576 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5577 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5578 "! TARGET_POWERPC64"
5579 "*
5580 {
5581 if (WORDS_BIG_ENDIAN)
5582 return (GET_CODE (operands[2])) != CONST_INT
5583 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5584 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5585 else
5586 return (GET_CODE (operands[2])) != CONST_INT
5587 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5588 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5589 }"
5590 [(set_attr "type" "two")
5591 (set_attr "length" "8")])
5593 (define_insn "*subdi3_noppc64"
5594 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5595 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5596 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5597 "! TARGET_POWERPC64"
5598 "*
5599 {
5600 if (WORDS_BIG_ENDIAN)
5601 return (GET_CODE (operands[1]) != CONST_INT)
5602 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5603 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5604 else
5605 return (GET_CODE (operands[1]) != CONST_INT)
5606 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5607 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5608 }"
5609 [(set_attr "type" "two")
5610 (set_attr "length" "8")])
5612 (define_insn "*negdi2_noppc64"
5613 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5614 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5615 "! TARGET_POWERPC64"
5616 "*
5617 {
5618 return (WORDS_BIG_ENDIAN)
5619 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5620 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5621 }"
5622 [(set_attr "type" "two")
5623 (set_attr "length" "8")])
5625 (define_expand "mulsidi3"
5626 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5627 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5628 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5629 "! TARGET_POWERPC64"
5630 "
5631 {
5632 if (! TARGET_POWER && ! TARGET_POWERPC)
5633 {
5634 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5635 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5636 emit_insn (gen_mull_call ());
5637 if (WORDS_BIG_ENDIAN)
5638 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5639 else
5640 {
5641 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5642 gen_rtx_REG (SImode, 3));
5643 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5644 gen_rtx_REG (SImode, 4));
5645 }
5646 DONE;
5647 }
5648 else if (TARGET_POWER)
5649 {
5650 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5651 DONE;
5652 }
5653 }")
5655 (define_insn "mulsidi3_mq"
5656 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5657 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5658 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5659 (clobber (match_scratch:SI 3 "=q"))]
5660 "TARGET_POWER"
5661 "mul %0,%1,%2\;mfmq %L0"
5662 [(set_attr "type" "imul")
5663 (set_attr "length" "8")])
5665 (define_insn "*mulsidi3_no_mq"
5666 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5667 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5668 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5669 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5670 "*
5671 {
5672 return (WORDS_BIG_ENDIAN)
5673 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5674 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5675 }"
5676 [(set_attr "type" "imul")
5677 (set_attr "length" "8")])
5679 (define_split
5680 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5681 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5682 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5683 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5684 [(set (match_dup 3)
5685 (truncate:SI
5686 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5687 (sign_extend:DI (match_dup 2)))
5688 (const_int 32))))
5689 (set (match_dup 4)
5690 (mult:SI (match_dup 1)
5691 (match_dup 2)))]
5692 "
5693 {
5694 int endian = (WORDS_BIG_ENDIAN == 0);
5695 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5696 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5697 }")
5699 (define_expand "umulsidi3"
5700 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5701 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5702 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5703 "TARGET_POWERPC && ! TARGET_POWERPC64"
5704 "
5705 {
5706 if (TARGET_POWER)
5707 {
5708 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5709 DONE;
5710 }
5711 }")
5713 (define_insn "umulsidi3_mq"
5714 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5715 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5716 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5717 (clobber (match_scratch:SI 3 "=q"))]
5718 "TARGET_POWERPC && TARGET_POWER"
5719 "*
5720 {
5721 return (WORDS_BIG_ENDIAN)
5722 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5723 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5724 }"
5725 [(set_attr "type" "imul")
5726 (set_attr "length" "8")])
5728 (define_insn "*umulsidi3_no_mq"
5729 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5730 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5731 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5732 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5733 "*
5734 {
5735 return (WORDS_BIG_ENDIAN)
5736 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5737 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5738 }"
5739 [(set_attr "type" "imul")
5740 (set_attr "length" "8")])
5742 (define_split
5743 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5744 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5745 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5746 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5747 [(set (match_dup 3)
5748 (truncate:SI
5749 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5750 (zero_extend:DI (match_dup 2)))
5751 (const_int 32))))
5752 (set (match_dup 4)
5753 (mult:SI (match_dup 1)
5754 (match_dup 2)))]
5755 "
5756 {
5757 int endian = (WORDS_BIG_ENDIAN == 0);
5758 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5759 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5760 }")
5762 (define_expand "smulsi3_highpart"
5763 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5764 (truncate:SI
5765 (lshiftrt:DI (mult:DI (sign_extend:DI
5766 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5767 (sign_extend:DI
5768 (match_operand:SI 2 "gpc_reg_operand" "r")))
5769 (const_int 32))))]
5770 ""
5771 "
5772 {
5773 if (! TARGET_POWER && ! TARGET_POWERPC)
5774 {
5775 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5776 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5777 emit_insn (gen_mulh_call ());
5778 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5779 DONE;
5780 }
5781 else if (TARGET_POWER)
5782 {
5783 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5784 DONE;
5785 }
5786 }")
5788 (define_insn "smulsi3_highpart_mq"
5789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5790 (truncate:SI
5791 (lshiftrt:DI (mult:DI (sign_extend:DI
5792 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5793 (sign_extend:DI
5794 (match_operand:SI 2 "gpc_reg_operand" "r")))
5795 (const_int 32))))
5796 (clobber (match_scratch:SI 3 "=q"))]
5797 "TARGET_POWER"
5798 "mul %0,%1,%2"
5799 [(set_attr "type" "imul")])
5801 (define_insn "*smulsi3_highpart_no_mq"
5802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5803 (truncate:SI
5804 (lshiftrt:DI (mult:DI (sign_extend:DI
5805 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5806 (sign_extend:DI
5807 (match_operand:SI 2 "gpc_reg_operand" "r")))
5808 (const_int 32))))]
5809 "TARGET_POWERPC && ! TARGET_POWER"
5810 "mulhw %0,%1,%2"
5811 [(set_attr "type" "imul")])
5813 (define_expand "umulsi3_highpart"
5814 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5815 (truncate:SI
5816 (lshiftrt:DI (mult:DI (zero_extend:DI
5817 (match_operand:SI 1 "gpc_reg_operand" ""))
5818 (zero_extend:DI
5819 (match_operand:SI 2 "gpc_reg_operand" "")))
5820 (const_int 32))))]
5821 "TARGET_POWERPC"
5822 "
5823 {
5824 if (TARGET_POWER)
5825 {
5826 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5827 DONE;
5828 }
5829 }")
5831 (define_insn "umulsi3_highpart_mq"
5832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5833 (truncate:SI
5834 (lshiftrt:DI (mult:DI (zero_extend:DI
5835 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5836 (zero_extend:DI
5837 (match_operand:SI 2 "gpc_reg_operand" "r")))
5838 (const_int 32))))
5839 (clobber (match_scratch:SI 3 "=q"))]
5840 "TARGET_POWERPC && TARGET_POWER"
5841 "mulhwu %0,%1,%2"
5842 [(set_attr "type" "imul")])
5844 (define_insn "*umulsi3_highpart_no_mq"
5845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5846 (truncate:SI
5847 (lshiftrt:DI (mult:DI (zero_extend:DI
5848 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5849 (zero_extend:DI
5850 (match_operand:SI 2 "gpc_reg_operand" "r")))
5851 (const_int 32))))]
5852 "TARGET_POWERPC && ! TARGET_POWER"
5853 "mulhwu %0,%1,%2"
5854 [(set_attr "type" "imul")])
5856 ;; If operands 0 and 2 are in the same register, we have a problem. But
5857 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5858 ;; why we have the strange constraints below.
5859 (define_insn "ashldi3_power"
5860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5861 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5862 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5863 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5864 "TARGET_POWER"
5865 "@
5866 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5867 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5868 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5869 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5870 [(set_attr "length" "8")])
5872 (define_insn "lshrdi3_power"
5873 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5874 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5875 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5876 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5877 "TARGET_POWER"
5878 "@
5879 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5880 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5881 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5882 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5883 [(set_attr "length" "8")])
5885 ;; Shift by a variable amount is too complex to be worth open-coding. We
5886 ;; just handle shifts by constants.
5887 (define_insn "ashrdi3_power"
5888 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5889 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5890 (match_operand:SI 2 "const_int_operand" "M,i")))
5891 (clobber (match_scratch:SI 3 "=X,q"))]
5892 "TARGET_POWER"
5893 "@
5894 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5895 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5896 [(set_attr "length" "8")])
5898 (define_insn "ashrdi3_no_power"
5899 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5900 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5901 (match_operand:SI 2 "const_int_operand" "M,i")))]
5902 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5903 "@
5904 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5905 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5906 [(set_attr "type" "two,three")
5907 (set_attr "length" "8,12")])
5909 (define_insn "*ashrdisi3_noppc64"
5910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5911 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5912 (const_int 32)) 4))]
5913 "TARGET_32BIT && !TARGET_POWERPC64"
5914 "*
5915 {
5916 if (REGNO (operands[0]) == REGNO (operands[1]))
5917 return \"\";
5918 else
5919 return \"mr %0,%1\";
5920 }"
5921 [(set_attr "length" "4")])
5923 \f
5924 ;; PowerPC64 DImode operations.
5926 (define_insn_and_split "absdi2"
5927 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5928 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5929 (clobber (match_scratch:DI 2 "=&r,&r"))]
5930 "TARGET_POWERPC64"
5931 "#"
5932 "&& reload_completed"
5933 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5934 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5935 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5936 "")
5938 (define_insn_and_split "*nabsdi2"
5939 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5940 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5941 (clobber (match_scratch:DI 2 "=&r,&r"))]
5942 "TARGET_POWERPC64"
5943 "#"
5944 "&& reload_completed"
5945 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5946 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5947 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5948 "")
5950 (define_insn "muldi3"
5951 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5952 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5953 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5954 "TARGET_POWERPC64"
5955 "mulld %0,%1,%2"
5956 [(set_attr "type" "lmul")])
5958 (define_insn "*muldi3_internal1"
5959 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5960 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5961 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5962 (const_int 0)))
5963 (clobber (match_scratch:DI 3 "=r,r"))]
5964 "TARGET_POWERPC64"
5965 "@
5966 mulld. %3,%1,%2
5967 #"
5968 [(set_attr "type" "lmul_compare")
5969 (set_attr "length" "4,8")])
5971 (define_split
5972 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5973 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5974 (match_operand:DI 2 "gpc_reg_operand" ""))
5975 (const_int 0)))
5976 (clobber (match_scratch:DI 3 ""))]
5977 "TARGET_POWERPC64 && reload_completed"
5978 [(set (match_dup 3)
5979 (mult:DI (match_dup 1) (match_dup 2)))
5980 (set (match_dup 0)
5981 (compare:CC (match_dup 3)
5982 (const_int 0)))]
5983 "")
5985 (define_insn "*muldi3_internal2"
5986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5987 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5988 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5989 (const_int 0)))
5990 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5991 (mult:DI (match_dup 1) (match_dup 2)))]
5992 "TARGET_POWERPC64"
5993 "@
5994 mulld. %0,%1,%2
5995 #"
5996 [(set_attr "type" "lmul_compare")
5997 (set_attr "length" "4,8")])
5999 (define_split
6000 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6001 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6002 (match_operand:DI 2 "gpc_reg_operand" ""))
6003 (const_int 0)))
6004 (set (match_operand:DI 0 "gpc_reg_operand" "")
6005 (mult:DI (match_dup 1) (match_dup 2)))]
6006 "TARGET_POWERPC64 && reload_completed"
6007 [(set (match_dup 0)
6008 (mult:DI (match_dup 1) (match_dup 2)))
6009 (set (match_dup 3)
6010 (compare:CC (match_dup 0)
6011 (const_int 0)))]
6012 "")
6014 (define_insn "smuldi3_highpart"
6015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6016 (truncate:DI
6017 (lshiftrt:TI (mult:TI (sign_extend:TI
6018 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6019 (sign_extend:TI
6020 (match_operand:DI 2 "gpc_reg_operand" "r")))
6021 (const_int 64))))]
6022 "TARGET_POWERPC64"
6023 "mulhd %0,%1,%2"
6024 [(set_attr "type" "lmul")])
6026 (define_insn "umuldi3_highpart"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6028 (truncate:DI
6029 (lshiftrt:TI (mult:TI (zero_extend:TI
6030 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6031 (zero_extend:TI
6032 (match_operand:DI 2 "gpc_reg_operand" "r")))
6033 (const_int 64))))]
6034 "TARGET_POWERPC64"
6035 "mulhdu %0,%1,%2"
6036 [(set_attr "type" "lmul")])
6038 (define_insn "rotldi3"
6039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6040 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6041 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6042 "TARGET_POWERPC64"
6043 "rld%I2cl %0,%1,%H2,0")
6045 (define_insn "*rotldi3_internal2"
6046 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6047 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6048 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6049 (const_int 0)))
6050 (clobber (match_scratch:DI 3 "=r,r"))]
6051 "TARGET_64BIT"
6052 "@
6053 rld%I2cl. %3,%1,%H2,0
6054 #"
6055 [(set_attr "type" "delayed_compare")
6056 (set_attr "length" "4,8")])
6058 (define_split
6059 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6060 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6061 (match_operand:DI 2 "reg_or_cint_operand" ""))
6062 (const_int 0)))
6063 (clobber (match_scratch:DI 3 ""))]
6064 "TARGET_POWERPC64 && reload_completed"
6065 [(set (match_dup 3)
6066 (rotate:DI (match_dup 1) (match_dup 2)))
6067 (set (match_dup 0)
6068 (compare:CC (match_dup 3)
6069 (const_int 0)))]
6070 "")
6072 (define_insn "*rotldi3_internal3"
6073 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6074 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6075 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6076 (const_int 0)))
6077 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6078 (rotate:DI (match_dup 1) (match_dup 2)))]
6079 "TARGET_64BIT"
6080 "@
6081 rld%I2cl. %0,%1,%H2,0
6082 #"
6083 [(set_attr "type" "delayed_compare")
6084 (set_attr "length" "4,8")])
6086 (define_split
6087 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6088 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6089 (match_operand:DI 2 "reg_or_cint_operand" ""))
6090 (const_int 0)))
6091 (set (match_operand:DI 0 "gpc_reg_operand" "")
6092 (rotate:DI (match_dup 1) (match_dup 2)))]
6093 "TARGET_POWERPC64 && reload_completed"
6094 [(set (match_dup 0)
6095 (rotate:DI (match_dup 1) (match_dup 2)))
6096 (set (match_dup 3)
6097 (compare:CC (match_dup 0)
6098 (const_int 0)))]
6099 "")
6101 (define_insn "*rotldi3_internal4"
6102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6103 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6104 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6105 (match_operand:DI 3 "mask_operand" "n")))]
6106 "TARGET_POWERPC64"
6107 "rld%I2c%B3 %0,%1,%H2,%S3")
6109 (define_insn "*rotldi3_internal5"
6110 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6111 (compare:CC (and:DI
6112 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6113 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6114 (match_operand:DI 3 "mask_operand" "n,n"))
6115 (const_int 0)))
6116 (clobber (match_scratch:DI 4 "=r,r"))]
6117 "TARGET_64BIT"
6118 "@
6119 rld%I2c%B3. %4,%1,%H2,%S3
6120 #"
6121 [(set_attr "type" "delayed_compare")
6122 (set_attr "length" "4,8")])
6124 (define_split
6125 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6126 (compare:CC (and:DI
6127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6128 (match_operand:DI 2 "reg_or_cint_operand" ""))
6129 (match_operand:DI 3 "mask_operand" ""))
6130 (const_int 0)))
6131 (clobber (match_scratch:DI 4 ""))]
6132 "TARGET_POWERPC64 && reload_completed"
6133 [(set (match_dup 4)
6134 (and:DI (rotate:DI (match_dup 1)
6135 (match_dup 2))
6136 (match_dup 3)))
6137 (set (match_dup 0)
6138 (compare:CC (match_dup 4)
6139 (const_int 0)))]
6140 "")
6142 (define_insn "*rotldi3_internal6"
6143 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6144 (compare:CC (and:DI
6145 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6146 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6147 (match_operand:DI 3 "mask_operand" "n,n"))
6148 (const_int 0)))
6149 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6150 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6151 "TARGET_64BIT"
6152 "@
6153 rld%I2c%B3. %0,%1,%H2,%S3
6154 #"
6155 [(set_attr "type" "delayed_compare")
6156 (set_attr "length" "4,8")])
6158 (define_split
6159 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6160 (compare:CC (and:DI
6161 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6162 (match_operand:DI 2 "reg_or_cint_operand" ""))
6163 (match_operand:DI 3 "mask_operand" ""))
6164 (const_int 0)))
6165 (set (match_operand:DI 0 "gpc_reg_operand" "")
6166 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6167 "TARGET_POWERPC64 && reload_completed"
6168 [(set (match_dup 0)
6169 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6170 (set (match_dup 4)
6171 (compare:CC (match_dup 0)
6172 (const_int 0)))]
6173 "")
6175 (define_insn "*rotldi3_internal7"
6176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6177 (zero_extend:DI
6178 (subreg:QI
6179 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6180 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6181 "TARGET_POWERPC64"
6182 "rld%I2cl %0,%1,%H2,56")
6184 (define_insn "*rotldi3_internal8"
6185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6186 (compare:CC (zero_extend:DI
6187 (subreg:QI
6188 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6189 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6190 (const_int 0)))
6191 (clobber (match_scratch:DI 3 "=r,r"))]
6192 "TARGET_64BIT"
6193 "@
6194 rld%I2cl. %3,%1,%H2,56
6195 #"
6196 [(set_attr "type" "delayed_compare")
6197 (set_attr "length" "4,8")])
6199 (define_split
6200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6201 (compare:CC (zero_extend:DI
6202 (subreg:QI
6203 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6204 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6205 (const_int 0)))
6206 (clobber (match_scratch:DI 3 ""))]
6207 "TARGET_POWERPC64 && reload_completed"
6208 [(set (match_dup 3)
6209 (zero_extend:DI (subreg:QI
6210 (rotate:DI (match_dup 1)
6211 (match_dup 2)) 0)))
6212 (set (match_dup 0)
6213 (compare:CC (match_dup 3)
6214 (const_int 0)))]
6215 "")
6217 (define_insn "*rotldi3_internal9"
6218 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6219 (compare:CC (zero_extend:DI
6220 (subreg:QI
6221 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6222 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6223 (const_int 0)))
6224 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6225 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6226 "TARGET_64BIT"
6227 "@
6228 rld%I2cl. %0,%1,%H2,56
6229 #"
6230 [(set_attr "type" "delayed_compare")
6231 (set_attr "length" "4,8")])
6233 (define_split
6234 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6235 (compare:CC (zero_extend:DI
6236 (subreg:QI
6237 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6238 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6239 (const_int 0)))
6240 (set (match_operand:DI 0 "gpc_reg_operand" "")
6241 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6242 "TARGET_POWERPC64 && reload_completed"
6243 [(set (match_dup 0)
6244 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6245 (set (match_dup 3)
6246 (compare:CC (match_dup 0)
6247 (const_int 0)))]
6248 "")
6250 (define_insn "*rotldi3_internal10"
6251 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6252 (zero_extend:DI
6253 (subreg:HI
6254 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6255 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6256 "TARGET_POWERPC64"
6257 "rld%I2cl %0,%1,%H2,48")
6259 (define_insn "*rotldi3_internal11"
6260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6261 (compare:CC (zero_extend:DI
6262 (subreg:HI
6263 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6264 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6265 (const_int 0)))
6266 (clobber (match_scratch:DI 3 "=r,r"))]
6267 "TARGET_64BIT"
6268 "@
6269 rld%I2cl. %3,%1,%H2,48
6270 #"
6271 [(set_attr "type" "delayed_compare")
6272 (set_attr "length" "4,8")])
6274 (define_split
6275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6276 (compare:CC (zero_extend:DI
6277 (subreg:HI
6278 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6279 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6280 (const_int 0)))
6281 (clobber (match_scratch:DI 3 ""))]
6282 "TARGET_POWERPC64 && reload_completed"
6283 [(set (match_dup 3)
6284 (zero_extend:DI (subreg:HI
6285 (rotate:DI (match_dup 1)
6286 (match_dup 2)) 0)))
6287 (set (match_dup 0)
6288 (compare:CC (match_dup 3)
6289 (const_int 0)))]
6290 "")
6292 (define_insn "*rotldi3_internal12"
6293 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6294 (compare:CC (zero_extend:DI
6295 (subreg:HI
6296 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6297 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6298 (const_int 0)))
6299 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6300 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6301 "TARGET_64BIT"
6302 "@
6303 rld%I2cl. %0,%1,%H2,48
6304 #"
6305 [(set_attr "type" "delayed_compare")
6306 (set_attr "length" "4,8")])
6308 (define_split
6309 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6310 (compare:CC (zero_extend:DI
6311 (subreg:HI
6312 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6313 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6314 (const_int 0)))
6315 (set (match_operand:DI 0 "gpc_reg_operand" "")
6316 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6317 "TARGET_POWERPC64 && reload_completed"
6318 [(set (match_dup 0)
6319 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6320 (set (match_dup 3)
6321 (compare:CC (match_dup 0)
6322 (const_int 0)))]
6323 "")
6325 (define_insn "*rotldi3_internal13"
6326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6327 (zero_extend:DI
6328 (subreg:SI
6329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6330 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6331 "TARGET_POWERPC64"
6332 "rld%I2cl %0,%1,%H2,32")
6334 (define_insn "*rotldi3_internal14"
6335 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6336 (compare:CC (zero_extend:DI
6337 (subreg:SI
6338 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6339 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6340 (const_int 0)))
6341 (clobber (match_scratch:DI 3 "=r,r"))]
6342 "TARGET_64BIT"
6343 "@
6344 rld%I2cl. %3,%1,%H2,32
6345 #"
6346 [(set_attr "type" "delayed_compare")
6347 (set_attr "length" "4,8")])
6349 (define_split
6350 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6351 (compare:CC (zero_extend:DI
6352 (subreg:SI
6353 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6354 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6355 (const_int 0)))
6356 (clobber (match_scratch:DI 3 ""))]
6357 "TARGET_POWERPC64 && reload_completed"
6358 [(set (match_dup 3)
6359 (zero_extend:DI (subreg:SI
6360 (rotate:DI (match_dup 1)
6361 (match_dup 2)) 0)))
6362 (set (match_dup 0)
6363 (compare:CC (match_dup 3)
6364 (const_int 0)))]
6365 "")
6367 (define_insn "*rotldi3_internal15"
6368 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6369 (compare:CC (zero_extend:DI
6370 (subreg:SI
6371 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6372 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6373 (const_int 0)))
6374 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6375 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6376 "TARGET_64BIT"
6377 "@
6378 rld%I2cl. %0,%1,%H2,32
6379 #"
6380 [(set_attr "type" "delayed_compare")
6381 (set_attr "length" "4,8")])
6383 (define_split
6384 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6385 (compare:CC (zero_extend:DI
6386 (subreg:SI
6387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6388 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6389 (const_int 0)))
6390 (set (match_operand:DI 0 "gpc_reg_operand" "")
6391 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6392 "TARGET_POWERPC64 && reload_completed"
6393 [(set (match_dup 0)
6394 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6395 (set (match_dup 3)
6396 (compare:CC (match_dup 0)
6397 (const_int 0)))]
6398 "")
6400 (define_expand "ashldi3"
6401 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6402 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6403 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6404 "TARGET_POWERPC64 || TARGET_POWER"
6405 "
6406 {
6407 if (TARGET_POWERPC64)
6408 ;
6409 else if (TARGET_POWER)
6410 {
6411 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6412 DONE;
6413 }
6414 else
6415 FAIL;
6416 }")
6418 (define_insn "*ashldi3_internal1"
6419 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6420 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6421 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6422 "TARGET_POWERPC64"
6423 "sld%I2 %0,%1,%H2")
6425 (define_insn "*ashldi3_internal2"
6426 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6427 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6428 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6429 (const_int 0)))
6430 (clobber (match_scratch:DI 3 "=r,r"))]
6431 "TARGET_64BIT"
6432 "@
6433 sld%I2. %3,%1,%H2
6434 #"
6435 [(set_attr "type" "delayed_compare")
6436 (set_attr "length" "4,8")])
6438 (define_split
6439 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6440 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6441 (match_operand:SI 2 "reg_or_cint_operand" ""))
6442 (const_int 0)))
6443 (clobber (match_scratch:DI 3 ""))]
6444 "TARGET_POWERPC64 && reload_completed"
6445 [(set (match_dup 3)
6446 (ashift:DI (match_dup 1) (match_dup 2)))
6447 (set (match_dup 0)
6448 (compare:CC (match_dup 3)
6449 (const_int 0)))]
6450 "")
6452 (define_insn "*ashldi3_internal3"
6453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6454 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6455 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6456 (const_int 0)))
6457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6458 (ashift:DI (match_dup 1) (match_dup 2)))]
6459 "TARGET_64BIT"
6460 "@
6461 sld%I2. %0,%1,%H2
6462 #"
6463 [(set_attr "type" "delayed_compare")
6464 (set_attr "length" "4,8")])
6466 (define_split
6467 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6468 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6469 (match_operand:SI 2 "reg_or_cint_operand" ""))
6470 (const_int 0)))
6471 (set (match_operand:DI 0 "gpc_reg_operand" "")
6472 (ashift:DI (match_dup 1) (match_dup 2)))]
6473 "TARGET_POWERPC64 && reload_completed"
6474 [(set (match_dup 0)
6475 (ashift:DI (match_dup 1) (match_dup 2)))
6476 (set (match_dup 3)
6477 (compare:CC (match_dup 0)
6478 (const_int 0)))]
6479 "")
6481 (define_insn "*ashldi3_internal4"
6482 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6483 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6484 (match_operand:SI 2 "const_int_operand" "i"))
6485 (match_operand:DI 3 "const_int_operand" "n")))]
6486 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6487 "rldic %0,%1,%H2,%W3")
6489 (define_insn "ashldi3_internal5"
6490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6491 (compare:CC
6492 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:SI 2 "const_int_operand" "i,i"))
6494 (match_operand:DI 3 "const_int_operand" "n,n"))
6495 (const_int 0)))
6496 (clobber (match_scratch:DI 4 "=r,r"))]
6497 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6498 "@
6499 rldic. %4,%1,%H2,%W3
6500 #"
6501 [(set_attr "type" "delayed_compare")
6502 (set_attr "length" "4,8")])
6504 (define_split
6505 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6506 (compare:CC
6507 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6508 (match_operand:SI 2 "const_int_operand" ""))
6509 (match_operand:DI 3 "const_int_operand" ""))
6510 (const_int 0)))
6511 (clobber (match_scratch:DI 4 ""))]
6512 "TARGET_POWERPC64 && reload_completed
6513 && includes_rldic_lshift_p (operands[2], operands[3])"
6514 [(set (match_dup 4)
6515 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6516 (match_dup 3)))
6517 (set (match_dup 0)
6518 (compare:CC (match_dup 4)
6519 (const_int 0)))]
6520 "")
6522 (define_insn "*ashldi3_internal6"
6523 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6524 (compare:CC
6525 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6526 (match_operand:SI 2 "const_int_operand" "i,i"))
6527 (match_operand:DI 3 "const_int_operand" "n,n"))
6528 (const_int 0)))
6529 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6530 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6531 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6532 "@
6533 rldic. %0,%1,%H2,%W3
6534 #"
6535 [(set_attr "type" "delayed_compare")
6536 (set_attr "length" "4,8")])
6538 (define_split
6539 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6540 (compare:CC
6541 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6542 (match_operand:SI 2 "const_int_operand" ""))
6543 (match_operand:DI 3 "const_int_operand" ""))
6544 (const_int 0)))
6545 (set (match_operand:DI 0 "gpc_reg_operand" "")
6546 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6547 "TARGET_POWERPC64 && reload_completed
6548 && includes_rldic_lshift_p (operands[2], operands[3])"
6549 [(set (match_dup 0)
6550 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6551 (match_dup 3)))
6552 (set (match_dup 4)
6553 (compare:CC (match_dup 0)
6554 (const_int 0)))]
6555 "")
6557 (define_insn "*ashldi3_internal7"
6558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6559 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6560 (match_operand:SI 2 "const_int_operand" "i"))
6561 (match_operand:DI 3 "mask_operand" "n")))]
6562 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6563 "rldicr %0,%1,%H2,%S3")
6565 (define_insn "ashldi3_internal8"
6566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6567 (compare:CC
6568 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6569 (match_operand:SI 2 "const_int_operand" "i,i"))
6570 (match_operand:DI 3 "mask_operand" "n,n"))
6571 (const_int 0)))
6572 (clobber (match_scratch:DI 4 "=r,r"))]
6573 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6574 "@
6575 rldicr. %4,%1,%H2,%S3
6576 #"
6577 [(set_attr "type" "delayed_compare")
6578 (set_attr "length" "4,8")])
6580 (define_split
6581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6582 (compare:CC
6583 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6584 (match_operand:SI 2 "const_int_operand" ""))
6585 (match_operand:DI 3 "mask_operand" ""))
6586 (const_int 0)))
6587 (clobber (match_scratch:DI 4 ""))]
6588 "TARGET_POWERPC64 && reload_completed
6589 && includes_rldicr_lshift_p (operands[2], operands[3])"
6590 [(set (match_dup 4)
6591 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6592 (match_dup 3)))
6593 (set (match_dup 0)
6594 (compare:CC (match_dup 4)
6595 (const_int 0)))]
6596 "")
6598 (define_insn "*ashldi3_internal9"
6599 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6600 (compare:CC
6601 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6602 (match_operand:SI 2 "const_int_operand" "i,i"))
6603 (match_operand:DI 3 "mask_operand" "n,n"))
6604 (const_int 0)))
6605 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6606 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6607 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6608 "@
6609 rldicr. %0,%1,%H2,%S3
6610 #"
6611 [(set_attr "type" "delayed_compare")
6612 (set_attr "length" "4,8")])
6614 (define_split
6615 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6616 (compare:CC
6617 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6618 (match_operand:SI 2 "const_int_operand" ""))
6619 (match_operand:DI 3 "mask_operand" ""))
6620 (const_int 0)))
6621 (set (match_operand:DI 0 "gpc_reg_operand" "")
6622 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6623 "TARGET_POWERPC64 && reload_completed
6624 && includes_rldicr_lshift_p (operands[2], operands[3])"
6625 [(set (match_dup 0)
6626 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6627 (match_dup 3)))
6628 (set (match_dup 4)
6629 (compare:CC (match_dup 0)
6630 (const_int 0)))]
6631 "")
6633 (define_expand "lshrdi3"
6634 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6636 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6637 "TARGET_POWERPC64 || TARGET_POWER"
6638 "
6639 {
6640 if (TARGET_POWERPC64)
6641 ;
6642 else if (TARGET_POWER)
6643 {
6644 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6645 DONE;
6646 }
6647 else
6648 FAIL;
6649 }")
6651 (define_insn "*lshrdi3_internal1"
6652 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6653 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6654 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6655 "TARGET_POWERPC64"
6656 "srd%I2 %0,%1,%H2")
6658 (define_insn "*lshrdi3_internal2"
6659 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6660 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6661 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 "=r,r"))]
6664 "TARGET_64BIT "
6665 "@
6666 srd%I2. %3,%1,%H2
6667 #"
6668 [(set_attr "type" "delayed_compare")
6669 (set_attr "length" "4,8")])
6671 (define_split
6672 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6673 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:SI 2 "reg_or_cint_operand" ""))
6675 (const_int 0)))
6676 (clobber (match_scratch:DI 3 ""))]
6677 "TARGET_POWERPC64 && reload_completed"
6678 [(set (match_dup 3)
6679 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6680 (set (match_dup 0)
6681 (compare:CC (match_dup 3)
6682 (const_int 0)))]
6683 "")
6685 (define_insn "*lshrdi3_internal3"
6686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6687 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6688 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6689 (const_int 0)))
6690 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6691 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6692 "TARGET_64BIT"
6693 "@
6694 srd%I2. %0,%1,%H2
6695 #"
6696 [(set_attr "type" "delayed_compare")
6697 (set_attr "length" "4,8")])
6699 (define_split
6700 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6701 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6702 (match_operand:SI 2 "reg_or_cint_operand" ""))
6703 (const_int 0)))
6704 (set (match_operand:DI 0 "gpc_reg_operand" "")
6705 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6706 "TARGET_POWERPC64 && reload_completed"
6707 [(set (match_dup 0)
6708 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6709 (set (match_dup 3)
6710 (compare:CC (match_dup 0)
6711 (const_int 0)))]
6712 "")
6714 (define_expand "ashrdi3"
6715 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6716 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6717 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6718 "WORDS_BIG_ENDIAN"
6719 "
6720 {
6721 if (TARGET_POWERPC64)
6722 ;
6723 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6724 {
6725 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6726 DONE;
6727 }
6728 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6729 && WORDS_BIG_ENDIAN)
6730 {
6731 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6732 DONE;
6733 }
6734 else
6735 FAIL;
6736 }")
6738 (define_insn "*ashrdi3_internal1"
6739 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6740 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6741 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6742 "TARGET_POWERPC64"
6743 "srad%I2 %0,%1,%H2")
6745 (define_insn "*ashrdi3_internal2"
6746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6747 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6748 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6749 (const_int 0)))
6750 (clobber (match_scratch:DI 3 "=r,r"))]
6751 "TARGET_64BIT"
6752 "@
6753 srad%I2. %3,%1,%H2
6754 #"
6755 [(set_attr "type" "delayed_compare")
6756 (set_attr "length" "4,8")])
6758 (define_split
6759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6760 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6761 (match_operand:SI 2 "reg_or_cint_operand" ""))
6762 (const_int 0)))
6763 (clobber (match_scratch:DI 3 ""))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 3)
6766 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 0)
6768 (compare:CC (match_dup 3)
6769 (const_int 0)))]
6770 "")
6772 (define_insn "*ashrdi3_internal3"
6773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6774 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6776 (const_int 0)))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6778 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6779 "TARGET_64BIT"
6780 "@
6781 srad%I2. %0,%1,%H2
6782 #"
6783 [(set_attr "type" "delayed_compare")
6784 (set_attr "length" "4,8")])
6786 (define_split
6787 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6788 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6789 (match_operand:SI 2 "reg_or_cint_operand" ""))
6790 (const_int 0)))
6791 (set (match_operand:DI 0 "gpc_reg_operand" "")
6792 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6793 "TARGET_POWERPC64 && reload_completed"
6794 [(set (match_dup 0)
6795 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6796 (set (match_dup 3)
6797 (compare:CC (match_dup 0)
6798 (const_int 0)))]
6799 "")
6801 (define_insn "anddi3"
6802 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6803 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6804 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6805 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6806 "TARGET_POWERPC64"
6807 "@
6808 and %0,%1,%2
6809 rldic%B2 %0,%1,0,%S2
6810 rlwinm %0,%1,0,%m2,%M2
6811 andi. %0,%1,%b2
6812 andis. %0,%1,%u2
6813 #"
6814 [(set_attr "type" "*,*,*,compare,compare,*")
6815 (set_attr "length" "4,4,4,4,4,8")])
6817 (define_split
6818 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6819 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6820 (match_operand:DI 2 "mask64_2_operand" "")))
6821 (clobber (match_scratch:CC 3 ""))]
6822 "TARGET_POWERPC64
6823 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6824 && !mask_operand (operands[2], DImode)"
6825 [(set (match_dup 0)
6826 (and:DI (rotate:DI (match_dup 1)
6827 (match_dup 4))
6828 (match_dup 5)))
6829 (set (match_dup 0)
6830 (and:DI (rotate:DI (match_dup 0)
6831 (match_dup 6))
6832 (match_dup 7)))]
6833 {
6834 build_mask64_2_operands (operands[2], &operands[4]);
6835 })
6837 (define_insn "*anddi3_internal2"
6838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6839 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6840 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6841 (const_int 0)))
6842 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6843 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6844 "TARGET_64BIT"
6845 "@
6846 and. %3,%1,%2
6847 rldic%B2. %3,%1,0,%S2
6848 andi. %3,%1,%b2
6849 andis. %3,%1,%u2
6850 #
6851 #
6852 #
6853 #
6854 #
6855 #"
6856 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6857 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6859 (define_split
6860 [(set (match_operand:CC 0 "cc_reg_operand" "")
6861 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6862 (match_operand:DI 2 "mask64_2_operand" ""))
6863 (const_int 0)))
6864 (clobber (match_scratch:DI 3 ""))
6865 (clobber (match_scratch:CC 4 ""))]
6866 "TARGET_POWERPC64 && reload_completed
6867 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6868 && !mask_operand (operands[2], DImode)"
6869 [(set (match_dup 3)
6870 (and:DI (rotate:DI (match_dup 1)
6871 (match_dup 5))
6872 (match_dup 6)))
6873 (parallel [(set (match_dup 0)
6874 (compare:CC (and:DI (rotate:DI (match_dup 3)
6875 (match_dup 7))
6876 (match_dup 8))
6877 (const_int 0)))
6878 (clobber (match_dup 3))])]
6879 "
6880 {
6881 build_mask64_2_operands (operands[2], &operands[5]);
6882 }")
6884 (define_insn "*anddi3_internal3"
6885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6886 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6887 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6888 (const_int 0)))
6889 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6890 (and:DI (match_dup 1) (match_dup 2)))
6891 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6892 "TARGET_64BIT"
6893 "@
6894 and. %0,%1,%2
6895 rldic%B2. %0,%1,0,%S2
6896 andi. %0,%1,%b2
6897 andis. %0,%1,%u2
6898 #
6899 #
6900 #
6901 #
6902 #
6903 #"
6904 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6905 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6907 (define_split
6908 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6909 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:DI 2 "and_operand" ""))
6911 (const_int 0)))
6912 (set (match_operand:DI 0 "gpc_reg_operand" "")
6913 (and:DI (match_dup 1) (match_dup 2)))
6914 (clobber (match_scratch:CC 4 ""))]
6915 "TARGET_POWERPC64 && reload_completed"
6916 [(parallel [(set (match_dup 0)
6917 (and:DI (match_dup 1) (match_dup 2)))
6918 (clobber (match_dup 4))])
6919 (set (match_dup 3)
6920 (compare:CC (match_dup 0)
6921 (const_int 0)))]
6922 "")
6924 (define_split
6925 [(set (match_operand:CC 3 "cc_reg_operand" "")
6926 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6927 (match_operand:DI 2 "mask64_2_operand" ""))
6928 (const_int 0)))
6929 (set (match_operand:DI 0 "gpc_reg_operand" "")
6930 (and:DI (match_dup 1) (match_dup 2)))
6931 (clobber (match_scratch:CC 4 ""))]
6932 "TARGET_POWERPC64 && reload_completed
6933 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6934 && !mask_operand (operands[2], DImode)"
6935 [(set (match_dup 0)
6936 (and:DI (rotate:DI (match_dup 1)
6937 (match_dup 5))
6938 (match_dup 6)))
6939 (parallel [(set (match_dup 3)
6940 (compare:CC (and:DI (rotate:DI (match_dup 0)
6941 (match_dup 7))
6942 (match_dup 8))
6943 (const_int 0)))
6944 (set (match_dup 0)
6945 (and:DI (rotate:DI (match_dup 0)
6946 (match_dup 7))
6947 (match_dup 8)))])]
6948 "
6949 {
6950 build_mask64_2_operands (operands[2], &operands[5]);
6951 }")
6953 (define_expand "iordi3"
6954 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6955 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6956 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6957 "TARGET_POWERPC64"
6958 "
6959 {
6960 if (non_logical_cint_operand (operands[2], DImode))
6961 {
6962 HOST_WIDE_INT value;
6963 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6964 ? operands[0] : gen_reg_rtx (DImode));
6966 if (GET_CODE (operands[2]) == CONST_INT)
6967 {
6968 value = INTVAL (operands[2]);
6969 emit_insn (gen_iordi3 (tmp, operands[1],
6970 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6971 }
6972 else
6973 {
6974 value = CONST_DOUBLE_LOW (operands[2]);
6975 emit_insn (gen_iordi3 (tmp, operands[1],
6976 immed_double_const (value
6977 & (~ (HOST_WIDE_INT) 0xffff),
6978 0, DImode)));
6979 }
6981 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6982 DONE;
6983 }
6984 }")
6986 (define_expand "xordi3"
6987 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6988 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6989 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6990 "TARGET_POWERPC64"
6991 "
6992 {
6993 if (non_logical_cint_operand (operands[2], DImode))
6994 {
6995 HOST_WIDE_INT value;
6996 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6997 ? operands[0] : gen_reg_rtx (DImode));
6999 if (GET_CODE (operands[2]) == CONST_INT)
7000 {
7001 value = INTVAL (operands[2]);
7002 emit_insn (gen_xordi3 (tmp, operands[1],
7003 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7004 }
7005 else
7006 {
7007 value = CONST_DOUBLE_LOW (operands[2]);
7008 emit_insn (gen_xordi3 (tmp, operands[1],
7009 immed_double_const (value
7010 & (~ (HOST_WIDE_INT) 0xffff),
7011 0, DImode)));
7012 }
7014 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7015 DONE;
7016 }
7017 }")
7019 (define_insn "*booldi3_internal1"
7020 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7021 (match_operator:DI 3 "boolean_or_operator"
7022 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7023 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7024 "TARGET_POWERPC64"
7025 "@
7026 %q3 %0,%1,%2
7027 %q3i %0,%1,%b2
7028 %q3is %0,%1,%u2")
7030 (define_insn "*booldi3_internal2"
7031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7032 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7033 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7034 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7035 (const_int 0)))
7036 (clobber (match_scratch:DI 3 "=r,r"))]
7037 "TARGET_64BIT"
7038 "@
7039 %q4. %3,%1,%2
7040 #"
7041 [(set_attr "type" "compare")
7042 (set_attr "length" "4,8")])
7044 (define_split
7045 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7046 (compare:CC (match_operator:DI 4 "boolean_operator"
7047 [(match_operand:DI 1 "gpc_reg_operand" "")
7048 (match_operand:DI 2 "gpc_reg_operand" "")])
7049 (const_int 0)))
7050 (clobber (match_scratch:DI 3 ""))]
7051 "TARGET_POWERPC64 && reload_completed"
7052 [(set (match_dup 3) (match_dup 4))
7053 (set (match_dup 0)
7054 (compare:CC (match_dup 3)
7055 (const_int 0)))]
7056 "")
7058 (define_insn "*booldi3_internal3"
7059 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7060 (compare:CC (match_operator:DI 4 "boolean_operator"
7061 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7062 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7063 (const_int 0)))
7064 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7065 (match_dup 4))]
7066 "TARGET_64BIT"
7067 "@
7068 %q4. %0,%1,%2
7069 #"
7070 [(set_attr "type" "compare")
7071 (set_attr "length" "4,8")])
7073 (define_split
7074 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7075 (compare:CC (match_operator:DI 4 "boolean_operator"
7076 [(match_operand:DI 1 "gpc_reg_operand" "")
7077 (match_operand:DI 2 "gpc_reg_operand" "")])
7078 (const_int 0)))
7079 (set (match_operand:DI 0 "gpc_reg_operand" "")
7080 (match_dup 4))]
7081 "TARGET_POWERPC64 && reload_completed"
7082 [(set (match_dup 0) (match_dup 4))
7083 (set (match_dup 3)
7084 (compare:CC (match_dup 0)
7085 (const_int 0)))]
7086 "")
7088 ;; Split a logical operation that we can't do in one insn into two insns,
7089 ;; each of which does one 16-bit part. This is used by combine.
7091 (define_split
7092 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7093 (match_operator:DI 3 "boolean_or_operator"
7094 [(match_operand:DI 1 "gpc_reg_operand" "")
7095 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7096 "TARGET_POWERPC64"
7097 [(set (match_dup 0) (match_dup 4))
7098 (set (match_dup 0) (match_dup 5))]
7099 "
7100 {
7101 rtx i3,i4;
7103 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7104 {
7105 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7106 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7107 0, DImode);
7108 i4 = GEN_INT (value & 0xffff);
7109 }
7110 else
7111 {
7112 i3 = GEN_INT (INTVAL (operands[2])
7113 & (~ (HOST_WIDE_INT) 0xffff));
7114 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7115 }
7116 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7117 operands[1], i3);
7118 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7119 operands[0], i4);
7120 }")
7122 (define_insn "*boolcdi3_internal1"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7124 (match_operator:DI 3 "boolean_operator"
7125 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7126 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7127 "TARGET_POWERPC64"
7128 "%q3 %0,%2,%1")
7130 (define_insn "*boolcdi3_internal2"
7131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7132 (compare:CC (match_operator:DI 4 "boolean_operator"
7133 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7134 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7135 (const_int 0)))
7136 (clobber (match_scratch:DI 3 "=r,r"))]
7137 "TARGET_64BIT"
7138 "@
7139 %q4. %3,%2,%1
7140 #"
7141 [(set_attr "type" "compare")
7142 (set_attr "length" "4,8")])
7144 (define_split
7145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7146 (compare:CC (match_operator:DI 4 "boolean_operator"
7147 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7148 (match_operand:DI 2 "gpc_reg_operand" "")])
7149 (const_int 0)))
7150 (clobber (match_scratch:DI 3 ""))]
7151 "TARGET_POWERPC64 && reload_completed"
7152 [(set (match_dup 3) (match_dup 4))
7153 (set (match_dup 0)
7154 (compare:CC (match_dup 3)
7155 (const_int 0)))]
7156 "")
7158 (define_insn "*boolcdi3_internal3"
7159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7160 (compare:CC (match_operator:DI 4 "boolean_operator"
7161 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7162 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7163 (const_int 0)))
7164 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7165 (match_dup 4))]
7166 "TARGET_64BIT"
7167 "@
7168 %q4. %0,%2,%1
7169 #"
7170 [(set_attr "type" "compare")
7171 (set_attr "length" "4,8")])
7173 (define_split
7174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7175 (compare:CC (match_operator:DI 4 "boolean_operator"
7176 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7177 (match_operand:DI 2 "gpc_reg_operand" "")])
7178 (const_int 0)))
7179 (set (match_operand:DI 0 "gpc_reg_operand" "")
7180 (match_dup 4))]
7181 "TARGET_POWERPC64 && reload_completed"
7182 [(set (match_dup 0) (match_dup 4))
7183 (set (match_dup 3)
7184 (compare:CC (match_dup 0)
7185 (const_int 0)))]
7186 "")
7188 (define_insn "*boolccdi3_internal1"
7189 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7190 (match_operator:DI 3 "boolean_operator"
7191 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7192 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7193 "TARGET_POWERPC64"
7194 "%q3 %0,%1,%2")
7196 (define_insn "*boolccdi3_internal2"
7197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7198 (compare:CC (match_operator:DI 4 "boolean_operator"
7199 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7200 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7201 (const_int 0)))
7202 (clobber (match_scratch:DI 3 "=r,r"))]
7203 "TARGET_64BIT"
7204 "@
7205 %q4. %3,%1,%2
7206 #"
7207 [(set_attr "type" "compare")
7208 (set_attr "length" "4,8")])
7210 (define_split
7211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7212 (compare:CC (match_operator:DI 4 "boolean_operator"
7213 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7214 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7215 (const_int 0)))
7216 (clobber (match_scratch:DI 3 ""))]
7217 "TARGET_POWERPC64 && reload_completed"
7218 [(set (match_dup 3) (match_dup 4))
7219 (set (match_dup 0)
7220 (compare:CC (match_dup 3)
7221 (const_int 0)))]
7222 "")
7224 (define_insn "*boolccdi3_internal3"
7225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7226 (compare:CC (match_operator:DI 4 "boolean_operator"
7227 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7228 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7229 (const_int 0)))
7230 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7231 (match_dup 4))]
7232 "TARGET_64BIT"
7233 "@
7234 %q4. %0,%1,%2
7235 #"
7236 [(set_attr "type" "compare")
7237 (set_attr "length" "4,8")])
7239 (define_split
7240 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7241 (compare:CC (match_operator:DI 4 "boolean_operator"
7242 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7243 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7244 (const_int 0)))
7245 (set (match_operand:DI 0 "gpc_reg_operand" "")
7246 (match_dup 4))]
7247 "TARGET_POWERPC64 && reload_completed"
7248 [(set (match_dup 0) (match_dup 4))
7249 (set (match_dup 3)
7250 (compare:CC (match_dup 0)
7251 (const_int 0)))]
7252 "")
7253 \f
7254 ;; Now define ways of moving data around.
7256 ;; Set up a register with a value from the GOT table
7258 (define_expand "movsi_got"
7259 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7260 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7261 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7262 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7263 "
7264 {
7265 if (GET_CODE (operands[1]) == CONST)
7266 {
7267 rtx offset = const0_rtx;
7268 HOST_WIDE_INT value;
7270 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7271 value = INTVAL (offset);
7272 if (value != 0)
7273 {
7274 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7275 emit_insn (gen_movsi_got (tmp, operands[1]));
7276 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7277 DONE;
7278 }
7279 }
7281 operands[2] = rs6000_got_register (operands[1]);
7282 }")
7284 (define_insn "*movsi_got_internal"
7285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7286 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7287 (match_operand:SI 2 "gpc_reg_operand" "b")]
7288 UNSPEC_MOVSI_GOT))]
7289 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7290 "{l|lwz} %0,%a1@got(%2)"
7291 [(set_attr "type" "load")])
7293 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7294 ;; didn't get allocated to a hard register.
7295 (define_split
7296 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7297 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7298 (match_operand:SI 2 "memory_operand" "")]
7299 UNSPEC_MOVSI_GOT))]
7300 "DEFAULT_ABI == ABI_V4
7301 && flag_pic == 1
7302 && (reload_in_progress || reload_completed)"
7303 [(set (match_dup 0) (match_dup 2))
7304 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7305 UNSPEC_MOVSI_GOT))]
7306 "")
7308 ;; For SI, we special-case integers that can't be loaded in one insn. We
7309 ;; do the load 16-bits at a time. We could do this by loading from memory,
7310 ;; and this is even supposed to be faster, but it is simpler not to get
7311 ;; integers in the TOC.
7312 (define_insn "movsi_low"
7313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7314 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7315 (match_operand 2 "" ""))))]
7316 "TARGET_MACHO && ! TARGET_64BIT"
7317 "{l|lwz} %0,lo16(%2)(%1)"
7318 [(set_attr "type" "load")
7319 (set_attr "length" "4")])
7321 (define_insn "*movsi_internal1"
7322 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7323 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7324 "gpc_reg_operand (operands[0], SImode)
7325 || gpc_reg_operand (operands[1], SImode)"
7326 "@
7327 mr %0,%1
7328 {cal|la} %0,%a1
7329 {l%U1%X1|lwz%U1%X1} %0,%1
7330 {st%U0%X0|stw%U0%X0} %1,%0
7331 {lil|li} %0,%1
7332 {liu|lis} %0,%v1
7333 #
7334 {cal|la} %0,%a1
7335 mf%1 %0
7336 mt%0 %1
7337 mt%0 %1
7338 mt%0 %1
7339 {cror 0,0,0|nop}"
7340 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7341 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7343 ;; Split a load of a large constant into the appropriate two-insn
7344 ;; sequence.
7346 (define_split
7347 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7348 (match_operand:SI 1 "const_int_operand" ""))]
7349 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7350 && (INTVAL (operands[1]) & 0xffff) != 0"
7351 [(set (match_dup 0)
7352 (match_dup 2))
7353 (set (match_dup 0)
7354 (ior:SI (match_dup 0)
7355 (match_dup 3)))]
7356 "
7357 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7359 if (tem == operands[0])
7360 DONE;
7361 else
7362 FAIL;
7363 }")
7365 (define_insn "*mov<mode>_internal2"
7366 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7367 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7368 (const_int 0)))
7369 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7370 ""
7371 "@
7372 {cmpi|cmp<wd>i} %2,%0,0
7373 mr. %0,%1
7374 #"
7375 [(set_attr "type" "cmp,compare,cmp")
7376 (set_attr "length" "4,4,8")])
7378 (define_split
7379 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7380 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7381 (const_int 0)))
7382 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7383 "reload_completed"
7384 [(set (match_dup 0) (match_dup 1))
7385 (set (match_dup 2)
7386 (compare:CC (match_dup 0)
7387 (const_int 0)))]
7388 "")
7389 \f
7390 (define_insn "*movhi_internal"
7391 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7392 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7393 "gpc_reg_operand (operands[0], HImode)
7394 || gpc_reg_operand (operands[1], HImode)"
7395 "@
7396 mr %0,%1
7397 lhz%U1%X1 %0,%1
7398 sth%U0%X0 %1,%0
7399 {lil|li} %0,%w1
7400 mf%1 %0
7401 mt%0 %1
7402 mt%0 %1
7403 {cror 0,0,0|nop}"
7404 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7406 (define_expand "mov<mode>"
7407 [(set (match_operand:INT 0 "general_operand" "")
7408 (match_operand:INT 1 "any_operand" ""))]
7409 ""
7410 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7412 (define_insn "*movqi_internal"
7413 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7414 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7415 "gpc_reg_operand (operands[0], QImode)
7416 || gpc_reg_operand (operands[1], QImode)"
7417 "@
7418 mr %0,%1
7419 lbz%U1%X1 %0,%1
7420 stb%U0%X0 %1,%0
7421 {lil|li} %0,%1
7422 mf%1 %0
7423 mt%0 %1
7424 mt%0 %1
7425 {cror 0,0,0|nop}"
7426 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7427 \f
7428 ;; Here is how to move condition codes around. When we store CC data in
7429 ;; an integer register or memory, we store just the high-order 4 bits.
7430 ;; This lets us not shift in the most common case of CR0.
7431 (define_expand "movcc"
7432 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7433 (match_operand:CC 1 "nonimmediate_operand" ""))]
7434 ""
7435 "")
7437 (define_insn "*movcc_internal1"
7438 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7439 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7440 "register_operand (operands[0], CCmode)
7441 || register_operand (operands[1], CCmode)"
7442 "@
7443 mcrf %0,%1
7444 mtcrf 128,%1
7445 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7446 mfcr %0%Q1
7447 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7448 mr %0,%1
7449 mf%1 %0
7450 mt%0 %1
7451 mt%0 %1
7452 {l%U1%X1|lwz%U1%X1} %0,%1
7453 {st%U0%U1|stw%U0%U1} %1,%0"
7454 [(set (attr "type")
7455 (cond [(eq_attr "alternative" "0")
7456 (const_string "cr_logical")
7457 (eq_attr "alternative" "1,2")
7458 (const_string "mtcr")
7459 (eq_attr "alternative" "5,7")
7460 (const_string "integer")
7461 (eq_attr "alternative" "6")
7462 (const_string "mfjmpr")
7463 (eq_attr "alternative" "8")
7464 (const_string "mtjmpr")
7465 (eq_attr "alternative" "9")
7466 (const_string "load")
7467 (eq_attr "alternative" "10")
7468 (const_string "store")
7469 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7470 (const_string "mfcrf")
7471 ]
7472 (const_string "mfcr")))
7473 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7474 \f
7475 ;; For floating-point, we normally deal with the floating-point registers
7476 ;; unless -msoft-float is used. The sole exception is that parameter passing
7477 ;; can produce floating-point values in fixed-point registers. Unless the
7478 ;; value is a simple constant or already in memory, we deal with this by
7479 ;; allocating memory and copying the value explicitly via that memory location.
7480 (define_expand "movsf"
7481 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7482 (match_operand:SF 1 "any_operand" ""))]
7483 ""
7484 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7486 (define_split
7487 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7488 (match_operand:SF 1 "const_double_operand" ""))]
7489 "reload_completed
7490 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7491 || (GET_CODE (operands[0]) == SUBREG
7492 && GET_CODE (SUBREG_REG (operands[0])) == REG
7493 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7494 [(set (match_dup 2) (match_dup 3))]
7495 "
7496 {
7497 long l;
7498 REAL_VALUE_TYPE rv;
7500 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7501 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7503 if (! TARGET_POWERPC64)
7504 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7505 else
7506 operands[2] = gen_lowpart (SImode, operands[0]);
7508 operands[3] = gen_int_mode (l, SImode);
7509 }")
7511 (define_insn "*movsf_hardfloat"
7512 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7513 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7514 "(gpc_reg_operand (operands[0], SFmode)
7515 || gpc_reg_operand (operands[1], SFmode))
7516 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7517 "@
7518 mr %0,%1
7519 {l%U1%X1|lwz%U1%X1} %0,%1
7520 {st%U0%X0|stw%U0%X0} %1,%0
7521 fmr %0,%1
7522 lfs%U1%X1 %0,%1
7523 stfs%U0%X0 %1,%0
7524 mt%0 %1
7525 mt%0 %1
7526 mf%1 %0
7527 {cror 0,0,0|nop}
7528 #
7529 #"
7530 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7531 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7533 (define_insn "*movsf_softfloat"
7534 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7535 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7536 "(gpc_reg_operand (operands[0], SFmode)
7537 || gpc_reg_operand (operands[1], SFmode))
7538 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7539 "@
7540 mr %0,%1
7541 mt%0 %1
7542 mt%0 %1
7543 mf%1 %0
7544 {l%U1%X1|lwz%U1%X1} %0,%1
7545 {st%U0%X0|stw%U0%X0} %1,%0
7546 {lil|li} %0,%1
7547 {liu|lis} %0,%v1
7548 {cal|la} %0,%a1
7549 #
7550 #
7551 {cror 0,0,0|nop}"
7552 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7553 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7555 \f
7556 (define_expand "movdf"
7557 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7558 (match_operand:DF 1 "any_operand" ""))]
7559 ""
7560 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7562 (define_split
7563 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7564 (match_operand:DF 1 "const_int_operand" ""))]
7565 "! TARGET_POWERPC64 && reload_completed
7566 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7567 || (GET_CODE (operands[0]) == SUBREG
7568 && GET_CODE (SUBREG_REG (operands[0])) == REG
7569 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7570 [(set (match_dup 2) (match_dup 4))
7571 (set (match_dup 3) (match_dup 1))]
7572 "
7573 {
7574 int endian = (WORDS_BIG_ENDIAN == 0);
7575 HOST_WIDE_INT value = INTVAL (operands[1]);
7577 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7578 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7579 #if HOST_BITS_PER_WIDE_INT == 32
7580 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7581 #else
7582 operands[4] = GEN_INT (value >> 32);
7583 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7584 #endif
7585 }")
7587 (define_split
7588 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7589 (match_operand:DF 1 "const_double_operand" ""))]
7590 "! TARGET_POWERPC64 && reload_completed
7591 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7592 || (GET_CODE (operands[0]) == SUBREG
7593 && GET_CODE (SUBREG_REG (operands[0])) == REG
7594 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7595 [(set (match_dup 2) (match_dup 4))
7596 (set (match_dup 3) (match_dup 5))]
7597 "
7598 {
7599 int endian = (WORDS_BIG_ENDIAN == 0);
7600 long l[2];
7601 REAL_VALUE_TYPE rv;
7603 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7604 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7606 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7607 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7608 operands[4] = gen_int_mode (l[endian], SImode);
7609 operands[5] = gen_int_mode (l[1 - endian], SImode);
7610 }")
7612 (define_split
7613 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7614 (match_operand:DF 1 "easy_fp_constant" ""))]
7615 "TARGET_POWERPC64 && reload_completed
7616 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7617 || (GET_CODE (operands[0]) == SUBREG
7618 && GET_CODE (SUBREG_REG (operands[0])) == REG
7619 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7620 [(set (match_dup 2) (match_dup 3))]
7621 "
7622 {
7623 int endian = (WORDS_BIG_ENDIAN == 0);
7624 long l[2];
7625 REAL_VALUE_TYPE rv;
7626 #if HOST_BITS_PER_WIDE_INT >= 64
7627 HOST_WIDE_INT val;
7628 #endif
7630 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7631 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7633 operands[2] = gen_lowpart (DImode, operands[0]);
7634 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7635 #if HOST_BITS_PER_WIDE_INT >= 64
7636 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7637 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7639 operands[3] = gen_int_mode (val, DImode);
7640 #else
7641 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7642 #endif
7643 }")
7645 ;; Don't have reload use general registers to load a constant. First,
7646 ;; it might not work if the output operand is the equivalent of
7647 ;; a non-offsettable memref, but also it is less efficient than loading
7648 ;; the constant into an FP register, since it will probably be used there.
7649 ;; The "??" is a kludge until we can figure out a more reasonable way
7650 ;; of handling these non-offsettable values.
7651 (define_insn "*movdf_hardfloat32"
7652 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7653 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7654 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7655 && (gpc_reg_operand (operands[0], DFmode)
7656 || gpc_reg_operand (operands[1], DFmode))"
7657 "*
7658 {
7659 switch (which_alternative)
7660 {
7661 default:
7662 gcc_unreachable ();
7663 case 0:
7664 /* We normally copy the low-numbered register first. However, if
7665 the first register operand 0 is the same as the second register
7666 of operand 1, we must copy in the opposite order. */
7667 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7668 return \"mr %L0,%L1\;mr %0,%1\";
7669 else
7670 return \"mr %0,%1\;mr %L0,%L1\";
7671 case 1:
7672 if (GET_CODE (operands[1]) == MEM
7673 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7674 reload_completed || reload_in_progress)
7675 || GET_CODE (XEXP (operands[1], 0)) == REG
7676 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7677 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7678 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7679 {
7680 /* If the low-address word is used in the address, we must load
7681 it last. Otherwise, load it first. Note that we cannot have
7682 auto-increment in that case since the address register is
7683 known to be dead. */
7684 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7685 operands[1], 0))
7686 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7687 else
7688 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7689 }
7690 else
7691 {
7692 rtx addreg;
7694 addreg = find_addr_reg (XEXP (operands[1], 0));
7695 if (refers_to_regno_p (REGNO (operands[0]),
7696 REGNO (operands[0]) + 1,
7697 operands[1], 0))
7698 {
7699 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7700 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7701 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7702 return \"{lx|lwzx} %0,%1\";
7703 }
7704 else
7705 {
7706 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7707 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7708 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7709 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7710 return \"\";
7711 }
7712 }
7713 case 2:
7714 if (GET_CODE (operands[0]) == MEM
7715 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7716 reload_completed || reload_in_progress)
7717 || GET_CODE (XEXP (operands[0], 0)) == REG
7718 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7719 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7720 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7721 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7722 else
7723 {
7724 rtx addreg;
7726 addreg = find_addr_reg (XEXP (operands[0], 0));
7727 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7728 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7729 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7730 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7731 return \"\";
7732 }
7733 case 3:
7734 return \"fmr %0,%1\";
7735 case 4:
7736 return \"lfd%U1%X1 %0,%1\";
7737 case 5:
7738 return \"stfd%U0%X0 %1,%0\";
7739 case 6:
7740 case 7:
7741 case 8:
7742 return \"#\";
7743 }
7744 }"
7745 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7746 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7748 (define_insn "*movdf_softfloat32"
7749 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7750 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7751 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7752 && (gpc_reg_operand (operands[0], DFmode)
7753 || gpc_reg_operand (operands[1], DFmode))"
7754 "*
7755 {
7756 switch (which_alternative)
7757 {
7758 default:
7759 gcc_unreachable ();
7760 case 0:
7761 /* We normally copy the low-numbered register first. However, if
7762 the first register operand 0 is the same as the second register of
7763 operand 1, we must copy in the opposite order. */
7764 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7765 return \"mr %L0,%L1\;mr %0,%1\";
7766 else
7767 return \"mr %0,%1\;mr %L0,%L1\";
7768 case 1:
7769 /* If the low-address word is used in the address, we must load
7770 it last. Otherwise, load it first. Note that we cannot have
7771 auto-increment in that case since the address register is
7772 known to be dead. */
7773 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7774 operands[1], 0))
7775 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7776 else
7777 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7778 case 2:
7779 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7780 case 3:
7781 case 4:
7782 case 5:
7783 return \"#\";
7784 }
7785 }"
7786 [(set_attr "type" "two,load,store,*,*,*")
7787 (set_attr "length" "8,8,8,8,12,16")])
7789 ; ld/std require word-aligned displacements -> 'Y' constraint.
7790 ; List Y->r and r->Y before r->r for reload.
7791 (define_insn "*movdf_hardfloat64"
7792 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7793 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7794 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7795 && (gpc_reg_operand (operands[0], DFmode)
7796 || gpc_reg_operand (operands[1], DFmode))"
7797 "@
7798 std%U0%X0 %1,%0
7799 ld%U1%X1 %0,%1
7800 mr %0,%1
7801 fmr %0,%1
7802 lfd%U1%X1 %0,%1
7803 stfd%U0%X0 %1,%0
7804 mt%0 %1
7805 mf%1 %0
7806 {cror 0,0,0|nop}
7807 #
7808 #
7809 #"
7810 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7811 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7813 (define_insn "*movdf_softfloat64"
7814 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7815 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7816 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7817 && (gpc_reg_operand (operands[0], DFmode)
7818 || gpc_reg_operand (operands[1], DFmode))"
7819 "@
7820 ld%U1%X1 %0,%1
7821 std%U0%X0 %1,%0
7822 mr %0,%1
7823 mt%0 %1
7824 mf%1 %0
7825 #
7826 #
7827 #
7828 {cror 0,0,0|nop}"
7829 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7830 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7831 \f
7832 (define_expand "movtf"
7833 [(set (match_operand:TF 0 "general_operand" "")
7834 (match_operand:TF 1 "any_operand" ""))]
7835 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7836 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7837 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7839 ; It's important to list the o->f and f->o moves before f->f because
7840 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7841 ; which doesn't make progress. Likewise r->Y must be before r->r.
7842 (define_insn_and_split "*movtf_internal"
7843 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7844 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7845 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7846 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7847 && (gpc_reg_operand (operands[0], TFmode)
7848 || gpc_reg_operand (operands[1], TFmode))"
7849 "#"
7850 "&& reload_completed"
7851 [(pc)]
7852 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7853 [(set_attr "length" "8,8,8,20,20,16")])
7855 (define_expand "extenddftf2"
7856 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7857 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7858 (use (match_dup 2))])]
7859 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7860 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7861 {
7862 operands[2] = CONST0_RTX (DFmode);
7863 })
7865 (define_insn_and_split "*extenddftf2_internal"
7866 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7867 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7868 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7869 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7870 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7871 "#"
7872 "&& reload_completed"
7873 [(pc)]
7874 {
7875 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7876 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7877 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7878 operands[1]);
7879 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7880 operands[2]);
7881 DONE;
7882 })
7884 (define_expand "extendsftf2"
7885 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7886 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7887 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7888 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7889 {
7890 rtx tmp = gen_reg_rtx (DFmode);
7891 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7892 emit_insn (gen_extenddftf2 (operands[0], tmp));
7893 DONE;
7894 })
7896 (define_expand "trunctfdf2"
7897 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7898 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7899 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7900 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7901 "")
7903 (define_insn_and_split "trunctfdf2_internal1"
7904 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7905 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7906 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7907 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7908 "@
7909 #
7910 fmr %0,%1"
7911 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7912 [(const_int 0)]
7913 {
7914 emit_note (NOTE_INSN_DELETED);
7915 DONE;
7916 }
7917 [(set_attr "type" "fp")])
7919 (define_insn "trunctfdf2_internal2"
7920 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7921 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7922 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7923 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7924 "fadd %0,%1,%L1"
7925 [(set_attr "type" "fp")])
7927 (define_insn_and_split "trunctfsf2"
7928 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7929 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7930 (clobber (match_scratch:DF 2 "=f"))]
7931 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7932 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7933 "#"
7934 "&& reload_completed"
7935 [(set (match_dup 2)
7936 (float_truncate:DF (match_dup 1)))
7937 (set (match_dup 0)
7938 (float_truncate:SF (match_dup 2)))]
7939 "")
7941 (define_expand "floatsitf2"
7942 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7943 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7944 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7945 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7946 {
7947 rtx tmp = gen_reg_rtx (DFmode);
7948 expand_float (tmp, operands[1], false);
7949 emit_insn (gen_extenddftf2 (operands[0], tmp));
7950 DONE;
7951 })
7953 ; fadd, but rounding towards zero.
7954 ; This is probably not the optimal code sequence.
7955 (define_insn "fix_trunc_helper"
7956 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7957 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7958 UNSPEC_FIX_TRUNC_TF))
7959 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7960 "TARGET_HARD_FLOAT && TARGET_FPRS"
7961 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7962 [(set_attr "type" "fp")
7963 (set_attr "length" "20")])
7965 (define_expand "fix_trunctfsi2"
7966 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7967 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7968 (clobber (match_dup 2))
7969 (clobber (match_dup 3))
7970 (clobber (match_dup 4))
7971 (clobber (match_dup 5))])]
7972 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7973 && (TARGET_POWER2 || TARGET_POWERPC)
7974 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7975 {
7976 operands[2] = gen_reg_rtx (DFmode);
7977 operands[3] = gen_reg_rtx (DFmode);
7978 operands[4] = gen_reg_rtx (DImode);
7979 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7980 })
7982 (define_insn_and_split "*fix_trunctfsi2_internal"
7983 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7984 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7985 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7986 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7987 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7988 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7989 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7990 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7991 "#"
7992 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7993 [(pc)]
7994 {
7995 rtx lowword;
7996 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7998 gcc_assert (MEM_P (operands[5]));
7999 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8001 emit_insn (gen_fctiwz (operands[4], operands[2]));
8002 emit_move_insn (operands[5], operands[4]);
8003 emit_move_insn (operands[0], lowword);
8004 DONE;
8005 })
8007 (define_insn "negtf2"
8008 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8009 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8010 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8011 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8012 "*
8013 {
8014 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8015 return \"fneg %L0,%L1\;fneg %0,%1\";
8016 else
8017 return \"fneg %0,%1\;fneg %L0,%L1\";
8018 }"
8019 [(set_attr "type" "fp")
8020 (set_attr "length" "8")])
8022 (define_expand "abstf2"
8023 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8024 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8025 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8026 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8027 "
8028 {
8029 rtx label = gen_label_rtx ();
8030 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8031 emit_label (label);
8032 DONE;
8033 }")
8035 (define_expand "abstf2_internal"
8036 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8037 (match_operand:TF 1 "gpc_reg_operand" "f"))
8038 (set (match_dup 3) (match_dup 5))
8039 (set (match_dup 5) (abs:DF (match_dup 5)))
8040 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8041 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8042 (label_ref (match_operand 2 "" ""))
8043 (pc)))
8044 (set (match_dup 6) (neg:DF (match_dup 6)))]
8045 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8046 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8047 "
8048 {
8049 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8050 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8051 operands[3] = gen_reg_rtx (DFmode);
8052 operands[4] = gen_reg_rtx (CCFPmode);
8053 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8054 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8055 }")
8056 \f
8057 ;; Next come the multi-word integer load and store and the load and store
8058 ;; multiple insns.
8060 ; List r->r after r->"o<>", otherwise reload will try to reload a
8061 ; non-offsettable address by using r->r which won't make progress.
8062 (define_insn "*movdi_internal32"
8063 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8064 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8065 "! TARGET_POWERPC64
8066 && (gpc_reg_operand (operands[0], DImode)
8067 || gpc_reg_operand (operands[1], DImode))"
8068 "@
8069 #
8070 #
8071 #
8072 fmr %0,%1
8073 lfd%U1%X1 %0,%1
8074 stfd%U0%X0 %1,%0
8075 #"
8076 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8078 (define_split
8079 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8080 (match_operand:DI 1 "const_int_operand" ""))]
8081 "! TARGET_POWERPC64 && reload_completed"
8082 [(set (match_dup 2) (match_dup 4))
8083 (set (match_dup 3) (match_dup 1))]
8084 "
8085 {
8086 HOST_WIDE_INT value = INTVAL (operands[1]);
8087 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8088 DImode);
8089 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8090 DImode);
8091 #if HOST_BITS_PER_WIDE_INT == 32
8092 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8093 #else
8094 operands[4] = GEN_INT (value >> 32);
8095 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8096 #endif
8097 }")
8099 (define_split
8100 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8101 (match_operand:DI 1 "input_operand" ""))]
8102 "reload_completed && !TARGET_POWERPC64
8103 && gpr_or_gpr_p (operands[0], operands[1])"
8104 [(pc)]
8105 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8107 (define_insn "*movdi_internal64"
8108 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8109 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8110 "TARGET_POWERPC64
8111 && (gpc_reg_operand (operands[0], DImode)
8112 || gpc_reg_operand (operands[1], DImode))"
8113 "@
8114 mr %0,%1
8115 ld%U1%X1 %0,%1
8116 std%U0%X0 %1,%0
8117 li %0,%1
8118 lis %0,%v1
8119 #
8120 {cal|la} %0,%a1
8121 fmr %0,%1
8122 lfd%U1%X1 %0,%1
8123 stfd%U0%X0 %1,%0
8124 mf%1 %0
8125 mt%0 %1
8126 {cror 0,0,0|nop}"
8127 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8128 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8130 ;; immediate value valid for a single instruction hiding in a const_double
8131 (define_insn ""
8132 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8133 (match_operand:DI 1 "const_double_operand" "F"))]
8134 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8135 && GET_CODE (operands[1]) == CONST_DOUBLE
8136 && num_insns_constant (operands[1], DImode) == 1"
8137 "*
8138 {
8139 return ((unsigned HOST_WIDE_INT)
8140 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8141 ? \"li %0,%1\" : \"lis %0,%v1\";
8142 }")
8144 ;; Generate all one-bits and clear left or right.
8145 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8146 (define_split
8147 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8148 (match_operand:DI 1 "mask_operand" ""))]
8149 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8150 [(set (match_dup 0) (const_int -1))
8151 (set (match_dup 0)
8152 (and:DI (rotate:DI (match_dup 0)
8153 (const_int 0))
8154 (match_dup 1)))]
8155 "")
8157 ;; Split a load of a large constant into the appropriate five-instruction
8158 ;; sequence. Handle anything in a constant number of insns.
8159 ;; When non-easy constants can go in the TOC, this should use
8160 ;; easy_fp_constant predicate.
8161 (define_split
8162 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8163 (match_operand:DI 1 "const_int_operand" ""))]
8164 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8165 [(set (match_dup 0) (match_dup 2))
8166 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8167 "
8168 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8170 if (tem == operands[0])
8171 DONE;
8172 else
8173 FAIL;
8174 }")
8176 (define_split
8177 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8178 (match_operand:DI 1 "const_double_operand" ""))]
8179 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8180 [(set (match_dup 0) (match_dup 2))
8181 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8182 "
8183 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8185 if (tem == operands[0])
8186 DONE;
8187 else
8188 FAIL;
8189 }")
8190 \f
8191 ;; TImode is similar, except that we usually want to compute the address into
8192 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8193 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8195 ;; We say that MQ is clobbered in the last alternative because the first
8196 ;; alternative would never get used otherwise since it would need a reload
8197 ;; while the 2nd alternative would not. We put memory cases first so they
8198 ;; are preferred. Otherwise, we'd try to reload the output instead of
8199 ;; giving the SCRATCH mq.
8201 (define_insn "*movti_power"
8202 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8203 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8204 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8205 "TARGET_POWER && ! TARGET_POWERPC64
8206 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8207 "*
8208 {
8209 switch (which_alternative)
8210 {
8211 default:
8212 gcc_unreachable ();
8214 case 0:
8215 if (TARGET_STRING)
8216 return \"{stsi|stswi} %1,%P0,16\";
8217 case 1:
8218 case 2:
8219 return \"#\";
8220 case 3:
8221 /* If the address is not used in the output, we can use lsi. Otherwise,
8222 fall through to generating four loads. */
8223 if (TARGET_STRING
8224 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8225 return \"{lsi|lswi} %0,%P1,16\";
8226 /* ... fall through ... */
8227 case 4:
8228 case 5:
8229 return \"#\";
8230 }
8231 }"
8232 [(set_attr "type" "store,store,*,load,load,*")])
8234 (define_insn "*movti_string"
8235 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8236 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8237 "! TARGET_POWER && ! TARGET_POWERPC64
8238 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8239 "*
8240 {
8241 switch (which_alternative)
8242 {
8243 default:
8244 gcc_unreachable ();
8245 case 0:
8246 if (TARGET_STRING)
8247 return \"{stsi|stswi} %1,%P0,16\";
8248 case 1:
8249 case 2:
8250 return \"#\";
8251 case 3:
8252 /* If the address is not used in the output, we can use lsi. Otherwise,
8253 fall through to generating four loads. */
8254 if (TARGET_STRING
8255 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8256 return \"{lsi|lswi} %0,%P1,16\";
8257 /* ... fall through ... */
8258 case 4:
8259 case 5:
8260 return \"#\";
8261 }
8262 }"
8263 [(set_attr "type" "store,store,*,load,load,*")])
8265 (define_insn "*movti_ppc64"
8266 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8267 (match_operand:TI 1 "input_operand" "r,r,m"))]
8268 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8269 || gpc_reg_operand (operands[1], TImode))"
8270 "#"
8271 [(set_attr "type" "*,load,store")])
8273 (define_split
8274 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8275 (match_operand:TI 1 "const_double_operand" ""))]
8276 "TARGET_POWERPC64"
8277 [(set (match_dup 2) (match_dup 4))
8278 (set (match_dup 3) (match_dup 5))]
8279 "
8280 {
8281 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8282 TImode);
8283 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8284 TImode);
8285 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8286 {
8287 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8288 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8289 }
8290 else if (GET_CODE (operands[1]) == CONST_INT)
8291 {
8292 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8293 operands[5] = operands[1];
8294 }
8295 else
8296 FAIL;
8297 }")
8299 (define_split
8300 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8301 (match_operand:TI 1 "input_operand" ""))]
8302 "reload_completed
8303 && gpr_or_gpr_p (operands[0], operands[1])"
8304 [(pc)]
8305 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8306 \f
8307 (define_expand "load_multiple"
8308 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8309 (match_operand:SI 1 "" ""))
8310 (use (match_operand:SI 2 "" ""))])]
8311 "TARGET_STRING && !TARGET_POWERPC64"
8312 "
8313 {
8314 int regno;
8315 int count;
8316 rtx op1;
8317 int i;
8319 /* Support only loading a constant number of fixed-point registers from
8320 memory and only bother with this if more than two; the machine
8321 doesn't support more than eight. */
8322 if (GET_CODE (operands[2]) != CONST_INT
8323 || INTVAL (operands[2]) <= 2
8324 || INTVAL (operands[2]) > 8
8325 || GET_CODE (operands[1]) != MEM
8326 || GET_CODE (operands[0]) != REG
8327 || REGNO (operands[0]) >= 32)
8328 FAIL;
8330 count = INTVAL (operands[2]);
8331 regno = REGNO (operands[0]);
8333 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8334 op1 = replace_equiv_address (operands[1],
8335 force_reg (SImode, XEXP (operands[1], 0)));
8337 for (i = 0; i < count; i++)
8338 XVECEXP (operands[3], 0, i)
8339 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8340 adjust_address_nv (op1, SImode, i * 4));
8341 }")
8343 (define_insn "*ldmsi8"
8344 [(match_parallel 0 "load_multiple_operation"
8345 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8346 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8347 (set (match_operand:SI 3 "gpc_reg_operand" "")
8348 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8349 (set (match_operand:SI 4 "gpc_reg_operand" "")
8350 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8351 (set (match_operand:SI 5 "gpc_reg_operand" "")
8352 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8353 (set (match_operand:SI 6 "gpc_reg_operand" "")
8354 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8355 (set (match_operand:SI 7 "gpc_reg_operand" "")
8356 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8357 (set (match_operand:SI 8 "gpc_reg_operand" "")
8358 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8359 (set (match_operand:SI 9 "gpc_reg_operand" "")
8360 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8361 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8362 "*
8363 { return rs6000_output_load_multiple (operands); }"
8364 [(set_attr "type" "load")
8365 (set_attr "length" "32")])
8367 (define_insn "*ldmsi7"
8368 [(match_parallel 0 "load_multiple_operation"
8369 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8370 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8371 (set (match_operand:SI 3 "gpc_reg_operand" "")
8372 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8373 (set (match_operand:SI 4 "gpc_reg_operand" "")
8374 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8375 (set (match_operand:SI 5 "gpc_reg_operand" "")
8376 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8377 (set (match_operand:SI 6 "gpc_reg_operand" "")
8378 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8379 (set (match_operand:SI 7 "gpc_reg_operand" "")
8380 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8381 (set (match_operand:SI 8 "gpc_reg_operand" "")
8382 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8383 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8384 "*
8385 { return rs6000_output_load_multiple (operands); }"
8386 [(set_attr "type" "load")
8387 (set_attr "length" "32")])
8389 (define_insn "*ldmsi6"
8390 [(match_parallel 0 "load_multiple_operation"
8391 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8392 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8393 (set (match_operand:SI 3 "gpc_reg_operand" "")
8394 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8395 (set (match_operand:SI 4 "gpc_reg_operand" "")
8396 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8397 (set (match_operand:SI 5 "gpc_reg_operand" "")
8398 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8399 (set (match_operand:SI 6 "gpc_reg_operand" "")
8400 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8401 (set (match_operand:SI 7 "gpc_reg_operand" "")
8402 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8403 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8404 "*
8405 { return rs6000_output_load_multiple (operands); }"
8406 [(set_attr "type" "load")
8407 (set_attr "length" "32")])
8409 (define_insn "*ldmsi5"
8410 [(match_parallel 0 "load_multiple_operation"
8411 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8412 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8413 (set (match_operand:SI 3 "gpc_reg_operand" "")
8414 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8415 (set (match_operand:SI 4 "gpc_reg_operand" "")
8416 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8417 (set (match_operand:SI 5 "gpc_reg_operand" "")
8418 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8419 (set (match_operand:SI 6 "gpc_reg_operand" "")
8420 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8421 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8422 "*
8423 { return rs6000_output_load_multiple (operands); }"
8424 [(set_attr "type" "load")
8425 (set_attr "length" "32")])
8427 (define_insn "*ldmsi4"
8428 [(match_parallel 0 "load_multiple_operation"
8429 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8430 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8431 (set (match_operand:SI 3 "gpc_reg_operand" "")
8432 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8433 (set (match_operand:SI 4 "gpc_reg_operand" "")
8434 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8435 (set (match_operand:SI 5 "gpc_reg_operand" "")
8436 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8437 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8438 "*
8439 { return rs6000_output_load_multiple (operands); }"
8440 [(set_attr "type" "load")
8441 (set_attr "length" "32")])
8443 (define_insn "*ldmsi3"
8444 [(match_parallel 0 "load_multiple_operation"
8445 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8446 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8447 (set (match_operand:SI 3 "gpc_reg_operand" "")
8448 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8449 (set (match_operand:SI 4 "gpc_reg_operand" "")
8450 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8451 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8452 "*
8453 { return rs6000_output_load_multiple (operands); }"
8454 [(set_attr "type" "load")
8455 (set_attr "length" "32")])
8457 (define_expand "store_multiple"
8458 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8459 (match_operand:SI 1 "" ""))
8460 (clobber (scratch:SI))
8461 (use (match_operand:SI 2 "" ""))])]
8462 "TARGET_STRING && !TARGET_POWERPC64"
8463 "
8464 {
8465 int regno;
8466 int count;
8467 rtx to;
8468 rtx op0;
8469 int i;
8471 /* Support only storing a constant number of fixed-point registers to
8472 memory and only bother with this if more than two; the machine
8473 doesn't support more than eight. */
8474 if (GET_CODE (operands[2]) != CONST_INT
8475 || INTVAL (operands[2]) <= 2
8476 || INTVAL (operands[2]) > 8
8477 || GET_CODE (operands[0]) != MEM
8478 || GET_CODE (operands[1]) != REG
8479 || REGNO (operands[1]) >= 32)
8480 FAIL;
8482 count = INTVAL (operands[2]);
8483 regno = REGNO (operands[1]);
8485 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8486 to = force_reg (SImode, XEXP (operands[0], 0));
8487 op0 = replace_equiv_address (operands[0], to);
8489 XVECEXP (operands[3], 0, 0)
8490 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8491 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8492 gen_rtx_SCRATCH (SImode));
8494 for (i = 1; i < count; i++)
8495 XVECEXP (operands[3], 0, i + 1)
8496 = gen_rtx_SET (VOIDmode,
8497 adjust_address_nv (op0, SImode, i * 4),
8498 gen_rtx_REG (SImode, regno + i));
8499 }")
8501 (define_insn "*store_multiple_power"
8502 [(match_parallel 0 "store_multiple_operation"
8503 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8504 (match_operand:SI 2 "gpc_reg_operand" "r"))
8505 (clobber (match_scratch:SI 3 "=q"))])]
8506 "TARGET_STRING && TARGET_POWER"
8507 "{stsi|stswi} %2,%P1,%O0"
8508 [(set_attr "type" "store")])
8510 (define_insn "*stmsi8"
8511 [(match_parallel 0 "store_multiple_operation"
8512 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8513 (match_operand:SI 2 "gpc_reg_operand" "r"))
8514 (clobber (match_scratch:SI 3 "X"))
8515 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8516 (match_operand:SI 4 "gpc_reg_operand" "r"))
8517 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8518 (match_operand:SI 5 "gpc_reg_operand" "r"))
8519 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8520 (match_operand:SI 6 "gpc_reg_operand" "r"))
8521 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8522 (match_operand:SI 7 "gpc_reg_operand" "r"))
8523 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8524 (match_operand:SI 8 "gpc_reg_operand" "r"))
8525 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8526 (match_operand:SI 9 "gpc_reg_operand" "r"))
8527 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8528 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8529 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8530 "{stsi|stswi} %2,%1,%O0"
8531 [(set_attr "type" "store")])
8533 (define_insn "*stmsi7"
8534 [(match_parallel 0 "store_multiple_operation"
8535 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8536 (match_operand:SI 2 "gpc_reg_operand" "r"))
8537 (clobber (match_scratch:SI 3 "X"))
8538 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8539 (match_operand:SI 4 "gpc_reg_operand" "r"))
8540 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8541 (match_operand:SI 5 "gpc_reg_operand" "r"))
8542 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8543 (match_operand:SI 6 "gpc_reg_operand" "r"))
8544 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8545 (match_operand:SI 7 "gpc_reg_operand" "r"))
8546 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8547 (match_operand:SI 8 "gpc_reg_operand" "r"))
8548 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8549 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8550 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8551 "{stsi|stswi} %2,%1,%O0"
8552 [(set_attr "type" "store")])
8554 (define_insn "*stmsi6"
8555 [(match_parallel 0 "store_multiple_operation"
8556 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8557 (match_operand:SI 2 "gpc_reg_operand" "r"))
8558 (clobber (match_scratch:SI 3 "X"))
8559 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8560 (match_operand:SI 4 "gpc_reg_operand" "r"))
8561 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8562 (match_operand:SI 5 "gpc_reg_operand" "r"))
8563 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8564 (match_operand:SI 6 "gpc_reg_operand" "r"))
8565 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8566 (match_operand:SI 7 "gpc_reg_operand" "r"))
8567 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8568 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8569 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8570 "{stsi|stswi} %2,%1,%O0"
8571 [(set_attr "type" "store")])
8573 (define_insn "*stmsi5"
8574 [(match_parallel 0 "store_multiple_operation"
8575 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8576 (match_operand:SI 2 "gpc_reg_operand" "r"))
8577 (clobber (match_scratch:SI 3 "X"))
8578 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8579 (match_operand:SI 4 "gpc_reg_operand" "r"))
8580 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8581 (match_operand:SI 5 "gpc_reg_operand" "r"))
8582 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8583 (match_operand:SI 6 "gpc_reg_operand" "r"))
8584 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8585 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8586 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8587 "{stsi|stswi} %2,%1,%O0"
8588 [(set_attr "type" "store")])
8590 (define_insn "*stmsi4"
8591 [(match_parallel 0 "store_multiple_operation"
8592 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8593 (match_operand:SI 2 "gpc_reg_operand" "r"))
8594 (clobber (match_scratch:SI 3 "X"))
8595 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8596 (match_operand:SI 4 "gpc_reg_operand" "r"))
8597 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8598 (match_operand:SI 5 "gpc_reg_operand" "r"))
8599 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8600 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8601 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8602 "{stsi|stswi} %2,%1,%O0"
8603 [(set_attr "type" "store")])
8605 (define_insn "*stmsi3"
8606 [(match_parallel 0 "store_multiple_operation"
8607 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8608 (match_operand:SI 2 "gpc_reg_operand" "r"))
8609 (clobber (match_scratch:SI 3 "X"))
8610 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8611 (match_operand:SI 4 "gpc_reg_operand" "r"))
8612 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8613 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8614 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8615 "{stsi|stswi} %2,%1,%O0"
8616 [(set_attr "type" "store")])
8617 \f
8618 (define_expand "setmemsi"
8619 [(parallel [(set (match_operand:BLK 0 "" "")
8620 (match_operand 2 "const_int_operand" ""))
8621 (use (match_operand:SI 1 "" ""))
8622 (use (match_operand:SI 3 "" ""))])]
8623 ""
8624 "
8625 {
8626 /* If value to set is not zero, use the library routine. */
8627 if (operands[2] != const0_rtx)
8628 FAIL;
8630 if (expand_block_clear (operands))
8631 DONE;
8632 else
8633 FAIL;
8634 }")
8636 ;; String/block move insn.
8637 ;; Argument 0 is the destination
8638 ;; Argument 1 is the source
8639 ;; Argument 2 is the length
8640 ;; Argument 3 is the alignment
8642 (define_expand "movmemsi"
8643 [(parallel [(set (match_operand:BLK 0 "" "")
8644 (match_operand:BLK 1 "" ""))
8645 (use (match_operand:SI 2 "" ""))
8646 (use (match_operand:SI 3 "" ""))])]
8647 ""
8648 "
8649 {
8650 if (expand_block_move (operands))
8651 DONE;
8652 else
8653 FAIL;
8654 }")
8656 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8657 ;; register allocator doesn't have a clue about allocating 8 word registers.
8658 ;; rD/rS = r5 is preferred, efficient form.
8659 (define_expand "movmemsi_8reg"
8660 [(parallel [(set (match_operand 0 "" "")
8661 (match_operand 1 "" ""))
8662 (use (match_operand 2 "" ""))
8663 (use (match_operand 3 "" ""))
8664 (clobber (reg:SI 5))
8665 (clobber (reg:SI 6))
8666 (clobber (reg:SI 7))
8667 (clobber (reg:SI 8))
8668 (clobber (reg:SI 9))
8669 (clobber (reg:SI 10))
8670 (clobber (reg:SI 11))
8671 (clobber (reg:SI 12))
8672 (clobber (match_scratch:SI 4 ""))])]
8673 "TARGET_STRING"
8674 "")
8676 (define_insn ""
8677 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8678 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8679 (use (match_operand:SI 2 "immediate_operand" "i"))
8680 (use (match_operand:SI 3 "immediate_operand" "i"))
8681 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8682 (clobber (reg:SI 6))
8683 (clobber (reg:SI 7))
8684 (clobber (reg:SI 8))
8685 (clobber (reg:SI 9))
8686 (clobber (reg:SI 10))
8687 (clobber (reg:SI 11))
8688 (clobber (reg:SI 12))
8689 (clobber (match_scratch:SI 5 "=q"))]
8690 "TARGET_STRING && TARGET_POWER
8691 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8692 || INTVAL (operands[2]) == 0)
8693 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8694 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8695 && REGNO (operands[4]) == 5"
8696 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8697 [(set_attr "type" "load")
8698 (set_attr "length" "8")])
8700 (define_insn ""
8701 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8702 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8703 (use (match_operand:SI 2 "immediate_operand" "i"))
8704 (use (match_operand:SI 3 "immediate_operand" "i"))
8705 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8706 (clobber (reg:SI 6))
8707 (clobber (reg:SI 7))
8708 (clobber (reg:SI 8))
8709 (clobber (reg:SI 9))
8710 (clobber (reg:SI 10))
8711 (clobber (reg:SI 11))
8712 (clobber (reg:SI 12))
8713 (clobber (match_scratch:SI 5 "X"))]
8714 "TARGET_STRING && ! TARGET_POWER
8715 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8716 || INTVAL (operands[2]) == 0)
8717 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8718 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8719 && REGNO (operands[4]) == 5"
8720 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8721 [(set_attr "type" "load")
8722 (set_attr "length" "8")])
8724 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8725 ;; register allocator doesn't have a clue about allocating 6 word registers.
8726 ;; rD/rS = r5 is preferred, efficient form.
8727 (define_expand "movmemsi_6reg"
8728 [(parallel [(set (match_operand 0 "" "")
8729 (match_operand 1 "" ""))
8730 (use (match_operand 2 "" ""))
8731 (use (match_operand 3 "" ""))
8732 (clobber (reg:SI 5))
8733 (clobber (reg:SI 6))
8734 (clobber (reg:SI 7))
8735 (clobber (reg:SI 8))
8736 (clobber (reg:SI 9))
8737 (clobber (reg:SI 10))
8738 (clobber (match_scratch:SI 4 ""))])]
8739 "TARGET_STRING"
8740 "")
8742 (define_insn ""
8743 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8744 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8745 (use (match_operand:SI 2 "immediate_operand" "i"))
8746 (use (match_operand:SI 3 "immediate_operand" "i"))
8747 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8748 (clobber (reg:SI 6))
8749 (clobber (reg:SI 7))
8750 (clobber (reg:SI 8))
8751 (clobber (reg:SI 9))
8752 (clobber (reg:SI 10))
8753 (clobber (match_scratch:SI 5 "=q"))]
8754 "TARGET_STRING && TARGET_POWER
8755 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8756 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8757 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8758 && REGNO (operands[4]) == 5"
8759 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8760 [(set_attr "type" "load")
8761 (set_attr "length" "8")])
8763 (define_insn ""
8764 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8765 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8766 (use (match_operand:SI 2 "immediate_operand" "i"))
8767 (use (match_operand:SI 3 "immediate_operand" "i"))
8768 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8769 (clobber (reg:SI 6))
8770 (clobber (reg:SI 7))
8771 (clobber (reg:SI 8))
8772 (clobber (reg:SI 9))
8773 (clobber (reg:SI 10))
8774 (clobber (match_scratch:SI 5 "X"))]
8775 "TARGET_STRING && ! TARGET_POWER
8776 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8777 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8778 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8779 && REGNO (operands[4]) == 5"
8780 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8781 [(set_attr "type" "load")
8782 (set_attr "length" "8")])
8784 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8785 ;; problems with TImode.
8786 ;; rD/rS = r5 is preferred, efficient form.
8787 (define_expand "movmemsi_4reg"
8788 [(parallel [(set (match_operand 0 "" "")
8789 (match_operand 1 "" ""))
8790 (use (match_operand 2 "" ""))
8791 (use (match_operand 3 "" ""))
8792 (clobber (reg:SI 5))
8793 (clobber (reg:SI 6))
8794 (clobber (reg:SI 7))
8795 (clobber (reg:SI 8))
8796 (clobber (match_scratch:SI 4 ""))])]
8797 "TARGET_STRING"
8798 "")
8800 (define_insn ""
8801 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8802 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8803 (use (match_operand:SI 2 "immediate_operand" "i"))
8804 (use (match_operand:SI 3 "immediate_operand" "i"))
8805 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8806 (clobber (reg:SI 6))
8807 (clobber (reg:SI 7))
8808 (clobber (reg:SI 8))
8809 (clobber (match_scratch:SI 5 "=q"))]
8810 "TARGET_STRING && TARGET_POWER
8811 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8812 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8813 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8814 && REGNO (operands[4]) == 5"
8815 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8816 [(set_attr "type" "load")
8817 (set_attr "length" "8")])
8819 (define_insn ""
8820 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8821 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8822 (use (match_operand:SI 2 "immediate_operand" "i"))
8823 (use (match_operand:SI 3 "immediate_operand" "i"))
8824 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8825 (clobber (reg:SI 6))
8826 (clobber (reg:SI 7))
8827 (clobber (reg:SI 8))
8828 (clobber (match_scratch:SI 5 "X"))]
8829 "TARGET_STRING && ! TARGET_POWER
8830 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8831 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8832 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8833 && REGNO (operands[4]) == 5"
8834 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8835 [(set_attr "type" "load")
8836 (set_attr "length" "8")])
8838 ;; Move up to 8 bytes at a time.
8839 (define_expand "movmemsi_2reg"
8840 [(parallel [(set (match_operand 0 "" "")
8841 (match_operand 1 "" ""))
8842 (use (match_operand 2 "" ""))
8843 (use (match_operand 3 "" ""))
8844 (clobber (match_scratch:DI 4 ""))
8845 (clobber (match_scratch:SI 5 ""))])]
8846 "TARGET_STRING && ! TARGET_POWERPC64"
8847 "")
8849 (define_insn ""
8850 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8851 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8852 (use (match_operand:SI 2 "immediate_operand" "i"))
8853 (use (match_operand:SI 3 "immediate_operand" "i"))
8854 (clobber (match_scratch:DI 4 "=&r"))
8855 (clobber (match_scratch:SI 5 "=q"))]
8856 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8857 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8858 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8859 [(set_attr "type" "load")
8860 (set_attr "length" "8")])
8862 (define_insn ""
8863 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8864 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8865 (use (match_operand:SI 2 "immediate_operand" "i"))
8866 (use (match_operand:SI 3 "immediate_operand" "i"))
8867 (clobber (match_scratch:DI 4 "=&r"))
8868 (clobber (match_scratch:SI 5 "X"))]
8869 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8870 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8871 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8872 [(set_attr "type" "load")
8873 (set_attr "length" "8")])
8875 ;; Move up to 4 bytes at a time.
8876 (define_expand "movmemsi_1reg"
8877 [(parallel [(set (match_operand 0 "" "")
8878 (match_operand 1 "" ""))
8879 (use (match_operand 2 "" ""))
8880 (use (match_operand 3 "" ""))
8881 (clobber (match_scratch:SI 4 ""))
8882 (clobber (match_scratch:SI 5 ""))])]
8883 "TARGET_STRING"
8884 "")
8886 (define_insn ""
8887 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8888 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8889 (use (match_operand:SI 2 "immediate_operand" "i"))
8890 (use (match_operand:SI 3 "immediate_operand" "i"))
8891 (clobber (match_scratch:SI 4 "=&r"))
8892 (clobber (match_scratch:SI 5 "=q"))]
8893 "TARGET_STRING && TARGET_POWER
8894 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8895 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8896 [(set_attr "type" "load")
8897 (set_attr "length" "8")])
8899 (define_insn ""
8900 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8901 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8902 (use (match_operand:SI 2 "immediate_operand" "i"))
8903 (use (match_operand:SI 3 "immediate_operand" "i"))
8904 (clobber (match_scratch:SI 4 "=&r"))
8905 (clobber (match_scratch:SI 5 "X"))]
8906 "TARGET_STRING && ! TARGET_POWER
8907 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8908 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8909 [(set_attr "type" "load")
8910 (set_attr "length" "8")])
8911 \f
8912 ;; Define insns that do load or store with update. Some of these we can
8913 ;; get by using pre-decrement or pre-increment, but the hardware can also
8914 ;; do cases where the increment is not the size of the object.
8915 ;;
8916 ;; In all these cases, we use operands 0 and 1 for the register being
8917 ;; incremented because those are the operands that local-alloc will
8918 ;; tie and these are the pair most likely to be tieable (and the ones
8919 ;; that will benefit the most).
8921 (define_insn "*movdi_update1"
8922 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8923 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8924 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8925 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8926 (plus:DI (match_dup 1) (match_dup 2)))]
8927 "TARGET_POWERPC64 && TARGET_UPDATE"
8928 "@
8929 ldux %3,%0,%2
8930 ldu %3,%2(%0)"
8931 [(set_attr "type" "load_ux,load_u")])
8933 (define_insn "movdi_<mode>_update"
8934 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8935 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8936 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8937 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8938 (plus:P (match_dup 1) (match_dup 2)))]
8939 "TARGET_POWERPC64 && TARGET_UPDATE"
8940 "@
8941 stdux %3,%0,%2
8942 stdu %3,%2(%0)"
8943 [(set_attr "type" "store_ux,store_u")])
8945 (define_insn "*movsi_update1"
8946 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8947 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8948 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8949 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8950 (plus:SI (match_dup 1) (match_dup 2)))]
8951 "TARGET_UPDATE"
8952 "@
8953 {lux|lwzux} %3,%0,%2
8954 {lu|lwzu} %3,%2(%0)"
8955 [(set_attr "type" "load_ux,load_u")])
8957 (define_insn "*movsi_update2"
8958 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8959 (sign_extend:DI
8960 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8961 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8962 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8963 (plus:DI (match_dup 1) (match_dup 2)))]
8964 "TARGET_POWERPC64"
8965 "lwaux %3,%0,%2"
8966 [(set_attr "type" "load_ext_ux")])
8968 (define_insn "movsi_update"
8969 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8970 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8971 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8972 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8973 (plus:SI (match_dup 1) (match_dup 2)))]
8974 "TARGET_UPDATE"
8975 "@
8976 {stux|stwux} %3,%0,%2
8977 {stu|stwu} %3,%2(%0)"
8978 [(set_attr "type" "store_ux,store_u")])
8980 (define_insn "*movhi_update1"
8981 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8982 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8983 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8984 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8985 (plus:SI (match_dup 1) (match_dup 2)))]
8986 "TARGET_UPDATE"
8987 "@
8988 lhzux %3,%0,%2
8989 lhzu %3,%2(%0)"
8990 [(set_attr "type" "load_ux,load_u")])
8992 (define_insn "*movhi_update2"
8993 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8994 (zero_extend:SI
8995 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8996 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8997 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8998 (plus:SI (match_dup 1) (match_dup 2)))]
8999 "TARGET_UPDATE"
9000 "@
9001 lhzux %3,%0,%2
9002 lhzu %3,%2(%0)"
9003 [(set_attr "type" "load_ux,load_u")])
9005 (define_insn "*movhi_update3"
9006 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9007 (sign_extend:SI
9008 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9009 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9010 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9011 (plus:SI (match_dup 1) (match_dup 2)))]
9012 "TARGET_UPDATE"
9013 "@
9014 lhaux %3,%0,%2
9015 lhau %3,%2(%0)"
9016 [(set_attr "type" "load_ext_ux,load_ext_u")])
9018 (define_insn "*movhi_update4"
9019 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9020 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9021 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9022 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9023 (plus:SI (match_dup 1) (match_dup 2)))]
9024 "TARGET_UPDATE"
9025 "@
9026 sthux %3,%0,%2
9027 sthu %3,%2(%0)"
9028 [(set_attr "type" "store_ux,store_u")])
9030 (define_insn "*movqi_update1"
9031 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9032 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9033 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9034 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9035 (plus:SI (match_dup 1) (match_dup 2)))]
9036 "TARGET_UPDATE"
9037 "@
9038 lbzux %3,%0,%2
9039 lbzu %3,%2(%0)"
9040 [(set_attr "type" "load_ux,load_u")])
9042 (define_insn "*movqi_update2"
9043 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9044 (zero_extend:SI
9045 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9046 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9047 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9048 (plus:SI (match_dup 1) (match_dup 2)))]
9049 "TARGET_UPDATE"
9050 "@
9051 lbzux %3,%0,%2
9052 lbzu %3,%2(%0)"
9053 [(set_attr "type" "load_ux,load_u")])
9055 (define_insn "*movqi_update3"
9056 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9057 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9058 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9059 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9060 (plus:SI (match_dup 1) (match_dup 2)))]
9061 "TARGET_UPDATE"
9062 "@
9063 stbux %3,%0,%2
9064 stbu %3,%2(%0)"
9065 [(set_attr "type" "store_ux,store_u")])
9067 (define_insn "*movsf_update1"
9068 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9069 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9070 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9071 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9072 (plus:SI (match_dup 1) (match_dup 2)))]
9073 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9074 "@
9075 lfsux %3,%0,%2
9076 lfsu %3,%2(%0)"
9077 [(set_attr "type" "fpload_ux,fpload_u")])
9079 (define_insn "*movsf_update2"
9080 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9081 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9082 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9083 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9084 (plus:SI (match_dup 1) (match_dup 2)))]
9085 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9086 "@
9087 stfsux %3,%0,%2
9088 stfsu %3,%2(%0)"
9089 [(set_attr "type" "fpstore_ux,fpstore_u")])
9091 (define_insn "*movsf_update3"
9092 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9093 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9094 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9095 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9096 (plus:SI (match_dup 1) (match_dup 2)))]
9097 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9098 "@
9099 {lux|lwzux} %3,%0,%2
9100 {lu|lwzu} %3,%2(%0)"
9101 [(set_attr "type" "load_ux,load_u")])
9103 (define_insn "*movsf_update4"
9104 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9105 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9106 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9107 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9108 (plus:SI (match_dup 1) (match_dup 2)))]
9109 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9110 "@
9111 {stux|stwux} %3,%0,%2
9112 {stu|stwu} %3,%2(%0)"
9113 [(set_attr "type" "store_ux,store_u")])
9115 (define_insn "*movdf_update1"
9116 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9117 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9118 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9119 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9120 (plus:SI (match_dup 1) (match_dup 2)))]
9121 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9122 "@
9123 lfdux %3,%0,%2
9124 lfdu %3,%2(%0)"
9125 [(set_attr "type" "fpload_ux,fpload_u")])
9127 (define_insn "*movdf_update2"
9128 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9129 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9130 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9131 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9132 (plus:SI (match_dup 1) (match_dup 2)))]
9133 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9134 "@
9135 stfdux %3,%0,%2
9136 stfdu %3,%2(%0)"
9137 [(set_attr "type" "fpstore_ux,fpstore_u")])
9139 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9141 (define_insn "*lfq_power2"
9142 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9143 (match_operand:TF 1 "memory_operand" ""))]
9144 "TARGET_POWER2
9145 && TARGET_HARD_FLOAT && TARGET_FPRS"
9146 "lfq%U1%X1 %0,%1")
9148 (define_peephole2
9149 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9150 (match_operand:DF 1 "memory_operand" ""))
9151 (set (match_operand:DF 2 "gpc_reg_operand" "")
9152 (match_operand:DF 3 "memory_operand" ""))]
9153 "TARGET_POWER2
9154 && TARGET_HARD_FLOAT && TARGET_FPRS
9155 && registers_ok_for_quad_peep (operands[0], operands[2])
9156 && mems_ok_for_quad_peep (operands[1], operands[3])"
9157 [(set (match_dup 0)
9158 (match_dup 1))]
9159 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9160 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9162 (define_insn "*stfq_power2"
9163 [(set (match_operand:TF 0 "memory_operand" "")
9164 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9165 "TARGET_POWER2
9166 && TARGET_HARD_FLOAT && TARGET_FPRS"
9167 "stfq%U0%X0 %1,%0")
9170 (define_peephole2
9171 [(set (match_operand:DF 0 "memory_operand" "")
9172 (match_operand:DF 1 "gpc_reg_operand" ""))
9173 (set (match_operand:DF 2 "memory_operand" "")
9174 (match_operand:DF 3 "gpc_reg_operand" ""))]
9175 "TARGET_POWER2
9176 && TARGET_HARD_FLOAT && TARGET_FPRS
9177 && registers_ok_for_quad_peep (operands[1], operands[3])
9178 && mems_ok_for_quad_peep (operands[0], operands[2])"
9179 [(set (match_dup 0)
9180 (match_dup 1))]
9181 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9182 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9184 ;; after inserting conditional returns we can sometimes have
9185 ;; unnecessary register moves. Unfortunately we cannot have a
9186 ;; modeless peephole here, because some single SImode sets have early
9187 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9188 ;; sequences, using get_attr_length here will smash the operands
9189 ;; array. Neither is there an early_cobbler_p predicate.
9190 (define_peephole2
9191 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9192 (match_operand:DF 1 "any_operand" ""))
9193 (set (match_operand:DF 2 "gpc_reg_operand" "")
9194 (match_dup 0))]
9195 "peep2_reg_dead_p (2, operands[0])"
9196 [(set (match_dup 2) (match_dup 1))])
9198 (define_peephole2
9199 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9200 (match_operand:SF 1 "any_operand" ""))
9201 (set (match_operand:SF 2 "gpc_reg_operand" "")
9202 (match_dup 0))]
9203 "peep2_reg_dead_p (2, operands[0])"
9204 [(set (match_dup 2) (match_dup 1))])
9206 \f
9207 ;; TLS support.
9209 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9210 (define_insn "tls_gd_32"
9211 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9212 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9213 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9214 UNSPEC_TLSGD))]
9215 "HAVE_AS_TLS && !TARGET_64BIT"
9216 "addi %0,%1,%2@got@tlsgd")
9218 (define_insn "tls_gd_64"
9219 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9220 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9221 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9222 UNSPEC_TLSGD))]
9223 "HAVE_AS_TLS && TARGET_64BIT"
9224 "addi %0,%1,%2@got@tlsgd")
9226 (define_insn "tls_ld_32"
9227 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9228 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9229 UNSPEC_TLSLD))]
9230 "HAVE_AS_TLS && !TARGET_64BIT"
9231 "addi %0,%1,%&@got@tlsld")
9233 (define_insn "tls_ld_64"
9234 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9235 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9236 UNSPEC_TLSLD))]
9237 "HAVE_AS_TLS && TARGET_64BIT"
9238 "addi %0,%1,%&@got@tlsld")
9240 (define_insn "tls_dtprel_32"
9241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9242 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9243 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9244 UNSPEC_TLSDTPREL))]
9245 "HAVE_AS_TLS && !TARGET_64BIT"
9246 "addi %0,%1,%2@dtprel")
9248 (define_insn "tls_dtprel_64"
9249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9250 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9251 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9252 UNSPEC_TLSDTPREL))]
9253 "HAVE_AS_TLS && TARGET_64BIT"
9254 "addi %0,%1,%2@dtprel")
9256 (define_insn "tls_dtprel_ha_32"
9257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9258 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9259 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9260 UNSPEC_TLSDTPRELHA))]
9261 "HAVE_AS_TLS && !TARGET_64BIT"
9262 "addis %0,%1,%2@dtprel@ha")
9264 (define_insn "tls_dtprel_ha_64"
9265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9266 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9267 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9268 UNSPEC_TLSDTPRELHA))]
9269 "HAVE_AS_TLS && TARGET_64BIT"
9270 "addis %0,%1,%2@dtprel@ha")
9272 (define_insn "tls_dtprel_lo_32"
9273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9274 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9275 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9276 UNSPEC_TLSDTPRELLO))]
9277 "HAVE_AS_TLS && !TARGET_64BIT"
9278 "addi %0,%1,%2@dtprel@l")
9280 (define_insn "tls_dtprel_lo_64"
9281 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9282 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9283 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9284 UNSPEC_TLSDTPRELLO))]
9285 "HAVE_AS_TLS && TARGET_64BIT"
9286 "addi %0,%1,%2@dtprel@l")
9288 (define_insn "tls_got_dtprel_32"
9289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9290 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9291 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9292 UNSPEC_TLSGOTDTPREL))]
9293 "HAVE_AS_TLS && !TARGET_64BIT"
9294 "lwz %0,%2@got@dtprel(%1)")
9296 (define_insn "tls_got_dtprel_64"
9297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9298 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9299 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9300 UNSPEC_TLSGOTDTPREL))]
9301 "HAVE_AS_TLS && TARGET_64BIT"
9302 "ld %0,%2@got@dtprel(%1)")
9304 (define_insn "tls_tprel_32"
9305 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9306 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9307 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9308 UNSPEC_TLSTPREL))]
9309 "HAVE_AS_TLS && !TARGET_64BIT"
9310 "addi %0,%1,%2@tprel")
9312 (define_insn "tls_tprel_64"
9313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9314 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9315 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9316 UNSPEC_TLSTPREL))]
9317 "HAVE_AS_TLS && TARGET_64BIT"
9318 "addi %0,%1,%2@tprel")
9320 (define_insn "tls_tprel_ha_32"
9321 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9322 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9323 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9324 UNSPEC_TLSTPRELHA))]
9325 "HAVE_AS_TLS && !TARGET_64BIT"
9326 "addis %0,%1,%2@tprel@ha")
9328 (define_insn "tls_tprel_ha_64"
9329 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9330 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9331 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9332 UNSPEC_TLSTPRELHA))]
9333 "HAVE_AS_TLS && TARGET_64BIT"
9334 "addis %0,%1,%2@tprel@ha")
9336 (define_insn "tls_tprel_lo_32"
9337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9338 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9339 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9340 UNSPEC_TLSTPRELLO))]
9341 "HAVE_AS_TLS && !TARGET_64BIT"
9342 "addi %0,%1,%2@tprel@l")
9344 (define_insn "tls_tprel_lo_64"
9345 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9346 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9347 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9348 UNSPEC_TLSTPRELLO))]
9349 "HAVE_AS_TLS && TARGET_64BIT"
9350 "addi %0,%1,%2@tprel@l")
9352 ;; "b" output constraint here and on tls_tls input to support linker tls
9353 ;; optimization. The linker may edit the instructions emitted by a
9354 ;; tls_got_tprel/tls_tls pair to addis,addi.
9355 (define_insn "tls_got_tprel_32"
9356 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9357 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9358 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9359 UNSPEC_TLSGOTTPREL))]
9360 "HAVE_AS_TLS && !TARGET_64BIT"
9361 "lwz %0,%2@got@tprel(%1)")
9363 (define_insn "tls_got_tprel_64"
9364 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9365 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9366 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9367 UNSPEC_TLSGOTTPREL))]
9368 "HAVE_AS_TLS && TARGET_64BIT"
9369 "ld %0,%2@got@tprel(%1)")
9371 (define_insn "tls_tls_32"
9372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9373 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9374 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9375 UNSPEC_TLSTLS))]
9376 "HAVE_AS_TLS && !TARGET_64BIT"
9377 "add %0,%1,%2@tls")
9379 (define_insn "tls_tls_64"
9380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9381 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9382 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9383 UNSPEC_TLSTLS))]
9384 "HAVE_AS_TLS && TARGET_64BIT"
9385 "add %0,%1,%2@tls")
9386 \f
9387 ;; Next come insns related to the calling sequence.
9388 ;;
9389 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9390 ;; We move the back-chain and decrement the stack pointer.
9392 (define_expand "allocate_stack"
9393 [(set (match_operand 0 "gpc_reg_operand" "=r")
9394 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9395 (set (reg 1)
9396 (minus (reg 1) (match_dup 1)))]
9397 ""
9398 "
9399 { rtx chain = gen_reg_rtx (Pmode);
9400 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9401 rtx neg_op0;
9403 emit_move_insn (chain, stack_bot);
9405 /* Check stack bounds if necessary. */
9406 if (current_function_limit_stack)
9407 {
9408 rtx available;
9409 available = expand_binop (Pmode, sub_optab,
9410 stack_pointer_rtx, stack_limit_rtx,
9411 NULL_RTX, 1, OPTAB_WIDEN);
9412 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9413 }
9415 if (GET_CODE (operands[1]) != CONST_INT
9416 || INTVAL (operands[1]) < -32767
9417 || INTVAL (operands[1]) > 32768)
9418 {
9419 neg_op0 = gen_reg_rtx (Pmode);
9420 if (TARGET_32BIT)
9421 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9422 else
9423 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9424 }
9425 else
9426 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9428 if (TARGET_UPDATE)
9429 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9430 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9432 else
9433 {
9434 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9435 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9436 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9437 }
9439 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9440 DONE;
9441 }")
9443 ;; These patterns say how to save and restore the stack pointer. We need not
9444 ;; save the stack pointer at function level since we are careful to
9445 ;; preserve the backchain. At block level, we have to restore the backchain
9446 ;; when we restore the stack pointer.
9447 ;;
9448 ;; For nonlocal gotos, we must save both the stack pointer and its
9449 ;; backchain and restore both. Note that in the nonlocal case, the
9450 ;; save area is a memory location.
9452 (define_expand "save_stack_function"
9453 [(match_operand 0 "any_operand" "")
9454 (match_operand 1 "any_operand" "")]
9455 ""
9456 "DONE;")
9458 (define_expand "restore_stack_function"
9459 [(match_operand 0 "any_operand" "")
9460 (match_operand 1 "any_operand" "")]
9461 ""
9462 "DONE;")
9464 (define_expand "restore_stack_block"
9465 [(use (match_operand 0 "register_operand" ""))
9466 (set (match_dup 2) (match_dup 3))
9467 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9468 (set (match_dup 3) (match_dup 2))]
9469 ""
9470 "
9471 {
9472 operands[2] = gen_reg_rtx (Pmode);
9473 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9474 }")
9476 (define_expand "save_stack_nonlocal"
9477 [(match_operand 0 "memory_operand" "")
9478 (match_operand 1 "register_operand" "")]
9479 ""
9480 "
9481 {
9482 rtx temp = gen_reg_rtx (Pmode);
9483 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9485 /* Copy the backchain to the first word, sp to the second. */
9486 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9487 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9488 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9489 operands[1]);
9490 DONE;
9491 }")
9493 (define_expand "restore_stack_nonlocal"
9494 [(match_operand 0 "register_operand" "")
9495 (match_operand 1 "memory_operand" "")]
9496 ""
9497 "
9498 {
9499 rtx temp = gen_reg_rtx (Pmode);
9500 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9502 /* Restore the backchain from the first word, sp from the second. */
9503 emit_move_insn (temp,
9504 adjust_address_nv (operands[1], Pmode, 0));
9505 emit_move_insn (operands[0],
9506 adjust_address_nv (operands[1], Pmode, units_per_word));
9507 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9508 DONE;
9509 }")
9510 \f
9511 ;; TOC register handling.
9513 ;; Code to initialize the TOC register...
9515 (define_insn "load_toc_aix_si"
9516 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9517 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9518 (use (reg:SI 2))])]
9519 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9520 "*
9521 {
9522 char buf[30];
9523 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9524 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9525 operands[2] = gen_rtx_REG (Pmode, 2);
9526 return \"{l|lwz} %0,%1(%2)\";
9527 }"
9528 [(set_attr "type" "load")])
9530 (define_insn "load_toc_aix_di"
9531 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9532 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9533 (use (reg:DI 2))])]
9534 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9535 "*
9536 {
9537 char buf[30];
9538 #ifdef TARGET_RELOCATABLE
9539 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9540 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9541 #else
9542 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9543 #endif
9544 if (TARGET_ELF)
9545 strcat (buf, \"@toc\");
9546 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9547 operands[2] = gen_rtx_REG (Pmode, 2);
9548 return \"ld %0,%1(%2)\";
9549 }"
9550 [(set_attr "type" "load")])
9552 (define_insn "load_toc_v4_pic_si"
9553 [(set (match_operand:SI 0 "register_operand" "=l")
9554 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9555 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9556 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9557 [(set_attr "type" "branch")
9558 (set_attr "length" "4")])
9560 (define_insn "load_toc_v4_PIC_1"
9561 [(set (match_operand:SI 0 "register_operand" "=l")
9562 (match_operand:SI 1 "immediate_operand" "s"))
9563 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9564 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9565 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9566 "bcl 20,31,%1\\n%1:"
9567 [(set_attr "type" "branch")
9568 (set_attr "length" "4")])
9570 (define_insn "load_toc_v4_PIC_1b"
9571 [(set (match_operand:SI 0 "register_operand" "=l")
9572 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9573 UNSPEC_TOCPTR))]
9574 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9575 "bcl 20,31,$+8\\n\\t.long %1-$"
9576 [(set_attr "type" "branch")
9577 (set_attr "length" "8")])
9579 (define_insn "load_toc_v4_PIC_2"
9580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9581 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9582 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9583 (match_operand:SI 3 "immediate_operand" "s")))))]
9584 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9585 "{l|lwz} %0,%2-%3(%1)"
9586 [(set_attr "type" "load")])
9588 (define_insn "load_toc_v4_PIC_3b"
9589 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9590 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9591 (high:SI
9592 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9593 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9594 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9595 "{cau|addis} %0,%1,%2-%3@ha")
9597 (define_insn "load_toc_v4_PIC_3c"
9598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9599 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9600 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9601 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9602 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9603 "{cal|addi} %0,%1,%2-%3@l")
9605 ;; If the TOC is shared over a translation unit, as happens with all
9606 ;; the kinds of PIC that we support, we need to restore the TOC
9607 ;; pointer only when jumping over units of translation.
9608 ;; On Darwin, we need to reload the picbase.
9610 (define_expand "builtin_setjmp_receiver"
9611 [(use (label_ref (match_operand 0 "" "")))]
9612 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9613 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9614 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9615 "
9616 {
9617 #if TARGET_MACHO
9618 if (DEFAULT_ABI == ABI_DARWIN)
9619 {
9620 const char *picbase = machopic_function_base_name ();
9621 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9622 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9623 rtx tmplabrtx;
9624 char tmplab[20];
9626 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9627 CODE_LABEL_NUMBER (operands[0]));
9628 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9630 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9631 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9632 }
9633 else
9634 #endif
9635 rs6000_emit_load_toc_table (FALSE);
9636 DONE;
9637 }")
9639 ;; Elf specific ways of loading addresses for non-PIC code.
9640 ;; The output of this could be r0, but we make a very strong
9641 ;; preference for a base register because it will usually
9642 ;; be needed there.
9643 (define_insn "elf_high"
9644 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9645 (high:SI (match_operand 1 "" "")))]
9646 "TARGET_ELF && ! TARGET_64BIT"
9647 "{liu|lis} %0,%1@ha")
9649 (define_insn "elf_low"
9650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9651 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9652 (match_operand 2 "" "")))]
9653 "TARGET_ELF && ! TARGET_64BIT"
9654 "@
9655 {cal|la} %0,%2@l(%1)
9656 {ai|addic} %0,%1,%K2")
9657 \f
9658 ;; A function pointer under AIX is a pointer to a data area whose first word
9659 ;; contains the actual address of the function, whose second word contains a
9660 ;; pointer to its TOC, and whose third word contains a value to place in the
9661 ;; static chain register (r11). Note that if we load the static chain, our
9662 ;; "trampoline" need not have any executable code.
9664 (define_expand "call_indirect_aix32"
9665 [(set (match_dup 2)
9666 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9667 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9668 (reg:SI 2))
9669 (set (reg:SI 2)
9670 (mem:SI (plus:SI (match_dup 0)
9671 (const_int 4))))
9672 (set (reg:SI 11)
9673 (mem:SI (plus:SI (match_dup 0)
9674 (const_int 8))))
9675 (parallel [(call (mem:SI (match_dup 2))
9676 (match_operand 1 "" ""))
9677 (use (reg:SI 2))
9678 (use (reg:SI 11))
9679 (set (reg:SI 2)
9680 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9681 (clobber (scratch:SI))])]
9682 "TARGET_32BIT"
9683 "
9684 { operands[2] = gen_reg_rtx (SImode); }")
9686 (define_expand "call_indirect_aix64"
9687 [(set (match_dup 2)
9688 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9689 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9690 (reg:DI 2))
9691 (set (reg:DI 2)
9692 (mem:DI (plus:DI (match_dup 0)
9693 (const_int 8))))
9694 (set (reg:DI 11)
9695 (mem:DI (plus:DI (match_dup 0)
9696 (const_int 16))))
9697 (parallel [(call (mem:SI (match_dup 2))
9698 (match_operand 1 "" ""))
9699 (use (reg:DI 2))
9700 (use (reg:DI 11))
9701 (set (reg:DI 2)
9702 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9703 (clobber (scratch:SI))])]
9704 "TARGET_64BIT"
9705 "
9706 { operands[2] = gen_reg_rtx (DImode); }")
9708 (define_expand "call_value_indirect_aix32"
9709 [(set (match_dup 3)
9710 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9711 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9712 (reg:SI 2))
9713 (set (reg:SI 2)
9714 (mem:SI (plus:SI (match_dup 1)
9715 (const_int 4))))
9716 (set (reg:SI 11)
9717 (mem:SI (plus:SI (match_dup 1)
9718 (const_int 8))))
9719 (parallel [(set (match_operand 0 "" "")
9720 (call (mem:SI (match_dup 3))
9721 (match_operand 2 "" "")))
9722 (use (reg:SI 2))
9723 (use (reg:SI 11))
9724 (set (reg:SI 2)
9725 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9726 (clobber (scratch:SI))])]
9727 "TARGET_32BIT"
9728 "
9729 { operands[3] = gen_reg_rtx (SImode); }")
9731 (define_expand "call_value_indirect_aix64"
9732 [(set (match_dup 3)
9733 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9734 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9735 (reg:DI 2))
9736 (set (reg:DI 2)
9737 (mem:DI (plus:DI (match_dup 1)
9738 (const_int 8))))
9739 (set (reg:DI 11)
9740 (mem:DI (plus:DI (match_dup 1)
9741 (const_int 16))))
9742 (parallel [(set (match_operand 0 "" "")
9743 (call (mem:SI (match_dup 3))
9744 (match_operand 2 "" "")))
9745 (use (reg:DI 2))
9746 (use (reg:DI 11))
9747 (set (reg:DI 2)
9748 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9749 (clobber (scratch:SI))])]
9750 "TARGET_64BIT"
9751 "
9752 { operands[3] = gen_reg_rtx (DImode); }")
9754 ;; Now the definitions for the call and call_value insns
9755 (define_expand "call"
9756 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9757 (match_operand 1 "" ""))
9758 (use (match_operand 2 "" ""))
9759 (clobber (scratch:SI))])]
9760 ""
9761 "
9762 {
9763 #if TARGET_MACHO
9764 if (MACHOPIC_INDIRECT)
9765 operands[0] = machopic_indirect_call_target (operands[0]);
9766 #endif
9768 gcc_assert (GET_CODE (operands[0]) == MEM);
9769 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9771 operands[0] = XEXP (operands[0], 0);
9773 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9774 && flag_pic
9775 && GET_CODE (operands[0]) == SYMBOL_REF
9776 && !SYMBOL_REF_LOCAL_P (operands[0]))
9777 {
9778 rtx call;
9779 rtvec tmp;
9781 tmp = gen_rtvec (3,
9782 gen_rtx_CALL (VOIDmode,
9783 gen_rtx_MEM (SImode, operands[0]),
9784 operands[1]),
9785 gen_rtx_USE (VOIDmode, operands[2]),
9786 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9787 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9788 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9789 DONE;
9790 }
9792 if (GET_CODE (operands[0]) != SYMBOL_REF
9793 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9794 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9795 {
9796 if (INTVAL (operands[2]) & CALL_LONG)
9797 operands[0] = rs6000_longcall_ref (operands[0]);
9799 switch (DEFAULT_ABI)
9800 {
9801 case ABI_V4:
9802 case ABI_DARWIN:
9803 operands[0] = force_reg (Pmode, operands[0]);
9804 break;
9806 case ABI_AIX:
9807 /* AIX function pointers are really pointers to a three word
9808 area. */
9809 emit_call_insn (TARGET_32BIT
9810 ? gen_call_indirect_aix32 (force_reg (SImode,
9811 operands[0]),
9812 operands[1])
9813 : gen_call_indirect_aix64 (force_reg (DImode,
9814 operands[0]),
9815 operands[1]));
9816 DONE;
9818 default:
9819 gcc_unreachable ();
9820 }
9821 }
9822 }")
9824 (define_expand "call_value"
9825 [(parallel [(set (match_operand 0 "" "")
9826 (call (mem:SI (match_operand 1 "address_operand" ""))
9827 (match_operand 2 "" "")))
9828 (use (match_operand 3 "" ""))
9829 (clobber (scratch:SI))])]
9830 ""
9831 "
9832 {
9833 #if TARGET_MACHO
9834 if (MACHOPIC_INDIRECT)
9835 operands[1] = machopic_indirect_call_target (operands[1]);
9836 #endif
9838 gcc_assert (GET_CODE (operands[1]) == MEM);
9839 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9841 operands[1] = XEXP (operands[1], 0);
9843 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9844 && flag_pic
9845 && GET_CODE (operands[1]) == SYMBOL_REF
9846 && !SYMBOL_REF_LOCAL_P (operands[1]))
9847 {
9848 rtx call;
9849 rtvec tmp;
9851 tmp = gen_rtvec (3,
9852 gen_rtx_SET (VOIDmode,
9853 operands[0],
9854 gen_rtx_CALL (VOIDmode,
9855 gen_rtx_MEM (SImode,
9856 operands[1]),
9857 operands[2])),
9858 gen_rtx_USE (VOIDmode, operands[3]),
9859 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9860 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9861 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9862 DONE;
9863 }
9865 if (GET_CODE (operands[1]) != SYMBOL_REF
9866 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9867 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9868 {
9869 if (INTVAL (operands[3]) & CALL_LONG)
9870 operands[1] = rs6000_longcall_ref (operands[1]);
9872 switch (DEFAULT_ABI)
9873 {
9874 case ABI_V4:
9875 case ABI_DARWIN:
9876 operands[1] = force_reg (Pmode, operands[1]);
9877 break;
9879 case ABI_AIX:
9880 /* AIX function pointers are really pointers to a three word
9881 area. */
9882 emit_call_insn (TARGET_32BIT
9883 ? gen_call_value_indirect_aix32 (operands[0],
9884 force_reg (SImode,
9885 operands[1]),
9886 operands[2])
9887 : gen_call_value_indirect_aix64 (operands[0],
9888 force_reg (DImode,
9889 operands[1]),
9890 operands[2]));
9891 DONE;
9893 default:
9894 gcc_unreachable ();
9895 }
9896 }
9897 }")
9899 ;; Call to function in current module. No TOC pointer reload needed.
9900 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9901 ;; either the function was not prototyped, or it was prototyped as a
9902 ;; variable argument function. It is > 0 if FP registers were passed
9903 ;; and < 0 if they were not.
9905 (define_insn "*call_local32"
9906 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9907 (match_operand 1 "" "g,g"))
9908 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9909 (clobber (match_scratch:SI 3 "=l,l"))]
9910 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9911 "*
9912 {
9913 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9914 output_asm_insn (\"crxor 6,6,6\", operands);
9916 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9917 output_asm_insn (\"creqv 6,6,6\", operands);
9919 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9920 }"
9921 [(set_attr "type" "branch")
9922 (set_attr "length" "4,8")])
9924 (define_insn "*call_local64"
9925 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9926 (match_operand 1 "" "g,g"))
9927 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9928 (clobber (match_scratch:SI 3 "=l,l"))]
9929 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9930 "*
9931 {
9932 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9933 output_asm_insn (\"crxor 6,6,6\", operands);
9935 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9936 output_asm_insn (\"creqv 6,6,6\", operands);
9938 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9939 }"
9940 [(set_attr "type" "branch")
9941 (set_attr "length" "4,8")])
9943 (define_insn "*call_value_local32"
9944 [(set (match_operand 0 "" "")
9945 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9946 (match_operand 2 "" "g,g")))
9947 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9948 (clobber (match_scratch:SI 4 "=l,l"))]
9949 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9950 "*
9951 {
9952 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9953 output_asm_insn (\"crxor 6,6,6\", operands);
9955 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9956 output_asm_insn (\"creqv 6,6,6\", operands);
9958 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9959 }"
9960 [(set_attr "type" "branch")
9961 (set_attr "length" "4,8")])
9964 (define_insn "*call_value_local64"
9965 [(set (match_operand 0 "" "")
9966 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9967 (match_operand 2 "" "g,g")))
9968 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9969 (clobber (match_scratch:SI 4 "=l,l"))]
9970 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9971 "*
9972 {
9973 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9974 output_asm_insn (\"crxor 6,6,6\", operands);
9976 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9977 output_asm_insn (\"creqv 6,6,6\", operands);
9979 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9980 }"
9981 [(set_attr "type" "branch")
9982 (set_attr "length" "4,8")])
9984 ;; Call to function which may be in another module. Restore the TOC
9985 ;; pointer (r2) after the call unless this is System V.
9986 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9987 ;; either the function was not prototyped, or it was prototyped as a
9988 ;; variable argument function. It is > 0 if FP registers were passed
9989 ;; and < 0 if they were not.
9991 (define_insn "*call_indirect_nonlocal_aix32"
9992 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9993 (match_operand 1 "" "g,g"))
9994 (use (reg:SI 2))
9995 (use (reg:SI 11))
9996 (set (reg:SI 2)
9997 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9998 (clobber (match_scratch:SI 2 "=l,l"))]
9999 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10000 "b%T0l\;{l|lwz} 2,20(1)"
10001 [(set_attr "type" "jmpreg")
10002 (set_attr "length" "8")])
10004 (define_insn "*call_nonlocal_aix32"
10005 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10006 (match_operand 1 "" "g"))
10007 (use (match_operand:SI 2 "immediate_operand" "O"))
10008 (clobber (match_scratch:SI 3 "=l"))]
10009 "TARGET_32BIT
10010 && DEFAULT_ABI == ABI_AIX
10011 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10012 "bl %z0\;%."
10013 [(set_attr "type" "branch")
10014 (set_attr "length" "8")])
10016 (define_insn "*call_indirect_nonlocal_aix64"
10017 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10018 (match_operand 1 "" "g,g"))
10019 (use (reg:DI 2))
10020 (use (reg:DI 11))
10021 (set (reg:DI 2)
10022 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10023 (clobber (match_scratch:SI 2 "=l,l"))]
10024 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10025 "b%T0l\;ld 2,40(1)"
10026 [(set_attr "type" "jmpreg")
10027 (set_attr "length" "8")])
10029 (define_insn "*call_nonlocal_aix64"
10030 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10031 (match_operand 1 "" "g"))
10032 (use (match_operand:SI 2 "immediate_operand" "O"))
10033 (clobber (match_scratch:SI 3 "=l"))]
10034 "TARGET_64BIT
10035 && DEFAULT_ABI == ABI_AIX
10036 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10037 "bl %z0\;%."
10038 [(set_attr "type" "branch")
10039 (set_attr "length" "8")])
10041 (define_insn "*call_value_indirect_nonlocal_aix32"
10042 [(set (match_operand 0 "" "")
10043 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10044 (match_operand 2 "" "g,g")))
10045 (use (reg:SI 2))
10046 (use (reg:SI 11))
10047 (set (reg:SI 2)
10048 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10049 (clobber (match_scratch:SI 3 "=l,l"))]
10050 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10051 "b%T1l\;{l|lwz} 2,20(1)"
10052 [(set_attr "type" "jmpreg")
10053 (set_attr "length" "8")])
10055 (define_insn "*call_value_nonlocal_aix32"
10056 [(set (match_operand 0 "" "")
10057 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10058 (match_operand 2 "" "g")))
10059 (use (match_operand:SI 3 "immediate_operand" "O"))
10060 (clobber (match_scratch:SI 4 "=l"))]
10061 "TARGET_32BIT
10062 && DEFAULT_ABI == ABI_AIX
10063 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10064 "bl %z1\;%."
10065 [(set_attr "type" "branch")
10066 (set_attr "length" "8")])
10068 (define_insn "*call_value_indirect_nonlocal_aix64"
10069 [(set (match_operand 0 "" "")
10070 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10071 (match_operand 2 "" "g,g")))
10072 (use (reg:DI 2))
10073 (use (reg:DI 11))
10074 (set (reg:DI 2)
10075 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10076 (clobber (match_scratch:SI 3 "=l,l"))]
10077 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10078 "b%T1l\;ld 2,40(1)"
10079 [(set_attr "type" "jmpreg")
10080 (set_attr "length" "8")])
10082 (define_insn "*call_value_nonlocal_aix64"
10083 [(set (match_operand 0 "" "")
10084 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10085 (match_operand 2 "" "g")))
10086 (use (match_operand:SI 3 "immediate_operand" "O"))
10087 (clobber (match_scratch:SI 4 "=l"))]
10088 "TARGET_64BIT
10089 && DEFAULT_ABI == ABI_AIX
10090 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10091 "bl %z1\;%."
10092 [(set_attr "type" "branch")
10093 (set_attr "length" "8")])
10095 ;; A function pointer under System V is just a normal pointer
10096 ;; operands[0] is the function pointer
10097 ;; operands[1] is the stack size to clean up
10098 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10099 ;; which indicates how to set cr1
10101 (define_insn "*call_indirect_nonlocal_sysv"
10102 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10103 (match_operand 1 "" "g,g,g,g"))
10104 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10105 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10106 "DEFAULT_ABI == ABI_V4
10107 || DEFAULT_ABI == ABI_DARWIN"
10108 {
10109 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10110 output_asm_insn ("crxor 6,6,6", operands);
10112 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10113 output_asm_insn ("creqv 6,6,6", operands);
10115 return "b%T0l";
10116 }
10117 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10118 (set_attr "length" "4,4,8,8")])
10120 (define_insn "*call_nonlocal_sysv"
10121 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10122 (match_operand 1 "" "g,g"))
10123 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10124 (clobber (match_scratch:SI 3 "=l,l"))]
10125 "(DEFAULT_ABI == ABI_DARWIN
10126 || (DEFAULT_ABI == ABI_V4
10127 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10128 {
10129 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10130 output_asm_insn ("crxor 6,6,6", operands);
10132 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10133 output_asm_insn ("creqv 6,6,6", operands);
10135 #if TARGET_MACHO
10136 return output_call(insn, operands, 0, 2);
10137 #else
10138 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10139 {
10140 if (TARGET_SECURE_PLT && flag_pic == 2)
10141 /* The magic 32768 offset here and in the other sysv call insns
10142 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10143 See sysv4.h:toc_section. */
10144 return "bl %z0+32768@plt";
10145 else
10146 return "bl %z0@plt";
10147 }
10148 else
10149 return "bl %z0";
10150 #endif
10151 }
10152 [(set_attr "type" "branch,branch")
10153 (set_attr "length" "4,8")])
10155 (define_insn "*call_value_indirect_nonlocal_sysv"
10156 [(set (match_operand 0 "" "")
10157 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10158 (match_operand 2 "" "g,g,g,g")))
10159 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10160 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10161 "DEFAULT_ABI == ABI_V4
10162 || DEFAULT_ABI == ABI_DARWIN"
10163 {
10164 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10165 output_asm_insn ("crxor 6,6,6", operands);
10167 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10168 output_asm_insn ("creqv 6,6,6", operands);
10170 return "b%T1l";
10171 }
10172 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10173 (set_attr "length" "4,4,8,8")])
10175 (define_insn "*call_value_nonlocal_sysv"
10176 [(set (match_operand 0 "" "")
10177 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10178 (match_operand 2 "" "g,g")))
10179 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10180 (clobber (match_scratch:SI 4 "=l,l"))]
10181 "(DEFAULT_ABI == ABI_DARWIN
10182 || (DEFAULT_ABI == ABI_V4
10183 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10184 {
10185 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10186 output_asm_insn ("crxor 6,6,6", operands);
10188 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10189 output_asm_insn ("creqv 6,6,6", operands);
10191 #if TARGET_MACHO
10192 return output_call(insn, operands, 1, 3);
10193 #else
10194 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10195 {
10196 if (TARGET_SECURE_PLT && flag_pic == 2)
10197 return "bl %z1+32768@plt";
10198 else
10199 return "bl %z1@plt";
10200 }
10201 else
10202 return "bl %z1";
10203 #endif
10204 }
10205 [(set_attr "type" "branch,branch")
10206 (set_attr "length" "4,8")])
10208 ;; Call subroutine returning any type.
10209 (define_expand "untyped_call"
10210 [(parallel [(call (match_operand 0 "" "")
10211 (const_int 0))
10212 (match_operand 1 "" "")
10213 (match_operand 2 "" "")])]
10214 ""
10215 "
10216 {
10217 int i;
10219 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10221 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10222 {
10223 rtx set = XVECEXP (operands[2], 0, i);
10224 emit_move_insn (SET_DEST (set), SET_SRC (set));
10225 }
10227 /* The optimizer does not know that the call sets the function value
10228 registers we stored in the result block. We avoid problems by
10229 claiming that all hard registers are used and clobbered at this
10230 point. */
10231 emit_insn (gen_blockage ());
10233 DONE;
10234 }")
10236 ;; sibling call patterns
10237 (define_expand "sibcall"
10238 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10239 (match_operand 1 "" ""))
10240 (use (match_operand 2 "" ""))
10241 (use (match_operand 3 "" ""))
10242 (return)])]
10243 ""
10244 "
10245 {
10246 #if TARGET_MACHO
10247 if (MACHOPIC_INDIRECT)
10248 operands[0] = machopic_indirect_call_target (operands[0]);
10249 #endif
10251 gcc_assert (GET_CODE (operands[0]) == MEM);
10252 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10254 operands[0] = XEXP (operands[0], 0);
10255 operands[3] = gen_reg_rtx (SImode);
10257 }")
10259 ;; this and similar patterns must be marked as using LR, otherwise
10260 ;; dataflow will try to delete the store into it. This is true
10261 ;; even when the actual reg to jump to is in CTR, when LR was
10262 ;; saved and restored around the PIC-setting BCL.
10263 (define_insn "*sibcall_local32"
10264 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10265 (match_operand 1 "" "g,g"))
10266 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10267 (use (match_operand:SI 3 "register_operand" "l,l"))
10268 (return)]
10269 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10270 "*
10271 {
10272 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10273 output_asm_insn (\"crxor 6,6,6\", operands);
10275 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10276 output_asm_insn (\"creqv 6,6,6\", operands);
10278 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10279 }"
10280 [(set_attr "type" "branch")
10281 (set_attr "length" "4,8")])
10283 (define_insn "*sibcall_local64"
10284 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10285 (match_operand 1 "" "g,g"))
10286 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10287 (use (match_operand:SI 3 "register_operand" "l,l"))
10288 (return)]
10289 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10290 "*
10291 {
10292 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10293 output_asm_insn (\"crxor 6,6,6\", operands);
10295 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10296 output_asm_insn (\"creqv 6,6,6\", operands);
10298 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10299 }"
10300 [(set_attr "type" "branch")
10301 (set_attr "length" "4,8")])
10303 (define_insn "*sibcall_value_local32"
10304 [(set (match_operand 0 "" "")
10305 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10306 (match_operand 2 "" "g,g")))
10307 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10308 (use (match_operand:SI 4 "register_operand" "l,l"))
10309 (return)]
10310 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10311 "*
10312 {
10313 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10314 output_asm_insn (\"crxor 6,6,6\", operands);
10316 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10317 output_asm_insn (\"creqv 6,6,6\", operands);
10319 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10320 }"
10321 [(set_attr "type" "branch")
10322 (set_attr "length" "4,8")])
10325 (define_insn "*sibcall_value_local64"
10326 [(set (match_operand 0 "" "")
10327 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10328 (match_operand 2 "" "g,g")))
10329 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10330 (use (match_operand:SI 4 "register_operand" "l,l"))
10331 (return)]
10332 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10333 "*
10334 {
10335 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10336 output_asm_insn (\"crxor 6,6,6\", operands);
10338 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10339 output_asm_insn (\"creqv 6,6,6\", operands);
10341 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10342 }"
10343 [(set_attr "type" "branch")
10344 (set_attr "length" "4,8")])
10346 (define_insn "*sibcall_nonlocal_aix32"
10347 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10348 (match_operand 1 "" "g"))
10349 (use (match_operand:SI 2 "immediate_operand" "O"))
10350 (use (match_operand:SI 3 "register_operand" "l"))
10351 (return)]
10352 "TARGET_32BIT
10353 && DEFAULT_ABI == ABI_AIX
10354 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10355 "b %z0"
10356 [(set_attr "type" "branch")
10357 (set_attr "length" "4")])
10359 (define_insn "*sibcall_nonlocal_aix64"
10360 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10361 (match_operand 1 "" "g"))
10362 (use (match_operand:SI 2 "immediate_operand" "O"))
10363 (use (match_operand:SI 3 "register_operand" "l"))
10364 (return)]
10365 "TARGET_64BIT
10366 && DEFAULT_ABI == ABI_AIX
10367 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10368 "b %z0"
10369 [(set_attr "type" "branch")
10370 (set_attr "length" "4")])
10372 (define_insn "*sibcall_value_nonlocal_aix32"
10373 [(set (match_operand 0 "" "")
10374 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10375 (match_operand 2 "" "g")))
10376 (use (match_operand:SI 3 "immediate_operand" "O"))
10377 (use (match_operand:SI 4 "register_operand" "l"))
10378 (return)]
10379 "TARGET_32BIT
10380 && DEFAULT_ABI == ABI_AIX
10381 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10382 "b %z1"
10383 [(set_attr "type" "branch")
10384 (set_attr "length" "4")])
10386 (define_insn "*sibcall_value_nonlocal_aix64"
10387 [(set (match_operand 0 "" "")
10388 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10389 (match_operand 2 "" "g")))
10390 (use (match_operand:SI 3 "immediate_operand" "O"))
10391 (use (match_operand:SI 4 "register_operand" "l"))
10392 (return)]
10393 "TARGET_64BIT
10394 && DEFAULT_ABI == ABI_AIX
10395 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10396 "b %z1"
10397 [(set_attr "type" "branch")
10398 (set_attr "length" "4")])
10400 (define_insn "*sibcall_nonlocal_sysv"
10401 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10402 (match_operand 1 "" ""))
10403 (use (match_operand 2 "immediate_operand" "O,n"))
10404 (use (match_operand:SI 3 "register_operand" "l,l"))
10405 (return)]
10406 "(DEFAULT_ABI == ABI_DARWIN
10407 || DEFAULT_ABI == ABI_V4)
10408 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10409 "*
10410 {
10411 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10412 output_asm_insn (\"crxor 6,6,6\", operands);
10414 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10415 output_asm_insn (\"creqv 6,6,6\", operands);
10417 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10418 {
10419 if (TARGET_SECURE_PLT && flag_pic == 2)
10420 return \"b %z0+32768@plt\";
10421 else
10422 return \"b %z0@plt\";
10423 }
10424 else
10425 return \"b %z0\";
10426 }"
10427 [(set_attr "type" "branch,branch")
10428 (set_attr "length" "4,8")])
10430 (define_expand "sibcall_value"
10431 [(parallel [(set (match_operand 0 "register_operand" "")
10432 (call (mem:SI (match_operand 1 "address_operand" ""))
10433 (match_operand 2 "" "")))
10434 (use (match_operand 3 "" ""))
10435 (use (match_operand 4 "" ""))
10436 (return)])]
10437 ""
10438 "
10439 {
10440 #if TARGET_MACHO
10441 if (MACHOPIC_INDIRECT)
10442 operands[1] = machopic_indirect_call_target (operands[1]);
10443 #endif
10445 gcc_assert (GET_CODE (operands[1]) == MEM);
10446 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10448 operands[1] = XEXP (operands[1], 0);
10449 operands[4] = gen_reg_rtx (SImode);
10451 }")
10453 (define_insn "*sibcall_value_nonlocal_sysv"
10454 [(set (match_operand 0 "" "")
10455 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10456 (match_operand 2 "" "")))
10457 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10458 (use (match_operand:SI 4 "register_operand" "l,l"))
10459 (return)]
10460 "(DEFAULT_ABI == ABI_DARWIN
10461 || DEFAULT_ABI == ABI_V4)
10462 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10463 "*
10464 {
10465 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10466 output_asm_insn (\"crxor 6,6,6\", operands);
10468 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10469 output_asm_insn (\"creqv 6,6,6\", operands);
10471 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10472 {
10473 if (TARGET_SECURE_PLT && flag_pic == 2)
10474 return \"b %z1+32768@plt\";
10475 else
10476 return \"b %z1@plt\";
10477 }
10478 else
10479 return \"b %z1\";
10480 }"
10481 [(set_attr "type" "branch,branch")
10482 (set_attr "length" "4,8")])
10484 (define_expand "sibcall_epilogue"
10485 [(use (const_int 0))]
10486 "TARGET_SCHED_PROLOG"
10487 "
10488 {
10489 rs6000_emit_epilogue (TRUE);
10490 DONE;
10491 }")
10493 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10494 ;; all of memory. This blocks insns from being moved across this point.
10496 (define_insn "blockage"
10497 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10498 ""
10499 "")
10500 \f
10501 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10502 ;; signed & unsigned, and one type of branch.
10503 ;;
10504 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10505 ;; insns, and branches. We store the operands of compares until we see
10506 ;; how it is used.
10507 (define_expand "cmp<mode>"
10508 [(set (cc0)
10509 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10510 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10511 ""
10512 "
10513 {
10514 /* Take care of the possibility that operands[1] might be negative but
10515 this might be a logical operation. That insn doesn't exist. */
10516 if (GET_CODE (operands[1]) == CONST_INT
10517 && INTVAL (operands[1]) < 0)
10518 operands[1] = force_reg (<MODE>mode, operands[1]);
10520 rs6000_compare_op0 = operands[0];
10521 rs6000_compare_op1 = operands[1];
10522 rs6000_compare_fp_p = 0;
10523 DONE;
10524 }")
10526 (define_expand "cmp<mode>"
10527 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10528 (match_operand:FP 1 "gpc_reg_operand" "")))]
10529 ""
10530 "
10531 {
10532 rs6000_compare_op0 = operands[0];
10533 rs6000_compare_op1 = operands[1];
10534 rs6000_compare_fp_p = 1;
10535 DONE;
10536 }")
10538 (define_expand "beq"
10539 [(use (match_operand 0 "" ""))]
10540 ""
10541 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10543 (define_expand "bne"
10544 [(use (match_operand 0 "" ""))]
10545 ""
10546 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10548 (define_expand "bge"
10549 [(use (match_operand 0 "" ""))]
10550 ""
10551 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10553 (define_expand "bgt"
10554 [(use (match_operand 0 "" ""))]
10555 ""
10556 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10558 (define_expand "ble"
10559 [(use (match_operand 0 "" ""))]
10560 ""
10561 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10563 (define_expand "blt"
10564 [(use (match_operand 0 "" ""))]
10565 ""
10566 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10568 (define_expand "bgeu"
10569 [(use (match_operand 0 "" ""))]
10570 ""
10571 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10573 (define_expand "bgtu"
10574 [(use (match_operand 0 "" ""))]
10575 ""
10576 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10578 (define_expand "bleu"
10579 [(use (match_operand 0 "" ""))]
10580 ""
10581 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10583 (define_expand "bltu"
10584 [(use (match_operand 0 "" ""))]
10585 ""
10586 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10588 (define_expand "bunordered"
10589 [(use (match_operand 0 "" ""))]
10590 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10591 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10593 (define_expand "bordered"
10594 [(use (match_operand 0 "" ""))]
10595 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10596 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10598 (define_expand "buneq"
10599 [(use (match_operand 0 "" ""))]
10600 ""
10601 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10603 (define_expand "bunge"
10604 [(use (match_operand 0 "" ""))]
10605 ""
10606 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10608 (define_expand "bungt"
10609 [(use (match_operand 0 "" ""))]
10610 ""
10611 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10613 (define_expand "bunle"
10614 [(use (match_operand 0 "" ""))]
10615 ""
10616 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10618 (define_expand "bunlt"
10619 [(use (match_operand 0 "" ""))]
10620 ""
10621 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10623 (define_expand "bltgt"
10624 [(use (match_operand 0 "" ""))]
10625 ""
10626 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10628 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10629 ;; For SEQ, likewise, except that comparisons with zero should be done
10630 ;; with an scc insns. However, due to the order that combine see the
10631 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10632 ;; the cases we don't want to handle.
10633 (define_expand "seq"
10634 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10635 ""
10636 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10638 (define_expand "sne"
10639 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10640 ""
10641 "
10642 {
10643 if (! rs6000_compare_fp_p)
10644 FAIL;
10646 rs6000_emit_sCOND (NE, operands[0]);
10647 DONE;
10648 }")
10650 ;; A >= 0 is best done the portable way for A an integer.
10651 (define_expand "sge"
10652 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10653 ""
10654 "
10655 {
10656 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10657 FAIL;
10659 rs6000_emit_sCOND (GE, operands[0]);
10660 DONE;
10661 }")
10663 ;; A > 0 is best done using the portable sequence, so fail in that case.
10664 (define_expand "sgt"
10665 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10666 ""
10667 "
10668 {
10669 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10670 FAIL;
10672 rs6000_emit_sCOND (GT, operands[0]);
10673 DONE;
10674 }")
10676 ;; A <= 0 is best done the portable way for A an integer.
10677 (define_expand "sle"
10678 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10679 ""
10680 "
10681 {
10682 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10683 FAIL;
10685 rs6000_emit_sCOND (LE, operands[0]);
10686 DONE;
10687 }")
10689 ;; A < 0 is best done in the portable way for A an integer.
10690 (define_expand "slt"
10691 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10692 ""
10693 "
10694 {
10695 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10696 FAIL;
10698 rs6000_emit_sCOND (LT, operands[0]);
10699 DONE;
10700 }")
10702 (define_expand "sgeu"
10703 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10704 ""
10705 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10707 (define_expand "sgtu"
10708 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10709 ""
10710 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10712 (define_expand "sleu"
10713 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10714 ""
10715 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10717 (define_expand "sltu"
10718 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10719 ""
10720 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10722 (define_expand "sunordered"
10723 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10724 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10725 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10727 (define_expand "sordered"
10728 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10729 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10730 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10732 (define_expand "suneq"
10733 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10734 ""
10735 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10737 (define_expand "sunge"
10738 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10739 ""
10740 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10742 (define_expand "sungt"
10743 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10744 ""
10745 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10747 (define_expand "sunle"
10748 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10749 ""
10750 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10752 (define_expand "sunlt"
10753 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10754 ""
10755 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10757 (define_expand "sltgt"
10758 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10759 ""
10760 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10762 (define_expand "stack_protect_set"
10763 [(match_operand 0 "memory_operand" "")
10764 (match_operand 1 "memory_operand" "")]
10765 ""
10766 {
10767 #ifdef TARGET_THREAD_SSP_OFFSET
10768 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10769 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10770 operands[1] = gen_rtx_MEM (Pmode, addr);
10771 #endif
10772 if (TARGET_64BIT)
10773 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10774 else
10775 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10776 DONE;
10777 })
10779 (define_insn "stack_protect_setsi"
10780 [(set (match_operand:SI 0 "memory_operand" "=m")
10781 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10782 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10783 "TARGET_32BIT"
10784 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
10785 [(set_attr "type" "three")
10786 (set_attr "length" "12")])
10788 (define_insn "stack_protect_setdi"
10789 [(set (match_operand:DI 0 "memory_operand" "=m")
10790 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10791 (set (match_scratch:DI 2 "=&r") (const_int 0))]
10792 "TARGET_64BIT"
10793 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
10794 [(set_attr "type" "three")
10795 (set_attr "length" "12")])
10797 (define_expand "stack_protect_test"
10798 [(match_operand 0 "memory_operand" "")
10799 (match_operand 1 "memory_operand" "")
10800 (match_operand 2 "" "")]
10801 ""
10802 {
10803 #ifdef TARGET_THREAD_SSP_OFFSET
10804 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
10805 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
10806 operands[1] = gen_rtx_MEM (Pmode, addr);
10807 #endif
10808 rs6000_compare_op0 = operands[0];
10809 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
10810 UNSPEC_SP_TEST);
10811 rs6000_compare_fp_p = 0;
10812 emit_jump_insn (gen_beq (operands[2]));
10813 DONE;
10814 })
10816 (define_insn "stack_protect_testsi"
10817 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10818 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
10819 (match_operand:SI 2 "memory_operand" "m,m")]
10820 UNSPEC_SP_TEST))
10821 (clobber (match_scratch:SI 3 "=&r,&r"))
10822 (set (match_scratch:SI 4 "=r,r") (const_int 0))]
10823 "TARGET_32BIT"
10824 "@
10825 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10826 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10827 [(set_attr "length" "16,20")])
10829 (define_insn "stack_protect_testdi"
10830 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
10831 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
10832 (match_operand:DI 2 "memory_operand" "m,m")]
10833 UNSPEC_SP_TEST))
10834 (clobber (match_scratch:DI 3 "=&r,&r"))
10835 (set (match_scratch:DI 4 "=r,r") (const_int 0))]
10836 "TARGET_64BIT"
10837 "@
10838 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
10839 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
10840 [(set_attr "length" "16,20")])
10842 \f
10843 ;; Here are the actual compare insns.
10844 (define_insn "*cmp<mode>_internal1"
10845 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10846 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10847 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10848 ""
10849 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10850 [(set_attr "type" "cmp")])
10852 ;; If we are comparing a register for equality with a large constant,
10853 ;; we can do this with an XOR followed by a compare. But we need a scratch
10854 ;; register for the result of the XOR.
10856 (define_split
10857 [(set (match_operand:CC 0 "cc_reg_operand" "")
10858 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10859 (match_operand:SI 2 "non_short_cint_operand" "")))
10860 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10861 "find_single_use (operands[0], insn, 0)
10862 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10863 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10864 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10865 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10866 "
10867 {
10868 /* Get the constant we are comparing against, C, and see what it looks like
10869 sign-extended to 16 bits. Then see what constant could be XOR'ed
10870 with C to get the sign-extended value. */
10872 HOST_WIDE_INT c = INTVAL (operands[2]);
10873 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10874 HOST_WIDE_INT xorv = c ^ sextc;
10876 operands[4] = GEN_INT (xorv);
10877 operands[5] = GEN_INT (sextc);
10878 }")
10880 (define_insn "*cmpsi_internal2"
10881 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10882 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10883 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10884 ""
10885 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10886 [(set_attr "type" "cmp")])
10888 (define_insn "*cmpdi_internal2"
10889 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10890 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10891 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10892 ""
10893 "cmpld%I2 %0,%1,%b2"
10894 [(set_attr "type" "cmp")])
10896 ;; The following two insns don't exist as single insns, but if we provide
10897 ;; them, we can swap an add and compare, which will enable us to overlap more
10898 ;; of the required delay between a compare and branch. We generate code for
10899 ;; them by splitting.
10901 (define_insn ""
10902 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10903 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10904 (match_operand:SI 2 "short_cint_operand" "i")))
10905 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10906 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10907 ""
10908 "#"
10909 [(set_attr "length" "8")])
10911 (define_insn ""
10912 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10913 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10914 (match_operand:SI 2 "u_short_cint_operand" "i")))
10915 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10916 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10917 ""
10918 "#"
10919 [(set_attr "length" "8")])
10921 (define_split
10922 [(set (match_operand:CC 3 "cc_reg_operand" "")
10923 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10924 (match_operand:SI 2 "short_cint_operand" "")))
10925 (set (match_operand:SI 0 "gpc_reg_operand" "")
10926 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10927 ""
10928 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10929 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10931 (define_split
10932 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10933 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10934 (match_operand:SI 2 "u_short_cint_operand" "")))
10935 (set (match_operand:SI 0 "gpc_reg_operand" "")
10936 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10937 ""
10938 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10939 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10941 (define_insn "*cmpsf_internal1"
10942 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10943 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10944 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10945 "TARGET_HARD_FLOAT && TARGET_FPRS"
10946 "fcmpu %0,%1,%2"
10947 [(set_attr "type" "fpcompare")])
10949 (define_insn "*cmpdf_internal1"
10950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10951 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10952 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10953 "TARGET_HARD_FLOAT && TARGET_FPRS"
10954 "fcmpu %0,%1,%2"
10955 [(set_attr "type" "fpcompare")])
10957 ;; Only need to compare second words if first words equal
10958 (define_insn "*cmptf_internal1"
10959 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10960 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10961 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10962 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10963 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10964 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10965 [(set_attr "type" "fpcompare")
10966 (set_attr "length" "12")])
10968 (define_insn_and_split "*cmptf_internal2"
10969 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10970 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10971 (match_operand:TF 2 "gpc_reg_operand" "f")))
10972 (clobber (match_scratch:DF 3 "=f"))
10973 (clobber (match_scratch:DF 4 "=f"))
10974 (clobber (match_scratch:DF 5 "=f"))
10975 (clobber (match_scratch:DF 6 "=f"))
10976 (clobber (match_scratch:DF 7 "=f"))
10977 (clobber (match_scratch:DF 8 "=f"))
10978 (clobber (match_scratch:DF 9 "=f"))
10979 (clobber (match_scratch:DF 10 "=f"))]
10980 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10981 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10982 "#"
10983 "&& reload_completed"
10984 [(set (match_dup 3) (match_dup 13))
10985 (set (match_dup 4) (match_dup 14))
10986 (set (match_dup 9) (abs:DF (match_dup 5)))
10987 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10988 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10989 (label_ref (match_dup 11))
10990 (pc)))
10991 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10992 (set (pc) (label_ref (match_dup 12)))
10993 (match_dup 11)
10994 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10995 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10996 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10997 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10998 (match_dup 12)]
10999 {
11000 REAL_VALUE_TYPE rv;
11001 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11002 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11004 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11005 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11006 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11007 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11008 operands[11] = gen_label_rtx ();
11009 operands[12] = gen_label_rtx ();
11010 real_inf (&rv);
11011 operands[13] = force_const_mem (DFmode,
11012 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11013 operands[14] = force_const_mem (DFmode,
11014 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11015 DFmode));
11016 if (TARGET_TOC)
11017 {
11018 operands[13] = gen_const_mem (DFmode,
11019 create_TOC_reference (XEXP (operands[13], 0)));
11020 operands[14] = gen_const_mem (DFmode,
11021 create_TOC_reference (XEXP (operands[14], 0)));
11022 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11023 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11024 }
11025 })
11026 \f
11027 ;; Now we have the scc insns. We can do some combinations because of the
11028 ;; way the machine works.
11029 ;;
11030 ;; Note that this is probably faster if we can put an insn between the
11031 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11032 ;; cases the insns below which don't use an intermediate CR field will
11033 ;; be used instead.
11034 (define_insn ""
11035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11036 (match_operator:SI 1 "scc_comparison_operator"
11037 [(match_operand 2 "cc_reg_operand" "y")
11038 (const_int 0)]))]
11039 ""
11040 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11041 [(set (attr "type")
11042 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11043 (const_string "mfcrf")
11044 ]
11045 (const_string "mfcr")))
11046 (set_attr "length" "8")])
11048 ;; Same as above, but get the GT bit.
11049 (define_insn "move_from_CR_gt_bit"
11050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11051 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11052 "TARGET_E500"
11053 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11054 [(set_attr "type" "mfcr")
11055 (set_attr "length" "8")])
11057 ;; Same as above, but get the OV/ORDERED bit.
11058 (define_insn "move_from_CR_ov_bit"
11059 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11060 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11061 "TARGET_ISEL"
11062 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11063 [(set_attr "type" "mfcr")
11064 (set_attr "length" "8")])
11066 (define_insn ""
11067 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11068 (match_operator:DI 1 "scc_comparison_operator"
11069 [(match_operand 2 "cc_reg_operand" "y")
11070 (const_int 0)]))]
11071 "TARGET_POWERPC64"
11072 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11073 [(set (attr "type")
11074 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11075 (const_string "mfcrf")
11076 ]
11077 (const_string "mfcr")))
11078 (set_attr "length" "8")])
11080 (define_insn ""
11081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11082 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11083 [(match_operand 2 "cc_reg_operand" "y,y")
11084 (const_int 0)])
11085 (const_int 0)))
11086 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11087 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11088 "TARGET_32BIT"
11089 "@
11090 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11091 #"
11092 [(set_attr "type" "delayed_compare")
11093 (set_attr "length" "8,16")])
11095 (define_split
11096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11097 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11098 [(match_operand 2 "cc_reg_operand" "")
11099 (const_int 0)])
11100 (const_int 0)))
11101 (set (match_operand:SI 3 "gpc_reg_operand" "")
11102 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11103 "TARGET_32BIT && reload_completed"
11104 [(set (match_dup 3)
11105 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11106 (set (match_dup 0)
11107 (compare:CC (match_dup 3)
11108 (const_int 0)))]
11109 "")
11111 (define_insn ""
11112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11113 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11114 [(match_operand 2 "cc_reg_operand" "y")
11115 (const_int 0)])
11116 (match_operand:SI 3 "const_int_operand" "n")))]
11117 ""
11118 "*
11119 {
11120 int is_bit = ccr_bit (operands[1], 1);
11121 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11122 int count;
11124 if (is_bit >= put_bit)
11125 count = is_bit - put_bit;
11126 else
11127 count = 32 - (put_bit - is_bit);
11129 operands[4] = GEN_INT (count);
11130 operands[5] = GEN_INT (put_bit);
11132 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11133 }"
11134 [(set (attr "type")
11135 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11136 (const_string "mfcrf")
11137 ]
11138 (const_string "mfcr")))
11139 (set_attr "length" "8")])
11141 (define_insn ""
11142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11143 (compare:CC
11144 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11145 [(match_operand 2 "cc_reg_operand" "y,y")
11146 (const_int 0)])
11147 (match_operand:SI 3 "const_int_operand" "n,n"))
11148 (const_int 0)))
11149 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11150 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11151 (match_dup 3)))]
11152 ""
11153 "*
11154 {
11155 int is_bit = ccr_bit (operands[1], 1);
11156 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11157 int count;
11159 /* Force split for non-cc0 compare. */
11160 if (which_alternative == 1)
11161 return \"#\";
11163 if (is_bit >= put_bit)
11164 count = is_bit - put_bit;
11165 else
11166 count = 32 - (put_bit - is_bit);
11168 operands[5] = GEN_INT (count);
11169 operands[6] = GEN_INT (put_bit);
11171 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11172 }"
11173 [(set_attr "type" "delayed_compare")
11174 (set_attr "length" "8,16")])
11176 (define_split
11177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11178 (compare:CC
11179 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11180 [(match_operand 2 "cc_reg_operand" "")
11181 (const_int 0)])
11182 (match_operand:SI 3 "const_int_operand" ""))
11183 (const_int 0)))
11184 (set (match_operand:SI 4 "gpc_reg_operand" "")
11185 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11186 (match_dup 3)))]
11187 "reload_completed"
11188 [(set (match_dup 4)
11189 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11190 (match_dup 3)))
11191 (set (match_dup 0)
11192 (compare:CC (match_dup 4)
11193 (const_int 0)))]
11194 "")
11196 ;; There is a 3 cycle delay between consecutive mfcr instructions
11197 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11199 (define_peephole
11200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11201 (match_operator:SI 1 "scc_comparison_operator"
11202 [(match_operand 2 "cc_reg_operand" "y")
11203 (const_int 0)]))
11204 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11205 (match_operator:SI 4 "scc_comparison_operator"
11206 [(match_operand 5 "cc_reg_operand" "y")
11207 (const_int 0)]))]
11208 "REGNO (operands[2]) != REGNO (operands[5])"
11209 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11210 [(set_attr "type" "mfcr")
11211 (set_attr "length" "12")])
11213 (define_peephole
11214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11215 (match_operator:DI 1 "scc_comparison_operator"
11216 [(match_operand 2 "cc_reg_operand" "y")
11217 (const_int 0)]))
11218 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11219 (match_operator:DI 4 "scc_comparison_operator"
11220 [(match_operand 5 "cc_reg_operand" "y")
11221 (const_int 0)]))]
11222 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11223 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11224 [(set_attr "type" "mfcr")
11225 (set_attr "length" "12")])
11227 ;; There are some scc insns that can be done directly, without a compare.
11228 ;; These are faster because they don't involve the communications between
11229 ;; the FXU and branch units. In fact, we will be replacing all of the
11230 ;; integer scc insns here or in the portable methods in emit_store_flag.
11231 ;;
11232 ;; Also support (neg (scc ..)) since that construct is used to replace
11233 ;; branches, (plus (scc ..) ..) since that construct is common and
11234 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11235 ;; cases where it is no more expensive than (neg (scc ..)).
11237 ;; Have reload force a constant into a register for the simple insns that
11238 ;; otherwise won't accept constants. We do this because it is faster than
11239 ;; the cmp/mfcr sequence we would otherwise generate.
11241 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11242 (DI "rKJI")])
11244 (define_insn_and_split "*eq<mode>"
11245 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11246 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11247 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
11248 (clobber (match_scratch:GPR 3 "=r"))
11249 (clobber (match_scratch:GPR 4 "=r"))]
11250 ""
11251 "#"
11252 "reload_completed"
11253 [(set (match_dup 3)
11254 (clz:GPR (match_dup 4)))
11255 (set (match_dup 0)
11256 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
11257 {
11258 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11259 {
11260 if (logical_operand (operands[2], <MODE>mode))
11261 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11262 gen_rtx_XOR (<MODE>mode,
11263 operands[1], operands[2])));
11264 else
11265 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11266 gen_rtx_PLUS (<MODE>mode, operands[1],
11267 negate_rtx (<MODE>mode,
11268 operands[2]))));
11269 }
11270 else
11271 operands[4] = operands[1];
11273 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11274 })
11276 (define_insn_and_split "*eq<mode>_compare"
11277 [(set (match_operand:CC 5 "cc_reg_operand" "=y")
11278 (compare:CC
11279 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11280 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11281 (const_int 0)))
11282 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11283 (eq:P (match_dup 1) (match_dup 2)))
11284 (clobber (match_scratch:P 3 "=r"))
11285 (clobber (match_scratch:P 4 "=r"))]
11286 ""
11287 "#"
11288 "reload_completed"
11289 [(set (match_dup 3)
11290 (clz:P (match_dup 4)))
11291 (parallel [(set (match_dup 5)
11292 (compare:CC (lshiftrt:P (match_dup 3) (match_dup 6))
11293 (const_int 0)))
11294 (set (match_dup 0)
11295 (lshiftrt:P (match_dup 3) (match_dup 6)))])]
11296 {
11297 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11298 {
11299 if (logical_operand (operands[2], <MODE>mode))
11300 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11301 gen_rtx_XOR (<MODE>mode,
11302 operands[1], operands[2])));
11303 else
11304 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11305 gen_rtx_PLUS (<MODE>mode, operands[1],
11306 negate_rtx (<MODE>mode,
11307 operands[2]))));
11308 }
11309 else
11310 operands[4] = operands[1];
11312 operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11313 })
11315 ;; We have insns of the form shown by the first define_insn below. If
11316 ;; there is something inside the comparison operation, we must split it.
11317 (define_split
11318 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11319 (plus:SI (match_operator 1 "comparison_operator"
11320 [(match_operand:SI 2 "" "")
11321 (match_operand:SI 3
11322 "reg_or_cint_operand" "")])
11323 (match_operand:SI 4 "gpc_reg_operand" "")))
11324 (clobber (match_operand:SI 5 "register_operand" ""))]
11325 "! gpc_reg_operand (operands[2], SImode)"
11326 [(set (match_dup 5) (match_dup 2))
11327 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11328 (match_dup 4)))])
11330 (define_insn ""
11331 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11332 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11333 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11334 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11335 "TARGET_32BIT"
11336 "@
11337 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11338 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11339 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11340 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11341 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11342 [(set_attr "type" "three,two,three,three,three")
11343 (set_attr "length" "12,8,12,12,12")])
11345 (define_insn ""
11346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11347 (compare:CC
11348 (plus:SI
11349 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11350 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11351 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11352 (const_int 0)))
11353 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11354 "TARGET_32BIT"
11355 "@
11356 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11357 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11358 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11359 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11360 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11361 #
11362 #
11363 #
11364 #
11365 #"
11366 [(set_attr "type" "compare")
11367 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11369 (define_split
11370 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11371 (compare:CC
11372 (plus:SI
11373 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11374 (match_operand:SI 2 "scc_eq_operand" ""))
11375 (match_operand:SI 3 "gpc_reg_operand" ""))
11376 (const_int 0)))
11377 (clobber (match_scratch:SI 4 ""))]
11378 "TARGET_32BIT && reload_completed"
11379 [(set (match_dup 4)
11380 (plus:SI (eq:SI (match_dup 1)
11381 (match_dup 2))
11382 (match_dup 3)))
11383 (set (match_dup 0)
11384 (compare:CC (match_dup 4)
11385 (const_int 0)))]
11386 "")
11388 (define_insn ""
11389 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11390 (compare:CC
11391 (plus:SI
11392 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11393 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11394 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11395 (const_int 0)))
11396 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11397 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11398 "TARGET_32BIT"
11399 "@
11400 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11401 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11402 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11403 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11404 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11405 #
11406 #
11407 #
11408 #
11409 #"
11410 [(set_attr "type" "compare")
11411 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11413 (define_split
11414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11415 (compare:CC
11416 (plus:SI
11417 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11418 (match_operand:SI 2 "scc_eq_operand" ""))
11419 (match_operand:SI 3 "gpc_reg_operand" ""))
11420 (const_int 0)))
11421 (set (match_operand:SI 0 "gpc_reg_operand" "")
11422 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11423 "TARGET_32BIT && reload_completed"
11424 [(set (match_dup 0)
11425 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11426 (set (match_dup 4)
11427 (compare:CC (match_dup 0)
11428 (const_int 0)))]
11429 "")
11431 (define_insn ""
11432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11433 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11434 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
11435 "TARGET_32BIT"
11436 "@
11437 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11438 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11439 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11440 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11441 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11442 [(set_attr "type" "three,two,three,three,three")
11443 (set_attr "length" "12,8,12,12,12")])
11445 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11446 ;; since it nabs/sr is just as fast.
11447 (define_insn "*ne0"
11448 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11449 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11450 (const_int 31)))
11451 (clobber (match_scratch:SI 2 "=&r"))]
11452 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11453 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11454 [(set_attr "type" "two")
11455 (set_attr "length" "8")])
11457 (define_insn ""
11458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11459 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11460 (const_int 63)))
11461 (clobber (match_scratch:DI 2 "=&r"))]
11462 "TARGET_64BIT"
11463 "addic %2,%1,-1\;subfe %0,%2,%1"
11464 [(set_attr "type" "two")
11465 (set_attr "length" "8")])
11467 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11468 (define_insn ""
11469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11470 (plus:SI (lshiftrt:SI
11471 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11472 (const_int 31))
11473 (match_operand:SI 2 "gpc_reg_operand" "r")))
11474 (clobber (match_scratch:SI 3 "=&r"))]
11475 "TARGET_32BIT"
11476 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11477 [(set_attr "type" "two")
11478 (set_attr "length" "8")])
11480 (define_insn ""
11481 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11482 (plus:DI (lshiftrt:DI
11483 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11484 (const_int 63))
11485 (match_operand:DI 2 "gpc_reg_operand" "r")))
11486 (clobber (match_scratch:DI 3 "=&r"))]
11487 "TARGET_64BIT"
11488 "addic %3,%1,-1\;addze %0,%2"
11489 [(set_attr "type" "two")
11490 (set_attr "length" "8")])
11492 (define_insn ""
11493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11494 (compare:CC
11495 (plus:SI (lshiftrt:SI
11496 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11497 (const_int 31))
11498 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11499 (const_int 0)))
11500 (clobber (match_scratch:SI 3 "=&r,&r"))
11501 (clobber (match_scratch:SI 4 "=X,&r"))]
11502 "TARGET_32BIT"
11503 "@
11504 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11505 #"
11506 [(set_attr "type" "compare")
11507 (set_attr "length" "8,12")])
11509 (define_split
11510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11511 (compare:CC
11512 (plus:SI (lshiftrt:SI
11513 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11514 (const_int 31))
11515 (match_operand:SI 2 "gpc_reg_operand" ""))
11516 (const_int 0)))
11517 (clobber (match_scratch:SI 3 ""))
11518 (clobber (match_scratch:SI 4 ""))]
11519 "TARGET_32BIT && reload_completed"
11520 [(parallel [(set (match_dup 3)
11521 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11522 (const_int 31))
11523 (match_dup 2)))
11524 (clobber (match_dup 4))])
11525 (set (match_dup 0)
11526 (compare:CC (match_dup 3)
11527 (const_int 0)))]
11528 "")
11530 (define_insn ""
11531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11532 (compare:CC
11533 (plus:DI (lshiftrt:DI
11534 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11535 (const_int 63))
11536 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11537 (const_int 0)))
11538 (clobber (match_scratch:DI 3 "=&r,&r"))]
11539 "TARGET_64BIT"
11540 "@
11541 addic %3,%1,-1\;addze. %3,%2
11542 #"
11543 [(set_attr "type" "compare")
11544 (set_attr "length" "8,12")])
11546 (define_split
11547 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11548 (compare:CC
11549 (plus:DI (lshiftrt:DI
11550 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11551 (const_int 63))
11552 (match_operand:DI 2 "gpc_reg_operand" ""))
11553 (const_int 0)))
11554 (clobber (match_scratch:DI 3 ""))]
11555 "TARGET_64BIT && reload_completed"
11556 [(set (match_dup 3)
11557 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11558 (const_int 63))
11559 (match_dup 2)))
11560 (set (match_dup 0)
11561 (compare:CC (match_dup 3)
11562 (const_int 0)))]
11563 "")
11565 (define_insn ""
11566 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11567 (compare:CC
11568 (plus:SI (lshiftrt:SI
11569 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11570 (const_int 31))
11571 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11572 (const_int 0)))
11573 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11574 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11575 (match_dup 2)))
11576 (clobber (match_scratch:SI 3 "=&r,&r"))]
11577 "TARGET_32BIT"
11578 "@
11579 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11580 #"
11581 [(set_attr "type" "compare")
11582 (set_attr "length" "8,12")])
11584 (define_split
11585 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11586 (compare:CC
11587 (plus:SI (lshiftrt:SI
11588 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11589 (const_int 31))
11590 (match_operand:SI 2 "gpc_reg_operand" ""))
11591 (const_int 0)))
11592 (set (match_operand:SI 0 "gpc_reg_operand" "")
11593 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11594 (match_dup 2)))
11595 (clobber (match_scratch:SI 3 ""))]
11596 "TARGET_32BIT && reload_completed"
11597 [(parallel [(set (match_dup 0)
11598 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11599 (match_dup 2)))
11600 (clobber (match_dup 3))])
11601 (set (match_dup 4)
11602 (compare:CC (match_dup 0)
11603 (const_int 0)))]
11604 "")
11606 (define_insn ""
11607 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11608 (compare:CC
11609 (plus:DI (lshiftrt:DI
11610 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11611 (const_int 63))
11612 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11613 (const_int 0)))
11614 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11615 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11616 (match_dup 2)))
11617 (clobber (match_scratch:DI 3 "=&r,&r"))]
11618 "TARGET_64BIT"
11619 "@
11620 addic %3,%1,-1\;addze. %0,%2
11621 #"
11622 [(set_attr "type" "compare")
11623 (set_attr "length" "8,12")])
11625 (define_split
11626 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11627 (compare:CC
11628 (plus:DI (lshiftrt:DI
11629 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11630 (const_int 63))
11631 (match_operand:DI 2 "gpc_reg_operand" ""))
11632 (const_int 0)))
11633 (set (match_operand:DI 0 "gpc_reg_operand" "")
11634 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11635 (match_dup 2)))
11636 (clobber (match_scratch:DI 3 ""))]
11637 "TARGET_64BIT && reload_completed"
11638 [(parallel [(set (match_dup 0)
11639 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11640 (match_dup 2)))
11641 (clobber (match_dup 3))])
11642 (set (match_dup 4)
11643 (compare:CC (match_dup 0)
11644 (const_int 0)))]
11645 "")
11647 (define_insn ""
11648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11649 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11650 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11651 (clobber (match_scratch:SI 3 "=r,X"))]
11652 "TARGET_POWER"
11653 "@
11654 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11655 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11656 [(set_attr "length" "12")])
11658 (define_insn ""
11659 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11660 (compare:CC
11661 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11662 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11663 (const_int 0)))
11664 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11665 (le:SI (match_dup 1) (match_dup 2)))
11666 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11667 "TARGET_POWER"
11668 "@
11669 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11670 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11671 #
11672 #"
11673 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11674 (set_attr "length" "12,12,16,16")])
11676 (define_split
11677 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11678 (compare:CC
11679 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11680 (match_operand:SI 2 "reg_or_short_operand" ""))
11681 (const_int 0)))
11682 (set (match_operand:SI 0 "gpc_reg_operand" "")
11683 (le:SI (match_dup 1) (match_dup 2)))
11684 (clobber (match_scratch:SI 3 ""))]
11685 "TARGET_POWER && reload_completed"
11686 [(parallel [(set (match_dup 0)
11687 (le:SI (match_dup 1) (match_dup 2)))
11688 (clobber (match_dup 3))])
11689 (set (match_dup 4)
11690 (compare:CC (match_dup 0)
11691 (const_int 0)))]
11692 "")
11694 (define_insn ""
11695 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11696 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11697 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11698 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11699 "TARGET_POWER"
11700 "@
11701 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11702 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11703 [(set_attr "length" "12")])
11705 (define_insn ""
11706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11707 (compare:CC
11708 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11709 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11710 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11711 (const_int 0)))
11712 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11713 "TARGET_POWER"
11714 "@
11715 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11716 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11717 #
11718 #"
11719 [(set_attr "type" "compare")
11720 (set_attr "length" "12,12,16,16")])
11722 (define_split
11723 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11724 (compare:CC
11725 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11726 (match_operand:SI 2 "reg_or_short_operand" ""))
11727 (match_operand:SI 3 "gpc_reg_operand" ""))
11728 (const_int 0)))
11729 (clobber (match_scratch:SI 4 ""))]
11730 "TARGET_POWER && reload_completed"
11731 [(set (match_dup 4)
11732 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11733 (match_dup 3)))
11734 (set (match_dup 0)
11735 (compare:CC (match_dup 4)
11736 (const_int 0)))]
11737 "")
11739 (define_insn ""
11740 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11741 (compare:CC
11742 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11743 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11744 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11745 (const_int 0)))
11746 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11747 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11748 "TARGET_POWER"
11749 "@
11750 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11751 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11752 #
11753 #"
11754 [(set_attr "type" "compare")
11755 (set_attr "length" "12,12,16,16")])
11757 (define_split
11758 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11759 (compare:CC
11760 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11761 (match_operand:SI 2 "reg_or_short_operand" ""))
11762 (match_operand:SI 3 "gpc_reg_operand" ""))
11763 (const_int 0)))
11764 (set (match_operand:SI 0 "gpc_reg_operand" "")
11765 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11766 "TARGET_POWER && reload_completed"
11767 [(set (match_dup 0)
11768 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11769 (set (match_dup 4)
11770 (compare:CC (match_dup 0)
11771 (const_int 0)))]
11772 "")
11774 (define_insn ""
11775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11776 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11777 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11778 "TARGET_POWER"
11779 "@
11780 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11781 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11782 [(set_attr "length" "12")])
11784 (define_insn ""
11785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11786 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11787 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11788 "TARGET_32BIT"
11789 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11790 [(set_attr "type" "three")
11791 (set_attr "length" "12")])
11793 (define_insn ""
11794 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11795 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11796 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11797 "TARGET_64BIT"
11798 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11799 [(set_attr "type" "three")
11800 (set_attr "length" "12")])
11802 (define_insn ""
11803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11804 (compare:CC
11805 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11806 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11807 (const_int 0)))
11808 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11809 (leu:DI (match_dup 1) (match_dup 2)))]
11810 "TARGET_64BIT"
11811 "@
11812 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11813 #"
11814 [(set_attr "type" "compare")
11815 (set_attr "length" "12,16")])
11817 (define_split
11818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11819 (compare:CC
11820 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11821 (match_operand:DI 2 "reg_or_short_operand" ""))
11822 (const_int 0)))
11823 (set (match_operand:DI 0 "gpc_reg_operand" "")
11824 (leu:DI (match_dup 1) (match_dup 2)))]
11825 "TARGET_64BIT && reload_completed"
11826 [(set (match_dup 0)
11827 (leu:DI (match_dup 1) (match_dup 2)))
11828 (set (match_dup 3)
11829 (compare:CC (match_dup 0)
11830 (const_int 0)))]
11831 "")
11833 (define_insn ""
11834 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11835 (compare:CC
11836 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11837 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11838 (const_int 0)))
11839 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11840 (leu:SI (match_dup 1) (match_dup 2)))]
11841 "TARGET_32BIT"
11842 "@
11843 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11844 #"
11845 [(set_attr "type" "compare")
11846 (set_attr "length" "12,16")])
11848 (define_split
11849 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11850 (compare:CC
11851 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11852 (match_operand:SI 2 "reg_or_short_operand" ""))
11853 (const_int 0)))
11854 (set (match_operand:SI 0 "gpc_reg_operand" "")
11855 (leu:SI (match_dup 1) (match_dup 2)))]
11856 "TARGET_32BIT && reload_completed"
11857 [(set (match_dup 0)
11858 (leu:SI (match_dup 1) (match_dup 2)))
11859 (set (match_dup 3)
11860 (compare:CC (match_dup 0)
11861 (const_int 0)))]
11862 "")
11864 (define_insn ""
11865 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11866 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11867 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11868 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11869 "TARGET_32BIT"
11870 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11871 [(set_attr "type" "two")
11872 (set_attr "length" "8")])
11874 (define_insn ""
11875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11876 (compare:CC
11877 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11878 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11879 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11880 (const_int 0)))
11881 (clobber (match_scratch:SI 4 "=&r,&r"))]
11882 "TARGET_32BIT"
11883 "@
11884 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11885 #"
11886 [(set_attr "type" "compare")
11887 (set_attr "length" "8,12")])
11889 (define_split
11890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11891 (compare:CC
11892 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11893 (match_operand:SI 2 "reg_or_short_operand" ""))
11894 (match_operand:SI 3 "gpc_reg_operand" ""))
11895 (const_int 0)))
11896 (clobber (match_scratch:SI 4 ""))]
11897 "TARGET_32BIT && reload_completed"
11898 [(set (match_dup 4)
11899 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11900 (match_dup 3)))
11901 (set (match_dup 0)
11902 (compare:CC (match_dup 4)
11903 (const_int 0)))]
11904 "")
11906 (define_insn ""
11907 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11908 (compare:CC
11909 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11910 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11911 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11912 (const_int 0)))
11913 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11914 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11915 "TARGET_32BIT"
11916 "@
11917 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11918 #"
11919 [(set_attr "type" "compare")
11920 (set_attr "length" "8,12")])
11922 (define_split
11923 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11924 (compare:CC
11925 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11926 (match_operand:SI 2 "reg_or_short_operand" ""))
11927 (match_operand:SI 3 "gpc_reg_operand" ""))
11928 (const_int 0)))
11929 (set (match_operand:SI 0 "gpc_reg_operand" "")
11930 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11931 "TARGET_32BIT && reload_completed"
11932 [(set (match_dup 0)
11933 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11934 (set (match_dup 4)
11935 (compare:CC (match_dup 0)
11936 (const_int 0)))]
11937 "")
11939 (define_insn ""
11940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11941 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11942 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11943 "TARGET_32BIT"
11944 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11945 [(set_attr "type" "three")
11946 (set_attr "length" "12")])
11948 (define_insn ""
11949 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11950 (and:SI (neg:SI
11951 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11952 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11953 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11954 "TARGET_32BIT"
11955 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11956 [(set_attr "type" "three")
11957 (set_attr "length" "12")])
11959 (define_insn ""
11960 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11961 (compare:CC
11962 (and:SI (neg:SI
11963 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11964 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11965 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11966 (const_int 0)))
11967 (clobber (match_scratch:SI 4 "=&r,&r"))]
11968 "TARGET_32BIT"
11969 "@
11970 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11971 #"
11972 [(set_attr "type" "compare")
11973 (set_attr "length" "12,16")])
11975 (define_split
11976 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11977 (compare:CC
11978 (and:SI (neg:SI
11979 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11980 (match_operand:SI 2 "reg_or_short_operand" "")))
11981 (match_operand:SI 3 "gpc_reg_operand" ""))
11982 (const_int 0)))
11983 (clobber (match_scratch:SI 4 ""))]
11984 "TARGET_32BIT && reload_completed"
11985 [(set (match_dup 4)
11986 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11987 (match_dup 3)))
11988 (set (match_dup 0)
11989 (compare:CC (match_dup 4)
11990 (const_int 0)))]
11991 "")
11993 (define_insn ""
11994 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11995 (compare:CC
11996 (and:SI (neg:SI
11997 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11998 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11999 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12000 (const_int 0)))
12001 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12002 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12003 "TARGET_32BIT"
12004 "@
12005 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12006 #"
12007 [(set_attr "type" "compare")
12008 (set_attr "length" "12,16")])
12010 (define_split
12011 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12012 (compare:CC
12013 (and:SI (neg:SI
12014 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12015 (match_operand:SI 2 "reg_or_short_operand" "")))
12016 (match_operand:SI 3 "gpc_reg_operand" ""))
12017 (const_int 0)))
12018 (set (match_operand:SI 0 "gpc_reg_operand" "")
12019 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12020 "TARGET_32BIT && reload_completed"
12021 [(set (match_dup 0)
12022 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12023 (match_dup 3)))
12024 (set (match_dup 4)
12025 (compare:CC (match_dup 0)
12026 (const_int 0)))]
12027 "")
12029 (define_insn ""
12030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12031 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12032 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12033 "TARGET_POWER"
12034 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12035 [(set_attr "length" "12")])
12037 (define_insn ""
12038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12039 (compare:CC
12040 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12041 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12042 (const_int 0)))
12043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12044 (lt:SI (match_dup 1) (match_dup 2)))]
12045 "TARGET_POWER"
12046 "@
12047 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12048 #"
12049 [(set_attr "type" "delayed_compare")
12050 (set_attr "length" "12,16")])
12052 (define_split
12053 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12054 (compare:CC
12055 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12056 (match_operand:SI 2 "reg_or_short_operand" ""))
12057 (const_int 0)))
12058 (set (match_operand:SI 0 "gpc_reg_operand" "")
12059 (lt:SI (match_dup 1) (match_dup 2)))]
12060 "TARGET_POWER && reload_completed"
12061 [(set (match_dup 0)
12062 (lt:SI (match_dup 1) (match_dup 2)))
12063 (set (match_dup 3)
12064 (compare:CC (match_dup 0)
12065 (const_int 0)))]
12066 "")
12068 (define_insn ""
12069 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12070 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12071 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12072 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12073 "TARGET_POWER"
12074 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12075 [(set_attr "length" "12")])
12077 (define_insn ""
12078 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12079 (compare:CC
12080 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12081 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12082 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12083 (const_int 0)))
12084 (clobber (match_scratch:SI 4 "=&r,&r"))]
12085 "TARGET_POWER"
12086 "@
12087 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12088 #"
12089 [(set_attr "type" "compare")
12090 (set_attr "length" "12,16")])
12092 (define_split
12093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12094 (compare:CC
12095 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12096 (match_operand:SI 2 "reg_or_short_operand" ""))
12097 (match_operand:SI 3 "gpc_reg_operand" ""))
12098 (const_int 0)))
12099 (clobber (match_scratch:SI 4 ""))]
12100 "TARGET_POWER && reload_completed"
12101 [(set (match_dup 4)
12102 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12103 (match_dup 3)))
12104 (set (match_dup 0)
12105 (compare:CC (match_dup 4)
12106 (const_int 0)))]
12107 "")
12109 (define_insn ""
12110 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12111 (compare:CC
12112 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12113 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12114 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12115 (const_int 0)))
12116 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12117 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12118 "TARGET_POWER"
12119 "@
12120 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12121 #"
12122 [(set_attr "type" "compare")
12123 (set_attr "length" "12,16")])
12125 (define_split
12126 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12127 (compare:CC
12128 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12129 (match_operand:SI 2 "reg_or_short_operand" ""))
12130 (match_operand:SI 3 "gpc_reg_operand" ""))
12131 (const_int 0)))
12132 (set (match_operand:SI 0 "gpc_reg_operand" "")
12133 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12134 "TARGET_POWER && reload_completed"
12135 [(set (match_dup 0)
12136 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12137 (set (match_dup 4)
12138 (compare:CC (match_dup 0)
12139 (const_int 0)))]
12140 "")
12142 (define_insn ""
12143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12144 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12145 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12146 "TARGET_POWER"
12147 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12148 [(set_attr "length" "12")])
12150 (define_insn_and_split ""
12151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12152 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12153 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12154 "TARGET_32BIT"
12155 "#"
12156 "TARGET_32BIT"
12157 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12158 (set (match_dup 0) (neg:SI (match_dup 0)))]
12159 "")
12161 (define_insn_and_split ""
12162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12163 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12164 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12165 "TARGET_64BIT"
12166 "#"
12167 "TARGET_64BIT"
12168 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12169 (set (match_dup 0) (neg:DI (match_dup 0)))]
12170 "")
12172 (define_insn ""
12173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12174 (compare:CC
12175 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12176 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12177 (const_int 0)))
12178 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12179 (ltu:SI (match_dup 1) (match_dup 2)))]
12180 "TARGET_32BIT"
12181 "@
12182 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12183 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12184 #
12185 #"
12186 [(set_attr "type" "compare")
12187 (set_attr "length" "12,12,16,16")])
12189 (define_split
12190 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12191 (compare:CC
12192 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12193 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12194 (const_int 0)))
12195 (set (match_operand:SI 0 "gpc_reg_operand" "")
12196 (ltu:SI (match_dup 1) (match_dup 2)))]
12197 "TARGET_32BIT && reload_completed"
12198 [(set (match_dup 0)
12199 (ltu:SI (match_dup 1) (match_dup 2)))
12200 (set (match_dup 3)
12201 (compare:CC (match_dup 0)
12202 (const_int 0)))]
12203 "")
12205 (define_insn_and_split ""
12206 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12207 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12208 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12209 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12210 "TARGET_32BIT"
12211 "#"
12212 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12213 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12214 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12215 "")
12217 (define_insn_and_split ""
12218 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12219 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12220 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12221 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12222 "TARGET_64BIT"
12223 "#"
12224 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12225 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12226 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12227 "")
12229 (define_insn ""
12230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12231 (compare:CC
12232 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12233 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12234 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12235 (const_int 0)))
12236 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12237 "TARGET_32BIT"
12238 "@
12239 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12240 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12241 #
12242 #"
12243 [(set_attr "type" "compare")
12244 (set_attr "length" "12,12,16,16")])
12246 (define_split
12247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12248 (compare:CC
12249 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12250 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12251 (match_operand:SI 3 "gpc_reg_operand" ""))
12252 (const_int 0)))
12253 (clobber (match_scratch:SI 4 ""))]
12254 "TARGET_32BIT && reload_completed"
12255 [(set (match_dup 4)
12256 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12257 (match_dup 3)))
12258 (set (match_dup 0)
12259 (compare:CC (match_dup 4)
12260 (const_int 0)))]
12261 "")
12263 (define_insn ""
12264 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12265 (compare:CC
12266 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12267 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12268 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12269 (const_int 0)))
12270 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12271 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12272 "TARGET_32BIT"
12273 "@
12274 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12275 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12276 #
12277 #"
12278 [(set_attr "type" "compare")
12279 (set_attr "length" "12,12,16,16")])
12281 (define_split
12282 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12283 (compare:CC
12284 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12285 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12286 (match_operand:SI 3 "gpc_reg_operand" ""))
12287 (const_int 0)))
12288 (set (match_operand:SI 0 "gpc_reg_operand" "")
12289 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12290 "TARGET_32BIT && reload_completed"
12291 [(set (match_dup 0)
12292 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12293 (set (match_dup 4)
12294 (compare:CC (match_dup 0)
12295 (const_int 0)))]
12296 "")
12298 (define_insn ""
12299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12300 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12301 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12302 "TARGET_32BIT"
12303 "@
12304 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12305 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12306 [(set_attr "type" "two")
12307 (set_attr "length" "8")])
12309 (define_insn ""
12310 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12311 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12312 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12313 "TARGET_64BIT"
12314 "@
12315 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12316 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12317 [(set_attr "type" "two")
12318 (set_attr "length" "8")])
12320 (define_insn ""
12321 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12322 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12323 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12324 (clobber (match_scratch:SI 3 "=r"))]
12325 "TARGET_POWER"
12326 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12327 [(set_attr "length" "12")])
12329 (define_insn ""
12330 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12331 (compare:CC
12332 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12333 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12334 (const_int 0)))
12335 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12336 (ge:SI (match_dup 1) (match_dup 2)))
12337 (clobber (match_scratch:SI 3 "=r,r"))]
12338 "TARGET_POWER"
12339 "@
12340 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12341 #"
12342 [(set_attr "type" "compare")
12343 (set_attr "length" "12,16")])
12345 (define_split
12346 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12347 (compare:CC
12348 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12349 (match_operand:SI 2 "reg_or_short_operand" ""))
12350 (const_int 0)))
12351 (set (match_operand:SI 0 "gpc_reg_operand" "")
12352 (ge:SI (match_dup 1) (match_dup 2)))
12353 (clobber (match_scratch:SI 3 ""))]
12354 "TARGET_POWER && reload_completed"
12355 [(parallel [(set (match_dup 0)
12356 (ge:SI (match_dup 1) (match_dup 2)))
12357 (clobber (match_dup 3))])
12358 (set (match_dup 4)
12359 (compare:CC (match_dup 0)
12360 (const_int 0)))]
12361 "")
12363 (define_insn ""
12364 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12365 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12366 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12367 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12368 "TARGET_POWER"
12369 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12370 [(set_attr "length" "12")])
12372 (define_insn ""
12373 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12374 (compare:CC
12375 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12376 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12377 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12378 (const_int 0)))
12379 (clobber (match_scratch:SI 4 "=&r,&r"))]
12380 "TARGET_POWER"
12381 "@
12382 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12383 #"
12384 [(set_attr "type" "compare")
12385 (set_attr "length" "12,16")])
12387 (define_split
12388 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12389 (compare:CC
12390 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12391 (match_operand:SI 2 "reg_or_short_operand" ""))
12392 (match_operand:SI 3 "gpc_reg_operand" ""))
12393 (const_int 0)))
12394 (clobber (match_scratch:SI 4 ""))]
12395 "TARGET_POWER && reload_completed"
12396 [(set (match_dup 4)
12397 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12398 (match_dup 3)))
12399 (set (match_dup 0)
12400 (compare:CC (match_dup 4)
12401 (const_int 0)))]
12402 "")
12404 (define_insn ""
12405 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12406 (compare:CC
12407 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12408 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12409 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12410 (const_int 0)))
12411 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12412 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12413 "TARGET_POWER"
12414 "@
12415 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12416 #"
12417 [(set_attr "type" "compare")
12418 (set_attr "length" "12,16")])
12420 (define_split
12421 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12422 (compare:CC
12423 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12424 (match_operand:SI 2 "reg_or_short_operand" ""))
12425 (match_operand:SI 3 "gpc_reg_operand" ""))
12426 (const_int 0)))
12427 (set (match_operand:SI 0 "gpc_reg_operand" "")
12428 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12429 "TARGET_POWER && reload_completed"
12430 [(set (match_dup 0)
12431 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12432 (set (match_dup 4)
12433 (compare:CC (match_dup 0)
12434 (const_int 0)))]
12435 "")
12437 (define_insn ""
12438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12439 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12440 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12441 "TARGET_POWER"
12442 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12443 [(set_attr "length" "12")])
12445 (define_insn ""
12446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12447 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12448 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12449 "TARGET_32BIT"
12450 "@
12451 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12452 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12453 [(set_attr "type" "three")
12454 (set_attr "length" "12")])
12456 (define_insn ""
12457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12458 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12459 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12460 "TARGET_64BIT"
12461 "@
12462 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12463 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12464 [(set_attr "type" "three")
12465 (set_attr "length" "12")])
12467 (define_insn ""
12468 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12469 (compare:CC
12470 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12471 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12472 (const_int 0)))
12473 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12474 (geu:SI (match_dup 1) (match_dup 2)))]
12475 "TARGET_32BIT"
12476 "@
12477 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12478 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12479 #
12480 #"
12481 [(set_attr "type" "compare")
12482 (set_attr "length" "12,12,16,16")])
12484 (define_split
12485 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12486 (compare:CC
12487 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12488 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12489 (const_int 0)))
12490 (set (match_operand:SI 0 "gpc_reg_operand" "")
12491 (geu:SI (match_dup 1) (match_dup 2)))]
12492 "TARGET_32BIT && reload_completed"
12493 [(set (match_dup 0)
12494 (geu:SI (match_dup 1) (match_dup 2)))
12495 (set (match_dup 3)
12496 (compare:CC (match_dup 0)
12497 (const_int 0)))]
12498 "")
12500 (define_insn ""
12501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12502 (compare:CC
12503 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12504 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12505 (const_int 0)))
12506 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12507 (geu:DI (match_dup 1) (match_dup 2)))]
12508 "TARGET_64BIT"
12509 "@
12510 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12511 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12512 #
12513 #"
12514 [(set_attr "type" "compare")
12515 (set_attr "length" "12,12,16,16")])
12517 (define_split
12518 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12519 (compare:CC
12520 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12521 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12522 (const_int 0)))
12523 (set (match_operand:DI 0 "gpc_reg_operand" "")
12524 (geu:DI (match_dup 1) (match_dup 2)))]
12525 "TARGET_64BIT && reload_completed"
12526 [(set (match_dup 0)
12527 (geu:DI (match_dup 1) (match_dup 2)))
12528 (set (match_dup 3)
12529 (compare:CC (match_dup 0)
12530 (const_int 0)))]
12531 "")
12533 (define_insn ""
12534 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12535 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12536 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12537 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12538 "TARGET_32BIT"
12539 "@
12540 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12541 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12542 [(set_attr "type" "two")
12543 (set_attr "length" "8")])
12545 (define_insn ""
12546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12547 (compare:CC
12548 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12549 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12550 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12551 (const_int 0)))
12552 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12553 "TARGET_32BIT"
12554 "@
12555 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12556 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12557 #
12558 #"
12559 [(set_attr "type" "compare")
12560 (set_attr "length" "8,8,12,12")])
12562 (define_split
12563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12564 (compare:CC
12565 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12566 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12567 (match_operand:SI 3 "gpc_reg_operand" ""))
12568 (const_int 0)))
12569 (clobber (match_scratch:SI 4 ""))]
12570 "TARGET_32BIT && reload_completed"
12571 [(set (match_dup 4)
12572 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12573 (match_dup 3)))
12574 (set (match_dup 0)
12575 (compare:CC (match_dup 4)
12576 (const_int 0)))]
12577 "")
12579 (define_insn ""
12580 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12581 (compare:CC
12582 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12583 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12584 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12585 (const_int 0)))
12586 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12587 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12588 "TARGET_32BIT"
12589 "@
12590 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12591 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12592 #
12593 #"
12594 [(set_attr "type" "compare")
12595 (set_attr "length" "8,8,12,12")])
12597 (define_split
12598 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12599 (compare:CC
12600 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12601 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12602 (match_operand:SI 3 "gpc_reg_operand" ""))
12603 (const_int 0)))
12604 (set (match_operand:SI 0 "gpc_reg_operand" "")
12605 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12606 "TARGET_32BIT && reload_completed"
12607 [(set (match_dup 0)
12608 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12609 (set (match_dup 4)
12610 (compare:CC (match_dup 0)
12611 (const_int 0)))]
12612 "")
12614 (define_insn ""
12615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12616 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12617 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12618 "TARGET_32BIT"
12619 "@
12620 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12621 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12622 [(set_attr "type" "three")
12623 (set_attr "length" "12")])
12625 (define_insn ""
12626 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12627 (and:SI (neg:SI
12628 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12629 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12630 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12631 "TARGET_32BIT"
12632 "@
12633 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12634 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12635 [(set_attr "type" "three")
12636 (set_attr "length" "12")])
12638 (define_insn ""
12639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12640 (compare:CC
12641 (and:SI (neg:SI
12642 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12643 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12644 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12645 (const_int 0)))
12646 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12647 "TARGET_32BIT"
12648 "@
12649 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12650 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12651 #
12652 #"
12653 [(set_attr "type" "compare")
12654 (set_attr "length" "12,12,16,16")])
12656 (define_split
12657 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12658 (compare:CC
12659 (and:SI (neg:SI
12660 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12661 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12662 (match_operand:SI 3 "gpc_reg_operand" ""))
12663 (const_int 0)))
12664 (clobber (match_scratch:SI 4 ""))]
12665 "TARGET_32BIT && reload_completed"
12666 [(set (match_dup 4)
12667 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12668 (match_dup 3)))
12669 (set (match_dup 0)
12670 (compare:CC (match_dup 4)
12671 (const_int 0)))]
12672 "")
12674 (define_insn ""
12675 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12676 (compare:CC
12677 (and:SI (neg:SI
12678 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12679 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12680 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12681 (const_int 0)))
12682 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12683 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12684 "TARGET_32BIT"
12685 "@
12686 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12687 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12688 #
12689 #"
12690 [(set_attr "type" "compare")
12691 (set_attr "length" "12,12,16,16")])
12693 (define_split
12694 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12695 (compare:CC
12696 (and:SI (neg:SI
12697 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12698 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12699 (match_operand:SI 3 "gpc_reg_operand" ""))
12700 (const_int 0)))
12701 (set (match_operand:SI 0 "gpc_reg_operand" "")
12702 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12703 "TARGET_32BIT && reload_completed"
12704 [(set (match_dup 0)
12705 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12706 (set (match_dup 4)
12707 (compare:CC (match_dup 0)
12708 (const_int 0)))]
12709 "")
12711 (define_insn ""
12712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12713 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12714 (const_int 0)))]
12715 "TARGET_32BIT"
12716 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12717 [(set_attr "type" "three")
12718 (set_attr "length" "12")])
12720 (define_insn ""
12721 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12722 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12723 (const_int 0)))]
12724 "TARGET_64BIT"
12725 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12726 [(set_attr "type" "three")
12727 (set_attr "length" "12")])
12729 (define_insn ""
12730 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12731 (compare:CC
12732 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12733 (const_int 0))
12734 (const_int 0)))
12735 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12736 (gt:SI (match_dup 1) (const_int 0)))]
12737 "TARGET_32BIT"
12738 "@
12739 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12740 #"
12741 [(set_attr "type" "delayed_compare")
12742 (set_attr "length" "12,16")])
12744 (define_split
12745 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12746 (compare:CC
12747 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12748 (const_int 0))
12749 (const_int 0)))
12750 (set (match_operand:SI 0 "gpc_reg_operand" "")
12751 (gt:SI (match_dup 1) (const_int 0)))]
12752 "TARGET_32BIT && reload_completed"
12753 [(set (match_dup 0)
12754 (gt:SI (match_dup 1) (const_int 0)))
12755 (set (match_dup 2)
12756 (compare:CC (match_dup 0)
12757 (const_int 0)))]
12758 "")
12760 (define_insn ""
12761 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12762 (compare:CC
12763 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12764 (const_int 0))
12765 (const_int 0)))
12766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12767 (gt:DI (match_dup 1) (const_int 0)))]
12768 "TARGET_64BIT"
12769 "@
12770 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12771 #"
12772 [(set_attr "type" "delayed_compare")
12773 (set_attr "length" "12,16")])
12775 (define_split
12776 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12777 (compare:CC
12778 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12779 (const_int 0))
12780 (const_int 0)))
12781 (set (match_operand:DI 0 "gpc_reg_operand" "")
12782 (gt:DI (match_dup 1) (const_int 0)))]
12783 "TARGET_64BIT && reload_completed"
12784 [(set (match_dup 0)
12785 (gt:DI (match_dup 1) (const_int 0)))
12786 (set (match_dup 2)
12787 (compare:CC (match_dup 0)
12788 (const_int 0)))]
12789 "")
12791 (define_insn ""
12792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12793 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12794 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12795 "TARGET_POWER"
12796 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12797 [(set_attr "length" "12")])
12799 (define_insn ""
12800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12801 (compare:CC
12802 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12803 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12804 (const_int 0)))
12805 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12806 (gt:SI (match_dup 1) (match_dup 2)))]
12807 "TARGET_POWER"
12808 "@
12809 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12810 #"
12811 [(set_attr "type" "delayed_compare")
12812 (set_attr "length" "12,16")])
12814 (define_split
12815 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12816 (compare:CC
12817 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12818 (match_operand:SI 2 "reg_or_short_operand" ""))
12819 (const_int 0)))
12820 (set (match_operand:SI 0 "gpc_reg_operand" "")
12821 (gt:SI (match_dup 1) (match_dup 2)))]
12822 "TARGET_POWER && reload_completed"
12823 [(set (match_dup 0)
12824 (gt:SI (match_dup 1) (match_dup 2)))
12825 (set (match_dup 3)
12826 (compare:CC (match_dup 0)
12827 (const_int 0)))]
12828 "")
12830 (define_insn ""
12831 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12832 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12833 (const_int 0))
12834 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12835 "TARGET_32BIT"
12836 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12837 [(set_attr "type" "three")
12838 (set_attr "length" "12")])
12840 (define_insn ""
12841 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12842 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12843 (const_int 0))
12844 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12845 "TARGET_64BIT"
12846 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12847 [(set_attr "type" "three")
12848 (set_attr "length" "12")])
12850 (define_insn ""
12851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12852 (compare:CC
12853 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12854 (const_int 0))
12855 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12856 (const_int 0)))
12857 (clobber (match_scratch:SI 3 "=&r,&r"))]
12858 "TARGET_32BIT"
12859 "@
12860 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12861 #"
12862 [(set_attr "type" "compare")
12863 (set_attr "length" "12,16")])
12865 (define_split
12866 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12867 (compare:CC
12868 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12869 (const_int 0))
12870 (match_operand:SI 2 "gpc_reg_operand" ""))
12871 (const_int 0)))
12872 (clobber (match_scratch:SI 3 ""))]
12873 "TARGET_32BIT && reload_completed"
12874 [(set (match_dup 3)
12875 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12876 (match_dup 2)))
12877 (set (match_dup 0)
12878 (compare:CC (match_dup 3)
12879 (const_int 0)))]
12880 "")
12882 (define_insn ""
12883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12884 (compare:CC
12885 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12886 (const_int 0))
12887 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12888 (const_int 0)))
12889 (clobber (match_scratch:DI 3 "=&r,&r"))]
12890 "TARGET_64BIT"
12891 "@
12892 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12893 #"
12894 [(set_attr "type" "compare")
12895 (set_attr "length" "12,16")])
12897 (define_split
12898 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12899 (compare:CC
12900 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12901 (const_int 0))
12902 (match_operand:DI 2 "gpc_reg_operand" ""))
12903 (const_int 0)))
12904 (clobber (match_scratch:DI 3 ""))]
12905 "TARGET_64BIT && reload_completed"
12906 [(set (match_dup 3)
12907 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12908 (match_dup 2)))
12909 (set (match_dup 0)
12910 (compare:CC (match_dup 3)
12911 (const_int 0)))]
12912 "")
12914 (define_insn ""
12915 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12916 (compare:CC
12917 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12918 (const_int 0))
12919 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12920 (const_int 0)))
12921 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12922 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12923 "TARGET_32BIT"
12924 "@
12925 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12926 #"
12927 [(set_attr "type" "compare")
12928 (set_attr "length" "12,16")])
12930 (define_split
12931 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12932 (compare:CC
12933 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12934 (const_int 0))
12935 (match_operand:SI 2 "gpc_reg_operand" ""))
12936 (const_int 0)))
12937 (set (match_operand:SI 0 "gpc_reg_operand" "")
12938 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12939 "TARGET_32BIT && reload_completed"
12940 [(set (match_dup 0)
12941 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12942 (set (match_dup 3)
12943 (compare:CC (match_dup 0)
12944 (const_int 0)))]
12945 "")
12947 (define_insn ""
12948 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12949 (compare:CC
12950 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12951 (const_int 0))
12952 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12953 (const_int 0)))
12954 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12955 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12956 "TARGET_64BIT"
12957 "@
12958 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12959 #"
12960 [(set_attr "type" "compare")
12961 (set_attr "length" "12,16")])
12963 (define_split
12964 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12965 (compare:CC
12966 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12967 (const_int 0))
12968 (match_operand:DI 2 "gpc_reg_operand" ""))
12969 (const_int 0)))
12970 (set (match_operand:DI 0 "gpc_reg_operand" "")
12971 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12972 "TARGET_64BIT && reload_completed"
12973 [(set (match_dup 0)
12974 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12975 (set (match_dup 3)
12976 (compare:CC (match_dup 0)
12977 (const_int 0)))]
12978 "")
12980 (define_insn ""
12981 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12982 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12983 (match_operand:SI 2 "reg_or_short_operand" "r"))
12984 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12985 "TARGET_POWER"
12986 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12987 [(set_attr "length" "12")])
12989 (define_insn ""
12990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12991 (compare:CC
12992 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12993 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12994 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12995 (const_int 0)))
12996 (clobber (match_scratch:SI 4 "=&r,&r"))]
12997 "TARGET_POWER"
12998 "@
12999 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13000 #"
13001 [(set_attr "type" "compare")
13002 (set_attr "length" "12,16")])
13004 (define_split
13005 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13006 (compare:CC
13007 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13008 (match_operand:SI 2 "reg_or_short_operand" ""))
13009 (match_operand:SI 3 "gpc_reg_operand" ""))
13010 (const_int 0)))
13011 (clobber (match_scratch:SI 4 ""))]
13012 "TARGET_POWER && reload_completed"
13013 [(set (match_dup 4)
13014 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13015 (set (match_dup 0)
13016 (compare:CC (match_dup 4)
13017 (const_int 0)))]
13018 "")
13020 (define_insn ""
13021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13022 (compare:CC
13023 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13024 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13025 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13026 (const_int 0)))
13027 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13028 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13029 "TARGET_POWER"
13030 "@
13031 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13032 #"
13033 [(set_attr "type" "compare")
13034 (set_attr "length" "12,16")])
13036 (define_split
13037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13038 (compare:CC
13039 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13040 (match_operand:SI 2 "reg_or_short_operand" ""))
13041 (match_operand:SI 3 "gpc_reg_operand" ""))
13042 (const_int 0)))
13043 (set (match_operand:SI 0 "gpc_reg_operand" "")
13044 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13045 "TARGET_POWER && reload_completed"
13046 [(set (match_dup 0)
13047 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13048 (set (match_dup 4)
13049 (compare:CC (match_dup 0)
13050 (const_int 0)))]
13051 "")
13053 (define_insn ""
13054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13055 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13056 (const_int 0))))]
13057 "TARGET_32BIT"
13058 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13059 [(set_attr "type" "three")
13060 (set_attr "length" "12")])
13062 (define_insn ""
13063 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13064 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13065 (const_int 0))))]
13066 "TARGET_64BIT"
13067 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13068 [(set_attr "type" "three")
13069 (set_attr "length" "12")])
13071 (define_insn ""
13072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13073 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13074 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13075 "TARGET_POWER"
13076 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13077 [(set_attr "length" "12")])
13079 (define_insn_and_split ""
13080 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13081 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13082 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13083 "TARGET_32BIT"
13084 "#"
13085 "TARGET_32BIT"
13086 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13087 (set (match_dup 0) (neg:SI (match_dup 0)))]
13088 "")
13090 (define_insn_and_split ""
13091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13092 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13093 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13094 "TARGET_64BIT"
13095 "#"
13096 "TARGET_64BIT"
13097 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13098 (set (match_dup 0) (neg:DI (match_dup 0)))]
13099 "")
13101 (define_insn ""
13102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13103 (compare:CC
13104 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13105 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13106 (const_int 0)))
13107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13108 (gtu:SI (match_dup 1) (match_dup 2)))]
13109 "TARGET_32BIT"
13110 "@
13111 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13112 #"
13113 [(set_attr "type" "compare")
13114 (set_attr "length" "12,16")])
13116 (define_split
13117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13118 (compare:CC
13119 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13120 (match_operand:SI 2 "reg_or_short_operand" ""))
13121 (const_int 0)))
13122 (set (match_operand:SI 0 "gpc_reg_operand" "")
13123 (gtu:SI (match_dup 1) (match_dup 2)))]
13124 "TARGET_32BIT && reload_completed"
13125 [(set (match_dup 0)
13126 (gtu:SI (match_dup 1) (match_dup 2)))
13127 (set (match_dup 3)
13128 (compare:CC (match_dup 0)
13129 (const_int 0)))]
13130 "")
13132 (define_insn ""
13133 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13134 (compare:CC
13135 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13136 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13137 (const_int 0)))
13138 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13139 (gtu:DI (match_dup 1) (match_dup 2)))]
13140 "TARGET_64BIT"
13141 "@
13142 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13143 #"
13144 [(set_attr "type" "compare")
13145 (set_attr "length" "12,16")])
13147 (define_split
13148 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13149 (compare:CC
13150 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13151 (match_operand:DI 2 "reg_or_short_operand" ""))
13152 (const_int 0)))
13153 (set (match_operand:DI 0 "gpc_reg_operand" "")
13154 (gtu:DI (match_dup 1) (match_dup 2)))]
13155 "TARGET_64BIT && reload_completed"
13156 [(set (match_dup 0)
13157 (gtu:DI (match_dup 1) (match_dup 2)))
13158 (set (match_dup 3)
13159 (compare:CC (match_dup 0)
13160 (const_int 0)))]
13161 "")
13163 (define_insn_and_split ""
13164 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13165 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13166 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13167 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13168 "TARGET_32BIT"
13169 "#"
13170 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13171 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13172 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13173 "")
13175 (define_insn_and_split ""
13176 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13177 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13178 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13179 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13180 "TARGET_64BIT"
13181 "#"
13182 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13183 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13184 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13185 "")
13187 (define_insn ""
13188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13189 (compare:CC
13190 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13191 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13192 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13193 (const_int 0)))
13194 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13195 "TARGET_32BIT"
13196 "@
13197 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13198 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13199 #
13200 #"
13201 [(set_attr "type" "compare")
13202 (set_attr "length" "8,12,12,16")])
13204 (define_split
13205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13206 (compare:CC
13207 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13208 (match_operand:SI 2 "reg_or_short_operand" ""))
13209 (match_operand:SI 3 "gpc_reg_operand" ""))
13210 (const_int 0)))
13211 (clobber (match_scratch:SI 4 ""))]
13212 "TARGET_32BIT && reload_completed"
13213 [(set (match_dup 4)
13214 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13215 (match_dup 3)))
13216 (set (match_dup 0)
13217 (compare:CC (match_dup 4)
13218 (const_int 0)))]
13219 "")
13221 (define_insn ""
13222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13223 (compare:CC
13224 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13225 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13226 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13227 (const_int 0)))
13228 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13229 "TARGET_64BIT"
13230 "@
13231 addic %4,%1,%k2\;addze. %4,%3
13232 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13233 #
13234 #"
13235 [(set_attr "type" "compare")
13236 (set_attr "length" "8,12,12,16")])
13238 (define_split
13239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13240 (compare:CC
13241 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13242 (match_operand:DI 2 "reg_or_short_operand" ""))
13243 (match_operand:DI 3 "gpc_reg_operand" ""))
13244 (const_int 0)))
13245 (clobber (match_scratch:DI 4 ""))]
13246 "TARGET_64BIT && reload_completed"
13247 [(set (match_dup 4)
13248 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13249 (match_dup 3)))
13250 (set (match_dup 0)
13251 (compare:CC (match_dup 4)
13252 (const_int 0)))]
13253 "")
13255 (define_insn ""
13256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13257 (compare:CC
13258 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13259 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13260 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13261 (const_int 0)))
13262 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13263 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13264 "TARGET_32BIT"
13265 "@
13266 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13267 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13268 #
13269 #"
13270 [(set_attr "type" "compare")
13271 (set_attr "length" "8,12,12,16")])
13273 (define_split
13274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13275 (compare:CC
13276 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13277 (match_operand:SI 2 "reg_or_short_operand" ""))
13278 (match_operand:SI 3 "gpc_reg_operand" ""))
13279 (const_int 0)))
13280 (set (match_operand:SI 0 "gpc_reg_operand" "")
13281 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13282 "TARGET_32BIT && reload_completed"
13283 [(set (match_dup 0)
13284 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13285 (set (match_dup 4)
13286 (compare:CC (match_dup 0)
13287 (const_int 0)))]
13288 "")
13290 (define_insn ""
13291 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13292 (compare:CC
13293 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13294 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13295 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13296 (const_int 0)))
13297 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13298 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13299 "TARGET_64BIT"
13300 "@
13301 addic %0,%1,%k2\;addze. %0,%3
13302 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13303 #
13304 #"
13305 [(set_attr "type" "compare")
13306 (set_attr "length" "8,12,12,16")])
13308 (define_split
13309 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13310 (compare:CC
13311 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13312 (match_operand:DI 2 "reg_or_short_operand" ""))
13313 (match_operand:DI 3 "gpc_reg_operand" ""))
13314 (const_int 0)))
13315 (set (match_operand:DI 0 "gpc_reg_operand" "")
13316 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13317 "TARGET_64BIT && reload_completed"
13318 [(set (match_dup 0)
13319 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13320 (set (match_dup 4)
13321 (compare:CC (match_dup 0)
13322 (const_int 0)))]
13323 "")
13325 (define_insn ""
13326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13327 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13328 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13329 "TARGET_32BIT"
13330 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13331 [(set_attr "type" "two")
13332 (set_attr "length" "8")])
13334 (define_insn ""
13335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13336 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13337 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13338 "TARGET_64BIT"
13339 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13340 [(set_attr "type" "two")
13341 (set_attr "length" "8")])
13342 \f
13343 ;; Define both directions of branch and return. If we need a reload
13344 ;; register, we'd rather use CR0 since it is much easier to copy a
13345 ;; register CC value to there.
13347 (define_insn ""
13348 [(set (pc)
13349 (if_then_else (match_operator 1 "branch_comparison_operator"
13350 [(match_operand 2
13351 "cc_reg_operand" "y")
13352 (const_int 0)])
13353 (label_ref (match_operand 0 "" ""))
13354 (pc)))]
13355 ""
13356 "*
13357 {
13358 return output_cbranch (operands[1], \"%l0\", 0, insn);
13359 }"
13360 [(set_attr "type" "branch")])
13362 (define_insn ""
13363 [(set (pc)
13364 (if_then_else (match_operator 0 "branch_comparison_operator"
13365 [(match_operand 1
13366 "cc_reg_operand" "y")
13367 (const_int 0)])
13368 (return)
13369 (pc)))]
13370 "direct_return ()"
13371 "*
13372 {
13373 return output_cbranch (operands[0], NULL, 0, insn);
13374 }"
13375 [(set_attr "type" "branch")
13376 (set_attr "length" "4")])
13378 (define_insn ""
13379 [(set (pc)
13380 (if_then_else (match_operator 1 "branch_comparison_operator"
13381 [(match_operand 2
13382 "cc_reg_operand" "y")
13383 (const_int 0)])
13384 (pc)
13385 (label_ref (match_operand 0 "" ""))))]
13386 ""
13387 "*
13388 {
13389 return output_cbranch (operands[1], \"%l0\", 1, insn);
13390 }"
13391 [(set_attr "type" "branch")])
13393 (define_insn ""
13394 [(set (pc)
13395 (if_then_else (match_operator 0 "branch_comparison_operator"
13396 [(match_operand 1
13397 "cc_reg_operand" "y")
13398 (const_int 0)])
13399 (pc)
13400 (return)))]
13401 "direct_return ()"
13402 "*
13403 {
13404 return output_cbranch (operands[0], NULL, 1, insn);
13405 }"
13406 [(set_attr "type" "branch")
13407 (set_attr "length" "4")])
13409 ;; Logic on condition register values.
13411 ; This pattern matches things like
13412 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13413 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13414 ; (const_int 1)))
13415 ; which are generated by the branch logic.
13416 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13418 (define_insn "*cceq_ior_compare"
13419 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13420 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13421 [(match_operator:SI 2
13422 "branch_positive_comparison_operator"
13423 [(match_operand 3
13424 "cc_reg_operand" "y,y")
13425 (const_int 0)])
13426 (match_operator:SI 4
13427 "branch_positive_comparison_operator"
13428 [(match_operand 5
13429 "cc_reg_operand" "0,y")
13430 (const_int 0)])])
13431 (const_int 1)))]
13432 ""
13433 "cr%q1 %E0,%j2,%j4"
13434 [(set_attr "type" "cr_logical,delayed_cr")])
13436 ; Why is the constant -1 here, but 1 in the previous pattern?
13437 ; Because ~1 has all but the low bit set.
13438 (define_insn ""
13439 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13440 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13441 [(not:SI (match_operator:SI 2
13442 "branch_positive_comparison_operator"
13443 [(match_operand 3
13444 "cc_reg_operand" "y,y")
13445 (const_int 0)]))
13446 (match_operator:SI 4
13447 "branch_positive_comparison_operator"
13448 [(match_operand 5
13449 "cc_reg_operand" "0,y")
13450 (const_int 0)])])
13451 (const_int -1)))]
13452 ""
13453 "cr%q1 %E0,%j2,%j4"
13454 [(set_attr "type" "cr_logical,delayed_cr")])
13456 (define_insn "*cceq_rev_compare"
13457 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13458 (compare:CCEQ (match_operator:SI 1
13459 "branch_positive_comparison_operator"
13460 [(match_operand 2
13461 "cc_reg_operand" "0,y")
13462 (const_int 0)])
13463 (const_int 0)))]
13464 ""
13465 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13466 [(set_attr "type" "cr_logical,delayed_cr")])
13468 ;; If we are comparing the result of two comparisons, this can be done
13469 ;; using creqv or crxor.
13471 (define_insn_and_split ""
13472 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13473 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13474 [(match_operand 2 "cc_reg_operand" "y")
13475 (const_int 0)])
13476 (match_operator 3 "branch_comparison_operator"
13477 [(match_operand 4 "cc_reg_operand" "y")
13478 (const_int 0)])))]
13479 ""
13480 "#"
13481 ""
13482 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13483 (match_dup 5)))]
13484 "
13485 {
13486 int positive_1, positive_2;
13488 positive_1 = branch_positive_comparison_operator (operands[1],
13489 GET_MODE (operands[1]));
13490 positive_2 = branch_positive_comparison_operator (operands[3],
13491 GET_MODE (operands[3]));
13493 if (! positive_1)
13494 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13495 GET_CODE (operands[1])),
13496 SImode,
13497 operands[2], const0_rtx);
13498 else if (GET_MODE (operands[1]) != SImode)
13499 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13500 operands[2], const0_rtx);
13502 if (! positive_2)
13503 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13504 GET_CODE (operands[3])),
13505 SImode,
13506 operands[4], const0_rtx);
13507 else if (GET_MODE (operands[3]) != SImode)
13508 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13509 operands[4], const0_rtx);
13511 if (positive_1 == positive_2)
13512 {
13513 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13514 operands[5] = constm1_rtx;
13515 }
13516 else
13517 {
13518 operands[5] = const1_rtx;
13519 }
13520 }")
13522 ;; Unconditional branch and return.
13524 (define_insn "jump"
13525 [(set (pc)
13526 (label_ref (match_operand 0 "" "")))]
13527 ""
13528 "b %l0"
13529 [(set_attr "type" "branch")])
13531 (define_insn "return"
13532 [(return)]
13533 "direct_return ()"
13534 "{br|blr}"
13535 [(set_attr "type" "jmpreg")])
13537 (define_expand "indirect_jump"
13538 [(set (pc) (match_operand 0 "register_operand" ""))])
13540 (define_insn "*indirect_jump<mode>"
13541 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13542 ""
13543 "@
13544 bctr
13545 {br|blr}"
13546 [(set_attr "type" "jmpreg")])
13548 ;; Table jump for switch statements:
13549 (define_expand "tablejump"
13550 [(use (match_operand 0 "" ""))
13551 (use (label_ref (match_operand 1 "" "")))]
13552 ""
13553 "
13554 {
13555 if (TARGET_32BIT)
13556 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13557 else
13558 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13559 DONE;
13560 }")
13562 (define_expand "tablejumpsi"
13563 [(set (match_dup 3)
13564 (plus:SI (match_operand:SI 0 "" "")
13565 (match_dup 2)))
13566 (parallel [(set (pc) (match_dup 3))
13567 (use (label_ref (match_operand 1 "" "")))])]
13568 "TARGET_32BIT"
13569 "
13570 { operands[0] = force_reg (SImode, operands[0]);
13571 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13572 operands[3] = gen_reg_rtx (SImode);
13573 }")
13575 (define_expand "tablejumpdi"
13576 [(set (match_dup 4)
13577 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13578 (set (match_dup 3)
13579 (plus:DI (match_dup 4)
13580 (match_dup 2)))
13581 (parallel [(set (pc) (match_dup 3))
13582 (use (label_ref (match_operand 1 "" "")))])]
13583 "TARGET_64BIT"
13584 "
13585 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13586 operands[3] = gen_reg_rtx (DImode);
13587 operands[4] = gen_reg_rtx (DImode);
13588 }")
13590 (define_insn ""
13591 [(set (pc)
13592 (match_operand:P 0 "register_operand" "c,*l"))
13593 (use (label_ref (match_operand 1 "" "")))]
13594 ""
13595 "@
13596 bctr
13597 {br|blr}"
13598 [(set_attr "type" "jmpreg")])
13600 (define_insn "nop"
13601 [(const_int 0)]
13602 ""
13603 "{cror 0,0,0|nop}")
13604 \f
13605 ;; Define the subtract-one-and-jump insns, starting with the template
13606 ;; so loop.c knows what to generate.
13608 (define_expand "doloop_end"
13609 [(use (match_operand 0 "" "")) ; loop pseudo
13610 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13611 (use (match_operand 2 "" "")) ; max iterations
13612 (use (match_operand 3 "" "")) ; loop level
13613 (use (match_operand 4 "" ""))] ; label
13614 ""
13615 "
13616 {
13617 /* Only use this on innermost loops. */
13618 if (INTVAL (operands[3]) > 1)
13619 FAIL;
13620 if (TARGET_64BIT)
13621 {
13622 if (GET_MODE (operands[0]) != DImode)
13623 FAIL;
13624 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13625 }
13626 else
13627 {
13628 if (GET_MODE (operands[0]) != SImode)
13629 FAIL;
13630 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13631 }
13632 DONE;
13633 }")
13635 (define_expand "ctr<mode>"
13636 [(parallel [(set (pc)
13637 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13638 (const_int 1))
13639 (label_ref (match_operand 1 "" ""))
13640 (pc)))
13641 (set (match_dup 0)
13642 (plus:P (match_dup 0)
13643 (const_int -1)))
13644 (clobber (match_scratch:CC 2 ""))
13645 (clobber (match_scratch:P 3 ""))])]
13646 ""
13647 "")
13649 ;; We need to be able to do this for any operand, including MEM, or we
13650 ;; will cause reload to blow up since we don't allow output reloads on
13651 ;; JUMP_INSNs.
13652 ;; For the length attribute to be calculated correctly, the
13653 ;; label MUST be operand 0.
13655 (define_insn "*ctr<mode>_internal1"
13656 [(set (pc)
13657 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13658 (const_int 1))
13659 (label_ref (match_operand 0 "" ""))
13660 (pc)))
13661 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13662 (plus:P (match_dup 1)
13663 (const_int -1)))
13664 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13665 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13666 ""
13667 "*
13668 {
13669 if (which_alternative != 0)
13670 return \"#\";
13671 else if (get_attr_length (insn) == 4)
13672 return \"{bdn|bdnz} %l0\";
13673 else
13674 return \"bdz $+8\;b %l0\";
13675 }"
13676 [(set_attr "type" "branch")
13677 (set_attr "length" "*,12,16,16")])
13679 (define_insn "*ctr<mode>_internal2"
13680 [(set (pc)
13681 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13682 (const_int 1))
13683 (pc)
13684 (label_ref (match_operand 0 "" ""))))
13685 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13686 (plus:P (match_dup 1)
13687 (const_int -1)))
13688 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13689 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13690 ""
13691 "*
13692 {
13693 if (which_alternative != 0)
13694 return \"#\";
13695 else if (get_attr_length (insn) == 4)
13696 return \"bdz %l0\";
13697 else
13698 return \"{bdn|bdnz} $+8\;b %l0\";
13699 }"
13700 [(set_attr "type" "branch")
13701 (set_attr "length" "*,12,16,16")])
13703 ;; Similar but use EQ
13705 (define_insn "*ctr<mode>_internal5"
13706 [(set (pc)
13707 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13708 (const_int 1))
13709 (label_ref (match_operand 0 "" ""))
13710 (pc)))
13711 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13712 (plus:P (match_dup 1)
13713 (const_int -1)))
13714 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13715 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13716 ""
13717 "*
13718 {
13719 if (which_alternative != 0)
13720 return \"#\";
13721 else if (get_attr_length (insn) == 4)
13722 return \"bdz %l0\";
13723 else
13724 return \"{bdn|bdnz} $+8\;b %l0\";
13725 }"
13726 [(set_attr "type" "branch")
13727 (set_attr "length" "*,12,16,16")])
13729 (define_insn "*ctr<mode>_internal6"
13730 [(set (pc)
13731 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13732 (const_int 1))
13733 (pc)
13734 (label_ref (match_operand 0 "" ""))))
13735 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13736 (plus:P (match_dup 1)
13737 (const_int -1)))
13738 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13739 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13740 ""
13741 "*
13742 {
13743 if (which_alternative != 0)
13744 return \"#\";
13745 else if (get_attr_length (insn) == 4)
13746 return \"{bdn|bdnz} %l0\";
13747 else
13748 return \"bdz $+8\;b %l0\";
13749 }"
13750 [(set_attr "type" "branch")
13751 (set_attr "length" "*,12,16,16")])
13753 ;; Now the splitters if we could not allocate the CTR register
13755 (define_split
13756 [(set (pc)
13757 (if_then_else (match_operator 2 "comparison_operator"
13758 [(match_operand:P 1 "gpc_reg_operand" "")
13759 (const_int 1)])
13760 (match_operand 5 "" "")
13761 (match_operand 6 "" "")))
13762 (set (match_operand:P 0 "gpc_reg_operand" "")
13763 (plus:P (match_dup 1) (const_int -1)))
13764 (clobber (match_scratch:CC 3 ""))
13765 (clobber (match_scratch:P 4 ""))]
13766 "reload_completed"
13767 [(parallel [(set (match_dup 3)
13768 (compare:CC (plus:P (match_dup 1)
13769 (const_int -1))
13770 (const_int 0)))
13771 (set (match_dup 0)
13772 (plus:P (match_dup 1)
13773 (const_int -1)))])
13774 (set (pc) (if_then_else (match_dup 7)
13775 (match_dup 5)
13776 (match_dup 6)))]
13777 "
13778 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13779 operands[3], const0_rtx); }")
13781 (define_split
13782 [(set (pc)
13783 (if_then_else (match_operator 2 "comparison_operator"
13784 [(match_operand:P 1 "gpc_reg_operand" "")
13785 (const_int 1)])
13786 (match_operand 5 "" "")
13787 (match_operand 6 "" "")))
13788 (set (match_operand:P 0 "nonimmediate_operand" "")
13789 (plus:P (match_dup 1) (const_int -1)))
13790 (clobber (match_scratch:CC 3 ""))
13791 (clobber (match_scratch:P 4 ""))]
13792 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13793 [(parallel [(set (match_dup 3)
13794 (compare:CC (plus:P (match_dup 1)
13795 (const_int -1))
13796 (const_int 0)))
13797 (set (match_dup 4)
13798 (plus:P (match_dup 1)
13799 (const_int -1)))])
13800 (set (match_dup 0)
13801 (match_dup 4))
13802 (set (pc) (if_then_else (match_dup 7)
13803 (match_dup 5)
13804 (match_dup 6)))]
13805 "
13806 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13807 operands[3], const0_rtx); }")
13808 \f
13809 (define_insn "trap"
13810 [(trap_if (const_int 1) (const_int 0))]
13811 ""
13812 "{t 31,0,0|trap}")
13814 (define_expand "conditional_trap"
13815 [(trap_if (match_operator 0 "trap_comparison_operator"
13816 [(match_dup 2) (match_dup 3)])
13817 (match_operand 1 "const_int_operand" ""))]
13818 ""
13819 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13820 operands[2] = rs6000_compare_op0;
13821 operands[3] = rs6000_compare_op1;")
13823 (define_insn ""
13824 [(trap_if (match_operator 0 "trap_comparison_operator"
13825 [(match_operand:GPR 1 "register_operand" "r")
13826 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13827 (const_int 0))]
13828 ""
13829 "{t|t<wd>}%V0%I2 %1,%2")
13830 \f
13831 ;; Insns related to generating the function prologue and epilogue.
13833 (define_expand "prologue"
13834 [(use (const_int 0))]
13835 "TARGET_SCHED_PROLOG"
13836 "
13837 {
13838 rs6000_emit_prologue ();
13839 DONE;
13840 }")
13842 (define_insn "*movesi_from_cr_one"
13843 [(match_parallel 0 "mfcr_operation"
13844 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13845 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13846 (match_operand 3 "immediate_operand" "n")]
13847 UNSPEC_MOVESI_FROM_CR))])]
13848 "TARGET_MFCRF"
13849 "*
13850 {
13851 int mask = 0;
13852 int i;
13853 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13854 {
13855 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13856 operands[4] = GEN_INT (mask);
13857 output_asm_insn (\"mfcr %1,%4\", operands);
13858 }
13859 return \"\";
13860 }"
13861 [(set_attr "type" "mfcrf")])
13863 (define_insn "movesi_from_cr"
13864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13865 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13866 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13867 UNSPEC_MOVESI_FROM_CR))]
13868 ""
13869 "mfcr %0"
13870 [(set_attr "type" "mfcr")])
13872 (define_insn "*stmw"
13873 [(match_parallel 0 "stmw_operation"
13874 [(set (match_operand:SI 1 "memory_operand" "=m")
13875 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13876 "TARGET_MULTIPLE"
13877 "{stm|stmw} %2,%1")
13879 (define_insn "*save_fpregs_<mode>"
13880 [(match_parallel 0 "any_parallel_operand"
13881 [(clobber (match_operand:P 1 "register_operand" "=l"))
13882 (use (match_operand:P 2 "call_operand" "s"))
13883 (set (match_operand:DF 3 "memory_operand" "=m")
13884 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13885 ""
13886 "bl %z2"
13887 [(set_attr "type" "branch")
13888 (set_attr "length" "4")])
13890 ; These are to explain that changes to the stack pointer should
13891 ; not be moved over stores to stack memory.
13892 (define_insn "stack_tie"
13893 [(set (match_operand:BLK 0 "memory_operand" "+m")
13894 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13895 ""
13896 ""
13897 [(set_attr "length" "0")])
13900 (define_expand "epilogue"
13901 [(use (const_int 0))]
13902 "TARGET_SCHED_PROLOG"
13903 "
13904 {
13905 rs6000_emit_epilogue (FALSE);
13906 DONE;
13907 }")
13909 ; On some processors, doing the mtcrf one CC register at a time is
13910 ; faster (like on the 604e). On others, doing them all at once is
13911 ; faster; for instance, on the 601 and 750.
13913 (define_expand "movsi_to_cr_one"
13914 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13915 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13916 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13917 ""
13918 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13920 (define_insn "*movsi_to_cr"
13921 [(match_parallel 0 "mtcrf_operation"
13922 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13923 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13924 (match_operand 3 "immediate_operand" "n")]
13925 UNSPEC_MOVESI_TO_CR))])]
13926 ""
13927 "*
13928 {
13929 int mask = 0;
13930 int i;
13931 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13932 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13933 operands[4] = GEN_INT (mask);
13934 return \"mtcrf %4,%2\";
13935 }"
13936 [(set_attr "type" "mtcr")])
13938 (define_insn "*mtcrfsi"
13939 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13940 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13941 (match_operand 2 "immediate_operand" "n")]
13942 UNSPEC_MOVESI_TO_CR))]
13943 "GET_CODE (operands[0]) == REG
13944 && CR_REGNO_P (REGNO (operands[0]))
13945 && GET_CODE (operands[2]) == CONST_INT
13946 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13947 "mtcrf %R0,%1"
13948 [(set_attr "type" "mtcr")])
13950 ; The load-multiple instructions have similar properties.
13951 ; Note that "load_multiple" is a name known to the machine-independent
13952 ; code that actually corresponds to the powerpc load-string.
13954 (define_insn "*lmw"
13955 [(match_parallel 0 "lmw_operation"
13956 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13957 (match_operand:SI 2 "memory_operand" "m"))])]
13958 "TARGET_MULTIPLE"
13959 "{lm|lmw} %1,%2")
13961 (define_insn "*return_internal_<mode>"
13962 [(return)
13963 (use (match_operand:P 0 "register_operand" "lc"))]
13964 ""
13965 "b%T0"
13966 [(set_attr "type" "jmpreg")])
13968 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13969 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13971 (define_insn "*return_and_restore_fpregs_<mode>"
13972 [(match_parallel 0 "any_parallel_operand"
13973 [(return)
13974 (use (match_operand:P 1 "register_operand" "l"))
13975 (use (match_operand:P 2 "call_operand" "s"))
13976 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13977 (match_operand:DF 4 "memory_operand" "m"))])]
13978 ""
13979 "b %z2")
13981 ; This is used in compiling the unwind routines.
13982 (define_expand "eh_return"
13983 [(use (match_operand 0 "general_operand" ""))]
13984 ""
13985 "
13986 {
13987 if (TARGET_32BIT)
13988 emit_insn (gen_eh_set_lr_si (operands[0]));
13989 else
13990 emit_insn (gen_eh_set_lr_di (operands[0]));
13991 DONE;
13992 }")
13994 ; We can't expand this before we know where the link register is stored.
13995 (define_insn "eh_set_lr_<mode>"
13996 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13997 UNSPECV_EH_RR)
13998 (clobber (match_scratch:P 1 "=&b"))]
13999 ""
14000 "#")
14002 (define_split
14003 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14004 (clobber (match_scratch 1 ""))]
14005 "reload_completed"
14006 [(const_int 0)]
14007 "
14008 {
14009 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14010 DONE;
14011 }")
14013 (define_insn "prefetch"
14014 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14015 (match_operand:SI 1 "const_int_operand" "n")
14016 (match_operand:SI 2 "const_int_operand" "n"))]
14017 "TARGET_POWERPC"
14018 "*
14019 {
14020 if (GET_CODE (operands[0]) == REG)
14021 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14022 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14023 }"
14024 [(set_attr "type" "load")])
14025 \f
14027 (include "sync.md")
14028 (include "altivec.md")
14029 (include "spe.md")