libitm/config/x86/target.h

   1 /* Copyright (C) 2008-2017 Free Software Foundation, Inc.
   2    Contributed by Richard Henderson <rth@redhat.com>.
   3
   4    This file is part of the GNU Transactional Memory Library (libitm).
   5
   6    Libitm is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
  12    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  13    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14    more details.
  15
  16    Under Section 7 of GPL version 3, you are granted additional
  17    permissions described in the GCC Runtime Library Exception, version
  18    3.1, as published by the Free Software Foundation.
  19
  20    You should have received a copy of the GNU General Public License and
  21    a copy of the GCC Runtime Library Exception along with this program;
  22    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  23    <http://www.gnu.org/licenses/>.  */
  24
  25 // We'll be using some of the cpu builtins, and their associated types.
  26 #include <x86intrin.h>
  27 #include <cpuid.h>
  28
  29 namespace GTM HIDDEN {
  30
  31 /* ??? This doesn't work for Win64.  */
  32 typedef struct gtm_jmpbuf
  33 {
  34   void *cfa;
  35 #ifdef __x86_64__
  36   unsigned long long rbx;
  37   unsigned long long rbp;
  38   unsigned long long r12;
  39   unsigned long long r13;
  40   unsigned long long r14;
  41   unsigned long long r15;
  42   unsigned long long rip;
  43 #else
  44   unsigned long ebx;
  45   unsigned long esi;
  46   unsigned long edi;
  47   unsigned long ebp;
  48   unsigned long eip;
  49 #endif
  50 } gtm_jmpbuf;
  51
  52 /* x86 doesn't require strict alignment for the basic types.  */
  53 #define STRICT_ALIGNMENT 0
  54
  55 /* The size of one line in hardware caches (in bytes). */
  56 #define HW_CACHELINE_SIZE 64
  57
  58
  59 static inline void
  60 cpu_relax (void)
  61 {
  62   __builtin_ia32_pause ();
  63 }
  64
  65 // Use Intel RTM if supported by the assembler.
  66 // See gtm_thread::begin_transaction for how these functions are used.
  67 #ifdef HAVE_AS_RTM
  68 #define USE_HTM_FASTPATH
  69 #ifdef __x86_64__
  70 // Use the custom fastpath in ITM_beginTransaction.
  71 #define HTM_CUSTOM_FASTPATH
  72 #endif
  73
  74 static inline bool
  75 htm_available ()
  76 {
  77   const unsigned cpuid_rtm = bit_RTM;
  78   unsigned vendor;
  79
  80   if (__get_cpuid_max (0, &vendor) >= 7)
  81     {
  82       unsigned a, b, c, d;
  83       unsigned family;
  84
  85       __cpuid (1, a, b, c, d);
  86       family = (a >> 8) & 0x0f;
  87       /* TSX is broken on some processors.  TSX can be disabled by microcode,
  88          but we cannot reliably detect whether the microcode has been
  89          updated.  Therefore, do not report availability of TSX on these
  90          processors.  We use the same approach here as in glibc (see
  91          https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html).  */
  92       if (vendor == signature_INTEL_ebx && family == 0x06)
  93         {
  94           unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0);
  95           unsigned stepping = a & 0x0f;
  96           if (model == 0x3c
  97               /* Xeon E7 v3 has correct TSX if stepping >= 4.  */
  98               || (model == 0x3f && stepping < 4)
  99               || model == 0x45
 100               || model == 0x46)
 101             return false;
 102         }
 103
 104       __cpuid_count (7, 0, a, b, c, d);
 105       if (b & cpuid_rtm)
 106         return true;
 107     }
 108   return false;
 109 }
 110
 111 static inline uint32_t
 112 htm_init ()
 113 {
 114   // Maximum number of times we try to execute a transaction as a HW
 115   // transaction.
 116   // ??? Why 2?  Any offline or runtime tuning necessary?
 117   return htm_available () ? 2 : 0;
 118 }
 119
 120 static inline uint32_t
 121 htm_begin ()
 122 {
 123   return _xbegin();
 124 }
 125
 126 static inline bool
 127 htm_begin_success (uint32_t begin_ret)
 128 {
 129   return begin_ret == _XBEGIN_STARTED;
 130 }
 131
 132 static inline void
 133 htm_commit ()
 134 {
 135   _xend();
 136 }
 137
 138 static inline void
 139 htm_abort ()
 140 {
 141   // ??? According to a yet unpublished ABI rule, 0xff is reserved and
 142   // supposed to signal a busy lock.  Source: andi.kleen@intel.com
 143   _xabort(0xff);
 144 }
 145
 146 static inline bool
 147 htm_abort_should_retry (uint32_t begin_ret)
 148 {
 149   return begin_ret & _XABORT_RETRY;
 150 }
 151
 152 /* Returns true iff a hardware transaction is currently being executed.  */
 153 static inline bool
 154 htm_transaction_active ()
 155 {
 156   return _xtest() != 0;
 157 }
 158 #endif
 159
 160
 161 } // namespace GTM