gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 /* combine_instructions may try to replace the right hand side of the
 127    second instruction with the value of an associated REG_EQUAL note
 128    before throwing it at try_combine.  That is problematic when there
 129    is a REG_DEAD note for a register used in the old right hand side
 130    and can cause distribute_notes to do wrong things.  This is the
 131    second instruction if it has been so modified, null otherwise.  */
 132
 133 static rtx i2mod;
 134
 135 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 136
 137 static rtx i2mod_old_rhs;
 138
 139 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 140
 141 static rtx i2mod_new_rhs;
 142 \f
 143 /* Vector mapping INSN_UIDs to cuids.
 144    The cuids are like uids but increase monotonically always.
 145    Combine always uses cuids so that it can compare them.
 146    But actually renumbering the uids, which we used to do,
 147    proves to be a bad idea because it makes it hard to compare
 148    the dumps produced by earlier passes with those from later passes.  */
 149
 150 static int *uid_cuid;
 151 static int max_uid_cuid;
 152
 153 /* Get the cuid of an insn.  */
 154
 155 #define INSN_CUID(INSN) \
 156 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 157
 158 /* Maximum register number, which is the size of the tables below.  */
 159
 160 static unsigned int combine_max_regno;
 161
 162 struct reg_stat {
 163   /* Record last point of death of (hard or pseudo) register n.  */
 164   rtx                           last_death;
 165
 166   /* Record last point of modification of (hard or pseudo) register n.  */
 167   rtx                           last_set;
 168
 169   /* The next group of fields allows the recording of the last value assigned
 170      to (hard or pseudo) register n.  We use this information to see if an
 171      operation being processed is redundant given a prior operation performed
 172      on the register.  For example, an `and' with a constant is redundant if
 173      all the zero bits are already known to be turned off.
 174
 175      We use an approach similar to that used by cse, but change it in the
 176      following ways:
 177
 178      (1) We do not want to reinitialize at each label.
 179      (2) It is useful, but not critical, to know the actual value assigned
 180          to a register.  Often just its form is helpful.
 181
 182      Therefore, we maintain the following fields:
 183
 184      last_set_value             the last value assigned
 185      last_set_label             records the value of label_tick when the
 186                                 register was assigned
 187      last_set_table_tick        records the value of label_tick when a
 188                                 value using the register is assigned
 189      last_set_invalid           set to nonzero when it is not valid
 190                                 to use the value of this register in some
 191                                 register's value
 192
 193      To understand the usage of these tables, it is important to understand
 194      the distinction between the value in last_set_value being valid and
 195      the register being validly contained in some other expression in the
 196      table.
 197
 198      (The next two parameters are out of date).
 199
 200      reg_stat[i].last_set_value is valid if it is nonzero, and either
 201      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 202
 203      Register I may validly appear in any expression returned for the value
 204      of another register if reg_n_sets[i] is 1.  It may also appear in the
 205      value for register J if reg_stat[j].last_set_invalid is zero, or
 206      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 207
 208      If an expression is found in the table containing a register which may
 209      not validly appear in an expression, the register is replaced by
 210      something that won't match, (clobber (const_int 0)).  */
 211
 212   /* Record last value assigned to (hard or pseudo) register n.  */
 213
 214   rtx                           last_set_value;
 215
 216   /* Record the value of label_tick when an expression involving register n
 217      is placed in last_set_value.  */
 218
 219   int                           last_set_table_tick;
 220
 221   /* Record the value of label_tick when the value for register n is placed in
 222      last_set_value.  */
 223
 224   int                           last_set_label;
 225
 226   /* These fields are maintained in parallel with last_set_value and are
 227      used to store the mode in which the register was last set, the bits
 228      that were known to be zero when it was last set, and the number of
 229      sign bits copies it was known to have when it was last set.  */
 230
 231   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 232   char                          last_set_sign_bit_copies;
 233   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 234
 235   /* Set nonzero if references to register n in expressions should not be
 236      used.  last_set_invalid is set nonzero when this register is being
 237      assigned to and last_set_table_tick == label_tick.  */
 238
 239   char                          last_set_invalid;
 240
 241   /* Some registers that are set more than once and used in more than one
 242      basic block are nevertheless always set in similar ways.  For example,
 243      a QImode register may be loaded from memory in two places on a machine
 244      where byte loads zero extend.
 245
 246      We record in the following fields if a register has some leading bits
 247      that are always equal to the sign bit, and what we know about the
 248      nonzero bits of a register, specifically which bits are known to be
 249      zero.
 250
 251      If an entry is zero, it means that we don't know anything special.  */
 252
 253   unsigned char                 sign_bit_copies;
 254
 255   unsigned HOST_WIDE_INT        nonzero_bits;
 256
 257   /* Record the value of the label_tick when the last truncation
 258      happened.  The field truncated_to_mode is only valid if
 259      truncation_label == label_tick.  */
 260
 261   int                           truncation_label;
 262
 263   /* Record the last truncation seen for this register.  If truncation
 264      is not a nop to this mode we might be able to save an explicit
 265      truncation if we know that value already contains a truncated
 266      value.  */
 267
 268   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 269 };
 270
 271 static struct reg_stat *reg_stat;
 272
 273 /* Record the cuid of the last insn that invalidated memory
 274    (anything that writes memory, and subroutine calls, but not pushes).  */
 275
 276 static int mem_last_set;
 277
 278 /* Record the cuid of the last CALL_INSN
 279    so we can tell whether a potential combination crosses any calls.  */
 280
 281 static int last_call_cuid;
 282
 283 /* When `subst' is called, this is the insn that is being modified
 284    (by combining in a previous insn).  The PATTERN of this insn
 285    is still the old pattern partially modified and it should not be
 286    looked at, but this may be used to examine the successors of the insn
 287    to judge whether a simplification is valid.  */
 288
 289 static rtx subst_insn;
 290
 291 /* This is the lowest CUID that `subst' is currently dealing with.
 292    get_last_value will not return a value if the register was set at or
 293    after this CUID.  If not for this mechanism, we could get confused if
 294    I2 or I1 in try_combine were an insn that used the old value of a register
 295    to obtain a new value.  In that case, we might erroneously get the
 296    new value of the register when we wanted the old one.  */
 297
 298 static int subst_low_cuid;
 299
 300 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 301    must consider all these registers to be always live.  */
 302
 303 static HARD_REG_SET newpat_used_regs;
 304
 305 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 306    insn is the earlier than I2 or I3, combine should rescan starting at
 307    that location.  */
 308
 309 static rtx added_links_insn;
 310
 311 /* Basic block in which we are performing combines.  */
 312 static basic_block this_basic_block;
 313
 314 /* A bitmap indicating which blocks had registers go dead at entry.
 315    After combine, we'll need to re-do global life analysis with
 316    those blocks as starting points.  */
 317 static sbitmap refresh_blocks;
 318 \f
 319 /* The following array records the insn_rtx_cost for every insn
 320    in the instruction stream.  */
 321
 322 static int *uid_insn_cost;
 323
 324 /* Length of the currently allocated uid_insn_cost array.  */
 325
 326 static int last_insn_cost;
 327
 328 /* Incremented for each label.  */
 329
 330 static int label_tick;
 331
 332 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 333    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 334
 335 static enum machine_mode nonzero_bits_mode;
 336
 337 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 338    be safely used.  It is zero while computing them and after combine has
 339    completed.  This former test prevents propagating values based on
 340    previously set values, which can be incorrect if a variable is modified
 341    in a loop.  */
 342
 343 static int nonzero_sign_valid;
 344
 345 \f
 346 /* Record one modification to rtl structure
 347    to be undone by storing old_contents into *where.  */
 348
 349 struct undo
 350 {
 351   struct undo *next;
 352   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 353   union { rtx r; int i; enum machine_mode m; } old_contents;
 354   union { rtx *r; int *i; } where;
 355 };
 356
 357 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 358    num_undo says how many are currently recorded.
 359
 360    other_insn is nonzero if we have modified some other insn in the process
 361    of working on subst_insn.  It must be verified too.  */
 362
 363 struct undobuf
 364 {
 365   struct undo *undos;
 366   struct undo *frees;
 367   rtx other_insn;
 368 };
 369
 370 static struct undobuf undobuf;
 371
 372 /* Number of times the pseudo being substituted for
 373    was found and replaced.  */
 374
 375 static int n_occurrences;
 376
 377 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 378                                          enum machine_mode,
 379                                          unsigned HOST_WIDE_INT,
 380                                          unsigned HOST_WIDE_INT *);
 381 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 382                                                 enum machine_mode,
 383                                                 unsigned int, unsigned int *);
 384 static void do_SUBST (rtx *, rtx);
 385 static void do_SUBST_INT (int *, int);
 386 static void init_reg_last (void);
 387 static void setup_incoming_promotions (void);
 388 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 389 static int cant_combine_insn_p (rtx);
 390 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 391 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 392 static int contains_muldiv (rtx);
 393 static rtx try_combine (rtx, rtx, rtx, int *);
 394 static void undo_all (void);
 395 static void undo_commit (void);
 396 static rtx *find_split_point (rtx *, rtx);
 397 static rtx subst (rtx, rtx, rtx, int, int);
 398 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 399 static rtx simplify_if_then_else (rtx);
 400 static rtx simplify_set (rtx);
 401 static rtx simplify_logical (rtx);
 402 static rtx expand_compound_operation (rtx);
 403 static rtx expand_field_assignment (rtx);
 404 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 405                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 406 static rtx extract_left_shift (rtx, int);
 407 static rtx make_compound_operation (rtx, enum rtx_code);
 408 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 409                               unsigned HOST_WIDE_INT *);
 410 static rtx canon_reg_for_combine (rtx, rtx);
 411 static rtx force_to_mode (rtx, enum machine_mode,
 412                           unsigned HOST_WIDE_INT, int);
 413 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 414 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 415 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 416 static rtx make_field_assignment (rtx);
 417 static rtx apply_distributive_law (rtx);
 418 static rtx distribute_and_simplify_rtx (rtx, int);
 419 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 420                                      unsigned HOST_WIDE_INT);
 421 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 422                                    unsigned HOST_WIDE_INT);
 423 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 424                             HOST_WIDE_INT, enum machine_mode, int *);
 425 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 426 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 427                                  int);
 428 static int recog_for_combine (rtx *, rtx, rtx *);
 429 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 430 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 431 static void update_table_tick (rtx);
 432 static void record_value_for_reg (rtx, rtx, rtx);
 433 static void check_conversions (rtx, rtx);
 434 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 435 static void record_dead_and_set_regs (rtx);
 436 static int get_last_value_validate (rtx *, rtx, int, int);
 437 static rtx get_last_value (rtx);
 438 static int use_crosses_set_p (rtx, int);
 439 static void reg_dead_at_p_1 (rtx, rtx, void *);
 440 static int reg_dead_at_p (rtx, rtx);
 441 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 442 static int reg_bitfield_target_p (rtx, rtx);
 443 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 444 static void distribute_links (rtx);
 445 static void mark_used_regs_combine (rtx);
 446 static int insn_cuid (rtx);
 447 static void record_promoted_value (rtx, rtx);
 448 static int unmentioned_reg_p_1 (rtx *, void *);
 449 static bool unmentioned_reg_p (rtx, rtx);
 450 static void record_truncated_value (rtx);
 451 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 452 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 453 \f
 454
 455 /* It is not safe to use ordinary gen_lowpart in combine.
 456    See comments in gen_lowpart_for_combine.  */
 457 #undef RTL_HOOKS_GEN_LOWPART
 458 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 459
 460 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 461 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 462 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 463
 464 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 465 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 466
 467 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 468 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 469
 470 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 471 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 472
 473 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 474
 475 \f
 476 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 477    insn.  The substitution can be undone by undo_all.  If INTO is already
 478    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 479    also call SUBST, we have to compute it before we put anything into
 480    the undo table.  */
 481
 482 static void
 483 do_SUBST (rtx *into, rtx newval)
 484 {
 485   struct undo *buf;
 486   rtx oldval = *into;
 487
 488   if (oldval == newval)
 489     return;
 490
 491   /* We'd like to catch as many invalid transformations here as
 492      possible.  Unfortunately, there are way too many mode changes
 493      that are perfectly valid, so we'd waste too much effort for
 494      little gain doing the checks here.  Focus on catching invalid
 495      transformations involving integer constants.  */
 496   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 497       && GET_CODE (newval) == CONST_INT)
 498     {
 499       /* Sanity check that we're replacing oldval with a CONST_INT
 500          that is a valid sign-extension for the original mode.  */
 501       gcc_assert (INTVAL (newval)
 502                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 503
 504       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 505          CONST_INT is not valid, because after the replacement, the
 506          original mode would be gone.  Unfortunately, we can't tell
 507          when do_SUBST is called to replace the operand thereof, so we
 508          perform this test on oldval instead, checking whether an
 509          invalid replacement took place before we got here.  */
 510       gcc_assert (!(GET_CODE (oldval) == SUBREG
 511                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 512       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 513                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 514     }
 515
 516   if (undobuf.frees)
 517     buf = undobuf.frees, undobuf.frees = buf->next;
 518   else
 519     buf = XNEW (struct undo);
 520
 521   buf->kind = UNDO_RTX;
 522   buf->where.r = into;
 523   buf->old_contents.r = oldval;
 524   *into = newval;
 525
 526   buf->next = undobuf.undos, undobuf.undos = buf;
 527 }
 528
 529 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 530
 531 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 532    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 533    not safe.  */
 534
 535 static void
 536 do_SUBST_INT (int *into, int newval)
 537 {
 538   struct undo *buf;
 539   int oldval = *into;
 540
 541   if (oldval == newval)
 542     return;
 543
 544   if (undobuf.frees)
 545     buf = undobuf.frees, undobuf.frees = buf->next;
 546   else
 547     buf = XNEW (struct undo);
 548
 549   buf->kind = UNDO_INT;
 550   buf->where.i = into;
 551   buf->old_contents.i = oldval;
 552   *into = newval;
 553
 554   buf->next = undobuf.undos, undobuf.undos = buf;
 555 }
 556
 557 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 558
 559 /* Similar to SUBST, but just substitute the mode.  This is used when
 560    changing the mode of a pseudo-register, so that any other
 561    references to the entry in the regno_reg_rtx array will change as
 562    well.  */
 563
 564 static void
 565 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 566 {
 567   struct undo *buf;
 568   enum machine_mode oldval = GET_MODE (*into);
 569
 570   if (oldval == newval)
 571     return;
 572
 573   if (undobuf.frees)
 574     buf = undobuf.frees, undobuf.frees = buf->next;
 575   else
 576     buf = XNEW (struct undo);
 577
 578   buf->kind = UNDO_MODE;
 579   buf->where.r = into;
 580   buf->old_contents.m = oldval;
 581   PUT_MODE (*into, newval);
 582
 583   buf->next = undobuf.undos, undobuf.undos = buf;
 584 }
 585
 586 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 587 \f
 588 /* Subroutine of try_combine.  Determine whether the combine replacement
 589    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 590    that the original instruction sequence I1, I2 and I3.  Note that I1
 591    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 592    costs of all instructions can be estimated, and the replacements are
 593    more expensive than the original sequence.  */
 594
 595 static bool
 596 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 597 {
 598   int i1_cost, i2_cost, i3_cost;
 599   int new_i2_cost, new_i3_cost;
 600   int old_cost, new_cost;
 601
 602   /* Lookup the original insn_rtx_costs.  */
 603   i2_cost = INSN_UID (i2) <= last_insn_cost
 604             ? uid_insn_cost[INSN_UID (i2)] : 0;
 605   i3_cost = INSN_UID (i3) <= last_insn_cost
 606             ? uid_insn_cost[INSN_UID (i3)] : 0;
 607
 608   if (i1)
 609     {
 610       i1_cost = INSN_UID (i1) <= last_insn_cost
 611                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 612       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 613                  ? i1_cost + i2_cost + i3_cost : 0;
 614     }
 615   else
 616     {
 617       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 618       i1_cost = 0;
 619     }
 620
 621   /* Calculate the replacement insn_rtx_costs.  */
 622   new_i3_cost = insn_rtx_cost (newpat);
 623   if (newi2pat)
 624     {
 625       new_i2_cost = insn_rtx_cost (newi2pat);
 626       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 627                  ? new_i2_cost + new_i3_cost : 0;
 628     }
 629   else
 630     {
 631       new_cost = new_i3_cost;
 632       new_i2_cost = 0;
 633     }
 634
 635   if (undobuf.other_insn)
 636     {
 637       int old_other_cost, new_other_cost;
 638
 639       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 640                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 641       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 642       if (old_other_cost > 0 && new_other_cost > 0)
 643         {
 644           old_cost += old_other_cost;
 645           new_cost += new_other_cost;
 646         }
 647       else
 648         old_cost = 0;
 649     }
 650
 651   /* Disallow this recombination if both new_cost and old_cost are
 652      greater than zero, and new_cost is greater than old cost.  */
 653   if (old_cost > 0
 654       && new_cost > old_cost)
 655     {
 656       if (dump_file)
 657         {
 658           if (i1)
 659             {
 660               fprintf (dump_file,
 661                        "rejecting combination of insns %d, %d and %d\n",
 662                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 663               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 664                        i1_cost, i2_cost, i3_cost, old_cost);
 665             }
 666           else
 667             {
 668               fprintf (dump_file,
 669                        "rejecting combination of insns %d and %d\n",
 670                        INSN_UID (i2), INSN_UID (i3));
 671               fprintf (dump_file, "original costs %d + %d = %d\n",
 672                        i2_cost, i3_cost, old_cost);
 673             }
 674
 675           if (newi2pat)
 676             {
 677               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 678                        new_i2_cost, new_i3_cost, new_cost);
 679             }
 680           else
 681             fprintf (dump_file, "replacement cost %d\n", new_cost);
 682         }
 683
 684       return false;
 685     }
 686
 687   /* Update the uid_insn_cost array with the replacement costs.  */
 688   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 689   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 690   if (i1)
 691     uid_insn_cost[INSN_UID (i1)] = 0;
 692
 693   return true;
 694 }
 695 \f
 696 /* Main entry point for combiner.  F is the first insn of the function.
 697    NREGS is the first unused pseudo-reg number.
 698
 699    Return nonzero if the combiner has turned an indirect jump
 700    instruction into a direct jump.  */
 701 static int
 702 combine_instructions (rtx f, unsigned int nregs)
 703 {
 704   rtx insn, next;
 705 #ifdef HAVE_cc0
 706   rtx prev;
 707 #endif
 708   int i;
 709   unsigned int j = 0;
 710   rtx links, nextlinks;
 711   sbitmap_iterator sbi;
 712
 713   int new_direct_jump_p = 0;
 714
 715   combine_attempts = 0;
 716   combine_merges = 0;
 717   combine_extras = 0;
 718   combine_successes = 0;
 719
 720   combine_max_regno = nregs;
 721
 722   rtl_hooks = combine_rtl_hooks;
 723
 724   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 725
 726   init_recog_no_volatile ();
 727
 728   /* Compute maximum uid value so uid_cuid can be allocated.  */
 729
 730   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 731     if (INSN_UID (insn) > i)
 732       i = INSN_UID (insn);
 733
 734   uid_cuid = XNEWVEC (int, i + 1);
 735   max_uid_cuid = i;
 736
 737   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 738
 739   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 740      problems when, for example, we have j <<= 1 in a loop.  */
 741
 742   nonzero_sign_valid = 0;
 743
 744   /* Compute the mapping from uids to cuids.
 745      Cuids are numbers assigned to insns, like uids,
 746      except that cuids increase monotonically through the code.
 747
 748      Scan all SETs and see if we can deduce anything about what
 749      bits are known to be zero for some registers and how many copies
 750      of the sign bit are known to exist for those registers.
 751
 752      Also set any known values so that we can use it while searching
 753      for what bits are known to be set.  */
 754
 755   label_tick = 1;
 756
 757   setup_incoming_promotions ();
 758
 759   refresh_blocks = sbitmap_alloc (last_basic_block);
 760   sbitmap_zero (refresh_blocks);
 761
 762   /* Allocate array of current insn_rtx_costs.  */
 763   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 764   last_insn_cost = max_uid_cuid;
 765
 766   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 767     {
 768       uid_cuid[INSN_UID (insn)] = ++i;
 769       subst_low_cuid = i;
 770       subst_insn = insn;
 771
 772       if (INSN_P (insn))
 773         {
 774           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 775                        NULL);
 776           record_dead_and_set_regs (insn);
 777
 778 #ifdef AUTO_INC_DEC
 779           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 780             if (REG_NOTE_KIND (links) == REG_INC)
 781               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 782                                                 NULL);
 783 #endif
 784
 785           /* Record the current insn_rtx_cost of this instruction.  */
 786           if (NONJUMP_INSN_P (insn))
 787             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 788           if (dump_file)
 789             fprintf(dump_file, "insn_cost %d: %d\n",
 790                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 791         }
 792
 793       if (LABEL_P (insn))
 794         label_tick++;
 795     }
 796
 797   nonzero_sign_valid = 1;
 798
 799   /* Now scan all the insns in forward order.  */
 800
 801   label_tick = 1;
 802   last_call_cuid = 0;
 803   mem_last_set = 0;
 804   init_reg_last ();
 805   setup_incoming_promotions ();
 806
 807   FOR_EACH_BB (this_basic_block)
 808     {
 809       for (insn = BB_HEAD (this_basic_block);
 810            insn != NEXT_INSN (BB_END (this_basic_block));
 811            insn = next ? next : NEXT_INSN (insn))
 812         {
 813           next = 0;
 814
 815           if (LABEL_P (insn))
 816             label_tick++;
 817
 818           else if (INSN_P (insn))
 819             {
 820               /* See if we know about function return values before this
 821                  insn based upon SUBREG flags.  */
 822               check_conversions (insn, PATTERN (insn));
 823
 824               /* Try this insn with each insn it links back to.  */
 825
 826               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 827                 if ((next = try_combine (insn, XEXP (links, 0),
 828                                          NULL_RTX, &new_direct_jump_p)) != 0)
 829                   goto retry;
 830
 831               /* Try each sequence of three linked insns ending with this one.  */
 832
 833               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 834                 {
 835                   rtx link = XEXP (links, 0);
 836
 837                   /* If the linked insn has been replaced by a note, then there
 838                      is no point in pursuing this chain any further.  */
 839                   if (NOTE_P (link))
 840                     continue;
 841
 842                   for (nextlinks = LOG_LINKS (link);
 843                        nextlinks;
 844                        nextlinks = XEXP (nextlinks, 1))
 845                     if ((next = try_combine (insn, link,
 846                                              XEXP (nextlinks, 0),
 847                                              &new_direct_jump_p)) != 0)
 848                       goto retry;
 849                 }
 850
 851 #ifdef HAVE_cc0
 852               /* Try to combine a jump insn that uses CC0
 853                  with a preceding insn that sets CC0, and maybe with its
 854                  logical predecessor as well.
 855                  This is how we make decrement-and-branch insns.
 856                  We need this special code because data flow connections
 857                  via CC0 do not get entered in LOG_LINKS.  */
 858
 859               if (JUMP_P (insn)
 860                   && (prev = prev_nonnote_insn (insn)) != 0
 861                   && NONJUMP_INSN_P (prev)
 862                   && sets_cc0_p (PATTERN (prev)))
 863                 {
 864                   if ((next = try_combine (insn, prev,
 865                                            NULL_RTX, &new_direct_jump_p)) != 0)
 866                     goto retry;
 867
 868                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 869                        nextlinks = XEXP (nextlinks, 1))
 870                     if ((next = try_combine (insn, prev,
 871                                              XEXP (nextlinks, 0),
 872                                              &new_direct_jump_p)) != 0)
 873                       goto retry;
 874                 }
 875
 876               /* Do the same for an insn that explicitly references CC0.  */
 877               if (NONJUMP_INSN_P (insn)
 878                   && (prev = prev_nonnote_insn (insn)) != 0
 879                   && NONJUMP_INSN_P (prev)
 880                   && sets_cc0_p (PATTERN (prev))
 881                   && GET_CODE (PATTERN (insn)) == SET
 882                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 883                 {
 884                   if ((next = try_combine (insn, prev,
 885                                            NULL_RTX, &new_direct_jump_p)) != 0)
 886                     goto retry;
 887
 888                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 889                        nextlinks = XEXP (nextlinks, 1))
 890                     if ((next = try_combine (insn, prev,
 891                                              XEXP (nextlinks, 0),
 892                                              &new_direct_jump_p)) != 0)
 893                       goto retry;
 894                 }
 895
 896               /* Finally, see if any of the insns that this insn links to
 897                  explicitly references CC0.  If so, try this insn, that insn,
 898                  and its predecessor if it sets CC0.  */
 899               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 900                 if (NONJUMP_INSN_P (XEXP (links, 0))
 901                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 902                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 903                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 904                     && NONJUMP_INSN_P (prev)
 905                     && sets_cc0_p (PATTERN (prev))
 906                     && (next = try_combine (insn, XEXP (links, 0),
 907                                             prev, &new_direct_jump_p)) != 0)
 908                   goto retry;
 909 #endif
 910
 911               /* Try combining an insn with two different insns whose results it
 912                  uses.  */
 913               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 914                 for (nextlinks = XEXP (links, 1); nextlinks;
 915                      nextlinks = XEXP (nextlinks, 1))
 916                   if ((next = try_combine (insn, XEXP (links, 0),
 917                                            XEXP (nextlinks, 0),
 918                                            &new_direct_jump_p)) != 0)
 919                     goto retry;
 920
 921               /* Try this insn with each REG_EQUAL note it links back to.  */
 922               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 923                 {
 924                   rtx set, note;
 925                   rtx temp = XEXP (links, 0);
 926                   if ((set = single_set (temp)) != 0
 927                       && (note = find_reg_equal_equiv_note (temp)) != 0
 928                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 929                       /* Avoid using a register that may already been marked
 930                          dead by an earlier instruction.  */
 931                       && ! unmentioned_reg_p (note, SET_SRC (set))
 932                       && (GET_MODE (note) == VOIDmode
 933                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 934                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 935                     {
 936                       /* Temporarily replace the set's source with the
 937                          contents of the REG_EQUAL note.  The insn will
 938                          be deleted or recognized by try_combine.  */
 939                       rtx orig = SET_SRC (set);
 940                       SET_SRC (set) = note;
 941                       i2mod = temp;
 942                       i2mod_old_rhs = copy_rtx (orig);
 943                       i2mod_new_rhs = copy_rtx (note);
 944                       next = try_combine (insn, i2mod, NULL_RTX,
 945                                           &new_direct_jump_p);
 946                       i2mod = NULL_RTX;
 947                       if (next)
 948                         goto retry;
 949                       SET_SRC (set) = orig;
 950                     }
 951                 }
 952
 953               if (!NOTE_P (insn))
 954                 record_dead_and_set_regs (insn);
 955
 956             retry:
 957               ;
 958             }
 959         }
 960     }
 961   clear_bb_flags ();
 962
 963   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 964     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 965   new_direct_jump_p |= purge_all_dead_edges ();
 966   delete_noop_moves ();
 967
 968   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 969                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 970                                     | PROP_KILL_DEAD_CODE);
 971
 972   /* Clean up.  */
 973   sbitmap_free (refresh_blocks);
 974   free (uid_insn_cost);
 975   free (reg_stat);
 976   free (uid_cuid);
 977
 978   {
 979     struct undo *undo, *next;
 980     for (undo = undobuf.frees; undo; undo = next)
 981       {
 982         next = undo->next;
 983         free (undo);
 984       }
 985     undobuf.frees = 0;
 986   }
 987
 988   total_attempts += combine_attempts;
 989   total_merges += combine_merges;
 990   total_extras += combine_extras;
 991   total_successes += combine_successes;
 992
 993   nonzero_sign_valid = 0;
 994   rtl_hooks = general_rtl_hooks;
 995
 996   /* Make recognizer allow volatile MEMs again.  */
 997   init_recog ();
 998
 999   return new_direct_jump_p;
1000 }
1001
1002 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1003
1004 static void
1005 init_reg_last (void)
1006 {
1007   unsigned int i;
1008   for (i = 0; i < combine_max_regno; i++)
1009     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
1010 }
1011 \f
1012 /* Set up any promoted values for incoming argument registers.  */
1013
1014 static void
1015 setup_incoming_promotions (void)
1016 {
1017   unsigned int regno;
1018   rtx reg;
1019   enum machine_mode mode;
1020   int unsignedp;
1021   rtx first = get_insns ();
1022
1023   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1024     {
1025       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1026         /* Check whether this register can hold an incoming pointer
1027            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1028            numbers, so translate if necessary due to register windows.  */
1029         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1030             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1031           {
1032             record_value_for_reg
1033               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1034                                            : SIGN_EXTEND),
1035                                           GET_MODE (reg),
1036                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1037           }
1038     }
1039 }
1040 \f
1041 /* Called via note_stores.  If X is a pseudo that is narrower than
1042    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1043
1044    If we are setting only a portion of X and we can't figure out what
1045    portion, assume all bits will be used since we don't know what will
1046    be happening.
1047
1048    Similarly, set how many bits of X are known to be copies of the sign bit
1049    at all locations in the function.  This is the smallest number implied
1050    by any set of X.  */
1051
1052 static void
1053 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1054                                   void *data ATTRIBUTE_UNUSED)
1055 {
1056   unsigned int num;
1057
1058   if (REG_P (x)
1059       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1060       /* If this register is undefined at the start of the file, we can't
1061          say what its contents were.  */
1062       && ! REGNO_REG_SET_P
1063          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1064       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1065     {
1066       if (set == 0 || GET_CODE (set) == CLOBBER)
1067         {
1068           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1069           reg_stat[REGNO (x)].sign_bit_copies = 1;
1070           return;
1071         }
1072
1073       /* If this is a complex assignment, see if we can convert it into a
1074          simple assignment.  */
1075       set = expand_field_assignment (set);
1076
1077       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1078          set what we know about X.  */
1079
1080       if (SET_DEST (set) == x
1081           || (GET_CODE (SET_DEST (set)) == SUBREG
1082               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1083                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1084               && SUBREG_REG (SET_DEST (set)) == x))
1085         {
1086           rtx src = SET_SRC (set);
1087
1088 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1089           /* If X is narrower than a word and SRC is a non-negative
1090              constant that would appear negative in the mode of X,
1091              sign-extend it for use in reg_stat[].nonzero_bits because some
1092              machines (maybe most) will actually do the sign-extension
1093              and this is the conservative approach.
1094
1095              ??? For 2.5, try to tighten up the MD files in this regard
1096              instead of this kludge.  */
1097
1098           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1099               && GET_CODE (src) == CONST_INT
1100               && INTVAL (src) > 0
1101               && 0 != (INTVAL (src)
1102                        & ((HOST_WIDE_INT) 1
1103                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1104             src = GEN_INT (INTVAL (src)
1105                            | ((HOST_WIDE_INT) (-1)
1106                               << GET_MODE_BITSIZE (GET_MODE (x))));
1107 #endif
1108
1109           /* Don't call nonzero_bits if it cannot change anything.  */
1110           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1111             reg_stat[REGNO (x)].nonzero_bits
1112               |= nonzero_bits (src, nonzero_bits_mode);
1113           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1114           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1115               || reg_stat[REGNO (x)].sign_bit_copies > num)
1116             reg_stat[REGNO (x)].sign_bit_copies = num;
1117         }
1118       else
1119         {
1120           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1121           reg_stat[REGNO (x)].sign_bit_copies = 1;
1122         }
1123     }
1124 }
1125 \f
1126 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1127    insns that were previously combined into I3 or that will be combined
1128    into the merger of INSN and I3.
1129
1130    Return 0 if the combination is not allowed for any reason.
1131
1132    If the combination is allowed, *PDEST will be set to the single
1133    destination of INSN and *PSRC to the single source, and this function
1134    will return 1.  */
1135
1136 static int
1137 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1138                rtx *pdest, rtx *psrc)
1139 {
1140   int i;
1141   rtx set = 0, src, dest;
1142   rtx p;
1143 #ifdef AUTO_INC_DEC
1144   rtx link;
1145 #endif
1146   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1147                               && next_active_insn (succ) == i3)
1148                       : next_active_insn (insn) == i3);
1149
1150   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1151      or a PARALLEL consisting of such a SET and CLOBBERs.
1152
1153      If INSN has CLOBBER parallel parts, ignore them for our processing.
1154      By definition, these happen during the execution of the insn.  When it
1155      is merged with another insn, all bets are off.  If they are, in fact,
1156      needed and aren't also supplied in I3, they may be added by
1157      recog_for_combine.  Otherwise, it won't match.
1158
1159      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1160      note.
1161
1162      Get the source and destination of INSN.  If more than one, can't
1163      combine.  */
1164
1165   if (GET_CODE (PATTERN (insn)) == SET)
1166     set = PATTERN (insn);
1167   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1168            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1169     {
1170       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1171         {
1172           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1173           rtx note;
1174
1175           switch (GET_CODE (elt))
1176             {
1177             /* This is important to combine floating point insns
1178                for the SH4 port.  */
1179             case USE:
1180               /* Combining an isolated USE doesn't make sense.
1181                  We depend here on combinable_i3pat to reject them.  */
1182               /* The code below this loop only verifies that the inputs of
1183                  the SET in INSN do not change.  We call reg_set_between_p
1184                  to verify that the REG in the USE does not change between
1185                  I3 and INSN.
1186                  If the USE in INSN was for a pseudo register, the matching
1187                  insn pattern will likely match any register; combining this
1188                  with any other USE would only be safe if we knew that the
1189                  used registers have identical values, or if there was
1190                  something to tell them apart, e.g. different modes.  For
1191                  now, we forgo such complicated tests and simply disallow
1192                  combining of USES of pseudo registers with any other USE.  */
1193               if (REG_P (XEXP (elt, 0))
1194                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1195                 {
1196                   rtx i3pat = PATTERN (i3);
1197                   int i = XVECLEN (i3pat, 0) - 1;
1198                   unsigned int regno = REGNO (XEXP (elt, 0));
1199
1200                   do
1201                     {
1202                       rtx i3elt = XVECEXP (i3pat, 0, i);
1203
1204                       if (GET_CODE (i3elt) == USE
1205                           && REG_P (XEXP (i3elt, 0))
1206                           && (REGNO (XEXP (i3elt, 0)) == regno
1207                               ? reg_set_between_p (XEXP (elt, 0),
1208                                                    PREV_INSN (insn), i3)
1209                               : regno >= FIRST_PSEUDO_REGISTER))
1210                         return 0;
1211                     }
1212                   while (--i >= 0);
1213                 }
1214               break;
1215
1216               /* We can ignore CLOBBERs.  */
1217             case CLOBBER:
1218               break;
1219
1220             case SET:
1221               /* Ignore SETs whose result isn't used but not those that
1222                  have side-effects.  */
1223               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1224                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1225                       || INTVAL (XEXP (note, 0)) <= 0)
1226                   && ! side_effects_p (elt))
1227                 break;
1228
1229               /* If we have already found a SET, this is a second one and
1230                  so we cannot combine with this insn.  */
1231               if (set)
1232                 return 0;
1233
1234               set = elt;
1235               break;
1236
1237             default:
1238               /* Anything else means we can't combine.  */
1239               return 0;
1240             }
1241         }
1242
1243       if (set == 0
1244           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1245              so don't do anything with it.  */
1246           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1247         return 0;
1248     }
1249   else
1250     return 0;
1251
1252   if (set == 0)
1253     return 0;
1254
1255   set = expand_field_assignment (set);
1256   src = SET_SRC (set), dest = SET_DEST (set);
1257
1258   /* Don't eliminate a store in the stack pointer.  */
1259   if (dest == stack_pointer_rtx
1260       /* Don't combine with an insn that sets a register to itself if it has
1261          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1262       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1263       /* Can't merge an ASM_OPERANDS.  */
1264       || GET_CODE (src) == ASM_OPERANDS
1265       /* Can't merge a function call.  */
1266       || GET_CODE (src) == CALL
1267       /* Don't eliminate a function call argument.  */
1268       || (CALL_P (i3)
1269           && (find_reg_fusage (i3, USE, dest)
1270               || (REG_P (dest)
1271                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1272                   && global_regs[REGNO (dest)])))
1273       /* Don't substitute into an incremented register.  */
1274       || FIND_REG_INC_NOTE (i3, dest)
1275       || (succ && FIND_REG_INC_NOTE (succ, dest))
1276       /* Don't substitute into a non-local goto, this confuses CFG.  */
1277       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1278 #if 0
1279       /* Don't combine the end of a libcall into anything.  */
1280       /* ??? This gives worse code, and appears to be unnecessary, since no
1281          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1282          use REG_RETVAL notes for noconflict blocks, but other code here
1283          makes sure that those insns don't disappear.  */
1284       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1285 #endif
1286       /* Make sure that DEST is not used after SUCC but before I3.  */
1287       || (succ && ! all_adjacent
1288           && reg_used_between_p (dest, succ, i3))
1289       /* Make sure that the value that is to be substituted for the register
1290          does not use any registers whose values alter in between.  However,
1291          If the insns are adjacent, a use can't cross a set even though we
1292          think it might (this can happen for a sequence of insns each setting
1293          the same destination; last_set of that register might point to
1294          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1295          equivalent to the memory so the substitution is valid even if there
1296          are intervening stores.  Also, don't move a volatile asm or
1297          UNSPEC_VOLATILE across any other insns.  */
1298       || (! all_adjacent
1299           && (((!MEM_P (src)
1300                 || ! find_reg_note (insn, REG_EQUIV, src))
1301                && use_crosses_set_p (src, INSN_CUID (insn)))
1302               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1303               || GET_CODE (src) == UNSPEC_VOLATILE))
1304       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1305          better register allocation by not doing the combine.  */
1306       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1307       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1308       /* Don't combine across a CALL_INSN, because that would possibly
1309          change whether the life span of some REGs crosses calls or not,
1310          and it is a pain to update that information.
1311          Exception: if source is a constant, moving it later can't hurt.
1312          Accept that special case, because it helps -fforce-addr a lot.  */
1313       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1314     return 0;
1315
1316   /* DEST must either be a REG or CC0.  */
1317   if (REG_P (dest))
1318     {
1319       /* If register alignment is being enforced for multi-word items in all
1320          cases except for parameters, it is possible to have a register copy
1321          insn referencing a hard register that is not allowed to contain the
1322          mode being copied and which would not be valid as an operand of most
1323          insns.  Eliminate this problem by not combining with such an insn.
1324
1325          Also, on some machines we don't want to extend the life of a hard
1326          register.  */
1327
1328       if (REG_P (src)
1329           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1330                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1331               /* Don't extend the life of a hard register unless it is
1332                  user variable (if we have few registers) or it can't
1333                  fit into the desired register (meaning something special
1334                  is going on).
1335                  Also avoid substituting a return register into I3, because
1336                  reload can't handle a conflict with constraints of other
1337                  inputs.  */
1338               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1339                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1340         return 0;
1341     }
1342   else if (GET_CODE (dest) != CC0)
1343     return 0;
1344
1345
1346   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1347     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1348       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1349         {
1350           /* Don't substitute for a register intended as a clobberable
1351              operand.  */
1352           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1353           if (rtx_equal_p (reg, dest))
1354             return 0;
1355
1356           /* If the clobber represents an earlyclobber operand, we must not
1357              substitute an expression containing the clobbered register.
1358              As we do not analyze the constraint strings here, we have to
1359              make the conservative assumption.  However, if the register is
1360              a fixed hard reg, the clobber cannot represent any operand;
1361              we leave it up to the machine description to either accept or
1362              reject use-and-clobber patterns.  */
1363           if (!REG_P (reg)
1364               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1365               || !fixed_regs[REGNO (reg)])
1366             if (reg_overlap_mentioned_p (reg, src))
1367               return 0;
1368         }
1369
1370   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1371      or not), reject, unless nothing volatile comes between it and I3 */
1372
1373   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1374     {
1375       /* Make sure succ doesn't contain a volatile reference.  */
1376       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1377         return 0;
1378
1379       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1380         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1381           return 0;
1382     }
1383
1384   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1385      to be an explicit register variable, and was chosen for a reason.  */
1386
1387   if (GET_CODE (src) == ASM_OPERANDS
1388       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1389     return 0;
1390
1391   /* If there are any volatile insns between INSN and I3, reject, because
1392      they might affect machine state.  */
1393
1394   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1395     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1396       return 0;
1397
1398   /* If INSN contains an autoincrement or autodecrement, make sure that
1399      register is not used between there and I3, and not already used in
1400      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1401      Also insist that I3 not be a jump; if it were one
1402      and the incremented register were spilled, we would lose.  */
1403
1404 #ifdef AUTO_INC_DEC
1405   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1406     if (REG_NOTE_KIND (link) == REG_INC
1407         && (JUMP_P (i3)
1408             || reg_used_between_p (XEXP (link, 0), insn, i3)
1409             || (pred != NULL_RTX
1410                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1411             || (succ != NULL_RTX
1412                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1413             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1414       return 0;
1415 #endif
1416
1417 #ifdef HAVE_cc0
1418   /* Don't combine an insn that follows a CC0-setting insn.
1419      An insn that uses CC0 must not be separated from the one that sets it.
1420      We do, however, allow I2 to follow a CC0-setting insn if that insn
1421      is passed as I1; in that case it will be deleted also.
1422      We also allow combining in this case if all the insns are adjacent
1423      because that would leave the two CC0 insns adjacent as well.
1424      It would be more logical to test whether CC0 occurs inside I1 or I2,
1425      but that would be much slower, and this ought to be equivalent.  */
1426
1427   p = prev_nonnote_insn (insn);
1428   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1429       && ! all_adjacent)
1430     return 0;
1431 #endif
1432
1433   /* If we get here, we have passed all the tests and the combination is
1434      to be allowed.  */
1435
1436   *pdest = dest;
1437   *psrc = src;
1438
1439   return 1;
1440 }
1441 \f
1442 /* LOC is the location within I3 that contains its pattern or the component
1443    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1444
1445    One problem is if I3 modifies its output, as opposed to replacing it
1446    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1447    so would produce an insn that is not equivalent to the original insns.
1448
1449    Consider:
1450
1451          (set (reg:DI 101) (reg:DI 100))
1452          (set (subreg:SI (reg:DI 101) 0) <foo>)
1453
1454    This is NOT equivalent to:
1455
1456          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1457                     (set (reg:DI 101) (reg:DI 100))])
1458
1459    Not only does this modify 100 (in which case it might still be valid
1460    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1461
1462    We can also run into a problem if I2 sets a register that I1
1463    uses and I1 gets directly substituted into I3 (not via I2).  In that
1464    case, we would be getting the wrong value of I2DEST into I3, so we
1465    must reject the combination.  This case occurs when I2 and I1 both
1466    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1467    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1468    of a SET must prevent combination from occurring.
1469
1470    Before doing the above check, we first try to expand a field assignment
1471    into a set of logical operations.
1472
1473    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1474    we place a register that is both set and used within I3.  If more than one
1475    such register is detected, we fail.
1476
1477    Return 1 if the combination is valid, zero otherwise.  */
1478
1479 static int
1480 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1481                   int i1_not_in_src, rtx *pi3dest_killed)
1482 {
1483   rtx x = *loc;
1484
1485   if (GET_CODE (x) == SET)
1486     {
1487       rtx set = x ;
1488       rtx dest = SET_DEST (set);
1489       rtx src = SET_SRC (set);
1490       rtx inner_dest = dest;
1491       rtx subdest;
1492
1493       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1494              || GET_CODE (inner_dest) == SUBREG
1495              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1496         inner_dest = XEXP (inner_dest, 0);
1497
1498       /* Check for the case where I3 modifies its output, as discussed
1499          above.  We don't want to prevent pseudos from being combined
1500          into the address of a MEM, so only prevent the combination if
1501          i1 or i2 set the same MEM.  */
1502       if ((inner_dest != dest &&
1503            (!MEM_P (inner_dest)
1504             || rtx_equal_p (i2dest, inner_dest)
1505             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1506            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1507                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1508
1509           /* This is the same test done in can_combine_p except we can't test
1510              all_adjacent; we don't have to, since this instruction will stay
1511              in place, thus we are not considering increasing the lifetime of
1512              INNER_DEST.
1513
1514              Also, if this insn sets a function argument, combining it with
1515              something that might need a spill could clobber a previous
1516              function argument; the all_adjacent test in can_combine_p also
1517              checks this; here, we do a more specific test for this case.  */
1518
1519           || (REG_P (inner_dest)
1520               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1521               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1522                                         GET_MODE (inner_dest))))
1523           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1524         return 0;
1525
1526       /* If DEST is used in I3, it is being killed in this insn, so
1527          record that for later.  We have to consider paradoxical
1528          subregs here, since they kill the whole register, but we
1529          ignore partial subregs, STRICT_LOW_PART, etc.
1530          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1531          STACK_POINTER_REGNUM, since these are always considered to be
1532          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1533       subdest = dest;
1534       if (GET_CODE (subdest) == SUBREG
1535           && (GET_MODE_SIZE (GET_MODE (subdest))
1536               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1537         subdest = SUBREG_REG (subdest);
1538       if (pi3dest_killed
1539           && REG_P (subdest)
1540           && reg_referenced_p (subdest, PATTERN (i3))
1541           && REGNO (subdest) != FRAME_POINTER_REGNUM
1542 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1543           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1544 #endif
1545 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1546           && (REGNO (subdest) != ARG_POINTER_REGNUM
1547               || ! fixed_regs [REGNO (subdest)])
1548 #endif
1549           && REGNO (subdest) != STACK_POINTER_REGNUM)
1550         {
1551           if (*pi3dest_killed)
1552             return 0;
1553
1554           *pi3dest_killed = subdest;
1555         }
1556     }
1557
1558   else if (GET_CODE (x) == PARALLEL)
1559     {
1560       int i;
1561
1562       for (i = 0; i < XVECLEN (x, 0); i++)
1563         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1564                                 i1_not_in_src, pi3dest_killed))
1565           return 0;
1566     }
1567
1568   return 1;
1569 }
1570 \f
1571 /* Return 1 if X is an arithmetic expression that contains a multiplication
1572    and division.  We don't count multiplications by powers of two here.  */
1573
1574 static int
1575 contains_muldiv (rtx x)
1576 {
1577   switch (GET_CODE (x))
1578     {
1579     case MOD:  case DIV:  case UMOD:  case UDIV:
1580       return 1;
1581
1582     case MULT:
1583       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1584                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1585     default:
1586       if (BINARY_P (x))
1587         return contains_muldiv (XEXP (x, 0))
1588             || contains_muldiv (XEXP (x, 1));
1589
1590       if (UNARY_P (x))
1591         return contains_muldiv (XEXP (x, 0));
1592
1593       return 0;
1594     }
1595 }
1596 \f
1597 /* Determine whether INSN can be used in a combination.  Return nonzero if
1598    not.  This is used in try_combine to detect early some cases where we
1599    can't perform combinations.  */
1600
1601 static int
1602 cant_combine_insn_p (rtx insn)
1603 {
1604   rtx set;
1605   rtx src, dest;
1606
1607   /* If this isn't really an insn, we can't do anything.
1608      This can occur when flow deletes an insn that it has merged into an
1609      auto-increment address.  */
1610   if (! INSN_P (insn))
1611     return 1;
1612
1613   /* Never combine loads and stores involving hard regs that are likely
1614      to be spilled.  The register allocator can usually handle such
1615      reg-reg moves by tying.  If we allow the combiner to make
1616      substitutions of likely-spilled regs, reload might die.
1617      As an exception, we allow combinations involving fixed regs; these are
1618      not available to the register allocator so there's no risk involved.  */
1619
1620   set = single_set (insn);
1621   if (! set)
1622     return 0;
1623   src = SET_SRC (set);
1624   dest = SET_DEST (set);
1625   if (GET_CODE (src) == SUBREG)
1626     src = SUBREG_REG (src);
1627   if (GET_CODE (dest) == SUBREG)
1628     dest = SUBREG_REG (dest);
1629   if (REG_P (src) && REG_P (dest)
1630       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1631            && ! fixed_regs[REGNO (src)]
1632            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1633           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1634               && ! fixed_regs[REGNO (dest)]
1635               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1636     return 1;
1637
1638   return 0;
1639 }
1640
1641 struct likely_spilled_retval_info
1642 {
1643   unsigned regno, nregs;
1644   unsigned mask;
1645 };
1646
1647 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1648    hard registers that are known to be written to / clobbered in full.  */
1649 static void
1650 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1651 {
1652   struct likely_spilled_retval_info *info = data;
1653   unsigned regno, nregs;
1654   unsigned new_mask;
1655
1656   if (!REG_P (XEXP (set, 0)))
1657     return;
1658   regno = REGNO (x);
1659   if (regno >= info->regno + info->nregs)
1660     return;
1661   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1662   if (regno + nregs <= info->regno)
1663     return;
1664   new_mask = (2U << (nregs - 1)) - 1;
1665   if (regno < info->regno)
1666     new_mask >>= info->regno - regno;
1667   else
1668     new_mask <<= regno - info->regno;
1669   info->mask &= ~new_mask;
1670 }
1671
1672 /* Return nonzero iff part of the return value is live during INSN, and
1673    it is likely spilled.  This can happen when more than one insn is needed
1674    to copy the return value, e.g. when we consider to combine into the
1675    second copy insn for a complex value.  */
1676
1677 static int
1678 likely_spilled_retval_p (rtx insn)
1679 {
1680   rtx use = BB_END (this_basic_block);
1681   rtx reg, p;
1682   unsigned regno, nregs;
1683   /* We assume here that no machine mode needs more than
1684      32 hard registers when the value overlaps with a register
1685      for which FUNCTION_VALUE_REGNO_P is true.  */
1686   unsigned mask;
1687   struct likely_spilled_retval_info info;
1688
1689   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1690     return 0;
1691   reg = XEXP (PATTERN (use), 0);
1692   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1693     return 0;
1694   regno = REGNO (reg);
1695   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1696   if (nregs == 1)
1697     return 0;
1698   mask = (2U << (nregs - 1)) - 1;
1699
1700   /* Disregard parts of the return value that are set later.  */
1701   info.regno = regno;
1702   info.nregs = nregs;
1703   info.mask = mask;
1704   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1705     if (INSN_P (p))
1706       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
1707   mask = info.mask;
1708
1709   /* Check if any of the (probably) live return value registers is
1710      likely spilled.  */
1711   nregs --;
1712   do
1713     {
1714       if ((mask & 1 << nregs)
1715           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1716         return 1;
1717     } while (nregs--);
1718   return 0;
1719 }
1720
1721 /* Adjust INSN after we made a change to its destination.
1722
1723    Changing the destination can invalidate notes that say something about
1724    the results of the insn and a LOG_LINK pointing to the insn.  */
1725
1726 static void
1727 adjust_for_new_dest (rtx insn)
1728 {
1729   rtx *loc;
1730
1731   /* For notes, be conservative and simply remove them.  */
1732   loc = &REG_NOTES (insn);
1733   while (*loc)
1734     {
1735       enum reg_note kind = REG_NOTE_KIND (*loc);
1736       if (kind == REG_EQUAL || kind == REG_EQUIV)
1737         *loc = XEXP (*loc, 1);
1738       else
1739         loc = &XEXP (*loc, 1);
1740     }
1741
1742   /* The new insn will have a destination that was previously the destination
1743      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1744      the next use of that destination.  */
1745   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1746 }
1747
1748 /* Return TRUE if combine can reuse reg X in mode MODE.
1749    ADDED_SETS is nonzero if the original set is still required.  */
1750 static bool
1751 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1752 {
1753   unsigned int regno;
1754
1755   if (!REG_P(x))
1756     return false;
1757
1758   regno = REGNO (x);
1759   /* Allow hard registers if the new mode is legal, and occupies no more
1760      registers than the old mode.  */
1761   if (regno < FIRST_PSEUDO_REGISTER)
1762     return (HARD_REGNO_MODE_OK (regno, mode)
1763             && (hard_regno_nregs[regno][GET_MODE (x)]
1764                 >= hard_regno_nregs[regno][mode]));
1765
1766   /* Or a pseudo that is only used once.  */
1767   return (REG_N_SETS (regno) == 1 && !added_sets
1768           && !REG_USERVAR_P (x));
1769 }
1770
1771
1772 /* Check whether X, the destination of a set, refers to part of
1773    the register specified by REG.  */
1774
1775 static bool
1776 reg_subword_p (rtx x, rtx reg)
1777 {
1778   /* Check that reg is an integer mode register.  */
1779   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1780     return false;
1781
1782   if (GET_CODE (x) == STRICT_LOW_PART
1783       || GET_CODE (x) == ZERO_EXTRACT)
1784     x = XEXP (x, 0);
1785
1786   return GET_CODE (x) == SUBREG
1787          && SUBREG_REG (x) == reg
1788          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1789 }
1790
1791
1792 /* Try to combine the insns I1 and I2 into I3.
1793    Here I1 and I2 appear earlier than I3.
1794    I1 can be zero; then we combine just I2 into I3.
1795
1796    If we are combining three insns and the resulting insn is not recognized,
1797    try splitting it into two insns.  If that happens, I2 and I3 are retained
1798    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1799    are pseudo-deleted.
1800
1801    Return 0 if the combination does not work.  Then nothing is changed.
1802    If we did the combination, return the insn at which combine should
1803    resume scanning.
1804
1805    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1806    new direct jump instruction.  */
1807
1808 static rtx
1809 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1810 {
1811   /* New patterns for I3 and I2, respectively.  */
1812   rtx newpat, newi2pat = 0;
1813   rtvec newpat_vec_with_clobbers = 0;
1814   int substed_i2 = 0, substed_i1 = 0;
1815   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1816   int added_sets_1, added_sets_2;
1817   /* Total number of SETs to put into I3.  */
1818   int total_sets;
1819   /* Nonzero if I2's body now appears in I3.  */
1820   int i2_is_used;
1821   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1822   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1823   /* Contains I3 if the destination of I3 is used in its source, which means
1824      that the old life of I3 is being killed.  If that usage is placed into
1825      I2 and not in I3, a REG_DEAD note must be made.  */
1826   rtx i3dest_killed = 0;
1827   /* SET_DEST and SET_SRC of I2 and I1.  */
1828   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1829   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
1830   rtx i1pat = 0, i2pat = 0;
1831   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1832   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1833   int i2dest_killed = 0, i1dest_killed = 0;
1834   int i1_feeds_i3 = 0;
1835   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1836   rtx new_i3_notes, new_i2_notes;
1837   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1838   int i3_subst_into_i2 = 0;
1839   /* Notes that I1, I2 or I3 is a MULT operation.  */
1840   int have_mult = 0;
1841   int swap_i2i3 = 0;
1842
1843   int maxreg;
1844   rtx temp;
1845   rtx link;
1846   int i;
1847
1848   /* Exit early if one of the insns involved can't be used for
1849      combinations.  */
1850   if (cant_combine_insn_p (i3)
1851       || cant_combine_insn_p (i2)
1852       || (i1 && cant_combine_insn_p (i1))
1853       || likely_spilled_retval_p (i3)
1854       /* We also can't do anything if I3 has a
1855          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1856          libcall.  */
1857 #if 0
1858       /* ??? This gives worse code, and appears to be unnecessary, since no
1859          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1860       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1861 #endif
1862       )
1863     return 0;
1864
1865   combine_attempts++;
1866   undobuf.other_insn = 0;
1867
1868   /* Reset the hard register usage information.  */
1869   CLEAR_HARD_REG_SET (newpat_used_regs);
1870
1871   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1872      code below, set I1 to be the earlier of the two insns.  */
1873   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1874     temp = i1, i1 = i2, i2 = temp;
1875
1876   added_links_insn = 0;
1877
1878   /* First check for one important special-case that the code below will
1879      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1880      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1881      we may be able to replace that destination with the destination of I3.
1882      This occurs in the common code where we compute both a quotient and
1883      remainder into a structure, in which case we want to do the computation
1884      directly into the structure to avoid register-register copies.
1885
1886      Note that this case handles both multiple sets in I2 and also
1887      cases where I2 has a number of CLOBBER or PARALLELs.
1888
1889      We make very conservative checks below and only try to handle the
1890      most common cases of this.  For example, we only handle the case
1891      where I2 and I3 are adjacent to avoid making difficult register
1892      usage tests.  */
1893
1894   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1895       && REG_P (SET_SRC (PATTERN (i3)))
1896       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1897       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1898       && GET_CODE (PATTERN (i2)) == PARALLEL
1899       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1900       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1901          below would need to check what is inside (and reg_overlap_mentioned_p
1902          doesn't support those codes anyway).  Don't allow those destinations;
1903          the resulting insn isn't likely to be recognized anyway.  */
1904       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1905       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1906       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1907                                     SET_DEST (PATTERN (i3)))
1908       && next_real_insn (i2) == i3)
1909     {
1910       rtx p2 = PATTERN (i2);
1911
1912       /* Make sure that the destination of I3,
1913          which we are going to substitute into one output of I2,
1914          is not used within another output of I2.  We must avoid making this:
1915          (parallel [(set (mem (reg 69)) ...)
1916                     (set (reg 69) ...)])
1917          which is not well-defined as to order of actions.
1918          (Besides, reload can't handle output reloads for this.)
1919
1920          The problem can also happen if the dest of I3 is a memory ref,
1921          if another dest in I2 is an indirect memory ref.  */
1922       for (i = 0; i < XVECLEN (p2, 0); i++)
1923         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1924              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1925             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1926                                         SET_DEST (XVECEXP (p2, 0, i))))
1927           break;
1928
1929       if (i == XVECLEN (p2, 0))
1930         for (i = 0; i < XVECLEN (p2, 0); i++)
1931           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1932                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1933               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1934             {
1935               combine_merges++;
1936
1937               subst_insn = i3;
1938               subst_low_cuid = INSN_CUID (i2);
1939
1940               added_sets_2 = added_sets_1 = 0;
1941               i2dest = SET_SRC (PATTERN (i3));
1942               i2dest_killed = dead_or_set_p (i2, i2dest);
1943
1944               /* Replace the dest in I2 with our dest and make the resulting
1945                  insn the new pattern for I3.  Then skip to where we
1946                  validate the pattern.  Everything was set up above.  */
1947               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1948                      SET_DEST (PATTERN (i3)));
1949
1950               newpat = p2;
1951               i3_subst_into_i2 = 1;
1952               goto validate_replacement;
1953             }
1954     }
1955
1956   /* If I2 is setting a pseudo to a constant and I3 is setting some
1957      sub-part of it to another constant, merge them by making a new
1958      constant.  */
1959   if (i1 == 0
1960       && (temp = single_set (i2)) != 0
1961       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1962           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1963       && GET_CODE (PATTERN (i3)) == SET
1964       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1965           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1966       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1967     {
1968       rtx dest = SET_DEST (PATTERN (i3));
1969       int offset = -1;
1970       int width = 0;
1971
1972       if (GET_CODE (dest) == ZERO_EXTRACT)
1973         {
1974           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1975               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1976             {
1977               width = INTVAL (XEXP (dest, 1));
1978               offset = INTVAL (XEXP (dest, 2));
1979               dest = XEXP (dest, 0);
1980               if (BITS_BIG_ENDIAN)
1981                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1982             }
1983         }
1984       else
1985         {
1986           if (GET_CODE (dest) == STRICT_LOW_PART)
1987             dest = XEXP (dest, 0);
1988           width = GET_MODE_BITSIZE (GET_MODE (dest));
1989           offset = 0;
1990         }
1991
1992       if (offset >= 0)
1993         {
1994           /* If this is the low part, we're done.  */
1995           if (subreg_lowpart_p (dest))
1996             ;
1997           /* Handle the case where inner is twice the size of outer.  */
1998           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1999                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2000             offset += GET_MODE_BITSIZE (GET_MODE (dest));
2001           /* Otherwise give up for now.  */
2002           else
2003             offset = -1;
2004         }
2005
2006       if (offset >= 0)
2007         {
2008           HOST_WIDE_INT mhi, ohi, ihi;
2009           HOST_WIDE_INT mlo, olo, ilo;
2010           rtx inner = SET_SRC (PATTERN (i3));
2011           rtx outer = SET_SRC (temp);
2012
2013           if (GET_CODE (outer) == CONST_INT)
2014             {
2015               olo = INTVAL (outer);
2016               ohi = olo < 0 ? -1 : 0;
2017             }
2018           else
2019             {
2020               olo = CONST_DOUBLE_LOW (outer);
2021               ohi = CONST_DOUBLE_HIGH (outer);
2022             }
2023
2024           if (GET_CODE (inner) == CONST_INT)
2025             {
2026               ilo = INTVAL (inner);
2027               ihi = ilo < 0 ? -1 : 0;
2028             }
2029           else
2030             {
2031               ilo = CONST_DOUBLE_LOW (inner);
2032               ihi = CONST_DOUBLE_HIGH (inner);
2033             }
2034
2035           if (width < HOST_BITS_PER_WIDE_INT)
2036             {
2037               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2038               mhi = 0;
2039             }
2040           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2041             {
2042               mhi = ((unsigned HOST_WIDE_INT) 1
2043                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2044               mlo = -1;
2045             }
2046           else
2047             {
2048               mlo = -1;
2049               mhi = -1;
2050             }
2051
2052           ilo &= mlo;
2053           ihi &= mhi;
2054
2055           if (offset >= HOST_BITS_PER_WIDE_INT)
2056             {
2057               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2058               mlo = 0;
2059               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2060               ilo = 0;
2061             }
2062           else if (offset > 0)
2063             {
2064               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2065                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2066               mlo = mlo << offset;
2067               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2068                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2069               ilo = ilo << offset;
2070             }
2071
2072           olo = (olo & ~mlo) | ilo;
2073           ohi = (ohi & ~mhi) | ihi;
2074
2075           combine_merges++;
2076           subst_insn = i3;
2077           subst_low_cuid = INSN_CUID (i2);
2078           added_sets_2 = added_sets_1 = 0;
2079           i2dest = SET_DEST (temp);
2080           i2dest_killed = dead_or_set_p (i2, i2dest);
2081
2082           SUBST (SET_SRC (temp),
2083                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2084
2085           newpat = PATTERN (i2);
2086           goto validate_replacement;
2087         }
2088     }
2089
2090 #ifndef HAVE_cc0
2091   /* If we have no I1 and I2 looks like:
2092         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2093                    (set Y OP)])
2094      make up a dummy I1 that is
2095         (set Y OP)
2096      and change I2 to be
2097         (set (reg:CC X) (compare:CC Y (const_int 0)))
2098
2099      (We can ignore any trailing CLOBBERs.)
2100
2101      This undoes a previous combination and allows us to match a branch-and-
2102      decrement insn.  */
2103
2104   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2105       && XVECLEN (PATTERN (i2), 0) >= 2
2106       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2107       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2108           == MODE_CC)
2109       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2110       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2111       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2112       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2113       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2114                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2115     {
2116       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2117         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2118           break;
2119
2120       if (i == 1)
2121         {
2122           /* We make I1 with the same INSN_UID as I2.  This gives it
2123              the same INSN_CUID for value tracking.  Our fake I1 will
2124              never appear in the insn stream so giving it the same INSN_UID
2125              as I2 will not cause a problem.  */
2126
2127           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2128                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2129                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2130                              NULL_RTX);
2131
2132           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2133           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2134                  SET_DEST (PATTERN (i1)));
2135         }
2136     }
2137 #endif
2138
2139   /* Verify that I2 and I1 are valid for combining.  */
2140   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2141       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2142     {
2143       undo_all ();
2144       return 0;
2145     }
2146
2147   /* Record whether I2DEST is used in I2SRC and similarly for the other
2148      cases.  Knowing this will help in register status updating below.  */
2149   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2150   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2151   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2152   i2dest_killed = dead_or_set_p (i2, i2dest);
2153   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2154
2155   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2156      in I2SRC.  */
2157   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2158
2159   /* Ensure that I3's pattern can be the destination of combines.  */
2160   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2161                           i1 && i2dest_in_i1src && i1_feeds_i3,
2162                           &i3dest_killed))
2163     {
2164       undo_all ();
2165       return 0;
2166     }
2167
2168   /* See if any of the insns is a MULT operation.  Unless one is, we will
2169      reject a combination that is, since it must be slower.  Be conservative
2170      here.  */
2171   if (GET_CODE (i2src) == MULT
2172       || (i1 != 0 && GET_CODE (i1src) == MULT)
2173       || (GET_CODE (PATTERN (i3)) == SET
2174           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2175     have_mult = 1;
2176
2177   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2178      We used to do this EXCEPT in one case: I3 has a post-inc in an
2179      output operand.  However, that exception can give rise to insns like
2180         mov r3,(r3)+
2181      which is a famous insn on the PDP-11 where the value of r3 used as the
2182      source was model-dependent.  Avoid this sort of thing.  */
2183
2184 #if 0
2185   if (!(GET_CODE (PATTERN (i3)) == SET
2186         && REG_P (SET_SRC (PATTERN (i3)))
2187         && MEM_P (SET_DEST (PATTERN (i3)))
2188         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2189             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2190     /* It's not the exception.  */
2191 #endif
2192 #ifdef AUTO_INC_DEC
2193     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2194       if (REG_NOTE_KIND (link) == REG_INC
2195           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2196               || (i1 != 0
2197                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2198         {
2199           undo_all ();
2200           return 0;
2201         }
2202 #endif
2203
2204   /* See if the SETs in I1 or I2 need to be kept around in the merged
2205      instruction: whenever the value set there is still needed past I3.
2206      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2207
2208      For the SET in I1, we have two cases:  If I1 and I2 independently
2209      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2210      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2211      in I1 needs to be kept around unless I1DEST dies or is set in either
2212      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2213      I1DEST.  If so, we know I1 feeds into I2.  */
2214
2215   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2216
2217   added_sets_1
2218     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2219                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2220
2221   /* If the set in I2 needs to be kept around, we must make a copy of
2222      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2223      PATTERN (I2), we are only substituting for the original I1DEST, not into
2224      an already-substituted copy.  This also prevents making self-referential
2225      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2226      I2DEST.  */
2227
2228   if (added_sets_2)
2229     {
2230       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2231         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2232       else
2233         i2pat = copy_rtx (PATTERN (i2));
2234     }
2235
2236   if (added_sets_1)
2237     {
2238       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2239         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2240       else
2241         i1pat = copy_rtx (PATTERN (i1));
2242     }
2243
2244   combine_merges++;
2245
2246   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2247
2248   maxreg = max_reg_num ();
2249
2250   subst_insn = i3;
2251
2252 #ifndef HAVE_cc0
2253   /* Many machines that don't use CC0 have insns that can both perform an
2254      arithmetic operation and set the condition code.  These operations will
2255      be represented as a PARALLEL with the first element of the vector
2256      being a COMPARE of an arithmetic operation with the constant zero.
2257      The second element of the vector will set some pseudo to the result
2258      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2259      match such a pattern and so will generate an extra insn.   Here we test
2260      for this case, where both the comparison and the operation result are
2261      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2262      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2263
2264   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2265       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2266       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2267       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2268     {
2269 #ifdef SELECT_CC_MODE
2270       rtx *cc_use;
2271       enum machine_mode compare_mode;
2272 #endif
2273
2274       newpat = PATTERN (i3);
2275       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2276
2277       i2_is_used = 1;
2278
2279 #ifdef SELECT_CC_MODE
2280       /* See if a COMPARE with the operand we substituted in should be done
2281          with the mode that is currently being used.  If not, do the same
2282          processing we do in `subst' for a SET; namely, if the destination
2283          is used only once, try to replace it with a register of the proper
2284          mode and also replace the COMPARE.  */
2285       if (undobuf.other_insn == 0
2286           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2287                                         &undobuf.other_insn))
2288           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2289                                               i2src, const0_rtx))
2290               != GET_MODE (SET_DEST (newpat))))
2291         {
2292           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2293                                    compare_mode))
2294             {
2295               unsigned int regno = REGNO (SET_DEST (newpat));
2296               rtx new_dest;
2297
2298               if (regno < FIRST_PSEUDO_REGISTER)
2299                 new_dest = gen_rtx_REG (compare_mode, regno);
2300               else
2301                 {
2302                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2303                   new_dest = regno_reg_rtx[regno];
2304                 }
2305
2306               SUBST (SET_DEST (newpat), new_dest);
2307               SUBST (XEXP (*cc_use, 0), new_dest);
2308               SUBST (SET_SRC (newpat),
2309                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2310             }
2311           else
2312             undobuf.other_insn = 0;
2313         }
2314 #endif
2315     }
2316   else
2317 #endif
2318     {
2319       /* It is possible that the source of I2 or I1 may be performing
2320          an unneeded operation, such as a ZERO_EXTEND of something
2321          that is known to have the high part zero.  Handle that case
2322          by letting subst look at the innermost one of them.
2323
2324          Another way to do this would be to have a function that tries
2325          to simplify a single insn instead of merging two or more
2326          insns.  We don't do this because of the potential of infinite
2327          loops and because of the potential extra memory required.
2328          However, doing it the way we are is a bit of a kludge and
2329          doesn't catch all cases.
2330
2331          But only do this if -fexpensive-optimizations since it slows
2332          things down and doesn't usually win.
2333
2334          This is not done in the COMPARE case above because the
2335          unmodified I2PAT is used in the PARALLEL and so a pattern
2336          with a modified I2SRC would not match.  */
2337
2338       if (flag_expensive_optimizations)
2339         {
2340           /* Pass pc_rtx so no substitutions are done, just
2341              simplifications.  */
2342           if (i1)
2343             {
2344               subst_low_cuid = INSN_CUID (i1);
2345               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2346             }
2347           else
2348             {
2349               subst_low_cuid = INSN_CUID (i2);
2350               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2351             }
2352         }
2353
2354       n_occurrences = 0;                /* `subst' counts here */
2355
2356       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2357          need to make a unique copy of I2SRC each time we substitute it
2358          to avoid self-referential rtl.  */
2359
2360       subst_low_cuid = INSN_CUID (i2);
2361       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2362                       ! i1_feeds_i3 && i1dest_in_i1src);
2363       substed_i2 = 1;
2364
2365       /* Record whether i2's body now appears within i3's body.  */
2366       i2_is_used = n_occurrences;
2367     }
2368
2369   /* If we already got a failure, don't try to do more.  Otherwise,
2370      try to substitute in I1 if we have it.  */
2371
2372   if (i1 && GET_CODE (newpat) != CLOBBER)
2373     {
2374       /* Before we can do this substitution, we must redo the test done
2375          above (see detailed comments there) that ensures  that I1DEST
2376          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2377
2378       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2379                               0, (rtx*) 0))
2380         {
2381           undo_all ();
2382           return 0;
2383         }
2384
2385       n_occurrences = 0;
2386       subst_low_cuid = INSN_CUID (i1);
2387       newpat = subst (newpat, i1dest, i1src, 0, 0);
2388       substed_i1 = 1;
2389     }
2390
2391   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2392      to count all the ways that I2SRC and I1SRC can be used.  */
2393   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2394        && i2_is_used + added_sets_2 > 1)
2395       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2396           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2397               > 1))
2398       /* Fail if we tried to make a new register.  */
2399       || max_reg_num () != maxreg
2400       /* Fail if we couldn't do something and have a CLOBBER.  */
2401       || GET_CODE (newpat) == CLOBBER
2402       /* Fail if this new pattern is a MULT and we didn't have one before
2403          at the outer level.  */
2404       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2405           && ! have_mult))
2406     {
2407       undo_all ();
2408       return 0;
2409     }
2410
2411   /* If the actions of the earlier insns must be kept
2412      in addition to substituting them into the latest one,
2413      we must make a new PARALLEL for the latest insn
2414      to hold additional the SETs.  */
2415
2416   if (added_sets_1 || added_sets_2)
2417     {
2418       combine_extras++;
2419
2420       if (GET_CODE (newpat) == PARALLEL)
2421         {
2422           rtvec old = XVEC (newpat, 0);
2423           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2424           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2425           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2426                   sizeof (old->elem[0]) * old->num_elem);
2427         }
2428       else
2429         {
2430           rtx old = newpat;
2431           total_sets = 1 + added_sets_1 + added_sets_2;
2432           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2433           XVECEXP (newpat, 0, 0) = old;
2434         }
2435
2436       if (added_sets_1)
2437         XVECEXP (newpat, 0, --total_sets) = i1pat;
2438
2439       if (added_sets_2)
2440         {
2441           /* If there is no I1, use I2's body as is.  We used to also not do
2442              the subst call below if I2 was substituted into I3,
2443              but that could lose a simplification.  */
2444           if (i1 == 0)
2445             XVECEXP (newpat, 0, --total_sets) = i2pat;
2446           else
2447             /* See comment where i2pat is assigned.  */
2448             XVECEXP (newpat, 0, --total_sets)
2449               = subst (i2pat, i1dest, i1src, 0, 0);
2450         }
2451     }
2452
2453   /* We come here when we are replacing a destination in I2 with the
2454      destination of I3.  */
2455  validate_replacement:
2456
2457   /* Note which hard regs this insn has as inputs.  */
2458   mark_used_regs_combine (newpat);
2459
2460   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2461      consider splitting this pattern, we might need these clobbers.  */
2462   if (i1 && GET_CODE (newpat) == PARALLEL
2463       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2464     {
2465       int len = XVECLEN (newpat, 0);
2466
2467       newpat_vec_with_clobbers = rtvec_alloc (len);
2468       for (i = 0; i < len; i++)
2469         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2470     }
2471
2472   /* Is the result of combination a valid instruction?  */
2473   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2474
2475   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2476      the second SET's destination is a register that is unused and isn't
2477      marked as an instruction that might trap in an EH region.  In that case,
2478      we just need the first SET.   This can occur when simplifying a divmod
2479      insn.  We *must* test for this case here because the code below that
2480      splits two independent SETs doesn't handle this case correctly when it
2481      updates the register status.
2482
2483      It's pointless doing this if we originally had two sets, one from
2484      i3, and one from i2.  Combining then splitting the parallel results
2485      in the original i2 again plus an invalid insn (which we delete).
2486      The net effect is only to move instructions around, which makes
2487      debug info less accurate.
2488
2489      Also check the case where the first SET's destination is unused.
2490      That would not cause incorrect code, but does cause an unneeded
2491      insn to remain.  */
2492
2493   if (insn_code_number < 0
2494       && !(added_sets_2 && i1 == 0)
2495       && GET_CODE (newpat) == PARALLEL
2496       && XVECLEN (newpat, 0) == 2
2497       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2498       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2499       && asm_noperands (newpat) < 0)
2500     {
2501       rtx set0 = XVECEXP (newpat, 0, 0);
2502       rtx set1 = XVECEXP (newpat, 0, 1);
2503       rtx note;
2504
2505       if (((REG_P (SET_DEST (set1))
2506             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2507            || (GET_CODE (SET_DEST (set1)) == SUBREG
2508                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2509           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2510               || INTVAL (XEXP (note, 0)) <= 0)
2511           && ! side_effects_p (SET_SRC (set1)))
2512         {
2513           newpat = set0;
2514           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2515         }
2516
2517       else if (((REG_P (SET_DEST (set0))
2518                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2519                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2520                     && find_reg_note (i3, REG_UNUSED,
2521                                       SUBREG_REG (SET_DEST (set0)))))
2522                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2523                    || INTVAL (XEXP (note, 0)) <= 0)
2524                && ! side_effects_p (SET_SRC (set0)))
2525         {
2526           newpat = set1;
2527           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2528
2529           if (insn_code_number >= 0)
2530             {
2531               /* If we will be able to accept this, we have made a
2532                  change to the destination of I3.  This requires us to
2533                  do a few adjustments.  */
2534
2535               PATTERN (i3) = newpat;
2536               adjust_for_new_dest (i3);
2537             }
2538         }
2539     }
2540
2541   /* If we were combining three insns and the result is a simple SET
2542      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2543      insns.  There are two ways to do this.  It can be split using a
2544      machine-specific method (like when you have an addition of a large
2545      constant) or by combine in the function find_split_point.  */
2546
2547   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2548       && asm_noperands (newpat) < 0)
2549     {
2550       rtx m_split, *split;
2551
2552       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2553          use I2DEST as a scratch register will help.  In the latter case,
2554          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2555
2556       m_split = split_insns (newpat, i3);
2557
2558       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2559          inputs of NEWPAT.  */
2560
2561       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2562          possible to try that as a scratch reg.  This would require adding
2563          more code to make it work though.  */
2564
2565       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2566         {
2567           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2568
2569           /* First try to split using the original register as a
2570              scratch register.  */
2571           m_split = split_insns (gen_rtx_PARALLEL
2572                                  (VOIDmode,
2573                                   gen_rtvec (2, newpat,
2574                                              gen_rtx_CLOBBER (VOIDmode,
2575                                                               i2dest))),
2576                                  i3);
2577
2578           /* If that didn't work, try changing the mode of I2DEST if
2579              we can.  */
2580           if (m_split == 0
2581               && new_mode != GET_MODE (i2dest)
2582               && new_mode != VOIDmode
2583               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2584             {
2585               enum machine_mode old_mode = GET_MODE (i2dest);
2586               rtx ni2dest;
2587
2588               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2589                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2590               else
2591                 {
2592                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2593                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2594                 }
2595
2596               m_split = split_insns (gen_rtx_PARALLEL
2597                                      (VOIDmode,
2598                                       gen_rtvec (2, newpat,
2599                                                  gen_rtx_CLOBBER (VOIDmode,
2600                                                                   ni2dest))),
2601                                      i3);
2602
2603               if (m_split == 0
2604                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2605                 {
2606                   struct undo *buf;
2607
2608                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2609                   buf = undobuf.undos;
2610                   undobuf.undos = buf->next;
2611                   buf->next = undobuf.frees;
2612                   undobuf.frees = buf;
2613                 }
2614             }
2615         }
2616
2617       /* If recog_for_combine has discarded clobbers, try to use them
2618          again for the split.  */
2619       if (m_split == 0 && newpat_vec_with_clobbers)
2620         m_split
2621           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2622                                            newpat_vec_with_clobbers), i3);
2623
2624       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2625         {
2626           m_split = PATTERN (m_split);
2627           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2628           if (insn_code_number >= 0)
2629             newpat = m_split;
2630         }
2631       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2632                && (next_real_insn (i2) == i3
2633                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2634         {
2635           rtx i2set, i3set;
2636           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2637           newi2pat = PATTERN (m_split);
2638
2639           i3set = single_set (NEXT_INSN (m_split));
2640           i2set = single_set (m_split);
2641
2642           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2643
2644           /* If I2 or I3 has multiple SETs, we won't know how to track
2645              register status, so don't use these insns.  If I2's destination
2646              is used between I2 and I3, we also can't use these insns.  */
2647
2648           if (i2_code_number >= 0 && i2set && i3set
2649               && (next_real_insn (i2) == i3
2650                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2651             insn_code_number = recog_for_combine (&newi3pat, i3,
2652                                                   &new_i3_notes);
2653           if (insn_code_number >= 0)
2654             newpat = newi3pat;
2655
2656           /* It is possible that both insns now set the destination of I3.
2657              If so, we must show an extra use of it.  */
2658
2659           if (insn_code_number >= 0)
2660             {
2661               rtx new_i3_dest = SET_DEST (i3set);
2662               rtx new_i2_dest = SET_DEST (i2set);
2663
2664               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2665                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2666                      || GET_CODE (new_i3_dest) == SUBREG)
2667                 new_i3_dest = XEXP (new_i3_dest, 0);
2668
2669               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2670                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2671                      || GET_CODE (new_i2_dest) == SUBREG)
2672                 new_i2_dest = XEXP (new_i2_dest, 0);
2673
2674               if (REG_P (new_i3_dest)
2675                   && REG_P (new_i2_dest)
2676                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2677                 REG_N_SETS (REGNO (new_i2_dest))++;
2678             }
2679         }
2680
2681       /* If we can split it and use I2DEST, go ahead and see if that
2682          helps things be recognized.  Verify that none of the registers
2683          are set between I2 and I3.  */
2684       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2685 #ifdef HAVE_cc0
2686           && REG_P (i2dest)
2687 #endif
2688           /* We need I2DEST in the proper mode.  If it is a hard register
2689              or the only use of a pseudo, we can change its mode.
2690              Make sure we don't change a hard register to have a mode that
2691              isn't valid for it, or change the number of registers.  */
2692           && (GET_MODE (*split) == GET_MODE (i2dest)
2693               || GET_MODE (*split) == VOIDmode
2694               || can_change_dest_mode (i2dest, added_sets_2,
2695                                        GET_MODE (*split)))
2696           && (next_real_insn (i2) == i3
2697               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2698           /* We can't overwrite I2DEST if its value is still used by
2699              NEWPAT.  */
2700           && ! reg_referenced_p (i2dest, newpat))
2701         {
2702           rtx newdest = i2dest;
2703           enum rtx_code split_code = GET_CODE (*split);
2704           enum machine_mode split_mode = GET_MODE (*split);
2705           bool subst_done = false;
2706           newi2pat = NULL_RTX;
2707
2708           /* Get NEWDEST as a register in the proper mode.  We have already
2709              validated that we can do this.  */
2710           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2711             {
2712               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2713                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2714               else
2715                 {
2716                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2717                   newdest = regno_reg_rtx[REGNO (i2dest)];
2718                 }
2719             }
2720
2721           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2722              an ASHIFT.  This can occur if it was inside a PLUS and hence
2723              appeared to be a memory address.  This is a kludge.  */
2724           if (split_code == MULT
2725               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2726               && INTVAL (XEXP (*split, 1)) > 0
2727               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2728             {
2729               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2730                                              XEXP (*split, 0), GEN_INT (i)));
2731               /* Update split_code because we may not have a multiply
2732                  anymore.  */
2733               split_code = GET_CODE (*split);
2734             }
2735
2736 #ifdef INSN_SCHEDULING
2737           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2738              be written as a ZERO_EXTEND.  */
2739           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2740             {
2741 #ifdef LOAD_EXTEND_OP
2742               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2743                  what it really is.  */
2744               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2745                   == SIGN_EXTEND)
2746                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2747                                                     SUBREG_REG (*split)));
2748               else
2749 #endif
2750                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2751                                                     SUBREG_REG (*split)));
2752             }
2753 #endif
2754
2755           /* Attempt to split binary operators using arithmetic identities.  */
2756           if (BINARY_P (SET_SRC (newpat))
2757               && split_mode == GET_MODE (SET_SRC (newpat))
2758               && ! side_effects_p (SET_SRC (newpat)))
2759             {
2760               rtx setsrc = SET_SRC (newpat);
2761               enum machine_mode mode = GET_MODE (setsrc);
2762               enum rtx_code code = GET_CODE (setsrc);
2763               rtx src_op0 = XEXP (setsrc, 0);
2764               rtx src_op1 = XEXP (setsrc, 1);
2765
2766               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2767               if (rtx_equal_p (src_op0, src_op1))
2768                 {
2769                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2770                   SUBST (XEXP (setsrc, 0), newdest);
2771                   SUBST (XEXP (setsrc, 1), newdest);
2772                   subst_done = true;
2773                 }
2774               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2775               else if ((code == PLUS || code == MULT)
2776                        && GET_CODE (src_op0) == code
2777                        && GET_CODE (XEXP (src_op0, 0)) == code
2778                        && (INTEGRAL_MODE_P (mode)
2779                            || (FLOAT_MODE_P (mode)
2780                                && flag_unsafe_math_optimizations)))
2781                 {
2782                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2783                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2784                   rtx r = XEXP (src_op0, 1);
2785                   rtx s = src_op1;
2786
2787                   /* Split both "((X op Y) op X) op Y" and
2788                      "((X op Y) op Y) op X" as "T op T" where T is
2789                      "X op Y".  */
2790                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2791                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2792                     {
2793                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2794                                               XEXP (src_op0, 0));
2795                       SUBST (XEXP (setsrc, 0), newdest);
2796                       SUBST (XEXP (setsrc, 1), newdest);
2797                       subst_done = true;
2798                     }
2799                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2800                      T is "X op Y".  */
2801                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2802                     {
2803                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2804                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2805                       SUBST (XEXP (setsrc, 0), newdest);
2806                       SUBST (XEXP (setsrc, 1), newdest);
2807                       subst_done = true;
2808                     }
2809                 }
2810             }
2811
2812           if (!subst_done)
2813             {
2814               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2815               SUBST (*split, newdest);
2816             }
2817
2818           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2819
2820           /* recog_for_combine might have added CLOBBERs to newi2pat.
2821              Make sure NEWPAT does not depend on the clobbered regs.  */
2822           if (GET_CODE (newi2pat) == PARALLEL)
2823             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2824               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2825                 {
2826                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2827                   if (reg_overlap_mentioned_p (reg, newpat))
2828                     {
2829                       undo_all ();
2830                       return 0;
2831                     }
2832                 }
2833
2834           /* If the split point was a MULT and we didn't have one before,
2835              don't use one now.  */
2836           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2837             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2838         }
2839     }
2840
2841   /* Check for a case where we loaded from memory in a narrow mode and
2842      then sign extended it, but we need both registers.  In that case,
2843      we have a PARALLEL with both loads from the same memory location.
2844      We can split this into a load from memory followed by a register-register
2845      copy.  This saves at least one insn, more if register allocation can
2846      eliminate the copy.
2847
2848      We cannot do this if the destination of the first assignment is a
2849      condition code register or cc0.  We eliminate this case by making sure
2850      the SET_DEST and SET_SRC have the same mode.
2851
2852      We cannot do this if the destination of the second assignment is
2853      a register that we have already assumed is zero-extended.  Similarly
2854      for a SUBREG of such a register.  */
2855
2856   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2857            && GET_CODE (newpat) == PARALLEL
2858            && XVECLEN (newpat, 0) == 2
2859            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2860            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2861            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2862                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2863            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2864            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2865                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2866            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2867                                    INSN_CUID (i2))
2868            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2869            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2870            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2871                  (REG_P (temp)
2872                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2873                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2874                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2875                   && (reg_stat[REGNO (temp)].nonzero_bits
2876                       != GET_MODE_MASK (word_mode))))
2877            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2878                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2879                      (REG_P (temp)
2880                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2881                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2882                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2883                       && (reg_stat[REGNO (temp)].nonzero_bits
2884                           != GET_MODE_MASK (word_mode)))))
2885            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2886                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2887            && ! find_reg_note (i3, REG_UNUSED,
2888                                SET_DEST (XVECEXP (newpat, 0, 0))))
2889     {
2890       rtx ni2dest;
2891
2892       newi2pat = XVECEXP (newpat, 0, 0);
2893       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2894       newpat = XVECEXP (newpat, 0, 1);
2895       SUBST (SET_SRC (newpat),
2896              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2897       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2898
2899       if (i2_code_number >= 0)
2900         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2901
2902       if (insn_code_number >= 0)
2903         swap_i2i3 = 1;
2904     }
2905
2906   /* Similarly, check for a case where we have a PARALLEL of two independent
2907      SETs but we started with three insns.  In this case, we can do the sets
2908      as two separate insns.  This case occurs when some SET allows two
2909      other insns to combine, but the destination of that SET is still live.  */
2910
2911   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2912            && GET_CODE (newpat) == PARALLEL
2913            && XVECLEN (newpat, 0) == 2
2914            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2915            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2916            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2917            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2918            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2919            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2920            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2921                                    INSN_CUID (i2))
2922            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2923                                   XVECEXP (newpat, 0, 0))
2924            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2925                                   XVECEXP (newpat, 0, 1))
2926            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2927                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2928 #ifdef HAVE_cc0
2929            /* We cannot split the parallel into two sets if both sets
2930               reference cc0.  */
2931            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2932                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2933 #endif
2934            )
2935     {
2936       /* Normally, it doesn't matter which of the two is done first,
2937          but it does if one references cc0.  In that case, it has to
2938          be first.  */
2939 #ifdef HAVE_cc0
2940       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2941         {
2942           newi2pat = XVECEXP (newpat, 0, 0);
2943           newpat = XVECEXP (newpat, 0, 1);
2944         }
2945       else
2946 #endif
2947         {
2948           newi2pat = XVECEXP (newpat, 0, 1);
2949           newpat = XVECEXP (newpat, 0, 0);
2950         }
2951
2952       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2953
2954       if (i2_code_number >= 0)
2955         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2956     }
2957
2958   /* If it still isn't recognized, fail and change things back the way they
2959      were.  */
2960   if ((insn_code_number < 0
2961        /* Is the result a reasonable ASM_OPERANDS?  */
2962        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2963     {
2964       undo_all ();
2965       return 0;
2966     }
2967
2968   /* If we had to change another insn, make sure it is valid also.  */
2969   if (undobuf.other_insn)
2970     {
2971       rtx other_pat = PATTERN (undobuf.other_insn);
2972       rtx new_other_notes;
2973       rtx note, next;
2974
2975       CLEAR_HARD_REG_SET (newpat_used_regs);
2976
2977       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2978                                              &new_other_notes);
2979
2980       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2981         {
2982           undo_all ();
2983           return 0;
2984         }
2985
2986       PATTERN (undobuf.other_insn) = other_pat;
2987
2988       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2989          are still valid.  Then add any non-duplicate notes added by
2990          recog_for_combine.  */
2991       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2992         {
2993           next = XEXP (note, 1);
2994
2995           if (REG_NOTE_KIND (note) == REG_UNUSED
2996               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2997             {
2998               if (REG_P (XEXP (note, 0)))
2999                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
3000
3001               remove_note (undobuf.other_insn, note);
3002             }
3003         }
3004
3005       for (note = new_other_notes; note; note = XEXP (note, 1))
3006         if (REG_P (XEXP (note, 0)))
3007           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
3008
3009       distribute_notes (new_other_notes, undobuf.other_insn,
3010                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3011     }
3012 #ifdef HAVE_cc0
3013   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3014      they are adjacent to each other or not.  */
3015   {
3016     rtx p = prev_nonnote_insn (i3);
3017     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3018         && sets_cc0_p (newi2pat))
3019       {
3020         undo_all ();
3021         return 0;
3022       }
3023   }
3024 #endif
3025
3026   /* Only allow this combination if insn_rtx_costs reports that the
3027      replacement instructions are cheaper than the originals.  */
3028   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3029     {
3030       undo_all ();
3031       return 0;
3032     }
3033
3034   /* We now know that we can do this combination.  Merge the insns and
3035      update the status of registers and LOG_LINKS.  */
3036
3037   if (swap_i2i3)
3038     {
3039       rtx insn;
3040       rtx link;
3041       rtx ni2dest;
3042
3043       /* I3 now uses what used to be its destination and which is now
3044          I2's destination.  This requires us to do a few adjustments.  */
3045       PATTERN (i3) = newpat;
3046       adjust_for_new_dest (i3);
3047
3048       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3049          so we still will.
3050
3051          However, some later insn might be using I2's dest and have
3052          a LOG_LINK pointing at I3.  We must remove this link.
3053          The simplest way to remove the link is to point it at I1,
3054          which we know will be a NOTE.  */
3055
3056       /* newi2pat is usually a SET here; however, recog_for_combine might
3057          have added some clobbers.  */
3058       if (GET_CODE (newi2pat) == PARALLEL)
3059         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3060       else
3061         ni2dest = SET_DEST (newi2pat);
3062
3063       for (insn = NEXT_INSN (i3);
3064            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3065                     || insn != BB_HEAD (this_basic_block->next_bb));
3066            insn = NEXT_INSN (insn))
3067         {
3068           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3069             {
3070               for (link = LOG_LINKS (insn); link;
3071                    link = XEXP (link, 1))
3072                 if (XEXP (link, 0) == i3)
3073                   XEXP (link, 0) = i1;
3074
3075               break;
3076             }
3077         }
3078     }
3079
3080   {
3081     rtx i3notes, i2notes, i1notes = 0;
3082     rtx i3links, i2links, i1links = 0;
3083     rtx midnotes = 0;
3084     unsigned int regno;
3085     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3086        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3087        same as i3dest, in which case newi2pat may be setting i1dest.  */
3088     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3089                    || i2dest_in_i2src || i2dest_in_i1src
3090                    || !i2dest_killed
3091                    ? 0 : i2dest);
3092     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3093                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3094                    || !i1dest_killed
3095                    ? 0 : i1dest);
3096
3097     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3098        clear them.  */
3099     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3100     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3101     if (i1)
3102       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3103
3104     /* Ensure that we do not have something that should not be shared but
3105        occurs multiple times in the new insns.  Check this by first
3106        resetting all the `used' flags and then copying anything is shared.  */
3107
3108     reset_used_flags (i3notes);
3109     reset_used_flags (i2notes);
3110     reset_used_flags (i1notes);
3111     reset_used_flags (newpat);
3112     reset_used_flags (newi2pat);
3113     if (undobuf.other_insn)
3114       reset_used_flags (PATTERN (undobuf.other_insn));
3115
3116     i3notes = copy_rtx_if_shared (i3notes);
3117     i2notes = copy_rtx_if_shared (i2notes);
3118     i1notes = copy_rtx_if_shared (i1notes);
3119     newpat = copy_rtx_if_shared (newpat);
3120     newi2pat = copy_rtx_if_shared (newi2pat);
3121     if (undobuf.other_insn)
3122       reset_used_flags (PATTERN (undobuf.other_insn));
3123
3124     INSN_CODE (i3) = insn_code_number;
3125     PATTERN (i3) = newpat;
3126
3127     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3128       {
3129         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3130
3131         reset_used_flags (call_usage);
3132         call_usage = copy_rtx (call_usage);
3133
3134         if (substed_i2)
3135           replace_rtx (call_usage, i2dest, i2src);
3136
3137         if (substed_i1)
3138           replace_rtx (call_usage, i1dest, i1src);
3139
3140         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3141       }
3142
3143     if (undobuf.other_insn)
3144       INSN_CODE (undobuf.other_insn) = other_code_number;
3145
3146     /* We had one special case above where I2 had more than one set and
3147        we replaced a destination of one of those sets with the destination
3148        of I3.  In that case, we have to update LOG_LINKS of insns later
3149        in this basic block.  Note that this (expensive) case is rare.
3150
3151        Also, in this case, we must pretend that all REG_NOTEs for I2
3152        actually came from I3, so that REG_UNUSED notes from I2 will be
3153        properly handled.  */
3154
3155     if (i3_subst_into_i2)
3156       {
3157         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3158           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3159                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3160               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3161               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3162               && ! find_reg_note (i2, REG_UNUSED,
3163                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3164             for (temp = NEXT_INSN (i2);
3165                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3166                           || BB_HEAD (this_basic_block) != temp);
3167                  temp = NEXT_INSN (temp))
3168               if (temp != i3 && INSN_P (temp))
3169                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3170                   if (XEXP (link, 0) == i2)
3171                     XEXP (link, 0) = i3;
3172
3173         if (i3notes)
3174           {
3175             rtx link = i3notes;
3176             while (XEXP (link, 1))
3177               link = XEXP (link, 1);
3178             XEXP (link, 1) = i2notes;
3179           }
3180         else
3181           i3notes = i2notes;
3182         i2notes = 0;
3183       }
3184
3185     LOG_LINKS (i3) = 0;
3186     REG_NOTES (i3) = 0;
3187     LOG_LINKS (i2) = 0;
3188     REG_NOTES (i2) = 0;
3189
3190     if (newi2pat)
3191       {
3192         INSN_CODE (i2) = i2_code_number;
3193         PATTERN (i2) = newi2pat;
3194       }
3195     else
3196       SET_INSN_DELETED (i2);
3197
3198     if (i1)
3199       {
3200         LOG_LINKS (i1) = 0;
3201         REG_NOTES (i1) = 0;
3202         SET_INSN_DELETED (i1);
3203       }
3204
3205     /* Get death notes for everything that is now used in either I3 or
3206        I2 and used to die in a previous insn.  If we built two new
3207        patterns, move from I1 to I2 then I2 to I3 so that we get the
3208        proper movement on registers that I2 modifies.  */
3209
3210     if (newi2pat)
3211       {
3212         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3213         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3214       }
3215     else
3216       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3217                    i3, &midnotes);
3218
3219     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3220     if (i3notes)
3221       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3222                         elim_i2, elim_i1);
3223     if (i2notes)
3224       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3225                         elim_i2, elim_i1);
3226     if (i1notes)
3227       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3228                         elim_i2, elim_i1);
3229     if (midnotes)
3230       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3231                         elim_i2, elim_i1);
3232
3233     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3234        know these are REG_UNUSED and want them to go to the desired insn,
3235        so we always pass it as i3.  We have not counted the notes in
3236        reg_n_deaths yet, so we need to do so now.  */
3237
3238     if (newi2pat && new_i2_notes)
3239       {
3240         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3241           if (REG_P (XEXP (temp, 0)))
3242             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3243
3244         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3245       }
3246
3247     if (new_i3_notes)
3248       {
3249         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3250           if (REG_P (XEXP (temp, 0)))
3251             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3252
3253         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3254       }
3255
3256     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3257        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3258        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3259        in that case, it might delete I2.  Similarly for I2 and I1.
3260        Show an additional death due to the REG_DEAD note we make here.  If
3261        we discard it in distribute_notes, we will decrement it again.  */
3262
3263     if (i3dest_killed)
3264       {
3265         if (REG_P (i3dest_killed))
3266           REG_N_DEATHS (REGNO (i3dest_killed))++;
3267
3268         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3269           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3270                                                NULL_RTX),
3271                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3272         else
3273           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3274                                                NULL_RTX),
3275                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3276                             elim_i2, elim_i1);
3277       }
3278
3279     if (i2dest_in_i2src)
3280       {
3281         if (REG_P (i2dest))
3282           REG_N_DEATHS (REGNO (i2dest))++;
3283
3284         if (newi2pat && reg_set_p (i2dest, newi2pat))
3285           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3286                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3287         else
3288           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3289                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3290                             NULL_RTX, NULL_RTX);
3291       }
3292
3293     if (i1dest_in_i1src)
3294       {
3295         if (REG_P (i1dest))
3296           REG_N_DEATHS (REGNO (i1dest))++;
3297
3298         if (newi2pat && reg_set_p (i1dest, newi2pat))
3299           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3300                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3301         else
3302           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3303                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3304                             NULL_RTX, NULL_RTX);
3305       }
3306
3307     distribute_links (i3links);
3308     distribute_links (i2links);
3309     distribute_links (i1links);
3310
3311     if (REG_P (i2dest))
3312       {
3313         rtx link;
3314         rtx i2_insn = 0, i2_val = 0, set;
3315
3316         /* The insn that used to set this register doesn't exist, and
3317            this life of the register may not exist either.  See if one of
3318            I3's links points to an insn that sets I2DEST.  If it does,
3319            that is now the last known value for I2DEST. If we don't update
3320            this and I2 set the register to a value that depended on its old
3321            contents, we will get confused.  If this insn is used, thing
3322            will be set correctly in combine_instructions.  */
3323
3324         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3325           if ((set = single_set (XEXP (link, 0))) != 0
3326               && rtx_equal_p (i2dest, SET_DEST (set)))
3327             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3328
3329         record_value_for_reg (i2dest, i2_insn, i2_val);
3330
3331         /* If the reg formerly set in I2 died only once and that was in I3,
3332            zero its use count so it won't make `reload' do any work.  */
3333         if (! added_sets_2
3334             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3335             && ! i2dest_in_i2src)
3336           {
3337             regno = REGNO (i2dest);
3338             REG_N_SETS (regno)--;
3339           }
3340       }
3341
3342     if (i1 && REG_P (i1dest))
3343       {
3344         rtx link;
3345         rtx i1_insn = 0, i1_val = 0, set;
3346
3347         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3348           if ((set = single_set (XEXP (link, 0))) != 0
3349               && rtx_equal_p (i1dest, SET_DEST (set)))
3350             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3351
3352         record_value_for_reg (i1dest, i1_insn, i1_val);
3353
3354         regno = REGNO (i1dest);
3355         if (! added_sets_1 && ! i1dest_in_i1src)
3356           REG_N_SETS (regno)--;
3357       }
3358
3359     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3360        been made to this insn.  The order of
3361        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3362        can affect nonzero_bits of newpat */
3363     if (newi2pat)
3364       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3365     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3366
3367     /* Set new_direct_jump_p if a new return or simple jump instruction
3368        has been created.
3369
3370        If I3 is now an unconditional jump, ensure that it has a
3371        BARRIER following it since it may have initially been a
3372        conditional jump.  It may also be the last nonnote insn.  */
3373
3374     if (returnjump_p (i3) || any_uncondjump_p (i3))
3375       {
3376         *new_direct_jump_p = 1;
3377         mark_jump_label (PATTERN (i3), i3, 0);
3378
3379         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3380             || !BARRIER_P (temp))
3381           emit_barrier_after (i3);
3382       }
3383
3384     if (undobuf.other_insn != NULL_RTX
3385         && (returnjump_p (undobuf.other_insn)
3386             || any_uncondjump_p (undobuf.other_insn)))
3387       {
3388         *new_direct_jump_p = 1;
3389
3390         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3391             || !BARRIER_P (temp))
3392           emit_barrier_after (undobuf.other_insn);
3393       }
3394
3395     /* An NOOP jump does not need barrier, but it does need cleaning up
3396        of CFG.  */
3397     if (GET_CODE (newpat) == SET
3398         && SET_SRC (newpat) == pc_rtx
3399         && SET_DEST (newpat) == pc_rtx)
3400       *new_direct_jump_p = 1;
3401   }
3402
3403   combine_successes++;
3404   undo_commit ();
3405
3406   if (added_links_insn
3407       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3408       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3409     return added_links_insn;
3410   else
3411     return newi2pat ? i2 : i3;
3412 }
3413 \f
3414 /* Undo all the modifications recorded in undobuf.  */
3415
3416 static void
3417 undo_all (void)
3418 {
3419   struct undo *undo, *next;
3420
3421   for (undo = undobuf.undos; undo; undo = next)
3422     {
3423       next = undo->next;
3424       switch (undo->kind)
3425         {
3426         case UNDO_RTX:
3427           *undo->where.r = undo->old_contents.r;
3428           break;
3429         case UNDO_INT:
3430           *undo->where.i = undo->old_contents.i;
3431           break;
3432         case UNDO_MODE:
3433           PUT_MODE (*undo->where.r, undo->old_contents.m);
3434           break;
3435         default:
3436           gcc_unreachable ();
3437         }
3438
3439       undo->next = undobuf.frees;
3440       undobuf.frees = undo;
3441     }
3442
3443   undobuf.undos = 0;
3444 }
3445
3446 /* We've committed to accepting the changes we made.  Move all
3447    of the undos to the free list.  */
3448
3449 static void
3450 undo_commit (void)
3451 {
3452   struct undo *undo, *next;
3453
3454   for (undo = undobuf.undos; undo; undo = next)
3455     {
3456       next = undo->next;
3457       undo->next = undobuf.frees;
3458       undobuf.frees = undo;
3459     }
3460   undobuf.undos = 0;
3461 }
3462 \f
3463 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3464    where we have an arithmetic expression and return that point.  LOC will
3465    be inside INSN.
3466
3467    try_combine will call this function to see if an insn can be split into
3468    two insns.  */
3469
3470 static rtx *
3471 find_split_point (rtx *loc, rtx insn)
3472 {
3473   rtx x = *loc;
3474   enum rtx_code code = GET_CODE (x);
3475   rtx *split;
3476   unsigned HOST_WIDE_INT len = 0;
3477   HOST_WIDE_INT pos = 0;
3478   int unsignedp = 0;
3479   rtx inner = NULL_RTX;
3480
3481   /* First special-case some codes.  */
3482   switch (code)
3483     {
3484     case SUBREG:
3485 #ifdef INSN_SCHEDULING
3486       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3487          point.  */
3488       if (MEM_P (SUBREG_REG (x)))
3489         return loc;
3490 #endif
3491       return find_split_point (&SUBREG_REG (x), insn);
3492
3493     case MEM:
3494 #ifdef HAVE_lo_sum
3495       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3496          using LO_SUM and HIGH.  */
3497       if (GET_CODE (XEXP (x, 0)) == CONST
3498           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3499         {
3500           SUBST (XEXP (x, 0),
3501                  gen_rtx_LO_SUM (Pmode,
3502                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3503                                  XEXP (x, 0)));
3504           return &XEXP (XEXP (x, 0), 0);
3505         }
3506 #endif
3507
3508       /* If we have a PLUS whose second operand is a constant and the
3509          address is not valid, perhaps will can split it up using
3510          the machine-specific way to split large constants.  We use
3511          the first pseudo-reg (one of the virtual regs) as a placeholder;
3512          it will not remain in the result.  */
3513       if (GET_CODE (XEXP (x, 0)) == PLUS
3514           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3515           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3516         {
3517           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3518           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3519                                  subst_insn);
3520
3521           /* This should have produced two insns, each of which sets our
3522              placeholder.  If the source of the second is a valid address,
3523              we can make put both sources together and make a split point
3524              in the middle.  */
3525
3526           if (seq
3527               && NEXT_INSN (seq) != NULL_RTX
3528               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3529               && NONJUMP_INSN_P (seq)
3530               && GET_CODE (PATTERN (seq)) == SET
3531               && SET_DEST (PATTERN (seq)) == reg
3532               && ! reg_mentioned_p (reg,
3533                                     SET_SRC (PATTERN (seq)))
3534               && NONJUMP_INSN_P (NEXT_INSN (seq))
3535               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3536               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3537               && memory_address_p (GET_MODE (x),
3538                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3539             {
3540               rtx src1 = SET_SRC (PATTERN (seq));
3541               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3542
3543               /* Replace the placeholder in SRC2 with SRC1.  If we can
3544                  find where in SRC2 it was placed, that can become our
3545                  split point and we can replace this address with SRC2.
3546                  Just try two obvious places.  */
3547
3548               src2 = replace_rtx (src2, reg, src1);
3549               split = 0;
3550               if (XEXP (src2, 0) == src1)
3551                 split = &XEXP (src2, 0);
3552               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3553                        && XEXP (XEXP (src2, 0), 0) == src1)
3554                 split = &XEXP (XEXP (src2, 0), 0);
3555
3556               if (split)
3557                 {
3558                   SUBST (XEXP (x, 0), src2);
3559                   return split;
3560                 }
3561             }
3562
3563           /* If that didn't work, perhaps the first operand is complex and
3564              needs to be computed separately, so make a split point there.
3565              This will occur on machines that just support REG + CONST
3566              and have a constant moved through some previous computation.  */
3567
3568           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3569                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3570                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3571             return &XEXP (XEXP (x, 0), 0);
3572         }
3573       break;
3574
3575     case SET:
3576 #ifdef HAVE_cc0
3577       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3578          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3579          we need to put the operand into a register.  So split at that
3580          point.  */
3581
3582       if (SET_DEST (x) == cc0_rtx
3583           && GET_CODE (SET_SRC (x)) != COMPARE
3584           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3585           && !OBJECT_P (SET_SRC (x))
3586           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3587                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3588         return &SET_SRC (x);
3589 #endif
3590
3591       /* See if we can split SET_SRC as it stands.  */
3592       split = find_split_point (&SET_SRC (x), insn);
3593       if (split && split != &SET_SRC (x))
3594         return split;
3595
3596       /* See if we can split SET_DEST as it stands.  */
3597       split = find_split_point (&SET_DEST (x), insn);
3598       if (split && split != &SET_DEST (x))
3599         return split;
3600
3601       /* See if this is a bitfield assignment with everything constant.  If
3602          so, this is an IOR of an AND, so split it into that.  */
3603       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3604           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3605               <= HOST_BITS_PER_WIDE_INT)
3606           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3607           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3608           && GET_CODE (SET_SRC (x)) == CONST_INT
3609           && ((INTVAL (XEXP (SET_DEST (x), 1))
3610                + INTVAL (XEXP (SET_DEST (x), 2)))
3611               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3612           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3613         {
3614           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3615           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3616           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3617           rtx dest = XEXP (SET_DEST (x), 0);
3618           enum machine_mode mode = GET_MODE (dest);
3619           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3620           rtx or_mask;
3621
3622           if (BITS_BIG_ENDIAN)
3623             pos = GET_MODE_BITSIZE (mode) - len - pos;
3624
3625           or_mask = gen_int_mode (src << pos, mode);
3626           if (src == mask)
3627             SUBST (SET_SRC (x),
3628                    simplify_gen_binary (IOR, mode, dest, or_mask));
3629           else
3630             {
3631               rtx negmask = gen_int_mode (~(mask << pos), mode);
3632               SUBST (SET_SRC (x),
3633                      simplify_gen_binary (IOR, mode,
3634                                           simplify_gen_binary (AND, mode,
3635                                                                dest, negmask),
3636                                           or_mask));
3637             }
3638
3639           SUBST (SET_DEST (x), dest);
3640
3641           split = find_split_point (&SET_SRC (x), insn);
3642           if (split && split != &SET_SRC (x))
3643             return split;
3644         }
3645
3646       /* Otherwise, see if this is an operation that we can split into two.
3647          If so, try to split that.  */
3648       code = GET_CODE (SET_SRC (x));
3649
3650       switch (code)
3651         {
3652         case AND:
3653           /* If we are AND'ing with a large constant that is only a single
3654              bit and the result is only being used in a context where we
3655              need to know if it is zero or nonzero, replace it with a bit
3656              extraction.  This will avoid the large constant, which might
3657              have taken more than one insn to make.  If the constant were
3658              not a valid argument to the AND but took only one insn to make,
3659              this is no worse, but if it took more than one insn, it will
3660              be better.  */
3661
3662           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3663               && REG_P (XEXP (SET_SRC (x), 0))
3664               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3665               && REG_P (SET_DEST (x))
3666               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3667               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3668               && XEXP (*split, 0) == SET_DEST (x)
3669               && XEXP (*split, 1) == const0_rtx)
3670             {
3671               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3672                                                 XEXP (SET_SRC (x), 0),
3673                                                 pos, NULL_RTX, 1, 1, 0, 0);
3674               if (extraction != 0)
3675                 {
3676                   SUBST (SET_SRC (x), extraction);
3677                   return find_split_point (loc, insn);
3678                 }
3679             }
3680           break;
3681
3682         case NE:
3683           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3684              is known to be on, this can be converted into a NEG of a shift.  */
3685           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3686               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3687               && 1 <= (pos = exact_log2
3688                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3689                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3690             {
3691               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3692
3693               SUBST (SET_SRC (x),
3694                      gen_rtx_NEG (mode,
3695                                   gen_rtx_LSHIFTRT (mode,
3696                                                     XEXP (SET_SRC (x), 0),
3697                                                     GEN_INT (pos))));
3698
3699               split = find_split_point (&SET_SRC (x), insn);
3700               if (split && split != &SET_SRC (x))
3701                 return split;
3702             }
3703           break;
3704
3705         case SIGN_EXTEND:
3706           inner = XEXP (SET_SRC (x), 0);
3707
3708           /* We can't optimize if either mode is a partial integer
3709              mode as we don't know how many bits are significant
3710              in those modes.  */
3711           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3712               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3713             break;
3714
3715           pos = 0;
3716           len = GET_MODE_BITSIZE (GET_MODE (inner));
3717           unsignedp = 0;
3718           break;
3719
3720         case SIGN_EXTRACT:
3721         case ZERO_EXTRACT:
3722           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3723               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3724             {
3725               inner = XEXP (SET_SRC (x), 0);
3726               len = INTVAL (XEXP (SET_SRC (x), 1));
3727               pos = INTVAL (XEXP (SET_SRC (x), 2));
3728
3729               if (BITS_BIG_ENDIAN)
3730                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3731               unsignedp = (code == ZERO_EXTRACT);
3732             }
3733           break;
3734
3735         default:
3736           break;
3737         }
3738
3739       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3740         {
3741           enum machine_mode mode = GET_MODE (SET_SRC (x));
3742
3743           /* For unsigned, we have a choice of a shift followed by an
3744              AND or two shifts.  Use two shifts for field sizes where the
3745              constant might be too large.  We assume here that we can
3746              always at least get 8-bit constants in an AND insn, which is
3747              true for every current RISC.  */
3748
3749           if (unsignedp && len <= 8)
3750             {
3751               SUBST (SET_SRC (x),
3752                      gen_rtx_AND (mode,
3753                                   gen_rtx_LSHIFTRT
3754                                   (mode, gen_lowpart (mode, inner),
3755                                    GEN_INT (pos)),
3756                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3757
3758               split = find_split_point (&SET_SRC (x), insn);
3759               if (split && split != &SET_SRC (x))
3760                 return split;
3761             }
3762           else
3763             {
3764               SUBST (SET_SRC (x),
3765                      gen_rtx_fmt_ee
3766                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3767                       gen_rtx_ASHIFT (mode,
3768                                       gen_lowpart (mode, inner),
3769                                       GEN_INT (GET_MODE_BITSIZE (mode)
3770                                                - len - pos)),
3771                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3772
3773               split = find_split_point (&SET_SRC (x), insn);
3774               if (split && split != &SET_SRC (x))
3775                 return split;
3776             }
3777         }
3778
3779       /* See if this is a simple operation with a constant as the second
3780          operand.  It might be that this constant is out of range and hence
3781          could be used as a split point.  */
3782       if (BINARY_P (SET_SRC (x))
3783           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3784           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3785               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3786                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3787         return &XEXP (SET_SRC (x), 1);
3788
3789       /* Finally, see if this is a simple operation with its first operand
3790          not in a register.  The operation might require this operand in a
3791          register, so return it as a split point.  We can always do this
3792          because if the first operand were another operation, we would have
3793          already found it as a split point.  */
3794       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3795           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3796         return &XEXP (SET_SRC (x), 0);
3797
3798       return 0;
3799
3800     case AND:
3801     case IOR:
3802       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3803          it is better to write this as (not (ior A B)) so we can split it.
3804          Similarly for IOR.  */
3805       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3806         {
3807           SUBST (*loc,
3808                  gen_rtx_NOT (GET_MODE (x),
3809                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3810                                               GET_MODE (x),
3811                                               XEXP (XEXP (x, 0), 0),
3812                                               XEXP (XEXP (x, 1), 0))));
3813           return find_split_point (loc, insn);
3814         }
3815
3816       /* Many RISC machines have a large set of logical insns.  If the
3817          second operand is a NOT, put it first so we will try to split the
3818          other operand first.  */
3819       if (GET_CODE (XEXP (x, 1)) == NOT)
3820         {
3821           rtx tem = XEXP (x, 0);
3822           SUBST (XEXP (x, 0), XEXP (x, 1));
3823           SUBST (XEXP (x, 1), tem);
3824         }
3825       break;
3826
3827     default:
3828       break;
3829     }
3830
3831   /* Otherwise, select our actions depending on our rtx class.  */
3832   switch (GET_RTX_CLASS (code))
3833     {
3834     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3835     case RTX_TERNARY:
3836       split = find_split_point (&XEXP (x, 2), insn);
3837       if (split)
3838         return split;
3839       /* ... fall through ...  */
3840     case RTX_BIN_ARITH:
3841     case RTX_COMM_ARITH:
3842     case RTX_COMPARE:
3843     case RTX_COMM_COMPARE:
3844       split = find_split_point (&XEXP (x, 1), insn);
3845       if (split)
3846         return split;
3847       /* ... fall through ...  */
3848     case RTX_UNARY:
3849       /* Some machines have (and (shift ...) ...) insns.  If X is not
3850          an AND, but XEXP (X, 0) is, use it as our split point.  */
3851       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3852         return &XEXP (x, 0);
3853
3854       split = find_split_point (&XEXP (x, 0), insn);
3855       if (split)
3856         return split;
3857       return loc;
3858
3859     default:
3860       /* Otherwise, we don't have a split point.  */
3861       return 0;
3862     }
3863 }
3864 \f
3865 /* Throughout X, replace FROM with TO, and return the result.
3866    The result is TO if X is FROM;
3867    otherwise the result is X, but its contents may have been modified.
3868    If they were modified, a record was made in undobuf so that
3869    undo_all will (among other things) return X to its original state.
3870
3871    If the number of changes necessary is too much to record to undo,
3872    the excess changes are not made, so the result is invalid.
3873    The changes already made can still be undone.
3874    undobuf.num_undo is incremented for such changes, so by testing that
3875    the caller can tell whether the result is valid.
3876
3877    `n_occurrences' is incremented each time FROM is replaced.
3878
3879    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3880
3881    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3882    by copying if `n_occurrences' is nonzero.  */
3883
3884 static rtx
3885 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3886 {
3887   enum rtx_code code = GET_CODE (x);
3888   enum machine_mode op0_mode = VOIDmode;
3889   const char *fmt;
3890   int len, i;
3891   rtx new;
3892
3893 /* Two expressions are equal if they are identical copies of a shared
3894    RTX or if they are both registers with the same register number
3895    and mode.  */
3896
3897 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3898   ((X) == (Y)                                           \
3899    || (REG_P (X) && REG_P (Y)   \
3900        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3901
3902   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3903     {
3904       n_occurrences++;
3905       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3906     }
3907
3908   /* If X and FROM are the same register but different modes, they will
3909      not have been seen as equal above.  However, flow.c will make a
3910      LOG_LINKS entry for that case.  If we do nothing, we will try to
3911      rerecognize our original insn and, when it succeeds, we will
3912      delete the feeding insn, which is incorrect.
3913
3914      So force this insn not to match in this (rare) case.  */
3915   if (! in_dest && code == REG && REG_P (from)
3916       && REGNO (x) == REGNO (from))
3917     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3918
3919   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3920      of which may contain things that can be combined.  */
3921   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3922     return x;
3923
3924   /* It is possible to have a subexpression appear twice in the insn.
3925      Suppose that FROM is a register that appears within TO.
3926      Then, after that subexpression has been scanned once by `subst',
3927      the second time it is scanned, TO may be found.  If we were
3928      to scan TO here, we would find FROM within it and create a
3929      self-referent rtl structure which is completely wrong.  */
3930   if (COMBINE_RTX_EQUAL_P (x, to))
3931     return to;
3932
3933   /* Parallel asm_operands need special attention because all of the
3934      inputs are shared across the arms.  Furthermore, unsharing the
3935      rtl results in recognition failures.  Failure to handle this case
3936      specially can result in circular rtl.
3937
3938      Solve this by doing a normal pass across the first entry of the
3939      parallel, and only processing the SET_DESTs of the subsequent
3940      entries.  Ug.  */
3941
3942   if (code == PARALLEL
3943       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3944       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3945     {
3946       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3947
3948       /* If this substitution failed, this whole thing fails.  */
3949       if (GET_CODE (new) == CLOBBER
3950           && XEXP (new, 0) == const0_rtx)
3951         return new;
3952
3953       SUBST (XVECEXP (x, 0, 0), new);
3954
3955       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3956         {
3957           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3958
3959           if (!REG_P (dest)
3960               && GET_CODE (dest) != CC0
3961               && GET_CODE (dest) != PC)
3962             {
3963               new = subst (dest, from, to, 0, unique_copy);
3964
3965               /* If this substitution failed, this whole thing fails.  */
3966               if (GET_CODE (new) == CLOBBER
3967                   && XEXP (new, 0) == const0_rtx)
3968                 return new;
3969
3970               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3971             }
3972         }
3973     }
3974   else
3975     {
3976       len = GET_RTX_LENGTH (code);
3977       fmt = GET_RTX_FORMAT (code);
3978
3979       /* We don't need to process a SET_DEST that is a register, CC0,
3980          or PC, so set up to skip this common case.  All other cases
3981          where we want to suppress replacing something inside a
3982          SET_SRC are handled via the IN_DEST operand.  */
3983       if (code == SET
3984           && (REG_P (SET_DEST (x))
3985               || GET_CODE (SET_DEST (x)) == CC0
3986               || GET_CODE (SET_DEST (x)) == PC))
3987         fmt = "ie";
3988
3989       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3990          constant.  */
3991       if (fmt[0] == 'e')
3992         op0_mode = GET_MODE (XEXP (x, 0));
3993
3994       for (i = 0; i < len; i++)
3995         {
3996           if (fmt[i] == 'E')
3997             {
3998               int j;
3999               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4000                 {
4001                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4002                     {
4003                       new = (unique_copy && n_occurrences
4004                              ? copy_rtx (to) : to);
4005                       n_occurrences++;
4006                     }
4007                   else
4008                     {
4009                       new = subst (XVECEXP (x, i, j), from, to, 0,
4010                                    unique_copy);
4011
4012                       /* If this substitution failed, this whole thing
4013                          fails.  */
4014                       if (GET_CODE (new) == CLOBBER
4015                           && XEXP (new, 0) == const0_rtx)
4016                         return new;
4017                     }
4018
4019                   SUBST (XVECEXP (x, i, j), new);
4020                 }
4021             }
4022           else if (fmt[i] == 'e')
4023             {
4024               /* If this is a register being set, ignore it.  */
4025               new = XEXP (x, i);
4026               if (in_dest
4027                   && i == 0
4028                   && (((code == SUBREG || code == ZERO_EXTRACT)
4029                        && REG_P (new))
4030                       || code == STRICT_LOW_PART))
4031                 ;
4032
4033               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4034                 {
4035                   /* In general, don't install a subreg involving two
4036                      modes not tieable.  It can worsen register
4037                      allocation, and can even make invalid reload
4038                      insns, since the reg inside may need to be copied
4039                      from in the outside mode, and that may be invalid
4040                      if it is an fp reg copied in integer mode.
4041
4042                      We allow two exceptions to this: It is valid if
4043                      it is inside another SUBREG and the mode of that
4044                      SUBREG and the mode of the inside of TO is
4045                      tieable and it is valid if X is a SET that copies
4046                      FROM to CC0.  */
4047
4048                   if (GET_CODE (to) == SUBREG
4049                       && ! MODES_TIEABLE_P (GET_MODE (to),
4050                                             GET_MODE (SUBREG_REG (to)))
4051                       && ! (code == SUBREG
4052                             && MODES_TIEABLE_P (GET_MODE (x),
4053                                                 GET_MODE (SUBREG_REG (to))))
4054 #ifdef HAVE_cc0
4055                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4056 #endif
4057                       )
4058                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4059
4060 #ifdef CANNOT_CHANGE_MODE_CLASS
4061                   if (code == SUBREG
4062                       && REG_P (to)
4063                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4064                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4065                                                    GET_MODE (to),
4066                                                    GET_MODE (x)))
4067                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4068 #endif
4069
4070                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4071                   n_occurrences++;
4072                 }
4073               else
4074                 /* If we are in a SET_DEST, suppress most cases unless we
4075                    have gone inside a MEM, in which case we want to
4076                    simplify the address.  We assume here that things that
4077                    are actually part of the destination have their inner
4078                    parts in the first expression.  This is true for SUBREG,
4079                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4080                    things aside from REG and MEM that should appear in a
4081                    SET_DEST.  */
4082                 new = subst (XEXP (x, i), from, to,
4083                              (((in_dest
4084                                 && (code == SUBREG || code == STRICT_LOW_PART
4085                                     || code == ZERO_EXTRACT))
4086                                || code == SET)
4087                               && i == 0), unique_copy);
4088
4089               /* If we found that we will have to reject this combination,
4090                  indicate that by returning the CLOBBER ourselves, rather than
4091                  an expression containing it.  This will speed things up as
4092                  well as prevent accidents where two CLOBBERs are considered
4093                  to be equal, thus producing an incorrect simplification.  */
4094
4095               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4096                 return new;
4097
4098               if (GET_CODE (x) == SUBREG
4099                   && (GET_CODE (new) == CONST_INT
4100                       || GET_CODE (new) == CONST_DOUBLE))
4101                 {
4102                   enum machine_mode mode = GET_MODE (x);
4103
4104                   x = simplify_subreg (GET_MODE (x), new,
4105                                        GET_MODE (SUBREG_REG (x)),
4106                                        SUBREG_BYTE (x));
4107                   if (! x)
4108                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4109                 }
4110               else if (GET_CODE (new) == CONST_INT
4111                        && GET_CODE (x) == ZERO_EXTEND)
4112                 {
4113                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4114                                                 new, GET_MODE (XEXP (x, 0)));
4115                   gcc_assert (x);
4116                 }
4117               else
4118                 SUBST (XEXP (x, i), new);
4119             }
4120         }
4121     }
4122
4123   /* Try to simplify X.  If the simplification changed the code, it is likely
4124      that further simplification will help, so loop, but limit the number
4125      of repetitions that will be performed.  */
4126
4127   for (i = 0; i < 4; i++)
4128     {
4129       /* If X is sufficiently simple, don't bother trying to do anything
4130          with it.  */
4131       if (code != CONST_INT && code != REG && code != CLOBBER)
4132         x = combine_simplify_rtx (x, op0_mode, in_dest);
4133
4134       if (GET_CODE (x) == code)
4135         break;
4136
4137       code = GET_CODE (x);
4138
4139       /* We no longer know the original mode of operand 0 since we
4140          have changed the form of X)  */
4141       op0_mode = VOIDmode;
4142     }
4143
4144   return x;
4145 }
4146 \f
4147 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4148    outer level; call `subst' to simplify recursively.  Return the new
4149    expression.
4150
4151    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4152    if we are inside a SET_DEST.  */
4153
4154 static rtx
4155 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4156 {
4157   enum rtx_code code = GET_CODE (x);
4158   enum machine_mode mode = GET_MODE (x);
4159   rtx temp;
4160   int i;
4161
4162   /* If this is a commutative operation, put a constant last and a complex
4163      expression first.  We don't need to do this for comparisons here.  */
4164   if (COMMUTATIVE_ARITH_P (x)
4165       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4166     {
4167       temp = XEXP (x, 0);
4168       SUBST (XEXP (x, 0), XEXP (x, 1));
4169       SUBST (XEXP (x, 1), temp);
4170     }
4171
4172   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4173      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4174      things.  Check for cases where both arms are testing the same
4175      condition.
4176
4177      Don't do anything if all operands are very simple.  */
4178
4179   if ((BINARY_P (x)
4180        && ((!OBJECT_P (XEXP (x, 0))
4181             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4182                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4183            || (!OBJECT_P (XEXP (x, 1))
4184                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4185                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4186       || (UNARY_P (x)
4187           && (!OBJECT_P (XEXP (x, 0))
4188                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4189                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4190     {
4191       rtx cond, true_rtx, false_rtx;
4192
4193       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4194       if (cond != 0
4195           /* If everything is a comparison, what we have is highly unlikely
4196              to be simpler, so don't use it.  */
4197           && ! (COMPARISON_P (x)
4198                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4199         {
4200           rtx cop1 = const0_rtx;
4201           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4202
4203           if (cond_code == NE && COMPARISON_P (cond))
4204             return x;
4205
4206           /* Simplify the alternative arms; this may collapse the true and
4207              false arms to store-flag values.  Be careful to use copy_rtx
4208              here since true_rtx or false_rtx might share RTL with x as a
4209              result of the if_then_else_cond call above.  */
4210           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4211           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4212
4213           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4214              is unlikely to be simpler.  */
4215           if (general_operand (true_rtx, VOIDmode)
4216               && general_operand (false_rtx, VOIDmode))
4217             {
4218               enum rtx_code reversed;
4219
4220               /* Restarting if we generate a store-flag expression will cause
4221                  us to loop.  Just drop through in this case.  */
4222
4223               /* If the result values are STORE_FLAG_VALUE and zero, we can
4224                  just make the comparison operation.  */
4225               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4226                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4227                                              cond, cop1);
4228               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4229                        && ((reversed = reversed_comparison_code_parts
4230                                         (cond_code, cond, cop1, NULL))
4231                            != UNKNOWN))
4232                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4233                                              cond, cop1);
4234
4235               /* Likewise, we can make the negate of a comparison operation
4236                  if the result values are - STORE_FLAG_VALUE and zero.  */
4237               else if (GET_CODE (true_rtx) == CONST_INT
4238                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4239                        && false_rtx == const0_rtx)
4240                 x = simplify_gen_unary (NEG, mode,
4241                                         simplify_gen_relational (cond_code,
4242                                                                  mode, VOIDmode,
4243                                                                  cond, cop1),
4244                                         mode);
4245               else if (GET_CODE (false_rtx) == CONST_INT
4246                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4247                        && true_rtx == const0_rtx
4248                        && ((reversed = reversed_comparison_code_parts
4249                                         (cond_code, cond, cop1, NULL))
4250                            != UNKNOWN))
4251                 x = simplify_gen_unary (NEG, mode,
4252                                         simplify_gen_relational (reversed,
4253                                                                  mode, VOIDmode,
4254                                                                  cond, cop1),
4255                                         mode);
4256               else
4257                 return gen_rtx_IF_THEN_ELSE (mode,
4258                                              simplify_gen_relational (cond_code,
4259                                                                       mode,
4260                                                                       VOIDmode,
4261                                                                       cond,
4262                                                                       cop1),
4263                                              true_rtx, false_rtx);
4264
4265               code = GET_CODE (x);
4266               op0_mode = VOIDmode;
4267             }
4268         }
4269     }
4270
4271   /* Try to fold this expression in case we have constants that weren't
4272      present before.  */
4273   temp = 0;
4274   switch (GET_RTX_CLASS (code))
4275     {
4276     case RTX_UNARY:
4277       if (op0_mode == VOIDmode)
4278         op0_mode = GET_MODE (XEXP (x, 0));
4279       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4280       break;
4281     case RTX_COMPARE:
4282     case RTX_COMM_COMPARE:
4283       {
4284         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4285         if (cmp_mode == VOIDmode)
4286           {
4287             cmp_mode = GET_MODE (XEXP (x, 1));
4288             if (cmp_mode == VOIDmode)
4289               cmp_mode = op0_mode;
4290           }
4291         temp = simplify_relational_operation (code, mode, cmp_mode,
4292                                               XEXP (x, 0), XEXP (x, 1));
4293       }
4294       break;
4295     case RTX_COMM_ARITH:
4296     case RTX_BIN_ARITH:
4297       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4298       break;
4299     case RTX_BITFIELD_OPS:
4300     case RTX_TERNARY:
4301       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4302                                          XEXP (x, 1), XEXP (x, 2));
4303       break;
4304     default:
4305       break;
4306     }
4307
4308   if (temp)
4309     {
4310       x = temp;
4311       code = GET_CODE (temp);
4312       op0_mode = VOIDmode;
4313       mode = GET_MODE (temp);
4314     }
4315
4316   /* First see if we can apply the inverse distributive law.  */
4317   if (code == PLUS || code == MINUS
4318       || code == AND || code == IOR || code == XOR)
4319     {
4320       x = apply_distributive_law (x);
4321       code = GET_CODE (x);
4322       op0_mode = VOIDmode;
4323     }
4324
4325   /* If CODE is an associative operation not otherwise handled, see if we
4326      can associate some operands.  This can win if they are constants or
4327      if they are logically related (i.e. (a & b) & a).  */
4328   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4329        || code == AND || code == IOR || code == XOR
4330        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4331       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4332           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4333     {
4334       if (GET_CODE (XEXP (x, 0)) == code)
4335         {
4336           rtx other = XEXP (XEXP (x, 0), 0);
4337           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4338           rtx inner_op1 = XEXP (x, 1);
4339           rtx inner;
4340
4341           /* Make sure we pass the constant operand if any as the second
4342              one if this is a commutative operation.  */
4343           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4344             {
4345               rtx tem = inner_op0;
4346               inner_op0 = inner_op1;
4347               inner_op1 = tem;
4348             }
4349           inner = simplify_binary_operation (code == MINUS ? PLUS
4350                                              : code == DIV ? MULT
4351                                              : code,
4352                                              mode, inner_op0, inner_op1);
4353
4354           /* For commutative operations, try the other pair if that one
4355              didn't simplify.  */
4356           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4357             {
4358               other = XEXP (XEXP (x, 0), 1);
4359               inner = simplify_binary_operation (code, mode,
4360                                                  XEXP (XEXP (x, 0), 0),
4361                                                  XEXP (x, 1));
4362             }
4363
4364           if (inner)
4365             return simplify_gen_binary (code, mode, other, inner);
4366         }
4367     }
4368
4369   /* A little bit of algebraic simplification here.  */
4370   switch (code)
4371     {
4372     case MEM:
4373       /* Ensure that our address has any ASHIFTs converted to MULT in case
4374          address-recognizing predicates are called later.  */
4375       temp = make_compound_operation (XEXP (x, 0), MEM);
4376       SUBST (XEXP (x, 0), temp);
4377       break;
4378
4379     case SUBREG:
4380       if (op0_mode == VOIDmode)
4381         op0_mode = GET_MODE (SUBREG_REG (x));
4382
4383       /* See if this can be moved to simplify_subreg.  */
4384       if (CONSTANT_P (SUBREG_REG (x))
4385           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4386              /* Don't call gen_lowpart if the inner mode
4387                 is VOIDmode and we cannot simplify it, as SUBREG without
4388                 inner mode is invalid.  */
4389           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4390               || gen_lowpart_common (mode, SUBREG_REG (x))))
4391         return gen_lowpart (mode, SUBREG_REG (x));
4392
4393       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4394         break;
4395       {
4396         rtx temp;
4397         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4398                                 SUBREG_BYTE (x));
4399         if (temp)
4400           return temp;
4401       }
4402
4403       /* Don't change the mode of the MEM if that would change the meaning
4404          of the address.  */
4405       if (MEM_P (SUBREG_REG (x))
4406           && (MEM_VOLATILE_P (SUBREG_REG (x))
4407               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4408         return gen_rtx_CLOBBER (mode, const0_rtx);
4409
4410       /* Note that we cannot do any narrowing for non-constants since
4411          we might have been counting on using the fact that some bits were
4412          zero.  We now do this in the SET.  */
4413
4414       break;
4415
4416     case NEG:
4417       temp = expand_compound_operation (XEXP (x, 0));
4418
4419       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4420          replaced by (lshiftrt X C).  This will convert
4421          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4422
4423       if (GET_CODE (temp) == ASHIFTRT
4424           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4425           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4426         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4427                                      INTVAL (XEXP (temp, 1)));
4428
4429       /* If X has only a single bit that might be nonzero, say, bit I, convert
4430          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4431          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4432          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4433          or a SUBREG of one since we'd be making the expression more
4434          complex if it was just a register.  */
4435
4436       if (!REG_P (temp)
4437           && ! (GET_CODE (temp) == SUBREG
4438                 && REG_P (SUBREG_REG (temp)))
4439           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4440         {
4441           rtx temp1 = simplify_shift_const
4442             (NULL_RTX, ASHIFTRT, mode,
4443              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4444                                    GET_MODE_BITSIZE (mode) - 1 - i),
4445              GET_MODE_BITSIZE (mode) - 1 - i);
4446
4447           /* If all we did was surround TEMP with the two shifts, we
4448              haven't improved anything, so don't use it.  Otherwise,
4449              we are better off with TEMP1.  */
4450           if (GET_CODE (temp1) != ASHIFTRT
4451               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4452               || XEXP (XEXP (temp1, 0), 0) != temp)
4453             return temp1;
4454         }
4455       break;
4456
4457     case TRUNCATE:
4458       /* We can't handle truncation to a partial integer mode here
4459          because we don't know the real bitsize of the partial
4460          integer mode.  */
4461       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4462         break;
4463
4464       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4465           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4466                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4467         SUBST (XEXP (x, 0),
4468                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4469                               GET_MODE_MASK (mode), 0));
4470
4471       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4472          whose value is a comparison can be replaced with a subreg if
4473          STORE_FLAG_VALUE permits.  */
4474       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4475           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4476           && (temp = get_last_value (XEXP (x, 0)))
4477           && COMPARISON_P (temp))
4478         return gen_lowpart (mode, XEXP (x, 0));
4479       break;
4480
4481 #ifdef HAVE_cc0
4482     case COMPARE:
4483       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4484          using cc0, in which case we want to leave it as a COMPARE
4485          so we can distinguish it from a register-register-copy.  */
4486       if (XEXP (x, 1) == const0_rtx)
4487         return XEXP (x, 0);
4488
4489       /* x - 0 is the same as x unless x's mode has signed zeros and
4490          allows rounding towards -infinity.  Under those conditions,
4491          0 - 0 is -0.  */
4492       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4493             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4494           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4495         return XEXP (x, 0);
4496       break;
4497 #endif
4498
4499     case CONST:
4500       /* (const (const X)) can become (const X).  Do it this way rather than
4501          returning the inner CONST since CONST can be shared with a
4502          REG_EQUAL note.  */
4503       if (GET_CODE (XEXP (x, 0)) == CONST)
4504         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4505       break;
4506
4507 #ifdef HAVE_lo_sum
4508     case LO_SUM:
4509       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4510          can add in an offset.  find_split_point will split this address up
4511          again if it doesn't match.  */
4512       if (GET_CODE (XEXP (x, 0)) == HIGH
4513           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4514         return XEXP (x, 1);
4515       break;
4516 #endif
4517
4518     case PLUS:
4519       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4520          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4521          bit-field and can be replaced by either a sign_extend or a
4522          sign_extract.  The `and' may be a zero_extend and the two
4523          <c>, -<c> constants may be reversed.  */
4524       if (GET_CODE (XEXP (x, 0)) == XOR
4525           && GET_CODE (XEXP (x, 1)) == CONST_INT
4526           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4527           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4528           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4529               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4530           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4531           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4532                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4533                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4534                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4535               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4536                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4537                       == (unsigned int) i + 1))))
4538         return simplify_shift_const
4539           (NULL_RTX, ASHIFTRT, mode,
4540            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4541                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4542                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4543            GET_MODE_BITSIZE (mode) - (i + 1));
4544
4545       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4546          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4547          the bitsize of the mode - 1.  This allows simplification of
4548          "a = (b & 8) == 0;"  */
4549       if (XEXP (x, 1) == constm1_rtx
4550           && !REG_P (XEXP (x, 0))
4551           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4552                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4553           && nonzero_bits (XEXP (x, 0), mode) == 1)
4554         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4555            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4556                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4557                                  GET_MODE_BITSIZE (mode) - 1),
4558            GET_MODE_BITSIZE (mode) - 1);
4559
4560       /* If we are adding two things that have no bits in common, convert
4561          the addition into an IOR.  This will often be further simplified,
4562          for example in cases like ((a & 1) + (a & 2)), which can
4563          become a & 3.  */
4564
4565       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4566           && (nonzero_bits (XEXP (x, 0), mode)
4567               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4568         {
4569           /* Try to simplify the expression further.  */
4570           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4571           temp = combine_simplify_rtx (tor, mode, in_dest);
4572
4573           /* If we could, great.  If not, do not go ahead with the IOR
4574              replacement, since PLUS appears in many special purpose
4575              address arithmetic instructions.  */
4576           if (GET_CODE (temp) != CLOBBER && temp != tor)
4577             return temp;
4578         }
4579       break;
4580
4581     case MINUS:
4582       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4583          (and <foo> (const_int pow2-1))  */
4584       if (GET_CODE (XEXP (x, 1)) == AND
4585           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4586           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4587           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4588         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4589                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4590       break;
4591
4592     case MULT:
4593       /* If we have (mult (plus A B) C), apply the distributive law and then
4594          the inverse distributive law to see if things simplify.  This
4595          occurs mostly in addresses, often when unrolling loops.  */
4596
4597       if (GET_CODE (XEXP (x, 0)) == PLUS)
4598         {
4599           rtx result = distribute_and_simplify_rtx (x, 0);
4600           if (result)
4601             return result;
4602         }
4603
4604       /* Try simplify a*(b/c) as (a*b)/c.  */
4605       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4606           && GET_CODE (XEXP (x, 0)) == DIV)
4607         {
4608           rtx tem = simplify_binary_operation (MULT, mode,
4609                                                XEXP (XEXP (x, 0), 0),
4610                                                XEXP (x, 1));
4611           if (tem)
4612             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4613         }
4614       break;
4615
4616     case UDIV:
4617       /* If this is a divide by a power of two, treat it as a shift if
4618          its first operand is a shift.  */
4619       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4620           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4621           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4622               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4623               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4624               || GET_CODE (XEXP (x, 0)) == ROTATE
4625               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4626         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4627       break;
4628
4629     case EQ:  case NE:
4630     case GT:  case GTU:  case GE:  case GEU:
4631     case LT:  case LTU:  case LE:  case LEU:
4632     case UNEQ:  case LTGT:
4633     case UNGT:  case UNGE:
4634     case UNLT:  case UNLE:
4635     case UNORDERED: case ORDERED:
4636       /* If the first operand is a condition code, we can't do anything
4637          with it.  */
4638       if (GET_CODE (XEXP (x, 0)) == COMPARE
4639           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4640               && ! CC0_P (XEXP (x, 0))))
4641         {
4642           rtx op0 = XEXP (x, 0);
4643           rtx op1 = XEXP (x, 1);
4644           enum rtx_code new_code;
4645
4646           if (GET_CODE (op0) == COMPARE)
4647             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4648
4649           /* Simplify our comparison, if possible.  */
4650           new_code = simplify_comparison (code, &op0, &op1);
4651
4652           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4653              if only the low-order bit is possibly nonzero in X (such as when
4654              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4655              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4656              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4657              (plus X 1).
4658
4659              Remove any ZERO_EXTRACT we made when thinking this was a
4660              comparison.  It may now be simpler to use, e.g., an AND.  If a
4661              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4662              the call to make_compound_operation in the SET case.  */
4663
4664           if (STORE_FLAG_VALUE == 1
4665               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4666               && op1 == const0_rtx
4667               && mode == GET_MODE (op0)
4668               && nonzero_bits (op0, mode) == 1)
4669             return gen_lowpart (mode,
4670                                 expand_compound_operation (op0));
4671
4672           else if (STORE_FLAG_VALUE == 1
4673                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4674                    && op1 == const0_rtx
4675                    && mode == GET_MODE (op0)
4676                    && (num_sign_bit_copies (op0, mode)
4677                        == GET_MODE_BITSIZE (mode)))
4678             {
4679               op0 = expand_compound_operation (op0);
4680               return simplify_gen_unary (NEG, mode,
4681                                          gen_lowpart (mode, op0),
4682                                          mode);
4683             }
4684
4685           else if (STORE_FLAG_VALUE == 1
4686                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4687                    && op1 == const0_rtx
4688                    && mode == GET_MODE (op0)
4689                    && nonzero_bits (op0, mode) == 1)
4690             {
4691               op0 = expand_compound_operation (op0);
4692               return simplify_gen_binary (XOR, mode,
4693                                           gen_lowpart (mode, op0),
4694                                           const1_rtx);
4695             }
4696
4697           else if (STORE_FLAG_VALUE == 1
4698                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4699                    && op1 == const0_rtx
4700                    && mode == GET_MODE (op0)
4701                    && (num_sign_bit_copies (op0, mode)
4702                        == GET_MODE_BITSIZE (mode)))
4703             {
4704               op0 = expand_compound_operation (op0);
4705               return plus_constant (gen_lowpart (mode, op0), 1);
4706             }
4707
4708           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4709              those above.  */
4710           if (STORE_FLAG_VALUE == -1
4711               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4712               && op1 == const0_rtx
4713               && (num_sign_bit_copies (op0, mode)
4714                   == GET_MODE_BITSIZE (mode)))
4715             return gen_lowpart (mode,
4716                                 expand_compound_operation (op0));
4717
4718           else if (STORE_FLAG_VALUE == -1
4719                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4720                    && op1 == const0_rtx
4721                    && mode == GET_MODE (op0)
4722                    && nonzero_bits (op0, mode) == 1)
4723             {
4724               op0 = expand_compound_operation (op0);
4725               return simplify_gen_unary (NEG, mode,
4726                                          gen_lowpart (mode, op0),
4727                                          mode);
4728             }
4729
4730           else if (STORE_FLAG_VALUE == -1
4731                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4732                    && op1 == const0_rtx
4733                    && mode == GET_MODE (op0)
4734                    && (num_sign_bit_copies (op0, mode)
4735                        == GET_MODE_BITSIZE (mode)))
4736             {
4737               op0 = expand_compound_operation (op0);
4738               return simplify_gen_unary (NOT, mode,
4739                                          gen_lowpart (mode, op0),
4740                                          mode);
4741             }
4742
4743           /* If X is 0/1, (eq X 0) is X-1.  */
4744           else if (STORE_FLAG_VALUE == -1
4745                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4746                    && op1 == const0_rtx
4747                    && mode == GET_MODE (op0)
4748                    && nonzero_bits (op0, mode) == 1)
4749             {
4750               op0 = expand_compound_operation (op0);
4751               return plus_constant (gen_lowpart (mode, op0), -1);
4752             }
4753
4754           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4755              one bit that might be nonzero, we can convert (ne x 0) to
4756              (ashift x c) where C puts the bit in the sign bit.  Remove any
4757              AND with STORE_FLAG_VALUE when we are done, since we are only
4758              going to test the sign bit.  */
4759           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4760               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4761               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4762                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4763               && op1 == const0_rtx
4764               && mode == GET_MODE (op0)
4765               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4766             {
4767               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4768                                         expand_compound_operation (op0),
4769                                         GET_MODE_BITSIZE (mode) - 1 - i);
4770               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4771                 return XEXP (x, 0);
4772               else
4773                 return x;
4774             }
4775
4776           /* If the code changed, return a whole new comparison.  */
4777           if (new_code != code)
4778             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4779
4780           /* Otherwise, keep this operation, but maybe change its operands.
4781              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4782           SUBST (XEXP (x, 0), op0);
4783           SUBST (XEXP (x, 1), op1);
4784         }
4785       break;
4786
4787     case IF_THEN_ELSE:
4788       return simplify_if_then_else (x);
4789
4790     case ZERO_EXTRACT:
4791     case SIGN_EXTRACT:
4792     case ZERO_EXTEND:
4793     case SIGN_EXTEND:
4794       /* If we are processing SET_DEST, we are done.  */
4795       if (in_dest)
4796         return x;
4797
4798       return expand_compound_operation (x);
4799
4800     case SET:
4801       return simplify_set (x);
4802
4803     case AND:
4804     case IOR:
4805       return simplify_logical (x);
4806
4807     case ASHIFT:
4808     case LSHIFTRT:
4809     case ASHIFTRT:
4810     case ROTATE:
4811     case ROTATERT:
4812       /* If this is a shift by a constant amount, simplify it.  */
4813       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4814         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4815                                      INTVAL (XEXP (x, 1)));
4816
4817       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4818         SUBST (XEXP (x, 1),
4819                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4820                               ((HOST_WIDE_INT) 1
4821                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4822                               - 1,
4823                               0));
4824       break;
4825
4826     default:
4827       break;
4828     }
4829
4830   return x;
4831 }
4832 \f
4833 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4834
4835 static rtx
4836 simplify_if_then_else (rtx x)
4837 {
4838   enum machine_mode mode = GET_MODE (x);
4839   rtx cond = XEXP (x, 0);
4840   rtx true_rtx = XEXP (x, 1);
4841   rtx false_rtx = XEXP (x, 2);
4842   enum rtx_code true_code = GET_CODE (cond);
4843   int comparison_p = COMPARISON_P (cond);
4844   rtx temp;
4845   int i;
4846   enum rtx_code false_code;
4847   rtx reversed;
4848
4849   /* Simplify storing of the truth value.  */
4850   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4851     return simplify_gen_relational (true_code, mode, VOIDmode,
4852                                     XEXP (cond, 0), XEXP (cond, 1));
4853
4854   /* Also when the truth value has to be reversed.  */
4855   if (comparison_p
4856       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4857       && (reversed = reversed_comparison (cond, mode)))
4858     return reversed;
4859
4860   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4861      in it is being compared against certain values.  Get the true and false
4862      comparisons and see if that says anything about the value of each arm.  */
4863
4864   if (comparison_p
4865       && ((false_code = reversed_comparison_code (cond, NULL))
4866           != UNKNOWN)
4867       && REG_P (XEXP (cond, 0)))
4868     {
4869       HOST_WIDE_INT nzb;
4870       rtx from = XEXP (cond, 0);
4871       rtx true_val = XEXP (cond, 1);
4872       rtx false_val = true_val;
4873       int swapped = 0;
4874
4875       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4876
4877       if (false_code == EQ)
4878         {
4879           swapped = 1, true_code = EQ, false_code = NE;
4880           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4881         }
4882
4883       /* If we are comparing against zero and the expression being tested has
4884          only a single bit that might be nonzero, that is its value when it is
4885          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4886
4887       if (true_code == EQ && true_val == const0_rtx
4888           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4889         false_code = EQ, false_val = GEN_INT (nzb);
4890       else if (true_code == EQ && true_val == const0_rtx
4891                && (num_sign_bit_copies (from, GET_MODE (from))
4892                    == GET_MODE_BITSIZE (GET_MODE (from))))
4893         false_code = EQ, false_val = constm1_rtx;
4894
4895       /* Now simplify an arm if we know the value of the register in the
4896          branch and it is used in the arm.  Be careful due to the potential
4897          of locally-shared RTL.  */
4898
4899       if (reg_mentioned_p (from, true_rtx))
4900         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4901                                       from, true_val),
4902                       pc_rtx, pc_rtx, 0, 0);
4903       if (reg_mentioned_p (from, false_rtx))
4904         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4905                                    from, false_val),
4906                        pc_rtx, pc_rtx, 0, 0);
4907
4908       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4909       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4910
4911       true_rtx = XEXP (x, 1);
4912       false_rtx = XEXP (x, 2);
4913       true_code = GET_CODE (cond);
4914     }
4915
4916   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4917      reversed, do so to avoid needing two sets of patterns for
4918      subtract-and-branch insns.  Similarly if we have a constant in the true
4919      arm, the false arm is the same as the first operand of the comparison, or
4920      the false arm is more complicated than the true arm.  */
4921
4922   if (comparison_p
4923       && reversed_comparison_code (cond, NULL) != UNKNOWN
4924       && (true_rtx == pc_rtx
4925           || (CONSTANT_P (true_rtx)
4926               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4927           || true_rtx == const0_rtx
4928           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4929           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4930               && !OBJECT_P (false_rtx))
4931           || reg_mentioned_p (true_rtx, false_rtx)
4932           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4933     {
4934       true_code = reversed_comparison_code (cond, NULL);
4935       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4936       SUBST (XEXP (x, 1), false_rtx);
4937       SUBST (XEXP (x, 2), true_rtx);
4938
4939       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4940       cond = XEXP (x, 0);
4941
4942       /* It is possible that the conditional has been simplified out.  */
4943       true_code = GET_CODE (cond);
4944       comparison_p = COMPARISON_P (cond);
4945     }
4946
4947   /* If the two arms are identical, we don't need the comparison.  */
4948
4949   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4950     return true_rtx;
4951
4952   /* Convert a == b ? b : a to "a".  */
4953   if (true_code == EQ && ! side_effects_p (cond)
4954       && !HONOR_NANS (mode)
4955       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4956       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4957     return false_rtx;
4958   else if (true_code == NE && ! side_effects_p (cond)
4959            && !HONOR_NANS (mode)
4960            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4961            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4962     return true_rtx;
4963
4964   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4965
4966   if (GET_MODE_CLASS (mode) == MODE_INT
4967       && GET_CODE (false_rtx) == NEG
4968       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4969       && comparison_p
4970       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4971       && ! side_effects_p (true_rtx))
4972     switch (true_code)
4973       {
4974       case GT:
4975       case GE:
4976         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4977       case LT:
4978       case LE:
4979         return
4980           simplify_gen_unary (NEG, mode,
4981                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4982                               mode);
4983       default:
4984         break;
4985       }
4986
4987   /* Look for MIN or MAX.  */
4988
4989   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4990       && comparison_p
4991       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4992       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4993       && ! side_effects_p (cond))
4994     switch (true_code)
4995       {
4996       case GE:
4997       case GT:
4998         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4999       case LE:
5000       case LT:
5001         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5002       case GEU:
5003       case GTU:
5004         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5005       case LEU:
5006       case LTU:
5007         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5008       default:
5009         break;
5010       }
5011
5012   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5013      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5014      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5015      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5016      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5017      neither 1 or -1, but it isn't worth checking for.  */
5018
5019   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5020       && comparison_p
5021       && GET_MODE_CLASS (mode) == MODE_INT
5022       && ! side_effects_p (x))
5023     {
5024       rtx t = make_compound_operation (true_rtx, SET);
5025       rtx f = make_compound_operation (false_rtx, SET);
5026       rtx cond_op0 = XEXP (cond, 0);
5027       rtx cond_op1 = XEXP (cond, 1);
5028       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5029       enum machine_mode m = mode;
5030       rtx z = 0, c1 = NULL_RTX;
5031
5032       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5033            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5034            || GET_CODE (t) == ASHIFT
5035            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5036           && rtx_equal_p (XEXP (t, 0), f))
5037         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5038
5039       /* If an identity-zero op is commutative, check whether there
5040          would be a match if we swapped the operands.  */
5041       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5042                 || GET_CODE (t) == XOR)
5043                && rtx_equal_p (XEXP (t, 1), f))
5044         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5045       else if (GET_CODE (t) == SIGN_EXTEND
5046                && (GET_CODE (XEXP (t, 0)) == PLUS
5047                    || GET_CODE (XEXP (t, 0)) == MINUS
5048                    || GET_CODE (XEXP (t, 0)) == IOR
5049                    || GET_CODE (XEXP (t, 0)) == XOR
5050                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5051                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5052                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5053                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5054                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5055                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5056                && (num_sign_bit_copies (f, GET_MODE (f))
5057                    > (unsigned int)
5058                      (GET_MODE_BITSIZE (mode)
5059                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5060         {
5061           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5062           extend_op = SIGN_EXTEND;
5063           m = GET_MODE (XEXP (t, 0));
5064         }
5065       else if (GET_CODE (t) == SIGN_EXTEND
5066                && (GET_CODE (XEXP (t, 0)) == PLUS
5067                    || GET_CODE (XEXP (t, 0)) == IOR
5068                    || GET_CODE (XEXP (t, 0)) == XOR)
5069                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5070                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5071                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5072                && (num_sign_bit_copies (f, GET_MODE (f))
5073                    > (unsigned int)
5074                      (GET_MODE_BITSIZE (mode)
5075                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5076         {
5077           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5078           extend_op = SIGN_EXTEND;
5079           m = GET_MODE (XEXP (t, 0));
5080         }
5081       else if (GET_CODE (t) == ZERO_EXTEND
5082                && (GET_CODE (XEXP (t, 0)) == PLUS
5083                    || GET_CODE (XEXP (t, 0)) == MINUS
5084                    || GET_CODE (XEXP (t, 0)) == IOR
5085                    || GET_CODE (XEXP (t, 0)) == XOR
5086                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5087                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5088                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5089                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5090                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5091                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5092                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5093                && ((nonzero_bits (f, GET_MODE (f))
5094                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5095                    == 0))
5096         {
5097           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5098           extend_op = ZERO_EXTEND;
5099           m = GET_MODE (XEXP (t, 0));
5100         }
5101       else if (GET_CODE (t) == ZERO_EXTEND
5102                && (GET_CODE (XEXP (t, 0)) == PLUS
5103                    || GET_CODE (XEXP (t, 0)) == IOR
5104                    || GET_CODE (XEXP (t, 0)) == XOR)
5105                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5106                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5107                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5108                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5109                && ((nonzero_bits (f, GET_MODE (f))
5110                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5111                    == 0))
5112         {
5113           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5114           extend_op = ZERO_EXTEND;
5115           m = GET_MODE (XEXP (t, 0));
5116         }
5117
5118       if (z)
5119         {
5120           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5121                                                  cond_op0, cond_op1),
5122                         pc_rtx, pc_rtx, 0, 0);
5123           temp = simplify_gen_binary (MULT, m, temp,
5124                                       simplify_gen_binary (MULT, m, c1,
5125                                                            const_true_rtx));
5126           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5127           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5128
5129           if (extend_op != UNKNOWN)
5130             temp = simplify_gen_unary (extend_op, mode, temp, m);
5131
5132           return temp;
5133         }
5134     }
5135
5136   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5137      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5138      negation of a single bit, we can convert this operation to a shift.  We
5139      can actually do this more generally, but it doesn't seem worth it.  */
5140
5141   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5142       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5143       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5144            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5145           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5146                == GET_MODE_BITSIZE (mode))
5147               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5148     return
5149       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5150                             gen_lowpart (mode, XEXP (cond, 0)), i);
5151
5152   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5153   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5154       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5155       && GET_MODE (XEXP (cond, 0)) == mode
5156       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5157           == nonzero_bits (XEXP (cond, 0), mode)
5158       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5159     return XEXP (cond, 0);
5160
5161   return x;
5162 }
5163 \f
5164 /* Simplify X, a SET expression.  Return the new expression.  */
5165
5166 static rtx
5167 simplify_set (rtx x)
5168 {
5169   rtx src = SET_SRC (x);
5170   rtx dest = SET_DEST (x);
5171   enum machine_mode mode
5172     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5173   rtx other_insn;
5174   rtx *cc_use;
5175
5176   /* (set (pc) (return)) gets written as (return).  */
5177   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5178     return src;
5179
5180   /* Now that we know for sure which bits of SRC we are using, see if we can
5181      simplify the expression for the object knowing that we only need the
5182      low-order bits.  */
5183
5184   if (GET_MODE_CLASS (mode) == MODE_INT
5185       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5186     {
5187       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5188       SUBST (SET_SRC (x), src);
5189     }
5190
5191   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5192      the comparison result and try to simplify it unless we already have used
5193      undobuf.other_insn.  */
5194   if ((GET_MODE_CLASS (mode) == MODE_CC
5195        || GET_CODE (src) == COMPARE
5196        || CC0_P (dest))
5197       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5198       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5199       && COMPARISON_P (*cc_use)
5200       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5201     {
5202       enum rtx_code old_code = GET_CODE (*cc_use);
5203       enum rtx_code new_code;
5204       rtx op0, op1, tmp;
5205       int other_changed = 0;
5206       enum machine_mode compare_mode = GET_MODE (dest);
5207
5208       if (GET_CODE (src) == COMPARE)
5209         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5210       else
5211         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5212
5213       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5214                                            op0, op1);
5215       if (!tmp)
5216         new_code = old_code;
5217       else if (!CONSTANT_P (tmp))
5218         {
5219           new_code = GET_CODE (tmp);
5220           op0 = XEXP (tmp, 0);
5221           op1 = XEXP (tmp, 1);
5222         }
5223       else
5224         {
5225           rtx pat = PATTERN (other_insn);
5226           undobuf.other_insn = other_insn;
5227           SUBST (*cc_use, tmp);
5228
5229           /* Attempt to simplify CC user.  */
5230           if (GET_CODE (pat) == SET)
5231             {
5232               rtx new = simplify_rtx (SET_SRC (pat));
5233               if (new != NULL_RTX)
5234                 SUBST (SET_SRC (pat), new);
5235             }
5236
5237           /* Convert X into a no-op move.  */
5238           SUBST (SET_DEST (x), pc_rtx);
5239           SUBST (SET_SRC (x), pc_rtx);
5240           return x;
5241         }
5242
5243       /* Simplify our comparison, if possible.  */
5244       new_code = simplify_comparison (new_code, &op0, &op1);
5245
5246 #ifdef SELECT_CC_MODE
5247       /* If this machine has CC modes other than CCmode, check to see if we
5248          need to use a different CC mode here.  */
5249       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5250         compare_mode = GET_MODE (op0);
5251       else
5252         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5253
5254 #ifndef HAVE_cc0
5255       /* If the mode changed, we have to change SET_DEST, the mode in the
5256          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5257          a hard register, just build new versions with the proper mode.  If it
5258          is a pseudo, we lose unless it is only time we set the pseudo, in
5259          which case we can safely change its mode.  */
5260       if (compare_mode != GET_MODE (dest))
5261         {
5262           if (can_change_dest_mode (dest, 0, compare_mode))
5263             {
5264               unsigned int regno = REGNO (dest);
5265               rtx new_dest;
5266
5267               if (regno < FIRST_PSEUDO_REGISTER)
5268                 new_dest = gen_rtx_REG (compare_mode, regno);
5269               else
5270                 {
5271                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5272                   new_dest = regno_reg_rtx[regno];
5273                 }
5274
5275               SUBST (SET_DEST (x), new_dest);
5276               SUBST (XEXP (*cc_use, 0), new_dest);
5277               other_changed = 1;
5278
5279               dest = new_dest;
5280             }
5281         }
5282 #endif  /* cc0 */
5283 #endif  /* SELECT_CC_MODE */
5284
5285       /* If the code changed, we have to build a new comparison in
5286          undobuf.other_insn.  */
5287       if (new_code != old_code)
5288         {
5289           int other_changed_previously = other_changed;
5290           unsigned HOST_WIDE_INT mask;
5291
5292           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5293                                           dest, const0_rtx));
5294           other_changed = 1;
5295
5296           /* If the only change we made was to change an EQ into an NE or
5297              vice versa, OP0 has only one bit that might be nonzero, and OP1
5298              is zero, check if changing the user of the condition code will
5299              produce a valid insn.  If it won't, we can keep the original code
5300              in that insn by surrounding our operation with an XOR.  */
5301
5302           if (((old_code == NE && new_code == EQ)
5303                || (old_code == EQ && new_code == NE))
5304               && ! other_changed_previously && op1 == const0_rtx
5305               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5306               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5307             {
5308               rtx pat = PATTERN (other_insn), note = 0;
5309
5310               if ((recog_for_combine (&pat, other_insn, &note) < 0
5311                    && ! check_asm_operands (pat)))
5312                 {
5313                   PUT_CODE (*cc_use, old_code);
5314                   other_changed = 0;
5315
5316                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5317                                              op0, GEN_INT (mask));
5318                 }
5319             }
5320         }
5321
5322       if (other_changed)
5323         undobuf.other_insn = other_insn;
5324
5325 #ifdef HAVE_cc0
5326       /* If we are now comparing against zero, change our source if
5327          needed.  If we do not use cc0, we always have a COMPARE.  */
5328       if (op1 == const0_rtx && dest == cc0_rtx)
5329         {
5330           SUBST (SET_SRC (x), op0);
5331           src = op0;
5332         }
5333       else
5334 #endif
5335
5336       /* Otherwise, if we didn't previously have a COMPARE in the
5337          correct mode, we need one.  */
5338       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5339         {
5340           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5341           src = SET_SRC (x);
5342         }
5343       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5344         {
5345           SUBST(SET_SRC (x), op0);
5346           src = SET_SRC (x);
5347         }
5348       else
5349         {
5350           /* Otherwise, update the COMPARE if needed.  */
5351           SUBST (XEXP (src, 0), op0);
5352           SUBST (XEXP (src, 1), op1);
5353         }
5354     }
5355   else
5356     {
5357       /* Get SET_SRC in a form where we have placed back any
5358          compound expressions.  Then do the checks below.  */
5359       src = make_compound_operation (src, SET);
5360       SUBST (SET_SRC (x), src);
5361     }
5362
5363   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5364      and X being a REG or (subreg (reg)), we may be able to convert this to
5365      (set (subreg:m2 x) (op)).
5366
5367      We can always do this if M1 is narrower than M2 because that means that
5368      we only care about the low bits of the result.
5369
5370      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5371      perform a narrower operation than requested since the high-order bits will
5372      be undefined.  On machine where it is defined, this transformation is safe
5373      as long as M1 and M2 have the same number of words.  */
5374
5375   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5376       && !OBJECT_P (SUBREG_REG (src))
5377       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5378            / UNITS_PER_WORD)
5379           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5380                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5381 #ifndef WORD_REGISTER_OPERATIONS
5382       && (GET_MODE_SIZE (GET_MODE (src))
5383         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5384 #endif
5385 #ifdef CANNOT_CHANGE_MODE_CLASS
5386       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5387             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5388                                          GET_MODE (SUBREG_REG (src)),
5389                                          GET_MODE (src)))
5390 #endif
5391       && (REG_P (dest)
5392           || (GET_CODE (dest) == SUBREG
5393               && REG_P (SUBREG_REG (dest)))))
5394     {
5395       SUBST (SET_DEST (x),
5396              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5397                                       dest));
5398       SUBST (SET_SRC (x), SUBREG_REG (src));
5399
5400       src = SET_SRC (x), dest = SET_DEST (x);
5401     }
5402
5403 #ifdef HAVE_cc0
5404   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5405      in SRC.  */
5406   if (dest == cc0_rtx
5407       && GET_CODE (src) == SUBREG
5408       && subreg_lowpart_p (src)
5409       && (GET_MODE_BITSIZE (GET_MODE (src))
5410           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5411     {
5412       rtx inner = SUBREG_REG (src);
5413       enum machine_mode inner_mode = GET_MODE (inner);
5414
5415       /* Here we make sure that we don't have a sign bit on.  */
5416       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5417           && (nonzero_bits (inner, inner_mode)
5418               < ((unsigned HOST_WIDE_INT) 1
5419                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5420         {
5421           SUBST (SET_SRC (x), inner);
5422           src = SET_SRC (x);
5423         }
5424     }
5425 #endif
5426
5427 #ifdef LOAD_EXTEND_OP
5428   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5429      would require a paradoxical subreg.  Replace the subreg with a
5430      zero_extend to avoid the reload that would otherwise be required.  */
5431
5432   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5433       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5434       && SUBREG_BYTE (src) == 0
5435       && (GET_MODE_SIZE (GET_MODE (src))
5436           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5437       && MEM_P (SUBREG_REG (src)))
5438     {
5439       SUBST (SET_SRC (x),
5440              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5441                             GET_MODE (src), SUBREG_REG (src)));
5442
5443       src = SET_SRC (x);
5444     }
5445 #endif
5446
5447   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5448      are comparing an item known to be 0 or -1 against 0, use a logical
5449      operation instead. Check for one of the arms being an IOR of the other
5450      arm with some value.  We compute three terms to be IOR'ed together.  In
5451      practice, at most two will be nonzero.  Then we do the IOR's.  */
5452
5453   if (GET_CODE (dest) != PC
5454       && GET_CODE (src) == IF_THEN_ELSE
5455       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5456       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5457       && XEXP (XEXP (src, 0), 1) == const0_rtx
5458       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5459 #ifdef HAVE_conditional_move
5460       && ! can_conditionally_move_p (GET_MODE (src))
5461 #endif
5462       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5463                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5464           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5465       && ! side_effects_p (src))
5466     {
5467       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5468                       ? XEXP (src, 1) : XEXP (src, 2));
5469       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5470                    ? XEXP (src, 2) : XEXP (src, 1));
5471       rtx term1 = const0_rtx, term2, term3;
5472
5473       if (GET_CODE (true_rtx) == IOR
5474           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5475         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5476       else if (GET_CODE (true_rtx) == IOR
5477                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5478         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5479       else if (GET_CODE (false_rtx) == IOR
5480                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5481         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5482       else if (GET_CODE (false_rtx) == IOR
5483                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5484         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5485
5486       term2 = simplify_gen_binary (AND, GET_MODE (src),
5487                                    XEXP (XEXP (src, 0), 0), true_rtx);
5488       term3 = simplify_gen_binary (AND, GET_MODE (src),
5489                                    simplify_gen_unary (NOT, GET_MODE (src),
5490                                                        XEXP (XEXP (src, 0), 0),
5491                                                        GET_MODE (src)),
5492                                    false_rtx);
5493
5494       SUBST (SET_SRC (x),
5495              simplify_gen_binary (IOR, GET_MODE (src),
5496                                   simplify_gen_binary (IOR, GET_MODE (src),
5497                                                        term1, term2),
5498                                   term3));
5499
5500       src = SET_SRC (x);
5501     }
5502
5503   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5504      whole thing fail.  */
5505   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5506     return src;
5507   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5508     return dest;
5509   else
5510     /* Convert this into a field assignment operation, if possible.  */
5511     return make_field_assignment (x);
5512 }
5513 \f
5514 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5515    result.  */
5516
5517 static rtx
5518 simplify_logical (rtx x)
5519 {
5520   enum machine_mode mode = GET_MODE (x);
5521   rtx op0 = XEXP (x, 0);
5522   rtx op1 = XEXP (x, 1);
5523
5524   switch (GET_CODE (x))
5525     {
5526     case AND:
5527       /* We can call simplify_and_const_int only if we don't lose
5528          any (sign) bits when converting INTVAL (op1) to
5529          "unsigned HOST_WIDE_INT".  */
5530       if (GET_CODE (op1) == CONST_INT
5531           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5532               || INTVAL (op1) > 0))
5533         {
5534           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5535           if (GET_CODE (x) != AND)
5536             return x;
5537
5538           op0 = XEXP (x, 0);
5539           op1 = XEXP (x, 1);
5540         }
5541
5542       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5543          apply the distributive law and then the inverse distributive
5544          law to see if things simplify.  */
5545       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5546         {
5547           rtx result = distribute_and_simplify_rtx (x, 0);
5548           if (result)
5549             return result;
5550         }
5551       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5552         {
5553           rtx result = distribute_and_simplify_rtx (x, 1);
5554           if (result)
5555             return result;
5556         }
5557       break;
5558
5559     case IOR:
5560       /* If we have (ior (and A B) C), apply the distributive law and then
5561          the inverse distributive law to see if things simplify.  */
5562
5563       if (GET_CODE (op0) == AND)
5564         {
5565           rtx result = distribute_and_simplify_rtx (x, 0);
5566           if (result)
5567             return result;
5568         }
5569
5570       if (GET_CODE (op1) == AND)
5571         {
5572           rtx result = distribute_and_simplify_rtx (x, 1);
5573           if (result)
5574             return result;
5575         }
5576       break;
5577
5578     default:
5579       gcc_unreachable ();
5580     }
5581
5582   return x;
5583 }
5584 \f
5585 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5586    operations" because they can be replaced with two more basic operations.
5587    ZERO_EXTEND is also considered "compound" because it can be replaced with
5588    an AND operation, which is simpler, though only one operation.
5589
5590    The function expand_compound_operation is called with an rtx expression
5591    and will convert it to the appropriate shifts and AND operations,
5592    simplifying at each stage.
5593
5594    The function make_compound_operation is called to convert an expression
5595    consisting of shifts and ANDs into the equivalent compound expression.
5596    It is the inverse of this function, loosely speaking.  */
5597
5598 static rtx
5599 expand_compound_operation (rtx x)
5600 {
5601   unsigned HOST_WIDE_INT pos = 0, len;
5602   int unsignedp = 0;
5603   unsigned int modewidth;
5604   rtx tem;
5605
5606   switch (GET_CODE (x))
5607     {
5608     case ZERO_EXTEND:
5609       unsignedp = 1;
5610     case SIGN_EXTEND:
5611       /* We can't necessarily use a const_int for a multiword mode;
5612          it depends on implicitly extending the value.
5613          Since we don't know the right way to extend it,
5614          we can't tell whether the implicit way is right.
5615
5616          Even for a mode that is no wider than a const_int,
5617          we can't win, because we need to sign extend one of its bits through
5618          the rest of it, and we don't know which bit.  */
5619       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5620         return x;
5621
5622       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5623          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5624          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5625          reloaded. If not for that, MEM's would very rarely be safe.
5626
5627          Reject MODEs bigger than a word, because we might not be able
5628          to reference a two-register group starting with an arbitrary register
5629          (and currently gen_lowpart might crash for a SUBREG).  */
5630
5631       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5632         return x;
5633
5634       /* Reject MODEs that aren't scalar integers because turning vector
5635          or complex modes into shifts causes problems.  */
5636
5637       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5638         return x;
5639
5640       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5641       /* If the inner object has VOIDmode (the only way this can happen
5642          is if it is an ASM_OPERANDS), we can't do anything since we don't
5643          know how much masking to do.  */
5644       if (len == 0)
5645         return x;
5646
5647       break;
5648
5649     case ZERO_EXTRACT:
5650       unsignedp = 1;
5651
5652       /* ... fall through ...  */
5653
5654     case SIGN_EXTRACT:
5655       /* If the operand is a CLOBBER, just return it.  */
5656       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5657         return XEXP (x, 0);
5658
5659       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5660           || GET_CODE (XEXP (x, 2)) != CONST_INT
5661           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5662         return x;
5663
5664       /* Reject MODEs that aren't scalar integers because turning vector
5665          or complex modes into shifts causes problems.  */
5666
5667       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5668         return x;
5669
5670       len = INTVAL (XEXP (x, 1));
5671       pos = INTVAL (XEXP (x, 2));
5672
5673       /* This should stay within the object being extracted, fail otherwise.  */
5674       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5675         return x;
5676
5677       if (BITS_BIG_ENDIAN)
5678         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5679
5680       break;
5681
5682     default:
5683       return x;
5684     }
5685   /* Convert sign extension to zero extension, if we know that the high
5686      bit is not set, as this is easier to optimize.  It will be converted
5687      back to cheaper alternative in make_extraction.  */
5688   if (GET_CODE (x) == SIGN_EXTEND
5689       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5690           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5691                 & ~(((unsigned HOST_WIDE_INT)
5692                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5693                      >> 1))
5694                == 0)))
5695     {
5696       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5697       rtx temp2 = expand_compound_operation (temp);
5698
5699       /* Make sure this is a profitable operation.  */
5700       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5701        return temp2;
5702       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5703        return temp;
5704       else
5705        return x;
5706     }
5707
5708   /* We can optimize some special cases of ZERO_EXTEND.  */
5709   if (GET_CODE (x) == ZERO_EXTEND)
5710     {
5711       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5712          know that the last value didn't have any inappropriate bits
5713          set.  */
5714       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5715           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5716           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5717           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5718               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5719         return XEXP (XEXP (x, 0), 0);
5720
5721       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5722       if (GET_CODE (XEXP (x, 0)) == SUBREG
5723           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5724           && subreg_lowpart_p (XEXP (x, 0))
5725           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5726           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5727               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5728         return SUBREG_REG (XEXP (x, 0));
5729
5730       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5731          is a comparison and STORE_FLAG_VALUE permits.  This is like
5732          the first case, but it works even when GET_MODE (x) is larger
5733          than HOST_WIDE_INT.  */
5734       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5735           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5736           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5737           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5738               <= HOST_BITS_PER_WIDE_INT)
5739           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5740               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5741         return XEXP (XEXP (x, 0), 0);
5742
5743       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5744       if (GET_CODE (XEXP (x, 0)) == SUBREG
5745           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5746           && subreg_lowpart_p (XEXP (x, 0))
5747           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5748           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5749               <= HOST_BITS_PER_WIDE_INT)
5750           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5751               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5752         return SUBREG_REG (XEXP (x, 0));
5753
5754     }
5755
5756   /* If we reach here, we want to return a pair of shifts.  The inner
5757      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5758      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5759      logical depending on the value of UNSIGNEDP.
5760
5761      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5762      converted into an AND of a shift.
5763
5764      We must check for the case where the left shift would have a negative
5765      count.  This can happen in a case like (x >> 31) & 255 on machines
5766      that can't shift by a constant.  On those machines, we would first
5767      combine the shift with the AND to produce a variable-position
5768      extraction.  Then the constant of 31 would be substituted in to produce
5769      a such a position.  */
5770
5771   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5772   if (modewidth + len >= pos)
5773     {
5774       enum machine_mode mode = GET_MODE (x);
5775       tem = gen_lowpart (mode, XEXP (x, 0));
5776       if (!tem || GET_CODE (tem) == CLOBBER)
5777         return x;
5778       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5779                                   tem, modewidth - pos - len);
5780       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5781                                   mode, tem, modewidth - len);
5782     }
5783   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5784     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5785                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5786                                                         GET_MODE (x),
5787                                                         XEXP (x, 0), pos),
5788                                   ((HOST_WIDE_INT) 1 << len) - 1);
5789   else
5790     /* Any other cases we can't handle.  */
5791     return x;
5792
5793   /* If we couldn't do this for some reason, return the original
5794      expression.  */
5795   if (GET_CODE (tem) == CLOBBER)
5796     return x;
5797
5798   return tem;
5799 }
5800 \f
5801 /* X is a SET which contains an assignment of one object into
5802    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5803    or certain SUBREGS). If possible, convert it into a series of
5804    logical operations.
5805
5806    We half-heartedly support variable positions, but do not at all
5807    support variable lengths.  */
5808
5809 static rtx
5810 expand_field_assignment (rtx x)
5811 {
5812   rtx inner;
5813   rtx pos;                      /* Always counts from low bit.  */
5814   int len;
5815   rtx mask, cleared, masked;
5816   enum machine_mode compute_mode;
5817
5818   /* Loop until we find something we can't simplify.  */
5819   while (1)
5820     {
5821       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5822           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5823         {
5824           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5825           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5826           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5827         }
5828       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5829                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5830         {
5831           inner = XEXP (SET_DEST (x), 0);
5832           len = INTVAL (XEXP (SET_DEST (x), 1));
5833           pos = XEXP (SET_DEST (x), 2);
5834
5835           /* A constant position should stay within the width of INNER.  */
5836           if (GET_CODE (pos) == CONST_INT
5837               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5838             break;
5839
5840           if (BITS_BIG_ENDIAN)
5841             {
5842               if (GET_CODE (pos) == CONST_INT)
5843                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5844                                - INTVAL (pos));
5845               else if (GET_CODE (pos) == MINUS
5846                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5847                        && (INTVAL (XEXP (pos, 1))
5848                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5849                 /* If position is ADJUST - X, new position is X.  */
5850                 pos = XEXP (pos, 0);
5851               else
5852                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5853                                            GEN_INT (GET_MODE_BITSIZE (
5854                                                     GET_MODE (inner))
5855                                                     - len),
5856                                            pos);
5857             }
5858         }
5859
5860       /* A SUBREG between two modes that occupy the same numbers of words
5861          can be done by moving the SUBREG to the source.  */
5862       else if (GET_CODE (SET_DEST (x)) == SUBREG
5863                /* We need SUBREGs to compute nonzero_bits properly.  */
5864                && nonzero_sign_valid
5865                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5866                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5867                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5868                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5869         {
5870           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5871                            gen_lowpart
5872                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5873                             SET_SRC (x)));
5874           continue;
5875         }
5876       else
5877         break;
5878
5879       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5880         inner = SUBREG_REG (inner);
5881
5882       compute_mode = GET_MODE (inner);
5883
5884       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5885       if (! SCALAR_INT_MODE_P (compute_mode))
5886         {
5887           enum machine_mode imode;
5888
5889           /* Don't do anything for vector or complex integral types.  */
5890           if (! FLOAT_MODE_P (compute_mode))
5891             break;
5892
5893           /* Try to find an integral mode to pun with.  */
5894           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5895           if (imode == BLKmode)
5896             break;
5897
5898           compute_mode = imode;
5899           inner = gen_lowpart (imode, inner);
5900         }
5901
5902       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5903       if (len >= HOST_BITS_PER_WIDE_INT)
5904         break;
5905
5906       /* Now compute the equivalent expression.  Make a copy of INNER
5907          for the SET_DEST in case it is a MEM into which we will substitute;
5908          we don't want shared RTL in that case.  */
5909       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5910       cleared = simplify_gen_binary (AND, compute_mode,
5911                                      simplify_gen_unary (NOT, compute_mode,
5912                                        simplify_gen_binary (ASHIFT,
5913                                                             compute_mode,
5914                                                             mask, pos),
5915                                        compute_mode),
5916                                      inner);
5917       masked = simplify_gen_binary (ASHIFT, compute_mode,
5918                                     simplify_gen_binary (
5919                                       AND, compute_mode,
5920                                       gen_lowpart (compute_mode, SET_SRC (x)),
5921                                       mask),
5922                                     pos);
5923
5924       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5925                        simplify_gen_binary (IOR, compute_mode,
5926                                             cleared, masked));
5927     }
5928
5929   return x;
5930 }
5931 \f
5932 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5933    it is an RTX that represents a variable starting position; otherwise,
5934    POS is the (constant) starting bit position (counted from the LSB).
5935
5936    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5937    signed reference.
5938
5939    IN_DEST is nonzero if this is a reference in the destination of a
5940    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5941    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5942    be used.
5943
5944    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5945    ZERO_EXTRACT should be built even for bits starting at bit 0.
5946
5947    MODE is the desired mode of the result (if IN_DEST == 0).
5948
5949    The result is an RTX for the extraction or NULL_RTX if the target
5950    can't handle it.  */
5951
5952 static rtx
5953 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5954                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5955                  int in_dest, int in_compare)
5956 {
5957   /* This mode describes the size of the storage area
5958      to fetch the overall value from.  Within that, we
5959      ignore the POS lowest bits, etc.  */
5960   enum machine_mode is_mode = GET_MODE (inner);
5961   enum machine_mode inner_mode;
5962   enum machine_mode wanted_inner_mode;
5963   enum machine_mode wanted_inner_reg_mode = word_mode;
5964   enum machine_mode pos_mode = word_mode;
5965   enum machine_mode extraction_mode = word_mode;
5966   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5967   rtx new = 0;
5968   rtx orig_pos_rtx = pos_rtx;
5969   HOST_WIDE_INT orig_pos;
5970
5971   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5972     {
5973       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5974          consider just the QI as the memory to extract from.
5975          The subreg adds or removes high bits; its mode is
5976          irrelevant to the meaning of this extraction,
5977          since POS and LEN count from the lsb.  */
5978       if (MEM_P (SUBREG_REG (inner)))
5979         is_mode = GET_MODE (SUBREG_REG (inner));
5980       inner = SUBREG_REG (inner);
5981     }
5982   else if (GET_CODE (inner) == ASHIFT
5983            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5984            && pos_rtx == 0 && pos == 0
5985            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5986     {
5987       /* We're extracting the least significant bits of an rtx
5988          (ashift X (const_int C)), where LEN > C.  Extract the
5989          least significant (LEN - C) bits of X, giving an rtx
5990          whose mode is MODE, then shift it left C times.  */
5991       new = make_extraction (mode, XEXP (inner, 0),
5992                              0, 0, len - INTVAL (XEXP (inner, 1)),
5993                              unsignedp, in_dest, in_compare);
5994       if (new != 0)
5995         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5996     }
5997
5998   inner_mode = GET_MODE (inner);
5999
6000   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6001     pos = INTVAL (pos_rtx), pos_rtx = 0;
6002
6003   /* See if this can be done without an extraction.  We never can if the
6004      width of the field is not the same as that of some integer mode. For
6005      registers, we can only avoid the extraction if the position is at the
6006      low-order bit and this is either not in the destination or we have the
6007      appropriate STRICT_LOW_PART operation available.
6008
6009      For MEM, we can avoid an extract if the field starts on an appropriate
6010      boundary and we can change the mode of the memory reference.  */
6011
6012   if (tmode != BLKmode
6013       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6014            && !MEM_P (inner)
6015            && (inner_mode == tmode
6016                || !REG_P (inner)
6017                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6018                                          GET_MODE_BITSIZE (inner_mode))
6019                || reg_truncated_to_mode (tmode, inner))
6020            && (! in_dest
6021                || (REG_P (inner)
6022                    && have_insn_for (STRICT_LOW_PART, tmode))))
6023           || (MEM_P (inner) && pos_rtx == 0
6024               && (pos
6025                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6026                      : BITS_PER_UNIT)) == 0
6027               /* We can't do this if we are widening INNER_MODE (it
6028                  may not be aligned, for one thing).  */
6029               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6030               && (inner_mode == tmode
6031                   || (! mode_dependent_address_p (XEXP (inner, 0))
6032                       && ! MEM_VOLATILE_P (inner))))))
6033     {
6034       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6035          field.  If the original and current mode are the same, we need not
6036          adjust the offset.  Otherwise, we do if bytes big endian.
6037
6038          If INNER is not a MEM, get a piece consisting of just the field
6039          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6040
6041       if (MEM_P (inner))
6042         {
6043           HOST_WIDE_INT offset;
6044
6045           /* POS counts from lsb, but make OFFSET count in memory order.  */
6046           if (BYTES_BIG_ENDIAN)
6047             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6048           else
6049             offset = pos / BITS_PER_UNIT;
6050
6051           new = adjust_address_nv (inner, tmode, offset);
6052         }
6053       else if (REG_P (inner))
6054         {
6055           if (tmode != inner_mode)
6056             {
6057               /* We can't call gen_lowpart in a DEST since we
6058                  always want a SUBREG (see below) and it would sometimes
6059                  return a new hard register.  */
6060               if (pos || in_dest)
6061                 {
6062                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6063
6064                   if (WORDS_BIG_ENDIAN
6065                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6066                     final_word = ((GET_MODE_SIZE (inner_mode)
6067                                    - GET_MODE_SIZE (tmode))
6068                                   / UNITS_PER_WORD) - final_word;
6069
6070                   final_word *= UNITS_PER_WORD;
6071                   if (BYTES_BIG_ENDIAN &&
6072                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6073                     final_word += (GET_MODE_SIZE (inner_mode)
6074                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6075
6076                   /* Avoid creating invalid subregs, for example when
6077                      simplifying (x>>32)&255.  */
6078                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6079                     return NULL_RTX;
6080
6081                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6082                 }
6083               else
6084                 new = gen_lowpart (tmode, inner);
6085             }
6086           else
6087             new = inner;
6088         }
6089       else
6090         new = force_to_mode (inner, tmode,
6091                              len >= HOST_BITS_PER_WIDE_INT
6092                              ? ~(unsigned HOST_WIDE_INT) 0
6093                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6094                              0);
6095
6096       /* If this extraction is going into the destination of a SET,
6097          make a STRICT_LOW_PART unless we made a MEM.  */
6098
6099       if (in_dest)
6100         return (MEM_P (new) ? new
6101                 : (GET_CODE (new) != SUBREG
6102                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6103                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6104
6105       if (mode == tmode)
6106         return new;
6107
6108       if (GET_CODE (new) == CONST_INT)
6109         return gen_int_mode (INTVAL (new), mode);
6110
6111       /* If we know that no extraneous bits are set, and that the high
6112          bit is not set, convert the extraction to the cheaper of
6113          sign and zero extension, that are equivalent in these cases.  */
6114       if (flag_expensive_optimizations
6115           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6116               && ((nonzero_bits (new, tmode)
6117                    & ~(((unsigned HOST_WIDE_INT)
6118                         GET_MODE_MASK (tmode))
6119                        >> 1))
6120                   == 0)))
6121         {
6122           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6123           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6124
6125           /* Prefer ZERO_EXTENSION, since it gives more information to
6126              backends.  */
6127           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6128             return temp;
6129           return temp1;
6130         }
6131
6132       /* Otherwise, sign- or zero-extend unless we already are in the
6133          proper mode.  */
6134
6135       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6136                              mode, new));
6137     }
6138
6139   /* Unless this is a COMPARE or we have a funny memory reference,
6140      don't do anything with zero-extending field extracts starting at
6141      the low-order bit since they are simple AND operations.  */
6142   if (pos_rtx == 0 && pos == 0 && ! in_dest
6143       && ! in_compare && unsignedp)
6144     return 0;
6145
6146   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6147      if the position is not a constant and the length is not 1.  In all
6148      other cases, we would only be going outside our object in cases when
6149      an original shift would have been undefined.  */
6150   if (MEM_P (inner)
6151       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6152           || (pos_rtx != 0 && len != 1)))
6153     return 0;
6154
6155   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6156      and the mode for the result.  */
6157   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6158     {
6159       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6160       pos_mode = mode_for_extraction (EP_insv, 2);
6161       extraction_mode = mode_for_extraction (EP_insv, 3);
6162     }
6163
6164   if (! in_dest && unsignedp
6165       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6166     {
6167       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6168       pos_mode = mode_for_extraction (EP_extzv, 3);
6169       extraction_mode = mode_for_extraction (EP_extzv, 0);
6170     }
6171
6172   if (! in_dest && ! unsignedp
6173       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6174     {
6175       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6176       pos_mode = mode_for_extraction (EP_extv, 3);
6177       extraction_mode = mode_for_extraction (EP_extv, 0);
6178     }
6179
6180   /* Never narrow an object, since that might not be safe.  */
6181
6182   if (mode != VOIDmode
6183       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6184     extraction_mode = mode;
6185
6186   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6187       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6188     pos_mode = GET_MODE (pos_rtx);
6189
6190   /* If this is not from memory, the desired mode is the preferred mode
6191      for an extraction pattern's first input operand, or word_mode if there
6192      is none.  */
6193   if (!MEM_P (inner))
6194     wanted_inner_mode = wanted_inner_reg_mode;
6195   else
6196     {
6197       /* Be careful not to go beyond the extracted object and maintain the
6198          natural alignment of the memory.  */
6199       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6200       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6201              > GET_MODE_BITSIZE (wanted_inner_mode))
6202         {
6203           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6204           gcc_assert (wanted_inner_mode != VOIDmode);
6205         }
6206
6207       /* If we have to change the mode of memory and cannot, the desired mode
6208          is EXTRACTION_MODE.  */
6209       if (inner_mode != wanted_inner_mode
6210           && (mode_dependent_address_p (XEXP (inner, 0))
6211               || MEM_VOLATILE_P (inner)
6212               || pos_rtx))
6213         wanted_inner_mode = extraction_mode;
6214     }
6215
6216   orig_pos = pos;
6217
6218   if (BITS_BIG_ENDIAN)
6219     {
6220       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6221          BITS_BIG_ENDIAN style.  If position is constant, compute new
6222          position.  Otherwise, build subtraction.
6223          Note that POS is relative to the mode of the original argument.
6224          If it's a MEM we need to recompute POS relative to that.
6225          However, if we're extracting from (or inserting into) a register,
6226          we want to recompute POS relative to wanted_inner_mode.  */
6227       int width = (MEM_P (inner)
6228                    ? GET_MODE_BITSIZE (is_mode)
6229                    : GET_MODE_BITSIZE (wanted_inner_mode));
6230
6231       if (pos_rtx == 0)
6232         pos = width - len - pos;
6233       else
6234         pos_rtx
6235           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6236       /* POS may be less than 0 now, but we check for that below.
6237          Note that it can only be less than 0 if !MEM_P (inner).  */
6238     }
6239
6240   /* If INNER has a wider mode, and this is a constant extraction, try to
6241      make it smaller and adjust the byte to point to the byte containing
6242      the value.  */
6243   if (wanted_inner_mode != VOIDmode
6244       && inner_mode != wanted_inner_mode
6245       && ! pos_rtx
6246       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6247       && MEM_P (inner)
6248       && ! mode_dependent_address_p (XEXP (inner, 0))
6249       && ! MEM_VOLATILE_P (inner))
6250     {
6251       int offset = 0;
6252
6253       /* The computations below will be correct if the machine is big
6254          endian in both bits and bytes or little endian in bits and bytes.
6255          If it is mixed, we must adjust.  */
6256
6257       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6258          adjust OFFSET to compensate.  */
6259       if (BYTES_BIG_ENDIAN
6260           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6261         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6262
6263       /* We can now move to the desired byte.  */
6264       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6265                 * GET_MODE_SIZE (wanted_inner_mode);
6266       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6267
6268       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6269           && is_mode != wanted_inner_mode)
6270         offset = (GET_MODE_SIZE (is_mode)
6271                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6272
6273       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6274     }
6275
6276   /* If INNER is not memory, we can always get it into the proper mode.  If we
6277      are changing its mode, POS must be a constant and smaller than the size
6278      of the new mode.  */
6279   else if (!MEM_P (inner))
6280     {
6281       if (GET_MODE (inner) != wanted_inner_mode
6282           && (pos_rtx != 0
6283               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6284         return 0;
6285
6286       if (orig_pos < 0)
6287         return 0;
6288
6289       inner = force_to_mode (inner, wanted_inner_mode,
6290                              pos_rtx
6291                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6292                              ? ~(unsigned HOST_WIDE_INT) 0
6293                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6294                                 << orig_pos),
6295                              0);
6296     }
6297
6298   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6299      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6300   if (pos_rtx != 0
6301       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6302     {
6303       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6304
6305       /* If we know that no extraneous bits are set, and that the high
6306          bit is not set, convert extraction to cheaper one - either
6307          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6308          cases.  */
6309       if (flag_expensive_optimizations
6310           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6311               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6312                    & ~(((unsigned HOST_WIDE_INT)
6313                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6314                        >> 1))
6315                   == 0)))
6316         {
6317           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6318
6319           /* Prefer ZERO_EXTENSION, since it gives more information to
6320              backends.  */
6321           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6322             temp = temp1;
6323         }
6324       pos_rtx = temp;
6325     }
6326   else if (pos_rtx != 0
6327            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6328     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6329
6330   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6331      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6332      be a CONST_INT.  */
6333   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6334     pos_rtx = orig_pos_rtx;
6335
6336   else if (pos_rtx == 0)
6337     pos_rtx = GEN_INT (pos);
6338
6339   /* Make the required operation.  See if we can use existing rtx.  */
6340   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6341                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6342   if (! in_dest)
6343     new = gen_lowpart (mode, new);
6344
6345   return new;
6346 }
6347 \f
6348 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6349    with any other operations in X.  Return X without that shift if so.  */
6350
6351 static rtx
6352 extract_left_shift (rtx x, int count)
6353 {
6354   enum rtx_code code = GET_CODE (x);
6355   enum machine_mode mode = GET_MODE (x);
6356   rtx tem;
6357
6358   switch (code)
6359     {
6360     case ASHIFT:
6361       /* This is the shift itself.  If it is wide enough, we will return
6362          either the value being shifted if the shift count is equal to
6363          COUNT or a shift for the difference.  */
6364       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6365           && INTVAL (XEXP (x, 1)) >= count)
6366         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6367                                      INTVAL (XEXP (x, 1)) - count);
6368       break;
6369
6370     case NEG:  case NOT:
6371       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6372         return simplify_gen_unary (code, mode, tem, mode);
6373
6374       break;
6375
6376     case PLUS:  case IOR:  case XOR:  case AND:
6377       /* If we can safely shift this constant and we find the inner shift,
6378          make a new operation.  */
6379       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6380           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6381           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6382         return simplify_gen_binary (code, mode, tem,
6383                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6384
6385       break;
6386
6387     default:
6388       break;
6389     }
6390
6391   return 0;
6392 }
6393 \f
6394 /* Look at the expression rooted at X.  Look for expressions
6395    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6396    Form these expressions.
6397
6398    Return the new rtx, usually just X.
6399
6400    Also, for machines like the VAX that don't have logical shift insns,
6401    try to convert logical to arithmetic shift operations in cases where
6402    they are equivalent.  This undoes the canonicalizations to logical
6403    shifts done elsewhere.
6404
6405    We try, as much as possible, to re-use rtl expressions to save memory.
6406
6407    IN_CODE says what kind of expression we are processing.  Normally, it is
6408    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6409    being kludges), it is MEM.  When processing the arguments of a comparison
6410    or a COMPARE against zero, it is COMPARE.  */
6411
6412 static rtx
6413 make_compound_operation (rtx x, enum rtx_code in_code)
6414 {
6415   enum rtx_code code = GET_CODE (x);
6416   enum machine_mode mode = GET_MODE (x);
6417   int mode_width = GET_MODE_BITSIZE (mode);
6418   rtx rhs, lhs;
6419   enum rtx_code next_code;
6420   int i;
6421   rtx new = 0;
6422   rtx tem;
6423   const char *fmt;
6424
6425   /* Select the code to be used in recursive calls.  Once we are inside an
6426      address, we stay there.  If we have a comparison, set to COMPARE,
6427      but once inside, go back to our default of SET.  */
6428
6429   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6430                : ((code == COMPARE || COMPARISON_P (x))
6431                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6432                : in_code == COMPARE ? SET : in_code);
6433
6434   /* Process depending on the code of this operation.  If NEW is set
6435      nonzero, it will be returned.  */
6436
6437   switch (code)
6438     {
6439     case ASHIFT:
6440       /* Convert shifts by constants into multiplications if inside
6441          an address.  */
6442       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6443           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6444           && INTVAL (XEXP (x, 1)) >= 0)
6445         {
6446           new = make_compound_operation (XEXP (x, 0), next_code);
6447           new = gen_rtx_MULT (mode, new,
6448                               GEN_INT ((HOST_WIDE_INT) 1
6449                                        << INTVAL (XEXP (x, 1))));
6450         }
6451       break;
6452
6453     case AND:
6454       /* If the second operand is not a constant, we can't do anything
6455          with it.  */
6456       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6457         break;
6458
6459       /* If the constant is a power of two minus one and the first operand
6460          is a logical right shift, make an extraction.  */
6461       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6462           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6463         {
6464           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6465           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6466                                  0, in_code == COMPARE);
6467         }
6468
6469       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6470       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6471                && subreg_lowpart_p (XEXP (x, 0))
6472                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6473                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6474         {
6475           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6476                                          next_code);
6477           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6478                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6479                                  0, in_code == COMPARE);
6480         }
6481       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6482       else if ((GET_CODE (XEXP (x, 0)) == XOR
6483                 || GET_CODE (XEXP (x, 0)) == IOR)
6484                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6485                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6486                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6487         {
6488           /* Apply the distributive law, and then try to make extractions.  */
6489           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6490                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6491                                              XEXP (x, 1)),
6492                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6493                                              XEXP (x, 1)));
6494           new = make_compound_operation (new, in_code);
6495         }
6496
6497       /* If we are have (and (rotate X C) M) and C is larger than the number
6498          of bits in M, this is an extraction.  */
6499
6500       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6501                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6502                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6503                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6504         {
6505           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6506           new = make_extraction (mode, new,
6507                                  (GET_MODE_BITSIZE (mode)
6508                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6509                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6510         }
6511
6512       /* On machines without logical shifts, if the operand of the AND is
6513          a logical shift and our mask turns off all the propagated sign
6514          bits, we can replace the logical shift with an arithmetic shift.  */
6515       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6516                && !have_insn_for (LSHIFTRT, mode)
6517                && have_insn_for (ASHIFTRT, mode)
6518                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6519                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6520                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6521                && mode_width <= HOST_BITS_PER_WIDE_INT)
6522         {
6523           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6524
6525           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6526           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6527             SUBST (XEXP (x, 0),
6528                    gen_rtx_ASHIFTRT (mode,
6529                                      make_compound_operation
6530                                      (XEXP (XEXP (x, 0), 0), next_code),
6531                                      XEXP (XEXP (x, 0), 1)));
6532         }
6533
6534       /* If the constant is one less than a power of two, this might be
6535          representable by an extraction even if no shift is present.
6536          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6537          we are in a COMPARE.  */
6538       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6539         new = make_extraction (mode,
6540                                make_compound_operation (XEXP (x, 0),
6541                                                         next_code),
6542                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6543
6544       /* If we are in a comparison and this is an AND with a power of two,
6545          convert this into the appropriate bit extract.  */
6546       else if (in_code == COMPARE
6547                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6548         new = make_extraction (mode,
6549                                make_compound_operation (XEXP (x, 0),
6550                                                         next_code),
6551                                i, NULL_RTX, 1, 1, 0, 1);
6552
6553       break;
6554
6555     case LSHIFTRT:
6556       /* If the sign bit is known to be zero, replace this with an
6557          arithmetic shift.  */
6558       if (have_insn_for (ASHIFTRT, mode)
6559           && ! have_insn_for (LSHIFTRT, mode)
6560           && mode_width <= HOST_BITS_PER_WIDE_INT
6561           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6562         {
6563           new = gen_rtx_ASHIFTRT (mode,
6564                                   make_compound_operation (XEXP (x, 0),
6565                                                            next_code),
6566                                   XEXP (x, 1));
6567           break;
6568         }
6569
6570       /* ... fall through ...  */
6571
6572     case ASHIFTRT:
6573       lhs = XEXP (x, 0);
6574       rhs = XEXP (x, 1);
6575
6576       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6577          this is a SIGN_EXTRACT.  */
6578       if (GET_CODE (rhs) == CONST_INT
6579           && GET_CODE (lhs) == ASHIFT
6580           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6581           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6582         {
6583           new = make_compound_operation (XEXP (lhs, 0), next_code);
6584           new = make_extraction (mode, new,
6585                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6586                                  NULL_RTX, mode_width - INTVAL (rhs),
6587                                  code == LSHIFTRT, 0, in_code == COMPARE);
6588           break;
6589         }
6590
6591       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6592          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6593          also do this for some cases of SIGN_EXTRACT, but it doesn't
6594          seem worth the effort; the case checked for occurs on Alpha.  */
6595
6596       if (!OBJECT_P (lhs)
6597           && ! (GET_CODE (lhs) == SUBREG
6598                 && (OBJECT_P (SUBREG_REG (lhs))))
6599           && GET_CODE (rhs) == CONST_INT
6600           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6601           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6602         new = make_extraction (mode, make_compound_operation (new, next_code),
6603                                0, NULL_RTX, mode_width - INTVAL (rhs),
6604                                code == LSHIFTRT, 0, in_code == COMPARE);
6605
6606       break;
6607
6608     case SUBREG:
6609       /* Call ourselves recursively on the inner expression.  If we are
6610          narrowing the object and it has a different RTL code from
6611          what it originally did, do this SUBREG as a force_to_mode.  */
6612
6613       tem = make_compound_operation (SUBREG_REG (x), in_code);
6614
6615       {
6616         rtx simplified;
6617         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6618                                       SUBREG_BYTE (x));
6619
6620         if (simplified)
6621           tem = simplified;
6622
6623         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6624             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6625             && subreg_lowpart_p (x))
6626           {
6627             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6628                                        0);
6629
6630             /* If we have something other than a SUBREG, we might have
6631                done an expansion, so rerun ourselves.  */
6632             if (GET_CODE (newer) != SUBREG)
6633               newer = make_compound_operation (newer, in_code);
6634
6635             return newer;
6636           }
6637
6638         if (simplified)
6639           return tem;
6640       }
6641       break;
6642
6643     default:
6644       break;
6645     }
6646
6647   if (new)
6648     {
6649       x = gen_lowpart (mode, new);
6650       code = GET_CODE (x);
6651     }
6652
6653   /* Now recursively process each operand of this operation.  */
6654   fmt = GET_RTX_FORMAT (code);
6655   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6656     if (fmt[i] == 'e')
6657       {
6658         new = make_compound_operation (XEXP (x, i), next_code);
6659         SUBST (XEXP (x, i), new);
6660       }
6661
6662   /* If this is a commutative operation, the changes to the operands
6663      may have made it noncanonical.  */
6664   if (COMMUTATIVE_ARITH_P (x)
6665       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6666     {
6667       tem = XEXP (x, 0);
6668       SUBST (XEXP (x, 0), XEXP (x, 1));
6669       SUBST (XEXP (x, 1), tem);
6670     }
6671
6672   return x;
6673 }
6674 \f
6675 /* Given M see if it is a value that would select a field of bits
6676    within an item, but not the entire word.  Return -1 if not.
6677    Otherwise, return the starting position of the field, where 0 is the
6678    low-order bit.
6679
6680    *PLEN is set to the length of the field.  */
6681
6682 static int
6683 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6684 {
6685   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6686   int pos = exact_log2 (m & -m);
6687   int len = 0;
6688
6689   if (pos >= 0)
6690     /* Now shift off the low-order zero bits and see if we have a
6691        power of two minus 1.  */
6692     len = exact_log2 ((m >> pos) + 1);
6693
6694   if (len <= 0)
6695     pos = -1;
6696
6697   *plen = len;
6698   return pos;
6699 }
6700 \f
6701 /* If X refers to a register that equals REG in value, replace these
6702    references with REG.  */
6703 static rtx
6704 canon_reg_for_combine (rtx x, rtx reg)
6705 {
6706   rtx op0, op1, op2;
6707   const char *fmt;
6708   int i;
6709   bool copied;
6710
6711   enum rtx_code code = GET_CODE (x);
6712   switch (GET_RTX_CLASS (code))
6713     {
6714     case RTX_UNARY:
6715       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6716       if (op0 != XEXP (x, 0))
6717         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6718                                    GET_MODE (reg));
6719       break;
6720
6721     case RTX_BIN_ARITH:
6722     case RTX_COMM_ARITH:
6723       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6724       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6725       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6726         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6727       break;
6728
6729     case RTX_COMPARE:
6730     case RTX_COMM_COMPARE:
6731       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6732       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6733       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6734         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6735                                         GET_MODE (op0), op0, op1);
6736       break;
6737
6738     case RTX_TERNARY:
6739     case RTX_BITFIELD_OPS:
6740       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6741       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6742       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6743       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6744         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6745                                      GET_MODE (op0), op0, op1, op2);
6746
6747     case RTX_OBJ:
6748       if (REG_P (x))
6749         {
6750           if (rtx_equal_p (get_last_value (reg), x)
6751               || rtx_equal_p (reg, get_last_value (x)))
6752             return reg;
6753           else
6754             break;
6755         }
6756
6757       /* fall through */
6758
6759     default:
6760       fmt = GET_RTX_FORMAT (code);
6761       copied = false;
6762       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6763         if (fmt[i] == 'e')
6764           {
6765             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6766             if (op != XEXP (x, i))
6767               {
6768                 if (!copied)
6769                   {
6770                     copied = true;
6771                     x = copy_rtx (x);
6772                   }
6773                 XEXP (x, i) = op;
6774               }
6775           }
6776         else if (fmt[i] == 'E')
6777           {
6778             int j;
6779             for (j = 0; j < XVECLEN (x, i); j++)
6780               {
6781                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6782                 if (op != XVECEXP (x, i, j))
6783                   {
6784                     if (!copied)
6785                       {
6786                         copied = true;
6787                         x = copy_rtx (x);
6788                       }
6789                     XVECEXP (x, i, j) = op;
6790                   }
6791               }
6792           }
6793
6794       break;
6795     }
6796
6797   return x;
6798 }
6799
6800 /* Return X converted to MODE.  If the value is already truncated to
6801    MODE we can just return a subreg even though in the general case we
6802    would need an explicit truncation.  */
6803
6804 static rtx
6805 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6806 {
6807   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6808       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6809                                 GET_MODE_BITSIZE (GET_MODE (x)))
6810       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6811     return gen_lowpart (mode, x);
6812   else
6813     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6814 }
6815
6816 /* See if X can be simplified knowing that we will only refer to it in
6817    MODE and will only refer to those bits that are nonzero in MASK.
6818    If other bits are being computed or if masking operations are done
6819    that select a superset of the bits in MASK, they can sometimes be
6820    ignored.
6821
6822    Return a possibly simplified expression, but always convert X to
6823    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6824
6825    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6826    are all off in X.  This is used when X will be complemented, by either
6827    NOT, NEG, or XOR.  */
6828
6829 static rtx
6830 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6831                int just_select)
6832 {
6833   enum rtx_code code = GET_CODE (x);
6834   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6835   enum machine_mode op_mode;
6836   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6837   rtx op0, op1, temp;
6838
6839   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6840      code below will do the wrong thing since the mode of such an
6841      expression is VOIDmode.
6842
6843      Also do nothing if X is a CLOBBER; this can happen if X was
6844      the return value from a call to gen_lowpart.  */
6845   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6846     return x;
6847
6848   /* We want to perform the operation is its present mode unless we know
6849      that the operation is valid in MODE, in which case we do the operation
6850      in MODE.  */
6851   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6852               && have_insn_for (code, mode))
6853              ? mode : GET_MODE (x));
6854
6855   /* It is not valid to do a right-shift in a narrower mode
6856      than the one it came in with.  */
6857   if ((code == LSHIFTRT || code == ASHIFTRT)
6858       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6859     op_mode = GET_MODE (x);
6860
6861   /* Truncate MASK to fit OP_MODE.  */
6862   if (op_mode)
6863     mask &= GET_MODE_MASK (op_mode);
6864
6865   /* When we have an arithmetic operation, or a shift whose count we
6866      do not know, we need to assume that all bits up to the highest-order
6867      bit in MASK will be needed.  This is how we form such a mask.  */
6868   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6869     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6870   else
6871     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6872                    - 1);
6873
6874   /* Determine what bits of X are guaranteed to be (non)zero.  */
6875   nonzero = nonzero_bits (x, mode);
6876
6877   /* If none of the bits in X are needed, return a zero.  */
6878   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
6879     x = const0_rtx;
6880
6881   /* If X is a CONST_INT, return a new one.  Do this here since the
6882      test below will fail.  */
6883   if (GET_CODE (x) == CONST_INT)
6884     {
6885       if (SCALAR_INT_MODE_P (mode))
6886         return gen_int_mode (INTVAL (x) & mask, mode);
6887       else
6888         {
6889           x = GEN_INT (INTVAL (x) & mask);
6890           return gen_lowpart_common (mode, x);
6891         }
6892     }
6893
6894   /* If X is narrower than MODE and we want all the bits in X's mode, just
6895      get X in the proper mode.  */
6896   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6897       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6898     return gen_lowpart (mode, x);
6899
6900   switch (code)
6901     {
6902     case CLOBBER:
6903       /* If X is a (clobber (const_int)), return it since we know we are
6904          generating something that won't match.  */
6905       return x;
6906
6907     case SIGN_EXTEND:
6908     case ZERO_EXTEND:
6909     case ZERO_EXTRACT:
6910     case SIGN_EXTRACT:
6911       x = expand_compound_operation (x);
6912       if (GET_CODE (x) != code)
6913         return force_to_mode (x, mode, mask, next_select);
6914       break;
6915
6916     case SUBREG:
6917       if (subreg_lowpart_p (x)
6918           /* We can ignore the effect of this SUBREG if it narrows the mode or
6919              if the constant masks to zero all the bits the mode doesn't
6920              have.  */
6921           && ((GET_MODE_SIZE (GET_MODE (x))
6922                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6923               || (0 == (mask
6924                         & GET_MODE_MASK (GET_MODE (x))
6925                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6926         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6927       break;
6928
6929     case AND:
6930       /* If this is an AND with a constant, convert it into an AND
6931          whose constant is the AND of that constant with MASK.  If it
6932          remains an AND of MASK, delete it since it is redundant.  */
6933
6934       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6935         {
6936           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6937                                       mask & INTVAL (XEXP (x, 1)));
6938
6939           /* If X is still an AND, see if it is an AND with a mask that
6940              is just some low-order bits.  If so, and it is MASK, we don't
6941              need it.  */
6942
6943           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6944               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6945                   == mask))
6946             x = XEXP (x, 0);
6947
6948           /* If it remains an AND, try making another AND with the bits
6949              in the mode mask that aren't in MASK turned on.  If the
6950              constant in the AND is wide enough, this might make a
6951              cheaper constant.  */
6952
6953           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6954               && GET_MODE_MASK (GET_MODE (x)) != mask
6955               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6956             {
6957               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6958                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6959               int width = GET_MODE_BITSIZE (GET_MODE (x));
6960               rtx y;
6961
6962               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6963                  number, sign extend it.  */
6964               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6965                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6966                 cval |= (HOST_WIDE_INT) -1 << width;
6967
6968               y = simplify_gen_binary (AND, GET_MODE (x),
6969                                        XEXP (x, 0), GEN_INT (cval));
6970               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6971                 x = y;
6972             }
6973
6974           break;
6975         }
6976
6977       goto binop;
6978
6979     case PLUS:
6980       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6981          low-order bits (as in an alignment operation) and FOO is already
6982          aligned to that boundary, mask C1 to that boundary as well.
6983          This may eliminate that PLUS and, later, the AND.  */
6984
6985       {
6986         unsigned int width = GET_MODE_BITSIZE (mode);
6987         unsigned HOST_WIDE_INT smask = mask;
6988
6989         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6990            number, sign extend it.  */
6991
6992         if (width < HOST_BITS_PER_WIDE_INT
6993             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6994           smask |= (HOST_WIDE_INT) -1 << width;
6995
6996         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6997             && exact_log2 (- smask) >= 0
6998             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6999             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7000           return force_to_mode (plus_constant (XEXP (x, 0),
7001                                                (INTVAL (XEXP (x, 1)) & smask)),
7002                                 mode, smask, next_select);
7003       }
7004
7005       /* ... fall through ...  */
7006
7007     case MULT:
7008       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7009          most significant bit in MASK since carries from those bits will
7010          affect the bits we are interested in.  */
7011       mask = fuller_mask;
7012       goto binop;
7013
7014     case MINUS:
7015       /* If X is (minus C Y) where C's least set bit is larger than any bit
7016          in the mask, then we may replace with (neg Y).  */
7017       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7018           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7019                                         & -INTVAL (XEXP (x, 0))))
7020               > mask))
7021         {
7022           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7023                                   GET_MODE (x));
7024           return force_to_mode (x, mode, mask, next_select);
7025         }
7026
7027       /* Similarly, if C contains every bit in the fuller_mask, then we may
7028          replace with (not Y).  */
7029       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7030           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7031               == INTVAL (XEXP (x, 0))))
7032         {
7033           x = simplify_gen_unary (NOT, GET_MODE (x),
7034                                   XEXP (x, 1), GET_MODE (x));
7035           return force_to_mode (x, mode, mask, next_select);
7036         }
7037
7038       mask = fuller_mask;
7039       goto binop;
7040
7041     case IOR:
7042     case XOR:
7043       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7044          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7045          operation which may be a bitfield extraction.  Ensure that the
7046          constant we form is not wider than the mode of X.  */
7047
7048       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7049           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7050           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7051           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7052           && GET_CODE (XEXP (x, 1)) == CONST_INT
7053           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7054                + floor_log2 (INTVAL (XEXP (x, 1))))
7055               < GET_MODE_BITSIZE (GET_MODE (x)))
7056           && (INTVAL (XEXP (x, 1))
7057               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7058         {
7059           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7060                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7061           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7062                                       XEXP (XEXP (x, 0), 0), temp);
7063           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7064                                    XEXP (XEXP (x, 0), 1));
7065           return force_to_mode (x, mode, mask, next_select);
7066         }
7067
7068     binop:
7069       /* For most binary operations, just propagate into the operation and
7070          change the mode if we have an operation of that mode.  */
7071
7072       op0 = gen_lowpart_or_truncate (op_mode,
7073                                      force_to_mode (XEXP (x, 0), mode, mask,
7074                                                     next_select));
7075       op1 = gen_lowpart_or_truncate (op_mode,
7076                                      force_to_mode (XEXP (x, 1), mode, mask,
7077                                         next_select));
7078
7079       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7080         x = simplify_gen_binary (code, op_mode, op0, op1);
7081       break;
7082
7083     case ASHIFT:
7084       /* For left shifts, do the same, but just for the first operand.
7085          However, we cannot do anything with shifts where we cannot
7086          guarantee that the counts are smaller than the size of the mode
7087          because such a count will have a different meaning in a
7088          wider mode.  */
7089
7090       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7091              && INTVAL (XEXP (x, 1)) >= 0
7092              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7093           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7094                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7095                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7096         break;
7097
7098       /* If the shift count is a constant and we can do arithmetic in
7099          the mode of the shift, refine which bits we need.  Otherwise, use the
7100          conservative form of the mask.  */
7101       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7102           && INTVAL (XEXP (x, 1)) >= 0
7103           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7104           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7105         mask >>= INTVAL (XEXP (x, 1));
7106       else
7107         mask = fuller_mask;
7108
7109       op0 = gen_lowpart_or_truncate (op_mode,
7110                                      force_to_mode (XEXP (x, 0), op_mode,
7111                                                     mask, next_select));
7112
7113       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7114         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7115       break;
7116
7117     case LSHIFTRT:
7118       /* Here we can only do something if the shift count is a constant,
7119          this shift constant is valid for the host, and we can do arithmetic
7120          in OP_MODE.  */
7121
7122       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7123           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7124           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7125         {
7126           rtx inner = XEXP (x, 0);
7127           unsigned HOST_WIDE_INT inner_mask;
7128
7129           /* Select the mask of the bits we need for the shift operand.  */
7130           inner_mask = mask << INTVAL (XEXP (x, 1));
7131
7132           /* We can only change the mode of the shift if we can do arithmetic
7133              in the mode of the shift and INNER_MASK is no wider than the
7134              width of X's mode.  */
7135           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7136             op_mode = GET_MODE (x);
7137
7138           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7139
7140           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7141             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7142         }
7143
7144       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7145          shift and AND produces only copies of the sign bit (C2 is one less
7146          than a power of two), we can do this with just a shift.  */
7147
7148       if (GET_CODE (x) == LSHIFTRT
7149           && GET_CODE (XEXP (x, 1)) == CONST_INT
7150           /* The shift puts one of the sign bit copies in the least significant
7151              bit.  */
7152           && ((INTVAL (XEXP (x, 1))
7153                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7154               >= GET_MODE_BITSIZE (GET_MODE (x)))
7155           && exact_log2 (mask + 1) >= 0
7156           /* Number of bits left after the shift must be more than the mask
7157              needs.  */
7158           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7159               <= GET_MODE_BITSIZE (GET_MODE (x)))
7160           /* Must be more sign bit copies than the mask needs.  */
7161           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7162               >= exact_log2 (mask + 1)))
7163         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7164                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7165                                           - exact_log2 (mask + 1)));
7166
7167       goto shiftrt;
7168
7169     case ASHIFTRT:
7170       /* If we are just looking for the sign bit, we don't need this shift at
7171          all, even if it has a variable count.  */
7172       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7173           && (mask == ((unsigned HOST_WIDE_INT) 1
7174                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7175         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7176
7177       /* If this is a shift by a constant, get a mask that contains those bits
7178          that are not copies of the sign bit.  We then have two cases:  If
7179          MASK only includes those bits, this can be a logical shift, which may
7180          allow simplifications.  If MASK is a single-bit field not within
7181          those bits, we are requesting a copy of the sign bit and hence can
7182          shift the sign bit to the appropriate location.  */
7183
7184       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7185           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7186         {
7187           int i;
7188
7189           /* If the considered data is wider than HOST_WIDE_INT, we can't
7190              represent a mask for all its bits in a single scalar.
7191              But we only care about the lower bits, so calculate these.  */
7192
7193           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7194             {
7195               nonzero = ~(HOST_WIDE_INT) 0;
7196
7197               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7198                  is the number of bits a full-width mask would have set.
7199                  We need only shift if these are fewer than nonzero can
7200                  hold.  If not, we must keep all bits set in nonzero.  */
7201
7202               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7203                   < HOST_BITS_PER_WIDE_INT)
7204                 nonzero >>= INTVAL (XEXP (x, 1))
7205                             + HOST_BITS_PER_WIDE_INT
7206                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7207             }
7208           else
7209             {
7210               nonzero = GET_MODE_MASK (GET_MODE (x));
7211               nonzero >>= INTVAL (XEXP (x, 1));
7212             }
7213
7214           if ((mask & ~nonzero) == 0)
7215             {
7216               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7217                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7218               if (GET_CODE (x) != ASHIFTRT)
7219                 return force_to_mode (x, mode, mask, next_select);
7220             }
7221
7222           else if ((i = exact_log2 (mask)) >= 0)
7223             {
7224               x = simplify_shift_const
7225                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7226                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7227
7228               if (GET_CODE (x) != ASHIFTRT)
7229                 return force_to_mode (x, mode, mask, next_select);
7230             }
7231         }
7232
7233       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7234          even if the shift count isn't a constant.  */
7235       if (mask == 1)
7236         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7237                                  XEXP (x, 0), XEXP (x, 1));
7238
7239     shiftrt:
7240
7241       /* If this is a zero- or sign-extension operation that just affects bits
7242          we don't care about, remove it.  Be sure the call above returned
7243          something that is still a shift.  */
7244
7245       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7246           && GET_CODE (XEXP (x, 1)) == CONST_INT
7247           && INTVAL (XEXP (x, 1)) >= 0
7248           && (INTVAL (XEXP (x, 1))
7249               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7250           && GET_CODE (XEXP (x, 0)) == ASHIFT
7251           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7252         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7253                               next_select);
7254
7255       break;
7256
7257     case ROTATE:
7258     case ROTATERT:
7259       /* If the shift count is constant and we can do computations
7260          in the mode of X, compute where the bits we care about are.
7261          Otherwise, we can't do anything.  Don't change the mode of
7262          the shift or propagate MODE into the shift, though.  */
7263       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7264           && INTVAL (XEXP (x, 1)) >= 0)
7265         {
7266           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7267                                             GET_MODE (x), GEN_INT (mask),
7268                                             XEXP (x, 1));
7269           if (temp && GET_CODE (temp) == CONST_INT)
7270             SUBST (XEXP (x, 0),
7271                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7272                                   INTVAL (temp), next_select));
7273         }
7274       break;
7275
7276     case NEG:
7277       /* If we just want the low-order bit, the NEG isn't needed since it
7278          won't change the low-order bit.  */
7279       if (mask == 1)
7280         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7281
7282       /* We need any bits less significant than the most significant bit in
7283          MASK since carries from those bits will affect the bits we are
7284          interested in.  */
7285       mask = fuller_mask;
7286       goto unop;
7287
7288     case NOT:
7289       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7290          same as the XOR case above.  Ensure that the constant we form is not
7291          wider than the mode of X.  */
7292
7293       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7294           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7295           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7296           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7297               < GET_MODE_BITSIZE (GET_MODE (x)))
7298           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7299         {
7300           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7301                                GET_MODE (x));
7302           temp = simplify_gen_binary (XOR, GET_MODE (x),
7303                                       XEXP (XEXP (x, 0), 0), temp);
7304           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7305                                    temp, XEXP (XEXP (x, 0), 1));
7306
7307           return force_to_mode (x, mode, mask, next_select);
7308         }
7309
7310       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7311          use the full mask inside the NOT.  */
7312       mask = fuller_mask;
7313
7314     unop:
7315       op0 = gen_lowpart_or_truncate (op_mode,
7316                                      force_to_mode (XEXP (x, 0), mode, mask,
7317                                                     next_select));
7318       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7319         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7320       break;
7321
7322     case NE:
7323       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7324          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7325          which is equal to STORE_FLAG_VALUE.  */
7326       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7327           && GET_MODE (XEXP (x, 0)) == mode
7328           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7329           && (nonzero_bits (XEXP (x, 0), mode)
7330               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7331         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7332
7333       break;
7334
7335     case IF_THEN_ELSE:
7336       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7337          written in a narrower mode.  We play it safe and do not do so.  */
7338
7339       SUBST (XEXP (x, 1),
7340              gen_lowpart_or_truncate (GET_MODE (x),
7341                                       force_to_mode (XEXP (x, 1), mode,
7342                                                      mask, next_select)));
7343       SUBST (XEXP (x, 2),
7344              gen_lowpart_or_truncate (GET_MODE (x),
7345                                       force_to_mode (XEXP (x, 2), mode,
7346                                                      mask, next_select)));
7347       break;
7348
7349     default:
7350       break;
7351     }
7352
7353   /* Ensure we return a value of the proper mode.  */
7354   return gen_lowpart_or_truncate (mode, x);
7355 }
7356 \f
7357 /* Return nonzero if X is an expression that has one of two values depending on
7358    whether some other value is zero or nonzero.  In that case, we return the
7359    value that is being tested, *PTRUE is set to the value if the rtx being
7360    returned has a nonzero value, and *PFALSE is set to the other alternative.
7361
7362    If we return zero, we set *PTRUE and *PFALSE to X.  */
7363
7364 static rtx
7365 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7366 {
7367   enum machine_mode mode = GET_MODE (x);
7368   enum rtx_code code = GET_CODE (x);
7369   rtx cond0, cond1, true0, true1, false0, false1;
7370   unsigned HOST_WIDE_INT nz;
7371
7372   /* If we are comparing a value against zero, we are done.  */
7373   if ((code == NE || code == EQ)
7374       && XEXP (x, 1) == const0_rtx)
7375     {
7376       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7377       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7378       return XEXP (x, 0);
7379     }
7380
7381   /* If this is a unary operation whose operand has one of two values, apply
7382      our opcode to compute those values.  */
7383   else if (UNARY_P (x)
7384            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7385     {
7386       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7387       *pfalse = simplify_gen_unary (code, mode, false0,
7388                                     GET_MODE (XEXP (x, 0)));
7389       return cond0;
7390     }
7391
7392   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7393      make can't possibly match and would suppress other optimizations.  */
7394   else if (code == COMPARE)
7395     ;
7396
7397   /* If this is a binary operation, see if either side has only one of two
7398      values.  If either one does or if both do and they are conditional on
7399      the same value, compute the new true and false values.  */
7400   else if (BINARY_P (x))
7401     {
7402       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7403       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7404
7405       if ((cond0 != 0 || cond1 != 0)
7406           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7407         {
7408           /* If if_then_else_cond returned zero, then true/false are the
7409              same rtl.  We must copy one of them to prevent invalid rtl
7410              sharing.  */
7411           if (cond0 == 0)
7412             true0 = copy_rtx (true0);
7413           else if (cond1 == 0)
7414             true1 = copy_rtx (true1);
7415
7416           if (COMPARISON_P (x))
7417             {
7418               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7419                                                 true0, true1);
7420               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7421                                                  false0, false1);
7422              }
7423           else
7424             {
7425               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7426               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7427             }
7428
7429           return cond0 ? cond0 : cond1;
7430         }
7431
7432       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7433          operands is zero when the other is nonzero, and vice-versa,
7434          and STORE_FLAG_VALUE is 1 or -1.  */
7435
7436       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7437           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7438               || code == UMAX)
7439           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7440         {
7441           rtx op0 = XEXP (XEXP (x, 0), 1);
7442           rtx op1 = XEXP (XEXP (x, 1), 1);
7443
7444           cond0 = XEXP (XEXP (x, 0), 0);
7445           cond1 = XEXP (XEXP (x, 1), 0);
7446
7447           if (COMPARISON_P (cond0)
7448               && COMPARISON_P (cond1)
7449               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7450                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7451                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7452                   || ((swap_condition (GET_CODE (cond0))
7453                        == reversed_comparison_code (cond1, NULL))
7454                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7455                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7456               && ! side_effects_p (x))
7457             {
7458               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7459               *pfalse = simplify_gen_binary (MULT, mode,
7460                                              (code == MINUS
7461                                               ? simplify_gen_unary (NEG, mode,
7462                                                                     op1, mode)
7463                                               : op1),
7464                                               const_true_rtx);
7465               return cond0;
7466             }
7467         }
7468
7469       /* Similarly for MULT, AND and UMIN, except that for these the result
7470          is always zero.  */
7471       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7472           && (code == MULT || code == AND || code == UMIN)
7473           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7474         {
7475           cond0 = XEXP (XEXP (x, 0), 0);
7476           cond1 = XEXP (XEXP (x, 1), 0);
7477
7478           if (COMPARISON_P (cond0)
7479               && COMPARISON_P (cond1)
7480               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7481                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7482                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7483                   || ((swap_condition (GET_CODE (cond0))
7484                        == reversed_comparison_code (cond1, NULL))
7485                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7486                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7487               && ! side_effects_p (x))
7488             {
7489               *ptrue = *pfalse = const0_rtx;
7490               return cond0;
7491             }
7492         }
7493     }
7494
7495   else if (code == IF_THEN_ELSE)
7496     {
7497       /* If we have IF_THEN_ELSE already, extract the condition and
7498          canonicalize it if it is NE or EQ.  */
7499       cond0 = XEXP (x, 0);
7500       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7501       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7502         return XEXP (cond0, 0);
7503       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7504         {
7505           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7506           return XEXP (cond0, 0);
7507         }
7508       else
7509         return cond0;
7510     }
7511
7512   /* If X is a SUBREG, we can narrow both the true and false values
7513      if the inner expression, if there is a condition.  */
7514   else if (code == SUBREG
7515            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7516                                                &true0, &false0)))
7517     {
7518       true0 = simplify_gen_subreg (mode, true0,
7519                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7520       false0 = simplify_gen_subreg (mode, false0,
7521                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7522       if (true0 && false0)
7523         {
7524           *ptrue = true0;
7525           *pfalse = false0;
7526           return cond0;
7527         }
7528     }
7529
7530   /* If X is a constant, this isn't special and will cause confusions
7531      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7532   else if (CONSTANT_P (x)
7533            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7534     ;
7535
7536   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7537      will be least confusing to the rest of the compiler.  */
7538   else if (mode == BImode)
7539     {
7540       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7541       return x;
7542     }
7543
7544   /* If X is known to be either 0 or -1, those are the true and
7545      false values when testing X.  */
7546   else if (x == constm1_rtx || x == const0_rtx
7547            || (mode != VOIDmode
7548                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7549     {
7550       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7551       return x;
7552     }
7553
7554   /* Likewise for 0 or a single bit.  */
7555   else if (SCALAR_INT_MODE_P (mode)
7556            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7557            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7558     {
7559       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7560       return x;
7561     }
7562
7563   /* Otherwise fail; show no condition with true and false values the same.  */
7564   *ptrue = *pfalse = x;
7565   return 0;
7566 }
7567 \f
7568 /* Return the value of expression X given the fact that condition COND
7569    is known to be true when applied to REG as its first operand and VAL
7570    as its second.  X is known to not be shared and so can be modified in
7571    place.
7572
7573    We only handle the simplest cases, and specifically those cases that
7574    arise with IF_THEN_ELSE expressions.  */
7575
7576 static rtx
7577 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7578 {
7579   enum rtx_code code = GET_CODE (x);
7580   rtx temp;
7581   const char *fmt;
7582   int i, j;
7583
7584   if (side_effects_p (x))
7585     return x;
7586
7587   /* If either operand of the condition is a floating point value,
7588      then we have to avoid collapsing an EQ comparison.  */
7589   if (cond == EQ
7590       && rtx_equal_p (x, reg)
7591       && ! FLOAT_MODE_P (GET_MODE (x))
7592       && ! FLOAT_MODE_P (GET_MODE (val)))
7593     return val;
7594
7595   if (cond == UNEQ && rtx_equal_p (x, reg))
7596     return val;
7597
7598   /* If X is (abs REG) and we know something about REG's relationship
7599      with zero, we may be able to simplify this.  */
7600
7601   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7602     switch (cond)
7603       {
7604       case GE:  case GT:  case EQ:
7605         return XEXP (x, 0);
7606       case LT:  case LE:
7607         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7608                                    XEXP (x, 0),
7609                                    GET_MODE (XEXP (x, 0)));
7610       default:
7611         break;
7612       }
7613
7614   /* The only other cases we handle are MIN, MAX, and comparisons if the
7615      operands are the same as REG and VAL.  */
7616
7617   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7618     {
7619       if (rtx_equal_p (XEXP (x, 0), val))
7620         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7621
7622       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7623         {
7624           if (COMPARISON_P (x))
7625             {
7626               if (comparison_dominates_p (cond, code))
7627                 return const_true_rtx;
7628
7629               code = reversed_comparison_code (x, NULL);
7630               if (code != UNKNOWN
7631                   && comparison_dominates_p (cond, code))
7632                 return const0_rtx;
7633               else
7634                 return x;
7635             }
7636           else if (code == SMAX || code == SMIN
7637                    || code == UMIN || code == UMAX)
7638             {
7639               int unsignedp = (code == UMIN || code == UMAX);
7640
7641               /* Do not reverse the condition when it is NE or EQ.
7642                  This is because we cannot conclude anything about
7643                  the value of 'SMAX (x, y)' when x is not equal to y,
7644                  but we can when x equals y.  */
7645               if ((code == SMAX || code == UMAX)
7646                   && ! (cond == EQ || cond == NE))
7647                 cond = reverse_condition (cond);
7648
7649               switch (cond)
7650                 {
7651                 case GE:   case GT:
7652                   return unsignedp ? x : XEXP (x, 1);
7653                 case LE:   case LT:
7654                   return unsignedp ? x : XEXP (x, 0);
7655                 case GEU:  case GTU:
7656                   return unsignedp ? XEXP (x, 1) : x;
7657                 case LEU:  case LTU:
7658                   return unsignedp ? XEXP (x, 0) : x;
7659                 default:
7660                   break;
7661                 }
7662             }
7663         }
7664     }
7665   else if (code == SUBREG)
7666     {
7667       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7668       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7669
7670       if (SUBREG_REG (x) != r)
7671         {
7672           /* We must simplify subreg here, before we lose track of the
7673              original inner_mode.  */
7674           new = simplify_subreg (GET_MODE (x), r,
7675                                  inner_mode, SUBREG_BYTE (x));
7676           if (new)
7677             return new;
7678           else
7679             SUBST (SUBREG_REG (x), r);
7680         }
7681
7682       return x;
7683     }
7684   /* We don't have to handle SIGN_EXTEND here, because even in the
7685      case of replacing something with a modeless CONST_INT, a
7686      CONST_INT is already (supposed to be) a valid sign extension for
7687      its narrower mode, which implies it's already properly
7688      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7689      story is different.  */
7690   else if (code == ZERO_EXTEND)
7691     {
7692       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7693       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7694
7695       if (XEXP (x, 0) != r)
7696         {
7697           /* We must simplify the zero_extend here, before we lose
7698              track of the original inner_mode.  */
7699           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7700                                           r, inner_mode);
7701           if (new)
7702             return new;
7703           else
7704             SUBST (XEXP (x, 0), r);
7705         }
7706
7707       return x;
7708     }
7709
7710   fmt = GET_RTX_FORMAT (code);
7711   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7712     {
7713       if (fmt[i] == 'e')
7714         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7715       else if (fmt[i] == 'E')
7716         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7717           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7718                                                 cond, reg, val));
7719     }
7720
7721   return x;
7722 }
7723 \f
7724 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7725    assignment as a field assignment.  */
7726
7727 static int
7728 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7729 {
7730   if (x == y || rtx_equal_p (x, y))
7731     return 1;
7732
7733   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7734     return 0;
7735
7736   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7737      Note that all SUBREGs of MEM are paradoxical; otherwise they
7738      would have been rewritten.  */
7739   if (MEM_P (x) && GET_CODE (y) == SUBREG
7740       && MEM_P (SUBREG_REG (y))
7741       && rtx_equal_p (SUBREG_REG (y),
7742                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7743     return 1;
7744
7745   if (MEM_P (y) && GET_CODE (x) == SUBREG
7746       && MEM_P (SUBREG_REG (x))
7747       && rtx_equal_p (SUBREG_REG (x),
7748                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7749     return 1;
7750
7751   /* We used to see if get_last_value of X and Y were the same but that's
7752      not correct.  In one direction, we'll cause the assignment to have
7753      the wrong destination and in the case, we'll import a register into this
7754      insn that might have already have been dead.   So fail if none of the
7755      above cases are true.  */
7756   return 0;
7757 }
7758 \f
7759 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7760    Return that assignment if so.
7761
7762    We only handle the most common cases.  */
7763
7764 static rtx
7765 make_field_assignment (rtx x)
7766 {
7767   rtx dest = SET_DEST (x);
7768   rtx src = SET_SRC (x);
7769   rtx assign;
7770   rtx rhs, lhs;
7771   HOST_WIDE_INT c1;
7772   HOST_WIDE_INT pos;
7773   unsigned HOST_WIDE_INT len;
7774   rtx other;
7775   enum machine_mode mode;
7776
7777   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7778      a clear of a one-bit field.  We will have changed it to
7779      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7780      for a SUBREG.  */
7781
7782   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7783       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7784       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7785       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7786     {
7787       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7788                                 1, 1, 1, 0);
7789       if (assign != 0)
7790         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7791       return x;
7792     }
7793
7794   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7795       && subreg_lowpart_p (XEXP (src, 0))
7796       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7797           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7798       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7799       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7800       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7801       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7802     {
7803       assign = make_extraction (VOIDmode, dest, 0,
7804                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7805                                 1, 1, 1, 0);
7806       if (assign != 0)
7807         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7808       return x;
7809     }
7810
7811   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7812      one-bit field.  */
7813   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7814       && XEXP (XEXP (src, 0), 0) == const1_rtx
7815       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7816     {
7817       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7818                                 1, 1, 1, 0);
7819       if (assign != 0)
7820         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7821       return x;
7822     }
7823
7824   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7825      SRC is an AND with all bits of that field set, then we can discard
7826      the AND.  */
7827   if (GET_CODE (dest) == ZERO_EXTRACT
7828       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7829       && GET_CODE (src) == AND
7830       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7831     {
7832       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7833       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7834       unsigned HOST_WIDE_INT ze_mask;
7835
7836       if (width >= HOST_BITS_PER_WIDE_INT)
7837         ze_mask = -1;
7838       else
7839         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7840
7841       /* Complete overlap.  We can remove the source AND.  */
7842       if ((and_mask & ze_mask) == ze_mask)
7843         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7844
7845       /* Partial overlap.  We can reduce the source AND.  */
7846       if ((and_mask & ze_mask) != and_mask)
7847         {
7848           mode = GET_MODE (src);
7849           src = gen_rtx_AND (mode, XEXP (src, 0),
7850                              gen_int_mode (and_mask & ze_mask, mode));
7851           return gen_rtx_SET (VOIDmode, dest, src);
7852         }
7853     }
7854
7855   /* The other case we handle is assignments into a constant-position
7856      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7857      a mask that has all one bits except for a group of zero bits and
7858      OTHER is known to have zeros where C1 has ones, this is such an
7859      assignment.  Compute the position and length from C1.  Shift OTHER
7860      to the appropriate position, force it to the required mode, and
7861      make the extraction.  Check for the AND in both operands.  */
7862
7863   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7864     return x;
7865
7866   rhs = expand_compound_operation (XEXP (src, 0));
7867   lhs = expand_compound_operation (XEXP (src, 1));
7868
7869   if (GET_CODE (rhs) == AND
7870       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7871       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7872     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7873   else if (GET_CODE (lhs) == AND
7874            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7875            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7876     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7877   else
7878     return x;
7879
7880   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7881   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7882       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7883       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7884     return x;
7885
7886   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7887   if (assign == 0)
7888     return x;
7889
7890   /* The mode to use for the source is the mode of the assignment, or of
7891      what is inside a possible STRICT_LOW_PART.  */
7892   mode = (GET_CODE (assign) == STRICT_LOW_PART
7893           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7894
7895   /* Shift OTHER right POS places and make it the source, restricting it
7896      to the proper length and mode.  */
7897
7898   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7899                                                      GET_MODE (src),
7900                                                      other, pos),
7901                                dest);
7902   src = force_to_mode (src, mode,
7903                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7904                        ? ~(unsigned HOST_WIDE_INT) 0
7905                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7906                        0);
7907
7908   /* If SRC is masked by an AND that does not make a difference in
7909      the value being stored, strip it.  */
7910   if (GET_CODE (assign) == ZERO_EXTRACT
7911       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7912       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7913       && GET_CODE (src) == AND
7914       && GET_CODE (XEXP (src, 1)) == CONST_INT
7915       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7916           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7917     src = XEXP (src, 0);
7918
7919   return gen_rtx_SET (VOIDmode, assign, src);
7920 }
7921 \f
7922 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7923    if so.  */
7924
7925 static rtx
7926 apply_distributive_law (rtx x)
7927 {
7928   enum rtx_code code = GET_CODE (x);
7929   enum rtx_code inner_code;
7930   rtx lhs, rhs, other;
7931   rtx tem;
7932
7933   /* Distributivity is not true for floating point as it can change the
7934      value.  So we don't do it unless -funsafe-math-optimizations.  */
7935   if (FLOAT_MODE_P (GET_MODE (x))
7936       && ! flag_unsafe_math_optimizations)
7937     return x;
7938
7939   /* The outer operation can only be one of the following:  */
7940   if (code != IOR && code != AND && code != XOR
7941       && code != PLUS && code != MINUS)
7942     return x;
7943
7944   lhs = XEXP (x, 0);
7945   rhs = XEXP (x, 1);
7946
7947   /* If either operand is a primitive we can't do anything, so get out
7948      fast.  */
7949   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7950     return x;
7951
7952   lhs = expand_compound_operation (lhs);
7953   rhs = expand_compound_operation (rhs);
7954   inner_code = GET_CODE (lhs);
7955   if (inner_code != GET_CODE (rhs))
7956     return x;
7957
7958   /* See if the inner and outer operations distribute.  */
7959   switch (inner_code)
7960     {
7961     case LSHIFTRT:
7962     case ASHIFTRT:
7963     case AND:
7964     case IOR:
7965       /* These all distribute except over PLUS.  */
7966       if (code == PLUS || code == MINUS)
7967         return x;
7968       break;
7969
7970     case MULT:
7971       if (code != PLUS && code != MINUS)
7972         return x;
7973       break;
7974
7975     case ASHIFT:
7976       /* This is also a multiply, so it distributes over everything.  */
7977       break;
7978
7979     case SUBREG:
7980       /* Non-paradoxical SUBREGs distributes over all operations,
7981          provided the inner modes and byte offsets are the same, this
7982          is an extraction of a low-order part, we don't convert an fp
7983          operation to int or vice versa, this is not a vector mode,
7984          and we would not be converting a single-word operation into a
7985          multi-word operation.  The latter test is not required, but
7986          it prevents generating unneeded multi-word operations.  Some
7987          of the previous tests are redundant given the latter test,
7988          but are retained because they are required for correctness.
7989
7990          We produce the result slightly differently in this case.  */
7991
7992       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7993           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7994           || ! subreg_lowpart_p (lhs)
7995           || (GET_MODE_CLASS (GET_MODE (lhs))
7996               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7997           || (GET_MODE_SIZE (GET_MODE (lhs))
7998               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7999           || VECTOR_MODE_P (GET_MODE (lhs))
8000           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8001           /* Result might need to be truncated.  Don't change mode if
8002              explicit truncation is needed.  */
8003           || !TRULY_NOOP_TRUNCATION
8004                (GET_MODE_BITSIZE (GET_MODE (x)),
8005                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8006         return x;
8007
8008       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8009                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8010       return gen_lowpart (GET_MODE (x), tem);
8011
8012     default:
8013       return x;
8014     }
8015
8016   /* Set LHS and RHS to the inner operands (A and B in the example
8017      above) and set OTHER to the common operand (C in the example).
8018      There is only one way to do this unless the inner operation is
8019      commutative.  */
8020   if (COMMUTATIVE_ARITH_P (lhs)
8021       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8022     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8023   else if (COMMUTATIVE_ARITH_P (lhs)
8024            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8025     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8026   else if (COMMUTATIVE_ARITH_P (lhs)
8027            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8028     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8029   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8030     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8031   else
8032     return x;
8033
8034   /* Form the new inner operation, seeing if it simplifies first.  */
8035   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8036
8037   /* There is one exception to the general way of distributing:
8038      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8039   if (code == XOR && inner_code == IOR)
8040     {
8041       inner_code = AND;
8042       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8043     }
8044
8045   /* We may be able to continuing distributing the result, so call
8046      ourselves recursively on the inner operation before forming the
8047      outer operation, which we return.  */
8048   return simplify_gen_binary (inner_code, GET_MODE (x),
8049                               apply_distributive_law (tem), other);
8050 }
8051
8052 /* See if X is of the form (* (+ A B) C), and if so convert to
8053    (+ (* A C) (* B C)) and try to simplify.
8054
8055    Most of the time, this results in no change.  However, if some of
8056    the operands are the same or inverses of each other, simplifications
8057    will result.
8058
8059    For example, (and (ior A B) (not B)) can occur as the result of
8060    expanding a bit field assignment.  When we apply the distributive
8061    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8062    which then simplifies to (and (A (not B))).
8063
8064    Note that no checks happen on the validity of applying the inverse
8065    distributive law.  This is pointless since we can do it in the
8066    few places where this routine is called.
8067
8068    N is the index of the term that is decomposed (the arithmetic operation,
8069    i.e. (+ A B) in the first example above).  !N is the index of the term that
8070    is distributed, i.e. of C in the first example above.  */
8071 static rtx
8072 distribute_and_simplify_rtx (rtx x, int n)
8073 {
8074   enum machine_mode mode;
8075   enum rtx_code outer_code, inner_code;
8076   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8077
8078   decomposed = XEXP (x, n);
8079   if (!ARITHMETIC_P (decomposed))
8080     return NULL_RTX;
8081
8082   mode = GET_MODE (x);
8083   outer_code = GET_CODE (x);
8084   distributed = XEXP (x, !n);
8085
8086   inner_code = GET_CODE (decomposed);
8087   inner_op0 = XEXP (decomposed, 0);
8088   inner_op1 = XEXP (decomposed, 1);
8089
8090   /* Special case (and (xor B C) (not A)), which is equivalent to
8091      (xor (ior A B) (ior A C))  */
8092   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8093     {
8094       distributed = XEXP (distributed, 0);
8095       outer_code = IOR;
8096     }
8097
8098   if (n == 0)
8099     {
8100       /* Distribute the second term.  */
8101       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8102       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8103     }
8104   else
8105     {
8106       /* Distribute the first term.  */
8107       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8108       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8109     }
8110
8111   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8112                                                      new_op0, new_op1));
8113   if (GET_CODE (tmp) != outer_code
8114       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8115     return tmp;
8116
8117   return NULL_RTX;
8118 }
8119 \f
8120 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8121    in MODE.  Return an equivalent form, if different from (and VAROP
8122    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8123
8124 static rtx
8125 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8126                           unsigned HOST_WIDE_INT constop)
8127 {
8128   unsigned HOST_WIDE_INT nonzero;
8129   unsigned HOST_WIDE_INT orig_constop;
8130   rtx orig_varop;
8131   int i;
8132
8133   orig_varop = varop;
8134   orig_constop = constop;
8135   if (GET_CODE (varop) == CLOBBER)
8136     return NULL_RTX;
8137
8138   /* Simplify VAROP knowing that we will be only looking at some of the
8139      bits in it.
8140
8141      Note by passing in CONSTOP, we guarantee that the bits not set in
8142      CONSTOP are not significant and will never be examined.  We must
8143      ensure that is the case by explicitly masking out those bits
8144      before returning.  */
8145   varop = force_to_mode (varop, mode, constop, 0);
8146
8147   /* If VAROP is a CLOBBER, we will fail so return it.  */
8148   if (GET_CODE (varop) == CLOBBER)
8149     return varop;
8150
8151   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8152      to VAROP and return the new constant.  */
8153   if (GET_CODE (varop) == CONST_INT)
8154     return gen_int_mode (INTVAL (varop) & constop, mode);
8155
8156   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8157      a call to nonzero_bits, here we don't care about bits outside
8158      MODE.  */
8159
8160   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8161
8162   /* Turn off all bits in the constant that are known to already be zero.
8163      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8164      which is tested below.  */
8165
8166   constop &= nonzero;
8167
8168   /* If we don't have any bits left, return zero.  */
8169   if (constop == 0)
8170     return const0_rtx;
8171
8172   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8173      a power of two, we can replace this with an ASHIFT.  */
8174   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8175       && (i = exact_log2 (constop)) >= 0)
8176     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8177
8178   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8179      or XOR, then try to apply the distributive law.  This may eliminate
8180      operations if either branch can be simplified because of the AND.
8181      It may also make some cases more complex, but those cases probably
8182      won't match a pattern either with or without this.  */
8183
8184   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8185     return
8186       gen_lowpart
8187         (mode,
8188          apply_distributive_law
8189          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8190                                simplify_and_const_int (NULL_RTX,
8191                                                        GET_MODE (varop),
8192                                                        XEXP (varop, 0),
8193                                                        constop),
8194                                simplify_and_const_int (NULL_RTX,
8195                                                        GET_MODE (varop),
8196                                                        XEXP (varop, 1),
8197                                                        constop))));
8198
8199   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8200      the AND and see if one of the operands simplifies to zero.  If so, we
8201      may eliminate it.  */
8202
8203   if (GET_CODE (varop) == PLUS
8204       && exact_log2 (constop + 1) >= 0)
8205     {
8206       rtx o0, o1;
8207
8208       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8209       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8210       if (o0 == const0_rtx)
8211         return o1;
8212       if (o1 == const0_rtx)
8213         return o0;
8214     }
8215
8216   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8217   varop = gen_lowpart (mode, varop);
8218   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8219     return NULL_RTX;
8220
8221   /* If we are only masking insignificant bits, return VAROP.  */
8222   if (constop == nonzero)
8223     return varop;
8224
8225   if (varop == orig_varop && constop == orig_constop)
8226     return NULL_RTX;
8227
8228   /* Otherwise, return an AND.  */
8229   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8230 }
8231
8232
8233 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8234    in MODE.
8235
8236    Return an equivalent form, if different from X.  Otherwise, return X.  If
8237    X is zero, we are to always construct the equivalent form.  */
8238
8239 static rtx
8240 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8241                         unsigned HOST_WIDE_INT constop)
8242 {
8243   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8244   if (tem)
8245     return tem;
8246
8247   if (!x)
8248     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8249                              gen_int_mode (constop, mode));
8250   if (GET_MODE (x) != mode)
8251     x = gen_lowpart (mode, x);
8252   return x;
8253 }
8254 \f
8255 /* Given a REG, X, compute which bits in X can be nonzero.
8256    We don't care about bits outside of those defined in MODE.
8257
8258    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8259    a shift, AND, or zero_extract, we can do better.  */
8260
8261 static rtx
8262 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8263                               rtx known_x ATTRIBUTE_UNUSED,
8264                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8265                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8266                               unsigned HOST_WIDE_INT *nonzero)
8267 {
8268   rtx tem;
8269
8270   /* If X is a register whose nonzero bits value is current, use it.
8271      Otherwise, if X is a register whose value we can find, use that
8272      value.  Otherwise, use the previously-computed global nonzero bits
8273      for this register.  */
8274
8275   if (reg_stat[REGNO (x)].last_set_value != 0
8276       && (reg_stat[REGNO (x)].last_set_mode == mode
8277           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8278               && GET_MODE_CLASS (mode) == MODE_INT))
8279       && (reg_stat[REGNO (x)].last_set_label == label_tick
8280           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8281               && REG_N_SETS (REGNO (x)) == 1
8282               && ! REGNO_REG_SET_P
8283                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8284                   REGNO (x))))
8285       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8286     {
8287       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8288       return NULL;
8289     }
8290
8291   tem = get_last_value (x);
8292
8293   if (tem)
8294     {
8295 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8296       /* If X is narrower than MODE and TEM is a non-negative
8297          constant that would appear negative in the mode of X,
8298          sign-extend it for use in reg_nonzero_bits because some
8299          machines (maybe most) will actually do the sign-extension
8300          and this is the conservative approach.
8301
8302          ??? For 2.5, try to tighten up the MD files in this regard
8303          instead of this kludge.  */
8304
8305       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8306           && GET_CODE (tem) == CONST_INT
8307           && INTVAL (tem) > 0
8308           && 0 != (INTVAL (tem)
8309                    & ((HOST_WIDE_INT) 1
8310                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8311         tem = GEN_INT (INTVAL (tem)
8312                        | ((HOST_WIDE_INT) (-1)
8313                           << GET_MODE_BITSIZE (GET_MODE (x))));
8314 #endif
8315       return tem;
8316     }
8317   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8318     {
8319       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8320
8321       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8322         /* We don't know anything about the upper bits.  */
8323         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8324       *nonzero &= mask;
8325     }
8326
8327   return NULL;
8328 }
8329
8330 /* Return the number of bits at the high-order end of X that are known to
8331    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8332    VOIDmode, X will be used in its own mode.  The returned value  will always
8333    be between 1 and the number of bits in MODE.  */
8334
8335 static rtx
8336 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8337                                      rtx known_x ATTRIBUTE_UNUSED,
8338                                      enum machine_mode known_mode
8339                                      ATTRIBUTE_UNUSED,
8340                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8341                                      unsigned int *result)
8342 {
8343   rtx tem;
8344
8345   if (reg_stat[REGNO (x)].last_set_value != 0
8346       && reg_stat[REGNO (x)].last_set_mode == mode
8347       && (reg_stat[REGNO (x)].last_set_label == label_tick
8348           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8349               && REG_N_SETS (REGNO (x)) == 1
8350               && ! REGNO_REG_SET_P
8351                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8352                   REGNO (x))))
8353       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8354     {
8355       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8356       return NULL;
8357     }
8358
8359   tem = get_last_value (x);
8360   if (tem != 0)
8361     return tem;
8362
8363   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8364       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8365     *result = reg_stat[REGNO (x)].sign_bit_copies;
8366
8367   return NULL;
8368 }
8369 \f
8370 /* Return the number of "extended" bits there are in X, when interpreted
8371    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8372    unsigned quantities, this is the number of high-order zero bits.
8373    For signed quantities, this is the number of copies of the sign bit
8374    minus 1.  In both case, this function returns the number of "spare"
8375    bits.  For example, if two quantities for which this function returns
8376    at least 1 are added, the addition is known not to overflow.
8377
8378    This function will always return 0 unless called during combine, which
8379    implies that it must be called from a define_split.  */
8380
8381 unsigned int
8382 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8383 {
8384   if (nonzero_sign_valid == 0)
8385     return 0;
8386
8387   return (unsignedp
8388           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8389              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8390                                - floor_log2 (nonzero_bits (x, mode)))
8391              : 0)
8392           : num_sign_bit_copies (x, mode) - 1);
8393 }
8394 \f
8395 /* This function is called from `simplify_shift_const' to merge two
8396    outer operations.  Specifically, we have already found that we need
8397    to perform operation *POP0 with constant *PCONST0 at the outermost
8398    position.  We would now like to also perform OP1 with constant CONST1
8399    (with *POP0 being done last).
8400
8401    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8402    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8403    complement the innermost operand, otherwise it is unchanged.
8404
8405    MODE is the mode in which the operation will be done.  No bits outside
8406    the width of this mode matter.  It is assumed that the width of this mode
8407    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8408
8409    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8410    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8411    result is simply *PCONST0.
8412
8413    If the resulting operation cannot be expressed as one operation, we
8414    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8415
8416 static int
8417 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8418 {
8419   enum rtx_code op0 = *pop0;
8420   HOST_WIDE_INT const0 = *pconst0;
8421
8422   const0 &= GET_MODE_MASK (mode);
8423   const1 &= GET_MODE_MASK (mode);
8424
8425   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8426   if (op0 == AND)
8427     const1 &= const0;
8428
8429   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8430      if OP0 is SET.  */
8431
8432   if (op1 == UNKNOWN || op0 == SET)
8433     return 1;
8434
8435   else if (op0 == UNKNOWN)
8436     op0 = op1, const0 = const1;
8437
8438   else if (op0 == op1)
8439     {
8440       switch (op0)
8441         {
8442         case AND:
8443           const0 &= const1;
8444           break;
8445         case IOR:
8446           const0 |= const1;
8447           break;
8448         case XOR:
8449           const0 ^= const1;
8450           break;
8451         case PLUS:
8452           const0 += const1;
8453           break;
8454         case NEG:
8455           op0 = UNKNOWN;
8456           break;
8457         default:
8458           break;
8459         }
8460     }
8461
8462   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8463   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8464     return 0;
8465
8466   /* If the two constants aren't the same, we can't do anything.  The
8467      remaining six cases can all be done.  */
8468   else if (const0 != const1)
8469     return 0;
8470
8471   else
8472     switch (op0)
8473       {
8474       case IOR:
8475         if (op1 == AND)
8476           /* (a & b) | b == b */
8477           op0 = SET;
8478         else /* op1 == XOR */
8479           /* (a ^ b) | b == a | b */
8480           {;}
8481         break;
8482
8483       case XOR:
8484         if (op1 == AND)
8485           /* (a & b) ^ b == (~a) & b */
8486           op0 = AND, *pcomp_p = 1;
8487         else /* op1 == IOR */
8488           /* (a | b) ^ b == a & ~b */
8489           op0 = AND, const0 = ~const0;
8490         break;
8491
8492       case AND:
8493         if (op1 == IOR)
8494           /* (a | b) & b == b */
8495         op0 = SET;
8496         else /* op1 == XOR */
8497           /* (a ^ b) & b) == (~a) & b */
8498           *pcomp_p = 1;
8499         break;
8500       default:
8501         break;
8502       }
8503
8504   /* Check for NO-OP cases.  */
8505   const0 &= GET_MODE_MASK (mode);
8506   if (const0 == 0
8507       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8508     op0 = UNKNOWN;
8509   else if (const0 == 0 && op0 == AND)
8510     op0 = SET;
8511   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8512            && op0 == AND)
8513     op0 = UNKNOWN;
8514
8515   /* ??? Slightly redundant with the above mask, but not entirely.
8516      Moving this above means we'd have to sign-extend the mode mask
8517      for the final test.  */
8518   const0 = trunc_int_for_mode (const0, mode);
8519
8520   *pop0 = op0;
8521   *pconst0 = const0;
8522
8523   return 1;
8524 }
8525 \f
8526 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8527    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8528    simplify it.  Otherwise, return a simplified value.
8529
8530    The shift is normally computed in the widest mode we find in VAROP, as
8531    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8532    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8533
8534 static rtx
8535 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8536                         rtx varop, int orig_count)
8537 {
8538   enum rtx_code orig_code = code;
8539   rtx orig_varop = varop;
8540   int count;
8541   enum machine_mode mode = result_mode;
8542   enum machine_mode shift_mode, tmode;
8543   unsigned int mode_words
8544     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8545   /* We form (outer_op (code varop count) (outer_const)).  */
8546   enum rtx_code outer_op = UNKNOWN;
8547   HOST_WIDE_INT outer_const = 0;
8548   int complement_p = 0;
8549   rtx new, x;
8550
8551   /* Make sure and truncate the "natural" shift on the way in.  We don't
8552      want to do this inside the loop as it makes it more difficult to
8553      combine shifts.  */
8554   if (SHIFT_COUNT_TRUNCATED)
8555     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8556
8557   /* If we were given an invalid count, don't do anything except exactly
8558      what was requested.  */
8559
8560   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8561     return NULL_RTX;
8562
8563   count = orig_count;
8564
8565   /* Unless one of the branches of the `if' in this loop does a `continue',
8566      we will `break' the loop after the `if'.  */
8567
8568   while (count != 0)
8569     {
8570       /* If we have an operand of (clobber (const_int 0)), fail.  */
8571       if (GET_CODE (varop) == CLOBBER)
8572         return NULL_RTX;
8573
8574       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8575          here would cause an infinite loop.  */
8576       if (complement_p)
8577         break;
8578
8579       /* Convert ROTATERT to ROTATE.  */
8580       if (code == ROTATERT)
8581         {
8582           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8583           code = ROTATE;
8584           if (VECTOR_MODE_P (result_mode))
8585             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8586           else
8587             count = bitsize - count;
8588         }
8589
8590       /* We need to determine what mode we will do the shift in.  If the
8591          shift is a right shift or a ROTATE, we must always do it in the mode
8592          it was originally done in.  Otherwise, we can do it in MODE, the
8593          widest mode encountered.  */
8594       shift_mode
8595         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8596            ? result_mode : mode);
8597
8598       /* Handle cases where the count is greater than the size of the mode
8599          minus 1.  For ASHIFT, use the size minus one as the count (this can
8600          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8601          take the count modulo the size.  For other shifts, the result is
8602          zero.
8603
8604          Since these shifts are being produced by the compiler by combining
8605          multiple operations, each of which are defined, we know what the
8606          result is supposed to be.  */
8607
8608       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8609         {
8610           if (code == ASHIFTRT)
8611             count = GET_MODE_BITSIZE (shift_mode) - 1;
8612           else if (code == ROTATE || code == ROTATERT)
8613             count %= GET_MODE_BITSIZE (shift_mode);
8614           else
8615             {
8616               /* We can't simply return zero because there may be an
8617                  outer op.  */
8618               varop = const0_rtx;
8619               count = 0;
8620               break;
8621             }
8622         }
8623
8624       /* An arithmetic right shift of a quantity known to be -1 or 0
8625          is a no-op.  */
8626       if (code == ASHIFTRT
8627           && (num_sign_bit_copies (varop, shift_mode)
8628               == GET_MODE_BITSIZE (shift_mode)))
8629         {
8630           count = 0;
8631           break;
8632         }
8633
8634       /* If we are doing an arithmetic right shift and discarding all but
8635          the sign bit copies, this is equivalent to doing a shift by the
8636          bitsize minus one.  Convert it into that shift because it will often
8637          allow other simplifications.  */
8638
8639       if (code == ASHIFTRT
8640           && (count + num_sign_bit_copies (varop, shift_mode)
8641               >= GET_MODE_BITSIZE (shift_mode)))
8642         count = GET_MODE_BITSIZE (shift_mode) - 1;
8643
8644       /* We simplify the tests below and elsewhere by converting
8645          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8646          `make_compound_operation' will convert it to an ASHIFTRT for
8647          those machines (such as VAX) that don't have an LSHIFTRT.  */
8648       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8649           && code == ASHIFTRT
8650           && ((nonzero_bits (varop, shift_mode)
8651                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8652               == 0))
8653         code = LSHIFTRT;
8654
8655       if (((code == LSHIFTRT
8656             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8657             && !(nonzero_bits (varop, shift_mode) >> count))
8658            || (code == ASHIFT
8659                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8660                && !((nonzero_bits (varop, shift_mode) << count)
8661                     & GET_MODE_MASK (shift_mode))))
8662           && !side_effects_p (varop))
8663         varop = const0_rtx;
8664
8665       switch (GET_CODE (varop))
8666         {
8667         case SIGN_EXTEND:
8668         case ZERO_EXTEND:
8669         case SIGN_EXTRACT:
8670         case ZERO_EXTRACT:
8671           new = expand_compound_operation (varop);
8672           if (new != varop)
8673             {
8674               varop = new;
8675               continue;
8676             }
8677           break;
8678
8679         case MEM:
8680           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8681              minus the width of a smaller mode, we can do this with a
8682              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8683           if ((code == ASHIFTRT || code == LSHIFTRT)
8684               && ! mode_dependent_address_p (XEXP (varop, 0))
8685               && ! MEM_VOLATILE_P (varop)
8686               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8687                                          MODE_INT, 1)) != BLKmode)
8688             {
8689               new = adjust_address_nv (varop, tmode,
8690                                        BYTES_BIG_ENDIAN ? 0
8691                                        : count / BITS_PER_UNIT);
8692
8693               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8694                                      : ZERO_EXTEND, mode, new);
8695               count = 0;
8696               continue;
8697             }
8698           break;
8699
8700         case SUBREG:
8701           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8702              the same number of words as what we've seen so far.  Then store
8703              the widest mode in MODE.  */
8704           if (subreg_lowpart_p (varop)
8705               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8706                   > GET_MODE_SIZE (GET_MODE (varop)))
8707               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8708                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8709                  == mode_words)
8710             {
8711               varop = SUBREG_REG (varop);
8712               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8713                 mode = GET_MODE (varop);
8714               continue;
8715             }
8716           break;
8717
8718         case MULT:
8719           /* Some machines use MULT instead of ASHIFT because MULT
8720              is cheaper.  But it is still better on those machines to
8721              merge two shifts into one.  */
8722           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8723               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8724             {
8725               varop
8726                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8727                                        XEXP (varop, 0),
8728                                        GEN_INT (exact_log2 (
8729                                                 INTVAL (XEXP (varop, 1)))));
8730               continue;
8731             }
8732           break;
8733
8734         case UDIV:
8735           /* Similar, for when divides are cheaper.  */
8736           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8737               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8738             {
8739               varop
8740                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8741                                        XEXP (varop, 0),
8742                                        GEN_INT (exact_log2 (
8743                                                 INTVAL (XEXP (varop, 1)))));
8744               continue;
8745             }
8746           break;
8747
8748         case ASHIFTRT:
8749           /* If we are extracting just the sign bit of an arithmetic
8750              right shift, that shift is not needed.  However, the sign
8751              bit of a wider mode may be different from what would be
8752              interpreted as the sign bit in a narrower mode, so, if
8753              the result is narrower, don't discard the shift.  */
8754           if (code == LSHIFTRT
8755               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8756               && (GET_MODE_BITSIZE (result_mode)
8757                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8758             {
8759               varop = XEXP (varop, 0);
8760               continue;
8761             }
8762
8763           /* ... fall through ...  */
8764
8765         case LSHIFTRT:
8766         case ASHIFT:
8767         case ROTATE:
8768           /* Here we have two nested shifts.  The result is usually the
8769              AND of a new shift with a mask.  We compute the result below.  */
8770           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8771               && INTVAL (XEXP (varop, 1)) >= 0
8772               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8773               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8774               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8775               && !VECTOR_MODE_P (result_mode))
8776             {
8777               enum rtx_code first_code = GET_CODE (varop);
8778               unsigned int first_count = INTVAL (XEXP (varop, 1));
8779               unsigned HOST_WIDE_INT mask;
8780               rtx mask_rtx;
8781
8782               /* We have one common special case.  We can't do any merging if
8783                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8784                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8785                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8786                  we can convert it to
8787                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8788                  This simplifies certain SIGN_EXTEND operations.  */
8789               if (code == ASHIFT && first_code == ASHIFTRT
8790                   && count == (GET_MODE_BITSIZE (result_mode)
8791                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8792                 {
8793                   /* C3 has the low-order C1 bits zero.  */
8794
8795                   mask = (GET_MODE_MASK (mode)
8796                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8797
8798                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8799                                                   XEXP (varop, 0), mask);
8800                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8801                                                 varop, count);
8802                   count = first_count;
8803                   code = ASHIFTRT;
8804                   continue;
8805                 }
8806
8807               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8808                  than C1 high-order bits equal to the sign bit, we can convert
8809                  this to either an ASHIFT or an ASHIFTRT depending on the
8810                  two counts.
8811
8812                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8813
8814               if (code == ASHIFTRT && first_code == ASHIFT
8815                   && GET_MODE (varop) == shift_mode
8816                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8817                       > first_count))
8818                 {
8819                   varop = XEXP (varop, 0);
8820                   count -= first_count;
8821                   if (count < 0)
8822                     {
8823                       count = -count;
8824                       code = ASHIFT;
8825                     }
8826
8827                   continue;
8828                 }
8829
8830               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8831                  we can only do this if FIRST_CODE is also ASHIFTRT.
8832
8833                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8834                  ASHIFTRT.
8835
8836                  If the mode of this shift is not the mode of the outer shift,
8837                  we can't do this if either shift is a right shift or ROTATE.
8838
8839                  Finally, we can't do any of these if the mode is too wide
8840                  unless the codes are the same.
8841
8842                  Handle the case where the shift codes are the same
8843                  first.  */
8844
8845               if (code == first_code)
8846                 {
8847                   if (GET_MODE (varop) != result_mode
8848                       && (code == ASHIFTRT || code == LSHIFTRT
8849                           || code == ROTATE))
8850                     break;
8851
8852                   count += first_count;
8853                   varop = XEXP (varop, 0);
8854                   continue;
8855                 }
8856
8857               if (code == ASHIFTRT
8858                   || (code == ROTATE && first_code == ASHIFTRT)
8859                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8860                   || (GET_MODE (varop) != result_mode
8861                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8862                           || first_code == ROTATE
8863                           || code == ROTATE)))
8864                 break;
8865
8866               /* To compute the mask to apply after the shift, shift the
8867                  nonzero bits of the inner shift the same way the
8868                  outer shift will.  */
8869
8870               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8871
8872               mask_rtx
8873                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8874                                                    GEN_INT (count));
8875
8876               /* Give up if we can't compute an outer operation to use.  */
8877               if (mask_rtx == 0
8878                   || GET_CODE (mask_rtx) != CONST_INT
8879                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8880                                         INTVAL (mask_rtx),
8881                                         result_mode, &complement_p))
8882                 break;
8883
8884               /* If the shifts are in the same direction, we add the
8885                  counts.  Otherwise, we subtract them.  */
8886               if ((code == ASHIFTRT || code == LSHIFTRT)
8887                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8888                 count += first_count;
8889               else
8890                 count -= first_count;
8891
8892               /* If COUNT is positive, the new shift is usually CODE,
8893                  except for the two exceptions below, in which case it is
8894                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8895                  always be used  */
8896               if (count > 0
8897                   && ((first_code == ROTATE && code == ASHIFT)
8898                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8899                 code = first_code;
8900               else if (count < 0)
8901                 code = first_code, count = -count;
8902
8903               varop = XEXP (varop, 0);
8904               continue;
8905             }
8906
8907           /* If we have (A << B << C) for any shift, we can convert this to
8908              (A << C << B).  This wins if A is a constant.  Only try this if
8909              B is not a constant.  */
8910
8911           else if (GET_CODE (varop) == code
8912                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8913                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8914             {
8915               rtx new = simplify_const_binary_operation (code, mode,
8916                                                          XEXP (varop, 0),
8917                                                          GEN_INT (count));
8918               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8919               count = 0;
8920               continue;
8921             }
8922           break;
8923
8924         case NOT:
8925           /* Make this fit the case below.  */
8926           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8927                                GEN_INT (GET_MODE_MASK (mode)));
8928           continue;
8929
8930         case IOR:
8931         case AND:
8932         case XOR:
8933           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8934              with C the size of VAROP - 1 and the shift is logical if
8935              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8936              we have an (le X 0) operation.   If we have an arithmetic shift
8937              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8938              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8939
8940           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8941               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8942               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8943               && (code == LSHIFTRT || code == ASHIFTRT)
8944               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8945               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8946             {
8947               count = 0;
8948               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8949                                   const0_rtx);
8950
8951               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8952                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8953
8954               continue;
8955             }
8956
8957           /* If we have (shift (logical)), move the logical to the outside
8958              to allow it to possibly combine with another logical and the
8959              shift to combine with another shift.  This also canonicalizes to
8960              what a ZERO_EXTRACT looks like.  Also, some machines have
8961              (and (shift)) insns.  */
8962
8963           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8964               /* We can't do this if we have (ashiftrt (xor))  and the
8965                  constant has its sign bit set in shift_mode.  */
8966               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8967                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8968                                               shift_mode))
8969               && (new = simplify_const_binary_operation (code, result_mode,
8970                                                          XEXP (varop, 1),
8971                                                          GEN_INT (count))) != 0
8972               && GET_CODE (new) == CONST_INT
8973               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8974                                   INTVAL (new), result_mode, &complement_p))
8975             {
8976               varop = XEXP (varop, 0);
8977               continue;
8978             }
8979
8980           /* If we can't do that, try to simplify the shift in each arm of the
8981              logical expression, make a new logical expression, and apply
8982              the inverse distributive law.  This also can't be done
8983              for some (ashiftrt (xor)).  */
8984           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8985              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8986                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8987                                              shift_mode)))
8988             {
8989               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8990                                               XEXP (varop, 0), count);
8991               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8992                                               XEXP (varop, 1), count);
8993
8994               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8995                                            lhs, rhs);
8996               varop = apply_distributive_law (varop);
8997
8998               count = 0;
8999               continue;
9000             }
9001           break;
9002
9003         case EQ:
9004           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9005              says that the sign bit can be tested, FOO has mode MODE, C is
9006              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9007              that may be nonzero.  */
9008           if (code == LSHIFTRT
9009               && XEXP (varop, 1) == const0_rtx
9010               && GET_MODE (XEXP (varop, 0)) == result_mode
9011               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9012               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9013               && STORE_FLAG_VALUE == -1
9014               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9015               && merge_outer_ops (&outer_op, &outer_const, XOR,
9016                                   (HOST_WIDE_INT) 1, result_mode,
9017                                   &complement_p))
9018             {
9019               varop = XEXP (varop, 0);
9020               count = 0;
9021               continue;
9022             }
9023           break;
9024
9025         case NEG:
9026           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9027              than the number of bits in the mode is equivalent to A.  */
9028           if (code == LSHIFTRT
9029               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9030               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9031             {
9032               varop = XEXP (varop, 0);
9033               count = 0;
9034               continue;
9035             }
9036
9037           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9038              NEG outside to allow shifts to combine.  */
9039           if (code == ASHIFT
9040               && merge_outer_ops (&outer_op, &outer_const, NEG,
9041                                   (HOST_WIDE_INT) 0, result_mode,
9042                                   &complement_p))
9043             {
9044               varop = XEXP (varop, 0);
9045               continue;
9046             }
9047           break;
9048
9049         case PLUS:
9050           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9051              is one less than the number of bits in the mode is
9052              equivalent to (xor A 1).  */
9053           if (code == LSHIFTRT
9054               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9055               && XEXP (varop, 1) == constm1_rtx
9056               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9057               && merge_outer_ops (&outer_op, &outer_const, XOR,
9058                                   (HOST_WIDE_INT) 1, result_mode,
9059                                   &complement_p))
9060             {
9061               count = 0;
9062               varop = XEXP (varop, 0);
9063               continue;
9064             }
9065
9066           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9067              that might be nonzero in BAR are those being shifted out and those
9068              bits are known zero in FOO, we can replace the PLUS with FOO.
9069              Similarly in the other operand order.  This code occurs when
9070              we are computing the size of a variable-size array.  */
9071
9072           if ((code == ASHIFTRT || code == LSHIFTRT)
9073               && count < HOST_BITS_PER_WIDE_INT
9074               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9075               && (nonzero_bits (XEXP (varop, 1), result_mode)
9076                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9077             {
9078               varop = XEXP (varop, 0);
9079               continue;
9080             }
9081           else if ((code == ASHIFTRT || code == LSHIFTRT)
9082                    && count < HOST_BITS_PER_WIDE_INT
9083                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9084                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9085                             >> count)
9086                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9087                             & nonzero_bits (XEXP (varop, 1),
9088                                                  result_mode)))
9089             {
9090               varop = XEXP (varop, 1);
9091               continue;
9092             }
9093
9094           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9095           if (code == ASHIFT
9096               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9097               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9098                                                          XEXP (varop, 1),
9099                                                          GEN_INT (count))) != 0
9100               && GET_CODE (new) == CONST_INT
9101               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9102                                   INTVAL (new), result_mode, &complement_p))
9103             {
9104               varop = XEXP (varop, 0);
9105               continue;
9106             }
9107
9108           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9109              signbit', and attempt to change the PLUS to an XOR and move it to
9110              the outer operation as is done above in the AND/IOR/XOR case
9111              leg for shift(logical). See details in logical handling above
9112              for reasoning in doing so.  */
9113           if (code == LSHIFTRT
9114               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9115               && mode_signbit_p (result_mode, XEXP (varop, 1))
9116               && (new = simplify_const_binary_operation (code, result_mode,
9117                                                          XEXP (varop, 1),
9118                                                          GEN_INT (count))) != 0
9119               && GET_CODE (new) == CONST_INT
9120               && merge_outer_ops (&outer_op, &outer_const, XOR,
9121                                   INTVAL (new), result_mode, &complement_p))
9122             {
9123               varop = XEXP (varop, 0);
9124               continue;
9125             }
9126
9127           break;
9128
9129         case MINUS:
9130           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9131              with C the size of VAROP - 1 and the shift is logical if
9132              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9133              we have a (gt X 0) operation.  If the shift is arithmetic with
9134              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9135              we have a (neg (gt X 0)) operation.  */
9136
9137           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9138               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9139               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9140               && (code == LSHIFTRT || code == ASHIFTRT)
9141               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9142               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9143               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9144             {
9145               count = 0;
9146               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9147                                   const0_rtx);
9148
9149               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9150                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9151
9152               continue;
9153             }
9154           break;
9155
9156         case TRUNCATE:
9157           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9158              if the truncate does not affect the value.  */
9159           if (code == LSHIFTRT
9160               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9161               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9162               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9163                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9164                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9165             {
9166               rtx varop_inner = XEXP (varop, 0);
9167
9168               varop_inner
9169                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9170                                     XEXP (varop_inner, 0),
9171                                     GEN_INT
9172                                     (count + INTVAL (XEXP (varop_inner, 1))));
9173               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9174               count = 0;
9175               continue;
9176             }
9177           break;
9178
9179         default:
9180           break;
9181         }
9182
9183       break;
9184     }
9185
9186   /* We need to determine what mode to do the shift in.  If the shift is
9187      a right shift or ROTATE, we must always do it in the mode it was
9188      originally done in.  Otherwise, we can do it in MODE, the widest mode
9189      encountered.  The code we care about is that of the shift that will
9190      actually be done, not the shift that was originally requested.  */
9191   shift_mode
9192     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9193        ? result_mode : mode);
9194
9195   /* We have now finished analyzing the shift.  The result should be
9196      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9197      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9198      to the result of the shift.  OUTER_CONST is the relevant constant,
9199      but we must turn off all bits turned off in the shift.  */
9200
9201   if (outer_op == UNKNOWN
9202       && orig_code == code && orig_count == count
9203       && varop == orig_varop
9204       && shift_mode == GET_MODE (varop))
9205     return NULL_RTX;
9206
9207   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9208   varop = gen_lowpart (shift_mode, varop);
9209   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9210     return NULL_RTX;
9211
9212   /* If we have an outer operation and we just made a shift, it is
9213      possible that we could have simplified the shift were it not
9214      for the outer operation.  So try to do the simplification
9215      recursively.  */
9216
9217   if (outer_op != UNKNOWN)
9218     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9219   else
9220     x = NULL_RTX;
9221
9222   if (x == NULL_RTX)
9223     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9224
9225   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9226      turn off all the bits that the shift would have turned off.  */
9227   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9228     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9229                                 GET_MODE_MASK (result_mode) >> orig_count);
9230
9231   /* Do the remainder of the processing in RESULT_MODE.  */
9232   x = gen_lowpart_or_truncate (result_mode, x);
9233
9234   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9235      operation.  */
9236   if (complement_p)
9237     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9238
9239   if (outer_op != UNKNOWN)
9240     {
9241       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9242         outer_const = trunc_int_for_mode (outer_const, result_mode);
9243
9244       if (outer_op == AND)
9245         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9246       else if (outer_op == SET)
9247         {
9248           /* This means that we have determined that the result is
9249              equivalent to a constant.  This should be rare.  */
9250           if (!side_effects_p (x))
9251             x = GEN_INT (outer_const);
9252         }
9253       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9254         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9255       else
9256         x = simplify_gen_binary (outer_op, result_mode, x,
9257                                  GEN_INT (outer_const));
9258     }
9259
9260   return x;
9261 }
9262
9263 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9264    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9265    return X or, if it is NULL, synthesize the expression with
9266    simplify_gen_binary.  Otherwise, return a simplified value.
9267
9268    The shift is normally computed in the widest mode we find in VAROP, as
9269    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9270    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9271
9272 static rtx
9273 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9274                       rtx varop, int count)
9275 {
9276   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9277   if (tem)
9278     return tem;
9279
9280   if (!x)
9281     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9282   if (GET_MODE (x) != result_mode)
9283     x = gen_lowpart (result_mode, x);
9284   return x;
9285 }
9286
9287 \f
9288 /* Like recog, but we receive the address of a pointer to a new pattern.
9289    We try to match the rtx that the pointer points to.
9290    If that fails, we may try to modify or replace the pattern,
9291    storing the replacement into the same pointer object.
9292
9293    Modifications include deletion or addition of CLOBBERs.
9294
9295    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9296    the CLOBBERs are placed.
9297
9298    The value is the final insn code from the pattern ultimately matched,
9299    or -1.  */
9300
9301 static int
9302 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9303 {
9304   rtx pat = *pnewpat;
9305   int insn_code_number;
9306   int num_clobbers_to_add = 0;
9307   int i;
9308   rtx notes = 0;
9309   rtx old_notes, old_pat;
9310
9311   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9312      we use to indicate that something didn't match.  If we find such a
9313      thing, force rejection.  */
9314   if (GET_CODE (pat) == PARALLEL)
9315     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9316       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9317           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9318         return -1;
9319
9320   old_pat = PATTERN (insn);
9321   old_notes = REG_NOTES (insn);
9322   PATTERN (insn) = pat;
9323   REG_NOTES (insn) = 0;
9324
9325   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9326
9327   /* If it isn't, there is the possibility that we previously had an insn
9328      that clobbered some register as a side effect, but the combined
9329      insn doesn't need to do that.  So try once more without the clobbers
9330      unless this represents an ASM insn.  */
9331
9332   if (insn_code_number < 0 && ! check_asm_operands (pat)
9333       && GET_CODE (pat) == PARALLEL)
9334     {
9335       int pos;
9336
9337       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9338         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9339           {
9340             if (i != pos)
9341               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9342             pos++;
9343           }
9344
9345       SUBST_INT (XVECLEN (pat, 0), pos);
9346
9347       if (pos == 1)
9348         pat = XVECEXP (pat, 0, 0);
9349
9350       PATTERN (insn) = pat;
9351       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9352     }
9353   PATTERN (insn) = old_pat;
9354   REG_NOTES (insn) = old_notes;
9355
9356   /* Recognize all noop sets, these will be killed by followup pass.  */
9357   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9358     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9359
9360   /* If we had any clobbers to add, make a new pattern than contains
9361      them.  Then check to make sure that all of them are dead.  */
9362   if (num_clobbers_to_add)
9363     {
9364       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9365                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9366                                                   ? (XVECLEN (pat, 0)
9367                                                      + num_clobbers_to_add)
9368                                                   : num_clobbers_to_add + 1));
9369
9370       if (GET_CODE (pat) == PARALLEL)
9371         for (i = 0; i < XVECLEN (pat, 0); i++)
9372           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9373       else
9374         XVECEXP (newpat, 0, 0) = pat;
9375
9376       add_clobbers (newpat, insn_code_number);
9377
9378       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9379            i < XVECLEN (newpat, 0); i++)
9380         {
9381           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9382               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9383             return -1;
9384           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9385                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9386         }
9387       pat = newpat;
9388     }
9389
9390   *pnewpat = pat;
9391   *pnotes = notes;
9392
9393   return insn_code_number;
9394 }
9395 \f
9396 /* Like gen_lowpart_general but for use by combine.  In combine it
9397    is not possible to create any new pseudoregs.  However, it is
9398    safe to create invalid memory addresses, because combine will
9399    try to recognize them and all they will do is make the combine
9400    attempt fail.
9401
9402    If for some reason this cannot do its job, an rtx
9403    (clobber (const_int 0)) is returned.
9404    An insn containing that will not be recognized.  */
9405
9406 static rtx
9407 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9408 {
9409   enum machine_mode imode = GET_MODE (x);
9410   unsigned int osize = GET_MODE_SIZE (omode);
9411   unsigned int isize = GET_MODE_SIZE (imode);
9412   rtx result;
9413
9414   if (omode == imode)
9415     return x;
9416
9417   /* Return identity if this is a CONST or symbolic reference.  */
9418   if (omode == Pmode
9419       && (GET_CODE (x) == CONST
9420           || GET_CODE (x) == SYMBOL_REF
9421           || GET_CODE (x) == LABEL_REF))
9422     return x;
9423
9424   /* We can only support MODE being wider than a word if X is a
9425      constant integer or has a mode the same size.  */
9426   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9427       && ! ((imode == VOIDmode
9428              && (GET_CODE (x) == CONST_INT
9429                  || GET_CODE (x) == CONST_DOUBLE))
9430             || isize == osize))
9431     goto fail;
9432
9433   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9434      won't know what to do.  So we will strip off the SUBREG here and
9435      process normally.  */
9436   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9437     {
9438       x = SUBREG_REG (x);
9439
9440       /* For use in case we fall down into the address adjustments
9441          further below, we need to adjust the known mode and size of
9442          x; imode and isize, since we just adjusted x.  */
9443       imode = GET_MODE (x);
9444
9445       if (imode == omode)
9446         return x;
9447
9448       isize = GET_MODE_SIZE (imode);
9449     }
9450
9451   result = gen_lowpart_common (omode, x);
9452
9453 #ifdef CANNOT_CHANGE_MODE_CLASS
9454   if (result != 0 && GET_CODE (result) == SUBREG)
9455     record_subregs_of_mode (result);
9456 #endif
9457
9458   if (result)
9459     return result;
9460
9461   if (MEM_P (x))
9462     {
9463       int offset = 0;
9464
9465       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9466          address.  */
9467       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9468         goto fail;
9469
9470       /* If we want to refer to something bigger than the original memref,
9471          generate a paradoxical subreg instead.  That will force a reload
9472          of the original memref X.  */
9473       if (isize < osize)
9474         return gen_rtx_SUBREG (omode, x, 0);
9475
9476       if (WORDS_BIG_ENDIAN)
9477         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9478
9479       /* Adjust the address so that the address-after-the-data is
9480          unchanged.  */
9481       if (BYTES_BIG_ENDIAN)
9482         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9483
9484       return adjust_address_nv (x, omode, offset);
9485     }
9486
9487   /* If X is a comparison operator, rewrite it in a new mode.  This
9488      probably won't match, but may allow further simplifications.  */
9489   else if (COMPARISON_P (x))
9490     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9491
9492   /* If we couldn't simplify X any other way, just enclose it in a
9493      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9494      include an explicit SUBREG or we may simplify it further in combine.  */
9495   else
9496     {
9497       int offset = 0;
9498       rtx res;
9499
9500       offset = subreg_lowpart_offset (omode, imode);
9501       if (imode == VOIDmode)
9502         {
9503           imode = int_mode_for_mode (omode);
9504           x = gen_lowpart_common (imode, x);
9505           if (x == NULL)
9506             goto fail;
9507         }
9508       res = simplify_gen_subreg (omode, x, imode, offset);
9509       if (res)
9510         return res;
9511     }
9512
9513  fail:
9514   return gen_rtx_CLOBBER (imode, const0_rtx);
9515 }
9516 \f
9517 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9518    comparison code that will be tested.
9519
9520    The result is a possibly different comparison code to use.  *POP0 and
9521    *POP1 may be updated.
9522
9523    It is possible that we might detect that a comparison is either always
9524    true or always false.  However, we do not perform general constant
9525    folding in combine, so this knowledge isn't useful.  Such tautologies
9526    should have been detected earlier.  Hence we ignore all such cases.  */
9527
9528 static enum rtx_code
9529 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9530 {
9531   rtx op0 = *pop0;
9532   rtx op1 = *pop1;
9533   rtx tem, tem1;
9534   int i;
9535   enum machine_mode mode, tmode;
9536
9537   /* Try a few ways of applying the same transformation to both operands.  */
9538   while (1)
9539     {
9540 #ifndef WORD_REGISTER_OPERATIONS
9541       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9542          so check specially.  */
9543       if (code != GTU && code != GEU && code != LTU && code != LEU
9544           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9545           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9546           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9547           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9548           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9549           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9550               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9551           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9552           && XEXP (op0, 1) == XEXP (op1, 1)
9553           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9554           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9555           && (INTVAL (XEXP (op0, 1))
9556               == (GET_MODE_BITSIZE (GET_MODE (op0))
9557                   - (GET_MODE_BITSIZE
9558                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9559         {
9560           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9561           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9562         }
9563 #endif
9564
9565       /* If both operands are the same constant shift, see if we can ignore the
9566          shift.  We can if the shift is a rotate or if the bits shifted out of
9567          this shift are known to be zero for both inputs and if the type of
9568          comparison is compatible with the shift.  */
9569       if (GET_CODE (op0) == GET_CODE (op1)
9570           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9571           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9572               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9573                   && (code != GT && code != LT && code != GE && code != LE))
9574               || (GET_CODE (op0) == ASHIFTRT
9575                   && (code != GTU && code != LTU
9576                       && code != GEU && code != LEU)))
9577           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9578           && INTVAL (XEXP (op0, 1)) >= 0
9579           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9580           && XEXP (op0, 1) == XEXP (op1, 1))
9581         {
9582           enum machine_mode mode = GET_MODE (op0);
9583           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9584           int shift_count = INTVAL (XEXP (op0, 1));
9585
9586           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9587             mask &= (mask >> shift_count) << shift_count;
9588           else if (GET_CODE (op0) == ASHIFT)
9589             mask = (mask & (mask << shift_count)) >> shift_count;
9590
9591           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9592               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9593             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9594           else
9595             break;
9596         }
9597
9598       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9599          SUBREGs are of the same mode, and, in both cases, the AND would
9600          be redundant if the comparison was done in the narrower mode,
9601          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9602          and the operand's possibly nonzero bits are 0xffffff01; in that case
9603          if we only care about QImode, we don't need the AND).  This case
9604          occurs if the output mode of an scc insn is not SImode and
9605          STORE_FLAG_VALUE == 1 (e.g., the 386).
9606
9607          Similarly, check for a case where the AND's are ZERO_EXTEND
9608          operations from some narrower mode even though a SUBREG is not
9609          present.  */
9610
9611       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9612                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9613                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9614         {
9615           rtx inner_op0 = XEXP (op0, 0);
9616           rtx inner_op1 = XEXP (op1, 0);
9617           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9618           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9619           int changed = 0;
9620
9621           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9622               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9623                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9624               && (GET_MODE (SUBREG_REG (inner_op0))
9625                   == GET_MODE (SUBREG_REG (inner_op1)))
9626               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9627                   <= HOST_BITS_PER_WIDE_INT)
9628               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9629                                              GET_MODE (SUBREG_REG (inner_op0)))))
9630               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9631                                              GET_MODE (SUBREG_REG (inner_op1))))))
9632             {
9633               op0 = SUBREG_REG (inner_op0);
9634               op1 = SUBREG_REG (inner_op1);
9635
9636               /* The resulting comparison is always unsigned since we masked
9637                  off the original sign bit.  */
9638               code = unsigned_condition (code);
9639
9640               changed = 1;
9641             }
9642
9643           else if (c0 == c1)
9644             for (tmode = GET_CLASS_NARROWEST_MODE
9645                  (GET_MODE_CLASS (GET_MODE (op0)));
9646                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9647               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9648                 {
9649                   op0 = gen_lowpart (tmode, inner_op0);
9650                   op1 = gen_lowpart (tmode, inner_op1);
9651                   code = unsigned_condition (code);
9652                   changed = 1;
9653                   break;
9654                 }
9655
9656           if (! changed)
9657             break;
9658         }
9659
9660       /* If both operands are NOT, we can strip off the outer operation
9661          and adjust the comparison code for swapped operands; similarly for
9662          NEG, except that this must be an equality comparison.  */
9663       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9664                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9665                    && (code == EQ || code == NE)))
9666         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9667
9668       else
9669         break;
9670     }
9671
9672   /* If the first operand is a constant, swap the operands and adjust the
9673      comparison code appropriately, but don't do this if the second operand
9674      is already a constant integer.  */
9675   if (swap_commutative_operands_p (op0, op1))
9676     {
9677       tem = op0, op0 = op1, op1 = tem;
9678       code = swap_condition (code);
9679     }
9680
9681   /* We now enter a loop during which we will try to simplify the comparison.
9682      For the most part, we only are concerned with comparisons with zero,
9683      but some things may really be comparisons with zero but not start
9684      out looking that way.  */
9685
9686   while (GET_CODE (op1) == CONST_INT)
9687     {
9688       enum machine_mode mode = GET_MODE (op0);
9689       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9690       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9691       int equality_comparison_p;
9692       int sign_bit_comparison_p;
9693       int unsigned_comparison_p;
9694       HOST_WIDE_INT const_op;
9695
9696       /* We only want to handle integral modes.  This catches VOIDmode,
9697          CCmode, and the floating-point modes.  An exception is that we
9698          can handle VOIDmode if OP0 is a COMPARE or a comparison
9699          operation.  */
9700
9701       if (GET_MODE_CLASS (mode) != MODE_INT
9702           && ! (mode == VOIDmode
9703                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9704         break;
9705
9706       /* Get the constant we are comparing against and turn off all bits
9707          not on in our mode.  */
9708       const_op = INTVAL (op1);
9709       if (mode != VOIDmode)
9710         const_op = trunc_int_for_mode (const_op, mode);
9711       op1 = GEN_INT (const_op);
9712
9713       /* If we are comparing against a constant power of two and the value
9714          being compared can only have that single bit nonzero (e.g., it was
9715          `and'ed with that bit), we can replace this with a comparison
9716          with zero.  */
9717       if (const_op
9718           && (code == EQ || code == NE || code == GE || code == GEU
9719               || code == LT || code == LTU)
9720           && mode_width <= HOST_BITS_PER_WIDE_INT
9721           && exact_log2 (const_op) >= 0
9722           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9723         {
9724           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9725           op1 = const0_rtx, const_op = 0;
9726         }
9727
9728       /* Similarly, if we are comparing a value known to be either -1 or
9729          0 with -1, change it to the opposite comparison against zero.  */
9730
9731       if (const_op == -1
9732           && (code == EQ || code == NE || code == GT || code == LE
9733               || code == GEU || code == LTU)
9734           && num_sign_bit_copies (op0, mode) == mode_width)
9735         {
9736           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9737           op1 = const0_rtx, const_op = 0;
9738         }
9739
9740       /* Do some canonicalizations based on the comparison code.  We prefer
9741          comparisons against zero and then prefer equality comparisons.
9742          If we can reduce the size of a constant, we will do that too.  */
9743
9744       switch (code)
9745         {
9746         case LT:
9747           /* < C is equivalent to <= (C - 1) */
9748           if (const_op > 0)
9749             {
9750               const_op -= 1;
9751               op1 = GEN_INT (const_op);
9752               code = LE;
9753               /* ... fall through to LE case below.  */
9754             }
9755           else
9756             break;
9757
9758         case LE:
9759           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9760           if (const_op < 0)
9761             {
9762               const_op += 1;
9763               op1 = GEN_INT (const_op);
9764               code = LT;
9765             }
9766
9767           /* If we are doing a <= 0 comparison on a value known to have
9768              a zero sign bit, we can replace this with == 0.  */
9769           else if (const_op == 0
9770                    && mode_width <= HOST_BITS_PER_WIDE_INT
9771                    && (nonzero_bits (op0, mode)
9772                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9773             code = EQ;
9774           break;
9775
9776         case GE:
9777           /* >= C is equivalent to > (C - 1).  */
9778           if (const_op > 0)
9779             {
9780               const_op -= 1;
9781               op1 = GEN_INT (const_op);
9782               code = GT;
9783               /* ... fall through to GT below.  */
9784             }
9785           else
9786             break;
9787
9788         case GT:
9789           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9790           if (const_op < 0)
9791             {
9792               const_op += 1;
9793               op1 = GEN_INT (const_op);
9794               code = GE;
9795             }
9796
9797           /* If we are doing a > 0 comparison on a value known to have
9798              a zero sign bit, we can replace this with != 0.  */
9799           else if (const_op == 0
9800                    && mode_width <= HOST_BITS_PER_WIDE_INT
9801                    && (nonzero_bits (op0, mode)
9802                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9803             code = NE;
9804           break;
9805
9806         case LTU:
9807           /* < C is equivalent to <= (C - 1).  */
9808           if (const_op > 0)
9809             {
9810               const_op -= 1;
9811               op1 = GEN_INT (const_op);
9812               code = LEU;
9813               /* ... fall through ...  */
9814             }
9815
9816           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9817           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9818                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9819             {
9820               const_op = 0, op1 = const0_rtx;
9821               code = GE;
9822               break;
9823             }
9824           else
9825             break;
9826
9827         case LEU:
9828           /* unsigned <= 0 is equivalent to == 0 */
9829           if (const_op == 0)
9830             code = EQ;
9831
9832           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9833           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9834                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9835             {
9836               const_op = 0, op1 = const0_rtx;
9837               code = GE;
9838             }
9839           break;
9840
9841         case GEU:
9842           /* >= C is equivalent to > (C - 1).  */
9843           if (const_op > 1)
9844             {
9845               const_op -= 1;
9846               op1 = GEN_INT (const_op);
9847               code = GTU;
9848               /* ... fall through ...  */
9849             }
9850
9851           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9852           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9853                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9854             {
9855               const_op = 0, op1 = const0_rtx;
9856               code = LT;
9857               break;
9858             }
9859           else
9860             break;
9861
9862         case GTU:
9863           /* unsigned > 0 is equivalent to != 0 */
9864           if (const_op == 0)
9865             code = NE;
9866
9867           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9868           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9869                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9870             {
9871               const_op = 0, op1 = const0_rtx;
9872               code = LT;
9873             }
9874           break;
9875
9876         default:
9877           break;
9878         }
9879
9880       /* Compute some predicates to simplify code below.  */
9881
9882       equality_comparison_p = (code == EQ || code == NE);
9883       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9884       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9885                                || code == GEU);
9886
9887       /* If this is a sign bit comparison and we can do arithmetic in
9888          MODE, say that we will only be needing the sign bit of OP0.  */
9889       if (sign_bit_comparison_p
9890           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9891         op0 = force_to_mode (op0, mode,
9892                              ((HOST_WIDE_INT) 1
9893                               << (GET_MODE_BITSIZE (mode) - 1)),
9894                              0);
9895
9896       /* Now try cases based on the opcode of OP0.  If none of the cases
9897          does a "continue", we exit this loop immediately after the
9898          switch.  */
9899
9900       switch (GET_CODE (op0))
9901         {
9902         case ZERO_EXTRACT:
9903           /* If we are extracting a single bit from a variable position in
9904              a constant that has only a single bit set and are comparing it
9905              with zero, we can convert this into an equality comparison
9906              between the position and the location of the single bit.  */
9907           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9908              have already reduced the shift count modulo the word size.  */
9909           if (!SHIFT_COUNT_TRUNCATED
9910               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9911               && XEXP (op0, 1) == const1_rtx
9912               && equality_comparison_p && const_op == 0
9913               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9914             {
9915               if (BITS_BIG_ENDIAN)
9916                 {
9917                   enum machine_mode new_mode
9918                     = mode_for_extraction (EP_extzv, 1);
9919                   if (new_mode == MAX_MACHINE_MODE)
9920                     i = BITS_PER_WORD - 1 - i;
9921                   else
9922                     {
9923                       mode = new_mode;
9924                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9925                     }
9926                 }
9927
9928               op0 = XEXP (op0, 2);
9929               op1 = GEN_INT (i);
9930               const_op = i;
9931
9932               /* Result is nonzero iff shift count is equal to I.  */
9933               code = reverse_condition (code);
9934               continue;
9935             }
9936
9937           /* ... fall through ...  */
9938
9939         case SIGN_EXTRACT:
9940           tem = expand_compound_operation (op0);
9941           if (tem != op0)
9942             {
9943               op0 = tem;
9944               continue;
9945             }
9946           break;
9947
9948         case NOT:
9949           /* If testing for equality, we can take the NOT of the constant.  */
9950           if (equality_comparison_p
9951               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9952             {
9953               op0 = XEXP (op0, 0);
9954               op1 = tem;
9955               continue;
9956             }
9957
9958           /* If just looking at the sign bit, reverse the sense of the
9959              comparison.  */
9960           if (sign_bit_comparison_p)
9961             {
9962               op0 = XEXP (op0, 0);
9963               code = (code == GE ? LT : GE);
9964               continue;
9965             }
9966           break;
9967
9968         case NEG:
9969           /* If testing for equality, we can take the NEG of the constant.  */
9970           if (equality_comparison_p
9971               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9972             {
9973               op0 = XEXP (op0, 0);
9974               op1 = tem;
9975               continue;
9976             }
9977
9978           /* The remaining cases only apply to comparisons with zero.  */
9979           if (const_op != 0)
9980             break;
9981
9982           /* When X is ABS or is known positive,
9983              (neg X) is < 0 if and only if X != 0.  */
9984
9985           if (sign_bit_comparison_p
9986               && (GET_CODE (XEXP (op0, 0)) == ABS
9987                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9988                       && (nonzero_bits (XEXP (op0, 0), mode)
9989                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9990             {
9991               op0 = XEXP (op0, 0);
9992               code = (code == LT ? NE : EQ);
9993               continue;
9994             }
9995
9996           /* If we have NEG of something whose two high-order bits are the
9997              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9998           if (num_sign_bit_copies (op0, mode) >= 2)
9999             {
10000               op0 = XEXP (op0, 0);
10001               code = swap_condition (code);
10002               continue;
10003             }
10004           break;
10005
10006         case ROTATE:
10007           /* If we are testing equality and our count is a constant, we
10008              can perform the inverse operation on our RHS.  */
10009           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10010               && (tem = simplify_binary_operation (ROTATERT, mode,
10011                                                    op1, XEXP (op0, 1))) != 0)
10012             {
10013               op0 = XEXP (op0, 0);
10014               op1 = tem;
10015               continue;
10016             }
10017
10018           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10019              a particular bit.  Convert it to an AND of a constant of that
10020              bit.  This will be converted into a ZERO_EXTRACT.  */
10021           if (const_op == 0 && sign_bit_comparison_p
10022               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10023               && mode_width <= HOST_BITS_PER_WIDE_INT)
10024             {
10025               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10026                                             ((HOST_WIDE_INT) 1
10027                                              << (mode_width - 1
10028                                                  - INTVAL (XEXP (op0, 1)))));
10029               code = (code == LT ? NE : EQ);
10030               continue;
10031             }
10032
10033           /* Fall through.  */
10034
10035         case ABS:
10036           /* ABS is ignorable inside an equality comparison with zero.  */
10037           if (const_op == 0 && equality_comparison_p)
10038             {
10039               op0 = XEXP (op0, 0);
10040               continue;
10041             }
10042           break;
10043
10044         case SIGN_EXTEND:
10045           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10046              (compare FOO CONST) if CONST fits in FOO's mode and we
10047              are either testing inequality or have an unsigned
10048              comparison with ZERO_EXTEND or a signed comparison with
10049              SIGN_EXTEND.  But don't do it if we don't have a compare
10050              insn of the given mode, since we'd have to revert it
10051              later on, and then we wouldn't know whether to sign- or
10052              zero-extend.  */
10053           mode = GET_MODE (XEXP (op0, 0));
10054           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10055               && ! unsigned_comparison_p
10056               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10057               && ((unsigned HOST_WIDE_INT) const_op
10058                   < (((unsigned HOST_WIDE_INT) 1
10059                       << (GET_MODE_BITSIZE (mode) - 1))))
10060               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10061             {
10062               op0 = XEXP (op0, 0);
10063               continue;
10064             }
10065           break;
10066
10067         case SUBREG:
10068           /* Check for the case where we are comparing A - C1 with C2, that is
10069
10070                (subreg:MODE (plus (A) (-C1))) op (C2)
10071
10072              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10073              comparison in the wider mode.  One of the following two conditions
10074              must be true in order for this to be valid:
10075
10076                1. The mode extension results in the same bit pattern being added
10077                   on both sides and the comparison is equality or unsigned.  As
10078                   C2 has been truncated to fit in MODE, the pattern can only be
10079                   all 0s or all 1s.
10080
10081                2. The mode extension results in the sign bit being copied on
10082                   each side.
10083
10084              The difficulty here is that we have predicates for A but not for
10085              (A - C1) so we need to check that C1 is within proper bounds so
10086              as to perturbate A as little as possible.  */
10087
10088           if (mode_width <= HOST_BITS_PER_WIDE_INT
10089               && subreg_lowpart_p (op0)
10090               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10091               && GET_CODE (SUBREG_REG (op0)) == PLUS
10092               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10093             {
10094               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10095               rtx a = XEXP (SUBREG_REG (op0), 0);
10096               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10097
10098               if ((c1 > 0
10099                    && (unsigned HOST_WIDE_INT) c1
10100                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10101                    && (equality_comparison_p || unsigned_comparison_p)
10102                    /* (A - C1) zero-extends if it is positive and sign-extends
10103                       if it is negative, C2 both zero- and sign-extends.  */
10104                    && ((0 == (nonzero_bits (a, inner_mode)
10105                               & ~GET_MODE_MASK (mode))
10106                         && const_op >= 0)
10107                        /* (A - C1) sign-extends if it is positive and 1-extends
10108                           if it is negative, C2 both sign- and 1-extends.  */
10109                        || (num_sign_bit_copies (a, inner_mode)
10110                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10111                                              - mode_width)
10112                            && const_op < 0)))
10113                   || ((unsigned HOST_WIDE_INT) c1
10114                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10115                       /* (A - C1) always sign-extends, like C2.  */
10116                       && num_sign_bit_copies (a, inner_mode)
10117                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10118                                            - (mode_width - 1))))
10119                 {
10120                   op0 = SUBREG_REG (op0);
10121                   continue;
10122                 }
10123             }
10124
10125           /* If the inner mode is narrower and we are extracting the low part,
10126              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10127           if (subreg_lowpart_p (op0)
10128               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10129             /* Fall through */ ;
10130           else
10131             break;
10132
10133           /* ... fall through ...  */
10134
10135         case ZERO_EXTEND:
10136           mode = GET_MODE (XEXP (op0, 0));
10137           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10138               && (unsigned_comparison_p || equality_comparison_p)
10139               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10140               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10141               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10142             {
10143               op0 = XEXP (op0, 0);
10144               continue;
10145             }
10146           break;
10147
10148         case PLUS:
10149           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10150              this for equality comparisons due to pathological cases involving
10151              overflows.  */
10152           if (equality_comparison_p
10153               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10154                                                         op1, XEXP (op0, 1))))
10155             {
10156               op0 = XEXP (op0, 0);
10157               op1 = tem;
10158               continue;
10159             }
10160
10161           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10162           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10163               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10164             {
10165               op0 = XEXP (XEXP (op0, 0), 0);
10166               code = (code == LT ? EQ : NE);
10167               continue;
10168             }
10169           break;
10170
10171         case MINUS:
10172           /* We used to optimize signed comparisons against zero, but that
10173              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10174              arrive here as equality comparisons, or (GEU, LTU) are
10175              optimized away.  No need to special-case them.  */
10176
10177           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10178              (eq B (minus A C)), whichever simplifies.  We can only do
10179              this for equality comparisons due to pathological cases involving
10180              overflows.  */
10181           if (equality_comparison_p
10182               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10183                                                         XEXP (op0, 1), op1)))
10184             {
10185               op0 = XEXP (op0, 0);
10186               op1 = tem;
10187               continue;
10188             }
10189
10190           if (equality_comparison_p
10191               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10192                                                         XEXP (op0, 0), op1)))
10193             {
10194               op0 = XEXP (op0, 1);
10195               op1 = tem;
10196               continue;
10197             }
10198
10199           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10200              of bits in X minus 1, is one iff X > 0.  */
10201           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10202               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10203               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10204                  == mode_width - 1
10205               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10206             {
10207               op0 = XEXP (op0, 1);
10208               code = (code == GE ? LE : GT);
10209               continue;
10210             }
10211           break;
10212
10213         case XOR:
10214           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10215              if C is zero or B is a constant.  */
10216           if (equality_comparison_p
10217               && 0 != (tem = simplify_binary_operation (XOR, mode,
10218                                                         XEXP (op0, 1), op1)))
10219             {
10220               op0 = XEXP (op0, 0);
10221               op1 = tem;
10222               continue;
10223             }
10224           break;
10225
10226         case EQ:  case NE:
10227         case UNEQ:  case LTGT:
10228         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10229         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10230         case UNORDERED: case ORDERED:
10231           /* We can't do anything if OP0 is a condition code value, rather
10232              than an actual data value.  */
10233           if (const_op != 0
10234               || CC0_P (XEXP (op0, 0))
10235               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10236             break;
10237
10238           /* Get the two operands being compared.  */
10239           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10240             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10241           else
10242             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10243
10244           /* Check for the cases where we simply want the result of the
10245              earlier test or the opposite of that result.  */
10246           if (code == NE || code == EQ
10247               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10248                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10249                   && (STORE_FLAG_VALUE
10250                       & (((HOST_WIDE_INT) 1
10251                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10252                   && (code == LT || code == GE)))
10253             {
10254               enum rtx_code new_code;
10255               if (code == LT || code == NE)
10256                 new_code = GET_CODE (op0);
10257               else
10258                 new_code = reversed_comparison_code (op0, NULL);
10259
10260               if (new_code != UNKNOWN)
10261                 {
10262                   code = new_code;
10263                   op0 = tem;
10264                   op1 = tem1;
10265                   continue;
10266                 }
10267             }
10268           break;
10269
10270         case IOR:
10271           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10272              iff X <= 0.  */
10273           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10274               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10275               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10276             {
10277               op0 = XEXP (op0, 1);
10278               code = (code == GE ? GT : LE);
10279               continue;
10280             }
10281           break;
10282
10283         case AND:
10284           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10285              will be converted to a ZERO_EXTRACT later.  */
10286           if (const_op == 0 && equality_comparison_p
10287               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10288               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10289             {
10290               op0 = simplify_and_const_int
10291                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10292                                                    XEXP (op0, 1),
10293                                                    XEXP (XEXP (op0, 0), 1)),
10294                  (HOST_WIDE_INT) 1);
10295               continue;
10296             }
10297
10298           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10299              zero and X is a comparison and C1 and C2 describe only bits set
10300              in STORE_FLAG_VALUE, we can compare with X.  */
10301           if (const_op == 0 && equality_comparison_p
10302               && mode_width <= HOST_BITS_PER_WIDE_INT
10303               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10304               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10305               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10306               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10307               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10308             {
10309               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10310                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10311               if ((~STORE_FLAG_VALUE & mask) == 0
10312                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10313                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10314                           && COMPARISON_P (tem))))
10315                 {
10316                   op0 = XEXP (XEXP (op0, 0), 0);
10317                   continue;
10318                 }
10319             }
10320
10321           /* If we are doing an equality comparison of an AND of a bit equal
10322              to the sign bit, replace this with a LT or GE comparison of
10323              the underlying value.  */
10324           if (equality_comparison_p
10325               && const_op == 0
10326               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10327               && mode_width <= HOST_BITS_PER_WIDE_INT
10328               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10329                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10330             {
10331               op0 = XEXP (op0, 0);
10332               code = (code == EQ ? GE : LT);
10333               continue;
10334             }
10335
10336           /* If this AND operation is really a ZERO_EXTEND from a narrower
10337              mode, the constant fits within that mode, and this is either an
10338              equality or unsigned comparison, try to do this comparison in
10339              the narrower mode.
10340
10341              Note that in:
10342
10343              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10344              -> (ne:DI (reg:SI 4) (const_int 0))
10345
10346              unless TRULY_NOOP_TRUNCATION allows it or the register is
10347              known to hold a value of the required mode the
10348              transformation is invalid.  */
10349           if ((equality_comparison_p || unsigned_comparison_p)
10350               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10351               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10352                                    & GET_MODE_MASK (mode))
10353                                   + 1)) >= 0
10354               && const_op >> i == 0
10355               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10356               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10357                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10358                   || (REG_P (XEXP (op0, 0))
10359                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10360             {
10361               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10362               continue;
10363             }
10364
10365           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10366              fits in both M1 and M2 and the SUBREG is either paradoxical
10367              or represents the low part, permute the SUBREG and the AND
10368              and try again.  */
10369           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10370             {
10371               unsigned HOST_WIDE_INT c1;
10372               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10373               /* Require an integral mode, to avoid creating something like
10374                  (AND:SF ...).  */
10375               if (SCALAR_INT_MODE_P (tmode)
10376                   /* It is unsafe to commute the AND into the SUBREG if the
10377                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10378                      not defined.  As originally written the upper bits
10379                      have a defined value due to the AND operation.
10380                      However, if we commute the AND inside the SUBREG then
10381                      they no longer have defined values and the meaning of
10382                      the code has been changed.  */
10383                   && (0
10384 #ifdef WORD_REGISTER_OPERATIONS
10385                       || (mode_width > GET_MODE_BITSIZE (tmode)
10386                           && mode_width <= BITS_PER_WORD)
10387 #endif
10388                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10389                           && subreg_lowpart_p (XEXP (op0, 0))))
10390                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10391                   && mode_width <= HOST_BITS_PER_WIDE_INT
10392                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10393                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10394                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10395                   && c1 != mask
10396                   && c1 != GET_MODE_MASK (tmode))
10397                 {
10398                   op0 = simplify_gen_binary (AND, tmode,
10399                                              SUBREG_REG (XEXP (op0, 0)),
10400                                              gen_int_mode (c1, tmode));
10401                   op0 = gen_lowpart (mode, op0);
10402                   continue;
10403                 }
10404             }
10405
10406           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10407           if (const_op == 0 && equality_comparison_p
10408               && XEXP (op0, 1) == const1_rtx
10409               && GET_CODE (XEXP (op0, 0)) == NOT)
10410             {
10411               op0 = simplify_and_const_int
10412                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10413               code = (code == NE ? EQ : NE);
10414               continue;
10415             }
10416
10417           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10418              (eq (and (lshiftrt X) 1) 0).
10419              Also handle the case where (not X) is expressed using xor.  */
10420           if (const_op == 0 && equality_comparison_p
10421               && XEXP (op0, 1) == const1_rtx
10422               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10423             {
10424               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10425               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10426
10427               if (GET_CODE (shift_op) == NOT
10428                   || (GET_CODE (shift_op) == XOR
10429                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10430                       && GET_CODE (shift_count) == CONST_INT
10431                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10432                       && (INTVAL (XEXP (shift_op, 1))
10433                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10434                 {
10435                   op0 = simplify_and_const_int
10436                     (NULL_RTX, mode,
10437                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10438                      (HOST_WIDE_INT) 1);
10439                   code = (code == NE ? EQ : NE);
10440                   continue;
10441                 }
10442             }
10443           break;
10444
10445         case ASHIFT:
10446           /* If we have (compare (ashift FOO N) (const_int C)) and
10447              the high order N bits of FOO (N+1 if an inequality comparison)
10448              are known to be zero, we can do this by comparing FOO with C
10449              shifted right N bits so long as the low-order N bits of C are
10450              zero.  */
10451           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10452               && INTVAL (XEXP (op0, 1)) >= 0
10453               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10454                   < HOST_BITS_PER_WIDE_INT)
10455               && ((const_op
10456                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10457               && mode_width <= HOST_BITS_PER_WIDE_INT
10458               && (nonzero_bits (XEXP (op0, 0), mode)
10459                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10460                                + ! equality_comparison_p))) == 0)
10461             {
10462               /* We must perform a logical shift, not an arithmetic one,
10463                  as we want the top N bits of C to be zero.  */
10464               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10465
10466               temp >>= INTVAL (XEXP (op0, 1));
10467               op1 = gen_int_mode (temp, mode);
10468               op0 = XEXP (op0, 0);
10469               continue;
10470             }
10471
10472           /* If we are doing a sign bit comparison, it means we are testing
10473              a particular bit.  Convert it to the appropriate AND.  */
10474           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10475               && mode_width <= HOST_BITS_PER_WIDE_INT)
10476             {
10477               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10478                                             ((HOST_WIDE_INT) 1
10479                                              << (mode_width - 1
10480                                                  - INTVAL (XEXP (op0, 1)))));
10481               code = (code == LT ? NE : EQ);
10482               continue;
10483             }
10484
10485           /* If this an equality comparison with zero and we are shifting
10486              the low bit to the sign bit, we can convert this to an AND of the
10487              low-order bit.  */
10488           if (const_op == 0 && equality_comparison_p
10489               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10490               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10491                  == mode_width - 1)
10492             {
10493               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10494                                             (HOST_WIDE_INT) 1);
10495               continue;
10496             }
10497           break;
10498
10499         case ASHIFTRT:
10500           /* If this is an equality comparison with zero, we can do this
10501              as a logical shift, which might be much simpler.  */
10502           if (equality_comparison_p && const_op == 0
10503               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10504             {
10505               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10506                                           XEXP (op0, 0),
10507                                           INTVAL (XEXP (op0, 1)));
10508               continue;
10509             }
10510
10511           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10512              do the comparison in a narrower mode.  */
10513           if (! unsigned_comparison_p
10514               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10515               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10516               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10517               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10518                                          MODE_INT, 1)) != BLKmode
10519               && (((unsigned HOST_WIDE_INT) const_op
10520                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10521                   <= GET_MODE_MASK (tmode)))
10522             {
10523               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10524               continue;
10525             }
10526
10527           /* Likewise if OP0 is a PLUS of a sign extension with a
10528              constant, which is usually represented with the PLUS
10529              between the shifts.  */
10530           if (! unsigned_comparison_p
10531               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10532               && GET_CODE (XEXP (op0, 0)) == PLUS
10533               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10534               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10535               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10536               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10537                                          MODE_INT, 1)) != BLKmode
10538               && (((unsigned HOST_WIDE_INT) const_op
10539                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10540                   <= GET_MODE_MASK (tmode)))
10541             {
10542               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10543               rtx add_const = XEXP (XEXP (op0, 0), 1);
10544               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10545                                                    add_const, XEXP (op0, 1));
10546
10547               op0 = simplify_gen_binary (PLUS, tmode,
10548                                          gen_lowpart (tmode, inner),
10549                                          new_const);
10550               continue;
10551             }
10552
10553           /* ... fall through ...  */
10554         case LSHIFTRT:
10555           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10556              the low order N bits of FOO are known to be zero, we can do this
10557              by comparing FOO with C shifted left N bits so long as no
10558              overflow occurs.  */
10559           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10560               && INTVAL (XEXP (op0, 1)) >= 0
10561               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10562               && mode_width <= HOST_BITS_PER_WIDE_INT
10563               && (nonzero_bits (XEXP (op0, 0), mode)
10564                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10565               && (((unsigned HOST_WIDE_INT) const_op
10566                    + (GET_CODE (op0) != LSHIFTRT
10567                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10568                          + 1)
10569                       : 0))
10570                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10571             {
10572               /* If the shift was logical, then we must make the condition
10573                  unsigned.  */
10574               if (GET_CODE (op0) == LSHIFTRT)
10575                 code = unsigned_condition (code);
10576
10577               const_op <<= INTVAL (XEXP (op0, 1));
10578               op1 = GEN_INT (const_op);
10579               op0 = XEXP (op0, 0);
10580               continue;
10581             }
10582
10583           /* If we are using this shift to extract just the sign bit, we
10584              can replace this with an LT or GE comparison.  */
10585           if (const_op == 0
10586               && (equality_comparison_p || sign_bit_comparison_p)
10587               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10588               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10589                  == mode_width - 1)
10590             {
10591               op0 = XEXP (op0, 0);
10592               code = (code == NE || code == GT ? LT : GE);
10593               continue;
10594             }
10595           break;
10596
10597         default:
10598           break;
10599         }
10600
10601       break;
10602     }
10603
10604   /* Now make any compound operations involved in this comparison.  Then,
10605      check for an outmost SUBREG on OP0 that is not doing anything or is
10606      paradoxical.  The latter transformation must only be performed when
10607      it is known that the "extra" bits will be the same in op0 and op1 or
10608      that they don't matter.  There are three cases to consider:
10609
10610      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10611      care bits and we can assume they have any convenient value.  So
10612      making the transformation is safe.
10613
10614      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10615      In this case the upper bits of op0 are undefined.  We should not make
10616      the simplification in that case as we do not know the contents of
10617      those bits.
10618
10619      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10620      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10621      also be sure that they are the same as the upper bits of op1.
10622
10623      We can never remove a SUBREG for a non-equality comparison because
10624      the sign bit is in a different place in the underlying object.  */
10625
10626   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10627   op1 = make_compound_operation (op1, SET);
10628
10629   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10630       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10631       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10632       && (code == NE || code == EQ))
10633     {
10634       if (GET_MODE_SIZE (GET_MODE (op0))
10635           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10636         {
10637           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10638              implemented.  */
10639           if (REG_P (SUBREG_REG (op0)))
10640             {
10641               op0 = SUBREG_REG (op0);
10642               op1 = gen_lowpart (GET_MODE (op0), op1);
10643             }
10644         }
10645       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10646                 <= HOST_BITS_PER_WIDE_INT)
10647                && (nonzero_bits (SUBREG_REG (op0),
10648                                  GET_MODE (SUBREG_REG (op0)))
10649                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10650         {
10651           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10652
10653           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10654                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10655             op0 = SUBREG_REG (op0), op1 = tem;
10656         }
10657     }
10658
10659   /* We now do the opposite procedure: Some machines don't have compare
10660      insns in all modes.  If OP0's mode is an integer mode smaller than a
10661      word and we can't do a compare in that mode, see if there is a larger
10662      mode for which we can do the compare.  There are a number of cases in
10663      which we can use the wider mode.  */
10664
10665   mode = GET_MODE (op0);
10666   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10667       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10668       && ! have_insn_for (COMPARE, mode))
10669     for (tmode = GET_MODE_WIDER_MODE (mode);
10670          (tmode != VOIDmode
10671           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10672          tmode = GET_MODE_WIDER_MODE (tmode))
10673       if (have_insn_for (COMPARE, tmode))
10674         {
10675           int zero_extended;
10676
10677           /* If the only nonzero bits in OP0 and OP1 are those in the
10678              narrower mode and this is an equality or unsigned comparison,
10679              we can use the wider mode.  Similarly for sign-extended
10680              values, in which case it is true for all comparisons.  */
10681           zero_extended = ((code == EQ || code == NE
10682                             || code == GEU || code == GTU
10683                             || code == LEU || code == LTU)
10684                            && (nonzero_bits (op0, tmode)
10685                                & ~GET_MODE_MASK (mode)) == 0
10686                            && ((GET_CODE (op1) == CONST_INT
10687                                 || (nonzero_bits (op1, tmode)
10688                                     & ~GET_MODE_MASK (mode)) == 0)));
10689
10690           if (zero_extended
10691               || ((num_sign_bit_copies (op0, tmode)
10692                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10693                                      - GET_MODE_BITSIZE (mode)))
10694                   && (num_sign_bit_copies (op1, tmode)
10695                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10696                                         - GET_MODE_BITSIZE (mode)))))
10697             {
10698               /* If OP0 is an AND and we don't have an AND in MODE either,
10699                  make a new AND in the proper mode.  */
10700               if (GET_CODE (op0) == AND
10701                   && !have_insn_for (AND, mode))
10702                 op0 = simplify_gen_binary (AND, tmode,
10703                                            gen_lowpart (tmode,
10704                                                         XEXP (op0, 0)),
10705                                            gen_lowpart (tmode,
10706                                                         XEXP (op0, 1)));
10707
10708               op0 = gen_lowpart (tmode, op0);
10709               if (zero_extended && GET_CODE (op1) == CONST_INT)
10710                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10711               op1 = gen_lowpart (tmode, op1);
10712               break;
10713             }
10714
10715           /* If this is a test for negative, we can make an explicit
10716              test of the sign bit.  */
10717
10718           if (op1 == const0_rtx && (code == LT || code == GE)
10719               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10720             {
10721               op0 = simplify_gen_binary (AND, tmode,
10722                                          gen_lowpart (tmode, op0),
10723                                          GEN_INT ((HOST_WIDE_INT) 1
10724                                                   << (GET_MODE_BITSIZE (mode)
10725                                                       - 1)));
10726               code = (code == LT) ? NE : EQ;
10727               break;
10728             }
10729         }
10730
10731 #ifdef CANONICALIZE_COMPARISON
10732   /* If this machine only supports a subset of valid comparisons, see if we
10733      can convert an unsupported one into a supported one.  */
10734   CANONICALIZE_COMPARISON (code, op0, op1);
10735 #endif
10736
10737   *pop0 = op0;
10738   *pop1 = op1;
10739
10740   return code;
10741 }
10742 \f
10743 /* Utility function for record_value_for_reg.  Count number of
10744    rtxs in X.  */
10745 static int
10746 count_rtxs (rtx x)
10747 {
10748   enum rtx_code code = GET_CODE (x);
10749   const char *fmt;
10750   int i, ret = 1;
10751
10752   if (GET_RTX_CLASS (code) == '2'
10753       || GET_RTX_CLASS (code) == 'c')
10754     {
10755       rtx x0 = XEXP (x, 0);
10756       rtx x1 = XEXP (x, 1);
10757
10758       if (x0 == x1)
10759         return 1 + 2 * count_rtxs (x0);
10760
10761       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10762            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10763           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10764         return 2 + 2 * count_rtxs (x0)
10765                + count_rtxs (x == XEXP (x1, 0)
10766                              ? XEXP (x1, 1) : XEXP (x1, 0));
10767
10768       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10769            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10770           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10771         return 2 + 2 * count_rtxs (x1)
10772                + count_rtxs (x == XEXP (x0, 0)
10773                              ? XEXP (x0, 1) : XEXP (x0, 0));
10774     }
10775
10776   fmt = GET_RTX_FORMAT (code);
10777   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10778     if (fmt[i] == 'e')
10779       ret += count_rtxs (XEXP (x, i));
10780
10781   return ret;
10782 }
10783 \f
10784 /* Utility function for following routine.  Called when X is part of a value
10785    being stored into last_set_value.  Sets last_set_table_tick
10786    for each register mentioned.  Similar to mention_regs in cse.c  */
10787
10788 static void
10789 update_table_tick (rtx x)
10790 {
10791   enum rtx_code code = GET_CODE (x);
10792   const char *fmt = GET_RTX_FORMAT (code);
10793   int i;
10794
10795   if (code == REG)
10796     {
10797       unsigned int regno = REGNO (x);
10798       unsigned int endregno
10799         = regno + (regno < FIRST_PSEUDO_REGISTER
10800                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10801       unsigned int r;
10802
10803       for (r = regno; r < endregno; r++)
10804         reg_stat[r].last_set_table_tick = label_tick;
10805
10806       return;
10807     }
10808
10809   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10810     /* Note that we can't have an "E" in values stored; see
10811        get_last_value_validate.  */
10812     if (fmt[i] == 'e')
10813       {
10814         /* Check for identical subexpressions.  If x contains
10815            identical subexpression we only have to traverse one of
10816            them.  */
10817         if (i == 0 && ARITHMETIC_P (x))
10818           {
10819             /* Note that at this point x1 has already been
10820                processed.  */
10821             rtx x0 = XEXP (x, 0);
10822             rtx x1 = XEXP (x, 1);
10823
10824             /* If x0 and x1 are identical then there is no need to
10825                process x0.  */
10826             if (x0 == x1)
10827               break;
10828
10829             /* If x0 is identical to a subexpression of x1 then while
10830                processing x1, x0 has already been processed.  Thus we
10831                are done with x.  */
10832             if (ARITHMETIC_P (x1)
10833                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10834               break;
10835
10836             /* If x1 is identical to a subexpression of x0 then we
10837                still have to process the rest of x0.  */
10838             if (ARITHMETIC_P (x0)
10839                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10840               {
10841                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10842                 break;
10843               }
10844           }
10845
10846         update_table_tick (XEXP (x, i));
10847       }
10848 }
10849
10850 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10851    are saying that the register is clobbered and we no longer know its
10852    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10853    only permitted with VALUE also zero and is used to invalidate the
10854    register.  */
10855
10856 static void
10857 record_value_for_reg (rtx reg, rtx insn, rtx value)
10858 {
10859   unsigned int regno = REGNO (reg);
10860   unsigned int endregno
10861     = regno + (regno < FIRST_PSEUDO_REGISTER
10862                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10863   unsigned int i;
10864
10865   /* If VALUE contains REG and we have a previous value for REG, substitute
10866      the previous value.  */
10867   if (value && insn && reg_overlap_mentioned_p (reg, value))
10868     {
10869       rtx tem;
10870
10871       /* Set things up so get_last_value is allowed to see anything set up to
10872          our insn.  */
10873       subst_low_cuid = INSN_CUID (insn);
10874       tem = get_last_value (reg);
10875
10876       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10877          it isn't going to be useful and will take a lot of time to process,
10878          so just use the CLOBBER.  */
10879
10880       if (tem)
10881         {
10882           if (ARITHMETIC_P (tem)
10883               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10884               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10885             tem = XEXP (tem, 0);
10886           else if (count_occurrences (value, reg, 1) >= 2)
10887             {
10888               /* If there are two or more occurrences of REG in VALUE,
10889                  prevent the value from growing too much.  */
10890               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10891                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10892             }
10893
10894           value = replace_rtx (copy_rtx (value), reg, tem);
10895         }
10896     }
10897
10898   /* For each register modified, show we don't know its value, that
10899      we don't know about its bitwise content, that its value has been
10900      updated, and that we don't know the location of the death of the
10901      register.  */
10902   for (i = regno; i < endregno; i++)
10903     {
10904       if (insn)
10905         reg_stat[i].last_set = insn;
10906
10907       reg_stat[i].last_set_value = 0;
10908       reg_stat[i].last_set_mode = 0;
10909       reg_stat[i].last_set_nonzero_bits = 0;
10910       reg_stat[i].last_set_sign_bit_copies = 0;
10911       reg_stat[i].last_death = 0;
10912       reg_stat[i].truncated_to_mode = 0;
10913     }
10914
10915   /* Mark registers that are being referenced in this value.  */
10916   if (value)
10917     update_table_tick (value);
10918
10919   /* Now update the status of each register being set.
10920      If someone is using this register in this block, set this register
10921      to invalid since we will get confused between the two lives in this
10922      basic block.  This makes using this register always invalid.  In cse, we
10923      scan the table to invalidate all entries using this register, but this
10924      is too much work for us.  */
10925
10926   for (i = regno; i < endregno; i++)
10927     {
10928       reg_stat[i].last_set_label = label_tick;
10929       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10930         reg_stat[i].last_set_invalid = 1;
10931       else
10932         reg_stat[i].last_set_invalid = 0;
10933     }
10934
10935   /* The value being assigned might refer to X (like in "x++;").  In that
10936      case, we must replace it with (clobber (const_int 0)) to prevent
10937      infinite loops.  */
10938   if (value && ! get_last_value_validate (&value, insn,
10939                                           reg_stat[regno].last_set_label, 0))
10940     {
10941       value = copy_rtx (value);
10942       if (! get_last_value_validate (&value, insn,
10943                                      reg_stat[regno].last_set_label, 1))
10944         value = 0;
10945     }
10946
10947   /* For the main register being modified, update the value, the mode, the
10948      nonzero bits, and the number of sign bit copies.  */
10949
10950   reg_stat[regno].last_set_value = value;
10951
10952   if (value)
10953     {
10954       enum machine_mode mode = GET_MODE (reg);
10955       subst_low_cuid = INSN_CUID (insn);
10956       reg_stat[regno].last_set_mode = mode;
10957       if (GET_MODE_CLASS (mode) == MODE_INT
10958           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10959         mode = nonzero_bits_mode;
10960       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10961       reg_stat[regno].last_set_sign_bit_copies
10962         = num_sign_bit_copies (value, GET_MODE (reg));
10963     }
10964 }
10965
10966 /* Called via note_stores from record_dead_and_set_regs to handle one
10967    SET or CLOBBER in an insn.  DATA is the instruction in which the
10968    set is occurring.  */
10969
10970 static void
10971 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10972 {
10973   rtx record_dead_insn = (rtx) data;
10974
10975   if (GET_CODE (dest) == SUBREG)
10976     dest = SUBREG_REG (dest);
10977
10978   if (!record_dead_insn)
10979     {
10980       if (REG_P (dest))
10981         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10982       return;
10983     }
10984
10985   if (REG_P (dest))
10986     {
10987       /* If we are setting the whole register, we know its value.  Otherwise
10988          show that we don't know the value.  We can handle SUBREG in
10989          some cases.  */
10990       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10991         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10992       else if (GET_CODE (setter) == SET
10993                && GET_CODE (SET_DEST (setter)) == SUBREG
10994                && SUBREG_REG (SET_DEST (setter)) == dest
10995                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10996                && subreg_lowpart_p (SET_DEST (setter)))
10997         record_value_for_reg (dest, record_dead_insn,
10998                               gen_lowpart (GET_MODE (dest),
10999                                                        SET_SRC (setter)));
11000       else
11001         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11002     }
11003   else if (MEM_P (dest)
11004            /* Ignore pushes, they clobber nothing.  */
11005            && ! push_operand (dest, GET_MODE (dest)))
11006     mem_last_set = INSN_CUID (record_dead_insn);
11007 }
11008
11009 /* Update the records of when each REG was most recently set or killed
11010    for the things done by INSN.  This is the last thing done in processing
11011    INSN in the combiner loop.
11012
11013    We update reg_stat[], in particular fields last_set, last_set_value,
11014    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11015    last_death, and also the similar information mem_last_set (which insn
11016    most recently modified memory) and last_call_cuid (which insn was the
11017    most recent subroutine call).  */
11018
11019 static void
11020 record_dead_and_set_regs (rtx insn)
11021 {
11022   rtx link;
11023   unsigned int i;
11024
11025   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11026     {
11027       if (REG_NOTE_KIND (link) == REG_DEAD
11028           && REG_P (XEXP (link, 0)))
11029         {
11030           unsigned int regno = REGNO (XEXP (link, 0));
11031           unsigned int endregno
11032             = regno + (regno < FIRST_PSEUDO_REGISTER
11033                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11034                        : 1);
11035
11036           for (i = regno; i < endregno; i++)
11037             reg_stat[i].last_death = insn;
11038         }
11039       else if (REG_NOTE_KIND (link) == REG_INC)
11040         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11041     }
11042
11043   if (CALL_P (insn))
11044     {
11045       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11046         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11047           {
11048             reg_stat[i].last_set_value = 0;
11049             reg_stat[i].last_set_mode = 0;
11050             reg_stat[i].last_set_nonzero_bits = 0;
11051             reg_stat[i].last_set_sign_bit_copies = 0;
11052             reg_stat[i].last_death = 0;
11053             reg_stat[i].truncated_to_mode = 0;
11054           }
11055
11056       last_call_cuid = mem_last_set = INSN_CUID (insn);
11057
11058       /* We can't combine into a call pattern.  Remember, though, that
11059          the return value register is set at this CUID.  We could
11060          still replace a register with the return value from the
11061          wrong subroutine call!  */
11062       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11063     }
11064   else
11065     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11066 }
11067
11068 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11069    register present in the SUBREG, so for each such SUBREG go back and
11070    adjust nonzero and sign bit information of the registers that are
11071    known to have some zero/sign bits set.
11072
11073    This is needed because when combine blows the SUBREGs away, the
11074    information on zero/sign bits is lost and further combines can be
11075    missed because of that.  */
11076
11077 static void
11078 record_promoted_value (rtx insn, rtx subreg)
11079 {
11080   rtx links, set;
11081   unsigned int regno = REGNO (SUBREG_REG (subreg));
11082   enum machine_mode mode = GET_MODE (subreg);
11083
11084   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11085     return;
11086
11087   for (links = LOG_LINKS (insn); links;)
11088     {
11089       insn = XEXP (links, 0);
11090       set = single_set (insn);
11091
11092       if (! set || !REG_P (SET_DEST (set))
11093           || REGNO (SET_DEST (set)) != regno
11094           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11095         {
11096           links = XEXP (links, 1);
11097           continue;
11098         }
11099
11100       if (reg_stat[regno].last_set == insn)
11101         {
11102           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11103             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11104         }
11105
11106       if (REG_P (SET_SRC (set)))
11107         {
11108           regno = REGNO (SET_SRC (set));
11109           links = LOG_LINKS (insn);
11110         }
11111       else
11112         break;
11113     }
11114 }
11115
11116 /* Check if X, a register, is known to contain a value already
11117    truncated to MODE.  In this case we can use a subreg to refer to
11118    the truncated value even though in the generic case we would need
11119    an explicit truncation.  */
11120
11121 static bool
11122 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11123 {
11124   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11125
11126   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11127     return false;
11128   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11129     return true;
11130   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11131                              GET_MODE_BITSIZE (truncated)))
11132     return true;
11133   return false;
11134 }
11135
11136 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11137    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11138    a truncate into a subreg using this information.  */
11139
11140 static void
11141 record_truncated_value (rtx x)
11142 {
11143   enum machine_mode truncated_mode;
11144
11145   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11146     {
11147       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11148       truncated_mode = GET_MODE (x);
11149
11150       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11151         return;
11152
11153       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11154                                  GET_MODE_BITSIZE (original_mode)))
11155         return;
11156
11157       x = SUBREG_REG (x);
11158     }
11159   /* ??? For hard-regs we now record everything.  We might be able to
11160      optimize this using last_set_mode.  */
11161   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11162     truncated_mode = GET_MODE (x);
11163   else
11164     return;
11165
11166   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11167       || reg_stat[REGNO (x)].truncation_label < label_tick
11168       || (GET_MODE_SIZE (truncated_mode)
11169           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11170     {
11171       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11172       reg_stat[REGNO (x)].truncation_label = label_tick;
11173     }
11174 }
11175
11176 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11177    found, note what it implies to the registers used in it.  */
11178
11179 static void
11180 check_conversions (rtx insn, rtx x)
11181 {
11182   if (GET_CODE (x) == SUBREG || REG_P (x))
11183     {
11184       if (GET_CODE (x) == SUBREG
11185           && SUBREG_PROMOTED_VAR_P (x)
11186           && REG_P (SUBREG_REG (x)))
11187         record_promoted_value (insn, x);
11188
11189       record_truncated_value (x);
11190     }
11191   else
11192     {
11193       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11194       int i, j;
11195
11196       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11197         switch (format[i])
11198           {
11199           case 'e':
11200             check_conversions (insn, XEXP (x, i));
11201             break;
11202           case 'V':
11203           case 'E':
11204             if (XVEC (x, i) != 0)
11205               for (j = 0; j < XVECLEN (x, i); j++)
11206                 check_conversions (insn, XVECEXP (x, i, j));
11207             break;
11208           }
11209     }
11210 }
11211 \f
11212 /* Utility routine for the following function.  Verify that all the registers
11213    mentioned in *LOC are valid when *LOC was part of a value set when
11214    label_tick == TICK.  Return 0 if some are not.
11215
11216    If REPLACE is nonzero, replace the invalid reference with
11217    (clobber (const_int 0)) and return 1.  This replacement is useful because
11218    we often can get useful information about the form of a value (e.g., if
11219    it was produced by a shift that always produces -1 or 0) even though
11220    we don't know exactly what registers it was produced from.  */
11221
11222 static int
11223 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11224 {
11225   rtx x = *loc;
11226   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11227   int len = GET_RTX_LENGTH (GET_CODE (x));
11228   int i;
11229
11230   if (REG_P (x))
11231     {
11232       unsigned int regno = REGNO (x);
11233       unsigned int endregno
11234         = regno + (regno < FIRST_PSEUDO_REGISTER
11235                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11236       unsigned int j;
11237
11238       for (j = regno; j < endregno; j++)
11239         if (reg_stat[j].last_set_invalid
11240             /* If this is a pseudo-register that was only set once and not
11241                live at the beginning of the function, it is always valid.  */
11242             || (! (regno >= FIRST_PSEUDO_REGISTER
11243                    && REG_N_SETS (regno) == 1
11244                    && (! REGNO_REG_SET_P
11245                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11246                         regno)))
11247                 && reg_stat[j].last_set_label > tick))
11248           {
11249             if (replace)
11250               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11251             return replace;
11252           }
11253
11254       return 1;
11255     }
11256   /* If this is a memory reference, make sure that there were
11257      no stores after it that might have clobbered the value.  We don't
11258      have alias info, so we assume any store invalidates it.  */
11259   else if (MEM_P (x) && !MEM_READONLY_P (x)
11260            && INSN_CUID (insn) <= mem_last_set)
11261     {
11262       if (replace)
11263         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11264       return replace;
11265     }
11266
11267   for (i = 0; i < len; i++)
11268     {
11269       if (fmt[i] == 'e')
11270         {
11271           /* Check for identical subexpressions.  If x contains
11272              identical subexpression we only have to traverse one of
11273              them.  */
11274           if (i == 1 && ARITHMETIC_P (x))
11275             {
11276               /* Note that at this point x0 has already been checked
11277                  and found valid.  */
11278               rtx x0 = XEXP (x, 0);
11279               rtx x1 = XEXP (x, 1);
11280
11281               /* If x0 and x1 are identical then x is also valid.  */
11282               if (x0 == x1)
11283                 return 1;
11284
11285               /* If x1 is identical to a subexpression of x0 then
11286                  while checking x0, x1 has already been checked.  Thus
11287                  it is valid and so as x.  */
11288               if (ARITHMETIC_P (x0)
11289                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11290                 return 1;
11291
11292               /* If x0 is identical to a subexpression of x1 then x is
11293                  valid iff the rest of x1 is valid.  */
11294               if (ARITHMETIC_P (x1)
11295                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11296                 return
11297                   get_last_value_validate (&XEXP (x1,
11298                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11299                                            insn, tick, replace);
11300             }
11301
11302           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11303                                        replace) == 0)
11304             return 0;
11305         }
11306       /* Don't bother with these.  They shouldn't occur anyway.  */
11307       else if (fmt[i] == 'E')
11308         return 0;
11309     }
11310
11311   /* If we haven't found a reason for it to be invalid, it is valid.  */
11312   return 1;
11313 }
11314
11315 /* Get the last value assigned to X, if known.  Some registers
11316    in the value may be replaced with (clobber (const_int 0)) if their value
11317    is known longer known reliably.  */
11318
11319 static rtx
11320 get_last_value (rtx x)
11321 {
11322   unsigned int regno;
11323   rtx value;
11324
11325   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11326      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11327      we cannot predict what values the "extra" bits might have.  */
11328   if (GET_CODE (x) == SUBREG
11329       && subreg_lowpart_p (x)
11330       && (GET_MODE_SIZE (GET_MODE (x))
11331           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11332       && (value = get_last_value (SUBREG_REG (x))) != 0)
11333     return gen_lowpart (GET_MODE (x), value);
11334
11335   if (!REG_P (x))
11336     return 0;
11337
11338   regno = REGNO (x);
11339   value = reg_stat[regno].last_set_value;
11340
11341   /* If we don't have a value, or if it isn't for this basic block and
11342      it's either a hard register, set more than once, or it's a live
11343      at the beginning of the function, return 0.
11344
11345      Because if it's not live at the beginning of the function then the reg
11346      is always set before being used (is never used without being set).
11347      And, if it's set only once, and it's always set before use, then all
11348      uses must have the same last value, even if it's not from this basic
11349      block.  */
11350
11351   if (value == 0
11352       || (reg_stat[regno].last_set_label != label_tick
11353           && (regno < FIRST_PSEUDO_REGISTER
11354               || REG_N_SETS (regno) != 1
11355               || (REGNO_REG_SET_P
11356                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11357                    regno)))))
11358     return 0;
11359
11360   /* If the value was set in a later insn than the ones we are processing,
11361      we can't use it even if the register was only set once.  */
11362   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11363     return 0;
11364
11365   /* If the value has all its registers valid, return it.  */
11366   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11367                                reg_stat[regno].last_set_label, 0))
11368     return value;
11369
11370   /* Otherwise, make a copy and replace any invalid register with
11371      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11372
11373   value = copy_rtx (value);
11374   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11375                                reg_stat[regno].last_set_label, 1))
11376     return value;
11377
11378   return 0;
11379 }
11380 \f
11381 /* Return nonzero if expression X refers to a REG or to memory
11382    that is set in an instruction more recent than FROM_CUID.  */
11383
11384 static int
11385 use_crosses_set_p (rtx x, int from_cuid)
11386 {
11387   const char *fmt;
11388   int i;
11389   enum rtx_code code = GET_CODE (x);
11390
11391   if (code == REG)
11392     {
11393       unsigned int regno = REGNO (x);
11394       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11395                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11396
11397 #ifdef PUSH_ROUNDING
11398       /* Don't allow uses of the stack pointer to be moved,
11399          because we don't know whether the move crosses a push insn.  */
11400       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11401         return 1;
11402 #endif
11403       for (; regno < endreg; regno++)
11404         if (reg_stat[regno].last_set
11405             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11406           return 1;
11407       return 0;
11408     }
11409
11410   if (code == MEM && mem_last_set > from_cuid)
11411     return 1;
11412
11413   fmt = GET_RTX_FORMAT (code);
11414
11415   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11416     {
11417       if (fmt[i] == 'E')
11418         {
11419           int j;
11420           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11421             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11422               return 1;
11423         }
11424       else if (fmt[i] == 'e'
11425                && use_crosses_set_p (XEXP (x, i), from_cuid))
11426         return 1;
11427     }
11428   return 0;
11429 }
11430 \f
11431 /* Define three variables used for communication between the following
11432    routines.  */
11433
11434 static unsigned int reg_dead_regno, reg_dead_endregno;
11435 static int reg_dead_flag;
11436
11437 /* Function called via note_stores from reg_dead_at_p.
11438
11439    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11440    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11441
11442 static void
11443 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11444 {
11445   unsigned int regno, endregno;
11446
11447   if (!REG_P (dest))
11448     return;
11449
11450   regno = REGNO (dest);
11451   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11452                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11453
11454   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11455     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11456 }
11457
11458 /* Return nonzero if REG is known to be dead at INSN.
11459
11460    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11461    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11462    live.  Otherwise, see if it is live or dead at the start of the basic
11463    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11464    must be assumed to be always live.  */
11465
11466 static int
11467 reg_dead_at_p (rtx reg, rtx insn)
11468 {
11469   basic_block block;
11470   unsigned int i;
11471
11472   /* Set variables for reg_dead_at_p_1.  */
11473   reg_dead_regno = REGNO (reg);
11474   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11475                                         ? hard_regno_nregs[reg_dead_regno]
11476                                                           [GET_MODE (reg)]
11477                                         : 1);
11478
11479   reg_dead_flag = 0;
11480
11481   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11482      we allow the machine description to decide whether use-and-clobber
11483      patterns are OK.  */
11484   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11485     {
11486       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11487         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11488           return 0;
11489     }
11490
11491   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11492      beginning of function.  */
11493   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11494        insn = prev_nonnote_insn (insn))
11495     {
11496       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11497       if (reg_dead_flag)
11498         return reg_dead_flag == 1 ? 1 : 0;
11499
11500       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11501         return 1;
11502     }
11503
11504   /* Get the basic block that we were in.  */
11505   if (insn == 0)
11506     block = ENTRY_BLOCK_PTR->next_bb;
11507   else
11508     {
11509       FOR_EACH_BB (block)
11510         if (insn == BB_HEAD (block))
11511           break;
11512
11513       if (block == EXIT_BLOCK_PTR)
11514         return 0;
11515     }
11516
11517   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11518     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11519       return 0;
11520
11521   return 1;
11522 }
11523 \f
11524 /* Note hard registers in X that are used.  This code is similar to
11525    that in flow.c, but much simpler since we don't care about pseudos.  */
11526
11527 static void
11528 mark_used_regs_combine (rtx x)
11529 {
11530   RTX_CODE code = GET_CODE (x);
11531   unsigned int regno;
11532   int i;
11533
11534   switch (code)
11535     {
11536     case LABEL_REF:
11537     case SYMBOL_REF:
11538     case CONST_INT:
11539     case CONST:
11540     case CONST_DOUBLE:
11541     case CONST_VECTOR:
11542     case PC:
11543     case ADDR_VEC:
11544     case ADDR_DIFF_VEC:
11545     case ASM_INPUT:
11546 #ifdef HAVE_cc0
11547     /* CC0 must die in the insn after it is set, so we don't need to take
11548        special note of it here.  */
11549     case CC0:
11550 #endif
11551       return;
11552
11553     case CLOBBER:
11554       /* If we are clobbering a MEM, mark any hard registers inside the
11555          address as used.  */
11556       if (MEM_P (XEXP (x, 0)))
11557         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11558       return;
11559
11560     case REG:
11561       regno = REGNO (x);
11562       /* A hard reg in a wide mode may really be multiple registers.
11563          If so, mark all of them just like the first.  */
11564       if (regno < FIRST_PSEUDO_REGISTER)
11565         {
11566           unsigned int endregno, r;
11567
11568           /* None of this applies to the stack, frame or arg pointers.  */
11569           if (regno == STACK_POINTER_REGNUM
11570 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11571               || regno == HARD_FRAME_POINTER_REGNUM
11572 #endif
11573 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11574               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11575 #endif
11576               || regno == FRAME_POINTER_REGNUM)
11577             return;
11578
11579           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11580           for (r = regno; r < endregno; r++)
11581             SET_HARD_REG_BIT (newpat_used_regs, r);
11582         }
11583       return;
11584
11585     case SET:
11586       {
11587         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11588            the address.  */
11589         rtx testreg = SET_DEST (x);
11590
11591         while (GET_CODE (testreg) == SUBREG
11592                || GET_CODE (testreg) == ZERO_EXTRACT
11593                || GET_CODE (testreg) == STRICT_LOW_PART)
11594           testreg = XEXP (testreg, 0);
11595
11596         if (MEM_P (testreg))
11597           mark_used_regs_combine (XEXP (testreg, 0));
11598
11599         mark_used_regs_combine (SET_SRC (x));
11600       }
11601       return;
11602
11603     default:
11604       break;
11605     }
11606
11607   /* Recursively scan the operands of this expression.  */
11608
11609   {
11610     const char *fmt = GET_RTX_FORMAT (code);
11611
11612     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11613       {
11614         if (fmt[i] == 'e')
11615           mark_used_regs_combine (XEXP (x, i));
11616         else if (fmt[i] == 'E')
11617           {
11618             int j;
11619
11620             for (j = 0; j < XVECLEN (x, i); j++)
11621               mark_used_regs_combine (XVECEXP (x, i, j));
11622           }
11623       }
11624   }
11625 }
11626 \f
11627 /* Remove register number REGNO from the dead registers list of INSN.
11628
11629    Return the note used to record the death, if there was one.  */
11630
11631 rtx
11632 remove_death (unsigned int regno, rtx insn)
11633 {
11634   rtx note = find_regno_note (insn, REG_DEAD, regno);
11635
11636   if (note)
11637     {
11638       REG_N_DEATHS (regno)--;
11639       remove_note (insn, note);
11640     }
11641
11642   return note;
11643 }
11644
11645 /* For each register (hardware or pseudo) used within expression X, if its
11646    death is in an instruction with cuid between FROM_CUID (inclusive) and
11647    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11648    list headed by PNOTES.
11649
11650    That said, don't move registers killed by maybe_kill_insn.
11651
11652    This is done when X is being merged by combination into TO_INSN.  These
11653    notes will then be distributed as needed.  */
11654
11655 static void
11656 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11657              rtx *pnotes)
11658 {
11659   const char *fmt;
11660   int len, i;
11661   enum rtx_code code = GET_CODE (x);
11662
11663   if (code == REG)
11664     {
11665       unsigned int regno = REGNO (x);
11666       rtx where_dead = reg_stat[regno].last_death;
11667       rtx before_dead, after_dead;
11668
11669       /* Don't move the register if it gets killed in between from and to.  */
11670       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11671           && ! reg_referenced_p (x, maybe_kill_insn))
11672         return;
11673
11674       /* WHERE_DEAD could be a USE insn made by combine, so first we
11675          make sure that we have insns with valid INSN_CUID values.  */
11676       before_dead = where_dead;
11677       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11678         before_dead = PREV_INSN (before_dead);
11679
11680       after_dead = where_dead;
11681       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11682         after_dead = NEXT_INSN (after_dead);
11683
11684       if (before_dead && after_dead
11685           && INSN_CUID (before_dead) >= from_cuid
11686           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11687               || (where_dead != after_dead
11688                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11689         {
11690           rtx note = remove_death (regno, where_dead);
11691
11692           /* It is possible for the call above to return 0.  This can occur
11693              when last_death points to I2 or I1 that we combined with.
11694              In that case make a new note.
11695
11696              We must also check for the case where X is a hard register
11697              and NOTE is a death note for a range of hard registers
11698              including X.  In that case, we must put REG_DEAD notes for
11699              the remaining registers in place of NOTE.  */
11700
11701           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11702               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11703                   > GET_MODE_SIZE (GET_MODE (x))))
11704             {
11705               unsigned int deadregno = REGNO (XEXP (note, 0));
11706               unsigned int deadend
11707                 = (deadregno + hard_regno_nregs[deadregno]
11708                                                [GET_MODE (XEXP (note, 0))]);
11709               unsigned int ourend
11710                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11711               unsigned int i;
11712
11713               for (i = deadregno; i < deadend; i++)
11714                 if (i < regno || i >= ourend)
11715                   REG_NOTES (where_dead)
11716                     = gen_rtx_EXPR_LIST (REG_DEAD,
11717                                          regno_reg_rtx[i],
11718                                          REG_NOTES (where_dead));
11719             }
11720
11721           /* If we didn't find any note, or if we found a REG_DEAD note that
11722              covers only part of the given reg, and we have a multi-reg hard
11723              register, then to be safe we must check for REG_DEAD notes
11724              for each register other than the first.  They could have
11725              their own REG_DEAD notes lying around.  */
11726           else if ((note == 0
11727                     || (note != 0
11728                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11729                             < GET_MODE_SIZE (GET_MODE (x)))))
11730                    && regno < FIRST_PSEUDO_REGISTER
11731                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11732             {
11733               unsigned int ourend
11734                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11735               unsigned int i, offset;
11736               rtx oldnotes = 0;
11737
11738               if (note)
11739                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11740               else
11741                 offset = 1;
11742
11743               for (i = regno + offset; i < ourend; i++)
11744                 move_deaths (regno_reg_rtx[i],
11745                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11746             }
11747
11748           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11749             {
11750               XEXP (note, 1) = *pnotes;
11751               *pnotes = note;
11752             }
11753           else
11754             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11755
11756           REG_N_DEATHS (regno)++;
11757         }
11758
11759       return;
11760     }
11761
11762   else if (GET_CODE (x) == SET)
11763     {
11764       rtx dest = SET_DEST (x);
11765
11766       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11767
11768       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11769          that accesses one word of a multi-word item, some
11770          piece of everything register in the expression is used by
11771          this insn, so remove any old death.  */
11772       /* ??? So why do we test for equality of the sizes?  */
11773
11774       if (GET_CODE (dest) == ZERO_EXTRACT
11775           || GET_CODE (dest) == STRICT_LOW_PART
11776           || (GET_CODE (dest) == SUBREG
11777               && (((GET_MODE_SIZE (GET_MODE (dest))
11778                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11779                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11780                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11781         {
11782           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11783           return;
11784         }
11785
11786       /* If this is some other SUBREG, we know it replaces the entire
11787          value, so use that as the destination.  */
11788       if (GET_CODE (dest) == SUBREG)
11789         dest = SUBREG_REG (dest);
11790
11791       /* If this is a MEM, adjust deaths of anything used in the address.
11792          For a REG (the only other possibility), the entire value is
11793          being replaced so the old value is not used in this insn.  */
11794
11795       if (MEM_P (dest))
11796         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11797                      to_insn, pnotes);
11798       return;
11799     }
11800
11801   else if (GET_CODE (x) == CLOBBER)
11802     return;
11803
11804   len = GET_RTX_LENGTH (code);
11805   fmt = GET_RTX_FORMAT (code);
11806
11807   for (i = 0; i < len; i++)
11808     {
11809       if (fmt[i] == 'E')
11810         {
11811           int j;
11812           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11813             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11814                          to_insn, pnotes);
11815         }
11816       else if (fmt[i] == 'e')
11817         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11818     }
11819 }
11820 \f
11821 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11822    pattern of an insn.  X must be a REG.  */
11823
11824 static int
11825 reg_bitfield_target_p (rtx x, rtx body)
11826 {
11827   int i;
11828
11829   if (GET_CODE (body) == SET)
11830     {
11831       rtx dest = SET_DEST (body);
11832       rtx target;
11833       unsigned int regno, tregno, endregno, endtregno;
11834
11835       if (GET_CODE (dest) == ZERO_EXTRACT)
11836         target = XEXP (dest, 0);
11837       else if (GET_CODE (dest) == STRICT_LOW_PART)
11838         target = SUBREG_REG (XEXP (dest, 0));
11839       else
11840         return 0;
11841
11842       if (GET_CODE (target) == SUBREG)
11843         target = SUBREG_REG (target);
11844
11845       if (!REG_P (target))
11846         return 0;
11847
11848       tregno = REGNO (target), regno = REGNO (x);
11849       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11850         return target == x;
11851
11852       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11853       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11854
11855       return endregno > tregno && regno < endtregno;
11856     }
11857
11858   else if (GET_CODE (body) == PARALLEL)
11859     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11860       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11861         return 1;
11862
11863   return 0;
11864 }
11865 \f
11866 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11867    as appropriate.  I3 and I2 are the insns resulting from the combination
11868    insns including FROM (I2 may be zero).
11869
11870    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11871    not need REG_DEAD notes because they are being substituted for.  This
11872    saves searching in the most common cases.
11873
11874    Each note in the list is either ignored or placed on some insns, depending
11875    on the type of note.  */
11876
11877 static void
11878 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11879                   rtx elim_i1)
11880 {
11881   rtx note, next_note;
11882   rtx tem;
11883
11884   for (note = notes; note; note = next_note)
11885     {
11886       rtx place = 0, place2 = 0;
11887
11888       next_note = XEXP (note, 1);
11889       switch (REG_NOTE_KIND (note))
11890         {
11891         case REG_BR_PROB:
11892         case REG_BR_PRED:
11893           /* Doesn't matter much where we put this, as long as it's somewhere.
11894              It is preferable to keep these notes on branches, which is most
11895              likely to be i3.  */
11896           place = i3;
11897           break;
11898
11899         case REG_VALUE_PROFILE:
11900           /* Just get rid of this note, as it is unused later anyway.  */
11901           break;
11902
11903         case REG_NON_LOCAL_GOTO:
11904           if (JUMP_P (i3))
11905             place = i3;
11906           else
11907             {
11908               gcc_assert (i2 && JUMP_P (i2));
11909               place = i2;
11910             }
11911           break;
11912
11913         case REG_EH_REGION:
11914           /* These notes must remain with the call or trapping instruction.  */
11915           if (CALL_P (i3))
11916             place = i3;
11917           else if (i2 && CALL_P (i2))
11918             place = i2;
11919           else
11920             {
11921               gcc_assert (flag_non_call_exceptions);
11922               if (may_trap_p (i3))
11923                 place = i3;
11924               else if (i2 && may_trap_p (i2))
11925                 place = i2;
11926               /* ??? Otherwise assume we've combined things such that we
11927                  can now prove that the instructions can't trap.  Drop the
11928                  note in this case.  */
11929             }
11930           break;
11931
11932         case REG_NORETURN:
11933         case REG_SETJMP:
11934           /* These notes must remain with the call.  It should not be
11935              possible for both I2 and I3 to be a call.  */
11936           if (CALL_P (i3))
11937             place = i3;
11938           else
11939             {
11940               gcc_assert (i2 && CALL_P (i2));
11941               place = i2;
11942             }
11943           break;
11944
11945         case REG_UNUSED:
11946           /* Any clobbers for i3 may still exist, and so we must process
11947              REG_UNUSED notes from that insn.
11948
11949              Any clobbers from i2 or i1 can only exist if they were added by
11950              recog_for_combine.  In that case, recog_for_combine created the
11951              necessary REG_UNUSED notes.  Trying to keep any original
11952              REG_UNUSED notes from these insns can cause incorrect output
11953              if it is for the same register as the original i3 dest.
11954              In that case, we will notice that the register is set in i3,
11955              and then add a REG_UNUSED note for the destination of i3, which
11956              is wrong.  However, it is possible to have REG_UNUSED notes from
11957              i2 or i1 for register which were both used and clobbered, so
11958              we keep notes from i2 or i1 if they will turn into REG_DEAD
11959              notes.  */
11960
11961           /* If this register is set or clobbered in I3, put the note there
11962              unless there is one already.  */
11963           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11964             {
11965               if (from_insn != i3)
11966                 break;
11967
11968               if (! (REG_P (XEXP (note, 0))
11969                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11970                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11971                 place = i3;
11972             }
11973           /* Otherwise, if this register is used by I3, then this register
11974              now dies here, so we must put a REG_DEAD note here unless there
11975              is one already.  */
11976           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11977                    && ! (REG_P (XEXP (note, 0))
11978                          ? find_regno_note (i3, REG_DEAD,
11979                                             REGNO (XEXP (note, 0)))
11980                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11981             {
11982               PUT_REG_NOTE_KIND (note, REG_DEAD);
11983               place = i3;
11984             }
11985           break;
11986
11987         case REG_EQUAL:
11988         case REG_EQUIV:
11989         case REG_NOALIAS:
11990           /* These notes say something about results of an insn.  We can
11991              only support them if they used to be on I3 in which case they
11992              remain on I3.  Otherwise they are ignored.
11993
11994              If the note refers to an expression that is not a constant, we
11995              must also ignore the note since we cannot tell whether the
11996              equivalence is still true.  It might be possible to do
11997              slightly better than this (we only have a problem if I2DEST
11998              or I1DEST is present in the expression), but it doesn't
11999              seem worth the trouble.  */
12000
12001           if (from_insn == i3
12002               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12003             place = i3;
12004           break;
12005
12006         case REG_INC:
12007         case REG_NO_CONFLICT:
12008           /* These notes say something about how a register is used.  They must
12009              be present on any use of the register in I2 or I3.  */
12010           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12011             place = i3;
12012
12013           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12014             {
12015               if (place)
12016                 place2 = i2;
12017               else
12018                 place = i2;
12019             }
12020           break;
12021
12022         case REG_LABEL:
12023           /* This can show up in several ways -- either directly in the
12024              pattern, or hidden off in the constant pool with (or without?)
12025              a REG_EQUAL note.  */
12026           /* ??? Ignore the without-reg_equal-note problem for now.  */
12027           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12028               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12029                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12030                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12031             place = i3;
12032
12033           if (i2
12034               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12035                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12036                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12037                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12038             {
12039               if (place)
12040                 place2 = i2;
12041               else
12042                 place = i2;
12043             }
12044
12045           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12046              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12047           if (place && JUMP_P (place))
12048             {
12049               rtx label = JUMP_LABEL (place);
12050
12051               if (!label)
12052                 JUMP_LABEL (place) = XEXP (note, 0);
12053               else
12054                 {
12055                   gcc_assert (label == XEXP (note, 0));
12056                   if (LABEL_P (label))
12057                     LABEL_NUSES (label)--;
12058                 }
12059               place = 0;
12060             }
12061           if (place2 && JUMP_P (place2))
12062             {
12063               rtx label = JUMP_LABEL (place2);
12064
12065               if (!label)
12066                 JUMP_LABEL (place2) = XEXP (note, 0);
12067               else
12068                 {
12069                   gcc_assert (label == XEXP (note, 0));
12070                   if (LABEL_P (label))
12071                     LABEL_NUSES (label)--;
12072                 }
12073               place2 = 0;
12074             }
12075           break;
12076
12077         case REG_NONNEG:
12078           /* This note says something about the value of a register prior
12079              to the execution of an insn.  It is too much trouble to see
12080              if the note is still correct in all situations.  It is better
12081              to simply delete it.  */
12082           break;
12083
12084         case REG_RETVAL:
12085           /* If the insn previously containing this note still exists,
12086              put it back where it was.  Otherwise move it to the previous
12087              insn.  Adjust the corresponding REG_LIBCALL note.  */
12088           if (!NOTE_P (from_insn))
12089             place = from_insn;
12090           else
12091             {
12092               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12093               place = prev_real_insn (from_insn);
12094               if (tem && place)
12095                 XEXP (tem, 0) = place;
12096               /* If we're deleting the last remaining instruction of a
12097                  libcall sequence, don't add the notes.  */
12098               else if (XEXP (note, 0) == from_insn)
12099                 tem = place = 0;
12100               /* Don't add the dangling REG_RETVAL note.  */
12101               else if (! tem)
12102                 place = 0;
12103             }
12104           break;
12105
12106         case REG_LIBCALL:
12107           /* This is handled similarly to REG_RETVAL.  */
12108           if (!NOTE_P (from_insn))
12109             place = from_insn;
12110           else
12111             {
12112               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12113               place = next_real_insn (from_insn);
12114               if (tem && place)
12115                 XEXP (tem, 0) = place;
12116               /* If we're deleting the last remaining instruction of a
12117                  libcall sequence, don't add the notes.  */
12118               else if (XEXP (note, 0) == from_insn)
12119                 tem = place = 0;
12120               /* Don't add the dangling REG_LIBCALL note.  */
12121               else if (! tem)
12122                 place = 0;
12123             }
12124           break;
12125
12126         case REG_DEAD:
12127           /* If we replaced the right hand side of FROM_INSN with a
12128              REG_EQUAL note, the original use of the dying register
12129              will not have been combined into I3 and I2.  In such cases,
12130              FROM_INSN is guaranteed to be the first of the combined
12131              instructions, so we simply need to search back before
12132              FROM_INSN for the previous use or set of this register,
12133              then alter the notes there appropriately.
12134
12135              If the register is used as an input in I3, it dies there.
12136              Similarly for I2, if it is nonzero and adjacent to I3.
12137
12138              If the register is not used as an input in either I3 or I2
12139              and it is not one of the registers we were supposed to eliminate,
12140              there are two possibilities.  We might have a non-adjacent I2
12141              or we might have somehow eliminated an additional register
12142              from a computation.  For example, we might have had A & B where
12143              we discover that B will always be zero.  In this case we will
12144              eliminate the reference to A.
12145
12146              In both cases, we must search to see if we can find a previous
12147              use of A and put the death note there.  */
12148
12149           if (from_insn
12150               && from_insn == i2mod
12151               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12152             tem = from_insn;
12153           else
12154             {
12155               if (from_insn
12156                   && CALL_P (from_insn)
12157                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12158                 place = from_insn;
12159               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12160                 place = i3;
12161               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12162                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12163                 place = i2;
12164               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12165                         && !(i2mod
12166                              && reg_overlap_mentioned_p (XEXP (note, 0),
12167                                                          i2mod_old_rhs)))
12168                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12169                 break;
12170               tem = i3;
12171             }
12172
12173           if (place == 0)
12174             {
12175               basic_block bb = this_basic_block;
12176
12177               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12178                 {
12179                   if (! INSN_P (tem))
12180                     {
12181                       if (tem == BB_HEAD (bb))
12182                         break;
12183                       continue;
12184                     }
12185
12186                   /* If the register is being set at TEM, see if that is all
12187                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12188                      into a REG_UNUSED note instead. Don't delete sets to
12189                      global register vars.  */
12190                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12191                        || !global_regs[REGNO (XEXP (note, 0))])
12192                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12193                     {
12194                       rtx set = single_set (tem);
12195                       rtx inner_dest = 0;
12196 #ifdef HAVE_cc0
12197                       rtx cc0_setter = NULL_RTX;
12198 #endif
12199
12200                       if (set != 0)
12201                         for (inner_dest = SET_DEST (set);
12202                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12203                               || GET_CODE (inner_dest) == SUBREG
12204                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12205                              inner_dest = XEXP (inner_dest, 0))
12206                           ;
12207
12208                       /* Verify that it was the set, and not a clobber that
12209                          modified the register.
12210
12211                          CC0 targets must be careful to maintain setter/user
12212                          pairs.  If we cannot delete the setter due to side
12213                          effects, mark the user with an UNUSED note instead
12214                          of deleting it.  */
12215
12216                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12217                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12218 #ifdef HAVE_cc0
12219                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12220                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12221                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12222 #endif
12223                           )
12224                         {
12225                           /* Move the notes and links of TEM elsewhere.
12226                              This might delete other dead insns recursively.
12227                              First set the pattern to something that won't use
12228                              any register.  */
12229                           rtx old_notes = REG_NOTES (tem);
12230
12231                           PATTERN (tem) = pc_rtx;
12232                           REG_NOTES (tem) = NULL;
12233
12234                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12235                                             NULL_RTX, NULL_RTX);
12236                           distribute_links (LOG_LINKS (tem));
12237
12238                           SET_INSN_DELETED (tem);
12239
12240 #ifdef HAVE_cc0
12241                           /* Delete the setter too.  */
12242                           if (cc0_setter)
12243                             {
12244                               PATTERN (cc0_setter) = pc_rtx;
12245                               old_notes = REG_NOTES (cc0_setter);
12246                               REG_NOTES (cc0_setter) = NULL;
12247
12248                               distribute_notes (old_notes, cc0_setter,
12249                                                 cc0_setter, NULL_RTX,
12250                                                 NULL_RTX, NULL_RTX);
12251                               distribute_links (LOG_LINKS (cc0_setter));
12252
12253                               SET_INSN_DELETED (cc0_setter);
12254                             }
12255 #endif
12256                         }
12257                       else
12258                         {
12259                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12260
12261                           /*  If there isn't already a REG_UNUSED note, put one
12262                               here.  Do not place a REG_DEAD note, even if
12263                               the register is also used here; that would not
12264                               match the algorithm used in lifetime analysis
12265                               and can cause the consistency check in the
12266                               scheduler to fail.  */
12267                           if (! find_regno_note (tem, REG_UNUSED,
12268                                                  REGNO (XEXP (note, 0))))
12269                             place = tem;
12270                           break;
12271                         }
12272                     }
12273                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12274                            || (CALL_P (tem)
12275                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12276                     {
12277                       place = tem;
12278
12279                       /* If we are doing a 3->2 combination, and we have a
12280                          register which formerly died in i3 and was not used
12281                          by i2, which now no longer dies in i3 and is used in
12282                          i2 but does not die in i2, and place is between i2
12283                          and i3, then we may need to move a link from place to
12284                          i2.  */
12285                       if (i2 && INSN_UID (place) <= max_uid_cuid
12286                           && INSN_CUID (place) > INSN_CUID (i2)
12287                           && from_insn
12288                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12289                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12290                         {
12291                           rtx links = LOG_LINKS (place);
12292                           LOG_LINKS (place) = 0;
12293                           distribute_links (links);
12294                         }
12295                       break;
12296                     }
12297
12298                   if (tem == BB_HEAD (bb))
12299                     break;
12300                 }
12301
12302               /* We haven't found an insn for the death note and it
12303                  is still a REG_DEAD note, but we have hit the beginning
12304                  of the block.  If the existing life info says the reg
12305                  was dead, there's nothing left to do.  Otherwise, we'll
12306                  need to do a global life update after combine.  */
12307               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12308                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12309                                       REGNO (XEXP (note, 0))))
12310                 SET_BIT (refresh_blocks, this_basic_block->index);
12311             }
12312
12313           /* If the register is set or already dead at PLACE, we needn't do
12314              anything with this note if it is still a REG_DEAD note.
12315              We check here if it is set at all, not if is it totally replaced,
12316              which is what `dead_or_set_p' checks, so also check for it being
12317              set partially.  */
12318
12319           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12320             {
12321               unsigned int regno = REGNO (XEXP (note, 0));
12322
12323               /* Similarly, if the instruction on which we want to place
12324                  the note is a noop, we'll need do a global live update
12325                  after we remove them in delete_noop_moves.  */
12326               if (noop_move_p (place))
12327                 SET_BIT (refresh_blocks, this_basic_block->index);
12328
12329               if (dead_or_set_p (place, XEXP (note, 0))
12330                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12331                 {
12332                   /* Unless the register previously died in PLACE, clear
12333                      last_death.  [I no longer understand why this is
12334                      being done.] */
12335                   if (reg_stat[regno].last_death != place)
12336                     reg_stat[regno].last_death = 0;
12337                   place = 0;
12338                 }
12339               else
12340                 reg_stat[regno].last_death = place;
12341
12342               /* If this is a death note for a hard reg that is occupying
12343                  multiple registers, ensure that we are still using all
12344                  parts of the object.  If we find a piece of the object
12345                  that is unused, we must arrange for an appropriate REG_DEAD
12346                  note to be added for it.  However, we can't just emit a USE
12347                  and tag the note to it, since the register might actually
12348                  be dead; so we recourse, and the recursive call then finds
12349                  the previous insn that used this register.  */
12350
12351               if (place && regno < FIRST_PSEUDO_REGISTER
12352                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12353                 {
12354                   unsigned int endregno
12355                     = regno + hard_regno_nregs[regno]
12356                                               [GET_MODE (XEXP (note, 0))];
12357                   int all_used = 1;
12358                   unsigned int i;
12359
12360                   for (i = regno; i < endregno; i++)
12361                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12362                          && ! find_regno_fusage (place, USE, i))
12363                         || dead_or_set_regno_p (place, i))
12364                       all_used = 0;
12365
12366                   if (! all_used)
12367                     {
12368                       /* Put only REG_DEAD notes for pieces that are
12369                          not already dead or set.  */
12370
12371                       for (i = regno; i < endregno;
12372                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12373                         {
12374                           rtx piece = regno_reg_rtx[i];
12375                           basic_block bb = this_basic_block;
12376
12377                           if (! dead_or_set_p (place, piece)
12378                               && ! reg_bitfield_target_p (piece,
12379                                                           PATTERN (place)))
12380                             {
12381                               rtx new_note
12382                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12383
12384                               distribute_notes (new_note, place, place,
12385                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12386                             }
12387                           else if (! refers_to_regno_p (i, i + 1,
12388                                                         PATTERN (place), 0)
12389                                    && ! find_regno_fusage (place, USE, i))
12390                             for (tem = PREV_INSN (place); ;
12391                                  tem = PREV_INSN (tem))
12392                               {
12393                                 if (! INSN_P (tem))
12394                                   {
12395                                     if (tem == BB_HEAD (bb))
12396                                       {
12397                                         SET_BIT (refresh_blocks,
12398                                                  this_basic_block->index);
12399                                         break;
12400                                       }
12401                                     continue;
12402                                   }
12403                                 if (dead_or_set_p (tem, piece)
12404                                     || reg_bitfield_target_p (piece,
12405                                                               PATTERN (tem)))
12406                                   {
12407                                     REG_NOTES (tem)
12408                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12409                                                            REG_NOTES (tem));
12410                                     break;
12411                                   }
12412                               }
12413
12414                         }
12415
12416                       place = 0;
12417                     }
12418                 }
12419             }
12420           break;
12421
12422         default:
12423           /* Any other notes should not be present at this point in the
12424              compilation.  */
12425           gcc_unreachable ();
12426         }
12427
12428       if (place)
12429         {
12430           XEXP (note, 1) = REG_NOTES (place);
12431           REG_NOTES (place) = note;
12432         }
12433       else if ((REG_NOTE_KIND (note) == REG_DEAD
12434                 || REG_NOTE_KIND (note) == REG_UNUSED)
12435                && REG_P (XEXP (note, 0)))
12436         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12437
12438       if (place2)
12439         {
12440           if ((REG_NOTE_KIND (note) == REG_DEAD
12441                || REG_NOTE_KIND (note) == REG_UNUSED)
12442               && REG_P (XEXP (note, 0)))
12443             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12444
12445           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12446                                                REG_NOTE_KIND (note),
12447                                                XEXP (note, 0),
12448                                                REG_NOTES (place2));
12449         }
12450     }
12451 }
12452 \f
12453 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12454    I3, I2, and I1 to new locations.  This is also called to add a link
12455    pointing at I3 when I3's destination is changed.  */
12456
12457 static void
12458 distribute_links (rtx links)
12459 {
12460   rtx link, next_link;
12461
12462   for (link = links; link; link = next_link)
12463     {
12464       rtx place = 0;
12465       rtx insn;
12466       rtx set, reg;
12467
12468       next_link = XEXP (link, 1);
12469
12470       /* If the insn that this link points to is a NOTE or isn't a single
12471          set, ignore it.  In the latter case, it isn't clear what we
12472          can do other than ignore the link, since we can't tell which
12473          register it was for.  Such links wouldn't be used by combine
12474          anyway.
12475
12476          It is not possible for the destination of the target of the link to
12477          have been changed by combine.  The only potential of this is if we
12478          replace I3, I2, and I1 by I3 and I2.  But in that case the
12479          destination of I2 also remains unchanged.  */
12480
12481       if (NOTE_P (XEXP (link, 0))
12482           || (set = single_set (XEXP (link, 0))) == 0)
12483         continue;
12484
12485       reg = SET_DEST (set);
12486       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12487              || GET_CODE (reg) == STRICT_LOW_PART)
12488         reg = XEXP (reg, 0);
12489
12490       /* A LOG_LINK is defined as being placed on the first insn that uses
12491          a register and points to the insn that sets the register.  Start
12492          searching at the next insn after the target of the link and stop
12493          when we reach a set of the register or the end of the basic block.
12494
12495          Note that this correctly handles the link that used to point from
12496          I3 to I2.  Also note that not much searching is typically done here
12497          since most links don't point very far away.  */
12498
12499       for (insn = NEXT_INSN (XEXP (link, 0));
12500            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12501                      || BB_HEAD (this_basic_block->next_bb) != insn));
12502            insn = NEXT_INSN (insn))
12503         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12504           {
12505             if (reg_referenced_p (reg, PATTERN (insn)))
12506               place = insn;
12507             break;
12508           }
12509         else if (CALL_P (insn)
12510                  && find_reg_fusage (insn, USE, reg))
12511           {
12512             place = insn;
12513             break;
12514           }
12515         else if (INSN_P (insn) && reg_set_p (reg, insn))
12516           break;
12517
12518       /* If we found a place to put the link, place it there unless there
12519          is already a link to the same insn as LINK at that point.  */
12520
12521       if (place)
12522         {
12523           rtx link2;
12524
12525           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12526             if (XEXP (link2, 0) == XEXP (link, 0))
12527               break;
12528
12529           if (link2 == 0)
12530             {
12531               XEXP (link, 1) = LOG_LINKS (place);
12532               LOG_LINKS (place) = link;
12533
12534               /* Set added_links_insn to the earliest insn we added a
12535                  link to.  */
12536               if (added_links_insn == 0
12537                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12538                 added_links_insn = place;
12539             }
12540         }
12541     }
12542 }
12543 \f
12544 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12545    Check whether the expression pointer to by LOC is a register or
12546    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12547    Otherwise return zero.  */
12548
12549 static int
12550 unmentioned_reg_p_1 (rtx *loc, void *expr)
12551 {
12552   rtx x = *loc;
12553
12554   if (x != NULL_RTX
12555       && (REG_P (x) || MEM_P (x))
12556       && ! reg_mentioned_p (x, (rtx) expr))
12557     return 1;
12558   return 0;
12559 }
12560
12561 /* Check for any register or memory mentioned in EQUIV that is not
12562    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12563    of EXPR where some registers may have been replaced by constants.  */
12564
12565 static bool
12566 unmentioned_reg_p (rtx equiv, rtx expr)
12567 {
12568   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12569 }
12570 \f
12571 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12572
12573 static int
12574 insn_cuid (rtx insn)
12575 {
12576   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12577          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12578     insn = NEXT_INSN (insn);
12579
12580   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12581
12582   return INSN_CUID (insn);
12583 }
12584 \f
12585 void
12586 dump_combine_stats (FILE *file)
12587 {
12588   fprintf
12589     (file,
12590      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12591      combine_attempts, combine_merges, combine_extras, combine_successes);
12592 }
12593
12594 void
12595 dump_combine_total_stats (FILE *file)
12596 {
12597   fprintf
12598     (file,
12599      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12600      total_attempts, total_merges, total_extras, total_successes);
12601 }
12602 \f
12603
12604 static bool
12605 gate_handle_combine (void)
12606 {
12607   return (optimize > 0);
12608 }
12609
12610 /* Try combining insns through substitution.  */
12611 static unsigned int
12612 rest_of_handle_combine (void)
12613 {
12614   int rebuild_jump_labels_after_combine
12615     = combine_instructions (get_insns (), max_reg_num ());
12616
12617   /* Combining insns may have turned an indirect jump into a
12618      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12619      instructions.  */
12620   if (rebuild_jump_labels_after_combine)
12621     {
12622       timevar_push (TV_JUMP);
12623       rebuild_jump_labels (get_insns ());
12624       timevar_pop (TV_JUMP);
12625
12626       delete_dead_jumptables ();
12627       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12628     }
12629   return 0;
12630 }
12631
12632 struct tree_opt_pass pass_combine =
12633 {
12634   "combine",                            /* name */
12635   gate_handle_combine,                  /* gate */
12636   rest_of_handle_combine,               /* execute */
12637   NULL,                                 /* sub */
12638   NULL,                                 /* next */
12639   0,                                    /* static_pass_number */
12640   TV_COMBINE,                           /* tv_id */
12641   0,                                    /* properties_required */
12642   0,                                    /* properties_provided */
12643   0,                                    /* properties_destroyed */
12644   0,                                    /* todo_flags_start */
12645   TODO_dump_func |
12646   TODO_ggc_collect,                     /* todo_flags_finish */
12647   'c'                                   /* letter */
12648 };
12649