| blob | 38da3a4a1f6a21afca8a5632383c5b20314613e0 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
63 #endif
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
71 : 4)
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 const
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
107 in SFmode, DFmode and XFmode */
109 in SFmode, DFmode and XFmode */
112 in SImode and DImode */
114 in SImode and DImode */
117 in SImode, DImode and TImode */
119 in SImode, DImode and TImode */
147 };
149 /* Processor costs (relative to an add) */
150 static const
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
178 in SFmode, DFmode and XFmode */
180 in SFmode, DFmode and XFmode */
183 in SImode and DImode */
185 in SImode and DImode */
188 in SImode, DImode and TImode */
190 in SImode, DImode and TImode */
204 DUMMY_STRINGOP_ALGS},
206 DUMMY_STRINGOP_ALGS},
218 };
220 static const
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
248 in SFmode, DFmode and XFmode */
250 in SFmode, DFmode and XFmode */
253 in SImode and DImode */
255 in SImode and DImode */
258 in SImode, DImode and TImode */
260 in SImode, DImode and TImode */
263 shared for code and data, so 4kB is
264 not really precise. */
276 DUMMY_STRINGOP_ALGS},
278 DUMMY_STRINGOP_ALGS},
290 };
292 static const
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
320 in SFmode, DFmode and XFmode */
322 in SFmode, DFmode and XFmode */
325 in SImode and DImode */
327 in SImode and DImode */
330 in SImode, DImode and TImode */
332 in SImode, DImode and TImode */
346 DUMMY_STRINGOP_ALGS},
348 DUMMY_STRINGOP_ALGS},
360 };
362 static const
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
390 in SFmode, DFmode and XFmode */
392 in SFmode, DFmode and XFmode */
395 in SImode and DImode */
397 in SImode and DImode */
400 in SImode, DImode and TImode */
402 in SImode, DImode and TImode */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 */
422 DUMMY_STRINGOP_ALGS},
425 DUMMY_STRINGOP_ALGS},
437 };
439 static const
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
467 in SFmode, DFmode and XFmode */
469 in SFmode, DFmode and XFmode */
473 in SImode and DImode */
475 in SImode and DImode */
478 in SImode, DImode and TImode */
480 in SImode, DImode and TImode */
494 DUMMY_STRINGOP_ALGS},
496 DUMMY_STRINGOP_ALGS},
508 };
510 static const
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
538 in SFmode, DFmode and XFmode */
540 in SFmode, DFmode and XFmode */
543 in SImode and DImode */
545 in SImode and DImode */
548 in SImode, DImode and TImode */
550 in SImode, DImode and TImode */
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
567 DUMMY_STRINGOP_ALGS},
569 DUMMY_STRINGOP_ALGS},
581 };
583 static const
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
611 in SFmode, DFmode and XFmode */
613 in SFmode, DFmode and XFmode */
616 in SImode and DImode */
618 in SImode and DImode */
621 in SImode, DImode and TImode */
623 in SImode, DImode and TImode */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
640 DUMMY_STRINGOP_ALGS},
642 DUMMY_STRINGOP_ALGS},
654 };
656 static const
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
684 in SFmode, DFmode and XFmode */
686 in SFmode, DFmode and XFmode */
689 in SImode and DImode */
691 in SImode and DImode */
694 in SImode, DImode and TImode */
696 in SImode, DImode and TImode */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
705 time). */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
733 };
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
762 in SFmode, DFmode and XFmode */
764 in SFmode, DFmode and XFmode */
767 in SImode and DImode */
769 in SImode and DImode */
772 in SImode, DImode and TImode */
774 in SImode, DImode and TImode */
776 /* On K8
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
779 On AMDFAM10
780 MOVD reg64, xmmreg Double FADD 3
781 1/1 1/1
782 MOVD reg32, xmmreg Double FADD 3
783 1/1 1/1 */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
791 time). */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
820 };
822 static const
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
850 in SFmode, DFmode and XFmode */
852 in SFmode, DFmode and XFmode */
855 in SImode and DImode */
857 in SImode and DImode */
860 in SImode, DImode and TImode */
862 in SImode, DImode and TImode */
876 DUMMY_STRINGOP_ALGS},
879 DUMMY_STRINGOP_ALGS},
891 };
893 static const
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
921 in SFmode, DFmode and XFmode */
923 in SFmode, DFmode and XFmode */
926 in SImode and DImode */
928 in SImode and DImode */
931 in SImode, DImode and TImode */
933 in SImode, DImode and TImode */
964 };
966 static const
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
994 in SFmode, DFmode and XFmode */
996 in SFmode, DFmode and XFmode */
999 in SImode and DImode */
1001 in SImode and DImode */
1004 in SImode, DImode and TImode */
1006 in SImode, DImode and TImode */
1037 };
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1040 static const
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1072 in SFmode, DFmode and XFmode */
1074 in SFmode, DFmode and XFmode */
1077 in SImode and DImode */
1079 in SImode and DImode */
1082 in SImode, DImode and TImode */
1084 in SImode, DImode and TImode */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1114 };
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1117 static const
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1145 in SFmode, DFmode and XFmode */
1147 in SFmode, DFmode and XFmode */
1150 in SImode and DImode */
1152 in SImode and DImode */
1155 in SImode, DImode and TImode */
1157 in SImode, DImode and TImode */
1171 DUMMY_STRINGOP_ALGS},
1173 DUMMY_STRINGOP_ALGS},
1185 };
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1226 /* X86_TUNE_PUSH_MEMORY */
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1265 m_PPRO,
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1276 /* X86_TUNE_USE_MOV0 */
1277 m_K6,
1279 /* X86_TUNE_USE_CLTD */
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1283 m_PENT4,
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1286 m_PPRO,
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1298 /* X86_TUNE_FAST_PREFIX */
1301 /* X86_TUNE_SINGLE_STRINGOP */
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1317 m_PPRO,
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1322 /* X86_TUNE_ADD_ESP_8 */
1326 /* X86_TUNE_SUB_ESP_4 */
1329 /* X86_TUNE_SUB_ESP_8 */
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1353 m_AMDFAM10,
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1359 m_ATHLON_K8,
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1362 m_AMD_MULTIPLE,
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1380 m_AMD_MULTIPLE,
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1392 /* X86_TUNE_SCHEDULE */
1395 /* X86_TUNE_USE_BT */
1398 /* X86_TUNE_USE_INCDEC */
1401 /* X86_TUNE_PAD_RETURNS */
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1422 machines. */
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1426 than a MOV. */
1427 m_PENT,
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1431 m_PENT,
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1436 m_K6,
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1439 from FP to FP. */
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1444 m_AMDFAM10,
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1449 m_CORE2,
1450 };
1452 /* Feature tests against the various architecture variations. */
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1472 };
1474 static const unsigned int x86_accumulate_outgoing_args
1477 static const unsigned int x86_arch_always_fancy_math_387
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1485 epilogue code. */
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1497 {
1498 /* ax, dx, cx, bx */
1500 /* si, di, bp, sp */
1502 /* FP registers */
1505 /* arg pointer */
1506 NON_Q_REGS,
1507 /* flags, fpsr, fpcr, frame */
1509 /* SSE registers */
1512 /* MMX registers */
1515 /* REX registers */
1518 /* SSE REX registers */
1521 };
1523 /* The "default" register map used in 32bit mode. */
1526 {
1534 };
1537 {
1540 };
1543 {
1546 };
1549 {
1551 };
1553 /* The "default" register map used in 64bit mode. */
1555 {
1563 };
1565 /* Define the register numbers to be used in Dwarf debugging information.
1566 The SVR4 reference port C compiler uses the following register numbers
1567 in its Dwarf output code:
1568 0 for %eax (gcc regno = 0)
1569 1 for %ecx (gcc regno = 2)
1570 2 for %edx (gcc regno = 1)
1571 3 for %ebx (gcc regno = 3)
1572 4 for %esp (gcc regno = 7)
1573 5 for %ebp (gcc regno = 6)
1574 6 for %esi (gcc regno = 4)
1575 7 for %edi (gcc regno = 5)
1576 The following three DWARF register numbers are never generated by
1577 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1578 believes these numbers have these meanings.
1579 8 for %eip (no gcc equivalent)
1580 9 for %eflags (gcc regno = 17)
1581 10 for %trapno (no gcc equivalent)
1582 It is not at all clear how we should number the FP stack registers
1583 for the x86 architecture. If the version of SDB on x86/svr4 were
1584 a bit less brain dead with respect to floating-point then we would
1585 have a precedent to follow with respect to DWARF register numbers
1586 for x86 FP registers, but the SDB on x86/svr4 is so completely
1587 broken with respect to FP registers that it is hardly worth thinking
1588 of it as something to strive for compatibility with.
1589 The version of x86/svr4 SDB I have at the moment does (partially)
1590 seem to believe that DWARF register number 11 is associated with
1591 the x86 register %st(0), but that's about all. Higher DWARF
1592 register numbers don't seem to be associated with anything in
1593 particular, and even for DWARF regno 11, SDB only seems to under-
1594 stand that it should say that a variable lives in %st(0) (when
1595 asked via an `=' command) if we said it was in DWARF regno 11,
1596 but SDB still prints garbage when asked for the value of the
1597 variable in question (via a `/' command).
1598 (Also note that the labels SDB prints for various FP stack regs
1599 when doing an `x' command are all wrong.)
1600 Note that these problems generally don't affect the native SVR4
1601 C compiler because it doesn't allow the use of -O with -g and
1602 because when it is *not* optimizing, it allocates a memory
1603 location for each floating-point variable, and the memory
1604 location is what gets described in the DWARF AT_location
1605 attribute for the variable in question.
1606 Regardless of the severe mental illness of the x86/svr4 SDB, we
1607 do something sensible here and we use the following DWARF
1608 register numbers. Note that these are all stack-top-relative
1609 numbers.
1610 11 for %st(0) (gcc regno = 8)
1611 12 for %st(1) (gcc regno = 9)
1612 13 for %st(2) (gcc regno = 10)
1613 14 for %st(3) (gcc regno = 11)
1614 15 for %st(4) (gcc regno = 12)
1615 16 for %st(5) (gcc regno = 13)
1616 17 for %st(6) (gcc regno = 14)
1617 18 for %st(7) (gcc regno = 15)
1618 */
1620 {
1628 };
1630 /* Test and compare insns in i386.md store the information needed to
1631 generate branch and scc insns here. */
1637 /* Define the structure for the machine field in struct function. */
1640 {
1643 rtx rtl;
1645 };
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1650 [arguments]
1651 <- ARG_POINTER
1652 saved pc
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1656 [saved regs]
1658 [padding1] \
1659 )
1660 [va_arg registers] (
1661 > to_allocate <- FRAME_POINTER
1662 [frame] (
1663 )
1664 [padding2] /
1665 */
1666 struct ix86_frame
1667 {
1671 HOST_WIDE_INT frame;
1676 HOST_WIDE_INT to_allocate;
1677 /* The offsets relative to ARG_POINTER. */
1678 HOST_WIDE_INT frame_pointer_offset;
1679 HOST_WIDE_INT hard_frame_pointer_offset;
1680 HOST_WIDE_INT stack_pointer_offset;
1682 /* When save_regs_using_mov is set, emit prologue using
1683 move instead of push instructions. */
1685 };
1687 /* Code model option. */
1689 /* Asm dialect. */
1691 /* TLS dialects. */
1694 /* Which unit we are generating floating point math for. */
1697 /* Which cpu are we scheduling for. */
1700 /* Which cpu are we optimizing for. */
1703 /* Which instruction set architecture to use. */
1706 /* true if sse prefetch instruction is not NOOP. */
1709 /* ix86_regparm_string as a number */
1712 /* -mstackrealign option */
1726 /* Preferred alignment for stack boundary in bits. */
1729 /* Alignment for incoming stack boundary in bits specified at
1730 command line. */
1733 /* Default alignment for incoming stack boundary in bits. */
1736 /* Alignment for incoming stack boundary in bits. */
1739 /* Values 1-5: see jump.c */
1742 /* Calling abi specific va_list type nodes. */
1746 /* Variables which are this size or smaller are put in the data/bss
1747 or ldata/lbss sections. */
1751 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1755 /* Fence to use after loop using movnt. */
1756 tree x86_mfence;
1758 /* Register class used for passing given 64bit part of the argument.
1759 These represent classes as documented by the PS ABI, with the exception
1760 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1761 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1763 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1764 whenever possible (upper half does contain padding). */
1765 enum x86_64_reg_class
1766 {
1767 X86_64_NO_CLASS,
1768 X86_64_INTEGER_CLASS,
1769 X86_64_INTEGERSI_CLASS,
1770 X86_64_AVX_CLASS,
1771 X86_64_SSE_CLASS,
1772 X86_64_SSESF_CLASS,
1773 X86_64_SSEDF_CLASS,
1774 X86_64_SSEUP_CLASS,
1775 X86_64_X87_CLASS,
1776 X86_64_X87UP_CLASS,
1777 X86_64_COMPLEX_X87_CLASS,
1778 X86_64_MEMORY_CLASS
1779 };
1781 {
1784 };
1786 #define MAX_CLASSES 4
1788 /* Table of constants used by fldpi, fldln2, etc.... */
1792 \f
1801 enum ix86_function_specific_strings
1802 {
1803 IX86_FUNCTION_SPECIFIC_ARCH,
1804 IX86_FUNCTION_SPECIFIC_TUNE,
1805 IX86_FUNCTION_SPECIFIC_FPMATH,
1806 IX86_FUNCTION_SPECIFIC_MAX
1807 };
1821 \f
1822 /* The svr4 ABI for the i386 says that records and unions are returned
1823 in memory. */
1824 #ifndef DEFAULT_PCC_STRUCT_RETURN
1825 #define DEFAULT_PCC_STRUCT_RETURN 1
1826 #endif
1828 /* Whether -mtune= or -march= were specified */
1832 /* Bit flags that specify the ISA we are compiling for. */
1835 /* A mask of ix86_isa_flags that includes bit X if X
1836 was set or cleared on the command line. */
1839 /* Define a set of ISAs which are available when a given ISA is
1840 enabled. MMX and SSE ISAs are handled separately. */
1842 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1843 #define OPTION_MASK_ISA_3DNOW_SET \
1844 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1846 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1847 #define OPTION_MASK_ISA_SSE2_SET \
1848 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1849 #define OPTION_MASK_ISA_SSE3_SET \
1850 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1851 #define OPTION_MASK_ISA_SSSE3_SET \
1852 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1853 #define OPTION_MASK_ISA_SSE4_1_SET \
1854 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1855 #define OPTION_MASK_ISA_SSE4_2_SET \
1856 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1857 #define OPTION_MASK_ISA_AVX_SET \
1858 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1859 #define OPTION_MASK_ISA_FMA_SET \
1860 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1862 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1863 as -msse4.2. */
1864 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1866 #define OPTION_MASK_ISA_SSE4A_SET \
1867 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1868 #define OPTION_MASK_ISA_SSE5_SET \
1869 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1871 /* AES and PCLMUL need SSE2 because they use xmm registers */
1872 #define OPTION_MASK_ISA_AES_SET \
1873 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1874 #define OPTION_MASK_ISA_PCLMUL_SET \
1875 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1877 #define OPTION_MASK_ISA_ABM_SET \
1878 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1879 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1880 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1881 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1883 /* Define a set of ISAs which aren't available when a given ISA is
1884 disabled. MMX and SSE ISAs are handled separately. */
1886 #define OPTION_MASK_ISA_MMX_UNSET \
1887 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1888 #define OPTION_MASK_ISA_3DNOW_UNSET \
1889 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1890 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1892 #define OPTION_MASK_ISA_SSE_UNSET \
1893 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1894 #define OPTION_MASK_ISA_SSE2_UNSET \
1895 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1896 #define OPTION_MASK_ISA_SSE3_UNSET \
1897 (OPTION_MASK_ISA_SSE3 \
1898 | OPTION_MASK_ISA_SSSE3_UNSET \
1899 | OPTION_MASK_ISA_SSE4A_UNSET )
1900 #define OPTION_MASK_ISA_SSSE3_UNSET \
1901 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1902 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1903 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1904 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1905 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1906 #define OPTION_MASK_ISA_AVX_UNSET \
1907 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1908 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1910 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1911 as -mno-sse4.1. */
1912 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1914 #define OPTION_MASK_ISA_SSE4A_UNSET \
1915 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1916 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1917 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1918 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1919 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1920 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1921 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1922 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1924 /* Vectorization library interface and handlers. */
1929 /* Processor target table, indexed by processor number */
1930 struct ptt
1931 {
1938 };
1941 {
1956 };
1959 {
1980 "amdfam10"
1981 };
1982 \f
1983 /* Implement TARGET_HANDLE_OPTION. */
1985 static bool
1987 {
1989 {
1992 {
1995 }
1996 else
1997 {
2000 }
2005 {
2008 }
2009 else
2010 {
2013 }
2021 {
2024 }
2025 else
2026 {
2029 }
2034 {
2037 }
2038 else
2039 {
2042 }
2047 {
2050 }
2051 else
2052 {
2055 }
2060 {
2063 }
2064 else
2065 {
2068 }
2073 {
2076 }
2077 else
2078 {
2081 }
2086 {
2089 }
2090 else
2091 {
2094 }
2099 {
2102 }
2103 else
2104 {
2107 }
2112 {
2115 }
2116 else
2117 {
2120 }
2135 {
2138 }
2139 else
2140 {
2143 }
2148 {
2151 }
2152 else
2153 {
2156 }
2161 {
2164 }
2165 else
2166 {
2169 }
2174 {
2177 }
2178 else
2179 {
2182 }
2187 {
2190 }
2191 else
2192 {
2195 }
2200 {
2203 }
2204 else
2205 {
2208 }
2213 {
2216 }
2217 else
2218 {
2221 }
2226 {
2229 }
2230 else
2231 {
2234 }
2239 }
2240 }
2241 \f
2242 /* Return a string the documents the current -m options. The caller is
2243 responsible for freeing the string. */
2248 {
2249 struct ix86_target_opts
2250 {
2253 };
2255 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2256 preceding options while match those first. */
2258 {
2275 };
2277 /* Flag options. */
2279 {
2301 };
2319 /* Add -march= option. */
2321 {
2324 }
2326 /* Add -mtune= option. */
2328 {
2331 }
2333 /* Pick out the options in isa options. */
2335 {
2337 {
2340 }
2341 }
2344 {
2347 }
2349 /* Add flag options. */
2351 {
2353 {
2356 }
2357 }
2360 {
2363 }
2365 /* Add -fpmath= option. */
2367 {
2370 }
2372 /* Any options? */
2378 /* Size the string. */
2382 {
2387 }
2389 /* Build the string. */
2394 {
2401 {
2403 line_len++;
2406 {
2410 }
2411 }
2415 {
2419 }
2420 }
2426 }
2428 /* Function that is callable from the debugger to print the current
2429 options. */
2430 void
2432 {
2438 {
2441 }
2442 else
2446 }
2447 \f
2448 /* Sometimes certain combinations of command options do not make
2449 sense on a particular target machine. You can define a macro
2450 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2451 defined, is executed once just after all the command options have
2452 been parsed.
2454 Don't use this macro to turn on various extra optimizations for
2455 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 void
2459 {
2466 /* Comes from final.c -- no real reason to change it. */
2467 #define MAX_CODE_ALIGN 16
2469 enum pta_flags
2470 {
2492 };
2494 static struct pta
2495 {
2500 }
2502 {
2581 };
2585 /* Set up prefix/suffix so the error messages refer to either the command
2586 line argument, or the attribute(target). */
2588 {
2592 }
2593 else
2594 {
2598 }
2600 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2601 SUBTARGET_OVERRIDE_OPTIONS;
2602 #endif
2604 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2605 SUBSUBTARGET_OVERRIDE_OPTIONS;
2606 #endif
2608 /* -fPIC is the default for x86_64. */
2612 /* Set the default values for switches whose default depends on TARGET_64BIT
2613 in case they weren't overwritten by command line options. */
2615 {
2616 /* Mach-O doesn't support omitting the frame pointer for now. */
2623 }
2624 else
2625 {
2632 }
2634 /* Need to check -mtune=generic first. */
2636 {
2639 /* As special support for cross compilers we read -mtune=native
2640 as -mtune=generic. With native compilers we won't see the
2641 -mtune=native, as it was changed by the driver. */
2643 {
2646 else
2648 }
2649 /* If this call is for setting the option attribute, allow the
2650 generic32/generic64 that was previously set. */
2654 ;
2658 }
2659 else
2660 {
2664 {
2667 }
2669 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2670 need to use a sensible tune option. */
2674 {
2677 else
2679 }
2680 }
2682 {
2697 else
2700 }
2708 else
2719 {
2732 else
2735 }
2736 else
2737 {
2738 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2739 use of rip-relative addressing. This eliminates fixups that
2740 would otherwise be needed if this object is to be placed in a
2741 DLL, and is essentially just as efficient as direct addressing. */
2746 else
2748 }
2750 {
2756 else
2759 }
2769 {
2772 /* Default cpu tuning to the architecture. */
2840 }
2852 {
2856 {
2858 {
2866 }
2867 else
2870 }
2871 /* Intel CPUs have always interpreted SSE prefetch instructions as
2872 NOPs; so, we can enable SSE prefetch instructions even when
2873 -mtune (rather than -march) points us to a processor that has them.
2874 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2875 higher processors. */
2880 }
2891 else
2894 /* Arrange to set up i386_stack_locals for all functions. */
2897 /* Validate -mregparm= value. */
2899 {
2906 else
2908 }
2912 /* If the user has provided any of the -malign-* options,
2913 warn and use that value only if -falign-* is not set.
2914 Remove this code in GCC 3.2 or later. */
2916 {
2920 {
2925 else
2927 }
2928 }
2931 {
2935 {
2940 else
2942 }
2943 }
2946 {
2950 {
2955 else
2957 }
2958 }
2960 /* Default align_* from the processor table. */
2962 {
2965 }
2967 {
2970 }
2972 {
2974 }
2976 /* Validate -mbranch-cost= value, or provide default. */
2979 {
2983 else
2985 }
2987 {
2991 else
2993 }
2996 {
3003 else
3006 }
3009 {
3013 }
3016 {
3019 /* Enable by default the SSE and MMX builtins. Do allow the user to
3020 explicitly disable any of these. In particular, disabling SSE and
3021 MMX for kernel code is extremely useful. */
3023 ix86_isa_flags
3029 }
3030 else
3031 {
3035 ix86_isa_flags
3038 /* i386 ABI does not specify red zone. It still makes sense to use it
3039 when programmer takes care to stack from being destroyed. */
3042 }
3044 /* Keep nonleaf frame pointers. */
3050 /* If we're doing fast math, we don't care about comparison order
3051 wrt NaNs. This lets us use a shorter comparison sequence. */
3055 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3056 since the insns won't need emulation. */
3060 /* Likewise, if the target doesn't have a 387, or we've specified
3061 software floating point, don't use 387 inline intrinsics. */
3065 /* Turn on MMX builtins for -msse. */
3067 {
3070 }
3072 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3076 /* Validate -mpreferred-stack-boundary= value or default it to
3077 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3080 {
3085 else
3087 }
3089 /* Set the default value for -mstackrealign. */
3093 /* Validate -mincoming-stack-boundary= value or default it to
3094 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3097 else
3101 {
3106 else
3107 {
3109 ix86_incoming_stack_boundary
3111 }
3112 }
3114 /* Accept -msseregparm only if at least SSE support is enabled. */
3121 {
3125 {
3127 {
3130 }
3131 else
3133 }
3139 {
3141 {
3144 }
3146 {
3149 }
3150 else
3152 }
3153 else
3156 }
3158 /* If the i387 is disabled, then do not return values in it. */
3162 /* Use external vectorized library in vectorizing intrinsics. */
3164 {
3169 else
3173 }
3180 /* ??? Unwind info is not correct around the CFG unless either a frame
3181 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3182 unwind info generation to be aware of the CFG and propagating states
3183 around edges. */
3186 && flag_omit_frame_pointer
3188 {
3194 }
3196 /* If stack probes are required, the space used for large function
3197 arguments on the stack must also be probed, so enable
3198 -maccumulate-outgoing-args so this happens in the prologue. */
3201 {
3206 }
3208 /* For sane SSE instruction set generation we need fcomi instruction.
3209 It is safe to enable all CMOVE instructions. */
3213 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3214 {
3220 }
3222 /* When scheduling description is not available, disable scheduler pass
3223 so it won't slow down the compilation and make x87 code slower. */
3237 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3238 can be optimized to ap = __builtin_next_arg (0). */
3243 {
3252 }
3253 else
3254 {
3263 }
3265 #ifdef USE_IX86_CLD
3266 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 #endif
3271 /* Save the initial options in case the user does function specific options */
3273 target_option_default_node = target_option_current_node
3275 }
3276 \f
3277 /* Save the current options */
3279 static void
3281 {
3297 }
3299 /* Restore the current options */
3301 static void
3303 {
3319 /* Recreate the arch feature tests if the arch changed */
3321 {
3326 }
3328 /* Recreate the tune optimization tests */
3330 {
3335 }
3336 }
3338 /* Print the current options */
3340 static void
3343 {
3368 {
3371 }
3372 }
3374 \f
3375 /* Inner function to process the attribute((target(...))), take an argument and
3376 set the current options from the argument. If we have a list, recursively go
3377 over the list. */
3379 static bool
3381 {
3385 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3386 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3387 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3388 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3390 enum ix86_opt_type
3391 {
3392 ix86_opt_unknown,
3393 ix86_opt_yes,
3394 ix86_opt_no,
3395 ix86_opt_str,
3396 ix86_opt_isa
3397 };
3399 static const struct
3400 {
3407 /* isa options */
3424 /* string options */
3429 /* flag options */
3431 OPT_mcld,
3432 MASK_CLD),
3435 OPT_mfancy_math_387,
3436 MASK_NO_FANCY_MATH_387),
3439 OPT_mfused_madd,
3440 MASK_NO_FUSED_MADD),
3443 OPT_mieee_fp,
3444 MASK_IEEE_FP),
3447 OPT_minline_all_stringops,
3448 MASK_INLINE_ALL_STRINGOPS),
3451 OPT_minline_stringops_dynamically,
3452 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3455 OPT_mno_align_stringops,
3456 MASK_NO_ALIGN_STRINGOPS),
3459 OPT_mrecip,
3460 MASK_RECIP),
3462 };
3464 /* If this is a list, recurse to get the options. */
3466 {
3475 }
3480 /* Handle multiple arguments separated by commas. */
3484 {
3498 {
3502 }
3503 else
3504 {
3507 }
3509 /* Recognize no-xxx. */
3511 {
3515 }
3516 else
3519 /* Find the option. */
3523 {
3529 {
3534 }
3535 }
3537 /* Process the option. */
3539 {
3542 }
3548 {
3554 else
3556 }
3559 {
3561 {
3564 }
3565 else
3567 }
3569 else
3571 }
3574 }
3576 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3578 tree
3580 {
3592 /* Process each of the options on the chain. */
3596 /* If the changed options are different from the default, rerun override_options,
3597 and then save the options away. The string options are are attribute options,
3598 and will be undone when we copy the save structure. */
3604 {
3605 /* If we are using the default tune= or arch=, undo the string assigned,
3606 and use the default. */
3617 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3623 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3626 /* Add any builtin functions with the new isa if any. */
3629 /* Save the current options unless we are validating options for
3630 #pragma. */
3637 /* Free up memory allocated to hold the strings */
3641 }
3644 }
3646 /* Hook to validate attribute((target("string"))). */
3648 static bool
3651 tree args,
3653 {
3660 /* If the function changed the optimization levels as well as setting target
3661 options, start with the optimizations specified. */
3665 /* The target attributes may also change some optimization flags, so update
3666 the optimization options if necessary. */
3675 {
3680 }
3688 }
3690 \f
3691 /* Hook to determine if one function can safely inline another. */
3693 static bool
3695 {
3700 /* If callee has no option attributes, then it is ok to inline. */
3704 /* If caller has no option attributes, but callee does then it is not ok to
3705 inline. */
3709 else
3710 {
3714 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3715 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3716 function. */
3721 /* See if we have the same non-isa options. */
3725 /* See if arch, tune, etc. are the same. */
3738 else
3740 }
3743 }
3745 \f
3746 /* Remember the last target of ix86_set_current_function. */
3749 /* Establish appropriate back-end context for processing the function
3750 FNDECL. The argument might be NULL to indicate processing at top
3751 level, outside of any function scope. */
3752 static void
3754 {
3755 /* Only change the context if the function changes. This hook is called
3756 several times in the course of compiling a function, and we don't want to
3757 slow things down too much or call target_reinit when it isn't safe. */
3759 {
3760 tree old_tree = (ix86_previous_fndecl
3764 tree new_tree = (fndecl
3770 ;
3773 {
3776 }
3779 {
3785 }
3786 }
3787 }
3789 \f
3790 /* Return true if this goes in large data/bss. */
3792 static bool
3794 {
3798 /* Functions are never large data. */
3803 {
3809 }
3810 else
3811 {
3814 /* If this is an incomplete type with size 0, then we can't put it
3815 in data because it might be too big when completed. */
3818 }
3821 }
3823 /* Switch to the appropriate section for output of DECL.
3824 DECL is either a `VAR_DECL' node or a constant of some sort.
3825 RELOC indicates whether forming the initial value of DECL requires
3826 link-time relocations. */
3829 ATTRIBUTE_UNUSED;
3834 {
3837 {
3841 {
3875 /* We don't split these for medium model. Place them into
3876 default sections and hope for best. */
3881 }
3883 {
3884 /* We might get called with string constants, but get_named_section
3885 doesn't like them as they are not DECLs. Also, we need to set
3886 flags in that case. */
3890 }
3891 }
3893 }
3895 /* Build up a unique section name, expressed as a
3896 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3897 RELOC indicates whether the initial value of EXP requires
3898 link-time relocations. */
3900 static void ATTRIBUTE_UNUSED
3902 {
3905 {
3907 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3911 {
3935 /* We don't split these for medium model. Place them into
3936 default sections and hope for best. */
3944 }
3946 {
3953 /* If we're using one_only, then there needs to be a .gnu.linkonce
3954 prefix to the section name. */
3961 }
3962 }
3964 }
3966 #ifdef COMMON_ASM_OP
3967 /* This says how to output assembler code to declare an
3968 uninitialized external linkage data object.
3970 For medium model x86-64 we need to use .largecomm opcode for
3971 large objects. */
3972 void
3976 {
3980 else
3985 }
3986 #endif
3988 /* Utility function for targets to use in implementing
3989 ASM_OUTPUT_ALIGNED_BSS. */
3991 void
3995 {
3999 else
4002 #ifdef ASM_DECLARE_OBJECT_NAME
4005 #else
4006 /* Standard thing is just output label for the object. */
4010 }
4011 \f
4012 void
4014 {
4015 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4016 make the problem with not enough registers even worse. */
4017 #ifdef INSN_SCHEDULING
4020 #endif
4023 /* The Darwin libraries never set errno, so we might as well
4024 avoid calling them when that's the only reason we would. */
4027 /* The default values of these switches depend on the TARGET_64BIT
4028 that is not known at this moment. Mark these values with 2 and
4029 let user the to override these. In case there is no command line option
4030 specifying them, we will set the defaults in override_options. */
4036 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4037 SUBTARGET_OPTIMIZATION_OPTIONS;
4038 #endif
4039 }
4040 \f
4041 /* Decide whether we can make a sibling call to a function. DECL is the
4042 declaration of the function being targeted by the call and EXP is the
4043 CALL_EXPR representing the call. */
4045 static bool
4047 {
4048 tree func;
4051 /* If we are generating position-independent code, we cannot sibcall
4052 optimize any indirect call, or a direct call to a global function,
4053 as the PLT requires %ebx be live. */
4059 else
4060 {
4064 }
4066 /* Check that the return value locations are the same. Like
4067 if we are returning floats on the 80387 register stack, we cannot
4068 make a sibcall from a function that doesn't return a float to a
4069 function that does or, conversely, from a function that does return
4070 a float to a function that doesn't; the necessary stack adjustment
4071 would not be executed. This is also the place we notice
4072 differences in the return value ABI. Note that it is ok for one
4073 of the functions to have void return type as long as the return
4074 value of the other is passed in a register. */
4079 {
4082 }
4084 ;
4088 /* If this call is indirect, we'll need to be able to use a call-clobbered
4089 register for the address of the target function. Make sure that all
4090 such registers are not used for passing parameters. */
4092 {
4093 tree type;
4095 /* We're looking at the CALL_EXPR, we need the type of the function. */
4101 {
4102 /* ??? Need to count the actual number of registers to be used,
4103 not the possible number of registers. Fix later. */
4105 }
4106 }
4108 /* Dllimport'd functions are also called indirectly. */
4110 && !TARGET_64BIT
4115 /* Otherwise okay. That also includes certain types of indirect calls. */
4117 }
4119 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4120 calling convention attributes;
4121 arguments as in struct attribute_spec.handler. */
4123 static tree
4125 tree args,
4128 {
4133 {
4138 }
4140 /* Can combine regparm with all attributes but fastcall. */
4142 {
4143 tree cst;
4146 {
4148 }
4152 {
4157 }
4159 {
4163 }
4166 }
4169 {
4170 /* Do not warn when emulating the MS ABI. */
4176 }
4178 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4180 {
4182 {
4184 }
4186 {
4188 }
4190 {
4192 }
4193 }
4195 /* Can combine stdcall with fastcall (redundant), regparm and
4196 sseregparm. */
4198 {
4200 {
4202 }
4204 {
4206 }
4207 }
4209 /* Can combine cdecl with regparm and sseregparm. */
4211 {
4213 {
4215 }
4217 {
4219 }
4220 }
4222 /* Can combine sseregparm with all attributes. */
4225 }
4227 /* Return 0 if the attributes for two types are incompatible, 1 if they
4228 are compatible, and 2 if they are nearly compatible (which causes a
4229 warning to be generated). */
4231 static int
4233 {
4234 /* Check for mismatch of non-default calling convention. */
4241 /* Check for mismatched fastcall/regparm types. */
4248 /* Check for mismatched sseregparm types. */
4253 /* Check for mismatched return types (cdecl vs stdcall). */
4259 }
4260 \f
4261 /* Return the regparm value for a function with the indicated TYPE and DECL.
4262 DECL may be NULL when calling function indirectly
4263 or considering a libcall. */
4265 static int
4267 {
4268 tree attr;
4274 {
4278 }
4282 {
4283 regparm
4287 {
4288 /* We can't use regparm(3) for nested functions because
4289 these pass static chain pointer in %ecx register. */
4293 {
4297 }
4298 }
4301 }
4306 /* Use register calling convention for local functions when possible. */
4309 {
4310 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4313 {
4317 /* Make sure no regparm register is taken by a
4318 fixed register variable. */
4323 /* We can't use regparm(3) for nested functions as these use
4324 static chain pointer in third argument. */
4330 /* If the function realigns its stackpointer, the prologue will
4331 clobber %ecx. If we've already generated code for the callee,
4332 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4333 scanning the attributes for the self-realigning property. */
4335 /* Since current internal arg pointer won't conflict with
4336 parameter passing regs, so no need to change stack
4337 realignment and adjust regparm number.
4339 Each fixed register usage increases register pressure,
4340 so less registers should be used for argument passing.
4341 This functionality can be overriden by an explicit
4342 regparm value. */
4345 globals++;
4347 local_regparm
4352 }
4353 }
4356 }
4358 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4359 DFmode (2) arguments in SSE registers for a function with the
4360 indicated TYPE and DECL. DECL may be NULL when calling function
4361 indirectly or considering a libcall. Otherwise return 0. */
4363 static int
4365 {
4368 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4369 by the sseregparm attribute. */
4372 {
4374 {
4376 {
4380 else
4383 }
4385 }
4388 }
4390 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4391 (and DFmode for SSE2) arguments in SSE registers. */
4393 {
4394 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4398 }
4401 }
4403 /* Return true if EAX is live at the start of the function. Used by
4404 ix86_expand_prologue to determine if we need special help before
4405 calling allocate_stack_worker. */
4407 static bool
4409 {
4410 /* Cheat. Don't bother working forward from ix86_function_regparm
4411 to the function type to whether an actual argument is located in
4412 eax. Instead just look at cfg info, which is still close enough
4413 to correct at this point. This gives false positives for broken
4414 functions that might use uninitialized data that happens to be
4415 allocated in eax, but who cares? */
4417 }
4419 /* Value is the number of bytes of arguments automatically
4420 popped when returning from a subroutine call.
4421 FUNDECL is the declaration node of the function (as a tree),
4422 FUNTYPE is the data type of the function (as a tree),
4423 or for a library call it is an identifier node for the subroutine name.
4424 SIZE is the number of bytes of arguments passed on the stack.
4426 On the 80386, the RTD insn may be used to pop them if the number
4427 of args is fixed, but if the number is variable then the caller
4428 must pop them all. RTD can't be used for library calls now
4429 because the library is compiled with the Unix compiler.
4430 Use of RTD is a selectable option, since it is incompatible with
4431 standard Unix calling sequences. If the option is not selected,
4432 the caller must always pop the args.
4434 The attribute stdcall is equivalent to RTD on a per module basis. */
4436 int
4438 {
4441 /* None of the 64-bit ABIs pop arguments. */
4447 /* Cdecl functions override -mrtd, and never pop the stack. */
4449 {
4450 /* Stdcall and fastcall functions will pop the stack if not
4451 variable args. */
4458 }
4460 /* Lose any fake structure return argument if it is passed on the stack. */
4463 {
4467 }
4470 }
4471 \f
4472 /* Argument support functions. */
4474 /* Return true when register may be used to pass function parameters. */
4475 bool
4477 {
4482 {
4486 else
4492 }
4495 {
4498 }
4499 else
4500 {
4504 }
4506 /* TODO: The function should depend on current function ABI but
4507 builtins.c would need updating then. Therefore we use the
4508 default ABI. */
4510 /* RAX is used as hidden argument to va_arg functions. */
4516 else
4523 }
4525 /* Return if we do not know how to pass TYPE solely in registers. */
4527 static bool
4529 {
4533 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4534 The layout_type routine is crafty and tries to trick us into passing
4535 currently unsupported vector types on the stack by using TImode. */
4538 }
4540 /* It returns the size, in bytes, of the area reserved for arguments passed
4541 in registers for the function represented by fndecl dependent to the used
4542 abi format. */
4543 int
4545 {
4547 /* For libcalls it is possible that there is no fndecl at hand.
4548 Therefore assume for this case the default abi of the target. */
4551 else
4556 }
4558 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4559 call abi used. */
4560 int
4562 {
4564 {
4568 else
4572 }
4574 }
4576 int
4578 {
4582 }
4584 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4585 call abi used. */
4586 int
4588 {
4592 }
4594 /* regclass.c */
4597 /* Implementation of call abi switching target hook. Specific to FNDECL
4598 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4599 for more details.
4600 To prevent redudant calls of costy function init_regs (), it checks not to
4601 reset register usage for default abi. */
4602 void
4604 {
4607 else
4610 {
4612 {
4616 }
4617 }
4619 {
4621 {
4625 }
4626 }
4627 }
4629 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4630 for a call to a function whose data type is FNTYPE.
4631 For a library call, FNTYPE is 0. */
4633 void
4637 tree fndecl)
4638 {
4643 /* Set up the number of registers to use for passing arguments. */
4646 {
4650 }
4652 {
4655 {
4659 }
4660 }
4667 /* Because type might mismatch in between caller and callee, we need to
4668 use actual type of function for local calls.
4669 FIXME: cgraph_analyze can be told to actually record if function uses
4670 va_start so for local functions maybe_vaarg can be made aggressive
4671 helping K&R code.
4672 FIXME: once typesytem is fixed, we won't need this code anymore. */
4680 {
4681 /* If there are variable arguments, then we won't pass anything
4682 in registers in 32-bit mode. */
4684 {
4692 }
4694 /* Use ecx and edx registers if function has fastcall attribute,
4695 else look for regparm information. */
4697 {
4699 {
4702 }
4703 else
4705 }
4707 /* Set up the number of SSE registers used for passing SFmode
4708 and DFmode arguments. Warn for mismatching ABI. */
4710 }
4711 }
4713 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4714 But in the case of vector types, it is some vector mode.
4716 When we have only some of our vector isa extensions enabled, then there
4717 are some modes for which vector_mode_supported_p is false. For these
4718 modes, the generic vector support in gcc will choose some non-vector mode
4719 in order to implement the type. By computing the natural mode, we'll
4720 select the proper ABI location for the operand and not depend on whatever
4721 the middle-end decides to do with these vector types. */
4723 static enum machine_mode
4725 {
4729 {
4732 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4734 {
4739 else
4742 /* Get the mode which has this inner mode and number of units. */
4749 }
4750 }
4753 }
4755 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4756 this may not agree with the mode that the type system has chosen for the
4757 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4758 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4760 static rtx
4763 {
4764 rtx tmp;
4768 else
4769 {
4773 }
4776 }
4778 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4779 of this code is to classify each 8bytes of incoming argument by the register
4780 class and assign registers accordingly. */
4782 /* Return the union class of CLASS1 and CLASS2.
4783 See the x86-64 PS ABI for details. */
4785 static enum x86_64_reg_class
4787 {
4788 /* Rule #1: If both classes are equal, this is the resulting class. */
4792 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4793 the other class. */
4799 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4803 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4811 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4812 MEMORY is used. */
4821 /* Rule #6: Otherwise class SSE is used. */
4823 }
4825 /* Classify the argument of type TYPE and mode MODE.
4826 CLASSES will be filled by the register class used to pass each word
4827 of the operand. The number of words is returned. In case the parameter
4828 should be passed in memory, 0 is returned. As a special case for zero
4829 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4831 BIT_OFFSET is used internally for handling records and specifies offset
4832 of the offset in bits modulo 256 to avoid overflow cases.
4834 See the x86-64 PS ABI for details.
4835 */
4837 static int
4840 {
4841 HOST_WIDE_INT bytes =
4845 /* Variable sized entities are always passed/returned in memory. */
4854 {
4856 tree field;
4859 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4866 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4867 signalize memory class, so handle it as special case. */
4869 {
4872 }
4874 /* Classify each field of record and merge classes. */
4876 {
4878 /* And now merge the fields of structure. */
4880 {
4882 {
4888 /* Bitfields are always classified as integer. Handle them
4889 early, since later code would consider them to be
4890 misaligned integers. */
4892 {
4900 }
4901 else
4902 {
4910 {
4915 }
4916 }
4917 }
4918 }
4922 /* Arrays are handled as small records. */
4923 {
4930 /* The partial classes are now full classes. */
4941 }
4944 /* Unions are similar to RECORD_TYPE but offset is always 0.
4945 */
4947 {
4949 {
4957 bit_offset);
4962 }
4963 }
4968 }
4970 /* Final merger cleanup. */
4972 {
4973 /* If one class is MEMORY, everything should be passed in
4974 memory. */
4978 /* The X86_64_SSEUP_CLASS should be always preceded by
4979 X86_64_SSE_CLASS. */
4984 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4988 }
4990 }
4992 /* Compute alignment needed. We align all types to natural boundaries with
4993 exception of XFmode that is aligned to 64bits. */
4995 {
5004 /* Misaligned fields are always returned in memory. */
5007 }
5009 /* for V1xx modes, just use the base mode */
5014 /* Classification of atomic types. */
5016 {
5034 else
5048 else
5073 /* This modes is larger than 16 bytes. */
5112 else
5116 }
5117 }
5119 /* Examine the argument and return set number of register required in each
5120 class. Return 0 iff parameter should be passed in memory. */
5121 static int
5124 {
5134 {
5157 }
5159 }
5161 /* Construct container for the argument used by GCC interface. See
5162 FUNCTION_ARG for the detailed description. */
5164 static rtx
5168 {
5169 /* The following variables hold the static issued_error state. */
5183 rtx ret;
5194 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5195 some less clueful developer tries to use floating-point anyway. */
5197 {
5199 {
5201 {
5204 }
5205 }
5207 {
5210 }
5212 }
5214 /* Likewise, error if the ABI requires us to return values in the
5215 x87 registers and the user specified -mno-80387. */
5221 {
5223 {
5226 }
5228 }
5230 /* First construct simple cases. Avoid SCmode, since we want to use
5231 single register to pass this type. */
5234 {
5247 /* Zero sized array, struct or class. */
5251 }
5265 /* Otherwise figure out the entries of the PARALLEL. */
5267 {
5269 {
5274 /* Merge TImodes on aligned occasions here too. */
5279 else
5281 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5287 intreg++;
5294 sse_regno++;
5301 sse_regno++;
5306 else
5313 i++;
5314 sse_regno++;
5318 }
5319 }
5321 /* Empty aligned struct, union or class. */
5329 }
5331 /* Update the data in CUM to advance over an argument of mode MODE
5332 and data type TYPE. (TYPE is null for libcalls where that information
5333 may not be available.) */
5335 static void
5338 {
5340 {
5347 /* FALLTHRU */
5358 {
5361 }
5370 /* FALLTHRU */
5387 {
5392 {
5395 }
5396 }
5405 {
5410 {
5413 }
5414 }
5416 }
5417 }
5419 static void
5422 {
5425 /* Unnamed 256bit vector mode parameters are passed on stack. */
5432 {
5437 }
5438 else
5440 }
5442 static void
5444 HOST_WIDE_INT words)
5445 {
5446 /* Otherwise, this should be passed indirect. */
5451 {
5454 }
5455 }
5457 void
5460 {
5465 else
5476 else
5478 }
5480 /* Define where to put the arguments to a function.
5481 Value is zero to push the argument on the stack,
5482 or a hard register in which to store the argument.
5484 MODE is the argument's machine mode.
5485 TYPE is the data type of the argument (as a tree).
5486 This is null for libcalls where that information may
5487 not be available.
5488 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5489 the preceding args and about the function being called.
5490 NAMED is nonzero if this argument is a named parameter
5491 (otherwise it is an extra parameter matching an ellipsis). */
5493 static rtx
5497 {
5500 /* Avoid the AL settings for the Unix64 ABI. */
5505 {
5512 /* FALLTHRU */
5518 {
5521 /* Fastcall allocates the first two DWORD (SImode) or
5522 smaller arguments to ECX and EDX if it isn't an
5523 aggregate type . */
5525 {
5531 /* ECX not EAX is the first allocated register. */
5534 }
5536 }
5545 /* FALLTHRU */
5547 /* In 32bit, we pass TImode in xmm registers. */
5555 {
5557 {
5561 }
5565 }
5569 /* In 32bit, we pass OImode in ymm registers. */
5577 {
5579 {
5583 }
5587 }
5596 {
5598 {
5602 }
5606 }
5608 }
5611 }
5613 static rtx
5616 {
5619 /* Handle a hidden AL argument containing number of registers
5620 for varargs x86-64 functions. */
5625 ? SSE_REGPARM_MAX
5632 {
5642 /* In 64bit, we pass TImode in interger registers and OImode on
5643 stack. */
5645 {
5647 {
5651 }
5652 }
5654 /* Unnamed 256bit vector mode parameters are passed on stack. */
5658 }
5664 }
5666 static rtx
5669 HOST_WIDE_INT bytes)
5670 {
5673 /* Avoid the AL settings for the Unix64 ABI. */
5677 /* If we've run out of registers, it goes on the stack. */
5683 /* Only floating point modes are passed in anything but integer regs. */
5685 {
5688 else
5689 {
5692 /* Unnamed floating parameters are passed in both the
5693 SSE and integer registers. */
5699 }
5700 }
5701 /* Handle aggregated types passed in register. */
5703 {
5708 }
5711 }
5713 rtx
5716 {
5722 else
5726 /* To simplify the code below, represent vector types with a vector mode
5727 even if MMX/SSE are not active. */
5735 else
5737 }
5739 /* A C expression that indicates when an argument must be passed by
5740 reference. If nonzero for an argument, a copy of that argument is
5741 made in memory and a pointer to the argument is passed instead of
5742 the argument itself. The pointer is passed in whatever way is
5743 appropriate for passing a pointer to that type. */
5745 static bool
5749 {
5750 /* See Windows x64 Software Convention. */
5752 {
5755 {
5756 /* Arrays are passed by reference. */
5761 {
5762 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5763 are passed by reference. */
5765 }
5766 }
5768 /* __m128 is passed by reference. */
5774 }
5775 }
5780 }
5782 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5783 ABI. */
5784 static bool
5786 {
5798 {
5799 /* Walk the aggregates recursively. */
5801 {
5805 {
5806 tree field;
5808 /* Walk all the structure fields. */
5810 {
5814 }
5816 }
5819 /* Just for use if some languages passes arrays by value. */
5826 }
5827 }
5829 }
5831 /* Gives the alignment boundary, in bits, of an argument with the
5832 specified mode and type. */
5834 int
5836 {
5839 {
5840 /* Since canonical type is used for call, we convert it to
5841 canonical type if needed. */
5845 }
5846 else
5850 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5851 natural boundaries. */
5853 {
5854 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5855 make an exception for SSE modes since these require 128bit
5856 alignment.
5858 The handling here differs from field_alignment. ICC aligns MMX
5859 arguments to 4 byte boundaries, while structure fields are aligned
5860 to 8 byte boundaries. */
5862 {
5865 }
5866 else
5867 {
5870 }
5871 }
5875 }
5877 /* Return true if N is a possible register number of function value. */
5879 bool
5881 {
5883 {
5888 /* TODO: The function should depend on current function ABI but
5889 builtins.c would need updating then. Therefore we use the
5890 default ABI. */
5902 }
5905 }
5907 /* Define how to find the value returned by a function.
5908 VALTYPE is the data type of the value (as a tree).
5909 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5910 otherwise, FUNC is 0. */
5912 static rtx
5915 {
5918 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5919 we normally prevent this case when mmx is not available. However
5920 some ABIs may require the result to be returned like DImode. */
5924 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5925 we prevent this case when sse is not available. However some ABIs
5926 may require the result to be returned like integer TImode. */
5931 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5934 else
5935 /* Most things go in %eax. */
5938 /* Override FP return register with %xmm0 for local functions when
5939 SSE math is enabled or for functions with sseregparm attribute. */
5941 {
5946 }
5949 }
5951 static rtx
5953 const_tree valtype)
5954 {
5955 rtx ret;
5957 /* Handle libcalls, which don't provide a type node. */
5959 {
5961 {
5978 }
5979 }
5985 /* For zero sized structures, construct_container returns NULL, but we
5986 need to keep rest of compiler happy by returning meaningful value. */
5991 }
5993 static rtx
5995 {
5999 {
6001 {
6014 }
6015 }
6017 }
6019 static rtx
6022 {
6034 else
6036 }
6038 static rtx
6041 {
6047 }
6049 rtx
6051 {
6053 }
6055 /* Return true iff type is returned in memory. */
6057 static int ATTRIBUTE_UNUSED
6059 {
6060 HOST_WIDE_INT size;
6071 {
6072 /* User-created vectors small enough to fit in EAX. */
6076 /* MMX/3dNow values are returned in MM0,
6077 except when it doesn't exits. */
6081 /* SSE values are returned in XMM0, except when it doesn't exist. */
6084 }
6092 }
6094 static int ATTRIBUTE_UNUSED
6096 {
6099 }
6101 static int ATTRIBUTE_UNUSED
6103 {
6106 /* __m128 is returned in xmm0. */
6111 /* Otherwise, the size must be exactly in [1248]. */
6113 }
6115 static bool
6117 {
6118 #ifdef SUBTARGET_RETURN_IN_MEMORY
6120 #else
6127 else
6129 #endif
6130 }
6132 /* Return false iff TYPE is returned in memory. This version is used
6133 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6134 but differs notably in that when MMX is available, 8-byte vectors
6135 are returned in memory, rather than in MMX registers. */
6137 bool
6139 {
6152 {
6153 /* Return in memory only if MMX registers *are* available. This
6154 seems backwards, but it is consistent with the existing
6155 Solaris x86 ABI. */
6160 }
6167 }
6169 /* When returning SSE vector types, we have a choice of either
6170 (1) being abi incompatible with a -march switch, or
6171 (2) generating an error.
6172 Given no good solution, I think the safest thing is one warning.
6173 The user won't be able to use -Werror, but....
6175 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6176 called in response to actually generating a caller or callee that
6177 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6178 via aggregate_value_p for general type probing from tree-ssa. */
6180 static rtx
6182 {
6186 {
6187 /* Look at the return type of the function, not the function type. */
6191 {
6194 {
6198 }
6199 }
6202 {
6204 {
6208 }
6209 }
6210 }
6213 }
6215 \f
6216 /* Create the va_list data type. */
6218 /* Returns the calling convention specific va_list date type.
6219 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6221 static tree
6223 {
6226 /* For i386 we use plain pointer to argument area. */
6234 unsigned_type_node);
6236 unsigned_type_node);
6238 ptr_type_node);
6240 ptr_type_node);
6259 /* The correct type is an array type of one element. */
6261 }
6263 /* Setup the builtin va_list data type and for 64-bit the additional
6264 calling convention specific va_list data types. */
6266 static tree
6268 {
6271 /* Initialize abi specific va_list builtin types. */
6273 {
6274 tree t;
6276 {
6281 }
6282 else
6283 {
6288 }
6290 {
6295 }
6296 else
6297 {
6302 }
6303 }
6306 }
6308 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6310 static void
6312 {
6314 rtx label;
6315 rtx label_ref;
6316 rtx tmp_reg;
6317 rtx nsse_reg;
6318 alias_set_type set;
6325 /* GPR size of varargs save area. */
6328 else
6331 /* FPR size of varargs save area. We don't need it if we don't pass
6332 anything in SSE registers. */
6335 else
6345 i < regparm
6347 i++)
6348 {
6355 }
6358 {
6359 /* Now emit code to save SSE registers. The AX parameter contains number
6360 of SSE parameter registers used to call this function. We use
6361 sse_prologue_save insn template that produces computed jump across
6362 SSE saves. We need some preparation work to get this working. */
6367 /* Compute address to jump to :
6368 label - eax*4 + nnamed_sse_arguments*4 Or
6369 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6377 /* vmovaps is one byte longer than movaps. */
6381 nsse_reg)));
6384 emit_move_insn
6388 label_ref,
6391 else
6395 /* Compute address of memory block we save into. We always use pointer
6396 pointing 127 bytes after first byte to store - this is needed to keep
6397 instruction size limited by 4 bytes (5 bytes for AVX) with one
6398 byte displacement. */
6408 /* And finally do the dirty job! */
6411 }
6412 }
6414 static void
6416 {
6421 {
6432 }
6433 }
6435 static void
6439 {
6440 CUMULATIVE_ARGS next_cum;
6441 tree fntype;
6443 /* This argument doesn't appear to be used anymore. Which is good,
6444 because the old code here didn't suppress rtl generation. */
6452 /* For varargs, we do not want to skip the dummy va_dcl argument.
6453 For stdargs, we do want to skip the last named argument. */
6460 else
6462 }
6464 /* Checks if TYPE is of kind va_list char *. */
6466 static bool
6468 {
6469 tree canonic;
6471 /* For 32-bit it is always true. */
6477 }
6479 /* Implement va_start. */
6481 static void
6483 {
6487 tree type;
6489 /* Only 64bit target needs something special. */
6491 {
6494 }
6507 /* Count number of gp and fp argument registers used. */
6513 {
6519 }
6522 {
6528 }
6530 /* Find the overflow area. */
6541 {
6542 /* Find the register save area.
6543 Prologue of the function save it right above stack frame. */
6552 }
6553 }
6555 /* Implement va_arg. */
6557 static tree
6560 {
6567 rtx container;
6569 tree ptrtype;
6573 /* Only 64bit target needs something special. */
6597 {
6604 /* Unnamed 256bit vector mode parameters are passed on stack. */
6606 {
6609 }
6617 }
6619 /* Pull the value out of the saved registers. */
6625 {
6639 /* In case we are passing structure, verify that it is consecutive block
6640 on the register save area. If not we need to do moves. */
6642 {
6643 /* Verify that all registers are strictly consecutive */
6645 {
6649 {
6654 }
6655 }
6656 else
6657 {
6661 {
6666 }
6667 }
6668 }
6670 {
6673 }
6674 else
6675 {
6680 }
6682 /* First ensure that we fit completely in registers. */
6684 {
6691 }
6693 {
6701 }
6703 /* Compute index to start of area used for integer regs. */
6705 {
6706 /* int_addr = gpr + sav; */
6710 }
6712 {
6713 /* sse_addr = fpr + sav; */
6717 }
6719 {
6723 /* addr = &temp; */
6728 {
6739 {
6742 }
6743 else
6744 {
6747 }
6759 }
6760 }
6763 {
6767 }
6770 {
6774 }
6779 }
6781 /* ... otherwise out of the overflow area. */
6783 /* When we align parameter on stack for caller, if the parameter
6784 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6785 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6786 here with caller. */
6791 /* Care for on-stack alignment if needed. */
6795 else
6796 {
6804 }
6821 }
6822 \f
6823 /* Return nonzero if OPNUM's MEM should be matched
6824 in movabs* patterns. */
6826 int
6828 {
6840 }
6841 \f
6842 /* Initialize the table of extra 80387 mathematical constants. */
6844 static void
6846 {
6848 {
6854 };
6858 {
6860 /* Ensure each constant is rounded to XFmode precision. */
6863 }
6866 }
6868 /* Return true if the constant is something that can be loaded with
6869 a special instruction. */
6871 int
6873 {
6876 REAL_VALUE_TYPE r;
6888 /* For XFmode constants, try to find a special 80387 instruction when
6889 optimizing for size or on those CPUs that benefit from them. */
6892 {
6901 }
6903 /* Load of the constant -0.0 or -1.0 will be split as
6904 fldz;fchs or fld1;fchs sequence. */
6911 }
6913 /* Return the opcode of the special instruction to be used to load
6914 the constant X. */
6918 {
6920 {
6940 }
6941 }
6943 /* Return the CONST_DOUBLE representing the 80387 constant that is
6944 loaded by the specified special instruction. The argument IDX
6945 matches the return value from standard_80387_constant_p. */
6947 rtx
6949 {
6956 {
6967 }
6970 XFmode);
6971 }
6973 /* Return 1 if mode is a valid mode for sse. */
6974 static int
6976 {
6978 {
6989 }
6990 }
6992 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
6993 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
6994 modes and AVX is enabled. */
6996 int
6998 {
7004 {
7009 }
7012 }
7014 /* Return the opcode of the special instruction to be used to load
7015 the constant X. */
7019 {
7021 {
7024 {
7039 }
7043 {
7051 }
7052 else
7054 }
7056 }
7058 /* Returns 1 if OP contains a symbol reference */
7060 int
7062 {
7071 {
7073 {
7079 }
7083 }
7086 }
7088 /* Return 1 if it is appropriate to emit `ret' instructions in the
7089 body of a function. Do this only if the epilogue is simple, needing a
7090 couple of insns. Prior to reloading, we can't tell how many registers
7091 must be saved, so return 0 then. Return 0 if there is no frame
7092 marker to de-allocate. */
7094 int
7096 {
7102 /* Don't allow more than 32 pop, since that's all we can do
7103 with one instruction. */
7110 }
7111 \f
7112 /* Value should be nonzero if functions must have frame pointers.
7113 Zero means the frame pointer need not be set up (and parms may
7114 be accessed via the stack pointer) in functions that seem suitable. */
7116 int
7118 {
7119 /* If we accessed previous frames, then the generated code expects
7120 to be able to access the saved ebp value in our frame. */
7124 /* Several x86 os'es need a frame pointer for other reasons,
7125 usually pertaining to setjmp. */
7129 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7130 the frame pointer by default. Turn it back on now if we've not
7131 got a leaf function. */
7133 && (!current_function_is_leaf
7141 }
7143 /* Record that the current function accesses previous call frames. */
7145 void
7147 {
7149 }
7150 \f
7151 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7152 # define USE_HIDDEN_LINKONCE 1
7153 #else
7154 # define USE_HIDDEN_LINKONCE 0
7155 #endif
7159 /* Fills in the label name that should be used for a pc thunk for
7160 the given register. */
7162 static void
7164 {
7169 else
7171 }
7174 /* This function generates code for -fpic that loads %ebx with
7175 the return address of the caller and then returns. */
7177 void
7179 {
7184 {
7192 #if TARGET_MACHO
7194 {
7202 }
7203 else
7204 #endif
7206 {
7207 tree decl;
7210 error_mark_node);
7223 }
7224 else
7225 {
7228 }
7234 }
7238 }
7240 /* Emit code for the SET_GOT patterns. */
7244 {
7250 {
7251 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7256 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7257 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7258 an unadorned address. */
7263 }
7268 {
7273 else
7276 #if TARGET_MACHO
7277 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7278 is what will be referenced by the Mach-O PIC subsystem. */
7281 #endif
7288 }
7289 else
7290 {
7298 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7299 is what will be referenced by the Mach-O PIC subsystem. */
7300 #if TARGET_MACHO
7303 else
7306 #endif
7307 }
7314 else
7318 }
7320 /* Generate an "push" pattern for input ARG. */
7322 static rtx
7324 {
7328 stack_pointer_rtx)),
7329 arg);
7330 }
7332 /* Return >= 0 if there is an unused call-clobbered register available
7333 for the entire function. */
7335 static unsigned int
7337 {
7340 {
7342 /* Can't use the same register for both PIC and DRAP. */
7345 else
7350 }
7353 }
7355 /* Return 1 if we need to save REGNO. */
7356 static int
7358 {
7365 {
7369 }
7372 {
7375 {
7381 }
7382 }
7392 }
7394 /* Return number of registers to be saved on the stack. */
7396 static int
7398 {
7404 nregs++;
7406 }
7408 /* Given FROM and TO register numbers, say whether this elimination is
7409 allowed. If stack alignment is needed, we can only replace argument
7410 pointer with hard frame pointer, or replace frame pointer with stack
7411 pointer. Otherwise, frame pointer elimination is automatically
7412 handled and all other eliminations are valid. */
7414 int
7416 {
7422 else
7424 }
7426 /* Return the offset between two registers, one to be eliminated, and the other
7427 its replacement, at the start of a routine. */
7429 HOST_WIDE_INT
7431 {
7440 else
7441 {
7449 }
7450 }
7452 /* Fill structure ix86_frame about frame of currently computed function. */
7454 static void
7456 {
7457 HOST_WIDE_INT total_size;
7459 HOST_WIDE_INT offset;
7473 /* During reload iteration the amount of registers saved can change.
7474 Recompute the value as needed. Do not recompute when amount of registers
7475 didn't change as reload does multiple calls to the function and does not
7476 expect the decision to change within single iteration. */
7479 {
7483 /* The fast prologue uses move instead of push to save registers. This
7484 is significantly longer, but also executes faster as modern hardware
7485 can execute the moves in parallel, but can't do that for push/pop.
7487 Be careful about choosing what prologue to emit: When function takes
7488 many instructions to execute we may use slow version as well as in
7489 case function is known to be outside hot spot (this is known with
7490 feedback only). Weight the size of function by number of registers
7491 to save as it is cheap to use one or two push instructions but very
7492 slow to use many of them. */
7496 || (flag_branch_probabilities
7499 else
7502 }
7506 else
7510 /* Skip return address and saved base pointer. */
7515 /* Set offset to aligned because the realigned frame starts from
7516 here. */
7520 /* Register save area */
7523 /* Va-arg area */
7527 /* Align start of frame for local function. */
7533 /* Frame pointer points here. */
7538 /* Add outgoing arguments area. Can be skipped if we eliminated
7539 all the function calls as dead code.
7540 Skipping is however impossible when function calls alloca. Alloca
7541 expander assumes that last crtl->outgoing_args_size
7542 of stack frame are unused. */
7546 {
7549 }
7550 else
7553 /* Align stack boundary. Only needed if we're calling another function
7554 or using alloca. */
7559 else
7564 /* We've reached end of stack frame. */
7567 /* Size prologue needs to allocate. */
7577 && current_function_is_leaf
7579 {
7585 }
7586 else
7590 #if 0
7606 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7607 #endif
7608 }
7610 /* Emit code to save registers in the prologue. */
7612 static void
7614 {
7616 rtx insn;
7620 {
7623 }
7624 }
7626 /* Emit code to save registers using MOV insns. First register
7627 is restored from POINTER + OFFSET. */
7628 static void
7630 {
7632 rtx insn;
7636 {
7642 }
7643 }
7645 /* Expand prologue or epilogue stack adjustment.
7646 The pattern exist to put a dependency on all ebp-based memory accesses.
7647 STYLE should be negative if instructions should be marked as frame related,
7648 zero if %r11 register is live and cannot be freely used and positive
7649 otherwise. */
7651 static void
7653 {
7654 rtx insn;
7660 else
7661 {
7662 rtx r11;
7663 /* r11 is used by indirect sibcall return as well, set before the
7664 epilogue and used after the epilogue. ATM indirect sibcall
7665 shouldn't be used together with huge frame sizes in one
7666 function because of the frame_size check in sibcall.c. */
7673 offset));
7674 }
7677 }
7679 /* Find an available register to be used as dynamic realign argument
7680 pointer regsiter. Such a register will be written in prologue and
7681 used in begin of body, so it must not be
7682 1. parameter passing register.
7683 2. GOT pointer.
7684 We reuse static-chain register if it is available. Otherwise, we
7685 use DI for i386 and R13 for x86-64. We chose R13 since it has
7686 shorter encoding.
7688 Return: the regno of chosen register. */
7690 static unsigned int
7692 {
7696 {
7697 /* Use R13 for nested function or function need static chain.
7698 Since function with tail call may use any caller-saved
7699 registers in epilogue, DRAP must not use caller-saved
7700 register in such case. */
7707 }
7708 else
7709 {
7710 /* Use DI for nested function or function need static chain.
7711 Since function with tail call may use any caller-saved
7712 registers in epilogue, DRAP must not use caller-saved
7713 register in such case. */
7719 /* Reuse static chain register if it isn't used for parameter
7720 passing. */
7725 else
7727 }
7728 }
7730 /* Update incoming stack boundary and estimated stack alignment. */
7732 static void
7734 {
7735 /* Prefer the one specified at command line. */
7736 ix86_incoming_stack_boundary
7737 = (ix86_user_incoming_stack_boundary
7738 ? ix86_user_incoming_stack_boundary
7741 /* Incoming stack alignment can be changed on individual functions
7742 via force_align_arg_pointer attribute. We use the smallest
7743 incoming stack boundary. */
7749 /* Stack at entrance of main is aligned by runtime. We use the
7750 smallest incoming stack boundary. */
7757 /* x86_64 vararg needs 16byte stack alignment for register save
7758 area. */
7763 }
7765 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7766 needed or an rtx for DRAP otherwise. */
7768 static rtx
7770 {
7775 {
7776 /* Assign DRAP to vDRAP and returns vDRAP */
7778 rtx drap_vreg;
7779 rtx arg_ptr;
7793 }
7794 else
7796 }
7798 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7800 static rtx
7802 {
7804 }
7806 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7807 This is called from dwarf2out.c to emit call frame instructions
7808 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7809 static void
7811 {
7816 {
7827 }
7828 }
7830 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
7831 to be generated in correct form. */
7832 static void
7834 {
7835 /* Check if stack realign is really needed after reload, and
7836 stores result in cfun */
7837 unsigned int incoming_stack_boundary
7841 < (current_function_is_leaf
7846 {
7847 /* After stack_realign_needed is finalized, we can't no longer
7848 change it. */
7850 }
7851 else
7852 {
7855 }
7856 }
7858 /* Expand the prologue into a bunch of separate insns. */
7860 void
7862 {
7863 rtx insn;
7866 HOST_WIDE_INT allocate;
7870 /* DRAP should not coexist with stack_realign_fp */
7875 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
7876 of DRAP is needed and stack realignment is really needed after reload */
7878 {
7886 /* Grab the argument pointer. */
7891 /* Only need to push parameter pointer reg if it is caller
7892 saved reg */
7894 {
7895 /* Push arg pointer reg */
7898 }
7903 /* Align the stack. */
7905 stack_pointer_rtx,
7909 /* Replicate the return address on the stack so that return
7910 address can be reached via (argp - 1) slot. This is needed
7911 to implement macro RETURN_ADDR_RTX and intrinsic function
7912 expand_builtin_return_addr etc. */
7918 }
7920 /* Note: AT&T enter does NOT have reversed args. Enter is probably
7921 slower on all targets. Also sdb doesn't like it. */
7924 {
7930 }
7933 {
7937 /* Align the stack. */
7939 stack_pointer_rtx,
7942 }
7948 else
7951 /* When using red zone we may start register saving before allocating
7952 the stack frame saving one cycle of the prologue. However I will
7953 avoid doing this if I am going to have to probe the stack since
7954 at least on x86_64 the stack probe can turn into a call that clobbers
7955 a red zone location */
7960 ? hard_frame_pointer_rtx
7965 ;
7969 else
7970 {
7971 /* Only valid for Win32. */
7974 rtx t;
7980 else
7984 {
7987 }
7993 else
8003 {
8006 allocate
8009 else
8012 }
8013 }
8018 {
8024 else
8027 }
8033 {
8040 }
8043 {
8045 {
8047 {
8057 }
8058 else
8060 }
8061 else
8063 }
8065 /* Prevent function calls from being scheduled before the call to mcount.
8066 In the pic_reg_used case, make sure that the got load isn't deleted. */
8068 {
8072 }
8075 {
8076 /* vDRAP is setup but after reload it turns out stack realign
8077 isn't necessary, here we will emit prologue to setup DRAP
8078 without stack realign adjustment */
8082 }
8084 /* Emit cld instruction if stringops are used in the function. */
8087 }
8089 /* Emit code to restore saved registers using MOV insns. First register
8090 is restored from POINTER + OFFSET. */
8091 static void
8094 {
8100 {
8101 /* Ensure that adjust_address won't be forced to produce pointer
8102 out of range allowed by x86-64 instruction set. */
8104 {
8105 rtx r11;
8112 }
8116 }
8117 }
8119 /* Restore function stack, frame, and registers. */
8121 void
8123 {
8127 HOST_WIDE_INT offset;
8131 /* When stack is realigned, SP must be valid. */
8132 sp_valid = (!frame_pointer_needed
8133 || current_function_sp_is_unchanging
8138 /* Calculate start of saved registers relative to ebp. Special care
8139 must be taken for the normal return case of a function using
8140 eh_return: the eax and edx registers are marked as saved, but not
8141 restored along this path. */
8147 /* If we're only restoring one register and sp is not valid then
8148 using a move instruction to restore the register since it's
8149 less work than reloading sp and popping the register.
8151 The default code result in stack adjustment using add/lea instruction,
8152 while this code results in LEAVE instruction (or discrete equivalent),
8153 so it is profitable in some other cases as well. Especially when there
8154 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8155 and there is exactly one register to pop. This heuristic may need some
8156 tuning in future. */
8158 || (TARGET_EPILOGUE_USING_MOVE
8166 {
8167 /* Restore registers. We can use ebp or esp to address the memory
8168 locations. If both are available, default to ebp, since offsets
8169 are known to be small. Only exception is esp pointing directly
8170 to the end of block of saved registers, where we may simplify
8171 addressing mode.
8173 If we are realigning stack with bp and sp, regs restore can't
8174 be addressed by bp. sp must be used instead. */
8181 else
8185 /* eh_return epilogues need %ecx added to the stack pointer. */
8187 {
8190 /* Stack align doesn't work with eh_return. */
8194 {
8204 }
8205 else
8206 {
8211 }
8212 }
8217 style);
8218 /* If not an i386, mov & pop is faster than "leave". */
8222 else
8223 {
8225 hard_frame_pointer_rtx,
8229 }
8230 }
8231 else
8232 {
8233 /* First step is to deallocate the stack frame so that we can
8234 pop the registers.
8236 If we realign stack with frame pointer, then stack pointer
8237 won't be able to recover via lea $offset(%bp), %sp, because
8238 there is a padding area between bp and sp for realign.
8239 "add $to_allocate, %sp" must be used instead. */
8241 {
8245 hard_frame_pointer_rtx,
8247 }
8256 {
8257 /* Leave results in shorter dependency chains on CPUs that are
8258 able to grok it fast. */
8261 else
8262 {
8263 /* For stack realigned really happens, recover stack
8264 pointer to hard frame pointer is a must, if not using
8265 leave. */
8268 hard_frame_pointer_rtx,
8271 }
8272 }
8273 }
8276 {
8287 }
8289 /* Sibcall epilogues don't want a return instruction. */
8294 {
8297 /* i386 can only pop 64K bytes. If asked to pop more, pop
8298 return address, do explicit add, and jump indirectly to the
8299 caller. */
8302 {
8305 /* There is no "pascal" calling convention in any 64bit ABI. */
8311 }
8312 else
8314 }
8315 else
8317 }
8319 /* Reset from the function's potential modifications. */
8321 static void
8323 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8324 {
8327 #if TARGET_MACHO
8328 /* Mach-O doesn't support labels at the end of objects, so if
8329 it looks like we might want one, insert a NOP. */
8330 {
8341 }
8342 #endif
8344 }
8345 \f
8346 /* Extract the parts of an RTL expression that is a valid memory address
8347 for an instruction. Return 0 if the structure of the address is
8348 grossly off. Return -1 if the address contains ASHIFT, so it is not
8349 strictly valid, but still used for computing length of lea instruction. */
8351 int
8353 {
8364 {
8369 do
8370 {
8375 }
8382 {
8385 {
8395 && TARGET_TLS_DIRECT_SEG_REFS
8398 else
8408 else
8423 }
8424 }
8425 }
8427 {
8430 }
8432 {
8433 rtx tmp;
8435 /* We're called for lea too, which implements ashift on occasion. */
8445 }
8446 else
8449 /* Extract the integral value of scale. */
8451 {
8455 }
8460 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8465 {
8466 rtx tmp;
8469 }
8471 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8477 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8478 Avoid this by transforming to [%esi+0].
8479 Reload calls address legitimization without cfun defined, so we need
8480 to test cfun for being non-NULL. */
8487 /* Special case: encode reg+reg instead of reg*2. */
8491 /* Special case: scaling cannot be encoded without base or displacement. */
8502 }
8503 \f
8504 /* Return cost of the memory address x.
8505 For i386, it is better to use a complex address than let gcc copy
8506 the address into a reg and make a new pseudo. But not if the address
8507 requires to two regs - that would mean more pseudos with longer
8508 lifetimes. */
8509 static int
8511 {
8523 /* Attempt to minimize number of registers in the address. */
8529 cost++;
8536 cost++;
8538 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8539 since it's predecode logic can't detect the length of instructions
8540 and it degenerates to vector decoded. Increase cost of such
8541 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8542 to split such addresses or even refuse such addresses at all.
8544 Following addressing modes are affected:
8545 [base+scale*index]
8546 [scale*index+disp]
8547 [base+index]
8549 The first and last case may be avoidable by explicitly coding the zero in
8550 memory address, but I don't have AMD-K6 machine handy to check this
8551 theory. */
8560 }
8561 \f
8562 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8563 this is used for to form addresses to local data when -fPIC is in
8564 use. */
8566 static bool
8568 {
8571 }
8573 /* Determine if a given RTX is a valid constant. We already know this
8574 satisfies CONSTANT_P. */
8576 bool
8578 {
8580 {
8585 {
8589 }
8594 /* Only some unspecs are valid as "constants". */
8597 {
8613 }
8615 /* We must have drilled down to a symbol. */
8620 /* FALLTHRU */
8623 /* TLS symbols are never valid. */
8627 /* DLLIMPORT symbols are never valid. */
8647 }
8649 /* Otherwise we handle everything else in the move patterns. */
8651 }
8653 /* Determine if it's legal to put X into the constant pool. This
8654 is not possible for the address of thread-local symbols, which
8655 is checked above. */
8657 static bool
8659 {
8660 /* We can always put integral constants and vectors in memory. */
8662 {
8670 }
8672 }
8674 /* Determine if a given RTX is a valid constant address. */
8676 bool
8678 {
8680 }
8682 /* Nonzero if the constant value X is a legitimate general operand
8683 when generating PIC code. It is given that flag_pic is on and
8684 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8686 bool
8688 {
8689 rtx inner;
8692 {
8699 /* Only some unspecs are valid as "constants". */
8702 {
8715 }
8716 /* FALLTHRU */
8724 }
8725 }
8727 /* Determine if a given CONST RTX is a valid memory displacement
8728 in PIC mode. */
8730 int
8732 {
8735 /* In 64bit mode we can allow direct addresses of symbols and labels
8736 when they are not dynamic symbols. */
8738 {
8742 {
8759 /* FALLTHRU */
8762 /* TLS references should always be enclosed in UNSPEC. */
8772 }
8773 }
8779 {
8780 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8781 of GOT tables. We should not need these anyway. */
8792 }
8796 {
8801 }
8810 {
8814 /* We need to check for both symbols and labels because VxWorks loads
8815 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8816 details. */
8820 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8821 While ABI specify also 32bit relocation but we don't produce it in
8822 small PIC model at all. */
8844 }
8847 }
8849 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
8850 memory address for an instruction. The MODE argument is the machine mode
8851 for the MEM expression that wants to use this address.
8853 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
8854 convert common non-canonical forms to canonical form so that they will
8855 be recognized. */
8857 int
8860 {
8863 HOST_WIDE_INT scale;
8868 {
8871 }
8878 /* Validate base register.
8880 Don't allow SUBREG's that span more than a word here. It can lead to spill
8881 failures when the base is one word out of a two word structure, which is
8882 represented internally as a DImode int. */
8885 {
8886 rtx reg;
8896 else
8897 {
8900 }
8903 {
8906 }
8910 {
8913 }
8914 }
8916 /* Validate index register.
8918 Don't allow SUBREG's that span more than a word here -- same as above. */
8921 {
8922 rtx reg;
8932 else
8933 {
8936 }
8939 {
8942 }
8946 {
8949 }
8950 }
8952 /* Validate scale factor. */
8954 {
8957 {
8960 }
8963 {
8966 }
8967 }
8969 /* Validate displacement. */
8971 {
8978 {
8979 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
8980 used. While ABI specify also 32bit relocations, we don't produce
8981 them at all and use IP relative instead. */
9004 }
9007 && (flag_pic
9008 || (TARGET_MACHO
9009 #if TARGET_MACHO
9010 && MACHOPIC_INDIRECT
9012 #endif
9013 )))
9014 {
9016 is_legitimate_pic:
9018 {
9019 /* foo@dtpoff(%rX) is ok. */
9026 {
9029 }
9030 }
9032 {
9035 }
9037 /* This code used to verify that a symbolic pic displacement
9038 includes the pic_offset_table_rtx register.
9040 While this is good idea, unfortunately these constructs may
9041 be created by "adds using lea" optimization for incorrect
9042 code like:
9044 int a;
9045 int foo(int i)
9046 {
9047 return *(&a+i);
9048 }
9050 This code is nonsensical, but results in addressing
9051 GOT table with pic_offset_table_rtx base. We can't
9052 just refuse it easily, since it gets matched by
9053 "addsi3" pattern, that later gets split to lea in the
9054 case output register differs from input. While this
9055 can be handled by separate addsi pattern for this case
9056 that never results in lea, this seems to be easier and
9057 correct fix for crash to disable this test. */
9058 }
9065 {
9068 }
9071 {
9074 }
9075 }
9077 /* Everything looks valid. */
9080 report_error:
9082 }
9083 \f
9084 /* Return a unique alias set for the GOT. */
9086 static alias_set_type
9088 {
9093 }
9095 /* Return a legitimate reference for ORIG (an address) using the
9096 register REG. If REG is 0, a new pseudo is generated.
9098 There are two types of references that must be handled:
9100 1. Global data references must load the address from the GOT, via
9101 the PIC reg. An insn is emitted to do this load, and the reg is
9102 returned.
9104 2. Static data references, constant pool addresses, and code labels
9105 compute the address as an offset from the GOT, whose base is in
9106 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9107 differentiate them from global data objects. The returned
9108 address is the PIC reg + an unspec constant.
9110 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9111 reg also appears in the address. */
9113 static rtx
9115 {
9118 rtx base;
9120 #if TARGET_MACHO
9122 {
9125 /* Use the generic Mach-O PIC machinery. */
9127 }
9128 #endif
9135 {
9136 rtx tmpreg;
9137 /* This symbol may be referenced via a displacement from the PIC
9138 base address (@GOTOFF). */
9145 {
9147 UNSPEC_GOTOFF);
9149 }
9150 else
9155 else
9160 {
9164 }
9166 }
9168 {
9169 /* This symbol may be referenced via a displacement from the PIC
9170 base address (@GOTOFF). */
9177 {
9179 UNSPEC_GOTOFF);
9181 }
9182 else
9188 {
9191 }
9192 }
9194 /* We can't use @GOTOFF for text labels on VxWorks;
9195 see gotoff_operand. */
9197 {
9199 {
9205 {
9208 }
9209 }
9212 {
9220 /* Use directly gen_movsi, otherwise the address is loaded
9221 into register for CSE. We don't want to CSE this addresses,
9222 instead we CSE addresses from the GOT table, so skip this. */
9225 }
9226 else
9227 {
9228 /* This symbol must be referenced via a load from the
9229 Global Offset Table (@GOT). */
9245 }
9246 }
9247 else
9248 {
9251 {
9253 {
9256 }
9257 else
9259 }
9261 {
9264 /* We must match stuff we generate before. Assume the only
9265 unspecs that can get here are ours. Not that we could do
9266 anything with them anyway.... */
9272 }
9274 {
9277 /* Check first to see if this is a constant offset from a @GOTOFF
9278 symbol reference. */
9281 {
9283 {
9287 UNSPEC_GOTOFF);
9293 {
9296 }
9297 }
9298 else
9299 {
9302 {
9306 }
9307 }
9308 }
9309 else
9310 {
9317 else
9318 {
9320 {
9323 }
9325 }
9326 }
9327 }
9328 }
9330 }
9331 \f
9332 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9334 static rtx
9336 {
9348 }
9350 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9351 false if we expect this to be used for a memory address and true if
9352 we expect to load the address into a register. */
9354 static rtx
9356 {
9361 {
9367 {
9377 }
9380 else
9384 {
9388 }
9396 {
9408 }
9411 else
9415 {
9420 }
9428 {
9432 }
9438 {
9441 }
9443 {
9448 }
9450 {
9454 }
9455 else
9456 {
9459 }
9469 {
9473 }
9474 else
9475 {
9479 }
9489 {
9492 }
9493 else
9494 {
9498 }
9503 }
9506 }
9508 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9509 to symbol DECL. */
9512 htab_t dllimport_map;
9514 static tree
9516 {
9523 tree to;
9524 rtx rtl;
9567 }
9569 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9570 true if we require the result be a register. */
9572 static rtx
9574 {
9575 tree imp_decl;
9576 rtx x;
9585 }
9587 /* Try machine-dependent ways of modifying an illegitimate address
9588 to be legitimate. If we find one, return the new, valid address.
9589 This macro is used in only one place: `memory_address' in explow.c.
9591 OLDX is the address as it was before break_out_memory_refs was called.
9592 In some cases it is useful to look at this to decide what needs to be done.
9594 MODE and WIN are passed so that this macro can use
9595 GO_IF_LEGITIMATE_ADDRESS.
9597 It is always safe for this macro to do nothing. It exists to recognize
9598 opportunities to optimize the output.
9600 For the 80386, we handle X+REG by loading X into a register R and
9601 using R+REG. R will go in a general reg and indexing will be used.
9602 However, if REG is a broken-out memory address or multiplication,
9603 nothing needs to be done because REG can certainly go in a general reg.
9605 When -fpic is used, special handling is needed for symbolic references.
9606 See comments by legitimize_pic_address in i386.c for details. */
9608 rtx
9610 {
9621 {
9625 }
9628 {
9635 {
9638 }
9639 }
9644 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9648 {
9653 }
9656 {
9657 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9662 {
9668 }
9673 {
9679 }
9681 /* Put multiply first if it isn't already. */
9683 {
9688 }
9690 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9691 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9692 created by virtual register instantiation, register elimination, and
9693 similar optimizations. */
9695 {
9701 }
9703 /* Canonicalize
9704 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9705 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9710 {
9711 rtx constant;
9715 {
9718 }
9720 {
9723 }
9724 else
9728 {
9734 }
9735 }
9741 {
9744 }
9747 {
9750 }
9758 {
9761 }
9767 {
9775 }
9778 {
9786 }
9787 }
9790 }
9791 \f
9792 /* Print an integer constant expression in assembler syntax. Addition
9793 and subtraction are the only arithmetic that may appear in these
9794 expressions. FILE is the stdio stream to write to, X is the rtx, and
9795 CODE is the operand print code from the output string. */
9797 static void
9799 {
9803 {
9812 else
9813 {
9816 /* Mark the decl as referenced so that cgraph will
9817 output the function. */
9821 #if TARGET_MACHO
9825 #endif
9827 }
9835 /* FALLTHRU */
9846 /* This used to output parentheses around the expression,
9847 but that does not work on the 386 (either ATT or BSD assembler). */
9853 {
9854 /* We can use %d if the number is <32 bits and positive. */
9859 else
9861 }
9862 else
9863 /* We can't handle floating point constants;
9864 PRINT_OPERAND must handle them. */
9869 /* Some assemblers need integer constants to appear first. */
9871 {
9875 }
9876 else
9877 {
9882 }
9899 {
9914 /* FIXME: This might be @TPOFF in Sun ld too. */
9923 else
9933 else
9939 #if TARGET_MACHO
9944 #endif
9948 }
9953 }
9954 }
9956 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9957 We need to emit DTP-relative relocations. */
9959 static void ATTRIBUTE_UNUSED
9961 {
9966 {
9974 }
9975 }
9977 /* Return true if X is a representation of the PIC register. This copes
9978 with calls from ix86_find_base_term, where the register might have
9979 been replaced by a cselib value. */
9981 static bool
9983 {
9987 else
9989 }
9991 /* In the name of slightly smaller debug output, and to cater to
9992 general assembler lossage, recognize PIC+GOTOFF and turn it back
9993 into a direct symbol reference.
9995 On Darwin, this is necessary to avoid a crash, because Darwin
9996 has a different PIC label for each routine but the DWARF debugging
9997 information is not associated with any particular routine, so it's
9998 necessary to remove references to the PIC label from RTL stored by
9999 the DWARF output code. */
10001 static rtx
10003 {
10005 /* reg_addend is NULL or a multiple of some register. */
10007 /* const_addend is NULL or a const_int. */
10009 /* This is the result, or NULL. */
10016 {
10023 }
10030 /* %ebx + GOT/GOTOFF */
10031 ;
10033 {
10034 /* %ebx + %reg * scale + GOT/GOTOFF */
10040 else
10046 }
10047 else
10053 {
10056 }
10075 }
10077 /* If X is a machine specific address (i.e. a symbol or label being
10078 referenced as a displacement from the GOT implemented using an
10079 UNSPEC), then return the base term. Otherwise return X. */
10081 rtx
10083 {
10084 rtx term;
10087 {
10100 }
10103 }
10104 \f
10105 static void
10108 {
10112 {
10118 }
10123 {
10126 {
10145 }
10149 {
10168 }
10175 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10176 Those same assemblers have the same but opposite lossage on cmov. */
10181 else
10186 {
10199 }
10207 {
10220 }
10223 /* ??? As above. */
10232 /* ??? As above. */
10237 else
10248 }
10250 }
10252 /* Print the name of register X to FILE based on its machine mode and number.
10253 If CODE is 'w', pretend the mode is HImode.
10254 If CODE is 'b', pretend the mode is QImode.
10255 If CODE is 'k', pretend the mode is SImode.
10256 If CODE is 'q', pretend the mode is DImode.
10257 If CODE is 'x', pretend the mode is V4SFmode.
10258 If CODE is 't', pretend the mode is V8SFmode.
10259 If CODE is 'h', pretend the reg is the 'high' byte register.
10260 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10261 If CODE is 'd', duplicate the operand for AVX instruction.
10262 */
10264 void
10266 {
10281 {
10285 }
10303 else
10306 /* Irritatingly, AMD extended registers use different naming convention
10307 from the normal registers. */
10309 {
10312 {
10331 }
10333 }
10337 {
10340 {
10343 }
10344 /* FALLTHRU */
10350 /* FALLTHRU */
10353 normal:
10368 {
10373 }
10377 }
10381 {
10384 else
10386 }
10387 }
10389 /* Locate some local-dynamic symbol still in use by this function
10390 so that we can print its name in some tls_local_dynamic_base
10391 pattern. */
10393 static int
10395 {
10400 {
10403 }
10406 }
10410 {
10411 rtx insn;
10422 }
10424 /* Meaning of CODE:
10425 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10426 C -- print opcode suffix for set/cmov insn.
10427 c -- like C, but print reversed condition
10428 E,e -- likewise, but for compare-and-branch fused insn.
10429 F,f -- likewise, but for floating-point.
10430 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10431 otherwise nothing
10432 R -- print the prefix for register names.
10433 z -- print the opcode suffix for the size of the current operand.
10434 * -- print a star (in certain assembler syntax)
10435 A -- print an absolute memory reference.
10436 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10437 s -- print a shift double count, followed by the assemblers argument
10438 delimiter.
10439 b -- print the QImode name of the register for the indicated operand.
10440 %b0 would print %al if operands[0] is reg 0.
10441 w -- likewise, print the HImode name of the register.
10442 k -- likewise, print the SImode name of the register.
10443 q -- likewise, print the DImode name of the register.
10444 x -- likewise, print the V4SFmode name of the register.
10445 t -- likewise, print the V8SFmode name of the register.
10446 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10447 y -- print "st(0)" instead of "st" as a register.
10448 d -- print duplicated register operand for AVX instruction.
10449 D -- print condition for SSE cmp instruction.
10450 P -- if PIC, print an @PLT suffix.
10451 X -- don't print any sort of PIC '@' suffix for a symbol.
10452 & -- print some in-use local-dynamic symbol name.
10453 H -- print a memory address offset by 8; used for sse high-parts
10454 Y -- print condition for SSE5 com* instruction.
10455 + -- print a branch hint as 'cs' or 'ds' prefix
10456 ; -- print a semicolon (after prefixes due to bug in older gas).
10457 */
10459 void
10461 {
10463 {
10465 {
10477 {
10483 /* Intel syntax. For absolute addresses, registers should not
10484 be surrounded by braces. */
10486 {
10491 }
10496 }
10533 /* 387 opcodes don't get size suffixes if the operands are
10534 registers. */
10538 /* Likewise if using Intel opcodes. */
10542 /* This is the size of op from size of operand. */
10544 {
10551 {
10552 #ifdef HAVE_GAS_FILDS_FISTS
10554 #endif
10556 }
10557 else
10563 {
10566 }
10567 else
10578 {
10580 {
10581 #ifdef GAS_MNEMONICS
10583 #else
10586 #endif
10587 }
10588 else
10590 }
10591 else
10597 }
10614 {
10617 }
10621 /* Little bit of braindamage here. The SSE compare instructions
10622 does use completely different names for the comparisons that the
10623 fp conditional moves. */
10625 {
10627 {
10672 }
10673 }
10674 else
10675 {
10677 {
10710 }
10711 }
10714 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10716 {
10718 {
10725 }
10727 }
10728 #endif
10734 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10737 #endif
10741 /* Like above, but reverse condition */
10743 /* Check to see if argument to %c is really a constant
10744 and not a condition code which needs to be reversed. */
10746 {
10747 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10749 }
10753 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10756 #endif
10769 /* It doesn't actually matter what mode we use here, as we're
10770 only going to use this for printing. */
10775 {
10776 rtx x;
10784 {
10789 {
10793 /* Emit hints only in the case default branch prediction
10794 heuristics would fail. */
10796 {
10797 /* We use 3e (DS) prefix for taken branches and
10798 2e (CS) prefix for not taken branches. */
10801 else
10803 }
10804 }
10805 }
10807 }
10811 {
10860 }
10864 #if TARGET_MACHO
10866 #else
10868 #endif
10873 }
10874 }
10880 {
10881 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
10884 {
10887 {
10896 else
10901 }
10903 /* Check for explicit size override (codes 'b', 'w' and 'k') */
10913 }
10916 /* Avoid (%rip) for call operands. */
10922 else
10924 }
10927 {
10928 REAL_VALUE_TYPE r;
10937 }
10939 /* These float cases don't actually occur as immediate operands. */
10941 {
10946 }
10950 {
10955 }
10957 else
10958 {
10959 /* We have patterns that allow zero sets of memory, for instance.
10960 In 64-bit mode, we should probably support all 8-byte vectors,
10961 since we can in fact encode that into an immediate. */
10963 {
10966 }
10969 {
10971 {
10974 }
10977 {
10980 else
10982 }
10983 }
10988 else
10990 }
10991 }
10992 \f
10993 /* Print a memory operand whose address is ADDR. */
10995 void
10997 {
11011 {
11022 }
11024 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11026 {
11038 }
11040 {
11041 /* Displacement only requires special attention. */
11044 {
11048 }
11051 else
11053 }
11054 else
11055 {
11057 {
11059 {
11064 else
11066 }
11072 {
11077 }
11079 }
11080 else
11081 {
11085 {
11086 /* Pull out the offset of a symbol; print any symbol itself. */
11090 {
11094 }
11102 else
11104 }
11108 {
11111 {
11115 }
11116 }
11119 else
11123 {
11128 }
11130 }
11131 }
11132 }
11134 bool
11136 {
11137 rtx op;
11144 {
11147 /* FIXME: This might be @TPOFF in Sun ld. */
11158 else
11170 else
11177 #if TARGET_MACHO
11183 #endif
11187 }
11190 }
11191 \f
11192 /* Split one or more DImode RTL references into pairs of SImode
11193 references. The RTL can be REG, offsettable MEM, integer constant, or
11194 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11195 split and "num" is its length. lo_half and hi_half are output arrays
11196 that parallel "operands". */
11198 void
11200 {
11202 {
11205 /* simplify_subreg refuse to split volatile memory addresses,
11206 but we still have to handle it. */
11208 {
11211 }
11212 else
11213 {
11220 }
11221 }
11222 }
11223 /* Split one or more TImode RTL references into pairs of DImode
11224 references. The RTL can be REG, offsettable MEM, integer constant, or
11225 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11226 split and "num" is its length. lo_half and hi_half are output arrays
11227 that parallel "operands". */
11229 void
11231 {
11233 {
11236 /* simplify_subreg refuse to split volatile memory addresses, but we
11237 still have to handle it. */
11239 {
11242 }
11243 else
11244 {
11247 }
11248 }
11249 }
11250 \f
11251 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11252 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11253 is the expression of the binary operation. The output may either be
11254 emitted here, or returned to the caller, like all output_* functions.
11256 There is no guarantee that the operands are the same mode, as they
11257 might be within FLOAT or FLOAT_EXTEND expressions. */
11259 #ifndef SYSV386_COMPAT
11260 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11261 wants to fix the assemblers because that causes incompatibility
11262 with gcc. No-one wants to fix gcc because that causes
11263 incompatibility with assemblers... You can use the option of
11264 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11265 #define SYSV386_COMPAT 1
11266 #endif
11270 {
11276 #ifdef ENABLE_CHECKING
11277 /* Even if we do not want to check the inputs, this documents input
11278 constraints. Which helps in understanding the following code. */
11288 else
11290 #endif
11293 {
11298 else
11307 else
11316 else
11325 else
11332 }
11335 {
11337 {
11341 else
11343 }
11344 else
11345 {
11349 else
11351 }
11353 }
11357 {
11361 {
11365 }
11367 /* know operands[0] == operands[1]. */
11370 {
11373 }
11376 {
11378 /* How is it that we are storing to a dead operand[2]?
11379 Well, presumably operands[1] is dead too. We can't
11380 store the result to st(0) as st(0) gets popped on this
11381 instruction. Instead store to operands[2] (which I
11382 think has to be st(1)). st(1) will be popped later.
11383 gcc <= 2.8.1 didn't have this check and generated
11384 assembly code that the Unixware assembler rejected. */
11386 else
11389 }
11393 else
11400 {
11403 }
11406 {
11409 }
11412 {
11413 #if SYSV386_COMPAT
11414 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11415 derived assemblers, confusingly reverse the direction of
11416 the operation for fsub{r} and fdiv{r} when the
11417 destination register is not st(0). The Intel assembler
11418 doesn't have this brain damage. Read !SYSV386_COMPAT to
11419 figure out what the hardware really does. */
11422 else
11424 #else
11426 /* As above for fmul/fadd, we can't store to st(0). */
11428 else
11430 #endif
11432 }
11435 {
11436 #if SYSV386_COMPAT
11439 else
11441 #else
11444 else
11446 #endif
11448 }
11451 {
11454 else
11457 }
11459 {
11460 #if SYSV386_COMPAT
11462 #else
11464 #endif
11465 }
11466 else
11467 {
11468 #if SYSV386_COMPAT
11470 #else
11472 #endif
11473 }
11478 }
11482 }
11484 /* Return needed mode for entity in optimize_mode_switching pass. */
11486 int
11488 {
11491 /* The mode UNINITIALIZED is used to store control word after a
11492 function call or ASM pattern. The mode ANY specify that function
11493 has no requirements on the control word and make no changes in the
11494 bits we are interested in. */
11508 {
11531 }
11534 }
11536 /* Output code to initialize control word copies used by trunc?f?i and
11537 rounding patterns. CURRENT_MODE is set to current control word,
11538 while NEW_MODE is set to new control word. */
11540 void
11542 {
11544 rtx new_mode;
11555 {
11557 {
11559 /* round toward zero (truncate) */
11565 /* round down toward -oo */
11572 /* round up toward +oo */
11579 /* mask precision exception for nearbyint() */
11586 }
11587 }
11588 else
11589 {
11591 {
11593 /* round toward zero (truncate) */
11599 /* round down toward -oo */
11605 /* round up toward +oo */
11611 /* mask precision exception for nearbyint() */
11618 }
11619 }
11625 }
11627 /* Output code for INSN to convert a float to a signed int. OPERANDS
11628 are the insn operands. The output may be [HSD]Imode and the input
11629 operand may be [SDX]Fmode. */
11633 {
11638 /* Jump through a hoop or two for DImode, since the hardware has no
11639 non-popping instruction. We used to do this a different way, but
11640 that was somewhat fragile and broke with post-reload splitters. */
11650 else
11651 {
11656 else
11660 }
11663 }
11665 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11666 have the values zero or one, indicates the ffreep insn's operand
11667 from the OPERANDS array. */
11671 {
11673 #if HAVE_AS_IX86_FFREEP
11675 #else
11676 {
11684 }
11685 #endif
11688 }
11691 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11692 should be used. UNORDERED_P is true when fucom should be used. */
11696 {
11702 {
11705 }
11706 else
11707 {
11710 }
11713 {
11722 else
11724 else
11727 else
11729 }
11736 {
11738 {
11741 }
11742 else
11744 }
11747 && stack_top_dies
11750 {
11751 /* If both the top of the 387 stack dies, and the other operand
11752 is also a stack register that dies, then this must be a
11753 `fcompp' float compare */
11756 {
11757 /* There is no double popping fcomi variant. Fortunately,
11758 eflags is immune from the fstp's cc clobbering. */
11761 else
11764 }
11765 else
11766 {
11769 else
11771 }
11772 }
11773 else
11774 {
11775 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11778 {
11786 NULL,
11787 NULL,
11794 NULL,
11795 NULL,
11796 NULL,
11797 NULL
11798 };
11813 }
11814 }
11816 void
11818 {
11821 #ifdef ASM_QUAD
11824 #else
11826 #endif
11829 }
11831 void
11833 {
11836 #ifdef ASM_QUAD
11839 #else
11841 #endif
11842 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
11848 #if TARGET_MACHO
11850 {
11854 }
11855 #endif
11856 else
11859 }
11860 \f
11861 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
11862 for the target. */
11864 void
11866 {
11867 rtx tmp;
11869 /* We play register width games, which are only valid after reload. */
11872 /* Avoid HImode and its attendant prefix byte. */
11877 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
11879 {
11882 }
11885 }
11887 /* X is an unchanging MEM. If it is a constant pool reference, return
11888 the constant pool rtx, else NULL. */
11890 rtx
11892 {
11899 }
11901 void
11903 {
11911 {
11914 {
11919 }
11923 }
11927 {
11940 {
11946 }
11947 }
11950 {
11952 {
11953 #if TARGET_MACHO
11955 {
11956 rtx temp = ((reload_in_progress
11963 }
11968 #endif
11969 }
11970 else
11971 {
11975 {
11980 }
11981 }
11982 }
11983 else
11984 {
11995 /* Force large constants in 64bit compilation into register
11996 to get them CSEed. */
12008 {
12009 /* If we are loading a floating point constant to a register,
12010 force the value to memory now, since we'll get better code
12011 out the back end. */
12015 {
12020 }
12021 }
12022 }
12025 }
12027 void
12029 {
12033 /* Force constants other than zero into memory. We do not know how
12034 the instructions used to build constants modify the upper 64 bits
12035 of the register, once we have that information we may be able
12036 to handle some of them more efficiently. */
12045 /* We need to check memory alignment for SSE mode since attribute
12046 can make operands unaligned. */
12051 {
12054 /* ix86_expand_vector_move_misalign() does not like constants ... */
12060 /* ... nor both arguments in memory. */
12068 }
12070 /* Make operand1 a register if it isn't already. */
12074 {
12077 }
12080 }
12082 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12083 straight to ix86_expand_vector_move. */
12084 /* Code generation for scalar reg-reg moves of single and double precision data:
12085 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12086 movaps reg, reg
12087 else
12088 movss reg, reg
12089 if (x86_sse_partial_reg_dependency == true)
12090 movapd reg, reg
12091 else
12092 movsd reg, reg
12094 Code generation for scalar loads of double precision data:
12095 if (x86_sse_split_regs == true)
12096 movlpd mem, reg (gas syntax)
12097 else
12098 movsd mem, reg
12100 Code generation for unaligned packed loads of single precision data
12101 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12102 if (x86_sse_unaligned_move_optimal)
12103 movups mem, reg
12105 if (x86_sse_partial_reg_dependency == true)
12106 {
12107 xorps reg, reg
12108 movlps mem, reg
12109 movhps mem+8, reg
12110 }
12111 else
12112 {
12113 movlps mem, reg
12114 movhps mem+8, reg
12115 }
12117 Code generation for unaligned packed loads of double precision data
12118 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12119 if (x86_sse_unaligned_move_optimal)
12120 movupd mem, reg
12122 if (x86_sse_split_regs == true)
12123 {
12124 movlpd mem, reg
12125 movhpd mem+8, reg
12126 }
12127 else
12128 {
12129 movsd mem, reg
12130 movhpd mem+8, reg
12131 }
12132 */
12134 void
12136 {
12143 {
12145 {
12149 {
12162 }
12169 {
12184 }
12189 }
12192 }
12195 {
12196 /* If we're optimizing for size, movups is the smallest. */
12198 {
12203 }
12205 /* ??? If we have typed data, then it would appear that using
12206 movdqu is the only way to get unaligned data loaded with
12207 integer type. */
12209 {
12214 }
12217 {
12218 rtx zero;
12221 {
12226 }
12228 /* When SSE registers are split into halves, we can avoid
12229 writing to the top half twice. */
12231 {
12234 }
12235 else
12236 {
12237 /* ??? Not sure about the best option for the Intel chips.
12238 The following would seem to satisfy; the register is
12239 entirely cleared, breaking the dependency chain. We
12240 then store to the upper half, with a dependency depth
12241 of one. A rumor has it that Intel recommends two movsd
12242 followed by an unpacklpd, but this is unconfirmed. And
12243 given that the dependency depth of the unpacklpd would
12244 still be one, I'm not sure why this would be better. */
12246 }
12252 }
12253 else
12254 {
12256 {
12261 }
12265 else
12274 }
12275 }
12277 {
12278 /* If we're optimizing for size, movups is the smallest. */
12280 {
12285 }
12287 /* ??? Similar to above, only less clear because of quote
12288 typeless stores unquote. */
12291 {
12296 }
12299 {
12304 }
12305 else
12306 {
12313 }
12314 }
12315 else
12317 }
12319 /* Expand a push in MODE. This is some mode for which we do not support
12320 proper push instructions, at least from the registers that we expect
12321 the value to live in. */
12323 void
12325 {
12326 rtx tmp;
12336 }
12338 /* Helper function of ix86_fixup_binary_operands to canonicalize
12339 operand order. Returns true if the operands should be swapped. */
12341 static bool
12343 rtx operands[])
12344 {
12349 /* If the operation is not commutative, we can't do anything. */
12353 /* Highest priority is that src1 should match dst. */
12359 /* Next highest priority is that immediate constants come second. */
12365 /* Lowest priority is that memory references should come second. */
12372 }
12375 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12376 destination to use for the operation. If different from the true
12377 destination in operands[0], a copy operation will be required. */
12379 rtx
12381 rtx operands[])
12382 {
12387 /* Canonicalize operand order. */
12389 {
12390 rtx temp;
12392 /* It is invalid to swap operands of different modes. */
12398 }
12400 /* Both source operands cannot be in memory. */
12402 {
12403 /* Optimization: Only read from memory once. */
12405 {
12408 }
12409 else
12411 }
12413 /* If the destination is memory, and we do not have matching source
12414 operands, do things in registers. */
12418 /* Source 1 cannot be a constant. */
12422 /* Source 1 cannot be a non-matching memory. */
12429 }
12431 /* Similarly, but assume that the destination has already been
12432 set up properly. */
12434 void
12437 {
12440 }
12442 /* Attempt to expand a binary operator. Make the expansion closer to the
12443 actual machine, then just general_operand, which will allow 3 separate
12444 memory references (one output, two input) in a single insn. */
12446 void
12448 rtx operands[])
12449 {
12456 /* Emit the instruction. */
12460 {
12461 /* Reload doesn't know about the flags register, and doesn't know that
12462 it doesn't want to clobber it. We can only do this with PLUS. */
12465 }
12466 else
12467 {
12470 }
12472 /* Fix up the destination if needed. */
12475 }
12477 /* Return TRUE or FALSE depending on whether the binary operator meets the
12478 appropriate constraints. */
12480 int
12483 {
12488 /* Both source operands cannot be in memory. */
12492 /* Canonicalize operand order for commutative operators. */
12494 {
12498 }
12500 /* If the destination is memory, we must have a matching source operand. */
12504 /* Source 1 cannot be a constant. */
12508 /* Source 1 cannot be a non-matching memory. */
12513 }
12515 /* Attempt to expand a unary operator. Make the expansion closer to the
12516 actual machine, then just general_operand, which will allow 2 separate
12517 memory references (one output, one input) in a single insn. */
12519 void
12521 rtx operands[])
12522 {
12529 /* If the destination is memory, and we do not have matching source
12530 operands, do things in registers. */
12533 {
12536 else
12538 }
12540 /* When source operand is memory, destination must match. */
12544 /* Emit the instruction. */
12548 {
12549 /* Reload doesn't know about the flags register, and doesn't know that
12550 it doesn't want to clobber it. */
12553 }
12554 else
12555 {
12558 }
12560 /* Fix up the destination if needed. */
12563 }
12565 /* Return TRUE or FALSE depending on whether the unary operator meets the
12566 appropriate constraints. */
12568 int
12572 {
12573 /* If one of operands is memory, source and destination must match. */
12579 }
12581 /* Post-reload splitter for converting an SF or DFmode value in an
12582 SSE register into an unsigned SImode. */
12584 void
12586 {
12597 /* Load up the value into the low element. We must ensure that the other
12598 elements are valid floats -- zero is the easiest such value. */
12600 {
12603 else
12605 }
12606 else
12607 {
12612 else
12614 }
12634 else
12639 }
12641 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12642 Expects the 64-bit DImode to be supplied in a pair of integral
12643 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12644 -mfpmath=sse, !optimize_size only. */
12646 void
12648 {
12652 rtx x;
12658 {
12661 }
12662 else
12663 {
12667 }
12675 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12678 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12679 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12680 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12681 (0x1.0p84 + double(fp_value_hi_xmm)).
12682 Note these exponents differ by 32. */
12686 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12687 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12696 /* Add the upper and lower DFmode values together. */
12699 else
12700 {
12704 }
12707 }
12709 /* Not used, but eases macroization of patterns. */
12710 void
12712 rtx input ATTRIBUTE_UNUSED)
12713 {
12715 }
12717 /* Convert an unsigned SImode value into a DFmode. Only currently used
12718 for SSE, but applicable anywhere. */
12720 void
12722 {
12723 REAL_VALUE_TYPE TWO31r;
12738 }
12740 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12741 32-bit mode; otherwise we have a direct convert instruction. */
12743 void
12745 {
12746 REAL_VALUE_TYPE TWO32r;
12764 }
12766 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12767 For x86_32, -mfpmath=sse, !optimize_size only. */
12768 void
12770 {
12771 REAL_VALUE_TYPE ONE16r;
12790 }
12792 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12793 then replicate the value for all elements of the vector
12794 register. */
12796 rtx
12798 {
12799 rtvec v;
12801 {
12815 else
12823 else
12829 }
12830 }
12832 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12833 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
12834 for an SSE register. If VECT is true, then replicate the mask for
12835 all elements of the vector register. If INVERT is true, then create
12836 a mask excluding the sign bit. */
12838 rtx
12840 {
12844 rtx v;
12845 rtx mask;
12847 /* Find the sign bit, sign extended to 2*HWI. */
12849 {
12863 else
12871 {
12874 }
12875 else
12876 {
12877 rtvec vec;
12883 {
12886 }
12887 else
12897 }
12902 }
12907 /* Force this value into the low part of a fp vector constant. */
12916 }
12918 /* Generate code for floating point ABS or NEG. */
12920 void
12922 rtx operands[])
12923 {
12930 {
12933 }
12939 /* NEG and ABS performed with SSE use bitwise mask operations.
12940 Create the appropriate mask now. */
12943 else
12950 {
12954 }
12955 else
12956 {
12960 {
12965 }
12966 else
12968 }
12969 }
12971 /* Expand a copysign operation. Special case operand 0 being a constant. */
12973 void
12975 {
12986 {
12993 {
13000 else
13001 {
13002 rtvec v;
13007 else
13011 }
13012 }
13022 else
13026 }
13027 else
13028 {
13038 else
13042 }
13043 }
13045 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13046 be a constant, and so has already been expanded into a vector constant. */
13048 void
13050 {
13067 {
13070 }
13071 }
13073 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13074 so we have to do two masks. */
13076 void
13078 {
13093 {
13094 /* Shouldn't happen often (it's useless, obviously), but when it does
13095 we'd generate incorrect code if we continue below. */
13098 }
13101 {
13112 }
13113 else
13114 {
13116 {
13118 }
13120 {
13124 }
13128 {
13131 }
13133 {
13138 }
13140 }
13144 }
13146 /* Return TRUE or FALSE depending on whether the first SET in INSN
13147 has source and destination with matching CC modes, and that the
13148 CC mode is at least as constrained as REQ_MODE. */
13150 int
13152 {
13153 rtx set;
13164 {
13174 /* FALLTHRU */
13178 /* FALLTHRU */
13182 /* FALLTHRU */
13192 }
13195 }
13197 /* Generate insn patterns to do an integer compare of OPERANDS. */
13199 static rtx
13201 {
13208 /* This is very simple, but making the interface the same as in the
13209 FP case makes the rest of the code easier. */
13213 /* Return the test that should be put into the flags user, i.e.
13214 the bcc, scc, or cmov instruction. */
13216 }
13218 /* Figure out whether to use ordered or unordered fp comparisons.
13219 Return the appropriate mode to use. */
13221 enum machine_mode
13223 {
13224 /* ??? In order to make all comparisons reversible, we do all comparisons
13225 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13226 all forms trapping and nontrapping comparisons, we can make inequality
13227 comparisons trapping again, since it results in better code when using
13228 FCOM based compares. */
13230 }
13232 enum machine_mode
13234 {
13238 {
13241 }
13244 {
13245 /* Only zero flag is needed. */
13249 /* Codes needing carry flag. */
13252 /* Detect overflow checks. They need just the carry flag. */
13256 else
13260 /* Detect overflow checks. They need just the carry flag. */
13264 else
13266 /* Codes possibly doable only with sign flag when
13267 comparing against zero. */
13272 else
13273 /* For other cases Carry flag is not required. */
13275 /* Codes doable only with sign flag when comparing
13276 against zero, but we miss jump instruction for it
13277 so we need to use relational tests against overflow
13278 that thus needs to be zero. */
13283 else
13285 /* strcmp pattern do (use flags) and combine may ask us for proper
13286 mode. */
13291 }
13292 }
13294 /* Return the fixed registers used for condition codes. */
13296 static bool
13298 {
13302 }
13304 /* If two condition code modes are compatible, return a condition code
13305 mode which is compatible with both. Otherwise, return
13306 VOIDmode. */
13308 static enum machine_mode
13310 {
13322 {
13336 {
13350 }
13354 /* These are only compatible with themselves, which we already
13355 checked above. */
13357 }
13358 }
13360 /* Split comparison code CODE into comparisons we can do using branch
13361 instructions. BYPASS_CODE is comparison code for branch that will
13362 branch around FIRST_CODE and SECOND_CODE. If some of branches
13363 is not required, set value to UNKNOWN.
13364 We never require more than two branches. */
13366 void
13370 {
13375 /* The fcomi comparison sets flags as follows:
13377 cmp ZF PF CF
13378 > 0 0 0
13379 < 0 0 1
13380 = 1 0 0
13381 un 1 1 1 */
13384 {
13420 }
13422 {
13425 }
13426 }
13428 /* Return cost of comparison done fcom + arithmetics operations on AX.
13429 All following functions do use number of instructions as a cost metrics.
13430 In future this should be tweaked to compute bytes for optimize_size and
13431 take into account performance of various instructions on various CPUs. */
13432 static int
13434 {
13437 /* The cost of code output by ix86_expand_fp_compare. */
13439 {
13462 }
13463 }
13465 /* Return cost of comparison done using fcomi operation.
13466 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13467 static int
13469 {
13471 /* Return arbitrarily high cost when instruction is not supported - this
13472 prevents gcc from using it. */
13477 }
13479 /* Return cost of comparison done using sahf operation.
13480 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13481 static int
13483 {
13485 /* Return arbitrarily high cost when instruction is not preferred - this
13486 avoids gcc from using it. */
13491 }
13493 /* Compute cost of the comparison done using any method.
13494 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13495 static int
13497 {
13510 }
13512 /* Return true if we should use an FCOMI instruction for this
13513 fp comparison. */
13515 int
13517 {
13524 }
13526 /* Swap, force into registers, or otherwise massage the two operands
13527 to a fp comparison. The operands are updated in place; the new
13528 comparison code is returned. */
13530 static enum rtx_code
13532 {
13538 /* All of the unordered compare instructions only work on registers.
13539 The same is true of the fcomi compare instructions. The XFmode
13540 compare instructions require registers except when comparing
13541 against zero or when converting operand 1 from fixed point to
13542 floating point. */
13551 {
13554 }
13555 else
13556 {
13557 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13558 things around if they appear profitable, otherwise force op0
13559 into a register. */
13565 {
13566 rtx tmp;
13569 }
13575 {
13580 {
13583 }
13584 else
13586 }
13587 }
13589 /* Try to rearrange the comparison to make it cheaper. */
13593 {
13594 rtx tmp;
13599 }
13604 }
13606 /* Convert comparison codes we use to represent FP comparison to integer
13607 code that will result in proper branch. Return UNKNOWN if no such code
13608 is available. */
13610 enum rtx_code
13612 {
13614 {
13637 }
13638 }
13640 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13642 static rtx
13645 {
13661 /* Do fcomi/sahf based test when profitable. */
13665 {
13668 tmp);
13671 else
13672 {
13680 }
13682 /* The FP codes work out to act like unsigned. */
13688 const0_rtx);
13692 const0_rtx);
13693 }
13694 else
13695 {
13696 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13703 /* In the unordered case, we have to check C2 for NaN's, which
13704 doesn't happen to work out to anything nice combination-wise.
13705 So do some bit twiddling on the value we've got in AH to come
13706 up with an appropriate set of condition codes. */
13710 {
13714 {
13717 }
13718 else
13719 {
13725 }
13730 {
13735 }
13736 else
13737 {
13740 }
13745 {
13748 }
13749 else
13750 {
13755 }
13760 {
13766 }
13767 else
13768 {
13771 }
13776 {
13781 }
13782 else
13783 {
13787 }
13792 {
13797 }
13798 else
13799 {
13802 }
13816 }
13817 }
13819 /* Return the test that should be put into the flags user, i.e.
13820 the bcc, scc, or cmov instruction. */
13823 const0_rtx);
13824 }
13826 rtx
13828 {
13839 {
13842 }
13844 {
13848 }
13849 else
13853 }
13855 /* Return true if the CODE will result in nontrivial jump sequence. */
13856 bool
13858 {
13864 }
13866 void
13868 {
13869 rtx tmp;
13871 /* If we have emitted a compare insn, go straight to simple.
13872 ix86_expand_compare won't emit anything if ix86_compare_emitted
13873 is non NULL. */
13878 {
13882 simple:
13886 pc_rtx);
13893 {
13894 rtvec vec;
13903 /* Check whether we will use the natural sequence with one jump. If
13904 so, we can expand jump early. Otherwise delay expansion by
13905 creating compound insn to not confuse optimizers. */
13907 {
13911 }
13912 else
13913 {
13918 pc_rtx);
13933 }
13935 }
13941 /* Expand DImode branch into multiple compare+branch. */
13942 {
13948 {
13953 }
13955 {
13959 }
13960 else
13961 {
13965 }
13967 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
13968 avoid two branches. This costs one extra insn, so disable when
13969 optimizing for size. */
13974 {
13994 }
13996 /* Otherwise, if we are doing less-than or greater-or-equal-than,
13997 op1 is a constant and the low word is zero, then we can just
13998 examine the high word. Similarly for low word -1 and
13999 less-or-equal-than or greater-than. */
14003 {
14006 {
14011 }
14015 {
14020 }
14024 }
14026 /* Otherwise, we need two or three jumps. */
14035 {
14049 }
14051 /*
14052 * a < b =>
14053 * if (hi(a) < hi(b)) goto true;
14054 * if (hi(a) > hi(b)) goto false;
14055 * if (lo(a) < lo(b)) goto true;
14056 * false:
14057 */
14074 }
14078 }
14079 }
14081 /* Split branch based on floating point condition. */
14082 void
14085 {
14088 rtx condition;
14090 rtx i;
14093 {
14098 }
14103 /* Remove pushed operand from stack. */
14108 {
14109 /* Distribute the probabilities across the jumps.
14110 Assume the BYPASS and SECOND to be always test
14111 for UNORDERED. */
14114 /* Value of 1 is low enough to make no need for probability
14115 to be updated. Later we may run some experiments and see
14116 if unordered values are more frequent in practice. */
14121 }
14123 {
14128 bypass,
14130 label),
14131 pc_rtx)));
14137 }
14148 {
14152 target2)));
14158 }
14161 }
14163 int
14165 {
14182 {
14187 {
14192 }
14198 else
14200 }
14202 /* Attach a REG_EQUAL note describing the comparison result. */
14204 {
14209 }
14212 }
14214 /* Expand comparison setting or clearing carry flag. Return true when
14215 successful and set pop for the operation. */
14216 static bool
14218 {
14222 /* Do not handle DImode compares that go through special path. */
14227 {
14233 /* Shortcut: following common codes never translate
14234 into carry flag compares. */
14239 /* These comparisons require zero flag; swap operands so they won't. */
14242 {
14247 }
14249 /* Try to expand the comparison and verify that we end up with
14250 carry flag based comparison. This fails to be true only when
14251 we decide to expand comparison using arithmetic that is not
14252 too common scenario. */
14265 else
14274 }
14280 {
14285 /* Convert a==0 into (unsigned)a<1. */
14294 /* Convert a>b into b<a or a>=b-1. */
14298 {
14300 /* Bail out on overflow. We still can swap operands but that
14301 would force loading of the constant into register. */
14306 }
14307 else
14308 {
14313 }
14316 /* Convert a>=0 into (unsigned)a<0x80000000. */
14334 }
14335 /* Swapping operands may cause constant to appear as first operand. */
14337 {
14341 }
14347 }
14349 int
14351 {
14369 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14370 HImode insns, we'd be swallowed in word prefix ops. */
14376 {
14380 HOST_WIDE_INT diff;
14383 /* Sign bit compares are better done using shifts than we do by using
14384 sbb. */
14388 {
14389 /* Detect overlap between destination and compare sources. */
14393 {
14400 {
14403 }
14405 /* To simplify rest of code, restrict to the GEU case. */
14407 {
14413 }
14414 else
14415 {
14418 reverse_condition_maybe_unordered
14420 else
14422 }
14431 else
14433 }
14434 else
14435 {
14438 else
14439 {
14444 }
14447 }
14450 {
14451 /*
14452 * cmpl op0,op1
14453 * sbbl dest,dest
14454 * [addl dest, ct]
14455 *
14456 * Size 5 - 8.
14457 */
14462 }
14464 {
14465 /*
14466 * cmpl op0,op1
14467 * sbbl dest,dest
14468 * orl $ct, dest
14469 *
14470 * Size 8.
14471 */
14475 }
14477 {
14478 /*
14479 * cmpl op0,op1
14480 * sbbl dest,dest
14481 * notl dest
14482 * [addl dest, cf]
14483 *
14484 * Size 8 - 11.
14485 */
14491 }
14492 else
14493 {
14494 /*
14495 * cmpl op0,op1
14496 * sbbl dest,dest
14497 * [notl dest]
14498 * andl cf - ct, dest
14499 * [addl dest, ct]
14500 *
14501 * Size 8 - 11.
14502 */
14505 {
14509 }
14519 }
14525 }
14528 {
14531 HOST_WIDE_INT tmp;
14536 {
14539 /* We may be reversing unordered compare to normal compare, that
14540 is not valid in general (we may convert non-trapping condition
14541 to trapping one), however on i386 we currently emit all
14542 comparisons unordered. */
14545 }
14546 else
14547 {
14550 }
14551 }
14556 {
14561 {
14566 }
14567 }
14569 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14573 {
14574 /* If lea code below could be used, only optimize
14575 if it results in a 2 insn sequence. */
14581 {
14582 /*
14583 * notl op1 (if necessary)
14584 * sarl $31, op1
14585 * orl cf, op1
14586 */
14588 {
14592 }
14604 }
14605 }
14613 {
14614 /*
14615 * xorl dest,dest
14616 * cmpl op1,op2
14617 * setcc dest
14618 * lea cf(dest*(ct-cf)),dest
14619 *
14620 * Size 14.
14621 *
14622 * This also catches the degenerate setcc-only case.
14623 */
14625 rtx tmp;
14632 /* On x86_64 the lea instruction operates on Pmode, so we need
14633 to get arithmetics done in proper mode to match. */
14636 else
14637 {
14638 rtx out1;
14641 nops++;
14643 {
14645 nops++;
14646 }
14647 }
14649 {
14651 nops++;
14652 }
14654 {
14657 else
14659 }
14664 }
14666 /*
14667 * General case: Jumpful:
14668 * xorl dest,dest cmpl op1, op2
14669 * cmpl op1, op2 movl ct, dest
14670 * setcc dest jcc 1f
14671 * decl dest movl cf, dest
14672 * andl (cf-ct),dest 1:
14673 * addl ct,dest
14674 *
14675 * Size 20. Size 14.
14676 *
14677 * This is reasonably steep, but branch mispredict costs are
14678 * high on modern cpus, so consider failing only if optimizing
14679 * for space.
14680 */
14685 {
14687 {
14694 {
14697 /* We may be reversing unordered compare to normal compare,
14698 that is not valid in general (we may convert non-trapping
14699 condition to trapping one), however on i386 we currently
14700 emit all comparisons unordered. */
14702 }
14703 else
14704 {
14708 }
14709 }
14712 {
14713 /* notl op1 (if needed)
14714 sarl $31, op1
14715 andl (cf-ct), op1
14716 addl ct, op1
14718 For x < 0 (resp. x <= -1) there will be no notl,
14719 so if possible swap the constants to get rid of the
14720 complement.
14721 True/false will be -1/0 while code below (store flag
14722 followed by decrement) is 0/-1, so the constants need
14723 to be exchanged once more. */
14726 {
14729 }
14730 else
14731 {
14735 }
14739 }
14740 else
14741 {
14747 }
14759 }
14760 }
14763 {
14764 /* Try a few things more with specific constants and a variable. */
14766 optab op;
14772 /* If one of the two operands is an interesting constant, load a
14773 constant with the above and mask it in with a logical operation. */
14776 {
14782 else
14784 }
14786 {
14792 else
14794 }
14795 else
14802 /* Recurse to get the constant loaded. */
14806 /* Mask in the interesting variable. */
14808 OPTAB_WIDEN);
14813 }
14815 /*
14816 * For comparison with above,
14817 *
14818 * movl cf,dest
14819 * movl ct,tmp
14820 * cmpl op1,op2
14821 * cmovcc tmp,dest
14822 *
14823 * Size 15.
14824 */
14832 {
14836 }
14838 {
14842 }
14861 bypass_test,
14867 second_test,
14872 }
14874 /* Swap, force into registers, or otherwise massage the two operands
14875 to an sse comparison with a mask result. Thus we differ a bit from
14876 ix86_prepare_fp_compare_args which expects to produce a flags result.
14878 The DEST operand exists to help determine whether to commute commutative
14879 operators. The POP0/POP1 operands are updated in place. The new
14880 comparison code is returned, or UNKNOWN if not implementable. */
14882 static enum rtx_code
14885 {
14886 rtx tmp;
14889 {
14892 /* We have no LTGT as an operator. We could implement it with
14893 NE & ORDERED, but this requires an extra temporary. It's
14894 not clear that it's worth it. */
14901 /* These are supported directly. */
14908 /* For commutative operators, try to canonicalize the destination
14909 operand to be first in the comparison - this helps reload to
14910 avoid extra moves. */
14913 /* FALLTHRU */
14919 /* These are not supported directly. Swap the comparison operands
14920 to transform into something that is supported. */
14929 }
14932 }
14934 /* Detect conditional moves that exactly match min/max operational
14935 semantics. Note that this is IEEE safe, as long as we don't
14936 interchange the operands.
14938 Returns FALSE if this conditional move doesn't match a MIN/MAX,
14939 and TRUE if the operation is successful and instructions are emitted. */
14941 static bool
14944 {
14947 rtx tmp;
14950 ;
14952 {
14956 }
14957 else
14964 else
14969 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
14970 but MODE may be a vector mode and thus not appropriate. */
14972 {
14974 rtvec v;
14979 }
14980 else
14981 {
14984 }
14988 }
14990 /* Expand an sse vector comparison. Return the register with the result. */
14992 static rtx
14995 {
14997 rtx x;
15012 }
15014 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15015 operations. This is used for both scalar and vector conditional moves. */
15017 static void
15019 {
15024 {
15028 }
15030 {
15035 }
15037 {
15040 op_true,
15041 op_false));
15043 }
15044 else
15045 {
15052 else
15064 }
15065 }
15067 /* Expand a floating-point conditional move. Return true if successful. */
15069 int
15071 {
15077 {
15080 /* Since we've no cmove for sse registers, don't force bad register
15081 allocation just to gain access to it. Deny movcc when the
15082 comparison mode doesn't match the move mode. */
15104 }
15106 /* The floating point conditional move instructions don't directly
15107 support conditions resulting from a signed integer comparison. */
15111 /* The floating point conditional move instructions don't directly
15112 support signed integer comparisons. */
15115 {
15123 }
15125 {
15129 }
15131 {
15135 }
15150 }
15152 /* Expand a floating-point vector conditional move; a vcond operation
15153 rather than a movcc operation. */
15155 bool
15157 {
15159 rtx cmp;
15174 }
15176 /* Expand a signed/unsigned integral vector conditional move. */
15178 bool
15180 {
15189 /* SSE5 supports all of the comparisons on all vector int types. */
15191 {
15192 /* Canonicalize the comparison to EQ, GT, GTU. */
15194 {
15211 /* FALLTHRU */
15221 }
15223 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15225 {
15227 {
15229 /* SSE4.1 supports EQ. */
15236 /* SSE4.2 supports GT/GTU. */
15243 }
15244 }
15246 /* Unsigned parallel compare is not supported by the hardware. Play some
15247 tricks to turn this into a signed comparison against 0. */
15249 {
15253 {
15256 {
15259 /* Perform a parallel modulo subtraction. */
15262 ? gen_subv4si3
15265 /* Extract the original sign bit of op0. */
15270 ? gen_andv4si3
15273 /* XOR it back into the result of the subtraction. This results
15274 in the sign bit set iff we saw unsigned underflow. */
15277 ? gen_xorv4si3
15281 }
15286 /* Perform a parallel unsigned saturating subtraction. */
15297 }
15301 }
15302 }
15310 }
15312 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15313 true if we should do zero extension, else sign extension. HIGH_P is
15314 true if we want the N/2 high elements, else the low elements. */
15316 void
15318 {
15324 {
15328 else
15334 else
15340 else
15345 }
15351 else
15356 }
15358 /* This function performs the same task as ix86_expand_sse_unpack,
15359 but with SSE4.1 instructions. */
15361 void
15363 {
15369 {
15373 else
15379 else
15385 else
15390 }
15394 {
15395 /* Shift higher 8 bytes to lower 8 bytes. */
15400 }
15401 else
15405 }
15407 /* This function performs the same task as ix86_expand_sse_unpack,
15408 but with sse5 instructions. */
15410 void
15412 {
15420 rtvec vs;
15425 {
15430 {
15433 ? PPERM_ZERO
15435 }
15447 else
15455 {
15457 ? PPERM_ZERO
15463 }
15475 else
15483 {
15485 ? PPERM_ZERO
15495 }
15507 else
15513 }
15516 }
15518 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15519 next narrower integer vector type */
15520 void
15522 {
15527 rtx x;
15533 {
15536 {
15539 }
15550 {
15555 }
15566 {
15575 }
15586 }
15589 }
15591 /* Expand conditional increment or decrement using adb/sbb instructions.
15592 The default case using setcc followed by the conditional move can be
15593 done by generic code. */
15594 int
15596 {
15598 rtx compare_op;
15613 {
15616 }
15619 {
15623 reverse_condition_maybe_unordered
15625 else
15627 }
15630 /* Construct either adc or sbb insn. */
15632 {
15634 {
15649 }
15650 }
15651 else
15652 {
15654 {
15669 }
15670 }
15672 }
15675 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15676 works for floating pointer parameters and nonoffsetable memories.
15677 For pushes, it returns just stack offsets; the values will be saved
15678 in the right order. Maximally three parts are generated. */
15680 static int
15682 {
15687 else
15693 /* Optimize constant pool reference to immediates. This is used by fp
15694 moves, that force all constants to memory to allow combining. */
15696 {
15700 }
15703 {
15704 /* The only non-offsetable memories we handle are pushes. */
15713 }
15716 {
15718 /* Caution: if we looked through a constant pool memory above,
15719 the operand may actually have a different mode now. That's
15720 ok, since we want to pun this all the way back to an integer. */
15724 }
15727 {
15730 else
15731 {
15735 {
15739 }
15741 {
15746 }
15748 {
15749 REAL_VALUE_TYPE r;
15754 {
15769 }
15772 }
15773 else
15775 }
15776 }
15777 else
15778 {
15782 {
15785 {
15789 }
15791 {
15795 }
15797 {
15798 REAL_VALUE_TYPE r;
15804 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15807 = gen_int_mode
15810 DImode);
15811 else
15818 = gen_int_mode
15821 DImode);
15822 else
15824 }
15825 else
15827 }
15828 }
15831 }
15833 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
15834 Return false when normal moves are needed; true when all required
15835 insns have been emitted. Operands 2-4 contain the input values
15836 int the correct order; operands 5-7 contain the output values. */
15838 void
15840 {
15848 /* The DFmode expanders may ask us to move double.
15849 For 64bit target this is single move. By hiding the fact
15850 here we simplify i386.md splitters. */
15852 {
15853 /* Optimize constant pool reference to immediates. This is used by
15854 fp moves, that force all constants to memory to allow combining. */
15861 {
15864 }
15865 else
15870 }
15872 /* The only non-offsettable memory we handle is push. */
15875 else
15882 /* When emitting push, take care for source operands on the stack. */
15890 /* We need to do copy in the right order in case an address register
15891 of the source overlaps the destination. */
15893 {
15894 rtx tmp;
15897 {
15901 collisions++;
15902 }
15904 /* Collision in the middle part can be handled by reordering. */
15906 {
15909 }
15913 {
15915 {
15918 }
15919 else
15920 {
15923 }
15924 }
15926 /* If there are more collisions, we can't handle it by reordering.
15927 Do an lea to the last part and use only one colliding move. */
15929 {
15930 rtx base;
15936 /* Handle the case when the last part isn't valid for lea.
15937 Happens in 64-bit mode storing the 12-byte XFmode. */
15944 {
15947 }
15948 }
15949 }
15952 {
15954 {
15956 {
15960 }
15962 {
15965 }
15966 }
15967 else
15968 {
15969 /* In 64bit mode we don't have 32bit push available. In case this is
15970 register, it is OK - we will just use larger counterpart. We also
15971 retype memory - these comes from attempt to avoid REX prefix on
15972 moving of second half of TFmode value. */
15974 {
15976 {
15987 }
15991 }
15992 }
15996 }
15998 /* Choose correct order to not overwrite the source before it is copied. */
16008 {
16010 {
16013 }
16014 }
16015 else
16016 {
16018 {
16021 }
16022 }
16024 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16026 {
16035 }
16041 }
16043 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16044 left shift by a constant, either using a single shift or
16045 a sequence of add instructions. */
16047 static void
16049 {
16051 {
16053 ? gen_addsi3
16055 }
16058 {
16061 {
16063 ? gen_addsi3
16065 }
16066 }
16067 else
16069 ? gen_ashlsi3
16071 }
16073 void
16075 {
16081 {
16086 {
16092 }
16093 else
16094 {
16098 ? gen_x86_shld
16101 }
16103 }
16108 {
16109 /* Assuming we've chosen a QImode capable registers, then 1 << N
16110 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16112 {
16128 }
16130 /* Otherwise, we can get the same results by manually performing
16131 a bit extract operation on bit 5/6, and then performing the two
16132 shifts. The two methods of getting 0/1 into low/high are exactly
16133 the same size. Avoiding the shift in the bit extract case helps
16134 pentium4 a bit; no one else seems to care much either way. */
16135 else
16136 {
16137 rtx x;
16141 else
16146 ? gen_lshrsi3
16149 ? gen_andsi3
16153 ? gen_xorsi3
16155 }
16158 ? gen_ashlsi3
16161 ? gen_ashlsi3
16164 }
16167 {
16168 /* For -1 << N, we can avoid the shld instruction, because we
16169 know that we're shifting 0...31/63 ones into a -1. */
16173 else
16175 }
16176 else
16177 {
16183 ? gen_x86_shld
16185 }
16190 {
16193 ? gen_x86_shift_adj_1
16195 scratch));
16196 }
16197 else
16199 ? gen_x86_shift_adj_2
16201 }
16203 void
16205 {
16211 {
16216 {
16219 ? gen_ashrsi3
16224 }
16226 {
16230 ? gen_ashrsi3
16235 ? gen_ashrsi3
16238 }
16239 else
16240 {
16244 ? gen_x86_shrd
16247 ? gen_ashrsi3
16249 }
16250 }
16251 else
16252 {
16259 ? gen_x86_shrd
16262 ? gen_ashrsi3
16266 {
16269 ? gen_ashrsi3
16273 ? gen_x86_shift_adj_1
16275 scratch));
16276 }
16277 else
16279 ? gen_x86_shift_adj_3
16281 }
16282 }
16284 void
16286 {
16292 {
16297 {
16303 ? gen_lshrsi3
16306 }
16307 else
16308 {
16312 ? gen_x86_shrd
16315 ? gen_lshrsi3
16317 }
16318 }
16319 else
16320 {
16327 ? gen_x86_shrd
16330 ? gen_lshrsi3
16333 /* Heh. By reversing the arguments, we can reuse this pattern. */
16335 {
16338 ? gen_x86_shift_adj_1
16340 scratch));
16341 }
16342 else
16344 ? gen_x86_shift_adj_2
16346 }
16347 }
16349 /* Predict just emitted jump instruction to be taken with probability PROB. */
16350 static void
16352 {
16359 }
16361 /* Helper function for the string operations below. Dest VARIABLE whether
16362 it is aligned to VALUE bytes. If true, jump to the label. */
16363 static rtx
16365 {
16370 else
16376 else
16379 }
16381 /* Adjust COUNTER by the VALUE. */
16382 static void
16384 {
16387 else
16389 }
16391 /* Zero extend possibly SImode EXP to Pmode register. */
16392 rtx
16394 {
16395 rtx r;
16403 }
16405 /* Divide COUNTREG by SCALE. */
16406 static rtx
16408 {
16409 rtx sc;
16410 rtx piece_size_mask;
16423 }
16425 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16426 DImode for constant loop counts. */
16428 static enum machine_mode
16430 {
16438 }
16440 /* When SRCPTR is non-NULL, output simple loop to move memory
16441 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16442 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16443 equivalent loop to set memory by VALUE (supposed to be in MODE).
16445 The size is rounded down to whole number of chunk size moved at once.
16446 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16449 static void
16454 {
16459 rtx size;
16460 rtx x_addr;
16461 rtx y_addr;
16470 /* Those two should combine. */
16472 {
16476 }
16486 {
16490 /* When unrolling for chips that reorder memory reads and writes,
16491 we can save registers by using single temporary.
16492 Also using 4 temporaries is overkill in 32bit mode. */
16494 {
16496 {
16498 {
16499 destmem =
16501 srcmem =
16503 }
16505 }
16506 }
16507 else
16508 {
16512 {
16515 {
16516 srcmem =
16518 }
16520 }
16522 {
16524 {
16525 destmem =
16527 }
16529 }
16530 }
16531 }
16532 else
16534 {
16536 destmem =
16539 }
16549 {
16555 else
16557 }
16558 else
16566 {
16571 }
16573 }
16575 /* Output "rep; mov" instruction.
16576 Arguments have same meaning as for previous function */
16577 static void
16580 rtx count,
16582 {
16583 rtx destexp;
16584 rtx srcexp;
16585 rtx countreg;
16587 /* If the size is known, it is shorter to use rep movs. */
16598 {
16605 }
16606 else
16607 {
16610 }
16613 }
16615 /* Output "rep; stos" instruction.
16616 Arguments have same meaning as for previous function */
16617 static void
16619 rtx count,
16621 {
16622 rtx destexp;
16623 rtx countreg;
16630 {
16634 }
16635 else
16638 }
16640 static void
16643 {
16647 }
16649 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16650 static void
16653 {
16656 {
16661 {
16663 {
16666 }
16667 else
16670 }
16672 {
16675 else
16676 {
16679 }
16681 }
16683 {
16686 }
16688 {
16691 }
16693 {
16696 }
16698 }
16700 {
16706 }
16708 /* When there are stringops, we can cheaply increase dest and src pointers.
16709 Otherwise we save code size by maintaining offset (zero is readily
16710 available from preceding rep operation) and using x86 addressing modes.
16711 */
16713 {
16715 {
16722 }
16724 {
16731 }
16733 {
16740 }
16741 }
16742 else
16743 {
16745 rtx tmp;
16748 {
16759 }
16761 {
16774 }
16776 {
16785 }
16786 }
16787 }
16789 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16790 static void
16793 {
16794 count =
16800 }
16802 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16803 static void
16805 {
16806 rtx dest;
16809 {
16814 {
16816 {
16821 }
16822 else
16825 }
16827 {
16829 {
16832 }
16833 else
16834 {
16839 }
16841 }
16843 {
16847 }
16849 {
16853 }
16855 {
16859 }
16861 }
16863 {
16866 }
16868 {
16871 {
16875 }
16876 else
16877 {
16883 }
16886 }
16888 {
16891 {
16894 }
16895 else
16896 {
16900 }
16903 }
16905 {
16911 }
16913 {
16919 }
16921 {
16927 }
16928 }
16930 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
16931 DESIRED_ALIGNMENT. */
16932 static void
16936 {
16938 {
16946 }
16948 {
16956 }
16958 {
16966 }
16968 }
16970 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
16971 DESIRED_ALIGNMENT. */
16972 static void
16975 {
16977 {
16984 }
16986 {
16993 }
16995 {
17002 }
17004 }
17006 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17007 static enum stringop_alg
17010 {
17013 /* Algorithms using the rep prefix want at least edi and ecx;
17014 additionally, memset wants eax and memcpy wants esi. Don't
17015 consider such algorithms if the user has appropriated those
17016 registers for their own purposes. */
17018 || (memset
17021 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17022 || (alg != rep_prefix_1_byte \
17023 && alg != rep_prefix_4_byte \
17024 && alg != rep_prefix_8_byte))
17027 /* Even if the string operation call is cold, we still might spend a lot
17028 of time processing large blocks. */
17033 else
17041 else
17045 /* rep; movq or rep; movl is the smallest variant. */
17047 {
17050 else
17052 }
17053 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17054 */
17058 {
17062 {
17063 /* We get here if the algorithms that were not libcall-based
17064 were rep-prefix based and we are unable to use rep prefixes
17065 based on global register usage. Break out of the loop and
17066 use the heuristic below. */
17070 {
17075 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17076 last non-libcall inline algorithm. */
17078 {
17079 /* When the current size is best to be copied by a libcall,
17080 but we are still forced to inline, run the heuristic below
17081 that will pick code for medium sized blocks. */
17085 }
17088 }
17089 }
17091 }
17092 /* When asked to inline the call anyway, try to pick meaningful choice.
17093 We look for maximal size of block that is faster to copy by hand and
17094 take blocks of at most of that size guessing that average size will
17095 be roughly half of the block.
17097 If this turns out to be bad, we might simply specify the preferred
17098 choice in ix86_costs. */
17101 {
17108 {
17115 }
17116 /* If there aren't any usable algorithms, then recursing on
17117 smaller sizes isn't going to find anything. Just return the
17118 simple byte-at-a-time copy loop. */
17120 {
17121 /* Pick something reasonable. */
17125 }
17134 }
17136 #undef ALG_USABLE_P
17137 }
17139 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17140 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17141 static int
17145 {
17148 {
17159 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17160 copying whole cacheline at once. */
17163 else
17167 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17168 copying whole cacheline at once. */
17171 else
17179 }
17188 }
17190 /* Return the smallest power of 2 greater than VAL. */
17191 static int
17193 {
17198 }
17200 /* Expand string move (memcpy) operation. Use i386 string operations when
17201 profitable. expand_setmem contains similar code. The code depends upon
17202 architecture, block size and alignment, but always has the same
17203 overall structure:
17205 1) Prologue guard: Conditional that jumps up to epilogues for small
17206 blocks that can be handled by epilogue alone. This is faster but
17207 also needed for correctness, since prologue assume the block is larger
17208 than the desired alignment.
17210 Optional dynamic check for size and libcall for large
17211 blocks is emitted here too, with -minline-stringops-dynamically.
17213 2) Prologue: copy first few bytes in order to get destination aligned
17214 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17215 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17216 We emit either a jump tree on power of two sized blocks, or a byte loop.
17218 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17219 with specified algorithm.
17221 4) Epilogue: code copying tail of the block that is too small to be
17222 handled by main body (or up to size guarded by prologue guard). */
17224 int
17227 {
17228 rtx destreg;
17229 rtx srcreg;
17231 rtx tmp;
17244 /* i386 can do misaligned access on reasonably increased cost. */
17253 /* Make sure we don't need to care about overflow later on. */
17257 /* Step 0: Decide on preferred algorithm, desired alignment and
17258 size of chunks to be copied by main loop. */
17274 {
17299 }
17303 /* Step 1: Prologue guard. */
17305 /* Alignment code needs count to be in register. */
17310 /* Ensure that alignment prologue won't copy past end of block. */
17312 {
17314 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17315 Make sure it is power of 2. */
17319 {
17322 }
17323 else
17324 {
17331 else
17333 }
17334 }
17336 /* Emit code to decide on runtime whether library call or inline should be
17337 used. */
17339 {
17341 {
17343 {
17347 }
17348 }
17349 else
17350 {
17359 }
17360 }
17362 /* Step 2: Alignment prologue. */
17365 {
17366 /* Except for the first move in epilogue, we no longer know
17367 constant offset in aliasing info. It don't seems to worth
17368 the pain to maintain it for the first move, so throw away
17369 the info early. */
17373 desired_align);
17375 {
17376 /* It is possible that we copied enough so the main loop will not
17377 execute. */
17384 else
17386 }
17387 }
17389 {
17393 }
17395 /* Step 3: Main loop. */
17398 {
17411 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17412 registers for 4 temporaries anyway. */
17415 expected_size);
17419 DImode);
17423 SImode);
17427 QImode);
17429 }
17430 /* Adjust properly the offset of src and dest memory for aliasing. */
17432 {
17437 }
17438 else
17439 {
17442 }
17444 /* Step 4: Epilogue to copy the remaining bytes. */
17445 epilogue:
17447 {
17448 /* When the main loop is done, COUNT_EXP might hold original count,
17449 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17450 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17451 bytes. Compensate if needed. */
17454 {
17455 tmp =
17458 OPTAB_DIRECT);
17461 }
17464 }
17468 epilogue_size_needed);
17472 }
17474 /* Helper function for memcpy. For QImode value 0xXY produce
17475 0xXYXYXYXY of wide specified by MODE. This is essentially
17476 a * 0x10101010, but we can do slightly better than
17477 synth_mult by unwinding the sequence by hand on CPUs with
17478 slow multiply. */
17479 static rtx
17481 {
17483 rtx tmp;
17490 {
17498 }
17507 nops--;
17512 {
17516 OPTAB_DIRECT);
17517 }
17518 else
17519 {
17525 else
17527 else
17528 {
17531 reg =
17533 }
17543 }
17544 }
17546 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
17547 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
17548 alignment from ALIGN to DESIRED_ALIGN. */
17549 static rtx
17551 {
17552 rtx promoted_val;
17561 else
17565 }
17567 /* Expand string clear operation (bzero). Use i386 string operations when
17568 profitable. See expand_movmem comment for explanation of individual
17569 steps performed. */
17570 int
17573 {
17574 rtx destreg;
17576 rtx tmp;
17591 /* i386 can do misaligned access on reasonably increased cost. */
17600 /* Make sure we don't need to care about overflow later on. */
17604 /* Step 0: Decide on preferred algorithm, desired alignment and
17605 size of chunks to be copied by main loop. */
17620 {
17645 }
17648 /* Step 1: Prologue guard. */
17650 /* Alignment code needs count to be in register. */
17652 {
17657 }
17658 /* Do the cheap promotion to allow better CSE across the
17659 main loop and epilogue (ie one load of the big constant in the
17660 front of all code. */
17664 /* Ensure that alignment prologue won't copy past end of block. */
17666 {
17668 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17669 Make sure it is power of 2. */
17672 /* To improve performance of small blocks, we jump around the VAL
17673 promoting mode. This mean that if the promoted VAL is not constant,
17674 we might not use it in the epilogue and have to use byte
17675 loop variant. */
17683 ;
17686 else
17688 }
17690 {
17699 }
17701 /* Step 2: Alignment prologue. */
17703 /* Do the expensive promotion once we branched off the small blocks. */
17710 {
17711 /* Except for the first move in epilogue, we no longer know
17712 constant offset in aliasing info. It don't seems to worth
17713 the pain to maintain it for the first move, so throw away
17714 the info early. */
17717 desired_align);
17719 {
17720 /* It is possible that we copied enough so the main loop will not
17721 execute. */
17728 else
17730 }
17731 }
17733 {
17737 }
17739 /* Step 3: Main loop. */
17742 {
17760 DImode);
17764 SImode);
17768 QImode);
17770 }
17771 /* Adjust properly the offset of src and dest memory for aliasing. */
17775 else
17778 /* Step 4: Epilogue to copy the remaining bytes. */
17781 {
17782 /* When the main loop is done, COUNT_EXP might hold original count,
17783 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17784 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17785 bytes. Compensate if needed. */
17788 {
17789 tmp =
17792 OPTAB_DIRECT);
17796 }
17799 }
17801 {
17804 size_needed);
17805 else
17807 size_needed);
17808 }
17812 }
17814 /* Expand the appropriate insns for doing strlen if not just doing
17815 repnz; scasb
17817 out = result, initialized with the start address
17818 align_rtx = alignment of the address.
17819 scratch = scratch register, initialized with the startaddress when
17820 not aligned, otherwise undefined
17822 This is just the body. It needs the initializations mentioned above and
17823 some address computing at the end. These things are done in i386.md. */
17825 static void
17827 {
17829 rtx tmp;
17834 rtx mem;
17837 rtx cmp;
17843 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
17845 /* Is there a known alignment and is it less than 4? */
17847 {
17850 /* Is there a known alignment and is it not 2? */
17852 {
17856 /* Leave just the 3 lower bits. */
17866 }
17867 else
17868 {
17869 /* Since the alignment is 2, we have to check 2 or 0 bytes;
17870 check if is aligned to 4 - byte. */
17877 }
17881 /* Now compare the bytes. */
17883 /* Compare the first n unaligned byte on a byte per byte basis. */
17887 /* Increment the address. */
17890 /* Not needed with an alignment of 2 */
17892 {
17896 end_0_label);
17901 }
17904 end_0_label);
17907 }
17909 /* Generate loop to check 4 bytes at a time. It is not a good idea to
17910 align this loop. It gives only huge programs, but does not help to
17911 speed up. */
17918 /* This formula yields a nonzero result iff one of the bytes is zero.
17919 This saves three branches inside loop and many cycles. */
17927 align_4_label);
17930 {
17936 /* If zero is not in the first two bytes, move two bytes forward. */
17942 reg,
17943 tmpreg)));
17944 /* Emit lea manually to avoid clobbering of flags. */
17952 reg2,
17953 out)));
17955 }
17956 else
17957 {
17959 /* Is zero in the first two bytes? */
17966 pc_rtx);
17970 /* Not in the first two. Move two bytes forward. */
17976 }
17978 /* Avoid branch in fixing the byte. */
17985 }
17987 /* Expand strlen. */
17989 int
17991 {
17994 /* The generic case of strlen expander is long. Avoid it's
17995 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
17998 && !TARGET_INLINE_ALL_STRINGOPS
18008 {
18009 /* Well it seems that some optimizer does not combine a call like
18010 foo(strlen(bar), strlen(bar));
18011 when the move and the subtraction is done here. It does calculate
18012 the length just once when these instructions are done inside of
18013 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18014 often used and I use one fewer register for the lifetime of
18015 output_strlen_unroll() this is better. */
18021 /* strlensi_unroll_1 returns the address of the zero at the end of
18022 the string, like memchr(), so compute the length by subtracting
18023 the start address. */
18025 }
18026 else
18027 {
18028 rtx unspec;
18030 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18043 /* If .md starts supporting :P, this can be done in .md. */
18049 }
18051 }
18053 /* For given symbol (function) construct code to compute address of it's PLT
18054 entry in large x86-64 PIC model. */
18055 rtx
18057 {
18067 }
18069 void
18071 rtx callarg2 ATTRIBUTE_UNUSED,
18073 {
18081 {
18082 #if TARGET_MACHO
18085 #endif
18086 }
18087 else
18088 {
18089 /* Static functions and indirect calls don't need the pic register. */
18094 }
18097 {
18101 }
18109 {
18112 }
18115 {
18116 rtx addr;
18121 }
18127 {
18131 }
18136 }
18138 \f
18139 /* Clear stack slot assignments remembered from previous functions.
18140 This is called from INIT_EXPANDERS once before RTL is emitted for each
18141 function. */
18145 {
18154 }
18156 /* Return a MEM corresponding to a stack slot with mode MODE.
18157 Allocate a new slot if necessary.
18159 The RTL for a function can have several slots available: N is
18160 which slot to use. */
18162 rtx
18164 {
18169 /* Virtual slot is valid only before vregs are instantiated. */
18185 }
18187 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18190 rtx
18192 {
18195 {
18197 (TARGET_ANY_GNU_TLS
18201 }
18204 }
18206 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18209 rtx
18211 {
18214 {
18219 }
18222 }
18223 \f
18224 /* Calculate the length of the memory address in the instruction
18225 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18227 int
18229 {
18254 /* Rule of thumb:
18255 - esp as the base always wants an index,
18256 - ebp as the base always wants a displacement. */
18258 /* Register Indirect. */
18260 {
18261 /* esp (for its index) and ebp (for its displacement) need
18262 the two-byte modrm form. */
18268 }
18270 /* Direct Addressing. */
18274 else
18275 {
18276 /* Find the length of the displacement constant. */
18278 {
18281 else
18283 }
18284 /* ebp always wants a displacement. */
18288 /* An index requires the two-byte modrm form.... */
18290 /* ...like esp, which always wants an index. */
18295 }
18298 }
18300 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18301 is set, expect that insn have 8bit immediate alternative. */
18302 int
18304 {
18310 {
18314 else
18315 {
18317 {
18327 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18333 }
18334 }
18335 }
18337 }
18338 /* Compute default value for "length_address" attribute. */
18339 int
18341 {
18345 {
18354 }
18359 {
18362 }
18364 }
18366 /* Compute default value for "length_vex" attribute. It includes
18367 2 or 3 byte VEX prefix and 1 opcode byte. */
18369 int
18372 {
18375 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18376 byte VEX prefix. */
18380 /* We can always use 2 byte VEX prefix in 32bit. */
18388 {
18389 /* REX.W bit uses 3 byte VEX prefix. */
18392 }
18393 else
18394 {
18395 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18399 }
18402 }
18403 \f
18404 /* Return the maximum number of instructions a cpu can issue. */
18406 static int
18408 {
18410 {
18430 }
18431 }
18433 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
18434 by DEP_INSN and nothing set by DEP_INSN. */
18436 static int
18438 {
18441 /* Simplify the test for uninteresting insns. */
18449 {
18452 }
18457 {
18460 }
18461 else
18467 /* This test is true if the dependent insn reads the flags but
18468 not any other potentially set register. */
18476 }
18478 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
18479 address with operands set by DEP_INSN. */
18481 static int
18483 {
18484 rtx addr;
18488 {
18497 }
18498 else
18499 {
18504 {
18507 }
18509 found:;
18510 }
18513 }
18515 static int
18517 {
18523 /* Anti and output dependencies have zero cost on all CPUs. */
18529 /* If we can't recognize the insns, we can't really do anything. */
18537 {
18539 /* Address Generation Interlock adds a cycle of latency. */
18543 /* ??? Compares pair with jump/setcc. */
18547 /* Floating point stores require value to be ready one cycle earlier. */
18557 /* INT->FP conversion is expensive. */
18561 /* There is one cycle extra latency between an FP op and a store. */
18569 /* Show ability of reorder buffer to hide latency of load by executing
18570 in parallel with previous instruction in case
18571 previous instruction is not needed to compute the address. */
18574 {
18575 /* Claim moves to take one cycle, as core can issue one load
18576 at time and the next load can start cycle later. */
18581 cost--;
18582 }
18588 /* The esp dependency is resolved before the instruction is really
18589 finished. */
18594 /* INT->FP conversion is expensive. */
18598 /* Show ability of reorder buffer to hide latency of load by executing
18599 in parallel with previous instruction in case
18600 previous instruction is not needed to compute the address. */
18603 {
18604 /* Claim moves to take one cycle, as core can issue one load
18605 at time and the next load can start cycle later. */
18611 else
18613 }
18623 /* Show ability of reorder buffer to hide latency of load by executing
18624 in parallel with previous instruction in case
18625 previous instruction is not needed to compute the address. */
18628 {
18632 /* Because of the difference between the length of integer and
18633 floating unit pipeline preparation stages, the memory operands
18634 for floating point are cheaper.
18636 ??? For Athlon it the difference is most probably 2. */
18639 else
18644 else
18646 }
18650 }
18653 }
18655 /* How many alternative schedules to try. This should be as wide as the
18656 scheduling freedom in the DFA, but no wider. Making this value too
18657 large results extra work for the scheduler. */
18659 static int
18661 {
18663 {
18673 }
18674 }
18676 \f
18677 /* Compute the alignment given to a constant that is being placed in memory.
18678 EXP is the constant and ALIGN is the alignment that the object would
18679 ordinarily have.
18680 The value of this function is used instead of that alignment to align
18681 the object. */
18683 int
18685 {
18688 {
18693 }
18699 }
18701 /* Compute the alignment for a static variable.
18702 TYPE is the data type, and ALIGN is the alignment that
18703 the object would ordinarily have. The value of this function is used
18704 instead of that alignment to align the object. */
18706 int
18708 {
18719 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18720 to 16byte boundary. */
18722 {
18729 }
18732 {
18737 }
18739 {
18746 }
18751 {
18756 }
18759 {
18764 }
18767 }
18769 /* Compute the alignment for a local variable or a stack slot. TYPE is
18770 the data type, MODE is the widest mode available and ALIGN is the
18771 alignment that the object would ordinarily have. The value of this
18772 macro is used instead of that alignment to align the object. */
18774 unsigned int
18777 {
18778 /* If TYPE is NULL, we are allocating a stack slot for caller-save
18779 register in MODE. We will return the largest alignment of XF
18780 and DF. */
18782 {
18786 }
18788 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18789 to 16byte boundary. */
18791 {
18798 }
18800 {
18805 }
18807 {
18813 }
18818 {
18823 }
18826 {
18832 }
18834 }
18835 \f
18836 /* Emit RTL insns to initialize the variable parts of a trampoline.
18837 FNADDR is an RTX for the address of the function's pure code.
18838 CXT is an RTX for the static chain value for the function. */
18839 void
18841 {
18843 {
18844 /* Compute offset from the end of the jmp to the target function. */
18854 }
18855 else
18856 {
18858 /* Try to load address using shorter movl instead of movabs.
18859 We may want to support movq for kernel mode, but kernel does not use
18860 trampolines at the moment. */
18862 {
18869 }
18870 else
18871 {
18875 fnaddr);
18877 }
18878 /* Load static chain using movabs to r10. */
18882 cxt);
18884 /* Jump to the r11 */
18891 }
18893 #ifdef ENABLE_EXECUTE_STACK
18896 #endif
18897 }
18898 \f
18899 /* Codes for all the SSE/MMX builtins. */
18900 enum ix86_builtins
18901 {
18902 IX86_BUILTIN_ADDPS,
18903 IX86_BUILTIN_ADDSS,
18904 IX86_BUILTIN_DIVPS,
18905 IX86_BUILTIN_DIVSS,
18906 IX86_BUILTIN_MULPS,
18907 IX86_BUILTIN_MULSS,
18908 IX86_BUILTIN_SUBPS,
18909 IX86_BUILTIN_SUBSS,
18911 IX86_BUILTIN_CMPEQPS,
18912 IX86_BUILTIN_CMPLTPS,
18913 IX86_BUILTIN_CMPLEPS,
18914 IX86_BUILTIN_CMPGTPS,
18915 IX86_BUILTIN_CMPGEPS,
18916 IX86_BUILTIN_CMPNEQPS,
18917 IX86_BUILTIN_CMPNLTPS,
18918 IX86_BUILTIN_CMPNLEPS,
18919 IX86_BUILTIN_CMPNGTPS,
18920 IX86_BUILTIN_CMPNGEPS,
18921 IX86_BUILTIN_CMPORDPS,
18922 IX86_BUILTIN_CMPUNORDPS,
18923 IX86_BUILTIN_CMPEQSS,
18924 IX86_BUILTIN_CMPLTSS,
18925 IX86_BUILTIN_CMPLESS,
18926 IX86_BUILTIN_CMPNEQSS,
18927 IX86_BUILTIN_CMPNLTSS,
18928 IX86_BUILTIN_CMPNLESS,
18929 IX86_BUILTIN_CMPNGTSS,
18930 IX86_BUILTIN_CMPNGESS,
18931 IX86_BUILTIN_CMPORDSS,
18932 IX86_BUILTIN_CMPUNORDSS,
18934 IX86_BUILTIN_COMIEQSS,
18935 IX86_BUILTIN_COMILTSS,
18936 IX86_BUILTIN_COMILESS,
18937 IX86_BUILTIN_COMIGTSS,
18938 IX86_BUILTIN_COMIGESS,
18939 IX86_BUILTIN_COMINEQSS,
18940 IX86_BUILTIN_UCOMIEQSS,
18941 IX86_BUILTIN_UCOMILTSS,
18942 IX86_BUILTIN_UCOMILESS,
18943 IX86_BUILTIN_UCOMIGTSS,
18944 IX86_BUILTIN_UCOMIGESS,
18945 IX86_BUILTIN_UCOMINEQSS,
18947 IX86_BUILTIN_CVTPI2PS,
18948 IX86_BUILTIN_CVTPS2PI,
18949 IX86_BUILTIN_CVTSI2SS,
18950 IX86_BUILTIN_CVTSI642SS,
18951 IX86_BUILTIN_CVTSS2SI,
18952 IX86_BUILTIN_CVTSS2SI64,
18953 IX86_BUILTIN_CVTTPS2PI,
18954 IX86_BUILTIN_CVTTSS2SI,
18955 IX86_BUILTIN_CVTTSS2SI64,
18957 IX86_BUILTIN_MAXPS,
18958 IX86_BUILTIN_MAXSS,
18959 IX86_BUILTIN_MINPS,
18960 IX86_BUILTIN_MINSS,
18962 IX86_BUILTIN_LOADUPS,
18963 IX86_BUILTIN_STOREUPS,
18964 IX86_BUILTIN_MOVSS,
18966 IX86_BUILTIN_MOVHLPS,
18967 IX86_BUILTIN_MOVLHPS,
18968 IX86_BUILTIN_LOADHPS,
18969 IX86_BUILTIN_LOADLPS,
18970 IX86_BUILTIN_STOREHPS,
18971 IX86_BUILTIN_STORELPS,
18973 IX86_BUILTIN_MASKMOVQ,
18974 IX86_BUILTIN_MOVMSKPS,
18975 IX86_BUILTIN_PMOVMSKB,
18977 IX86_BUILTIN_MOVNTPS,
18978 IX86_BUILTIN_MOVNTQ,
18980 IX86_BUILTIN_LOADDQU,
18981 IX86_BUILTIN_STOREDQU,
18983 IX86_BUILTIN_PACKSSWB,
18984 IX86_BUILTIN_PACKSSDW,
18985 IX86_BUILTIN_PACKUSWB,
18987 IX86_BUILTIN_PADDB,
18988 IX86_BUILTIN_PADDW,
18989 IX86_BUILTIN_PADDD,
18990 IX86_BUILTIN_PADDQ,
18991 IX86_BUILTIN_PADDSB,
18992 IX86_BUILTIN_PADDSW,
18993 IX86_BUILTIN_PADDUSB,
18994 IX86_BUILTIN_PADDUSW,
18995 IX86_BUILTIN_PSUBB,
18996 IX86_BUILTIN_PSUBW,
18997 IX86_BUILTIN_PSUBD,
18998 IX86_BUILTIN_PSUBQ,
18999 IX86_BUILTIN_PSUBSB,
19000 IX86_BUILTIN_PSUBSW,
19001 IX86_BUILTIN_PSUBUSB,
19002 IX86_BUILTIN_PSUBUSW,
19004 IX86_BUILTIN_PAND,
19005 IX86_BUILTIN_PANDN,
19006 IX86_BUILTIN_POR,
19007 IX86_BUILTIN_PXOR,
19009 IX86_BUILTIN_PAVGB,
19010 IX86_BUILTIN_PAVGW,
19012 IX86_BUILTIN_PCMPEQB,
19013 IX86_BUILTIN_PCMPEQW,
19014 IX86_BUILTIN_PCMPEQD,
19015 IX86_BUILTIN_PCMPGTB,
19016 IX86_BUILTIN_PCMPGTW,
19017 IX86_BUILTIN_PCMPGTD,
19019 IX86_BUILTIN_PMADDWD,
19021 IX86_BUILTIN_PMAXSW,
19022 IX86_BUILTIN_PMAXUB,
19023 IX86_BUILTIN_PMINSW,
19024 IX86_BUILTIN_PMINUB,
19026 IX86_BUILTIN_PMULHUW,
19027 IX86_BUILTIN_PMULHW,
19028 IX86_BUILTIN_PMULLW,
19030 IX86_BUILTIN_PSADBW,
19031 IX86_BUILTIN_PSHUFW,
19033 IX86_BUILTIN_PSLLW,
19034 IX86_BUILTIN_PSLLD,
19035 IX86_BUILTIN_PSLLQ,
19036 IX86_BUILTIN_PSRAW,
19037 IX86_BUILTIN_PSRAD,
19038 IX86_BUILTIN_PSRLW,
19039 IX86_BUILTIN_PSRLD,
19040 IX86_BUILTIN_PSRLQ,
19041 IX86_BUILTIN_PSLLWI,
19042 IX86_BUILTIN_PSLLDI,
19043 IX86_BUILTIN_PSLLQI,
19044 IX86_BUILTIN_PSRAWI,
19045 IX86_BUILTIN_PSRADI,
19046 IX86_BUILTIN_PSRLWI,
19047 IX86_BUILTIN_PSRLDI,
19048 IX86_BUILTIN_PSRLQI,
19050 IX86_BUILTIN_PUNPCKHBW,
19051 IX86_BUILTIN_PUNPCKHWD,
19052 IX86_BUILTIN_PUNPCKHDQ,
19053 IX86_BUILTIN_PUNPCKLBW,
19054 IX86_BUILTIN_PUNPCKLWD,
19055 IX86_BUILTIN_PUNPCKLDQ,
19057 IX86_BUILTIN_SHUFPS,
19059 IX86_BUILTIN_RCPPS,
19060 IX86_BUILTIN_RCPSS,
19061 IX86_BUILTIN_RSQRTPS,
19062 IX86_BUILTIN_RSQRTPS_NR,
19063 IX86_BUILTIN_RSQRTSS,
19064 IX86_BUILTIN_RSQRTF,
19065 IX86_BUILTIN_SQRTPS,
19066 IX86_BUILTIN_SQRTPS_NR,
19067 IX86_BUILTIN_SQRTSS,
19069 IX86_BUILTIN_UNPCKHPS,
19070 IX86_BUILTIN_UNPCKLPS,
19072 IX86_BUILTIN_ANDPS,
19073 IX86_BUILTIN_ANDNPS,
19074 IX86_BUILTIN_ORPS,
19075 IX86_BUILTIN_XORPS,
19077 IX86_BUILTIN_EMMS,
19078 IX86_BUILTIN_LDMXCSR,
19079 IX86_BUILTIN_STMXCSR,
19080 IX86_BUILTIN_SFENCE,
19082 /* 3DNow! Original */
19083 IX86_BUILTIN_FEMMS,
19084 IX86_BUILTIN_PAVGUSB,
19085 IX86_BUILTIN_PF2ID,
19086 IX86_BUILTIN_PFACC,
19087 IX86_BUILTIN_PFADD,
19088 IX86_BUILTIN_PFCMPEQ,
19089 IX86_BUILTIN_PFCMPGE,
19090 IX86_BUILTIN_PFCMPGT,
19091 IX86_BUILTIN_PFMAX,
19092 IX86_BUILTIN_PFMIN,
19093 IX86_BUILTIN_PFMUL,
19094 IX86_BUILTIN_PFRCP,
19095 IX86_BUILTIN_PFRCPIT1,
19096 IX86_BUILTIN_PFRCPIT2,
19097 IX86_BUILTIN_PFRSQIT1,
19098 IX86_BUILTIN_PFRSQRT,
19099 IX86_BUILTIN_PFSUB,
19100 IX86_BUILTIN_PFSUBR,
19101 IX86_BUILTIN_PI2FD,
19102 IX86_BUILTIN_PMULHRW,
19104 /* 3DNow! Athlon Extensions */
19105 IX86_BUILTIN_PF2IW,
19106 IX86_BUILTIN_PFNACC,
19107 IX86_BUILTIN_PFPNACC,
19108 IX86_BUILTIN_PI2FW,
19109 IX86_BUILTIN_PSWAPDSI,
19110 IX86_BUILTIN_PSWAPDSF,
19112 /* SSE2 */
19113 IX86_BUILTIN_ADDPD,
19114 IX86_BUILTIN_ADDSD,
19115 IX86_BUILTIN_DIVPD,
19116 IX86_BUILTIN_DIVSD,
19117 IX86_BUILTIN_MULPD,
19118 IX86_BUILTIN_MULSD,
19119 IX86_BUILTIN_SUBPD,
19120 IX86_BUILTIN_SUBSD,
19122 IX86_BUILTIN_CMPEQPD,
19123 IX86_BUILTIN_CMPLTPD,
19124 IX86_BUILTIN_CMPLEPD,
19125 IX86_BUILTIN_CMPGTPD,
19126 IX86_BUILTIN_CMPGEPD,
19127 IX86_BUILTIN_CMPNEQPD,
19128 IX86_BUILTIN_CMPNLTPD,
19129 IX86_BUILTIN_CMPNLEPD,
19130 IX86_BUILTIN_CMPNGTPD,
19131 IX86_BUILTIN_CMPNGEPD,
19132 IX86_BUILTIN_CMPORDPD,
19133 IX86_BUILTIN_CMPUNORDPD,
19134 IX86_BUILTIN_CMPEQSD,
19135 IX86_BUILTIN_CMPLTSD,
19136 IX86_BUILTIN_CMPLESD,
19137 IX86_BUILTIN_CMPNEQSD,
19138 IX86_BUILTIN_CMPNLTSD,
19139 IX86_BUILTIN_CMPNLESD,
19140 IX86_BUILTIN_CMPORDSD,
19141 IX86_BUILTIN_CMPUNORDSD,
19143 IX86_BUILTIN_COMIEQSD,
19144 IX86_BUILTIN_COMILTSD,
19145 IX86_BUILTIN_COMILESD,
19146 IX86_BUILTIN_COMIGTSD,
19147 IX86_BUILTIN_COMIGESD,
19148 IX86_BUILTIN_COMINEQSD,
19149 IX86_BUILTIN_UCOMIEQSD,
19150 IX86_BUILTIN_UCOMILTSD,
19151 IX86_BUILTIN_UCOMILESD,
19152 IX86_BUILTIN_UCOMIGTSD,
19153 IX86_BUILTIN_UCOMIGESD,
19154 IX86_BUILTIN_UCOMINEQSD,
19156 IX86_BUILTIN_MAXPD,
19157 IX86_BUILTIN_MAXSD,
19158 IX86_BUILTIN_MINPD,
19159 IX86_BUILTIN_MINSD,
19161 IX86_BUILTIN_ANDPD,
19162 IX86_BUILTIN_ANDNPD,
19163 IX86_BUILTIN_ORPD,
19164 IX86_BUILTIN_XORPD,
19166 IX86_BUILTIN_SQRTPD,
19167 IX86_BUILTIN_SQRTSD,
19169 IX86_BUILTIN_UNPCKHPD,
19170 IX86_BUILTIN_UNPCKLPD,
19172 IX86_BUILTIN_SHUFPD,
19174 IX86_BUILTIN_LOADUPD,
19175 IX86_BUILTIN_STOREUPD,
19176 IX86_BUILTIN_MOVSD,
19178 IX86_BUILTIN_LOADHPD,
19179 IX86_BUILTIN_LOADLPD,
19181 IX86_BUILTIN_CVTDQ2PD,
19182 IX86_BUILTIN_CVTDQ2PS,
19184 IX86_BUILTIN_CVTPD2DQ,
19185 IX86_BUILTIN_CVTPD2PI,
19186 IX86_BUILTIN_CVTPD2PS,
19187 IX86_BUILTIN_CVTTPD2DQ,
19188 IX86_BUILTIN_CVTTPD2PI,
19190 IX86_BUILTIN_CVTPI2PD,
19191 IX86_BUILTIN_CVTSI2SD,
19192 IX86_BUILTIN_CVTSI642SD,
19194 IX86_BUILTIN_CVTSD2SI,
19195 IX86_BUILTIN_CVTSD2SI64,
19196 IX86_BUILTIN_CVTSD2SS,
19197 IX86_BUILTIN_CVTSS2SD,
19198 IX86_BUILTIN_CVTTSD2SI,
19199 IX86_BUILTIN_CVTTSD2SI64,
19201 IX86_BUILTIN_CVTPS2DQ,
19202 IX86_BUILTIN_CVTPS2PD,
19203 IX86_BUILTIN_CVTTPS2DQ,
19205 IX86_BUILTIN_MOVNTI,
19206 IX86_BUILTIN_MOVNTPD,
19207 IX86_BUILTIN_MOVNTDQ,
19209 IX86_BUILTIN_MOVQ128,
19211 /* SSE2 MMX */
19212 IX86_BUILTIN_MASKMOVDQU,
19213 IX86_BUILTIN_MOVMSKPD,
19214 IX86_BUILTIN_PMOVMSKB128,
19216 IX86_BUILTIN_PACKSSWB128,
19217 IX86_BUILTIN_PACKSSDW128,
19218 IX86_BUILTIN_PACKUSWB128,
19220 IX86_BUILTIN_PADDB128,
19221 IX86_BUILTIN_PADDW128,
19222 IX86_BUILTIN_PADDD128,
19223 IX86_BUILTIN_PADDQ128,
19224 IX86_BUILTIN_PADDSB128,
19225 IX86_BUILTIN_PADDSW128,
19226 IX86_BUILTIN_PADDUSB128,
19227 IX86_BUILTIN_PADDUSW128,
19228 IX86_BUILTIN_PSUBB128,
19229 IX86_BUILTIN_PSUBW128,
19230 IX86_BUILTIN_PSUBD128,
19231 IX86_BUILTIN_PSUBQ128,
19232 IX86_BUILTIN_PSUBSB128,
19233 IX86_BUILTIN_PSUBSW128,
19234 IX86_BUILTIN_PSUBUSB128,
19235 IX86_BUILTIN_PSUBUSW128,
19237 IX86_BUILTIN_PAND128,
19238 IX86_BUILTIN_PANDN128,
19239 IX86_BUILTIN_POR128,
19240 IX86_BUILTIN_PXOR128,
19242 IX86_BUILTIN_PAVGB128,
19243 IX86_BUILTIN_PAVGW128,
19245 IX86_BUILTIN_PCMPEQB128,
19246 IX86_BUILTIN_PCMPEQW128,
19247 IX86_BUILTIN_PCMPEQD128,
19248 IX86_BUILTIN_PCMPGTB128,
19249 IX86_BUILTIN_PCMPGTW128,
19250 IX86_BUILTIN_PCMPGTD128,
19252 IX86_BUILTIN_PMADDWD128,
19254 IX86_BUILTIN_PMAXSW128,
19255 IX86_BUILTIN_PMAXUB128,
19256 IX86_BUILTIN_PMINSW128,
19257 IX86_BUILTIN_PMINUB128,
19259 IX86_BUILTIN_PMULUDQ,
19260 IX86_BUILTIN_PMULUDQ128,
19261 IX86_BUILTIN_PMULHUW128,
19262 IX86_BUILTIN_PMULHW128,
19263 IX86_BUILTIN_PMULLW128,
19265 IX86_BUILTIN_PSADBW128,
19266 IX86_BUILTIN_PSHUFHW,
19267 IX86_BUILTIN_PSHUFLW,
19268 IX86_BUILTIN_PSHUFD,
19270 IX86_BUILTIN_PSLLDQI128,
19271 IX86_BUILTIN_PSLLWI128,
19272 IX86_BUILTIN_PSLLDI128,
19273 IX86_BUILTIN_PSLLQI128,
19274 IX86_BUILTIN_PSRAWI128,
19275 IX86_BUILTIN_PSRADI128,
19276 IX86_BUILTIN_PSRLDQI128,
19277 IX86_BUILTIN_PSRLWI128,
19278 IX86_BUILTIN_PSRLDI128,
19279 IX86_BUILTIN_PSRLQI128,
19281 IX86_BUILTIN_PSLLDQ128,
19282 IX86_BUILTIN_PSLLW128,
19283 IX86_BUILTIN_PSLLD128,
19284 IX86_BUILTIN_PSLLQ128,
19285 IX86_BUILTIN_PSRAW128,
19286 IX86_BUILTIN_PSRAD128,
19287 IX86_BUILTIN_PSRLW128,
19288 IX86_BUILTIN_PSRLD128,
19289 IX86_BUILTIN_PSRLQ128,
19291 IX86_BUILTIN_PUNPCKHBW128,
19292 IX86_BUILTIN_PUNPCKHWD128,
19293 IX86_BUILTIN_PUNPCKHDQ128,
19294 IX86_BUILTIN_PUNPCKHQDQ128,
19295 IX86_BUILTIN_PUNPCKLBW128,
19296 IX86_BUILTIN_PUNPCKLWD128,
19297 IX86_BUILTIN_PUNPCKLDQ128,
19298 IX86_BUILTIN_PUNPCKLQDQ128,
19300 IX86_BUILTIN_CLFLUSH,
19301 IX86_BUILTIN_MFENCE,
19302 IX86_BUILTIN_LFENCE,
19304 /* SSE3. */
19305 IX86_BUILTIN_ADDSUBPS,
19306 IX86_BUILTIN_HADDPS,
19307 IX86_BUILTIN_HSUBPS,
19308 IX86_BUILTIN_MOVSHDUP,
19309 IX86_BUILTIN_MOVSLDUP,
19310 IX86_BUILTIN_ADDSUBPD,
19311 IX86_BUILTIN_HADDPD,
19312 IX86_BUILTIN_HSUBPD,
19313 IX86_BUILTIN_LDDQU,
19315 IX86_BUILTIN_MONITOR,
19316 IX86_BUILTIN_MWAIT,
19318 /* SSSE3. */
19319 IX86_BUILTIN_PHADDW,
19320 IX86_BUILTIN_PHADDD,
19321 IX86_BUILTIN_PHADDSW,
19322 IX86_BUILTIN_PHSUBW,
19323 IX86_BUILTIN_PHSUBD,
19324 IX86_BUILTIN_PHSUBSW,
19325 IX86_BUILTIN_PMADDUBSW,
19326 IX86_BUILTIN_PMULHRSW,
19327 IX86_BUILTIN_PSHUFB,
19328 IX86_BUILTIN_PSIGNB,
19329 IX86_BUILTIN_PSIGNW,
19330 IX86_BUILTIN_PSIGND,
19331 IX86_BUILTIN_PALIGNR,
19332 IX86_BUILTIN_PABSB,
19333 IX86_BUILTIN_PABSW,
19334 IX86_BUILTIN_PABSD,
19336 IX86_BUILTIN_PHADDW128,
19337 IX86_BUILTIN_PHADDD128,
19338 IX86_BUILTIN_PHADDSW128,
19339 IX86_BUILTIN_PHSUBW128,
19340 IX86_BUILTIN_PHSUBD128,
19341 IX86_BUILTIN_PHSUBSW128,
19342 IX86_BUILTIN_PMADDUBSW128,
19343 IX86_BUILTIN_PMULHRSW128,
19344 IX86_BUILTIN_PSHUFB128,
19345 IX86_BUILTIN_PSIGNB128,
19346 IX86_BUILTIN_PSIGNW128,
19347 IX86_BUILTIN_PSIGND128,
19348 IX86_BUILTIN_PALIGNR128,
19349 IX86_BUILTIN_PABSB128,
19350 IX86_BUILTIN_PABSW128,
19351 IX86_BUILTIN_PABSD128,
19353 /* AMDFAM10 - SSE4A New Instructions. */
19354 IX86_BUILTIN_MOVNTSD,
19355 IX86_BUILTIN_MOVNTSS,
19356 IX86_BUILTIN_EXTRQI,
19357 IX86_BUILTIN_EXTRQ,
19358 IX86_BUILTIN_INSERTQI,
19359 IX86_BUILTIN_INSERTQ,
19361 /* SSE4.1. */
19362 IX86_BUILTIN_BLENDPD,
19363 IX86_BUILTIN_BLENDPS,
19364 IX86_BUILTIN_BLENDVPD,
19365 IX86_BUILTIN_BLENDVPS,
19366 IX86_BUILTIN_PBLENDVB128,
19367 IX86_BUILTIN_PBLENDW128,
19369 IX86_BUILTIN_DPPD,
19370 IX86_BUILTIN_DPPS,
19372 IX86_BUILTIN_INSERTPS128,
19374 IX86_BUILTIN_MOVNTDQA,
19375 IX86_BUILTIN_MPSADBW128,
19376 IX86_BUILTIN_PACKUSDW128,
19377 IX86_BUILTIN_PCMPEQQ,
19378 IX86_BUILTIN_PHMINPOSUW128,
19380 IX86_BUILTIN_PMAXSB128,
19381 IX86_BUILTIN_PMAXSD128,
19382 IX86_BUILTIN_PMAXUD128,
19383 IX86_BUILTIN_PMAXUW128,
19385 IX86_BUILTIN_PMINSB128,
19386 IX86_BUILTIN_PMINSD128,
19387 IX86_BUILTIN_PMINUD128,
19388 IX86_BUILTIN_PMINUW128,
19390 IX86_BUILTIN_PMOVSXBW128,
19391 IX86_BUILTIN_PMOVSXBD128,
19392 IX86_BUILTIN_PMOVSXBQ128,
19393 IX86_BUILTIN_PMOVSXWD128,
19394 IX86_BUILTIN_PMOVSXWQ128,
19395 IX86_BUILTIN_PMOVSXDQ128,
19397 IX86_BUILTIN_PMOVZXBW128,
19398 IX86_BUILTIN_PMOVZXBD128,
19399 IX86_BUILTIN_PMOVZXBQ128,
19400 IX86_BUILTIN_PMOVZXWD128,
19401 IX86_BUILTIN_PMOVZXWQ128,
19402 IX86_BUILTIN_PMOVZXDQ128,
19404 IX86_BUILTIN_PMULDQ128,
19405 IX86_BUILTIN_PMULLD128,
19407 IX86_BUILTIN_ROUNDPD,
19408 IX86_BUILTIN_ROUNDPS,
19409 IX86_BUILTIN_ROUNDSD,
19410 IX86_BUILTIN_ROUNDSS,
19412 IX86_BUILTIN_PTESTZ,
19413 IX86_BUILTIN_PTESTC,
19414 IX86_BUILTIN_PTESTNZC,
19416 IX86_BUILTIN_VEC_INIT_V2SI,
19417 IX86_BUILTIN_VEC_INIT_V4HI,
19418 IX86_BUILTIN_VEC_INIT_V8QI,
19419 IX86_BUILTIN_VEC_EXT_V2DF,
19420 IX86_BUILTIN_VEC_EXT_V2DI,
19421 IX86_BUILTIN_VEC_EXT_V4SF,
19422 IX86_BUILTIN_VEC_EXT_V4SI,
19423 IX86_BUILTIN_VEC_EXT_V8HI,
19424 IX86_BUILTIN_VEC_EXT_V2SI,
19425 IX86_BUILTIN_VEC_EXT_V4HI,
19426 IX86_BUILTIN_VEC_EXT_V16QI,
19427 IX86_BUILTIN_VEC_SET_V2DI,
19428 IX86_BUILTIN_VEC_SET_V4SF,
19429 IX86_BUILTIN_VEC_SET_V4SI,
19430 IX86_BUILTIN_VEC_SET_V8HI,
19431 IX86_BUILTIN_VEC_SET_V4HI,
19432 IX86_BUILTIN_VEC_SET_V16QI,
19434 IX86_BUILTIN_VEC_PACK_SFIX,
19436 /* SSE4.2. */
19437 IX86_BUILTIN_CRC32QI,
19438 IX86_BUILTIN_CRC32HI,
19439 IX86_BUILTIN_CRC32SI,
19440 IX86_BUILTIN_CRC32DI,
19442 IX86_BUILTIN_PCMPESTRI128,
19443 IX86_BUILTIN_PCMPESTRM128,
19444 IX86_BUILTIN_PCMPESTRA128,
19445 IX86_BUILTIN_PCMPESTRC128,
19446 IX86_BUILTIN_PCMPESTRO128,
19447 IX86_BUILTIN_PCMPESTRS128,
19448 IX86_BUILTIN_PCMPESTRZ128,
19449 IX86_BUILTIN_PCMPISTRI128,
19450 IX86_BUILTIN_PCMPISTRM128,
19451 IX86_BUILTIN_PCMPISTRA128,
19452 IX86_BUILTIN_PCMPISTRC128,
19453 IX86_BUILTIN_PCMPISTRO128,
19454 IX86_BUILTIN_PCMPISTRS128,
19455 IX86_BUILTIN_PCMPISTRZ128,
19457 IX86_BUILTIN_PCMPGTQ,
19459 /* AES instructions */
19460 IX86_BUILTIN_AESENC128,
19461 IX86_BUILTIN_AESENCLAST128,
19462 IX86_BUILTIN_AESDEC128,
19463 IX86_BUILTIN_AESDECLAST128,
19464 IX86_BUILTIN_AESIMC128,
19465 IX86_BUILTIN_AESKEYGENASSIST128,
19467 /* PCLMUL instruction */
19468 IX86_BUILTIN_PCLMULQDQ128,
19470 /* AVX */
19471 IX86_BUILTIN_ADDPD256,
19472 IX86_BUILTIN_ADDPS256,
19473 IX86_BUILTIN_ADDSUBPD256,
19474 IX86_BUILTIN_ADDSUBPS256,
19475 IX86_BUILTIN_ANDPD256,
19476 IX86_BUILTIN_ANDPS256,
19477 IX86_BUILTIN_ANDNPD256,
19478 IX86_BUILTIN_ANDNPS256,
19479 IX86_BUILTIN_BLENDPD256,
19480 IX86_BUILTIN_BLENDPS256,
19481 IX86_BUILTIN_BLENDVPD256,
19482 IX86_BUILTIN_BLENDVPS256,
19483 IX86_BUILTIN_DIVPD256,
19484 IX86_BUILTIN_DIVPS256,
19485 IX86_BUILTIN_DPPS256,
19486 IX86_BUILTIN_HADDPD256,
19487 IX86_BUILTIN_HADDPS256,
19488 IX86_BUILTIN_HSUBPD256,
19489 IX86_BUILTIN_HSUBPS256,
19490 IX86_BUILTIN_MAXPD256,
19491 IX86_BUILTIN_MAXPS256,
19492 IX86_BUILTIN_MINPD256,
19493 IX86_BUILTIN_MINPS256,
19494 IX86_BUILTIN_MULPD256,
19495 IX86_BUILTIN_MULPS256,
19496 IX86_BUILTIN_ORPD256,
19497 IX86_BUILTIN_ORPS256,
19498 IX86_BUILTIN_SHUFPD256,
19499 IX86_BUILTIN_SHUFPS256,
19500 IX86_BUILTIN_SUBPD256,
19501 IX86_BUILTIN_SUBPS256,
19502 IX86_BUILTIN_XORPD256,
19503 IX86_BUILTIN_XORPS256,
19504 IX86_BUILTIN_CMPSD,
19505 IX86_BUILTIN_CMPSS,
19506 IX86_BUILTIN_CMPPD,
19507 IX86_BUILTIN_CMPPS,
19508 IX86_BUILTIN_CMPPD256,
19509 IX86_BUILTIN_CMPPS256,
19510 IX86_BUILTIN_CVTDQ2PD256,
19511 IX86_BUILTIN_CVTDQ2PS256,
19512 IX86_BUILTIN_CVTPD2PS256,
19513 IX86_BUILTIN_CVTPS2DQ256,
19514 IX86_BUILTIN_CVTPS2PD256,
19515 IX86_BUILTIN_CVTTPD2DQ256,
19516 IX86_BUILTIN_CVTPD2DQ256,
19517 IX86_BUILTIN_CVTTPS2DQ256,
19518 IX86_BUILTIN_EXTRACTF128PD256,
19519 IX86_BUILTIN_EXTRACTF128PS256,
19520 IX86_BUILTIN_EXTRACTF128SI256,
19521 IX86_BUILTIN_VZEROALL,
19522 IX86_BUILTIN_VZEROUPPER,
19523 IX86_BUILTIN_VZEROUPPER_REX64,
19524 IX86_BUILTIN_VPERMILVARPD,
19525 IX86_BUILTIN_VPERMILVARPS,
19526 IX86_BUILTIN_VPERMILVARPD256,
19527 IX86_BUILTIN_VPERMILVARPS256,
19528 IX86_BUILTIN_VPERMILPD,
19529 IX86_BUILTIN_VPERMILPS,
19530 IX86_BUILTIN_VPERMILPD256,
19531 IX86_BUILTIN_VPERMILPS256,
19532 IX86_BUILTIN_VPERMIL2PD,
19533 IX86_BUILTIN_VPERMIL2PS,
19534 IX86_BUILTIN_VPERMIL2PD256,
19535 IX86_BUILTIN_VPERMIL2PS256,
19536 IX86_BUILTIN_VPERM2F128PD256,
19537 IX86_BUILTIN_VPERM2F128PS256,
19538 IX86_BUILTIN_VPERM2F128SI256,
19539 IX86_BUILTIN_VBROADCASTSS,
19540 IX86_BUILTIN_VBROADCASTSD256,
19541 IX86_BUILTIN_VBROADCASTSS256,
19542 IX86_BUILTIN_VBROADCASTPD256,
19543 IX86_BUILTIN_VBROADCASTPS256,
19544 IX86_BUILTIN_VINSERTF128PD256,
19545 IX86_BUILTIN_VINSERTF128PS256,
19546 IX86_BUILTIN_VINSERTF128SI256,
19547 IX86_BUILTIN_LOADUPD256,
19548 IX86_BUILTIN_LOADUPS256,
19549 IX86_BUILTIN_STOREUPD256,
19550 IX86_BUILTIN_STOREUPS256,
19551 IX86_BUILTIN_LDDQU256,
19552 IX86_BUILTIN_LOADDQU256,
19553 IX86_BUILTIN_STOREDQU256,
19554 IX86_BUILTIN_MASKLOADPD,
19555 IX86_BUILTIN_MASKLOADPS,
19556 IX86_BUILTIN_MASKSTOREPD,
19557 IX86_BUILTIN_MASKSTOREPS,
19558 IX86_BUILTIN_MASKLOADPD256,
19559 IX86_BUILTIN_MASKLOADPS256,
19560 IX86_BUILTIN_MASKSTOREPD256,
19561 IX86_BUILTIN_MASKSTOREPS256,
19562 IX86_BUILTIN_MOVSHDUP256,
19563 IX86_BUILTIN_MOVSLDUP256,
19564 IX86_BUILTIN_MOVDDUP256,
19566 IX86_BUILTIN_SQRTPD256,
19567 IX86_BUILTIN_SQRTPS256,
19568 IX86_BUILTIN_SQRTPS_NR256,
19569 IX86_BUILTIN_RSQRTPS256,
19570 IX86_BUILTIN_RSQRTPS_NR256,
19572 IX86_BUILTIN_RCPPS256,
19574 IX86_BUILTIN_ROUNDPD256,
19575 IX86_BUILTIN_ROUNDPS256,
19577 IX86_BUILTIN_UNPCKHPD256,
19578 IX86_BUILTIN_UNPCKLPD256,
19579 IX86_BUILTIN_UNPCKHPS256,
19580 IX86_BUILTIN_UNPCKLPS256,
19582 IX86_BUILTIN_SI256_SI,
19583 IX86_BUILTIN_PS256_PS,
19584 IX86_BUILTIN_PD256_PD,
19585 IX86_BUILTIN_SI_SI256,
19586 IX86_BUILTIN_PS_PS256,
19587 IX86_BUILTIN_PD_PD256,
19589 IX86_BUILTIN_VTESTZPD,
19590 IX86_BUILTIN_VTESTCPD,
19591 IX86_BUILTIN_VTESTNZCPD,
19592 IX86_BUILTIN_VTESTZPS,
19593 IX86_BUILTIN_VTESTCPS,
19594 IX86_BUILTIN_VTESTNZCPS,
19595 IX86_BUILTIN_VTESTZPD256,
19596 IX86_BUILTIN_VTESTCPD256,
19597 IX86_BUILTIN_VTESTNZCPD256,
19598 IX86_BUILTIN_VTESTZPS256,
19599 IX86_BUILTIN_VTESTCPS256,
19600 IX86_BUILTIN_VTESTNZCPS256,
19601 IX86_BUILTIN_PTESTZ256,
19602 IX86_BUILTIN_PTESTC256,
19603 IX86_BUILTIN_PTESTNZC256,
19605 IX86_BUILTIN_MOVMSKPD256,
19606 IX86_BUILTIN_MOVMSKPS256,
19608 /* TFmode support builtins. */
19609 IX86_BUILTIN_INFQ,
19610 IX86_BUILTIN_FABSQ,
19611 IX86_BUILTIN_COPYSIGNQ,
19613 /* SSE5 instructions */
19614 IX86_BUILTIN_FMADDSS,
19615 IX86_BUILTIN_FMADDSD,
19616 IX86_BUILTIN_FMADDPS,
19617 IX86_BUILTIN_FMADDPD,
19618 IX86_BUILTIN_FMSUBSS,
19619 IX86_BUILTIN_FMSUBSD,
19620 IX86_BUILTIN_FMSUBPS,
19621 IX86_BUILTIN_FMSUBPD,
19622 IX86_BUILTIN_FNMADDSS,
19623 IX86_BUILTIN_FNMADDSD,
19624 IX86_BUILTIN_FNMADDPS,
19625 IX86_BUILTIN_FNMADDPD,
19626 IX86_BUILTIN_FNMSUBSS,
19627 IX86_BUILTIN_FNMSUBSD,
19628 IX86_BUILTIN_FNMSUBPS,
19629 IX86_BUILTIN_FNMSUBPD,
19630 IX86_BUILTIN_PCMOV,
19631 IX86_BUILTIN_PCMOV_V2DI,
19632 IX86_BUILTIN_PCMOV_V4SI,
19633 IX86_BUILTIN_PCMOV_V8HI,
19634 IX86_BUILTIN_PCMOV_V16QI,
19635 IX86_BUILTIN_PCMOV_V4SF,
19636 IX86_BUILTIN_PCMOV_V2DF,
19637 IX86_BUILTIN_PPERM,
19638 IX86_BUILTIN_PERMPS,
19639 IX86_BUILTIN_PERMPD,
19640 IX86_BUILTIN_PMACSSWW,
19641 IX86_BUILTIN_PMACSWW,
19642 IX86_BUILTIN_PMACSSWD,
19643 IX86_BUILTIN_PMACSWD,
19644 IX86_BUILTIN_PMACSSDD,
19645 IX86_BUILTIN_PMACSDD,
19646 IX86_BUILTIN_PMACSSDQL,
19647 IX86_BUILTIN_PMACSSDQH,
19648 IX86_BUILTIN_PMACSDQL,
19649 IX86_BUILTIN_PMACSDQH,
19650 IX86_BUILTIN_PMADCSSWD,
19651 IX86_BUILTIN_PMADCSWD,
19652 IX86_BUILTIN_PHADDBW,
19653 IX86_BUILTIN_PHADDBD,
19654 IX86_BUILTIN_PHADDBQ,
19655 IX86_BUILTIN_PHADDWD,
19656 IX86_BUILTIN_PHADDWQ,
19657 IX86_BUILTIN_PHADDDQ,
19658 IX86_BUILTIN_PHADDUBW,
19659 IX86_BUILTIN_PHADDUBD,
19660 IX86_BUILTIN_PHADDUBQ,
19661 IX86_BUILTIN_PHADDUWD,
19662 IX86_BUILTIN_PHADDUWQ,
19663 IX86_BUILTIN_PHADDUDQ,
19664 IX86_BUILTIN_PHSUBBW,
19665 IX86_BUILTIN_PHSUBWD,
19666 IX86_BUILTIN_PHSUBDQ,
19667 IX86_BUILTIN_PROTB,
19668 IX86_BUILTIN_PROTW,
19669 IX86_BUILTIN_PROTD,
19670 IX86_BUILTIN_PROTQ,
19671 IX86_BUILTIN_PROTB_IMM,
19672 IX86_BUILTIN_PROTW_IMM,
19673 IX86_BUILTIN_PROTD_IMM,
19674 IX86_BUILTIN_PROTQ_IMM,
19675 IX86_BUILTIN_PSHLB,
19676 IX86_BUILTIN_PSHLW,
19677 IX86_BUILTIN_PSHLD,
19678 IX86_BUILTIN_PSHLQ,
19679 IX86_BUILTIN_PSHAB,
19680 IX86_BUILTIN_PSHAW,
19681 IX86_BUILTIN_PSHAD,
19682 IX86_BUILTIN_PSHAQ,
19683 IX86_BUILTIN_FRCZSS,
19684 IX86_BUILTIN_FRCZSD,
19685 IX86_BUILTIN_FRCZPS,
19686 IX86_BUILTIN_FRCZPD,
19687 IX86_BUILTIN_CVTPH2PS,
19688 IX86_BUILTIN_CVTPS2PH,
19690 IX86_BUILTIN_COMEQSS,
19691 IX86_BUILTIN_COMNESS,
19692 IX86_BUILTIN_COMLTSS,
19693 IX86_BUILTIN_COMLESS,
19694 IX86_BUILTIN_COMGTSS,
19695 IX86_BUILTIN_COMGESS,
19696 IX86_BUILTIN_COMUEQSS,
19697 IX86_BUILTIN_COMUNESS,
19698 IX86_BUILTIN_COMULTSS,
19699 IX86_BUILTIN_COMULESS,
19700 IX86_BUILTIN_COMUGTSS,
19701 IX86_BUILTIN_COMUGESS,
19702 IX86_BUILTIN_COMORDSS,
19703 IX86_BUILTIN_COMUNORDSS,
19704 IX86_BUILTIN_COMFALSESS,
19705 IX86_BUILTIN_COMTRUESS,
19707 IX86_BUILTIN_COMEQSD,
19708 IX86_BUILTIN_COMNESD,
19709 IX86_BUILTIN_COMLTSD,
19710 IX86_BUILTIN_COMLESD,
19711 IX86_BUILTIN_COMGTSD,
19712 IX86_BUILTIN_COMGESD,
19713 IX86_BUILTIN_COMUEQSD,
19714 IX86_BUILTIN_COMUNESD,
19715 IX86_BUILTIN_COMULTSD,
19716 IX86_BUILTIN_COMULESD,
19717 IX86_BUILTIN_COMUGTSD,
19718 IX86_BUILTIN_COMUGESD,
19719 IX86_BUILTIN_COMORDSD,
19720 IX86_BUILTIN_COMUNORDSD,
19721 IX86_BUILTIN_COMFALSESD,
19722 IX86_BUILTIN_COMTRUESD,
19724 IX86_BUILTIN_COMEQPS,
19725 IX86_BUILTIN_COMNEPS,
19726 IX86_BUILTIN_COMLTPS,
19727 IX86_BUILTIN_COMLEPS,
19728 IX86_BUILTIN_COMGTPS,
19729 IX86_BUILTIN_COMGEPS,
19730 IX86_BUILTIN_COMUEQPS,
19731 IX86_BUILTIN_COMUNEPS,
19732 IX86_BUILTIN_COMULTPS,
19733 IX86_BUILTIN_COMULEPS,
19734 IX86_BUILTIN_COMUGTPS,
19735 IX86_BUILTIN_COMUGEPS,
19736 IX86_BUILTIN_COMORDPS,
19737 IX86_BUILTIN_COMUNORDPS,
19738 IX86_BUILTIN_COMFALSEPS,
19739 IX86_BUILTIN_COMTRUEPS,
19741 IX86_BUILTIN_COMEQPD,
19742 IX86_BUILTIN_COMNEPD,
19743 IX86_BUILTIN_COMLTPD,
19744 IX86_BUILTIN_COMLEPD,
19745 IX86_BUILTIN_COMGTPD,
19746 IX86_BUILTIN_COMGEPD,
19747 IX86_BUILTIN_COMUEQPD,
19748 IX86_BUILTIN_COMUNEPD,
19749 IX86_BUILTIN_COMULTPD,
19750 IX86_BUILTIN_COMULEPD,
19751 IX86_BUILTIN_COMUGTPD,
19752 IX86_BUILTIN_COMUGEPD,
19753 IX86_BUILTIN_COMORDPD,
19754 IX86_BUILTIN_COMUNORDPD,
19755 IX86_BUILTIN_COMFALSEPD,
19756 IX86_BUILTIN_COMTRUEPD,
19758 IX86_BUILTIN_PCOMEQUB,
19759 IX86_BUILTIN_PCOMNEUB,
19760 IX86_BUILTIN_PCOMLTUB,
19761 IX86_BUILTIN_PCOMLEUB,
19762 IX86_BUILTIN_PCOMGTUB,
19763 IX86_BUILTIN_PCOMGEUB,
19764 IX86_BUILTIN_PCOMFALSEUB,
19765 IX86_BUILTIN_PCOMTRUEUB,
19766 IX86_BUILTIN_PCOMEQUW,
19767 IX86_BUILTIN_PCOMNEUW,
19768 IX86_BUILTIN_PCOMLTUW,
19769 IX86_BUILTIN_PCOMLEUW,
19770 IX86_BUILTIN_PCOMGTUW,
19771 IX86_BUILTIN_PCOMGEUW,
19772 IX86_BUILTIN_PCOMFALSEUW,
19773 IX86_BUILTIN_PCOMTRUEUW,
19774 IX86_BUILTIN_PCOMEQUD,
19775 IX86_BUILTIN_PCOMNEUD,
19776 IX86_BUILTIN_PCOMLTUD,
19777 IX86_BUILTIN_PCOMLEUD,
19778 IX86_BUILTIN_PCOMGTUD,
19779 IX86_BUILTIN_PCOMGEUD,
19780 IX86_BUILTIN_PCOMFALSEUD,
19781 IX86_BUILTIN_PCOMTRUEUD,
19782 IX86_BUILTIN_PCOMEQUQ,
19783 IX86_BUILTIN_PCOMNEUQ,
19784 IX86_BUILTIN_PCOMLTUQ,
19785 IX86_BUILTIN_PCOMLEUQ,
19786 IX86_BUILTIN_PCOMGTUQ,
19787 IX86_BUILTIN_PCOMGEUQ,
19788 IX86_BUILTIN_PCOMFALSEUQ,
19789 IX86_BUILTIN_PCOMTRUEUQ,
19791 IX86_BUILTIN_PCOMEQB,
19792 IX86_BUILTIN_PCOMNEB,
19793 IX86_BUILTIN_PCOMLTB,
19794 IX86_BUILTIN_PCOMLEB,
19795 IX86_BUILTIN_PCOMGTB,
19796 IX86_BUILTIN_PCOMGEB,
19797 IX86_BUILTIN_PCOMFALSEB,
19798 IX86_BUILTIN_PCOMTRUEB,
19799 IX86_BUILTIN_PCOMEQW,
19800 IX86_BUILTIN_PCOMNEW,
19801 IX86_BUILTIN_PCOMLTW,
19802 IX86_BUILTIN_PCOMLEW,
19803 IX86_BUILTIN_PCOMGTW,
19804 IX86_BUILTIN_PCOMGEW,
19805 IX86_BUILTIN_PCOMFALSEW,
19806 IX86_BUILTIN_PCOMTRUEW,
19807 IX86_BUILTIN_PCOMEQD,
19808 IX86_BUILTIN_PCOMNED,
19809 IX86_BUILTIN_PCOMLTD,
19810 IX86_BUILTIN_PCOMLED,
19811 IX86_BUILTIN_PCOMGTD,
19812 IX86_BUILTIN_PCOMGED,
19813 IX86_BUILTIN_PCOMFALSED,
19814 IX86_BUILTIN_PCOMTRUED,
19815 IX86_BUILTIN_PCOMEQQ,
19816 IX86_BUILTIN_PCOMNEQ,
19817 IX86_BUILTIN_PCOMLTQ,
19818 IX86_BUILTIN_PCOMLEQ,
19819 IX86_BUILTIN_PCOMGTQ,
19820 IX86_BUILTIN_PCOMGEQ,
19821 IX86_BUILTIN_PCOMFALSEQ,
19822 IX86_BUILTIN_PCOMTRUEQ,
19824 IX86_BUILTIN_MAX
19825 };
19827 /* Table for the ix86 builtin decls. */
19830 /* Table of all of the builtin functions that are possible with different ISA's
19831 but are waiting to be built until a function is declared to use that
19832 ISA. */
19834 {
19839 };
19844 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
19845 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
19846 * function decl in the ix86_builtins array. Returns the function decl or
19847 * NULL_TREE, if the builtin was not added.
19848 *
19849 * If the front end has a special hook for builtin functions, delay adding
19850 * builtin functions that aren't in the current ISA until the ISA is changed
19851 * with function specific optimization. Doing so, can save about 300K for the
19852 * default compiler. When the builtin is expanded, check at that time whether
19853 * it is valid.
19854 *
19855 * If the front end doesn't have a special hook, record all builtins, even if
19856 * it isn't an instruction set in the current ISA in case the user uses
19857 * function specific options for a different ISA, so that we don't get scope
19858 * errors if a builtin is added in the middle of a function scope. */
19862 {
19866 {
19873 {
19875 NULL_TREE);
19878 }
19879 else
19880 {
19885 }
19886 }
19889 }
19891 /* Like def_builtin, but also marks the function decl "const". */
19896 {
19900 else
19904 }
19906 /* Add any new builtin functions for a given ISA that may not have been
19907 declared. This saves a bit of space compared to adding all of the
19908 declarations to the tree, even if we didn't use them. */
19910 static void
19912 {
19914 tree decl;
19917 {
19920 {
19924 NULL_TREE);
19930 }
19931 }
19932 }
19934 /* Bits for builtin_description.flag. */
19936 /* Set when we don't support the comparison natively, and should
19937 swap_comparison in order to support it. */
19938 #define BUILTIN_DESC_SWAP_OPERANDS 1
19940 struct builtin_description
19941 {
19948 };
19951 {
19952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
19953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
19954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
19955 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
19956 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
19957 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
19958 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
19959 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
19960 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
19961 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
19962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
19963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
19964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
19965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
19966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
19967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
19968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
19969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
19970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
19971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
19972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
19973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
19974 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
19975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
19976 };
19979 {
19980 /* SSE4.2 */
19981 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
19982 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
19983 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
19984 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
19985 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
19986 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
19987 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
19988 };
19991 {
19992 /* SSE4.2 */
19993 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
19994 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
19995 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
19996 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
19997 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
19998 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
19999 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20000 };
20002 /* Special builtin types */
20003 enum ix86_special_builtin_type
20004 {
20005 SPECIAL_FTYPE_UNKNOWN,
20006 VOID_FTYPE_VOID,
20007 V32QI_FTYPE_PCCHAR,
20008 V16QI_FTYPE_PCCHAR,
20009 V8SF_FTYPE_PCV4SF,
20010 V8SF_FTYPE_PCFLOAT,
20011 V4DF_FTYPE_PCV2DF,
20012 V4DF_FTYPE_PCDOUBLE,
20013 V4SF_FTYPE_PCFLOAT,
20014 V2DF_FTYPE_PCDOUBLE,
20015 V8SF_FTYPE_PCV8SF_V8SF,
20016 V4DF_FTYPE_PCV4DF_V4DF,
20017 V4SF_FTYPE_V4SF_PCV2SF,
20018 V4SF_FTYPE_PCV4SF_V4SF,
20019 V2DF_FTYPE_V2DF_PCDOUBLE,
20020 V2DF_FTYPE_PCV2DF_V2DF,
20021 V2DI_FTYPE_PV2DI,
20022 VOID_FTYPE_PV2SF_V4SF,
20023 VOID_FTYPE_PV2DI_V2DI,
20024 VOID_FTYPE_PCHAR_V32QI,
20025 VOID_FTYPE_PCHAR_V16QI,
20026 VOID_FTYPE_PFLOAT_V8SF,
20027 VOID_FTYPE_PFLOAT_V4SF,
20028 VOID_FTYPE_PDOUBLE_V4DF,
20029 VOID_FTYPE_PDOUBLE_V2DF,
20030 VOID_FTYPE_PDI_DI,
20031 VOID_FTYPE_PINT_INT,
20032 VOID_FTYPE_PV8SF_V8SF_V8SF,
20033 VOID_FTYPE_PV4DF_V4DF_V4DF,
20034 VOID_FTYPE_PV4SF_V4SF_V4SF,
20035 VOID_FTYPE_PV2DF_V2DF_V2DF
20036 };
20038 /* Builtin types */
20039 enum ix86_builtin_type
20040 {
20041 FTYPE_UNKNOWN,
20042 FLOAT128_FTYPE_FLOAT128,
20043 FLOAT_FTYPE_FLOAT,
20044 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20045 INT_FTYPE_V8SF_V8SF_PTEST,
20046 INT_FTYPE_V4DI_V4DI_PTEST,
20047 INT_FTYPE_V4DF_V4DF_PTEST,
20048 INT_FTYPE_V4SF_V4SF_PTEST,
20049 INT_FTYPE_V2DI_V2DI_PTEST,
20050 INT_FTYPE_V2DF_V2DF_PTEST,
20051 INT64_FTYPE_V4SF,
20052 INT64_FTYPE_V2DF,
20053 INT_FTYPE_V16QI,
20054 INT_FTYPE_V8QI,
20055 INT_FTYPE_V8SF,
20056 INT_FTYPE_V4DF,
20057 INT_FTYPE_V4SF,
20058 INT_FTYPE_V2DF,
20059 V16QI_FTYPE_V16QI,
20060 V8SI_FTYPE_V8SF,
20061 V8SI_FTYPE_V4SI,
20062 V8HI_FTYPE_V8HI,
20063 V8HI_FTYPE_V16QI,
20064 V8QI_FTYPE_V8QI,
20065 V8SF_FTYPE_V8SF,
20066 V8SF_FTYPE_V8SI,
20067 V8SF_FTYPE_V4SF,
20068 V4SI_FTYPE_V4SI,
20069 V4SI_FTYPE_V16QI,
20070 V4SI_FTYPE_V8SI,
20071 V4SI_FTYPE_V8HI,
20072 V4SI_FTYPE_V4DF,
20073 V4SI_FTYPE_V4SF,
20074 V4SI_FTYPE_V2DF,
20075 V4HI_FTYPE_V4HI,
20076 V4DF_FTYPE_V4DF,
20077 V4DF_FTYPE_V4SI,
20078 V4DF_FTYPE_V4SF,
20079 V4DF_FTYPE_V2DF,
20080 V4SF_FTYPE_V4DF,
20081 V4SF_FTYPE_V4SF,
20082 V4SF_FTYPE_V4SF_VEC_MERGE,
20083 V4SF_FTYPE_V8SF,
20084 V4SF_FTYPE_V4SI,
20085 V4SF_FTYPE_V2DF,
20086 V2DI_FTYPE_V2DI,
20087 V2DI_FTYPE_V16QI,
20088 V2DI_FTYPE_V8HI,
20089 V2DI_FTYPE_V4SI,
20090 V2DF_FTYPE_V2DF,
20091 V2DF_FTYPE_V2DF_VEC_MERGE,
20092 V2DF_FTYPE_V4SI,
20093 V2DF_FTYPE_V4DF,
20094 V2DF_FTYPE_V4SF,
20095 V2DF_FTYPE_V2SI,
20096 V2SI_FTYPE_V2SI,
20097 V2SI_FTYPE_V4SF,
20098 V2SI_FTYPE_V2SF,
20099 V2SI_FTYPE_V2DF,
20100 V2SF_FTYPE_V2SF,
20101 V2SF_FTYPE_V2SI,
20102 V16QI_FTYPE_V16QI_V16QI,
20103 V16QI_FTYPE_V8HI_V8HI,
20104 V8QI_FTYPE_V8QI_V8QI,
20105 V8QI_FTYPE_V4HI_V4HI,
20106 V8HI_FTYPE_V8HI_V8HI,
20107 V8HI_FTYPE_V8HI_V8HI_COUNT,
20108 V8HI_FTYPE_V16QI_V16QI,
20109 V8HI_FTYPE_V4SI_V4SI,
20110 V8HI_FTYPE_V8HI_SI_COUNT,
20111 V8SF_FTYPE_V8SF_V8SF,
20112 V8SF_FTYPE_V8SF_V8SI,
20113 V4SI_FTYPE_V4SI_V4SI,
20114 V4SI_FTYPE_V4SI_V4SI_COUNT,
20115 V4SI_FTYPE_V8HI_V8HI,
20116 V4SI_FTYPE_V4SF_V4SF,
20117 V4SI_FTYPE_V2DF_V2DF,
20118 V4SI_FTYPE_V4SI_SI_COUNT,
20119 V4HI_FTYPE_V4HI_V4HI,
20120 V4HI_FTYPE_V4HI_V4HI_COUNT,
20121 V4HI_FTYPE_V8QI_V8QI,
20122 V4HI_FTYPE_V2SI_V2SI,
20123 V4HI_FTYPE_V4HI_SI_COUNT,
20124 V4DF_FTYPE_V4DF_V4DF,
20125 V4DF_FTYPE_V4DF_V4DI,
20126 V4SF_FTYPE_V4SF_V4SF,
20127 V4SF_FTYPE_V4SF_V4SF_SWAP,
20128 V4SF_FTYPE_V4SF_V4SI,
20129 V4SF_FTYPE_V4SF_V2SI,
20130 V4SF_FTYPE_V4SF_V2DF,
20131 V4SF_FTYPE_V4SF_DI,
20132 V4SF_FTYPE_V4SF_SI,
20133 V2DI_FTYPE_V2DI_V2DI,
20134 V2DI_FTYPE_V2DI_V2DI_COUNT,
20135 V2DI_FTYPE_V16QI_V16QI,
20136 V2DI_FTYPE_V4SI_V4SI,
20137 V2DI_FTYPE_V2DI_V16QI,
20138 V2DI_FTYPE_V2DF_V2DF,
20139 V2DI_FTYPE_V2DI_SI_COUNT,
20140 V2SI_FTYPE_V2SI_V2SI,
20141 V2SI_FTYPE_V2SI_V2SI_COUNT,
20142 V2SI_FTYPE_V4HI_V4HI,
20143 V2SI_FTYPE_V2SF_V2SF,
20144 V2SI_FTYPE_V2SI_SI_COUNT,
20145 V2DF_FTYPE_V2DF_V2DF,
20146 V2DF_FTYPE_V2DF_V2DF_SWAP,
20147 V2DF_FTYPE_V2DF_V4SF,
20148 V2DF_FTYPE_V2DF_V2DI,
20149 V2DF_FTYPE_V2DF_DI,
20150 V2DF_FTYPE_V2DF_SI,
20151 V2SF_FTYPE_V2SF_V2SF,
20152 V1DI_FTYPE_V1DI_V1DI,
20153 V1DI_FTYPE_V1DI_V1DI_COUNT,
20154 V1DI_FTYPE_V8QI_V8QI,
20155 V1DI_FTYPE_V2SI_V2SI,
20156 V1DI_FTYPE_V1DI_SI_COUNT,
20157 UINT64_FTYPE_UINT64_UINT64,
20158 UINT_FTYPE_UINT_UINT,
20159 UINT_FTYPE_UINT_USHORT,
20160 UINT_FTYPE_UINT_UCHAR,
20161 V8HI_FTYPE_V8HI_INT,
20162 V4SI_FTYPE_V4SI_INT,
20163 V4HI_FTYPE_V4HI_INT,
20164 V8SF_FTYPE_V8SF_INT,
20165 V4SI_FTYPE_V8SI_INT,
20166 V4SF_FTYPE_V8SF_INT,
20167 V2DF_FTYPE_V4DF_INT,
20168 V4DF_FTYPE_V4DF_INT,
20169 V4SF_FTYPE_V4SF_INT,
20170 V2DI_FTYPE_V2DI_INT,
20171 V2DI2TI_FTYPE_V2DI_INT,
20172 V2DF_FTYPE_V2DF_INT,
20173 V16QI_FTYPE_V16QI_V16QI_V16QI,
20174 V8SF_FTYPE_V8SF_V8SF_V8SF,
20175 V4DF_FTYPE_V4DF_V4DF_V4DF,
20176 V4SF_FTYPE_V4SF_V4SF_V4SF,
20177 V2DF_FTYPE_V2DF_V2DF_V2DF,
20178 V16QI_FTYPE_V16QI_V16QI_INT,
20179 V8SI_FTYPE_V8SI_V8SI_INT,
20180 V8SI_FTYPE_V8SI_V4SI_INT,
20181 V8HI_FTYPE_V8HI_V8HI_INT,
20182 V8SF_FTYPE_V8SF_V8SF_INT,
20183 V8SF_FTYPE_V8SF_V4SF_INT,
20184 V4SI_FTYPE_V4SI_V4SI_INT,
20185 V4DF_FTYPE_V4DF_V4DF_INT,
20186 V4DF_FTYPE_V4DF_V2DF_INT,
20187 V4SF_FTYPE_V4SF_V4SF_INT,
20188 V2DI_FTYPE_V2DI_V2DI_INT,
20189 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20190 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20191 V2DF_FTYPE_V2DF_V2DF_INT,
20192 V8SF_FTYPE_V8SF_V8SF_V8SI_INT,
20193 V4DF_FTYPE_V4DF_V4DF_V4DI_INT,
20194 V4SF_FTYPE_V4SF_V4SF_V4SI_INT,
20195 V2DF_FTYPE_V2DF_V2DF_V2DI_INT,
20196 V2DI_FTYPE_V2DI_UINT_UINT,
20197 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20198 };
20200 /* Special builtins with variable number of arguments. */
20202 {
20203 /* MMX */
20204 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20206 /* 3DNow! */
20207 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20209 /* SSE */
20210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20219 /* SSE or 3DNow!A */
20220 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20221 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20223 /* SSE2 */
20224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20237 /* SSE3 */
20238 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20240 /* SSE4.1 */
20241 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20243 /* SSE4A */
20244 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20245 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20247 /* AVX */
20248 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20249 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20250 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20255 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20258 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20262 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20263 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20266 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20267 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20268 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20269 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20270 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20271 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20272 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20273 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20274 };
20276 /* Builtins with variable number of arguments. */
20278 {
20279 /* MMX */
20280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20282 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20305 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20308 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20333 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20343 /* 3DNow! */
20344 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20345 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20346 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20347 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20349 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20350 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20353 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20355 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20356 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20357 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20358 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20359 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20361 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20362 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20363 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20365 /* 3DNow!A */
20366 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20367 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20368 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20369 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20370 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20371 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20373 /* SSE */
20374 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20376 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20378 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20379 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20382 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20385 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20389 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20390 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20391 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20395 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20396 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
20409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
20415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
20416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
20417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
20419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
20421 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20422 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20423 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20424 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20426 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20428 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20429 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
20438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
20439 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
20441 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
20443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
20447 /* SSE MMX or 3Dnow!A */
20448 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20449 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20450 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20452 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20453 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20454 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20455 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20457 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
20458 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
20460 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
20462 /* SSE2 */
20463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
20466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
20467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
20468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
20469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
20471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
20474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
20475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
20477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
20479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
20481 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20482 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
20484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
20486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
20488 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20489 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20490 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20491 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
20502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
20508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
20510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
20511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
20512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
20514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
20515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
20516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
20518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20519 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20523 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20525 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20526 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20532 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
20534 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20535 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20536 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20537 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20538 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20539 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20540 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20541 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20546 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20547 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20552 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20553 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
20555 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20557 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20558 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20560 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20563 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20570 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20571 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20572 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
20588 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
20591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
20592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20594 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
20596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
20597 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
20598 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
20599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
20601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20602 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20603 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20604 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20605 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20606 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20607 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
20610 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20611 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20612 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
20613 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20614 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20615 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
20617 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
20618 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
20619 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
20620 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
20622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
20623 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
20626 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
20628 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
20629 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
20631 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20633 /* SSE2 MMX */
20634 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20635 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
20637 /* SSE3 */
20638 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
20639 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20641 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20642 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20643 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20644 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20645 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20646 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
20648 /* SSSE3 */
20649 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
20650 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
20651 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20652 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
20653 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
20654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
20669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
20670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20671 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20672 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20675 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20676 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20677 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20678 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20681 /* SSSE3. */
20682 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
20683 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
20685 /* SSE4.1 */
20686 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20687 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20688 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
20689 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
20690 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
20694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
20695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
20697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20701 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
20704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
20705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
20706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
20707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
20708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
20709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
20711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
20712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20714 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20715 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20717 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
20718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
20721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
20722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
20724 /* SSE4.1 and SSE5 */
20725 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20726 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20727 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20728 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20730 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20731 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
20734 /* SSE4.2 */
20735 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20736 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
20737 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
20738 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
20739 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
20741 /* SSE4A */
20742 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
20743 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
20744 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
20745 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20747 /* AES */
20748 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
20749 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
20751 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20752 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20753 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20754 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
20756 /* PCLMUL */
20757 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
20759 /* AVX */
20760 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20761 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20763 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20764 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20765 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20768 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20769 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20774 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20775 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20776 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20777 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20778 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20779 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20780 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20781 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20782 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20783 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20784 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20785 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
20788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
20789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
20790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
20792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
20795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
20796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
20802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
20806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
20807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
20808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
20809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
20810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
20811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
20813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
20815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
20816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
20817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
20818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
20819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
20820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
20821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT },
20824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT },
20825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT },
20826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT },
20827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
20828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
20829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
20831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20835 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
20836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20837 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20839 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
20843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
20844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
20846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
20848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
20851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
20855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
20856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
20858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
20861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
20864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
20867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
20870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
20874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
20875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
20876 };
20878 /* SSE5 */
20880 MULTI_ARG_UNKNOWN,
20881 MULTI_ARG_3_SF,
20882 MULTI_ARG_3_DF,
20883 MULTI_ARG_3_DI,
20884 MULTI_ARG_3_SI,
20885 MULTI_ARG_3_SI_DI,
20886 MULTI_ARG_3_HI,
20887 MULTI_ARG_3_HI_SI,
20888 MULTI_ARG_3_QI,
20889 MULTI_ARG_3_PERMPS,
20890 MULTI_ARG_3_PERMPD,
20891 MULTI_ARG_2_SF,
20892 MULTI_ARG_2_DF,
20893 MULTI_ARG_2_DI,
20894 MULTI_ARG_2_SI,
20895 MULTI_ARG_2_HI,
20896 MULTI_ARG_2_QI,
20897 MULTI_ARG_2_DI_IMM,
20898 MULTI_ARG_2_SI_IMM,
20899 MULTI_ARG_2_HI_IMM,
20900 MULTI_ARG_2_QI_IMM,
20901 MULTI_ARG_2_SF_CMP,
20902 MULTI_ARG_2_DF_CMP,
20903 MULTI_ARG_2_DI_CMP,
20904 MULTI_ARG_2_SI_CMP,
20905 MULTI_ARG_2_HI_CMP,
20906 MULTI_ARG_2_QI_CMP,
20907 MULTI_ARG_2_DI_TF,
20908 MULTI_ARG_2_SI_TF,
20909 MULTI_ARG_2_HI_TF,
20910 MULTI_ARG_2_QI_TF,
20911 MULTI_ARG_2_SF_TF,
20912 MULTI_ARG_2_DF_TF,
20913 MULTI_ARG_1_SF,
20914 MULTI_ARG_1_DF,
20915 MULTI_ARG_1_DI,
20916 MULTI_ARG_1_SI,
20917 MULTI_ARG_1_HI,
20918 MULTI_ARG_1_QI,
20919 MULTI_ARG_1_SI_DI,
20920 MULTI_ARG_1_HI_DI,
20921 MULTI_ARG_1_HI_SI,
20922 MULTI_ARG_1_QI_DI,
20923 MULTI_ARG_1_QI_SI,
20924 MULTI_ARG_1_QI_HI,
20925 MULTI_ARG_1_PH2PS,
20926 MULTI_ARG_1_PS2PH
20927 };
20930 {
20931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
20932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
20933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
20934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
20935 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
20936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
20937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
20938 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
20939 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
20940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
20941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
20942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
20943 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
20944 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
20945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
20946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
20947 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
20948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
20949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
20950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
20951 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
20952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
20953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
20954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
20955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
20956 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
20957 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
20958 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
20959 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20960 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
20961 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
20962 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
20963 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20964 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20965 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20966 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
20969 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
20970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
20971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
20972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
20973 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
20974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
20975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
20976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
20977 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
20978 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
20979 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
20980 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
20981 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
20982 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
20983 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
20984 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
20985 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
20986 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
20987 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
20988 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
20989 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
20990 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
20991 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
20992 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
20993 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
20994 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
20995 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
20996 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
20997 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
20998 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
20999 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21000 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21001 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21002 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21003 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21004 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21005 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21007 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21008 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21009 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21010 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21011 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21012 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21013 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21014 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21015 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21016 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21017 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21018 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21019 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21020 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21021 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21022 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21024 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21025 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21026 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21027 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21028 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21029 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21030 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21031 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21032 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21033 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21034 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21035 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21036 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21037 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21038 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21054 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21059 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21063 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21065 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21072 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21073 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21076 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21081 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21083 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21084 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21085 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21086 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21087 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21088 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21089 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21091 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21092 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21093 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21094 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21095 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21096 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21097 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21099 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21100 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21101 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21102 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21103 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21104 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21105 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21107 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21108 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21109 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21110 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21111 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21112 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21113 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21115 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21116 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21117 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21118 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21119 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21120 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21121 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21123 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21124 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21125 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21126 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21127 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21128 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21129 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21131 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21132 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21133 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21134 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21135 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21136 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21137 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21139 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21140 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21141 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21142 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21143 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21144 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21145 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21146 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21148 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21149 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21150 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21151 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21152 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21153 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21154 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21155 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21157 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21158 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21159 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21160 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21161 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21162 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21163 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21164 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21165 };
21167 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21168 in the current target ISA to allow the user to compile particular modules
21169 with different target specific options that differ from the command line
21170 options. */
21171 static void
21173 {
21179 tree V1DI_type_node
21182 tree V2DI_type_node
21192 tree pcchar_type_node
21195 tree pcfloat_type_node
21198 tree pcv2sf_type_node
21203 /* Comparisons. */
21204 tree int_ftype_v4sf_v4sf
21207 tree v4si_ftype_v4sf_v4sf
21210 /* MMX/SSE/integer conversions. */
21211 tree int_ftype_v4sf
21214 tree int64_ftype_v4sf
21217 tree int_ftype_v8qi
21219 tree v4sf_ftype_v4sf_int
21222 tree v4sf_ftype_v4sf_int64
21225 NULL_TREE);
21226 tree v4sf_ftype_v4sf_v2si
21230 /* Miscellaneous. */
21231 tree v8qi_ftype_v4hi_v4hi
21234 tree v4hi_ftype_v2si_v2si
21237 tree v4sf_ftype_v4sf_v4sf_int
21241 tree v2si_ftype_v4hi_v4hi
21244 tree v4hi_ftype_v4hi_int
21247 tree v2si_ftype_v2si_int
21250 tree v1di_ftype_v1di_int
21254 tree void_ftype_void
21256 tree void_ftype_unsigned
21258 tree void_ftype_unsigned_unsigned
21261 tree void_ftype_pcvoid_unsigned_unsigned
21264 NULL_TREE);
21265 tree unsigned_ftype_void
21267 tree v2si_ftype_v4sf
21269 /* Loads/stores. */
21270 tree void_ftype_v8qi_v8qi_pchar
21274 tree v4sf_ftype_pcfloat
21276 tree v4sf_ftype_v4sf_pcv2sf
21279 tree void_ftype_pv2sf_v4sf
21282 tree void_ftype_pfloat_v4sf
21285 tree void_ftype_pdi_di
21288 NULL_TREE);
21289 tree void_ftype_pv2di_v2di
21292 /* Normal vector unops. */
21293 tree v4sf_ftype_v4sf
21295 tree v16qi_ftype_v16qi
21297 tree v8hi_ftype_v8hi
21299 tree v4si_ftype_v4si
21301 tree v8qi_ftype_v8qi
21303 tree v4hi_ftype_v4hi
21306 /* Normal vector binops. */
21307 tree v4sf_ftype_v4sf_v4sf
21310 tree v8qi_ftype_v8qi_v8qi
21313 tree v4hi_ftype_v4hi_v4hi
21316 tree v2si_ftype_v2si_v2si
21319 tree v1di_ftype_v1di_v1di
21322 tree v1di_ftype_v1di_v1di_int
21326 tree v2si_ftype_v2sf
21328 tree v2sf_ftype_v2si
21330 tree v2si_ftype_v2si
21332 tree v2sf_ftype_v2sf
21334 tree v2sf_ftype_v2sf_v2sf
21337 tree v2si_ftype_v2sf_v2sf
21344 tree int_ftype_v2df_v2df
21348 tree void_ftype_pcvoid
21350 tree v4sf_ftype_v4si
21352 tree v4si_ftype_v4sf
21354 tree v2df_ftype_v4si
21356 tree v4si_ftype_v2df
21358 tree v4si_ftype_v2df_v2df
21361 tree v2si_ftype_v2df
21363 tree v4sf_ftype_v2df
21365 tree v2df_ftype_v2si
21367 tree v2df_ftype_v4sf
21369 tree int_ftype_v2df
21371 tree int64_ftype_v2df
21374 tree v2df_ftype_v2df_int
21377 tree v2df_ftype_v2df_int64
21380 NULL_TREE);
21381 tree v4sf_ftype_v4sf_v2df
21384 tree v2df_ftype_v2df_v4sf
21387 tree v2df_ftype_v2df_v2df_int
21390 integer_type_node,
21391 NULL_TREE);
21392 tree v2df_ftype_v2df_pcdouble
21395 tree void_ftype_pdouble_v2df
21398 tree void_ftype_pint_int
21401 tree void_ftype_v16qi_v16qi_pchar
21405 tree v2df_ftype_pcdouble
21407 tree v2df_ftype_v2df_v2df
21410 tree v16qi_ftype_v16qi_v16qi
21413 tree v8hi_ftype_v8hi_v8hi
21416 tree v4si_ftype_v4si_v4si
21419 tree v2di_ftype_v2di_v2di
21422 tree v2di_ftype_v2df_v2df
21425 tree v2df_ftype_v2df
21427 tree v2di_ftype_v2di_int
21430 tree v2di_ftype_v2di_v2di_int
21433 tree v4si_ftype_v4si_int
21436 tree v8hi_ftype_v8hi_int
21439 tree v4si_ftype_v8hi_v8hi
21442 tree v1di_ftype_v8qi_v8qi
21445 tree v1di_ftype_v2si_v2si
21448 tree v2di_ftype_v16qi_v16qi
21451 tree v2di_ftype_v4si_v4si
21454 tree int_ftype_v16qi
21456 tree v16qi_ftype_pcchar
21458 tree void_ftype_pchar_v16qi
21462 tree v2di_ftype_v2di_unsigned_unsigned
21465 NULL_TREE);
21466 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21469 NULL_TREE);
21470 tree v2di_ftype_v2di_v16qi
21472 NULL_TREE);
21473 tree v2df_ftype_v2df_v2df_v2df
21477 tree v4sf_ftype_v4sf_v4sf_v4sf
21481 tree v8hi_ftype_v16qi
21483 NULL_TREE);
21484 tree v4si_ftype_v16qi
21486 NULL_TREE);
21487 tree v2di_ftype_v16qi
21489 NULL_TREE);
21490 tree v4si_ftype_v8hi
21492 NULL_TREE);
21493 tree v2di_ftype_v8hi
21495 NULL_TREE);
21496 tree v2di_ftype_v4si
21498 NULL_TREE);
21499 tree v2di_ftype_pv2di
21501 NULL_TREE);
21502 tree v16qi_ftype_v16qi_v16qi_int
21505 NULL_TREE);
21506 tree v16qi_ftype_v16qi_v16qi_v16qi
21509 NULL_TREE);
21510 tree v8hi_ftype_v8hi_v8hi_int
21513 NULL_TREE);
21514 tree v4si_ftype_v4si_v4si_int
21517 NULL_TREE);
21518 tree int_ftype_v2di_v2di
21521 NULL_TREE);
21522 tree int_ftype_v16qi_int_v16qi_int_int
21524 V16QI_type_node,
21525 integer_type_node,
21526 V16QI_type_node,
21527 integer_type_node,
21528 integer_type_node,
21529 NULL_TREE);
21530 tree v16qi_ftype_v16qi_int_v16qi_int_int
21532 V16QI_type_node,
21533 integer_type_node,
21534 V16QI_type_node,
21535 integer_type_node,
21536 integer_type_node,
21537 NULL_TREE);
21538 tree int_ftype_v16qi_v16qi_int
21540 V16QI_type_node,
21541 V16QI_type_node,
21542 integer_type_node,
21543 NULL_TREE);
21545 /* SSE5 instructions */
21546 tree v2di_ftype_v2di_v2di_v2di
21548 V2DI_type_node,
21549 V2DI_type_node,
21550 V2DI_type_node,
21551 NULL_TREE);
21553 tree v4si_ftype_v4si_v4si_v4si
21555 V4SI_type_node,
21556 V4SI_type_node,
21557 V4SI_type_node,
21558 NULL_TREE);
21560 tree v4si_ftype_v4si_v4si_v2di
21562 V4SI_type_node,
21563 V4SI_type_node,
21564 V2DI_type_node,
21565 NULL_TREE);
21567 tree v8hi_ftype_v8hi_v8hi_v8hi
21569 V8HI_type_node,
21570 V8HI_type_node,
21571 V8HI_type_node,
21572 NULL_TREE);
21574 tree v8hi_ftype_v8hi_v8hi_v4si
21576 V8HI_type_node,
21577 V8HI_type_node,
21578 V4SI_type_node,
21579 NULL_TREE);
21581 tree v2df_ftype_v2df_v2df_v16qi
21583 V2DF_type_node,
21584 V2DF_type_node,
21585 V16QI_type_node,
21586 NULL_TREE);
21588 tree v4sf_ftype_v4sf_v4sf_v16qi
21590 V4SF_type_node,
21591 V4SF_type_node,
21592 V16QI_type_node,
21593 NULL_TREE);
21595 tree v2di_ftype_v2di_si
21597 V2DI_type_node,
21598 integer_type_node,
21599 NULL_TREE);
21601 tree v4si_ftype_v4si_si
21603 V4SI_type_node,
21604 integer_type_node,
21605 NULL_TREE);
21607 tree v8hi_ftype_v8hi_si
21609 V8HI_type_node,
21610 integer_type_node,
21611 NULL_TREE);
21613 tree v16qi_ftype_v16qi_si
21615 V16QI_type_node,
21616 integer_type_node,
21617 NULL_TREE);
21618 tree v4sf_ftype_v4hi
21620 V4HI_type_node,
21621 NULL_TREE);
21623 tree v4hi_ftype_v4sf
21625 V4SF_type_node,
21626 NULL_TREE);
21628 tree v2di_ftype_v2di
21631 tree v16qi_ftype_v8hi_v8hi
21634 NULL_TREE);
21635 tree v8hi_ftype_v4si_v4si
21638 NULL_TREE);
21639 tree v8hi_ftype_v16qi_v16qi
21642 NULL_TREE);
21643 tree v4hi_ftype_v8qi_v8qi
21646 NULL_TREE);
21647 tree unsigned_ftype_unsigned_uchar
21649 unsigned_type_node,
21650 unsigned_char_type_node,
21651 NULL_TREE);
21652 tree unsigned_ftype_unsigned_ushort
21654 unsigned_type_node,
21655 short_unsigned_type_node,
21656 NULL_TREE);
21657 tree unsigned_ftype_unsigned_unsigned
21659 unsigned_type_node,
21660 unsigned_type_node,
21661 NULL_TREE);
21662 tree uint64_ftype_uint64_uint64
21664 long_long_unsigned_type_node,
21665 long_long_unsigned_type_node,
21666 NULL_TREE);
21667 tree float_ftype_float
21669 float_type_node,
21670 NULL_TREE);
21672 /* AVX builtins */
21674 V32QImode);
21676 V8SImode);
21678 V8SFmode);
21680 V4DImode);
21682 V4DFmode);
21683 tree v8sf_ftype_v8sf
21685 V8SF_type_node,
21686 NULL_TREE);
21687 tree v8si_ftype_v8sf
21689 V8SF_type_node,
21690 NULL_TREE);
21691 tree v8sf_ftype_v8si
21693 V8SI_type_node,
21694 NULL_TREE);
21695 tree v4si_ftype_v4df
21697 V4DF_type_node,
21698 NULL_TREE);
21699 tree v4df_ftype_v4df
21701 V4DF_type_node,
21702 NULL_TREE);
21703 tree v4df_ftype_v4si
21705 V4SI_type_node,
21706 NULL_TREE);
21707 tree v4df_ftype_v4sf
21709 V4SF_type_node,
21710 NULL_TREE);
21711 tree v4sf_ftype_v4df
21713 V4DF_type_node,
21714 NULL_TREE);
21715 tree v8sf_ftype_v8sf_v8sf
21718 NULL_TREE);
21719 tree v4df_ftype_v4df_v4df
21722 NULL_TREE);
21723 tree v8sf_ftype_v8sf_int
21726 NULL_TREE);
21727 tree v4si_ftype_v8si_int
21730 NULL_TREE);
21731 tree v4df_ftype_v4df_int
21734 NULL_TREE);
21735 tree v4sf_ftype_v8sf_int
21738 NULL_TREE);
21739 tree v2df_ftype_v4df_int
21742 NULL_TREE);
21743 tree v8sf_ftype_v8sf_v8sf_int
21746 integer_type_node,
21747 NULL_TREE);
21748 tree v8sf_ftype_v8sf_v8sf_v8sf
21751 V8SF_type_node,
21752 NULL_TREE);
21753 tree v4df_ftype_v4df_v4df_v4df
21756 V4DF_type_node,
21757 NULL_TREE);
21758 tree v8si_ftype_v8si_v8si_int
21761 integer_type_node,
21762 NULL_TREE);
21763 tree v4df_ftype_v4df_v4df_int
21766 integer_type_node,
21767 NULL_TREE);
21768 tree v8sf_ftype_v8sf_v8sf_v8si_int
21772 NULL_TREE);
21773 tree v4df_ftype_v4df_v4df_v4di_int
21777 NULL_TREE);
21778 tree v4sf_ftype_v4sf_v4sf_v4si_int
21782 NULL_TREE);
21783 tree v2df_ftype_v2df_v2df_v2di_int
21787 NULL_TREE);
21788 tree v8sf_ftype_pcfloat
21790 pcfloat_type_node,
21791 NULL_TREE);
21792 tree v4df_ftype_pcdouble
21794 pcdouble_type_node,
21795 NULL_TREE);
21796 tree pcv4sf_type_node
21798 tree pcv2df_type_node
21800 tree v8sf_ftype_pcv4sf
21802 pcv4sf_type_node,
21803 NULL_TREE);
21804 tree v4df_ftype_pcv2df
21806 pcv2df_type_node,
21807 NULL_TREE);
21808 tree v32qi_ftype_pcchar
21810 pcchar_type_node,
21811 NULL_TREE);
21812 tree void_ftype_pchar_v32qi
21815 NULL_TREE);
21816 tree v8si_ftype_v8si_v4si_int
21819 integer_type_node,
21820 NULL_TREE);
21821 tree v8sf_ftype_v8sf_v4sf_int
21824 integer_type_node,
21825 NULL_TREE);
21826 tree v4df_ftype_v4df_v2df_int
21829 integer_type_node,
21830 NULL_TREE);
21831 tree void_ftype_pfloat_v8sf
21834 NULL_TREE);
21835 tree void_ftype_pdouble_v4df
21838 NULL_TREE);
21843 tree pcv8sf_type_node
21845 tree pcv4df_type_node
21847 tree v8sf_ftype_pcv8sf_v8sf
21850 NULL_TREE);
21851 tree v4df_ftype_pcv4df_v4df
21854 NULL_TREE);
21855 tree v4sf_ftype_pcv4sf_v4sf
21858 NULL_TREE);
21859 tree v2df_ftype_pcv2df_v2df
21862 NULL_TREE);
21863 tree void_ftype_pv8sf_v8sf_v8sf
21866 V8SF_type_node,
21867 NULL_TREE);
21868 tree void_ftype_pv4df_v4df_v4df
21871 V4DF_type_node,
21872 NULL_TREE);
21873 tree void_ftype_pv4sf_v4sf_v4sf
21876 V4SF_type_node,
21877 NULL_TREE);
21878 tree void_ftype_pv2df_v2df_v2df
21881 V2DF_type_node,
21882 NULL_TREE);
21883 tree v4df_ftype_v2df
21885 V2DF_type_node,
21886 NULL_TREE);
21887 tree v8sf_ftype_v4sf
21889 V4SF_type_node,
21890 NULL_TREE);
21891 tree v8si_ftype_v4si
21893 V4SI_type_node,
21894 NULL_TREE);
21895 tree v2df_ftype_v4df
21897 V4DF_type_node,
21898 NULL_TREE);
21899 tree v4sf_ftype_v8sf
21901 V8SF_type_node,
21902 NULL_TREE);
21903 tree v4si_ftype_v8si
21905 V8SI_type_node,
21906 NULL_TREE);
21907 tree int_ftype_v4df
21909 V4DF_type_node,
21910 NULL_TREE);
21911 tree int_ftype_v8sf
21913 V8SF_type_node,
21914 NULL_TREE);
21915 tree int_ftype_v8sf_v8sf
21918 NULL_TREE);
21919 tree int_ftype_v4di_v4di
21922 NULL_TREE);
21923 tree int_ftype_v4df_v4df
21926 NULL_TREE);
21927 tree v8sf_ftype_v8sf_v8si
21930 NULL_TREE);
21931 tree v4df_ftype_v4df_v4di
21934 NULL_TREE);
21935 tree v4sf_ftype_v4sf_v4si
21938 tree v2df_ftype_v2df_v2di
21942 tree ftype;
21944 /* Add all special builtins with variable number of operands. */
21948 {
21949 tree type;
21955 {
22048 }
22051 }
22053 /* Add all builtins with variable number of operands. */
22057 {
22058 tree type;
22064 {
22505 }
22508 }
22510 /* pcmpestr[im] insns. */
22514 {
22517 else
22520 }
22522 /* pcmpistr[im] insns. */
22526 {
22529 else
22532 }
22534 /* comi/ucomi insns. */
22538 else
22541 /* SSE */
22542 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
22543 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
22545 /* SSE or 3DNow!A */
22546 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
22548 /* SSE2 */
22549 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
22551 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
22552 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
22554 /* SSE3. */
22555 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
22556 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
22558 /* AES */
22559 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
22560 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
22561 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
22562 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
22563 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
22564 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
22566 /* PCLMUL */
22567 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
22569 /* AVX */
22573 /* Access to the vec_init patterns. */
22576 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
22579 short_integer_type_node,
22580 short_integer_type_node,
22582 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
22589 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
22591 /* Access to the vec_extract patterns. */
22594 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
22598 NULL_TREE);
22599 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
22603 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
22607 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
22611 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
22615 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
22619 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
22623 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
22625 /* Access to the vec_set patterns. */
22627 intDI_type_node,
22629 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
22632 float_type_node,
22634 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
22637 intSI_type_node,
22639 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
22642 intHI_type_node,
22644 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
22647 intHI_type_node,
22649 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
22652 intQI_type_node,
22654 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
22656 /* Add SSE5 multi-arg argument instructions */
22658 {
22665 {
22715 }
22719 }
22720 }
22722 /* Internal method for ix86_init_builtins. */
22724 static void
22726 {
22738 sysv_va_ref =
22741 fnvoid_va_end_ms =
22743 fnvoid_va_start_ms =
22745 fnvoid_va_end_sysv =
22747 fnvoid_va_start_sysv =
22749 NULL_TREE);
22750 fnvoid_va_copy_ms =
22752 NULL_TREE);
22753 fnvoid_va_copy_sysv =
22769 }
22771 static void
22773 {
22777 /* The __float80 type. */
22781 else
22782 {
22783 /* The __float80 type. */
22790 }
22792 /* The __float128 type. */
22798 /* TFmode support builtins. */
22805 /* We will expand them to normal call if SSE2 isn't available since
22806 they are used by libgcc. */
22808 float128_type_node,
22809 NULL_TREE);
22817 float128_type_node,
22818 float128_type_node,
22819 NULL_TREE);
22829 }
22831 /* Errors in the source file can cause expand_expr to return const0_rtx
22832 where we expect a vector. To avoid crashing, use one of the vector
22833 clear instructions. */
22834 static rtx
22836 {
22840 }
22842 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
22844 static rtx
22846 {
22847 rtx pat;
22867 {
22871 }
22885 }
22887 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
22889 static rtx
22893 {
22894 rtx pat;
22902 rtx op;
22909 {
22980 }
22990 {
22997 {
22999 {
23002 }
23003 }
23004 else
23005 {
23009 /* If we aren't optimizing, only allow one memory operand to be
23010 generated. */
23012 num_memory++;
23020 }
23024 }
23027 {
23038 else
23039 {
23045 }
23054 }
23061 }
23063 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23064 insns with vec_merge. */
23066 static rtx
23068 rtx target)
23069 {
23070 rtx pat;
23097 }
23099 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23101 static rtx
23104 {
23105 rtx pat;
23110 rtx op2;
23121 /* Swap operands if we have a comparison that isn't available in
23122 hardware. */
23124 {
23129 }
23149 }
23151 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23153 static rtx
23155 rtx target)
23156 {
23157 rtx pat;
23171 /* Swap operands if we have a comparison that isn't available in
23172 hardware. */
23174 {
23178 }
23199 const0_rtx)));
23202 }
23204 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23206 static rtx
23208 rtx target)
23209 {
23210 rtx pat;
23243 const0_rtx)));
23246 }
23248 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23250 static rtx
23253 {
23254 rtx pat;
23292 {
23295 }
23298 {
23307 }
23309 {
23318 }
23319 else
23320 {
23327 }
23335 {
23340 emit_insn
23344 FLAGS_REG),
23345 const0_rtx)));
23347 }
23348 else
23350 }
23353 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23355 static rtx
23358 {
23359 rtx pat;
23387 {
23390 }
23393 {
23402 }
23404 {
23413 }
23414 else
23415 {
23422 }
23430 {
23435 emit_insn
23439 FLAGS_REG),
23440 const0_rtx)));
23442 }
23443 else
23445 }
23447 /* Subroutine of ix86_expand_builtin to take care of insns with
23448 variable number of operands. */
23450 static rtx
23453 {
23458 struct
23459 {
23460 rtx op;
23472 {
23677 }
23682 {
23685 }
23688 {
23695 }
23696 else
23697 {
23700 }
23703 {
23710 {
23711 /* SIMD shift insns take either an 8-bit immediate or
23712 register as count. But builtin functions take int as
23713 count. If count doesn't match, we put it in register. */
23715 {
23719 }
23720 }
23722 {
23725 {
23767 {
23770 {
23773 }
23779 }
23781 }
23782 }
23783 else
23784 {
23788 /* If we aren't optimizing, only allow one memory operand to
23789 be generated. */
23791 num_memory++;
23794 {
23797 }
23798 else
23799 {
23802 }
23803 }
23807 }
23810 {
23827 }
23834 }
23836 /* Subroutine of ix86_expand_builtin to take care of special insns
23837 with variable number of operands. */
23839 static rtx
23842 {
23843 tree arg;
23846 struct
23847 {
23848 rtx op;
23858 {
23887 /* Reserve memory operand for target. */
23910 /* Reserve memory operand for target. */
23915 }
23920 {
23926 }
23927 else
23928 {
23935 }
23938 {
23947 {
23950 {
23954 }
23955 }
23956 else
23957 {
23959 {
23960 /* This must be the memory operand. */
23964 }
23965 else
23966 {
23967 /* This must be register. */
23974 }
23975 }
23979 }
23982 {
23991 }
23997 }
23999 /* Return the integer constant in ARG. Constrain it to be in the range
24000 of the subparts of VEC_TYPE; issue an error if not. */
24002 static int
24004 {
24009 {
24012 }
24015 }
24017 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24018 ix86_expand_vector_init. We DO have language-level syntax for this, in
24019 the form of (type){ init-list }. Except that since we can't place emms
24020 instructions from inside the compiler, we can't allow the use of MMX
24021 registers unless the user explicitly asks for it. So we do *not* define
24022 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24023 we have builtins invoked by mmintrin.h that gives us license to emit
24024 these sorts of instructions. */
24026 static rtx
24028 {
24038 {
24041 }
24048 }
24050 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24051 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24052 had a language-level syntax for referencing vector elements. */
24054 static rtx
24056 {
24060 rtx op0;
24080 }
24082 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24083 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24084 a language-level syntax for referencing vector elements. */
24086 static rtx
24088 {
24112 /* OP0 is the source of these builtin functions and shouldn't be
24113 modified. Create a copy, use it and return it as target. */
24119 }
24121 /* Expand an expression EXP that calls a built-in function,
24122 with result going to TARGET if that's convenient
24123 (and in mode MODE if that's convenient).
24124 SUBTARGET may be used as the target for computing one of EXP's operands.
24125 IGNORE is nonzero if the value is to be ignored. */
24127 static rtx
24131 {
24141 /* Determine whether the builtin function is available under the current ISA.
24142 Originally the builtin was not created if it wasn't applicable to the
24143 current ISA based on the command line switches. With function specific
24144 options, we need to check in the context of the function making the call
24145 whether it is supported. */
24148 {
24154 else
24155 {
24159 }
24161 }
24164 {
24168 ? CODE_FOR_mmx_maskmovq
24170 /* Note the arg order is different from the operand order. */
24270 {
24271 REAL_VALUE_TYPE inf;
24272 rtx tmp;
24284 }
24288 }
24301 {
24305 /* Emit a normal call if SSE2 isn't available. */
24309 }
24334 }
24336 /* Returns a function decl for a vectorized version of the builtin function
24337 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24338 if it is not available. */
24340 static tree
24342 tree type_in)
24343 {
24357 {
24383 ;
24384 }
24386 /* Dispatch to a handler for a vectorization library. */
24391 }
24393 /* Handler for an SVML-style interface to
24394 a library with vectorized intrinsics. */
24396 static tree
24398 {
24406 /* The SVML is suitable for unsafe math only. */
24419 {
24466 }
24475 {
24478 }
24479 else
24482 /* Convert to uppercase. */
24488 arity++;
24492 else
24495 /* Build a function declaration for the vectorized function. */
24503 }
24505 /* Handler for an ACML-style interface to
24506 a library with vectorized intrinsics. */
24508 static tree
24510 {
24518 /* The ACML is 64bits only and suitable for unsafe math only as
24519 it does not correctly support parts of IEEE with the required
24520 precision such as denormals. */
24534 {
24564 }
24572 arity++;
24576 else
24579 /* Build a function declaration for the vectorized function. */
24587 }
24590 /* Returns a decl of a function that implements conversion of an integer vector
24591 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24592 side of the conversion.
24593 Return NULL_TREE if it is not available. */
24595 static tree
24597 {
24602 {
24605 {
24610 }
24614 {
24619 }
24623 }
24624 }
24626 /* Returns a code for a target-specific builtin that implements
24627 reciprocal of the function, or NULL_TREE if not available. */
24629 static tree
24632 {
24639 /* Machine dependent builtins. */
24641 {
24642 /* Vectorized version of sqrt to rsqrt conversion. */
24648 }
24649 else
24650 /* Normal builtins. */
24652 {
24653 /* Sqrt to rsqrt conversion. */
24659 }
24660 }
24662 /* Store OPERAND to the memory after reload is completed. This means
24663 that we can't easily use assign_stack_local. */
24664 rtx
24666 {
24667 rtx result;
24671 {
24674 stack_pointer_rtx,
24677 }
24679 {
24681 {
24685 /* FALLTHRU */
24691 stack_pointer_rtx)),
24692 operand));
24696 }
24698 }
24699 else
24700 {
24702 {
24704 {
24711 stack_pointer_rtx)),
24717 stack_pointer_rtx)),
24719 }
24722 /* Store HImodes as SImodes. */
24724 /* FALLTHRU */
24730 stack_pointer_rtx)),
24731 operand));
24735 }
24737 }
24739 }
24741 /* Free operand from the memory. */
24742 void
24744 {
24746 {
24751 else
24753 /* Use LEA to deallocate stack space. In peephole2 it will be converted
24754 to pop or add instruction if registers are available. */
24758 }
24759 }
24761 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
24762 QImode must go into class Q_REGS.
24763 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
24764 movdf to do mem-to-mem moves through integer regs. */
24765 enum reg_class
24767 {
24770 /* We're only allowed to return a subclass of CLASS. Many of the
24771 following checks fail for NO_REGS, so eliminate that early. */
24775 /* All classes can load zeros. */
24779 /* Force constants into memory if we are loading a (nonzero) constant into
24780 an MMX or SSE register. This is because there are no MMX/SSE instructions
24781 to load from a constant. */
24786 /* Prefer SSE regs only, if we can use them for math. */
24790 /* Floating-point constants need more complex checks. */
24792 {
24793 /* General regs can load everything. */
24797 /* Floats can load 0 and 1 plus some others. Note that we eliminated
24798 zero above. We only want to wind up preferring 80387 registers if
24799 we plan on doing computation with them. */
24802 {
24803 /* Limit class to non-sse. */
24812 }
24815 }
24817 /* Generally when we see PLUS here, it's the function invariant
24818 (plus soft-fp const_int). Which can only be computed into general
24819 regs. */
24823 /* QImode constants are easy to load, but non-constant QImode data
24824 must go into Q_REGS. */
24826 {
24832 }
24835 }
24837 /* Discourage putting floating-point values in SSE registers unless
24838 SSE math is being used, and likewise for the 387 registers. */
24839 enum reg_class
24841 {
24844 /* Restrict the output reload class to the register bank that we are doing
24845 math on. If we would like not to return a subset of CLASS, reject this
24846 alternative: if reload cannot do this, it will still use its choice. */
24852 {
24857 else
24859 }
24862 }
24864 static enum reg_class
24868 {
24869 /* QImode spills from non-QI registers require
24870 intermediate register on 32bit targets. */
24875 {
24880 else
24886 /* Return Q_REGS if the operand is in memory. */
24889 }
24892 }
24894 /* If we are copying between general and FP registers, we need a memory
24895 location. The same is true for SSE and MMX registers.
24897 To optimize register_move_cost performance, allow inline variant.
24899 The macro can't work reliably when one of the CLASSES is class containing
24900 registers from multiple units (SSE, MMX, integer). We avoid this by never
24901 combining those units in single alternative in the machine description.
24902 Ensure that this constraint holds to avoid unexpected surprises.
24904 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
24905 enforce these sanity checks. */
24910 {
24917 {
24920 }
24925 /* ??? This is a lie. We do have moves between mmx/general, and for
24926 mmx/sse2. But by saying we need secondary memory we discourage the
24927 register allocator from using the mmx registers unless needed. */
24932 {
24933 /* SSE1 doesn't have any direct moves from other classes. */
24937 /* If the target says that inter-unit moves are more expensive
24938 than moving through memory, then don't generate them. */
24942 /* Between SSE and general, we have moves no larger than word size. */
24945 }
24948 }
24950 int
24953 {
24955 }
24957 /* Return true if the registers in CLASS cannot represent the change from
24958 modes FROM to TO. */
24960 bool
24963 {
24967 /* x87 registers can't do subreg at all, as all values are reformatted
24968 to extended precision. */
24973 {
24974 /* Vector registers do not support QI or HImode loads. If we don't
24975 disallow a change to these modes, reload will assume it's ok to
24976 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
24977 the vec_dupv4hi pattern. */
24981 /* Vector registers do not support subreg with nonzero offsets, which
24982 are otherwise valid for integer registers. Since we can't see
24983 whether we have a nonzero offset from here, prohibit all
24984 nonparadoxical subregs changing size. */
24987 }
24990 }
24992 /* Return the cost of moving data of mode M between a
24993 register and memory. A value of 2 is the default; this cost is
24994 relative to those in `REGISTER_MOVE_COST'.
24996 This function is used extensively by register_move_cost that is used to
24997 build tables at startup. Make it inline in this case.
24998 When IN is 2, return maximum of in and out move cost.
25000 If moving between registers and memory is more expensive than
25001 between two registers, you should define this macro to express the
25002 relative cost.
25004 Model also increased moving costs of QImode registers in non
25005 Q_REGS classes.
25006 */
25010 {
25013 {
25016 {
25028 }
25032 }
25034 {
25037 {
25049 }
25053 }
25055 {
25058 {
25067 }
25071 }
25073 {
25076 {
25082 else
25087 }
25088 else
25089 {
25094 else
25096 }
25103 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25110 else
25114 }
25115 }
25117 int
25119 {
25121 }
25124 /* Return the cost of moving data from a register in class CLASS1 to
25125 one in class CLASS2.
25127 It is not required that the cost always equal 2 when FROM is the same as TO;
25128 on some machines it is expensive to move between registers if they are not
25129 general registers. */
25131 int
25134 {
25135 /* In case we require secondary memory, compute cost of the store followed
25136 by load. In order to avoid bad register allocation choices, we need
25137 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25140 {
25146 /* In case of copying from general_purpose_register we may emit multiple
25147 stores followed by single load causing memory size mismatch stall.
25148 Count this as arbitrarily high cost of 20. */
25152 /* In the case of FP/MMX moves, the registers actually overlap, and we
25153 have to switch modes in order to treat them differently. */
25159 }
25161 /* Moves between SSE/MMX and integer unit are expensive. */
25165 /* ??? By keeping returned value relatively high, we limit the number
25166 of moves between integer and MMX/SSE registers for all targets.
25167 Additionally, high value prevents problem with x86_modes_tieable_p(),
25168 where integer modes in MMX/SSE registers are not tieable
25169 because of missing QImode and HImode moves to, from or between
25170 MMX/SSE registers. */
25180 }
25182 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25184 bool
25186 {
25187 /* Flags and only flags can only hold CCmode values. */
25197 {
25198 /* We implement the move patterns for all vector modes into and
25199 out of SSE registers, even when no operation instructions
25200 are available. OImode move is available only when AVX is
25201 enabled. */
25208 }
25210 {
25211 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25212 so if the register is available at all, then we can move data of
25213 the given mode into or out of it. */
25216 }
25219 {
25220 /* Take care for QImode values - they can be in non-QI regs,
25221 but then they do cause partial register stalls. */
25227 }
25228 /* We handle both integer and floats in the general purpose registers. */
25235 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25236 on to use that value in smaller contexts, this can easily force a
25237 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25238 supporting DImode, allow it. */
25243 }
25245 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25246 tieable integer mode. */
25248 static bool
25250 {
25252 {
25265 }
25266 }
25268 /* Return true if MODE1 is accessible in a register that can hold MODE2
25269 without copying. That is, all register classes that can hold MODE2
25270 can also hold MODE1. */
25272 bool
25274 {
25282 /* MODE2 being XFmode implies fp stack or general regs, which means we
25283 can tie any smaller floating point modes to it. Note that we do not
25284 tie this with TFmode. */
25288 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25289 that we can tie it with SFmode. */
25293 /* If MODE2 is only appropriate for an SSE register, then tie with
25294 any other mode acceptable to SSE registers. */
25300 /* If MODE2 is appropriate for an MMX register, then tie
25301 with any other mode acceptable to MMX registers. */
25308 }
25310 /* Compute a (partial) cost for rtx X. Return true if the complete
25311 cost has been computed, and false if subexpressions should be
25312 scanned. In either case, *TOTAL contains the cost result. */
25314 static bool
25316 {
25322 {
25332 && (!TARGET_64BIT
25337 else
25344 else
25346 {
25355 /* Start with (MEM (SYMBOL_REF)), since that's where
25356 it'll probably end up. Add a penalty for size. */
25361 }
25365 /* The zero extensions is often completely free on x86_64, so make
25366 it as cheap as possible. */
25372 else
25383 {
25386 {
25389 }
25392 {
25395 }
25396 }
25397 /* FALLTHRU */
25404 {
25406 {
25409 else
25411 }
25412 else
25413 {
25416 else
25418 }
25419 }
25420 else
25421 {
25424 else
25426 }
25431 {
25432 /* ??? SSE scalar cost should be used here. */
25435 }
25437 {
25440 }
25442 {
25443 /* ??? SSE vector cost should be used here. */
25446 }
25447 else
25448 {
25453 {
25456 nbits++;
25457 }
25458 else
25459 /* This is arbitrary. */
25462 /* Compute costs correctly for widening multiplication. */
25466 {
25473 {
25477 else
25479 }
25483 }
25490 }
25497 /* ??? SSE cost should be used here. */
25502 /* ??? SSE vector cost should be used here. */
25504 else
25511 {
25516 {
25519 {
25526 }
25527 }
25530 {
25533 {
25538 }
25539 }
25541 {
25547 }
25548 }
25549 /* FALLTHRU */
25553 {
25554 /* ??? SSE cost should be used here. */
25557 }
25559 {
25562 }
25564 {
25565 /* ??? SSE vector cost should be used here. */
25568 }
25569 /* FALLTHRU */
25575 {
25582 }
25583 /* FALLTHRU */
25587 {
25588 /* ??? SSE cost should be used here. */
25591 }
25593 {
25596 }
25598 {
25599 /* ??? SSE vector cost should be used here. */
25602 }
25603 /* FALLTHRU */
25608 else
25617 {
25618 /* This kind of construct is implemented using test[bwl].
25619 Treat it as if we had an AND. */
25624 }
25634 /* ??? SSE cost should be used here. */
25639 /* ??? SSE vector cost should be used here. */
25645 /* ??? SSE cost should be used here. */
25650 /* ??? SSE vector cost should be used here. */
25661 }
25662 }
25664 #if TARGET_MACHO
25668 /* Given a symbol name and its associated stub, write out the
25669 definition of the stub. */
25671 void
25673 {
25678 /* For 64-bit we shouldn't get here. */
25681 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25696 else
25703 {
25707 }
25708 else
25714 {
25717 }
25718 else
25727 }
25729 void
25731 {
25734 }
25737 /* Order the registers for register allocator. */
25739 void
25741 {
25745 /* First allocate the local general purpose registers. */
25750 /* Global general purpose registers. */
25755 /* x87 registers come first in case we are doing FP math
25756 using them. */
25761 /* SSE registers. */
25767 /* x87 registers. */
25775 /* Initialize the rest of array as we do not allocate some registers
25776 at all. */
25779 }
25781 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
25782 struct attribute_spec.handler. */
25783 static tree
25785 tree args ATTRIBUTE_UNUSED,
25787 {
25792 {
25797 }
25799 {
25804 }
25806 /* Can combine regparm with all attributes but fastcall. */
25808 {
25810 {
25812 }
25815 }
25817 {
25819 {
25821 }
25824 }
25827 }
25829 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
25830 struct attribute_spec.handler. */
25831 static tree
25833 tree args ATTRIBUTE_UNUSED,
25835 {
25838 {
25841 }
25842 else
25847 {
25851 }
25857 {
25861 }
25864 }
25866 static bool
25868 {
25872 }
25874 /* Returns an expression indicating where the this parameter is
25875 located on entry to the FUNCTION. */
25877 static rtx
25879 {
25885 {
25890 else
25893 }
25898 {
25903 else
25904 {
25907 {
25912 }
25913 }
25915 }
25918 }
25920 /* Determine whether x86_output_mi_thunk can succeed. */
25922 static bool
25924 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
25926 {
25927 /* 64-bit can handle anything. */
25931 /* For 32-bit, everything's fine if we have one free register. */
25935 /* Need a free register for vcall_offset. */
25939 /* Need a free register for GOT references. */
25943 /* Otherwise ok. */
25945 }
25947 /* Output the assembler code for a thunk function. THUNK_DECL is the
25948 declaration for the thunk function itself, FUNCTION is the decl for
25949 the target function. DELTA is an immediate constant offset to be
25950 added to THIS. If VCALL_OFFSET is nonzero, the word at
25951 *(*this + vcall_offset) should be added to THIS. */
25953 static void
25957 {
25962 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
25963 pull it in now and let DELTA benefit. */
25967 {
25968 /* Put the this parameter into %eax. */
25972 }
25973 else
25976 /* Adjust the this parameter by a fixed constant. */
25978 {
25982 {
25984 {
25990 }
25992 }
25993 else
25995 }
25997 /* Adjust the this parameter by a value stored in the vtable. */
25999 {
26002 else
26003 {
26009 }
26015 /* Adjust the this parameter. */
26018 {
26024 }
26027 }
26029 /* If necessary, drop THIS back to its stack slot. */
26031 {
26035 }
26039 {
26042 /* All thunks should be in the same object as their target,
26043 and thus binds_local_p should be true. */
26046 else
26047 {
26053 }
26054 }
26055 else
26056 {
26059 else
26060 #if TARGET_MACHO
26062 {
26064 tmp = (gen_rtx_SYMBOL_REF
26070 }
26071 else
26073 {
26080 }
26081 }
26082 }
26084 static void
26086 {
26088 #if TARGET_MACHO
26090 #endif
26097 }
26099 int
26101 {
26113 }
26115 /* Output assembler code to FILE to increment profiler label # LABELNO
26116 for profiling a function entry. */
26117 void
26119 {
26121 {
26122 #ifndef NO_PROFILE_COUNTERS
26124 #endif
26128 else
26130 }
26132 {
26133 #ifndef NO_PROFILE_COUNTERS
26136 #endif
26138 }
26139 else
26140 {
26141 #ifndef NO_PROFILE_COUNTERS
26143 PROFILE_COUNT_REGISTER);
26144 #endif
26146 }
26147 }
26149 /* We don't have exact information about the insn sizes, but we may assume
26150 quite safely that we are informed about all 1 byte insns and memory
26151 address sizes. This is enough to eliminate unnecessary padding in
26152 99% of cases. */
26154 static int
26156 {
26162 /* Discard alignments we've emit and jump instructions. */
26171 /* Important case - calls are always 5 bytes.
26172 It is common to have many calls in the row. */
26180 /* For normal instructions we may rely on the sizes of addresses
26181 and the presence of symbol to require 4 bytes of encoding.
26182 This is not the case for jumps where references are PC relative. */
26184 {
26188 }
26191 else
26193 }
26195 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26196 window. */
26198 static void
26200 {
26205 /* Look for all minimal intervals of instructions containing 4 jumps.
26206 The intervals are bounded by START and INSN. NBYTES is the total
26207 size of instructions in the interval including INSN and not including
26208 START. When the NBYTES is smaller than 16 bytes, it is possible
26209 that the end of START and INSN ends up in the same 16byte page.
26211 The smallest offset in the page INSN can start is the case where START
26212 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26213 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26214 */
26216 {
26226 njumps++;
26227 else
26231 {
26238 else
26241 }
26248 {
26255 }
26256 }
26257 }
26259 /* AMD Athlon works faster
26260 when RET is not destination of conditional jump or directly preceded
26261 by other jump instruction. We avoid the penalty by inserting NOP just
26262 before the RET instructions in such cases. */
26263 static void
26265 {
26266 edge e;
26267 edge_iterator ei;
26270 {
26273 rtx prev;
26283 {
26284 edge e;
26285 edge_iterator ei;
26291 }
26293 {
26299 /* Empty functions get branch mispredict even when the jump destination
26300 is not visible to us. */
26303 }
26305 {
26308 }
26309 }
26310 }
26312 /* Implement machine specific optimizations. We implement padding of returns
26313 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26314 static void
26316 {
26323 }
26325 /* Return nonzero when QImode register that must be represented via REX prefix
26326 is used. */
26327 bool
26329 {
26337 }
26339 /* Return nonzero when P points to register encoded via REX prefix.
26340 Called via for_each_rtx. */
26341 static int
26343 {
26349 }
26351 /* Return true when INSN mentions register that must be encoded using REX
26352 prefix. */
26353 bool
26355 {
26358 }
26360 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26361 optabs would emit if we didn't have TFmode patterns. */
26363 void
26365 {
26399 }
26400 \f
26401 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26402 with all elements equal to VAR. Return true if successful. */
26404 static bool
26407 {
26409 rtx x;
26412 {
26417 /* FALLTHRU */
26432 {
26438 }
26439 else
26440 {
26445 }
26456 {
26458 /* Extend HImode to SImode using a paradoxical SUBREG. */
26461 /* Insert the SImode value as low element of V4SImode vector. */
26466 const1_rtx);
26468 /* Cast the V4SImode vector back to a V8HImode vector. */
26471 /* Duplicate the low short through the whole low SImode word. */
26473 /* Cast the V8HImode vector back to a V4SImode vector. */
26476 /* Replicate the low element of the V4SImode vector. */
26478 /* Cast the V2SImode back to V8HImode, and store in target. */
26481 }
26488 {
26490 /* Extend QImode to SImode using a paradoxical SUBREG. */
26493 /* Insert the SImode value as low element of V4SImode vector. */
26498 const1_rtx);
26500 /* Cast the V4SImode vector back to a V16QImode vector. */
26503 /* Duplicate the low byte through the whole low SImode word. */
26506 /* Cast the V16QImode vector back to a V4SImode vector. */
26509 /* Replicate the low element of the V4SImode vector. */
26511 /* Cast the V2SImode back to V16QImode, and store in target. */
26514 }
26519 widen:
26520 /* Replicate the value once into the next wider mode and recurse. */
26551 half:
26552 {
26557 }
26562 }
26563 }
26565 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26566 whose ONE_VAR element is VAR, and other elements are zero. Return true
26567 if successful. */
26569 static bool
26572 {
26574 rtx new_target;
26579 {
26581 /* For SSE4.1, we normally use vector set. But if the second
26582 element is zero and inter-unit moves are OK, we use movq
26583 instead. */
26584 use_vector_set = (TARGET_64BIT
26585 && TARGET_SSE4_1
26586 && !(TARGET_INTER_UNIT_MOVES
26610 }
26613 {
26618 }
26621 {
26626 /* FALLTHRU */
26641 else
26648 {
26649 /* We need to shuffle the value to the correct position, so
26650 create a new pseudo to store the intermediate result. */
26652 /* With SSE2, we can use the integer shuffle insns. */
26654 {
26663 }
26665 /* Otherwise convert the intermediate result to V4SFmode and
26666 use the SSE1 shuffle instructions. */
26668 {
26671 }
26672 else
26685 }
26700 widen:
26704 /* Zero extend the variable element to SImode and recurse. */
26717 }
26718 }
26720 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26721 consisting of the values in VALS. It is known that all elements
26722 except ONE_VAR are constants. Return true if successful. */
26724 static bool
26727 {
26737 {
26742 /* For the two element vectors, it's just as easy to use
26743 the general case. */
26766 widen:
26767 /* There's no way to set one QImode entry easily. Combine
26768 the variable value with its adjacent constant value, and
26769 promote to an HImode set. */
26772 {
26777 }
26778 else
26779 {
26782 }
26796 }
26801 }
26803 /* A subroutine of ix86_expand_vector_init_general. Use vector
26804 concatenate to handle the most general case: all values variable,
26805 and none identical. */
26807 static void
26810 {
26813 rtvec v;
26817 {
26820 {
26853 }
26866 {
26881 }
26886 {
26897 }
26900 half:
26901 /* FIXME: We process inputs backward to help RA. PR 36222. */
26905 {
26910 }
26914 {
26917 {
26921 }
26924 }
26925 else
26931 }
26932 }
26934 /* A subroutine of ix86_expand_vector_init_general. Use vector
26935 interleave to handle the most general case: all values variable,
26936 and none identical. */
26938 static void
26941 {
26950 {
26971 }
26974 {
26975 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
26979 /* Insert the SImode value as low element of V4SImode vector. */
26983 op0),
26985 const1_rtx);
26988 /* Cast the V4SImode vector back to a vector in orignal mode. */
26992 /* Load even elements into the second positon. */
26996 const1_rtx));
26998 /* Cast vector to FIRST_IMODE vector. */
27001 }
27003 /* Interleave low FIRST_IMODE vectors. */
27005 {
27009 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27012 }
27014 /* Interleave low SECOND_IMODE vectors. */
27016 {
27019 {
27024 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27025 vector. */
27028 }
27031 /* FALLTHRU */
27038 /* Cast the SECOND_IMODE vector back to a vector on original
27039 mode. */
27046 }
27047 }
27049 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27050 all values variable, and none identical. */
27052 static void
27055 {
27061 {
27066 /* FALLTHRU */
27090 half:
27107 /* FALLTHRU */
27113 /* Don't use ix86_expand_vector_init_interleave if we can't
27114 move from GPR to SSE register directly. */
27130 }
27132 {
27144 {
27148 {
27154 else
27155 {
27160 }
27161 }
27164 }
27169 {
27175 }
27177 {
27183 }
27184 else
27186 }
27187 }
27189 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27190 instructions unless MMX_OK is true. */
27192 void
27194 {
27201 rtx x;
27204 {
27214 }
27216 /* Constants are best loaded from the constant pool. */
27218 {
27221 }
27223 /* If all values are identical, broadcast the value. */
27229 /* Values where only one field is non-constant are best loaded from
27230 the pool and overwritten via move later. */
27232 {
27236 one_var))
27241 }
27244 }
27246 void
27248 {
27253 rtx tmp;
27255 = {
27262 };
27264 = {
27271 };
27275 {
27279 {
27284 else
27288 }
27297 {
27300 /* For the two element vectors, we implement a VEC_CONCAT with
27301 the extraction of the other element. */
27308 else
27313 }
27322 {
27328 /* tmp = target = A B C D */
27330 /* target = A A B B */
27332 /* target = X A B B */
27334 /* target = A X C D */
27341 /* tmp = target = A B C D */
27343 /* tmp = X B C D */
27345 /* target = A B X D */
27352 /* tmp = target = A B C D */
27354 /* tmp = X B C D */
27356 /* target = A B X D */
27364 }
27372 /* Element 0 handled by vec_merge below. */
27374 {
27377 }
27380 {
27381 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27382 store into element 0, then shuffle them back. */
27399 }
27400 else
27401 {
27402 /* For SSE1, we have to reuse the V4SF code. */
27405 }
27458 half:
27459 /* Compute offset. */
27465 /* Extract the half. */
27469 /* Put val in tmp at elt. */
27472 /* Put it back. */
27478 }
27481 {
27485 }
27486 else
27487 {
27496 }
27497 }
27499 void
27501 {
27505 rtx tmp;
27508 {
27513 /* FALLTHRU */
27526 {
27546 }
27558 {
27560 {
27580 }
27584 }
27585 else
27586 {
27587 /* For SSE1, we have to reuse the V4SF code. */
27591 }
27606 /* ??? Could extract the appropriate HImode element and shift. */
27609 }
27612 {
27616 /* Let the rtl optimizers know about the zero extension performed. */
27618 {
27621 }
27624 }
27625 else
27626 {
27633 }
27634 }
27636 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27637 pattern to reduce; DEST is the destination; IN is the input vector. */
27639 void
27641 {
27655 }
27656 \f
27657 /* Target hook for scalar_mode_supported_p. */
27658 static bool
27660 {
27665 else
27667 }
27669 /* Implements target hook vector_mode_supported_p. */
27670 static bool
27672 {
27684 }
27686 /* Target hook for c_mode_for_suffix. */
27687 static enum machine_mode
27689 {
27696 }
27698 /* Worker function for TARGET_MD_ASM_CLOBBERS.
27700 We do this in the new i386 backend to maintain source compatibility
27701 with the old cc0-based compiler. */
27703 static tree
27705 tree inputs ATTRIBUTE_UNUSED,
27706 tree clobbers)
27707 {
27709 clobbers);
27711 clobbers);
27713 }
27715 /* Implements target vector targetm.asm.encode_section_info. This
27716 is not used by netware. */
27718 static void ATTRIBUTE_UNUSED
27720 {
27727 }
27729 /* Worker function for REVERSE_CONDITION. */
27731 enum rtx_code
27733 {
27737 }
27739 /* Output code to perform an x87 FP register move, from OPERANDS[1]
27740 to OPERANDS[0]. */
27744 {
27746 {
27749 {
27753 }
27757 }
27759 {
27763 else
27764 {
27765 /* There is no non-popping store to memory for XFmode.
27766 So if we need one, follow the store with a load. */
27769 else
27771 }
27772 }
27773 else
27775 }
27777 /* Output code to perform a conditional jump to LABEL, if C2 flag in
27778 FP status register is set. */
27780 void
27782 {
27784 rtx temp;
27789 {
27794 }
27795 else
27796 {
27801 }
27805 pc_rtx);
27810 }
27812 /* Output code to perform a log1p XFmode calculation. */
27815 {
27826 XFmode)));
27840 }
27842 /* Output code to perform a Newton-Rhapson approximation of a single precision
27843 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
27846 {
27861 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
27863 /* x0 = rcp(b) estimate */
27866 UNSPEC_RCP)));
27867 /* e0 = x0 * b */
27870 /* e1 = 2. - e0 */
27873 /* x1 = x0 * e1 */
27876 /* res = a * x1 */
27879 }
27881 /* Output code to perform a Newton-Rhapson approximation of a
27882 single precision floating point [reciprocal] square root. */
27886 {
27888 REAL_VALUE_TYPE r;
27903 {
27906 }
27908 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
27909 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
27911 /* x0 = rsqrt(a) estimate */
27914 UNSPEC_RSQRT)));
27916 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
27918 {
27930 }
27932 /* e0 = x0 * a */
27935 /* e1 = e0 * x0 */
27939 /* e2 = e1 - 3. */
27946 /* e3 = -.5 * x0 */
27949 else
27950 /* e3 = -.5 * e0 */
27953 /* ret = e2 * e3 */
27956 }
27958 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
27960 static void ATTRIBUTE_UNUSED
27962 tree decl)
27963 {
27964 /* With Binutils 2.15, the "@unwind" marker must be specified on
27965 every occurrence of the ".eh_frame" section, not just the first
27966 one. */
27969 {
27973 }
27975 }
27977 /* Return the mangling of TYPE if it is an extended fundamental type. */
27981 {
27989 {
27991 /* __float128 is "g". */
27994 /* "long double" or __float80 is "e". */
27998 }
27999 }
28001 /* For 32-bit code we can save PIC register setup by using
28002 __stack_chk_fail_local hidden function instead of calling
28003 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28004 register, so it is better to call __stack_chk_fail directly. */
28006 static tree
28008 {
28009 return TARGET_64BIT
28012 }
28014 /* Select a format to encode pointers in exception handling data. CODE
28015 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28016 true if the symbol may be affected by dynamic relocations.
28018 ??? All x86 object file formats are capable of representing this.
28019 After all, the relocation needed is the same as for the call insn.
28020 Whether or not a particular assembler allows us to enter such, I
28021 guess we'll have to see. */
28022 int
28024 {
28026 {
28033 }
28038 }
28039 \f
28040 /* Expand copysign from SIGN to the positive value ABS_VALUE
28041 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28042 the sign-bit. */
28043 static void
28045 {
28049 {
28052 {
28053 /* We need to generate a scalar mode mask in this case. */
28058 }
28059 }
28060 else
28066 }
28068 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28069 mask for masking out the sign-bit is stored in *SMASK, if that is
28070 non-null. */
28071 static rtx
28073 {
28080 {
28081 /* We need to generate a scalar mode mask in this case. */
28086 }
28094 }
28096 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28097 swapping the operands if SWAP_OPERANDS is true. The expanded
28098 code is a forward jump to a newly created label in case the
28099 comparison is true. The generated label rtx is returned. */
28100 static rtx
28103 {
28107 {
28111 }
28124 }
28126 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28127 using comparison code CODE. Operands are swapped for the comparison if
28128 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28129 static rtx
28132 {
28137 {
28141 }
28146 else
28151 }
28153 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28154 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28155 static rtx
28157 {
28158 REAL_VALUE_TYPE TWO52r;
28159 rtx TWO52;
28166 }
28168 /* Expand SSE sequence for computing lround from OP1 storing
28169 into OP0. */
28170 void
28172 {
28173 /* C code for the stuff we're doing below:
28174 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28175 return (long)tmp;
28176 */
28180 rtx adj;
28182 /* load nextafter (0.5, 0.0) */
28187 /* adj = copysign (0.5, op1) */
28191 /* adj = op1 + adj */
28194 /* op0 = (imode)adj */
28196 }
28198 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28199 into OPERAND0. */
28200 void
28202 {
28203 /* C code for the stuff we're doing below (for do_floor):
28204 xi = (long)op1;
28205 xi -= (double)xi > op1 ? 1 : 0;
28206 return xi;
28207 */
28212 /* reg = (long)op1 */
28216 /* freg = (double)reg */
28220 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28231 }
28233 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28234 result in OPERAND0. */
28235 void
28237 {
28238 /* C code for the stuff we're doing below:
28239 xa = fabs (operand1);
28240 if (!isless (xa, 2**52))
28241 return operand1;
28242 xa = xa + 2**52 - 2**52;
28243 return copysign (xa, operand1);
28244 */
28251 /* xa = abs (operand1) */
28254 /* if (!isless (xa, TWO52)) goto label; */
28267 }
28269 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28270 into OPERAND0. */
28271 void
28273 {
28274 /* C code for the stuff we expand below.
28275 double xa = fabs (x), x2;
28276 if (!isless (xa, TWO52))
28277 return x;
28278 xa = xa + TWO52 - TWO52;
28279 x2 = copysign (xa, x);
28280 Compensate. Floor:
28281 if (x2 > x)
28282 x2 -= 1;
28283 Compensate. Ceil:
28284 if (x2 < x)
28285 x2 -= -1;
28286 return x2;
28287 */
28293 /* Temporary for holding the result, initialized to the input
28294 operand to ease control flow. */
28298 /* xa = abs (operand1) */
28301 /* if (!isless (xa, TWO52)) goto label; */
28304 /* xa = xa + TWO52 - TWO52; */
28308 /* xa = copysign (xa, operand1) */
28311 /* generate 1.0 or -1.0 */
28316 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28320 /* We always need to subtract here to preserve signed zero. */
28329 }
28331 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28332 into OPERAND0. */
28333 void
28335 {
28336 /* C code for the stuff we expand below.
28337 double xa = fabs (x), x2;
28338 if (!isless (xa, TWO52))
28339 return x;
28340 x2 = (double)(long)x;
28341 Compensate. Floor:
28342 if (x2 > x)
28343 x2 -= 1;
28344 Compensate. Ceil:
28345 if (x2 < x)
28346 x2 += 1;
28347 if (HONOR_SIGNED_ZEROS (mode))
28348 return copysign (x2, x);
28349 return x2;
28350 */
28356 /* Temporary for holding the result, initialized to the input
28357 operand to ease control flow. */
28361 /* xa = abs (operand1) */
28364 /* if (!isless (xa, TWO52)) goto label; */
28367 /* xa = (double)(long)x */
28372 /* generate 1.0 */
28375 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28390 }
28392 /* Expand SSE sequence for computing round from OPERAND1 storing
28393 into OPERAND0. Sequence that works without relying on DImode truncation
28394 via cvttsd2siq that is only available on 64bit targets. */
28395 void
28397 {
28398 /* C code for the stuff we expand below.
28399 double xa = fabs (x), xa2, x2;
28400 if (!isless (xa, TWO52))
28401 return x;
28402 Using the absolute value and copying back sign makes
28403 -0.0 -> -0.0 correct.
28404 xa2 = xa + TWO52 - TWO52;
28405 Compensate.
28406 dxa = xa2 - xa;
28407 if (dxa <= -0.5)
28408 xa2 += 1;
28409 else if (dxa > 0.5)
28410 xa2 -= 1;
28411 x2 = copysign (xa2, x);
28412 return x2;
28413 */
28419 /* Temporary for holding the result, initialized to the input
28420 operand to ease control flow. */
28424 /* xa = abs (operand1) */
28427 /* if (!isless (xa, TWO52)) goto label; */
28430 /* xa2 = xa + TWO52 - TWO52; */
28434 /* dxa = xa2 - xa; */
28437 /* generate 0.5, 1.0 and -0.5 */
28443 /* Compensate. */
28445 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28450 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28456 /* res = copysign (xa2, operand1) */
28463 }
28465 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28466 into OPERAND0. */
28467 void
28469 {
28470 /* C code for SSE variant we expand below.
28471 double xa = fabs (x), x2;
28472 if (!isless (xa, TWO52))
28473 return x;
28474 x2 = (double)(long)x;
28475 if (HONOR_SIGNED_ZEROS (mode))
28476 return copysign (x2, x);
28477 return x2;
28478 */
28484 /* Temporary for holding the result, initialized to the input
28485 operand to ease control flow. */
28489 /* xa = abs (operand1) */
28492 /* if (!isless (xa, TWO52)) goto label; */
28495 /* x = (double)(long)x */
28507 }
28509 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28510 into OPERAND0. */
28511 void
28513 {
28517 /* C code for SSE variant we expand below.
28518 double xa = fabs (x), x2;
28519 if (!isless (xa, TWO52))
28520 return x;
28521 xa2 = xa + TWO52 - TWO52;
28522 Compensate:
28523 if (xa2 > xa)
28524 xa2 -= 1.0;
28525 x2 = copysign (xa2, x);
28526 return x2;
28527 */
28531 /* Temporary for holding the result, initialized to the input
28532 operand to ease control flow. */
28536 /* xa = abs (operand1) */
28539 /* if (!isless (xa, TWO52)) goto label; */
28542 /* res = xa + TWO52 - TWO52; */
28547 /* generate 1.0 */
28550 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28558 /* res = copysign (res, operand1) */
28565 }
28567 /* Expand SSE sequence for computing round from OPERAND1 storing
28568 into OPERAND0. */
28569 void
28571 {
28572 /* C code for the stuff we're doing below:
28573 double xa = fabs (x);
28574 if (!isless (xa, TWO52))
28575 return x;
28576 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28577 return copysign (xa, x);
28578 */
28584 /* Temporary for holding the result, initialized to the input
28585 operand to ease control flow. */
28593 /* load nextafter (0.5, 0.0) */
28598 /* xa = xa + 0.5 */
28602 /* xa = (double)(int64_t)xa */
28607 /* res = copysign (xa, operand1) */
28614 }
28616 \f
28617 /* Validate whether a SSE5 instruction is valid or not.
28618 OPERANDS is the array of operands.
28619 NUM is the number of operands.
28620 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
28621 NUM_MEMORY is the maximum number of memory operands to accept.
28622 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
28624 bool
28627 {
28632 /* Count the number of memory arguments */
28636 {
28639 ;
28642 {
28644 mem_count++;
28645 }
28647 else
28648 {
28651 /* allow 0 for pcmov */
28657 }
28658 }
28660 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
28661 a memory operation. */
28663 {
28666 {
28668 mem_count--;
28669 }
28670 }
28672 /* If there were no memory operations, allow the insn */
28676 /* Do not allow the destination register to be a memory operand. */
28680 /* If there are too many memory operations, disallow the instruction. While
28681 the hardware only allows 1 memory reference, before register allocation
28682 for some insns, we allow two memory operations sometimes in order to allow
28683 code like the following to be optimized:
28685 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
28687 or similar cases that are vectorized into using the fmaddss
28688 instruction. */
28692 /* Don't allow more than one memory operation if not optimizing. */
28697 {
28698 /* formats (destination is the first argument), example fmaddss:
28699 xmm1, xmm1, xmm2, xmm3/mem
28700 xmm1, xmm1, xmm2/mem, xmm3
28701 xmm1, xmm2, xmm3/mem, xmm1
28702 xmm1, xmm2/mem, xmm3, xmm1 */
28708 /* format, example pmacsdd:
28709 xmm1, xmm2, xmm3/mem, xmm1 */
28712 else
28714 }
28717 {
28718 /* If there are two memory operations, we can load one of the memory ops
28719 into the destination register. This is for optimizing the
28720 multiply/add ops, which the combiner has optimized both the multiply
28721 and the add insns to have a memory operation. We have to be careful
28722 that the destination doesn't overlap with the inputs. */
28730 /* formats (destination is the first argument), example fmaddss:
28731 xmm1, xmm1, xmm2, xmm3/mem
28732 xmm1, xmm1, xmm2/mem, xmm3
28733 xmm1, xmm2, xmm3/mem, xmm1
28734 xmm1, xmm2/mem, xmm3, xmm1
28736 For the oc0 case, we will load either operands[1] or operands[3] into
28737 operands[0], so any combination of 2 memory operands is ok. */
28741 /* format, example pmacsdd:
28742 xmm1, xmm2, xmm3/mem, xmm1
28744 For the integer multiply/add instructions be more restrictive and
28745 require operands[2] and operands[3] to be the memory operands. */
28748 else
28750 }
28753 {
28754 /* formats, example protb:
28755 xmm1, xmm2, xmm3/mem
28756 xmm1, xmm2/mem, xmm3 */
28760 /* format, example comeq:
28761 xmm1, xmm2, xmm3/mem */
28762 else
28764 }
28766 else
28770 }
28772 \f
28773 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
28774 hardware will allow by using the destination register to load one of the
28775 memory operations. Presently this is used by the multiply/add routines to
28776 allow 2 memory references. */
28778 void
28782 {
28791 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
28792 the destination register. */
28794 {
28797 }
28799 {
28802 }
28803 else
28807 }
28809 \f
28810 /* Table of valid machine attributes. */
28812 {
28813 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28814 /* Stdcall attribute says callee is responsible for popping arguments
28815 if they are not variable. */
28817 /* Fastcall attribute says callee is responsible for popping arguments
28818 if they are not variable. */
28820 /* Cdecl attribute says the callee is a normal C declaration */
28822 /* Regparm attribute specifies how many integer arguments are to be
28823 passed in registers. */
28825 /* Sseregparm attribute says we are using x86_64 calling conventions
28826 for FP arguments. */
28828 /* force_align_arg_pointer says this function realigns the stack at entry. */
28831 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28835 #endif
28838 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28839 SUBTARGET_ATTRIBUTE_TABLE,
28840 #endif
28841 /* ms_abi and sysv_abi calling convention function attributes. */
28844 /* End element. */
28846 };
28848 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28849 static int
28851 {
28852 /* If the branch of the runtime test is taken - i.e. - the vectorized
28853 version is skipped - this incurs a misprediction cost (because the
28854 vectorized version is expected to be the fall-through). So we subtract
28855 the latency of a mispredicted branch from the costs that are incured
28856 when the vectorized version is executed.
28858 TODO: The values in individual target tables have to be tuned or new
28859 fields may be needed. For eg. on K8, the default branch path is the
28860 not-taken path. If the taken path is predicted correctly, the minimum
28861 penalty of going down the taken-path is 1 cycle. If the taken-path is
28862 not predicted correctly, then the minimum penalty is 10 cycles. */
28865 {
28867 }
28868 else
28870 }
28872 /* This function returns the calling abi specific va_list type node.
28873 It returns the FNDECL specific va_list type. */
28875 tree
28877 {
28887 else
28889 }
28891 /* Returns the canonical va_list type specified by TYPE. If there
28892 is no valid TYPE provided, it return NULL_TREE. */
28894 tree
28896 {
28899 /* Resolve references and pointers to va_list type. */
28906 {
28911 {
28912 /* If va_list is an array type, the argument may have decayed
28913 to a pointer type, e.g. by being passed to another function.
28914 In that case, unwrap both types so that we can compare the
28915 underlying records. */
28918 {
28921 }
28922 }
28929 {
28930 /* If va_list is an array type, the argument may have decayed
28931 to a pointer type, e.g. by being passed to another function.
28932 In that case, unwrap both types so that we can compare the
28933 underlying records. */
28936 {
28939 }
28940 }
28947 {
28948 /* If va_list is an array type, the argument may have decayed
28949 to a pointer type, e.g. by being passed to another function.
28950 In that case, unwrap both types so that we can compare the
28951 underlying records. */
28954 {
28957 }
28958 }
28962 }
28964 }
28966 /* Iterate through the target-specific builtin types for va_list.
28967 IDX denotes the iterator, *PTREE is set to the result type of
28968 the va_list builtin, and *PNAME to its internal type.
28969 Returns zero if there is no element for this index, otherwise
28970 IDX should be increased upon the next call.
28971 Note, do not iterate a base builtin's name like __builtin_va_list.
28972 Used from c_common_nodes_and_builtins. */
28974 int
28976 {
28990 }
28992 }
28994 /* Initialize the GCC target structure. */
28995 #undef TARGET_RETURN_IN_MEMORY
28996 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
28998 #undef TARGET_ATTRIBUTE_TABLE
28999 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29000 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29001 # undef TARGET_MERGE_DECL_ATTRIBUTES
29002 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29003 #endif
29005 #undef TARGET_COMP_TYPE_ATTRIBUTES
29006 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29008 #undef TARGET_INIT_BUILTINS
29009 #define TARGET_INIT_BUILTINS ix86_init_builtins
29010 #undef TARGET_EXPAND_BUILTIN
29011 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29013 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29014 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29015 ix86_builtin_vectorized_function
29017 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29018 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29020 #undef TARGET_BUILTIN_RECIPROCAL
29021 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29023 #undef TARGET_ASM_FUNCTION_EPILOGUE
29024 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29026 #undef TARGET_ENCODE_SECTION_INFO
29027 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29028 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29029 #else
29030 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29031 #endif
29033 #undef TARGET_ASM_OPEN_PAREN
29035 #undef TARGET_ASM_CLOSE_PAREN
29038 #undef TARGET_ASM_ALIGNED_HI_OP
29039 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29040 #undef TARGET_ASM_ALIGNED_SI_OP
29041 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29042 #ifdef ASM_QUAD
29043 #undef TARGET_ASM_ALIGNED_DI_OP
29044 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29045 #endif
29047 #undef TARGET_ASM_UNALIGNED_HI_OP
29048 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29049 #undef TARGET_ASM_UNALIGNED_SI_OP
29050 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29051 #undef TARGET_ASM_UNALIGNED_DI_OP
29052 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29054 #undef TARGET_SCHED_ADJUST_COST
29055 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29056 #undef TARGET_SCHED_ISSUE_RATE
29057 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29058 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29059 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29060 ia32_multipass_dfa_lookahead
29062 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29063 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29065 #ifdef HAVE_AS_TLS
29066 #undef TARGET_HAVE_TLS
29067 #define TARGET_HAVE_TLS true
29068 #endif
29069 #undef TARGET_CANNOT_FORCE_CONST_MEM
29070 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29071 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29072 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29074 #undef TARGET_DELEGITIMIZE_ADDRESS
29075 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29077 #undef TARGET_MS_BITFIELD_LAYOUT_P
29078 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29080 #if TARGET_MACHO
29081 #undef TARGET_BINDS_LOCAL_P
29082 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29083 #endif
29084 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29085 #undef TARGET_BINDS_LOCAL_P
29086 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29087 #endif
29089 #undef TARGET_ASM_OUTPUT_MI_THUNK
29090 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29091 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29092 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29094 #undef TARGET_ASM_FILE_START
29095 #define TARGET_ASM_FILE_START x86_file_start
29097 #undef TARGET_DEFAULT_TARGET_FLAGS
29098 #define TARGET_DEFAULT_TARGET_FLAGS \
29099 (TARGET_DEFAULT \
29100 | TARGET_SUBTARGET_DEFAULT \
29101 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29103 #undef TARGET_HANDLE_OPTION
29104 #define TARGET_HANDLE_OPTION ix86_handle_option
29106 #undef TARGET_RTX_COSTS
29107 #define TARGET_RTX_COSTS ix86_rtx_costs
29108 #undef TARGET_ADDRESS_COST
29109 #define TARGET_ADDRESS_COST ix86_address_cost
29111 #undef TARGET_FIXED_CONDITION_CODE_REGS
29112 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29113 #undef TARGET_CC_MODES_COMPATIBLE
29114 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29116 #undef TARGET_MACHINE_DEPENDENT_REORG
29117 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29119 #undef TARGET_BUILD_BUILTIN_VA_LIST
29120 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29122 #undef TARGET_FN_ABI_VA_LIST
29123 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29125 #undef TARGET_CANONICAL_VA_LIST_TYPE
29126 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29128 #undef TARGET_EXPAND_BUILTIN_VA_START
29129 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29131 #undef TARGET_MD_ASM_CLOBBERS
29132 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29134 #undef TARGET_PROMOTE_PROTOTYPES
29135 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29136 #undef TARGET_STRUCT_VALUE_RTX
29137 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29138 #undef TARGET_SETUP_INCOMING_VARARGS
29139 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29140 #undef TARGET_MUST_PASS_IN_STACK
29141 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29142 #undef TARGET_PASS_BY_REFERENCE
29143 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29144 #undef TARGET_INTERNAL_ARG_POINTER
29145 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29146 #undef TARGET_UPDATE_STACK_BOUNDARY
29147 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29148 #undef TARGET_GET_DRAP_RTX
29149 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29150 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29151 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29152 #undef TARGET_STRICT_ARGUMENT_NAMING
29153 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29155 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29156 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29158 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29159 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29161 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29162 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29164 #undef TARGET_C_MODE_FOR_SUFFIX
29165 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29167 #ifdef HAVE_AS_TLS
29168 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29169 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29170 #endif
29172 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29173 #undef TARGET_INSERT_ATTRIBUTES
29174 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29175 #endif
29177 #undef TARGET_MANGLE_TYPE
29178 #define TARGET_MANGLE_TYPE ix86_mangle_type
29180 #undef TARGET_STACK_PROTECT_FAIL
29181 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29183 #undef TARGET_FUNCTION_VALUE
29184 #define TARGET_FUNCTION_VALUE ix86_function_value
29186 #undef TARGET_SECONDARY_RELOAD
29187 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29189 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29190 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29192 #undef TARGET_SET_CURRENT_FUNCTION
29193 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29195 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29196 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29198 #undef TARGET_OPTION_SAVE
29199 #define TARGET_OPTION_SAVE ix86_function_specific_save
29201 #undef TARGET_OPTION_RESTORE
29202 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29204 #undef TARGET_OPTION_PRINT
29205 #define TARGET_OPTION_PRINT ix86_function_specific_print
29207 #undef TARGET_OPTION_CAN_INLINE_P
29208 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29211 \f