1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "insn-config.h"
35 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
37 #include "addresses.h"
39 #include "hard-reg-set.h"
40 #include "function-abi.h"
42 /* Forward declarations */
43 static void set_of_1 (rtx
, const_rtx
, void *);
44 static bool covers_regno_p (const_rtx
, unsigned int);
45 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
46 static int computed_jump_p_1 (const_rtx
);
47 static void parms_set (rtx
, const_rtx
, void *);
49 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, scalar_int_mode
,
50 const_rtx
, machine_mode
,
51 unsigned HOST_WIDE_INT
);
52 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, scalar_int_mode
,
53 const_rtx
, machine_mode
,
54 unsigned HOST_WIDE_INT
);
55 static unsigned int cached_num_sign_bit_copies (const_rtx
, scalar_int_mode
,
56 const_rtx
, machine_mode
,
58 static unsigned int num_sign_bit_copies1 (const_rtx
, scalar_int_mode
,
59 const_rtx
, machine_mode
,
62 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
63 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
65 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
66 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
67 SIGN_EXTEND then while narrowing we also have to enforce the
68 representation and sign-extend the value to mode DESTINATION_REP.
70 If the value is already sign-extended to DESTINATION_REP mode we
71 can just switch to DESTINATION mode on it. For each pair of
72 integral modes SOURCE and DESTINATION, when truncating from SOURCE
73 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
74 contains the number of high-order bits in SOURCE that have to be
75 copies of the sign-bit so that we can do this mode-switch to
79 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
81 /* Store X into index I of ARRAY. ARRAY is known to have at least I
82 elements. Return the new base of ARRAY. */
85 typename
T::value_type
*
86 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
88 size_t i
, value_type x
)
90 if (base
== array
.stack
)
97 gcc_checking_assert (i
== LOCAL_ELEMS
);
98 /* A previous iteration might also have moved from the stack to the
99 heap, in which case the heap array will already be big enough. */
100 if (vec_safe_length (array
.heap
) <= i
)
101 vec_safe_grow (array
.heap
, i
+ 1, true);
102 base
= array
.heap
->address ();
103 memcpy (base
, array
.stack
, sizeof (array
.stack
));
104 base
[LOCAL_ELEMS
] = x
;
107 unsigned int length
= array
.heap
->length ();
110 gcc_checking_assert (base
== array
.heap
->address ());
116 gcc_checking_assert (i
== length
);
117 vec_safe_push (array
.heap
, x
);
118 return array
.heap
->address ();
122 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
123 number of elements added to the worklist. */
125 template <typename T
>
127 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
129 size_t end
, rtx_type x
)
131 enum rtx_code code
= GET_CODE (x
);
132 const char *format
= GET_RTX_FORMAT (code
);
133 size_t orig_end
= end
;
134 if (__builtin_expect (INSN_P (x
), false))
136 /* Put the pattern at the top of the queue, since that's what
137 we're likely to want most. It also allows for the SEQUENCE
139 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
140 if (format
[i
] == 'e')
142 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
143 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
146 base
= add_single_to_queue (array
, base
, end
++, subx
);
150 for (int i
= 0; format
[i
]; ++i
)
151 if (format
[i
] == 'e')
153 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
154 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
157 base
= add_single_to_queue (array
, base
, end
++, subx
);
159 else if (format
[i
] == 'E')
161 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
162 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
163 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
164 for (unsigned int j
= 0; j
< length
; j
++)
165 base
[end
++] = T::get_value (vec
[j
]);
167 for (unsigned int j
= 0; j
< length
; j
++)
168 base
= add_single_to_queue (array
, base
, end
++,
169 T::get_value (vec
[j
]));
170 if (code
== SEQUENCE
&& end
== length
)
171 /* If the subrtxes of the sequence fill the entire array then
172 we know that no other parts of a containing insn are queued.
173 The caller is therefore iterating over the sequence as a
174 PATTERN (...), so we also want the patterns of the
176 for (unsigned int j
= 0; j
< length
; j
++)
178 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
180 base
[j
] = T::get_value (PATTERN (x
));
183 return end
- orig_end
;
186 template <typename T
>
188 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
190 vec_free (array
.heap
);
193 template <typename T
>
194 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
196 template class generic_subrtx_iterator
<const_rtx_accessor
>;
197 template class generic_subrtx_iterator
<rtx_var_accessor
>;
198 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
200 /* Return 1 if the value of X is unstable
201 (would be different at a different point in the program).
202 The frame pointer, arg pointer, etc. are considered stable
203 (within one function) and so is anything marked `unchanging'. */
206 rtx_unstable_p (const_rtx x
)
208 const RTX_CODE code
= GET_CODE (x
);
215 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
224 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
225 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
226 /* The arg pointer varies if it is not a fixed register. */
227 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
229 /* ??? When call-clobbered, the value is stable modulo the restore
230 that must happen after a call. This currently screws up local-alloc
231 into believing that the restore is not needed. */
232 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
237 if (MEM_VOLATILE_P (x
))
246 fmt
= GET_RTX_FORMAT (code
);
247 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
250 if (rtx_unstable_p (XEXP (x
, i
)))
253 else if (fmt
[i
] == 'E')
256 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
257 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
264 /* Return 1 if X has a value that can vary even between two
265 executions of the program. 0 means X can be compared reliably
266 against certain constants or near-constants.
267 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
268 zero, we are slightly more conservative.
269 The frame pointer and the arg pointer are considered constant. */
272 rtx_varies_p (const_rtx x
, bool for_alias
)
285 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
294 /* Note that we have to test for the actual rtx used for the frame
295 and arg pointers and not just the register number in case we have
296 eliminated the frame and/or arg pointer and are using it
298 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
299 /* The arg pointer varies if it is not a fixed register. */
300 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
302 if (x
== pic_offset_table_rtx
303 /* ??? When call-clobbered, the value is stable modulo the restore
304 that must happen after a call. This currently screws up
305 local-alloc into believing that the restore is not needed, so we
306 must return 0 only if we are called from alias analysis. */
307 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
312 /* The operand 0 of a LO_SUM is considered constant
313 (in fact it is related specifically to operand 1)
314 during alias analysis. */
315 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
316 || rtx_varies_p (XEXP (x
, 1), for_alias
);
319 if (MEM_VOLATILE_P (x
))
328 fmt
= GET_RTX_FORMAT (code
);
329 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
332 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
335 else if (fmt
[i
] == 'E')
338 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
339 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
346 /* Compute an approximation for the offset between the register
347 FROM and TO for the current function, as it was at the start
351 get_initial_register_offset (int from
, int to
)
353 static const struct elim_table_t
357 } table
[] = ELIMINABLE_REGS
;
358 poly_int64 offset1
, offset2
;
364 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
365 is completed, but we need to give at least an estimate for the stack
366 pointer based on the frame size. */
367 if (!epilogue_completed
)
369 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
370 #if !STACK_GROWS_DOWNWARD
373 if (to
== STACK_POINTER_REGNUM
)
375 else if (from
== STACK_POINTER_REGNUM
)
381 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
382 if (table
[i
].from
== from
)
384 if (table
[i
].to
== to
)
386 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
390 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
392 if (table
[j
].to
== to
393 && table
[j
].from
== table
[i
].to
)
395 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
397 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
399 return offset1
+ offset2
;
401 if (table
[j
].from
== to
402 && table
[j
].to
== table
[i
].to
)
404 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
406 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
408 return offset1
- offset2
;
412 else if (table
[i
].to
== from
)
414 if (table
[i
].from
== to
)
416 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
420 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
422 if (table
[j
].to
== to
423 && table
[j
].from
== table
[i
].from
)
425 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
427 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
429 return - offset1
+ offset2
;
431 if (table
[j
].from
== to
432 && table
[j
].to
== table
[i
].from
)
434 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
436 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
438 return - offset1
- offset2
;
443 /* If the requested register combination was not found,
444 try a different more simple combination. */
445 if (from
== ARG_POINTER_REGNUM
)
446 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
447 else if (to
== ARG_POINTER_REGNUM
)
448 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
449 else if (from
== HARD_FRAME_POINTER_REGNUM
)
450 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
451 else if (to
== HARD_FRAME_POINTER_REGNUM
)
452 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
457 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
458 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
459 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
460 references on strict alignment machines. */
463 rtx_addr_can_trap_p_1 (const_rtx x
, poly_int64 offset
, poly_int64 size
,
464 machine_mode mode
, bool unaligned_mems
)
466 enum rtx_code code
= GET_CODE (x
);
467 gcc_checking_assert (mode
== BLKmode
469 || known_size_p (size
));
472 /* The offset must be a multiple of the mode size if we are considering
473 unaligned memory references on strict alignment machines. */
479 poly_int64 actual_offset
= offset
;
481 #ifdef SPARC_STACK_BOUNDARY_HACK
482 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
483 the real alignment of %sp. However, when it does this, the
484 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
485 if (SPARC_STACK_BOUNDARY_HACK
486 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
487 actual_offset
-= STACK_POINTER_OFFSET
;
490 if (!multiple_p (actual_offset
, GET_MODE_SIZE (mode
)))
497 if (SYMBOL_REF_WEAK (x
))
499 if (!CONSTANT_POOL_ADDRESS_P (x
) && !SYMBOL_REF_FUNCTION_P (x
))
502 poly_int64 decl_size
;
504 if (maybe_lt (offset
, 0))
506 if (!known_size_p (size
))
507 return maybe_ne (offset
, 0);
509 /* If the size of the access or of the symbol is unknown,
511 decl
= SYMBOL_REF_DECL (x
);
513 /* Else check that the access is in bounds. TODO: restructure
514 expr_size/tree_expr_size/int_expr_size and just use the latter. */
517 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
519 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl
), &decl_size
))
522 else if (TREE_CODE (decl
) == STRING_CST
)
523 decl_size
= TREE_STRING_LENGTH (decl
);
524 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
525 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
529 return (!known_size_p (decl_size
) || known_eq (decl_size
, 0)
530 ? maybe_ne (offset
, 0)
531 : !known_subrange_p (offset
, size
, 0, decl_size
));
540 /* Stack references are assumed not to trap, but we need to deal with
541 nonsensical offsets. */
542 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
543 || x
== stack_pointer_rtx
544 /* The arg pointer varies if it is not a fixed register. */
545 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
548 poly_int64 red_zone_size
= RED_ZONE_SIZE
;
550 poly_int64 red_zone_size
= 0;
552 poly_int64 stack_boundary
= PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
;
553 poly_int64 low_bound
, high_bound
;
555 if (!known_size_p (size
))
558 if (x
== frame_pointer_rtx
)
560 if (FRAME_GROWS_DOWNWARD
)
562 high_bound
= targetm
.starting_frame_offset ();
563 low_bound
= high_bound
- get_frame_size ();
567 low_bound
= targetm
.starting_frame_offset ();
568 high_bound
= low_bound
+ get_frame_size ();
571 else if (x
== hard_frame_pointer_rtx
)
574 = get_initial_register_offset (STACK_POINTER_REGNUM
,
575 HARD_FRAME_POINTER_REGNUM
);
577 = get_initial_register_offset (ARG_POINTER_REGNUM
,
578 HARD_FRAME_POINTER_REGNUM
);
580 #if STACK_GROWS_DOWNWARD
581 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
582 high_bound
= ap_offset
583 + FIRST_PARM_OFFSET (current_function_decl
)
584 #if !ARGS_GROW_DOWNWARD
589 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
590 low_bound
= ap_offset
591 + FIRST_PARM_OFFSET (current_function_decl
)
592 #if ARGS_GROW_DOWNWARD
598 else if (x
== stack_pointer_rtx
)
601 = get_initial_register_offset (ARG_POINTER_REGNUM
,
602 STACK_POINTER_REGNUM
);
604 #if STACK_GROWS_DOWNWARD
605 low_bound
= - red_zone_size
- stack_boundary
;
606 high_bound
= ap_offset
607 + FIRST_PARM_OFFSET (current_function_decl
)
608 #if !ARGS_GROW_DOWNWARD
613 high_bound
= red_zone_size
+ stack_boundary
;
614 low_bound
= ap_offset
615 + FIRST_PARM_OFFSET (current_function_decl
)
616 #if ARGS_GROW_DOWNWARD
624 /* We assume that accesses are safe to at least the
626 Examples are varargs and __builtin_return_address. */
627 #if ARGS_GROW_DOWNWARD
628 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
630 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
631 - crtl
->args
.size
- stack_boundary
;
633 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
635 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
636 + crtl
->args
.size
+ stack_boundary
;
640 if (known_ge (offset
, low_bound
)
641 && known_le (offset
, high_bound
- size
))
645 /* All of the virtual frame registers are stack references. */
646 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
647 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
652 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
653 mode
, unaligned_mems
);
656 /* An address is assumed not to trap if:
657 - it is the pic register plus a const unspec without offset. */
658 if (XEXP (x
, 0) == pic_offset_table_rtx
659 && GET_CODE (XEXP (x
, 1)) == CONST
660 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == UNSPEC
661 && known_eq (offset
, 0))
664 /* - or it is an address that can't trap plus a constant integer. */
665 if (poly_int_rtx_p (XEXP (x
, 1), &const_x1
)
666 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ const_x1
,
667 size
, mode
, unaligned_mems
))
674 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
675 mode
, unaligned_mems
);
682 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
683 mode
, unaligned_mems
);
689 /* If it isn't one of the case above, it can cause a trap. */
693 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
696 rtx_addr_can_trap_p (const_rtx x
)
698 return rtx_addr_can_trap_p_1 (x
, 0, -1, BLKmode
, false);
701 /* Return true if X contains a MEM subrtx. */
704 contains_mem_rtx_p (rtx x
)
706 subrtx_iterator::array_type array
;
707 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
714 /* Return true if X is an address that is known to not be zero. */
717 nonzero_address_p (const_rtx x
)
719 const enum rtx_code code
= GET_CODE (x
);
724 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
730 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
731 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
732 || x
== stack_pointer_rtx
733 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
735 /* All of the virtual frame registers are stack references. */
736 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
737 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
742 return nonzero_address_p (XEXP (x
, 0));
745 /* Handle PIC references. */
746 if (XEXP (x
, 0) == pic_offset_table_rtx
747 && CONSTANT_P (XEXP (x
, 1)))
752 /* Similar to the above; allow positive offsets. Further, since
753 auto-inc is only allowed in memories, the register must be a
755 if (CONST_INT_P (XEXP (x
, 1))
756 && INTVAL (XEXP (x
, 1)) > 0)
758 return nonzero_address_p (XEXP (x
, 0));
761 /* Similarly. Further, the offset is always positive. */
768 return nonzero_address_p (XEXP (x
, 0));
771 return nonzero_address_p (XEXP (x
, 1));
777 /* If it isn't one of the case above, might be zero. */
781 /* Return 1 if X refers to a memory location whose address
782 cannot be compared reliably with constant addresses,
783 or if X refers to a BLKmode memory object.
784 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
785 zero, we are slightly more conservative. */
788 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
799 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
801 fmt
= GET_RTX_FORMAT (code
);
802 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
805 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
808 else if (fmt
[i
] == 'E')
811 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
812 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
818 /* Return the CALL in X if there is one. */
821 get_call_rtx_from (const rtx_insn
*insn
)
823 rtx x
= PATTERN (insn
);
824 if (GET_CODE (x
) == PARALLEL
)
825 x
= XVECEXP (x
, 0, 0);
826 if (GET_CODE (x
) == SET
)
828 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
833 /* Get the declaration of the function called by INSN. */
836 get_call_fndecl (const rtx_insn
*insn
)
840 note
= find_reg_note (insn
, REG_CALL_DECL
, NULL_RTX
);
841 if (note
== NULL_RTX
)
844 datum
= XEXP (note
, 0);
845 if (datum
!= NULL_RTX
)
846 return SYMBOL_REF_DECL (datum
);
851 /* Return the value of the integer term in X, if one is apparent;
853 Only obvious integer terms are detected.
854 This is used in cse.cc with the `related_value' field. */
857 get_integer_term (const_rtx x
)
859 if (GET_CODE (x
) == CONST
)
862 if (GET_CODE (x
) == MINUS
863 && CONST_INT_P (XEXP (x
, 1)))
864 return - INTVAL (XEXP (x
, 1));
865 if (GET_CODE (x
) == PLUS
866 && CONST_INT_P (XEXP (x
, 1)))
867 return INTVAL (XEXP (x
, 1));
871 /* If X is a constant, return the value sans apparent integer term;
873 Only obvious integer terms are detected. */
876 get_related_value (const_rtx x
)
878 if (GET_CODE (x
) != CONST
)
881 if (GET_CODE (x
) == PLUS
882 && CONST_INT_P (XEXP (x
, 1)))
884 else if (GET_CODE (x
) == MINUS
885 && CONST_INT_P (XEXP (x
, 1)))
890 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
891 to somewhere in the same object or object_block as SYMBOL. */
894 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
898 if (GET_CODE (symbol
) != SYMBOL_REF
)
906 if (CONSTANT_POOL_ADDRESS_P (symbol
)
907 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
910 decl
= SYMBOL_REF_DECL (symbol
);
911 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
915 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
916 && SYMBOL_REF_BLOCK (symbol
)
917 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
918 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
919 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
925 /* Split X into a base and a constant offset, storing them in *BASE_OUT
926 and *OFFSET_OUT respectively. */
929 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
931 if (GET_CODE (x
) == CONST
)
934 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
936 *base_out
= XEXP (x
, 0);
937 *offset_out
= XEXP (x
, 1);
942 *offset_out
= const0_rtx
;
945 /* Express integer value X as some value Y plus a polynomial offset,
946 where Y is either const0_rtx, X or something within X (as opposed
947 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
950 strip_offset (rtx x
, poly_int64_pod
*offset_out
)
952 rtx base
= const0_rtx
;
954 if (GET_CODE (test
) == CONST
)
955 test
= XEXP (test
, 0);
956 if (GET_CODE (test
) == PLUS
)
958 base
= XEXP (test
, 0);
959 test
= XEXP (test
, 1);
961 if (poly_int_rtx_p (test
, offset_out
))
967 /* Return the argument size in REG_ARGS_SIZE note X. */
970 get_args_size (const_rtx x
)
972 gcc_checking_assert (REG_NOTE_KIND (x
) == REG_ARGS_SIZE
);
973 return rtx_to_poly_int64 (XEXP (x
, 0));
976 /* Return the number of places FIND appears within X. If COUNT_DEST is
977 zero, we do not count occurrences inside the destination of a SET. */
980 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
984 const char *format_ptr
;
1002 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
1004 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
1008 if (MEM_P (find
) && rtx_equal_p (x
, find
))
1013 if (SET_DEST (x
) == find
&& ! count_dest
)
1014 return count_occurrences (SET_SRC (x
), find
, count_dest
);
1021 format_ptr
= GET_RTX_FORMAT (code
);
1024 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
1026 switch (*format_ptr
++)
1029 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
1033 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1034 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
1042 /* Return TRUE if OP is a register or subreg of a register that
1043 holds an unsigned quantity. Otherwise, return FALSE. */
1046 unsigned_reg_p (rtx op
)
1050 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
1053 if (GET_CODE (op
) == SUBREG
1054 && SUBREG_PROMOTED_SIGN (op
))
1061 /* Nonzero if register REG appears somewhere within IN.
1062 Also works if REG is not a register; in this case it checks
1063 for a subexpression of IN that is Lisp "equal" to REG. */
1066 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1078 if (GET_CODE (in
) == LABEL_REF
)
1079 return reg
== label_ref_label (in
);
1081 code
= GET_CODE (in
);
1085 /* Compare registers by number. */
1087 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1089 /* These codes have no constituent expressions
1096 /* These are kept unique for a given value. */
1103 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1106 fmt
= GET_RTX_FORMAT (code
);
1108 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1113 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1114 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1117 else if (fmt
[i
] == 'e'
1118 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1124 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1125 no CODE_LABEL insn. */
1128 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1133 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1139 /* Nonzero if register REG is used in an insn between
1140 FROM_INSN and TO_INSN (exclusive of those two). */
1143 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1144 const rtx_insn
*to_insn
)
1148 if (from_insn
== to_insn
)
1151 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1152 if (NONDEBUG_INSN_P (insn
)
1153 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1154 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1159 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1160 is entirely replaced by a new value and the only use is as a SET_DEST,
1161 we do not consider it a reference. */
1164 reg_referenced_p (const_rtx x
, const_rtx body
)
1168 switch (GET_CODE (body
))
1171 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1174 /* If the destination is anything other than PC, a REG or a SUBREG
1175 of a REG that occupies all of the REG, the insn references X if
1176 it is mentioned in the destination. */
1177 if (GET_CODE (SET_DEST (body
)) != PC
1178 && !REG_P (SET_DEST (body
))
1179 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1180 && REG_P (SUBREG_REG (SET_DEST (body
)))
1181 && !read_modify_subreg_p (SET_DEST (body
)))
1182 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1187 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1188 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1195 return reg_overlap_mentioned_p (x
, body
);
1198 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1201 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1204 case UNSPEC_VOLATILE
:
1205 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1206 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1211 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1212 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1217 if (MEM_P (XEXP (body
, 0)))
1218 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1223 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1225 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1232 /* Nonzero if register REG is set or clobbered in an insn between
1233 FROM_INSN and TO_INSN (exclusive of those two). */
1236 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1237 const rtx_insn
*to_insn
)
1239 const rtx_insn
*insn
;
1241 if (from_insn
== to_insn
)
1244 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1245 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1250 /* Return true if REG is set or clobbered inside INSN. */
1253 reg_set_p (const_rtx reg
, const_rtx insn
)
1255 /* After delay slot handling, call and branch insns might be in a
1256 sequence. Check all the elements there. */
1257 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1259 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1260 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1266 /* We can be passed an insn or part of one. If we are passed an insn,
1267 check if a side-effect of the insn clobbers REG. */
1269 && (FIND_REG_INC_NOTE (insn
, reg
)
1272 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1273 && (insn_callee_abi (as_a
<const rtx_insn
*> (insn
))
1274 .clobbers_reg_p (GET_MODE (reg
), REGNO (reg
))))
1276 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1279 /* There are no REG_INC notes for SP autoinc. */
1280 if (reg
== stack_pointer_rtx
&& INSN_P (insn
))
1282 subrtx_var_iterator::array_type array
;
1283 FOR_EACH_SUBRTX_VAR (iter
, array
, PATTERN (insn
), NONCONST
)
1288 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
1290 if (XEXP (XEXP (mem
, 0), 0) == stack_pointer_rtx
)
1292 iter
.skip_subrtxes ();
1297 return set_of (reg
, insn
) != NULL_RTX
;
1300 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1301 only if none of them are modified between START and END. Return 1 if
1302 X contains a MEM; this routine does use memory aliasing. */
1305 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1307 const enum rtx_code code
= GET_CODE (x
);
1327 if (modified_between_p (XEXP (x
, 0), start
, end
))
1329 if (MEM_READONLY_P (x
))
1331 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1332 if (memory_modified_in_insn_p (x
, insn
))
1337 return reg_set_between_p (x
, start
, end
);
1343 fmt
= GET_RTX_FORMAT (code
);
1344 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1346 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1349 else if (fmt
[i
] == 'E')
1350 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1351 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1358 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1359 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1360 does use memory aliasing. */
1363 modified_in_p (const_rtx x
, const_rtx insn
)
1365 const enum rtx_code code
= GET_CODE (x
);
1381 if (modified_in_p (XEXP (x
, 0), insn
))
1383 if (MEM_READONLY_P (x
))
1385 if (memory_modified_in_insn_p (x
, insn
))
1390 return reg_set_p (x
, insn
);
1396 fmt
= GET_RTX_FORMAT (code
);
1397 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1399 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1402 else if (fmt
[i
] == 'E')
1403 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1404 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1411 /* Return true if X is a SUBREG and if storing a value to X would
1412 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1413 target, using a SUBREG to store to one half of a DImode REG would
1414 preserve the other half. */
1417 read_modify_subreg_p (const_rtx x
)
1419 if (GET_CODE (x
) != SUBREG
)
1421 poly_uint64 isize
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)));
1422 poly_uint64 osize
= GET_MODE_SIZE (GET_MODE (x
));
1423 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x
)));
1424 /* The inner and outer modes of a subreg must be ordered, so that we
1425 can tell whether they're paradoxical or partial. */
1426 gcc_checking_assert (ordered_p (isize
, osize
));
1427 return (maybe_gt (isize
, osize
) && maybe_gt (isize
, regsize
));
1430 /* Helper function for set_of. */
1438 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1440 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1441 if (rtx_equal_p (x
, data
->pat
)
1442 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1446 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1447 (either directly or via STRICT_LOW_PART and similar modifiers). */
1449 set_of (const_rtx pat
, const_rtx insn
)
1451 struct set_of_data data
;
1452 data
.found
= NULL_RTX
;
1454 note_pattern_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1458 /* Check whether instruction pattern PAT contains a SET with the following
1461 - the SET is executed unconditionally; and
1463 - the destination of the SET is a REG that contains REGNO; or
1465 - the destination of the SET is a SUBREG of such a REG; and
1466 - writing to the subreg clobbers all of the SUBREG_REG
1467 (in other words, read_modify_subreg_p is false).
1469 If PAT does have a SET like that, return the set, otherwise return null.
1471 This is intended to be an alternative to single_set for passes that
1472 can handle patterns with multiple_sets. */
1474 simple_regno_set (rtx pat
, unsigned int regno
)
1476 if (GET_CODE (pat
) == PARALLEL
)
1478 int last
= XVECLEN (pat
, 0) - 1;
1479 for (int i
= 0; i
< last
; ++i
)
1480 if (rtx set
= simple_regno_set (XVECEXP (pat
, 0, i
), regno
))
1483 pat
= XVECEXP (pat
, 0, last
);
1486 if (GET_CODE (pat
) == SET
1487 && covers_regno_no_parallel_p (SET_DEST (pat
), regno
))
1493 /* Add all hard register in X to *PSET. */
1495 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1497 subrtx_iterator::array_type array
;
1498 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1500 const_rtx x
= *iter
;
1501 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1502 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1506 /* This function, called through note_stores, collects sets and
1507 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1510 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1512 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1513 if (REG_P (x
) && HARD_REGISTER_P (x
))
1514 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1517 /* Examine INSN, and compute the set of hard registers written by it.
1518 Store it in *PSET. Should only be called after reload.
1520 IMPLICIT is true if we should include registers that are fully-clobbered
1521 by calls. This should be used with caution, since it doesn't include
1522 partially-clobbered registers. */
1524 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1528 CLEAR_HARD_REG_SET (*pset
);
1529 note_stores (insn
, record_hard_reg_sets
, pset
);
1530 if (CALL_P (insn
) && implicit
)
1531 *pset
|= insn_callee_abi (insn
).full_reg_clobbers ();
1532 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1533 if (REG_NOTE_KIND (link
) == REG_INC
)
1534 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1537 /* Like record_hard_reg_sets, but called through note_uses. */
1539 record_hard_reg_uses (rtx
*px
, void *data
)
1541 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1544 /* Given an INSN, return a SET expression if this insn has only a single SET.
1545 It may also have CLOBBERs, USEs, or SET whose output
1546 will not be used, which we ignore. */
1549 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1552 int set_verified
= 1;
1555 if (GET_CODE (pat
) == PARALLEL
)
1557 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1559 rtx sub
= XVECEXP (pat
, 0, i
);
1560 switch (GET_CODE (sub
))
1567 /* We can consider insns having multiple sets, where all
1568 but one are dead as single set insns. In common case
1569 only single set is present in the pattern so we want
1570 to avoid checking for REG_UNUSED notes unless necessary.
1572 When we reach set first time, we just expect this is
1573 the single set we are looking for and only when more
1574 sets are found in the insn, we check them. */
1577 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1578 && !side_effects_p (set
))
1584 set
= sub
, set_verified
= 0;
1585 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1586 || side_effects_p (sub
))
1598 /* Given an INSN, return nonzero if it has more than one SET, else return
1602 multiple_sets (const_rtx insn
)
1607 /* INSN must be an insn. */
1608 if (! INSN_P (insn
))
1611 /* Only a PARALLEL can have multiple SETs. */
1612 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1614 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1615 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1617 /* If we have already found a SET, then return now. */
1625 /* Either zero or one SET. */
1629 /* Return nonzero if the destination of SET equals the source
1630 and there are no side effects. */
1633 set_noop_p (const_rtx set
)
1635 rtx src
= SET_SRC (set
);
1636 rtx dst
= SET_DEST (set
);
1638 if (dst
== pc_rtx
&& src
== pc_rtx
)
1641 if (MEM_P (dst
) && MEM_P (src
))
1642 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1644 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1645 return rtx_equal_p (XEXP (dst
, 0), src
)
1646 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1647 && !side_effects_p (src
);
1649 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1650 dst
= XEXP (dst
, 0);
1652 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1654 if (maybe_ne (SUBREG_BYTE (src
), SUBREG_BYTE (dst
)))
1656 src
= SUBREG_REG (src
);
1657 dst
= SUBREG_REG (dst
);
1658 if (GET_MODE (src
) != GET_MODE (dst
))
1659 /* It is hard to tell whether subregs refer to the same bits, so act
1660 conservatively and return 0. */
1664 /* It is a NOOP if destination overlaps with selected src vector
1666 if (GET_CODE (src
) == VEC_SELECT
1667 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1668 && HARD_REGISTER_P (XEXP (src
, 0))
1669 && HARD_REGISTER_P (dst
))
1672 rtx par
= XEXP (src
, 1);
1673 rtx src0
= XEXP (src
, 0);
1675 if (!poly_int_rtx_p (XVECEXP (par
, 0, 0), &c0
))
1677 poly_int64 offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1679 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1682 if (!poly_int_rtx_p (XVECEXP (par
, 0, i
), &c0i
)
1683 || maybe_ne (c0i
, c0
+ i
))
1687 REG_CAN_CHANGE_MODE_P (REGNO (dst
), GET_MODE (src0
), GET_MODE (dst
))
1688 && simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1689 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1692 return (REG_P (src
) && REG_P (dst
)
1693 && REGNO (src
) == REGNO (dst
));
1696 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1700 noop_move_p (const rtx_insn
*insn
)
1702 rtx pat
= PATTERN (insn
);
1704 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1707 /* Check the code to be executed for COND_EXEC. */
1708 if (GET_CODE (pat
) == COND_EXEC
)
1709 pat
= COND_EXEC_CODE (pat
);
1711 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1714 if (GET_CODE (pat
) == PARALLEL
)
1717 /* If nothing but SETs of registers to themselves,
1718 this insn can also be deleted. */
1719 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1721 rtx tem
= XVECEXP (pat
, 0, i
);
1723 if (GET_CODE (tem
) == USE
|| GET_CODE (tem
) == CLOBBER
)
1726 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1736 /* Return nonzero if register in range [REGNO, ENDREGNO)
1737 appears either explicitly or implicitly in X
1738 other than being stored into.
1740 References contained within the substructure at LOC do not count.
1741 LOC may be zero, meaning don't ignore anything. */
1744 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1748 unsigned int x_regno
;
1753 /* The contents of a REG_NONNEG note is always zero, so we must come here
1754 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1758 code
= GET_CODE (x
);
1763 x_regno
= REGNO (x
);
1765 /* If we modifying the stack, frame, or argument pointer, it will
1766 clobber a virtual register. In fact, we could be more precise,
1767 but it isn't worth it. */
1768 if ((x_regno
== STACK_POINTER_REGNUM
1769 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1770 && x_regno
== ARG_POINTER_REGNUM
)
1771 || x_regno
== FRAME_POINTER_REGNUM
)
1772 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1775 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1778 /* If this is a SUBREG of a hard reg, we can see exactly which
1779 registers are being modified. Otherwise, handle normally. */
1780 if (REG_P (SUBREG_REG (x
))
1781 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1783 unsigned int inner_regno
= subreg_regno (x
);
1784 unsigned int inner_endregno
1785 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1786 ? subreg_nregs (x
) : 1);
1788 return endregno
> inner_regno
&& regno
< inner_endregno
;
1794 if (&SET_DEST (x
) != loc
1795 /* Note setting a SUBREG counts as referring to the REG it is in for
1796 a pseudo but not for hard registers since we can
1797 treat each word individually. */
1798 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1799 && loc
!= &SUBREG_REG (SET_DEST (x
))
1800 && REG_P (SUBREG_REG (SET_DEST (x
)))
1801 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1802 && refers_to_regno_p (regno
, endregno
,
1803 SUBREG_REG (SET_DEST (x
)), loc
))
1804 || (!REG_P (SET_DEST (x
))
1805 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1808 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1817 /* X does not match, so try its subexpressions. */
1819 fmt
= GET_RTX_FORMAT (code
);
1820 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1822 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1830 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1833 else if (fmt
[i
] == 'E')
1836 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1837 if (loc
!= &XVECEXP (x
, i
, j
)
1838 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1845 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1846 we check if any register number in X conflicts with the relevant register
1847 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1848 contains a MEM (we don't bother checking for memory addresses that can't
1849 conflict because we expect this to be a rare case. */
1852 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1854 unsigned int regno
, endregno
;
1856 /* If either argument is a constant, then modifying X cannot
1857 affect IN. Here we look at IN, we can profitably combine
1858 CONSTANT_P (x) with the switch statement below. */
1859 if (CONSTANT_P (in
))
1863 switch (GET_CODE (x
))
1866 case STRICT_LOW_PART
:
1869 /* Overly conservative. */
1874 regno
= REGNO (SUBREG_REG (x
));
1875 if (regno
< FIRST_PSEUDO_REGISTER
)
1876 regno
= subreg_regno (x
);
1877 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1878 ? subreg_nregs (x
) : 1);
1883 endregno
= END_REGNO (x
);
1885 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1895 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1896 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1899 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1902 else if (fmt
[i
] == 'E')
1905 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1906 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1915 return reg_mentioned_p (x
, in
);
1921 /* If any register in here refers to it we return true. */
1922 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1923 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1924 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1930 gcc_assert (CONSTANT_P (x
));
1935 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1936 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1937 ignored by note_stores, but passed to FUN.
1939 FUN receives three arguments:
1940 1. the REG, MEM or PC being stored in or clobbered,
1941 2. the SET or CLOBBER rtx that does the store,
1942 3. the pointer DATA provided to note_stores.
1944 If the item being stored in or clobbered is a SUBREG of a hard register,
1945 the SUBREG will be passed. */
1948 note_pattern_stores (const_rtx x
,
1949 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1953 if (GET_CODE (x
) == COND_EXEC
)
1954 x
= COND_EXEC_CODE (x
);
1956 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1958 rtx dest
= SET_DEST (x
);
1960 while ((GET_CODE (dest
) == SUBREG
1961 && (!REG_P (SUBREG_REG (dest
))
1962 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1963 || GET_CODE (dest
) == ZERO_EXTRACT
1964 || GET_CODE (dest
) == STRICT_LOW_PART
)
1965 dest
= XEXP (dest
, 0);
1967 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1968 each of whose first operand is a register. */
1969 if (GET_CODE (dest
) == PARALLEL
)
1971 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1972 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1973 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1976 (*fun
) (dest
, x
, data
);
1979 else if (GET_CODE (x
) == PARALLEL
)
1980 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1981 note_pattern_stores (XVECEXP (x
, 0, i
), fun
, data
);
1984 /* Same, but for an instruction. If the instruction is a call, include
1985 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1988 note_stores (const rtx_insn
*insn
,
1989 void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1992 for (rtx link
= CALL_INSN_FUNCTION_USAGE (insn
);
1993 link
; link
= XEXP (link
, 1))
1994 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1995 note_pattern_stores (XEXP (link
, 0), fun
, data
);
1996 note_pattern_stores (PATTERN (insn
), fun
, data
);
1999 /* Like notes_stores, but call FUN for each expression that is being
2000 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
2001 FUN for each expression, not any interior subexpressions. FUN receives a
2002 pointer to the expression and the DATA passed to this function.
2004 Note that this is not quite the same test as that done in reg_referenced_p
2005 since that considers something as being referenced if it is being
2006 partially set, while we do not. */
2009 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
2014 switch (GET_CODE (body
))
2017 (*fun
) (&COND_EXEC_TEST (body
), data
);
2018 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
2022 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2023 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
2027 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2028 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
2032 (*fun
) (&XEXP (body
, 0), data
);
2036 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
2037 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
2041 (*fun
) (&TRAP_CONDITION (body
), data
);
2045 (*fun
) (&XEXP (body
, 0), data
);
2049 case UNSPEC_VOLATILE
:
2050 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
2051 (*fun
) (&XVECEXP (body
, 0, i
), data
);
2055 if (MEM_P (XEXP (body
, 0)))
2056 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
2061 rtx dest
= SET_DEST (body
);
2063 /* For sets we replace everything in source plus registers in memory
2064 expression in store and operands of a ZERO_EXTRACT. */
2065 (*fun
) (&SET_SRC (body
), data
);
2067 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2069 (*fun
) (&XEXP (dest
, 1), data
);
2070 (*fun
) (&XEXP (dest
, 2), data
);
2073 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
2074 dest
= XEXP (dest
, 0);
2077 (*fun
) (&XEXP (dest
, 0), data
);
2082 /* All the other possibilities never store. */
2083 (*fun
) (pbody
, data
);
2088 /* Try to add a description of REG X to this object, stopping once
2089 the REF_END limit has been reached. FLAGS is a bitmask of
2090 rtx_obj_reference flags that describe the context. */
2093 rtx_properties::try_to_add_reg (const_rtx x
, unsigned int flags
)
2095 if (REG_NREGS (x
) != 1)
2096 flags
|= rtx_obj_flags::IS_MULTIREG
;
2097 machine_mode mode
= GET_MODE (x
);
2098 unsigned int start_regno
= REGNO (x
);
2099 unsigned int end_regno
= END_REGNO (x
);
2100 for (unsigned int regno
= start_regno
; regno
< end_regno
; ++regno
)
2101 if (ref_iter
!= ref_end
)
2102 *ref_iter
++ = rtx_obj_reference (regno
, flags
, mode
,
2103 regno
- start_regno
);
2106 /* Add a description of destination X to this object. FLAGS is a bitmask
2107 of rtx_obj_reference flags that describe the context.
2109 This routine accepts all rtxes that can legitimately appear in a
2113 rtx_properties::try_to_add_dest (const_rtx x
, unsigned int flags
)
2115 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
2116 each of whose first operand is a register. */
2117 if (__builtin_expect (GET_CODE (x
) == PARALLEL
, 0))
2119 for (int i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
2120 if (rtx dest
= XEXP (XVECEXP (x
, 0, i
), 0))
2121 try_to_add_dest (dest
, flags
);
2125 unsigned int base_flags
= flags
& rtx_obj_flags::STICKY_FLAGS
;
2126 flags
|= rtx_obj_flags::IS_WRITE
;
2128 if (GET_CODE (x
) == ZERO_EXTRACT
)
2130 try_to_add_src (XEXP (x
, 1), base_flags
);
2131 try_to_add_src (XEXP (x
, 2), base_flags
);
2132 flags
|= rtx_obj_flags::IS_READ
;
2135 else if (GET_CODE (x
) == STRICT_LOW_PART
)
2137 flags
|= rtx_obj_flags::IS_READ
;
2140 else if (GET_CODE (x
) == SUBREG
)
2142 flags
|= rtx_obj_flags::IN_SUBREG
;
2143 if (read_modify_subreg_p (x
))
2144 flags
|= rtx_obj_flags::IS_READ
;
2152 if (ref_iter
!= ref_end
)
2153 *ref_iter
++ = rtx_obj_reference (MEM_REGNO
, flags
, GET_MODE (x
));
2155 unsigned int addr_flags
= base_flags
| rtx_obj_flags::IN_MEM_STORE
;
2156 if (flags
& rtx_obj_flags::IS_READ
)
2157 addr_flags
|= rtx_obj_flags::IN_MEM_LOAD
;
2158 try_to_add_src (XEXP (x
, 0), addr_flags
);
2162 if (__builtin_expect (REG_P (x
), 1))
2164 /* We want to keep sp alive everywhere - by making all
2165 writes to sp also use sp. */
2166 if (REGNO (x
) == STACK_POINTER_REGNUM
)
2167 flags
|= rtx_obj_flags::IS_READ
;
2168 try_to_add_reg (x
, flags
);
2173 /* Try to add a description of source X to this object, stopping once
2174 the REF_END limit has been reached. FLAGS is a bitmask of
2175 rtx_obj_reference flags that describe the context.
2177 This routine accepts all rtxes that can legitimately appear in a SET_SRC. */
2180 rtx_properties::try_to_add_src (const_rtx x
, unsigned int flags
)
2182 unsigned int base_flags
= flags
& rtx_obj_flags::STICKY_FLAGS
;
2183 subrtx_iterator::array_type array
;
2184 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2186 const_rtx x
= *iter
;
2187 rtx_code code
= GET_CODE (x
);
2189 try_to_add_reg (x
, flags
| rtx_obj_flags::IS_READ
);
2190 else if (code
== MEM
)
2192 if (MEM_VOLATILE_P (x
))
2193 has_volatile_refs
= true;
2195 if (!MEM_READONLY_P (x
) && ref_iter
!= ref_end
)
2197 auto mem_flags
= flags
| rtx_obj_flags::IS_READ
;
2198 *ref_iter
++ = rtx_obj_reference (MEM_REGNO
, mem_flags
,
2202 try_to_add_src (XEXP (x
, 0),
2203 base_flags
| rtx_obj_flags::IN_MEM_LOAD
);
2204 iter
.skip_subrtxes ();
2206 else if (code
== SUBREG
)
2208 try_to_add_src (SUBREG_REG (x
), flags
| rtx_obj_flags::IN_SUBREG
);
2209 iter
.skip_subrtxes ();
2211 else if (code
== UNSPEC_VOLATILE
)
2212 has_volatile_refs
= true;
2213 else if (code
== ASM_INPUT
|| code
== ASM_OPERANDS
)
2216 if (MEM_VOLATILE_P (x
))
2217 has_volatile_refs
= true;
2219 else if (code
== PRE_INC
2223 || code
== PRE_MODIFY
2224 || code
== POST_MODIFY
)
2226 has_pre_post_modify
= true;
2228 unsigned int addr_flags
= (base_flags
2229 | rtx_obj_flags::IS_PRE_POST_MODIFY
2230 | rtx_obj_flags::IS_READ
);
2231 try_to_add_dest (XEXP (x
, 0), addr_flags
);
2232 if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2233 iter
.substitute (XEXP (XEXP (x
, 1), 1));
2235 iter
.skip_subrtxes ();
2237 else if (code
== CALL
)
2242 /* Try to add a description of instruction pattern PAT to this object,
2243 stopping once the REF_END limit has been reached. */
2246 rtx_properties::try_to_add_pattern (const_rtx pat
)
2248 switch (GET_CODE (pat
))
2251 try_to_add_src (COND_EXEC_TEST (pat
));
2252 try_to_add_pattern (COND_EXEC_CODE (pat
));
2257 int last
= XVECLEN (pat
, 0) - 1;
2258 for (int i
= 0; i
< last
; ++i
)
2259 try_to_add_pattern (XVECEXP (pat
, 0, i
));
2260 try_to_add_pattern (XVECEXP (pat
, 0, last
));
2265 for (int i
= 0, len
= ASM_OPERANDS_INPUT_LENGTH (pat
); i
< len
; ++i
)
2266 try_to_add_src (ASM_OPERANDS_INPUT (pat
, i
));
2270 try_to_add_dest (XEXP (pat
, 0), rtx_obj_flags::IS_CLOBBER
);
2274 try_to_add_dest (SET_DEST (pat
));
2275 try_to_add_src (SET_SRC (pat
));
2279 /* All the other possibilities never store and can use a normal
2280 rtx walk. This includes:
2286 - UNSPEC_VOLATILE. */
2287 try_to_add_src (pat
);
2292 /* Try to add a description of INSN to this object, stopping once
2293 the REF_END limit has been reached. INCLUDE_NOTES is true if the
2294 description should include REG_EQUAL and REG_EQUIV notes; all such
2295 references will then be marked with rtx_obj_flags::IN_NOTE.
2297 For calls, this description includes all accesses in
2298 CALL_INSN_FUNCTION_USAGE. It also include all implicit accesses
2299 to global registers by the target function. However, it does not
2300 include clobbers performed by the target function; callers that want
2301 this information should instead use the function_abi interface. */
2304 rtx_properties::try_to_add_insn (const rtx_insn
*insn
, bool include_notes
)
2308 /* Non-const functions can read from global registers. Impure
2309 functions can also set them.
2311 Adding the global registers first removes a situation in which
2312 a fixed-form clobber of register R could come before a real set
2314 if (!hard_reg_set_empty_p (global_reg_set
)
2315 && !RTL_CONST_CALL_P (insn
))
2317 unsigned int flags
= rtx_obj_flags::IS_READ
;
2318 if (!RTL_PURE_CALL_P (insn
))
2319 flags
|= rtx_obj_flags::IS_WRITE
;
2320 for (unsigned int regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2321 /* As a special case, the stack pointer is invariant across calls
2322 even if it has been marked global; see the corresponding
2323 handling in df_get_call_refs. */
2324 if (regno
!= STACK_POINTER_REGNUM
2325 && global_regs
[regno
]
2326 && ref_iter
!= ref_end
)
2327 *ref_iter
++ = rtx_obj_reference (regno
, flags
,
2328 reg_raw_mode
[regno
], 0);
2330 /* Untyped calls implicitly set all function value registers.
2331 Again, we add them first in case the main pattern contains
2332 a fixed-form clobber. */
2333 if (find_reg_note (insn
, REG_UNTYPED_CALL
, NULL_RTX
))
2334 for (unsigned int regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2335 if (targetm
.calls
.function_value_regno_p (regno
)
2336 && ref_iter
!= ref_end
)
2337 *ref_iter
++ = rtx_obj_reference (regno
, rtx_obj_flags::IS_WRITE
,
2338 reg_raw_mode
[regno
], 0);
2339 if (ref_iter
!= ref_end
&& !RTL_CONST_CALL_P (insn
))
2341 auto mem_flags
= rtx_obj_flags::IS_READ
;
2342 if (!RTL_PURE_CALL_P (insn
))
2343 mem_flags
|= rtx_obj_flags::IS_WRITE
;
2344 *ref_iter
++ = rtx_obj_reference (MEM_REGNO
, mem_flags
, BLKmode
);
2346 try_to_add_pattern (PATTERN (insn
));
2347 for (rtx link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
2348 link
= XEXP (link
, 1))
2350 rtx x
= XEXP (link
, 0);
2351 if (GET_CODE (x
) == CLOBBER
)
2352 try_to_add_dest (XEXP (x
, 0), rtx_obj_flags::IS_CLOBBER
);
2353 else if (GET_CODE (x
) == USE
)
2354 try_to_add_src (XEXP (x
, 0));
2358 try_to_add_pattern (PATTERN (insn
));
2361 for (rtx note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2362 if (REG_NOTE_KIND (note
) == REG_EQUAL
2363 || REG_NOTE_KIND (note
) == REG_EQUIV
)
2364 try_to_add_note (XEXP (note
, 0));
2367 /* Grow the storage by a bit while keeping the contents of the first
2371 vec_rtx_properties_base::grow (ptrdiff_t start
)
2373 /* The same heuristic that vec uses. */
2374 ptrdiff_t new_elems
= (ref_end
- ref_begin
) * 3 / 2;
2375 if (ref_begin
== m_storage
)
2377 ref_begin
= XNEWVEC (rtx_obj_reference
, new_elems
);
2379 memcpy (ref_begin
, m_storage
, start
* sizeof (rtx_obj_reference
));
2382 ref_begin
= reinterpret_cast<rtx_obj_reference
*>
2383 (xrealloc (ref_begin
, new_elems
* sizeof (rtx_obj_reference
)));
2384 ref_iter
= ref_begin
+ start
;
2385 ref_end
= ref_begin
+ new_elems
;
2388 /* Return nonzero if X's old contents don't survive after INSN.
2389 This will be true if X is a register and X dies in INSN or because
2390 INSN entirely sets X.
2392 "Entirely set" means set directly and not through a SUBREG, or
2393 ZERO_EXTRACT, so no trace of the old contents remains.
2394 Likewise, REG_INC does not count.
2396 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2397 but for this use that makes no difference, since regs don't overlap
2398 during their lifetimes. Therefore, this function may be used
2399 at any time after deaths have been computed.
2401 If REG is a hard reg that occupies multiple machine registers, this
2402 function will only return 1 if each of those registers will be replaced
2406 dead_or_set_p (const rtx_insn
*insn
, const_rtx x
)
2408 unsigned int regno
, end_regno
;
2411 gcc_assert (REG_P (x
));
2414 end_regno
= END_REGNO (x
);
2415 for (i
= regno
; i
< end_regno
; i
++)
2416 if (! dead_or_set_regno_p (insn
, i
))
2422 /* Return TRUE iff DEST is a register or subreg of a register, is a
2423 complete rather than read-modify-write destination, and contains
2424 register TEST_REGNO. */
2427 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
2429 unsigned int regno
, endregno
;
2431 if (GET_CODE (dest
) == SUBREG
&& !read_modify_subreg_p (dest
))
2432 dest
= SUBREG_REG (dest
);
2437 regno
= REGNO (dest
);
2438 endregno
= END_REGNO (dest
);
2439 return (test_regno
>= regno
&& test_regno
< endregno
);
2442 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2443 any member matches the covers_regno_no_parallel_p criteria. */
2446 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
2448 if (GET_CODE (dest
) == PARALLEL
)
2450 /* Some targets place small structures in registers for return
2451 values of functions, and those registers are wrapped in
2452 PARALLELs that we may see as the destination of a SET. */
2455 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2457 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2458 if (inner
!= NULL_RTX
2459 && covers_regno_no_parallel_p (inner
, test_regno
))
2466 return covers_regno_no_parallel_p (dest
, test_regno
);
2469 /* Utility function for dead_or_set_p to check an individual register. */
2472 dead_or_set_regno_p (const rtx_insn
*insn
, unsigned int test_regno
)
2476 /* See if there is a death note for something that includes TEST_REGNO. */
2477 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2481 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2484 pattern
= PATTERN (insn
);
2486 /* If a COND_EXEC is not executed, the value survives. */
2487 if (GET_CODE (pattern
) == COND_EXEC
)
2490 if (GET_CODE (pattern
) == SET
|| GET_CODE (pattern
) == CLOBBER
)
2491 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2492 else if (GET_CODE (pattern
) == PARALLEL
)
2496 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2498 rtx body
= XVECEXP (pattern
, 0, i
);
2500 if (GET_CODE (body
) == COND_EXEC
)
2501 body
= COND_EXEC_CODE (body
);
2503 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2504 && covers_regno_p (SET_DEST (body
), test_regno
))
2512 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2513 If DATUM is nonzero, look for one whose datum is DATUM. */
2516 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2520 gcc_checking_assert (insn
);
2522 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2523 if (! INSN_P (insn
))
2527 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2528 if (REG_NOTE_KIND (link
) == kind
)
2533 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2534 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2539 /* Return the reg-note of kind KIND in insn INSN which applies to register
2540 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2541 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2542 it might be the case that the note overlaps REGNO. */
2545 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2549 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2550 if (! INSN_P (insn
))
2553 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2554 if (REG_NOTE_KIND (link
) == kind
2555 /* Verify that it is a register, so that scratch and MEM won't cause a
2557 && REG_P (XEXP (link
, 0))
2558 && REGNO (XEXP (link
, 0)) <= regno
2559 && END_REGNO (XEXP (link
, 0)) > regno
)
2564 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2568 find_reg_equal_equiv_note (const_rtx insn
)
2575 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2576 if (REG_NOTE_KIND (link
) == REG_EQUAL
2577 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2579 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2580 insns that have multiple sets. Checking single_set to
2581 make sure of this is not the proper check, as explained
2582 in the comment in set_unique_reg_note.
2584 This should be changed into an assert. */
2585 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2592 /* Check whether INSN is a single_set whose source is known to be
2593 equivalent to a constant. Return that constant if so, otherwise
2597 find_constant_src (const rtx_insn
*insn
)
2601 set
= single_set (insn
);
2604 x
= avoid_constant_pool_reference (SET_SRC (set
));
2609 note
= find_reg_equal_equiv_note (insn
);
2610 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2611 return XEXP (note
, 0);
2616 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2617 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2620 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2622 /* If it's not a CALL_INSN, it can't possibly have a
2623 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2633 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2635 link
= XEXP (link
, 1))
2636 if (GET_CODE (XEXP (link
, 0)) == code
2637 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2642 unsigned int regno
= REGNO (datum
);
2644 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2645 to pseudo registers, so don't bother checking. */
2647 if (regno
< FIRST_PSEUDO_REGISTER
)
2649 unsigned int end_regno
= END_REGNO (datum
);
2652 for (i
= regno
; i
< end_regno
; i
++)
2653 if (find_regno_fusage (insn
, code
, i
))
2661 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2662 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2665 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2669 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2670 to pseudo registers, so don't bother checking. */
2672 if (regno
>= FIRST_PSEUDO_REGISTER
2676 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2680 if (GET_CODE (op
= XEXP (link
, 0)) == code
2681 && REG_P (reg
= XEXP (op
, 0))
2682 && REGNO (reg
) <= regno
2683 && END_REGNO (reg
) > regno
)
2691 /* Return true if KIND is an integer REG_NOTE. */
2694 int_reg_note_p (enum reg_note kind
)
2696 return kind
== REG_BR_PROB
;
2699 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2700 stored as the pointer to the next register note. */
2703 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2707 gcc_checking_assert (!int_reg_note_p (kind
));
2710 case REG_LABEL_TARGET
:
2711 case REG_LABEL_OPERAND
:
2713 /* These types of register notes use an INSN_LIST rather than an
2714 EXPR_LIST, so that copying is done right and dumps look
2716 note
= alloc_INSN_LIST (datum
, list
);
2717 PUT_REG_NOTE_KIND (note
, kind
);
2721 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2728 /* Add register note with kind KIND and datum DATUM to INSN. */
2731 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2733 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2736 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2739 add_int_reg_note (rtx_insn
*insn
, enum reg_note kind
, int datum
)
2741 gcc_checking_assert (int_reg_note_p (kind
));
2742 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2743 datum
, REG_NOTES (insn
));
2746 /* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2749 add_args_size_note (rtx_insn
*insn
, poly_int64 value
)
2751 gcc_checking_assert (!find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
));
2752 add_reg_note (insn
, REG_ARGS_SIZE
, gen_int_mode (value
, Pmode
));
2755 /* Add a register note like NOTE to INSN. */
2758 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2760 if (GET_CODE (note
) == INT_LIST
)
2761 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2763 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2766 /* Duplicate NOTE and return the copy. */
2768 duplicate_reg_note (rtx note
)
2770 reg_note kind
= REG_NOTE_KIND (note
);
2772 if (GET_CODE (note
) == INT_LIST
)
2773 return gen_rtx_INT_LIST ((machine_mode
) kind
, XINT (note
, 0), NULL_RTX
);
2774 else if (GET_CODE (note
) == EXPR_LIST
)
2775 return alloc_reg_note (kind
, copy_insn_1 (XEXP (note
, 0)), NULL_RTX
);
2777 return alloc_reg_note (kind
, XEXP (note
, 0), NULL_RTX
);
2780 /* Remove register note NOTE from the REG_NOTES of INSN. */
2783 remove_note (rtx_insn
*insn
, const_rtx note
)
2787 if (note
== NULL_RTX
)
2790 if (REG_NOTES (insn
) == note
)
2791 REG_NOTES (insn
) = XEXP (note
, 1);
2793 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2794 if (XEXP (link
, 1) == note
)
2796 XEXP (link
, 1) = XEXP (note
, 1);
2800 switch (REG_NOTE_KIND (note
))
2804 df_notes_rescan (insn
);
2811 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2812 If NO_RESCAN is false and any notes were removed, call
2813 df_notes_rescan. Return true if any note has been removed. */
2816 remove_reg_equal_equiv_notes (rtx_insn
*insn
, bool no_rescan
)
2821 loc
= ®_NOTES (insn
);
2824 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2825 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2827 *loc
= XEXP (*loc
, 1);
2831 loc
= &XEXP (*loc
, 1);
2833 if (ret
&& !no_rescan
)
2834 df_notes_rescan (insn
);
2838 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2841 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2848 /* This loop is a little tricky. We cannot just go down the chain because
2849 it is being modified by some actions in the loop. So we just iterate
2850 over the head. We plan to drain the list anyway. */
2851 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2853 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2854 rtx note
= find_reg_equal_equiv_note (insn
);
2856 /* This assert is generally triggered when someone deletes a REG_EQUAL
2857 or REG_EQUIV note by hacking the list manually rather than calling
2861 remove_note (insn
, note
);
2865 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2866 return 1 if it is found. A simple equality test is used to determine if
2870 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2874 for (x
= listp
; x
; x
= XEXP (x
, 1))
2875 if (node
== XEXP (x
, 0))
2881 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2882 remove that entry from the list if it is found.
2884 A simple equality test is used to determine if NODE matches. */
2887 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2889 rtx_expr_list
*temp
= *listp
;
2890 rtx_expr_list
*prev
= NULL
;
2894 if (node
== temp
->element ())
2896 /* Splice the node out of the list. */
2898 XEXP (prev
, 1) = temp
->next ();
2900 *listp
= temp
->next ();
2906 temp
= temp
->next ();
2910 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2911 remove that entry from the list if it is found.
2913 A simple equality test is used to determine if NODE matches. */
2916 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2918 rtx_insn_list
*temp
= *listp
;
2919 rtx_insn_list
*prev
= NULL
;
2923 if (node
== temp
->insn ())
2925 /* Splice the node out of the list. */
2927 XEXP (prev
, 1) = temp
->next ();
2929 *listp
= temp
->next ();
2935 temp
= temp
->next ();
2939 /* Nonzero if X contains any volatile instructions. These are instructions
2940 which may cause unpredictable machine state instructions, and thus no
2941 instructions or register uses should be moved or combined across them.
2942 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2945 volatile_insn_p (const_rtx x
)
2947 const RTX_CODE code
= GET_CODE (x
);
2964 case UNSPEC_VOLATILE
:
2969 if (MEM_VOLATILE_P (x
))
2976 /* Recursively scan the operands of this expression. */
2979 const char *const fmt
= GET_RTX_FORMAT (code
);
2982 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2986 if (volatile_insn_p (XEXP (x
, i
)))
2989 else if (fmt
[i
] == 'E')
2992 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2993 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
3001 /* Nonzero if X contains any volatile memory references
3002 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
3005 volatile_refs_p (const_rtx x
)
3007 const RTX_CODE code
= GET_CODE (x
);
3022 case UNSPEC_VOLATILE
:
3028 if (MEM_VOLATILE_P (x
))
3035 /* Recursively scan the operands of this expression. */
3038 const char *const fmt
= GET_RTX_FORMAT (code
);
3041 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3045 if (volatile_refs_p (XEXP (x
, i
)))
3048 else if (fmt
[i
] == 'E')
3051 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3052 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
3060 /* Similar to above, except that it also rejects register pre- and post-
3064 side_effects_p (const_rtx x
)
3066 const RTX_CODE code
= GET_CODE (x
);
3082 /* Reject CLOBBER with a non-VOID mode. These are made by combine.cc
3083 when some combination can't be done. If we see one, don't think
3084 that we can simplify the expression. */
3085 return (GET_MODE (x
) != VOIDmode
);
3094 case UNSPEC_VOLATILE
:
3100 if (MEM_VOLATILE_P (x
))
3107 /* Recursively scan the operands of this expression. */
3110 const char *fmt
= GET_RTX_FORMAT (code
);
3113 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3117 if (side_effects_p (XEXP (x
, i
)))
3120 else if (fmt
[i
] == 'E')
3123 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3124 if (side_effects_p (XVECEXP (x
, i
, j
)))
3132 /* Return nonzero if evaluating rtx X might cause a trap.
3133 FLAGS controls how to consider MEMs. A nonzero means the context
3134 of the access may have changed from the original, such that the
3135 address may have become invalid. */
3138 may_trap_p_1 (const_rtx x
, unsigned flags
)
3144 /* We make no distinction currently, but this function is part of
3145 the internal target-hooks ABI so we keep the parameter as
3146 "unsigned flags". */
3147 bool code_changed
= flags
!= 0;
3151 code
= GET_CODE (x
);
3154 /* Handle these cases quickly. */
3165 return targetm
.unspec_may_trap_p (x
, flags
);
3167 case UNSPEC_VOLATILE
:
3173 return MEM_VOLATILE_P (x
);
3175 /* Memory ref can trap unless it's a static var or a stack slot. */
3177 /* Recognize specific pattern of stack checking probes. */
3178 if (flag_stack_check
3179 && MEM_VOLATILE_P (x
)
3180 && XEXP (x
, 0) == stack_pointer_rtx
)
3182 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
3183 reference; moving it out of context such as when moving code
3184 when optimizing, might cause its address to become invalid. */
3186 || !MEM_NOTRAP_P (x
))
3188 poly_int64 size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : -1;
3189 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
3190 GET_MODE (x
), code_changed
);
3195 /* Division by a non-constant might trap. */
3200 if (HONOR_SNANS (x
))
3202 if (FLOAT_MODE_P (GET_MODE (x
)))
3203 return flag_trapping_math
;
3204 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
3206 if (GET_CODE (XEXP (x
, 1)) == CONST_VECTOR
)
3208 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
3209 unsigned int n_elts
;
3210 rtx op
= XEXP (x
, 1);
3211 if (!GET_MODE_NUNITS (GET_MODE (op
)).is_constant (&n_elts
))
3213 if (!CONST_VECTOR_DUPLICATE_P (op
))
3215 for (unsigned i
= 0; i
< (unsigned int) XVECLEN (op
, 0); i
++)
3216 if (CONST_VECTOR_ENCODED_ELT (op
, i
) == const0_rtx
)
3220 for (unsigned i
= 0; i
< n_elts
; i
++)
3221 if (CONST_VECTOR_ELT (op
, i
) == const0_rtx
)
3227 /* An EXPR_LIST is used to represent a function call. This
3228 certainly may trap. */
3237 /* Some floating point comparisons may trap. */
3238 if (!flag_trapping_math
)
3240 /* ??? There is no machine independent way to check for tests that trap
3241 when COMPARE is used, though many targets do make this distinction.
3242 For instance, sparc uses CCFPE for compares which generate exceptions
3243 and CCFP for compares which do not generate exceptions. */
3246 /* But often the compare has some CC mode, so check operand
3248 if (HONOR_NANS (XEXP (x
, 0))
3249 || HONOR_NANS (XEXP (x
, 1)))
3255 if (HONOR_SNANS (x
))
3257 /* Often comparison is CC mode, so check operand modes. */
3258 if (HONOR_SNANS (XEXP (x
, 0))
3259 || HONOR_SNANS (XEXP (x
, 1)))
3265 /* Conversion of floating point might trap. */
3266 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
3277 /* These operations don't trap even with floating point. */
3281 /* Any floating arithmetic may trap. */
3282 if (FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
3286 fmt
= GET_RTX_FORMAT (code
);
3287 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3291 if (may_trap_p_1 (XEXP (x
, i
), flags
))
3294 else if (fmt
[i
] == 'E')
3297 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3298 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
3305 /* Return nonzero if evaluating rtx X might cause a trap. */
3308 may_trap_p (const_rtx x
)
3310 return may_trap_p_1 (x
, 0);
3313 /* Same as above, but additionally return nonzero if evaluating rtx X might
3314 cause a fault. We define a fault for the purpose of this function as a
3315 erroneous execution condition that cannot be encountered during the normal
3316 execution of a valid program; the typical example is an unaligned memory
3317 access on a strict alignment machine. The compiler guarantees that it
3318 doesn't generate code that will fault from a valid program, but this
3319 guarantee doesn't mean anything for individual instructions. Consider
3320 the following example:
3322 struct S { int d; union { char *cp; int *ip; }; };
3324 int foo(struct S *s)
3332 on a strict alignment machine. In a valid program, foo will never be
3333 invoked on a structure for which d is equal to 1 and the underlying
3334 unique field of the union not aligned on a 4-byte boundary, but the
3335 expression *s->ip might cause a fault if considered individually.
3337 At the RTL level, potentially problematic expressions will almost always
3338 verify may_trap_p; for example, the above dereference can be emitted as
3339 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3340 However, suppose that foo is inlined in a caller that causes s->cp to
3341 point to a local character variable and guarantees that s->d is not set
3342 to 1; foo may have been effectively translated into pseudo-RTL as:
3345 (set (reg:SI) (mem:SI (%fp - 7)))
3347 (set (reg:QI) (mem:QI (%fp - 7)))
3349 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3350 memory reference to a stack slot, but it will certainly cause a fault
3351 on a strict alignment machine. */
3354 may_trap_or_fault_p (const_rtx x
)
3356 return may_trap_p_1 (x
, 1);
3359 /* Replace any occurrence of FROM in X with TO. The function does
3360 not enter into CONST_DOUBLE for the replace.
3362 Note that copying is not done so X must not be shared unless all copies
3365 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3366 those pointer-equal ones. */
3369 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
3377 /* Allow this function to make replacements in EXPR_LISTs. */
3384 && REGNO (x
) == REGNO (from
))
3386 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
3389 else if (GET_CODE (x
) == SUBREG
)
3391 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
3393 if (CONST_SCALAR_INT_P (new_rtx
))
3395 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
3396 GET_MODE (SUBREG_REG (x
)),
3401 SUBREG_REG (x
) = new_rtx
;
3405 else if (GET_CODE (x
) == ZERO_EXTEND
)
3407 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
3409 if (CONST_SCALAR_INT_P (new_rtx
))
3411 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3412 new_rtx
, GET_MODE (XEXP (x
, 0)));
3416 XEXP (x
, 0) = new_rtx
;
3421 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3422 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3425 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
3426 else if (fmt
[i
] == 'E')
3427 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3428 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
3429 from
, to
, all_regs
);
3435 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3436 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3439 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
3441 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3443 if (JUMP_TABLE_DATA_P (x
))
3446 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3447 int len
= GET_NUM_ELEM (vec
);
3448 for (int i
= 0; i
< len
; ++i
)
3450 rtx ref
= RTVEC_ELT (vec
, i
);
3451 if (XEXP (ref
, 0) == old_label
)
3453 XEXP (ref
, 0) = new_label
;
3454 if (update_label_nuses
)
3456 ++LABEL_NUSES (new_label
);
3457 --LABEL_NUSES (old_label
);
3464 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3465 field. This is not handled by the iterator because it doesn't
3466 handle unprinted ('0') fields. */
3467 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3468 JUMP_LABEL (x
) = new_label
;
3470 subrtx_ptr_iterator::array_type array
;
3471 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3476 if (GET_CODE (x
) == SYMBOL_REF
3477 && CONSTANT_POOL_ADDRESS_P (x
))
3479 rtx c
= get_pool_constant (x
);
3480 if (rtx_referenced_p (old_label
, c
))
3482 /* Create a copy of constant C; replace the label inside
3483 but do not update LABEL_NUSES because uses in constant pool
3485 rtx new_c
= copy_rtx (c
);
3486 replace_label (&new_c
, old_label
, new_label
, false);
3488 /* Add the new constant NEW_C to constant pool and replace
3489 the old reference to constant by new reference. */
3490 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3491 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3495 if ((GET_CODE (x
) == LABEL_REF
3496 || GET_CODE (x
) == INSN_LIST
)
3497 && XEXP (x
, 0) == old_label
)
3499 XEXP (x
, 0) = new_label
;
3500 if (update_label_nuses
)
3502 ++LABEL_NUSES (new_label
);
3503 --LABEL_NUSES (old_label
);
3511 replace_label_in_insn (rtx_insn
*insn
, rtx_insn
*old_label
,
3512 rtx_insn
*new_label
, bool update_label_nuses
)
3514 rtx insn_as_rtx
= insn
;
3515 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3516 gcc_checking_assert (insn_as_rtx
== insn
);
3519 /* Return true if X is referenced in BODY. */
3522 rtx_referenced_p (const_rtx x
, const_rtx body
)
3524 subrtx_iterator::array_type array
;
3525 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3526 if (const_rtx y
= *iter
)
3528 /* Check if a label_ref Y refers to label X. */
3529 if (GET_CODE (y
) == LABEL_REF
3531 && label_ref_label (y
) == x
)
3534 if (rtx_equal_p (x
, y
))
3537 /* If Y is a reference to pool constant traverse the constant. */
3538 if (GET_CODE (y
) == SYMBOL_REF
3539 && CONSTANT_POOL_ADDRESS_P (y
))
3540 iter
.substitute (get_pool_constant (y
));
3545 /* If INSN is a tablejump return true and store the label (before jump table) to
3546 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3549 tablejump_p (const rtx_insn
*insn
, rtx_insn
**labelp
,
3550 rtx_jump_table_data
**tablep
)
3555 rtx target
= JUMP_LABEL (insn
);
3556 if (target
== NULL_RTX
|| ANY_RETURN_P (target
))
3559 rtx_insn
*label
= as_a
<rtx_insn
*> (target
);
3560 rtx_insn
*table
= next_insn (label
);
3561 if (table
== NULL_RTX
|| !JUMP_TABLE_DATA_P (table
))
3567 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3571 /* For INSN known to satisfy tablejump_p, determine if it actually is a
3572 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3575 tablejump_casesi_pattern (const rtx_insn
*insn
)
3579 if ((tmp
= single_set (insn
)) != NULL
3580 && SET_DEST (tmp
) == pc_rtx
3581 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3582 && GET_CODE (XEXP (SET_SRC (tmp
), 2)) == LABEL_REF
)
3588 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3589 constant that is not in the constant pool and not in the condition
3590 of an IF_THEN_ELSE. */
3593 computed_jump_p_1 (const_rtx x
)
3595 const enum rtx_code code
= GET_CODE (x
);
3612 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3613 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3616 return (computed_jump_p_1 (XEXP (x
, 1))
3617 || computed_jump_p_1 (XEXP (x
, 2)));
3623 fmt
= GET_RTX_FORMAT (code
);
3624 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3627 && computed_jump_p_1 (XEXP (x
, i
)))
3630 else if (fmt
[i
] == 'E')
3631 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3632 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3639 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3641 Tablejumps and casesi insns are not considered indirect jumps;
3642 we can recognize them by a (use (label_ref)). */
3645 computed_jump_p (const rtx_insn
*insn
)
3650 rtx pat
= PATTERN (insn
);
3652 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3653 if (JUMP_LABEL (insn
) != NULL
)
3656 if (GET_CODE (pat
) == PARALLEL
)
3658 int len
= XVECLEN (pat
, 0);
3659 int has_use_labelref
= 0;
3661 for (i
= len
- 1; i
>= 0; i
--)
3662 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3663 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3666 has_use_labelref
= 1;
3670 if (! has_use_labelref
)
3671 for (i
= len
- 1; i
>= 0; i
--)
3672 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3673 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3674 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3677 else if (GET_CODE (pat
) == SET
3678 && SET_DEST (pat
) == pc_rtx
3679 && computed_jump_p_1 (SET_SRC (pat
)))
3687 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3688 the equivalent add insn and pass the result to FN, using DATA as the
3692 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3694 rtx x
= XEXP (mem
, 0);
3695 switch (GET_CODE (x
))
3700 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3701 rtx r1
= XEXP (x
, 0);
3702 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3703 return fn (mem
, x
, r1
, r1
, c
, data
);
3709 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
3710 rtx r1
= XEXP (x
, 0);
3711 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3712 return fn (mem
, x
, r1
, r1
, c
, data
);
3718 rtx r1
= XEXP (x
, 0);
3719 rtx add
= XEXP (x
, 1);
3720 return fn (mem
, x
, r1
, add
, NULL
, data
);
3728 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3729 For each such autoinc operation found, call FN, passing it
3730 the innermost enclosing MEM, the operation itself, the RTX modified
3731 by the operation, two RTXs (the second may be NULL) that, once
3732 added, represent the value to be held by the modified RTX
3733 afterwards, and DATA. FN is to return 0 to continue the
3734 traversal or any other value to have it returned to the caller of
3735 for_each_inc_dec. */
3738 for_each_inc_dec (rtx x
,
3739 for_each_inc_dec_fn fn
,
3742 subrtx_var_iterator::array_type array
;
3743 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3748 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3750 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3753 iter
.skip_subrtxes ();
3760 /* Searches X for any reference to REGNO, returning the rtx of the
3761 reference found if any. Otherwise, returns NULL_RTX. */
3764 regno_use_in (unsigned int regno
, rtx x
)
3770 if (REG_P (x
) && REGNO (x
) == regno
)
3773 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3774 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3778 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3781 else if (fmt
[i
] == 'E')
3782 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3783 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3790 /* Return a value indicating whether OP, an operand of a commutative
3791 operation, is preferred as the first or second operand. The more
3792 positive the value, the stronger the preference for being the first
3796 commutative_operand_precedence (rtx op
)
3798 enum rtx_code code
= GET_CODE (op
);
3800 /* Constants always become the second operand. Prefer "nice" constants. */
3801 if (code
== CONST_INT
)
3803 if (code
== CONST_WIDE_INT
)
3805 if (code
== CONST_POLY_INT
)
3807 if (code
== CONST_DOUBLE
)
3809 if (code
== CONST_FIXED
)
3811 op
= avoid_constant_pool_reference (op
);
3812 code
= GET_CODE (op
);
3814 switch (GET_RTX_CLASS (code
))
3817 if (code
== CONST_INT
)
3819 if (code
== CONST_WIDE_INT
)
3821 if (code
== CONST_POLY_INT
)
3823 if (code
== CONST_DOUBLE
)
3825 if (code
== CONST_FIXED
)
3830 /* SUBREGs of objects should come second. */
3831 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3836 /* Complex expressions should be the first, so decrease priority
3837 of objects. Prefer pointer objects over non pointer objects. */
3838 if ((REG_P (op
) && REG_POINTER (op
))
3839 || (MEM_P (op
) && MEM_POINTER (op
)))
3843 case RTX_COMM_ARITH
:
3844 /* Prefer operands that are themselves commutative to be first.
3845 This helps to make things linear. In particular,
3846 (and (and (reg) (reg)) (not (reg))) is canonical. */
3850 /* If only one operand is a binary expression, it will be the first
3851 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3852 is canonical, although it will usually be further simplified. */
3856 /* Then prefer NEG and NOT. */
3857 if (code
== NEG
|| code
== NOT
)
3866 /* Return 1 iff it is necessary to swap operands of commutative operation
3867 in order to canonicalize expression. */
3870 swap_commutative_operands_p (rtx x
, rtx y
)
3872 return (commutative_operand_precedence (x
)
3873 < commutative_operand_precedence (y
));
3876 /* Return 1 if X is an autoincrement side effect and the register is
3877 not the stack pointer. */
3879 auto_inc_p (const_rtx x
)
3881 switch (GET_CODE (x
))
3889 /* There are no REG_INC notes for SP. */
3890 if (XEXP (x
, 0) != stack_pointer_rtx
)
3898 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3900 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3909 code
= GET_CODE (in
);
3910 fmt
= GET_RTX_FORMAT (code
);
3911 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3915 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3918 else if (fmt
[i
] == 'E')
3919 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3920 if (loc
== &XVECEXP (in
, i
, j
)
3921 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3927 /* Reinterpret a subreg as a bit extraction from an integer and return
3928 the position of the least significant bit of the extracted value.
3929 In other words, if the extraction were performed as a shift right
3930 and mask, return the number of bits to shift right.
3932 The outer value of the subreg has OUTER_BYTES bytes and starts at
3933 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3936 subreg_size_lsb (poly_uint64 outer_bytes
,
3937 poly_uint64 inner_bytes
,
3938 poly_uint64 subreg_byte
)
3940 poly_uint64 subreg_end
, trailing_bytes
, byte_pos
;
3942 /* A paradoxical subreg begins at bit position 0. */
3943 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
3944 if (maybe_gt (outer_bytes
, inner_bytes
))
3946 gcc_checking_assert (known_eq (subreg_byte
, 0U));
3950 subreg_end
= subreg_byte
+ outer_bytes
;
3951 trailing_bytes
= inner_bytes
- subreg_end
;
3952 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
3953 byte_pos
= trailing_bytes
;
3954 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
3955 byte_pos
= subreg_byte
;
3958 /* When bytes and words have opposite endianness, we must be able
3959 to split offsets into words and bytes at compile time. */
3960 poly_uint64 leading_word_part
3961 = force_align_down (subreg_byte
, UNITS_PER_WORD
);
3962 poly_uint64 trailing_word_part
3963 = force_align_down (trailing_bytes
, UNITS_PER_WORD
);
3964 /* If the subreg crosses a word boundary ensure that
3965 it also begins and ends on a word boundary. */
3966 gcc_assert (known_le (subreg_end
- leading_word_part
,
3967 (unsigned int) UNITS_PER_WORD
)
3968 || (known_eq (leading_word_part
, subreg_byte
)
3969 && known_eq (trailing_word_part
, trailing_bytes
)));
3970 if (WORDS_BIG_ENDIAN
)
3971 byte_pos
= trailing_word_part
+ (subreg_byte
- leading_word_part
);
3973 byte_pos
= leading_word_part
+ (trailing_bytes
- trailing_word_part
);
3976 return byte_pos
* BITS_PER_UNIT
;
3979 /* Given a subreg X, return the bit offset where the subreg begins
3980 (counting from the least significant bit of the reg). */
3983 subreg_lsb (const_rtx x
)
3985 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3989 /* Return the subreg byte offset for a subreg whose outer value has
3990 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3991 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3992 lsb of the inner value. This is the inverse of the calculation
3993 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3996 subreg_size_offset_from_lsb (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
,
3997 poly_uint64 lsb_shift
)
3999 /* A paradoxical subreg begins at bit position 0. */
4000 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
4001 if (maybe_gt (outer_bytes
, inner_bytes
))
4003 gcc_checking_assert (known_eq (lsb_shift
, 0U));
4007 poly_uint64 lower_bytes
= exact_div (lsb_shift
, BITS_PER_UNIT
);
4008 poly_uint64 upper_bytes
= inner_bytes
- (lower_bytes
+ outer_bytes
);
4009 if (WORDS_BIG_ENDIAN
&& BYTES_BIG_ENDIAN
)
4011 else if (!WORDS_BIG_ENDIAN
&& !BYTES_BIG_ENDIAN
)
4015 /* When bytes and words have opposite endianness, we must be able
4016 to split offsets into words and bytes at compile time. */
4017 poly_uint64 lower_word_part
= force_align_down (lower_bytes
,
4019 poly_uint64 upper_word_part
= force_align_down (upper_bytes
,
4021 if (WORDS_BIG_ENDIAN
)
4022 return upper_word_part
+ (lower_bytes
- lower_word_part
);
4024 return lower_word_part
+ (upper_bytes
- upper_word_part
);
4028 /* Fill in information about a subreg of a hard register.
4029 xregno - A regno of an inner hard subreg_reg (or what will become one).
4030 xmode - The mode of xregno.
4031 offset - The byte offset.
4032 ymode - The mode of a top level SUBREG (or what may become one).
4033 info - Pointer to structure to fill in.
4035 Rather than considering one particular inner register (and thus one
4036 particular "outer" register) in isolation, this function really uses
4037 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
4038 function does not check whether adding INFO->offset to XREGNO gives
4039 a valid hard register; even if INFO->offset + XREGNO is out of range,
4040 there might be another register of the same type that is in range.
4041 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
4042 the new register, since that can depend on things like whether the final
4043 register number is even or odd. Callers that want to check whether
4044 this particular subreg can be replaced by a simple (reg ...) should
4045 use simplify_subreg_regno. */
4048 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
4049 poly_uint64 offset
, machine_mode ymode
,
4050 struct subreg_info
*info
)
4052 unsigned int nregs_xmode
, nregs_ymode
;
4054 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
4056 poly_uint64 xsize
= GET_MODE_SIZE (xmode
);
4057 poly_uint64 ysize
= GET_MODE_SIZE (ymode
);
4059 bool rknown
= false;
4061 /* If the register representation of a non-scalar mode has holes in it,
4062 we expect the scalar units to be concatenated together, with the holes
4063 distributed evenly among the scalar units. Each scalar unit must occupy
4064 at least one register. */
4065 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
4067 /* As a consequence, we must be dealing with a constant number of
4068 scalars, and thus a constant offset and number of units. */
4069 HOST_WIDE_INT coffset
= offset
.to_constant ();
4070 HOST_WIDE_INT cysize
= ysize
.to_constant ();
4071 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
4072 unsigned int nunits
= GET_MODE_NUNITS (xmode
).to_constant ();
4073 scalar_mode xmode_unit
= GET_MODE_INNER (xmode
);
4074 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
4075 gcc_assert (nregs_xmode
4077 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
4078 gcc_assert (hard_regno_nregs (xregno
, xmode
)
4079 == hard_regno_nregs (xregno
, xmode_unit
) * nunits
);
4081 /* You can only ask for a SUBREG of a value with holes in the middle
4082 if you don't cross the holes. (Such a SUBREG should be done by
4083 picking a different register class, or doing it in memory if
4084 necessary.) An example of a value with holes is XCmode on 32-bit
4085 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
4086 3 for each part, but in memory it's two 128-bit parts.
4087 Padding is assumed to be at the end (not necessarily the 'high part')
4089 if ((coffset
/ GET_MODE_SIZE (xmode_unit
) + 1 < nunits
)
4090 && (coffset
/ GET_MODE_SIZE (xmode_unit
)
4091 != ((coffset
+ cysize
- 1) / GET_MODE_SIZE (xmode_unit
))))
4093 info
->representable_p
= false;
4098 nregs_xmode
= hard_regno_nregs (xregno
, xmode
);
4100 nregs_ymode
= hard_regno_nregs (xregno
, ymode
);
4102 /* Subreg sizes must be ordered, so that we can tell whether they are
4103 partial, paradoxical or complete. */
4104 gcc_checking_assert (ordered_p (xsize
, ysize
));
4106 /* Paradoxical subregs are otherwise valid. */
4107 if (!rknown
&& known_eq (offset
, 0U) && maybe_gt (ysize
, xsize
))
4109 info
->representable_p
= true;
4110 /* If this is a big endian paradoxical subreg, which uses more
4111 actual hard registers than the original register, we must
4112 return a negative offset so that we find the proper highpart
4115 We assume that the ordering of registers within a multi-register
4116 value has a consistent endianness: if bytes and register words
4117 have different endianness, the hard registers that make up a
4118 multi-register value must be at least word-sized. */
4119 if (REG_WORDS_BIG_ENDIAN
)
4120 info
->offset
= (int) nregs_xmode
- (int) nregs_ymode
;
4123 info
->nregs
= nregs_ymode
;
4127 /* If registers store different numbers of bits in the different
4128 modes, we cannot generally form this subreg. */
4129 poly_uint64 regsize_xmode
, regsize_ymode
;
4130 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
4131 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
4132 && multiple_p (xsize
, nregs_xmode
, ®size_xmode
)
4133 && multiple_p (ysize
, nregs_ymode
, ®size_ymode
))
4136 && ((nregs_ymode
> 1 && maybe_gt (regsize_xmode
, regsize_ymode
))
4137 || (nregs_xmode
> 1 && maybe_gt (regsize_ymode
, regsize_xmode
))))
4139 info
->representable_p
= false;
4140 if (!can_div_away_from_zero_p (ysize
, regsize_xmode
, &info
->nregs
)
4141 || !can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
4142 /* Checked by validate_subreg. We must know at compile time
4143 which inner registers are being accessed. */
4147 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
4148 would go outside of XMODE. */
4149 if (!rknown
&& maybe_gt (ysize
+ offset
, xsize
))
4151 info
->representable_p
= false;
4152 info
->nregs
= nregs_ymode
;
4153 if (!can_div_trunc_p (offset
, regsize_xmode
, &info
->offset
))
4154 /* Checked by validate_subreg. We must know at compile time
4155 which inner registers are being accessed. */
4159 /* Quick exit for the simple and common case of extracting whole
4160 subregisters from a multiregister value. */
4161 /* ??? It would be better to integrate this into the code below,
4162 if we can generalize the concept enough and figure out how
4163 odd-sized modes can coexist with the other weird cases we support. */
4164 HOST_WIDE_INT count
;
4166 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
4167 && known_eq (regsize_xmode
, regsize_ymode
)
4168 && constant_multiple_p (offset
, regsize_ymode
, &count
))
4170 info
->representable_p
= true;
4171 info
->nregs
= nregs_ymode
;
4172 info
->offset
= count
;
4173 gcc_assert (info
->offset
+ info
->nregs
<= (int) nregs_xmode
);
4178 /* Lowpart subregs are otherwise valid. */
4179 if (!rknown
&& known_eq (offset
, subreg_lowpart_offset (ymode
, xmode
)))
4181 info
->representable_p
= true;
4184 if (known_eq (offset
, 0U) || nregs_xmode
== nregs_ymode
)
4187 info
->nregs
= nregs_ymode
;
4192 /* Set NUM_BLOCKS to the number of independently-representable YMODE
4193 values there are in (reg:XMODE XREGNO). We can view the register
4194 as consisting of this number of independent "blocks", where each
4195 block occupies NREGS_YMODE registers and contains exactly one
4196 representable YMODE value. */
4197 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
4198 unsigned int num_blocks
= nregs_xmode
/ nregs_ymode
;
4200 /* Calculate the number of bytes in each block. This must always
4201 be exact, otherwise we don't know how to verify the constraint.
4202 These conditions may be relaxed but subreg_regno_offset would
4203 need to be redesigned. */
4204 poly_uint64 bytes_per_block
= exact_div (xsize
, num_blocks
);
4206 /* Get the number of the first block that contains the subreg and the byte
4207 offset of the subreg from the start of that block. */
4208 unsigned int block_number
;
4209 poly_uint64 subblock_offset
;
4210 if (!can_div_trunc_p (offset
, bytes_per_block
, &block_number
,
4212 /* Checked by validate_subreg. We must know at compile time which
4213 inner registers are being accessed. */
4218 /* Only the lowpart of each block is representable. */
4219 info
->representable_p
4220 = known_eq (subblock_offset
,
4221 subreg_size_lowpart_offset (ysize
, bytes_per_block
));
4225 /* We assume that the ordering of registers within a multi-register
4226 value has a consistent endianness: if bytes and register words
4227 have different endianness, the hard registers that make up a
4228 multi-register value must be at least word-sized. */
4229 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
)
4230 /* The block number we calculated above followed memory endianness.
4231 Convert it to register endianness by counting back from the end.
4232 (Note that, because of the assumption above, each block must be
4233 at least word-sized.) */
4234 info
->offset
= (num_blocks
- block_number
- 1) * nregs_ymode
;
4236 info
->offset
= block_number
* nregs_ymode
;
4237 info
->nregs
= nregs_ymode
;
4240 /* This function returns the regno offset of a subreg expression.
4241 xregno - A regno of an inner hard subreg_reg (or what will become one).
4242 xmode - The mode of xregno.
4243 offset - The byte offset.
4244 ymode - The mode of a top level SUBREG (or what may become one).
4245 RETURN - The regno offset which would be used. */
4247 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
4248 poly_uint64 offset
, machine_mode ymode
)
4250 struct subreg_info info
;
4251 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
4255 /* This function returns true when the offset is representable via
4256 subreg_offset in the given regno.
4257 xregno - A regno of an inner hard subreg_reg (or what will become one).
4258 xmode - The mode of xregno.
4259 offset - The byte offset.
4260 ymode - The mode of a top level SUBREG (or what may become one).
4261 RETURN - Whether the offset is representable. */
4263 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
4264 poly_uint64 offset
, machine_mode ymode
)
4266 struct subreg_info info
;
4267 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
4268 return info
.representable_p
;
4271 /* Return the number of a YMODE register to which
4273 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
4275 can be simplified. Return -1 if the subreg can't be simplified.
4277 XREGNO is a hard register number. */
4280 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
4281 poly_uint64 offset
, machine_mode ymode
)
4283 struct subreg_info info
;
4284 unsigned int yregno
;
4286 /* Give the backend a chance to disallow the mode change. */
4287 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
4288 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
4289 && !REG_CAN_CHANGE_MODE_P (xregno
, xmode
, ymode
))
4292 /* We shouldn't simplify stack-related registers. */
4293 if ((!reload_completed
|| frame_pointer_needed
)
4294 && xregno
== FRAME_POINTER_REGNUM
)
4297 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
4298 && xregno
== ARG_POINTER_REGNUM
)
4301 if (xregno
== STACK_POINTER_REGNUM
4302 /* We should convert hard stack register in LRA if it is
4304 && ! lra_in_progress
)
4307 /* Try to get the register offset. */
4308 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
4309 if (!info
.representable_p
)
4312 /* Make sure that the offsetted register value is in range. */
4313 yregno
= xregno
+ info
.offset
;
4314 if (!HARD_REGISTER_NUM_P (yregno
))
4317 /* See whether (reg:YMODE YREGNO) is valid.
4319 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
4320 This is a kludge to work around how complex FP arguments are passed
4321 on IA-64 and should be fixed. See PR target/49226. */
4322 if (!targetm
.hard_regno_mode_ok (yregno
, ymode
)
4323 && targetm
.hard_regno_mode_ok (xregno
, xmode
))
4326 return (int) yregno
;
4329 /* A wrapper around simplify_subreg_regno that uses subreg_lowpart_offset
4330 (xmode, ymode) as the offset. */
4333 lowpart_subreg_regno (unsigned int regno
, machine_mode xmode
,
4336 poly_uint64 offset
= subreg_lowpart_offset (xmode
, ymode
);
4337 return simplify_subreg_regno (regno
, xmode
, offset
, ymode
);
4340 /* Return the final regno that a subreg expression refers to. */
4342 subreg_regno (const_rtx x
)
4345 rtx subreg
= SUBREG_REG (x
);
4346 int regno
= REGNO (subreg
);
4348 ret
= regno
+ subreg_regno_offset (regno
,
4356 /* Return the number of registers that a subreg expression refers
4359 subreg_nregs (const_rtx x
)
4361 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
4364 /* Return the number of registers that a subreg REG with REGNO
4365 expression refers to. This is a copy of the rtlanal.cc:subreg_nregs
4366 changed so that the regno can be passed in. */
4369 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
4371 struct subreg_info info
;
4372 rtx subreg
= SUBREG_REG (x
);
4374 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
4379 struct parms_set_data
4385 /* Helper function for noticing stores to parameter registers. */
4387 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
4389 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
4390 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
4391 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
4393 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
4398 /* Look backward for first parameter to be loaded.
4399 Note that loads of all parameters will not necessarily be
4400 found if CSE has eliminated some of them (e.g., an argument
4401 to the outer function is passed down as a parameter).
4402 Do not skip BOUNDARY. */
4404 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
4406 struct parms_set_data parm
;
4408 rtx_insn
*before
, *first_set
;
4410 /* Since different machines initialize their parameter registers
4411 in different orders, assume nothing. Collect the set of all
4412 parameter registers. */
4413 CLEAR_HARD_REG_SET (parm
.regs
);
4415 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
4416 if (GET_CODE (XEXP (p
, 0)) == USE
4417 && REG_P (XEXP (XEXP (p
, 0), 0))
4418 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p
, 0), 0)))
4420 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
4422 /* We only care about registers which can hold function
4424 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
4427 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
4431 first_set
= call_insn
;
4433 /* Search backward for the first set of a register in this set. */
4434 while (parm
.nregs
&& before
!= boundary
)
4436 before
= PREV_INSN (before
);
4438 /* It is possible that some loads got CSEed from one call to
4439 another. Stop in that case. */
4440 if (CALL_P (before
))
4443 /* Our caller needs either ensure that we will find all sets
4444 (in case code has not been optimized yet), or take care
4445 for possible labels in a way by setting boundary to preceding
4447 if (LABEL_P (before
))
4449 gcc_assert (before
== boundary
);
4453 if (INSN_P (before
))
4455 int nregs_old
= parm
.nregs
;
4456 note_stores (before
, parms_set
, &parm
);
4457 /* If we found something that did not set a parameter reg,
4458 we're done. Do not keep going, as that might result
4459 in hoisting an insn before the setting of a pseudo
4460 that is used by the hoisted insn. */
4461 if (nregs_old
!= parm
.nregs
)
4470 /* Return true if we should avoid inserting code between INSN and preceding
4471 call instruction. */
4474 keep_with_call_p (const rtx_insn
*insn
)
4478 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
4480 if (REG_P (SET_DEST (set
))
4481 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
4482 && fixed_regs
[REGNO (SET_DEST (set
))]
4483 && general_operand (SET_SRC (set
), VOIDmode
))
4485 if (REG_P (SET_SRC (set
))
4486 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
4487 && REG_P (SET_DEST (set
))
4488 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
4490 /* There may be a stack pop just after the call and before the store
4491 of the return register. Search for the actual store when deciding
4492 if we can break or not. */
4493 if (SET_DEST (set
) == stack_pointer_rtx
)
4495 /* This CONST_CAST is okay because next_nonnote_insn just
4496 returns its argument and we assign it to a const_rtx
4499 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
4500 if (i2
&& keep_with_call_p (i2
))
4507 /* Return true if LABEL is a target of JUMP_INSN. This applies only
4508 to non-complex jumps. That is, direct unconditional, conditional,
4509 and tablejumps, but not computed jumps or returns. It also does
4510 not apply to the fallthru case of a conditional jump. */
4513 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
4515 rtx tmp
= JUMP_LABEL (jump_insn
);
4516 rtx_jump_table_data
*table
;
4521 if (tablejump_p (jump_insn
, NULL
, &table
))
4523 rtvec vec
= table
->get_labels ();
4524 int i
, veclen
= GET_NUM_ELEM (vec
);
4526 for (i
= 0; i
< veclen
; ++i
)
4527 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4531 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4538 /* Return an estimate of the cost of computing rtx X.
4539 One use is in cse, to decide which expression to keep in the hash table.
4540 Another is in rtl generation, to pick the cheapest way to multiply.
4541 Other uses like the latter are expected in the future.
4543 X appears as operand OPNO in an expression with code OUTER_CODE.
4544 SPEED specifies whether costs optimized for speed or size should
4548 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4549 int opno
, bool speed
)
4561 if (GET_CODE (x
) == SET
)
4562 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4563 the mode for the factor. */
4564 mode
= GET_MODE (SET_DEST (x
));
4565 else if (GET_MODE (x
) != VOIDmode
)
4566 mode
= GET_MODE (x
);
4568 mode_size
= estimated_poly_value (GET_MODE_SIZE (mode
));
4570 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4571 many insns, taking N times as long. */
4572 factor
= mode_size
> UNITS_PER_WORD
? mode_size
/ UNITS_PER_WORD
: 1;
4574 /* Compute the default costs of certain things.
4575 Note that targetm.rtx_costs can override the defaults. */
4577 code
= GET_CODE (x
);
4581 /* Multiplication has time-complexity O(N*N), where N is the
4582 number of units (translated from digits) when using
4583 schoolbook long multiplication. */
4584 total
= factor
* factor
* COSTS_N_INSNS (5);
4590 /* Similarly, complexity for schoolbook long division. */
4591 total
= factor
* factor
* COSTS_N_INSNS (7);
4594 /* Used in combine.cc as a marker. */
4598 total
= factor
* COSTS_N_INSNS (1);
4608 /* If we can't tie these modes, make this expensive. The larger
4609 the mode, the more expensive it is. */
4610 if (!targetm
.modes_tieable_p (mode
, GET_MODE (SUBREG_REG (x
))))
4611 return COSTS_N_INSNS (2 + factor
);
4615 if (targetm
.modes_tieable_p (mode
, GET_MODE (XEXP (x
, 0))))
4622 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4627 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4628 which is already in total. */
4630 fmt
= GET_RTX_FORMAT (code
);
4631 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4633 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4634 else if (fmt
[i
] == 'E')
4635 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4636 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4641 /* Fill in the structure C with information about both speed and size rtx
4642 costs for X, which is operand OPNO in an expression with code OUTER. */
4645 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4646 struct full_rtx_costs
*c
)
4648 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4649 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4653 /* Return cost of address expression X.
4654 Expect that X is properly formed address reference.
4656 SPEED parameter specify whether costs optimized for speed or size should
4660 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4662 /* We may be asked for cost of various unusual addresses, such as operands
4663 of push instruction. It is not worthwhile to complicate writing
4664 of the target hook by such cases. */
4666 if (!memory_address_addr_space_p (mode
, x
, as
))
4669 return targetm
.address_cost (x
, mode
, as
, speed
);
4672 /* If the target doesn't override, compute the cost as with arithmetic. */
4675 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4677 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4681 unsigned HOST_WIDE_INT
4682 nonzero_bits (const_rtx x
, machine_mode mode
)
4684 if (mode
== VOIDmode
)
4685 mode
= GET_MODE (x
);
4686 scalar_int_mode int_mode
;
4687 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4688 return GET_MODE_MASK (mode
);
4689 return cached_nonzero_bits (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4693 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4695 if (mode
== VOIDmode
)
4696 mode
= GET_MODE (x
);
4697 scalar_int_mode int_mode
;
4698 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
4700 return cached_num_sign_bit_copies (x
, int_mode
, NULL_RTX
, VOIDmode
, 0);
4703 /* Return true if nonzero_bits1 might recurse into both operands
4707 nonzero_bits_binary_arith_p (const_rtx x
)
4709 if (!ARITHMETIC_P (x
))
4711 switch (GET_CODE (x
))
4733 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4734 It avoids exponential behavior in nonzero_bits1 when X has
4735 identical subexpressions on the first or the second level. */
4737 static unsigned HOST_WIDE_INT
4738 cached_nonzero_bits (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4739 machine_mode known_mode
,
4740 unsigned HOST_WIDE_INT known_ret
)
4742 if (x
== known_x
&& mode
== known_mode
)
4745 /* Try to find identical subexpressions. If found call
4746 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4747 precomputed value for the subexpression as KNOWN_RET. */
4749 if (nonzero_bits_binary_arith_p (x
))
4751 rtx x0
= XEXP (x
, 0);
4752 rtx x1
= XEXP (x
, 1);
4754 /* Check the first level. */
4756 return nonzero_bits1 (x
, mode
, x0
, mode
,
4757 cached_nonzero_bits (x0
, mode
, known_x
,
4758 known_mode
, known_ret
));
4760 /* Check the second level. */
4761 if (nonzero_bits_binary_arith_p (x0
)
4762 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4763 return nonzero_bits1 (x
, mode
, x1
, mode
,
4764 cached_nonzero_bits (x1
, mode
, known_x
,
4765 known_mode
, known_ret
));
4767 if (nonzero_bits_binary_arith_p (x1
)
4768 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4769 return nonzero_bits1 (x
, mode
, x0
, mode
,
4770 cached_nonzero_bits (x0
, mode
, known_x
,
4771 known_mode
, known_ret
));
4774 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4777 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4778 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4779 is less useful. We can't allow both, because that results in exponential
4780 run time recursion. There is a nullstone testcase that triggered
4781 this. This macro avoids accidental uses of num_sign_bit_copies. */
4782 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4784 /* Given an expression, X, compute which bits in X can be nonzero.
4785 We don't care about bits outside of those defined in MODE.
4787 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4788 an arithmetic operation, we can do better. */
4790 static unsigned HOST_WIDE_INT
4791 nonzero_bits1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
4792 machine_mode known_mode
,
4793 unsigned HOST_WIDE_INT known_ret
)
4795 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4796 unsigned HOST_WIDE_INT inner_nz
;
4797 enum rtx_code code
= GET_CODE (x
);
4798 machine_mode inner_mode
;
4799 unsigned int inner_width
;
4800 scalar_int_mode xmode
;
4802 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4804 if (CONST_INT_P (x
))
4806 if (SHORT_IMMEDIATES_SIGN_EXTEND
4808 && mode_width
< BITS_PER_WORD
4809 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1))) != 0)
4810 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4815 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
4817 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
4819 /* If X is wider than MODE, use its mode instead. */
4820 if (xmode_width
> mode_width
)
4823 nonzero
= GET_MODE_MASK (mode
);
4824 mode_width
= xmode_width
;
4827 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4828 /* Our only callers in this case look for single bit values. So
4829 just return the mode mask. Those tests will then be false. */
4832 /* If MODE is wider than X, but both are a single word for both the host
4833 and target machines, we can compute this from which bits of the object
4834 might be nonzero in its own mode, taking into account the fact that, on
4835 CISC machines, accessing an object in a wider mode generally causes the
4836 high-order bits to become undefined, so they are not known to be zero.
4837 We extend this reasoning to RISC machines for operations that might not
4838 operate on the full registers. */
4839 if (mode_width
> xmode_width
4840 && xmode_width
<= BITS_PER_WORD
4841 && xmode_width
<= HOST_BITS_PER_WIDE_INT
4842 && !(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
4844 nonzero
&= cached_nonzero_bits (x
, xmode
,
4845 known_x
, known_mode
, known_ret
);
4846 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
);
4850 /* Please keep nonzero_bits_binary_arith_p above in sync with
4851 the code in the switch below. */
4855 #if defined(POINTERS_EXTEND_UNSIGNED)
4856 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4857 all the bits above ptr_mode are known to be zero. */
4858 /* As we do not know which address space the pointer is referring to,
4859 we can do this only if the target does not support different pointer
4860 or address modes depending on the address space. */
4861 if (target_default_pointer_address_modes_p ()
4862 && POINTERS_EXTEND_UNSIGNED
4865 && !targetm
.have_ptr_extend ())
4866 nonzero
&= GET_MODE_MASK (ptr_mode
);
4869 /* Include declared information about alignment of pointers. */
4870 /* ??? We don't properly preserve REG_POINTER changes across
4871 pointer-to-integer casts, so we can't trust it except for
4872 things that we know must be pointers. See execute/960116-1.c. */
4873 if ((x
== stack_pointer_rtx
4874 || x
== frame_pointer_rtx
4875 || x
== arg_pointer_rtx
)
4876 && REGNO_POINTER_ALIGN (REGNO (x
)))
4878 unsigned HOST_WIDE_INT alignment
4879 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4881 #ifdef PUSH_ROUNDING
4882 /* If PUSH_ROUNDING is defined, it is possible for the
4883 stack to be momentarily aligned only to that amount,
4884 so we pick the least alignment. */
4885 if (x
== stack_pointer_rtx
&& targetm
.calls
.push_argument (0))
4887 poly_uint64 rounded_1
= PUSH_ROUNDING (poly_int64 (1));
4888 alignment
= MIN (known_alignment (rounded_1
), alignment
);
4892 nonzero
&= ~(alignment
- 1);
4896 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4897 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, xmode
, mode
,
4901 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4902 known_mode
, known_ret
);
4904 return nonzero_for_hook
;
4908 /* In many, if not most, RISC machines, reading a byte from memory
4909 zeros the rest of the register. Noticing that fact saves a lot
4910 of extra zero-extends. */
4911 if (load_extend_op (xmode
) == ZERO_EXTEND
)
4912 nonzero
&= GET_MODE_MASK (xmode
);
4916 case UNEQ
: case LTGT
:
4917 case GT
: case GTU
: case UNGT
:
4918 case LT
: case LTU
: case UNLT
:
4919 case GE
: case GEU
: case UNGE
:
4920 case LE
: case LEU
: case UNLE
:
4921 case UNORDERED
: case ORDERED
:
4922 /* If this produces an integer result, we know which bits are set.
4923 Code here used to clear bits outside the mode of X, but that is
4925 /* Mind that MODE is the mode the caller wants to look at this
4926 operation in, and not the actual operation mode. We can wind
4927 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4928 that describes the results of a vector compare. */
4929 if (GET_MODE_CLASS (xmode
) == MODE_INT
4930 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4931 nonzero
= STORE_FLAG_VALUE
;
4936 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4937 and num_sign_bit_copies. */
4938 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4942 if (xmode_width
< mode_width
)
4943 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (xmode
));
4948 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4949 and num_sign_bit_copies. */
4950 if (num_sign_bit_copies (XEXP (x
, 0), xmode
) == xmode_width
)
4956 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4957 known_x
, known_mode
, known_ret
)
4958 & GET_MODE_MASK (mode
));
4962 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4963 known_x
, known_mode
, known_ret
);
4964 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4965 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4969 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4970 Otherwise, show all the bits in the outer mode but not the inner
4972 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4973 known_x
, known_mode
, known_ret
);
4974 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4976 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4977 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4978 inner_nz
|= (GET_MODE_MASK (mode
)
4979 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4982 nonzero
&= inner_nz
;
4986 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4987 known_x
, known_mode
, known_ret
)
4988 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4989 known_x
, known_mode
, known_ret
);
4993 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4995 unsigned HOST_WIDE_INT nonzero0
4996 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4997 known_x
, known_mode
, known_ret
);
4999 /* Don't call nonzero_bits for the second time if it cannot change
5001 if ((nonzero
& nonzero0
) != nonzero
)
5003 | cached_nonzero_bits (XEXP (x
, 1), mode
,
5004 known_x
, known_mode
, known_ret
);
5008 case PLUS
: case MINUS
:
5010 case DIV
: case UDIV
:
5011 case MOD
: case UMOD
:
5012 /* We can apply the rules of arithmetic to compute the number of
5013 high- and low-order zero bits of these operations. We start by
5014 computing the width (position of the highest-order nonzero bit)
5015 and the number of low-order zero bits for each value. */
5017 unsigned HOST_WIDE_INT nz0
5018 = cached_nonzero_bits (XEXP (x
, 0), mode
,
5019 known_x
, known_mode
, known_ret
);
5020 unsigned HOST_WIDE_INT nz1
5021 = cached_nonzero_bits (XEXP (x
, 1), mode
,
5022 known_x
, known_mode
, known_ret
);
5023 int sign_index
= xmode_width
- 1;
5024 int width0
= floor_log2 (nz0
) + 1;
5025 int width1
= floor_log2 (nz1
) + 1;
5026 int low0
= ctz_or_zero (nz0
);
5027 int low1
= ctz_or_zero (nz1
);
5028 unsigned HOST_WIDE_INT op0_maybe_minusp
5029 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
5030 unsigned HOST_WIDE_INT op1_maybe_minusp
5031 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
5032 unsigned int result_width
= mode_width
;
5038 result_width
= MAX (width0
, width1
) + 1;
5039 result_low
= MIN (low0
, low1
);
5042 result_low
= MIN (low0
, low1
);
5045 result_width
= width0
+ width1
;
5046 result_low
= low0
+ low1
;
5051 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
5052 result_width
= width0
;
5057 result_width
= width0
;
5062 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
5063 result_width
= MIN (width0
, width1
);
5064 result_low
= MIN (low0
, low1
);
5069 result_width
= MIN (width0
, width1
);
5070 result_low
= MIN (low0
, low1
);
5076 /* Note that mode_width <= HOST_BITS_PER_WIDE_INT, see above. */
5077 if (result_width
< mode_width
)
5078 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
5082 if (result_low
< HOST_BITS_PER_WIDE_INT
)
5083 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
5091 if (CONST_INT_P (XEXP (x
, 1))
5092 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
5093 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
5097 /* If this is a SUBREG formed for a promoted variable that has
5098 been zero-extended, we know that at least the high-order bits
5099 are zero, though others might be too. */
5100 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
5101 nonzero
= GET_MODE_MASK (xmode
)
5102 & cached_nonzero_bits (SUBREG_REG (x
), xmode
,
5103 known_x
, known_mode
, known_ret
);
5105 /* If the inner mode is a single word for both the host and target
5106 machines, we can compute this from which bits of the inner
5107 object might be nonzero. */
5108 inner_mode
= GET_MODE (SUBREG_REG (x
));
5109 if (GET_MODE_PRECISION (inner_mode
).is_constant (&inner_width
)
5110 && inner_width
<= BITS_PER_WORD
5111 && inner_width
<= HOST_BITS_PER_WIDE_INT
)
5113 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
5114 known_x
, known_mode
, known_ret
);
5116 /* On a typical CISC machine, accessing an object in a wider mode
5117 causes the high-order bits to become undefined. So they are
5118 not known to be zero.
5120 On a typical RISC machine, we only have to worry about the way
5121 loads are extended. Otherwise, if we get a reload for the inner
5122 part, it may be loaded from the stack, and then we may lose all
5123 the zero bits that existed before the store to the stack. */
5125 if ((!WORD_REGISTER_OPERATIONS
5126 || ((extend_op
= load_extend_op (inner_mode
)) == SIGN_EXTEND
5127 ? val_signbit_known_set_p (inner_mode
, nonzero
)
5128 : extend_op
!= ZERO_EXTEND
)
5129 || !MEM_P (SUBREG_REG (x
)))
5130 && xmode_width
> inner_width
)
5132 |= (GET_MODE_MASK (GET_MODE (x
)) & ~GET_MODE_MASK (inner_mode
));
5141 /* The nonzero bits are in two classes: any bits within MODE
5142 that aren't in xmode are always significant. The rest of the
5143 nonzero bits are those that are significant in the operand of
5144 the shift when shifted the appropriate number of bits. This
5145 shows that high-order bits are cleared by the right shift and
5146 low-order bits by left shifts. */
5147 if (CONST_INT_P (XEXP (x
, 1))
5148 && INTVAL (XEXP (x
, 1)) >= 0
5149 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
5150 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5152 int count
= INTVAL (XEXP (x
, 1));
5153 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (xmode
);
5154 unsigned HOST_WIDE_INT op_nonzero
5155 = cached_nonzero_bits (XEXP (x
, 0), mode
,
5156 known_x
, known_mode
, known_ret
);
5157 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
5158 unsigned HOST_WIDE_INT outer
= 0;
5160 if (mode_width
> xmode_width
)
5161 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
5176 /* If the sign bit may have been nonzero before the shift, we
5177 need to mark all the places it could have been copied to
5178 by the shift as possibly nonzero. */
5179 if (inner
& (HOST_WIDE_INT_1U
<< (xmode_width
- 1 - count
)))
5180 inner
|= (((HOST_WIDE_INT_1U
<< count
) - 1)
5181 << (xmode_width
- count
));
5185 inner
= (inner
<< (count
% xmode_width
)
5186 | (inner
>> (xmode_width
- (count
% xmode_width
))))
5191 inner
= (inner
>> (count
% xmode_width
)
5192 | (inner
<< (xmode_width
- (count
% xmode_width
))))
5200 nonzero
&= (outer
| inner
);
5206 /* This is at most the number of bits in the mode. */
5207 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
5211 /* If CLZ has a known value at zero, then the nonzero bits are
5212 that value, plus the number of bits in the mode minus one. */
5213 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
5215 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
5221 /* If CTZ has a known value at zero, then the nonzero bits are
5222 that value, plus the number of bits in the mode minus one. */
5223 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
5225 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
5231 /* This is at most the number of bits in the mode minus 1. */
5232 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
5241 unsigned HOST_WIDE_INT nonzero_true
5242 = cached_nonzero_bits (XEXP (x
, 1), mode
,
5243 known_x
, known_mode
, known_ret
);
5245 /* Don't call nonzero_bits for the second time if it cannot change
5247 if ((nonzero
& nonzero_true
) != nonzero
)
5248 nonzero
&= nonzero_true
5249 | cached_nonzero_bits (XEXP (x
, 2), mode
,
5250 known_x
, known_mode
, known_ret
);
5261 /* See the macro definition above. */
5262 #undef cached_num_sign_bit_copies
5265 /* Return true if num_sign_bit_copies1 might recurse into both operands
5269 num_sign_bit_copies_binary_arith_p (const_rtx x
)
5271 if (!ARITHMETIC_P (x
))
5273 switch (GET_CODE (x
))
5291 /* The function cached_num_sign_bit_copies is a wrapper around
5292 num_sign_bit_copies1. It avoids exponential behavior in
5293 num_sign_bit_copies1 when X has identical subexpressions on the
5294 first or the second level. */
5297 cached_num_sign_bit_copies (const_rtx x
, scalar_int_mode mode
,
5298 const_rtx known_x
, machine_mode known_mode
,
5299 unsigned int known_ret
)
5301 if (x
== known_x
&& mode
== known_mode
)
5304 /* Try to find identical subexpressions. If found call
5305 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
5306 the precomputed value for the subexpression as KNOWN_RET. */
5308 if (num_sign_bit_copies_binary_arith_p (x
))
5310 rtx x0
= XEXP (x
, 0);
5311 rtx x1
= XEXP (x
, 1);
5313 /* Check the first level. */
5316 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5317 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5321 /* Check the second level. */
5322 if (num_sign_bit_copies_binary_arith_p (x0
)
5323 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
5325 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
5326 cached_num_sign_bit_copies (x1
, mode
, known_x
,
5330 if (num_sign_bit_copies_binary_arith_p (x1
)
5331 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
5333 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
5334 cached_num_sign_bit_copies (x0
, mode
, known_x
,
5339 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
5342 /* Return the number of bits at the high-order end of X that are known to
5343 be equal to the sign bit. X will be used in mode MODE. The returned
5344 value will always be between 1 and the number of bits in MODE. */
5347 num_sign_bit_copies1 (const_rtx x
, scalar_int_mode mode
, const_rtx known_x
,
5348 machine_mode known_mode
,
5349 unsigned int known_ret
)
5351 enum rtx_code code
= GET_CODE (x
);
5352 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
5353 int num0
, num1
, result
;
5354 unsigned HOST_WIDE_INT nonzero
;
5356 if (CONST_INT_P (x
))
5358 /* If the constant is negative, take its 1's complement and remask.
5359 Then see how many zero bits we have. */
5360 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
5361 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5362 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5363 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5365 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5368 scalar_int_mode xmode
, inner_mode
;
5369 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
5372 unsigned int xmode_width
= GET_MODE_PRECISION (xmode
);
5374 /* For a smaller mode, just ignore the high bits. */
5375 if (bitwidth
< xmode_width
)
5377 num0
= cached_num_sign_bit_copies (x
, xmode
,
5378 known_x
, known_mode
, known_ret
);
5379 return MAX (1, num0
- (int) (xmode_width
- bitwidth
));
5382 if (bitwidth
> xmode_width
)
5384 /* If this machine does not do all register operations on the entire
5385 register and MODE is wider than the mode of X, we can say nothing
5386 at all about the high-order bits. We extend this reasoning to RISC
5387 machines for operations that might not operate on full registers. */
5388 if (!(WORD_REGISTER_OPERATIONS
&& word_register_operation_p (x
)))
5391 /* Likewise on machines that do, if the mode of the object is smaller
5392 than a word and loads of that size don't sign extend, we can say
5393 nothing about the high order bits. */
5394 if (xmode_width
< BITS_PER_WORD
5395 && load_extend_op (xmode
) != SIGN_EXTEND
)
5399 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5400 the code in the switch below. */
5405 #if defined(POINTERS_EXTEND_UNSIGNED)
5406 /* If pointers extend signed and this is a pointer in Pmode, say that
5407 all the bits above ptr_mode are known to be sign bit copies. */
5408 /* As we do not know which address space the pointer is referring to,
5409 we can do this only if the target does not support different pointer
5410 or address modes depending on the address space. */
5411 if (target_default_pointer_address_modes_p ()
5412 && ! POINTERS_EXTEND_UNSIGNED
&& xmode
== Pmode
5413 && mode
== Pmode
&& REG_POINTER (x
)
5414 && !targetm
.have_ptr_extend ())
5415 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
5419 unsigned int copies_for_hook
= 1, copies
= 1;
5420 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, xmode
, mode
,
5424 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
5425 known_mode
, known_ret
);
5427 if (copies
> 1 || copies_for_hook
> 1)
5428 return MAX (copies
, copies_for_hook
);
5430 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5435 /* Some RISC machines sign-extend all loads of smaller than a word. */
5436 if (load_extend_op (xmode
) == SIGN_EXTEND
)
5437 return MAX (1, ((int) bitwidth
- (int) xmode_width
+ 1));
5441 /* If this is a SUBREG for a promoted object that is sign-extended
5442 and we are looking at it in a wider mode, we know that at least the
5443 high-order bits are known to be sign bit copies. */
5445 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
5447 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5448 known_x
, known_mode
, known_ret
);
5449 return MAX ((int) bitwidth
- (int) xmode_width
+ 1, num0
);
5452 if (is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (x
)), &inner_mode
))
5454 /* For a smaller object, just ignore the high bits. */
5455 if (bitwidth
<= GET_MODE_PRECISION (inner_mode
))
5457 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), inner_mode
,
5458 known_x
, known_mode
,
5460 return MAX (1, num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5464 /* For paradoxical SUBREGs on machines where all register operations
5465 affect the entire register, just look inside. Note that we are
5466 passing MODE to the recursive call, so the number of sign bit
5467 copies will remain relative to that mode, not the inner mode.
5469 This works only if loads sign extend. Otherwise, if we get a
5470 reload for the inner part, it may be loaded from the stack, and
5471 then we lose all sign bit copies that existed before the store
5473 if (WORD_REGISTER_OPERATIONS
5474 && load_extend_op (inner_mode
) == SIGN_EXTEND
5475 && paradoxical_subreg_p (x
)
5476 && MEM_P (SUBREG_REG (x
)))
5477 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
5478 known_x
, known_mode
, known_ret
);
5483 if (CONST_INT_P (XEXP (x
, 1)))
5484 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
5488 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
5489 return (bitwidth
- GET_MODE_PRECISION (inner_mode
)
5490 + cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5491 known_x
, known_mode
, known_ret
));
5495 /* For a smaller object, just ignore the high bits. */
5496 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
5497 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), inner_mode
,
5498 known_x
, known_mode
, known_ret
);
5499 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (inner_mode
)
5503 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5504 known_x
, known_mode
, known_ret
);
5506 case ROTATE
: case ROTATERT
:
5507 /* If we are rotating left by a number of bits less than the number
5508 of sign bit copies, we can just subtract that amount from the
5510 if (CONST_INT_P (XEXP (x
, 1))
5511 && INTVAL (XEXP (x
, 1)) >= 0
5512 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
5514 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5515 known_x
, known_mode
, known_ret
);
5516 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
5517 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
5522 /* In general, this subtracts one sign bit copy. But if the value
5523 is known to be positive, the number of sign bit copies is the
5524 same as that of the input. Finally, if the input has just one bit
5525 that might be nonzero, all the bits are copies of the sign bit. */
5526 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5527 known_x
, known_mode
, known_ret
);
5528 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5529 return num0
> 1 ? num0
- 1 : 1;
5531 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5536 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
5541 case IOR
: case AND
: case XOR
:
5542 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5543 /* Logical operations will preserve the number of sign-bit copies.
5544 MIN and MAX operations always return one of the operands. */
5545 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5546 known_x
, known_mode
, known_ret
);
5547 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5548 known_x
, known_mode
, known_ret
);
5550 /* If num1 is clearing some of the top bits then regardless of
5551 the other term, we are guaranteed to have at least that many
5552 high-order zero bits. */
5555 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5556 && CONST_INT_P (XEXP (x
, 1))
5557 && (UINTVAL (XEXP (x
, 1))
5558 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5561 /* Similarly for IOR when setting high-order bits. */
5564 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5565 && CONST_INT_P (XEXP (x
, 1))
5566 && (UINTVAL (XEXP (x
, 1))
5567 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5570 return MIN (num0
, num1
);
5572 case PLUS
: case MINUS
:
5573 /* For addition and subtraction, we can have a 1-bit carry. However,
5574 if we are subtracting 1 from a positive number, there will not
5575 be such a carry. Furthermore, if the positive number is known to
5576 be 0 or 1, we know the result is either -1 or 0. */
5578 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5579 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5581 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5582 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5583 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5584 : bitwidth
- floor_log2 (nonzero
) - 1);
5587 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5588 known_x
, known_mode
, known_ret
);
5589 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5590 known_x
, known_mode
, known_ret
);
5591 result
= MAX (1, MIN (num0
, num1
) - 1);
5596 /* The number of bits of the product is the sum of the number of
5597 bits of both terms. However, unless one of the terms if known
5598 to be positive, we must allow for an additional bit since negating
5599 a negative number can remove one sign bit copy. */
5601 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5602 known_x
, known_mode
, known_ret
);
5603 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5604 known_x
, known_mode
, known_ret
);
5606 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5608 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5609 || (((nonzero_bits (XEXP (x
, 0), mode
)
5610 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5611 && ((nonzero_bits (XEXP (x
, 1), mode
)
5612 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5616 return MAX (1, result
);
5619 /* The result must be <= the first operand. If the first operand
5620 has the high bit set, we know nothing about the number of sign
5622 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5624 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5625 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5628 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5629 known_x
, known_mode
, known_ret
);
5632 /* The result must be <= the second operand. If the second operand
5633 has (or just might have) the high bit set, we know nothing about
5634 the number of sign bit copies. */
5635 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5637 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5638 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5641 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5642 known_x
, known_mode
, known_ret
);
5645 /* Similar to unsigned division, except that we have to worry about
5646 the case where the divisor is negative, in which case we have
5648 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5649 known_x
, known_mode
, known_ret
);
5651 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5652 || (nonzero_bits (XEXP (x
, 1), mode
)
5653 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5659 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5660 known_x
, known_mode
, known_ret
);
5662 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5663 || (nonzero_bits (XEXP (x
, 1), mode
)
5664 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5670 /* Shifts by a constant add to the number of bits equal to the
5672 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5673 known_x
, known_mode
, known_ret
);
5674 if (CONST_INT_P (XEXP (x
, 1))
5675 && INTVAL (XEXP (x
, 1)) > 0
5676 && INTVAL (XEXP (x
, 1)) < xmode_width
)
5677 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5682 /* Left shifts destroy copies. */
5683 if (!CONST_INT_P (XEXP (x
, 1))
5684 || INTVAL (XEXP (x
, 1)) < 0
5685 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5686 || INTVAL (XEXP (x
, 1)) >= xmode_width
)
5689 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5690 known_x
, known_mode
, known_ret
);
5691 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5694 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5695 known_x
, known_mode
, known_ret
);
5696 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5697 known_x
, known_mode
, known_ret
);
5698 return MIN (num0
, num1
);
5700 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5701 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5702 case GEU
: case GTU
: case LEU
: case LTU
:
5703 case UNORDERED
: case ORDERED
:
5704 /* If the constant is negative, take its 1's complement and remask.
5705 Then see how many zero bits we have. */
5706 nonzero
= STORE_FLAG_VALUE
;
5707 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5708 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5709 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5711 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5717 /* If we haven't been able to figure it out by one of the above rules,
5718 see if some of the high-order bits are known to be zero. If so,
5719 count those bits and return one less than that amount. If we can't
5720 safely compute the mask for this mode, always return BITWIDTH. */
5722 bitwidth
= GET_MODE_PRECISION (mode
);
5723 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5726 nonzero
= nonzero_bits (x
, mode
);
5727 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5728 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5731 /* Calculate the rtx_cost of a single instruction pattern. A return value of
5732 zero indicates an instruction pattern without a known cost. */
5735 pattern_cost (rtx pat
, bool speed
)
5740 /* Extract the single set rtx from the instruction pattern. We
5741 can't use single_set since we only have the pattern. We also
5742 consider PARALLELs of a normal set and a single comparison. In
5743 that case we use the cost of the non-comparison SET operation,
5744 which is most-likely to be the real cost of this operation. */
5745 if (GET_CODE (pat
) == SET
)
5747 else if (GET_CODE (pat
) == PARALLEL
)
5750 rtx comparison
= NULL_RTX
;
5752 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5754 rtx x
= XVECEXP (pat
, 0, i
);
5755 if (GET_CODE (x
) == SET
)
5757 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
5772 if (!set
&& comparison
)
5781 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5782 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5785 /* Calculate the cost of a single instruction. A return value of zero
5786 indicates an instruction pattern without a known cost. */
5789 insn_cost (rtx_insn
*insn
, bool speed
)
5791 if (targetm
.insn_cost
)
5792 return targetm
.insn_cost (insn
, speed
);
5794 return pattern_cost (PATTERN (insn
), speed
);
5797 /* Returns estimate on cost of computing SEQ. */
5800 seq_cost (const rtx_insn
*seq
, bool speed
)
5805 for (; seq
; seq
= NEXT_INSN (seq
))
5807 set
= single_set (seq
);
5809 cost
+= set_rtx_cost (set
, speed
);
5810 else if (NONDEBUG_INSN_P (seq
))
5812 int this_cost
= insn_cost (CONST_CAST_RTX_INSN (seq
), speed
);
5823 /* Given an insn INSN and condition COND, return the condition in a
5824 canonical form to simplify testing by callers. Specifically:
5826 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5827 (2) Both operands will be machine operands.
5828 (3) If an operand is a constant, it will be the second operand.
5829 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5830 for GE, GEU, and LEU.
5832 If the condition cannot be understood, or is an inequality floating-point
5833 comparison which needs to be reversed, 0 will be returned.
5835 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5837 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5838 insn used in locating the condition was found. If a replacement test
5839 of the condition is desired, it should be placed in front of that
5840 insn and we will be sure that the inputs are still valid.
5842 If WANT_REG is nonzero, we wish the condition to be relative to that
5843 register, if possible. Therefore, do not canonicalize the condition
5844 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5845 to be a compare to a CC mode register.
5847 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5851 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5852 rtx_insn
**earliest
,
5853 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5856 rtx_insn
*prev
= insn
;
5860 int reverse_code
= 0;
5862 basic_block bb
= BLOCK_FOR_INSN (insn
);
5864 code
= GET_CODE (cond
);
5865 mode
= GET_MODE (cond
);
5866 op0
= XEXP (cond
, 0);
5867 op1
= XEXP (cond
, 1);
5870 code
= reversed_comparison_code (cond
, insn
);
5871 if (code
== UNKNOWN
)
5877 /* If we are comparing a register with zero, see if the register is set
5878 in the previous insn to a COMPARE or a comparison operation. Perform
5879 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5882 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5883 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5884 && op1
== CONST0_RTX (GET_MODE (op0
))
5887 /* Set nonzero when we find something of interest. */
5890 /* If this is a COMPARE, pick up the two things being compared. */
5891 if (GET_CODE (op0
) == COMPARE
)
5893 op1
= XEXP (op0
, 1);
5894 op0
= XEXP (op0
, 0);
5897 else if (!REG_P (op0
))
5900 /* Go back to the previous insn. Stop if it is not an INSN. We also
5901 stop if it isn't a single set or if it has a REG_INC note because
5902 we don't want to bother dealing with it. */
5904 prev
= prev_nonnote_nondebug_insn (prev
);
5907 || !NONJUMP_INSN_P (prev
)
5908 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5909 /* In cfglayout mode, there do not have to be labels at the
5910 beginning of a block, or jumps at the end, so the previous
5911 conditions would not stop us when we reach bb boundary. */
5912 || BLOCK_FOR_INSN (prev
) != bb
)
5915 set
= set_of (op0
, prev
);
5918 && (GET_CODE (set
) != SET
5919 || !rtx_equal_p (SET_DEST (set
), op0
)))
5922 /* If this is setting OP0, get what it sets it to if it looks
5926 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5927 #ifdef FLOAT_STORE_FLAG_VALUE
5928 REAL_VALUE_TYPE fsfv
;
5931 /* ??? We may not combine comparisons done in a CCmode with
5932 comparisons not done in a CCmode. This is to aid targets
5933 like Alpha that have an IEEE compliant EQ instruction, and
5934 a non-IEEE compliant BEQ instruction. The use of CCmode is
5935 actually artificial, simply to prevent the combination, but
5936 should not affect other platforms.
5938 However, we must allow VOIDmode comparisons to match either
5939 CCmode or non-CCmode comparison, because some ports have
5940 modeless comparisons inside branch patterns.
5942 ??? This mode check should perhaps look more like the mode check
5943 in simplify_comparison in combine. */
5944 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5945 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5947 && inner_mode
!= VOIDmode
)
5949 if (GET_CODE (SET_SRC (set
)) == COMPARE
5952 && val_signbit_known_set_p (inner_mode
,
5954 #ifdef FLOAT_STORE_FLAG_VALUE
5956 && SCALAR_FLOAT_MODE_P (inner_mode
)
5957 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5958 REAL_VALUE_NEGATIVE (fsfv
)))
5961 && COMPARISON_P (SET_SRC (set
))))
5963 else if (((code
== EQ
5965 && val_signbit_known_set_p (inner_mode
,
5967 #ifdef FLOAT_STORE_FLAG_VALUE
5969 && SCALAR_FLOAT_MODE_P (inner_mode
)
5970 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5971 REAL_VALUE_NEGATIVE (fsfv
)))
5974 && COMPARISON_P (SET_SRC (set
)))
5979 else if ((code
== EQ
|| code
== NE
)
5980 && GET_CODE (SET_SRC (set
)) == XOR
)
5981 /* Handle sequences like:
5984 ...(eq|ne op0 (const_int 0))...
5988 (eq op0 (const_int 0)) reduces to (eq X Y)
5989 (ne op0 (const_int 0)) reduces to (ne X Y)
5991 This is the form used by MIPS16, for example. */
5997 else if (reg_set_p (op0
, prev
))
5998 /* If this sets OP0, but not directly, we have to give up. */
6003 /* If the caller is expecting the condition to be valid at INSN,
6004 make sure X doesn't change before INSN. */
6005 if (valid_at_insn_p
)
6006 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
6008 if (COMPARISON_P (x
))
6009 code
= GET_CODE (x
);
6012 code
= reversed_comparison_code (x
, prev
);
6013 if (code
== UNKNOWN
)
6018 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
6024 /* If constant is first, put it last. */
6025 if (CONSTANT_P (op0
))
6026 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
6028 /* If OP0 is the result of a comparison, we weren't able to find what
6029 was really being compared, so fail. */
6031 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6034 /* Canonicalize any ordered comparison with integers involving equality
6035 if we can do computations in the relevant mode and we do not
6038 scalar_int_mode op0_mode
;
6039 if (CONST_INT_P (op1
)
6040 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &op0_mode
)
6041 && GET_MODE_PRECISION (op0_mode
) <= HOST_BITS_PER_WIDE_INT
)
6043 HOST_WIDE_INT const_val
= INTVAL (op1
);
6044 unsigned HOST_WIDE_INT uconst_val
= const_val
;
6045 unsigned HOST_WIDE_INT max_val
6046 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (op0_mode
);
6051 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
6052 code
= LT
, op1
= gen_int_mode (const_val
+ 1, op0_mode
);
6055 /* When cross-compiling, const_val might be sign-extended from
6056 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
6058 if ((const_val
& max_val
)
6059 != (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (op0_mode
) - 1)))
6060 code
= GT
, op1
= gen_int_mode (const_val
- 1, op0_mode
);
6064 if (uconst_val
< max_val
)
6065 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, op0_mode
);
6069 if (uconst_val
!= 0)
6070 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, op0_mode
);
6078 /* We promised to return a comparison. */
6079 rtx ret
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
6080 if (COMPARISON_P (ret
))
6085 /* Given a jump insn JUMP, return the condition that will cause it to branch
6086 to its JUMP_LABEL. If the condition cannot be understood, or is an
6087 inequality floating-point comparison which needs to be reversed, 0 will
6090 If EARLIEST is nonzero, it is a pointer to a place where the earliest
6091 insn used in locating the condition was found. If a replacement test
6092 of the condition is desired, it should be placed in front of that
6093 insn and we will be sure that the inputs are still valid. If EARLIEST
6094 is null, the returned condition will be valid at INSN.
6096 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
6097 compare CC mode register.
6099 VALID_AT_INSN_P is the same as for canonicalize_condition. */
6102 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
6103 int valid_at_insn_p
)
6109 /* If this is not a standard conditional jump, we can't parse it. */
6111 || ! any_condjump_p (jump
))
6113 set
= pc_set (jump
);
6115 cond
= XEXP (SET_SRC (set
), 0);
6117 /* If this branches to JUMP_LABEL when the condition is false, reverse
6120 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
6121 && label_ref_label (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
6123 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
6124 allow_cc_mode
, valid_at_insn_p
);
6127 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
6128 TARGET_MODE_REP_EXTENDED.
6130 Note that we assume that the property of
6131 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
6132 narrower than mode B. I.e., if A is a mode narrower than B then in
6133 order to be able to operate on it in mode B, mode A needs to
6134 satisfy the requirements set by the representation of mode B. */
6137 init_num_sign_bit_copies_in_rep (void)
6139 opt_scalar_int_mode in_mode_iter
;
6140 scalar_int_mode mode
;
6142 FOR_EACH_MODE_IN_CLASS (in_mode_iter
, MODE_INT
)
6143 FOR_EACH_MODE_UNTIL (mode
, in_mode_iter
.require ())
6145 scalar_int_mode in_mode
= in_mode_iter
.require ();
6148 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
6149 extends to the next widest mode. */
6150 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
6151 || GET_MODE_WIDER_MODE (mode
).require () == in_mode
);
6153 /* We are in in_mode. Count how many bits outside of mode
6154 have to be copies of the sign-bit. */
6155 FOR_EACH_MODE (i
, mode
, in_mode
)
6157 /* This must always exist (for the last iteration it will be
6159 scalar_int_mode wider
= GET_MODE_WIDER_MODE (i
).require ();
6161 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
6162 /* We can only check sign-bit copies starting from the
6163 top-bit. In order to be able to check the bits we
6164 have already seen we pretend that subsequent bits
6165 have to be sign-bit copies too. */
6166 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
6167 num_sign_bit_copies_in_rep
[in_mode
][mode
]
6168 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
6173 /* Suppose that truncation from the machine mode of X to MODE is not a
6174 no-op. See if there is anything special about X so that we can
6175 assume it already contains a truncated value of MODE. */
6178 truncated_to_mode (machine_mode mode
, const_rtx x
)
6180 /* This register has already been used in MODE without explicit
6182 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
6185 /* See if we already satisfy the requirements of MODE. If yes we
6186 can just switch to MODE. */
6187 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
6188 && (num_sign_bit_copies (x
, GET_MODE (x
))
6189 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
6195 /* Return true if RTX code CODE has a single sequence of zero or more
6196 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
6197 entry in that case. */
6200 setup_reg_subrtx_bounds (unsigned int code
)
6202 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
6204 for (; format
[i
] != 'e'; ++i
)
6207 /* No subrtxes. Leave start and count as 0. */
6209 if (format
[i
] == 'E' || format
[i
] == 'V')
6213 /* Record the sequence of 'e's. */
6214 rtx_all_subrtx_bounds
[code
].start
= i
;
6217 while (format
[i
] == 'e');
6218 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
6219 /* rtl-iter.h relies on this. */
6220 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
6222 for (; format
[i
]; ++i
)
6223 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
6229 /* Initialize rtx_all_subrtx_bounds. */
6234 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
6236 if (!setup_reg_subrtx_bounds (i
))
6237 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
6238 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
6239 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
6242 init_num_sign_bit_copies_in_rep ();
6245 /* Check whether this is a constant pool constant. */
6247 constant_pool_constant_p (rtx x
)
6249 x
= avoid_constant_pool_reference (x
);
6250 return CONST_DOUBLE_P (x
);
6253 /* If M is a bitmask that selects a field of low-order bits within an item but
6254 not the entire word, return the length of the field. Return -1 otherwise.
6255 M is used in machine mode MODE. */
6258 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
6260 if (mode
!= VOIDmode
)
6262 if (!HWI_COMPUTABLE_MODE_P (mode
))
6264 m
&= GET_MODE_MASK (mode
);
6267 return exact_log2 (m
+ 1);
6270 /* Return the mode of MEM's address. */
6273 get_address_mode (rtx mem
)
6277 gcc_assert (MEM_P (mem
));
6278 mode
= GET_MODE (XEXP (mem
, 0));
6279 if (mode
!= VOIDmode
)
6280 return as_a
<scalar_int_mode
> (mode
);
6281 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
6284 /* Split up a CONST_DOUBLE or integer constant rtx
6285 into two rtx's for single words,
6286 storing in *FIRST the word that comes first in memory in the target
6287 and in *SECOND the other.
6289 TODO: This function needs to be rewritten to work on any size
6293 split_double (rtx value
, rtx
*first
, rtx
*second
)
6295 if (CONST_INT_P (value
))
6297 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
6299 /* In this case the CONST_INT holds both target words.
6300 Extract the bits from it into two word-sized pieces.
6301 Sign extend each half to HOST_WIDE_INT. */
6302 unsigned HOST_WIDE_INT low
, high
;
6303 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
6304 unsigned bits_per_word
= BITS_PER_WORD
;
6306 /* Set sign_bit to the most significant bit of a word. */
6308 sign_bit
<<= bits_per_word
- 1;
6310 /* Set mask so that all bits of the word are set. We could
6311 have used 1 << BITS_PER_WORD instead of basing the
6312 calculation on sign_bit. However, on machines where
6313 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
6314 compiler warning, even though the code would never be
6316 mask
= sign_bit
<< 1;
6319 /* Set sign_extend as any remaining bits. */
6320 sign_extend
= ~mask
;
6322 /* Pick the lower word and sign-extend it. */
6323 low
= INTVAL (value
);
6328 /* Pick the higher word, shifted to the least significant
6329 bits, and sign-extend it. */
6330 high
= INTVAL (value
);
6331 high
>>= bits_per_word
- 1;
6334 if (high
& sign_bit
)
6335 high
|= sign_extend
;
6337 /* Store the words in the target machine order. */
6338 if (WORDS_BIG_ENDIAN
)
6340 *first
= GEN_INT (high
);
6341 *second
= GEN_INT (low
);
6345 *first
= GEN_INT (low
);
6346 *second
= GEN_INT (high
);
6351 /* The rule for using CONST_INT for a wider mode
6352 is that we regard the value as signed.
6353 So sign-extend it. */
6354 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
6355 if (WORDS_BIG_ENDIAN
)
6367 else if (GET_CODE (value
) == CONST_WIDE_INT
)
6369 /* All of this is scary code and needs to be converted to
6370 properly work with any size integer. */
6371 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
6372 if (WORDS_BIG_ENDIAN
)
6374 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6375 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6379 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
6380 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
6383 else if (!CONST_DOUBLE_P (value
))
6385 if (WORDS_BIG_ENDIAN
)
6387 *first
= const0_rtx
;
6393 *second
= const0_rtx
;
6396 else if (GET_MODE (value
) == VOIDmode
6397 /* This is the old way we did CONST_DOUBLE integers. */
6398 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
6400 /* In an integer, the words are defined as most and least significant.
6401 So order them by the target's convention. */
6402 if (WORDS_BIG_ENDIAN
)
6404 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6405 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
6409 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
6410 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
6417 /* Note, this converts the REAL_VALUE_TYPE to the target's
6418 format, splits up the floating point double and outputs
6419 exactly 32 bits of it into each of l[0] and l[1] --
6420 not necessarily BITS_PER_WORD bits. */
6421 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
6423 /* If 32 bits is an entire word for the target, but not for the host,
6424 then sign-extend on the host so that the number will look the same
6425 way on the host that it would on the target. See for instance
6426 simplify_unary_operation. The #if is needed to avoid compiler
6429 #if HOST_BITS_PER_LONG > 32
6430 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
6432 if (l
[0] & ((long) 1 << 31))
6433 l
[0] |= ((unsigned long) (-1) << 32);
6434 if (l
[1] & ((long) 1 << 31))
6435 l
[1] |= ((unsigned long) (-1) << 32);
6439 *first
= GEN_INT (l
[0]);
6440 *second
= GEN_INT (l
[1]);
6444 /* Return true if X is a sign_extract or zero_extract from the least
6448 lsb_bitfield_op_p (rtx x
)
6450 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
6452 machine_mode mode
= GET_MODE (XEXP (x
, 0));
6453 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
6454 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
6455 poly_int64 remaining_bits
= GET_MODE_PRECISION (mode
) - len
;
6457 return known_eq (pos
, BITS_BIG_ENDIAN
? remaining_bits
: 0);
6462 /* Strip outer address "mutations" from LOC and return a pointer to the
6463 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6464 stripped expression there.
6466 "Mutations" either convert between modes or apply some kind of
6467 extension, truncation or alignment. */
6470 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
6474 enum rtx_code code
= GET_CODE (*loc
);
6475 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
6476 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6477 used to convert between pointer sizes. */
6478 loc
= &XEXP (*loc
, 0);
6479 else if (lsb_bitfield_op_p (*loc
))
6480 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6481 acts as a combined truncation and extension. */
6482 loc
= &XEXP (*loc
, 0);
6483 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
6484 /* (and ... (const_int -X)) is used to align to X bytes. */
6485 loc
= &XEXP (*loc
, 0);
6486 else if (code
== SUBREG
6487 && !OBJECT_P (SUBREG_REG (*loc
))
6488 && subreg_lowpart_p (*loc
))
6489 /* (subreg (operator ...) ...) inside and is used for mode
6491 loc
= &SUBREG_REG (*loc
);
6499 /* Return true if CODE applies some kind of scale. The scaled value is
6500 is the first operand and the scale is the second. */
6503 binary_scale_code_p (enum rtx_code code
)
6505 return (code
== MULT
6507 /* Needed by ARM targets. */
6511 || code
== ROTATERT
);
6514 /* If *INNER can be interpreted as a base, return a pointer to the inner term
6515 (see address_info). Return null otherwise. */
6518 get_base_term (rtx
*inner
)
6520 if (GET_CODE (*inner
) == LO_SUM
)
6521 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6524 || GET_CODE (*inner
) == SUBREG
6525 || GET_CODE (*inner
) == SCRATCH
)
6530 /* If *INNER can be interpreted as an index, return a pointer to the inner term
6531 (see address_info). Return null otherwise. */
6534 get_index_term (rtx
*inner
)
6536 /* At present, only constant scales are allowed. */
6537 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
6538 inner
= strip_address_mutations (&XEXP (*inner
, 0));
6541 || GET_CODE (*inner
) == SUBREG
6542 || GET_CODE (*inner
) == SCRATCH
)
6547 /* Set the segment part of address INFO to LOC, given that INNER is the
6551 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6553 gcc_assert (!info
->segment
);
6554 info
->segment
= loc
;
6555 info
->segment_term
= inner
;
6558 /* Set the base part of address INFO to LOC, given that INNER is the
6562 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6564 gcc_assert (!info
->base
);
6566 info
->base_term
= inner
;
6569 /* Set the index part of address INFO to LOC, given that INNER is the
6573 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6575 gcc_assert (!info
->index
);
6577 info
->index_term
= inner
;
6580 /* Set the displacement part of address INFO to LOC, given that INNER
6581 is the constant term. */
6584 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6586 gcc_assert (!info
->disp
);
6588 info
->disp_term
= inner
;
6591 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6592 rest of INFO accordingly. */
6595 decompose_incdec_address (struct address_info
*info
)
6597 info
->autoinc_p
= true;
6599 rtx
*base
= &XEXP (*info
->inner
, 0);
6600 set_address_base (info
, base
, base
);
6601 gcc_checking_assert (info
->base
== info
->base_term
);
6603 /* These addresses are only valid when the size of the addressed
6605 gcc_checking_assert (info
->mode
!= VOIDmode
);
6608 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6609 of INFO accordingly. */
6612 decompose_automod_address (struct address_info
*info
)
6614 info
->autoinc_p
= true;
6616 rtx
*base
= &XEXP (*info
->inner
, 0);
6617 set_address_base (info
, base
, base
);
6618 gcc_checking_assert (info
->base
== info
->base_term
);
6620 rtx plus
= XEXP (*info
->inner
, 1);
6621 gcc_assert (GET_CODE (plus
) == PLUS
);
6623 info
->base_term2
= &XEXP (plus
, 0);
6624 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6626 rtx
*step
= &XEXP (plus
, 1);
6627 rtx
*inner_step
= strip_address_mutations (step
);
6628 if (CONSTANT_P (*inner_step
))
6629 set_address_disp (info
, step
, inner_step
);
6631 set_address_index (info
, step
, inner_step
);
6634 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6635 values in [PTR, END). Return a pointer to the end of the used array. */
6638 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6641 if (GET_CODE (x
) == PLUS
)
6643 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6644 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6648 gcc_assert (ptr
!= end
);
6654 /* Evaluate the likelihood of X being a base or index value, returning
6655 positive if it is likely to be a base, negative if it is likely to be
6656 an index, and 0 if we can't tell. Make the magnitude of the return
6657 value reflect the amount of confidence we have in the answer.
6659 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6662 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6663 enum rtx_code outer_code
, enum rtx_code index_code
)
6665 /* Believe *_POINTER unless the address shape requires otherwise. */
6666 if (REG_P (x
) && REG_POINTER (x
))
6668 if (MEM_P (x
) && MEM_POINTER (x
))
6671 if (REG_P (x
) && HARD_REGISTER_P (x
))
6673 /* X is a hard register. If it only fits one of the base
6674 or index classes, choose that interpretation. */
6675 int regno
= REGNO (x
);
6676 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6677 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6678 if (base_p
!= index_p
)
6679 return base_p
? 1 : -1;
6684 /* INFO->INNER describes a normal, non-automodified address.
6685 Fill in the rest of INFO accordingly. */
6688 decompose_normal_address (struct address_info
*info
)
6690 /* Treat the address as the sum of up to four values. */
6692 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6693 ops
+ ARRAY_SIZE (ops
)) - ops
;
6695 /* If there is more than one component, any base component is in a PLUS. */
6697 info
->base_outer_code
= PLUS
;
6699 /* Try to classify each sum operand now. Leave those that could be
6700 either a base or an index in OPS. */
6703 for (size_t in
= 0; in
< n_ops
; ++in
)
6706 rtx
*inner
= strip_address_mutations (loc
);
6707 if (CONSTANT_P (*inner
))
6708 set_address_disp (info
, loc
, inner
);
6709 else if (GET_CODE (*inner
) == UNSPEC
)
6710 set_address_segment (info
, loc
, inner
);
6713 /* The only other possibilities are a base or an index. */
6714 rtx
*base_term
= get_base_term (inner
);
6715 rtx
*index_term
= get_index_term (inner
);
6716 gcc_assert (base_term
|| index_term
);
6718 set_address_index (info
, loc
, index_term
);
6719 else if (!index_term
)
6720 set_address_base (info
, loc
, base_term
);
6723 gcc_assert (base_term
== index_term
);
6725 inner_ops
[out
] = base_term
;
6731 /* Classify the remaining OPS members as bases and indexes. */
6734 /* If we haven't seen a base or an index yet, assume that this is
6735 the base. If we were confident that another term was the base
6736 or index, treat the remaining operand as the other kind. */
6738 set_address_base (info
, ops
[0], inner_ops
[0]);
6740 set_address_index (info
, ops
[0], inner_ops
[0]);
6744 /* In the event of a tie, assume the base comes first. */
6745 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6747 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6748 GET_CODE (*ops
[0])))
6750 set_address_base (info
, ops
[0], inner_ops
[0]);
6751 set_address_index (info
, ops
[1], inner_ops
[1]);
6755 set_address_base (info
, ops
[1], inner_ops
[1]);
6756 set_address_index (info
, ops
[0], inner_ops
[0]);
6760 gcc_assert (out
== 0);
6763 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6764 or VOIDmode if not known. AS is the address space associated with LOC.
6765 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6768 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6769 addr_space_t as
, enum rtx_code outer_code
)
6771 memset (info
, 0, sizeof (*info
));
6774 info
->addr_outer_code
= outer_code
;
6776 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6777 info
->base_outer_code
= outer_code
;
6778 switch (GET_CODE (*info
->inner
))
6784 decompose_incdec_address (info
);
6789 decompose_automod_address (info
);
6793 decompose_normal_address (info
);
6798 /* Describe address operand LOC in INFO. */
6801 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6803 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6806 /* Describe the address of MEM X in INFO. */
6809 decompose_mem_address (struct address_info
*info
, rtx x
)
6811 gcc_assert (MEM_P (x
));
6812 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6813 MEM_ADDR_SPACE (x
), MEM
);
6816 /* Update INFO after a change to the address it describes. */
6819 update_address (struct address_info
*info
)
6821 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6822 info
->addr_outer_code
);
6825 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6826 more complicated than that. */
6829 get_index_scale (const struct address_info
*info
)
6831 rtx index
= *info
->index
;
6832 if (GET_CODE (index
) == MULT
6833 && CONST_INT_P (XEXP (index
, 1))
6834 && info
->index_term
== &XEXP (index
, 0))
6835 return INTVAL (XEXP (index
, 1));
6837 if (GET_CODE (index
) == ASHIFT
6838 && CONST_INT_P (XEXP (index
, 1))
6839 && info
->index_term
== &XEXP (index
, 0))
6840 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6842 if (info
->index
== info
->index_term
)
6848 /* Return the "index code" of INFO, in the form required by
6852 get_index_code (const struct address_info
*info
)
6855 return GET_CODE (*info
->index
);
6858 return GET_CODE (*info
->disp
);
6863 /* Return true if RTL X contains a SYMBOL_REF. */
6866 contains_symbol_ref_p (const_rtx x
)
6868 subrtx_iterator::array_type array
;
6869 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6870 if (SYMBOL_REF_P (*iter
))
6876 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6879 contains_symbolic_reference_p (const_rtx x
)
6881 subrtx_iterator::array_type array
;
6882 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6883 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6889 /* Return true if RTL X contains a constant pool address. */
6892 contains_constant_pool_address_p (const_rtx x
)
6894 subrtx_iterator::array_type array
;
6895 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6896 if (SYMBOL_REF_P (*iter
) && CONSTANT_POOL_ADDRESS_P (*iter
))
6903 /* Return true if X contains a thread-local symbol. */
6906 tls_referenced_p (const_rtx x
)
6908 if (!targetm
.have_tls
)
6911 subrtx_iterator::array_type array
;
6912 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6913 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)
6918 /* Process recursively X of INSN and add REG_INC notes if necessary. */
6920 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
6922 enum rtx_code code
= GET_CODE (x
);
6926 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
6928 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
6932 /* Scan all X sub-expressions. */
6933 fmt
= GET_RTX_FORMAT (code
);
6934 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6937 add_auto_inc_notes (insn
, XEXP (x
, i
));
6938 else if (fmt
[i
] == 'E')
6939 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6940 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
6944 /* Return true if X is register asm. */
6947 register_asm_p (const_rtx x
)
6950 && REG_EXPR (x
) != NULL_TREE
6951 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (x
))
6952 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (x
))
6953 && DECL_REGISTER (REG_EXPR (x
)));
6956 /* Return true if, for all OP of mode OP_MODE:
6958 (vec_select:RESULT_MODE OP SEL)
6960 is equivalent to the highpart RESULT_MODE of OP. */
6963 vec_series_highpart_p (machine_mode result_mode
, machine_mode op_mode
, rtx sel
)
6966 if (GET_MODE_NUNITS (op_mode
).is_constant (&nunits
)
6967 && targetm
.can_change_mode_class (op_mode
, result_mode
, ALL_REGS
))
6969 int offset
= BYTES_BIG_ENDIAN
? 0 : nunits
- XVECLEN (sel
, 0);
6970 return rtvec_series_p (XVEC (sel
, 0), offset
);
6975 /* Return true if, for all OP of mode OP_MODE:
6977 (vec_select:RESULT_MODE OP SEL)
6979 is equivalent to the lowpart RESULT_MODE of OP. */
6982 vec_series_lowpart_p (machine_mode result_mode
, machine_mode op_mode
, rtx sel
)
6985 if (GET_MODE_NUNITS (op_mode
).is_constant (&nunits
)
6986 && targetm
.can_change_mode_class (op_mode
, result_mode
, ALL_REGS
))
6988 int offset
= BYTES_BIG_ENDIAN
? nunits
- XVECLEN (sel
, 0) : 0;
6989 return rtvec_series_p (XVEC (sel
, 0), offset
);