1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2022 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
132 #include "print-rtl.h"
133 #include "function-abi.h"
134 #include "rtl-iter.h"
136 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
137 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
139 static int bb_reload_num
;
141 /* The current insn being processed and corresponding its single set
142 (NULL otherwise), its data (basic block, the insn data, the insn
143 static data, and the mode of each operand). */
144 static rtx_insn
*curr_insn
;
145 static rtx curr_insn_set
;
146 static basic_block curr_bb
;
147 static lra_insn_recog_data_t curr_id
;
148 static struct lra_static_insn_data
*curr_static_id
;
149 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Mode of the register substituted by its equivalence with VOIDmode
151 (e.g. constant) and whose subreg is given operand of the current
152 insn. VOIDmode in all other cases. */
153 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
157 /* Start numbers for new registers and insns at the current constraints
159 static int new_regno_start
;
160 static int new_insn_uid_start
;
162 /* If LOC is nonnull, strip any outer subreg from it. */
164 strip_subreg (rtx
*loc
)
166 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
169 /* Return hard regno of REGNO or if it is was not assigned to a hard
170 register, use a hard register from its allocno class. */
172 get_try_hard_regno (int regno
)
175 enum reg_class rclass
;
177 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
178 hard_regno
= lra_get_regno_hard_regno (regno
);
181 rclass
= lra_get_allocno_class (regno
);
182 if (rclass
== NO_REGS
)
184 return ira_class_hard_regs
[rclass
][0];
187 /* Return the hard regno of X after removing its subreg. If X is not
188 a register or a subreg of a register, return -1. If X is a pseudo,
189 use its assignment. If FINAL_P return the final hard regno which will
190 be after elimination. */
192 get_hard_regno (rtx x
, bool final_p
)
199 reg
= SUBREG_REG (x
);
202 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
203 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
207 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
209 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
210 SUBREG_BYTE (x
), GET_MODE (x
));
214 /* If REGNO is a hard register or has been allocated a hard register,
215 return the class of that register. If REGNO is a reload pseudo
216 created by the current constraints pass, return its allocno class.
217 Return NO_REGS otherwise. */
218 static enum reg_class
219 get_reg_class (int regno
)
223 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
224 hard_regno
= lra_get_regno_hard_regno (regno
);
227 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
228 return REGNO_REG_CLASS (hard_regno
);
230 if (regno
>= new_regno_start
)
231 return lra_get_allocno_class (regno
);
235 /* Return true if REG satisfies (or will satisfy) reg class constraint
236 CL. Use elimination first if REG is a hard register. If REG is a
237 reload pseudo created by this constraints pass, assume that it will
238 be allocated a hard register from its allocno class, but allow that
239 class to be narrowed to CL if it is currently a superset of CL and
242 - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
243 - the instruction we're processing is not a reload move.
245 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
246 REGNO (reg), or NO_REGS if no change in its class was needed. */
248 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
,
249 bool allow_all_reload_class_changes_p
= false)
251 enum reg_class rclass
, common_class
;
252 machine_mode reg_mode
;
254 int class_size
, hard_regno
, nregs
, i
, j
;
255 int regno
= REGNO (reg
);
257 if (new_class
!= NULL
)
258 *new_class
= NO_REGS
;
259 if (regno
< FIRST_PSEUDO_REGISTER
)
262 rtx
*final_loc
= &final_reg
;
264 lra_eliminate_reg_if_possible (final_loc
);
265 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
267 reg_mode
= GET_MODE (reg
);
268 rclass
= get_reg_class (regno
);
269 src
= curr_insn_set
!= NULL
? SET_SRC (curr_insn_set
) : NULL
;
270 if (regno
< new_regno_start
271 /* Do not allow the constraints for reload instructions to
272 influence the classes of new pseudos. These reloads are
273 typically moves that have many alternatives, and restricting
274 reload pseudos for one alternative may lead to situations
275 where other reload pseudos are no longer allocatable. */
276 || (!allow_all_reload_class_changes_p
277 && INSN_UID (curr_insn
) >= new_insn_uid_start
279 && ((REG_P (src
) || MEM_P (src
))
280 || (GET_CODE (src
) == SUBREG
281 && (REG_P (SUBREG_REG (src
)) || MEM_P (SUBREG_REG (src
)))))))
282 /* When we don't know what class will be used finally for reload
283 pseudos, we use ALL_REGS. */
284 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
285 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
286 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
287 lra_no_alloc_regs
)));
290 common_class
= ira_reg_class_subset
[rclass
][cl
];
291 if (new_class
!= NULL
)
292 *new_class
= common_class
;
293 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
296 /* Check that there are enough allocatable regs. */
297 class_size
= ira_class_hard_regs_num
[common_class
];
298 for (i
= 0; i
< class_size
; i
++)
300 hard_regno
= ira_class_hard_regs
[common_class
][i
];
301 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
304 for (j
= 0; j
< nregs
; j
++)
305 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
306 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
316 /* Return true if REGNO satisfies a memory constraint. */
320 return get_reg_class (regno
) == NO_REGS
;
323 /* Return 1 if ADDR is a valid memory address for mode MODE in address
324 space AS, and check that each pseudo has the proper kind of hard
327 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
328 rtx addr
, addr_space_t as
)
330 #ifdef GO_IF_LEGITIMATE_ADDRESS
331 lra_assert (ADDR_SPACE_GENERIC_P (as
));
332 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
338 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
343 /* Temporarily eliminates registers in an address (for the lifetime of
345 class address_eliminator
{
347 address_eliminator (struct address_info
*ad
);
348 ~address_eliminator ();
351 struct address_info
*m_ad
;
359 address_eliminator::address_eliminator (struct address_info
*ad
)
361 m_base_loc (strip_subreg (ad
->base_term
)),
362 m_base_reg (NULL_RTX
),
363 m_index_loc (strip_subreg (ad
->index_term
)),
364 m_index_reg (NULL_RTX
)
366 if (m_base_loc
!= NULL
)
368 m_base_reg
= *m_base_loc
;
369 /* If we have non-legitimate address which is decomposed not in
370 the way we expected, don't do elimination here. In such case
371 the address will be reloaded and elimination will be done in
372 reload insn finally. */
373 if (REG_P (m_base_reg
))
374 lra_eliminate_reg_if_possible (m_base_loc
);
375 if (m_ad
->base_term2
!= NULL
)
376 *m_ad
->base_term2
= *m_ad
->base_term
;
378 if (m_index_loc
!= NULL
)
380 m_index_reg
= *m_index_loc
;
381 if (REG_P (m_index_reg
))
382 lra_eliminate_reg_if_possible (m_index_loc
);
386 address_eliminator::~address_eliminator ()
388 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
390 *m_base_loc
= m_base_reg
;
391 if (m_ad
->base_term2
!= NULL
)
392 *m_ad
->base_term2
= *m_ad
->base_term
;
394 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
395 *m_index_loc
= m_index_reg
;
398 /* Return true if the eliminated form of AD is a legitimate target address.
399 If OP is a MEM, AD is the address within OP, otherwise OP should be
400 ignored. CONSTRAINT is one constraint that the operand may need
403 valid_address_p (rtx op
, struct address_info
*ad
,
404 enum constraint_num constraint
)
406 address_eliminator
eliminator (ad
);
408 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
410 Need to extract memory from op for special memory constraint,
411 i.e. bcst_mem_operand in i386 backend. */
412 if (MEM_P (extract_mem_from_operand (op
))
413 && insn_extra_relaxed_memory_constraint (constraint
)
414 && constraint_satisfied_p (op
, constraint
))
417 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
420 /* For special_memory_operand, it could be false for MEM_P (op),
421 i.e. bcst_mem_operand in i386 backend.
422 Extract and return real memory operand or op. */
424 extract_mem_from_operand (rtx op
)
426 for (rtx x
= op
;; x
= XEXP (x
, 0))
430 if (GET_RTX_LENGTH (GET_CODE (x
)) != 1
431 || GET_RTX_FORMAT (GET_CODE (x
))[0] != 'e')
437 /* Return true if the eliminated form of memory reference OP satisfies
438 extra (special) memory constraint CONSTRAINT. */
440 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
442 struct address_info ad
;
443 rtx mem
= extract_mem_from_operand (op
);
447 decompose_mem_address (&ad
, mem
);
448 address_eliminator
eliminator (&ad
);
449 return constraint_satisfied_p (op
, constraint
);
452 /* Return true if the eliminated form of address AD satisfies extra
453 address constraint CONSTRAINT. */
455 satisfies_address_constraint_p (struct address_info
*ad
,
456 enum constraint_num constraint
)
458 address_eliminator
eliminator (ad
);
459 return constraint_satisfied_p (*ad
->outer
, constraint
);
462 /* Return true if the eliminated form of address OP satisfies extra
463 address constraint CONSTRAINT. */
465 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
467 struct address_info ad
;
469 decompose_lea_address (&ad
, &op
);
470 return satisfies_address_constraint_p (&ad
, constraint
);
473 /* Initiate equivalences for LRA. As we keep original equivalences
474 before any elimination, we need to make copies otherwise any change
475 in insns might change the equivalences. */
477 lra_init_equiv (void)
479 ira_expand_reg_equiv ();
480 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
484 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
485 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
486 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
487 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
491 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
493 /* Update equivalence for REGNO. We need to this as the equivalence
494 might contain other pseudos which are changed by their
497 update_equiv (int regno
)
501 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
502 ira_reg_equiv
[regno
].memory
503 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
505 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
506 ira_reg_equiv
[regno
].invariant
507 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
511 /* If we have decided to substitute X with another value, return that
512 value, otherwise return X. */
519 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
520 || ! ira_reg_equiv
[regno
].defined_p
521 || ! ira_reg_equiv
[regno
].profitable_p
522 || lra_get_regno_hard_regno (regno
) >= 0)
524 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
526 if (targetm
.cannot_substitute_mem_equiv_p (res
))
530 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
532 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
537 /* If we have decided to substitute X with the equivalent value,
538 return that value after elimination for INSN, otherwise return
541 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
543 rtx res
= get_equiv (x
);
545 if (x
== res
|| CONSTANT_P (res
))
547 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
548 false, false, 0, true);
551 /* Set up curr_operand_mode. */
553 init_curr_operand_mode (void)
555 int nop
= curr_static_id
->n_operands
;
556 for (int i
= 0; i
< nop
; i
++)
558 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
559 if (mode
== VOIDmode
)
561 /* The .md mode for address operands is the mode of the
562 addressed value rather than the mode of the address itself. */
563 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
566 mode
= curr_static_id
->operand
[i
].mode
;
568 curr_operand_mode
[i
] = mode
;
574 /* The page contains code to reuse input reloads. */
576 /* Structure describes input reload of the current insns. */
579 /* True for input reload of matched operands. */
581 /* Reloaded value. */
583 /* Reload pseudo used. */
587 /* The number of elements in the following array. */
588 static int curr_insn_input_reloads_num
;
589 /* Array containing info about input reloads. It is used to find the
590 same input reload and reuse the reload pseudo in this case. */
591 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
593 /* Initiate data concerning reuse of input reloads for the current
596 init_curr_insn_input_reloads (void)
598 curr_insn_input_reloads_num
= 0;
601 /* The canonical form of an rtx inside a MEM is not necessarily the same as the
602 canonical form of the rtx outside the MEM. Fix this up in the case that
603 we're reloading an address (and therefore pulling it outside a MEM). */
605 canonicalize_reload_addr (rtx addr
)
607 subrtx_var_iterator::array_type array
;
608 FOR_EACH_SUBRTX_VAR (iter
, array
, addr
, NONCONST
)
611 if (GET_CODE (x
) == MULT
&& CONST_INT_P (XEXP (x
, 1)))
613 const HOST_WIDE_INT ci
= INTVAL (XEXP (x
, 1));
614 const int pwr2
= exact_log2 (ci
);
617 /* Rewrite this to use a shift instead, which is canonical when
619 PUT_CODE (x
, ASHIFT
);
620 XEXP (x
, 1) = GEN_INT (pwr2
);
628 /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or
629 reuse an existing reload pseudo. Don't reuse an existing reload pseudo if
630 IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG.
631 The result pseudo is returned through RESULT_REG. Return TRUE if we created
632 a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to
633 describe new registers for debug purposes. */
635 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
636 enum reg_class rclass
, HARD_REG_SET
*exclude_start_hard_regs
,
637 bool in_subreg_p
, const char *title
, rtx
*result_reg
)
640 enum reg_class new_class
;
641 bool unique_p
= false;
645 /* Output reload registers tend to start out with a conservative
646 choice of register class. Usually this is ALL_REGS, although
647 a target might narrow it (for performance reasons) through
648 targetm.preferred_reload_class. It's therefore quite common
649 for a reload instruction to require a more restrictive class
650 than the class that was originally assigned to the reload register.
652 In these situations, it's more efficient to refine the choice
653 of register class rather than create a second reload register.
654 This also helps to avoid cycling for registers that are only
655 used by reload instructions. */
657 && (int) REGNO (original
) >= new_regno_start
658 && INSN_UID (curr_insn
) >= new_insn_uid_start
659 && in_class_p (original
, rclass
, &new_class
, true))
661 unsigned int regno
= REGNO (original
);
662 if (lra_dump_file
!= NULL
)
664 fprintf (lra_dump_file
, " Reuse r%d for output ", regno
);
665 dump_value_slim (lra_dump_file
, original
, 1);
667 if (new_class
!= lra_get_allocno_class (regno
))
668 lra_change_class (regno
, new_class
, ", change to", false);
669 if (lra_dump_file
!= NULL
)
670 fprintf (lra_dump_file
, "\n");
671 *result_reg
= original
;
675 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
,
676 exclude_start_hard_regs
, title
);
679 /* Prevent reuse value of expression with side effects,
680 e.g. volatile memory. */
681 if (! side_effects_p (original
))
682 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
684 if (! curr_insn_input_reloads
[i
].match_p
685 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
686 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
688 rtx reg
= curr_insn_input_reloads
[i
].reg
;
690 /* If input is equal to original and both are VOIDmode,
691 GET_MODE (reg) might be still different from mode.
692 Ensure we don't return *result_reg with wrong mode. */
693 if (GET_MODE (reg
) != mode
)
697 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
698 GET_MODE_SIZE (mode
)))
700 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
701 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
705 if (lra_dump_file
!= NULL
)
707 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
708 dump_value_slim (lra_dump_file
, original
, 1);
710 if (new_class
!= lra_get_allocno_class (regno
))
711 lra_change_class (regno
, new_class
, ", change to", false);
712 if (lra_dump_file
!= NULL
)
713 fprintf (lra_dump_file
, "\n");
716 /* If we have an input reload with a different mode, make sure it
717 will get a different hard reg. */
718 else if (REG_P (original
)
719 && REG_P (curr_insn_input_reloads
[i
].input
)
720 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
721 && (GET_MODE (original
)
722 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
725 *result_reg
= (unique_p
726 ? lra_create_new_reg_with_unique_value
727 : lra_create_new_reg
) (mode
, original
, rclass
,
728 exclude_start_hard_regs
, title
);
729 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
730 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
731 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
732 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
737 /* The page contains major code to choose the current insn alternative
738 and generate reloads for it. */
740 /* Return the offset from REGNO of the least significant register
743 This function is used to tell whether two registers satisfy
744 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
746 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
747 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
749 lra_constraint_offset (int regno
, machine_mode mode
)
751 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
753 scalar_int_mode int_mode
;
755 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
756 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
757 return hard_regno_nregs (regno
, mode
) - 1;
761 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
762 if they are the same hard reg, and has special hacks for
763 auto-increment and auto-decrement. This is specifically intended for
764 process_alt_operands to use in determining whether two operands
765 match. X is the operand whose number is the lower of the two.
767 It is supposed that X is the output operand and Y is the input
768 operand. Y_HARD_REGNO is the final hard regno of register Y or
769 register in subreg Y as we know it now. Otherwise, it is a
772 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
775 RTX_CODE code
= GET_CODE (x
);
780 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
781 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
785 i
= get_hard_regno (x
, false);
789 if ((j
= y_hard_regno
) < 0)
792 i
+= lra_constraint_offset (i
, GET_MODE (x
));
793 j
+= lra_constraint_offset (j
, GET_MODE (y
));
798 /* If two operands must match, because they are really a single
799 operand of an assembler insn, then two post-increments are invalid
800 because the assembler insn would increment only once. On the
801 other hand, a post-increment matches ordinary indexing if the
802 post-increment is the output operand. */
803 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
804 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
806 /* Two pre-increments are invalid because the assembler insn would
807 increment only once. On the other hand, a pre-increment matches
808 ordinary indexing if the pre-increment is the input operand. */
809 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
810 || GET_CODE (y
) == PRE_MODIFY
)
811 return operands_match_p (x
, XEXP (y
, 0), -1);
815 if (code
== REG
&& REG_P (y
))
816 return REGNO (x
) == REGNO (y
);
818 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
819 && x
== SUBREG_REG (y
))
821 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
822 && SUBREG_REG (x
) == y
)
825 /* Now we have disposed of all the cases in which different rtx
827 if (code
!= GET_CODE (y
))
830 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
831 if (GET_MODE (x
) != GET_MODE (y
))
840 if (!same_vector_encodings_p (x
, y
))
845 return label_ref_label (x
) == label_ref_label (y
);
847 return XSTR (x
, 0) == XSTR (y
, 0);
853 /* Compare the elements. If any pair of corresponding elements fail
854 to match, return false for the whole things. */
856 fmt
= GET_RTX_FORMAT (code
);
857 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
863 if (XWINT (x
, i
) != XWINT (y
, i
))
868 if (XINT (x
, i
) != XINT (y
, i
))
873 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
878 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
887 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
889 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
891 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
897 /* It is believed that rtx's at this level will never
898 contain anything but integers and other rtx's, except for
899 within LABEL_REFs and SYMBOL_REFs. */
907 /* True if X is a constant that can be forced into the constant pool.
908 MODE is the mode of the operand, or VOIDmode if not known. */
909 #define CONST_POOL_OK_P(MODE, X) \
910 ((MODE) != VOIDmode \
912 && GET_CODE (X) != HIGH \
913 && GET_MODE_SIZE (MODE).is_constant () \
914 && !targetm.cannot_force_const_mem (MODE, X))
916 /* True if C is a non-empty register class that has too few registers
917 to be safely used as a reload target class. */
918 #define SMALL_REGISTER_CLASS_P(C) \
919 (ira_class_hard_regs_num [(C)] == 1 \
920 || (ira_class_hard_regs_num [(C)] >= 1 \
921 && targetm.class_likely_spilled_p (C)))
923 /* If REG is a reload pseudo, try to make its class satisfying CL. */
925 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
927 enum reg_class rclass
;
929 /* Do not make more accurate class from reloads generated. They are
930 mostly moves with a lot of constraints. Making more accurate
931 class may results in very narrow class and impossibility of find
932 registers for several reloads of one insn. */
933 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
935 if (GET_CODE (reg
) == SUBREG
)
936 reg
= SUBREG_REG (reg
);
937 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
939 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
940 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
943 /* Searches X for any reference to a reg with the same value as REGNO,
944 returning the rtx of the reference found if any. Otherwise,
947 regno_val_use_in (unsigned int regno
, rtx x
)
953 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
956 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
957 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
961 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
964 else if (fmt
[i
] == 'E')
965 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
966 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
973 /* Return true if all current insn non-output operands except INS (it
974 has a negaitve end marker) do not use pseudos with the same value
977 check_conflict_input_operands (int regno
, signed char *ins
)
980 int n_operands
= curr_static_id
->n_operands
;
982 for (int nop
= 0; nop
< n_operands
; nop
++)
983 if (! curr_static_id
->operand
[nop
].is_operator
984 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
986 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
990 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
996 /* Generate reloads for matching OUT and INS (array of input operand numbers
997 with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS,
998 considering output operands OUTS (similar array to INS) needing to be in
999 different registers. Add input and output reloads correspondingly to the
1000 lists *BEFORE and *AFTER. OUT might be negative. In this case we generate
1001 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1002 that the output operand is early clobbered for chosen alternative. */
1004 match_reload (signed char out
, signed char *ins
, signed char *outs
,
1005 enum reg_class goal_class
, HARD_REG_SET
*exclude_start_hard_regs
,
1006 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
1010 rtx new_in_reg
, new_out_reg
, reg
;
1011 machine_mode inmode
, outmode
;
1012 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
1013 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
1015 inmode
= curr_operand_mode
[ins
[0]];
1016 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
1017 push_to_sequence (*before
);
1018 if (inmode
!= outmode
)
1020 /* process_alt_operands has already checked that the mode sizes
1022 if (partial_subreg_p (outmode
, inmode
))
1025 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
, goal_class
,
1026 exclude_start_hard_regs
,
1028 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
1029 LRA_SUBREG_P (new_out_reg
) = 1;
1030 /* If the input reg is dying here, we can use the same hard
1031 register for REG and IN_RTX. We do it only for original
1032 pseudos as reload pseudos can die although original
1033 pseudos still live where reload pseudos dies. */
1034 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
1035 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1036 && (!early_clobber_p
1037 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
1038 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
1043 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1045 exclude_start_hard_regs
,
1047 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
1048 /* NEW_IN_REG is non-paradoxical subreg. We don't want
1049 NEW_OUT_REG living above. We add clobber clause for
1050 this. This is just a temporary clobber. We can remove
1051 it at the end of LRA work. */
1052 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
1053 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
1054 LRA_SUBREG_P (new_in_reg
) = 1;
1055 if (GET_CODE (in_rtx
) == SUBREG
)
1057 rtx subreg_reg
= SUBREG_REG (in_rtx
);
1059 /* If SUBREG_REG is dying here and sub-registers IN_RTX
1060 and NEW_IN_REG are similar, we can use the same hard
1061 register for REG and SUBREG_REG. */
1062 if (REG_P (subreg_reg
)
1063 && (int) REGNO (subreg_reg
) < lra_new_regno_start
1064 && GET_MODE (subreg_reg
) == outmode
1065 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
1066 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
1067 && (! early_clobber_p
1068 || check_conflict_input_operands (REGNO (subreg_reg
),
1070 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1076 /* Pseudos have values -- see comments for lra_reg_info.
1077 Different pseudos with the same value do not conflict even if
1078 they live in the same place. When we create a pseudo we
1079 assign value of original pseudo (if any) from which we
1080 created the new pseudo. If we create the pseudo from the
1081 input pseudo, the new pseudo will have no conflict with the
1082 input pseudo which is wrong when the input pseudo lives after
1083 the insn and as the new pseudo value is changed by the insn
1084 output. Therefore we create the new pseudo from the output
1085 except the case when we have single matched dying input
1088 We cannot reuse the current output register because we might
1089 have a situation like "a <- a op b", where the constraints
1090 force the second input operand ("b") to match the output
1091 operand ("a"). "b" must then be copied into a new register
1092 so that it doesn't clobber the current value of "a".
1094 We cannot use the same value if the output pseudo is
1095 early clobbered or the input pseudo is mentioned in the
1096 output, e.g. as an address part in memory, because
1097 output reload will actually extend the pseudo liveness.
1098 We don't care about eliminable hard regs here as we are
1099 interesting only in pseudos. */
1101 /* Matching input's register value is the same as one of the other
1102 output operand. Output operands in a parallel insn must be in
1103 different registers. */
1104 out_conflict
= false;
1107 for (i
= 0; outs
[i
] >= 0; i
++)
1109 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1110 if (outs
[i
] != out
&& REG_P (other_out_rtx
)
1111 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1114 out_conflict
= true;
1120 new_in_reg
= new_out_reg
1121 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1122 && (int) REGNO (in_rtx
) < lra_new_regno_start
1123 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1124 && (! early_clobber_p
1125 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1127 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1129 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
,
1130 exclude_start_hard_regs
, "")
1131 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
, goal_class
,
1132 exclude_start_hard_regs
,
1135 /* In operand can be got from transformations before processing insn
1136 constraints. One example of such transformations is subreg
1137 reloading (see function simplify_operand_subreg). The new
1138 pseudos created by the transformations might have inaccurate
1139 class (ALL_REGS) and we should make their classes more
1141 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1142 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1143 *before
= get_insns ();
1145 /* Add the new pseudo to consider values of subsequent input reload
1147 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1148 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1149 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1150 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1151 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1152 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1153 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1154 *curr_id
->operand_loc
[in
] = new_in_reg
;
1158 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1159 *curr_id
->operand_loc
[in
] = new_out_reg
;
1161 lra_update_dups (curr_id
, ins
);
1164 /* See a comment for the input operand above. */
1165 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1166 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1168 reg
= SUBREG_P (out_rtx
) ? SUBREG_REG (out_rtx
) : out_rtx
;
1170 /* If we had strict_low_part, use it also in reload to keep other
1171 parts unchanged but do it only for regs as strict_low_part
1172 has no sense for memory and probably there is no insn pattern
1173 to match the reload insn in memory case. */
1174 if (out
>= 0 && curr_static_id
->operand
[out
].strict_low
&& REG_P (reg
))
1175 out_rtx
= gen_rtx_STRICT_LOW_PART (VOIDmode
, out_rtx
);
1176 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1178 *after
= get_insns ();
1181 *curr_id
->operand_loc
[out
] = new_out_reg
;
1182 lra_update_dup (curr_id
, out
);
1185 /* Return register class which is union of all reg classes in insn
1186 constraint alternative string starting with P. */
1187 static enum reg_class
1188 reg_class_from_constraints (const char *p
)
1191 enum reg_class op_class
= NO_REGS
;
1194 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1201 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1205 enum constraint_num cn
= lookup_constraint (p
);
1206 enum reg_class cl
= reg_class_for_constraint (cn
);
1209 if (insn_extra_address_constraint (cn
))
1211 = (reg_class_subunion
1212 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1213 ADDRESS
, SCRATCH
)]);
1217 op_class
= reg_class_subunion
[op_class
][cl
];
1220 while ((p
+= len
), c
);
1224 /* If OP is a register, return the class of the register as per
1225 get_reg_class, otherwise return NO_REGS. */
1226 static inline enum reg_class
1227 get_op_class (rtx op
)
1229 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1232 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1233 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1234 SUBREG for VAL to make them equal. */
1236 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1238 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1240 /* Usually size of mem_pseudo is greater than val size but in
1241 rare cases it can be less as it can be defined by target
1242 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1245 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1246 GET_CODE (val
) == SUBREG
1247 ? SUBREG_REG (val
) : val
);
1248 LRA_SUBREG_P (val
) = 1;
1252 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1253 LRA_SUBREG_P (mem_pseudo
) = 1;
1256 return to_p
? gen_move_insn (mem_pseudo
, val
)
1257 : gen_move_insn (val
, mem_pseudo
);
1260 /* Process a special case insn (register move), return true if we
1261 don't need to process it anymore. INSN should be a single set
1262 insn. Set up that RTL was changed through CHANGE_P and that hook
1263 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1266 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1269 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1271 enum reg_class dclass
, sclass
, secondary_class
;
1272 secondary_reload_info sri
;
1274 lra_assert (curr_insn_set
!= NULL_RTX
);
1275 dreg
= dest
= SET_DEST (curr_insn_set
);
1276 sreg
= src
= SET_SRC (curr_insn_set
);
1277 if (GET_CODE (dest
) == SUBREG
)
1278 dreg
= SUBREG_REG (dest
);
1279 if (GET_CODE (src
) == SUBREG
)
1280 sreg
= SUBREG_REG (src
);
1281 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1283 sclass
= dclass
= NO_REGS
;
1285 dclass
= get_reg_class (REGNO (dreg
));
1286 gcc_assert (dclass
< LIM_REG_CLASSES
&& dclass
>= NO_REGS
);
1287 if (dclass
== ALL_REGS
)
1288 /* ALL_REGS is used for new pseudos created by transformations
1289 like reload of SUBREG_REG (see function
1290 simplify_operand_subreg). We don't know their class yet. We
1291 should figure out the class from processing the insn
1292 constraints not in this fast path function. Even if ALL_REGS
1293 were a right class for the pseudo, secondary_... hooks usually
1294 are not define for ALL_REGS. */
1297 sclass
= get_reg_class (REGNO (sreg
));
1298 gcc_assert (sclass
< LIM_REG_CLASSES
&& sclass
>= NO_REGS
);
1299 if (sclass
== ALL_REGS
)
1300 /* See comments above. */
1302 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1304 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1305 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1307 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1312 if (! REG_P (dreg
) || ! REG_P (sreg
))
1314 sri
.prev_sri
= NULL
;
1315 sri
.icode
= CODE_FOR_nothing
;
1317 secondary_class
= NO_REGS
;
1318 /* Set up hard register for a reload pseudo for hook
1319 secondary_reload because some targets just ignore unassigned
1320 pseudos in the hook. */
1321 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1323 dregno
= REGNO (dreg
);
1324 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1328 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1330 sregno
= REGNO (sreg
);
1331 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1335 if (sclass
!= NO_REGS
)
1337 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1338 (reg_class_t
) sclass
,
1339 GET_MODE (src
), &sri
);
1340 if (sclass
== NO_REGS
1341 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1342 && dclass
!= NO_REGS
))
1344 enum reg_class old_sclass
= secondary_class
;
1345 secondary_reload_info old_sri
= sri
;
1347 sri
.prev_sri
= NULL
;
1348 sri
.icode
= CODE_FOR_nothing
;
1351 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1352 (reg_class_t
) dclass
,
1353 GET_MODE (src
), &sri
);
1354 /* Check the target hook consistency. */
1356 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1357 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1358 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1361 reg_renumber
[sregno
] = -1;
1363 reg_renumber
[dregno
] = -1;
1364 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1368 if (secondary_class
!= NO_REGS
)
1369 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1370 secondary_class
, NULL
,
1373 if (sri
.icode
== CODE_FOR_nothing
)
1374 lra_emit_move (new_reg
, src
);
1377 enum reg_class scratch_class
;
1379 scratch_class
= (reg_class_from_constraints
1380 (insn_data
[sri
.icode
].operand
[2].constraint
));
1381 scratch_reg
= (lra_create_new_reg_with_unique_value
1382 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1383 scratch_class
, NULL
, "scratch"));
1384 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1387 before
= get_insns ();
1389 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1390 if (new_reg
!= NULL_RTX
)
1391 SET_SRC (curr_insn_set
) = new_reg
;
1394 if (lra_dump_file
!= NULL
)
1396 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1397 dump_insn_slim (lra_dump_file
, curr_insn
);
1399 lra_set_insn_deleted (curr_insn
);
1405 /* The following data describe the result of process_alt_operands.
1406 The data are used in curr_insn_transform to generate reloads. */
1408 /* The chosen reg classes which should be used for the corresponding
1410 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1411 /* Hard registers which cannot be a start hard register for the corresponding
1413 static HARD_REG_SET goal_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
1414 /* True if the operand should be the same as another operand and that
1415 other operand does not need a reload. */
1416 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1417 /* True if the operand does not need a reload. */
1418 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1419 /* True if the operand can be offsetable memory. */
1420 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1421 /* The number of an operand to which given operand can be matched to. */
1422 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1423 /* The number of elements in the following array. */
1424 static int goal_alt_dont_inherit_ops_num
;
1425 /* Numbers of operands whose reload pseudos should not be inherited. */
1426 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1427 /* True if the insn commutative operands should be swapped. */
1428 static bool goal_alt_swapped
;
1429 /* The chosen insn alternative. */
1430 static int goal_alt_number
;
1432 /* True if the corresponding operand is the result of an equivalence
1434 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1436 /* The following five variables are used to choose the best insn
1437 alternative. They reflect final characteristics of the best
1440 /* Number of necessary reloads and overall cost reflecting the
1441 previous value and other unpleasantness of the best alternative. */
1442 static int best_losers
, best_overall
;
1443 /* Overall number hard registers used for reloads. For example, on
1444 some targets we need 2 general registers to reload DFmode and only
1445 one floating point register. */
1446 static int best_reload_nregs
;
1447 /* Overall number reflecting distances of previous reloading the same
1448 value. The distances are counted from the current BB start. It is
1449 used to improve inheritance chances. */
1450 static int best_reload_sum
;
1452 /* True if the current insn should have no correspondingly input or
1454 static bool no_input_reloads_p
, no_output_reloads_p
;
1456 /* True if we swapped the commutative operands in the current
1458 static int curr_swapped
;
1460 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1461 register of class CL. Add any input reloads to list BEFORE. AFTER
1462 is nonnull if *LOC is an automodified value; handle that case by
1463 adding the required output reloads to list AFTER. Return true if
1464 the RTL was changed.
1466 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1467 register. Return false if the address register is correct. */
1469 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1473 enum reg_class rclass
, new_class
;
1477 bool subreg_p
, before_p
= false;
1479 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1482 reg
= SUBREG_REG (*loc
);
1483 mode
= GET_MODE (reg
);
1485 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1486 between two registers with different classes, but there normally will
1487 be "mov" which transfers element of vector register into the general
1488 register, and this normally will be a subreg which should be reloaded
1489 as a whole. This is particularly likely to be triggered when
1490 -fno-split-wide-types specified. */
1492 || in_class_p (reg
, cl
, &new_class
)
1493 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1494 loc
= &SUBREG_REG (*loc
);
1498 mode
= GET_MODE (reg
);
1503 /* Always reload memory in an address even if the target supports
1505 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, NULL
,
1511 regno
= REGNO (reg
);
1512 rclass
= get_reg_class (regno
);
1514 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1516 if (lra_dump_file
!= NULL
)
1518 fprintf (lra_dump_file
,
1519 "Changing pseudo %d in address of insn %u on equiv ",
1520 REGNO (reg
), INSN_UID (curr_insn
));
1521 dump_value_slim (lra_dump_file
, *loc
, 1);
1522 fprintf (lra_dump_file
, "\n");
1524 *loc
= copy_rtx (*loc
);
1526 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1531 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1532 mode
, reg
, cl
, NULL
,
1533 subreg_p
, "address", &new_reg
))
1536 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1540 lra_change_class (regno
, new_class
, " Change to", true);
1548 push_to_sequence (*before
);
1549 lra_emit_move (new_reg
, reg
);
1550 *before
= get_insns ();
1557 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1559 *after
= get_insns ();
1565 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1566 the insn to be inserted before curr insn. AFTER returns the
1567 the insn to be inserted after curr insn. ORIGREG and NEWREG
1568 are the original reg and new reg for reload. */
1570 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1575 push_to_sequence (*before
);
1576 lra_emit_move (newreg
, origreg
);
1577 *before
= get_insns ();
1583 lra_emit_move (origreg
, newreg
);
1585 *after
= get_insns ();
1590 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1591 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1593 /* Make reloads for subreg in operand NOP with internal subreg mode
1594 REG_MODE, add new reloads for further processing. Return true if
1595 any change was done. */
1597 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1599 int hard_regno
, inner_hard_regno
;
1600 rtx_insn
*before
, *after
;
1601 machine_mode mode
, innermode
;
1603 rtx operand
= *curr_id
->operand_loc
[nop
];
1604 enum reg_class regclass
;
1607 before
= after
= NULL
;
1609 if (GET_CODE (operand
) != SUBREG
)
1612 mode
= GET_MODE (operand
);
1613 reg
= SUBREG_REG (operand
);
1614 innermode
= GET_MODE (reg
);
1615 type
= curr_static_id
->operand
[nop
].type
;
1618 const bool addr_was_valid
1619 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1620 alter_subreg (curr_id
->operand_loc
[nop
], false);
1621 rtx subst
= *curr_id
->operand_loc
[nop
];
1622 lra_assert (MEM_P (subst
));
1623 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1625 MEM_ADDR_SPACE (subst
));
1628 || ((get_constraint_type (lookup_constraint
1629 (curr_static_id
->operand
[nop
].constraint
))
1630 != CT_SPECIAL_MEMORY
)
1631 /* We still can reload address and if the address is
1632 valid, we can remove subreg without reloading its
1634 && valid_address_p (GET_MODE (subst
),
1636 [ira_class_hard_regs
1637 [base_reg_class (GET_MODE (subst
),
1638 MEM_ADDR_SPACE (subst
),
1639 ADDRESS
, SCRATCH
)][0]],
1640 MEM_ADDR_SPACE (subst
))))
1642 /* If we change the address for a paradoxical subreg of memory, the
1643 new address might violate the necessary alignment or the access
1644 might be slow; take this into consideration. We need not worry
1645 about accesses beyond allocated memory for paradoxical memory
1646 subregs as we don't substitute such equiv memory (see processing
1647 equivalences in function lra_constraints) and because for spilled
1648 pseudos we allocate stack memory enough for the biggest
1649 corresponding paradoxical subreg.
1651 However, do not blindly simplify a (subreg (mem ...)) for
1652 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1653 data into a register when the inner is narrower than outer or
1654 missing important data from memory when the inner is wider than
1655 outer. This rule only applies to modes that are no wider than
1658 If valid memory becomes invalid after subreg elimination
1659 and address might be different we still have to reload
1662 if ((! addr_was_valid
1664 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1665 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1666 GET_MODE_PRECISION (innermode
))
1667 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1668 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1669 && WORD_REGISTER_OPERATIONS
)
1670 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1671 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1672 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1673 && targetm
.slow_unaligned_access (innermode
,
1677 *curr_id
->operand_loc
[nop
] = operand
;
1679 /* But if the address was not valid, we cannot reload the MEM without
1680 reloading the address first. */
1681 if (!addr_was_valid
)
1682 process_address (nop
, false, &before
, &after
);
1684 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1685 enum reg_class rclass
1686 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1687 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1689 TRUE
, "slow/invalid mem", &new_reg
))
1691 bool insert_before
, insert_after
;
1692 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1694 insert_before
= (type
!= OP_OUT
1695 || partial_subreg_p (mode
, innermode
));
1696 insert_after
= type
!= OP_IN
;
1697 insert_move_for_subreg (insert_before
? &before
: NULL
,
1698 insert_after
? &after
: NULL
,
1701 SUBREG_REG (operand
) = new_reg
;
1703 /* Convert to MODE. */
1706 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1707 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1709 TRUE
, "slow/invalid mem", &new_reg
))
1711 bool insert_before
, insert_after
;
1712 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1714 insert_before
= type
!= OP_OUT
;
1715 insert_after
= type
!= OP_IN
;
1716 insert_move_for_subreg (insert_before
? &before
: NULL
,
1717 insert_after
? &after
: NULL
,
1720 *curr_id
->operand_loc
[nop
] = new_reg
;
1721 lra_process_new_insns (curr_insn
, before
, after
,
1722 "Inserting slow/invalid mem reload");
1726 /* If the address was valid and became invalid, prefer to reload
1727 the memory. Typical case is when the index scale should
1728 correspond the memory. */
1729 *curr_id
->operand_loc
[nop
] = operand
;
1730 /* Do not return false here as the MEM_P (reg) will be processed
1731 later in this function. */
1733 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1735 alter_subreg (curr_id
->operand_loc
[nop
], false);
1738 else if (CONSTANT_P (reg
))
1740 /* Try to simplify subreg of constant. It is usually result of
1741 equivalence substitution. */
1742 if (innermode
== VOIDmode
1743 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1744 innermode
= curr_static_id
->operand
[nop
].mode
;
1745 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1746 SUBREG_BYTE (operand
))) != NULL_RTX
)
1748 *curr_id
->operand_loc
[nop
] = new_reg
;
1752 /* Put constant into memory when we have mixed modes. It generates
1753 a better code in most cases as it does not need a secondary
1754 reload memory. It also prevents LRA looping when LRA is using
1755 secondary reload memory again and again. */
1756 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1757 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1759 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1760 alter_subreg (curr_id
->operand_loc
[nop
], false);
1763 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1764 if there may be a problem accessing OPERAND in the outer
1767 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1768 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1769 /* Don't reload paradoxical subregs because we could be looping
1770 having repeatedly final regno out of hard regs range. */
1771 && (hard_regno_nregs (hard_regno
, innermode
)
1772 >= hard_regno_nregs (hard_regno
, mode
))
1773 && simplify_subreg_regno (hard_regno
, innermode
,
1774 SUBREG_BYTE (operand
), mode
) < 0
1775 /* Don't reload subreg for matching reload. It is actually
1776 valid subreg in LRA. */
1777 && ! LRA_SUBREG_P (operand
))
1778 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1780 enum reg_class rclass
;
1783 /* There is a big probability that we will get the same class
1784 for the new pseudo and we will get the same insn which
1785 means infinite looping. So spill the new pseudo. */
1788 /* The class will be defined later in curr_insn_transform. */
1790 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1792 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1794 TRUE
, "subreg reg", &new_reg
))
1796 bool insert_before
, insert_after
;
1797 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1799 insert_before
= (type
!= OP_OUT
1800 || read_modify_subreg_p (operand
));
1801 insert_after
= (type
!= OP_IN
);
1802 insert_move_for_subreg (insert_before
? &before
: NULL
,
1803 insert_after
? &after
: NULL
,
1806 SUBREG_REG (operand
) = new_reg
;
1807 lra_process_new_insns (curr_insn
, before
, after
,
1808 "Inserting subreg reload");
1811 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1812 IRA allocates hardreg to the inner pseudo reg according to its mode
1813 instead of the outermode, so the size of the hardreg may not be enough
1814 to contain the outermode operand, in that case we may need to insert
1815 reload for the reg. For the following two types of paradoxical subreg,
1816 we need to insert reload:
1817 1. If the op_type is OP_IN, and the hardreg could not be paired with
1818 other hardreg to contain the outermode operand
1819 (checked by in_hard_reg_set_p), we need to insert the reload.
1820 2. If the op_type is OP_OUT or OP_INOUT.
1822 Here is a paradoxical subreg example showing how the reload is generated:
1824 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1825 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1827 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1828 here, if reg107 is assigned to hardreg R15, because R15 is the last
1829 hardreg, compiler cannot find another hardreg to pair with R15 to
1830 contain TImode data. So we insert a TImode reload reg180 for it.
1831 After reload is inserted:
1833 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1834 (reg:DI 107 [ __comp ])) -1
1835 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1836 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1838 Two reload hard registers will be allocated to reg180 to save TImode data
1841 For LRA pseudos this should normally be handled by the biggest_mode
1842 mechanism. However, it's possible for new uses of an LRA pseudo
1843 to be introduced after we've allocated it, such as when undoing
1844 inheritance, and the allocated register might not then be appropriate
1845 for the new uses. */
1846 else if (REG_P (reg
)
1847 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1848 && paradoxical_subreg_p (operand
)
1849 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1851 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1852 SUBREG_BYTE (operand
), mode
)) < 0
1853 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1854 < hard_regno_nregs (hard_regno
, mode
))
1855 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1857 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1859 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1860 mode
, hard_regno
)))))
1862 /* The class will be defined later in curr_insn_transform. */
1863 enum reg_class rclass
1864 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1866 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1868 TRUE
, "paradoxical subreg", &new_reg
))
1871 bool insert_before
, insert_after
;
1873 PUT_MODE (new_reg
, mode
);
1874 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1875 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1877 insert_before
= (type
!= OP_OUT
);
1878 insert_after
= (type
!= OP_IN
);
1879 insert_move_for_subreg (insert_before
? &before
: NULL
,
1880 insert_after
? &after
: NULL
,
1883 SUBREG_REG (operand
) = new_reg
;
1884 lra_process_new_insns (curr_insn
, before
, after
,
1885 "Inserting paradoxical subreg reload");
1891 /* Return TRUE if X refers for a hard register from SET. */
1893 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1895 int i
, j
, x_hard_regno
;
1902 code
= GET_CODE (x
);
1903 mode
= GET_MODE (x
);
1907 /* For all SUBREGs we want to check whether the full multi-register
1908 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1909 the inner register, for paradoxical SUBREGs this means the
1910 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1911 fine. Use the wider mode for all cases. */
1912 rtx subreg
= SUBREG_REG (x
);
1913 mode
= wider_subreg_mode (x
);
1914 if (mode
== GET_MODE (subreg
))
1917 code
= GET_CODE (x
);
1921 if (REG_P (x
) || SUBREG_P (x
))
1923 x_hard_regno
= get_hard_regno (x
, true);
1924 return (x_hard_regno
>= 0
1925 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1927 fmt
= GET_RTX_FORMAT (code
);
1928 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1932 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1935 else if (fmt
[i
] == 'E')
1937 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1938 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1945 /* Return true if OP is a spilled pseudo. */
1947 spilled_pseudo_p (rtx op
)
1950 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1953 /* Return true if X is a general constant. */
1955 general_constant_p (rtx x
)
1957 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1961 reg_in_class_p (rtx reg
, enum reg_class cl
)
1964 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1965 return in_class_p (reg
, cl
, NULL
);
1968 /* Return true if SET of RCLASS contains no hard regs which can be
1971 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1977 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1978 temp
= set
& ~lra_no_alloc_regs
;
1979 return (hard_reg_set_subset_p
1980 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1984 /* Used to check validity info about small class input operands. It
1985 should be incremented at start of processing an insn
1987 static unsigned int curr_small_class_check
= 0;
1989 /* Update number of used inputs of class OP_CLASS for operand NOP
1990 of alternative NALT. Return true if we have more such class operands
1991 than the number of available regs. */
1993 update_and_check_small_class_inputs (int nop
, int nalt
,
1994 enum reg_class op_class
)
1996 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1997 static int small_class_input_nums
[LIM_REG_CLASSES
];
1999 if (SMALL_REGISTER_CLASS_P (op_class
)
2000 /* We are interesting in classes became small because of fixing
2001 some hard regs, e.g. by an user through GCC options. */
2002 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
2004 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
2005 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
2007 if (small_class_check
[op_class
] == curr_small_class_check
)
2008 small_class_input_nums
[op_class
]++;
2011 small_class_check
[op_class
] = curr_small_class_check
;
2012 small_class_input_nums
[op_class
] = 1;
2014 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
2020 /* Major function to choose the current insn alternative and what
2021 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2022 negative we should consider only this alternative. Return false if
2023 we cannot choose the alternative or find how to reload the
2026 process_alt_operands (int only_alternative
)
2029 int nop
, overall
, nalt
;
2030 int n_alternatives
= curr_static_id
->n_alternatives
;
2031 int n_operands
= curr_static_id
->n_operands
;
2032 /* LOSERS counts the operands that don't fit this alternative and
2033 would require loading. */
2036 /* REJECT is a count of how undesirable this alternative says it is
2037 if any reloading is required. If the alternative matches exactly
2038 then REJECT is ignored, but otherwise it gets this much counted
2039 against it in addition to the reloading needed. */
2041 /* This is defined by '!' or '?' alternative constraint and added to
2042 reject. But in some cases it can be ignored. */
2045 /* The number of elements in the following array. */
2046 int early_clobbered_regs_num
;
2047 /* Numbers of operands which are early clobber registers. */
2048 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
2049 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
2050 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
2051 HARD_REG_SET curr_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
2052 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
2053 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
2054 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
2055 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
2056 /* The number of elements in the following array. */
2057 int curr_alt_dont_inherit_ops_num
;
2058 /* Numbers of operands whose reload pseudos should not be inherited. */
2059 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
2061 /* The register when the operand is a subreg of register, otherwise the
2063 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
2064 /* The register if the operand is a register or subreg of register,
2066 rtx operand_reg
[MAX_RECOG_OPERANDS
];
2067 int hard_regno
[MAX_RECOG_OPERANDS
];
2068 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
2069 int reload_nregs
, reload_sum
;
2073 /* Calculate some data common for all alternatives to speed up the
2075 for (nop
= 0; nop
< n_operands
; nop
++)
2079 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
2080 /* The real hard regno of the operand after the allocation. */
2081 hard_regno
[nop
] = get_hard_regno (op
, true);
2083 operand_reg
[nop
] = reg
= op
;
2084 biggest_mode
[nop
] = GET_MODE (op
);
2085 if (GET_CODE (op
) == SUBREG
)
2087 biggest_mode
[nop
] = wider_subreg_mode (op
);
2088 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
2091 operand_reg
[nop
] = NULL_RTX
;
2092 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2093 || ((int) REGNO (reg
)
2094 == lra_get_elimination_hard_regno (REGNO (reg
))))
2095 no_subreg_reg_operand
[nop
] = reg
;
2097 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
2098 /* Just use natural mode for elimination result. It should
2099 be enough for extra constraints hooks. */
2100 = regno_reg_rtx
[hard_regno
[nop
]];
2103 /* The constraints are made of several alternatives. Each operand's
2104 constraint looks like foo,bar,... with commas separating the
2105 alternatives. The first alternatives for all operands go
2106 together, the second alternatives go together, etc.
2108 First loop over alternatives. */
2109 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2110 if (only_alternative
>= 0)
2111 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2113 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2115 /* Loop over operands for one constraint alternative. */
2116 if (!TEST_BIT (preferred
, nalt
))
2119 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2120 curr_small_class_check
++;
2121 overall
= losers
= addr_losers
= 0;
2122 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2123 for (nop
= 0; nop
< n_operands
; nop
++)
2125 int inc
= (curr_static_id
2126 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2127 if (lra_dump_file
!= NULL
&& inc
!= 0)
2128 fprintf (lra_dump_file
,
2129 " Staticly defined alt reject+=%d\n", inc
);
2130 static_reject
+= inc
;
2131 matching_early_clobber
[nop
] = 0;
2133 reject
+= static_reject
;
2134 early_clobbered_regs_num
= 0;
2136 for (nop
= 0; nop
< n_operands
; nop
++)
2140 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2141 bool win
, did_match
, offmemok
, early_clobber_p
;
2142 /* false => this operand can be reloaded somehow for this
2145 /* true => this operand can be reloaded if the alternative
2148 /* True if a constant forced into memory would be OK for
2151 enum reg_class this_alternative
, this_costly_alternative
;
2152 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2153 HARD_REG_SET this_alternative_exclude_start_hard_regs
;
2154 bool this_alternative_match_win
, this_alternative_win
;
2155 bool this_alternative_offmemok
;
2158 enum constraint_num cn
;
2160 opalt_num
= nalt
* n_operands
+ nop
;
2161 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2163 /* Fast track for no constraints at all. */
2164 curr_alt
[nop
] = NO_REGS
;
2165 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2166 curr_alt_win
[nop
] = true;
2167 curr_alt_match_win
[nop
] = false;
2168 curr_alt_offmemok
[nop
] = false;
2169 curr_alt_matches
[nop
] = -1;
2173 op
= no_subreg_reg_operand
[nop
];
2174 mode
= curr_operand_mode
[nop
];
2176 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2179 early_clobber_p
= false;
2180 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2182 this_costly_alternative
= this_alternative
= NO_REGS
;
2183 /* We update set of possible hard regs besides its class
2184 because reg class might be inaccurate. For example,
2185 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2186 is translated in HI_REGS because classes are merged by
2187 pairs and there is no accurate intermediate class. */
2188 CLEAR_HARD_REG_SET (this_alternative_set
);
2189 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2190 CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs
);
2191 this_alternative_win
= false;
2192 this_alternative_match_win
= false;
2193 this_alternative_offmemok
= false;
2194 this_alternative_matches
= -1;
2196 /* An empty constraint should be excluded by the fast
2198 lra_assert (*p
!= 0 && *p
!= ',');
2201 /* Scan this alternative's specs for this operand; set WIN
2202 if the operand fits any letter in this alternative.
2203 Otherwise, clear BADOP if this operand could fit some
2204 letter after reloads, or set WINREG if this operand could
2205 fit after reloads provided the constraint allows some
2210 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2220 early_clobber_p
= true;
2224 op_reject
+= LRA_MAX_REJECT
;
2227 op_reject
+= LRA_LOSER_COST_FACTOR
;
2231 /* Ignore rest of this alternative. */
2235 case '0': case '1': case '2': case '3': case '4':
2236 case '5': case '6': case '7': case '8': case '9':
2241 m
= strtoul (p
, &end
, 10);
2244 lra_assert (nop
> m
);
2246 /* Reject matches if we don't know which operand is
2247 bigger. This situation would arguably be a bug in
2248 an .md pattern, but could also occur in a user asm. */
2249 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2250 GET_MODE_SIZE (biggest_mode
[nop
])))
2253 /* Don't match wrong asm insn operands for proper
2254 diagnostic later. */
2255 if (INSN_CODE (curr_insn
) < 0
2256 && (curr_operand_mode
[m
] == BLKmode
2257 || curr_operand_mode
[nop
] == BLKmode
)
2258 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2261 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2262 /* We are supposed to match a previous operand.
2263 If we do, we win if that one did. If we do
2264 not, count both of the operands as losers.
2265 (This is too conservative, since most of the
2266 time only a single reload insn will be needed
2267 to make the two operands win. As a result,
2268 this alternative may be rejected when it is
2269 actually desirable.) */
2271 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2272 *curr_id
->operand_loc
[m
], m_hregno
))
2274 /* We should reject matching of an early
2275 clobber operand if the matching operand is
2276 not dying in the insn. */
2277 if (!TEST_BIT (curr_static_id
->operand
[m
]
2278 .early_clobber_alts
, nalt
)
2279 || operand_reg
[nop
] == NULL_RTX
2280 || (find_regno_note (curr_insn
, REG_DEAD
,
2282 || REGNO (op
) == REGNO (operand_reg
[m
])))
2287 /* If we are matching a non-offsettable
2288 address where an offsettable address was
2289 expected, then we must reject this
2290 combination, because we can't reload
2292 if (curr_alt_offmemok
[m
]
2293 && MEM_P (*curr_id
->operand_loc
[m
])
2294 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2299 /* If the operands do not match and one
2300 operand is INOUT, we can not match them.
2301 Try other possibilities, e.g. other
2302 alternatives or commutative operand
2304 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2305 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2307 /* Operands don't match. If the operands are
2308 different user defined explicit hard
2309 registers, then we cannot make them match
2310 when one is early clobber operand. */
2311 if ((REG_P (*curr_id
->operand_loc
[nop
])
2312 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2313 && (REG_P (*curr_id
->operand_loc
[m
])
2314 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2316 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2317 if (SUBREG_P (nop_reg
))
2318 nop_reg
= SUBREG_REG (nop_reg
);
2319 rtx m_reg
= *curr_id
->operand_loc
[m
];
2320 if (SUBREG_P (m_reg
))
2321 m_reg
= SUBREG_REG (m_reg
);
2324 && HARD_REGISTER_P (nop_reg
)
2325 && REG_USERVAR_P (nop_reg
)
2327 && HARD_REGISTER_P (m_reg
)
2328 && REG_USERVAR_P (m_reg
))
2332 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2333 if (m
== early_clobbered_nops
[i
])
2335 if (i
< early_clobbered_regs_num
2340 /* Both operands must allow a reload register,
2341 otherwise we cannot make them match. */
2342 if (curr_alt
[m
] == NO_REGS
)
2344 /* Retroactively mark the operand we had to
2345 match as a loser, if it wasn't already and
2346 it wasn't matched to a register constraint
2347 (e.g it might be matched by memory). */
2349 && (operand_reg
[m
] == NULL_RTX
2350 || hard_regno
[m
] < 0))
2354 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2355 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2358 /* Prefer matching earlyclobber alternative as
2359 it results in less hard regs required for
2360 the insn than a non-matching earlyclobber
2362 if (TEST_BIT (curr_static_id
->operand
[m
]
2363 .early_clobber_alts
, nalt
))
2365 if (lra_dump_file
!= NULL
)
2368 " %d Matching earlyclobber alt:"
2371 if (!matching_early_clobber
[m
])
2374 matching_early_clobber
[m
] = 1;
2377 /* Otherwise we prefer no matching
2378 alternatives because it gives more freedom
2380 else if (operand_reg
[nop
] == NULL_RTX
2381 || (find_regno_note (curr_insn
, REG_DEAD
,
2382 REGNO (operand_reg
[nop
]))
2385 if (lra_dump_file
!= NULL
)
2388 " %d Matching alt: reject+=2\n",
2393 /* If we have to reload this operand and some
2394 previous operand also had to match the same
2395 thing as this operand, we don't know how to do
2397 if (!match_p
|| !curr_alt_win
[m
])
2399 for (i
= 0; i
< nop
; i
++)
2400 if (curr_alt_matches
[i
] == m
)
2408 this_alternative_matches
= m
;
2409 /* This can be fixed with reloads if the operand
2410 we are supposed to match can be fixed with
2413 this_alternative
= curr_alt
[m
];
2414 this_alternative_set
= curr_alt_set
[m
];
2415 this_alternative_exclude_start_hard_regs
2416 = curr_alt_exclude_start_hard_regs
[m
];
2417 winreg
= this_alternative
!= NO_REGS
;
2423 || general_constant_p (op
)
2424 || spilled_pseudo_p (op
))
2430 cn
= lookup_constraint (p
);
2431 switch (get_constraint_type (cn
))
2434 cl
= reg_class_for_constraint (cn
);
2440 if (CONST_INT_P (op
)
2441 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2446 case CT_RELAXED_MEMORY
:
2448 && satisfies_memory_constraint_p (op
, cn
))
2450 else if (spilled_pseudo_p (op
))
2453 /* If we didn't already win, we can reload constants
2454 via force_const_mem or put the pseudo value into
2455 memory, or make other memory by reloading the
2456 address like for 'o'. */
2457 if (CONST_POOL_OK_P (mode
, op
)
2458 || MEM_P (op
) || REG_P (op
)
2459 /* We can restore the equiv insn by a
2461 || equiv_substition_p
[nop
])
2468 /* An asm operand with an address constraint
2469 that doesn't satisfy address_operand has
2470 is_address cleared, so that we don't try to
2471 make a non-address fit. */
2472 if (!curr_static_id
->operand
[nop
].is_address
)
2474 /* If we didn't already win, we can reload the address
2475 into a base register. */
2476 if (satisfies_address_constraint_p (op
, cn
))
2478 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2484 if (constraint_satisfied_p (op
, cn
))
2488 case CT_SPECIAL_MEMORY
:
2489 if (satisfies_memory_constraint_p (op
, cn
))
2491 else if (spilled_pseudo_p (op
))
2498 if (mode
== BLKmode
)
2500 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2501 if (hard_reg_set_subset_p (this_alternative_set
,
2502 reg_class_contents
[cl
]))
2503 this_alternative_exclude_start_hard_regs
2504 = ira_exclude_class_mode_regs
[cl
][mode
];
2505 else if (!hard_reg_set_subset_p (reg_class_contents
[cl
],
2506 this_alternative_set
))
2507 this_alternative_exclude_start_hard_regs
2508 |= ira_exclude_class_mode_regs
[cl
][mode
];
2509 this_alternative_set
|= reg_class_contents
[cl
];
2512 this_costly_alternative
2513 = reg_class_subunion
[this_costly_alternative
][cl
];
2514 this_costly_alternative_set
|= reg_class_contents
[cl
];
2519 if (hard_regno
[nop
] >= 0
2520 && in_hard_reg_set_p (this_alternative_set
,
2521 mode
, hard_regno
[nop
])
2522 && !TEST_HARD_REG_BIT
2523 (this_alternative_exclude_start_hard_regs
,
2526 else if (hard_regno
[nop
] < 0
2527 && in_class_p (op
, this_alternative
, NULL
))
2532 if (c
!= ' ' && c
!= '\t')
2533 costly_p
= c
== '*';
2535 while ((p
+= len
), c
);
2537 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2538 && ira_former_scratch_p (REGNO (operand_reg
[nop
])));
2539 /* Record which operands fit this alternative. */
2542 this_alternative_win
= true;
2543 if (operand_reg
[nop
] != NULL_RTX
)
2545 if (hard_regno
[nop
] >= 0)
2547 if (in_hard_reg_set_p (this_costly_alternative_set
,
2548 mode
, hard_regno
[nop
]))
2550 if (lra_dump_file
!= NULL
)
2551 fprintf (lra_dump_file
,
2552 " %d Costly set: reject++\n",
2559 /* Prefer won reg to spilled pseudo under other
2560 equal conditions for possibe inheritance. */
2563 if (lra_dump_file
!= NULL
)
2566 " %d Non pseudo reload: reject++\n",
2570 if (in_class_p (operand_reg
[nop
],
2571 this_costly_alternative
, NULL
))
2573 if (lra_dump_file
!= NULL
)
2576 " %d Non pseudo costly reload:"
2582 /* We simulate the behavior of old reload here.
2583 Although scratches need hard registers and it
2584 might result in spilling other pseudos, no reload
2585 insns are generated for the scratches. So it
2586 might cost something but probably less than old
2587 reload pass believes. */
2590 if (lra_dump_file
!= NULL
)
2591 fprintf (lra_dump_file
,
2592 " %d Scratch win: reject+=2\n",
2599 this_alternative_match_win
= true;
2602 int const_to_mem
= 0;
2605 reject
+= op_reject
;
2606 /* Never do output reload of stack pointer. It makes
2607 impossible to do elimination when SP is changed in
2609 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2610 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2613 /* If this alternative asks for a specific reg class, see if there
2614 is at least one allocatable register in that class. */
2616 = (this_alternative
== NO_REGS
2617 || (hard_reg_set_subset_p
2618 (reg_class_contents
[this_alternative
],
2619 lra_no_alloc_regs
)));
2621 /* For asms, verify that the class for this alternative is possible
2622 for the mode that is specified. */
2623 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2626 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2627 if (targetm
.hard_regno_mode_ok (i
, mode
)
2628 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2631 if (i
== FIRST_PSEUDO_REGISTER
)
2635 /* If this operand accepts a register, and if the
2636 register class has at least one allocatable register,
2637 then this operand can be reloaded. */
2638 if (winreg
&& !no_regs_p
)
2643 if (lra_dump_file
!= NULL
)
2644 fprintf (lra_dump_file
,
2645 " alt=%d: Bad operand -- refuse\n",
2650 if (this_alternative
!= NO_REGS
)
2652 HARD_REG_SET available_regs
2653 = (reg_class_contents
[this_alternative
]
2654 & ~((ira_prohibited_class_mode_regs
2655 [this_alternative
][mode
])
2656 | lra_no_alloc_regs
));
2657 if (hard_reg_set_empty_p (available_regs
))
2659 /* There are no hard regs holding a value of given
2663 this_alternative
= NO_REGS
;
2664 if (lra_dump_file
!= NULL
)
2665 fprintf (lra_dump_file
,
2666 " %d Using memory because of"
2667 " a bad mode: reject+=2\n",
2673 if (lra_dump_file
!= NULL
)
2674 fprintf (lra_dump_file
,
2675 " alt=%d: Wrong mode -- refuse\n",
2682 /* If not assigned pseudo has a class which a subset of
2683 required reg class, it is a less costly alternative
2684 as the pseudo still can get a hard reg of necessary
2686 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2687 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2688 && ira_class_subset_p
[this_alternative
][cl
])
2690 if (lra_dump_file
!= NULL
)
2693 " %d Super set class reg: reject-=3\n", nop
);
2697 this_alternative_offmemok
= offmemok
;
2698 if (this_costly_alternative
!= NO_REGS
)
2700 if (lra_dump_file
!= NULL
)
2701 fprintf (lra_dump_file
,
2702 " %d Costly loser: reject++\n", nop
);
2705 /* If the operand is dying, has a matching constraint,
2706 and satisfies constraints of the matched operand
2707 which failed to satisfy the own constraints, most probably
2708 the reload for this operand will be gone. */
2709 if (this_alternative_matches
>= 0
2710 && !curr_alt_win
[this_alternative_matches
]
2712 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2713 && (hard_regno
[nop
] >= 0
2714 ? in_hard_reg_set_p (this_alternative_set
,
2715 mode
, hard_regno
[nop
])
2716 : in_class_p (op
, this_alternative
, NULL
)))
2718 if (lra_dump_file
!= NULL
)
2721 " %d Dying matched operand reload: reject++\n",
2727 /* Strict_low_part requires to reload the register
2728 not the sub-register. In this case we should
2729 check that a final reload hard reg can hold the
2731 if (curr_static_id
->operand
[nop
].strict_low
2733 && hard_regno
[nop
] < 0
2734 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2735 && ira_class_hard_regs_num
[this_alternative
] > 0
2736 && (!targetm
.hard_regno_mode_ok
2737 (ira_class_hard_regs
[this_alternative
][0],
2738 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2740 if (lra_dump_file
!= NULL
)
2743 " alt=%d: Strict low subreg reload -- refuse\n",
2749 if (operand_reg
[nop
] != NULL_RTX
2750 /* Output operands and matched input operands are
2751 not inherited. The following conditions do not
2752 exactly describe the previous statement but they
2753 are pretty close. */
2754 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2755 && (this_alternative_matches
< 0
2756 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2758 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2762 /* The value of reload_sum has sense only if we
2763 process insns in their order. It happens only on
2764 the first constraints sub-pass when we do most of
2766 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2767 reload_sum
+= last_reload
- bb_reload_num
;
2769 /* If this is a constant that is reloaded into the
2770 desired class by copying it to memory first, count
2771 that as another reload. This is consistent with
2772 other code and is required to avoid choosing another
2773 alternative when the constant is moved into memory.
2774 Note that the test here is precisely the same as in
2775 the code below that calls force_const_mem. */
2776 if (CONST_POOL_OK_P (mode
, op
)
2777 && ((targetm
.preferred_reload_class
2778 (op
, this_alternative
) == NO_REGS
)
2779 || no_input_reloads_p
))
2786 /* Alternative loses if it requires a type of reload not
2787 permitted for this insn. We can always reload
2788 objects with a REG_UNUSED note. */
2789 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2790 && no_output_reloads_p
2791 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2792 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2793 && no_input_reloads_p
&& ! const_to_mem
)
2794 || (this_alternative_matches
>= 0
2795 && (no_input_reloads_p
2796 || (no_output_reloads_p
2797 && (curr_static_id
->operand
2798 [this_alternative_matches
].type
!= OP_IN
)
2799 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2800 no_subreg_reg_operand
2801 [this_alternative_matches
])))))
2803 if (lra_dump_file
!= NULL
)
2806 " alt=%d: No input/output reload -- refuse\n",
2811 /* Alternative loses if it required class pseudo cannot
2812 hold value of required mode. Such insns can be
2813 described by insn definitions with mode iterators. */
2814 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2815 && ! hard_reg_set_empty_p (this_alternative_set
)
2816 /* It is common practice for constraints to use a
2817 class which does not have actually enough regs to
2818 hold the value (e.g. x86 AREG for mode requiring
2819 more one general reg). Therefore we have 2
2820 conditions to check that the reload pseudo cannot
2821 hold the mode value. */
2822 && (!targetm
.hard_regno_mode_ok
2823 (ira_class_hard_regs
[this_alternative
][0],
2824 GET_MODE (*curr_id
->operand_loc
[nop
])))
2825 /* The above condition is not enough as the first
2826 reg in ira_class_hard_regs can be not aligned for
2827 multi-words mode values. */
2828 && (prohibited_class_reg_set_mode_p
2829 (this_alternative
, this_alternative_set
,
2830 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2832 if (lra_dump_file
!= NULL
)
2833 fprintf (lra_dump_file
,
2834 " alt=%d: reload pseudo for op %d "
2835 "cannot hold the mode value -- refuse\n",
2840 /* Check strong discouragement of reload of non-constant
2841 into class THIS_ALTERNATIVE. */
2842 if (! CONSTANT_P (op
) && ! no_regs_p
2843 && (targetm
.preferred_reload_class
2844 (op
, this_alternative
) == NO_REGS
2845 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2846 && (targetm
.preferred_output_reload_class
2847 (op
, this_alternative
) == NO_REGS
))))
2849 if (offmemok
&& REG_P (op
))
2851 if (lra_dump_file
!= NULL
)
2854 " %d Spill pseudo into memory: reject+=3\n",
2860 if (lra_dump_file
!= NULL
)
2863 " %d Non-prefered reload: reject+=%d\n",
2864 nop
, LRA_MAX_REJECT
);
2865 reject
+= LRA_MAX_REJECT
;
2869 if (! (MEM_P (op
) && offmemok
)
2870 && ! (const_to_mem
&& constmemok
))
2872 /* We prefer to reload pseudos over reloading other
2873 things, since such reloads may be able to be
2874 eliminated later. So bump REJECT in other cases.
2875 Don't do this in the case where we are forcing a
2876 constant into memory and it will then win since
2877 we don't want to have a different alternative
2879 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2881 if (lra_dump_file
!= NULL
)
2884 " %d Non-pseudo reload: reject+=2\n",
2891 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2893 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2895 if (lra_dump_file
!= NULL
)
2898 " %d Small class reload: reject+=%d\n",
2899 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2900 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2904 /* We are trying to spill pseudo into memory. It is
2905 usually more costly than moving to a hard register
2906 although it might takes the same number of
2909 Non-pseudo spill may happen also. Suppose a target allows both
2910 register and memory in the operand constraint alternatives,
2911 then it's typical that an eliminable register has a substition
2912 of "base + offset" which can either be reloaded by a simple
2913 "new_reg <= base + offset" which will match the register
2914 constraint, or a similar reg addition followed by further spill
2915 to and reload from memory which will match the memory
2916 constraint, but this memory spill will be much more costly
2919 Code below increases the reject for both pseudo and non-pseudo
2922 && !(MEM_P (op
) && offmemok
)
2923 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2925 if (lra_dump_file
!= NULL
)
2928 " %d Spill %spseudo into memory: reject+=3\n",
2929 nop
, REG_P (op
) ? "" : "Non-");
2931 if (VECTOR_MODE_P (mode
))
2933 /* Spilling vectors into memory is usually more
2934 costly as they contain big values. */
2935 if (lra_dump_file
!= NULL
)
2938 " %d Spill vector pseudo: reject+=2\n",
2944 /* When we use an operand requiring memory in given
2945 alternative, the insn should write *and* read the
2946 value to/from memory it is costly in comparison with
2947 an insn alternative which does not use memory
2948 (e.g. register or immediate operand). We exclude
2949 memory operand for such case as we can satisfy the
2950 memory constraints by reloading address. */
2951 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2953 if (lra_dump_file
!= NULL
)
2956 " Using memory insn operand %d: reject+=3\n",
2961 /* If reload requires moving value through secondary
2962 memory, it will need one more insn at least. */
2963 if (this_alternative
!= NO_REGS
2964 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2965 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2966 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2968 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2969 && (targetm
.secondary_memory_needed
2970 (GET_MODE (op
), this_alternative
, cl
)))))
2973 if (MEM_P (op
) && offmemok
)
2977 /* Input reloads can be inherited more often than
2978 output reloads can be removed, so penalize output
2980 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2982 if (lra_dump_file
!= NULL
)
2985 " %d Non input pseudo reload: reject++\n",
2990 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2992 if (lra_dump_file
!= NULL
)
2995 " %d Input/Output reload: reject+=%d\n",
2996 nop
, LRA_LOSER_COST_FACTOR
);
2997 reject
+= LRA_LOSER_COST_FACTOR
;
3002 if (early_clobber_p
&& ! scratch_p
)
3004 if (lra_dump_file
!= NULL
)
3005 fprintf (lra_dump_file
,
3006 " %d Early clobber: reject++\n", nop
);
3009 /* ??? We check early clobbers after processing all operands
3010 (see loop below) and there we update the costs more.
3011 Should we update the cost (may be approximately) here
3012 because of early clobber register reloads or it is a rare
3013 or non-important thing to be worth to do it. */
3014 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
3015 - (addr_losers
== losers
? static_reject
: 0));
3016 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
3018 if (lra_dump_file
!= NULL
)
3019 fprintf (lra_dump_file
,
3020 " alt=%d,overall=%d,losers=%d -- refuse\n",
3021 nalt
, overall
, losers
);
3025 if (update_and_check_small_class_inputs (nop
, nalt
,
3028 if (lra_dump_file
!= NULL
)
3029 fprintf (lra_dump_file
,
3030 " alt=%d, not enough small class regs -- refuse\n",
3034 curr_alt
[nop
] = this_alternative
;
3035 curr_alt_set
[nop
] = this_alternative_set
;
3036 curr_alt_exclude_start_hard_regs
[nop
]
3037 = this_alternative_exclude_start_hard_regs
;
3038 curr_alt_win
[nop
] = this_alternative_win
;
3039 curr_alt_match_win
[nop
] = this_alternative_match_win
;
3040 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
3041 curr_alt_matches
[nop
] = this_alternative_matches
;
3043 if (this_alternative_matches
>= 0
3044 && !did_match
&& !this_alternative_win
)
3045 curr_alt_win
[this_alternative_matches
] = false;
3047 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
3048 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
3051 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
3052 /* Prevent processing non-move insns. */
3053 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
3054 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
3055 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
3056 && REG_P (no_subreg_reg_operand
[0])
3057 && REG_P (no_subreg_reg_operand
[1])
3058 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3059 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
3060 || (! curr_alt_win
[0] && curr_alt_win
[1]
3061 && REG_P (no_subreg_reg_operand
[1])
3062 /* Check that we reload memory not the memory
3064 && ! (curr_alt_offmemok
[0]
3065 && MEM_P (no_subreg_reg_operand
[0]))
3066 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
3067 || (curr_alt_win
[0] && ! curr_alt_win
[1]
3068 && REG_P (no_subreg_reg_operand
[0])
3069 /* Check that we reload memory not the memory
3071 && ! (curr_alt_offmemok
[1]
3072 && MEM_P (no_subreg_reg_operand
[1]))
3073 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3074 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
3075 no_subreg_reg_operand
[1])
3076 || (targetm
.preferred_reload_class
3077 (no_subreg_reg_operand
[1],
3078 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
3079 /* If it is a result of recent elimination in move
3080 insn we can transform it into an add still by
3081 using this alternative. */
3082 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
3083 /* Likewise if the source has been replaced with an
3084 equivalent value. This only happens once -- the reload
3085 will use the equivalent value instead of the register it
3086 replaces -- so there should be no danger of cycling. */
3087 && !equiv_substition_p
[1])))
3089 /* We have a move insn and a new reload insn will be similar
3090 to the current insn. We should avoid such situation as
3091 it results in LRA cycling. */
3092 if (lra_dump_file
!= NULL
)
3093 fprintf (lra_dump_file
,
3094 " Cycle danger: overall += LRA_MAX_REJECT\n");
3095 overall
+= LRA_MAX_REJECT
;
3098 curr_alt_dont_inherit_ops_num
= 0;
3099 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
3101 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
3102 HARD_REG_SET temp_set
;
3104 i
= early_clobbered_nops
[nop
];
3105 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
3106 || hard_regno
[i
] < 0)
3108 lra_assert (operand_reg
[i
] != NULL_RTX
);
3109 clobbered_hard_regno
= hard_regno
[i
];
3110 CLEAR_HARD_REG_SET (temp_set
);
3111 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
3112 first_conflict_j
= last_conflict_j
= -1;
3113 for (j
= 0; j
< n_operands
; j
++)
3115 /* We don't want process insides of match_operator and
3116 match_parallel because otherwise we would process
3117 their operands once again generating a wrong
3119 || curr_static_id
->operand
[j
].is_operator
)
3121 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3122 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3124 /* If we don't reload j-th operand, check conflicts. */
3125 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3126 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3128 if (first_conflict_j
< 0)
3129 first_conflict_j
= j
;
3130 last_conflict_j
= j
;
3131 /* Both the earlyclobber operand and conflicting operand
3132 cannot both be user defined hard registers. */
3133 if (HARD_REGISTER_P (operand_reg
[i
])
3134 && REG_USERVAR_P (operand_reg
[i
])
3135 && operand_reg
[j
] != NULL_RTX
3136 && HARD_REGISTER_P (operand_reg
[j
])
3137 && REG_USERVAR_P (operand_reg
[j
]))
3139 /* For asm, let curr_insn_transform diagnose it. */
3140 if (INSN_CODE (curr_insn
) < 0)
3142 fatal_insn ("unable to generate reloads for "
3143 "impossible constraints:", curr_insn
);
3146 if (last_conflict_j
< 0)
3149 /* If an earlyclobber operand conflicts with another non-matching
3150 operand (ie, they have been assigned the same hard register),
3151 then it is better to reload the other operand, as there may
3152 exist yet another operand with a matching constraint associated
3153 with the earlyclobber operand. However, if one of the operands
3154 is an explicit use of a hard register, then we must reload the
3155 other non-hard register operand. */
3156 if (HARD_REGISTER_P (operand_reg
[i
])
3157 || (first_conflict_j
== last_conflict_j
3158 && operand_reg
[last_conflict_j
] != NULL_RTX
3159 && !curr_alt_match_win
[last_conflict_j
]
3160 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3162 curr_alt_win
[last_conflict_j
] = false;
3163 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3166 if (lra_dump_file
!= NULL
)
3169 " %d Conflict early clobber reload: reject--\n",
3174 /* We need to reload early clobbered register and the
3175 matched registers. */
3176 for (j
= 0; j
< n_operands
; j
++)
3177 if (curr_alt_matches
[j
] == i
)
3179 curr_alt_match_win
[j
] = false;
3181 overall
+= LRA_LOSER_COST_FACTOR
;
3183 if (! curr_alt_match_win
[i
])
3184 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3187 /* Remember pseudos used for match reloads are never
3189 lra_assert (curr_alt_matches
[i
] >= 0);
3190 curr_alt_win
[curr_alt_matches
[i
]] = false;
3192 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3194 if (lra_dump_file
!= NULL
)
3197 " %d Matched conflict early clobber reloads: "
3201 /* Early clobber was already reflected in REJECT. */
3202 if (!matching_early_clobber
[i
])
3204 lra_assert (reject
> 0);
3206 matching_early_clobber
[i
] = 1;
3208 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3210 if (lra_dump_file
!= NULL
)
3211 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3212 nalt
, overall
, losers
, reload_nregs
);
3214 /* If this alternative can be made to work by reloading, and it
3215 needs less reloading than the others checked so far, record
3216 it as the chosen goal for reloading. */
3217 if ((best_losers
!= 0 && losers
== 0)
3218 || (((best_losers
== 0 && losers
== 0)
3219 || (best_losers
!= 0 && losers
!= 0))
3220 && (best_overall
> overall
3221 || (best_overall
== overall
3222 /* If the cost of the reloads is the same,
3223 prefer alternative which requires minimal
3224 number of reload regs. */
3225 && (reload_nregs
< best_reload_nregs
3226 || (reload_nregs
== best_reload_nregs
3227 && (best_reload_sum
< reload_sum
3228 || (best_reload_sum
== reload_sum
3229 && nalt
< goal_alt_number
))))))))
3231 for (nop
= 0; nop
< n_operands
; nop
++)
3233 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3234 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3235 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3236 goal_alt
[nop
] = curr_alt
[nop
];
3237 goal_alt_exclude_start_hard_regs
[nop
]
3238 = curr_alt_exclude_start_hard_regs
[nop
];
3239 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3241 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3242 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3243 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3244 goal_alt_swapped
= curr_swapped
;
3245 best_overall
= overall
;
3246 best_losers
= losers
;
3247 best_reload_nregs
= reload_nregs
;
3248 best_reload_sum
= reload_sum
;
3249 goal_alt_number
= nalt
;
3252 /* Everything is satisfied. Do not process alternatives
3261 /* Make reload base reg from address AD. */
3263 base_to_reg (struct address_info
*ad
)
3267 rtx new_inner
= NULL_RTX
;
3268 rtx new_reg
= NULL_RTX
;
3270 rtx_insn
*last_insn
= get_last_insn();
3272 lra_assert (ad
->disp
== ad
->disp_term
);
3273 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3274 get_index_code (ad
));
3275 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
, cl
, NULL
,
3277 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3278 ad
->disp_term
== NULL
3281 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3283 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3284 code
= recog_memoized (insn
);
3287 delete_insns_since (last_insn
);
3294 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3296 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3301 lra_assert (ad
->base
== ad
->base_term
);
3302 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3303 get_index_code (ad
));
3304 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
, cl
, NULL
,
3306 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3310 /* Make reload of index part of address AD. Return the new
3313 index_part_to_reg (struct address_info
*ad
)
3317 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3318 INDEX_REG_CLASS
, NULL
, "index term");
3319 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3320 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3324 /* Return true if we can add a displacement to address AD, even if that
3325 makes the address invalid. The fix-up code requires any new address
3326 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3328 can_add_disp_p (struct address_info
*ad
)
3330 return (!ad
->autoinc_p
3331 && ad
->segment
== NULL
3332 && ad
->base
== ad
->base_term
3333 && ad
->disp
== ad
->disp_term
);
3336 /* Make equiv substitution in address AD. Return true if a substitution
3339 equiv_address_substitution (struct address_info
*ad
)
3341 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3343 HOST_WIDE_INT scale
;
3346 base_term
= strip_subreg (ad
->base_term
);
3347 if (base_term
== NULL
)
3348 base_reg
= new_base_reg
= NULL_RTX
;
3351 base_reg
= *base_term
;
3352 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3354 index_term
= strip_subreg (ad
->index_term
);
3355 if (index_term
== NULL
)
3356 index_reg
= new_index_reg
= NULL_RTX
;
3359 index_reg
= *index_term
;
3360 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3362 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3366 if (lra_dump_file
!= NULL
)
3368 fprintf (lra_dump_file
, "Changing address in insn %d ",
3369 INSN_UID (curr_insn
));
3370 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3372 if (base_reg
!= new_base_reg
)
3375 if (REG_P (new_base_reg
))
3377 *base_term
= new_base_reg
;
3380 else if (GET_CODE (new_base_reg
) == PLUS
3381 && REG_P (XEXP (new_base_reg
, 0))
3382 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3383 && can_add_disp_p (ad
))
3386 *base_term
= XEXP (new_base_reg
, 0);
3389 if (ad
->base_term2
!= NULL
)
3390 *ad
->base_term2
= *ad
->base_term
;
3392 if (index_reg
!= new_index_reg
)
3395 if (REG_P (new_index_reg
))
3397 *index_term
= new_index_reg
;
3400 else if (GET_CODE (new_index_reg
) == PLUS
3401 && REG_P (XEXP (new_index_reg
, 0))
3402 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3403 && can_add_disp_p (ad
)
3404 && (scale
= get_index_scale (ad
)))
3406 disp
+= offset
* scale
;
3407 *index_term
= XEXP (new_index_reg
, 0);
3411 if (maybe_ne (disp
, 0))
3413 if (ad
->disp
!= NULL
)
3414 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3417 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3418 update_address (ad
);
3422 if (lra_dump_file
!= NULL
)
3425 fprintf (lra_dump_file
, " -- no change\n");
3428 fprintf (lra_dump_file
, " on equiv ");
3429 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3430 fprintf (lra_dump_file
, "\n");
3436 /* Skip all modifiers and whitespaces in constraint STR and return the
3439 skip_constraint_modifiers (const char *str
)
3444 case '+': case '&' : case '=': case '*': case ' ': case '\t':
3445 case '$': case '^' : case '%': case '?': case '!':
3447 default: return str
;
3451 /* Major function to make reloads for an address in operand NOP or
3452 check its correctness (If CHECK_ONLY_P is true). The supported
3455 1) an address that existed before LRA started, at which point it
3456 must have been valid. These addresses are subject to elimination
3457 and may have become invalid due to the elimination offset being out
3460 2) an address created by forcing a constant to memory
3461 (force_const_to_mem). The initial form of these addresses might
3462 not be valid, and it is this function's job to make them valid.
3464 3) a frame address formed from a register and a (possibly zero)
3465 constant offset. As above, these addresses might not be valid and
3466 this function must make them so.
3468 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3469 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3470 address. Return true for any RTL change.
3472 The function is a helper function which does not produce all
3473 transformations (when CHECK_ONLY_P is false) which can be
3474 necessary. It does just basic steps. To do all necessary
3475 transformations use function process_address. */
3477 process_address_1 (int nop
, bool check_only_p
,
3478 rtx_insn
**before
, rtx_insn
**after
)
3480 struct address_info ad
;
3482 HOST_WIDE_INT scale
;
3483 rtx op
= *curr_id
->operand_loc
[nop
];
3484 rtx mem
= extract_mem_from_operand (op
);
3485 const char *constraint
;
3486 enum constraint_num cn
;
3487 bool change_p
= false;
3490 && GET_MODE (mem
) == BLKmode
3491 && GET_CODE (XEXP (mem
, 0)) == SCRATCH
)
3495 = skip_constraint_modifiers (curr_static_id
->operand
[nop
].constraint
);
3496 if (IN_RANGE (constraint
[0], '0', '9'))
3499 unsigned long dup
= strtoul (constraint
, &end
, 10);
3501 = skip_constraint_modifiers (curr_static_id
->operand
[dup
].constraint
);
3503 cn
= lookup_constraint (*constraint
== '\0' ? "X" : constraint
);
3504 /* If we have several alternatives or/and several constraints in an
3505 alternative and we can not say at this stage what constraint will be used,
3506 use unknown constraint. The exception is an address constraint. If
3507 operand has one address constraint, probably all others constraints are
3509 if (constraint
[0] != '\0' && get_constraint_type (cn
) != CT_ADDRESS
3510 && *skip_constraint_modifiers (constraint
3511 + CONSTRAINT_LEN (constraint
[0],
3512 constraint
)) != '\0')
3513 cn
= CONSTRAINT__UNKNOWN
;
3514 if (insn_extra_address_constraint (cn
)
3515 /* When we find an asm operand with an address constraint that
3516 doesn't satisfy address_operand to begin with, we clear
3517 is_address, so that we don't try to make a non-address fit.
3518 If the asm statement got this far, it's because other
3519 constraints are available, and we'll use them, disregarding
3520 the unsatisfiable address ones. */
3521 && curr_static_id
->operand
[nop
].is_address
)
3522 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3523 /* Do not attempt to decompose arbitrary addresses generated by combine
3524 for asm operands with loose constraints, e.g 'X'.
3525 Need to extract memory from op for special memory constraint,
3526 i.e. bcst_mem_operand in i386 backend. */
3527 else if (MEM_P (mem
)
3528 && !(INSN_CODE (curr_insn
) < 0
3529 && get_constraint_type (cn
) == CT_FIXED_FORM
3530 && constraint_satisfied_p (op
, cn
)))
3531 decompose_mem_address (&ad
, mem
);
3532 else if (GET_CODE (op
) == SUBREG
3533 && MEM_P (SUBREG_REG (op
)))
3534 decompose_mem_address (&ad
, SUBREG_REG (op
));
3537 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3538 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3539 when INDEX_REG_CLASS is a single register class. */
3540 if (ad
.base_term
!= NULL
3541 && ad
.index_term
!= NULL
3542 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3543 && REG_P (*ad
.base_term
)
3544 && REG_P (*ad
.index_term
)
3545 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3546 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3548 std::swap (ad
.base
, ad
.index
);
3549 std::swap (ad
.base_term
, ad
.index_term
);
3552 change_p
= equiv_address_substitution (&ad
);
3553 if (ad
.base_term
!= NULL
3554 && (process_addr_reg
3555 (ad
.base_term
, check_only_p
, before
,
3557 && !(REG_P (*ad
.base_term
)
3558 && find_regno_note (curr_insn
, REG_DEAD
,
3559 REGNO (*ad
.base_term
)) != NULL_RTX
)
3561 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3562 get_index_code (&ad
)))))
3565 if (ad
.base_term2
!= NULL
)
3566 *ad
.base_term2
= *ad
.base_term
;
3568 if (ad
.index_term
!= NULL
3569 && process_addr_reg (ad
.index_term
, check_only_p
,
3570 before
, NULL
, INDEX_REG_CLASS
))
3573 /* Target hooks sometimes don't treat extra-constraint addresses as
3574 legitimate address_operands, so handle them specially. */
3575 if (insn_extra_address_constraint (cn
)
3576 && satisfies_address_constraint_p (&ad
, cn
))
3582 /* There are three cases where the shape of *AD.INNER may now be invalid:
3584 1) the original address was valid, but either elimination or
3585 equiv_address_substitution was applied and that made
3586 the address invalid.
3588 2) the address is an invalid symbolic address created by
3591 3) the address is a frame address with an invalid offset.
3593 4) the address is a frame address with an invalid base.
3595 All these cases involve a non-autoinc address, so there is no
3596 point revalidating other types. */
3597 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3600 /* Any index existed before LRA started, so we can assume that the
3601 presence and shape of the index is valid. */
3602 push_to_sequence (*before
);
3603 lra_assert (ad
.disp
== ad
.disp_term
);
3604 if (ad
.base
== NULL
)
3606 if (ad
.index
== NULL
)
3609 rtx_insn
*last
= get_last_insn ();
3611 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3613 rtx addr
= *ad
.inner
;
3615 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3618 /* addr => lo_sum (new_base, addr), case (2) above. */
3619 insn
= emit_insn (gen_rtx_SET
3621 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3622 code
= recog_memoized (insn
);
3625 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3626 if (!valid_address_p (op
, &ad
, cn
))
3628 /* Try to put lo_sum into register. */
3629 insn
= emit_insn (gen_rtx_SET
3631 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3632 code
= recog_memoized (insn
);
3635 *ad
.inner
= new_reg
;
3636 if (!valid_address_p (op
, &ad
, cn
))
3646 delete_insns_since (last
);
3651 /* addr => new_base, case (2) above. */
3652 lra_emit_move (new_reg
, addr
);
3654 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3656 insn
= NEXT_INSN (insn
))
3657 if (recog_memoized (insn
) < 0)
3659 if (insn
!= NULL_RTX
)
3661 /* Do nothing if we cannot generate right insns.
3662 This is analogous to reload pass behavior. */
3663 delete_insns_since (last
);
3667 *ad
.inner
= new_reg
;
3672 /* index * scale + disp => new base + index * scale,
3674 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3675 GET_CODE (*ad
.index
));
3677 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3678 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "disp");
3679 lra_emit_move (new_reg
, *ad
.disp
);
3680 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3681 new_reg
, *ad
.index
);
3684 else if (ad
.index
== NULL
)
3689 rtx_insn
*insns
, *last_insn
;
3690 /* Try to reload base into register only if the base is invalid
3691 for the address but with valid offset, case (4) above. */
3693 new_reg
= base_to_reg (&ad
);
3695 /* base + disp => new base, cases (1) and (3) above. */
3696 /* Another option would be to reload the displacement into an
3697 index register. However, postreload has code to optimize
3698 address reloads that have the same base and different
3699 displacements, so reloading into an index register would
3700 not necessarily be a win. */
3701 if (new_reg
== NULL_RTX
)
3703 /* See if the target can split the displacement into a
3704 legitimate new displacement from a local anchor. */
3705 gcc_assert (ad
.disp
== ad
.disp_term
);
3706 poly_int64 orig_offset
;
3707 rtx offset1
, offset2
;
3708 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3709 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3713 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3714 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3717 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3719 insns
= get_insns ();
3720 last_insn
= get_last_insn ();
3721 /* If we generated at least two insns, try last insn source as
3722 an address. If we succeed, we generate one less insn. */
3724 && last_insn
!= insns
3725 && (set
= single_set (last_insn
)) != NULL_RTX
3726 && GET_CODE (SET_SRC (set
)) == PLUS
3727 && REG_P (XEXP (SET_SRC (set
), 0))
3728 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3730 *ad
.inner
= SET_SRC (set
);
3731 if (valid_address_p (op
, &ad
, cn
))
3733 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3734 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3735 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3736 get_index_code (&ad
));
3737 regno
= REGNO (*ad
.base_term
);
3738 if (regno
>= FIRST_PSEUDO_REGISTER
3739 && cl
!= lra_get_allocno_class (regno
))
3740 lra_change_class (regno
, cl
, " Change to", true);
3741 new_reg
= SET_SRC (set
);
3742 delete_insns_since (PREV_INSN (last_insn
));
3747 *ad
.inner
= new_reg
;
3749 else if (ad
.disp_term
!= NULL
)
3751 /* base + scale * index + disp => new base + scale * index,
3753 gcc_assert (ad
.disp
== ad
.disp_term
);
3754 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3755 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3756 new_reg
, *ad
.index
);
3758 else if ((scale
= get_index_scale (&ad
)) == 1)
3760 /* The last transformation to one reg will be made in
3761 curr_insn_transform function. */
3765 else if (scale
!= 0)
3767 /* base + scale * index => base + new_reg,
3769 Index part of address may become invalid. For example, we
3770 changed pseudo on the equivalent memory and a subreg of the
3771 pseudo onto the memory of different mode for which the scale is
3773 new_reg
= index_part_to_reg (&ad
);
3774 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3775 *ad
.base_term
, new_reg
);
3779 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3781 rtx addr
= *ad
.inner
;
3783 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3784 /* addr => new_base. */
3785 lra_emit_move (new_reg
, addr
);
3786 *ad
.inner
= new_reg
;
3788 *before
= get_insns ();
3793 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3794 Use process_address_1 as a helper function. Return true for any
3797 If CHECK_ONLY_P is true, just check address correctness. Return
3798 false if the address correct. */
3800 process_address (int nop
, bool check_only_p
,
3801 rtx_insn
**before
, rtx_insn
**after
)
3805 while (process_address_1 (nop
, check_only_p
, before
, after
))
3814 /* Emit insns to reload VALUE into a new register. VALUE is an
3815 auto-increment or auto-decrement RTX whose operand is a register or
3816 memory location; so reloading involves incrementing that location.
3817 IN is either identical to VALUE, or some cheaper place to reload
3818 value being incremented/decremented from.
3820 INC_AMOUNT is the number to increment or decrement by (always
3821 positive and ignored for POST_MODIFY/PRE_MODIFY).
3823 Return pseudo containing the result. */
3825 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3827 /* REG or MEM to be copied and incremented. */
3828 rtx incloc
= XEXP (value
, 0);
3829 /* Nonzero if increment after copying. */
3830 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3831 || GET_CODE (value
) == POST_MODIFY
);
3836 rtx real_in
= in
== value
? incloc
: in
;
3840 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3842 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3843 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3844 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3845 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3846 inc
= XEXP (XEXP (value
, 1), 1);
3850 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3851 inc_amount
= -inc_amount
;
3853 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3856 if (! post
&& REG_P (incloc
))
3859 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
, NULL
,
3862 if (real_in
!= result
)
3864 /* First copy the location to the result register. */
3865 lra_assert (REG_P (result
));
3866 emit_insn (gen_move_insn (result
, real_in
));
3869 /* We suppose that there are insns to add/sub with the constant
3870 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3871 old reload worked with this assumption. If the assumption
3872 becomes wrong, we should use approach in function
3873 base_plus_disp_to_reg. */
3876 /* See if we can directly increment INCLOC. */
3877 last
= get_last_insn ();
3878 add_insn
= emit_insn (plus_p
3879 ? gen_add2_insn (incloc
, inc
)
3880 : gen_sub2_insn (incloc
, inc
));
3882 code
= recog_memoized (add_insn
);
3885 if (! post
&& result
!= incloc
)
3886 emit_insn (gen_move_insn (result
, incloc
));
3889 delete_insns_since (last
);
3892 /* If couldn't do the increment directly, must increment in RESULT.
3893 The way we do this depends on whether this is pre- or
3894 post-increment. For pre-increment, copy INCLOC to the reload
3895 register, increment it there, then save back. */
3898 if (real_in
!= result
)
3899 emit_insn (gen_move_insn (result
, real_in
));
3901 emit_insn (gen_add2_insn (result
, inc
));
3903 emit_insn (gen_sub2_insn (result
, inc
));
3904 if (result
!= incloc
)
3905 emit_insn (gen_move_insn (incloc
, result
));
3911 Because this might be a jump insn or a compare, and because
3912 RESULT may not be available after the insn in an input
3913 reload, we must do the incrementing before the insn being
3916 We have already copied IN to RESULT. Increment the copy in
3917 RESULT, save that back, then decrement RESULT so it has
3918 the original value. */
3920 emit_insn (gen_add2_insn (result
, inc
));
3922 emit_insn (gen_sub2_insn (result
, inc
));
3923 emit_insn (gen_move_insn (incloc
, result
));
3924 /* Restore non-modified value for the result. We prefer this
3925 way because it does not require an additional hard
3930 if (poly_int_rtx_p (inc
, &offset
))
3931 emit_insn (gen_add2_insn (result
,
3932 gen_int_mode (-offset
,
3933 GET_MODE (result
))));
3935 emit_insn (gen_sub2_insn (result
, inc
));
3938 emit_insn (gen_add2_insn (result
, inc
));
3943 /* Return true if the current move insn does not need processing as we
3944 already know that it satisfies its constraints. */
3946 simple_move_p (void)
3949 enum reg_class dclass
, sclass
;
3951 lra_assert (curr_insn_set
!= NULL_RTX
);
3952 dest
= SET_DEST (curr_insn_set
);
3953 src
= SET_SRC (curr_insn_set
);
3955 /* If the instruction has multiple sets we need to process it even if it
3956 is single_set. This can happen if one or more of the SETs are dead.
3958 if (multiple_sets (curr_insn
))
3961 return ((dclass
= get_op_class (dest
)) != NO_REGS
3962 && (sclass
= get_op_class (src
)) != NO_REGS
3963 /* The backend guarantees that register moves of cost 2
3964 never need reloads. */
3965 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3968 /* Swap operands NOP and NOP + 1. */
3970 swap_operands (int nop
)
3972 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3973 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3974 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3975 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3976 /* Swap the duplicates too. */
3977 lra_update_dup (curr_id
, nop
);
3978 lra_update_dup (curr_id
, nop
+ 1);
3981 /* Main entry point of the constraint code: search the body of the
3982 current insn to choose the best alternative. It is mimicking insn
3983 alternative cost calculation model of former reload pass. That is
3984 because machine descriptions were written to use this model. This
3985 model can be changed in future. Make commutative operand exchange
3988 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3989 constraints. Return true if any change happened during function
3992 If CHECK_ONLY_P is true then don't do any transformation. Just
3993 check that the insn satisfies all constraints. If the insn does
3994 not satisfy any constraint, return true. */
3996 curr_insn_transform (bool check_only_p
)
4003 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
4004 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
4005 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
4006 rtx_insn
*before
, *after
;
4008 /* Flag that the insn has been changed through a transformation. */
4012 int max_regno_before
;
4013 int reused_alternative_num
;
4015 curr_insn_set
= single_set (curr_insn
);
4016 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
4018 /* We assume that the corresponding insn alternative has no
4019 earlier clobbers. If it is not the case, don't define move
4020 cost equal to 2 for the corresponding register classes. */
4021 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
4025 no_input_reloads_p
= no_output_reloads_p
= false;
4026 goal_alt_number
= -1;
4027 change_p
= sec_mem_p
= false;
4029 /* CALL_INSNs are not allowed to have any output reloads. */
4030 if (CALL_P (curr_insn
))
4031 no_output_reloads_p
= true;
4033 n_operands
= curr_static_id
->n_operands
;
4034 n_alternatives
= curr_static_id
->n_alternatives
;
4036 /* Just return "no reloads" if insn has no operands with
4038 if (n_operands
== 0 || n_alternatives
== 0)
4041 max_regno_before
= max_reg_num ();
4043 for (i
= 0; i
< n_operands
; i
++)
4045 goal_alt_matched
[i
][0] = -1;
4046 goal_alt_matches
[i
] = -1;
4049 commutative
= curr_static_id
->commutative
;
4051 /* Now see what we need for pseudos that didn't get hard regs or got
4052 the wrong kind of hard reg. For this, we must consider all the
4053 operands together against the register constraints. */
4055 best_losers
= best_overall
= INT_MAX
;
4056 best_reload_sum
= 0;
4058 curr_swapped
= false;
4059 goal_alt_swapped
= false;
4062 /* Make equivalence substitution and memory subreg elimination
4063 before address processing because an address legitimacy can
4064 depend on memory mode. */
4065 for (i
= 0; i
< n_operands
; i
++)
4068 bool op_change_p
= false;
4070 if (curr_static_id
->operand
[i
].is_operator
)
4073 old
= op
= *curr_id
->operand_loc
[i
];
4074 if (GET_CODE (old
) == SUBREG
)
4075 old
= SUBREG_REG (old
);
4076 subst
= get_equiv_with_elimination (old
, curr_insn
);
4077 original_subreg_reg_mode
[i
] = VOIDmode
;
4078 equiv_substition_p
[i
] = false;
4081 equiv_substition_p
[i
] = true;
4082 subst
= copy_rtx (subst
);
4083 lra_assert (REG_P (old
));
4084 if (GET_CODE (op
) != SUBREG
)
4085 *curr_id
->operand_loc
[i
] = subst
;
4088 SUBREG_REG (op
) = subst
;
4089 if (GET_MODE (subst
) == VOIDmode
)
4090 original_subreg_reg_mode
[i
] = GET_MODE (old
);
4092 if (lra_dump_file
!= NULL
)
4094 fprintf (lra_dump_file
,
4095 "Changing pseudo %d in operand %i of insn %u on equiv ",
4096 REGNO (old
), i
, INSN_UID (curr_insn
));
4097 dump_value_slim (lra_dump_file
, subst
, 1);
4098 fprintf (lra_dump_file
, "\n");
4100 op_change_p
= change_p
= true;
4102 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
4105 lra_update_dup (curr_id
, i
);
4109 /* Reload address registers and displacements. We do it before
4110 finding an alternative because of memory constraints. */
4111 before
= after
= NULL
;
4112 for (i
= 0; i
< n_operands
; i
++)
4113 if (! curr_static_id
->operand
[i
].is_operator
4114 && process_address (i
, check_only_p
, &before
, &after
))
4119 lra_update_dup (curr_id
, i
);
4123 /* If we've changed the instruction then any alternative that
4124 we chose previously may no longer be valid. */
4125 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
4127 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
4128 && check_and_process_move (&change_p
, &sec_mem_p
))
4133 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
4134 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
4135 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
4136 reused_alternative_num
, INSN_UID (curr_insn
));
4138 if (process_alt_operands (reused_alternative_num
))
4142 return ! alt_p
|| best_losers
!= 0;
4144 /* If insn is commutative (it's safe to exchange a certain pair of
4145 operands) then we need to try each alternative twice, the second
4146 time matching those two operands as if we had exchanged them. To
4147 do this, really exchange them in operands.
4149 If we have just tried the alternatives the second time, return
4150 operands to normal and drop through. */
4152 if (reused_alternative_num
< 0 && commutative
>= 0)
4154 curr_swapped
= !curr_swapped
;
4157 swap_operands (commutative
);
4161 swap_operands (commutative
);
4164 if (! alt_p
&& ! sec_mem_p
)
4166 /* No alternative works with reloads?? */
4167 if (INSN_CODE (curr_insn
) >= 0)
4168 fatal_insn ("unable to generate reloads for:", curr_insn
);
4169 error_for_asm (curr_insn
,
4170 "inconsistent operand constraints in an %<asm%>");
4171 lra_asm_error_p
= true;
4172 if (! JUMP_P (curr_insn
))
4174 /* Avoid further trouble with this insn. Don't generate use
4175 pattern here as we could use the insn SP offset. */
4176 lra_set_insn_deleted (curr_insn
);
4180 lra_invalidate_insn_data (curr_insn
);
4181 ira_nullify_asm_goto (curr_insn
);
4182 lra_update_insn_regno_info (curr_insn
);
4187 /* If the best alternative is with operands 1 and 2 swapped, swap
4188 them. Update the operand numbers of any reloads already
4191 if (goal_alt_swapped
)
4193 if (lra_dump_file
!= NULL
)
4194 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4195 INSN_UID (curr_insn
));
4197 /* Swap the duplicates too. */
4198 swap_operands (commutative
);
4202 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4203 too conservatively. So we use the secondary memory only if there
4204 is no any alternative without reloads. */
4205 use_sec_mem_p
= false;
4207 use_sec_mem_p
= true;
4210 for (i
= 0; i
< n_operands
; i
++)
4211 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4213 use_sec_mem_p
= i
< n_operands
;
4218 int in
= -1, out
= -1;
4219 rtx new_reg
, src
, dest
, rld
;
4220 machine_mode sec_mode
, rld_mode
;
4222 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4223 dest
= SET_DEST (curr_insn_set
);
4224 src
= SET_SRC (curr_insn_set
);
4225 for (i
= 0; i
< n_operands
; i
++)
4226 if (*curr_id
->operand_loc
[i
] == dest
)
4228 else if (*curr_id
->operand_loc
[i
] == src
)
4230 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4231 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4232 out
= curr_static_id
->dup_num
[i
];
4233 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4234 in
= curr_static_id
->dup_num
[i
];
4235 lra_assert (out
>= 0 && in
>= 0
4236 && curr_static_id
->operand
[out
].type
== OP_OUT
4237 && curr_static_id
->operand
[in
].type
== OP_IN
);
4238 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4239 rld_mode
= GET_MODE (rld
);
4240 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4241 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
, NO_REGS
, NULL
,
4243 /* If the mode is changed, it should be wider. */
4244 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4245 if (sec_mode
!= rld_mode
)
4247 /* If the target says specifically to use another mode for
4248 secondary memory moves we cannot reuse the original
4250 after
= emit_spill_move (false, new_reg
, dest
);
4251 lra_process_new_insns (curr_insn
, NULL
, after
,
4252 "Inserting the sec. move");
4253 /* We may have non null BEFORE here (e.g. after address
4255 push_to_sequence (before
);
4256 before
= emit_spill_move (true, new_reg
, src
);
4258 before
= get_insns ();
4260 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4261 lra_set_insn_deleted (curr_insn
);
4263 else if (dest
== rld
)
4265 *curr_id
->operand_loc
[out
] = new_reg
;
4266 lra_update_dup (curr_id
, out
);
4267 after
= emit_spill_move (false, new_reg
, dest
);
4268 lra_process_new_insns (curr_insn
, NULL
, after
,
4269 "Inserting the sec. move");
4273 *curr_id
->operand_loc
[in
] = new_reg
;
4274 lra_update_dup (curr_id
, in
);
4275 /* See comments above. */
4276 push_to_sequence (before
);
4277 before
= emit_spill_move (true, new_reg
, src
);
4279 before
= get_insns ();
4281 lra_process_new_insns (curr_insn
, before
, NULL
,
4282 "Inserting the sec. move");
4284 lra_update_insn_regno_info (curr_insn
);
4288 lra_assert (goal_alt_number
>= 0);
4289 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4291 if (lra_dump_file
!= NULL
)
4295 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4296 goal_alt_number
, INSN_UID (curr_insn
));
4297 for (i
= 0; i
< n_operands
; i
++)
4299 p
= (curr_static_id
->operand_alternative
4300 [goal_alt_number
* n_operands
+ i
].constraint
);
4303 fprintf (lra_dump_file
, " (%d) ", i
);
4304 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4305 fputc (*p
, lra_dump_file
);
4307 if (INSN_CODE (curr_insn
) >= 0
4308 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4309 fprintf (lra_dump_file
, " {%s}", p
);
4310 if (maybe_ne (curr_id
->sp_offset
, 0))
4312 fprintf (lra_dump_file
, " (sp_off=");
4313 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4314 fprintf (lra_dump_file
, ")");
4316 fprintf (lra_dump_file
, "\n");
4319 /* Right now, for any pair of operands I and J that are required to
4320 match, with J < I, goal_alt_matches[I] is J. Add I to
4321 goal_alt_matched[J]. */
4323 for (i
= 0; i
< n_operands
; i
++)
4324 if ((j
= goal_alt_matches
[i
]) >= 0)
4326 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4328 /* We allow matching one output operand and several input
4331 || (curr_static_id
->operand
[j
].type
== OP_OUT
4332 && curr_static_id
->operand
[i
].type
== OP_IN
4333 && (curr_static_id
->operand
4334 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4335 goal_alt_matched
[j
][k
] = i
;
4336 goal_alt_matched
[j
][k
+ 1] = -1;
4339 for (i
= 0; i
< n_operands
; i
++)
4340 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4342 /* Any constants that aren't allowed and can't be reloaded into
4343 registers are here changed into memory references. */
4344 for (i
= 0; i
< n_operands
; i
++)
4345 if (goal_alt_win
[i
])
4348 enum reg_class new_class
;
4349 rtx reg
= *curr_id
->operand_loc
[i
];
4351 if (GET_CODE (reg
) == SUBREG
)
4352 reg
= SUBREG_REG (reg
);
4354 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4356 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4358 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4361 lra_change_class (regno
, new_class
, " Change to", true);
4367 const char *constraint
;
4369 rtx op
= *curr_id
->operand_loc
[i
];
4370 rtx subreg
= NULL_RTX
;
4371 machine_mode mode
= curr_operand_mode
[i
];
4373 if (GET_CODE (op
) == SUBREG
)
4376 op
= SUBREG_REG (op
);
4377 mode
= GET_MODE (op
);
4380 if (CONST_POOL_OK_P (mode
, op
)
4381 && ((targetm
.preferred_reload_class
4382 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4383 || no_input_reloads_p
))
4385 rtx tem
= force_const_mem (mode
, op
);
4388 if (subreg
!= NULL_RTX
)
4389 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4391 *curr_id
->operand_loc
[i
] = tem
;
4392 lra_update_dup (curr_id
, i
);
4393 process_address (i
, false, &before
, &after
);
4395 /* If the alternative accepts constant pool refs directly
4396 there will be no reload needed at all. */
4397 if (subreg
!= NULL_RTX
)
4399 /* Skip alternatives before the one requested. */
4400 constraint
= (curr_static_id
->operand_alternative
4401 [goal_alt_number
* n_operands
+ i
].constraint
);
4403 (c
= *constraint
) && c
!= ',' && c
!= '#';
4404 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4406 enum constraint_num cn
= lookup_constraint (constraint
);
4407 if ((insn_extra_memory_constraint (cn
)
4408 || insn_extra_special_memory_constraint (cn
)
4409 || insn_extra_relaxed_memory_constraint (cn
))
4410 && satisfies_memory_constraint_p (tem
, cn
))
4413 if (c
== '\0' || c
== ',' || c
== '#')
4416 goal_alt_win
[i
] = true;
4421 for (i
= 0; i
< n_operands
; i
++)
4422 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4423 outputs
[n_outputs
++] = i
;
4424 outputs
[n_outputs
] = -1;
4425 for (i
= 0; i
< n_operands
; i
++)
4428 bool optional_p
= false;
4430 rtx op
= *curr_id
->operand_loc
[i
];
4432 if (goal_alt_win
[i
])
4434 if (goal_alt
[i
] == NO_REGS
4436 /* When we assign NO_REGS it means that we will not
4437 assign a hard register to the scratch pseudo by
4438 assigment pass and the scratch pseudo will be
4439 spilled. Spilled scratch pseudos are transformed
4440 back to scratches at the LRA end. */
4441 && ira_former_scratch_operand_p (curr_insn
, i
)
4442 && ira_former_scratch_p (REGNO (op
)))
4444 int regno
= REGNO (op
);
4445 lra_change_class (regno
, NO_REGS
, " Change to", true);
4446 if (lra_get_regno_hard_regno (regno
) >= 0)
4447 /* We don't have to mark all insn affected by the
4448 spilled pseudo as there is only one such insn, the
4450 reg_renumber
[regno
] = -1;
4451 lra_assert (bitmap_single_bit_set_p
4452 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4454 /* We can do an optional reload. If the pseudo got a hard
4455 reg, we might improve the code through inheritance. If
4456 it does not get a hard register we coalesce memory/memory
4457 moves later. Ignore move insns to avoid cycling. */
4459 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4460 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4461 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4462 && regno
< new_regno_start
4463 && ! ira_former_scratch_p (regno
)
4464 && reg_renumber
[regno
] < 0
4465 /* Check that the optional reload pseudo will be able to
4466 hold given mode value. */
4467 && ! (prohibited_class_reg_set_mode_p
4468 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4469 PSEUDO_REGNO_MODE (regno
)))
4470 && (curr_insn_set
== NULL_RTX
4471 || !((REG_P (SET_SRC (curr_insn_set
))
4472 || MEM_P (SET_SRC (curr_insn_set
))
4473 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4474 && (REG_P (SET_DEST (curr_insn_set
))
4475 || MEM_P (SET_DEST (curr_insn_set
))
4476 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4478 else if (goal_alt_matched
[i
][0] != -1
4479 && curr_static_id
->operand
[i
].type
== OP_OUT
4480 && (curr_static_id
->operand_alternative
4481 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4484 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4486 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4488 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4491 if (goal_alt_matched
[i
][j
] != -1)
4493 /* Generate reloads for different output and matched
4494 input registers. This is the easiest way to avoid
4495 creation of non-existing register conflicts in
4497 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4498 &goal_alt_exclude_start_hard_regs
[i
], &before
,
4507 /* Operands that match previous ones have already been handled. */
4508 if (goal_alt_matches
[i
] >= 0)
4511 /* We should not have an operand with a non-offsettable address
4512 appearing where an offsettable address will do. It also may
4513 be a case when the address should be special in other words
4514 not a general one (e.g. it needs no index reg). */
4515 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4517 enum reg_class rclass
;
4518 rtx
*loc
= &XEXP (op
, 0);
4519 enum rtx_code code
= GET_CODE (*loc
);
4521 push_to_sequence (before
);
4522 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4524 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4525 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4526 /* This value does not matter for MODIFY. */
4527 GET_MODE_SIZE (GET_MODE (op
)));
4528 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
4530 "offsetable address", &new_reg
))
4533 enum rtx_code code
= GET_CODE (addr
);
4534 bool align_p
= false;
4536 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4538 /* (and ... (const_int -X)) is used to align to X bytes. */
4540 addr
= XEXP (*loc
, 0);
4543 addr
= canonicalize_reload_addr (addr
);
4545 lra_emit_move (new_reg
, addr
);
4547 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4549 before
= get_insns ();
4552 lra_update_dup (curr_id
, i
);
4554 else if (goal_alt_matched
[i
][0] == -1)
4559 enum op_type type
= curr_static_id
->operand
[i
].type
;
4561 loc
= curr_id
->operand_loc
[i
];
4562 mode
= curr_operand_mode
[i
];
4563 if (GET_CODE (*loc
) == SUBREG
)
4565 reg
= SUBREG_REG (*loc
);
4566 poly_int64 byte
= SUBREG_BYTE (*loc
);
4568 /* Strict_low_part requires reloading the register and not
4569 just the subreg. Likewise for a strict subreg no wider
4570 than a word for WORD_REGISTER_OPERATIONS targets. */
4571 && (curr_static_id
->operand
[i
].strict_low
4572 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4574 = get_try_hard_regno (REGNO (reg
))) >= 0
4575 && (simplify_subreg_regno
4577 GET_MODE (reg
), byte
, mode
) < 0)
4578 && (goal_alt
[i
] == NO_REGS
4579 || (simplify_subreg_regno
4580 (ira_class_hard_regs
[goal_alt
[i
]][0],
4581 GET_MODE (reg
), byte
, mode
) >= 0)))
4582 || (partial_subreg_p (mode
, GET_MODE (reg
))
4583 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4585 && WORD_REGISTER_OPERATIONS
)))
4587 /* An OP_INOUT is required when reloading a subreg of a
4588 mode wider than a word to ensure that data beyond the
4589 word being reloaded is preserved. Also automatically
4590 ensure that strict_low_part reloads are made into
4591 OP_INOUT which should already be true from the backend
4594 && (curr_static_id
->operand
[i
].strict_low
4595 || read_modify_subreg_p (*loc
)))
4597 loc
= &SUBREG_REG (*loc
);
4598 mode
= GET_MODE (*loc
);
4602 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4603 &goal_alt_exclude_start_hard_regs
[i
],
4604 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4607 push_to_sequence (before
);
4608 lra_emit_move (new_reg
, old
);
4609 before
= get_insns ();
4614 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4617 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4619 after
= get_insns ();
4623 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4624 if (goal_alt_dont_inherit_ops
[j
] == i
)
4626 lra_set_regno_unique_value (REGNO (new_reg
));
4629 lra_update_dup (curr_id
, i
);
4631 else if (curr_static_id
->operand
[i
].type
== OP_IN
4632 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4634 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4636 && (operands_match_p
4637 (*curr_id
->operand_loc
[i
],
4638 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4641 /* generate reloads for input and matched outputs. */
4642 match_inputs
[0] = i
;
4643 match_inputs
[1] = -1;
4644 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4645 goal_alt
[i
], &goal_alt_exclude_start_hard_regs
[i
],
4647 curr_static_id
->operand_alternative
4648 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4651 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4652 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4653 && (operands_match_p
4654 (*curr_id
->operand_loc
[i
],
4655 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4657 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4659 /* Generate reloads for output and matched inputs. */
4660 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4661 &goal_alt_exclude_start_hard_regs
[i
], &before
, &after
,
4662 curr_static_id
->operand_alternative
4663 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4664 else if (curr_static_id
->operand
[i
].type
== OP_IN
4665 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4668 /* Generate reloads for matched inputs. */
4669 match_inputs
[0] = i
;
4670 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4671 match_inputs
[j
+ 1] = k
;
4672 match_inputs
[j
+ 1] = -1;
4673 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
],
4674 &goal_alt_exclude_start_hard_regs
[i
],
4675 &before
, &after
, false);
4678 /* We must generate code in any case when function
4679 process_alt_operands decides that it is possible. */
4686 lra_assert (REG_P (reg
));
4687 regno
= REGNO (reg
);
4688 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4689 if (GET_CODE (op
) == SUBREG
)
4690 op
= SUBREG_REG (op
);
4691 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4692 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4693 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4694 if (lra_dump_file
!= NULL
)
4695 fprintf (lra_dump_file
,
4696 " Making reload reg %d for reg %d optional\n",
4700 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4701 || max_regno_before
!= max_reg_num ())
4705 lra_update_operator_dups (curr_id
);
4706 /* Something changes -- process the insn. */
4707 lra_update_insn_regno_info (curr_insn
);
4709 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4713 /* Return true if INSN satisfies all constraints. In other words, no
4714 reload insns are needed. */
4716 lra_constrain_insn (rtx_insn
*insn
)
4718 int saved_new_regno_start
= new_regno_start
;
4719 int saved_new_insn_uid_start
= new_insn_uid_start
;
4723 curr_id
= lra_get_insn_recog_data (curr_insn
);
4724 curr_static_id
= curr_id
->insn_static_data
;
4725 new_insn_uid_start
= get_max_uid ();
4726 new_regno_start
= max_reg_num ();
4727 change_p
= curr_insn_transform (true);
4728 new_regno_start
= saved_new_regno_start
;
4729 new_insn_uid_start
= saved_new_insn_uid_start
;
4733 /* Return true if X is in LIST. */
4735 in_list_p (rtx x
, rtx list
)
4737 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4738 if (XEXP (list
, 0) == x
)
4743 /* Return true if X contains an allocatable hard register (if
4744 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4746 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4752 code
= GET_CODE (x
);
4755 int regno
= REGNO (x
);
4756 HARD_REG_SET alloc_regs
;
4760 if (regno
>= FIRST_PSEUDO_REGISTER
)
4761 regno
= lra_get_regno_hard_regno (regno
);
4764 alloc_regs
= ~lra_no_alloc_regs
;
4765 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4769 if (regno
< FIRST_PSEUDO_REGISTER
)
4773 return lra_get_regno_hard_regno (regno
) < 0;
4776 fmt
= GET_RTX_FORMAT (code
);
4777 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4781 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4784 else if (fmt
[i
] == 'E')
4786 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4787 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4794 /* Process all regs in location *LOC and change them on equivalent
4795 substitution. Return true if any change was done. */
4797 loc_equivalence_change_p (rtx
*loc
)
4799 rtx subst
, reg
, x
= *loc
;
4800 bool result
= false;
4801 enum rtx_code code
= GET_CODE (x
);
4807 reg
= SUBREG_REG (x
);
4808 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4809 && GET_MODE (subst
) == VOIDmode
)
4811 /* We cannot reload debug location. Simplify subreg here
4812 while we know the inner mode. */
4813 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4814 GET_MODE (reg
), SUBREG_BYTE (x
));
4818 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4824 /* Scan all the operand sub-expressions. */
4825 fmt
= GET_RTX_FORMAT (code
);
4826 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4829 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4830 else if (fmt
[i
] == 'E')
4831 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4833 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4838 /* Similar to loc_equivalence_change_p, but for use as
4839 simplify_replace_fn_rtx callback. DATA is insn for which the
4840 elimination is done. If it null we don't do the elimination. */
4842 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4847 rtx subst
= (data
== NULL
4848 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4855 /* Maximum number of generated reload insns per an insn. It is for
4856 preventing this pass cycling in a bug case. */
4857 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4859 /* The current iteration number of this LRA pass. */
4860 int lra_constraint_iter
;
4862 /* True if we should during assignment sub-pass check assignment
4863 correctness for all pseudos and spill some of them to correct
4864 conflicts. It can be necessary when we substitute equiv which
4865 needs checking register allocation correctness because the
4866 equivalent value contains allocatable hard registers, or when we
4867 restore multi-register pseudo, or when we change the insn code and
4868 its operand became INOUT operand when it was IN one before. */
4869 bool check_and_force_assignment_correctness_p
;
4871 /* Return true if REGNO is referenced in more than one block. */
4873 multi_block_pseudo_p (int regno
)
4875 basic_block bb
= NULL
;
4879 if (regno
< FIRST_PSEUDO_REGISTER
)
4882 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4884 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4885 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4890 /* Return true if LIST contains a deleted insn. */
4892 contains_deleted_insn_p (rtx_insn_list
*list
)
4894 for (; list
!= NULL_RTX
; list
= list
->next ())
4895 if (NOTE_P (list
->insn ())
4896 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4901 /* Return true if X contains a pseudo dying in INSN. */
4903 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4910 return (insn
!= NULL_RTX
4911 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4912 code
= GET_CODE (x
);
4913 fmt
= GET_RTX_FORMAT (code
);
4914 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4918 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4921 else if (fmt
[i
] == 'E')
4923 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4924 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4931 /* Return true if INSN contains a dying pseudo in INSN right hand
4934 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4936 rtx set
= single_set (insn
);
4938 gcc_assert (set
!= NULL
);
4939 return dead_pseudo_p (SET_SRC (set
), insn
);
4942 /* Return true if any init insn of REGNO contains a dying pseudo in
4943 insn right hand side. */
4945 init_insn_rhs_dead_pseudo_p (int regno
)
4947 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4951 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4952 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4957 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4958 reverse only if we have one init insn with given REGNO as a
4961 reverse_equiv_p (int regno
)
4963 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4968 if (! INSN_P (insns
->insn ())
4969 || insns
->next () != NULL
)
4971 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4973 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4976 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4977 call this function only for non-reverse equivalence. */
4979 contains_reloaded_insn_p (int regno
)
4982 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4984 for (; list
!= NULL
; list
= list
->next ())
4985 if ((set
= single_set (list
->insn ())) == NULL_RTX
4986 || ! REG_P (SET_DEST (set
))
4987 || (int) REGNO (SET_DEST (set
)) != regno
)
4992 /* Entry function of LRA constraint pass. Return true if the
4993 constraint pass did change the code. */
4995 lra_constraints (bool first_p
)
4998 int i
, hard_regno
, new_insns_num
;
4999 unsigned int min_len
, new_min_len
, uid
;
5000 rtx set
, x
, reg
, dest_reg
;
5001 basic_block last_bb
;
5004 lra_constraint_iter
++;
5005 if (lra_dump_file
!= NULL
)
5006 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
5007 lra_constraint_iter
);
5009 if (pic_offset_table_rtx
5010 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5011 check_and_force_assignment_correctness_p
= true;
5013 /* On the first iteration we should check IRA assignment
5014 correctness. In rare cases, the assignments can be wrong as
5015 early clobbers operands are ignored in IRA or usages of
5016 paradoxical sub-registers are not taken into account by
5018 check_and_force_assignment_correctness_p
= true;
5019 new_insn_uid_start
= get_max_uid ();
5020 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
5021 /* Mark used hard regs for target stack size calulations. */
5022 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5023 if (lra_reg_info
[i
].nrefs
!= 0
5024 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5028 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
5029 for (j
= 0; j
< nregs
; j
++)
5030 df_set_regs_ever_live (hard_regno
+ j
, true);
5032 /* Do elimination before the equivalence processing as we can spill
5033 some pseudos during elimination. */
5034 lra_eliminate (false, first_p
);
5035 auto_bitmap
equiv_insn_bitmap (®_obstack
);
5036 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5037 if (lra_reg_info
[i
].nrefs
!= 0)
5039 ira_reg_equiv
[i
].profitable_p
= true;
5040 reg
= regno_reg_rtx
[i
];
5041 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
5043 bool pseudo_p
= contains_reg_p (x
, false, false);
5045 /* After RTL transformation, we cannot guarantee that
5046 pseudo in the substitution was not reloaded which might
5047 make equivalence invalid. For example, in reverse
5054 the memory address register was reloaded before the 2nd
5056 if ((! first_p
&& pseudo_p
)
5057 /* We don't use DF for compilation speed sake. So it
5058 is problematic to update live info when we use an
5059 equivalence containing pseudos in more than one
5061 || (pseudo_p
&& multi_block_pseudo_p (i
))
5062 /* If an init insn was deleted for some reason, cancel
5063 the equiv. We could update the equiv insns after
5064 transformations including an equiv insn deletion
5065 but it is not worthy as such cases are extremely
5067 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
5068 /* If it is not a reverse equivalence, we check that a
5069 pseudo in rhs of the init insn is not dying in the
5070 insn. Otherwise, the live info at the beginning of
5071 the corresponding BB might be wrong after we
5072 removed the insn. When the equiv can be a
5073 constant, the right hand side of the init insn can
5075 || (! reverse_equiv_p (i
)
5076 && (init_insn_rhs_dead_pseudo_p (i
)
5077 /* If we reloaded the pseudo in an equivalence
5078 init insn, we cannot remove the equiv init
5079 insns and the init insns might write into
5080 const memory in this case. */
5081 || contains_reloaded_insn_p (i
)))
5082 /* Prevent access beyond equivalent memory for
5083 paradoxical subregs. */
5085 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
5086 GET_MODE_SIZE (GET_MODE (x
))))
5087 || (pic_offset_table_rtx
5088 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
5089 && (targetm
.preferred_reload_class
5090 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
5091 || contains_symbol_ref_p (x
))))
5092 ira_reg_equiv
[i
].defined_p
= false;
5093 if (contains_reg_p (x
, false, true))
5094 ira_reg_equiv
[i
].profitable_p
= false;
5095 if (get_equiv (reg
) != reg
)
5096 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
5099 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5101 /* We should add all insns containing pseudos which should be
5102 substituted by their equivalences. */
5103 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
5104 lra_push_insn_by_uid (uid
);
5105 min_len
= lra_insn_stack_length ();
5109 while ((new_min_len
= lra_insn_stack_length ()) != 0)
5111 curr_insn
= lra_pop_insn ();
5113 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5114 if (curr_bb
!= last_bb
)
5117 bb_reload_num
= lra_curr_reload_num
;
5119 if (min_len
> new_min_len
)
5121 min_len
= new_min_len
;
5124 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
5126 ("maximum number of generated reload insns per insn achieved (%d)",
5127 MAX_RELOAD_INSNS_NUMBER
);
5129 if (DEBUG_INSN_P (curr_insn
))
5131 /* We need to check equivalence in debug insn and change
5132 pseudo to the equivalent value if necessary. */
5133 curr_id
= lra_get_insn_recog_data (curr_insn
);
5134 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
5136 rtx old
= *curr_id
->operand_loc
[0];
5137 *curr_id
->operand_loc
[0]
5138 = simplify_replace_fn_rtx (old
, NULL_RTX
,
5139 loc_equivalence_callback
, curr_insn
);
5140 if (old
!= *curr_id
->operand_loc
[0])
5142 lra_update_insn_regno_info (curr_insn
);
5147 else if (INSN_P (curr_insn
))
5149 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
5151 dest_reg
= SET_DEST (set
);
5152 /* The equivalence pseudo could be set up as SUBREG in a
5153 case when it is a call restore insn in a mode
5154 different from the pseudo mode. */
5155 if (GET_CODE (dest_reg
) == SUBREG
)
5156 dest_reg
= SUBREG_REG (dest_reg
);
5157 if ((REG_P (dest_reg
)
5158 && (x
= get_equiv (dest_reg
)) != dest_reg
5159 /* Remove insns which set up a pseudo whose value
5160 cannot be changed. Such insns might be not in
5161 init_insns because we don't update equiv data
5162 during insn transformations.
5164 As an example, let suppose that a pseudo got
5165 hard register and on the 1st pass was not
5166 changed to equivalent constant. We generate an
5167 additional insn setting up the pseudo because of
5168 secondary memory movement. Then the pseudo is
5169 spilled and we use the equiv constant. In this
5170 case we should remove the additional insn and
5171 this insn is not init_insns list. */
5172 && (! MEM_P (x
) || MEM_READONLY_P (x
)
5173 /* Check that this is actually an insn setting
5174 up the equivalence. */
5175 || in_list_p (curr_insn
,
5177 [REGNO (dest_reg
)].init_insns
)))
5178 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5179 && in_list_p (curr_insn
,
5181 [REGNO (SET_SRC (set
))].init_insns
)))
5183 /* This is equiv init insn of pseudo which did not get a
5184 hard register -- remove the insn. */
5185 if (lra_dump_file
!= NULL
)
5187 fprintf (lra_dump_file
,
5188 " Removing equiv init insn %i (freq=%d)\n",
5189 INSN_UID (curr_insn
),
5190 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5191 dump_insn_slim (lra_dump_file
, curr_insn
);
5193 if (contains_reg_p (x
, true, false))
5194 check_and_force_assignment_correctness_p
= true;
5195 lra_set_insn_deleted (curr_insn
);
5199 curr_id
= lra_get_insn_recog_data (curr_insn
);
5200 curr_static_id
= curr_id
->insn_static_data
;
5201 init_curr_insn_input_reloads ();
5202 init_curr_operand_mode ();
5203 if (curr_insn_transform (false))
5205 /* Check non-transformed insns too for equiv change as USE
5206 or CLOBBER don't need reloads but can contain pseudos
5207 being changed on their equivalences. */
5208 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5209 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5211 lra_update_insn_regno_info (curr_insn
);
5217 /* If we used a new hard regno, changed_p should be true because the
5218 hard reg is assigned to a new pseudo. */
5219 if (flag_checking
&& !changed_p
)
5221 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5222 if (lra_reg_info
[i
].nrefs
!= 0
5223 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5225 int j
, nregs
= hard_regno_nregs (hard_regno
,
5226 PSEUDO_REGNO_MODE (i
));
5228 for (j
= 0; j
< nregs
; j
++)
5229 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5235 static void initiate_invariants (void);
5236 static void finish_invariants (void);
5238 /* Initiate the LRA constraint pass. It is done once per
5241 lra_constraints_init (void)
5243 initiate_invariants ();
5246 /* Finalize the LRA constraint pass. It is done once per
5249 lra_constraints_finish (void)
5251 finish_invariants ();
5256 /* Structure describes invariants for ineheritance. */
5257 struct lra_invariant
5259 /* The order number of the invariant. */
5261 /* The invariant RTX. */
5263 /* The origin insn of the invariant. */
5267 typedef lra_invariant invariant_t
;
5268 typedef invariant_t
*invariant_ptr_t
;
5269 typedef const invariant_t
*const_invariant_ptr_t
;
5271 /* Pointer to the inheritance invariants. */
5272 static vec
<invariant_ptr_t
> invariants
;
5274 /* Allocation pool for the invariants. */
5275 static object_allocator
<lra_invariant
> *invariants_pool
;
5277 /* Hash table for the invariants. */
5278 static htab_t invariant_table
;
5280 /* Hash function for INVARIANT. */
5282 invariant_hash (const void *invariant
)
5284 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5285 return lra_rtx_hash (inv
);
5288 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5290 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5292 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5293 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5295 return rtx_equal_p (inv1
, inv2
);
5298 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5299 invariant which is in the table. */
5300 static invariant_ptr_t
5301 insert_invariant (rtx invariant_rtx
)
5304 invariant_t invariant
;
5305 invariant_ptr_t invariant_ptr
;
5307 invariant
.invariant_rtx
= invariant_rtx
;
5308 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5309 if (*entry_ptr
== NULL
)
5311 invariant_ptr
= invariants_pool
->allocate ();
5312 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5313 invariant_ptr
->insn
= NULL
;
5314 invariants
.safe_push (invariant_ptr
);
5315 *entry_ptr
= (void *) invariant_ptr
;
5317 return (invariant_ptr_t
) *entry_ptr
;
5320 /* Initiate the invariant table. */
5322 initiate_invariants (void)
5324 invariants
.create (100);
5326 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5327 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5330 /* Finish the invariant table. */
5332 finish_invariants (void)
5334 htab_delete (invariant_table
);
5335 delete invariants_pool
;
5336 invariants
.release ();
5339 /* Make the invariant table empty. */
5341 clear_invariants (void)
5343 htab_empty (invariant_table
);
5344 invariants_pool
->release ();
5345 invariants
.truncate (0);
5350 /* This page contains code to do inheritance/split
5353 /* Number of reloads passed so far in current EBB. */
5354 static int reloads_num
;
5356 /* Number of calls passed so far in current EBB. */
5357 static int calls_num
;
5359 /* Index ID is the CALLS_NUM associated the last call we saw with
5360 ABI identifier ID. */
5361 static int last_call_for_abi
[NUM_ABI_IDS
];
5363 /* Which registers have been fully or partially clobbered by a call
5364 since they were last used. */
5365 static HARD_REG_SET full_and_partial_call_clobbers
;
5367 /* Current reload pseudo check for validity of elements in
5369 static int curr_usage_insns_check
;
5371 /* Info about last usage of registers in EBB to do inheritance/split
5372 transformation. Inheritance transformation is done from a spilled
5373 pseudo and split transformations from a hard register or a pseudo
5374 assigned to a hard register. */
5377 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5378 value INSNS is valid. The insns is chain of optional debug insns
5379 and a finishing non-debug insn using the corresponding reg. The
5380 value is also used to mark the registers which are set up in the
5381 current insn. The negated insn uid is used for this. */
5383 /* Value of global reloads_num at the last insn in INSNS. */
5385 /* Value of global reloads_nums at the last insn in INSNS. */
5387 /* It can be true only for splitting. And it means that the restore
5388 insn should be put after insn given by the following member. */
5390 /* Next insns in the current EBB which use the original reg and the
5391 original reg value is not changed between the current insn and
5392 the next insns. In order words, e.g. for inheritance, if we need
5393 to use the original reg value again in the next insns we can try
5394 to use the value in a hard register from a reload insn of the
5399 /* Map: regno -> corresponding pseudo usage insns. */
5400 static struct usage_insns
*usage_insns
;
5403 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5405 usage_insns
[regno
].check
= curr_usage_insns_check
;
5406 usage_insns
[regno
].insns
= insn
;
5407 usage_insns
[regno
].reloads_num
= reloads_num
;
5408 usage_insns
[regno
].calls_num
= calls_num
;
5409 usage_insns
[regno
].after_p
= after_p
;
5410 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5411 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5412 PSEUDO_REGNO_MODE (regno
),
5413 reg_renumber
[regno
]);
5416 /* The function is used to form list REGNO usages which consists of
5417 optional debug insns finished by a non-debug insn using REGNO.
5418 RELOADS_NUM is current number of reload insns processed so far. */
5420 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5422 rtx next_usage_insns
;
5424 if (usage_insns
[regno
].check
== curr_usage_insns_check
5425 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5426 && DEBUG_INSN_P (insn
))
5428 /* Check that we did not add the debug insn yet. */
5429 if (next_usage_insns
!= insn
5430 && (GET_CODE (next_usage_insns
) != INSN_LIST
5431 || XEXP (next_usage_insns
, 0) != insn
))
5432 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5435 else if (NONDEBUG_INSN_P (insn
))
5436 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5438 usage_insns
[regno
].check
= 0;
5441 /* Return first non-debug insn in list USAGE_INSNS. */
5443 skip_usage_debug_insns (rtx usage_insns
)
5447 /* Skip debug insns. */
5448 for (insn
= usage_insns
;
5449 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5450 insn
= XEXP (insn
, 1))
5452 return safe_as_a
<rtx_insn
*> (insn
);
5455 /* Return true if we need secondary memory moves for insn in
5456 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5459 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5460 rtx usage_insns ATTRIBUTE_UNUSED
)
5466 if (inher_cl
== ALL_REGS
5467 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5469 lra_assert (INSN_P (insn
));
5470 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5472 dest
= SET_DEST (set
);
5475 lra_assert (inher_cl
!= NO_REGS
);
5476 cl
= get_reg_class (REGNO (dest
));
5477 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5478 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5481 /* Registers involved in inheritance/split in the current EBB
5482 (inheritance/split pseudos and original registers). */
5483 static bitmap_head check_only_regs
;
5485 /* Reload pseudos cannot be involded in invariant inheritance in the
5487 static bitmap_head invalid_invariant_regs
;
5489 /* Do inheritance transformations for insn INSN, which defines (if
5490 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5491 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5492 form as the "insns" field of usage_insns. Return true if we
5493 succeed in such transformation.
5495 The transformations look like:
5498 ... p <- i (new insn)
5500 <- ... p ... <- ... i ...
5502 ... i <- p (new insn)
5503 <- ... p ... <- ... i ...
5505 <- ... p ... <- ... i ...
5506 where p is a spilled original pseudo and i is a new inheritance pseudo.
5509 The inheritance pseudo has the smallest class of two classes CL and
5510 class of ORIGINAL REGNO. */
5512 inherit_reload_reg (bool def_p
, int original_regno
,
5513 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5515 if (optimize_function_for_size_p (cfun
))
5518 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5519 rtx original_reg
= regno_reg_rtx
[original_regno
];
5520 rtx new_reg
, usage_insn
;
5521 rtx_insn
*new_insns
;
5523 lra_assert (! usage_insns
[original_regno
].after_p
);
5524 if (lra_dump_file
!= NULL
)
5525 fprintf (lra_dump_file
,
5526 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5527 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5529 if (lra_dump_file
!= NULL
)
5531 fprintf (lra_dump_file
,
5532 " Rejecting inheritance for %d "
5533 "because of disjoint classes %s and %s\n",
5534 original_regno
, reg_class_names
[cl
],
5535 reg_class_names
[rclass
]);
5536 fprintf (lra_dump_file
,
5537 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5541 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5542 /* We don't use a subset of two classes because it can be
5543 NO_REGS. This transformation is still profitable in most
5544 cases even if the classes are not intersected as register
5545 move is probably cheaper than a memory load. */
5546 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5548 if (lra_dump_file
!= NULL
)
5549 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5550 reg_class_names
[cl
], reg_class_names
[rclass
]);
5554 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5556 /* Reject inheritance resulting in secondary memory moves.
5557 Otherwise, there is a danger in LRA cycling. Also such
5558 transformation will be unprofitable. */
5559 if (lra_dump_file
!= NULL
)
5561 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5562 rtx set
= single_set (insn
);
5564 lra_assert (set
!= NULL_RTX
);
5566 rtx dest
= SET_DEST (set
);
5568 lra_assert (REG_P (dest
));
5569 fprintf (lra_dump_file
,
5570 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5571 "as secondary mem is needed\n",
5572 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5573 original_regno
, reg_class_names
[rclass
]);
5574 fprintf (lra_dump_file
,
5575 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5579 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5580 rclass
, NULL
, "inheritance");
5583 lra_emit_move (original_reg
, new_reg
);
5585 lra_emit_move (new_reg
, original_reg
);
5586 new_insns
= get_insns ();
5588 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5590 if (lra_dump_file
!= NULL
)
5592 fprintf (lra_dump_file
,
5593 " Rejecting inheritance %d->%d "
5594 "as it results in 2 or more insns:\n",
5595 original_regno
, REGNO (new_reg
));
5596 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5597 fprintf (lra_dump_file
,
5598 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5602 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5603 lra_update_insn_regno_info (insn
);
5605 /* We now have a new usage insn for original regno. */
5606 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5607 if (lra_dump_file
!= NULL
)
5608 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5609 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5610 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5611 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5612 bitmap_set_bit (&check_only_regs
, original_regno
);
5613 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5615 lra_process_new_insns (insn
, NULL
, new_insns
,
5616 "Add original<-inheritance");
5618 lra_process_new_insns (insn
, new_insns
, NULL
,
5619 "Add inheritance<-original");
5620 while (next_usage_insns
!= NULL_RTX
)
5622 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5624 usage_insn
= next_usage_insns
;
5625 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5626 next_usage_insns
= NULL
;
5630 usage_insn
= XEXP (next_usage_insns
, 0);
5631 lra_assert (DEBUG_INSN_P (usage_insn
));
5632 next_usage_insns
= XEXP (next_usage_insns
, 1);
5634 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5635 DEBUG_INSN_P (usage_insn
));
5636 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5637 if (lra_dump_file
!= NULL
)
5639 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5640 fprintf (lra_dump_file
,
5641 " Inheritance reuse change %d->%d (bb%d):\n",
5642 original_regno
, REGNO (new_reg
),
5643 bb
? bb
->index
: -1);
5644 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5647 if (lra_dump_file
!= NULL
)
5648 fprintf (lra_dump_file
,
5649 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5653 /* Return true if we need a caller save/restore for pseudo REGNO which
5654 was assigned to a hard register. */
5656 need_for_call_save_p (int regno
)
5658 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5659 if (usage_insns
[regno
].calls_num
< calls_num
)
5661 unsigned int abis
= 0;
5662 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5663 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5666 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5667 PSEUDO_REGNO_MODE (regno
),
5668 reg_renumber
[regno
]))
5674 /* Global registers occurring in the current EBB. */
5675 static bitmap_head ebb_global_regs
;
5677 /* Return true if we need a split for hard register REGNO or pseudo
5678 REGNO which was assigned to a hard register.
5679 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5680 used for reloads since the EBB end. It is an approximation of the
5681 used hard registers in the split range. The exact value would
5682 require expensive calculations. If we were aggressive with
5683 splitting because of the approximation, the split pseudo will save
5684 the same hard register assignment and will be removed in the undo
5685 pass. We still need the approximation because too aggressive
5686 splitting would result in too inaccurate cost calculation in the
5687 assignment pass because of too many generated moves which will be
5688 probably removed in the undo pass. */
5690 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5692 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5694 lra_assert (hard_regno
>= 0);
5695 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5696 /* Don't split eliminable hard registers, otherwise we can
5697 split hard registers like hard frame pointer, which
5698 lives on BB start/end according to DF-infrastructure,
5699 when there is a pseudo assigned to the register and
5700 living in the same BB. */
5701 && (regno
>= FIRST_PSEUDO_REGISTER
5702 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5703 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5704 /* Don't split call clobbered hard regs living through
5705 calls, otherwise we might have a check problem in the
5706 assign sub-pass as in the most cases (exception is a
5707 situation when check_and_force_assignment_correctness_p value is
5708 true) the assign pass assumes that all pseudos living
5709 through calls are assigned to call saved hard regs. */
5710 && (regno
>= FIRST_PSEUDO_REGISTER
5711 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
5712 /* We need at least 2 reloads to make pseudo splitting
5713 profitable. We should provide hard regno splitting in
5714 any case to solve 1st insn scheduling problem when
5715 moving hard register definition up might result in
5716 impossibility to find hard register for reload pseudo of
5717 small register class. */
5718 && (usage_insns
[regno
].reloads_num
5719 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5720 && (regno
< FIRST_PSEUDO_REGISTER
5721 /* For short living pseudos, spilling + inheritance can
5722 be considered a substitution for splitting.
5723 Therefore we do not splitting for local pseudos. It
5724 decreases also aggressiveness of splitting. The
5725 minimal number of references is chosen taking into
5726 account that for 2 references splitting has no sense
5727 as we can just spill the pseudo. */
5728 || (regno
>= FIRST_PSEUDO_REGISTER
5729 && lra_reg_info
[regno
].nrefs
> 3
5730 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5731 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5734 /* Return class for the split pseudo created from original pseudo with
5735 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5736 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5737 results in no secondary memory movements. */
5738 static enum reg_class
5739 choose_split_class (enum reg_class allocno_class
,
5740 int hard_regno ATTRIBUTE_UNUSED
,
5741 machine_mode mode ATTRIBUTE_UNUSED
)
5744 enum reg_class cl
, best_cl
= NO_REGS
;
5745 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5746 = REGNO_REG_CLASS (hard_regno
);
5748 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5749 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5750 return allocno_class
;
5752 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5754 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5755 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5756 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5757 && (best_cl
== NO_REGS
5758 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5763 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5764 It only makes sense to call this function if NEW_REGNO is always
5765 equal to ORIGINAL_REGNO. */
5768 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5770 if (!ira_reg_equiv
[original_regno
].defined_p
)
5773 ira_expand_reg_equiv ();
5774 ira_reg_equiv
[new_regno
].defined_p
= true;
5775 if (ira_reg_equiv
[original_regno
].memory
)
5776 ira_reg_equiv
[new_regno
].memory
5777 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5778 if (ira_reg_equiv
[original_regno
].constant
)
5779 ira_reg_equiv
[new_regno
].constant
5780 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5781 if (ira_reg_equiv
[original_regno
].invariant
)
5782 ira_reg_equiv
[new_regno
].invariant
5783 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5786 /* Do split transformations for insn INSN, which defines or uses
5787 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5788 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5789 "insns" field of usage_insns. If TO is not NULL, we don't use
5790 usage_insns, we put restore insns after TO insn. It is a case when
5791 we call it from lra_split_hard_reg_for, outside the inheritance
5794 The transformations look like:
5797 ... s <- p (new insn -- save)
5799 ... p <- s (new insn -- restore)
5800 <- ... p ... <- ... p ...
5802 <- ... p ... <- ... p ...
5803 ... s <- p (new insn -- save)
5805 ... p <- s (new insn -- restore)
5806 <- ... p ... <- ... p ...
5808 where p is an original pseudo got a hard register or a hard
5809 register and s is a new split pseudo. The save is put before INSN
5810 if BEFORE_P is true. Return true if we succeed in such
5813 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5814 rtx next_usage_insns
, rtx_insn
*to
)
5816 enum reg_class rclass
;
5818 int hard_regno
, nregs
;
5819 rtx new_reg
, usage_insn
;
5820 rtx_insn
*restore
, *save
;
5825 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5827 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5828 hard_regno
= original_regno
;
5829 call_save_p
= false;
5831 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5832 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5833 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
5834 part of a multi-word register. In that case, just use the reg_rtx
5835 mode. Do the same also if the biggest mode was larger than a register
5836 or we can not compare the modes. Otherwise, limit the size to that of
5837 the biggest access in the function or to the natural mode at least. */
5838 if (mode
== VOIDmode
5839 || !ordered_p (GET_MODE_PRECISION (mode
),
5840 GET_MODE_PRECISION (reg_rtx_mode
))
5841 || paradoxical_subreg_p (mode
, reg_rtx_mode
)
5842 || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode
), GET_MODE_PRECISION (mode
)))
5844 original_reg
= regno_reg_rtx
[hard_regno
];
5845 mode
= reg_rtx_mode
;
5848 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5852 mode
= PSEUDO_REGNO_MODE (original_regno
);
5853 hard_regno
= reg_renumber
[original_regno
];
5854 nregs
= hard_regno_nregs (hard_regno
, mode
);
5855 rclass
= lra_get_allocno_class (original_regno
);
5856 original_reg
= regno_reg_rtx
[original_regno
];
5857 call_save_p
= need_for_call_save_p (original_regno
);
5859 lra_assert (hard_regno
>= 0);
5860 if (lra_dump_file
!= NULL
)
5861 fprintf (lra_dump_file
,
5862 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5866 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5867 hard_regno_nregs (hard_regno
, mode
),
5869 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, NULL
, "save");
5873 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5874 if (rclass
== NO_REGS
)
5876 if (lra_dump_file
!= NULL
)
5878 fprintf (lra_dump_file
,
5879 " Rejecting split of %d(%s): "
5880 "no good reg class for %d(%s)\n",
5882 reg_class_names
[lra_get_allocno_class (original_regno
)],
5884 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5887 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5891 /* Split_if_necessary can split hard registers used as part of a
5892 multi-register mode but splits each register individually. The
5893 mode used for each independent register may not be supported
5894 so reject the split. Splitting the wider mode should theoretically
5895 be possible but is not implemented. */
5896 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5898 if (lra_dump_file
!= NULL
)
5900 fprintf (lra_dump_file
,
5901 " Rejecting split of %d(%s): unsuitable mode %s\n",
5903 reg_class_names
[lra_get_allocno_class (original_regno
)],
5904 GET_MODE_NAME (mode
));
5907 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5911 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, NULL
, "split");
5912 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5914 int new_regno
= REGNO (new_reg
);
5915 save
= emit_spill_move (true, new_reg
, original_reg
);
5916 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5918 if (lra_dump_file
!= NULL
)
5922 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5923 original_regno
, new_regno
);
5924 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5925 fprintf (lra_dump_file
,
5926 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5930 restore
= emit_spill_move (false, new_reg
, original_reg
);
5931 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5933 if (lra_dump_file
!= NULL
)
5935 fprintf (lra_dump_file
,
5936 " Rejecting split %d->%d "
5937 "resulting in > 2 restore insns:\n",
5938 original_regno
, new_regno
);
5939 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5940 fprintf (lra_dump_file
,
5941 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5945 /* Transfer equivalence information to the spill register, so that
5946 if we fail to allocate the spill register, we have the option of
5947 rematerializing the original value instead of spilling to the stack. */
5948 if (!HARD_REGISTER_NUM_P (original_regno
)
5949 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5950 lra_copy_reg_equiv (new_regno
, original_regno
);
5951 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5952 bitmap_set_bit (&lra_split_regs
, new_regno
);
5955 lra_assert (next_usage_insns
== NULL
);
5961 /* We need check_only_regs only inside the inheritance pass. */
5962 bitmap_set_bit (&check_only_regs
, new_regno
);
5963 bitmap_set_bit (&check_only_regs
, original_regno
);
5964 after_p
= usage_insns
[original_regno
].after_p
;
5967 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5969 usage_insn
= next_usage_insns
;
5972 usage_insn
= XEXP (next_usage_insns
, 0);
5973 lra_assert (DEBUG_INSN_P (usage_insn
));
5974 next_usage_insns
= XEXP (next_usage_insns
, 1);
5975 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5977 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5978 if (lra_dump_file
!= NULL
)
5980 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5981 original_regno
, new_regno
);
5982 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5986 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5987 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5988 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5989 after_p
? NULL
: restore
,
5990 after_p
? restore
: NULL
,
5992 ? "Add reg<-save" : "Add reg<-split");
5993 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5994 before_p
? NULL
: save
,
5996 ? "Add save<-reg" : "Add split<-reg");
5997 if (nregs
> 1 || original_regno
< FIRST_PSEUDO_REGISTER
)
5998 /* If we are trying to split multi-register. We should check
5999 conflicts on the next assignment sub-pass. IRA can allocate on
6000 sub-register levels, LRA do this on pseudos level right now and
6001 this discrepancy may create allocation conflicts after
6004 If we are trying to split hard register we should also check conflicts
6005 as such splitting can create artificial conflict of the hard register
6006 with another pseudo because of simplified conflict calculation in
6008 check_and_force_assignment_correctness_p
= true;
6009 if (lra_dump_file
!= NULL
)
6010 fprintf (lra_dump_file
,
6011 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6015 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
6016 in the range [FROM, TO]. Return true if did a split. Otherwise,
6019 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
6026 HARD_REG_SET ignore
;
6028 lra_assert (from
!= NULL
&& to
!= NULL
);
6029 ignore
= lra_no_alloc_regs
;
6030 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
6032 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
6033 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
6034 struct lra_insn_reg
*reg
;
6036 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6037 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
6038 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6039 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6040 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6042 rclass_size
= ira_class_hard_regs_num
[rclass
];
6043 for (i
= 0; i
< rclass_size
; i
++)
6045 hard_regno
= ira_class_hard_regs
[rclass
][i
];
6046 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
6047 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
6049 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
6051 struct lra_static_insn_data
*static_id
;
6052 struct lra_insn_reg
*reg
;
6056 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
6059 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
6060 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6061 if (reg
->regno
== hard_regno
)
6066 if (insn
!= NEXT_INSN (to
))
6068 if (split_reg (TRUE
, hard_regno
, from
, NULL
, to
))
6074 /* Recognize that we need a split transformation for insn INSN, which
6075 defines or uses REGNO in its insn biggest MODE (we use it only if
6076 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
6077 hard registers which might be used for reloads since the EBB end.
6078 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
6079 uid before starting INSN processing. Return true if we succeed in
6080 such transformation. */
6082 split_if_necessary (int regno
, machine_mode mode
,
6083 HARD_REG_SET potential_reload_hard_regs
,
6084 bool before_p
, rtx_insn
*insn
, int max_uid
)
6088 rtx next_usage_insns
;
6090 if (regno
< FIRST_PSEUDO_REGISTER
)
6091 nregs
= hard_regno_nregs (regno
, mode
);
6092 for (i
= 0; i
< nregs
; i
++)
6093 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
6094 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
6095 /* To avoid processing the register twice or more. */
6096 && ((GET_CODE (next_usage_insns
) != INSN_LIST
6097 && INSN_UID (next_usage_insns
) < max_uid
)
6098 || (GET_CODE (next_usage_insns
) == INSN_LIST
6099 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
6100 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
6101 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
6106 /* Return TRUE if rtx X is considered as an invariant for
6109 invariant_p (const_rtx x
)
6116 if (side_effects_p (x
))
6119 code
= GET_CODE (x
);
6120 mode
= GET_MODE (x
);
6124 code
= GET_CODE (x
);
6125 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
6133 int i
, nregs
, regno
= REGNO (x
);
6135 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
6136 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
6137 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
6139 nregs
= hard_regno_nregs (regno
, mode
);
6140 for (i
= 0; i
< nregs
; i
++)
6141 if (! fixed_regs
[regno
+ i
]
6142 /* A hard register may be clobbered in the current insn
6143 but we can ignore this case because if the hard
6144 register is used it should be set somewhere after the
6146 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
6149 fmt
= GET_RTX_FORMAT (code
);
6150 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6154 if (! invariant_p (XEXP (x
, i
)))
6157 else if (fmt
[i
] == 'E')
6159 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6160 if (! invariant_p (XVECEXP (x
, i
, j
)))
6167 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6168 inheritance transformation (using dest_reg instead invariant in a
6169 subsequent insn). */
6171 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
6173 invariant_ptr_t invariant_ptr
;
6174 rtx_insn
*insn
, *new_insns
;
6175 rtx insn_set
, insn_reg
, new_reg
;
6177 bool succ_p
= false;
6178 int dst_regno
= REGNO (dst_reg
);
6179 machine_mode dst_mode
= GET_MODE (dst_reg
);
6180 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
6182 invariant_ptr
= insert_invariant (invariant_rtx
);
6183 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6185 /* We have a subsequent insn using the invariant. */
6186 insn_set
= single_set (insn
);
6187 lra_assert (insn_set
!= NULL
);
6188 insn_reg
= SET_DEST (insn_set
);
6189 lra_assert (REG_P (insn_reg
));
6190 insn_regno
= REGNO (insn_reg
);
6191 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6193 if (dst_mode
== GET_MODE (insn_reg
)
6194 /* We should consider only result move reg insns which are
6196 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6197 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6199 if (lra_dump_file
!= NULL
)
6200 fprintf (lra_dump_file
,
6201 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6202 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
, cl
, NULL
,
6203 "invariant inheritance");
6204 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6205 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6206 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6208 lra_emit_move (new_reg
, dst_reg
);
6209 new_insns
= get_insns ();
6211 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6212 "Add invariant inheritance<-original");
6214 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6215 new_insns
= get_insns ();
6217 lra_process_new_insns (insn
, NULL
, new_insns
,
6218 "Changing reload<-inheritance");
6219 lra_set_insn_deleted (insn
);
6221 if (lra_dump_file
!= NULL
)
6223 fprintf (lra_dump_file
,
6224 " Invariant inheritance reuse change %d (bb%d):\n",
6225 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6226 dump_insn_slim (lra_dump_file
, insn
);
6227 fprintf (lra_dump_file
,
6228 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6232 invariant_ptr
->insn
= curr_insn
;
6236 /* Check only registers living at the current program point in the
6238 static bitmap_head live_regs
;
6240 /* Update live info in EBB given by its HEAD and TAIL insns after
6241 inheritance/split transformation. The function removes dead moves
6244 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6249 rtx_insn
*prev_insn
;
6252 basic_block last_bb
, prev_bb
, curr_bb
;
6254 struct lra_insn_reg
*reg
;
6258 last_bb
= BLOCK_FOR_INSN (tail
);
6260 for (curr_insn
= tail
;
6261 curr_insn
!= PREV_INSN (head
);
6262 curr_insn
= prev_insn
)
6264 prev_insn
= PREV_INSN (curr_insn
);
6265 /* We need to process empty blocks too. They contain
6266 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6267 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6269 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6270 if (curr_bb
!= prev_bb
)
6272 if (prev_bb
!= NULL
)
6274 /* Update df_get_live_in (prev_bb): */
6275 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6276 if (bitmap_bit_p (&live_regs
, j
))
6277 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6279 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6281 if (curr_bb
!= last_bb
)
6283 /* Update df_get_live_out (curr_bb): */
6284 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6286 live_p
= bitmap_bit_p (&live_regs
, j
);
6288 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6289 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6295 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6297 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6301 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6303 if (! NONDEBUG_INSN_P (curr_insn
))
6305 curr_id
= lra_get_insn_recog_data (curr_insn
);
6306 curr_static_id
= curr_id
->insn_static_data
;
6308 if ((set
= single_set (curr_insn
)) != NULL_RTX
6309 && REG_P (SET_DEST (set
))
6310 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6311 && SET_DEST (set
) != pic_offset_table_rtx
6312 && bitmap_bit_p (&check_only_regs
, regno
)
6313 && ! bitmap_bit_p (&live_regs
, regno
))
6315 /* See which defined values die here. */
6316 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6317 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6318 bitmap_clear_bit (&live_regs
, reg
->regno
);
6319 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6320 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6321 bitmap_clear_bit (&live_regs
, reg
->regno
);
6322 if (curr_id
->arg_hard_regs
!= NULL
)
6323 /* Make clobbered argument hard registers die. */
6324 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6325 if (regno
>= FIRST_PSEUDO_REGISTER
)
6326 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6327 /* Mark each used value as live. */
6328 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6329 if (reg
->type
!= OP_OUT
6330 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6331 bitmap_set_bit (&live_regs
, reg
->regno
);
6332 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6333 if (reg
->type
!= OP_OUT
6334 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6335 bitmap_set_bit (&live_regs
, reg
->regno
);
6336 if (curr_id
->arg_hard_regs
!= NULL
)
6337 /* Make used argument hard registers live. */
6338 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6339 if (regno
< FIRST_PSEUDO_REGISTER
6340 && bitmap_bit_p (&check_only_regs
, regno
))
6341 bitmap_set_bit (&live_regs
, regno
);
6342 /* It is quite important to remove dead move insns because it
6343 means removing dead store. We don't need to process them for
6347 if (lra_dump_file
!= NULL
)
6349 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6350 dump_insn_slim (lra_dump_file
, curr_insn
);
6352 lra_set_insn_deleted (curr_insn
);
6357 /* The structure describes info to do an inheritance for the current
6358 insn. We need to collect such info first before doing the
6359 transformations because the transformations change the insn
6360 internal representation. */
6363 /* Original regno. */
6365 /* Subsequent insns which can inherit original reg value. */
6369 /* Array containing all info for doing inheritance from the current
6371 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6373 /* Number elements in the previous array. */
6374 static int to_inherit_num
;
6376 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6377 structure to_inherit. */
6379 add_to_inherit (int regno
, rtx insns
)
6383 for (i
= 0; i
< to_inherit_num
; i
++)
6384 if (to_inherit
[i
].regno
== regno
)
6386 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6387 to_inherit
[to_inherit_num
].regno
= regno
;
6388 to_inherit
[to_inherit_num
++].insns
= insns
;
6391 /* Return the last non-debug insn in basic block BB, or the block begin
6394 get_last_insertion_point (basic_block bb
)
6398 FOR_BB_INSNS_REVERSE (bb
, insn
)
6399 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6404 /* Set up RES by registers living on edges FROM except the edge (FROM,
6405 TO) or by registers set up in a jump insn in BB FROM. */
6407 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6410 struct lra_insn_reg
*reg
;
6414 lra_assert (to
!= NULL
);
6416 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6418 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6419 last
= get_last_insertion_point (from
);
6420 if (! JUMP_P (last
))
6422 curr_id
= lra_get_insn_recog_data (last
);
6423 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6424 if (reg
->type
!= OP_IN
)
6425 bitmap_set_bit (res
, reg
->regno
);
6428 /* Used as a temporary results of some bitmap calculations. */
6429 static bitmap_head temp_bitmap
;
6431 /* We split for reloads of small class of hard regs. The following
6432 defines how many hard regs the class should have to be qualified as
6433 small. The code is mostly oriented to x86/x86-64 architecture
6434 where some insns need to use only specific register or pair of
6435 registers and these register can live in RTL explicitly, e.g. for
6436 parameter passing. */
6437 static const int max_small_class_regs_num
= 2;
6439 /* Do inheritance/split transformations in EBB starting with HEAD and
6440 finishing on TAIL. We process EBB insns in the reverse order.
6441 Return true if we did any inheritance/split transformation in the
6444 We should avoid excessive splitting which results in worse code
6445 because of inaccurate cost calculations for spilling new split
6446 pseudos in such case. To achieve this we do splitting only if
6447 register pressure is high in given basic block and there are reload
6448 pseudos requiring hard registers. We could do more register
6449 pressure calculations at any given program point to avoid necessary
6450 splitting even more but it is to expensive and the current approach
6451 works well enough. */
6453 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6455 int i
, src_regno
, dst_regno
, nregs
;
6456 bool change_p
, succ_p
, update_reloads_num_p
;
6457 rtx_insn
*prev_insn
, *last_insn
;
6458 rtx next_usage_insns
, curr_set
;
6460 struct lra_insn_reg
*reg
;
6461 basic_block last_processed_bb
, curr_bb
= NULL
;
6462 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6466 bool head_p
, after_p
;
6469 curr_usage_insns_check
++;
6470 clear_invariants ();
6471 reloads_num
= calls_num
= 0;
6472 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6473 last_call_for_abi
[i
] = 0;
6474 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6475 bitmap_clear (&check_only_regs
);
6476 bitmap_clear (&invalid_invariant_regs
);
6477 last_processed_bb
= NULL
;
6478 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6479 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6480 /* We don't process new insns generated in the loop. */
6481 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6483 prev_insn
= PREV_INSN (curr_insn
);
6484 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6485 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6486 if (last_processed_bb
!= curr_bb
)
6488 /* We are at the end of BB. Add qualified living
6489 pseudos for potential splitting. */
6490 to_process
= df_get_live_out (curr_bb
);
6491 if (last_processed_bb
!= NULL
)
6493 /* We are somewhere in the middle of EBB. */
6494 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6496 to_process
= &temp_bitmap
;
6498 last_processed_bb
= curr_bb
;
6499 last_insn
= get_last_insertion_point (curr_bb
);
6500 after_p
= (! JUMP_P (last_insn
)
6501 && (! CALL_P (last_insn
)
6502 || (find_reg_note (last_insn
,
6503 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6504 && ! SIBLING_CALL_P (last_insn
))));
6505 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6506 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6508 if ((int) j
>= lra_constraint_new_regno_start
)
6510 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6512 if (j
< FIRST_PSEUDO_REGISTER
)
6513 SET_HARD_REG_BIT (live_hard_regs
, j
);
6515 add_to_hard_reg_set (&live_hard_regs
,
6516 PSEUDO_REGNO_MODE (j
),
6518 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6522 src_regno
= dst_regno
= -1;
6523 curr_set
= single_set (curr_insn
);
6524 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6525 dst_regno
= REGNO (SET_DEST (curr_set
));
6526 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6527 src_regno
= REGNO (SET_SRC (curr_set
));
6528 update_reloads_num_p
= true;
6529 if (src_regno
< lra_constraint_new_regno_start
6530 && src_regno
>= FIRST_PSEUDO_REGISTER
6531 && reg_renumber
[src_regno
] < 0
6532 && dst_regno
>= lra_constraint_new_regno_start
6533 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6535 /* 'reload_pseudo <- original_pseudo'. */
6536 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6538 update_reloads_num_p
= false;
6540 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6541 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6542 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6543 curr_insn
, next_usage_insns
);
6547 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6548 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6549 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6551 else if (src_regno
< 0
6552 && dst_regno
>= lra_constraint_new_regno_start
6553 && invariant_p (SET_SRC (curr_set
))
6554 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6555 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6556 && ! bitmap_bit_p (&invalid_invariant_regs
,
6557 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6559 /* 'reload_pseudo <- invariant'. */
6560 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6562 update_reloads_num_p
= false;
6563 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6565 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6566 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6568 else if (src_regno
>= lra_constraint_new_regno_start
6569 && dst_regno
< lra_constraint_new_regno_start
6570 && dst_regno
>= FIRST_PSEUDO_REGISTER
6571 && reg_renumber
[dst_regno
] < 0
6572 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6573 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6574 && (next_usage_insns
6575 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6577 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6579 update_reloads_num_p
= false;
6580 /* 'original_pseudo <- reload_pseudo'. */
6581 if (! JUMP_P (curr_insn
)
6582 && inherit_reload_reg (true, dst_regno
, cl
,
6583 curr_insn
, next_usage_insns
))
6586 usage_insns
[dst_regno
].check
= 0;
6587 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6588 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6590 else if (INSN_P (curr_insn
))
6593 int max_uid
= get_max_uid ();
6595 curr_id
= lra_get_insn_recog_data (curr_insn
);
6596 curr_static_id
= curr_id
->insn_static_data
;
6598 /* Process insn definitions. */
6599 for (iter
= 0; iter
< 2; iter
++)
6600 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6603 if (reg
->type
!= OP_IN
6604 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6606 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6607 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6608 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6609 && (next_usage_insns
6610 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6612 struct lra_insn_reg
*r
;
6614 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6615 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6617 /* Don't do inheritance if the pseudo is also
6618 used in the insn. */
6620 /* We cannot do inheritance right now
6621 because the current insn reg info (chain
6622 regs) can change after that. */
6623 add_to_inherit (dst_regno
, next_usage_insns
);
6625 /* We cannot process one reg twice here because of
6626 usage_insns invalidation. */
6627 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6628 || reg_renumber
[dst_regno
] >= 0)
6629 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6633 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6634 potential_reload_hard_regs
,
6635 false, curr_insn
, max_uid
))
6637 CLEAR_HARD_REG_SET (s
);
6638 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6639 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6641 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6642 reg_renumber
[dst_regno
]);
6643 live_hard_regs
&= ~s
;
6644 potential_reload_hard_regs
&= ~s
;
6646 /* We should invalidate potential inheritance or
6647 splitting for the current insn usages to the next
6648 usage insns (see code below) as the output pseudo
6650 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6651 && reg_renumber
[dst_regno
] < 0)
6652 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6653 && (dst_regno
< FIRST_PSEUDO_REGISTER
6654 || reg_renumber
[dst_regno
] >= 0)))
6656 /* Invalidate and mark definitions. */
6657 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6658 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6661 nregs
= hard_regno_nregs (dst_regno
,
6663 for (i
= 0; i
< nregs
; i
++)
6664 usage_insns
[dst_regno
+ i
].check
6665 = -(int) INSN_UID (curr_insn
);
6669 /* Process clobbered call regs. */
6670 if (curr_id
->arg_hard_regs
!= NULL
)
6671 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6672 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6673 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6674 = -(int) INSN_UID (curr_insn
);
6675 if (! JUMP_P (curr_insn
))
6676 for (i
= 0; i
< to_inherit_num
; i
++)
6677 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6678 ALL_REGS
, curr_insn
,
6679 to_inherit
[i
].insns
))
6681 if (CALL_P (curr_insn
))
6683 rtx cheap
, pat
, dest
;
6685 int regno
, hard_regno
;
6688 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6689 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6690 full_and_partial_call_clobbers
6691 |= callee_abi
.full_and_partial_reg_clobbers ();
6692 if ((cheap
= find_reg_note (curr_insn
,
6693 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6694 && ((cheap
= XEXP (cheap
, 0)), true)
6695 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6696 && (hard_regno
= reg_renumber
[regno
]) >= 0
6697 && usage_insns
[regno
].check
== curr_usage_insns_check
6698 /* If there are pending saves/restores, the
6699 optimization is not worth. */
6700 && usage_insns
[regno
].calls_num
== calls_num
- 1
6701 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6703 /* Restore the pseudo from the call result as
6704 REG_RETURNED note says that the pseudo value is
6705 in the call result and the pseudo is an argument
6707 pat
= PATTERN (curr_insn
);
6708 if (GET_CODE (pat
) == PARALLEL
)
6709 pat
= XVECEXP (pat
, 0, 0);
6710 dest
= SET_DEST (pat
);
6711 /* For multiple return values dest is PARALLEL.
6712 Currently we handle only single return value case. */
6716 emit_move_insn (cheap
, copy_rtx (dest
));
6717 restore
= get_insns ();
6719 lra_process_new_insns (curr_insn
, NULL
, restore
,
6720 "Inserting call parameter restore");
6721 /* We don't need to save/restore of the pseudo from
6723 usage_insns
[regno
].calls_num
= calls_num
;
6724 remove_from_hard_reg_set
6725 (&full_and_partial_call_clobbers
,
6726 GET_MODE (cheap
), hard_regno
);
6727 bitmap_set_bit (&check_only_regs
, regno
);
6732 /* Process insn usages. */
6733 for (iter
= 0; iter
< 2; iter
++)
6734 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6737 if ((reg
->type
!= OP_OUT
6738 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6739 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6741 if (src_regno
>= FIRST_PSEUDO_REGISTER
6742 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6744 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6745 && (next_usage_insns
6746 = usage_insns
[src_regno
].insns
) != NULL_RTX
6747 && NONDEBUG_INSN_P (curr_insn
))
6748 add_to_inherit (src_regno
, next_usage_insns
);
6749 else if (usage_insns
[src_regno
].check
6750 != -(int) INSN_UID (curr_insn
))
6751 /* Add usages but only if the reg is not set up
6752 in the same insn. */
6753 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6755 else if (src_regno
< FIRST_PSEUDO_REGISTER
6756 || reg_renumber
[src_regno
] >= 0)
6759 rtx_insn
*use_insn
= curr_insn
;
6761 before_p
= (JUMP_P (curr_insn
)
6762 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6763 if (NONDEBUG_INSN_P (curr_insn
)
6764 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6765 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6766 potential_reload_hard_regs
,
6767 before_p
, curr_insn
, max_uid
))
6770 check_and_force_assignment_correctness_p
= true;
6773 usage_insns
[src_regno
].check
= 0;
6775 use_insn
= PREV_INSN (curr_insn
);
6777 if (NONDEBUG_INSN_P (curr_insn
))
6779 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6780 add_to_hard_reg_set (&live_hard_regs
,
6781 reg
->biggest_mode
, src_regno
);
6783 add_to_hard_reg_set (&live_hard_regs
,
6784 PSEUDO_REGNO_MODE (src_regno
),
6785 reg_renumber
[src_regno
]);
6787 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
6788 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6791 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
6792 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
6796 /* Process used call regs. */
6797 if (curr_id
->arg_hard_regs
!= NULL
)
6798 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6799 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6801 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6802 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6804 for (i
= 0; i
< to_inherit_num
; i
++)
6806 src_regno
= to_inherit
[i
].regno
;
6807 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6808 curr_insn
, to_inherit
[i
].insns
))
6811 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6814 if (update_reloads_num_p
6815 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6818 if ((REG_P (SET_DEST (curr_set
))
6819 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6820 && reg_renumber
[regno
] < 0
6821 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6822 || (REG_P (SET_SRC (curr_set
))
6823 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6824 && reg_renumber
[regno
] < 0
6825 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6827 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6829 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6830 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6833 if (NONDEBUG_INSN_P (curr_insn
))
6837 /* Invalidate invariants with changed regs. */
6838 curr_id
= lra_get_insn_recog_data (curr_insn
);
6839 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6840 if (reg
->type
!= OP_IN
)
6842 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6843 bitmap_set_bit (&invalid_invariant_regs
,
6844 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6846 curr_static_id
= curr_id
->insn_static_data
;
6847 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6848 if (reg
->type
!= OP_IN
)
6849 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6850 if (curr_id
->arg_hard_regs
!= NULL
)
6851 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6852 if (regno
>= FIRST_PSEUDO_REGISTER
)
6853 bitmap_set_bit (&invalid_invariant_regs
,
6854 regno
- FIRST_PSEUDO_REGISTER
);
6856 /* We reached the start of the current basic block. */
6857 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6858 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6860 /* We reached the beginning of the current block -- do
6861 rest of spliting in the current BB. */
6862 to_process
= df_get_live_in (curr_bb
);
6863 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6865 /* We are somewhere in the middle of EBB. */
6866 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6867 curr_bb
, &temp_bitmap
);
6868 to_process
= &temp_bitmap
;
6871 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6873 if ((int) j
>= lra_constraint_new_regno_start
)
6875 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6876 && usage_insns
[j
].check
== curr_usage_insns_check
6877 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6879 if (need_for_split_p (potential_reload_hard_regs
, j
))
6881 if (lra_dump_file
!= NULL
&& head_p
)
6883 fprintf (lra_dump_file
,
6884 " ----------------------------------\n");
6887 if (split_reg (false, j
, bb_note (curr_bb
),
6888 next_usage_insns
, NULL
))
6891 usage_insns
[j
].check
= 0;
6899 /* This value affects EBB forming. If probability of edge from EBB to
6900 a BB is not greater than the following value, we don't add the BB
6902 #define EBB_PROBABILITY_CUTOFF \
6903 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
6905 /* Current number of inheritance/split iteration. */
6906 int lra_inheritance_iter
;
6908 /* Entry function for inheritance/split pass. */
6910 lra_inheritance (void)
6913 basic_block bb
, start_bb
;
6916 lra_inheritance_iter
++;
6917 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6919 timevar_push (TV_LRA_INHERITANCE
);
6920 if (lra_dump_file
!= NULL
)
6921 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6922 lra_inheritance_iter
);
6923 curr_usage_insns_check
= 0;
6924 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6925 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6926 usage_insns
[i
].check
= 0;
6927 bitmap_initialize (&check_only_regs
, ®_obstack
);
6928 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6929 bitmap_initialize (&live_regs
, ®_obstack
);
6930 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6931 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6932 FOR_EACH_BB_FN (bb
, cfun
)
6935 if (lra_dump_file
!= NULL
)
6936 fprintf (lra_dump_file
, "EBB");
6937 /* Form a EBB starting with BB. */
6938 bitmap_clear (&ebb_global_regs
);
6939 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6942 if (lra_dump_file
!= NULL
)
6943 fprintf (lra_dump_file
, " %d", bb
->index
);
6944 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6945 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6947 e
= find_fallthru_edge (bb
->succs
);
6950 if (e
->probability
.initialized_p ()
6951 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6955 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6956 if (lra_dump_file
!= NULL
)
6957 fprintf (lra_dump_file
, "\n");
6958 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6959 /* Remember that the EBB head and tail can change in
6961 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6963 bitmap_release (&ebb_global_regs
);
6964 bitmap_release (&temp_bitmap
);
6965 bitmap_release (&live_regs
);
6966 bitmap_release (&invalid_invariant_regs
);
6967 bitmap_release (&check_only_regs
);
6970 timevar_pop (TV_LRA_INHERITANCE
);
6975 /* This page contains code to undo failed inheritance/split
6978 /* Current number of iteration undoing inheritance/split. */
6979 int lra_undo_inheritance_iter
;
6981 /* Fix BB live info LIVE after removing pseudos created on pass doing
6982 inheritance/split which are REMOVED_PSEUDOS. */
6984 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6989 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6990 if (bitmap_clear_bit (live
, regno
)
6991 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6992 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6995 /* Return regno of the (subreg of) REG. Otherwise, return a negative
7000 if (GET_CODE (reg
) == SUBREG
)
7001 reg
= SUBREG_REG (reg
);
7007 /* Delete a move INSN with destination reg DREGNO and a previous
7008 clobber insn with the same regno. The inheritance/split code can
7009 generate moves with preceding clobber and when we delete such moves
7010 we should delete the clobber insn too to keep the correct life
7013 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
7015 rtx_insn
*prev_insn
= PREV_INSN (insn
);
7017 lra_set_insn_deleted (insn
);
7018 lra_assert (dregno
>= 0);
7019 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
7020 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
7021 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
7022 lra_set_insn_deleted (prev_insn
);
7025 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
7026 return true if we did any change. The undo transformations for
7027 inheritance looks like
7031 p <- i, i <- p, and i <- i3
7032 where p is original pseudo from which inheritance pseudo i was
7033 created, i and i3 are removed inheritance pseudos, i2 is another
7034 not removed inheritance pseudo. All split pseudos or other
7035 occurrences of removed inheritance pseudos are changed on the
7036 corresponding original pseudos.
7038 The function also schedules insns changed and created during
7039 inheritance/split pass for processing by the subsequent constraint
7042 remove_inheritance_pseudos (bitmap remove_pseudos
)
7045 int regno
, sregno
, prev_sregno
, dregno
;
7048 rtx_insn
*prev_insn
;
7049 bool change_p
, done_p
;
7051 change_p
= ! bitmap_empty_p (remove_pseudos
);
7052 /* We cannot finish the function right away if CHANGE_P is true
7053 because we need to marks insns affected by previous
7054 inheritance/split pass for processing by the subsequent
7056 FOR_EACH_BB_FN (bb
, cfun
)
7058 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
7059 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
7060 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
7062 if (! INSN_P (curr_insn
))
7065 sregno
= dregno
= -1;
7066 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
7067 && (set
= single_set (curr_insn
)) != NULL_RTX
)
7069 dregno
= get_regno (SET_DEST (set
));
7070 sregno
= get_regno (SET_SRC (set
));
7073 if (sregno
>= 0 && dregno
>= 0)
7075 if (bitmap_bit_p (remove_pseudos
, dregno
)
7076 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
7078 /* invariant inheritance pseudo <- original pseudo */
7079 if (lra_dump_file
!= NULL
)
7081 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
7082 dump_insn_slim (lra_dump_file
, curr_insn
);
7083 fprintf (lra_dump_file
, "\n");
7085 delete_move_and_clobber (curr_insn
, dregno
);
7088 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7089 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
7091 /* reload pseudo <- invariant inheritance pseudo */
7093 /* We cannot just change the source. It might be
7094 an insn different from the move. */
7095 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
7096 rtx_insn
*new_insns
= get_insns ();
7098 lra_assert (single_set (new_insns
) != NULL
7099 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
7100 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
7101 "Changing reload<-invariant inheritance");
7102 delete_move_and_clobber (curr_insn
, dregno
);
7105 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
7106 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
7107 || (bitmap_bit_p (remove_pseudos
, dregno
)
7108 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7109 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7110 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
7111 || (bitmap_bit_p (remove_pseudos
, dregno
)
7112 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
7113 /* One of the following cases:
7114 original <- removed inheritance pseudo
7115 removed inherit pseudo <- another removed inherit pseudo
7116 removed inherit pseudo <- original pseudo
7118 removed_split_pseudo <- original_reg
7119 original_reg <- removed_split_pseudo */
7121 if (lra_dump_file
!= NULL
)
7123 fprintf (lra_dump_file
, " Removing %s:\n",
7124 bitmap_bit_p (&lra_split_regs
, sregno
)
7125 || bitmap_bit_p (&lra_split_regs
, dregno
)
7126 ? "split" : "inheritance");
7127 dump_insn_slim (lra_dump_file
, curr_insn
);
7129 delete_move_and_clobber (curr_insn
, dregno
);
7132 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7133 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
7135 /* Search the following pattern:
7136 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
7137 original_pseudo <- inherit_or_split_pseudo1
7138 where the 2nd insn is the current insn and
7139 inherit_or_split_pseudo2 is not removed. If it is found,
7140 change the current insn onto:
7141 original_pseudo <- inherit_or_split_pseudo2. */
7142 for (prev_insn
= PREV_INSN (curr_insn
);
7143 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
7144 prev_insn
= PREV_INSN (prev_insn
))
7146 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
7147 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
7148 /* There should be no subregs in insn we are
7149 searching because only the original reg might
7150 be in subreg when we changed the mode of
7151 load/store for splitting. */
7152 && REG_P (SET_DEST (prev_set
))
7153 && REG_P (SET_SRC (prev_set
))
7154 && (int) REGNO (SET_DEST (prev_set
)) == sregno
7155 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
7156 >= FIRST_PSEUDO_REGISTER
)
7157 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
7159 /* As we consider chain of inheritance or
7160 splitting described in above comment we should
7161 check that sregno and prev_sregno were
7162 inheritance/split pseudos created from the
7163 same original regno. */
7164 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7165 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7166 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
7167 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
7169 lra_assert (GET_MODE (SET_SRC (prev_set
))
7170 == GET_MODE (regno_reg_rtx
[sregno
]));
7171 /* Although we have a single set, the insn can
7172 contain more one sregno register occurrence
7173 as a source. Change all occurrences. */
7174 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
7177 /* As we are finishing with processing the insn
7178 here, check the destination too as it might
7179 inheritance pseudo for another pseudo. */
7180 if (bitmap_bit_p (remove_pseudos
, dregno
)
7181 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7183 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7185 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7186 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7188 SET_DEST (set
) = restore_rtx
;
7190 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7191 lra_set_used_insn_alternative_by_uid
7192 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7194 if (lra_dump_file
!= NULL
)
7196 fprintf (lra_dump_file
, " Change reload insn:\n");
7197 dump_insn_slim (lra_dump_file
, curr_insn
);
7204 struct lra_insn_reg
*reg
;
7205 bool restored_regs_p
= false;
7206 bool kept_regs_p
= false;
7208 curr_id
= lra_get_insn_recog_data (curr_insn
);
7209 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7212 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7213 if (restore_rtx
!= NULL_RTX
)
7215 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7217 lra_substitute_pseudo_within_insn
7218 (curr_insn
, regno
, restore_rtx
, false);
7219 restored_regs_p
= true;
7225 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7227 /* The instruction has changed since the previous
7228 constraints pass. */
7229 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7230 lra_set_used_insn_alternative_by_uid
7231 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7233 else if (restored_regs_p
)
7234 /* The instruction has been restored to the form that
7235 it had during the previous constraints pass. */
7236 lra_update_insn_regno_info (curr_insn
);
7237 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7239 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7240 dump_insn_slim (lra_dump_file
, curr_insn
);
7248 /* If optional reload pseudos failed to get a hard register or was not
7249 inherited, it is better to remove optional reloads. We do this
7250 transformation after undoing inheritance to figure out necessity to
7251 remove optional reloads easier. Return true if we do any
7254 undo_optional_reloads (void)
7256 bool change_p
, keep_p
;
7257 unsigned int regno
, uid
;
7258 bitmap_iterator bi
, bi2
;
7261 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7263 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7264 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7267 /* Keep optional reloads from previous subpasses. */
7268 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7269 /* If the original pseudo changed its allocation, just
7270 removing the optional pseudo is dangerous as the original
7271 pseudo will have longer live range. */
7272 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7274 else if (reg_renumber
[regno
] >= 0)
7275 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7277 insn
= lra_insn_recog_data
[uid
]->insn
;
7278 if ((set
= single_set (insn
)) == NULL_RTX
)
7280 src
= SET_SRC (set
);
7281 dest
= SET_DEST (set
);
7282 if ((! REG_P (src
) && ! SUBREG_P (src
))
7283 || (! REG_P (dest
) && ! SUBREG_P (dest
)))
7285 if (get_regno (dest
) == (int) regno
7286 /* Ignore insn for optional reloads itself. */
7287 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7289 /* Check only inheritance on last inheritance pass. */
7290 && get_regno (src
) >= new_regno_start
7291 /* Check that the optional reload was inherited. */
7292 && bitmap_bit_p (&lra_inheritance_pseudos
, get_regno (src
)))
7300 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7301 if (lra_dump_file
!= NULL
)
7302 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7305 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7306 auto_bitmap
insn_bitmap (®_obstack
);
7307 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7309 if (lra_dump_file
!= NULL
)
7310 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7311 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7312 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7314 /* We may have already removed a clobber. */
7315 if (!lra_insn_recog_data
[uid
])
7317 insn
= lra_insn_recog_data
[uid
]->insn
;
7318 if ((set
= single_set (insn
)) != NULL_RTX
)
7320 src
= SET_SRC (set
);
7321 dest
= SET_DEST (set
);
7322 if ((REG_P (src
) || SUBREG_P (src
))
7323 && (REG_P (dest
) || SUBREG_P (dest
))
7324 && ((get_regno (src
) == (int) regno
7325 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7326 == get_regno (dest
)))
7327 || (get_regno (dest
) == (int) regno
7328 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7329 == get_regno (src
)))))
7331 if (lra_dump_file
!= NULL
)
7333 fprintf (lra_dump_file
, " Deleting move %u\n",
7335 dump_insn_slim (lra_dump_file
, insn
);
7337 delete_move_and_clobber (insn
, get_regno (dest
));
7340 /* We should not worry about generation memory-memory
7341 moves here as if the corresponding inheritance did
7342 not work (inheritance pseudo did not get a hard reg),
7343 we remove the inheritance pseudo and the optional
7346 if (GET_CODE (PATTERN (insn
)) == CLOBBER
7347 && REG_P (SET_DEST (insn
))
7348 && get_regno (SET_DEST (insn
)) == (int) regno
)
7349 /* Refuse to remap clobbers to preexisting pseudos. */
7351 lra_substitute_pseudo_within_insn
7352 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7353 lra_update_insn_regno_info (insn
);
7354 if (lra_dump_file
!= NULL
)
7356 fprintf (lra_dump_file
,
7357 " Restoring original insn:\n");
7358 dump_insn_slim (lra_dump_file
, insn
);
7362 /* Clear restore_regnos. */
7363 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7364 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7368 /* Entry function for undoing inheritance/split transformation. Return true
7369 if we did any RTL change in this pass. */
7371 lra_undo_inheritance (void)
7375 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7380 lra_undo_inheritance_iter
++;
7381 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7383 if (lra_dump_file
!= NULL
)
7384 fprintf (lra_dump_file
,
7385 "\n********** Undoing inheritance #%d: **********\n\n",
7386 lra_undo_inheritance_iter
);
7387 auto_bitmap
remove_pseudos (®_obstack
);
7388 n_inherit
= n_all_inherit
= 0;
7389 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7390 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7393 if (reg_renumber
[regno
] < 0
7394 /* If the original pseudo changed its allocation, just
7395 removing inheritance is dangerous as for changing
7396 allocation we used shorter live-ranges. */
7397 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7398 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7399 bitmap_set_bit (remove_pseudos
, regno
);
7403 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7404 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7405 n_inherit
, n_all_inherit
,
7406 (double) n_inherit
/ n_all_inherit
* 100);
7407 n_split
= n_all_split
= 0;
7408 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7409 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7411 int restore_regno
= REGNO (restore_rtx
);
7414 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7415 ? reg_renumber
[restore_regno
] : restore_regno
);
7416 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7417 bitmap_set_bit (remove_pseudos
, regno
);
7421 if (lra_dump_file
!= NULL
)
7422 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7423 regno
, restore_regno
);
7426 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7427 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7428 n_split
, n_all_split
,
7429 (double) n_split
/ n_all_split
* 100);
7430 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7431 /* Clear restore_regnos. */
7432 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7433 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7434 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7435 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7436 change_p
= undo_optional_reloads () || change_p
;