1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; TODO: Add a comment here.
23 (define_predicate "trapping_target_operand"
24 (match_code "if_then_else")
26 rtx cond, mem, res, tar, and_expr;
28 if (GET_MODE (op) != PDImode)
34 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
37 if (!rtx_equal_p (XEXP (mem, 0), tar)
38 || GET_MODE (tar) != Pmode)
40 if (GET_CODE (cond) == CONST)
42 cond = XEXP (cond, 0);
43 if (!satisfies_constraint_Csy (tar))
45 if (GET_CODE (tar) == CONST)
48 else if (!arith_reg_operand (tar, VOIDmode)
49 && ! satisfies_constraint_Csy (tar))
51 if (GET_CODE (cond) != EQ)
53 and_expr = XEXP (cond, 0);
54 return (GET_CODE (and_expr) == AND
55 && rtx_equal_p (XEXP (and_expr, 0), tar)
56 && CONST_INT_P (XEXP (and_expr, 1))
57 && CONST_INT_P (XEXP (cond, 1))
58 && INTVAL (XEXP (and_expr, 1)) == 3
59 && INTVAL (XEXP (cond, 1)) == 3);
62 ;; TODO: Add a comment here.
64 (define_predicate "and_operand"
65 (match_code "subreg,reg,const_int")
67 if (logical_operand (op, mode))
70 /* Check mshflo.l / mshflhi.l opportunities. */
73 && satisfies_constraint_J16 (op))
79 ;; Like arith_reg_dest, but this predicate is defined with
80 ;; define_special_predicate, not define_predicate.
82 (define_special_predicate "any_arith_reg_dest"
83 (match_code "subreg,reg")
85 return arith_reg_dest (op, mode);
88 ;; Like register_operand, but this predicate is defined with
89 ;; define_special_predicate, not define_predicate.
91 (define_special_predicate "any_register_operand"
92 (match_code "subreg,reg")
94 return register_operand (op, mode);
97 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
99 (define_predicate "arith_operand"
100 (match_code "subreg,reg,const_int,truncate")
102 if (arith_reg_operand (op, mode))
107 /* FIXME: We should be checking whether the CONST_INT fits in a
108 signed 16-bit here, but this causes reload_cse to crash when
109 attempting to transform a sequence of two 64-bit sets of the
110 same register from literal constants into a set and an add,
111 when the difference is too wide for an add. */
113 || satisfies_constraint_Css (op))
115 else if (GET_CODE (op) == TRUNCATE
116 && REG_P (XEXP (op, 0))
117 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
118 && (mode == VOIDmode || mode == GET_MODE (op))
119 && (GET_MODE_SIZE (GET_MODE (op))
120 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
121 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
122 || GET_MODE_SIZE (GET_MODE (op)) == 4))
123 return register_operand (XEXP (op, 0), VOIDmode);
127 else if (satisfies_constraint_I08 (op))
133 ;; Like above, but for DImode destinations: forbid paradoxical DImode
134 ;; subregs, because this would lead to missing sign extensions when
135 ;; truncating from DImode to SImode.
137 (define_predicate "arith_reg_dest"
138 (match_code "subreg,reg")
140 if (mode == DImode && GET_CODE (op) == SUBREG
141 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
144 return arith_reg_operand (op, mode);
147 ;; Returns 1 if OP is a normal arithmetic register.
149 (define_predicate "arith_reg_operand"
150 (match_code "subreg,reg,sign_extend")
152 if (register_operand (op, mode))
158 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
159 regno = REGNO (SUBREG_REG (op));
163 return (regno != T_REG && regno != PR_REG
164 && ! TARGET_REGISTER_P (regno)
165 && (regno != FPUL_REG || TARGET_SH4)
166 && regno != MACH_REG && regno != MACL_REG);
168 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
169 We allow SImode here, as not using an FP register is just a matter of
170 proper register allocation. */
172 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
173 && GET_MODE (XEXP (op, 0)) == SImode
174 && GET_CODE (XEXP (op, 0)) != SUBREG)
175 return register_operand (XEXP (op, 0), VOIDmode);
176 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
177 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
178 && GET_MODE (XEXP (op, 0)) == HImode
179 && REG_P (XEXP (op, 0))
180 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
181 return register_operand (XEXP (op, 0), VOIDmode);
183 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
184 && GET_CODE (op) == SUBREG
185 && GET_MODE (SUBREG_REG (op)) == DImode
186 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
187 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
188 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
189 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
193 ;; Returns 1 if OP is a valid source operand for a compare insn.
195 (define_predicate "arith_reg_or_0_operand"
196 (match_code "subreg,reg,const_int,const_vector")
198 if (arith_reg_operand (op, mode))
201 if (satisfies_constraint_Z (op))
207 ;; TODO: Add a comment here.
209 (define_predicate "binary_float_operator"
210 (and (match_code "plus,minus,mult,div")
211 (match_test "GET_MODE (op) == mode")))
213 ;; TODO: Add a comment here.
215 (define_predicate "binary_logical_operator"
216 (and (match_code "and,ior,xor")
217 (match_test "GET_MODE (op) == mode")))
219 ;; Return 1 of OP is an address suitable for a cache manipulation operation.
220 ;; MODE has the meaning as in address_operand.
222 (define_special_predicate "cache_address_operand"
223 (match_code "plus,reg")
225 if (GET_CODE (op) == PLUS)
227 if (!REG_P (XEXP (op, 0)))
229 if (!CONST_INT_P (XEXP (op, 1))
230 || (INTVAL (XEXP (op, 1)) & 31))
233 else if (!REG_P (op))
235 return address_operand (op, mode);
238 ;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
240 (define_predicate "cmp_operand"
241 (match_code "subreg,reg,const_int")
243 if (satisfies_constraint_N (op))
246 && mode != DImode && GET_CODE (op) == SUBREG
247 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
249 return arith_reg_operand (op, mode);
252 ;; TODO: Add a comment here.
254 (define_predicate "cmpsi_operand"
255 (match_code "subreg,reg,const_int")
257 if (REG_P (op) && REGNO (op) == T_REG
258 && GET_MODE (op) == SImode
261 return arith_operand (op, mode);
264 ;; TODO: Add a comment here.
266 (define_predicate "commutative_float_operator"
267 (and (match_code "plus,mult")
268 (match_test "GET_MODE (op) == mode")))
270 ;; TODO: Add a comment here.
272 (define_predicate "equality_comparison_operator"
273 (match_code "eq,ne"))
275 ;; TODO: Add a comment here.
277 (define_predicate "extend_reg_operand"
278 (match_code "subreg,reg,truncate")
280 return (GET_CODE (op) == TRUNCATE
282 : arith_reg_operand) (op, mode);
285 ;; TODO: Add a comment here.
287 (define_predicate "extend_reg_or_0_operand"
288 (match_code "subreg,reg,truncate,const_int")
290 return (GET_CODE (op) == TRUNCATE
292 : arith_reg_or_0_operand) (op, mode);
295 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
297 (define_predicate "ext_dest_operand"
298 (match_code "subreg,reg")
300 return arith_reg_operand (op, mode);
303 ;; TODO: Add a comment here.
305 (define_predicate "fp_arith_reg_dest"
306 (match_code "subreg,reg")
308 if (mode == DImode && GET_CODE (op) == SUBREG
309 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
311 return fp_arith_reg_operand (op, mode);
314 ;; TODO: Add a comment here.
316 (define_predicate "fp_arith_reg_operand"
317 (match_code "subreg,reg")
319 if (register_operand (op, mode))
325 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
326 regno = REGNO (SUBREG_REG (op));
330 return (regno >= FIRST_PSEUDO_REGISTER
331 || FP_REGISTER_P (regno));
336 ;; TODO: Add a comment here.
338 (define_predicate "fpscr_operand"
342 && (REGNO (op) == FPSCR_REG
343 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
344 && !(reload_in_progress || reload_completed)))
345 && GET_MODE (op) == PSImode);
348 ;; TODO: Add a comment here.
350 (define_predicate "fpul_operand"
354 return fp_arith_reg_operand (op, mode);
357 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
358 && GET_MODE (op) == mode);
361 ;; TODO: Add a comment here.
363 (define_predicate "general_extend_operand"
364 (match_code "subreg,reg,mem,truncate")
366 return (GET_CODE (op) == TRUNCATE
368 : nonimmediate_operand) (op, mode);
371 ;; Returns 1 if OP can be source of a simple move operation. Same as
372 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
373 ;; are subregs of system registers.
375 (define_predicate "general_movsrc_operand"
376 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
380 rtx inside = XEXP (op, 0);
381 if (GET_CODE (inside) == CONST)
382 inside = XEXP (inside, 0);
384 if (GET_CODE (inside) == LABEL_REF)
387 if (GET_CODE (inside) == PLUS
388 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
389 && CONST_INT_P (XEXP (inside, 1)))
392 /* Only post inc allowed. */
393 if (GET_CODE (inside) == PRE_DEC)
397 if ((mode == QImode || mode == HImode)
398 && mode == GET_MODE (op)
400 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
402 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
404 if (GET_CODE (x) == PLUS
405 && REG_P (XEXP (x, 0))
406 && CONST_INT_P (XEXP (x, 1)))
407 return sh_legitimate_index_p (mode, XEXP (x, 1));
411 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
412 && sh_rep_vec (op, mode))
414 if (TARGET_SHMEDIA && 1
415 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
416 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
417 /* FIXME */ abort (); /* return 1; */
418 return general_operand (op, mode);
421 ;; Returns 1 if OP can be a destination of a move. Same as
422 ;; general_operand, but no preinc allowed.
424 (define_predicate "general_movdst_operand"
425 (match_code "subreg,reg,mem")
427 /* Only pre dec allowed. */
428 if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
430 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
431 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
432 && ! (high_life_started || reload_completed))
435 if ((mode == QImode || mode == HImode)
436 && mode == GET_MODE (op)
438 || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
440 rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
442 if (GET_CODE (x) == PLUS
443 && REG_P (XEXP (x, 0))
444 && CONST_INT_P (XEXP (x, 1)))
445 return sh_legitimate_index_p (mode, XEXP (x, 1));
448 return general_operand (op, mode);
452 ;; Returns 1 if OP is a POST_INC on stack pointer register.
454 (define_predicate "sh_no_delay_pop_operand"
458 inside = XEXP (op, 0);
460 if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
461 && GET_CODE (inside) == POST_INC
462 && GET_CODE (XEXP (inside, 0)) == REG
463 && REGNO (XEXP (inside, 0)) == SP_REG)
470 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
472 (define_predicate "unaligned_load_operand"
477 if (!MEM_P (op) || GET_MODE (op) != mode)
480 inside = XEXP (op, 0);
482 if (GET_CODE (inside) == POST_INC)
483 inside = XEXP (inside, 0);
491 ;; TODO: Add a comment here.
493 (define_predicate "greater_comparison_operator"
494 (match_code "gt,ge,gtu,geu"))
496 ;; TODO: Add a comment here.
498 (define_predicate "inqhi_operand"
499 (match_code "truncate")
501 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
504 /* Can't use true_regnum here because copy_cost wants to know about
505 SECONDARY_INPUT_RELOAD_CLASS. */
506 return REG_P (op) && FP_REGISTER_P (REGNO (op));
509 ;; TODO: Add a comment here.
511 (define_special_predicate "int_gpr_dest"
512 (match_code "subreg,reg")
514 enum machine_mode op_mode = GET_MODE (op);
516 if (GET_MODE_CLASS (op_mode) != MODE_INT
517 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
519 if (! reload_completed)
521 return true_regnum (op) <= LAST_GENERAL_REG;
524 ;; TODO: Add a comment here.
526 (define_predicate "less_comparison_operator"
527 (match_code "lt,le,ltu,leu"))
529 ;; Returns 1 if OP is a valid source operand for a logical operation.
531 (define_predicate "logical_operand"
532 (match_code "subreg,reg,const_int")
535 && mode != DImode && GET_CODE (op) == SUBREG
536 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
539 if (arith_reg_operand (op, mode))
544 if (satisfies_constraint_I10 (op))
549 else if (satisfies_constraint_K08 (op))
555 ;; TODO: Add a comment here.
557 (define_predicate "logical_operator"
558 (match_code "and,ior,xor"))
560 ;; Like arith_reg_operand, but for register source operands of narrow
561 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
563 (define_predicate "logical_reg_operand"
564 (match_code "subreg,reg")
567 && GET_CODE (op) == SUBREG
568 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
571 return arith_reg_operand (op, mode);
574 ;; TODO: Add a comment here.
576 (define_predicate "mextr_bit_offset"
577 (match_code "const_int")
581 if (!CONST_INT_P (op))
584 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
587 ;; TODO: Add a comment here.
589 (define_predicate "minuend_operand"
590 (match_code "subreg,reg,truncate,const_int")
592 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
595 ;; TODO: Add a comment here.
597 (define_predicate "noncommutative_float_operator"
598 (and (match_code "minus,div")
599 (match_test "GET_MODE (op) == mode")))
601 ;; UNORDERED is only supported on SHMEDIA.
603 (define_predicate "sh_float_comparison_operator"
604 (ior (match_operand 0 "ordered_comparison_operator")
605 (and (match_test "TARGET_SHMEDIA")
606 (match_code "unordered"))))
608 (define_predicate "shmedia_cbranch_comparison_operator"
609 (ior (match_operand 0 "equality_comparison_operator")
610 (match_operand 0 "greater_comparison_operator")))
612 ;; TODO: Add a comment here.
614 (define_predicate "sh_const_vec"
615 (match_code "const_vector")
619 if (GET_CODE (op) != CONST_VECTOR
620 || (GET_MODE (op) != mode && mode != VOIDmode))
622 i = XVECLEN (op, 0) - 1;
624 if (!CONST_INT_P (XVECEXP (op, 0, i)))
629 ;; Determine if OP is a constant vector matching MODE with only one
630 ;; element that is not a sign extension. Two byte-sized elements
633 (define_predicate "sh_1el_vec"
634 (match_code "const_vector")
637 int i, last, least, sign_ix;
640 if (GET_CODE (op) != CONST_VECTOR
641 || (GET_MODE (op) != mode && mode != VOIDmode))
643 /* Determine numbers of last and of least significant elements. */
644 last = XVECLEN (op, 0) - 1;
645 least = TARGET_LITTLE_ENDIAN ? 0 : last;
646 if (!CONST_INT_P (XVECEXP (op, 0, least)))
649 if (GET_MODE_UNIT_SIZE (mode) == 1)
650 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
651 if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
653 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
654 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
655 ? constm1_rtx : const0_rtx);
656 i = XVECLEN (op, 0) - 1;
658 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
664 ;; Like register_operand, but take into account that SHMEDIA can use
665 ;; the constant zero like a general register.
667 (define_predicate "sh_register_operand"
668 (match_code "reg,subreg,const_int,const_double")
670 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
672 return register_operand (op, mode);
675 ;; TODO: Add a comment here.
677 (define_predicate "sh_rep_vec"
678 (match_code "const_vector,parallel")
683 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
684 || (GET_MODE (op) != mode && mode != VOIDmode))
686 i = XVECLEN (op, 0) - 2;
687 x = XVECEXP (op, 0, i + 1);
688 if (GET_MODE_UNIT_SIZE (mode) == 1)
690 y = XVECEXP (op, 0, i);
691 for (i -= 2; i >= 0; i -= 2)
692 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
693 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
698 if (XVECEXP (op, 0, i) != x)
703 ;; TODO: Add a comment here.
705 (define_predicate "shift_count_operand"
706 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
708 return (CONSTANT_P (op)
710 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
711 : nonmemory_operand (op, mode))
712 : shift_count_reg_operand (op, mode));
715 ;; TODO: Add a comment here.
717 (define_predicate "shift_count_reg_operand"
718 (match_code "subreg,reg,zero_extend,sign_extend")
720 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
721 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
722 && (mode == VOIDmode || mode == GET_MODE (op))
723 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
724 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
729 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
730 || GET_CODE (op) == TRUNCATE)
731 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
732 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
735 return arith_reg_operand (op, mode);
738 ;; TODO: Add a comment here.
740 (define_predicate "shift_operator"
741 (match_code "ashift,ashiftrt,lshiftrt"))
743 ;; TODO: Add a comment here.
745 (define_predicate "symbol_ref_operand"
746 (match_code "symbol_ref"))
748 ;; Same as target_reg_operand, except that label_refs and symbol_refs
749 ;; are accepted before reload.
751 (define_special_predicate "target_operand"
752 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
754 if (mode != VOIDmode && mode != Pmode)
757 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
758 && satisfies_constraint_Csy (op))
759 return ! reload_completed;
761 return target_reg_operand (op, mode);
764 ;; Accept pseudos and branch target registers.
766 (define_special_predicate "target_reg_operand"
767 (match_code "subreg,reg")
770 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
771 : mode != GET_MODE (op))
774 if (GET_CODE (op) == SUBREG)
780 /* We must protect ourselves from matching pseudos that are virtual
781 register, because they will eventually be replaced with hardware
782 registers that aren't branch-target registers. */
783 if (REGNO (op) > LAST_VIRTUAL_REGISTER
784 || TARGET_REGISTER_P (REGNO (op)))
790 ;; TODO: Add a comment here.
792 (define_special_predicate "trunc_hi_operand"
793 (match_code "subreg,reg,truncate")
795 enum machine_mode op_mode = GET_MODE (op);
797 if (op_mode != SImode && op_mode != DImode
798 && op_mode != V4HImode && op_mode != V2SImode)
800 return extend_reg_operand (op, mode);
803 ;; Return 1 of OP is an address suitable for an unaligned access instruction.
805 (define_special_predicate "ua_address_operand"
806 (match_code "subreg,reg,plus")
808 if (GET_CODE (op) == PLUS
809 && (! satisfies_constraint_I06 (XEXP (op, 1))))
811 return address_operand (op, QImode);
814 ;; TODO: Add a comment here.
816 (define_predicate "ua_offset"
817 (match_code "const_int")
819 return satisfies_constraint_I06 (op);
822 ;; TODO: Add a comment here.
824 (define_predicate "unary_float_operator"
825 (and (match_code "abs,neg,sqrt")
826 (match_test "GET_MODE (op) == mode")))
828 ;; Return 1 if OP is a valid source operand for xor.
830 (define_predicate "xor_operand"
831 (match_code "subreg,reg,const_int")
833 if (CONST_INT_P (op))
834 return (TARGET_SHMEDIA
835 ? (satisfies_constraint_I06 (op)
836 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
837 : satisfies_constraint_K08 (op));
839 && mode != DImode && GET_CODE (op) == SUBREG
840 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
842 return arith_reg_operand (op, mode);
845 (define_predicate "bitwise_memory_operand"
850 if (REG_P (XEXP (op, 0)))
853 if (GET_CODE (XEXP (op, 0)) == PLUS
854 && REG_P (XEXP (XEXP (op, 0), 0))
855 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))