| blob | 91e65105a5cb40b7945316a0b67142e5c3bc27e7 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
71 #ifndef CHECK_STACK_LIMIT
72 #define CHECK_STACK_LIMIT (-1)
73 #endif
75 /* Return index of given mode in mult and division cost tables. */
76 #define MODE_INDEX(mode) \
77 ((mode) == QImode ? 0 \
78 : (mode) == HImode ? 1 \
79 : (mode) == SImode ? 2 \
80 : (mode) == DImode ? 3 \
81 : 4)
83 /* Processor costs (relative to an add) */
84 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
85 #define COSTS_N_BYTES(N) ((N) * 2)
87 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
96 const
119 in QImode, HImode and SImode.
120 Relative to reg-reg move (2). */
124 in SFmode, DFmode and XFmode */
126 in SFmode, DFmode and XFmode */
129 in SImode and DImode */
131 in SImode and DImode */
134 in SImode, DImode and TImode */
136 in SImode, DImode and TImode */
149 ix86_size_memcpy,
150 ix86_size_memset,
162 };
164 /* Processor costs (relative to an add) */
167 DUMMY_STRINGOP_ALGS};
170 DUMMY_STRINGOP_ALGS};
172 static const
195 in QImode, HImode and SImode.
196 Relative to reg-reg move (2). */
200 in SFmode, DFmode and XFmode */
202 in SFmode, DFmode and XFmode */
205 in SImode and DImode */
207 in SImode and DImode */
210 in SImode, DImode and TImode */
212 in SImode, DImode and TImode */
225 i386_memcpy,
226 i386_memset,
238 };
242 DUMMY_STRINGOP_ALGS};
245 DUMMY_STRINGOP_ALGS};
247 static const
270 in QImode, HImode and SImode.
271 Relative to reg-reg move (2). */
275 in SFmode, DFmode and XFmode */
277 in SFmode, DFmode and XFmode */
280 in SImode and DImode */
282 in SImode and DImode */
285 in SImode, DImode and TImode */
287 in SImode, DImode and TImode */
290 shared for code and data, so 4kB is
291 not really precise. */
302 i486_memcpy,
303 i486_memset,
315 };
319 DUMMY_STRINGOP_ALGS};
322 DUMMY_STRINGOP_ALGS};
324 static const
347 in QImode, HImode and SImode.
348 Relative to reg-reg move (2). */
352 in SFmode, DFmode and XFmode */
354 in SFmode, DFmode and XFmode */
357 in SImode and DImode */
359 in SImode and DImode */
362 in SImode, DImode and TImode */
364 in SImode, DImode and TImode */
377 pentium_memcpy,
378 pentium_memset,
390 };
392 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
393 (we ensure the alignment). For small blocks inline loop is still a
394 noticeable win, for bigger blocks either rep movsl or rep movsb is
395 way to go. Rep movsb has apparently more expensive startup time in CPU,
396 but after 4K the difference is down in the noise. */
401 DUMMY_STRINGOP_ALGS};
406 DUMMY_STRINGOP_ALGS};
407 static const
430 in QImode, HImode and SImode.
431 Relative to reg-reg move (2). */
435 in SFmode, DFmode and XFmode */
437 in SFmode, DFmode and XFmode */
440 in SImode and DImode */
442 in SImode and DImode */
445 in SImode, DImode and TImode */
447 in SImode, DImode and TImode */
460 pentiumpro_memcpy,
461 pentiumpro_memset,
473 };
477 DUMMY_STRINGOP_ALGS};
480 DUMMY_STRINGOP_ALGS};
481 static const
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
509 in SFmode, DFmode and XFmode */
511 in SFmode, DFmode and XFmode */
515 in SImode and DImode */
517 in SImode and DImode */
520 in SImode, DImode and TImode */
522 in SImode, DImode and TImode */
535 geode_memcpy,
536 geode_memset,
548 };
552 DUMMY_STRINGOP_ALGS};
555 DUMMY_STRINGOP_ALGS};
556 static const
579 in QImode, HImode and SImode.
580 Relative to reg-reg move (2). */
584 in SFmode, DFmode and XFmode */
586 in SFmode, DFmode and XFmode */
589 in SImode and DImode */
591 in SImode and DImode */
594 in SImode, DImode and TImode */
596 in SImode, DImode and TImode */
600 have integrated l2 cache, but
601 optimizing for k6 is not important
602 enough to worry about that. */
612 k6_memcpy,
613 k6_memset,
625 };
627 /* For some reason, Athlon deals better with REP prefix (relative to loops)
628 compared to K8. Alignment becomes important after 8 bytes for memcpy and
629 128 bytes for memset. */
632 DUMMY_STRINGOP_ALGS};
635 DUMMY_STRINGOP_ALGS};
636 static const
659 in QImode, HImode and SImode.
660 Relative to reg-reg move (2). */
664 in SFmode, DFmode and XFmode */
666 in SFmode, DFmode and XFmode */
669 in SImode and DImode */
671 in SImode and DImode */
674 in SImode, DImode and TImode */
676 in SImode, DImode and TImode */
689 athlon_memcpy,
690 athlon_memset,
702 };
704 /* K8 has optimized REP instruction for medium sized blocks, but for very
705 small blocks it is better to use loop. For large blocks, libcall can
706 do nontemporary accesses and beat inline considerably. */
717 static const
740 in QImode, HImode and SImode.
741 Relative to reg-reg move (2). */
745 in SFmode, DFmode and XFmode */
747 in SFmode, DFmode and XFmode */
750 in SImode and DImode */
752 in SImode and DImode */
755 in SImode, DImode and TImode */
757 in SImode, DImode and TImode */
762 /* New AMD processors never drop prefetches; if they cannot be performed
763 immediately, they are queued. We set number of simultaneous prefetches
764 to a large constant to reflect this (it probably is not a good idea not
765 to limit number of prefetches at all, as their execution also takes some
766 time). */
776 k8_memcpy,
777 k8_memset,
789 };
791 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
792 very small blocks it is better to use loop. For large blocks, libcall can
793 do nontemporary accesses and beat inline considerably. */
826 in QImode, HImode and SImode.
827 Relative to reg-reg move (2). */
831 in SFmode, DFmode and XFmode */
833 in SFmode, DFmode and XFmode */
836 in SImode and DImode */
838 in SImode and DImode */
841 in SImode, DImode and TImode */
843 in SImode, DImode and TImode */
845 /* On K8:
846 MOVD reg64, xmmreg Double FSTORE 4
847 MOVD reg32, xmmreg Double FSTORE 4
848 On AMDFAM10:
849 MOVD reg64, xmmreg Double FADD 3
850 1/1 1/1
851 MOVD reg32, xmmreg Double FADD 3
852 1/1 1/1 */
856 /* New AMD processors never drop prefetches; if they cannot be performed
857 immediately, they are queued. We set number of simultaneous prefetches
858 to a large constant to reflect this (it probably is not a good idea not
859 to limit number of prefetches at all, as their execution also takes some
860 time). */
870 amdfam10_memcpy,
871 amdfam10_memset,
883 };
885 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
886 very small blocks it is better to use loop. For large blocks, libcall
887 can do nontemporary accesses and beat inline considerably. */
921 in QImode, HImode and SImode.
922 Relative to reg-reg move (2). */
926 in SFmode, DFmode and XFmode */
928 in SFmode, DFmode and XFmode */
931 in SImode and DImode */
933 in SImode and DImode */
936 in SImode, DImode and TImode */
938 in SImode, DImode and TImode */
940 /* On K8:
941 MOVD reg64, xmmreg Double FSTORE 4
942 MOVD reg32, xmmreg Double FSTORE 4
943 On AMDFAM10:
944 MOVD reg64, xmmreg Double FADD 3
945 1/1 1/1
946 MOVD reg32, xmmreg Double FADD 3
947 1/1 1/1 */
951 /* New AMD processors never drop prefetches; if they cannot be performed
952 immediately, they are queued. We set number of simultaneous prefetches
953 to a large constant to reflect this (it probably is not a good idea not
954 to limit number of prefetches at all, as their execution also takes some
955 time). */
965 bdver1_memcpy,
966 bdver1_memset,
978 };
980 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
981 very small blocks it is better to use loop. For large blocks, libcall
982 can do nontemporary accesses and beat inline considerably. */
1017 in QImode, HImode and SImode.
1018 Relative to reg-reg move (2). */
1022 in SFmode, DFmode and XFmode */
1024 in SFmode, DFmode and XFmode */
1027 in SImode and DImode */
1029 in SImode and DImode */
1032 in SImode, DImode and TImode */
1034 in SImode, DImode and TImode */
1036 /* On K8:
1037 MOVD reg64, xmmreg Double FSTORE 4
1038 MOVD reg32, xmmreg Double FSTORE 4
1039 On AMDFAM10:
1040 MOVD reg64, xmmreg Double FADD 3
1041 1/1 1/1
1042 MOVD reg32, xmmreg Double FADD 3
1043 1/1 1/1 */
1047 /* New AMD processors never drop prefetches; if they cannot be performed
1048 immediately, they are queued. We set number of simultaneous prefetches
1049 to a large constant to reflect this (it probably is not a good idea not
1050 to limit number of prefetches at all, as their execution also takes some
1051 time). */
1061 bdver2_memcpy,
1062 bdver2_memset,
1074 };
1077 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1078 very small blocks it is better to use loop. For large blocks, libcall
1079 can do nontemporary accesses and beat inline considerably. */
1112 in QImode, HImode and SImode.
1113 Relative to reg-reg move (2). */
1117 in SFmode, DFmode and XFmode */
1119 in SFmode, DFmode and XFmode */
1122 in SImode and DImode */
1124 in SImode and DImode */
1127 in SImode, DImode and TImode */
1129 in SImode, DImode and TImode */
1134 /* New AMD processors never drop prefetches; if they cannot be performed
1135 immediately, they are queued. We set number of simultaneous prefetches
1136 to a large constant to reflect this (it probably is not a good idea not
1137 to limit number of prefetches at all, as their execution also takes some
1138 time). */
1148 bdver3_memcpy,
1149 bdver3_memset,
1161 };
1163 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1164 very small blocks it is better to use loop. For large blocks, libcall can
1165 do nontemporary accesses and beat inline considerably. */
1198 in QImode, HImode and SImode.
1199 Relative to reg-reg move (2). */
1203 in SFmode, DFmode and XFmode */
1205 in SFmode, DFmode and XFmode */
1208 in SImode and DImode */
1210 in SImode and DImode */
1213 in SImode, DImode and TImode */
1215 in SImode, DImode and TImode */
1217 /* On K8:
1218 MOVD reg64, xmmreg Double FSTORE 4
1219 MOVD reg32, xmmreg Double FSTORE 4
1220 On AMDFAM10:
1221 MOVD reg64, xmmreg Double FADD 3
1222 1/1 1/1
1223 MOVD reg32, xmmreg Double FADD 3
1224 1/1 1/1 */
1237 btver1_memcpy,
1238 btver1_memset,
1250 };
1284 in QImode, HImode and SImode.
1285 Relative to reg-reg move (2). */
1289 in SFmode, DFmode and XFmode */
1291 in SFmode, DFmode and XFmode */
1294 in SImode and DImode */
1296 in SImode and DImode */
1299 in SImode, DImode and TImode */
1301 in SImode, DImode and TImode */
1303 /* On K8:
1304 MOVD reg64, xmmreg Double FSTORE 4
1305 MOVD reg32, xmmreg Double FSTORE 4
1306 On AMDFAM10:
1307 MOVD reg64, xmmreg Double FADD 3
1308 1/1 1/1
1309 MOVD reg32, xmmreg Double FADD 3
1310 1/1 1/1 */
1322 btver2_memcpy,
1323 btver2_memset,
1335 };
1339 DUMMY_STRINGOP_ALGS};
1343 DUMMY_STRINGOP_ALGS};
1345 static const
1368 in QImode, HImode and SImode.
1369 Relative to reg-reg move (2). */
1373 in SFmode, DFmode and XFmode */
1375 in SFmode, DFmode and XFmode */
1378 in SImode and DImode */
1380 in SImode and DImode */
1383 in SImode, DImode and TImode */
1385 in SImode, DImode and TImode */
1398 pentium4_memcpy,
1399 pentium4_memset,
1411 };
1424 static const
1447 in QImode, HImode and SImode.
1448 Relative to reg-reg move (2). */
1452 in SFmode, DFmode and XFmode */
1454 in SFmode, DFmode and XFmode */
1457 in SImode and DImode */
1459 in SImode and DImode */
1462 in SImode, DImode and TImode */
1464 in SImode, DImode and TImode */
1477 nocona_memcpy,
1478 nocona_memset,
1490 };
1501 static const
1524 in QImode, HImode and SImode.
1525 Relative to reg-reg move (2). */
1529 in SFmode, DFmode and XFmode */
1531 in SFmode, DFmode and XFmode */
1534 in SImode and DImode */
1536 in SImode and DImode */
1539 in SImode, DImode and TImode */
1541 in SImode, DImode and TImode */
1554 atom_memcpy,
1555 atom_memset,
1567 };
1578 static const
1601 in QImode, HImode and SImode.
1602 Relative to reg-reg move (2). */
1606 in SFmode, DFmode and XFmode */
1608 in SFmode, DFmode and XFmode */
1611 in SImode and DImode */
1613 in SImode and DImode */
1616 in SImode, DImode and TImode */
1618 in SImode, DImode and TImode */
1631 slm_memcpy,
1632 slm_memset,
1644 };
1646 /* Generic should produce code tuned for Core-i7 (and newer chips)
1647 and btver1 (and newer chips). */
1659 static const
1662 /* On all chips taken into consideration lea is 2 cycles and more. With
1663 this cost however our current implementation of synth_mult results in
1664 use of unnecessary temporary registers causing regression on several
1665 SPECfp benchmarks. */
1686 in QImode, HImode and SImode.
1687 Relative to reg-reg move (2). */
1691 in SFmode, DFmode and XFmode */
1693 in SFmode, DFmode and XFmode */
1696 in SImode and DImode */
1698 in SImode and DImode */
1701 in SImode, DImode and TImode */
1703 in SImode, DImode and TImode */
1709 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1710 value is increased to perhaps more appropriate value of 5. */
1718 generic_memcpy,
1719 generic_memset,
1731 };
1733 /* core_cost should produce code tuned for Core familly of CPUs. */
1746 static const
1749 /* On all chips taken into consideration lea is 2 cycles and more. With
1750 this cost however our current implementation of synth_mult results in
1751 use of unnecessary temporary registers causing regression on several
1752 SPECfp benchmarks. */
1773 in QImode, HImode and SImode.
1774 Relative to reg-reg move (2). */
1778 in SFmode, DFmode and XFmode */
1780 in SFmode, DFmode and XFmode */
1783 in SImode and DImode */
1785 in SImode and DImode */
1788 in SImode, DImode and TImode */
1790 in SImode, DImode and TImode */
1796 /* FIXME perhaps more appropriate value is 5. */
1804 core_memcpy,
1805 core_memset,
1817 };
1820 /* Set by -mtune. */
1823 /* Set by -mtune or -Os. */
1826 /* Processor feature/optimization bitmasks. */
1827 #define m_386 (1<<PROCESSOR_I386)
1828 #define m_486 (1<<PROCESSOR_I486)
1829 #define m_PENT (1<<PROCESSOR_PENTIUM)
1830 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1831 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1832 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1833 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1834 #define m_CORE2 (1<<PROCESSOR_CORE2)
1835 #define m_COREI7 (1<<PROCESSOR_COREI7)
1836 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1837 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1838 #define m_ATOM (1<<PROCESSOR_ATOM)
1839 #define m_SLM (1<<PROCESSOR_SLM)
1841 #define m_GEODE (1<<PROCESSOR_GEODE)
1842 #define m_K6 (1<<PROCESSOR_K6)
1843 #define m_K6_GEODE (m_K6 | m_GEODE)
1844 #define m_K8 (1<<PROCESSOR_K8)
1845 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1846 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1847 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1848 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1849 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1850 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1851 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1852 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1853 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1854 #define m_BTVER (m_BTVER1 | m_BTVER2)
1855 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1857 #define m_GENERIC (1<<PROCESSOR_GENERIC)
1860 #undef DEF_TUNE
1861 #define DEF_TUNE(tune, name, selector) name,
1863 #undef DEF_TUNE
1864 };
1866 /* Feature tests against the various tunings. */
1869 /* Feature tests against the various tunings used to create ix86_tune_features
1870 based on the processor mask. */
1872 #undef DEF_TUNE
1873 #define DEF_TUNE(tune, name, selector) selector,
1875 #undef DEF_TUNE
1876 };
1878 /* Feature tests against the various architecture variations. */
1881 /* Feature tests against the various architecture variations, used to create
1882 ix86_arch_features based on the processor mask. */
1884 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
1887 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1890 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1893 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1896 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1898 };
1900 /* In case the average insn count for single function invocation is
1901 lower than this constant, emit fast (but longer) prologue and
1902 epilogue code. */
1903 #define FAST_PROLOGUE_INSN_COUNT 20
1905 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1910 /* Array of the smallest class containing reg number REGNO, indexed by
1911 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1914 {
1915 /* ax, dx, cx, bx */
1917 /* si, di, bp, sp */
1919 /* FP registers */
1922 /* arg pointer */
1923 NON_Q_REGS,
1924 /* flags, fpsr, fpcr, frame */
1926 /* SSE registers */
1929 /* MMX registers */
1932 /* REX registers */
1935 /* SSE REX registers */
1938 /* AVX-512 SSE registers */
1943 /* Mask registers. */
1946 };
1948 /* The "default" register map used in 32bit mode. */
1951 {
1962 };
1964 /* The "default" register map used in 64bit mode. */
1967 {
1978 };
1980 /* Define the register numbers to be used in Dwarf debugging information.
1981 The SVR4 reference port C compiler uses the following register numbers
1982 in its Dwarf output code:
1983 0 for %eax (gcc regno = 0)
1984 1 for %ecx (gcc regno = 2)
1985 2 for %edx (gcc regno = 1)
1986 3 for %ebx (gcc regno = 3)
1987 4 for %esp (gcc regno = 7)
1988 5 for %ebp (gcc regno = 6)
1989 6 for %esi (gcc regno = 4)
1990 7 for %edi (gcc regno = 5)
1991 The following three DWARF register numbers are never generated by
1992 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1993 believes these numbers have these meanings.
1994 8 for %eip (no gcc equivalent)
1995 9 for %eflags (gcc regno = 17)
1996 10 for %trapno (no gcc equivalent)
1997 It is not at all clear how we should number the FP stack registers
1998 for the x86 architecture. If the version of SDB on x86/svr4 were
1999 a bit less brain dead with respect to floating-point then we would
2000 have a precedent to follow with respect to DWARF register numbers
2001 for x86 FP registers, but the SDB on x86/svr4 is so completely
2002 broken with respect to FP registers that it is hardly worth thinking
2003 of it as something to strive for compatibility with.
2004 The version of x86/svr4 SDB I have at the moment does (partially)
2005 seem to believe that DWARF register number 11 is associated with
2006 the x86 register %st(0), but that's about all. Higher DWARF
2007 register numbers don't seem to be associated with anything in
2008 particular, and even for DWARF regno 11, SDB only seems to under-
2009 stand that it should say that a variable lives in %st(0) (when
2010 asked via an `=' command) if we said it was in DWARF regno 11,
2011 but SDB still prints garbage when asked for the value of the
2012 variable in question (via a `/' command).
2013 (Also note that the labels SDB prints for various FP stack regs
2014 when doing an `x' command are all wrong.)
2015 Note that these problems generally don't affect the native SVR4
2016 C compiler because it doesn't allow the use of -O with -g and
2017 because when it is *not* optimizing, it allocates a memory
2018 location for each floating-point variable, and the memory
2019 location is what gets described in the DWARF AT_location
2020 attribute for the variable in question.
2021 Regardless of the severe mental illness of the x86/svr4 SDB, we
2022 do something sensible here and we use the following DWARF
2023 register numbers. Note that these are all stack-top-relative
2024 numbers.
2025 11 for %st(0) (gcc regno = 8)
2026 12 for %st(1) (gcc regno = 9)
2027 13 for %st(2) (gcc regno = 10)
2028 14 for %st(3) (gcc regno = 11)
2029 15 for %st(4) (gcc regno = 12)
2030 16 for %st(5) (gcc regno = 13)
2031 17 for %st(6) (gcc regno = 14)
2032 18 for %st(7) (gcc regno = 15)
2033 */
2035 {
2046 };
2048 /* Define parameter passing and return registers. */
2051 {
2053 };
2056 {
2058 };
2061 {
2063 };
2065 /* Additional registers that are clobbered by SYSV calls. */
2068 {
2073 };
2075 /* Define the structure for the machine field in struct function. */
2080 rtx rtl;
2082 };
2084 /* Structure describing stack frame layout.
2085 Stack grows downward:
2087 [arguments]
2088 <- ARG_POINTER
2089 saved pc
2091 saved static chain if ix86_static_chain_on_stack
2093 saved frame pointer if frame_pointer_needed
2094 <- HARD_FRAME_POINTER
2095 [saved regs]
2096 <- regs_save_offset
2097 [padding0]
2099 [saved SSE regs]
2100 <- sse_regs_save_offset
2101 [padding1] |
2102 | <- FRAME_POINTER
2103 [va_arg registers] |
2104 |
2105 [frame] |
2106 |
2107 [padding2] | = to_allocate
2108 <- STACK_POINTER
2109 */
2110 struct ix86_frame
2111 {
2118 /* The offsets relative to ARG_POINTER. */
2119 HOST_WIDE_INT frame_pointer_offset;
2120 HOST_WIDE_INT hard_frame_pointer_offset;
2121 HOST_WIDE_INT stack_pointer_offset;
2122 HOST_WIDE_INT hfp_save_offset;
2123 HOST_WIDE_INT reg_save_offset;
2124 HOST_WIDE_INT sse_reg_save_offset;
2126 /* When save_regs_using_mov is set, emit prologue using
2127 move instead of push instructions. */
2129 };
2131 /* Which cpu are we scheduling for. */
2134 /* Which cpu are we optimizing for. */
2137 /* Which instruction set architecture to use. */
2140 /* True if processor has SSE prefetch instruction. */
2143 /* -mstackrealign option */
2160 /* Preferred alignment for stack boundary in bits. */
2163 /* Alignment for incoming stack boundary in bits specified at
2164 command line. */
2167 /* Default alignment for incoming stack boundary in bits. */
2170 /* Alignment for incoming stack boundary in bits. */
2173 /* Calling abi specific va_list type nodes. */
2177 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2181 /* Fence to use after loop using movnt. */
2182 tree x86_mfence;
2184 /* Register class used for passing given 64bit part of the argument.
2185 These represent classes as documented by the PS ABI, with the exception
2186 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2187 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2189 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2190 whenever possible (upper half does contain padding). */
2191 enum x86_64_reg_class
2192 {
2193 X86_64_NO_CLASS,
2194 X86_64_INTEGER_CLASS,
2195 X86_64_INTEGERSI_CLASS,
2196 X86_64_SSE_CLASS,
2197 X86_64_SSESF_CLASS,
2198 X86_64_SSEDF_CLASS,
2199 X86_64_SSEUP_CLASS,
2200 X86_64_X87_CLASS,
2201 X86_64_X87UP_CLASS,
2202 X86_64_COMPLEX_X87_CLASS,
2203 X86_64_MEMORY_CLASS
2204 };
2206 #define MAX_CLASSES 4
2208 /* Table of constants used by fldpi, fldln2, etc.... */
2212 \f
2217 const_tree);
2229 enum ix86_function_specific_strings
2230 {
2231 IX86_FUNCTION_SPECIFIC_ARCH,
2232 IX86_FUNCTION_SPECIFIC_TUNE,
2233 IX86_FUNCTION_SPECIFIC_MAX
2234 };
2255 \f
2256 #ifndef SUBTARGET32_DEFAULT_CPU
2258 #endif
2260 /* Whether -mtune= or -march= were specified */
2264 /* Vectorization library interface and handlers. */
2270 /* Processor target table, indexed by processor number */
2271 struct ptt
2272 {
2279 };
2282 {
2293 /* Core 2 */
2295 /* Core i7 */
2297 /* Core avx2 */
2308 };
2311 {
2341 "btver2"
2342 };
2343 \f
2344 static bool
2346 {
2348 }
2350 static unsigned int
2352 {
2355 /* vzeroupper instructions are inserted immediately after reload to
2356 account for possible spills from 256bit registers. The pass
2357 reuses mode switching infrastructure by re-running mode insertion
2358 pass, so disable entities that have already been processed. */
2364 /* Call optimize_mode_switching. */
2367 }
2372 {
2384 };
2387 {
2391 {}
2393 /* opt_pass methods: */
2401 rtl_opt_pass *
2403 {
2405 }
2407 /* Return true if a red-zone is in use. */
2411 {
2413 }
2414 \f
2415 /* Return a string that documents the current -m options. The caller is
2416 responsible for freeing the string. */
2422 {
2423 struct ix86_target_opts
2424 {
2427 };
2429 /* This table is ordered so that options like -msse4.2 that imply
2430 preceding options while match those first. */
2432 {
2472 };
2474 /* Flag options. */
2476 {
2504 };
2521 /* Add -march= option. */
2523 {
2526 }
2528 /* Add -mtune= option. */
2530 {
2533 }
2535 /* Add -m32/-m64/-mx32. */
2537 {
2540 else
2542 isa &= ~ (OPTION_MASK_ISA_64BIT
2543 | OPTION_MASK_ABI_64
2545 }
2546 else
2550 /* Pick out the options in isa options. */
2552 {
2554 {
2557 }
2558 }
2561 {
2564 isa);
2565 }
2567 /* Add flag options. */
2569 {
2571 {
2574 }
2575 }
2578 {
2581 }
2583 /* Add -fpmath= option. */
2585 {
2588 {
2603 }
2604 }
2606 /* Any options? */
2612 /* Size the string. */
2616 {
2621 }
2623 /* Build the string. */
2628 {
2635 {
2637 line_len++;
2640 {
2644 }
2645 }
2649 {
2653 }
2654 }
2660 }
2662 /* Return true, if profiling code should be emitted before
2663 prologue. Otherwise it returns false.
2664 Note: For x86 with "hotfix" it is sorried. */
2665 static bool
2667 {
2669 }
2671 /* Function that is callable from the debugger to print the current
2672 options. */
2673 void ATTRIBUTE_UNUSED
2675 {
2681 {
2684 }
2685 else
2689 }
2692 #define DEF_ENUM
2693 #define DEF_ALG(alg, name) #name,
2695 #undef DEF_ENUM
2696 #undef DEF_ALG
2697 };
2699 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2700 The string is of the following form (or comma separated list of it):
2702 strategy_alg:max_size:[align|noalign]
2704 where the full size range for the strategy is either [0, max_size] or
2705 [min_size, max_size], in which min_size is the max_size + 1 of the
2706 preceding range. The last size range must have max_size == -1.
2708 Examples:
2710 1.
2711 -mmemcpy-strategy=libcall:-1:noalign
2713 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2716 2.
2717 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2719 This is to tell the compiler to use the following strategy for memset
2720 1) when the expected size is between [1, 16], use rep_8byte strategy;
2721 2) when the size is between [17, 2048], use vector_loop;
2722 3) when the size is > 2048, use libcall. */
2724 struct stringop_size_range
2725 {
2727 stringop_alg alg;
2729 };
2731 static void
2733 {
2741 else
2746 do
2747 {
2749 stringop_alg alg;
2758 {
2762 }
2765 {
2769 }
2772 {
2774 {
2777 }
2778 }
2781 {
2783 alg_name,
2786 }
2794 else
2795 {
2799 }
2800 n++;
2802 }
2806 {
2811 }
2814 {
2818 }
2820 /* Now override the default algs array. */
2822 {
2828 }
2829 }
2831 \f
2832 /* parse -mtune-ctrl= option. When DUMP is true,
2833 print the features that are explicitly set. */
2835 static void
2837 {
2845 do
2846 {
2853 {
2854 curr_feature_string++;
2856 }
2858 {
2860 {
2866 }
2867 }
2872 }
2875 }
2877 /* Helper function to set ix86_tune_features. IX86_TUNE is the
2878 processor type. */
2880 static void
2882 {
2887 {
2890 else
2892 }
2895 {
2900 }
2903 }
2906 /* Override various settings based on options. If MAIN_ARGS_P, the
2907 options are from the command line, otherwise they are from
2908 attributes. */
2910 static void
2914 {
2922 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2923 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2924 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2925 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2926 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2927 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2928 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2929 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2930 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2931 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2932 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2933 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2934 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2935 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2936 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2937 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2938 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2939 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2940 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2941 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2942 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2943 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2944 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2945 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2946 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2947 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2948 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2949 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2950 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2951 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2952 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2953 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2954 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2955 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2956 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2957 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2958 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2959 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2960 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2961 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2962 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
2963 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
2964 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
2965 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
2967 /* if this reaches 64, need to widen struct pta flags below */
2969 static struct pta
2970 {
2975 }
2977 {
3110 PTA_64BIT
3112 };
3114 /* -mrecip options. */
3115 static struct
3116 {
3119 }
3121 {
3128 };
3132 /* Set up prefix/suffix so the error messages refer to either the command
3133 line argument, or the attribute(target). */
3135 {
3139 }
3140 else
3141 {
3145 }
3147 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3148 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3151 #ifdef TARGET_BI_ARCH
3152 else
3153 {
3154 #if TARGET_BI_ARCH == 1
3155 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3156 is on and OPTION_MASK_ABI_X32 is off. We turn off
3157 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3158 -mx32. */
3161 #else
3162 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3163 on and OPTION_MASK_ABI_64 is off. We turn off
3164 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3165 -m64. */
3168 #endif
3169 }
3170 #endif
3173 {
3174 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3175 OPTION_MASK_ABI_64 for TARGET_X32. */
3178 }
3180 {
3181 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3182 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3185 }
3187 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3188 SUBTARGET_OVERRIDE_OPTIONS;
3189 #endif
3191 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3192 SUBSUBTARGET_OVERRIDE_OPTIONS;
3193 #endif
3195 /* -fPIC is the default for x86_64. */
3199 /* Need to check -mtune=generic first. */
3201 {
3204 /* As special support for cross compilers we read -mtune=native
3205 as -mtune=generic. With native compilers we won't see the
3206 -mtune=native, as it was changed by the driver. */
3208 {
3210 }
3211 /* If this call is for setting the option attribute, allow the
3212 generic that was previously set. */
3215 ;
3223 }
3224 else
3225 {
3229 {
3232 }
3234 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3235 or defaulted. We need to use a sensible tune option. */
3239 {
3241 }
3242 }
3246 {
3247 /* rep; movq isn't available in 32-bit code. */
3250 }
3253 opts->x_ix86_arch_string
3256 else
3260 {
3268 }
3269 else
3276 /* For targets using ms ABI enable ms-extensions, if not
3277 explicit turned off. For non-ms ABI we turn off this
3278 option. */
3283 {
3285 {
3329 {
3332 }
3340 }
3341 }
3342 else
3343 {
3344 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3345 use of rip-relative addressing. This eliminates fixups that
3346 would otherwise be needed if this object is to be placed in a
3347 DLL, and is essentially just as efficient as direct addressing. */
3353 else
3355 }
3357 {
3360 }
3368 {
3371 /* Default cpu tuning to the architecture. */
3510 }
3525 {
3529 {
3531 {
3533 {
3541 }
3542 else
3545 }
3546 }
3547 /* Intel CPUs have always interpreted SSE prefetch instructions as
3548 NOPs; so, we can enable SSE prefetch instructions even when
3549 -mtune (rather than -march) points us to a processor that has them.
3550 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3551 higher processors. */
3556 }
3564 #ifndef USE_IX86_FRAME_POINTER
3565 #define USE_IX86_FRAME_POINTER 0
3566 #endif
3568 #ifndef USE_X86_64_FRAME_POINTER
3569 #define USE_X86_64_FRAME_POINTER 0
3570 #endif
3572 /* Set the default values for switches whose default depends on TARGET_64BIT
3573 in case they weren't overwritten by command line options. */
3575 {
3579 opts->x_flag_unwind_tables
3583 }
3584 else
3585 {
3587 opts->x_flag_omit_frame_pointer
3593 }
3598 else
3601 /* Arrange to set up i386_stack_locals for all functions. */
3604 /* Validate -mregparm= value. */
3606 {
3610 {
3614 }
3615 }
3619 /* Default align_* from the processor table. */
3621 {
3624 }
3626 {
3629 }
3631 {
3633 }
3635 /* Provide default for -mbranch-cost= value. */
3640 {
3641 opts->x_target_flags
3644 /* Enable by default the SSE and MMX builtins. Do allow the user to
3645 explicitly disable any of these. In particular, disabling SSE and
3646 MMX for kernel code is extremely useful. */
3648 opts->x_ix86_isa_flags
3655 }
3656 else
3657 {
3658 opts->x_target_flags
3662 opts->x_ix86_isa_flags
3665 /* i386 ABI does not specify red zone. It still makes sense to use it
3666 when programmer takes care to stack from being destroyed. */
3669 }
3671 /* Keep nonleaf frame pointers. */
3677 /* If we're doing fast math, we don't care about comparison order
3678 wrt NaNs. This lets us use a shorter comparison sequence. */
3682 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3683 since the insns won't need emulation. */
3687 /* Likewise, if the target doesn't have a 387, or we've specified
3688 software floating point, don't use 387 inline intrinsics. */
3692 /* Turn on MMX builtins for -msse. */
3694 opts->x_ix86_isa_flags
3697 /* Enable SSE prefetch. */
3702 /* Enable prefetch{,w} instructions for -m3dnow. */
3704 opts->x_ix86_isa_flags
3707 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3710 opts->x_ix86_isa_flags
3713 /* Enable lzcnt instruction for -mabm. */
3715 opts->x_ix86_isa_flags
3718 /* Validate -mpreferred-stack-boundary= value or default it to
3719 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3722 {
3729 {
3733 else
3736 }
3737 else
3738 ix86_preferred_stack_boundary
3740 }
3742 /* Set the default value for -mstackrealign. */
3748 /* Validate -mincoming-stack-boundary= value or default it to
3749 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3752 {
3757 ix86_incoming_stack_boundary_arg,
3759 else
3760 {
3761 ix86_user_incoming_stack_boundary
3763 ix86_incoming_stack_boundary
3765 }
3766 }
3768 /* Accept -msseregparm only if at least SSE support is enabled. */
3774 {
3776 {
3778 {
3781 }
3784 {
3787 }
3788 }
3789 }
3790 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3791 fpmath=387. The second is however default at many targets since the
3792 extra 80bit precision of temporaries is considered to be part of ABI.
3793 Overwrite the default at least for -ffast-math.
3794 TODO: -mfpmath=both seems to produce same performing code with bit
3795 smaller binaries. It is however not clear if register allocation is
3796 ready for this setting.
3797 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3798 codegen. We may switch to 387 with -ffast-math for size optimized
3799 functions. */
3803 else
3806 /* If the i387 is disabled, then do not return values in it. */
3810 /* Use external vectorized library in vectorizing intrinsics. */
3813 {
3824 }
3831 /* If stack probes are required, the space used for large function
3832 arguments on the stack must also be probed, so enable
3833 -maccumulate-outgoing-args so this happens in the prologue. */
3836 {
3841 }
3843 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3844 {
3850 }
3852 /* When scheduling description is not available, disable scheduler pass
3853 so it won't slow down the compilation and make x87 code slower. */
3874 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3876 && HAVE_prefetch
3881 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3882 can be opts->x_optimized to ap = __builtin_next_arg (0). */
3887 {
3890 {
3892 ix86_gen_tls_local_dynamic_base_64
3894 }
3895 else
3896 {
3898 ix86_gen_tls_local_dynamic_base_64
3900 }
3901 }
3902 else
3906 {
3916 }
3917 else
3918 {
3928 }
3930 #ifdef USE_IX86_CLD
3931 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3934 #endif
3937 {
3942 }
3944 {
3948 }
3950 {
3951 #if defined(PROFILE_BEFORE_PROLOGUE)
3953 #else
3955 #endif
3956 }
3958 /* When not opts->x_optimize for size, enable vzeroupper optimization for
3959 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3960 AVX unaligned load/store. */
3962 {
3972 /* Enable 128-bit AVX instruction generation
3973 for the auto-vectorizer. */
3977 }
3980 {
3987 {
3990 {
3992 q++;
3993 }
3994 else
3999 else
4000 {
4003 {
4006 }
4009 {
4013 }
4014 }
4019 else
4021 }
4022 }
4029 /* Default long double to 64-bit for Bionic. */
4034 /* Save the initial options in case the user does function specific
4035 options. */
4037 target_option_default_node = target_option_current_node
4040 /* Handle stack protector */
4042 opts->x_ix86_stack_protector_guard
4045 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4047 {
4051 }
4054 {
4058 }
4059 }
4061 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4063 static void
4065 {
4067 static struct register_pass_info insert_vzeroupper_info
4070 };
4075 /* This needs to be done at start up. It's convenient to do it here. */
4077 }
4079 /* Update register usage after having seen the compiler flags. */
4081 static void
4083 {
4087 /* The PIC register, if it exists, is fixed. */
4092 /* For 32-bit targets, squash the REX registers. */
4094 {
4101 }
4103 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4111 {
4112 /* Set/reset conditionally defined registers from
4113 CALL_USED_REGISTERS initializer. */
4117 /* Calculate registers of CLOBBERED_REGS register set
4118 as call used registers from GENERAL_REGS register set. */
4122 }
4124 /* If MMX is disabled, squash the registers. */
4130 /* If SSE is disabled, squash the registers. */
4136 /* If the FPU is disabled, squash the registers. */
4142 /* If AVX512F is disabled, squash the registers. */
4144 {
4150 }
4151 }
4153 \f
4154 /* Save the current options */
4156 static void
4159 {
4170 /* The fields are char but the variables are not; make sure the
4171 values fit in the fields. */
4176 }
4178 /* Restore the current options */
4180 static void
4183 {
4199 /* Recreate the arch feature tests if the arch changed */
4201 {
4206 }
4208 /* Recreate the tune optimization tests */
4211 }
4213 /* Print the current options */
4215 static void
4218 {
4240 {
4243 }
4244 }
4246 \f
4247 /* Inner function to process the attribute((target(...))), take an argument and
4248 set the current options from the argument. If we have a list, recursively go
4249 over the list. */
4251 static bool
4256 {
4260 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4261 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4262 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4263 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4264 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4266 enum ix86_opt_type
4267 {
4268 ix86_opt_unknown,
4269 ix86_opt_yes,
4270 ix86_opt_no,
4271 ix86_opt_str,
4272 ix86_opt_enum,
4273 ix86_opt_isa
4274 };
4276 static const struct
4277 {
4284 /* isa options */
4325 /* enum options */
4328 /* string options */
4332 /* flag options */
4334 OPT_mcld,
4335 MASK_CLD),
4338 OPT_mfancy_math_387,
4339 MASK_NO_FANCY_MATH_387),
4342 OPT_mieee_fp,
4343 MASK_IEEE_FP),
4346 OPT_minline_all_stringops,
4347 MASK_INLINE_ALL_STRINGOPS),
4350 OPT_minline_stringops_dynamically,
4351 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4354 OPT_mno_align_stringops,
4355 MASK_NO_ALIGN_STRINGOPS),
4358 OPT_mrecip,
4359 MASK_RECIP),
4361 };
4363 /* If this is a list, recurse to get the options. */
4365 {
4372 enum_opts_set))
4376 }
4379 {
4382 }
4384 /* Handle multiple arguments separated by commas. */
4388 {
4402 {
4406 }
4407 else
4408 {
4411 }
4413 /* Recognize no-xxx. */
4415 {
4419 }
4420 else
4423 /* Find the option. */
4427 {
4435 {
4440 }
4441 }
4443 /* Process the option. */
4445 {
4448 }
4451 {
4457 }
4460 {
4466 else
4468 }
4471 {
4473 {
4476 }
4477 else
4479 }
4482 {
4490 global_dc);
4491 else
4492 {
4495 }
4496 }
4498 else
4500 }
4503 }
4505 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4507 tree
4511 {
4526 /* Process each of the options on the chain. */
4531 /* If the changed options are different from the default, rerun
4532 ix86_option_override_internal, and then save the options away.
4533 The string options are are attribute options, and will be undone
4534 when we copy the save structure. */
4540 {
4541 /* If we are using the default tune= or arch=, undo the string assigned,
4542 and use the default. */
4553 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4557 {
4560 }
4562 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4565 /* Add any builtin functions with the new isa if any. */
4568 /* Save the current options unless we are validating options for
4569 #pragma. */
4576 /* Free up memory allocated to hold the strings */
4579 }
4582 }
4584 /* Hook to validate attribute((target("string"))). */
4586 static bool
4589 tree args,
4591 {
4596 /* attribute((target("default"))) does nothing, beyond
4597 affecting multi-versioning. */
4606 /* Get the optimization options of the current function. */
4612 /* Init func_options. */
4620 /* Initialize func_options to the default before its target options can
4621 be set. */
4634 {
4639 }
4642 }
4644 \f
4645 /* Hook to determine if one function can safely inline another. */
4647 static bool
4649 {
4654 /* If callee has no option attributes, then it is ok to inline. */
4658 /* If caller has no option attributes, but callee does then it is not ok to
4659 inline. */
4663 else
4664 {
4668 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4669 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4670 function. */
4675 /* See if we have the same non-isa options. */
4679 /* See if arch, tune, etc. are the same. */
4692 else
4694 }
4697 }
4699 \f
4700 /* Remember the last target of ix86_set_current_function. */
4703 /* Invalidate ix86_previous_fndecl cache. */
4704 void
4706 {
4708 }
4710 /* Establish appropriate back-end context for processing the function
4711 FNDECL. The argument might be NULL to indicate processing at top
4712 level, outside of any function scope. */
4713 static void
4715 {
4716 /* Only change the context if the function changes. This hook is called
4717 several times in the course of compiling a function, and we don't want to
4718 slow things down too much or call target_reinit when it isn't safe. */
4720 {
4721 tree old_tree = (ix86_previous_fndecl
4725 tree new_tree = (fndecl
4731 ;
4734 {
4738 }
4741 {
4747 }
4748 }
4749 }
4751 \f
4752 /* Return true if this goes in large data/bss. */
4754 static bool
4756 {
4760 /* Functions are never large data. */
4765 {
4771 }
4772 else
4773 {
4776 /* If this is an incomplete type with size 0, then we can't put it
4777 in data because it might be too big when completed. */
4780 }
4783 }
4785 /* Switch to the appropriate section for output of DECL.
4786 DECL is either a `VAR_DECL' node or a constant of some sort.
4787 RELOC indicates whether forming the initial value of DECL requires
4788 link-time relocations. */
4793 {
4796 {
4800 {
4834 /* We don't split these for medium model. Place them into
4835 default sections and hope for best. */
4837 }
4839 {
4840 /* We might get called with string constants, but get_named_section
4841 doesn't like them as they are not DECLs. Also, we need to set
4842 flags in that case. */
4846 }
4847 }
4849 }
4851 /* Select a set of attributes for section NAME based on the properties
4852 of DECL and whether or not RELOC indicates that DECL's initializer
4853 might contain runtime relocations. */
4855 static unsigned int ATTRIBUTE_UNUSED
4857 {
4871 }
4873 /* Build up a unique section name, expressed as a
4874 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4875 RELOC indicates whether the initial value of EXP requires
4876 link-time relocations. */
4878 static void ATTRIBUTE_UNUSED
4880 {
4883 {
4885 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4889 {
4913 /* We don't split these for medium model. Place them into
4914 default sections and hope for best. */
4916 }
4918 {
4925 /* If we're using one_only, then there needs to be a .gnu.linkonce
4926 prefix to the section name. */
4933 }
4934 }
4936 }
4938 #ifdef COMMON_ASM_OP
4939 /* This says how to output assembler code to declare an
4940 uninitialized external linkage data object.
4942 For medium model x86-64 we need to use .largecomm opcode for
4943 large objects. */
4944 void
4948 {
4952 else
4957 }
4958 #endif
4960 /* Utility function for targets to use in implementing
4961 ASM_OUTPUT_ALIGNED_BSS. */
4963 void
4967 {
4971 else
4974 #ifdef ASM_DECLARE_OBJECT_NAME
4977 #else
4978 /* Standard thing is just output label for the object. */
4982 }
4983 \f
4984 /* Decide whether we must probe the stack before any space allocation
4985 on this target. It's essentially TARGET_STACK_PROBE except when
4986 -fstack-check causes the stack to be already probed differently. */
4988 bool
4990 {
4991 /* Do not probe the stack twice if static stack checking is enabled. */
4996 }
4997 \f
4998 /* Decide whether we can make a sibling call to a function. DECL is the
4999 declaration of the function being targeted by the call and EXP is the
5000 CALL_EXPR representing the call. */
5002 static bool
5004 {
5008 /* If we are generating position-independent code, we cannot sibcall
5009 optimize any indirect call, or a direct call to a global function,
5010 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5012 && !TARGET_64BIT
5013 && flag_pic
5017 /* If we need to align the outgoing stack, then sibcalling would
5018 unalign the stack, which may break the called function. */
5024 {
5027 }
5028 else
5029 {
5030 /* We're looking at the CALL_EXPR, we need the type of the function. */
5035 }
5037 /* Check that the return value locations are the same. Like
5038 if we are returning floats on the 80387 register stack, we cannot
5039 make a sibcall from a function that doesn't return a float to a
5040 function that does or, conversely, from a function that does return
5041 a float to a function that doesn't; the necessary stack adjustment
5042 would not be executed. This is also the place we notice
5043 differences in the return value ABI. Note that it is ok for one
5044 of the functions to have void return type as long as the return
5045 value of the other is passed in a register. */
5050 {
5053 }
5055 ;
5060 {
5061 /* The SYSV ABI has more call-clobbered registers;
5062 disallow sibcalls from MS to SYSV. */
5066 }
5067 else
5068 {
5069 /* If this call is indirect, we'll need to be able to use a
5070 call-clobbered register for the address of the target function.
5071 Make sure that all such registers are not used for passing
5072 parameters. Note that DLLIMPORT functions are indirect. */
5075 {
5077 {
5078 /* ??? Need to count the actual number of registers to be used,
5079 not the possible number of registers. Fix later. */
5081 }
5082 }
5083 }
5085 /* Otherwise okay. That also includes certain types of indirect calls. */
5087 }
5089 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5090 and "sseregparm" calling convention attributes;
5091 arguments as in struct attribute_spec.handler. */
5093 static tree
5095 tree args,
5098 {
5103 {
5105 name);
5108 }
5110 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5112 {
5113 tree cst;
5116 {
5118 }
5121 {
5123 }
5127 {
5130 name);
5132 }
5134 {
5138 }
5141 }
5144 {
5145 /* Do not warn when emulating the MS ABI. */
5150 name);
5153 }
5155 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5157 {
5159 {
5161 }
5163 {
5165 }
5167 {
5169 }
5171 {
5173 }
5174 }
5176 /* Can combine stdcall with fastcall (redundant), regparm and
5177 sseregparm. */
5179 {
5181 {
5183 }
5185 {
5187 }
5189 {
5191 }
5192 }
5194 /* Can combine cdecl with regparm and sseregparm. */
5196 {
5198 {
5200 }
5202 {
5204 }
5206 {
5208 }
5209 }
5211 {
5214 name);
5216 {
5218 }
5220 {
5222 }
5224 {
5226 }
5227 }
5229 /* Can combine sseregparm with all attributes. */
5232 }
5234 /* The transactional memory builtins are implicitly regparm or fastcall
5235 depending on the ABI. Override the generic do-nothing attribute that
5236 these builtins were declared with, and replace it with one of the two
5237 attributes that we expect elsewhere. */
5239 static tree
5241 tree args ATTRIBUTE_UNUSED,
5243 {
5244 tree alt;
5246 /* In no case do we want to add the placeholder attribute. */
5249 /* The 64-bit ABI is unchanged for transactional memory. */
5253 /* ??? Is there a better way to validate 32-bit windows? We have
5254 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5257 else
5258 {
5261 }
5265 }
5267 /* This function determines from TYPE the calling-convention. */
5269 unsigned int
5271 {
5274 tree attrs;
5281 {
5291 /* Regparam isn't allowed for thiscall and fastcall. */
5293 {
5298 }
5302 }
5309 || is_stdarg
5315 }
5317 /* Return 0 if the attributes for two types are incompatible, 1 if they
5318 are compatible, and 2 if they are nearly compatible (which causes a
5319 warning to be generated). */
5321 static int
5323 {
5339 }
5340 \f
5341 /* Return the regparm value for a function with the indicated TYPE and DECL.
5342 DECL may be NULL when calling function indirectly
5343 or considering a libcall. */
5345 static int
5347 {
5348 tree attr;
5359 {
5362 {
5365 }
5366 }
5372 /* Use register calling convention for local functions when possible. */
5375 && optimize
5377 {
5378 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5381 {
5384 /* Make sure no regparm register is taken by a
5385 fixed register variable. */
5390 /* We don't want to use regparm(3) for nested functions as
5391 these use a static chain pointer in the third argument. */
5395 /* In 32-bit mode save a register for the split stack. */
5399 /* Each fixed register usage increases register pressure,
5400 so less registers should be used for argument passing.
5401 This functionality can be overriden by an explicit
5402 regparm value. */
5405 globals++;
5407 local_regparm
5412 }
5413 }
5416 }
5418 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5419 DFmode (2) arguments in SSE registers for a function with the
5420 indicated TYPE and DECL. DECL may be NULL when calling function
5421 indirectly or considering a libcall. Otherwise return 0. */
5423 static int
5425 {
5428 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5429 by the sseregparm attribute. */
5432 {
5434 {
5436 {
5440 else
5443 }
5445 }
5448 }
5450 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5451 (and DFmode for SSE2) arguments in SSE registers. */
5454 {
5455 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5459 }
5462 }
5464 /* Return true if EAX is live at the start of the function. Used by
5465 ix86_expand_prologue to determine if we need special help before
5466 calling allocate_stack_worker. */
5468 static bool
5470 {
5471 /* Cheat. Don't bother working forward from ix86_function_regparm
5472 to the function type to whether an actual argument is located in
5473 eax. Instead just look at cfg info, which is still close enough
5474 to correct at this point. This gives false positives for broken
5475 functions that might use uninitialized data that happens to be
5476 allocated in eax, but who cares? */
5478 }
5480 static bool
5482 {
5483 tree attr;
5486 {
5492 /* For 32-bit MS-ABI the default is to keep aggregate
5493 return pointer. */
5496 }
5498 }
5500 /* Value is the number of bytes of arguments automatically
5501 popped when returning from a subroutine call.
5502 FUNDECL is the declaration node of the function (as a tree),
5503 FUNTYPE is the data type of the function (as a tree),
5504 or for a library call it is an identifier node for the subroutine name.
5505 SIZE is the number of bytes of arguments passed on the stack.
5507 On the 80386, the RTD insn may be used to pop them if the number
5508 of args is fixed, but if the number is variable then the caller
5509 must pop them all. RTD can't be used for library calls now
5510 because the library is compiled with the Unix compiler.
5511 Use of RTD is a selectable option, since it is incompatible with
5512 standard Unix calling sequences. If the option is not selected,
5513 the caller must always pop the args.
5515 The attribute stdcall is equivalent to RTD on a per module basis. */
5517 static int
5519 {
5522 /* None of the 64-bit ABIs pop arguments. */
5533 /* Lose any fake structure return argument if it is passed on the stack. */
5536 {
5540 }
5543 }
5545 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5547 static bool
5549 {
5550 /* Check operand constraints in case hard registers were propagated
5551 into insn pattern. This check prevents combine pass from
5552 generating insn patterns with invalid hard register operands.
5553 These invalid insns can eventually confuse reload to error out
5554 with a spill failure. See also PRs 46829 and 46843. */
5556 {
5563 {
5571 /* A unary operator may be accepted by the predicate, but it
5572 is irrelevant for matching constraints. */
5577 {
5585 }
5592 /* Operand has no constraints, anything is OK. */
5596 {
5599 && operands_match_p
5603 {
5606 }
5607 }
5611 }
5612 }
5615 }
5616 \f
5617 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5619 static unsigned HOST_WIDE_INT
5621 {
5625 }
5626 \f
5627 /* Argument support functions. */
5629 /* Return true when register may be used to pass function parameters. */
5630 bool
5632 {
5637 {
5641 else
5647 }
5653 /* TODO: The function should depend on current function ABI but
5654 builtins.c would need updating then. Therefore we use the
5655 default ABI. */
5657 /* RAX is used as hidden argument to va_arg functions. */
5663 else
5670 }
5672 /* Return if we do not know how to pass TYPE solely in registers. */
5674 static bool
5676 {
5680 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5681 The layout_type routine is crafty and tries to trick us into passing
5682 currently unsupported vector types on the stack by using TImode. */
5685 }
5687 /* It returns the size, in bytes, of the area reserved for arguments passed
5688 in registers for the function represented by fndecl dependent to the used
5689 abi format. */
5690 int
5692 {
5696 else
5701 }
5703 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5704 call abi used. */
5705 enum calling_abi
5707 {
5709 {
5712 {
5715 }
5719 }
5721 }
5723 /* We add this as a workaround in order to use libc_has_function
5724 hook in i386.md. */
5725 bool
5727 {
5729 }
5731 static bool
5733 {
5735 {
5739 else
5741 }
5743 }
5745 static enum calling_abi
5747 {
5751 }
5753 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5754 call abi used. */
5755 enum calling_abi
5757 {
5761 }
5763 /* Write the extra assembler code needed to declare a function properly. */
5765 void
5767 tree decl)
5768 {
5772 {
5778 }
5780 #ifdef SUBTARGET_ASM_UNWIND_INIT
5782 #endif
5786 /* Output magic byte marker, if hot-patch attribute is set. */
5788 {
5790 {
5791 /* leaq [%rsp + 0], %rsp */
5794 }
5795 else
5796 {
5797 /* movl.s %edi, %edi
5798 push %ebp
5799 movl.s %esp, %ebp */
5802 }
5803 }
5804 }
5806 /* regclass.c */
5809 /* Implementation of call abi switching target hook. Specific to FNDECL
5810 the specific call register sets are set. See also
5811 ix86_conditional_register_usage for more details. */
5812 void
5814 {
5817 else
5819 }
5821 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5822 expensive re-initialization of init_regs each time we switch function context
5823 since this is needed only during RTL expansion. */
5824 static void
5826 {
5830 }
5832 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5833 for a call to a function whose data type is FNTYPE.
5834 For a library call, FNTYPE is 0. */
5836 void
5840 tree fndecl,
5842 {
5848 {
5851 }
5852 else
5853 {
5856 }
5860 /* Set up the number of registers to use for passing arguments. */
5867 {
5869 ? X86_64_REGPARM_MAX
5871 }
5873 {
5876 {
5878 ? X86_64_SSE_REGPARM_MAX
5880 }
5881 }
5888 /* Because type might mismatch in between caller and callee, we need to
5889 use actual type of function for local calls.
5890 FIXME: cgraph_analyze can be told to actually record if function uses
5891 va_start so for local functions maybe_vaarg can be made aggressive
5892 helping K&R code.
5893 FIXME: once typesytem is fixed, we won't need this code anymore. */
5901 {
5902 /* If there are variable arguments, then we won't pass anything
5903 in registers in 32-bit mode. */
5905 {
5913 }
5915 /* Use ecx and edx registers if function has fastcall attribute,
5916 else look for regparm information. */
5918 {
5921 {
5924 }
5926 {
5929 }
5930 else
5932 }
5934 /* Set up the number of SSE registers used for passing SFmode
5935 and DFmode arguments. Warn for mismatching ABI. */
5937 }
5938 }
5940 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5941 But in the case of vector types, it is some vector mode.
5943 When we have only some of our vector isa extensions enabled, then there
5944 are some modes for which vector_mode_supported_p is false. For these
5945 modes, the generic vector support in gcc will choose some non-vector mode
5946 in order to implement the type. By computing the natural mode, we'll
5947 select the proper ABI location for the operand and not depend on whatever
5948 the middle-end decides to do with these vector types.
5950 The midde-end can't deal with the vector types > 16 bytes. In this
5951 case, we return the original mode and warn ABI change if CUM isn't
5952 NULL. */
5954 static enum machine_mode
5956 {
5960 {
5963 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5965 {
5970 else
5973 /* Get the mode which has this inner mode and number of units. */
5977 {
5979 {
5983 && !warnedavx
5985 {
5989 }
5991 }
5993 {
5997 && !warnedsse
5999 {
6003 }
6005 }
6006 else
6008 }
6011 }
6012 }
6015 }
6017 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6018 this may not agree with the mode that the type system has chosen for the
6019 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6020 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6022 static rtx
6025 {
6026 rtx tmp;
6030 else
6031 {
6035 }
6038 }
6040 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6041 of this code is to classify each 8bytes of incoming argument by the register
6042 class and assign registers accordingly. */
6044 /* Return the union class of CLASS1 and CLASS2.
6045 See the x86-64 PS ABI for details. */
6047 static enum x86_64_reg_class
6049 {
6050 /* Rule #1: If both classes are equal, this is the resulting class. */
6054 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6055 the other class. */
6061 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6065 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6073 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6074 MEMORY is used. */
6083 /* Rule #6: Otherwise class SSE is used. */
6085 }
6087 /* Classify the argument of type TYPE and mode MODE.
6088 CLASSES will be filled by the register class used to pass each word
6089 of the operand. The number of words is returned. In case the parameter
6090 should be passed in memory, 0 is returned. As a special case for zero
6091 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6093 BIT_OFFSET is used internally for handling records and specifies offset
6094 of the offset in bits modulo 256 to avoid overflow cases.
6096 See the x86-64 PS ABI for details.
6097 */
6099 static int
6102 {
6103 HOST_WIDE_INT bytes =
6105 int words
6108 /* Variable sized entities are always passed/returned in memory. */
6117 {
6119 tree field;
6122 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6129 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6130 signalize memory class, so handle it as special case. */
6132 {
6135 }
6137 /* Classify each field of record and merge classes. */
6139 {
6141 /* And now merge the fields of structure. */
6143 {
6145 {
6151 /* Bitfields are always classified as integer. Handle them
6152 early, since later code would consider them to be
6153 misaligned integers. */
6155 {
6164 }
6165 else
6166 {
6171 /* Flexible array member is ignored. */
6178 {
6182 {
6185 "the ABI of passing struct with"
6186 " a flexible array member has"
6188 }
6190 }
6192 subclasses,
6202 }
6203 }
6204 }
6208 /* Arrays are handled as small records. */
6209 {
6216 /* The partial classes are now full classes. */
6227 }
6230 /* Unions are similar to RECORD_TYPE but offset is always 0.
6231 */
6233 {
6235 {
6243 bit_offset);
6248 }
6249 }
6254 }
6257 {
6258 /* When size > 16 bytes, if the first one isn't
6259 X86_64_SSE_CLASS or any other ones aren't
6260 X86_64_SSEUP_CLASS, everything should be passed in
6261 memory. */
6268 }
6270 /* Final merger cleanup. */
6272 {
6273 /* If one class is MEMORY, everything should be passed in
6274 memory. */
6278 /* The X86_64_SSEUP_CLASS should be always preceded by
6279 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6283 {
6284 /* The first one should never be X86_64_SSEUP_CLASS. */
6287 }
6289 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6290 everything should be passed in memory. */
6293 {
6296 /* The first one should never be X86_64_X87UP_CLASS. */
6299 {
6302 "the ABI of passing union with long double"
6304 }
6306 }
6307 }
6309 }
6311 /* Compute alignment needed. We align all types to natural boundaries with
6312 exception of XFmode that is aligned to 64bits. */
6314 {
6323 /* Misaligned fields are always returned in memory. */
6326 }
6328 /* for V1xx modes, just use the base mode */
6333 /* Classification of atomic types. */
6335 {
6351 {
6355 {
6358 }
6360 {
6363 }
6365 {
6369 }
6371 {
6374 }
6375 else
6377 }
6384 /* OImode shouldn't be used directly. */
6391 else
6409 else
6410 {
6414 {
6417 "the ABI of passing structure with complex float"
6419 }
6422 }
6431 /* This modes is larger than 16 bytes. */
6474 else
6478 }
6479 }
6481 /* Examine the argument and return set number of register required in each
6482 class. Return 0 iff parameter should be passed in memory. */
6483 static int
6486 {
6496 {
6518 }
6520 }
6522 /* Construct container for the argument used by GCC interface. See
6523 FUNCTION_ARG for the detailed description. */
6525 static rtx
6529 {
6530 /* The following variables hold the static issued_error state. */
6544 rtx ret;
6555 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6556 some less clueful developer tries to use floating-point anyway. */
6558 {
6560 {
6562 {
6565 }
6566 }
6568 {
6571 }
6573 }
6575 /* Likewise, error if the ABI requires us to return values in the
6576 x87 registers and the user specified -mno-80387. */
6582 {
6584 {
6587 }
6589 }
6591 /* First construct simple cases. Avoid SCmode, since we want to use
6592 single register to pass this type. */
6595 {
6610 /* Zero sized array, struct or class. */
6614 }
6641 /* Otherwise figure out the entries of the PARALLEL. */
6643 {
6647 {
6652 /* Merge TImodes on aligned occasions here too. */
6654 tmpmode
6658 else
6660 /* We've requested 24 bytes we
6661 don't have mode for. Use DImode. */
6668 intreg++;
6676 sse_regno++;
6684 sse_regno++;
6689 {
6695 {
6697 i++;
6698 }
6699 else
6712 }
6718 sse_regno++;
6722 }
6723 }
6725 /* Empty aligned struct, union or class. */
6733 }
6735 /* Update the data in CUM to advance over an argument of mode MODE
6736 and data type TYPE. (TYPE is null for libcalls where that information
6737 may not be available.) */
6739 static void
6742 HOST_WIDE_INT words)
6743 {
6745 {
6752 /* FALLTHRU */
6763 {
6766 }
6770 /* OImode shouldn't be used directly. */
6779 /* FALLTHRU */
6795 {
6800 {
6803 }
6804 }
6814 {
6819 {
6822 }
6823 }
6825 }
6826 }
6828 static void
6831 {
6834 /* Unnamed 256bit vector mode parameters are passed on stack. */
6840 {
6845 }
6846 else
6847 {
6851 }
6852 }
6854 static void
6856 HOST_WIDE_INT words)
6857 {
6858 /* Otherwise, this should be passed indirect. */
6863 {
6866 }
6867 }
6869 /* Update the data in CUM to advance over an argument of mode MODE and
6870 data type TYPE. (TYPE is null for libcalls where that information
6871 may not be available.) */
6873 static void
6876 {
6882 else
6893 else
6895 }
6897 /* Define where to put the arguments to a function.
6898 Value is zero to push the argument on the stack,
6899 or a hard register in which to store the argument.
6901 MODE is the argument's machine mode.
6902 TYPE is the data type of the argument (as a tree).
6903 This is null for libcalls where that information may
6904 not be available.
6905 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6906 the preceding args and about the function being called.
6907 NAMED is nonzero if this argument is a named parameter
6908 (otherwise it is an extra parameter matching an ellipsis). */
6910 static rtx
6914 {
6917 /* Avoid the AL settings for the Unix64 ABI. */
6922 {
6929 /* FALLTHRU */
6935 {
6938 /* Fastcall allocates the first two DWORD (SImode) or
6939 smaller arguments to ECX and EDX if it isn't an
6940 aggregate type . */
6942 {
6948 /* ECX not EAX is the first allocated register. */
6951 }
6953 }
6962 /* FALLTHRU */
6964 /* In 32bit, we pass TImode in xmm registers. */
6972 {
6974 {
6978 }
6982 }
6986 /* OImode shouldn't be used directly. */
6996 {
7000 }
7010 {
7012 {
7016 }
7020 }
7022 }
7025 }
7027 static rtx
7030 {
7031 /* Handle a hidden AL argument containing number of registers
7032 for varargs x86-64 functions. */
7036 ? X86_64_SSE_REGPARM_MAX
7041 {
7051 /* Unnamed 256bit vector mode parameters are passed on stack. */
7055 }
7061 }
7063 static rtx
7066 HOST_WIDE_INT bytes)
7067 {
7070 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7071 We use value of -2 to specify that current function call is MSABI. */
7075 /* If we've run out of registers, it goes on the stack. */
7081 /* Only floating point modes are passed in anything but integer regs. */
7083 {
7086 else
7087 {
7090 /* Unnamed floating parameters are passed in both the
7091 SSE and integer registers. */
7097 }
7098 }
7099 /* Handle aggregated types passed in register. */
7101 {
7106 }
7109 }
7111 /* Return where to put the arguments to a function.
7112 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7114 MODE is the argument's machine mode. TYPE is the data type of the
7115 argument. It is null for libcalls where that information may not be
7116 available. CUM gives information about the preceding args and about
7117 the function being called. NAMED is nonzero if this argument is a
7118 named parameter (otherwise it is an extra parameter matching an
7119 ellipsis). */
7121 static rtx
7124 {
7128 rtx arg;
7132 else
7136 /* To simplify the code below, represent vector types with a vector mode
7137 even if MMX/SSE are not active. */
7145 else
7149 }
7151 /* A C expression that indicates when an argument must be passed by
7152 reference. If nonzero for an argument, a copy of that argument is
7153 made in memory and a pointer to the argument is passed instead of
7154 the argument itself. The pointer is passed in whatever way is
7155 appropriate for passing a pointer to that type. */
7157 static bool
7160 {
7163 /* See Windows x64 Software Convention. */
7165 {
7168 {
7169 /* Arrays are passed by reference. */
7174 {
7175 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7176 are passed by reference. */
7178 }
7179 }
7181 /* __m128 is passed by reference. */
7187 }
7188 }
7193 }
7195 /* Return true when TYPE should be 128bit aligned for 32bit argument
7196 passing ABI. XXX: This function is obsolete and is only used for
7197 checking psABI compatibility with previous versions of GCC. */
7199 static bool
7201 {
7213 {
7214 /* Walk the aggregates recursively. */
7216 {
7220 {
7221 tree field;
7223 /* Walk all the structure fields. */
7225 {
7229 }
7231 }
7234 /* Just for use if some languages passes arrays by value. */
7241 }
7242 }
7244 }
7246 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7247 XXX: This function is obsolete and is only used for checking psABI
7248 compatibility with previous versions of GCC. */
7250 static unsigned int
7253 {
7254 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7255 natural boundaries. */
7257 {
7258 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7259 make an exception for SSE modes since these require 128bit
7260 alignment.
7262 The handling here differs from field_alignment. ICC aligns MMX
7263 arguments to 4 byte boundaries, while structure fields are aligned
7264 to 8 byte boundaries. */
7266 {
7269 }
7270 else
7271 {
7274 }
7275 }
7279 }
7281 /* Return true when TYPE should be 128bit aligned for 32bit argument
7282 passing ABI. */
7284 static bool
7286 {
7296 {
7297 /* Walk the aggregates recursively. */
7299 {
7303 {
7304 tree field;
7306 /* Walk all the structure fields. */
7308 field;
7310 {
7314 }
7316 }
7319 /* Just for use if some languages passes arrays by value. */
7326 }
7327 }
7328 else
7332 }
7334 /* Gives the alignment boundary, in bits, of an argument with the
7335 specified mode and type. */
7337 static unsigned int
7339 {
7342 {
7343 /* Since the main variant type is used for call, we convert it to
7344 the main variant type. */
7347 }
7348 else
7352 else
7353 {
7358 {
7359 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7361 {
7364 }
7370 }
7373 && !warned
7375 saved_align))
7376 {
7379 "The ABI for passing parameters with %d-byte"
7382 }
7383 }
7386 }
7388 /* Return true if N is a possible register number of function value. */
7390 static bool
7392 {
7394 {
7399 /* TODO: The function should depend on current function ABI but
7400 builtins.c would need updating then. Therefore we use the
7401 default ABI. */
7413 }
7416 }
7418 /* Define how to find the value returned by a function.
7419 VALTYPE is the data type of the value (as a tree).
7420 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7421 otherwise, FUNC is 0. */
7423 static rtx
7426 {
7429 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7430 we normally prevent this case when mmx is not available. However
7431 some ABIs may require the result to be returned like DImode. */
7435 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7436 we prevent this case when sse is not available. However some ABIs
7437 may require the result to be returned like integer TImode. */
7442 /* 32-byte vector modes in %ymm0. */
7446 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7449 else
7450 /* Most things go in %eax. */
7453 /* Override FP return register with %xmm0 for local functions when
7454 SSE math is enabled or for functions with sseregparm attribute. */
7456 {
7461 }
7463 /* OImode shouldn't be used directly. */
7467 }
7469 static rtx
7471 const_tree valtype)
7472 {
7473 rtx ret;
7475 /* Handle libcalls, which don't provide a type node. */
7477 {
7481 {
7500 }
7503 }
7505 {
7506 /* Pointers are always returned in word_mode. */
7508 }
7514 /* For zero sized structures, construct_container returns NULL, but we
7515 need to keep rest of compiler happy by returning meaningful value. */
7520 }
7522 static rtx
7524 const_tree valtype)
7525 {
7529 {
7531 {
7550 }
7551 }
7553 }
7555 static rtx
7558 {
7570 else
7572 }
7574 static rtx
7577 {
7583 }
7585 /* Pointer function arguments and return values are promoted to
7586 word_mode. */
7588 static enum machine_mode
7592 {
7594 {
7597 }
7599 for_return);
7600 }
7602 /* Return true if a structure, union or array with MODE containing FIELD
7603 should be accessed using BLKmode. */
7605 static bool
7607 {
7608 /* Union with XFmode must be in BLKmode. */
7612 }
7614 rtx
7616 {
7618 }
7620 /* Return true iff type is returned in memory. */
7622 static bool ATTRIBUTE_UNUSED
7624 {
7625 HOST_WIDE_INT size;
7636 {
7637 /* User-created vectors small enough to fit in EAX. */
7641 /* MMX/3dNow values are returned in MM0,
7642 except when it doesn't exits or the ABI prescribes otherwise. */
7646 /* SSE values are returned in XMM0, except when it doesn't exist. */
7650 /* AVX values are returned in YMM0, except when it doesn't exist. */
7653 }
7661 /* OImode shouldn't be used directly. */
7665 }
7667 static bool ATTRIBUTE_UNUSED
7669 {
7672 }
7674 static bool ATTRIBUTE_UNUSED
7676 {
7679 /* __m128 is returned in xmm0. */
7686 /* Otherwise, the size must be exactly in [1248]. */
7688 }
7690 static bool
7692 {
7693 #ifdef SUBTARGET_RETURN_IN_MEMORY
7695 #else
7699 {
7702 else
7704 }
7705 else
7707 #endif
7708 }
7710 /* When returning SSE vector types, we have a choice of either
7711 (1) being abi incompatible with a -march switch, or
7712 (2) generating an error.
7713 Given no good solution, I think the safest thing is one warning.
7714 The user won't be able to use -Werror, but....
7716 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7717 called in response to actually generating a caller or callee that
7718 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7719 via aggregate_value_p for general type probing from tree-ssa. */
7721 static rtx
7723 {
7727 {
7728 /* Look at the return type of the function, not the function type. */
7732 {
7735 {
7739 }
7740 }
7743 {
7745 {
7749 }
7750 }
7751 }
7754 }
7756 \f
7757 /* Create the va_list data type. */
7759 /* Returns the calling convention specific va_list date type.
7760 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7762 static tree
7764 {
7767 /* For i386 we use plain pointer to argument area. */
7777 unsigned_type_node);
7780 unsigned_type_node);
7783 ptr_type_node);
7786 ptr_type_node);
7805 /* The correct type is an array type of one element. */
7807 }
7809 /* Setup the builtin va_list data type and for 64-bit the additional
7810 calling convention specific va_list data types. */
7812 static tree
7814 {
7817 /* Initialize abi specific va_list builtin types. */
7819 {
7820 tree t;
7822 {
7827 }
7828 else
7829 {
7834 }
7836 {
7841 }
7842 else
7843 {
7848 }
7849 }
7852 }
7854 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7856 static void
7858 {
7860 alias_set_type set;
7863 /* GPR size of varargs save area. */
7866 else
7869 /* FPR size of varargs save area. We don't need it if we don't pass
7870 anything in SSE registers. */
7873 else
7887 {
7895 }
7898 {
7902 /* Now emit code to save SSE registers. The AX parameter contains number
7903 of SSE parameter registers used to call this function, though all we
7904 actually check here is the zero/non-zero status. */
7909 label));
7911 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7912 we used movdqa (i.e. TImode) instead? Perhaps even better would
7913 be if we could determine the real mode of the data, via a hook
7914 into pass_stdarg. Ignore all that for now. */
7924 {
7933 }
7936 }
7937 }
7939 static void
7941 {
7945 /* Reset to zero, as there might be a sysv vaarg used
7946 before. */
7951 {
7962 }
7963 }
7965 static void
7969 {
7971 CUMULATIVE_ARGS next_cum;
7972 tree fntype;
7974 /* This argument doesn't appear to be used anymore. Which is good,
7975 because the old code here didn't suppress rtl generation. */
7983 /* For varargs, we do not want to skip the dummy va_dcl argument.
7984 For stdargs, we do want to skip the last named argument. */
7992 else
7994 }
7996 /* Checks if TYPE is of kind va_list char *. */
7998 static bool
8000 {
8001 tree canonic;
8003 /* For 32-bit it is always true. */
8009 }
8011 /* Implement va_start. */
8013 static void
8015 {
8019 tree type;
8020 rtx ovf_rtx;
8024 {
8027 /* When we are splitting the stack, we can't refer to the stack
8028 arguments using internal_arg_pointer, because they may be on
8029 the old stack. The split stack prologue will arrange to
8030 leave a pointer to the old stack arguments in a scratch
8031 register, which we here copy to a pseudo-register. The split
8032 stack prologue can't set the pseudo-register directly because
8033 it (the prologue) runs before any registers have been saved. */
8037 {
8051 }
8052 }
8054 /* Only 64bit target needs something special. */
8056 {
8059 else
8060 {
8069 }
8071 }
8080 /* The following should be folded into the MEM_REF offset. */
8090 /* Count number of gp and fp argument registers used. */
8096 {
8102 }
8105 {
8111 }
8113 /* Find the overflow area. */
8117 else
8127 {
8128 /* Find the register save area.
8129 Prologue of the function save it right above stack frame. */
8137 }
8138 }
8140 /* Implement va_arg. */
8142 static tree
8145 {
8152 rtx container;
8154 tree ptrtype;
8158 /* Only 64bit target needs something special. */
8182 {
8189 /* Unnamed 256bit vector mode parameters are passed on stack. */
8191 {
8194 }
8202 }
8204 /* Pull the value out of the saved registers. */
8209 {
8223 /* In case we are passing structure, verify that it is consecutive block
8224 on the register save area. If not we need to do moves. */
8226 {
8227 /* Verify that all registers are strictly consecutive */
8229 {
8233 {
8238 }
8239 }
8240 else
8241 {
8245 {
8250 }
8251 }
8252 }
8254 {
8257 }
8258 else
8259 {
8262 }
8264 /* First ensure that we fit completely in registers. */
8266 {
8273 }
8275 {
8283 }
8285 /* Compute index to start of area used for integer regs. */
8287 {
8288 /* int_addr = gpr + sav; */
8291 }
8293 {
8294 /* sse_addr = fpr + sav; */
8297 }
8299 {
8303 /* addr = &temp; */
8308 {
8312 tree piece_type;
8313 tree addr_type;
8314 tree daddr_type;
8323 {
8328 }
8332 else
8339 {
8342 }
8343 else
8344 {
8347 }
8354 {
8359 }
8360 else
8361 {
8362 tree copy
8367 }
8369 }
8370 }
8373 {
8377 }
8380 {
8384 }
8389 }
8391 /* ... otherwise out of the overflow area. */
8393 /* When we align parameter on stack for caller, if the parameter
8394 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8395 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8396 here with caller. */
8401 /* Care for on-stack alignment if needed. */
8404 else
8405 {
8410 }
8427 }
8428 \f
8429 /* Return true if OPNUM's MEM should be matched
8430 in movabs* patterns. */
8432 bool
8434 {
8446 }
8447 \f
8448 /* Initialize the table of extra 80387 mathematical constants. */
8450 static void
8452 {
8454 {
8460 };
8464 {
8466 /* Ensure each constant is rounded to XFmode precision. */
8469 }
8472 }
8474 /* Return non-zero if the constant is something that
8475 can be loaded with a special instruction. */
8477 int
8479 {
8482 REAL_VALUE_TYPE r;
8494 /* For XFmode constants, try to find a special 80387 instruction when
8495 optimizing for size or on those CPUs that benefit from them. */
8498 {
8507 }
8509 /* Load of the constant -0.0 or -1.0 will be split as
8510 fldz;fchs or fld1;fchs sequence. */
8517 }
8519 /* Return the opcode of the special instruction to be used to load
8520 the constant X. */
8524 {
8526 {
8546 }
8547 }
8549 /* Return the CONST_DOUBLE representing the 80387 constant that is
8550 loaded by the specified special instruction. The argument IDX
8551 matches the return value from standard_80387_constant_p. */
8553 rtx
8555 {
8562 {
8573 }
8576 XFmode);
8577 }
8579 /* Return 1 if X is all 0s and 2 if x is all 1s
8580 in supported SSE/AVX vector mode. */
8582 int
8584 {
8591 {
8606 }
8609 }
8611 /* Return the opcode of the special instruction to be used to load
8612 the constant X. */
8616 {
8618 {
8621 {
8638 }
8647 else
8652 }
8654 }
8656 /* Returns true if OP contains a symbol reference */
8658 bool
8660 {
8669 {
8671 {
8677 }
8681 }
8684 }
8686 /* Return true if it is appropriate to emit `ret' instructions in the
8687 body of a function. Do this only if the epilogue is simple, needing a
8688 couple of insns. Prior to reloading, we can't tell how many registers
8689 must be saved, so return false then. Return false if there is no frame
8690 marker to de-allocate. */
8692 bool
8694 {
8700 /* Don't allow more than 32k pop, since that's all we can do
8701 with one instruction. */
8708 }
8709 \f
8710 /* Value should be nonzero if functions must have frame pointers.
8711 Zero means the frame pointer need not be set up (and parms may
8712 be accessed via the stack pointer) in functions that seem suitable. */
8714 static bool
8716 {
8717 /* If we accessed previous frames, then the generated code expects
8718 to be able to access the saved ebp value in our frame. */
8722 /* Several x86 os'es need a frame pointer for other reasons,
8723 usually pertaining to setjmp. */
8727 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8731 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8732 allocation is 4GB. */
8736 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8737 turns off the frame pointer by default. Turn it back on now if
8738 we've not got a leaf function. */
8748 }
8750 /* Record that the current function accesses previous call frames. */
8752 void
8754 {
8756 }
8757 \f
8758 #ifndef USE_HIDDEN_LINKONCE
8759 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8760 # define USE_HIDDEN_LINKONCE 1
8761 # else
8762 # define USE_HIDDEN_LINKONCE 0
8763 # endif
8764 #endif
8768 /* Fills in the label name that should be used for a pc thunk for
8769 the given register. */
8771 static void
8773 {
8778 else
8780 }
8783 /* This function generates code for -fpic that loads %ebx with
8784 the return address of the caller and then returns. */
8786 static void
8788 {
8793 {
8795 tree decl;
8811 #if TARGET_MACHO
8813 {
8822 }
8823 else
8824 #endif
8826 {
8837 }
8838 else
8839 {
8842 }
8848 /* Make sure unwind info is emitted for the thunk if needed. */
8851 /* Pad stack IP move with 4 instructions (two NOPs count
8852 as one instruction). */
8854 {
8859 }
8870 }
8874 }
8876 /* Emit code for the SET_GOT patterns. */
8880 {
8886 {
8887 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8892 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8893 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8894 an unadorned address. */
8899 }
8904 {
8906 /* We don't need a pic base, we're not producing pic. */
8913 }
8914 else
8915 {
8924 #if TARGET_MACHO
8925 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
8926 This is what will be referenced by the Mach-O PIC subsystem. */
8930 /* When we are restoring the pic base at the site of a nonlocal label,
8931 and we decided to emit the pic base above, we will still output a
8932 local label used for calculating the correction offset (even though
8933 the offset will be 0 in that case). */
8937 #endif
8938 }
8944 }
8946 /* Generate an "push" pattern for input ARG. */
8948 static rtx
8950 {
8963 stack_pointer_rtx)),
8964 arg);
8965 }
8967 /* Generate an "pop" pattern for input ARG. */
8969 static rtx
8971 {
8976 arg,
8979 stack_pointer_rtx)));
8980 }
8982 /* Return >= 0 if there is an unused call-clobbered register available
8983 for the entire function. */
8985 static unsigned int
8987 {
8991 {
8993 /* Can't use the same register for both PIC and DRAP. */
8996 else
9001 }
9004 }
9006 /* Return TRUE if we need to save REGNO. */
9008 static bool
9010 {
9021 {
9024 {
9030 }
9031 }
9040 }
9042 /* Return number of saved general prupose registers. */
9044 static int
9046 {
9052 nregs ++;
9054 }
9056 /* Return number of saved SSE registrers. */
9058 static int
9060 {
9068 nregs ++;
9070 }
9072 /* Given FROM and TO register numbers, say whether this elimination is
9073 allowed. If stack alignment is needed, we can only replace argument
9074 pointer with hard frame pointer, or replace frame pointer with stack
9075 pointer. Otherwise, frame pointer elimination is automatically
9076 handled and all other eliminations are valid. */
9078 static bool
9080 {
9086 else
9088 }
9090 /* Return the offset between two registers, one to be eliminated, and the other
9091 its replacement, at the start of a routine. */
9093 HOST_WIDE_INT
9095 {
9104 else
9105 {
9113 }
9114 }
9116 /* In a dynamically-aligned function, we can't know the offset from
9117 stack pointer to frame pointer, so we must ensure that setjmp
9118 eliminates fp against the hard fp (%ebp) rather than trying to
9119 index from %esp up to the top of the frame across a gap that is
9120 of unknown (at compile-time) size. */
9121 static rtx
9123 {
9125 }
9127 /* When using -fsplit-stack, the allocation routines set a field in
9128 the TCB to the bottom of the stack plus this much space, measured
9129 in bytes. */
9131 #define SPLIT_STACK_AVAILABLE 256
9133 /* Fill structure ix86_frame about frame of currently computed function. */
9135 static void
9137 {
9139 HOST_WIDE_INT offset;
9142 HOST_WIDE_INT to_allocate;
9150 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9151 function prologues and leaf. */
9155 {
9160 }
9166 /* For SEH we have to limit the amount of code movement into the prologue.
9167 At present we do this via a BLOCKAGE, at which point there's very little
9168 scheduling that can be done, which means that there's very little point
9169 in doing anything except PUSHs. */
9173 /* During reload iteration the amount of registers saved can change.
9174 Recompute the value as needed. Do not recompute when amount of registers
9175 didn't change as reload does multiple calls to the function and does not
9176 expect the decision to change within single iteration. */
9179 {
9185 /* The fast prologue uses move instead of push to save registers. This
9186 is significantly longer, but also executes faster as modern hardware
9187 can execute the moves in parallel, but can't do that for push/pop.
9189 Be careful about choosing what prologue to emit: When function takes
9190 many instructions to execute we may use slow version as well as in
9191 case function is known to be outside hot spot (this is known with
9192 feedback only). Weight the size of function by number of registers
9193 to save as it is cheap to use one or two push instructions but very
9194 slow to use many of them. */
9198 || (flag_branch_probabilities
9201 else
9204 }
9206 frame->save_regs_using_mov
9208 /* If static stack checking is enabled and done with probes,
9209 the registers need to be saved before allocating the frame. */
9212 /* Skip return address. */
9215 /* Skip pushed static chain. */
9219 /* Skip saved base pointer. */
9224 /* The traditional frame pointer location is at the top of the frame. */
9227 /* Register save area */
9231 /* On SEH target, registers are pushed just before the frame pointer
9232 location. */
9236 /* Align and set SSE register save area. */
9238 {
9239 /* The only ABI that has saved SSE registers (Win64) also has a
9240 16-byte aligned default stack, and thus we don't need to be
9241 within the re-aligned local stack frame to save them. */
9245 }
9248 /* The re-aligned stack starts here. Values before this point are not
9249 directly comparable with values below this point. In order to make
9250 sure that no value happens to be the same before and after, force
9251 the alignment computation below to add a non-zero value. */
9255 /* Va-arg area */
9259 /* Align start of frame for local function. */
9268 /* Frame pointer points here. */
9273 /* Add outgoing arguments area. Can be skipped if we eliminated
9274 all the function calls as dead code.
9275 Skipping is however impossible when function calls alloca. Alloca
9276 expander assumes that last crtl->outgoing_args_size
9277 of stack frame are unused. */
9281 {
9284 }
9285 else
9288 /* Align stack boundary. Only needed if we're calling another function
9289 or using alloca. */
9294 /* We've reached end of stack frame. */
9297 /* Size prologue needs to allocate. */
9308 {
9314 }
9315 else
9319 /* The SEH frame pointer location is near the bottom of the frame.
9320 This is enforced by the fact that the difference between the
9321 stack pointer and the frame pointer is limited to 240 bytes in
9322 the unwind data structure. */
9324 {
9325 HOST_WIDE_INT diff;
9327 /* If we can leave the frame pointer where it is, do so. Also, returns
9328 the establisher frame for __builtin_frame_address (0). */
9333 {
9334 /* Ideally we'd determine what portion of the local stack frame
9335 (within the constraint of the lowest 240) is most heavily used.
9336 But without that complication, simply bias the frame pointer
9337 by 128 bytes so as to maximize the amount of the local stack
9338 frame that is addressable with 8-bit offsets. */
9340 }
9341 }
9342 }
9344 /* This is semi-inlined memory_address_length, but simplified
9345 since we know that we're always dealing with reg+offset, and
9346 to avoid having to create and discard all that rtl. */
9350 {
9354 {
9355 /* EBP and R13 cannot be encoded without an offset. */
9357 }
9361 /* ESP and R12 must be encoded with a SIB byte. */
9363 len++;
9366 }
9368 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9369 The valid base registers are taken from CFUN->MACHINE->FS. */
9371 static rtx
9373 {
9379 {
9380 /* Choose the base register most likely to allow the most scheduling
9381 opportunities. Generally FP is valid throughout the function,
9382 while DRAP must be reloaded within the epilogue. But choose either
9383 over the SP due to increased encoding size. */
9386 {
9389 }
9391 {
9394 }
9396 {
9399 }
9400 }
9401 else
9402 {
9403 HOST_WIDE_INT toffset;
9406 /* Choose the base register with the smallest address encoding.
9407 With a tie, choose FP > DRAP > SP. */
9409 {
9413 }
9415 {
9419 {
9423 }
9424 }
9426 {
9430 {
9434 }
9435 }
9436 }
9440 }
9442 /* Emit code to save registers in the prologue. */
9444 static void
9446 {
9448 rtx insn;
9452 {
9455 }
9456 }
9458 /* Emit a single register save at CFA - CFA_OFFSET. */
9460 static void
9462 HOST_WIDE_INT cfa_offset)
9463 {
9471 /* For SSE saves, we need to indicate the 128-bit alignment. */
9482 /* When saving registers into a re-aligned local stack frame, avoid
9483 any tricky guessing by dwarf2out. */
9485 {
9489 {
9490 /* A bit of a hack. We force the DRAP register to be saved in
9491 the re-aligned stack frame, which provides us with a copy
9492 of the CFA that will last past the prologue. Install it. */
9498 }
9499 else
9500 {
9501 /* The frame pointer is a stable reference within the
9502 aligned frame. Use it. */
9509 }
9510 }
9512 /* The memory may not be relative to the current CFA register,
9513 which means that we may need to generate a new pattern for
9514 use by the unwind info. */
9516 {
9521 }
9522 }
9524 /* Emit code to save registers using MOV insns.
9525 First register is stored at CFA - CFA_OFFSET. */
9526 static void
9528 {
9533 {
9536 }
9537 }
9539 /* Emit code to save SSE registers using MOV insns.
9540 First register is stored at CFA - CFA_OFFSET. */
9541 static void
9543 {
9548 {
9551 }
9552 }
9556 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9557 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9558 Don't add the note if the previously saved value will be left untouched
9559 within stack red-zone till return, as unwinders can find the same value
9560 in the register and on the stack. */
9562 static void
9564 {
9570 {
9573 }
9574 else
9575 queued_cfa_restores
9577 }
9579 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9581 static void
9583 {
9584 rtx last;
9588 ;
9593 }
9595 /* Expand prologue or epilogue stack adjustment.
9596 The pattern exist to put a dependency on all ebp-based memory accesses.
9597 STYLE should be negative if instructions should be marked as frame related,
9598 zero if %r11 register is live and cannot be freely used and positive
9599 otherwise. */
9601 static void
9604 {
9606 rtx insn;
9613 else
9614 {
9615 rtx tmp;
9616 /* r11 is used by indirect sibcall return as well, set before the
9617 epilogue and used after the epilogue. */
9620 else
9621 {
9625 }
9631 }
9638 {
9639 rtx r;
9649 }
9651 {
9654 {
9658 }
9659 }
9662 {
9667 {
9670 }
9672 {
9675 }
9676 else
9677 {
9678 /* Else there are two possibilities: SP itself, which we set
9679 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9680 taken care of this by hand along the eh_return path. */
9683 }
9687 }
9688 }
9690 /* Find an available register to be used as dynamic realign argument
9691 pointer regsiter. Such a register will be written in prologue and
9692 used in begin of body, so it must not be
9693 1. parameter passing register.
9694 2. GOT pointer.
9695 We reuse static-chain register if it is available. Otherwise, we
9696 use DI for i386 and R13 for x86-64. We chose R13 since it has
9697 shorter encoding.
9699 Return: the regno of chosen register. */
9701 static unsigned int
9703 {
9707 {
9708 /* Use R13 for nested function or function need static chain.
9709 Since function with tail call may use any caller-saved
9710 registers in epilogue, DRAP must not use caller-saved
9711 register in such case. */
9716 }
9717 else
9718 {
9719 /* Use DI for nested function or function need static chain.
9720 Since function with tail call may use any caller-saved
9721 registers in epilogue, DRAP must not use caller-saved
9722 register in such case. */
9726 /* Reuse static chain register if it isn't used for parameter
9727 passing. */
9729 {
9733 }
9735 }
9736 }
9738 /* Return minimum incoming stack alignment. */
9740 static unsigned int
9742 {
9745 /* Prefer the one specified at command line. */
9748 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9749 if -mstackrealign is used, it isn't used for sibcall check and
9750 estimated stack alignment is 128bit. */
9752 && !TARGET_64BIT
9753 && ix86_force_align_arg_pointer
9756 else
9759 /* Incoming stack alignment can be changed on individual functions
9760 via force_align_arg_pointer attribute. We use the smallest
9761 incoming stack boundary. */
9767 /* The incoming stack frame has to be aligned at least at
9768 parm_stack_boundary. */
9772 /* Stack at entrance of main is aligned by runtime. We use the
9773 smallest incoming stack boundary. */
9781 }
9783 /* Update incoming stack boundary and estimated stack alignment. */
9785 static void
9787 {
9788 ix86_incoming_stack_boundary
9791 /* x86_64 vararg needs 16byte stack alignment for register save
9792 area. */
9797 }
9799 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9800 needed or an rtx for DRAP otherwise. */
9802 static rtx
9804 {
9809 {
9810 /* Assign DRAP to vDRAP and returns vDRAP */
9812 rtx drap_vreg;
9813 rtx arg_ptr;
9826 {
9829 }
9831 }
9832 else
9834 }
9836 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9838 static rtx
9840 {
9842 }
9845 rtx reg;
9847 };
9849 /* Return a short-lived scratch register for use on function entry.
9850 In 32-bit mode, it is valid only after the registers are saved
9851 in the prologue. This register must be released by means of
9852 release_scratch_register_on_entry once it is dead. */
9854 static void
9856 {
9862 {
9863 /* We always use R11 in 64-bit mode. */
9865 }
9866 else
9867 {
9869 bool fastcall_p
9871 bool thiscall_p
9875 int drap_regno
9878 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9879 for the static chain register. */
9883 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9884 for the static chain register. */
9889 /* ecx is the static chain register. */
9891 && !static_chain_p
9896 /* esi is the static chain register. */
9902 else
9903 {
9906 }
9907 }
9911 {
9914 }
9915 }
9917 /* Release a scratch register obtained from the preceding function. */
9919 static void
9921 {
9923 {
9927 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9933 }
9934 }
9936 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9938 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9940 static void
9942 {
9943 /* We skip the probe for the first interval + a small dope of 4 words and
9944 probe that many bytes past the specified size to maintain a protection
9945 area at the botton of the stack. */
9949 /* See if we have a constant small number of probes to generate. If so,
9950 that's the easy case. The run-time loop is made up of 11 insns in the
9951 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9952 for n # of intervals. */
9954 {
9958 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9959 values of N from 1 until it exceeds SIZE. If only one probe is
9960 needed, this will not generate any code. Then adjust and probe
9961 to PROBE_INTERVAL + SIZE. */
9963 {
9965 {
9968 }
9969 else
9976 }
9980 else
9988 /* Adjust back to account for the additional first interval. */
9992 }
9994 /* Otherwise, do the same as above, but in a loop. Note that we must be
9995 extra careful with variables wrapping around because we might be at
9996 the very top (or the very bottom) of the address space and we have
9997 to be able to handle this case properly; in particular, we use an
9998 equality test for the loop condition. */
9999 else
10000 {
10001 HOST_WIDE_INT rounded_size;
10007 /* Step 1: round SIZE to the previous multiple of the interval. */
10012 /* Step 2: compute initial and final value of the loop counter. */
10014 /* SP = SP_0 + PROBE_INTERVAL. */
10019 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10023 stack_pointer_rtx)));
10026 /* Step 3: the loop
10028 while (SP != LAST_ADDR)
10029 {
10030 SP = SP + PROBE_INTERVAL
10031 probe at SP
10032 }
10034 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10035 values of N from 1 until it is equal to ROUNDED_SIZE. */
10040 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10041 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10044 {
10049 }
10051 /* Adjust back to account for the additional first interval. */
10057 }
10061 /* Even if the stack pointer isn't the CFA register, we need to correctly
10062 describe the adjustments made to it, in particular differentiate the
10063 frame-related ones from the frame-unrelated ones. */
10065 {
10078 }
10080 /* Make sure nothing is scheduled before we are done. */
10082 }
10084 /* Adjust the stack pointer up to REG while probing it. */
10088 {
10098 /* Jump to END_LAB if SP == LAST_ADDR. */
10106 /* SP = SP + PROBE_INTERVAL. */
10110 /* Probe at SP. */
10121 }
10123 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10124 inclusive. These are offsets from the current stack pointer. */
10126 static void
10128 {
10129 /* See if we have a constant small number of probes to generate. If so,
10130 that's the easy case. The run-time loop is made up of 7 insns in the
10131 generic case while the compile-time loop is made up of n insns for n #
10132 of intervals. */
10134 {
10135 HOST_WIDE_INT i;
10137 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10138 it exceeds SIZE. If only one probe is needed, this will not
10139 generate any code. Then probe at FIRST + SIZE. */
10146 }
10148 /* Otherwise, do the same as above, but in a loop. Note that we must be
10149 extra careful with variables wrapping around because we might be at
10150 the very top (or the very bottom) of the address space and we have
10151 to be able to handle this case properly; in particular, we use an
10152 equality test for the loop condition. */
10153 else
10154 {
10161 /* Step 1: round SIZE to the previous multiple of the interval. */
10166 /* Step 2: compute initial and final value of the loop counter. */
10168 /* TEST_OFFSET = FIRST. */
10171 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10175 /* Step 3: the loop
10177 while (TEST_ADDR != LAST_ADDR)
10178 {
10179 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10180 probe at TEST_ADDR
10181 }
10183 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10184 until it is equal to ROUNDED_SIZE. */
10189 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10190 that SIZE is equal to ROUNDED_SIZE. */
10195 stack_pointer_rtx,
10200 }
10202 /* Make sure nothing is scheduled before we are done. */
10204 }
10206 /* Probe a range of stack addresses from REG to END, inclusive. These are
10207 offsets from the current stack pointer. */
10211 {
10221 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10229 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10233 /* Probe at TEST_ADDR. */
10246 }
10248 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10249 to be generated in correct form. */
10250 static void
10252 {
10253 /* Check if stack realign is really needed after reload, and
10254 stores result in cfun */
10255 unsigned int incoming_stack_boundary
10264 {
10265 /* After stack_realign_needed is finalized, we can't no longer
10266 change it. */
10269 }
10271 /* If the only reason for frame_pointer_needed is that we conservatively
10272 assumed stack realignment might be needed, but in the end nothing that
10273 needed the stack alignment had been spilled, clear frame_pointer_needed
10274 and say we don't need stack realignment. */
10277 && frame_pointer_needed
10279 && flag_omit_frame_pointer
10281 && !ix86_current_function_calls_tls_descriptor
10290 {
10292 basic_block bb;
10299 HARD_FRAME_POINTER_REGNUM);
10301 {
10302 rtx insn;
10306 set_up_by_prologue))
10307 {
10311 }
10312 }
10326 }
10330 }
10332 /* Expand the prologue into a bunch of separate insns. */
10334 void
10336 {
10341 HOST_WIDE_INT allocate;
10347 /* DRAP should not coexist with stack_realign_fp */
10352 /* Initialize CFA state for before the prologue. */
10356 /* Track SP offset to the CFA. We continue tracking this after we've
10357 swapped the CFA register away from SP. In the case of re-alignment
10358 this is fudged; we're interested to offsets within the local frame. */
10365 {
10366 /* We should have already generated an error for any use of
10367 ms_hook on a nested function. */
10370 /* Check if profiling is active and we shall use profiling before
10371 prologue variant. If so sorry. */
10376 /* In ix86_asm_output_function_label we emitted:
10377 8b ff movl.s %edi,%edi
10378 55 push %ebp
10379 8b ec movl.s %esp,%ebp
10381 This matches the hookable function prologue in Win32 API
10382 functions in Microsoft Windows XP Service Pack 2 and newer.
10383 Wine uses this to enable Windows apps to hook the Win32 API
10384 functions provided by Wine.
10386 What that means is that we've already set up the frame pointer. */
10390 {
10393 /* We've decided to use the frame pointer already set up.
10394 Describe this to the unwinder by pretending that both
10395 push and mov insns happen right here.
10397 Putting the unwind info here at the end of the ms_hook
10398 is done so that we can make absolutely certain we get
10399 the required byte sequence at the start of the function,
10400 rather than relying on an assembler that can produce
10401 the exact encoding required.
10403 However it does mean (in the unpatched case) that we have
10404 a 1 insn window where the asynchronous unwind info is
10405 incorrect. However, if we placed the unwind info at
10406 its correct location we would have incorrect unwind info
10407 in the patched case. Which is probably all moot since
10408 I don't expect Wine generates dwarf2 unwind info for the
10409 system libraries that use this feature. */
10415 stack_pointer_rtx);
10423 /* Note that gen_push incremented m->fs.cfa_offset, even
10424 though we didn't emit the push insn here. */
10428 }
10429 else
10430 {
10431 /* The frame pointer is not needed so pop %ebp again.
10432 This leaves us with a pristine state. */
10434 }
10435 }
10437 /* The first insn of a function that accepts its static chain on the
10438 stack is to push the register that would be filled in by a direct
10439 call. This insn will be skipped by the trampoline. */
10441 {
10445 /* We don't want to interpret this push insn as a register save,
10446 only as a stack adjustment. The real copy of the register as
10447 a save will be done later, if needed. */
10452 }
10454 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10455 of DRAP is needed and stack realignment is really needed after reload */
10457 {
10460 /* Only need to push parameter pointer reg if it is caller saved. */
10462 {
10463 /* Push arg pointer reg */
10466 }
10468 /* Grab the argument pointer. */
10475 /* Align the stack. */
10477 stack_pointer_rtx,
10481 /* Replicate the return address on the stack so that return
10482 address can be reached via (argp - 1) slot. This is needed
10483 to implement macro RETURN_ADDR_RTX and intrinsic function
10484 expand_builtin_return_addr etc. */
10490 /* For the purposes of frame and register save area addressing,
10491 we've started over with a new frame. */
10494 }
10500 {
10501 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10502 slower on all targets. Also sdb doesn't like it. */
10506 /* Push registers now, before setting the frame pointer
10507 on SEH target. */
10509 && TARGET_SEH
10511 {
10515 }
10518 {
10526 }
10527 }
10530 {
10531 /* If saving registers via PUSH, do so now. */
10533 {
10537 }
10539 /* When using red zone we may start register saving before allocating
10540 the stack frame saving one cycle of the prologue. However, avoid
10541 doing this if we have to probe the stack; at least on x86_64 the
10542 stack probe can turn into a call that clobbers a red zone location. */
10544 && (! TARGET_STACK_PROBE
10546 {
10549 }
10550 }
10553 {
10557 /* The computation of the size of the re-aligned stack frame means
10558 that we must allocate the size of the register save area before
10559 performing the actual alignment. Otherwise we cannot guarantee
10560 that there's enough storage above the realignment point. */
10567 /* Align the stack. */
10569 stack_pointer_rtx,
10572 /* For the purposes of register save area addressing, the stack
10573 pointer is no longer valid. As for the value of sp_offset,
10574 see ix86_compute_frame_layout, which we need to match in order
10575 to pass verification of stack_pointer_offset at the end. */
10578 }
10583 {
10584 /* We start to count from ARG_POINTER. */
10587 /* If it was realigned, take into account the fake frame. */
10589 {
10596 /* This over-estimates by 1 minimal-stack-alignment-unit but
10597 mitigates that by counting in the new return address slot. */
10598 current_function_dynamic_stack_size
10600 }
10603 }
10605 /* On SEH target with very large frame size, allocate an area to save
10606 SSE registers (as the very large allocation won't be described). */
10610 {
10611 HOST_WIDE_INT sse_size =
10616 /* No need to do stack checking as the area will be immediately
10617 written. */
10624 }
10626 /* The stack has already been decremented by the instruction calling us
10627 so probe if the size is non-negative to preserve the protection area. */
10629 {
10630 /* We expect the registers to be saved when probes are used. */
10634 {
10637 }
10638 else
10639 {
10647 else
10649 }
10650 }
10653 ;
10656 {
10660 }
10661 else
10662 {
10675 /* Note that SEH directives need to continue tracking the stack
10676 pointer even after the frame pointer has been set up. */
10678 {
10682 {
10686 }
10687 }
10690 {
10695 {
10699 }
10700 }
10705 /* Use the fact that AX still contains ALLOCATE. */
10707 ? gen_pro_epilogue_adjust_stack_di_sub
10714 {
10722 }
10726 {
10733 }
10735 {
10740 }
10741 }
10744 /* If we havn't already set up the frame pointer, do so now. */
10746 {
10758 }
10766 /* We don't use pic-register for pe-coff target. */
10768 && !TARGET_PECOFF
10771 {
10778 }
10781 {
10783 {
10785 {
10795 label));
10799 }
10800 else
10802 }
10803 else
10804 {
10808 }
10809 }
10811 /* In the pic_reg_used case, make sure that the got load isn't deleted
10812 when mcount needs it. Blockage to avoid call movement across mcount
10813 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10814 note. */
10819 {
10820 /* vDRAP is setup but after reload it turns out stack realign
10821 isn't necessary, here we will emit prologue to setup DRAP
10822 without stack realign adjustment */
10825 }
10827 /* Prevent instructions from being scheduled into register save push
10828 sequence when access to the redzone area is done through frame pointer.
10829 The offset between the frame pointer and the stack pointer is calculated
10830 relative to the value of the stack pointer at the end of the function
10831 prologue, and moving instructions that access redzone area via frame
10832 pointer inside push sequence violates this assumption. */
10836 /* Emit cld instruction if stringops are used in the function. */
10840 /* SEH requires that the prologue end within 256 bytes of the start of
10841 the function. Prevent instruction schedules that would extend that.
10842 Further, prevent alloca modifications to the stack pointer from being
10843 combined with prologue modifications. */
10846 }
10848 /* Emit code to restore REG using a POP insn. */
10850 static void
10852 {
10861 {
10862 /* Previously we'd represented the CFA as an expression
10863 like *(%ebp - 8). We've just popped that value from
10864 the stack, which means we need to reset the CFA to
10865 the drap register. This will remain until we restore
10866 the stack pointer. */
10870 /* This means that the DRAP register is valid for addressing too. */
10873 }
10876 {
10883 }
10885 /* When the frame pointer is the CFA, and we pop it, we are
10886 swapping back to the stack pointer as the CFA. This happens
10887 for stack frames that don't allocate other data, so we assume
10888 the stack pointer is now pointing at the return address, i.e.
10889 the function entry state, which makes the offset be 1 word. */
10891 {
10894 {
10902 }
10903 }
10904 }
10906 /* Emit code to restore saved registers using POP insns. */
10908 static void
10910 {
10916 }
10918 /* Emit code and notes for the LEAVE instruction. */
10920 static void
10922 {
10934 {
10942 }
10945 }
10947 /* Emit code to restore saved registers using MOV insns.
10948 First register is restored from CFA - CFA_OFFSET. */
10949 static void
10952 {
10958 {
10967 {
10968 /* Previously we'd represented the CFA as an expression
10969 like *(%ebp - 8). We've just popped that value from
10970 the stack, which means we need to reset the CFA to
10971 the drap register. This will remain until we restore
10972 the stack pointer. */
10976 /* This means that the DRAP register is valid for addressing. */
10978 }
10979 else
10983 }
10984 }
10986 /* Emit code to restore saved registers using MOV insns.
10987 First register is restored from CFA - CFA_OFFSET. */
10988 static void
10991 {
10996 {
10998 rtx mem;
11008 }
11009 }
11011 /* Restore function stack, frame, and registers. */
11013 void
11015 {
11031 /* The FP must be valid if the frame pointer is present. */
11036 /* We must have *some* valid pointer to the stack frame. */
11039 /* The DRAP is never valid at this point. */
11042 /* See the comment about red zone and frame
11043 pointer usage in ix86_expand_prologue. */
11050 /* Determine the CFA offset of the end of the red-zone. */
11053 {
11054 /* The red-zone begins below the return address. */
11057 /* When the register save area is in the aligned portion of
11058 the stack, determine the maximum runtime displacement that
11059 matches up with the aligned frame. */
11063 }
11065 /* Special care must be taken for the normal return case of a function
11066 using eh_return: the eax and edx registers are marked as saved, but
11067 not restored along this path. Adjust the save location to match. */
11071 /* EH_RETURN requires the use of moves to function properly. */
11074 /* SEH requires the use of pops to identify the epilogue. */
11077 /* If we're only restoring one register and sp is not valid then
11078 using a move instruction to restore the register since it's
11079 less work than reloading sp and popping the register. */
11092 && TARGET_USE_LEAVE
11096 else
11100 {
11101 /* Ensure that the entire register save area is addressable via
11102 the stack pointer, if we will restore via sp. */
11107 {
11111 style,
11113 }
11114 }
11116 /* If there are any SSE registers to restore, then we have to do it
11117 via moves, since there's obviously no pop for SSE regs. */
11123 {
11124 rtx t;
11129 /* eh_return epilogues need %ecx added to the stack pointer. */
11131 {
11134 /* Stack align doesn't work with eh_return. */
11136 /* Neither does regparm nested functions. */
11140 {
11148 /* Note that we use SA as a temporary CFA, as the return
11149 address is at the proper place relative to it. We
11150 pretend this happens at the FP restore insn because
11151 prior to this insn the FP would be stored at the wrong
11152 offset relative to SA, and after this insn we have no
11153 other reasonable register to use for the CFA. We don't
11154 bother resetting the CFA to the SP for the duration of
11155 the return insn. */
11168 }
11169 else
11170 {
11178 {
11182 UNITS_PER_WORD));
11184 }
11185 }
11188 }
11189 }
11190 else
11191 {
11192 /* SEH requires that the function end with (1) a stack adjustment
11193 if necessary, (2) a sequence of pops, and (3) a return or
11194 jump instruction. Prevent insns from the function body from
11195 being scheduled into this sequence. */
11197 {
11198 /* Prevent a catch region from being adjacent to the standard
11199 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11200 several other flags that would be interesting to test are
11201 not yet set up. */
11204 else
11206 }
11208 /* First step is to deallocate the stack frame so that we can
11209 pop the registers. Also do it on SEH target for very large
11210 frame as the emitted instructions aren't allowed by the ABI in
11211 epilogues. */
11213 || (TARGET_SEH
11216 {
11221 }
11223 {
11227 style,
11229 }
11232 }
11234 /* If we used a stack pointer and haven't already got rid of it,
11235 then do so now. */
11237 {
11238 /* If the stack pointer is valid and pointing at the frame
11239 pointer store address, then we only need a pop. */
11242 /* Leave results in shorter dependency chains on CPUs that are
11243 able to grok it fast. */
11248 else
11249 {
11251 hard_frame_pointer_rtx,
11254 }
11255 }
11258 {
11260 rtx insn;
11286 }
11288 /* At this point the stack pointer must be valid, and we must have
11289 restored all of the registers. We may not have deallocated the
11290 entire stack frame. We've delayed this until now because it may
11291 be possible to merge the local stack deallocation with the
11292 deallocation forced by ix86_static_chain_on_stack. */
11297 {
11301 }
11302 else
11305 /* Sibcall epilogues don't want a return instruction. */
11307 {
11310 }
11313 {
11316 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11317 address, do explicit add, and jump indirectly to the caller. */
11320 {
11322 rtx insn;
11324 /* There is no "pascal" calling convention in any 64bit ABI. */
11340 }
11341 else
11343 }
11344 else
11347 /* Restore the state back to the state from the prologue,
11348 so that it's correct for the next epilogue. */
11350 }
11352 /* Reset from the function's potential modifications. */
11354 static void
11356 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11357 {
11360 #if TARGET_MACHO
11361 /* Mach-O doesn't support labels at the end of objects, so if
11362 it looks like we might want one, insert a NOP. */
11363 {
11369 {
11370 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11371 notes only, instead set their CODE_LABEL_NUMBER to -1,
11372 otherwise there would be code generation differences
11373 in between -g and -g0. */
11377 }
11387 }
11388 #endif
11390 }
11392 /* Return a scratch register to use in the split stack prologue. The
11393 split stack prologue is used for -fsplit-stack. It is the first
11394 instructions in the function, even before the regular prologue.
11395 The scratch register can be any caller-saved register which is not
11396 used for parameters or for the static chain. */
11398 static unsigned int
11400 {
11403 else
11404 {
11417 {
11419 {
11423 }
11425 }
11427 {
11431 }
11433 {
11436 else
11437 {
11439 {
11443 }
11445 }
11446 }
11447 else
11448 {
11449 /* FIXME: We could make this work by pushing a register
11450 around the addition and comparison. */
11453 }
11454 }
11455 }
11457 /* A SYMBOL_REF for the function which allocates new stackspace for
11458 -fsplit-stack. */
11462 /* A SYMBOL_REF for the more stack function when using the large
11463 model. */
11467 /* Handle -fsplit-stack. These are the first instructions in the
11468 function, even before the regular prologue. */
11470 void
11472 {
11474 HOST_WIDE_INT allocate;
11479 rtx fn;
11487 /* This is the label we will branch to if we have enough stack
11488 space. We expect the basic block reordering pass to reverse this
11489 branch if optimizing, so that we branch in the unlikely case. */
11492 /* We need to compare the stack pointer minus the frame size with
11493 the stack boundary in the TCB. The stack boundary always gives
11494 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11495 can compare directly. Otherwise we need to do an addition. */
11498 UNSPEC_STACK_CHECK);
11503 else
11504 {
11506 rtx offset;
11508 /* We need a scratch register to hold the stack pointer minus
11509 the required frame size. Since this is the very start of the
11510 function, the scratch register can be any caller-saved
11511 register which is not used for parameters. */
11518 {
11519 /* We don't use ix86_gen_add3 in this case because it will
11520 want to split to lea, but when not optimizing the insn
11521 will not be split after this point. */
11524 offset)));
11525 }
11526 else
11527 {
11530 stack_pointer_rtx));
11531 }
11533 }
11539 /* Mark the jump as very likely to be taken. */
11547 /* Get more stack space. We pass in the desired stack space and the
11548 size of the arguments to copy to the new stack. In 32-bit mode
11549 we push the parameters; __morestack will return on a new stack
11550 anyhow. In 64-bit mode we pass the parameters in r10 and
11551 r11. */
11556 {
11562 /* If this function uses a static chain, it will be in %r10.
11563 Preserve it across the call to __morestack. */
11565 {
11566 rtx rax;
11571 }
11575 {
11576 HOST_WIDE_INT argval;
11579 /* When using the large model we need to load the address
11580 into a register, and we've run out of registers. So we
11581 switch to a different calling convention, and we call a
11582 different function: __morestack_large. We pass the
11583 argument size in the upper 32 bits of r10 and pass the
11584 frame size in the lower 32 bits. */
11589 split_stack_fn_large =
11593 {
11603 UNSPEC_GOT);
11609 }
11610 else
11617 }
11618 else
11619 {
11623 }
11626 }
11627 else
11628 {
11631 }
11637 /* In order to make call/return prediction work right, we now need
11638 to execute a return instruction. See
11639 libgcc/config/i386/morestack.S for the details on how this works.
11641 For flow purposes gcc must not see this as a return
11642 instruction--we need control flow to continue at the subsequent
11643 label. Therefore, we use an unspec. */
11647 /* If we are in 64-bit mode and this function uses a static chain,
11648 we saved %r10 in %rax before calling _morestack. */
11653 /* If this function calls va_start, we need to store a pointer to
11654 the arguments on the old stack, because they may not have been
11655 all copied to the new stack. At this point the old stack can be
11656 found at the frame pointer value used by __morestack, because
11657 __morestack has set that up before calling back to us. Here we
11658 store that pointer in a scratch register, and in
11659 ix86_expand_prologue we store the scratch register in a stack
11660 slot. */
11662 {
11664 rtx frame_reg;
11671 /* 64-bit:
11672 fp -> old fp value
11673 return address within this function
11674 return address of caller of this function
11675 stack arguments
11676 So we add three words to get to the stack arguments.
11678 32-bit:
11679 fp -> old fp value
11680 return address within this function
11681 first argument to __morestack
11682 second argument to __morestack
11683 return address of caller of this function
11684 stack arguments
11685 So we add five words to get to the stack arguments.
11686 */
11697 }
11702 /* If this function calls va_start, we now have to set the scratch
11703 register for the case where we do not call __morestack. In this
11704 case we need to set it based on the stack pointer. */
11706 {
11713 }
11714 }
11716 /* We may have to tell the dataflow pass that the split stack prologue
11717 is initializing a scratch register. */
11719 static void
11721 {
11723 {
11726 }
11727 }
11728 \f
11729 /* Determine if op is suitable SUBREG RTX for address. */
11731 static bool
11733 {
11744 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11745 failures when the register is one word out of a two word structure. */
11749 /* Allow only SUBREGs of non-eliminable hard registers. */
11751 }
11753 /* Extract the parts of an RTL expression that is a valid memory address
11754 for an instruction. Return 0 if the structure of the address is
11755 grossly off. Return -1 if the address contains ASHIFT, so it is not
11756 strictly valid, but still used for computing length of lea instruction. */
11758 int
11760 {
11765 rtx tmp;
11769 /* Allow zero-extended SImode addresses,
11770 they will be emitted with addr32 prefix. */
11772 {
11775 {
11779 }
11782 {
11789 }
11790 }
11792 /* Allow SImode subregs of DImode addresses,
11793 they will be emitted with addr32 prefix. */
11795 {
11798 {
11802 }
11803 }
11808 {
11811 else
11813 }
11815 {
11820 do
11821 {
11826 }
11833 {
11836 {
11861 /* FALLTHRU */
11865 && TARGET_TLS_DIRECT_SEG_REFS
11868 else
11875 /* FALLTHRU */
11882 else
11897 }
11898 }
11899 }
11901 {
11904 }
11906 {
11907 /* We're called for lea too, which implements ashift on occasion. */
11917 }
11919 {
11923 /* Constant addresses are sign extended to 64bit, we have to
11924 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11930 }
11931 else
11935 {
11937 ;
11940 ;
11941 else
11943 }
11945 /* Address override works only on the (%reg) part of %fs:(%reg). */
11951 /* Extract the integral value of scale. */
11953 {
11957 }
11962 /* Avoid useless 0 displacement. */
11966 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11971 {
11972 rtx tmp;
11975 }
11977 /* Special case: %ebp cannot be encoded as a base without a displacement.
11978 Similarly %r13. */
11980 && base_reg
11989 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11990 Avoid this by transforming to [%esi+0].
11991 Reload calls address legitimization without cfun defined, so we need
11992 to test cfun for being non-NULL. */
11998 /* Special case: encode reg+reg instead of reg*2. */
12002 /* Special case: scaling cannot be encoded without base or displacement. */
12013 }
12014 \f
12015 /* Return cost of the memory address x.
12016 For i386, it is better to use a complex address than let gcc copy
12017 the address into a reg and make a new pseudo. But not if the address
12018 requires to two regs - that would mean more pseudos with longer
12019 lifetimes. */
12020 static int
12022 addr_space_t as ATTRIBUTE_UNUSED,
12024 {
12036 /* Attempt to minimize number of registers in the address. */
12042 cost++;
12049 cost++;
12051 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12052 since it's predecode logic can't detect the length of instructions
12053 and it degenerates to vector decoded. Increase cost of such
12054 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12055 to split such addresses or even refuse such addresses at all.
12057 Following addressing modes are affected:
12058 [base+scale*index]
12059 [scale*index+disp]
12060 [base+index]
12062 The first and last case may be avoidable by explicitly coding the zero in
12063 memory address, but I don't have AMD-K6 machine handy to check this
12064 theory. */
12073 }
12074 \f
12075 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12076 this is used for to form addresses to local data when -fPIC is in
12077 use. */
12079 static bool
12081 {
12084 }
12086 /* Determine if a given RTX is a valid constant. We already know this
12087 satisfies CONSTANT_P. */
12089 static bool
12091 {
12093 {
12098 {
12102 }
12107 /* Only some unspecs are valid as "constants". */
12110 {
12126 }
12128 /* We must have drilled down to a symbol. */
12133 /* FALLTHRU */
12136 /* TLS symbols are never valid. */
12140 /* DLLIMPORT symbols are never valid. */
12145 #if TARGET_MACHO
12146 /* mdynamic-no-pic */
12149 #endif
12165 }
12167 /* Otherwise we handle everything else in the move patterns. */
12169 }
12171 /* Determine if it's legal to put X into the constant pool. This
12172 is not possible for the address of thread-local symbols, which
12173 is checked above. */
12175 static bool
12177 {
12178 /* We can always put integral constants and vectors in memory. */
12180 {
12188 }
12190 }
12192 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12193 otherwise zero. */
12195 static bool
12197 {
12203 }
12206 /* Nonzero if the constant value X is a legitimate general operand
12207 when generating PIC code. It is given that flag_pic is on and
12208 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12210 bool
12212 {
12213 rtx inner;
12216 {
12223 /* Only some unspecs are valid as "constants". */
12226 {
12239 }
12240 /* FALLTHRU */
12248 }
12249 }
12251 /* Determine if a given CONST RTX is a valid memory displacement
12252 in PIC mode. */
12254 bool
12256 {
12259 /* In 64bit mode we can allow direct addresses of symbols and labels
12260 when they are not dynamic symbols. */
12262 {
12266 {
12290 /* FALLTHRU */
12293 /* TLS references should always be enclosed in UNSPEC.
12294 The dllimported symbol needs always to be resolved. */
12300 {
12308 /* Function-symbols need to be resolved only for
12309 large-model.
12310 For the small-model we don't need to resolve anything
12311 here. */
12316 /* Non-external symbols don't need to be resolved for
12317 large, and medium-model. */
12322 }
12331 }
12332 }
12338 {
12339 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12340 of GOT tables. We should not need these anyway. */
12352 }
12356 {
12361 }
12370 {
12374 /* We need to check for both symbols and labels because VxWorks loads
12375 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12376 details. */
12380 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12381 While ABI specify also 32bit relocation but we don't produce it in
12382 small PIC model at all. */
12404 }
12407 }
12409 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12410 replace the input X, or the original X if no replacement is called for.
12411 The output parameter *WIN is 1 if the calling macro should goto WIN,
12412 0 if it should not. */
12414 bool
12419 {
12420 /* Reload can generate:
12422 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12423 (reg:DI 97))
12424 (reg:DI 2 cx))
12426 This RTX is rejected from ix86_legitimate_address_p due to
12427 non-strictness of base register 97. Following this rejection,
12428 reload pushes all three components into separate registers,
12429 creating invalid memory address RTX.
12431 Following code reloads only the invalid part of the
12432 memory address RTX. */
12438 {
12444 {
12449 }
12453 {
12458 }
12462 }
12465 }
12467 /* Recognizes RTL expressions that are valid memory addresses for an
12468 instruction. The MODE argument is the machine mode for the MEM
12469 expression that wants to use this address.
12471 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12472 convert common non-canonical forms to canonical form so that they will
12473 be recognized. */
12475 static bool
12478 {
12481 HOST_WIDE_INT scale;
12484 /* Decomposition failed. */
12492 /* Validate base register. */
12494 {
12495 rtx reg;
12501 else
12502 /* Base is not a register. */
12510 /* Base is not valid. */
12512 }
12514 /* Validate index register. */
12516 {
12517 rtx reg;
12523 else
12524 /* Index is not a register. */
12532 /* Index is not valid. */
12534 }
12536 /* Index and base should have the same mode. */
12541 /* Validate scale factor. */
12543 {
12545 /* Scale without index. */
12549 /* Scale is not a valid multiplier. */
12551 }
12553 /* Validate displacement. */
12555 {
12560 {
12561 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12562 used. While ABI specify also 32bit relocations, we don't produce
12563 them at all and use IP relative instead. */
12570 /* 64bit address unspec. */
12590 /* Invalid address unspec. */
12592 }
12595 && (flag_pic
12596 || (TARGET_MACHO
12597 #if TARGET_MACHO
12598 && MACHOPIC_INDIRECT
12600 #endif
12601 )))
12602 {
12604 is_legitimate_pic:
12606 {
12607 /* foo@dtpoff(%rX) is ok. */
12614 /* Non-constant pic memory reference. */
12616 }
12619 /* Displacement is an invalid pic construct. */
12621 #if TARGET_MACHO
12624 /* displacment must be referenced via non_lazy_pointer */
12626 #endif
12628 /* This code used to verify that a symbolic pic displacement
12629 includes the pic_offset_table_rtx register.
12631 While this is good idea, unfortunately these constructs may
12632 be created by "adds using lea" optimization for incorrect
12633 code like:
12635 int a;
12636 int foo(int i)
12637 {
12638 return *(&a+i);
12639 }
12641 This code is nonsensical, but results in addressing
12642 GOT table with pic_offset_table_rtx base. We can't
12643 just refuse it easily, since it gets matched by
12644 "addsi3" pattern, that later gets split to lea in the
12645 case output register differs from input. While this
12646 can be handled by separate addsi pattern for this case
12647 that never results in lea, this seems to be easier and
12648 correct fix for crash to disable this test. */
12649 }
12656 /* Displacement is not constant. */
12660 /* Displacement is out of range. */
12662 }
12664 /* Everything looks valid. */
12666 }
12668 /* Determine if a given RTX is a valid constant address. */
12670 bool
12672 {
12674 }
12675 \f
12676 /* Return a unique alias set for the GOT. */
12678 static alias_set_type
12680 {
12685 }
12687 /* Return a legitimate reference for ORIG (an address) using the
12688 register REG. If REG is 0, a new pseudo is generated.
12690 There are two types of references that must be handled:
12692 1. Global data references must load the address from the GOT, via
12693 the PIC reg. An insn is emitted to do this load, and the reg is
12694 returned.
12696 2. Static data references, constant pool addresses, and code labels
12697 compute the address as an offset from the GOT, whose base is in
12698 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12699 differentiate them from global data objects. The returned
12700 address is the PIC reg + an unspec constant.
12702 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12703 reg also appears in the address. */
12705 static rtx
12707 {
12711 #if TARGET_MACHO
12713 {
12716 /* Use the generic Mach-O PIC machinery. */
12718 }
12719 #endif
12722 {
12726 }
12732 {
12733 rtx tmpreg;
12734 /* This symbol may be referenced via a displacement from the PIC
12735 base address (@GOTOFF). */
12742 {
12744 UNSPEC_GOTOFF);
12746 }
12747 else
12752 else
12757 {
12761 }
12762 else
12764 }
12766 {
12767 /* This symbol may be referenced via a displacement from the PIC
12768 base address (@GOTOFF). */
12775 {
12777 UNSPEC_GOTOFF);
12779 }
12780 else
12786 {
12789 }
12790 }
12792 /* We can't use @GOTOFF for text labels on VxWorks;
12793 see gotoff_operand. */
12795 {
12800 /* For x64 PE-COFF there is no GOT table. So we use address
12801 directly. */
12803 {
12811 }
12813 {
12821 /* Use directly gen_movsi, otherwise the address is loaded
12822 into register for CSE. We don't want to CSE this addresses,
12823 instead we CSE addresses from the GOT table, so skip this. */
12826 }
12827 else
12828 {
12829 /* This symbol must be referenced via a load from the
12830 Global Offset Table (@GOT). */
12846 }
12847 }
12848 else
12849 {
12852 {
12854 {
12857 }
12858 else
12860 }
12862 {
12865 /* We must match stuff we generate before. Assume the only
12866 unspecs that can get here are ours. Not that we could do
12867 anything with them anyway.... */
12873 }
12875 {
12878 /* Check first to see if this is a constant offset from a @GOTOFF
12879 symbol reference. */
12882 {
12884 {
12888 UNSPEC_GOTOFF);
12894 {
12897 }
12898 }
12899 else
12900 {
12903 {
12907 }
12908 }
12909 }
12910 else
12911 {
12914 new_rtx
12918 {
12921 {
12924 new_rtx
12926 }
12927 else
12929 }
12930 else
12931 {
12934 {
12937 }
12939 }
12940 }
12941 }
12942 }
12944 }
12945 \f
12946 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12948 static rtx
12950 {
12954 {
12959 }
12965 }
12967 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12971 static rtx
12973 {
12975 {
12981 }
12984 {
12986 UNSPEC_PLTOFF);
12989 }
12992 }
12994 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12998 rtx
13000 {
13002 {
13003 ix86_tls_module_base_symbol
13008 }
13011 }
13013 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13014 false if we expect this to be used for a memory address and true if
13015 we expect to load the address into a register. */
13017 static rtx
13019 {
13026 {
13031 {
13034 else
13035 {
13038 }
13039 }
13042 {
13045 else
13055 }
13056 else
13057 {
13061 {
13063 rtx insns;
13066 emit_call_insn
13076 }
13077 else
13079 }
13086 {
13089 else
13090 {
13093 }
13094 }
13097 {
13102 else
13108 }
13109 else
13110 {
13114 {
13119 emit_call_insn
13124 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13125 share the LD_BASE result with other LD model accesses. */
13127 UNSPEC_TLS_LD_BASE);
13131 }
13132 else
13134 }
13142 {
13149 }
13154 {
13156 {
13157 /* The Sun linker took the AMD64 TLS spec literally
13158 and can only handle %rax as destination of the
13159 initial executable code sequence. */
13164 }
13166 /* Generate DImode references to avoid %fs:(%reg32)
13167 problems and linker IE->LE relaxation bug. */
13171 }
13173 {
13178 }
13180 {
13184 }
13185 else
13186 {
13189 }
13199 {
13204 }
13205 else
13206 {
13210 }
13220 {
13224 }
13225 else
13226 {
13230 }
13235 }
13238 }
13240 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13241 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13242 unique refptr-DECL symbol corresponding to symbol DECL. */
13245 htab_t dllimport_map;
13247 static tree
13249 {
13256 tree to;
13257 rtx rtl;
13284 else
13297 {
13299 #ifdef SUB_TARGET_RECORD_STUB
13301 #endif
13302 }
13311 }
13313 /* Expand SYMBOL into its corresponding far-addresse symbol.
13314 WANT_REG is true if we require the result be a register. */
13316 static rtx
13318 {
13319 tree imp_decl;
13320 rtx x;
13329 }
13331 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13332 true if we require the result be a register. */
13334 static rtx
13336 {
13337 tree imp_decl;
13338 rtx x;
13347 }
13349 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13350 is true if we require the result be a register. */
13352 static rtx
13354 {
13359 {
13366 {
13369 }
13370 }
13386 {
13389 }
13391 }
13393 /* Try machine-dependent ways of modifying an illegitimate address
13394 to be legitimate. If we find one, return the new, valid address.
13395 This macro is used in only one place: `memory_address' in explow.c.
13397 OLDX is the address as it was before break_out_memory_refs was called.
13398 In some cases it is useful to look at this to decide what needs to be done.
13400 It is always safe for this macro to do nothing. It exists to recognize
13401 opportunities to optimize the output.
13403 For the 80386, we handle X+REG by loading X into a register R and
13404 using R+REG. R will go in a general reg and indexing will be used.
13405 However, if REG is a broken-out memory address or multiplication,
13406 nothing needs to be done because REG can certainly go in a general reg.
13408 When -fpic is used, special handling is needed for symbolic references.
13409 See comments by legitimize_pic_address in i386.c for details. */
13411 static rtx
13414 {
13425 {
13429 }
13432 {
13436 }
13441 #if TARGET_MACHO
13444 #endif
13446 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13450 {
13455 }
13458 {
13459 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13464 {
13470 }
13475 {
13481 }
13483 /* Put multiply first if it isn't already. */
13485 {
13490 }
13492 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13493 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13494 created by virtual register instantiation, register elimination, and
13495 similar optimizations. */
13497 {
13503 }
13505 /* Canonicalize
13506 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13507 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13512 {
13513 rtx constant;
13517 {
13520 }
13522 {
13525 }
13526 else
13530 {
13537 }
13538 }
13544 {
13547 }
13550 {
13553 }
13561 {
13564 }
13570 {
13574 {
13577 }
13581 }
13584 {
13588 {
13591 }
13595 }
13596 }
13599 }
13600 \f
13601 /* Print an integer constant expression in assembler syntax. Addition
13602 and subtraction are the only arithmetic that may appear in these
13603 expressions. FILE is the stdio stream to write to, X is the rtx, and
13604 CODE is the operand print code from the output string. */
13606 static void
13608 {
13612 {
13621 else
13622 {
13625 /* Mark the decl as referenced so that cgraph will
13626 output the function. */
13630 #if TARGET_MACHO
13634 #endif
13636 }
13644 /* FALLTHRU */
13655 /* This used to output parentheses around the expression,
13656 but that does not work on the 386 (either ATT or BSD assembler). */
13662 {
13663 /* We can use %d if the number is <32 bits and positive. */
13668 else
13670 }
13671 else
13672 /* We can't handle floating point constants;
13673 TARGET_PRINT_OPERAND must handle them. */
13678 /* Some assemblers need integer constants to appear first. */
13680 {
13684 }
13685 else
13686 {
13691 }
13706 {
13710 }
13715 {
13734 /* FIXME: This might be @TPOFF in Sun ld too. */
13743 else
13753 else
13759 #if TARGET_MACHO
13764 #endif
13768 }
13773 }
13774 }
13776 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13777 We need to emit DTP-relative relocations. */
13779 static void ATTRIBUTE_UNUSED
13781 {
13786 {
13794 }
13795 }
13797 /* Return true if X is a representation of the PIC register. This copes
13798 with calls from ix86_find_base_term, where the register might have
13799 been replaced by a cselib value. */
13801 static bool
13803 {
13807 else
13809 }
13811 /* Helper function for ix86_delegitimize_address.
13812 Attempt to delegitimize TLS local-exec accesses. */
13814 static rtx
13816 {
13841 {
13846 }
13852 }
13854 /* In the name of slightly smaller debug output, and to cater to
13855 general assembler lossage, recognize PIC+GOTOFF and turn it back
13856 into a direct symbol reference.
13858 On Darwin, this is necessary to avoid a crash, because Darwin
13859 has a different PIC label for each routine but the DWARF debugging
13860 information is not associated with any particular routine, so it's
13861 necessary to remove references to the PIC label from RTL stored by
13862 the DWARF output code. */
13864 static rtx
13866 {
13868 /* addend is NULL or some rtx if x is something+GOTOFF where
13869 something doesn't include the PIC register. */
13871 /* reg_addend is NULL or a multiple of some register. */
13873 /* const_addend is NULL or a const_int. */
13875 /* This is the result, or NULL. */
13884 {
13891 {
13897 }
13904 {
13907 {
13912 }
13914 }
13919 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
13920 and -mcmodel=medium -fpic. */
13921 }
13928 /* %ebx + GOT/GOTOFF */
13929 ;
13931 {
13932 /* %ebx + %reg * scale + GOT/GOTOFF */
13938 else
13939 {
13942 }
13943 }
13944 else
13950 {
13953 }
13974 {
13975 /* If the rest of original X doesn't involve the PIC register, add
13976 addend and subtract pic_offset_table_rtx. This can happen e.g.
13977 for code like:
13978 leal (%ebx, %ecx, 4), %ecx
13979 ...
13980 movl foo@GOTOFF(%ecx), %edx
13981 in which case we return (%ecx - %ebx) + foo. */
13984 pic_offset_table_rtx),
13985 result);
13986 else
13988 }
13990 {
13994 }
13996 }
13998 /* If X is a machine specific address (i.e. a symbol or label being
13999 referenced as a displacement from the GOT implemented using an
14000 UNSPEC), then return the base term. Otherwise return X. */
14002 rtx
14004 {
14005 rtx term;
14008 {
14022 }
14025 }
14026 \f
14027 static void
14030 {
14034 {
14037 }
14042 {
14045 {
14064 }
14068 {
14087 }
14094 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14095 Those same assemblers have the same but opposite lossage on cmov. */
14100 else
14105 {
14118 }
14126 {
14139 }
14142 /* ??? As above. */
14151 /* ??? As above. */
14156 else
14167 }
14169 }
14171 /* Print the name of register X to FILE based on its machine mode and number.
14172 If CODE is 'w', pretend the mode is HImode.
14173 If CODE is 'b', pretend the mode is QImode.
14174 If CODE is 'k', pretend the mode is SImode.
14175 If CODE is 'q', pretend the mode is DImode.
14176 If CODE is 'x', pretend the mode is V4SFmode.
14177 If CODE is 't', pretend the mode is V8SFmode.
14178 If CODE is 'g', pretend the mode is V16SFmode.
14179 If CODE is 'h', pretend the reg is the 'high' byte register.
14180 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14181 If CODE is 'd', duplicate the operand for AVX instruction.
14182 */
14184 void
14186 {
14195 {
14199 }
14226 else
14229 /* Irritatingly, AMD extended registers use different naming convention
14230 from the normal registers: "r%d[bwd]" */
14232 {
14237 {
14251 /* no suffix */
14256 }
14258 }
14262 {
14265 {
14268 }
14269 /* FALLTHRU */
14275 /* FALLTHRU */
14278 normal:
14293 {
14298 }
14301 {
14306 }
14310 }
14314 {
14317 else
14319 }
14320 }
14322 /* Locate some local-dynamic symbol still in use by this function
14323 so that we can print its name in some tls_local_dynamic_base
14324 pattern. */
14326 static int
14328 {
14333 {
14336 }
14339 }
14343 {
14344 rtx insn;
14355 }
14357 /* Meaning of CODE:
14358 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14359 C -- print opcode suffix for set/cmov insn.
14360 c -- like C, but print reversed condition
14361 F,f -- likewise, but for floating-point.
14362 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14363 otherwise nothing
14364 R -- print the prefix for register names.
14365 z -- print the opcode suffix for the size of the current operand.
14366 Z -- likewise, with special suffixes for x87 instructions.
14367 * -- print a star (in certain assembler syntax)
14368 A -- print an absolute memory reference.
14369 E -- print address with DImode register names if TARGET_64BIT.
14370 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14371 s -- print a shift double count, followed by the assemblers argument
14372 delimiter.
14373 b -- print the QImode name of the register for the indicated operand.
14374 %b0 would print %al if operands[0] is reg 0.
14375 w -- likewise, print the HImode name of the register.
14376 k -- likewise, print the SImode name of the register.
14377 q -- likewise, print the DImode name of the register.
14378 x -- likewise, print the V4SFmode name of the register.
14379 t -- likewise, print the V8SFmode name of the register.
14380 g -- likewise, print the V16SFmode name of the register.
14381 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14382 y -- print "st(0)" instead of "st" as a register.
14383 d -- print duplicated register operand for AVX instruction.
14384 D -- print condition for SSE cmp instruction.
14385 P -- if PIC, print an @PLT suffix.
14386 p -- print raw symbol name.
14387 X -- don't print any sort of PIC '@' suffix for a symbol.
14388 & -- print some in-use local-dynamic symbol name.
14389 H -- print a memory address offset by 8; used for sse high-parts
14390 Y -- print condition for XOP pcom* instruction.
14391 + -- print a branch hint as 'cs' or 'ds' prefix
14392 ; -- print a semicolon (after prefixes due to bug in older gas).
14393 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14394 @ -- print a segment register of thread base pointer load
14395 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14396 */
14398 void
14400 {
14402 {
14404 {
14407 {
14413 /* Intel syntax. For absolute addresses, registers should not
14414 be surrounded by braces. */
14416 {
14421 }
14426 }
14432 /* Wrap address in an UNSPEC to declare special handling. */
14470 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14475 {
14489 output_operand_lossage
14492 }
14495 #endif
14500 {
14501 /* Opcodes don't get size suffixes if using Intel opcodes. */
14506 {
14524 output_operand_lossage
14527 }
14528 }
14531 warning
14533 /* FALLTHRU */
14536 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14541 {
14543 {
14545 #ifdef HAVE_AS_IX86_FILDS
14547 #endif
14555 #ifdef HAVE_AS_IX86_FILDQ
14557 #else
14559 #endif
14564 }
14565 }
14567 {
14568 /* 387 opcodes don't get size suffixes
14569 if the operands are registers. */
14574 {
14590 }
14591 }
14592 else
14593 {
14594 output_operand_lossage
14597 }
14599 output_operand_lossage
14620 {
14623 }
14628 {
14679 }
14683 /* Little bit of braindamage here. The SSE compare instructions
14684 does use completely different names for the comparisons that the
14685 fp conditional moves. */
14687 {
14690 {
14693 }
14699 {
14702 }
14708 {
14711 }
14720 {
14723 }
14729 {
14732 }
14738 {
14741 }
14752 }
14757 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14760 #endif
14765 {
14769 }
14773 file);
14778 {
14782 }
14783 /* It doesn't actually matter what mode we use here, as we're
14784 only going to use this for printing. */
14786 /* Output 'qword ptr' for intel assembler dialect. */
14795 #ifdef HAVE_AS_IX86_HLE
14797 #else
14799 #endif
14801 #ifdef HAVE_AS_IX86_HLE
14803 #else
14805 #endif
14806 /* We do not want to print value of the operand. */
14815 {
14820 else
14823 }
14826 {
14827 rtx x;
14836 {
14841 {
14843 bool cputaken
14846 /* Emit hints only in the case default branch prediction
14847 heuristics would fail. */
14849 {
14850 /* We use 3e (DS) prefix for taken branches and
14851 2e (CS) prefix for not taken branches. */
14854 else
14856 }
14857 }
14858 }
14860 }
14863 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14865 #endif
14872 /* The kernel uses a different segment register for performance
14873 reasons; a system call would not have to trash the userspace
14874 segment register, which would be expensive. */
14877 else
14892 }
14893 }
14899 {
14900 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14903 {
14906 {
14915 else
14922 }
14924 /* Check for explicit size override (codes 'b', 'w', 'k',
14925 'q' and 'x') */
14939 }
14942 /* Avoid (%rip) for call operands. */
14948 else
14950 }
14953 {
14954 REAL_VALUE_TYPE r;
14962 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14966 else
14968 }
14971 {
14972 REAL_VALUE_TYPE r;
14981 }
14983 /* These float cases don't actually occur as immediate operands. */
14985 {
14990 }
14992 else
14993 {
14994 /* We have patterns that allow zero sets of memory, for instance.
14995 In 64-bit mode, we should probably support all 8-byte vectors,
14996 since we can in fact encode that into an immediate. */
14998 {
15001 }
15004 {
15006 {
15009 }
15012 {
15015 else
15017 }
15018 }
15023 else
15025 }
15026 }
15028 static bool
15030 {
15033 }
15034 \f
15035 /* Print a memory operand whose address is ADDR. */
15037 static void
15039 {
15048 {
15055 }
15057 {
15061 }
15062 else
15073 {
15084 }
15086 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15088 {
15100 }
15102 {
15103 /* Displacement only requires special attention. */
15106 {
15110 }
15113 else
15115 }
15116 else
15117 {
15118 /* Print SImode register names to force addr32 prefix. */
15120 {
15121 #ifdef ENABLE_CHECKING
15124 {
15135 }
15136 #endif
15139 }
15141 && TARGET_X32
15142 && disp
15145 {
15146 /* X32 runs in 64-bit mode, where displacement, DISP, in
15147 address DISP(%r64), is encoded as 32-bit immediate sign-
15148 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15149 address is %r64 + 0xffffffffbffffd00. When %r64 <
15150 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15151 which is invalid for x32. The correct address is %r64
15152 - 0x40000300 == 0xf7ffdd64. To properly encode
15153 -0x40000300(%r64) for x32, we zero-extend negative
15154 displacement by forcing addr32 prefix which truncates
15155 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15156 zero-extend all negative displacements, including -1(%rsp).
15157 However, for small negative displacements, sign-extension
15158 won't cause overflow. We only zero-extend negative
15159 displacements if they < -16*1024*1024, which is also used
15160 to check legitimate address displacements for PIC. */
15162 }
15165 {
15167 {
15172 else
15174 }
15180 {
15185 }
15187 }
15188 else
15189 {
15193 {
15194 /* Pull out the offset of a symbol; print any symbol itself. */
15198 {
15202 }
15210 else
15212 }
15216 {
15219 {
15223 }
15224 }
15227 else
15231 {
15236 }
15238 }
15239 }
15240 }
15242 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15244 static bool
15246 {
15247 rtx op;
15254 {
15257 /* FIXME: This might be @TPOFF in Sun ld. */
15268 else
15280 else
15287 #if TARGET_MACHO
15293 #endif
15296 {
15301 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15303 #else
15305 #endif
15308 }
15313 }
15316 }
15317 \f
15318 /* Split one or more double-mode RTL references into pairs of half-mode
15319 references. The RTL can be REG, offsettable MEM, integer constant, or
15320 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15321 split and "num" is its length. lo_half and hi_half are output arrays
15322 that parallel "operands". */
15324 void
15327 {
15332 {
15341 }
15346 {
15349 /* simplify_subreg refuse to split volatile memory addresses,
15350 but we still have to handle it. */
15352 {
15355 }
15356 else
15357 {
15364 }
15365 }
15366 }
15367 \f
15368 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15369 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15370 is the expression of the binary operation. The output may either be
15371 emitted here, or returned to the caller, like all output_* functions.
15373 There is no guarantee that the operands are the same mode, as they
15374 might be within FLOAT or FLOAT_EXTEND expressions. */
15376 #ifndef SYSV386_COMPAT
15377 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15378 wants to fix the assemblers because that causes incompatibility
15379 with gcc. No-one wants to fix gcc because that causes
15380 incompatibility with assemblers... You can use the option of
15381 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15382 #define SYSV386_COMPAT 1
15383 #endif
15387 {
15393 #ifdef ENABLE_CHECKING
15394 /* Even if we do not want to check the inputs, this documents input
15395 constraints. Which helps in understanding the following code. */
15405 else
15407 #endif
15410 {
15415 else
15424 else
15433 else
15442 else
15449 }
15452 {
15454 {
15458 else
15460 }
15461 else
15462 {
15466 else
15468 }
15470 }
15474 {
15478 {
15482 }
15484 /* know operands[0] == operands[1]. */
15487 {
15490 }
15493 {
15495 /* How is it that we are storing to a dead operand[2]?
15496 Well, presumably operands[1] is dead too. We can't
15497 store the result to st(0) as st(0) gets popped on this
15498 instruction. Instead store to operands[2] (which I
15499 think has to be st(1)). st(1) will be popped later.
15500 gcc <= 2.8.1 didn't have this check and generated
15501 assembly code that the Unixware assembler rejected. */
15503 else
15506 }
15510 else
15517 {
15520 }
15523 {
15526 }
15529 {
15530 #if SYSV386_COMPAT
15531 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15532 derived assemblers, confusingly reverse the direction of
15533 the operation for fsub{r} and fdiv{r} when the
15534 destination register is not st(0). The Intel assembler
15535 doesn't have this brain damage. Read !SYSV386_COMPAT to
15536 figure out what the hardware really does. */
15539 else
15541 #else
15543 /* As above for fmul/fadd, we can't store to st(0). */
15545 else
15547 #endif
15549 }
15552 {
15553 #if SYSV386_COMPAT
15556 else
15558 #else
15561 else
15563 #endif
15565 }
15568 {
15571 else
15574 }
15576 {
15577 #if SYSV386_COMPAT
15579 #else
15581 #endif
15582 }
15583 else
15584 {
15585 #if SYSV386_COMPAT
15587 #else
15589 #endif
15590 }
15595 }
15599 }
15601 /* Check if a 256bit AVX register is referenced inside of EXP. */
15603 static int
15605 {
15616 }
15618 /* Return needed mode for entity in optimize_mode_switching pass. */
15620 static int
15622 {
15624 {
15625 rtx link;
15627 /* Needed mode is set to AVX_U128_CLEAN if there are
15628 no 256bit modes used in function arguments. */
15630 link;
15632 {
15634 {
15639 }
15640 }
15643 }
15645 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15646 changes state only when a 256bit register is written to, but we need
15647 to prevent the compiler from moving optimal insertion point above
15648 eventual read from 256bit register. */
15653 }
15655 /* Return mode that i387 must be switched into
15656 prior to the execution of insn. */
15658 static int
15660 {
15663 /* The mode UNINITIALIZED is used to store control word after a
15664 function call or ASM pattern. The mode ANY specify that function
15665 has no requirements on the control word and make no changes in the
15666 bits we are interested in. */
15680 {
15703 }
15706 }
15708 /* Return mode that entity must be switched into
15709 prior to the execution of insn. */
15711 int
15713 {
15715 {
15725 }
15727 }
15729 /* Check if a 256bit AVX register is referenced in stores. */
15731 static void
15733 {
15735 {
15738 }
15739 }
15741 /* Calculate mode of upper 128bit AVX registers after the insn. */
15743 static int
15745 {
15752 /* We know that state is clean after CALL insn if there are no
15753 256bit registers used in the function return register. */
15755 {
15760 }
15762 /* Otherwise, return current mode. Remember that if insn
15763 references AVX 256bit registers, the mode was already changed
15764 to DIRTY from MODE_NEEDED. */
15766 }
15768 /* Return the mode that an insn results in. */
15770 int
15772 {
15774 {
15784 }
15785 }
15787 static int
15789 {
15790 tree arg;
15792 /* Entry mode is set to AVX_U128_DIRTY if there are
15793 256bit modes used in function arguments. */
15796 {
15801 }
15804 }
15806 /* Return a mode that ENTITY is assumed to be
15807 switched to at function entry. */
15809 int
15811 {
15813 {
15823 }
15824 }
15826 static int
15828 {
15831 /* Exit mode is set to AVX_U128_DIRTY if there are
15832 256bit modes used in the function return register. */
15837 }
15839 /* Return a mode that ENTITY is assumed to be
15840 switched to at function exit. */
15842 int
15844 {
15846 {
15856 }
15857 }
15859 /* Output code to initialize control word copies used by trunc?f?i and
15860 rounding patterns. CURRENT_MODE is set to current control word,
15861 while NEW_MODE is set to new control word. */
15863 static void
15865 {
15867 rtx new_mode;
15878 {
15880 {
15882 /* round toward zero (truncate) */
15888 /* round down toward -oo */
15895 /* round up toward +oo */
15902 /* mask precision exception for nearbyint() */
15909 }
15910 }
15911 else
15912 {
15914 {
15916 /* round toward zero (truncate) */
15922 /* round down toward -oo */
15928 /* round up toward +oo */
15934 /* mask precision exception for nearbyint() */
15941 }
15942 }
15948 }
15950 /* Emit vzeroupper. */
15952 void
15954 {
15957 /* Cancel automatic vzeroupper insertion if there are
15958 live call-saved SSE registers at the insertion point. */
15970 }
15972 /* Generate one or more insns to set ENTITY to MODE. */
15974 void
15976 {
15978 {
15993 }
15994 }
15996 /* Output code for INSN to convert a float to a signed int. OPERANDS
15997 are the insn operands. The output may be [HSD]Imode and the input
15998 operand may be [SDX]Fmode. */
16002 {
16007 /* Jump through a hoop or two for DImode, since the hardware has no
16008 non-popping instruction. We used to do this a different way, but
16009 that was somewhat fragile and broke with post-reload splitters. */
16019 else
16020 {
16025 else
16029 }
16032 }
16034 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16035 have the values zero or one, indicates the ffreep insn's operand
16036 from the OPERANDS array. */
16040 {
16042 #ifdef HAVE_AS_IX86_FFREEP
16044 #else
16045 {
16055 }
16056 #endif
16059 }
16062 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16063 should be used. UNORDERED_P is true when fucom should be used. */
16067 {
16073 {
16076 }
16077 else
16078 {
16081 }
16084 {
16088 else
16090 else
16093 else
16095 }
16102 {
16104 {
16107 }
16108 else
16110 }
16113 && stack_top_dies
16116 {
16117 /* If both the top of the 387 stack dies, and the other operand
16118 is also a stack register that dies, then this must be a
16119 `fcompp' float compare */
16122 {
16123 /* There is no double popping fcomi variant. Fortunately,
16124 eflags is immune from the fstp's cc clobbering. */
16127 else
16130 }
16131 else
16132 {
16135 else
16137 }
16138 }
16139 else
16140 {
16141 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16144 {
16152 NULL,
16153 NULL,
16160 NULL,
16161 NULL,
16162 NULL,
16163 NULL
16164 };
16179 }
16180 }
16182 void
16184 {
16187 #ifdef ASM_QUAD
16190 #else
16192 #endif
16195 }
16197 void
16199 {
16202 #ifdef ASM_QUAD
16205 #else
16207 #endif
16208 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16214 #if TARGET_MACHO
16216 {
16220 }
16221 #endif
16222 else
16225 }
16226 \f
16227 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16228 for the target. */
16230 void
16232 {
16233 rtx tmp;
16235 /* We play register width games, which are only valid after reload. */
16238 /* Avoid HImode and its attendant prefix byte. */
16243 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16245 {
16248 }
16251 }
16253 /* X is an unchanging MEM. If it is a constant pool reference, return
16254 the constant pool rtx, else NULL. */
16256 rtx
16258 {
16265 }
16267 void
16269 {
16277 {
16278 rtx tmp;
16282 {
16288 }
16291 }
16295 {
16298 rtx tmp;
16303 else
16307 {
16314 }
16315 }
16319 {
16321 {
16322 #if TARGET_MACHO
16323 /* dynamic-no-pic */
16325 {
16326 rtx temp = ((reload_in_progress
16334 }
16336 {
16340 }
16343 else
16344 {
16352 }
16353 /* dynamic-no-pic */
16354 #endif
16355 }
16356 else
16357 {
16361 {
16367 }
16368 }
16369 }
16370 else
16371 {
16382 /* Force large constants in 64bit compilation into register
16383 to get them CSEed. */
16395 {
16396 /* If we are loading a floating point constant to a register,
16397 force the value to memory now, since we'll get better code
16398 out the back end. */
16402 {
16407 }
16408 }
16409 }
16412 }
16414 void
16416 {
16420 /* Force constants other than zero into memory. We do not know how
16421 the instructions used to build constants modify the upper 64 bits
16422 of the register, once we have that information we may be able
16423 to handle some of them more efficiently. */
16432 /* We need to check memory alignment for SSE mode since attribute
16433 can make operands unaligned. */
16438 {
16441 /* ix86_expand_vector_move_misalign() does not like constants ... */
16447 /* ... nor both arguments in memory. */
16455 }
16457 /* Make operand1 a register if it isn't already. */
16461 {
16464 }
16467 }
16469 /* Split 32-byte AVX unaligned load and store if needed. */
16471 static void
16473 {
16474 rtx m;
16481 {
16502 }
16505 {
16507 {
16514 }
16515 else
16517 }
16519 {
16521 {
16526 }
16527 else
16529 }
16530 else
16532 }
16534 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16535 straight to ix86_expand_vector_move. */
16536 /* Code generation for scalar reg-reg moves of single and double precision data:
16537 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16538 movaps reg, reg
16539 else
16540 movss reg, reg
16541 if (x86_sse_partial_reg_dependency == true)
16542 movapd reg, reg
16543 else
16544 movsd reg, reg
16546 Code generation for scalar loads of double precision data:
16547 if (x86_sse_split_regs == true)
16548 movlpd mem, reg (gas syntax)
16549 else
16550 movsd mem, reg
16552 Code generation for unaligned packed loads of single precision data
16553 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16554 if (x86_sse_unaligned_move_optimal)
16555 movups mem, reg
16557 if (x86_sse_partial_reg_dependency == true)
16558 {
16559 xorps reg, reg
16560 movlps mem, reg
16561 movhps mem+8, reg
16562 }
16563 else
16564 {
16565 movlps mem, reg
16566 movhps mem+8, reg
16567 }
16569 Code generation for unaligned packed loads of double precision data
16570 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16571 if (x86_sse_unaligned_move_optimal)
16572 movupd mem, reg
16574 if (x86_sse_split_regs == true)
16575 {
16576 movlpd mem, reg
16577 movhpd mem+8, reg
16578 }
16579 else
16580 {
16581 movsd mem, reg
16582 movhpd mem+8, reg
16583 }
16584 */
16586 void
16588 {
16597 {
16599 {
16604 /* FALLTHRU */
16608 {
16623 }
16629 else
16635 }
16638 }
16642 {
16644 {
16649 /* FALLTHRU */
16657 }
16660 }
16663 {
16664 /* ??? If we have typed data, then it would appear that using
16665 movdqu is the only way to get unaligned data loaded with
16666 integer type. */
16668 {
16671 /* We will eventually emit movups based on insn attributes. */
16673 }
16675 {
16676 rtx zero;
16679 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16680 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16682 {
16683 /* We will eventually emit movups based on insn attributes. */
16686 }
16688 /* When SSE registers are split into halves, we can avoid
16689 writing to the top half twice. */
16691 {
16694 }
16695 else
16696 {
16697 /* ??? Not sure about the best option for the Intel chips.
16698 The following would seem to satisfy; the register is
16699 entirely cleared, breaking the dependency chain. We
16700 then store to the upper half, with a dependency depth
16701 of one. A rumor has it that Intel recommends two movsd
16702 followed by an unpacklpd, but this is unconfirmed. And
16703 given that the dependency depth of the unpacklpd would
16704 still be one, I'm not sure why this would be better. */
16706 }
16712 }
16713 else
16714 {
16716 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16717 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16719 {
16724 }
16728 else
16738 }
16739 }
16741 {
16743 {
16746 /* We will eventually emit movups based on insn attributes. */
16748 }
16750 {
16752 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16753 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16755 /* We will eventually emit movups based on insn attributes. */
16757 else
16758 {
16763 }
16764 }
16765 else
16766 {
16771 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16772 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16774 {
16777 }
16778 else
16779 {
16784 }
16785 }
16786 }
16787 else
16789 }
16791 /* Expand a push in MODE. This is some mode for which we do not support
16792 proper push instructions, at least from the registers that we expect
16793 the value to live in. */
16795 void
16797 {
16798 rtx tmp;
16808 /* When we push an operand onto stack, it has to be aligned at least
16809 at the function argument boundary. However since we don't have
16810 the argument type, we can't determine the actual argument
16811 boundary. */
16813 }
16815 /* Helper function of ix86_fixup_binary_operands to canonicalize
16816 operand order. Returns true if the operands should be swapped. */
16818 static bool
16820 rtx operands[])
16821 {
16826 /* If the operation is not commutative, we can't do anything. */
16830 /* Highest priority is that src1 should match dst. */
16836 /* Next highest priority is that immediate constants come second. */
16842 /* Lowest priority is that memory references should come second. */
16849 }
16852 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16853 destination to use for the operation. If different from the true
16854 destination in operands[0], a copy operation will be required. */
16856 rtx
16858 rtx operands[])
16859 {
16864 /* Canonicalize operand order. */
16866 {
16867 rtx temp;
16869 /* It is invalid to swap operands of different modes. */
16875 }
16877 /* Both source operands cannot be in memory. */
16879 {
16880 /* Optimization: Only read from memory once. */
16882 {
16885 }
16888 else
16890 }
16892 /* If the destination is memory, and we do not have matching source
16893 operands, do things in registers. */
16897 /* Source 1 cannot be a constant. */
16901 /* Source 1 cannot be a non-matching memory. */
16905 /* Improve address combine. */
16914 }
16916 /* Similarly, but assume that the destination has already been
16917 set up properly. */
16919 void
16922 {
16925 }
16927 /* Attempt to expand a binary operator. Make the expansion closer to the
16928 actual machine, then just general_operand, which will allow 3 separate
16929 memory references (one output, two input) in a single insn. */
16931 void
16933 rtx operands[])
16934 {
16941 /* Emit the instruction. */
16945 {
16946 /* Reload doesn't know about the flags register, and doesn't know that
16947 it doesn't want to clobber it. We can only do this with PLUS. */
16950 }
16954 {
16955 /* This is going to be an LEA; avoid splitting it later. */
16957 }
16958 else
16959 {
16962 }
16964 /* Fix up the destination if needed. */
16967 }
16969 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16970 the given OPERANDS. */
16972 void
16974 rtx operands[])
16975 {
16978 {
16981 }
16983 {
16986 }
16987 /* Optimize (__m128i) d | (__m128i) e and similar code
16988 when d and e are float vectors into float vector logical
16989 insn. In C/C++ without using intrinsics there is no other way
16990 to express vector logical operation on float vectors than
16991 to cast them temporarily to integer vectors. */
16993 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17002 {
17003 rtx dst;
17005 {
17012 {
17015 }
17016 else
17017 {
17022 }
17033 }
17034 }
17043 }
17045 /* Return TRUE or FALSE depending on whether the binary operator meets the
17046 appropriate constraints. */
17048 bool
17051 {
17056 /* Both source operands cannot be in memory. */
17060 /* Canonicalize operand order for commutative operators. */
17062 {
17066 }
17068 /* If the destination is memory, we must have a matching source operand. */
17072 /* Source 1 cannot be a constant. */
17076 /* Source 1 cannot be a non-matching memory. */
17078 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17086 }
17088 /* Attempt to expand a unary operator. Make the expansion closer to the
17089 actual machine, then just general_operand, which will allow 2 separate
17090 memory references (one output, one input) in a single insn. */
17092 void
17094 rtx operands[])
17095 {
17102 /* If the destination is memory, and we do not have matching source
17103 operands, do things in registers. */
17106 {
17109 else
17111 }
17113 /* When source operand is memory, destination must match. */
17117 /* Emit the instruction. */
17121 {
17122 /* Reload doesn't know about the flags register, and doesn't know that
17123 it doesn't want to clobber it. */
17126 }
17127 else
17128 {
17131 }
17133 /* Fix up the destination if needed. */
17136 }
17138 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17139 divisor are within the range [0-255]. */
17141 void
17144 {
17153 {
17166 }
17173 /* Use 8bit unsigned divimod if dividend and divisor are within
17174 the range [0-255]. */
17183 pc_rtx);
17188 /* Generate original signed/unsigned divimod. */
17193 /* Branch to the end. */
17197 /* Generate 8bit unsigned divide. */
17199 /* Don't use operands[0] for result of 8bit divide since not all
17200 registers support QImode ZERO_EXTRACT. */
17207 {
17210 }
17211 else
17212 {
17215 }
17217 /* Extract remainder from AH. */
17221 else
17222 {
17223 /* Need a new scratch register since the old one has result
17224 of 8bit divide. */
17228 }
17231 /* Zero extend quotient from AL. */
17237 }
17239 #define LEA_MAX_STALL (3)
17240 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17242 /* Increase given DISTANCE in half-cycles according to
17243 dependencies between PREV and NEXT instructions.
17244 Add 1 half-cycle if there is no dependency and
17245 go to next cycle if there is some dependecy. */
17247 static unsigned int
17249 {
17266 }
17268 /* Function checks if instruction INSN defines register number
17269 REGNO1 or REGNO2. */
17271 static bool
17273 rtx insn)
17274 {
17282 {
17284 }
17287 }
17289 /* Function checks if instruction INSN uses register number
17290 REGNO as a part of address expression. */
17292 static bool
17294 {
17302 }
17304 /* Search backward for non-agu definition of register number REGNO1
17305 or register number REGNO2 in basic block starting from instruction
17306 START up to head of basic block or instruction INSN.
17308 Function puts true value into *FOUND var if definition was found
17309 and false otherwise.
17311 Distance in half-cycles between START and found instruction or head
17312 of BB is added to DISTANCE and returned. */
17314 static int
17318 {
17328 {
17330 {
17333 {
17336 {
17339 }
17340 }
17343 }
17348 }
17351 }
17353 /* Search backward for non-agu definition of register number REGNO1
17354 or register number REGNO2 in INSN's basic block until
17355 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17356 2. Reach neighbour BBs boundary, or
17357 3. Reach agu definition.
17358 Returns the distance between the non-agu definition point and INSN.
17359 If no definition point, returns -1. */
17361 static int
17363 rtx insn)
17364 {
17375 {
17376 edge e;
17377 edge_iterator ei;
17382 {
17385 }
17391 else
17392 {
17397 {
17398 int bb_dist
17404 {
17411 }
17412 }
17415 }
17416 }
17418 /* get_attr_type may modify recog data. We want to make sure
17419 that recog data is valid for instruction INSN, on which
17420 distance_non_agu_define is called. INSN is unchanged here. */
17427 }
17429 /* Return the distance in half-cycles between INSN and the next
17430 insn that uses register number REGNO in memory address added
17431 to DISTANCE. Return -1 if REGNO0 is set.
17433 Put true value into *FOUND if register usage was found and
17434 false otherwise.
17435 Put true value into *REDEFINED if register redefinition was
17436 found and false otherwise. */
17438 static int
17442 {
17451 {
17454 /* If insn and start belong to the same bb, set prev to insn,
17455 so the call to increase_distance will increase the distance
17456 between insns by 1. */
17458 }
17463 {
17465 {
17468 {
17469 /* Return DISTANCE if OP0 is used in memory
17470 address in NEXT. */
17473 }
17476 {
17477 /* Return -1 if OP0 is set in NEXT. */
17480 }
17483 }
17489 }
17492 }
17494 /* Return the distance between INSN and the next insn that uses
17495 register number REGNO0 in memory address. Return -1 if no such
17496 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17498 static int
17500 {
17512 {
17513 edge e;
17514 edge_iterator ei;
17519 {
17522 }
17528 else
17529 {
17535 {
17536 int bb_dist
17541 {
17548 }
17549 }
17552 }
17553 }
17559 }
17561 /* Define this macro to tune LEA priority vs ADD, it take effect when
17562 there is a dilemma of choicing LEA or ADD
17563 Negative value: ADD is more preferred than LEA
17564 Zero: Netrual
17565 Positive value: LEA is more preferred than ADD*/
17566 #define IX86_LEA_PRIORITY 0
17568 /* Return true if usage of lea INSN has performance advantage
17569 over a sequence of instructions. Instructions sequence has
17570 SPLIT_COST cycles higher latency than lea latency. */
17572 static bool
17575 {
17578 /* For Silvermont if using a 2-source or 3-source LEA for
17579 non-destructive destination purposes, or due to wanting
17580 ability to use SCALE, the use of LEA is justified. */
17582 {
17590 }
17596 {
17597 /* If there is no non AGU operand definition, no AGU
17598 operand usage and split cost is 0 then both lea
17599 and non lea variants have same priority. Currently
17600 we prefer lea for 64 bit code and non lea on 32 bit
17601 code. */
17604 else
17606 }
17608 /* With longer definitions distance lea is more preferable.
17609 Here we change it to take into account splitting cost and
17610 lea priority. */
17613 /* If there is no use in memory addess then we just check
17614 that split cost exceeds AGU stall. */
17618 /* If this insn has both backward non-agu dependence and forward
17619 agu dependence, the one with short distance takes effect. */
17621 }
17623 /* Return true if it is legal to clobber flags by INSN and
17624 false otherwise. */
17626 static bool
17628 {
17631 bitmap live;
17634 {
17636 {
17643 }
17649 }
17653 }
17655 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17656 move and add to avoid AGU stalls. */
17658 bool
17660 {
17663 /* Check if we need to optimize. */
17667 /* Check it is correct to split here. */
17675 /* We need to split only adds with non destructive
17676 destination operand. */
17679 else
17681 }
17683 /* Return true if we should emit lea instruction instead of mov
17684 instruction. */
17686 bool
17688 {
17691 /* Check if we need to optimize. */
17695 /* Use lea for reg to reg moves only. */
17703 }
17705 /* Return true if we need to split lea into a sequence of
17706 instructions to avoid AGU stalls. */
17708 bool
17710 {
17716 /* Check we need to optimize. */
17720 /* Check it is correct to split here. */
17727 /* There should be at least two components in the address. */
17732 /* We should not split into add if non legitimate pic
17733 operand is used as displacement. */
17748 /* Compute how many cycles we will add to execution time
17749 if split lea into a sequence of instructions. */
17751 {
17752 /* Have to use mov instruction if non desctructive
17753 destination form is used. */
17757 /* Have to add index to base if both exist. */
17761 /* Have to use shift and adds if scale is 2 or greater. */
17763 {
17768 else
17770 }
17772 /* Have to use add instruction with immediate if
17773 disp is non zero. */
17777 /* Subtract the price of lea. */
17779 }
17783 }
17785 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17786 matches destination. RTX includes clobber of FLAGS_REG. */
17788 static void
17791 {
17798 }
17800 /* Return true if regno1 def is nearest to the insn. */
17802 static bool
17804 {
17811 {
17813 {
17816 }
17822 }
17824 /* None of the regs is defined in the bb. */
17826 }
17828 /* Split lea instructions into a sequence of instructions
17829 which are executed on ALU to avoid AGU stalls.
17830 It is assumed that it is allowed to clobber flags register
17831 at lea position. */
17833 void
17835 {
17851 {
17854 }
17857 {
17860 }
17866 {
17867 /* Case r1 = r1 + ... */
17869 {
17870 /* If we have a case r1 = r1 + C * r1 then we
17871 should use multiplication which is very
17872 expensive. Assume cost model is wrong if we
17873 have such case here. */
17878 }
17879 else
17880 {
17881 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17885 /* Use shift for scaling. */
17894 }
17895 }
17897 {
17900 }
17901 else
17902 {
17904 {
17907 }
17909 {
17912 }
17913 else
17914 {
17919 else
17920 {
17921 rtx tmp1;
17923 /* Find better operand for SET instruction, depending
17924 on which definition is farther from the insn. */
17927 else
17937 }
17940 }
17944 }
17945 }
17947 /* Return true if it is ok to optimize an ADD operation to LEA
17948 operation to avoid flag register consumation. For most processors,
17949 ADD is faster than LEA. For the processors like ATOM, if the
17950 destination register of LEA holds an actual address which will be
17951 used soon, LEA is better and otherwise ADD is better. */
17953 bool
17955 {
17960 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17968 }
17970 /* Return true if destination reg of SET_BODY is shift count of
17971 USE_BODY. */
17973 static bool
17975 {
17976 rtx set_dest;
17977 rtx shift_rtx;
17980 /* Retrieve destination of SET_BODY. */
17982 {
17991 use_body))
17996 }
17998 /* Retrieve shift count of USE_BODY. */
18000 {
18012 }
18020 {
18023 /* Return true if shift count is dest of SET_BODY. */
18025 {
18026 /* Add check since it can be invoked before register
18027 allocation in pre-reload schedule. */
18033 }
18034 }
18037 }
18039 /* Return true if destination reg of SET_INSN is shift count of
18040 USE_INSN. */
18042 bool
18044 {
18047 }
18049 /* Return TRUE or FALSE depending on whether the unary operator meets the
18050 appropriate constraints. */
18052 bool
18056 {
18057 /* If one of operands is memory, source and destination must match. */
18063 }
18065 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18066 are ok, keeping in mind the possible movddup alternative. */
18068 bool
18070 {
18076 }
18078 /* Post-reload splitter for converting an SF or DFmode value in an
18079 SSE register into an unsigned SImode. */
18081 void
18083 {
18094 /* Load up the value into the low element. We must ensure that the other
18095 elements are valid floats -- zero is the easiest such value. */
18097 {
18100 else
18102 }
18103 else
18104 {
18109 else
18111 }
18131 else
18136 }
18138 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18139 Expects the 64-bit DImode to be supplied in a pair of integral
18140 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18141 -mfpmath=sse, !optimize_size only. */
18143 void
18145 {
18149 rtx x;
18155 {
18158 }
18159 else
18160 {
18164 }
18172 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18175 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18176 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18177 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18178 (0x1.0p84 + double(fp_value_hi_xmm)).
18179 Note these exponents differ by 32. */
18183 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18184 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18193 /* Add the upper and lower DFmode values together. */
18196 else
18197 {
18201 }
18204 }
18206 /* Not used, but eases macroization of patterns. */
18207 void
18209 rtx input ATTRIBUTE_UNUSED)
18210 {
18212 }
18214 /* Convert an unsigned SImode value into a DFmode. Only currently used
18215 for SSE, but applicable anywhere. */
18217 void
18219 {
18220 REAL_VALUE_TYPE TWO31r;
18235 }
18237 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18238 32-bit mode; otherwise we have a direct convert instruction. */
18240 void
18242 {
18243 REAL_VALUE_TYPE TWO32r;
18261 }
18263 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18264 For x86_32, -mfpmath=sse, !optimize_size only. */
18265 void
18267 {
18268 REAL_VALUE_TYPE ONE16r;
18287 }
18289 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18290 a vector of unsigned ints VAL to vector of floats TARGET. */
18292 void
18294 {
18296 REAL_VALUE_TYPE TWO16r;
18303 else
18308 OPTAB_DIRECT);
18319 OPTAB_DIRECT);
18321 OPTAB_DIRECT);
18324 }
18326 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18327 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18328 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18329 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18331 rtx
18333 {
18334 REAL_VALUE_TYPE TWO31r;
18349 {
18355 }
18364 OPTAB_DIRECT);
18365 else
18366 {
18372 OPTAB_DIRECT);
18373 }
18376 }
18378 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18379 then replicate the value for all elements of the vector
18380 register. */
18382 rtx
18384 {
18386 rtvec v;
18390 {
18417 }
18418 }
18420 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18421 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18422 for an SSE register. If VECT is true, then replicate the mask for
18423 all elements of the vector register. If INVERT is true, then create
18424 a mask excluding the sign bit. */
18426 rtx
18428 {
18432 rtx v;
18433 rtx mask;
18435 /* Find the sign bit, sign extended to 2*HWI. */
18437 {
18457 else
18465 {
18468 }
18469 else
18470 {
18471 rtvec vec;
18477 {
18480 }
18481 else
18491 }
18496 }
18501 /* Force this value into the low part of a fp vector constant. */
18510 }
18512 /* Generate code for floating point ABS or NEG. */
18514 void
18516 rtx operands[])
18517 {
18528 {
18534 }
18536 /* NEG and ABS performed with SSE use bitwise mask operations.
18537 Create the appropriate mask now. */
18540 else
18550 {
18552 rtvec par;
18557 else
18558 {
18561 }
18563 }
18564 else
18566 }
18568 /* Expand a copysign operation. Special case operand 0 being a constant. */
18570 void
18572 {
18586 else
18590 {
18597 {
18600 else
18601 {
18605 }
18606 }
18616 else
18620 }
18621 else
18622 {
18632 else
18636 }
18637 }
18639 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18640 be a constant, and so has already been expanded into a vector constant. */
18642 void
18644 {
18660 {
18663 }
18664 }
18666 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18667 so we have to do two masks. */
18669 void
18671 {
18686 {
18687 /* Shouldn't happen often (it's useless, obviously), but when it does
18688 we'd generate incorrect code if we continue below. */
18691 }
18694 {
18705 }
18706 else
18707 {
18709 {
18711 }
18713 {
18717 }
18721 {
18724 }
18726 {
18731 }
18733 }
18737 }
18739 /* Return TRUE or FALSE depending on whether the first SET in INSN
18740 has source and destination with matching CC modes, and that the
18741 CC mode is at least as constrained as REQ_MODE. */
18743 bool
18745 {
18746 rtx set;
18757 {
18767 /* FALLTHRU */
18771 /* FALLTHRU */
18775 /* FALLTHRU */
18789 }
18792 }
18794 /* Generate insn patterns to do an integer compare of OPERANDS. */
18796 static rtx
18798 {
18805 /* This is very simple, but making the interface the same as in the
18806 FP case makes the rest of the code easier. */
18810 /* Return the test that should be put into the flags user, i.e.
18811 the bcc, scc, or cmov instruction. */
18813 }
18815 /* Figure out whether to use ordered or unordered fp comparisons.
18816 Return the appropriate mode to use. */
18818 enum machine_mode
18820 {
18821 /* ??? In order to make all comparisons reversible, we do all comparisons
18822 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18823 all forms trapping and nontrapping comparisons, we can make inequality
18824 comparisons trapping again, since it results in better code when using
18825 FCOM based compares. */
18827 }
18829 enum machine_mode
18831 {
18835 {
18838 }
18841 {
18842 /* Only zero flag is needed. */
18846 /* Codes needing carry flag. */
18849 /* Detect overflow checks. They need just the carry flag. */
18853 else
18857 /* Detect overflow checks. They need just the carry flag. */
18861 else
18863 /* Codes possibly doable only with sign flag when
18864 comparing against zero. */
18869 else
18870 /* For other cases Carry flag is not required. */
18872 /* Codes doable only with sign flag when comparing
18873 against zero, but we miss jump instruction for it
18874 so we need to use relational tests against overflow
18875 that thus needs to be zero. */
18880 else
18882 /* strcmp pattern do (use flags) and combine may ask us for proper
18883 mode. */
18888 }
18889 }
18891 /* Return the fixed registers used for condition codes. */
18893 static bool
18895 {
18899 }
18901 /* If two condition code modes are compatible, return a condition code
18902 mode which is compatible with both. Otherwise, return
18903 VOIDmode. */
18905 static enum machine_mode
18907 {
18924 {
18938 {
18952 }
18956 /* These are only compatible with themselves, which we already
18957 checked above. */
18959 }
18960 }
18963 /* Return a comparison we can do and that it is equivalent to
18964 swap_condition (code) apart possibly from orderedness.
18965 But, never change orderedness if TARGET_IEEE_FP, returning
18966 UNKNOWN in that case if necessary. */
18968 static enum rtx_code
18970 {
18972 {
18983 }
18984 }
18986 /* Return cost of comparison CODE using the best strategy for performance.
18987 All following functions do use number of instructions as a cost metrics.
18988 In future this should be tweaked to compute bytes for optimize_size and
18989 take into account performance of various instructions on various CPUs. */
18991 static int
18993 {
18996 /* The cost of code using bit-twiddling on %ah. */
18998 {
19021 }
19024 {
19031 }
19032 }
19034 /* Return strategy to use for floating-point. We assume that fcomi is always
19035 preferrable where available, since that is also true when looking at size
19036 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19038 enum ix86_fpcmp_strategy
19040 {
19041 /* Do fcomi/sahf based test when profitable. */
19050 }
19052 /* Swap, force into registers, or otherwise massage the two operands
19053 to a fp comparison. The operands are updated in place; the new
19054 comparison code is returned. */
19056 static enum rtx_code
19058 {
19064 /* All of the unordered compare instructions only work on registers.
19065 The same is true of the fcomi compare instructions. The XFmode
19066 compare instructions require registers except when comparing
19067 against zero or when converting operand 1 from fixed point to
19068 floating point. */
19077 {
19080 }
19081 else
19082 {
19083 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19084 things around if they appear profitable, otherwise force op0
19085 into a register. */
19091 {
19094 {
19095 rtx tmp;
19098 }
19099 }
19105 {
19110 {
19113 }
19114 else
19116 }
19117 }
19119 /* Try to rearrange the comparison to make it cheaper. */
19123 {
19124 rtx tmp;
19129 }
19134 }
19136 /* Convert comparison codes we use to represent FP comparison to integer
19137 code that will result in proper branch. Return UNKNOWN if no such code
19138 is available. */
19140 enum rtx_code
19142 {
19144 {
19167 }
19168 }
19170 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19172 static rtx
19174 {
19181 /* Do fcomi/sahf based test when profitable. */
19183 {
19188 tmp);
19196 tmp);
19205 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19212 /* In the unordered case, we have to check C2 for NaN's, which
19213 doesn't happen to work out to anything nice combination-wise.
19214 So do some bit twiddling on the value we've got in AH to come
19215 up with an appropriate set of condition codes. */
19219 {
19223 {
19226 }
19227 else
19228 {
19234 }
19239 {
19244 }
19245 else
19246 {
19249 }
19254 {
19257 }
19258 else
19259 {
19263 }
19268 {
19274 }
19275 else
19276 {
19279 }
19284 {
19289 }
19290 else
19291 {
19294 }
19299 {
19304 }
19305 else
19306 {
19309 }
19323 }
19328 }
19330 /* Return the test that should be put into the flags user, i.e.
19331 the bcc, scc, or cmov instruction. */
19334 const0_rtx);
19335 }
19337 static rtx
19339 {
19340 rtx ret;
19346 {
19349 }
19350 else
19354 }
19356 void
19358 {
19360 rtx tmp;
19363 {
19370 simple:
19374 pc_rtx);
19382 /* Expand DImode branch into multiple compare+branch. */
19383 {
19389 {
19392 }
19399 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19400 avoid two branches. This costs one extra insn, so disable when
19401 optimizing for size. */
19406 {
19424 }
19426 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19427 op1 is a constant and the low word is zero, then we can just
19428 examine the high word. Similarly for low word -1 and
19429 less-or-equal-than or greater-than. */
19433 {
19436 {
19439 }
19443 {
19446 }
19450 }
19452 /* Otherwise, we need two or three jumps. */
19461 {
19475 }
19477 /*
19478 * a < b =>
19479 * if (hi(a) < hi(b)) goto true;
19480 * if (hi(a) > hi(b)) goto false;
19481 * if (lo(a) < lo(b)) goto true;
19482 * false:
19483 */
19495 }
19500 }
19501 }
19503 /* Split branch based on floating point condition. */
19504 void
19507 {
19508 rtx condition;
19509 rtx i;
19512 {
19517 }
19520 tmp);
19522 /* Remove pushed operand from stack. */
19532 }
19534 void
19536 {
19537 rtx ret;
19544 }
19546 /* Expand comparison setting or clearing carry flag. Return true when
19547 successful and set pop for the operation. */
19548 static bool
19550 {
19554 /* Do not handle double-mode compares that go through special path. */
19559 {
19564 /* Shortcut: following common codes never translate
19565 into carry flag compares. */
19570 /* These comparisons require zero flag; swap operands so they won't. */
19573 {
19578 }
19580 /* Try to expand the comparison and verify that we end up with
19581 carry flag based comparison. This fails to be true only when
19582 we decide to expand comparison using arithmetic that is not
19583 too common scenario. */
19592 else
19601 }
19607 {
19612 /* Convert a==0 into (unsigned)a<1. */
19621 /* Convert a>b into b<a or a>=b-1. */
19625 {
19627 /* Bail out on overflow. We still can swap operands but that
19628 would force loading of the constant into register. */
19633 }
19634 else
19635 {
19640 }
19643 /* Convert a>=0 into (unsigned)a<0x80000000. */
19661 }
19662 /* Swapping operands may cause constant to appear as first operand. */
19664 {
19668 }
19672 }
19674 bool
19676 {
19700 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19701 HImode insns, we'd be swallowed in word prefix ops. */
19707 {
19711 HOST_WIDE_INT diff;
19714 /* Sign bit compares are better done using shifts than we do by using
19715 sbb. */
19718 {
19719 /* Detect overlap between destination and compare sources. */
19723 {
19724 rtx flags;
19733 {
19735 compare_code
19737 }
19739 /* To simplify rest of code, restrict to the GEU case. */
19741 {
19747 }
19748 else
19749 {
19752 reverse_condition_maybe_unordered
19754 else
19757 }
19766 else
19769 }
19770 else
19771 {
19774 else
19775 {
19780 }
19782 }
19785 {
19786 /*
19787 * cmpl op0,op1
19788 * sbbl dest,dest
19789 * [addl dest, ct]
19790 *
19791 * Size 5 - 8.
19792 */
19797 }
19799 {
19800 /*
19801 * cmpl op0,op1
19802 * sbbl dest,dest
19803 * orl $ct, dest
19804 *
19805 * Size 8.
19806 */
19810 }
19812 {
19813 /*
19814 * cmpl op0,op1
19815 * sbbl dest,dest
19816 * notl dest
19817 * [addl dest, cf]
19818 *
19819 * Size 8 - 11.
19820 */
19826 }
19827 else
19828 {
19829 /*
19830 * cmpl op0,op1
19831 * sbbl dest,dest
19832 * [notl dest]
19833 * andl cf - ct, dest
19834 * [addl dest, ct]
19835 *
19836 * Size 8 - 11.
19837 */
19840 {
19844 }
19854 }
19860 }
19863 {
19866 HOST_WIDE_INT tmp;
19871 {
19874 /* We may be reversing unordered compare to normal compare, that
19875 is not valid in general (we may convert non-trapping condition
19876 to trapping one), however on i386 we currently emit all
19877 comparisons unordered. */
19880 }
19881 else
19882 {
19885 }
19886 }
19891 {
19896 {
19901 }
19902 }
19904 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19908 {
19909 /* If lea code below could be used, only optimize
19910 if it results in a 2 insn sequence. */
19916 {
19917 /*
19918 * notl op1 (if necessary)
19919 * sarl $31, op1
19920 * orl cf, op1
19921 */
19923 {
19927 }
19938 }
19939 }
19947 {
19948 /*
19949 * xorl dest,dest
19950 * cmpl op1,op2
19951 * setcc dest
19952 * lea cf(dest*(ct-cf)),dest
19953 *
19954 * Size 14.
19955 *
19956 * This also catches the degenerate setcc-only case.
19957 */
19959 rtx tmp;
19965 /* On x86_64 the lea instruction operates on Pmode, so we need
19966 to get arithmetics done in proper mode to match. */
19969 else
19970 {
19971 rtx out1;
19974 nops++;
19976 {
19978 nops++;
19979 }
19980 }
19982 {
19984 nops++;
19985 }
19987 {
19990 else
19992 }
19997 }
19999 /*
20000 * General case: Jumpful:
20001 * xorl dest,dest cmpl op1, op2
20002 * cmpl op1, op2 movl ct, dest
20003 * setcc dest jcc 1f
20004 * decl dest movl cf, dest
20005 * andl (cf-ct),dest 1:
20006 * addl ct,dest
20007 *
20008 * Size 20. Size 14.
20009 *
20010 * This is reasonably steep, but branch mispredict costs are
20011 * high on modern cpus, so consider failing only if optimizing
20012 * for space.
20013 */
20018 {
20020 {
20027 {
20030 /* We may be reversing unordered compare to normal compare,
20031 that is not valid in general (we may convert non-trapping
20032 condition to trapping one), however on i386 we currently
20033 emit all comparisons unordered. */
20035 }
20036 else
20037 {
20041 }
20042 }
20045 {
20046 /* notl op1 (if needed)
20047 sarl $31, op1
20048 andl (cf-ct), op1
20049 addl ct, op1
20051 For x < 0 (resp. x <= -1) there will be no notl,
20052 so if possible swap the constants to get rid of the
20053 complement.
20054 True/false will be -1/0 while code below (store flag
20055 followed by decrement) is 0/-1, so the constants need
20056 to be exchanged once more. */
20059 {
20062 }
20063 else
20064 {
20068 }
20071 }
20072 else
20073 {
20077 constm1_rtx,
20079 }
20091 }
20092 }
20095 {
20096 /* Try a few things more with specific constants and a variable. */
20098 optab op;
20104 /* If one of the two operands is an interesting constant, load a
20105 constant with the above and mask it in with a logical operation. */
20108 {
20114 else
20116 }
20118 {
20124 else
20126 }
20127 else
20134 /* Recurse to get the constant loaded. */
20138 /* Mask in the interesting variable. */
20140 OPTAB_WIDEN);
20145 }
20147 /*
20148 * For comparison with above,
20149 *
20150 * movl cf,dest
20151 * movl ct,tmp
20152 * cmpl op1,op2
20153 * cmovcc tmp,dest
20154 *
20155 * Size 15.
20156 */
20178 }
20180 /* Swap, force into registers, or otherwise massage the two operands
20181 to an sse comparison with a mask result. Thus we differ a bit from
20182 ix86_prepare_fp_compare_args which expects to produce a flags result.
20184 The DEST operand exists to help determine whether to commute commutative
20185 operators. The POP0/POP1 operands are updated in place. The new
20186 comparison code is returned, or UNKNOWN if not implementable. */
20188 static enum rtx_code
20191 {
20192 rtx tmp;
20195 {
20198 /* AVX supports all the needed comparisons. */
20201 /* We have no LTGT as an operator. We could implement it with
20202 NE & ORDERED, but this requires an extra temporary. It's
20203 not clear that it's worth it. */
20210 /* These are supported directly. */
20217 /* AVX has 3 operand comparisons, no need to swap anything. */
20220 /* For commutative operators, try to canonicalize the destination
20221 operand to be first in the comparison - this helps reload to
20222 avoid extra moves. */
20225 /* FALLTHRU */
20231 /* These are not supported directly before AVX, and furthermore
20232 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20233 comparison operands to transform into something that is
20234 supported. */
20243 }
20246 }
20248 /* Detect conditional moves that exactly match min/max operational
20249 semantics. Note that this is IEEE safe, as long as we don't
20250 interchange the operands.
20252 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20253 and TRUE if the operation is successful and instructions are emitted. */
20255 static bool
20258 {
20261 rtx tmp;
20264 ;
20266 {
20270 }
20271 else
20278 else
20283 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20284 but MODE may be a vector mode and thus not appropriate. */
20286 {
20288 rtvec v;
20293 }
20294 else
20295 {
20298 }
20302 }
20304 /* Expand an sse vector comparison. Return the register with the result. */
20306 static rtx
20309 {
20312 rtx x;
20325 {
20328 }
20329 else
20333 }
20335 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20336 operations. This is used for both scalar and vector conditional moves. */
20338 static void
20340 {
20346 {
20348 }
20350 {
20354 }
20356 {
20361 }
20363 {
20367 }
20369 {
20377 op_true,
20378 op_false)));
20379 }
20380 else
20381 {
20390 {
20404 {
20410 }
20425 {
20431 }
20435 }
20439 else
20440 {
20446 else
20458 }
20459 }
20460 }
20462 /* Expand a floating-point conditional move. Return true if successful. */
20464 bool
20466 {
20474 {
20477 /* Since we've no cmove for sse registers, don't force bad register
20478 allocation just to gain access to it. Deny movcc when the
20479 comparison mode doesn't match the move mode. */
20498 }
20505 /* The floating point conditional move instructions don't directly
20506 support conditions resulting from a signed integer comparison. */
20510 {
20515 }
20522 }
20524 /* Expand a floating-point vector conditional move; a vcond operation
20525 rather than a movcc operation. */
20527 bool
20529 {
20531 rtx cmp;
20536 {
20537 rtx temp;
20539 {
20556 }
20558 OPTAB_DIRECT);
20561 }
20571 }
20573 /* Expand a signed/unsigned integral vector conditional move. */
20575 bool
20577 {
20587 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20588 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20597 {
20601 {
20607 }
20610 {
20616 }
20617 }
20626 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20630 ;
20631 else
20632 {
20633 /* Canonicalize the comparison to EQ, GT, GTU. */
20635 {
20652 /* FALLTHRU */
20662 }
20664 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20666 {
20668 {
20670 /* SSE4.1 supports EQ. */
20677 /* SSE4.2 supports GT/GTU. */
20684 }
20685 }
20687 /* Unsigned parallel compare is not supported by the hardware.
20688 Play some tricks to turn this into a signed comparison
20689 against 0. */
20691 {
20695 {
20700 {
20705 {
20712 }
20713 /* Subtract (-(INT MAX) - 1) from both operands to make
20714 them signed. */
20725 }
20732 /* Perform a parallel unsigned saturating subtraction. */
20745 }
20746 }
20747 }
20749 /* Allow the comparison to be done in one mode, but the movcc to
20750 happen in another mode. */
20752 {
20755 }
20756 else
20757 {
20763 }
20768 }
20770 /* Expand a variable vector permutation. */
20772 void
20774 {
20785 /* Number of elements in the vector. */
20791 {
20793 {
20794 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20795 an constant shuffle operand. With a tiny bit of effort we can
20796 use VPERMD instead. A re-interpretation stall for V4DFmode is
20797 unfortunate but there's no avoiding it.
20798 Similarly for V16HImode we don't have instructions for variable
20799 shuffling, while for V32QImode we can use after preparing suitable
20800 masks vpshufb; vpshufb; vpermq; vpor. */
20803 {
20807 }
20808 else
20809 {
20813 }
20816 /* Replicate the low bits of the V4DImode mask into V8SImode:
20817 mask = { A B C D }
20818 t1 = { A A B B C C D D }. */
20826 else
20829 /* Multiply the shuffle indicies by two. */
20831 OPTAB_DIRECT);
20833 /* Add one to the odd shuffle indicies:
20834 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20836 {
20839 }
20843 OPTAB_DIRECT);
20845 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20850 }
20853 {
20855 /* The VPERMD and VPERMPS instructions already properly ignore
20856 the high bits of the shuffle elements. No need for us to
20857 perform an AND ourselves. */
20860 else
20861 {
20867 }
20874 else
20875 {
20881 }
20885 /* By combining the two 128-bit input vectors into one 256-bit
20886 input vector, we can use VPERMD and VPERMPS for the full
20887 two-operand shuffle. */
20919 /* From mask create two adjusted masks, which contain the same
20920 bits as mask in the low 7 bits of each vector element.
20921 The first mask will have the most significant bit clear
20922 if it requests element from the same 128-bit lane
20923 and MSB set if it requests element from the other 128-bit lane.
20924 The second mask will have the opposite values of the MSB,
20925 and additionally will have its 128-bit lanes swapped.
20926 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20927 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20928 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20929 stands for other 12 bytes. */
20930 /* The bit whether element is from the same lane or the other
20931 lane is bit 4, so shift it up by 3 to the MSB position. */
20935 /* Clear MSB bits from the mask just in case it had them set. */
20937 /* After this t1 will have MSB set for elements from other lane. */
20939 /* Clear bits other than MSB. */
20941 /* Or in the lower bits from mask into t3. */
20943 /* And invert MSB bits in t1, so MSB is set for elements from the same
20944 lane. */
20946 /* Swap 128-bit lanes in t3. */
20951 /* And or in the lower bits from mask into t1. */
20954 {
20955 /* Each of these shuffles will put 0s in places where
20956 element from the other 128-bit lane is needed, otherwise
20957 will shuffle in the requested value. */
20960 /* For t3 the 128-bit lanes are swapped again. */
20965 /* And oring both together leads to the result. */
20968 }
20971 /* Similarly to the above one_operand_shuffle code,
20972 just for repeated twice for each operand. merge_two:
20973 code will merge the two results together. */
20995 }
20996 }
20999 {
21000 /* The XOP VPPERM insn supports three inputs. By ignoring the
21001 one_operand_shuffle special case, we avoid creating another
21002 set of constant vectors in memory. */
21005 /* mask = mask & {2*w-1, ...} */
21007 }
21008 else
21009 {
21010 /* mask = mask & {w-1, ...} */
21012 }
21020 /* For non-QImode operations, convert the word permutation control
21021 into a byte permutation control. */
21023 {
21028 /* Convert mask to vector of chars. */
21031 /* Replicate each of the input bytes into byte positions:
21032 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21033 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21034 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21041 else
21044 /* Convert it into the byte positions by doing
21045 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21051 }
21053 /* The actual shuffle operations all operate on V16QImode. */
21059 {
21061 }
21063 {
21065 }
21066 else
21067 {
21071 /* Shuffle the two input vectors independently. */
21077 merge_two:
21078 /* Then merge them together. The key is whether any given control
21079 element contained a bit set that indicates the second word. */
21083 {
21084 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21085 more shuffle to convert the V2DI input mask into a V4SI
21086 input mask. At which point the masking that expand_int_vcond
21087 will work as desired. */
21095 }
21112 }
21113 }
21115 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21116 true if we should do zero extension, else sign extension. HIGH_P is
21117 true if we want the N/2 high elements, else the low elements. */
21119 void
21121 {
21123 rtx tmp;
21126 {
21132 {
21136 else
21139 extract
21145 else
21148 extract
21154 else
21157 extract
21163 else
21169 else
21175 else
21180 }
21183 {
21186 }
21188 {
21189 /* Shift higher 8 bytes to lower 8 bytes. */
21194 }
21195 else
21199 }
21200 else
21201 {
21205 {
21209 else
21215 else
21221 else
21226 }
21230 else
21235 }
21236 }
21238 /* Expand conditional increment or decrement using adb/sbb instructions.
21239 The default case using setcc followed by the conditional move can be
21240 done by generic code. */
21241 bool
21243 {
21245 rtx flags;
21247 rtx compare_op;
21265 {
21268 }
21271 {
21275 reverse_condition_maybe_unordered
21277 else
21279 }
21283 /* Construct either adc or sbb insn. */
21285 {
21287 {
21302 }
21303 }
21304 else
21305 {
21307 {
21322 }
21323 }
21327 }
21330 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21331 but works for floating pointer parameters and nonoffsetable memories.
21332 For pushes, it returns just stack offsets; the values will be saved
21333 in the right order. Maximally three parts are generated. */
21335 static int
21337 {
21342 else
21348 /* Optimize constant pool reference to immediates. This is used by fp
21349 moves, that force all constants to memory to allow combining. */
21351 {
21355 }
21358 {
21359 /* The only non-offsetable memories we handle are pushes. */
21368 }
21371 {
21373 /* Caution: if we looked through a constant pool memory above,
21374 the operand may actually have a different mode now. That's
21375 ok, since we want to pun this all the way back to an integer. */
21379 }
21382 {
21385 else
21386 {
21390 {
21394 }
21396 {
21401 }
21403 {
21404 REAL_VALUE_TYPE r;
21409 {
21416 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21417 long double may not be 80-bit. */
21426 }
21429 }
21430 else
21432 }
21433 }
21434 else
21435 {
21439 {
21442 {
21446 }
21448 {
21452 }
21454 {
21455 REAL_VALUE_TYPE r;
21461 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21464 = gen_int_mode
21467 DImode);
21468 else
21475 = gen_int_mode
21478 DImode);
21479 else
21481 }
21482 else
21484 }
21485 }
21488 }
21490 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21491 Return false when normal moves are needed; true when all required
21492 insns have been emitted. Operands 2-4 contain the input values
21493 int the correct order; operands 5-7 contain the output values. */
21495 void
21497 {
21505 /* The DFmode expanders may ask us to move double.
21506 For 64bit target this is single move. By hiding the fact
21507 here we simplify i386.md splitters. */
21509 {
21510 /* Optimize constant pool reference to immediates. This is used by
21511 fp moves, that force all constants to memory to allow combining. */
21518 {
21521 }
21522 else
21527 }
21529 /* The only non-offsettable memory we handle is push. */
21532 else
21539 /* When emitting push, take care for source operands on the stack. */
21542 {
21545 /* Compensate for the stack decrement by 4. */
21550 /* src_base refers to the stack pointer and is
21551 automatically decreased by emitted push. */
21555 }
21557 /* We need to do copy in the right order in case an address register
21558 of the source overlaps the destination. */
21560 {
21561 rtx tmp;
21564 {
21568 collisions++;
21569 }
21571 /* Collision in the middle part can be handled by reordering. */
21573 {
21576 }
21580 {
21582 {
21585 }
21586 else
21587 {
21590 }
21591 }
21593 /* If there are more collisions, we can't handle it by reordering.
21594 Do an lea to the last part and use only one colliding move. */
21596 {
21597 rtx base;
21603 /* Handle the case when the last part isn't valid for lea.
21604 Happens in 64-bit mode storing the 12-byte XFmode. */
21611 {
21614 }
21615 }
21616 }
21619 {
21621 {
21623 {
21628 }
21630 {
21633 }
21634 }
21635 else
21636 {
21637 /* In 64bit mode we don't have 32bit push available. In case this is
21638 register, it is OK - we will just use larger counterpart. We also
21639 retype memory - these comes from attempt to avoid REX prefix on
21640 moving of second half of TFmode value. */
21642 {
21644 {
21655 }
21659 }
21660 }
21664 }
21666 /* Choose correct order to not overwrite the source before it is copied. */
21676 {
21678 {
21681 }
21682 }
21683 else
21684 {
21686 {
21689 }
21690 }
21692 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21694 {
21703 }
21709 }
21711 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21712 left shift by a constant, either using a single shift or
21713 a sequence of add instructions. */
21715 static void
21717 {
21723 {
21727 }
21728 else
21729 {
21732 }
21733 }
21735 void
21737 {
21746 {
21751 {
21757 }
21758 else
21759 {
21767 }
21769 }
21776 {
21777 /* Assuming we've chosen a QImode capable registers, then 1 << N
21778 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21780 {
21796 }
21798 /* Otherwise, we can get the same results by manually performing
21799 a bit extract operation on bit 5/6, and then performing the two
21800 shifts. The two methods of getting 0/1 into low/high are exactly
21801 the same size. Avoiding the shift in the bit extract case helps
21802 pentium4 a bit; no one else seems to care much either way. */
21803 else
21804 {
21809 HOST_WIDE_INT bits;
21810 rtx x;
21813 {
21819 }
21820 else
21821 {
21827 }
21831 else
21839 }
21844 }
21847 {
21848 /* For -1 << N, we can avoid the shld instruction, because we
21849 know that we're shifting 0...31/63 ones into a -1. */
21853 else
21855 }
21856 else
21857 {
21865 }
21870 {
21876 }
21877 else
21878 {
21883 }
21884 }
21886 void
21888 {
21898 {
21903 {
21909 }
21911 {
21920 }
21921 else
21922 {
21930 }
21931 }
21932 else
21933 {
21945 {
21953 scratch));
21954 }
21955 else
21956 {
21961 }
21962 }
21963 }
21965 void
21967 {
21977 {
21982 {
21989 }
21990 else
21991 {
21999 }
22000 }
22001 else
22002 {
22014 {
22020 scratch));
22021 }
22022 else
22023 {
22028 }
22029 }
22030 }
22032 /* Predict just emitted jump instruction to be taken with probability PROB. */
22033 static void
22035 {
22039 }
22041 /* Helper function for the string operations below. Dest VARIABLE whether
22042 it is aligned to VALUE bytes. If true, jump to the label. */
22043 static rtx
22045 {
22050 else
22056 else
22059 }
22061 /* Adjust COUNTER by the VALUE. */
22062 static void
22064 {
22069 }
22071 /* Zero extend possibly SImode EXP to Pmode register. */
22072 rtx
22074 {
22076 }
22078 /* Divide COUNTREG by SCALE. */
22079 static rtx
22081 {
22082 rtx sc;
22094 }
22096 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22097 DImode for constant loop counts. */
22099 static enum machine_mode
22101 {
22109 }
22111 /* Copy the address to a Pmode register. This is used for x32 to
22112 truncate DImode TLS address to a SImode register. */
22114 static rtx
22116 {
22119 else
22120 {
22123 }
22124 }
22126 /* When SRCPTR is non-NULL, output simple loop to move memory
22127 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
22128 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
22129 equivalent loop to set memory by VALUE (supposed to be in MODE).
22131 The size is rounded down to whole number of chunk size moved at once.
22132 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22135 static void
22140 {
22146 rtx size;
22155 /* Those two should combine. */
22157 {
22161 }
22168 /* This assert could be relaxed - in this case we'll need to compute
22169 smallest power of two, containing in PIECE_SIZE_N and pass it to
22170 offset_address. */
22176 {
22180 /* When unrolling for chips that reorder memory reads and writes,
22181 we can save registers by using single temporary.
22182 Also using 4 temporaries is overkill in 32bit mode. */
22184 {
22186 {
22188 {
22189 destmem =
22191 srcmem =
22193 }
22195 }
22196 }
22197 else
22198 {
22202 {
22205 {
22206 srcmem =
22208 }
22210 }
22212 {
22214 {
22215 destmem =
22217 }
22219 }
22220 }
22221 }
22222 else
22224 {
22226 destmem =
22229 }
22239 {
22245 else
22247 }
22248 else
22256 {
22261 }
22263 }
22265 /* Output "rep; mov" instruction.
22266 Arguments have same meaning as for previous function */
22267 static void
22270 rtx count,
22272 {
22273 rtx destexp;
22274 rtx srcexp;
22275 rtx countreg;
22276 HOST_WIDE_INT rounded_count;
22278 /* If the size is known, it is shorter to use rep movs. */
22289 {
22296 }
22297 else
22298 {
22301 }
22303 {
22310 }
22311 else
22312 {
22317 }
22320 }
22322 /* Output "rep; stos" instruction.
22323 Arguments have same meaning as for previous function */
22324 static void
22327 rtx orig_value)
22328 {
22329 rtx destexp;
22330 rtx countreg;
22331 HOST_WIDE_INT rounded_count;
22338 {
22342 }
22343 else
22346 {
22351 }
22355 }
22357 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22358 DESTMEM.
22359 SRC is passed by pointer to be updated on return.
22360 Return value is updated DST. */
22361 static rtx
22363 HOST_WIDE_INT size_to_move)
22364 {
22370 /* Find the widest mode in which we could perform moves.
22371 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22372 it until move of such size is supported. */
22377 {
22381 }
22383 /* Find the corresponding vector mode with the same size as MOVE_MODE.
22384 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
22386 {
22391 {
22395 }
22396 }
22402 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
22406 {
22407 /* We move from memory to memory, so we'll need to do it via
22408 a temporary register. */
22419 piece_size);
22421 piece_size);
22422 }
22424 /* Update DST and SRC rtx. */
22427 }
22429 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
22430 static void
22433 {
22436 {
22441 /* For now MAX_SIZE should be a power of 2. This assert could be
22442 relaxed, but it'll require a bit more complicated epilogue
22443 expanding. */
22446 {
22449 }
22451 }
22453 {
22459 }
22461 /* When there are stringops, we can cheaply increase dest and src pointers.
22462 Otherwise we save code size by maintaining offset (zero is readily
22463 available from preceding rep operation) and using x86 addressing modes.
22464 */
22466 {
22468 {
22475 }
22477 {
22484 }
22486 {
22493 }
22494 }
22495 else
22496 {
22498 rtx tmp;
22501 {
22512 }
22514 {
22527 }
22529 {
22538 }
22539 }
22540 }
22542 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22543 static void
22546 {
22547 count =
22553 }
22555 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22556 static void
22558 {
22559 rtx dest;
22562 {
22567 {
22569 {
22574 }
22575 else
22578 }
22580 {
22582 {
22585 }
22586 else
22587 {
22592 }
22594 }
22596 {
22600 }
22602 {
22606 }
22608 {
22612 }
22614 }
22616 {
22619 }
22621 {
22624 {
22628 }
22629 else
22630 {
22636 }
22639 }
22641 {
22644 {
22647 }
22648 else
22649 {
22653 }
22656 }
22658 {
22664 }
22666 {
22672 }
22674 {
22680 }
22681 }
22683 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22684 DESIRED_ALIGNMENT.
22685 Return value is updated DESTMEM. */
22686 static rtx
22690 {
22693 {
22695 {
22702 }
22703 }
22705 }
22707 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22708 ALIGN_BYTES is how many bytes need to be copied.
22709 The function updates DST and SRC, namely, it sets proper alignment.
22710 DST is returned via return value, SRC is updated via pointer SRCP. */
22711 static rtx
22714 {
22727 {
22729 {
22732 }
22733 }
22738 {
22741 {
22745 }
22750 }
22757 }
22759 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22760 DESIRED_ALIGNMENT. */
22761 static void
22764 {
22766 {
22773 }
22775 {
22782 }
22784 {
22791 }
22793 }
22795 /* Set enough from DST to align DST known to by aligned by ALIGN to
22796 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22797 static rtx
22800 {
22804 {
22809 }
22811 {
22818 }
22820 {
22827 }
22834 }
22836 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22837 static enum stringop_alg
22840 {
22843 /* Algorithms using the rep prefix want at least edi and ecx;
22844 additionally, memset wants eax and memcpy wants esi. Don't
22845 consider such algorithms if the user has appropriated those
22846 registers for their own purposes. */
22848 || (memset
22852 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22853 || (alg != rep_prefix_1_byte \
22854 && alg != rep_prefix_4_byte \
22855 && alg != rep_prefix_8_byte))
22858 /* Even if the string operation call is cold, we still might spend a lot
22859 of time processing large blocks. */
22864 else
22872 else
22876 /* rep; movq or rep; movl is the smallest variant. */
22878 {
22881 else
22883 }
22884 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22885 */
22889 {
22893 {
22894 /* We get here if the algorithms that were not libcall-based
22895 were rep-prefix based and we are unable to use rep prefixes
22896 based on global register usage. Break out of the loop and
22897 use the heuristic below. */
22901 {
22906 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22907 last non-libcall inline algorithm. */
22909 {
22910 /* When the current size is best to be copied by a libcall,
22911 but we are still forced to inline, run the heuristic below
22912 that will pick code for medium sized blocks. */
22916 }
22918 {
22921 }
22922 }
22923 }
22925 }
22926 /* When asked to inline the call anyway, try to pick meaningful choice.
22927 We look for maximal size of block that is faster to copy by hand and
22928 take blocks of at most of that size guessing that average size will
22929 be roughly half of the block.
22931 If this turns out to be bad, we might simply specify the preferred
22932 choice in ix86_costs. */
22935 {
22942 {
22949 }
22950 /* If there aren't any usable algorithms, then recursing on
22951 smaller sizes isn't going to find anything. Just return the
22952 simple byte-at-a-time copy loop. */
22954 {
22955 /* Pick something reasonable. */
22959 }
22968 }
22970 #undef ALG_USABLE_P
22971 }
22973 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22974 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22975 static int
22980 {
22991 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22992 copying whole cacheline at once. */
23005 }
23007 /* Expand string move (memcpy) operation. Use i386 string operations
23008 when profitable. expand_setmem contains similar code. The code
23009 depends upon architecture, block size and alignment, but always has
23010 the same overall structure:
23012 1) Prologue guard: Conditional that jumps up to epilogues for small
23013 blocks that can be handled by epilogue alone. This is faster
23014 but also needed for correctness, since prologue assume the block
23015 is larger than the desired alignment.
23017 Optional dynamic check for size and libcall for large
23018 blocks is emitted here too, with -minline-stringops-dynamically.
23020 2) Prologue: copy first few bytes in order to get destination
23021 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
23022 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
23023 copied. We emit either a jump tree on power of two sized
23024 blocks, or a byte loop.
23026 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
23027 with specified algorithm.
23029 4) Epilogue: code copying tail of the block that is too small to be
23030 handled by main body (or up to size guarded by prologue guard). */
23032 bool
23035 {
23036 rtx destreg;
23037 rtx srcreg;
23039 rtx tmp;
23055 /* i386 can do misaligned access on reasonably increased cost. */
23059 /* ALIGN is the minimum of destination and source alignment, but we care here
23060 just about destination alignment. */
23069 /* Make sure we don't need to care about overflow later on. */
23073 /* Step 0: Decide on preferred algorithm, desired alignment and
23074 size of chunks to be copied by main loop. */
23088 {
23107 /* Find the widest supported mode. */
23113 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23114 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23116 {
23121 }
23133 }
23141 /* Step 1: Prologue guard. */
23143 /* Alignment code needs count to be in register. */
23145 {
23148 {
23149 align_bytes
23153 else
23155 }
23158 }
23161 /* Ensure that alignment prologue won't copy past end of block. */
23163 {
23165 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
23166 Make sure it is power of 2. */
23170 {
23172 {
23173 /* If main algorithm works on QImode, no epilogue is needed.
23174 For small sizes just don't align anything. */
23177 else
23179 }
23180 }
23181 else
23182 {
23189 else
23191 }
23192 }
23194 /* Emit code to decide on runtime whether library call or inline should be
23195 used. */
23197 {
23199 {
23201 {
23205 }
23206 }
23207 else
23208 {
23217 }
23218 }
23220 /* Step 2: Alignment prologue. */
23223 {
23225 {
23226 /* Except for the first move in epilogue, we no longer know
23227 constant offset in aliasing info. It don't seems to worth
23228 the pain to maintain it for the first move, so throw away
23229 the info early. */
23233 desired_align);
23234 }
23235 else
23236 {
23237 /* If we know how many bytes need to be stored before dst is
23238 sufficiently aligned, maintain aliasing info accurately. */
23244 }
23250 {
23251 /* It is possible that we copied enough so the main loop will not
23252 execute. */
23262 else
23264 }
23265 }
23267 {
23272 }
23276 /* Step 3: Main loop. */
23279 {
23290 expected_size);
23296 move_mode);
23298 }
23299 /* Adjust properly the offset of src and dest memory for aliasing. */
23301 {
23306 }
23307 else
23308 {
23311 }
23313 /* Step 4: Epilogue to copy the remaining bytes. */
23314 epilogue:
23316 {
23317 /* When the main loop is done, COUNT_EXP might hold original count,
23318 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23319 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23320 bytes. Compensate if needed. */
23323 {
23324 tmp =
23327 OPTAB_DIRECT);
23330 }
23333 }
23337 epilogue_size_needed);
23341 }
23343 /* Helper function for memcpy. For QImode value 0xXY produce
23344 0xXYXYXYXY of wide specified by MODE. This is essentially
23345 a * 0x10101010, but we can do slightly better than
23346 synth_mult by unwinding the sequence by hand on CPUs with
23347 slow multiply. */
23348 static rtx
23350 {
23352 rtx tmp;
23359 {
23367 }
23376 nops--;
23381 {
23385 OPTAB_DIRECT);
23386 }
23387 else
23388 {
23394 else
23396 else
23397 {
23400 reg =
23402 }
23412 }
23413 }
23415 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23416 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23417 alignment from ALIGN to DESIRED_ALIGN. */
23418 static rtx
23420 {
23421 rtx promoted_val;
23430 else
23434 }
23436 /* Expand string clear operation (bzero). Use i386 string operations when
23437 profitable. See expand_movmem comment for explanation of individual
23438 steps performed. */
23439 bool
23442 {
23443 rtx destreg;
23445 rtx tmp;
23463 /* i386 can do misaligned access on reasonably increased cost. */
23472 /* Make sure we don't need to care about overflow later on. */
23476 /* Step 0: Decide on preferred algorithm, desired alignment and
23477 size of chunks to be copied by main loop. */
23491 {
23517 }
23525 /* Step 1: Prologue guard. */
23527 /* Alignment code needs count to be in register. */
23529 {
23532 {
23533 align_bytes
23537 else
23539 }
23541 {
23546 }
23547 }
23548 /* Do the cheap promotion to allow better CSE across the
23549 main loop and epilogue (ie one load of the big constant in the
23550 front of all code. */
23554 /* Ensure that alignment prologue won't copy past end of block. */
23556 {
23558 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23559 Make sure it is power of 2. */
23562 /* To improve performance of small blocks, we jump around the VAL
23563 promoting mode. This mean that if the promoted VAL is not constant,
23564 we might not use it in the epilogue and have to use byte
23565 loop variant. */
23569 {
23571 {
23572 /* If main algorithm works on QImode, no epilogue is needed.
23573 For small sizes just don't align anything. */
23576 else
23578 }
23579 }
23580 else
23581 {
23588 else
23590 }
23591 }
23593 {
23602 }
23604 /* Step 2: Alignment prologue. */
23606 /* Do the expensive promotion once we branched off the small blocks. */
23613 {
23615 {
23616 /* Except for the first move in epilogue, we no longer know
23617 constant offset in aliasing info. It don't seems to worth
23618 the pain to maintain it for the first move, so throw away
23619 the info early. */
23622 desired_align);
23623 }
23624 else
23625 {
23626 /* If we know how many bytes need to be stored before dst is
23627 sufficiently aligned, maintain aliasing info accurately. */
23633 }
23639 {
23640 /* It is possible that we copied enough so the main loop will not
23641 execute. */
23651 else
23653 }
23654 }
23656 {
23662 }
23666 /* Step 3: Main loop. */
23669 {
23680 expected_size);
23694 }
23695 /* Adjust properly the offset of src and dest memory for aliasing. */
23699 else
23702 /* Step 4: Epilogue to copy the remaining bytes. */
23705 {
23706 /* When the main loop is done, COUNT_EXP might hold original count,
23707 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23708 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23709 bytes. Compensate if needed. */
23712 {
23713 tmp =
23716 OPTAB_DIRECT);
23719 }
23722 }
23723 epilogue:
23725 {
23728 epilogue_size_needed);
23729 else
23731 epilogue_size_needed);
23732 }
23736 }
23738 /* Expand the appropriate insns for doing strlen if not just doing
23739 repnz; scasb
23741 out = result, initialized with the start address
23742 align_rtx = alignment of the address.
23743 scratch = scratch register, initialized with the startaddress when
23744 not aligned, otherwise undefined
23746 This is just the body. It needs the initializations mentioned above and
23747 some address computing at the end. These things are done in i386.md. */
23749 static void
23751 {
23753 rtx tmp;
23758 rtx mem;
23761 rtx cmp;
23767 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23769 /* Is there a known alignment and is it less than 4? */
23771 {
23774 /* Is there a known alignment and is it not 2? */
23776 {
23780 /* Leave just the 3 lower bits. */
23790 }
23791 else
23792 {
23793 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23794 check if is aligned to 4 - byte. */
23801 }
23805 /* Now compare the bytes. */
23807 /* Compare the first n unaligned byte on a byte per byte basis. */
23811 /* Increment the address. */
23814 /* Not needed with an alignment of 2 */
23816 {
23820 end_0_label);
23825 }
23828 end_0_label);
23831 }
23833 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23834 align this loop. It gives only huge programs, but does not help to
23835 speed up. */
23842 /* This formula yields a nonzero result iff one of the bytes is zero.
23843 This saves three branches inside loop and many cycles. */
23851 align_4_label);
23854 {
23860 /* If zero is not in the first two bytes, move two bytes forward. */
23866 reg,
23867 tmpreg)));
23868 /* Emit lea manually to avoid clobbering of flags. */
23876 reg2,
23877 out)));
23878 }
23879 else
23880 {
23882 /* Is zero in the first two bytes? */
23889 pc_rtx);
23893 /* Not in the first two. Move two bytes forward. */
23899 }
23901 /* Avoid branch in fixing the byte. */
23909 }
23911 /* Expand strlen. */
23913 bool
23915 {
23918 /* The generic case of strlen expander is long. Avoid it's
23919 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23922 && !TARGET_INLINE_ALL_STRINGOPS
23932 {
23933 /* Well it seems that some optimizer does not combine a call like
23934 foo(strlen(bar), strlen(bar));
23935 when the move and the subtraction is done here. It does calculate
23936 the length just once when these instructions are done inside of
23937 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23938 often used and I use one fewer register for the lifetime of
23939 output_strlen_unroll() this is better. */
23945 /* strlensi_unroll_1 returns the address of the zero at the end of
23946 the string, like memchr(), so compute the length by subtracting
23947 the start address. */
23949 }
23950 else
23951 {
23952 rtx unspec;
23954 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23967 /* If .md starts supporting :P, this can be done in .md. */
23973 }
23975 }
23977 /* For given symbol (function) construct code to compute address of it's PLT
23978 entry in large x86-64 PIC model. */
23979 static rtx
23981 {
23994 }
23996 rtx
23998 rtx callarg2,
24000 {
24001 unsigned int const cregs_size
24012 {
24013 #if TARGET_MACHO
24016 #endif
24017 }
24018 else
24019 {
24020 /* Static functions and indirect calls don't need the pic register. */
24022 && (!TARGET_64BIT
24028 }
24031 {
24035 }
24038 && !TARGET_PECOFF
24046 {
24049 }
24057 {
24061 }
24065 {
24069 UNSPEC_MS_TO_SYSV_CALL);
24072 {
24078 }
24079 }
24088 }
24090 /* Output the assembly for a call instruction. */
24094 {
24100 {
24103 /* SEH epilogue detection requires the indirect branch case
24104 to include REX.W. */
24107 else
24112 }
24114 /* SEH unwinding can require an extra nop to be emitted in several
24115 circumstances. Determine if we have one of those. */
24117 {
24118 rtx i;
24121 {
24122 /* If we get to another real insn, we don't need the nop. */
24126 /* If we get to the epilogue note, prevent a catch region from
24127 being adjacent to the standard epilogue sequence. If non-
24128 call-exceptions, we'll have done this during epilogue emission. */
24130 && !flag_non_call_exceptions
24132 {
24135 }
24136 }
24138 /* If we didn't find a real insn following the call, prevent the
24139 unwinder from looking into the next function. */
24142 }
24146 else
24155 }
24156 \f
24157 /* Clear stack slot assignments remembered from previous functions.
24158 This is called from INIT_EXPANDERS once before RTL is emitted for each
24159 function. */
24163 {
24171 }
24173 /* Return a MEM corresponding to a stack slot with mode MODE.
24174 Allocate a new slot if necessary.
24176 The RTL for a function can have several slots available: N is
24177 which slot to use. */
24179 rtx
24181 {
24198 }
24200 static void
24202 {
24208 }
24209 \f
24210 /* Calculate the length of the memory address in the instruction encoding.
24211 Includes addr32 prefix, does not include the one-byte modrm, opcode,
24212 or other prefixes. We never generate addr32 prefix for LEA insn. */
24214 int
24216 {
24233 /* If this is not LEA instruction, add the length of addr32 prefix. */
24238 len++;
24252 /* Rule of thumb:
24253 - esp as the base always wants an index,
24254 - ebp as the base always wants a displacement,
24255 - r12 as the base always wants an index,
24256 - r13 as the base always wants a displacement. */
24258 /* Register Indirect. */
24260 {
24261 /* esp (for its index) and ebp (for its displacement) need
24262 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
24263 code. */
24270 len++;
24271 }
24273 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
24274 is not disp32, but disp32(%rip), so for disp32
24275 SIB byte is needed, unless print_operand_address
24276 optimizes it into disp32(%rip) or (%rip) is implied
24277 by UNSPEC. */
24279 {
24282 {
24298 len++;
24299 }
24300 }
24301 else
24302 {
24303 /* Find the length of the displacement constant. */
24305 {
24308 else
24310 }
24311 /* ebp always wants a displacement. Similarly r13. */
24313 len++;
24315 /* An index requires the two-byte modrm form.... */
24317 /* ...like esp (or r12), which always wants an index. */
24321 len++;
24322 }
24325 }
24327 /* Compute default value for "length_immediate" attribute. When SHORTFORM
24328 is set, expect that insn have 8bit immediate alternative. */
24329 int
24331 {
24337 {
24342 {
24345 {
24357 }
24359 {
24362 }
24363 }
24365 {
24375 /* Immediates for DImode instructions are encoded
24376 as 32bit sign extended values. */
24382 }
24383 }
24385 }
24387 /* Compute default value for "length_address" attribute. */
24388 int
24390 {
24394 {
24405 }
24410 {
24413 {
24418 constraints++;
24421 ;
24422 /* Skip ignored operands. */
24425 }
24427 }
24429 }
24431 /* Compute default value for "length_vex" attribute. It includes
24432 2 or 3 byte VEX prefix and 1 opcode byte. */
24434 int
24436 {
24439 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24440 byte VEX prefix. */
24444 /* We can always use 2 byte VEX prefix in 32bit. */
24452 {
24453 /* REX.W bit uses 3 byte VEX prefix. */
24457 }
24458 else
24459 {
24460 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24464 }
24467 }
24468 \f
24469 /* Return the maximum number of instructions a cpu can issue. */
24471 static int
24473 {
24475 {
24503 }
24504 }
24506 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24507 by DEP_INSN and nothing set by DEP_INSN. */
24509 static bool
24511 {
24514 /* Simplify the test for uninteresting insns. */
24522 {
24525 }
24530 {
24533 }
24534 else
24540 /* This test is true if the dependent insn reads the flags but
24541 not any other potentially set register. */
24549 }
24551 /* Return true iff USE_INSN has a memory address with operands set by
24552 SET_INSN. */
24554 bool
24556 {
24561 {
24564 }
24566 }
24568 /* Helper function for exact_store_load_dependency.
24569 Return true if addr is found in insn. */
24570 static bool
24572 {
24579 {
24585 CASE_CONST_ANY:
24594 }
24598 {
24600 {
24610 }
24611 }
24613 }
24615 /* Return true if there exists exact dependency for store & load, i.e.
24616 the same memory address is used in them. */
24617 static bool
24619 {
24633 }
24635 static int
24637 {
24643 /* Anti and output dependencies have zero cost on all CPUs. */
24649 /* If we can't recognize the insns, we can't really do anything. */
24657 {
24659 /* Address Generation Interlock adds a cycle of latency. */
24661 {
24672 }
24676 /* ??? Compares pair with jump/setcc. */
24680 /* Floating point stores require value to be ready one cycle earlier. */
24690 /* INT->FP conversion is expensive. */
24694 /* There is one cycle extra latency between an FP op and a store. */
24702 /* Show ability of reorder buffer to hide latency of load by executing
24703 in parallel with previous instruction in case
24704 previous instruction is not needed to compute the address. */
24707 {
24708 /* Claim moves to take one cycle, as core can issue one load
24709 at time and the next load can start cycle later. */
24714 cost--;
24715 }
24721 /* The esp dependency is resolved before the instruction is really
24722 finished. */
24727 /* INT->FP conversion is expensive. */
24731 /* Show ability of reorder buffer to hide latency of load by executing
24732 in parallel with previous instruction in case
24733 previous instruction is not needed to compute the address. */
24736 {
24737 /* Claim moves to take one cycle, as core can issue one load
24738 at time and the next load can start cycle later. */
24744 else
24746 }
24760 /* Stack engine allows to execute push&pop instructions in parall. */
24766 /* Show ability of reorder buffer to hide latency of load by executing
24767 in parallel with previous instruction in case
24768 previous instruction is not needed to compute the address. */
24771 {
24775 /* Because of the difference between the length of integer and
24776 floating unit pipeline preparation stages, the memory operands
24777 for floating point are cheaper.
24779 ??? For Athlon it the difference is most probably 2. */
24782 else
24787 else
24789 }
24797 /* Stack engine allows to execute push&pop instructions in parall. */
24802 /* Show ability of reorder buffer to hide latency of load by executing
24803 in parallel with previous instruction in case
24804 previous instruction is not needed to compute the address. */
24807 {
24810 else
24812 }
24819 /* Increase cost of integer loads. */
24822 {
24825 {
24828 else
24829 {
24830 /* Increase cost of ld/st for short int types only
24831 because of store forwarding issue. */
24835 {
24836 /* Increase cost of store/load insn if exact
24837 dependence exists and it is load insn. */
24842 }
24843 }
24844 }
24845 }
24849 }
24852 }
24854 /* How many alternative schedules to try. This should be as wide as the
24855 scheduling freedom in the DFA, but no wider. Making this value too
24856 large results extra work for the scheduler. */
24858 static int
24860 {
24862 {
24875 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24876 as many instructions can be executed on a cycle, i.e.,
24877 issue_rate. I wonder why tuning for many CPUs does not do this. */
24880 /* Don't use lookahead for pre-reload schedule to save compile time. */
24885 }
24886 }
24888 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24889 execution. It is applied if
24890 (1) IMUL instruction is on the top of list;
24891 (2) There exists the only producer of independent IMUL instruction in
24892 ready list.
24893 Return index of IMUL producer if it was found and -1 otherwise. */
24894 static int
24896 {
24898 sd_iterator_def sd_it;
24899 dep_t dep;
24906 /* Check that IMUL instruction is on the top of ready list. */
24915 /* Search for producer of independent IMUL instruction. */
24917 {
24921 /* Skip IMUL instruction. */
24931 {
24932 rtx con;
24943 {
24944 sd_iterator_def sd_it1;
24945 dep_t dep1;
24946 /* Check if there is no other dependee for IMUL. */
24949 {
24950 rtx pro;
24956 }
24959 }
24960 }
24963 }
24965 }
24967 /* Try to find the best candidate on the top of ready list if two insns
24968 have the same priority - candidate is best if its dependees were
24969 scheduled earlier. Applied for Silvermont only.
24970 Return true if top 2 insns must be interchanged. */
24971 static bool
24973 {
24976 rtx set;
24977 sd_iterator_def sd_it;
24978 dep_t dep;
24981 #define INSN_TICK(INSN) (HID (INSN)->tick)
25002 {
25005 /* Determine winner more precise. */
25007 {
25008 rtx pro;
25014 }
25016 {
25017 rtx pro;
25023 }
25026 {
25027 /* Determine winner - load must win. */
25033 }
25035 }
25037 #undef INSN_TICK
25038 }
25040 /* Perform possible reodering of ready list for Atom/Silvermont only.
25041 Return issue rate. */
25042 static int
25045 {
25049 rtx insn;
25052 /* Set up issue rate. */
25055 /* Do reodering for Atom/SLM only. */
25059 /* Nothing to do if ready list contains only 1 instruction. */
25063 /* Do reodering for post-reload scheduler only. */
25068 {
25073 /* Put IMUL producer (ready[index]) at the top of ready list. */
25079 }
25081 {
25085 /* Swap 2 top elements of ready list. */
25089 }
25091 }
25093 static bool
25096 /* Returns true if lhs of insn is HW function argument register and set up
25097 is_spilled to true if it is likely spilled HW register. */
25098 static bool
25100 {
25101 rtx dst;
25105 /* Call instructions are not movable, ignore it. */
25116 {
25117 /* Is it likely spilled HW register? */
25122 }
25124 }
25126 /* Add output dependencies for chain of function adjacent arguments if only
25127 there is a move to likely spilled HW register. Return first argument
25128 if at least one dependence was added or NULL otherwise. */
25129 static rtx
25131 {
25132 rtx insn;
25139 /* Find nearest to call argument passing instruction. */
25141 {
25150 }
25154 {
25161 {
25164 }
25166 {
25167 /* Add output depdendence between two function arguments if chain
25168 of output arguments contains likely spilled HW registers. */
25172 }
25173 else
25175 }
25179 }
25181 /* Add output or anti dependency from insn to first_arg to restrict its code
25182 motion. */
25183 static void
25185 {
25186 rtx set;
25187 rtx tmp;
25194 {
25195 /* Add output dependency to the first function argument. */
25198 }
25199 /* Add anti dependency. */
25201 }
25203 /* Avoid cross block motion of function argument through adding dependency
25204 from the first non-jump instruction in bb. */
25205 static void
25207 {
25211 {
25213 {
25216 {
25219 }
25220 }
25224 }
25225 }
25227 /* Hook for pre-reload schedule - avoid motion of function arguments
25228 passed in likely spilled HW registers. */
25229 static void
25231 {
25232 rtx insn;
25240 {
25243 {
25244 /* Add dependee for first argument to predecessors if only
25245 region contains more than one block. */
25249 /* Skip trivial regions and region head blocks that can have
25250 predecessors outside of region. */
25252 {
25253 edge e;
25254 edge_iterator ei;
25255 /* Assume that region is SCC, i.e. all immediate predecessors
25256 of non-head block are in the same region. */
25258 {
25259 /* Avoid creating of loop-carried dependencies through
25260 using topological odering in region. */
25263 }
25264 }
25268 }
25269 }
25272 }
25274 /* Hook for pre-reload schedule - set priority of moves from likely spilled
25275 HW registers to maximum, to schedule them at soon as possible. These are
25276 moves from function argument registers at the top of the function entry
25277 and moves from function return value registers after call. */
25278 static int
25280 {
25281 rtx set;
25291 {
25298 }
25301 }
25303 /* Model decoder of Core 2/i7.
25304 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
25305 track the instruction fetch block boundaries and make sure that long
25306 (9+ bytes) instructions are assigned to D0. */
25308 /* Maximum length of an insn that can be handled by
25309 a secondary decoder unit. '8' for Core 2/i7. */
25312 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
25313 '16' for Core 2/i7. */
25316 /* Maximum number of instructions decoder can handle per cycle.
25317 '6' for Core 2/i7. */
25321 ix86_first_cycle_multipass_data_t;
25323 const_ix86_first_cycle_multipass_data_t;
25325 /* A variable to store target state across calls to max_issue within
25326 one cycle. */
25330 /* Initialize DATA. */
25331 static void
25333 {
25334 ix86_first_cycle_multipass_data_t data
25341 }
25343 /* Advancing the cycle; reset ifetch block counts. */
25344 static void
25346 {
25353 }
25357 /* Filter out insns from ready_try that the core will not be able to issue
25358 on current cycle due to decoder. */
25359 static void
25360 core2i7_first_cycle_multipass_filter_ready_try
25363 {
25365 {
25366 rtx insn;
25376 (!first_cycle_insn_p
25378 /* ... or it would not fit into the ifetch block ... */
25380 /* ... or the decoder is full already ... */
25382 /* ... mask the insn out. */
25383 {
25388 }
25389 }
25390 }
25392 /* Prepare for a new round of multipass lookahead scheduling. */
25393 static void
25396 {
25397 ix86_first_cycle_multipass_data_t data
25399 const_ix86_first_cycle_multipass_data_t prev_data
25402 /* Restore the state from the end of the previous round. */
25406 /* Filter instructions that cannot be issued on current cycle due to
25407 decoder restrictions. */
25409 first_cycle_insn_p);
25410 }
25412 /* INSN is being issued in current solution. Account for its impact on
25413 the decoder model. */
25414 static void
25417 {
25418 ix86_first_cycle_multipass_data_t data
25420 const_ix86_first_cycle_multipass_data_t prev_data
25430 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
25432 {
25435 }
25437 {
25441 }
25444 /* Filter out insns from ready_try that the core will not be able to issue
25445 on current cycle due to decoder. */
25448 }
25450 /* Revert the effect on ready_try. */
25451 static void
25455 {
25456 const_ix86_first_cycle_multipass_data_t data
25459 sbitmap_iterator sbi;
25463 {
25465 }
25466 }
25468 /* Save the result of multipass lookahead scheduling for the next round. */
25469 static void
25471 {
25472 const_ix86_first_cycle_multipass_data_t data
25474 ix86_first_cycle_multipass_data_t next_data
25478 {
25481 }
25482 }
25484 /* Deallocate target data. */
25485 static void
25487 {
25488 ix86_first_cycle_multipass_data_t data
25492 {
25496 }
25497 }
25499 /* Prepare for scheduling pass. */
25500 static void
25504 {
25505 /* Install scheduling hooks for current CPU. Some of these hooks are used
25506 in time-critical parts of the scheduler, so we only set them up when
25507 they are actually used. */
25509 {
25513 /* Do not perform multipass scheduling for pre-reload schedule
25514 to save compile time. */
25516 {
25532 /* Set decoder parameters. */
25537 }
25538 /* ... Fall through ... */
25548 }
25549 }
25551 \f
25552 /* Compute the alignment given to a constant that is being placed in memory.
25553 EXP is the constant and ALIGN is the alignment that the object would
25554 ordinarily have.
25555 The value of this function is used instead of that alignment to align
25556 the object. */
25558 int
25560 {
25563 {
25568 }
25574 }
25576 /* Compute the alignment for a static variable.
25577 TYPE is the data type, and ALIGN is the alignment that
25578 the object would ordinarily have. The value of this function is used
25579 instead of that alignment to align the object. */
25581 int
25583 {
25595 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25596 to 16byte boundary. */
25598 {
25605 }
25611 {
25616 }
25618 {
25625 }
25630 {
25635 }
25638 {
25643 }
25646 }
25648 /* Compute the alignment for a local variable or a stack slot. EXP is
25649 the data type or decl itself, MODE is the widest mode available and
25650 ALIGN is the alignment that the object would ordinarily have. The
25651 value of this macro is used instead of that alignment to align the
25652 object. */
25654 unsigned int
25657 {
25661 {
25664 }
25665 else
25666 {
25669 }
25671 /* Don't do dynamic stack realignment for long long objects with
25672 -mpreferred-stack-boundary=2. */
25681 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25682 register in MODE. We will return the largest alignment of XF
25683 and DF. */
25685 {
25689 }
25691 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25692 to 16byte boundary. Exact wording is:
25694 An array uses the same alignment as its elements, except that a local or
25695 global array variable of length at least 16 bytes or
25696 a C99 variable-length array variable always has alignment of at least 16 bytes.
25698 This was added to allow use of aligned SSE instructions at arrays. This
25699 rule is meant for static storage (where compiler can not do the analysis
25700 by itself). We follow it for automatic variables only when convenient.
25701 We fully control everything in the function compiled and functions from
25702 other unit can not rely on the alignment.
25704 Exclude va_list type. It is the common case of local array where
25705 we can not benefit from the alignment.
25707 TODO: Probably one should optimize for size only when var is not escaping. */
25710 {
25720 }
25722 {
25727 }
25729 {
25735 }
25740 {
25745 }
25748 {
25754 }
25756 }
25758 /* Compute the minimum required alignment for dynamic stack realignment
25759 purposes for a local variable, parameter or a stack slot. EXP is
25760 the data type or decl itself, MODE is its mode and ALIGN is the
25761 alignment that the object would ordinarily have. */
25763 unsigned int
25766 {
25770 {
25773 }
25774 else
25775 {
25778 }
25783 /* Don't do dynamic stack realignment for long long objects with
25784 -mpreferred-stack-boundary=2. */
25791 }
25792 \f
25793 /* Find a location for the static chain incoming to a nested function.
25794 This is a register, unless all free registers are used by arguments. */
25796 static rtx
25798 {
25805 {
25806 /* We always use R10 in 64-bit mode. */
25808 }
25809 else
25810 {
25811 tree fntype;
25814 /* By default in 32-bit mode we use ECX to pass the static chain. */
25820 {
25821 /* Fastcall functions use ecx/edx for arguments, which leaves
25822 us with EAX for the static chain.
25823 Thiscall functions use ecx for arguments, which also
25824 leaves us with EAX for the static chain. */
25826 }
25828 {
25829 /* Thiscall functions use ecx for arguments, which leaves
25830 us with EAX and EDX for the static chain.
25831 We are using for abi-compatibility EAX. */
25833 }
25835 {
25836 /* For regparm 3, we have no free call-clobbered registers in
25837 which to store the static chain. In order to implement this,
25838 we have the trampoline push the static chain to the stack.
25839 However, we can't push a value below the return address when
25840 we call the nested function directly, so we have to use an
25841 alternate entry point. For this we use ESI, and have the
25842 alternate entry point push ESI, so that things appear the
25843 same once we're executing the nested function. */
25845 {
25851 }
25853 }
25854 }
25857 }
25859 /* Emit RTL insns to initialize the variable parts of a trampoline.
25860 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25861 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25862 to be passed to the target function. */
25864 static void
25866 {
25874 {
25877 /* Load the function address to r11. Try to load address using
25878 the shorter movl instead of movabs. We may want to support
25879 movq for kernel mode, but kernel does not use trampolines at
25880 the moment. FNADDR is a 32bit address and may not be in
25881 DImode when ptr_mode == SImode. Always use movl in this
25882 case. */
25885 {
25894 }
25895 else
25896 {
25903 }
25905 /* Load static chain using movabs to r10. Use the shorter movl
25906 instead of movabs when ptr_mode == SImode. */
25908 {
25911 }
25912 else
25913 {
25916 }
25925 /* Jump to r11; the last (unused) byte is a nop, only there to
25926 pad the write out to a single 32-bit store. */
25930 }
25931 else
25932 {
25935 /* Depending on the static chain location, either load a register
25936 with a constant, or push the constant to the stack. All of the
25937 instructions are the same size. */
25940 {
25942 {
25949 }
25950 }
25951 else
25966 /* Compute offset from the end of the jmp to the target function.
25967 In the case in which the trampoline stores the static chain on
25968 the stack, we need to skip the first insn which pushes the
25969 (call-saved) register static chain; this push is 1 byte. */
25976 }
25980 #ifdef HAVE_ENABLE_EXECUTE_STACK
25981 #ifdef CHECK_EXECUTE_STACK_ENABLED
25983 #endif
25986 #endif
25987 }
25988 \f
25989 /* The following file contains several enumerations and data structures
25990 built from the definitions in i386-builtin-types.def. */
25994 /* Table for the ix86 builtin non-function types. */
25997 /* Retrieve an element from the above table, building some of
25998 the types lazily. */
26000 static tree
26002 {
26014 {
26022 }
26023 else
26024 {
26030 else
26038 }
26042 }
26044 /* Table for the ix86 builtin function types. */
26047 /* Retrieve an element from the above table, building some of
26048 the types lazily. */
26050 static tree
26052 {
26053 tree type;
26062 {
26070 {
26073 }
26076 }
26077 else
26078 {
26084 }
26088 }
26091 /* Codes for all the SSE/MMX builtins. */
26092 enum ix86_builtins
26093 {
26094 IX86_BUILTIN_ADDPS,
26095 IX86_BUILTIN_ADDSS,
26096 IX86_BUILTIN_DIVPS,
26097 IX86_BUILTIN_DIVSS,
26098 IX86_BUILTIN_MULPS,
26099 IX86_BUILTIN_MULSS,
26100 IX86_BUILTIN_SUBPS,
26101 IX86_BUILTIN_SUBSS,
26103 IX86_BUILTIN_CMPEQPS,
26104 IX86_BUILTIN_CMPLTPS,
26105 IX86_BUILTIN_CMPLEPS,
26106 IX86_BUILTIN_CMPGTPS,
26107 IX86_BUILTIN_CMPGEPS,
26108 IX86_BUILTIN_CMPNEQPS,
26109 IX86_BUILTIN_CMPNLTPS,
26110 IX86_BUILTIN_CMPNLEPS,
26111 IX86_BUILTIN_CMPNGTPS,
26112 IX86_BUILTIN_CMPNGEPS,
26113 IX86_BUILTIN_CMPORDPS,
26114 IX86_BUILTIN_CMPUNORDPS,
26115 IX86_BUILTIN_CMPEQSS,
26116 IX86_BUILTIN_CMPLTSS,
26117 IX86_BUILTIN_CMPLESS,
26118 IX86_BUILTIN_CMPNEQSS,
26119 IX86_BUILTIN_CMPNLTSS,
26120 IX86_BUILTIN_CMPNLESS,
26121 IX86_BUILTIN_CMPORDSS,
26122 IX86_BUILTIN_CMPUNORDSS,
26124 IX86_BUILTIN_COMIEQSS,
26125 IX86_BUILTIN_COMILTSS,
26126 IX86_BUILTIN_COMILESS,
26127 IX86_BUILTIN_COMIGTSS,
26128 IX86_BUILTIN_COMIGESS,
26129 IX86_BUILTIN_COMINEQSS,
26130 IX86_BUILTIN_UCOMIEQSS,
26131 IX86_BUILTIN_UCOMILTSS,
26132 IX86_BUILTIN_UCOMILESS,
26133 IX86_BUILTIN_UCOMIGTSS,
26134 IX86_BUILTIN_UCOMIGESS,
26135 IX86_BUILTIN_UCOMINEQSS,
26137 IX86_BUILTIN_CVTPI2PS,
26138 IX86_BUILTIN_CVTPS2PI,
26139 IX86_BUILTIN_CVTSI2SS,
26140 IX86_BUILTIN_CVTSI642SS,
26141 IX86_BUILTIN_CVTSS2SI,
26142 IX86_BUILTIN_CVTSS2SI64,
26143 IX86_BUILTIN_CVTTPS2PI,
26144 IX86_BUILTIN_CVTTSS2SI,
26145 IX86_BUILTIN_CVTTSS2SI64,
26147 IX86_BUILTIN_MAXPS,
26148 IX86_BUILTIN_MAXSS,
26149 IX86_BUILTIN_MINPS,
26150 IX86_BUILTIN_MINSS,
26152 IX86_BUILTIN_LOADUPS,
26153 IX86_BUILTIN_STOREUPS,
26154 IX86_BUILTIN_MOVSS,
26156 IX86_BUILTIN_MOVHLPS,
26157 IX86_BUILTIN_MOVLHPS,
26158 IX86_BUILTIN_LOADHPS,
26159 IX86_BUILTIN_LOADLPS,
26160 IX86_BUILTIN_STOREHPS,
26161 IX86_BUILTIN_STORELPS,
26163 IX86_BUILTIN_MASKMOVQ,
26164 IX86_BUILTIN_MOVMSKPS,
26165 IX86_BUILTIN_PMOVMSKB,
26167 IX86_BUILTIN_MOVNTPS,
26168 IX86_BUILTIN_MOVNTQ,
26170 IX86_BUILTIN_LOADDQU,
26171 IX86_BUILTIN_STOREDQU,
26173 IX86_BUILTIN_PACKSSWB,
26174 IX86_BUILTIN_PACKSSDW,
26175 IX86_BUILTIN_PACKUSWB,
26177 IX86_BUILTIN_PADDB,
26178 IX86_BUILTIN_PADDW,
26179 IX86_BUILTIN_PADDD,
26180 IX86_BUILTIN_PADDQ,
26181 IX86_BUILTIN_PADDSB,
26182 IX86_BUILTIN_PADDSW,
26183 IX86_BUILTIN_PADDUSB,
26184 IX86_BUILTIN_PADDUSW,
26185 IX86_BUILTIN_PSUBB,
26186 IX86_BUILTIN_PSUBW,
26187 IX86_BUILTIN_PSUBD,
26188 IX86_BUILTIN_PSUBQ,
26189 IX86_BUILTIN_PSUBSB,
26190 IX86_BUILTIN_PSUBSW,
26191 IX86_BUILTIN_PSUBUSB,
26192 IX86_BUILTIN_PSUBUSW,
26194 IX86_BUILTIN_PAND,
26195 IX86_BUILTIN_PANDN,
26196 IX86_BUILTIN_POR,
26197 IX86_BUILTIN_PXOR,
26199 IX86_BUILTIN_PAVGB,
26200 IX86_BUILTIN_PAVGW,
26202 IX86_BUILTIN_PCMPEQB,
26203 IX86_BUILTIN_PCMPEQW,
26204 IX86_BUILTIN_PCMPEQD,
26205 IX86_BUILTIN_PCMPGTB,
26206 IX86_BUILTIN_PCMPGTW,
26207 IX86_BUILTIN_PCMPGTD,
26209 IX86_BUILTIN_PMADDWD,
26211 IX86_BUILTIN_PMAXSW,
26212 IX86_BUILTIN_PMAXUB,
26213 IX86_BUILTIN_PMINSW,
26214 IX86_BUILTIN_PMINUB,
26216 IX86_BUILTIN_PMULHUW,
26217 IX86_BUILTIN_PMULHW,
26218 IX86_BUILTIN_PMULLW,
26220 IX86_BUILTIN_PSADBW,
26221 IX86_BUILTIN_PSHUFW,
26223 IX86_BUILTIN_PSLLW,
26224 IX86_BUILTIN_PSLLD,
26225 IX86_BUILTIN_PSLLQ,
26226 IX86_BUILTIN_PSRAW,
26227 IX86_BUILTIN_PSRAD,
26228 IX86_BUILTIN_PSRLW,
26229 IX86_BUILTIN_PSRLD,
26230 IX86_BUILTIN_PSRLQ,
26231 IX86_BUILTIN_PSLLWI,
26232 IX86_BUILTIN_PSLLDI,
26233 IX86_BUILTIN_PSLLQI,
26234 IX86_BUILTIN_PSRAWI,
26235 IX86_BUILTIN_PSRADI,
26236 IX86_BUILTIN_PSRLWI,
26237 IX86_BUILTIN_PSRLDI,
26238 IX86_BUILTIN_PSRLQI,
26240 IX86_BUILTIN_PUNPCKHBW,
26241 IX86_BUILTIN_PUNPCKHWD,
26242 IX86_BUILTIN_PUNPCKHDQ,
26243 IX86_BUILTIN_PUNPCKLBW,
26244 IX86_BUILTIN_PUNPCKLWD,
26245 IX86_BUILTIN_PUNPCKLDQ,
26247 IX86_BUILTIN_SHUFPS,
26249 IX86_BUILTIN_RCPPS,
26250 IX86_BUILTIN_RCPSS,
26251 IX86_BUILTIN_RSQRTPS,
26252 IX86_BUILTIN_RSQRTPS_NR,
26253 IX86_BUILTIN_RSQRTSS,
26254 IX86_BUILTIN_RSQRTF,
26255 IX86_BUILTIN_SQRTPS,
26256 IX86_BUILTIN_SQRTPS_NR,
26257 IX86_BUILTIN_SQRTSS,
26259 IX86_BUILTIN_UNPCKHPS,
26260 IX86_BUILTIN_UNPCKLPS,
26262 IX86_BUILTIN_ANDPS,
26263 IX86_BUILTIN_ANDNPS,
26264 IX86_BUILTIN_ORPS,
26265 IX86_BUILTIN_XORPS,
26267 IX86_BUILTIN_EMMS,
26268 IX86_BUILTIN_LDMXCSR,
26269 IX86_BUILTIN_STMXCSR,
26270 IX86_BUILTIN_SFENCE,
26272 IX86_BUILTIN_FXSAVE,
26273 IX86_BUILTIN_FXRSTOR,
26274 IX86_BUILTIN_FXSAVE64,
26275 IX86_BUILTIN_FXRSTOR64,
26277 IX86_BUILTIN_XSAVE,
26278 IX86_BUILTIN_XRSTOR,
26279 IX86_BUILTIN_XSAVE64,
26280 IX86_BUILTIN_XRSTOR64,
26282 IX86_BUILTIN_XSAVEOPT,
26283 IX86_BUILTIN_XSAVEOPT64,
26285 /* 3DNow! Original */
26286 IX86_BUILTIN_FEMMS,
26287 IX86_BUILTIN_PAVGUSB,
26288 IX86_BUILTIN_PF2ID,
26289 IX86_BUILTIN_PFACC,
26290 IX86_BUILTIN_PFADD,
26291 IX86_BUILTIN_PFCMPEQ,
26292 IX86_BUILTIN_PFCMPGE,
26293 IX86_BUILTIN_PFCMPGT,
26294 IX86_BUILTIN_PFMAX,
26295 IX86_BUILTIN_PFMIN,
26296 IX86_BUILTIN_PFMUL,
26297 IX86_BUILTIN_PFRCP,
26298 IX86_BUILTIN_PFRCPIT1,
26299 IX86_BUILTIN_PFRCPIT2,
26300 IX86_BUILTIN_PFRSQIT1,
26301 IX86_BUILTIN_PFRSQRT,
26302 IX86_BUILTIN_PFSUB,
26303 IX86_BUILTIN_PFSUBR,
26304 IX86_BUILTIN_PI2FD,
26305 IX86_BUILTIN_PMULHRW,
26307 /* 3DNow! Athlon Extensions */
26308 IX86_BUILTIN_PF2IW,
26309 IX86_BUILTIN_PFNACC,
26310 IX86_BUILTIN_PFPNACC,
26311 IX86_BUILTIN_PI2FW,
26312 IX86_BUILTIN_PSWAPDSI,
26313 IX86_BUILTIN_PSWAPDSF,
26315 /* SSE2 */
26316 IX86_BUILTIN_ADDPD,
26317 IX86_BUILTIN_ADDSD,
26318 IX86_BUILTIN_DIVPD,
26319 IX86_BUILTIN_DIVSD,
26320 IX86_BUILTIN_MULPD,
26321 IX86_BUILTIN_MULSD,
26322 IX86_BUILTIN_SUBPD,
26323 IX86_BUILTIN_SUBSD,
26325 IX86_BUILTIN_CMPEQPD,
26326 IX86_BUILTIN_CMPLTPD,
26327 IX86_BUILTIN_CMPLEPD,
26328 IX86_BUILTIN_CMPGTPD,
26329 IX86_BUILTIN_CMPGEPD,
26330 IX86_BUILTIN_CMPNEQPD,
26331 IX86_BUILTIN_CMPNLTPD,
26332 IX86_BUILTIN_CMPNLEPD,
26333 IX86_BUILTIN_CMPNGTPD,
26334 IX86_BUILTIN_CMPNGEPD,
26335 IX86_BUILTIN_CMPORDPD,
26336 IX86_BUILTIN_CMPUNORDPD,
26337 IX86_BUILTIN_CMPEQSD,
26338 IX86_BUILTIN_CMPLTSD,
26339 IX86_BUILTIN_CMPLESD,
26340 IX86_BUILTIN_CMPNEQSD,
26341 IX86_BUILTIN_CMPNLTSD,
26342 IX86_BUILTIN_CMPNLESD,
26343 IX86_BUILTIN_CMPORDSD,
26344 IX86_BUILTIN_CMPUNORDSD,
26346 IX86_BUILTIN_COMIEQSD,
26347 IX86_BUILTIN_COMILTSD,
26348 IX86_BUILTIN_COMILESD,
26349 IX86_BUILTIN_COMIGTSD,
26350 IX86_BUILTIN_COMIGESD,
26351 IX86_BUILTIN_COMINEQSD,
26352 IX86_BUILTIN_UCOMIEQSD,
26353 IX86_BUILTIN_UCOMILTSD,
26354 IX86_BUILTIN_UCOMILESD,
26355 IX86_BUILTIN_UCOMIGTSD,
26356 IX86_BUILTIN_UCOMIGESD,
26357 IX86_BUILTIN_UCOMINEQSD,
26359 IX86_BUILTIN_MAXPD,
26360 IX86_BUILTIN_MAXSD,
26361 IX86_BUILTIN_MINPD,
26362 IX86_BUILTIN_MINSD,
26364 IX86_BUILTIN_ANDPD,
26365 IX86_BUILTIN_ANDNPD,
26366 IX86_BUILTIN_ORPD,
26367 IX86_BUILTIN_XORPD,
26369 IX86_BUILTIN_SQRTPD,
26370 IX86_BUILTIN_SQRTSD,
26372 IX86_BUILTIN_UNPCKHPD,
26373 IX86_BUILTIN_UNPCKLPD,
26375 IX86_BUILTIN_SHUFPD,
26377 IX86_BUILTIN_LOADUPD,
26378 IX86_BUILTIN_STOREUPD,
26379 IX86_BUILTIN_MOVSD,
26381 IX86_BUILTIN_LOADHPD,
26382 IX86_BUILTIN_LOADLPD,
26384 IX86_BUILTIN_CVTDQ2PD,
26385 IX86_BUILTIN_CVTDQ2PS,
26387 IX86_BUILTIN_CVTPD2DQ,
26388 IX86_BUILTIN_CVTPD2PI,
26389 IX86_BUILTIN_CVTPD2PS,
26390 IX86_BUILTIN_CVTTPD2DQ,
26391 IX86_BUILTIN_CVTTPD2PI,
26393 IX86_BUILTIN_CVTPI2PD,
26394 IX86_BUILTIN_CVTSI2SD,
26395 IX86_BUILTIN_CVTSI642SD,
26397 IX86_BUILTIN_CVTSD2SI,
26398 IX86_BUILTIN_CVTSD2SI64,
26399 IX86_BUILTIN_CVTSD2SS,
26400 IX86_BUILTIN_CVTSS2SD,
26401 IX86_BUILTIN_CVTTSD2SI,
26402 IX86_BUILTIN_CVTTSD2SI64,
26404 IX86_BUILTIN_CVTPS2DQ,
26405 IX86_BUILTIN_CVTPS2PD,
26406 IX86_BUILTIN_CVTTPS2DQ,
26408 IX86_BUILTIN_MOVNTI,
26409 IX86_BUILTIN_MOVNTI64,
26410 IX86_BUILTIN_MOVNTPD,
26411 IX86_BUILTIN_MOVNTDQ,
26413 IX86_BUILTIN_MOVQ128,
26415 /* SSE2 MMX */
26416 IX86_BUILTIN_MASKMOVDQU,
26417 IX86_BUILTIN_MOVMSKPD,
26418 IX86_BUILTIN_PMOVMSKB128,
26420 IX86_BUILTIN_PACKSSWB128,
26421 IX86_BUILTIN_PACKSSDW128,
26422 IX86_BUILTIN_PACKUSWB128,
26424 IX86_BUILTIN_PADDB128,
26425 IX86_BUILTIN_PADDW128,
26426 IX86_BUILTIN_PADDD128,
26427 IX86_BUILTIN_PADDQ128,
26428 IX86_BUILTIN_PADDSB128,
26429 IX86_BUILTIN_PADDSW128,
26430 IX86_BUILTIN_PADDUSB128,
26431 IX86_BUILTIN_PADDUSW128,
26432 IX86_BUILTIN_PSUBB128,
26433 IX86_BUILTIN_PSUBW128,
26434 IX86_BUILTIN_PSUBD128,
26435 IX86_BUILTIN_PSUBQ128,
26436 IX86_BUILTIN_PSUBSB128,
26437 IX86_BUILTIN_PSUBSW128,
26438 IX86_BUILTIN_PSUBUSB128,
26439 IX86_BUILTIN_PSUBUSW128,
26441 IX86_BUILTIN_PAND128,
26442 IX86_BUILTIN_PANDN128,
26443 IX86_BUILTIN_POR128,
26444 IX86_BUILTIN_PXOR128,
26446 IX86_BUILTIN_PAVGB128,
26447 IX86_BUILTIN_PAVGW128,
26449 IX86_BUILTIN_PCMPEQB128,
26450 IX86_BUILTIN_PCMPEQW128,
26451 IX86_BUILTIN_PCMPEQD128,
26452 IX86_BUILTIN_PCMPGTB128,
26453 IX86_BUILTIN_PCMPGTW128,
26454 IX86_BUILTIN_PCMPGTD128,
26456 IX86_BUILTIN_PMADDWD128,
26458 IX86_BUILTIN_PMAXSW128,
26459 IX86_BUILTIN_PMAXUB128,
26460 IX86_BUILTIN_PMINSW128,
26461 IX86_BUILTIN_PMINUB128,
26463 IX86_BUILTIN_PMULUDQ,
26464 IX86_BUILTIN_PMULUDQ128,
26465 IX86_BUILTIN_PMULHUW128,
26466 IX86_BUILTIN_PMULHW128,
26467 IX86_BUILTIN_PMULLW128,
26469 IX86_BUILTIN_PSADBW128,
26470 IX86_BUILTIN_PSHUFHW,
26471 IX86_BUILTIN_PSHUFLW,
26472 IX86_BUILTIN_PSHUFD,
26474 IX86_BUILTIN_PSLLDQI128,
26475 IX86_BUILTIN_PSLLWI128,
26476 IX86_BUILTIN_PSLLDI128,
26477 IX86_BUILTIN_PSLLQI128,
26478 IX86_BUILTIN_PSRAWI128,
26479 IX86_BUILTIN_PSRADI128,
26480 IX86_BUILTIN_PSRLDQI128,
26481 IX86_BUILTIN_PSRLWI128,
26482 IX86_BUILTIN_PSRLDI128,
26483 IX86_BUILTIN_PSRLQI128,
26485 IX86_BUILTIN_PSLLDQ128,
26486 IX86_BUILTIN_PSLLW128,
26487 IX86_BUILTIN_PSLLD128,
26488 IX86_BUILTIN_PSLLQ128,
26489 IX86_BUILTIN_PSRAW128,
26490 IX86_BUILTIN_PSRAD128,
26491 IX86_BUILTIN_PSRLW128,
26492 IX86_BUILTIN_PSRLD128,
26493 IX86_BUILTIN_PSRLQ128,
26495 IX86_BUILTIN_PUNPCKHBW128,
26496 IX86_BUILTIN_PUNPCKHWD128,
26497 IX86_BUILTIN_PUNPCKHDQ128,
26498 IX86_BUILTIN_PUNPCKHQDQ128,
26499 IX86_BUILTIN_PUNPCKLBW128,
26500 IX86_BUILTIN_PUNPCKLWD128,
26501 IX86_BUILTIN_PUNPCKLDQ128,
26502 IX86_BUILTIN_PUNPCKLQDQ128,
26504 IX86_BUILTIN_CLFLUSH,
26505 IX86_BUILTIN_MFENCE,
26506 IX86_BUILTIN_LFENCE,
26507 IX86_BUILTIN_PAUSE,
26509 IX86_BUILTIN_BSRSI,
26510 IX86_BUILTIN_BSRDI,
26511 IX86_BUILTIN_RDPMC,
26512 IX86_BUILTIN_RDTSC,
26513 IX86_BUILTIN_RDTSCP,
26514 IX86_BUILTIN_ROLQI,
26515 IX86_BUILTIN_ROLHI,
26516 IX86_BUILTIN_RORQI,
26517 IX86_BUILTIN_RORHI,
26519 /* SSE3. */
26520 IX86_BUILTIN_ADDSUBPS,
26521 IX86_BUILTIN_HADDPS,
26522 IX86_BUILTIN_HSUBPS,
26523 IX86_BUILTIN_MOVSHDUP,
26524 IX86_BUILTIN_MOVSLDUP,
26525 IX86_BUILTIN_ADDSUBPD,
26526 IX86_BUILTIN_HADDPD,
26527 IX86_BUILTIN_HSUBPD,
26528 IX86_BUILTIN_LDDQU,
26530 IX86_BUILTIN_MONITOR,
26531 IX86_BUILTIN_MWAIT,
26533 /* SSSE3. */
26534 IX86_BUILTIN_PHADDW,
26535 IX86_BUILTIN_PHADDD,
26536 IX86_BUILTIN_PHADDSW,
26537 IX86_BUILTIN_PHSUBW,
26538 IX86_BUILTIN_PHSUBD,
26539 IX86_BUILTIN_PHSUBSW,
26540 IX86_BUILTIN_PMADDUBSW,
26541 IX86_BUILTIN_PMULHRSW,
26542 IX86_BUILTIN_PSHUFB,
26543 IX86_BUILTIN_PSIGNB,
26544 IX86_BUILTIN_PSIGNW,
26545 IX86_BUILTIN_PSIGND,
26546 IX86_BUILTIN_PALIGNR,
26547 IX86_BUILTIN_PABSB,
26548 IX86_BUILTIN_PABSW,
26549 IX86_BUILTIN_PABSD,
26551 IX86_BUILTIN_PHADDW128,
26552 IX86_BUILTIN_PHADDD128,
26553 IX86_BUILTIN_PHADDSW128,
26554 IX86_BUILTIN_PHSUBW128,
26555 IX86_BUILTIN_PHSUBD128,
26556 IX86_BUILTIN_PHSUBSW128,
26557 IX86_BUILTIN_PMADDUBSW128,
26558 IX86_BUILTIN_PMULHRSW128,
26559 IX86_BUILTIN_PSHUFB128,
26560 IX86_BUILTIN_PSIGNB128,
26561 IX86_BUILTIN_PSIGNW128,
26562 IX86_BUILTIN_PSIGND128,
26563 IX86_BUILTIN_PALIGNR128,
26564 IX86_BUILTIN_PABSB128,
26565 IX86_BUILTIN_PABSW128,
26566 IX86_BUILTIN_PABSD128,
26568 /* AMDFAM10 - SSE4A New Instructions. */
26569 IX86_BUILTIN_MOVNTSD,
26570 IX86_BUILTIN_MOVNTSS,
26571 IX86_BUILTIN_EXTRQI,
26572 IX86_BUILTIN_EXTRQ,
26573 IX86_BUILTIN_INSERTQI,
26574 IX86_BUILTIN_INSERTQ,
26576 /* SSE4.1. */
26577 IX86_BUILTIN_BLENDPD,
26578 IX86_BUILTIN_BLENDPS,
26579 IX86_BUILTIN_BLENDVPD,
26580 IX86_BUILTIN_BLENDVPS,
26581 IX86_BUILTIN_PBLENDVB128,
26582 IX86_BUILTIN_PBLENDW128,
26584 IX86_BUILTIN_DPPD,
26585 IX86_BUILTIN_DPPS,
26587 IX86_BUILTIN_INSERTPS128,
26589 IX86_BUILTIN_MOVNTDQA,
26590 IX86_BUILTIN_MPSADBW128,
26591 IX86_BUILTIN_PACKUSDW128,
26592 IX86_BUILTIN_PCMPEQQ,
26593 IX86_BUILTIN_PHMINPOSUW128,
26595 IX86_BUILTIN_PMAXSB128,
26596 IX86_BUILTIN_PMAXSD128,
26597 IX86_BUILTIN_PMAXUD128,
26598 IX86_BUILTIN_PMAXUW128,
26600 IX86_BUILTIN_PMINSB128,
26601 IX86_BUILTIN_PMINSD128,
26602 IX86_BUILTIN_PMINUD128,
26603 IX86_BUILTIN_PMINUW128,
26605 IX86_BUILTIN_PMOVSXBW128,
26606 IX86_BUILTIN_PMOVSXBD128,
26607 IX86_BUILTIN_PMOVSXBQ128,
26608 IX86_BUILTIN_PMOVSXWD128,
26609 IX86_BUILTIN_PMOVSXWQ128,
26610 IX86_BUILTIN_PMOVSXDQ128,
26612 IX86_BUILTIN_PMOVZXBW128,
26613 IX86_BUILTIN_PMOVZXBD128,
26614 IX86_BUILTIN_PMOVZXBQ128,
26615 IX86_BUILTIN_PMOVZXWD128,
26616 IX86_BUILTIN_PMOVZXWQ128,
26617 IX86_BUILTIN_PMOVZXDQ128,
26619 IX86_BUILTIN_PMULDQ128,
26620 IX86_BUILTIN_PMULLD128,
26622 IX86_BUILTIN_ROUNDSD,
26623 IX86_BUILTIN_ROUNDSS,
26625 IX86_BUILTIN_ROUNDPD,
26626 IX86_BUILTIN_ROUNDPS,
26628 IX86_BUILTIN_FLOORPD,
26629 IX86_BUILTIN_CEILPD,
26630 IX86_BUILTIN_TRUNCPD,
26631 IX86_BUILTIN_RINTPD,
26632 IX86_BUILTIN_ROUNDPD_AZ,
26634 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26635 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26636 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26638 IX86_BUILTIN_FLOORPS,
26639 IX86_BUILTIN_CEILPS,
26640 IX86_BUILTIN_TRUNCPS,
26641 IX86_BUILTIN_RINTPS,
26642 IX86_BUILTIN_ROUNDPS_AZ,
26644 IX86_BUILTIN_FLOORPS_SFIX,
26645 IX86_BUILTIN_CEILPS_SFIX,
26646 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26648 IX86_BUILTIN_PTESTZ,
26649 IX86_BUILTIN_PTESTC,
26650 IX86_BUILTIN_PTESTNZC,
26652 IX86_BUILTIN_VEC_INIT_V2SI,
26653 IX86_BUILTIN_VEC_INIT_V4HI,
26654 IX86_BUILTIN_VEC_INIT_V8QI,
26655 IX86_BUILTIN_VEC_EXT_V2DF,
26656 IX86_BUILTIN_VEC_EXT_V2DI,
26657 IX86_BUILTIN_VEC_EXT_V4SF,
26658 IX86_BUILTIN_VEC_EXT_V4SI,
26659 IX86_BUILTIN_VEC_EXT_V8HI,
26660 IX86_BUILTIN_VEC_EXT_V2SI,
26661 IX86_BUILTIN_VEC_EXT_V4HI,
26662 IX86_BUILTIN_VEC_EXT_V16QI,
26663 IX86_BUILTIN_VEC_SET_V2DI,
26664 IX86_BUILTIN_VEC_SET_V4SF,
26665 IX86_BUILTIN_VEC_SET_V4SI,
26666 IX86_BUILTIN_VEC_SET_V8HI,
26667 IX86_BUILTIN_VEC_SET_V4HI,
26668 IX86_BUILTIN_VEC_SET_V16QI,
26670 IX86_BUILTIN_VEC_PACK_SFIX,
26671 IX86_BUILTIN_VEC_PACK_SFIX256,
26673 /* SSE4.2. */
26674 IX86_BUILTIN_CRC32QI,
26675 IX86_BUILTIN_CRC32HI,
26676 IX86_BUILTIN_CRC32SI,
26677 IX86_BUILTIN_CRC32DI,
26679 IX86_BUILTIN_PCMPESTRI128,
26680 IX86_BUILTIN_PCMPESTRM128,
26681 IX86_BUILTIN_PCMPESTRA128,
26682 IX86_BUILTIN_PCMPESTRC128,
26683 IX86_BUILTIN_PCMPESTRO128,
26684 IX86_BUILTIN_PCMPESTRS128,
26685 IX86_BUILTIN_PCMPESTRZ128,
26686 IX86_BUILTIN_PCMPISTRI128,
26687 IX86_BUILTIN_PCMPISTRM128,
26688 IX86_BUILTIN_PCMPISTRA128,
26689 IX86_BUILTIN_PCMPISTRC128,
26690 IX86_BUILTIN_PCMPISTRO128,
26691 IX86_BUILTIN_PCMPISTRS128,
26692 IX86_BUILTIN_PCMPISTRZ128,
26694 IX86_BUILTIN_PCMPGTQ,
26696 /* AES instructions */
26697 IX86_BUILTIN_AESENC128,
26698 IX86_BUILTIN_AESENCLAST128,
26699 IX86_BUILTIN_AESDEC128,
26700 IX86_BUILTIN_AESDECLAST128,
26701 IX86_BUILTIN_AESIMC128,
26702 IX86_BUILTIN_AESKEYGENASSIST128,
26704 /* PCLMUL instruction */
26705 IX86_BUILTIN_PCLMULQDQ128,
26707 /* AVX */
26708 IX86_BUILTIN_ADDPD256,
26709 IX86_BUILTIN_ADDPS256,
26710 IX86_BUILTIN_ADDSUBPD256,
26711 IX86_BUILTIN_ADDSUBPS256,
26712 IX86_BUILTIN_ANDPD256,
26713 IX86_BUILTIN_ANDPS256,
26714 IX86_BUILTIN_ANDNPD256,
26715 IX86_BUILTIN_ANDNPS256,
26716 IX86_BUILTIN_BLENDPD256,
26717 IX86_BUILTIN_BLENDPS256,
26718 IX86_BUILTIN_BLENDVPD256,
26719 IX86_BUILTIN_BLENDVPS256,
26720 IX86_BUILTIN_DIVPD256,
26721 IX86_BUILTIN_DIVPS256,
26722 IX86_BUILTIN_DPPS256,
26723 IX86_BUILTIN_HADDPD256,
26724 IX86_BUILTIN_HADDPS256,
26725 IX86_BUILTIN_HSUBPD256,
26726 IX86_BUILTIN_HSUBPS256,
26727 IX86_BUILTIN_MAXPD256,
26728 IX86_BUILTIN_MAXPS256,
26729 IX86_BUILTIN_MINPD256,
26730 IX86_BUILTIN_MINPS256,
26731 IX86_BUILTIN_MULPD256,
26732 IX86_BUILTIN_MULPS256,
26733 IX86_BUILTIN_ORPD256,
26734 IX86_BUILTIN_ORPS256,
26735 IX86_BUILTIN_SHUFPD256,
26736 IX86_BUILTIN_SHUFPS256,
26737 IX86_BUILTIN_SUBPD256,
26738 IX86_BUILTIN_SUBPS256,
26739 IX86_BUILTIN_XORPD256,
26740 IX86_BUILTIN_XORPS256,
26741 IX86_BUILTIN_CMPSD,
26742 IX86_BUILTIN_CMPSS,
26743 IX86_BUILTIN_CMPPD,
26744 IX86_BUILTIN_CMPPS,
26745 IX86_BUILTIN_CMPPD256,
26746 IX86_BUILTIN_CMPPS256,
26747 IX86_BUILTIN_CVTDQ2PD256,
26748 IX86_BUILTIN_CVTDQ2PS256,
26749 IX86_BUILTIN_CVTPD2PS256,
26750 IX86_BUILTIN_CVTPS2DQ256,
26751 IX86_BUILTIN_CVTPS2PD256,
26752 IX86_BUILTIN_CVTTPD2DQ256,
26753 IX86_BUILTIN_CVTPD2DQ256,
26754 IX86_BUILTIN_CVTTPS2DQ256,
26755 IX86_BUILTIN_EXTRACTF128PD256,
26756 IX86_BUILTIN_EXTRACTF128PS256,
26757 IX86_BUILTIN_EXTRACTF128SI256,
26758 IX86_BUILTIN_VZEROALL,
26759 IX86_BUILTIN_VZEROUPPER,
26760 IX86_BUILTIN_VPERMILVARPD,
26761 IX86_BUILTIN_VPERMILVARPS,
26762 IX86_BUILTIN_VPERMILVARPD256,
26763 IX86_BUILTIN_VPERMILVARPS256,
26764 IX86_BUILTIN_VPERMILPD,
26765 IX86_BUILTIN_VPERMILPS,
26766 IX86_BUILTIN_VPERMILPD256,
26767 IX86_BUILTIN_VPERMILPS256,
26768 IX86_BUILTIN_VPERMIL2PD,
26769 IX86_BUILTIN_VPERMIL2PS,
26770 IX86_BUILTIN_VPERMIL2PD256,
26771 IX86_BUILTIN_VPERMIL2PS256,
26772 IX86_BUILTIN_VPERM2F128PD256,
26773 IX86_BUILTIN_VPERM2F128PS256,
26774 IX86_BUILTIN_VPERM2F128SI256,
26775 IX86_BUILTIN_VBROADCASTSS,
26776 IX86_BUILTIN_VBROADCASTSD256,
26777 IX86_BUILTIN_VBROADCASTSS256,
26778 IX86_BUILTIN_VBROADCASTPD256,
26779 IX86_BUILTIN_VBROADCASTPS256,
26780 IX86_BUILTIN_VINSERTF128PD256,
26781 IX86_BUILTIN_VINSERTF128PS256,
26782 IX86_BUILTIN_VINSERTF128SI256,
26783 IX86_BUILTIN_LOADUPD256,
26784 IX86_BUILTIN_LOADUPS256,
26785 IX86_BUILTIN_STOREUPD256,
26786 IX86_BUILTIN_STOREUPS256,
26787 IX86_BUILTIN_LDDQU256,
26788 IX86_BUILTIN_MOVNTDQ256,
26789 IX86_BUILTIN_MOVNTPD256,
26790 IX86_BUILTIN_MOVNTPS256,
26791 IX86_BUILTIN_LOADDQU256,
26792 IX86_BUILTIN_STOREDQU256,
26793 IX86_BUILTIN_MASKLOADPD,
26794 IX86_BUILTIN_MASKLOADPS,
26795 IX86_BUILTIN_MASKSTOREPD,
26796 IX86_BUILTIN_MASKSTOREPS,
26797 IX86_BUILTIN_MASKLOADPD256,
26798 IX86_BUILTIN_MASKLOADPS256,
26799 IX86_BUILTIN_MASKSTOREPD256,
26800 IX86_BUILTIN_MASKSTOREPS256,
26801 IX86_BUILTIN_MOVSHDUP256,
26802 IX86_BUILTIN_MOVSLDUP256,
26803 IX86_BUILTIN_MOVDDUP256,
26805 IX86_BUILTIN_SQRTPD256,
26806 IX86_BUILTIN_SQRTPS256,
26807 IX86_BUILTIN_SQRTPS_NR256,
26808 IX86_BUILTIN_RSQRTPS256,
26809 IX86_BUILTIN_RSQRTPS_NR256,
26811 IX86_BUILTIN_RCPPS256,
26813 IX86_BUILTIN_ROUNDPD256,
26814 IX86_BUILTIN_ROUNDPS256,
26816 IX86_BUILTIN_FLOORPD256,
26817 IX86_BUILTIN_CEILPD256,
26818 IX86_BUILTIN_TRUNCPD256,
26819 IX86_BUILTIN_RINTPD256,
26820 IX86_BUILTIN_ROUNDPD_AZ256,
26822 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26823 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26824 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26826 IX86_BUILTIN_FLOORPS256,
26827 IX86_BUILTIN_CEILPS256,
26828 IX86_BUILTIN_TRUNCPS256,
26829 IX86_BUILTIN_RINTPS256,
26830 IX86_BUILTIN_ROUNDPS_AZ256,
26832 IX86_BUILTIN_FLOORPS_SFIX256,
26833 IX86_BUILTIN_CEILPS_SFIX256,
26834 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26836 IX86_BUILTIN_UNPCKHPD256,
26837 IX86_BUILTIN_UNPCKLPD256,
26838 IX86_BUILTIN_UNPCKHPS256,
26839 IX86_BUILTIN_UNPCKLPS256,
26841 IX86_BUILTIN_SI256_SI,
26842 IX86_BUILTIN_PS256_PS,
26843 IX86_BUILTIN_PD256_PD,
26844 IX86_BUILTIN_SI_SI256,
26845 IX86_BUILTIN_PS_PS256,
26846 IX86_BUILTIN_PD_PD256,
26848 IX86_BUILTIN_VTESTZPD,
26849 IX86_BUILTIN_VTESTCPD,
26850 IX86_BUILTIN_VTESTNZCPD,
26851 IX86_BUILTIN_VTESTZPS,
26852 IX86_BUILTIN_VTESTCPS,
26853 IX86_BUILTIN_VTESTNZCPS,
26854 IX86_BUILTIN_VTESTZPD256,
26855 IX86_BUILTIN_VTESTCPD256,
26856 IX86_BUILTIN_VTESTNZCPD256,
26857 IX86_BUILTIN_VTESTZPS256,
26858 IX86_BUILTIN_VTESTCPS256,
26859 IX86_BUILTIN_VTESTNZCPS256,
26860 IX86_BUILTIN_PTESTZ256,
26861 IX86_BUILTIN_PTESTC256,
26862 IX86_BUILTIN_PTESTNZC256,
26864 IX86_BUILTIN_MOVMSKPD256,
26865 IX86_BUILTIN_MOVMSKPS256,
26867 /* AVX2 */
26868 IX86_BUILTIN_MPSADBW256,
26869 IX86_BUILTIN_PABSB256,
26870 IX86_BUILTIN_PABSW256,
26871 IX86_BUILTIN_PABSD256,
26872 IX86_BUILTIN_PACKSSDW256,
26873 IX86_BUILTIN_PACKSSWB256,
26874 IX86_BUILTIN_PACKUSDW256,
26875 IX86_BUILTIN_PACKUSWB256,
26876 IX86_BUILTIN_PADDB256,
26877 IX86_BUILTIN_PADDW256,
26878 IX86_BUILTIN_PADDD256,
26879 IX86_BUILTIN_PADDQ256,
26880 IX86_BUILTIN_PADDSB256,
26881 IX86_BUILTIN_PADDSW256,
26882 IX86_BUILTIN_PADDUSB256,
26883 IX86_BUILTIN_PADDUSW256,
26884 IX86_BUILTIN_PALIGNR256,
26885 IX86_BUILTIN_AND256I,
26886 IX86_BUILTIN_ANDNOT256I,
26887 IX86_BUILTIN_PAVGB256,
26888 IX86_BUILTIN_PAVGW256,
26889 IX86_BUILTIN_PBLENDVB256,
26890 IX86_BUILTIN_PBLENDVW256,
26891 IX86_BUILTIN_PCMPEQB256,
26892 IX86_BUILTIN_PCMPEQW256,
26893 IX86_BUILTIN_PCMPEQD256,
26894 IX86_BUILTIN_PCMPEQQ256,
26895 IX86_BUILTIN_PCMPGTB256,
26896 IX86_BUILTIN_PCMPGTW256,
26897 IX86_BUILTIN_PCMPGTD256,
26898 IX86_BUILTIN_PCMPGTQ256,
26899 IX86_BUILTIN_PHADDW256,
26900 IX86_BUILTIN_PHADDD256,
26901 IX86_BUILTIN_PHADDSW256,
26902 IX86_BUILTIN_PHSUBW256,
26903 IX86_BUILTIN_PHSUBD256,
26904 IX86_BUILTIN_PHSUBSW256,
26905 IX86_BUILTIN_PMADDUBSW256,
26906 IX86_BUILTIN_PMADDWD256,
26907 IX86_BUILTIN_PMAXSB256,
26908 IX86_BUILTIN_PMAXSW256,
26909 IX86_BUILTIN_PMAXSD256,
26910 IX86_BUILTIN_PMAXUB256,
26911 IX86_BUILTIN_PMAXUW256,
26912 IX86_BUILTIN_PMAXUD256,
26913 IX86_BUILTIN_PMINSB256,
26914 IX86_BUILTIN_PMINSW256,
26915 IX86_BUILTIN_PMINSD256,
26916 IX86_BUILTIN_PMINUB256,
26917 IX86_BUILTIN_PMINUW256,
26918 IX86_BUILTIN_PMINUD256,
26919 IX86_BUILTIN_PMOVMSKB256,
26920 IX86_BUILTIN_PMOVSXBW256,
26921 IX86_BUILTIN_PMOVSXBD256,
26922 IX86_BUILTIN_PMOVSXBQ256,
26923 IX86_BUILTIN_PMOVSXWD256,
26924 IX86_BUILTIN_PMOVSXWQ256,
26925 IX86_BUILTIN_PMOVSXDQ256,
26926 IX86_BUILTIN_PMOVZXBW256,
26927 IX86_BUILTIN_PMOVZXBD256,
26928 IX86_BUILTIN_PMOVZXBQ256,
26929 IX86_BUILTIN_PMOVZXWD256,
26930 IX86_BUILTIN_PMOVZXWQ256,
26931 IX86_BUILTIN_PMOVZXDQ256,
26932 IX86_BUILTIN_PMULDQ256,
26933 IX86_BUILTIN_PMULHRSW256,
26934 IX86_BUILTIN_PMULHUW256,
26935 IX86_BUILTIN_PMULHW256,
26936 IX86_BUILTIN_PMULLW256,
26937 IX86_BUILTIN_PMULLD256,
26938 IX86_BUILTIN_PMULUDQ256,
26939 IX86_BUILTIN_POR256,
26940 IX86_BUILTIN_PSADBW256,
26941 IX86_BUILTIN_PSHUFB256,
26942 IX86_BUILTIN_PSHUFD256,
26943 IX86_BUILTIN_PSHUFHW256,
26944 IX86_BUILTIN_PSHUFLW256,
26945 IX86_BUILTIN_PSIGNB256,
26946 IX86_BUILTIN_PSIGNW256,
26947 IX86_BUILTIN_PSIGND256,
26948 IX86_BUILTIN_PSLLDQI256,
26949 IX86_BUILTIN_PSLLWI256,
26950 IX86_BUILTIN_PSLLW256,
26951 IX86_BUILTIN_PSLLDI256,
26952 IX86_BUILTIN_PSLLD256,
26953 IX86_BUILTIN_PSLLQI256,
26954 IX86_BUILTIN_PSLLQ256,
26955 IX86_BUILTIN_PSRAWI256,
26956 IX86_BUILTIN_PSRAW256,
26957 IX86_BUILTIN_PSRADI256,
26958 IX86_BUILTIN_PSRAD256,
26959 IX86_BUILTIN_PSRLDQI256,
26960 IX86_BUILTIN_PSRLWI256,
26961 IX86_BUILTIN_PSRLW256,
26962 IX86_BUILTIN_PSRLDI256,
26963 IX86_BUILTIN_PSRLD256,
26964 IX86_BUILTIN_PSRLQI256,
26965 IX86_BUILTIN_PSRLQ256,
26966 IX86_BUILTIN_PSUBB256,
26967 IX86_BUILTIN_PSUBW256,
26968 IX86_BUILTIN_PSUBD256,
26969 IX86_BUILTIN_PSUBQ256,
26970 IX86_BUILTIN_PSUBSB256,
26971 IX86_BUILTIN_PSUBSW256,
26972 IX86_BUILTIN_PSUBUSB256,
26973 IX86_BUILTIN_PSUBUSW256,
26974 IX86_BUILTIN_PUNPCKHBW256,
26975 IX86_BUILTIN_PUNPCKHWD256,
26976 IX86_BUILTIN_PUNPCKHDQ256,
26977 IX86_BUILTIN_PUNPCKHQDQ256,
26978 IX86_BUILTIN_PUNPCKLBW256,
26979 IX86_BUILTIN_PUNPCKLWD256,
26980 IX86_BUILTIN_PUNPCKLDQ256,
26981 IX86_BUILTIN_PUNPCKLQDQ256,
26982 IX86_BUILTIN_PXOR256,
26983 IX86_BUILTIN_MOVNTDQA256,
26984 IX86_BUILTIN_VBROADCASTSS_PS,
26985 IX86_BUILTIN_VBROADCASTSS_PS256,
26986 IX86_BUILTIN_VBROADCASTSD_PD256,
26987 IX86_BUILTIN_VBROADCASTSI256,
26988 IX86_BUILTIN_PBLENDD256,
26989 IX86_BUILTIN_PBLENDD128,
26990 IX86_BUILTIN_PBROADCASTB256,
26991 IX86_BUILTIN_PBROADCASTW256,
26992 IX86_BUILTIN_PBROADCASTD256,
26993 IX86_BUILTIN_PBROADCASTQ256,
26994 IX86_BUILTIN_PBROADCASTB128,
26995 IX86_BUILTIN_PBROADCASTW128,
26996 IX86_BUILTIN_PBROADCASTD128,
26997 IX86_BUILTIN_PBROADCASTQ128,
26998 IX86_BUILTIN_VPERMVARSI256,
26999 IX86_BUILTIN_VPERMDF256,
27000 IX86_BUILTIN_VPERMVARSF256,
27001 IX86_BUILTIN_VPERMDI256,
27002 IX86_BUILTIN_VPERMTI256,
27003 IX86_BUILTIN_VEXTRACT128I256,
27004 IX86_BUILTIN_VINSERT128I256,
27005 IX86_BUILTIN_MASKLOADD,
27006 IX86_BUILTIN_MASKLOADQ,
27007 IX86_BUILTIN_MASKLOADD256,
27008 IX86_BUILTIN_MASKLOADQ256,
27009 IX86_BUILTIN_MASKSTORED,
27010 IX86_BUILTIN_MASKSTOREQ,
27011 IX86_BUILTIN_MASKSTORED256,
27012 IX86_BUILTIN_MASKSTOREQ256,
27013 IX86_BUILTIN_PSLLVV4DI,
27014 IX86_BUILTIN_PSLLVV2DI,
27015 IX86_BUILTIN_PSLLVV8SI,
27016 IX86_BUILTIN_PSLLVV4SI,
27017 IX86_BUILTIN_PSRAVV8SI,
27018 IX86_BUILTIN_PSRAVV4SI,
27019 IX86_BUILTIN_PSRLVV4DI,
27020 IX86_BUILTIN_PSRLVV2DI,
27021 IX86_BUILTIN_PSRLVV8SI,
27022 IX86_BUILTIN_PSRLVV4SI,
27024 IX86_BUILTIN_GATHERSIV2DF,
27025 IX86_BUILTIN_GATHERSIV4DF,
27026 IX86_BUILTIN_GATHERDIV2DF,
27027 IX86_BUILTIN_GATHERDIV4DF,
27028 IX86_BUILTIN_GATHERSIV4SF,
27029 IX86_BUILTIN_GATHERSIV8SF,
27030 IX86_BUILTIN_GATHERDIV4SF,
27031 IX86_BUILTIN_GATHERDIV8SF,
27032 IX86_BUILTIN_GATHERSIV2DI,
27033 IX86_BUILTIN_GATHERSIV4DI,
27034 IX86_BUILTIN_GATHERDIV2DI,
27035 IX86_BUILTIN_GATHERDIV4DI,
27036 IX86_BUILTIN_GATHERSIV4SI,
27037 IX86_BUILTIN_GATHERSIV8SI,
27038 IX86_BUILTIN_GATHERDIV4SI,
27039 IX86_BUILTIN_GATHERDIV8SI,
27041 /* Alternate 4 element gather for the vectorizer where
27042 all operands are 32-byte wide. */
27043 IX86_BUILTIN_GATHERALTSIV4DF,
27044 IX86_BUILTIN_GATHERALTDIV8SF,
27045 IX86_BUILTIN_GATHERALTSIV4DI,
27046 IX86_BUILTIN_GATHERALTDIV8SI,
27048 /* TFmode support builtins. */
27049 IX86_BUILTIN_INFQ,
27050 IX86_BUILTIN_HUGE_VALQ,
27051 IX86_BUILTIN_FABSQ,
27052 IX86_BUILTIN_COPYSIGNQ,
27054 /* Vectorizer support builtins. */
27055 IX86_BUILTIN_CPYSGNPS,
27056 IX86_BUILTIN_CPYSGNPD,
27057 IX86_BUILTIN_CPYSGNPS256,
27058 IX86_BUILTIN_CPYSGNPD256,
27060 /* FMA4 instructions. */
27061 IX86_BUILTIN_VFMADDSS,
27062 IX86_BUILTIN_VFMADDSD,
27063 IX86_BUILTIN_VFMADDPS,
27064 IX86_BUILTIN_VFMADDPD,
27065 IX86_BUILTIN_VFMADDPS256,
27066 IX86_BUILTIN_VFMADDPD256,
27067 IX86_BUILTIN_VFMADDSUBPS,
27068 IX86_BUILTIN_VFMADDSUBPD,
27069 IX86_BUILTIN_VFMADDSUBPS256,
27070 IX86_BUILTIN_VFMADDSUBPD256,
27072 /* FMA3 instructions. */
27073 IX86_BUILTIN_VFMADDSS3,
27074 IX86_BUILTIN_VFMADDSD3,
27076 /* XOP instructions. */
27077 IX86_BUILTIN_VPCMOV,
27078 IX86_BUILTIN_VPCMOV_V2DI,
27079 IX86_BUILTIN_VPCMOV_V4SI,
27080 IX86_BUILTIN_VPCMOV_V8HI,
27081 IX86_BUILTIN_VPCMOV_V16QI,
27082 IX86_BUILTIN_VPCMOV_V4SF,
27083 IX86_BUILTIN_VPCMOV_V2DF,
27084 IX86_BUILTIN_VPCMOV256,
27085 IX86_BUILTIN_VPCMOV_V4DI256,
27086 IX86_BUILTIN_VPCMOV_V8SI256,
27087 IX86_BUILTIN_VPCMOV_V16HI256,
27088 IX86_BUILTIN_VPCMOV_V32QI256,
27089 IX86_BUILTIN_VPCMOV_V8SF256,
27090 IX86_BUILTIN_VPCMOV_V4DF256,
27092 IX86_BUILTIN_VPPERM,
27094 IX86_BUILTIN_VPMACSSWW,
27095 IX86_BUILTIN_VPMACSWW,
27096 IX86_BUILTIN_VPMACSSWD,
27097 IX86_BUILTIN_VPMACSWD,
27098 IX86_BUILTIN_VPMACSSDD,
27099 IX86_BUILTIN_VPMACSDD,
27100 IX86_BUILTIN_VPMACSSDQL,
27101 IX86_BUILTIN_VPMACSSDQH,
27102 IX86_BUILTIN_VPMACSDQL,
27103 IX86_BUILTIN_VPMACSDQH,
27104 IX86_BUILTIN_VPMADCSSWD,
27105 IX86_BUILTIN_VPMADCSWD,
27107 IX86_BUILTIN_VPHADDBW,
27108 IX86_BUILTIN_VPHADDBD,
27109 IX86_BUILTIN_VPHADDBQ,
27110 IX86_BUILTIN_VPHADDWD,
27111 IX86_BUILTIN_VPHADDWQ,
27112 IX86_BUILTIN_VPHADDDQ,
27113 IX86_BUILTIN_VPHADDUBW,
27114 IX86_BUILTIN_VPHADDUBD,
27115 IX86_BUILTIN_VPHADDUBQ,
27116 IX86_BUILTIN_VPHADDUWD,
27117 IX86_BUILTIN_VPHADDUWQ,
27118 IX86_BUILTIN_VPHADDUDQ,
27119 IX86_BUILTIN_VPHSUBBW,
27120 IX86_BUILTIN_VPHSUBWD,
27121 IX86_BUILTIN_VPHSUBDQ,
27123 IX86_BUILTIN_VPROTB,
27124 IX86_BUILTIN_VPROTW,
27125 IX86_BUILTIN_VPROTD,
27126 IX86_BUILTIN_VPROTQ,
27127 IX86_BUILTIN_VPROTB_IMM,
27128 IX86_BUILTIN_VPROTW_IMM,
27129 IX86_BUILTIN_VPROTD_IMM,
27130 IX86_BUILTIN_VPROTQ_IMM,
27132 IX86_BUILTIN_VPSHLB,
27133 IX86_BUILTIN_VPSHLW,
27134 IX86_BUILTIN_VPSHLD,
27135 IX86_BUILTIN_VPSHLQ,
27136 IX86_BUILTIN_VPSHAB,
27137 IX86_BUILTIN_VPSHAW,
27138 IX86_BUILTIN_VPSHAD,
27139 IX86_BUILTIN_VPSHAQ,
27141 IX86_BUILTIN_VFRCZSS,
27142 IX86_BUILTIN_VFRCZSD,
27143 IX86_BUILTIN_VFRCZPS,
27144 IX86_BUILTIN_VFRCZPD,
27145 IX86_BUILTIN_VFRCZPS256,
27146 IX86_BUILTIN_VFRCZPD256,
27148 IX86_BUILTIN_VPCOMEQUB,
27149 IX86_BUILTIN_VPCOMNEUB,
27150 IX86_BUILTIN_VPCOMLTUB,
27151 IX86_BUILTIN_VPCOMLEUB,
27152 IX86_BUILTIN_VPCOMGTUB,
27153 IX86_BUILTIN_VPCOMGEUB,
27154 IX86_BUILTIN_VPCOMFALSEUB,
27155 IX86_BUILTIN_VPCOMTRUEUB,
27157 IX86_BUILTIN_VPCOMEQUW,
27158 IX86_BUILTIN_VPCOMNEUW,
27159 IX86_BUILTIN_VPCOMLTUW,
27160 IX86_BUILTIN_VPCOMLEUW,
27161 IX86_BUILTIN_VPCOMGTUW,
27162 IX86_BUILTIN_VPCOMGEUW,
27163 IX86_BUILTIN_VPCOMFALSEUW,
27164 IX86_BUILTIN_VPCOMTRUEUW,
27166 IX86_BUILTIN_VPCOMEQUD,
27167 IX86_BUILTIN_VPCOMNEUD,
27168 IX86_BUILTIN_VPCOMLTUD,
27169 IX86_BUILTIN_VPCOMLEUD,
27170 IX86_BUILTIN_VPCOMGTUD,
27171 IX86_BUILTIN_VPCOMGEUD,
27172 IX86_BUILTIN_VPCOMFALSEUD,
27173 IX86_BUILTIN_VPCOMTRUEUD,
27175 IX86_BUILTIN_VPCOMEQUQ,
27176 IX86_BUILTIN_VPCOMNEUQ,
27177 IX86_BUILTIN_VPCOMLTUQ,
27178 IX86_BUILTIN_VPCOMLEUQ,
27179 IX86_BUILTIN_VPCOMGTUQ,
27180 IX86_BUILTIN_VPCOMGEUQ,
27181 IX86_BUILTIN_VPCOMFALSEUQ,
27182 IX86_BUILTIN_VPCOMTRUEUQ,
27184 IX86_BUILTIN_VPCOMEQB,
27185 IX86_BUILTIN_VPCOMNEB,
27186 IX86_BUILTIN_VPCOMLTB,
27187 IX86_BUILTIN_VPCOMLEB,
27188 IX86_BUILTIN_VPCOMGTB,
27189 IX86_BUILTIN_VPCOMGEB,
27190 IX86_BUILTIN_VPCOMFALSEB,
27191 IX86_BUILTIN_VPCOMTRUEB,
27193 IX86_BUILTIN_VPCOMEQW,
27194 IX86_BUILTIN_VPCOMNEW,
27195 IX86_BUILTIN_VPCOMLTW,
27196 IX86_BUILTIN_VPCOMLEW,
27197 IX86_BUILTIN_VPCOMGTW,
27198 IX86_BUILTIN_VPCOMGEW,
27199 IX86_BUILTIN_VPCOMFALSEW,
27200 IX86_BUILTIN_VPCOMTRUEW,
27202 IX86_BUILTIN_VPCOMEQD,
27203 IX86_BUILTIN_VPCOMNED,
27204 IX86_BUILTIN_VPCOMLTD,
27205 IX86_BUILTIN_VPCOMLED,
27206 IX86_BUILTIN_VPCOMGTD,
27207 IX86_BUILTIN_VPCOMGED,
27208 IX86_BUILTIN_VPCOMFALSED,
27209 IX86_BUILTIN_VPCOMTRUED,
27211 IX86_BUILTIN_VPCOMEQQ,
27212 IX86_BUILTIN_VPCOMNEQ,
27213 IX86_BUILTIN_VPCOMLTQ,
27214 IX86_BUILTIN_VPCOMLEQ,
27215 IX86_BUILTIN_VPCOMGTQ,
27216 IX86_BUILTIN_VPCOMGEQ,
27217 IX86_BUILTIN_VPCOMFALSEQ,
27218 IX86_BUILTIN_VPCOMTRUEQ,
27220 /* LWP instructions. */
27221 IX86_BUILTIN_LLWPCB,
27222 IX86_BUILTIN_SLWPCB,
27223 IX86_BUILTIN_LWPVAL32,
27224 IX86_BUILTIN_LWPVAL64,
27225 IX86_BUILTIN_LWPINS32,
27226 IX86_BUILTIN_LWPINS64,
27228 IX86_BUILTIN_CLZS,
27230 /* RTM */
27231 IX86_BUILTIN_XBEGIN,
27232 IX86_BUILTIN_XEND,
27233 IX86_BUILTIN_XABORT,
27234 IX86_BUILTIN_XTEST,
27236 /* BMI instructions. */
27237 IX86_BUILTIN_BEXTR32,
27238 IX86_BUILTIN_BEXTR64,
27239 IX86_BUILTIN_CTZS,
27241 /* TBM instructions. */
27242 IX86_BUILTIN_BEXTRI32,
27243 IX86_BUILTIN_BEXTRI64,
27245 /* BMI2 instructions. */
27246 IX86_BUILTIN_BZHI32,
27247 IX86_BUILTIN_BZHI64,
27248 IX86_BUILTIN_PDEP32,
27249 IX86_BUILTIN_PDEP64,
27250 IX86_BUILTIN_PEXT32,
27251 IX86_BUILTIN_PEXT64,
27253 /* ADX instructions. */
27254 IX86_BUILTIN_ADDCARRYX32,
27255 IX86_BUILTIN_ADDCARRYX64,
27257 /* FSGSBASE instructions. */
27258 IX86_BUILTIN_RDFSBASE32,
27259 IX86_BUILTIN_RDFSBASE64,
27260 IX86_BUILTIN_RDGSBASE32,
27261 IX86_BUILTIN_RDGSBASE64,
27262 IX86_BUILTIN_WRFSBASE32,
27263 IX86_BUILTIN_WRFSBASE64,
27264 IX86_BUILTIN_WRGSBASE32,
27265 IX86_BUILTIN_WRGSBASE64,
27267 /* RDRND instructions. */
27268 IX86_BUILTIN_RDRAND16_STEP,
27269 IX86_BUILTIN_RDRAND32_STEP,
27270 IX86_BUILTIN_RDRAND64_STEP,
27272 /* RDSEED instructions. */
27273 IX86_BUILTIN_RDSEED16_STEP,
27274 IX86_BUILTIN_RDSEED32_STEP,
27275 IX86_BUILTIN_RDSEED64_STEP,
27277 /* F16C instructions. */
27278 IX86_BUILTIN_CVTPH2PS,
27279 IX86_BUILTIN_CVTPH2PS256,
27280 IX86_BUILTIN_CVTPS2PH,
27281 IX86_BUILTIN_CVTPS2PH256,
27283 /* CFString built-in for darwin */
27284 IX86_BUILTIN_CFSTRING,
27286 /* Builtins to get CPU type and supported features. */
27287 IX86_BUILTIN_CPU_INIT,
27288 IX86_BUILTIN_CPU_IS,
27289 IX86_BUILTIN_CPU_SUPPORTS,
27291 IX86_BUILTIN_MAX
27292 };
27294 /* Table for the ix86 builtin decls. */
27297 /* Table of all of the builtin functions that are possible with different ISA's
27298 but are waiting to be built until a function is declared to use that
27299 ISA. */
27306 };
27311 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
27312 of which isa_flags to use in the ix86_builtins_isa array. Stores the
27313 function decl in the ix86_builtins array. Returns the function decl or
27314 NULL_TREE, if the builtin was not added.
27316 If the front end has a special hook for builtin functions, delay adding
27317 builtin functions that aren't in the current ISA until the ISA is changed
27318 with function specific optimization. Doing so, can save about 300K for the
27319 default compiler. When the builtin is expanded, check at that time whether
27320 it is valid.
27322 If the front end doesn't have a special hook, record all builtins, even if
27323 it isn't an instruction set in the current ISA in case the user uses
27324 function specific options for a different ISA, so that we don't get scope
27325 errors if a builtin is added in the middle of a function scope. */
27331 {
27335 {
27344 {
27350 }
27351 else
27352 {
27358 }
27359 }
27362 }
27364 /* Like def_builtin, but also marks the function decl "const". */
27369 {
27373 else
27377 }
27379 /* Add any new builtin functions for a given ISA that may not have been
27380 declared. This saves a bit of space compared to adding all of the
27381 declarations to the tree, even if we didn't use them. */
27383 static void
27385 {
27389 {
27392 {
27395 /* Don't define the builtin again. */
27401 NULL_TREE);
27406 }
27407 }
27408 }
27410 /* Bits for builtin_description.flag. */
27412 /* Set when we don't support the comparison natively, and should
27413 swap_comparison in order to support it. */
27414 #define BUILTIN_DESC_SWAP_OPERANDS 1
27416 struct builtin_description
27417 {
27424 };
27427 {
27428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
27429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
27430 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
27431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
27432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
27433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
27434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
27435 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
27436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
27437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
27438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
27439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
27440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
27441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
27442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
27443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
27444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
27445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
27446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
27447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
27448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
27449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
27450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
27451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
27452 };
27455 {
27456 /* SSE4.2 */
27457 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
27458 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
27459 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
27460 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
27461 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
27462 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
27463 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
27464 };
27467 {
27468 /* SSE4.2 */
27469 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
27470 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
27471 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
27472 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
27473 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
27474 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
27475 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
27476 };
27478 /* Special builtins with variable number of arguments. */
27480 {
27481 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
27482 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
27483 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
27485 /* MMX */
27486 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27488 /* 3DNow! */
27489 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27491 /* FXSR, XSAVE and XSAVEOPT */
27492 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
27493 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
27494 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27495 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27496 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27498 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27499 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27500 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27501 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27502 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27504 /* SSE */
27505 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27506 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27507 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27509 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27510 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27511 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27512 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27514 /* SSE or 3DNow!A */
27515 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27516 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
27518 /* SSE2 */
27519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
27523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
27525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
27526 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
27527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
27528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27533 /* SSE3 */
27534 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27536 /* SSE4.1 */
27537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
27539 /* SSE4A */
27540 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27541 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27543 /* AVX */
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
27562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
27566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
27572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
27574 /* AVX2 */
27575 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
27576 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
27577 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
27578 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
27579 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
27580 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
27581 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
27582 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
27583 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
27585 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
27586 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
27587 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
27588 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
27589 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
27590 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
27592 /* FSGSBASE */
27593 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27594 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27595 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27596 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27597 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27598 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27599 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27600 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27602 /* RTM */
27603 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27604 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
27605 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
27606 };
27608 /* Builtins with variable number of arguments. */
27610 {
27611 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
27612 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
27613 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
27614 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27615 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27616 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27617 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27619 /* MMX */
27620 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27621 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27622 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27623 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27624 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27625 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27627 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27628 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27629 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27630 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27631 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27632 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27634 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27637 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27639 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27642 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27644 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27646 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27649 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27651 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27653 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27654 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27656 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27658 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27659 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27660 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27662 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27664 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27668 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27669 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27671 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27678 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27680 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27681 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27683 /* 3DNow! */
27684 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27685 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27686 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27687 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27689 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27690 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27691 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27692 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27694 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27696 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27698 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27699 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27700 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27701 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27702 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27703 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27705 /* 3DNow!A */
27706 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27707 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27708 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27709 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27710 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27711 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27713 /* SSE */
27714 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27715 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27716 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27718 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27719 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27720 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27721 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27722 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27723 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27724 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27725 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27727 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27729 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27730 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27731 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27733 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27736 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27759 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27760 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27764 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27766 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27767 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27769 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27774 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27775 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27777 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27779 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27781 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27787 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27788 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27790 /* SSE MMX or 3Dnow!A */
27791 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27792 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27793 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27795 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27796 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27797 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27798 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27800 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27801 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27803 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27805 /* SSE2 */
27806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27812 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27824 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27825 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27829 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27831 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27832 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27833 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27834 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27862 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27866 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27868 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27869 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27871 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27874 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27875 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27877 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27879 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27880 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27881 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27882 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27883 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27884 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27885 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27886 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27897 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27898 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27900 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27902 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27903 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27915 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27916 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27917 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27920 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27921 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27922 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27923 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27924 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27925 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27926 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27927 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27929 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27933 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27937 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27942 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27947 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27948 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27949 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27950 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27951 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27952 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27954 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27955 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27956 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27957 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27958 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27959 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27960 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27962 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27963 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27964 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27965 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27975 /* SSE2 MMX */
27976 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27977 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27979 /* SSE3 */
27980 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27981 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27983 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27984 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27985 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27986 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27987 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27988 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27990 /* SSSE3 */
27991 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27992 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27993 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27994 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27995 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27996 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27998 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27999 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28000 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28001 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
28002 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28003 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28004 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28005 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28006 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28007 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
28008 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28009 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28010 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
28011 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
28012 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28013 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28014 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
28015 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
28016 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
28017 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
28018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28019 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
28020 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28021 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
28023 /* SSSE3. */
28024 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
28025 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
28027 /* SSE4.1 */
28028 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28029 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28030 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
28031 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
28032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28033 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28034 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28035 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
28036 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
28037 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
28039 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
28040 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
28041 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
28042 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
28043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
28044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
28045 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
28046 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
28047 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
28048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
28049 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
28050 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
28051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
28053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
28054 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
28056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
28060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28062 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
28063 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
28064 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28066 /* SSE4.1 */
28067 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
28068 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
28069 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28070 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28072 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
28073 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
28074 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
28075 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
28077 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
28078 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
28080 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
28081 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
28083 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
28084 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
28085 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
28086 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
28088 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
28089 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
28091 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
28092 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
28094 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
28095 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
28096 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
28098 /* SSE4.2 */
28099 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28100 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
28101 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
28102 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28103 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28105 /* SSE4A */
28106 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
28107 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
28108 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
28109 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28111 /* AES */
28112 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
28113 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
28115 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28116 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28117 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28118 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28120 /* PCLMUL */
28121 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
28123 /* AVX */
28124 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28125 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28128 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28129 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28132 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28138 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28139 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28140 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28141 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28142 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28143 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28144 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28145 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28146 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28147 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28148 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28149 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
28152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
28153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
28154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
28159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
28160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28165 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
28170 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
28171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
28172 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
28173 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
28174 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
28175 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
28177 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28179 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28180 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
28184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
28185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
28188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
28189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
28191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28195 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28197 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28199 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
28207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
28208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
28209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
28211 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28212 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28215 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
28218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
28219 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
28220 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
28222 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
28223 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
28225 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28226 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28230 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28231 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28234 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28235 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28236 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
28237 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
28238 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
28240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28241 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28242 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28243 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28244 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28245 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28246 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28247 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28248 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28249 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28250 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
28257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
28259 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28260 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28262 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28264 /* AVX2 */
28265 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
28266 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
28267 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
28268 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
28269 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28270 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28271 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28272 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28273 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28274 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28275 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28276 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28277 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28278 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28279 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28280 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28281 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
28282 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28283 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28284 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28285 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28286 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
28287 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
28288 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28289 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28290 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28291 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28292 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28293 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28294 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28295 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28296 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28297 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28298 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28299 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28300 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28301 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28302 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28303 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
28304 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28305 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28306 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28307 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28308 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28309 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28310 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28311 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28312 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28313 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28314 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28315 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28316 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
28317 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28318 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28319 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28320 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28321 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28322 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28323 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28324 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28325 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28326 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28327 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28328 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28329 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28330 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28331 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28332 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28333 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28334 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28335 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28336 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28337 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28338 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28339 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
28340 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28341 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28342 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28343 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28344 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28345 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28346 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28347 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28348 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28349 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28350 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28351 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28352 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28353 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28354 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28355 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28356 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28357 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28358 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28359 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28360 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28361 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28362 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28363 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28364 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28365 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28366 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28367 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28368 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28369 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28370 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28371 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28372 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28373 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28374 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28375 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28376 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28377 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28378 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28379 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28380 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
28381 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28382 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28383 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28384 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
28385 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28386 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
28387 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
28388 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28389 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28390 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
28391 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
28392 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
28393 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
28394 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28395 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28396 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28397 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
28398 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
28399 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
28400 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
28401 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28402 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28403 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28404 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28405 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28406 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28407 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28408 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28409 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28410 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28412 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28414 /* BMI */
28415 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28416 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28417 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28419 /* TBM */
28420 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28421 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28423 /* F16C */
28424 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
28425 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
28426 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
28427 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
28429 /* BMI2 */
28430 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28431 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28432 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28433 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28434 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28435 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28436 };
28438 /* FMA4 and XOP. */
28439 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
28440 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
28441 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
28442 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
28443 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
28444 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
28445 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
28446 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
28447 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
28448 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
28449 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
28450 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
28451 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
28452 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
28453 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
28454 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
28455 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
28456 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
28457 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
28458 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
28459 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
28460 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
28461 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
28462 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
28463 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
28464 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
28465 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
28466 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
28467 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
28468 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
28469 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
28470 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
28471 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
28472 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
28473 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
28474 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
28475 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
28476 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
28477 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
28478 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
28479 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
28480 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
28481 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
28482 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
28483 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
28484 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
28485 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
28486 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
28487 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
28488 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
28489 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
28490 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
28493 {
28534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
28535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
28536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
28537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
28538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
28539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
28540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
28542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
28545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
28546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
28547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
28548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
28550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
28552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
28567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
28568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
28569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
28570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
28571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
28572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
28573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
28575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
28576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
28577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
28579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
28580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
28582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
28583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
28584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
28585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
28586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
28587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
28589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
28606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
28609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
28610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
28611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
28613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
28614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
28617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28646 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28654 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28662 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28669 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28670 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28672 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28673 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28674 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28675 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28676 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28678 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28679 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28680 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28681 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28682 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28683 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28684 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28685 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28687 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28688 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28689 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28690 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28692 };
28693 \f
28694 /* TM vector builtins. */
28696 /* Reuse the existing x86-specific `struct builtin_description' cause
28697 we're lazy. Add casts to make them fit. */
28699 {
28700 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28701 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28702 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28703 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28704 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28705 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28706 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28708 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28709 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28710 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28711 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28712 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28713 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28714 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28716 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28717 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28718 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28719 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28720 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28721 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28722 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28724 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28725 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28726 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28727 };
28729 /* TM callbacks. */
28731 /* Return the builtin decl needed to load a vector of TYPE. */
28733 static tree
28735 {
28737 {
28739 {
28746 }
28747 }
28749 }
28751 /* Return the builtin decl needed to store a vector of TYPE. */
28753 static tree
28755 {
28757 {
28759 {
28766 }
28767 }
28769 }
28770 \f
28771 /* Initialize the transactional memory vector load/store builtins. */
28773 static void
28775 {
28779 tree decl;
28786 /* If there are no builtins defined, we must be compiling in a
28787 language without trans-mem support. */
28791 /* Use whatever attributes a normal TM load has. */
28795 /* Use whatever attributes a normal TM store has. */
28799 /* Use whatever attributes a normal TM log has. */
28807 {
28811 {
28819 {
28822 }
28824 {
28827 }
28828 else
28829 {
28832 }
28834 /* The builtin without the prefix for
28835 calling it directly. */
28837 attrs);
28838 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28839 set the TYPE_ATTRIBUTES. */
28843 }
28844 }
28845 }
28847 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28848 in the current target ISA to allow the user to compile particular modules
28849 with different target specific options that differ from the command line
28850 options. */
28851 static void
28853 {
28858 /* Add all special builtins with variable number of operands. */
28862 {
28868 }
28870 /* Add all builtins with variable number of operands. */
28874 {
28880 }
28882 /* pcmpestr[im] insns. */
28886 {
28889 else
28892 }
28894 /* pcmpistr[im] insns. */
28898 {
28901 else
28904 }
28906 /* comi/ucomi insns. */
28908 {
28911 else
28914 }
28916 /* SSE */
28922 /* SSE or 3DNow!A */
28925 IX86_BUILTIN_MASKMOVQ);
28927 /* SSE2 */
28936 /* SSE3. */
28942 /* AES */
28956 /* PCLMUL */
28960 /* RDRND */
28967 IX86_BUILTIN_RDRAND64_STEP);
28969 /* AVX2 */
28971 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28972 IX86_BUILTIN_GATHERSIV2DF);
28975 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28976 IX86_BUILTIN_GATHERSIV4DF);
28979 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28980 IX86_BUILTIN_GATHERDIV2DF);
28983 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28984 IX86_BUILTIN_GATHERDIV4DF);
28987 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28988 IX86_BUILTIN_GATHERSIV4SF);
28991 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28992 IX86_BUILTIN_GATHERSIV8SF);
28995 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28996 IX86_BUILTIN_GATHERDIV4SF);
28999 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
29000 IX86_BUILTIN_GATHERDIV8SF);
29003 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
29004 IX86_BUILTIN_GATHERSIV2DI);
29007 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
29008 IX86_BUILTIN_GATHERSIV4DI);
29011 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
29012 IX86_BUILTIN_GATHERDIV2DI);
29015 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
29016 IX86_BUILTIN_GATHERDIV4DI);
29019 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
29020 IX86_BUILTIN_GATHERSIV4SI);
29023 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
29024 IX86_BUILTIN_GATHERSIV8SI);
29027 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
29028 IX86_BUILTIN_GATHERDIV4SI);
29031 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
29032 IX86_BUILTIN_GATHERDIV8SI);
29035 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
29036 IX86_BUILTIN_GATHERALTSIV4DF);
29039 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
29040 IX86_BUILTIN_GATHERALTDIV8SF);
29043 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
29044 IX86_BUILTIN_GATHERALTSIV4DI);
29047 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
29048 IX86_BUILTIN_GATHERALTDIV8SI);
29050 /* RTM. */
29054 /* MMX access to the vec_init patterns. */
29059 V4HI_FTYPE_HI_HI_HI_HI,
29060 IX86_BUILTIN_VEC_INIT_V4HI);
29063 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
29064 IX86_BUILTIN_VEC_INIT_V8QI);
29066 /* Access to the vec_extract patterns. */
29088 /* Access to the vec_set patterns. */
29109 /* RDSEED */
29118 /* ADCX */
29123 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
29124 IX86_BUILTIN_ADDCARRYX64);
29126 /* Add FMA4 multi-arg argument instructions */
29128 {
29134 }
29135 }
29137 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
29138 to return a pointer to VERSION_DECL if the outcome of the expression
29139 formed by PREDICATE_CHAIN is true. This function will be called during
29140 version dispatch to decide which function version to execute. It returns
29141 the basic block at the end, to which more conditions can be added. */
29143 static basic_block
29146 {
29147 gimple return_stmt;
29149 gimple convert_stmt;
29150 gimple call_cond_stmt;
29151 gimple if_else_stmt;
29157 gimple_seq gseq;
29174 {
29182 }
29185 {
29200 else
29201 {
29202 gimple assign_stmt;
29203 /* Use MIN_EXPR to check if any integer is zero?.
29204 and_expr_var = min_expr <cond_var, and_expr_var> */
29212 }
29213 }
29216 integer_zero_node,
29246 }
29248 /* This parses the attribute arguments to target in DECL and determines
29249 the right builtin to use to match the platform specification.
29250 It returns the priority value for this version decl. If PREDICATE_LIST
29251 is not NULL, it stores the list of cpu features that need to be checked
29252 before dispatching this function. */
29254 static unsigned int
29256 {
29257 tree attrs;
29259 tree target_node;
29266 /* Priority of i386 features, greater value is higher priority. This is
29267 used to decide the order in which function dispatch must happen. For
29268 instance, a version specialized for SSE4.2 should be checked for dispatch
29269 before a version for SSE3, as SSE4.2 implies SSE3. */
29270 enum feature_priority
29271 {
29273 P_MMX,
29274 P_SSE,
29275 P_SSE2,
29276 P_SSE3,
29277 P_SSSE3,
29278 P_PROC_SSSE3,
29279 P_SSE4_a,
29280 P_PROC_SSE4_a,
29281 P_SSE4_1,
29282 P_SSE4_2,
29283 P_PROC_SSE4_2,
29284 P_POPCNT,
29285 P_AVX,
29286 P_AVX2,
29287 P_FMA,
29288 P_PROC_FMA
29289 };
29293 /* These are the target attribute strings for which a dispatcher is
29294 available, from fold_builtin_cpu. */
29296 static struct _feature_list
29297 {
29300 }
29302 {
29313 };
29316 static unsigned int NUM_FEATURES
29332 /* Return priority zero for default function. */
29336 /* Handle arch= if specified. For priority, set it to be 1 more than
29337 the best instruction set the processor can handle. For instance, if
29338 there is a version for atom and a version for ssse3 (the highest ISA
29339 priority for atom), the atom version must be checked for dispatch
29340 before the ssse3 version. */
29342 {
29352 {
29354 {
29379 }
29380 }
29385 {
29389 }
29392 {
29394 /* For a C string literal the length includes the trailing NULL. */
29397 predicate_chain);
29398 }
29399 }
29401 /* Process feature name. */
29408 {
29409 /* Do not process "arch=" */
29411 {
29414 }
29416 {
29418 {
29420 {
29425 predicate_chain);
29426 }
29427 /* Find the maximum priority feature. */
29432 }
29433 }
29435 {
29439 }
29441 }
29445 {
29448 attrs_str);
29450 }
29452 {
29455 }
29458 }
29460 /* This compares the priority of target features in function DECL1
29461 and DECL2. It returns positive value if DECL1 is higher priority,
29462 negative value if DECL2 is higher priority and 0 if they are the
29463 same. */
29465 static int
29467 {
29472 }
29474 /* V1 and V2 point to function versions with different priorities
29475 based on the target ISA. This function compares their priorities. */
29477 static int
29479 {
29481 {
29482 tree version_decl;
29483 tree predicate_chain;
29490 }
29492 /* This function generates the dispatch function for
29493 multi-versioned functions. DISPATCH_DECL is the function which will
29494 contain the dispatch logic. FNDECLS are the function choices for
29495 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
29496 in DISPATCH_DECL in which the dispatch code is generated. */
29498 static int
29502 {
29503 tree default_decl;
29504 gimple ifunc_cpu_init_stmt;
29505 gimple_seq gseq;
29507 tree ele;
29513 struct _function_version_info
29514 {
29515 tree version_decl;
29516 tree predicate_chain;
29524 /*fndecls_p is actually a vector. */
29527 /* At least one more version other than the default. */
29534 /* The first version in the vector is the default decl. */
29540 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
29541 constructors, so explicity call __builtin_cpu_init here. */
29552 {
29556 /* Get attribute string, parse it and find the right predicate decl.
29557 The predicate function could be a lengthy combination of many
29558 features, like arch-type and various isa-variants. */
29569 actual_versions++;
29570 }
29572 /* Sort the versions according to descending order of dispatch priority. The
29573 priority is based on the ISA. This is not a perfect solution. There
29574 could still be ambiguity. If more than one function version is suitable
29575 to execute, which one should be dispatched? In future, allow the user
29576 to specify a dispatch priority next to the version. */
29586 /* dispatch default version at the end. */
29592 }
29594 /* Comparator function to be used in qsort routine to sort attribute
29595 specification strings to "target". */
29597 static int
29599 {
29603 }
29605 /* ARGLIST is the argument to target attribute. This function tokenizes
29606 the comma separated arguments, sorts them and returns a string which
29607 is a unique identifier for the comma separated arguments. It also
29608 replaces non-identifier characters "=,-" with "_". */
29612 {
29613 tree arg;
29622 {
29627 argnum++;
29630 argnum++;
29631 }
29636 {
29642 }
29644 /* Replace "=,-" with "_". */
29657 {
29659 i++;
29661 }
29668 {
29673 }
29678 }
29680 /* This function changes the assembler name for functions that are
29681 versions. If DECL is a function version and has a "target"
29682 attribute, it appends the attribute string to its assembler name. */
29684 static tree
29686 {
29687 tree version_attr;
29695 "Function versions cannot be marked as gnu_inline,"
29704 /* target attribute string cannot be NULL. */
29708 version_string
29719 /* Allow assembler name to be modified if already set. */
29727 }
29729 /* This function returns true if FN1 and FN2 are versions of the same function,
29730 that is, the target strings of the function decls are different. This assumes
29731 that FN1 and FN2 have the same signature. */
29733 static bool
29735 {
29747 /* At least one function decl should have the target attribute specified. */
29751 /* Diagnose missing target attribute if one of the decls is already
29752 multi-versioned. */
29754 {
29756 {
29758 {
29763 }
29766 fn2);
29769 /* Prevent diagnosing of the same error multiple times. */
29774 }
29776 }
29781 /* The sorted target strings must be different for fn1 and fn2
29782 to be versions. */
29785 else
29792 }
29794 static tree
29796 {
29797 /* For function version, add the target suffix to the assembler name. */
29801 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29803 #endif
29806 }
29808 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29809 is true, append the full path name of the source file. */
29813 {
29821 /* Get a unique name that can be used globally without any chances
29822 of collision at link time. */
29832 /* Use '.' to concatenate names as it is demangler friendly. */
29835 suffix);
29836 else
29840 }
29842 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29844 /* Make a dispatcher declaration for the multi-versioned function DECL.
29845 Calls to DECL function will be replaced with calls to the dispatcher
29846 by the front-end. Return the decl created. */
29848 static tree
29850 {
29851 tree func_decl;
29871 /* Mark this func as external, the resolver will flip it again if
29872 it gets generated. */
29874 /* This will be of type IFUNCs have to be externally visible. */
29878 }
29880 #endif
29882 /* Returns true if decl is multi-versioned and DECL is the default function,
29883 that is it is not tagged with target specific optimization. */
29885 static bool
29887 {
29896 }
29898 /* Make a dispatcher declaration for the multi-versioned function DECL.
29899 Calls to DECL function will be replaced with calls to the dispatcher
29900 by the front-end. Returns the decl of the dispatcher function. */
29902 static tree
29904 {
29926 /* Find the default version and make it the first node. */
29928 /* Go to the beginning of the chain. */
29933 {
29938 }
29940 /* If there is no default node, just return NULL. */
29944 /* Make default info the first node. */
29946 {
29953 }
29957 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29959 {
29964 /* Right now, the dispatching is done via ifunc. */
29970 dispatcher_version_info
29975 /* Set the dispatcher for all the versions. */
29978 {
29981 }
29982 }
29983 else
29984 #endif
29985 {
29987 "multiversioning needs ifunc which is not supported "
29989 }
29992 }
29994 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29995 it to CHAIN. */
29997 static tree
29999 {
30000 tree attr_name;
30001 tree attr_arg_name;
30002 tree attr_args;
30003 tree attr;
30010 }
30012 /* Make the resolver function decl to dispatch the versions of
30013 a multi-versioned function, DEFAULT_DECL. Create an
30014 empty basic block in the resolver and store the pointer in
30015 EMPTY_BB. Return the decl of the resolver function. */
30017 static tree
30021 {
30026 /* IFUNC's have to be globally visible. So, if the default_decl is
30027 not, then the name of the IFUNC should be made unique. */
30031 /* Append the filename to the resolver function if the versions are
30032 not externally visible. This is because the resolver function has
30033 to be externally visible for the loader to find it. So, appending
30034 the filename will prevent conflicts with a resolver function from
30035 another module which is based on the same version name. */
30038 /* The resolver function should return a (void *). */
30049 /* IFUNC resolvers have to be externally visible. */
30053 /* Resolver is not external, body is generated. */
30063 {
30064 /* In this case, each translation unit with a call to this
30065 versioned function will put out a resolver. Ensure it
30066 is comdat to keep just one copy. */
30069 }
30070 /* Build result decl and add to function_decl. */
30086 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
30090 /* Create the alias for dispatch to resolver here. */
30091 /*cgraph_create_function_alias (dispatch_decl, decl);*/
30095 }
30097 /* Generate the dispatching code body to dispatch multi-versioned function
30098 DECL. The target hook is called to process the "target" attributes and
30099 provide the code to dispatch the right function at run-time. NODE points
30100 to the dispatcher decl whose body will be created. */
30102 static tree
30104 {
30105 tree resolver_decl;
30106 basic_block empty_bb;
30108 tree default_ver_decl;
30124 /* The first version in the chain corresponds to the default version. */
30127 /* node is going to be an alias, so remove the finalized bit. */
30141 {
30143 /* Check for virtual functions here again, as by this time it should
30144 have been determined if this function needs a vtable index or
30145 not. This happens for methods in derived classes that override
30146 virtual methods in base classes but are not explicitly marked as
30147 virtual. */
30152 }
30159 }
30160 /* This builds the processor_model struct type defined in
30161 libgcc/config/i386/cpuinfo.c */
30163 static tree
30165 {
30172 /* The first 3 fields are unsigned int. */
30174 {
30180 }
30182 /* The last field is an array of unsigned integers of size one. */
30193 }
30195 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
30197 static tree
30199 {
30200 tree new_decl;
30203 VAR_DECL,
30205 type);
30218 }
30220 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
30221 into an integer defined in libgcc/config/i386/cpuinfo.c */
30223 static tree
30225 {
30231 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
30232 enum processor_features
30233 {
30235 F_MMX,
30236 F_POPCNT,
30237 F_SSE,
30238 F_SSE2,
30239 F_SSE3,
30240 F_SSSE3,
30241 F_SSE4_1,
30242 F_SSE4_2,
30243 F_AVX,
30244 F_AVX2,
30245 F_MAX
30246 };
30248 /* These are the values for vendor types and cpu types and subtypes
30249 in cpuinfo.c. Cpu types and subtypes should be subtracted by
30250 the corresponding start value. */
30251 enum processor_model
30252 {
30254 M_AMD,
30255 M_CPU_TYPE_START,
30256 M_INTEL_ATOM,
30257 M_INTEL_CORE2,
30258 M_INTEL_COREI7,
30259 M_AMDFAM10H,
30260 M_AMDFAM15H,
30261 M_INTEL_SLM,
30262 M_CPU_SUBTYPE_START,
30263 M_INTEL_COREI7_NEHALEM,
30264 M_INTEL_COREI7_WESTMERE,
30265 M_INTEL_COREI7_SANDYBRIDGE,
30266 M_AMDFAM10H_BARCELONA,
30267 M_AMDFAM10H_SHANGHAI,
30268 M_AMDFAM10H_ISTANBUL,
30269 M_AMDFAM15H_BDVER1,
30270 M_AMDFAM15H_BDVER2,
30271 M_AMDFAM15H_BDVER3
30272 };
30274 static struct _arch_names_table
30275 {
30278 }
30280 {
30298 };
30300 static struct _isa_names_table
30301 {
30304 }
30306 {
30318 };
30332 {
30333 /* *args must be a expr that can contain other EXPRS leading to a
30334 STRING_CST. */
30336 {
30339 }
30341 }
30346 {
30347 tree ref;
30348 tree field;
30349 tree final;
30352 unsigned int NUM_ARCH_NAMES
30361 {
30365 }
30370 /* CPU types are stored in the next field. */
30373 {
30376 }
30378 /* CPU subtypes are stored in the next field. */
30380 {
30383 }
30385 /* Get the appropriate field in __cpu_model. */
30389 /* Check the value. */
30393 }
30395 {
30396 tree ref;
30397 tree array_elt;
30398 tree field;
30399 tree final;
30402 unsigned int NUM_ISA_NAMES
30411 {
30415 }
30418 /* Get the last field, which is __cpu_features. */
30422 /* Get the appropriate field: __cpu_model.__cpu_features */
30426 /* Access the 0th element of __cpu_features array. */
30431 /* Return __cpu_model.__cpu_features[0] & field_val */
30435 }
30437 }
30439 static tree
30442 {
30444 {
30449 {
30452 }
30453 }
30455 #ifdef SUBTARGET_FOLD_BUILTIN
30457 #endif
30460 }
30462 /* Make builtins to detect cpu type and features supported. NAME is
30463 the builtin name, CODE is the builtin code, and FTYPE is the function
30464 type of the builtin. */
30466 static void
30469 {
30470 tree decl;
30471 tree type;
30479 }
30481 /* Make builtins to get CPU type and features supported. The created
30482 builtins are :
30484 __builtin_cpu_init (), to detect cpu type and features,
30485 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
30486 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
30487 */
30489 static void
30491 {
30498 }
30500 /* Internal method for ix86_init_builtins. */
30502 static void
30504 {
30516 sysv_va_ref =
30519 fnvoid_va_end_ms =
30521 fnvoid_va_start_ms =
30523 fnvoid_va_end_sysv =
30525 fnvoid_va_start_sysv =
30527 NULL_TREE);
30528 fnvoid_va_copy_ms =
30530 NULL_TREE);
30531 fnvoid_va_copy_sysv =
30547 }
30549 static void
30551 {
30554 /* The __float80 type. */
30557 {
30558 /* The __float80 type. */
30563 }
30566 /* The __float128 type. */
30572 /* This macro is built by i386-builtin-types.awk. */
30573 DEFINE_BUILTIN_PRIMITIVE_TYPES;
30574 }
30576 static void
30578 {
30579 tree t;
30583 /* Builtins to get CPU type and features. */
30586 /* TFmode support builtins. */
30592 /* We will expand them to normal call if SSE isn't available since
30593 they are used by libgcc. */
30612 #ifdef SUBTARGET_INIT_BUILTINS
30613 SUBTARGET_INIT_BUILTINS;
30614 #endif
30615 }
30617 /* Return the ix86 builtin for CODE. */
30619 static tree
30621 {
30626 }
30628 /* Errors in the source file can cause expand_expr to return const0_rtx
30629 where we expect a vector. To avoid crashing, use one of the vector
30630 clear instructions. */
30631 static rtx
30633 {
30637 }
30639 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30641 static rtx
30643 {
30644 rtx pat;
30664 {
30668 }
30682 }
30684 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30686 static rtx
30690 {
30691 rtx pat;
30699 rtx op;
30706 {
30786 }
30796 {
30803 {
30805 {
30808 {
30826 xop_rotl:
30828 {
30831 gcc_checking_assert
30833 }
30834 else
30835 {
30836 gcc_checking_assert
30847 }
30851 }
30852 }
30853 }
30854 else
30855 {
30856 non_constant:
30860 /* If we aren't optimizing, only allow one memory operand to be
30861 generated. */
30863 num_memory++;
30871 }
30875 }
30878 {
30889 else
30890 {
30896 }
30909 }
30916 }
30918 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30919 insns with vec_merge. */
30921 static rtx
30923 rtx target)
30924 {
30925 rtx pat;
30952 }
30954 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30956 static rtx
30959 {
30960 rtx pat;
30965 rtx op2;
30976 /* Swap operands if we have a comparison that isn't available in
30977 hardware. */
30979 {
30984 }
31004 }
31006 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
31008 static rtx
31010 rtx target)
31011 {
31012 rtx pat;
31026 /* Swap operands if we have a comparison that isn't available in
31027 hardware. */
31029 {
31033 }
31054 const0_rtx)));
31057 }
31059 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
31061 static rtx
31063 rtx target)
31064 {
31065 rtx pat;
31090 }
31092 static rtx
31095 {
31096 rtx pat;
31101 rtx op2;
31128 }
31130 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
31132 static rtx
31134 rtx target)
31135 {
31136 rtx pat;
31169 const0_rtx)));
31172 }
31174 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
31176 static rtx
31179 {
31180 rtx pat;
31218 {
31221 }
31224 {
31233 }
31235 {
31244 }
31245 else
31246 {
31253 }
31261 {
31266 emit_insn
31270 FLAGS_REG),
31271 const0_rtx)));
31273 }
31274 else
31276 }
31279 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
31281 static rtx
31284 {
31285 rtx pat;
31313 {
31316 }
31319 {
31328 }
31330 {
31339 }
31340 else
31341 {
31348 }
31356 {
31361 emit_insn
31365 FLAGS_REG),
31366 const0_rtx)));
31368 }
31369 else
31371 }
31373 /* Subroutine of ix86_expand_builtin to take care of insns with
31374 variable number of operands. */
31376 static rtx
31379 {
31384 struct
31385 {
31386 rtx op;
31398 {
31677 }
31682 {
31685 }
31688 {
31695 }
31696 else
31697 {
31700 }
31703 {
31710 {
31711 /* SIMD shift insns take either an 8-bit immediate or
31712 register as count. But builtin functions take int as
31713 count. If count doesn't match, we put it in register. */
31715 {
31719 }
31720 }
31722 {
31725 {
31779 {
31782 {
31785 }
31791 }
31793 }
31794 }
31795 else
31796 {
31800 /* If we aren't optimizing, only allow one memory operand to
31801 be generated. */
31803 num_memory++;
31806 {
31809 }
31810 else
31811 {
31814 }
31815 }
31819 }
31822 {
31839 }
31846 }
31848 /* Subroutine of ix86_expand_builtin to take care of special insns
31849 with variable number of operands. */
31851 static rtx
31854 {
31855 tree arg;
31858 struct
31859 {
31860 rtx op;
31870 {
31918 /* Reserve memory operand for target. */
31949 /* Reserve memory operand for target. */
31963 }
31968 {
31973 {
31976 }
31977 else
31980 }
31981 else
31982 {
31989 }
31992 {
32001 {
32003 {
32009 else
32012 }
32013 }
32014 else
32015 {
32017 {
32018 /* This must be the memory operand. */
32023 }
32024 else
32025 {
32026 /* This must be register. */
32033 }
32034 }
32038 }
32041 {
32056 }
32062 }
32064 /* Return the integer constant in ARG. Constrain it to be in the range
32065 of the subparts of VEC_TYPE; issue an error if not. */
32067 static int
32069 {
32074 {
32077 }
32080 }
32082 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
32083 ix86_expand_vector_init. We DO have language-level syntax for this, in
32084 the form of (type){ init-list }. Except that since we can't place emms
32085 instructions from inside the compiler, we can't allow the use of MMX
32086 registers unless the user explicitly asks for it. So we do *not* define
32087 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
32088 we have builtins invoked by mmintrin.h that gives us license to emit
32089 these sorts of instructions. */
32091 static rtx
32093 {
32103 {
32106 }
32113 }
32115 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
32116 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
32117 had a language-level syntax for referencing vector elements. */
32119 static rtx
32121 {
32125 rtx op0;
32145 }
32147 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
32148 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
32149 a language-level syntax for referencing vector elements. */
32151 static rtx
32153 {
32177 /* OP0 is the source of these builtin functions and shouldn't be
32178 modified. Create a copy, use it and return it as target. */
32184 }
32186 /* Expand an expression EXP that calls a built-in function,
32187 with result going to TARGET if that's convenient
32188 (and in mode MODE if that's convenient).
32189 SUBTARGET may be used as the target for computing one of EXP's operands.
32190 IGNORE is nonzero if the value is to be ignored. */
32192 static rtx
32195 {
32205 /* For CPU builtins that can be folded, fold first and expand the fold. */
32207 {
32209 {
32210 /* Make it call __cpu_indicator_init in libgcc. */
32216 }
32219 {
32224 }
32225 }
32227 /* Determine whether the builtin function is available under the current ISA.
32228 Originally the builtin was not created if it wasn't applicable to the
32229 current ISA based on the command line switches. With function specific
32230 options, we need to check in the context of the function making the call
32231 whether it is supported. */
32234 {
32240 else
32241 {
32245 }
32247 }
32250 {
32254 ? CODE_FOR_mmx_maskmovq
32256 /* Note the arg order is different from the operand order. */
32357 {
32358 REAL_VALUE_TYPE inf;
32359 rtx tmp;
32371 }
32381 {
32387 insn = (TARGET_64BIT
32391 }
32393 {
32394 insn = (TARGET_64BIT
32398 }
32399 else
32400 {
32403 insn = (TARGET_64BIT
32411 {
32414 }
32416 }
32419 {
32420 /* mode is VOIDmode if __builtin_rd* has been called
32421 without lhs. */
32425 }
32428 {
32433 }
32443 {
32458 }
32464 {
32467 }
32487 {
32490 }
32496 {
32500 {
32521 }
32526 }
32527 else
32528 {
32530 {
32542 }
32544 }
32574 ? CODE_FOR_tbm_bextri_si
32577 {
32580 }
32581 else
32582 {
32591 }
32607 rdrand_step:
32614 {
32617 }
32623 /* Emit SImode conditional move. */
32625 {
32628 }
32631 else
32638 const0_rtx);
32657 rdseed_step:
32664 {
32667 }
32673 const0_rtx);
32691 addcarryx:
32699 /* Generate CF from input operand. */
32704 /* Gen ADCX instruction to compute X+Y+CF. */
32719 /* Store the result. */
32722 {
32725 }
32728 /* Return current CF value. */
32797 gather_gen:
32808 /* Note the arg order is different from the operand order. */
32817 else
32822 {
32828 }
32831 {
32836 else
32846 }
32848 /* Force memory operand only with base register here. But we
32849 don't want to do it on memory operand for other builtin
32850 functions. */
32862 {
32865 }
32867 /* Optimize. If mask is known to have all high bits set,
32868 replace op0 with pc_rtx to signal that the instruction
32869 overwrites the whole destination and doesn't use its
32870 previous contents. */
32872 {
32874 {
32877 {
32881 negative++;
32884 negative++;
32885 }
32888 }
32890 {
32891 /* Recognize also when mask is like:
32892 __v2df src = _mm_setzero_pd ();
32893 __v2df mask = _mm_cmpeq_pd (src, src);
32894 or
32895 __v8sf src = _mm256_setzero_ps ();
32896 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32897 as that is a cheaper way to load all ones into
32898 a register than having to load a constant from
32899 memory. */
32902 {
32907 {
32914 /* FALLTHRU */
32924 }
32925 }
32926 }
32927 }
32936 {
32943 else
32945 }
32946 else
32957 {
32960 }
32966 }
32979 {
32983 /* Emit a normal call if SSE isn't available. */
32987 }
33012 }
33014 /* Returns a function decl for a vectorized version of the builtin function
33015 with builtin function code FN and the result vector type TYPE, or NULL_TREE
33016 if it is not available. */
33018 static tree
33020 tree type_in)
33021 {
33037 {
33040 {
33045 }
33050 {
33055 }
33061 /* The round insn does not trap on denormals. */
33066 {
33071 }
33077 /* The round insn does not trap on denormals. */
33082 {
33087 }
33093 /* The round insn does not trap on denormals. */
33098 {
33103 }
33109 /* The round insn does not trap on denormals. */
33114 {
33119 }
33126 {
33131 }
33138 {
33143 }
33149 /* The round insn does not trap on denormals. */
33154 {
33159 }
33165 /* The round insn does not trap on denormals. */
33170 {
33175 }
33180 {
33185 }
33190 {
33195 }
33199 /* The round insn does not trap on denormals. */
33204 {
33209 }
33213 /* The round insn does not trap on denormals. */
33218 {
33223 }
33227 /* The round insn does not trap on denormals. */
33232 {
33237 }
33241 /* The round insn does not trap on denormals. */
33246 {
33251 }
33255 /* The round insn does not trap on denormals. */
33260 {
33265 }
33269 /* The round insn does not trap on denormals. */
33274 {
33279 }
33283 /* The round insn does not trap on denormals. */
33288 {
33293 }
33297 /* The round insn does not trap on denormals. */
33302 {
33307 }
33311 /* The round insn does not trap on denormals. */
33316 {
33321 }
33325 /* The round insn does not trap on denormals. */
33330 {
33335 }
33340 {
33345 }
33350 {
33355 }
33360 }
33362 /* Dispatch to a handler for a vectorization library. */
33365 type_in);
33368 }
33370 /* Handler for an SVML-style interface to
33371 a library with vectorized intrinsics. */
33373 static tree
33375 {
33383 /* The SVML is suitable for unsafe math only. */
33396 {
33443 }
33452 {
33455 }
33456 else
33459 /* Convert to uppercase. */
33464 args;
33466 arity++;
33470 else
33473 /* Build a function declaration for the vectorized function. */
33482 }
33484 /* Handler for an ACML-style interface to
33485 a library with vectorized intrinsics. */
33487 static tree
33489 {
33497 /* The ACML is 64bits only and suitable for unsafe math only as
33498 it does not correctly support parts of IEEE with the required
33499 precision such as denormals. */
33513 {
33543 }
33550 args;
33552 arity++;
33556 else
33559 /* Build a function declaration for the vectorized function. */
33568 }
33570 /* Returns a decl of a function that implements gather load with
33571 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
33572 Return NULL_TREE if it is not available. */
33574 static tree
33577 {
33593 /* v*gather* insn sign extends index to pointer mode. */
33605 {
33632 }
33635 }
33637 /* Returns a code for a target-specific builtin that implements
33638 reciprocal of the function, or NULL_TREE if not available. */
33640 static tree
33643 {
33650 /* Machine dependent builtins. */
33652 {
33653 /* Vectorized version of sqrt to rsqrt conversion. */
33662 }
33663 else
33664 /* Normal builtins. */
33666 {
33667 /* Sqrt to rsqrt conversion. */
33673 }
33674 }
33675 \f
33676 /* Helper for avx_vpermilps256_operand et al. This is also used by
33677 the expansion functions to turn the parallel back into a mask.
33678 The return value is 0 for no match and the imm8+1 for a match. */
33680 int
33682 {
33690 /* Validate that all of the elements are constants, and not totally
33691 out of range. Copy the data into an integral array to make the
33692 subsequent checks easier. */
33694 {
33704 }
33707 {
33709 /* In the 256-bit DFmode case, we can only move elements within
33710 a 128-bit lane. */
33712 {
33716 }
33718 {
33722 }
33726 /* In the 256-bit SFmode case, we have full freedom of movement
33727 within the low 128-bit lane, but the high 128-bit lane must
33728 mirror the exact same pattern. */
33733 /* FALLTHRU */
33737 /* In the 128-bit case, we've full freedom in the placement of
33738 the elements from the source operand. */
33745 }
33747 /* Make sure success has a non-zero value by adding one. */
33749 }
33751 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33752 the expansion functions to turn the parallel back into a mask.
33753 The return value is 0 for no match and the imm8+1 for a match. */
33755 int
33757 {
33765 /* Validate that all of the elements are constants, and not totally
33766 out of range. Copy the data into an integral array to make the
33767 subsequent checks easier. */
33769 {
33779 }
33781 /* Validate that the halves of the permute are halves. */
33789 /* Reconstruct the mask. */
33791 {
33797 }
33799 /* Make sure success has a non-zero value by adding one. */
33801 }
33802 \f
33803 /* Store OPERAND to the memory after reload is completed. This means
33804 that we can't easily use assign_stack_local. */
33805 rtx
33807 {
33808 rtx result;
33812 {
33815 stack_pointer_rtx,
33818 }
33820 {
33822 {
33826 /* FALLTHRU */
33832 stack_pointer_rtx)),
33833 operand));
33837 }
33839 }
33840 else
33841 {
33843 {
33845 {
33852 stack_pointer_rtx)),
33858 stack_pointer_rtx)),
33860 }
33863 /* Store HImodes as SImodes. */
33865 /* FALLTHRU */
33871 stack_pointer_rtx)),
33872 operand));
33876 }
33878 }
33880 }
33882 /* Free operand from the memory. */
33883 void
33885 {
33887 {
33892 else
33894 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33895 to pop or add instruction if registers are available. */
33899 }
33900 }
33902 /* Return a register priority for hard reg REGNO. */
33903 static int
33905 {
33906 /* ebp and r13 as the base always wants a displacement, r12 as the
33907 base always wants an index. So discourage their usage in an
33908 address. */
33913 /* New x86-64 int registers result in bigger code size. Discourage
33914 them. */
33917 /* New x86-64 SSE registers result in bigger code size. Discourage
33918 them. */
33921 /* Usage of AX register results in smaller code. Prefer it. */
33925 }
33927 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33929 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33930 QImode must go into class Q_REGS.
33931 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33932 movdf to do mem-to-mem moves through integer regs. */
33934 static reg_class_t
33936 {
33939 /* We're only allowed to return a subclass of CLASS. Many of the
33940 following checks fail for NO_REGS, so eliminate that early. */
33944 /* All classes can load zeros. */
33948 /* Force constants into memory if we are loading a (nonzero) constant into
33949 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
33950 instructions to load from a constant. */
33957 /* Prefer SSE regs only, if we can use them for math. */
33961 /* Floating-point constants need more complex checks. */
33963 {
33964 /* General regs can load everything. */
33968 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33969 zero above. We only want to wind up preferring 80387 registers if
33970 we plan on doing computation with them. */
33973 {
33974 /* Limit class to non-sse. */
33983 }
33986 }
33988 /* Generally when we see PLUS here, it's the function invariant
33989 (plus soft-fp const_int). Which can only be computed into general
33990 regs. */
33994 /* QImode constants are easy to load, but non-constant QImode data
33995 must go into Q_REGS. */
33997 {
34003 }
34006 }
34008 /* Discourage putting floating-point values in SSE registers unless
34009 SSE math is being used, and likewise for the 387 registers. */
34010 static reg_class_t
34012 {
34015 /* Restrict the output reload class to the register bank that we are doing
34016 math on. If we would like not to return a subset of CLASS, reject this
34017 alternative: if reload cannot do this, it will still use its choice. */
34023 {
34028 else
34030 }
34033 }
34035 static reg_class_t
34038 {
34039 /* Double-word spills from general registers to non-offsettable memory
34040 references (zero-extended addresses) require special handling. */
34046 {
34048 ? CODE_FOR_reload_noff_load
34050 /* Add the cost of moving address to a temporary. */
34054 }
34056 /* QImode spills from non-QI registers require
34057 intermediate register on 32bit targets. */
34063 {
34068 else
34074 /* Return Q_REGS if the operand is in memory. */
34077 }
34079 /* This condition handles corner case where an expression involving
34080 pointers gets vectorized. We're trying to use the address of a
34081 stack slot as a vector initializer.
34083 (set (reg:V2DI 74 [ vect_cst_.2 ])
34084 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
34086 Eventually frame gets turned into sp+offset like this:
34088 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
34089 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
34090 (const_int 392 [0x188]))))
34092 That later gets turned into:
34094 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
34095 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
34096 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
34098 We'll have the following reload recorded:
34100 Reload 0: reload_in (DI) =
34101 (plus:DI (reg/f:DI 7 sp)
34102 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
34103 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
34104 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
34105 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
34106 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
34107 reload_reg_rtx: (reg:V2DI 22 xmm1)
34109 Which isn't going to work since SSE instructions can't handle scalar
34110 additions. Returning GENERAL_REGS forces the addition into integer
34111 register and reload can handle subsequent reloads without problems. */
34119 }
34121 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
34123 static bool
34125 {
34127 {
34142 }
34145 }
34147 /* If we are copying between general and FP registers, we need a memory
34148 location. The same is true for SSE and MMX registers.
34150 To optimize register_move_cost performance, allow inline variant.
34152 The macro can't work reliably when one of the CLASSES is class containing
34153 registers from multiple units (SSE, MMX, integer). We avoid this by never
34154 combining those units in single alternative in the machine description.
34155 Ensure that this constraint holds to avoid unexpected surprises.
34157 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
34158 enforce these sanity checks. */
34163 {
34172 {
34175 }
34180 /* ??? This is a lie. We do have moves between mmx/general, and for
34181 mmx/sse2. But by saying we need secondary memory we discourage the
34182 register allocator from using the mmx registers unless needed. */
34187 {
34188 /* SSE1 doesn't have any direct moves from other classes. */
34192 /* If the target says that inter-unit moves are more expensive
34193 than moving through memory, then don't generate them. */
34198 /* Between SSE and general, we have moves no larger than word size. */
34201 }
34204 }
34206 bool
34209 {
34211 }
34213 /* Implement the TARGET_CLASS_MAX_NREGS hook.
34215 On the 80386, this is the size of MODE in words,
34216 except in the FP regs, where a single reg is always enough. */
34218 static unsigned char
34220 {
34222 {
34227 else
34229 }
34230 else
34231 {
34234 else
34236 }
34237 }
34239 /* Return true if the registers in CLASS cannot represent the change from
34240 modes FROM to TO. */
34242 bool
34245 {
34249 /* x87 registers can't do subreg at all, as all values are reformatted
34250 to extended precision. */
34255 {
34256 /* Vector registers do not support QI or HImode loads. If we don't
34257 disallow a change to these modes, reload will assume it's ok to
34258 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
34259 the vec_dupv4hi pattern. */
34263 /* Vector registers do not support subreg with nonzero offsets, which
34264 are otherwise valid for integer registers. Since we can't see
34265 whether we have a nonzero offset from here, prohibit all
34266 nonparadoxical subregs changing size. */
34269 }
34272 }
34274 /* Return the cost of moving data of mode M between a
34275 register and memory. A value of 2 is the default; this cost is
34276 relative to those in `REGISTER_MOVE_COST'.
34278 This function is used extensively by register_move_cost that is used to
34279 build tables at startup. Make it inline in this case.
34280 When IN is 2, return maximum of in and out move cost.
34282 If moving between registers and memory is more expensive than
34283 between two registers, you should define this macro to express the
34284 relative cost.
34286 Model also increased moving costs of QImode registers in non
34287 Q_REGS classes.
34288 */
34292 {
34295 {
34298 {
34310 }
34314 }
34316 {
34319 {
34331 }
34335 }
34337 {
34340 {
34349 }
34353 }
34355 {
34358 {
34364 else
34369 }
34370 else
34371 {
34376 else
34378 }
34385 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
34392 else
34396 }
34397 }
34399 static int
34402 {
34404 }
34407 /* Return the cost of moving data from a register in class CLASS1 to
34408 one in class CLASS2.
34410 It is not required that the cost always equal 2 when FROM is the same as TO;
34411 on some machines it is expensive to move between registers if they are not
34412 general registers. */
34414 static int
34416 reg_class_t class2_i)
34417 {
34421 /* In case we require secondary memory, compute cost of the store followed
34422 by load. In order to avoid bad register allocation choices, we need
34423 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
34426 {
34432 /* In case of copying from general_purpose_register we may emit multiple
34433 stores followed by single load causing memory size mismatch stall.
34434 Count this as arbitrarily high cost of 20. */
34439 /* In the case of FP/MMX moves, the registers actually overlap, and we
34440 have to switch modes in order to treat them differently. */
34446 }
34448 /* Moves between SSE/MMX and integer unit are expensive. */
34452 /* ??? By keeping returned value relatively high, we limit the number
34453 of moves between integer and MMX/SSE registers for all targets.
34454 Additionally, high value prevents problem with x86_modes_tieable_p(),
34455 where integer modes in MMX/SSE registers are not tieable
34456 because of missing QImode and HImode moves to, from or between
34457 MMX/SSE registers. */
34467 }
34469 /* Return TRUE if hard register REGNO can hold a value of machine-mode
34470 MODE. */
34472 bool
34474 {
34475 /* Flags and only flags can only hold CCmode values. */
34487 {
34488 /* We implement the move patterns for all vector modes into and
34489 out of SSE registers, even when no operation instructions
34490 are available. */
34492 /* For AVX-512 we allow, regardless of regno:
34493 - XI mode
34494 - any of 512-bit wide vector mode
34495 - any scalar mode. */
34502 /* xmm16-xmm31 are only available for AVX-512. */
34506 /* OImode move is available only when AVX is enabled. */
34513 }
34515 {
34516 /* We implement the move patterns for 3DNOW modes even in MMX mode,
34517 so if the register is available at all, then we can move data of
34518 the given mode into or out of it. */
34521 }
34524 {
34525 /* Take care for QImode values - they can be in non-QI regs,
34526 but then they do cause partial register stalls. */
34531 /* LRA checks if the hard register is OK for the given mode.
34532 QImode values can live in non-QI regs, so we allow all
34533 registers here. */
34537 }
34538 /* We handle both integer and floats in the general purpose registers. */
34545 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
34546 on to use that value in smaller contexts, this can easily force a
34547 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
34548 supporting DImode, allow it. */
34553 }
34555 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
34556 tieable integer mode. */
34558 static bool
34560 {
34562 {
34575 }
34576 }
34578 /* Return true if MODE1 is accessible in a register that can hold MODE2
34579 without copying. That is, all register classes that can hold MODE2
34580 can also hold MODE1. */
34582 bool
34584 {
34592 /* MODE2 being XFmode implies fp stack or general regs, which means we
34593 can tie any smaller floating point modes to it. Note that we do not
34594 tie this with TFmode. */
34598 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
34599 that we can tie it with SFmode. */
34603 /* If MODE2 is only appropriate for an SSE register, then tie with
34604 any other mode acceptable to SSE registers. */
34614 /* If MODE2 is appropriate for an MMX register, then tie
34615 with any other mode acceptable to MMX registers. */
34622 }
34624 /* Return the cost of moving between two registers of mode MODE. */
34626 static int
34628 {
34632 {
34664 }
34666 /* Return the cost of moving between two registers of mode MODE,
34667 assuming that the move will be in pieces of at most UNITS bytes. */
34669 }
34671 /* Compute a (partial) cost for rtx X. Return true if the complete
34672 cost has been computed, and false if subexpressions should be
34673 scanned. In either case, *TOTAL contains the cost result. */
34675 static bool
34678 {
34685 {
34689 {
34692 }
34704 && (!TARGET_64BIT
34709 else
34715 {
34718 }
34720 {
34730 }
34732 {
34735 {
34744 }
34745 }
34746 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34747 it'll probably end up. Add a penalty for size. */
34754 /* The zero extensions is often completely free on x86_64, so make
34755 it as cheap as possible. */
34761 else
34773 {
34776 {
34779 }
34782 {
34785 }
34786 }
34787 /* FALLTHRU */
34794 {
34795 /* ??? Should be SSE vector operation cost. */
34796 /* At least for published AMD latencies, this really is the same
34797 as the latency for a simple fpu operation like fabs. */
34798 /* V*QImode is emulated with 1-11 insns. */
34800 {
34803 {
34804 /* For XOP we use vpshab, which requires a broadcast of the
34805 value to the variable shift insn. For constants this
34806 means a V16Q const in mem; even when we can perform the
34807 shift with one insn set the cost to prefer paddb. */
34809 {
34814 }
34816 }
34820 }
34821 else
34823 }
34825 {
34827 {
34830 else
34832 }
34833 else
34834 {
34837 else
34839 }
34840 }
34841 else
34842 {
34847 {
34848 /* Return the cost after shift-and truncation. */
34851 }
34852 else
34854 }
34858 {
34859 rtx sub;
34864 /* ??? SSE scalar/vector cost should be used here. */
34865 /* ??? Bald assumption that fma has the same cost as fmul. */
34869 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34880 }
34884 {
34885 /* ??? SSE scalar cost should be used here. */
34888 }
34890 {
34893 }
34895 {
34896 /* ??? SSE vector cost should be used here. */
34899 }
34901 {
34902 /* V*QImode is emulated with 7-13 insns. */
34904 {
34911 }
34912 /* V*DImode is emulated with 5-8 insns. */
34914 {
34917 else
34919 }
34920 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34921 insns, including two PMULUDQ. */
34924 else
34927 }
34928 else
34929 {
34934 {
34937 nbits++;
34938 }
34939 else
34940 /* This is arbitrary. */
34943 /* Compute costs correctly for widening multiplication. */
34947 {
34954 {
34958 else
34960 }
34964 }
34972 }
34979 /* ??? SSE cost should be used here. */
34984 /* ??? SSE vector cost should be used here. */
34986 else
34993 {
34998 {
35001 {
35009 }
35010 }
35013 {
35016 {
35022 }
35023 }
35025 {
35033 }
35034 }
35035 /* FALLTHRU */
35039 {
35040 /* ??? SSE cost should be used here. */
35043 }
35045 {
35048 }
35050 {
35051 /* ??? SSE vector cost should be used here. */
35054 }
35055 /* FALLTHRU */
35062 {
35069 }
35070 /* FALLTHRU */
35074 {
35075 /* ??? SSE cost should be used here. */
35078 }
35080 {
35083 }
35085 {
35086 /* ??? SSE vector cost should be used here. */
35089 }
35090 /* FALLTHRU */
35094 {
35095 /* ??? Should be SSE vector operation cost. */
35096 /* At least for published AMD latencies, this really is the same
35097 as the latency for a simple fpu operation like fabs. */
35099 }
35102 else
35111 {
35112 /* This kind of construct is implemented using test[bwl].
35113 Treat it as if we had an AND. */
35118 }
35128 /* ??? SSE cost should be used here. */
35133 /* ??? SSE vector cost should be used here. */
35139 /* ??? SSE cost should be used here. */
35144 /* ??? SSE vector cost should be used here. */
35157 /* ??? Assume all of these vector manipulation patterns are
35158 recognizable. In which case they all pretty much have the
35159 same cost. */
35165 }
35166 }
35168 #if TARGET_MACHO
35172 /* Given a symbol name and its associated stub, write out the
35173 definition of the stub. */
35175 void
35177 {
35182 /* For 64-bit we shouldn't get here. */
35185 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
35202 else
35209 {
35211 }
35213 {
35214 /* PIC stub. */
35215 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35221 }
35222 else
35225 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
35226 it needs no stub-binding-helper. */
35233 {
35236 }
35237 else
35242 /* N.B. Keep the correspondence of these
35243 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
35244 old-pic/new-pic/non-pic stubs; altering this will break
35245 compatibility with existing dylibs. */
35247 {
35248 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35250 }
35251 else
35252 /* 16-byte -mdynamic-no-pic stub. */
35258 }
35261 /* Order the registers for register allocator. */
35263 void
35265 {
35269 /* First allocate the local general purpose registers. */
35274 /* Global general purpose registers. */
35279 /* x87 registers come first in case we are doing FP math
35280 using them. */
35285 /* SSE registers. */
35291 /* Extended REX SSE registers. */
35295 /* Mask register. */
35299 /* x87 registers. */
35307 /* Initialize the rest of array as we do not allocate some registers
35308 at all. */
35311 }
35313 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
35314 in struct attribute_spec handler. */
35315 static tree
35317 tree args,
35320 {
35325 {
35327 name);
35330 }
35332 {
35334 name);
35337 }
35339 {
35340 tree cst;
35344 {
35347 name);
35349 }
35352 {
35355 name);
35357 }
35360 }
35363 }
35365 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
35366 struct attribute_spec.handler. */
35367 static tree
35369 tree args ATTRIBUTE_UNUSED,
35371 {
35376 {
35378 name);
35381 }
35383 /* Can combine regparm with all attributes but fastcall. */
35385 {
35387 {
35389 }
35392 }
35394 {
35396 {
35398 }
35401 }
35404 }
35406 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
35407 struct attribute_spec.handler. */
35408 static tree
35410 tree args ATTRIBUTE_UNUSED,
35412 {
35415 {
35418 }
35419 else
35423 {
35425 name);
35427 }
35433 {
35435 name);
35437 }
35440 }
35442 static tree
35444 tree args ATTRIBUTE_UNUSED,
35446 {
35448 {
35450 name);
35452 }
35454 }
35456 static bool
35458 {
35462 }
35464 /* Returns an expression indicating where the this parameter is
35465 located on entry to the FUNCTION. */
35467 static rtx
35469 {
35475 {
35480 else
35483 }
35488 {
35495 {
35500 }
35501 else
35502 {
35505 {
35511 }
35512 }
35514 }
35518 }
35520 /* Determine whether x86_output_mi_thunk can succeed. */
35522 static bool
35524 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
35526 {
35527 /* 64-bit can handle anything. */
35531 /* For 32-bit, everything's fine if we have one free register. */
35535 /* Need a free register for vcall_offset. */
35539 /* Need a free register for GOT references. */
35543 /* Otherwise ok. */
35545 }
35547 /* Output the assembler code for a thunk function. THUNK_DECL is the
35548 declaration for the thunk function itself, FUNCTION is the decl for
35549 the target function. DELTA is an immediate constant offset to be
35550 added to THIS. If VCALL_OFFSET is nonzero, the word at
35551 *(*this + vcall_offset) should be added to THIS. */
35553 static void
35557 {
35564 else
35565 {
35571 else
35573 }
35577 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
35578 pull it in now and let DELTA benefit. */
35582 {
35583 /* Put the this parameter into %eax. */
35586 }
35587 else
35590 /* Adjust the this parameter by a fixed constant. */
35592 {
35597 {
35599 {
35603 }
35604 }
35607 }
35609 /* Adjust the this parameter by a value stored in the vtable. */
35611 {
35621 /* Adjust the this parameter. */
35625 {
35629 }
35636 vcall_mem));
35637 else
35639 }
35641 /* If necessary, drop THIS back to its stack slot. */
35647 {
35650 ;
35651 else
35652 {
35656 }
35657 }
35658 else
35659 {
35661 ;
35662 #if TARGET_MACHO
35664 {
35667 }
35669 else
35670 {
35677 }
35678 }
35680 /* Our sibling call patterns do not allow memories, because we have no
35681 predicate that can distinguish between frame and non-frame memory.
35682 For our purposes here, we can get away with (ab)using a jump pattern,
35683 because we're going to do no optimization. */
35686 else
35687 {
35693 {
35699 }
35705 }
35708 /* Emit just enough of rest_of_compilation to get the insns emitted.
35709 Note that use_thunk calls assemble_start_function et al. */
35715 }
35717 static void
35719 {
35721 #if TARGET_MACHO
35723 #endif
35730 }
35732 int
35734 {
35746 }
35748 /* Output assembler code to FILE to increment profiler label # LABELNO
35749 for profiling a function entry. */
35750 void
35752 {
35757 {
35758 #ifndef NO_PROFILE_COUNTERS
35760 #endif
35764 else
35766 }
35768 {
35769 #ifndef NO_PROFILE_COUNTERS
35772 #endif
35774 }
35775 else
35776 {
35777 #ifndef NO_PROFILE_COUNTERS
35780 #endif
35782 }
35783 }
35785 /* We don't have exact information about the insn sizes, but we may assume
35786 quite safely that we are informed about all 1 byte insns and memory
35787 address sizes. This is enough to eliminate unnecessary padding in
35788 99% of cases. */
35790 static int
35792 {
35798 /* Discard alignments we've emit and jump instructions. */
35803 /* Important case - calls are always 5 bytes.
35804 It is common to have many calls in the row. */
35813 /* For normal instructions we rely on get_attr_length being exact,
35814 with a few exceptions. */
35816 {
35820 {
35830 /* Otherwise trust get_attr_length. */
35832 }
35837 }
35840 else
35842 }
35844 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35846 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35847 window. */
35849 static void
35851 {
35856 /* Look for all minimal intervals of instructions containing 4 jumps.
35857 The intervals are bounded by START and INSN. NBYTES is the total
35858 size of instructions in the interval including INSN and not including
35859 START. When the NBYTES is smaller than 16 bytes, it is possible
35860 that the end of START and INSN ends up in the same 16byte page.
35862 The smallest offset in the page INSN can start is the case where START
35863 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35864 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35865 */
35867 {
35871 {
35877 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35878 already in the current 16 byte page, because otherwise
35879 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35880 bytes to reach 16 byte boundary. */
35888 {
35890 {
35894 else
35897 }
35898 }
35900 }
35908 njumps++;
35909 else
35913 {
35917 else
35920 }
35927 {
35934 }
35935 }
35936 }
35937 #endif
35939 /* AMD Athlon works faster
35940 when RET is not destination of conditional jump or directly preceded
35941 by other jump instruction. We avoid the penalty by inserting NOP just
35942 before the RET instructions in such cases. */
35943 static void
35945 {
35946 edge e;
35947 edge_iterator ei;
35950 {
35953 rtx prev;
35963 {
35964 edge e;
35965 edge_iterator ei;
35970 {
35973 }
35974 }
35976 {
35982 /* Empty functions get branch mispredict even when
35983 the jump destination is not visible to us. */
35986 }
35988 {
35991 }
35992 }
35993 }
35995 /* Count the minimum number of instructions in BB. Return 4 if the
35996 number of instructions >= 4. */
35998 static int
36000 {
36001 rtx insn;
36004 /* Count number of instructions in this block. Return 4 if the number
36005 of instructions >= 4. */
36007 {
36008 /* Only happen in exit blocks. */
36016 {
36017 insn_count++;
36020 }
36021 }
36024 }
36027 /* Count the minimum number of instructions in code path in BB.
36028 Return 4 if the number of instructions >= 4. */
36030 static int
36032 {
36033 edge e;
36034 edge_iterator ei;
36037 /* Only bother counting instructions along paths with no
36038 more than 2 basic blocks between entry and exit. Given
36039 that BB has an edge to exit, determine if a predecessor
36040 of BB has an edge from entry. If so, compute the number
36041 of instructions in the predecessor block. If there
36042 happen to be multiple such blocks, compute the minimum. */
36045 {
36046 edge prev_e;
36047 edge_iterator prev_ei;
36050 {
36053 }
36055 {
36057 {
36062 }
36063 }
36064 }
36070 }
36072 /* Pad short function to 4 instructions. */
36074 static void
36076 {
36077 edge e;
36078 edge_iterator ei;
36081 {
36084 {
36087 /* Pad short function. */
36089 {
36092 /* Find epilogue. */
36101 /* Two NOPs count as one instruction. */
36104 }
36105 }
36106 }
36107 }
36109 /* Fix up a Windows system unwinder issue. If an EH region falls through into
36110 the epilogue, the Windows system unwinder will apply epilogue logic and
36111 produce incorrect offsets. This can be avoided by adding a nop between
36112 the last insn that can throw and the first insn of the epilogue. */
36114 static void
36116 {
36117 edge e;
36118 edge_iterator ei;
36121 {
36124 /* Find the beginning of the epilogue. */
36131 /* We only care about preceding insns that can throw. */
36136 /* Do not separate calls from their debug information. */
36142 else
36146 }
36147 }
36149 /* Implement machine specific optimizations. We implement padding of returns
36150 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
36151 static void
36153 {
36154 /* We are freeing block_for_insn in the toplev to keep compatibility
36155 with old MDEP_REORGS that are not CFG based. Recompute it now. */
36162 {
36167 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
36170 #endif
36171 }
36172 }
36174 /* Return nonzero when QImode register that must be represented via REX prefix
36175 is used. */
36176 bool
36178 {
36186 }
36188 /* Return nonzero when P points to register encoded via REX prefix.
36189 Called via for_each_rtx. */
36190 static int
36192 {
36198 }
36200 /* Return true when INSN mentions register that must be encoded using REX
36201 prefix. */
36202 bool
36204 {
36207 }
36209 /* If profitable, negate (without causing overflow) integer constant
36210 of mode MODE at location LOC. Return true in this case. */
36211 bool
36213 {
36214 HOST_WIDE_INT val;
36220 {
36222 /* DImode x86_64 constants must fit in 32 bits. */
36235 }
36237 /* Avoid overflows. */
36243 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
36244 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
36247 {
36250 }
36253 }
36255 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
36256 optabs would emit if we didn't have TFmode patterns. */
36258 void
36260 {
36294 }
36295 \f
36296 /* AVX512F does support 64-byte integer vector operations,
36297 thus the longest vector we are faced with is V64QImode. */
36298 #define MAX_VECT_LEN 64
36300 struct expand_vec_perm_d
36301 {
36308 };
36314 /* Get a vector mode of the same size as the original but with elements
36315 twice as wide. This is only guaranteed to apply to integral vectors. */
36319 {
36320 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
36325 }
36327 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36328 with all elements equal to VAR. Return true if successful. */
36330 static bool
36333 {
36337 {
36342 /* FALLTHRU */
36352 {
36355 /* First attempt to recognize VAL as-is. */
36359 {
36360 rtx seq;
36361 /* If that fails, force VAL into a register. */
36372 }
36373 }
36380 {
36381 rtx x;
36388 }
36398 {
36402 permute:
36410 /* Extend to SImode using a paradoxical SUBREG. */
36414 /* Insert the SImode value as low element of a V4SImode vector. */
36422 }
36430 widen:
36431 /* Replicate the value once into the next wider mode and recurse. */
36432 {
36434 rtx x;
36450 }
36454 {
36463 }
36468 }
36469 }
36471 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36472 whose ONE_VAR element is VAR, and other elements are zero. Return true
36473 if successful. */
36475 static bool
36478 {
36480 rtx new_target;
36485 {
36487 /* For SSE4.1, we normally use vector set. But if the second
36488 element is zero and inter-unit moves are OK, we use movq
36489 instead. */
36491 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
36513 /* Use ix86_expand_vector_set in 64bit mode only. */
36518 }
36521 {
36526 }
36529 {
36534 /* FALLTHRU */
36549 else
36556 {
36557 /* We need to shuffle the value to the correct position, so
36558 create a new pseudo to store the intermediate result. */
36560 /* With SSE2, we can use the integer shuffle insns. */
36562 {
36564 const1_rtx,
36571 }
36573 /* Otherwise convert the intermediate result to V4SFmode and
36574 use the SSE1 shuffle instructions. */
36576 {
36579 }
36580 else
36584 const1_rtx,
36593 }
36608 widen:
36612 /* Zero extend the variable element to SImode and recurse. */
36625 }
36626 }
36628 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36629 consisting of the values in VALS. It is known that all elements
36630 except ONE_VAR are constants. Return true if successful. */
36632 static bool
36635 {
36645 {
36650 /* For the two element vectors, it's just as easy to use
36651 the general case. */
36655 /* Use ix86_expand_vector_set in 64bit mode only. */
36677 widen:
36678 /* There's no way to set one QImode entry easily. Combine
36679 the variable value with its adjacent constant value, and
36680 promote to an HImode set. */
36683 {
36688 }
36689 else
36690 {
36693 }
36707 }
36712 }
36714 /* A subroutine of ix86_expand_vector_init_general. Use vector
36715 concatenate to handle the most general case: all values variable,
36716 and none identical. */
36718 static void
36721 {
36724 rtvec v;
36728 {
36731 {
36764 }
36777 {
36792 }
36797 {
36808 }
36811 half:
36812 /* FIXME: We process inputs backward to help RA. PR 36222. */
36816 {
36821 }
36825 {
36828 {
36832 }
36835 }
36836 else
36842 }
36843 }
36845 /* A subroutine of ix86_expand_vector_init_general. Use vector
36846 interleave to handle the most general case: all values variable,
36847 and none identical. */
36849 static void
36852 {
36861 {
36882 }
36885 {
36886 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36890 /* Insert the SImode value as low element of V4SImode vector. */
36894 op0),
36896 const1_rtx);
36899 /* Cast the V4SImode vector back to a vector in orignal mode. */
36903 /* Load even elements into the second position. */
36907 const1_rtx));
36909 /* Cast vector to FIRST_IMODE vector. */
36912 }
36914 /* Interleave low FIRST_IMODE vectors. */
36916 {
36920 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36923 }
36925 /* Interleave low SECOND_IMODE vectors. */
36927 {
36930 {
36935 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36936 vector. */
36939 }
36942 /* FALLTHRU */
36949 /* Cast the SECOND_IMODE vector back to a vector on original
36950 mode. */
36957 }
36958 }
36960 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36961 all values variable, and none identical. */
36963 static void
36966 {
36972 {
36977 /* FALLTHRU */
37001 half:
37018 /* FALLTHRU */
37024 /* Don't use ix86_expand_vector_init_interleave if we can't
37025 move from GPR to SSE register directly. */
37041 }
37043 {
37055 {
37059 {
37065 else
37066 {
37071 }
37072 }
37075 }
37080 {
37086 }
37088 {
37094 }
37095 else
37097 }
37098 }
37100 /* Initialize vector TARGET via VALS. Suppress the use of MMX
37101 instructions unless MMX_OK is true. */
37103 void
37105 {
37112 rtx x;
37115 {
37125 }
37127 /* Constants are best loaded from the constant pool. */
37129 {
37132 }
37134 /* If all values are identical, broadcast the value. */
37140 /* Values where only one field is non-constant are best loaded from
37141 the pool and overwritten via move later. */
37143 {
37147 one_var))
37152 }
37155 }
37157 void
37159 {
37164 rtx tmp;
37166 = {
37173 };
37175 = {
37182 };
37186 {
37190 {
37195 else
37199 }
37211 else
37217 {
37220 /* For the two element vectors, we implement a VEC_CONCAT with
37221 the extraction of the other element. */
37228 else
37233 }
37242 {
37248 /* tmp = target = A B C D */
37250 /* target = A A B B */
37252 /* target = X A B B */
37254 /* target = A X C D */
37261 /* tmp = target = A B C D */
37263 /* tmp = X B C D */
37265 /* target = A B X D */
37272 /* tmp = target = A B C D */
37274 /* tmp = X B C D */
37276 /* target = A B X D */
37284 }
37292 /* Element 0 handled by vec_merge below. */
37294 {
37297 }
37300 {
37301 /* With SSE2, use integer shuffles to swap element 0 and ELT,
37302 store into element 0, then shuffle them back. */
37319 }
37320 else
37321 {
37322 /* For SSE1, we have to reuse the V4SF code. */
37325 }
37378 half:
37379 /* Compute offset. */
37385 /* Extract the half. */
37389 /* Put val in tmp at elt. */
37392 /* Put it back. */
37398 }
37401 {
37405 }
37406 else
37407 {
37416 }
37417 }
37419 void
37421 {
37425 rtx tmp;
37428 {
37433 /* FALLTHRU */
37446 {
37466 }
37478 {
37480 {
37500 }
37504 }
37505 else
37506 {
37507 /* For SSE1, we have to reuse the V4SF code. */
37511 }
37527 {
37531 else
37535 }
37540 {
37544 else
37548 }
37553 {
37557 else
37561 }
37566 {
37570 else
37574 }
37579 {
37583 else
37587 }
37592 {
37596 else
37600 }
37604 /* ??? Could extract the appropriate HImode element and shift. */
37607 }
37610 {
37614 /* Let the rtl optimizers know about the zero extension performed. */
37616 {
37619 }
37622 }
37623 else
37624 {
37631 }
37632 }
37634 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
37635 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
37636 The upper bits of DEST are undefined, though they shouldn't cause
37637 exceptions (some bits from src or all zeros are ok). */
37639 static void
37641 {
37642 rtx tem;
37644 {
37648 else
37666 else
37673 else
37684 const1_rtx);
37685 else
37692 }
37694 }
37696 /* Expand a vector reduction. FN is the binary pattern to reduce;
37697 DEST is the destination; IN is the input vector. */
37699 void
37701 {
37706 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37710 {
37713 }
37718 {
37723 else
37727 }
37728 }
37729 \f
37730 /* Target hook for scalar_mode_supported_p. */
37731 static bool
37733 {
37738 else
37740 }
37742 /* Implements target hook vector_mode_supported_p. */
37743 static bool
37745 {
37757 }
37759 /* Target hook for c_mode_for_suffix. */
37760 static enum machine_mode
37762 {
37769 }
37771 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37773 We do this in the new i386 backend to maintain source compatibility
37774 with the old cc0-based compiler. */
37776 static tree
37778 tree inputs ATTRIBUTE_UNUSED,
37779 tree clobbers)
37780 {
37782 clobbers);
37784 clobbers);
37786 }
37788 /* Implements target vector targetm.asm.encode_section_info. */
37790 static void ATTRIBUTE_UNUSED
37792 {
37799 }
37801 /* Worker function for REVERSE_CONDITION. */
37803 enum rtx_code
37805 {
37809 }
37811 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37812 to OPERANDS[0]. */
37816 {
37818 {
37821 {
37825 }
37829 }
37831 {
37835 else
37836 {
37837 /* There is no non-popping store to memory for XFmode.
37838 So if we need one, follow the store with a load. */
37841 else
37843 }
37844 }
37845 else
37847 }
37849 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37850 FP status register is set. */
37852 void
37854 {
37856 rtx temp;
37861 {
37866 }
37867 else
37868 {
37873 }
37877 pc_rtx);
37882 }
37884 /* Output code to perform a log1p XFmode calculation. */
37887 {
37893 rtx test;
37899 XFmode));
37913 }
37915 /* Emit code for round calculation. */
37917 {
37924 rtx insn;
37929 {
37941 }
37944 {
37965 }
37973 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37975 /* scratch = fxam(op1) */
37978 UNSPEC_FXAM)));
37979 /* e1 = fabs(op1) */
37982 /* e2 = e1 + 0.5 */
37987 /* res = floor(e2) */
37989 {
37994 }
37995 else
37999 {
38002 {
38009 UNSPEC_TRUNC_NOOP)));
38010 }
38026 }
38028 /* flags = signbit(a) */
38031 /* if (flags) then res = -res */
38035 pc_rtx);
38046 }
38048 /* Output code to perform a Newton-Rhapson approximation of a single precision
38049 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
38052 {
38060 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
38064 /* x0 = rcp(b) estimate */
38067 UNSPEC_RCP)));
38068 /* e0 = x0 * b */
38072 /* e0 = x0 * e0 */
38076 /* e1 = x0 + x0 */
38080 /* x1 = e1 - e0 */
38084 /* res = a * x1 */
38087 }
38089 /* Output code to perform a Newton-Rhapson approximation of a
38090 single precision floating point [reciprocal] square root. */
38094 {
38096 REAL_VALUE_TYPE r;
38111 {
38114 }
38116 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
38117 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
38121 /* x0 = rsqrt(a) estimate */
38124 UNSPEC_RSQRT)));
38126 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
38128 {
38140 }
38142 /* e0 = x0 * a */
38145 /* e1 = e0 * x0 */
38149 /* e2 = e1 - 3. */
38156 /* e3 = -.5 * x0 */
38159 else
38160 /* e3 = -.5 * e0 */
38163 /* ret = e2 * e3 */
38166 }
38168 #ifdef TARGET_SOLARIS
38169 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
38171 static void
38173 tree decl)
38174 {
38175 /* With Binutils 2.15, the "@unwind" marker must be specified on
38176 every occurrence of the ".eh_frame" section, not just the first
38177 one. */
38180 {
38184 }
38186 #ifndef USE_GAS
38188 {
38191 }
38192 #endif
38195 }
38198 /* Return the mangling of TYPE if it is an extended fundamental type. */
38202 {
38210 {
38212 /* __float128 is "g". */
38215 /* "long double" or __float80 is "e". */
38219 }
38220 }
38222 /* For 32-bit code we can save PIC register setup by using
38223 __stack_chk_fail_local hidden function instead of calling
38224 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
38225 register, so it is better to call __stack_chk_fail directly. */
38227 static tree ATTRIBUTE_UNUSED
38229 {
38230 return TARGET_64BIT
38233 }
38235 /* Select a format to encode pointers in exception handling data. CODE
38236 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
38237 true if the symbol may be affected by dynamic relocations.
38239 ??? All x86 object file formats are capable of representing this.
38240 After all, the relocation needed is the same as for the call insn.
38241 Whether or not a particular assembler allows us to enter such, I
38242 guess we'll have to see. */
38243 int
38245 {
38247 {
38254 }
38259 }
38260 \f
38261 /* Expand copysign from SIGN to the positive value ABS_VALUE
38262 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
38263 the sign-bit. */
38264 static void
38266 {
38270 {
38277 else
38282 {
38283 /* We need to generate a scalar mode mask in this case. */
38288 }
38289 }
38290 else
38296 }
38298 /* Expand fabs (OP0) and return a new rtx that holds the result. The
38299 mask for masking out the sign-bit is stored in *SMASK, if that is
38300 non-null. */
38301 static rtx
38303 {
38312 else
38316 {
38317 /* We need to generate a scalar mode mask in this case. */
38322 }
38330 }
38332 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
38333 swapping the operands if SWAP_OPERANDS is true. The expanded
38334 code is a forward jump to a newly created label in case the
38335 comparison is true. The generated label rtx is returned. */
38336 static rtx
38339 {
38344 {
38348 }
38361 }
38363 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
38364 using comparison code CODE. Operands are swapped for the comparison if
38365 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
38366 static rtx
38369 {
38375 {
38379 }
38386 }
38388 /* Generate and return a rtx of mode MODE for 2**n where n is the number
38389 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
38390 static rtx
38392 {
38393 REAL_VALUE_TYPE TWO52r;
38394 rtx TWO52;
38401 }
38403 /* Expand SSE sequence for computing lround from OP1 storing
38404 into OP0. */
38405 void
38407 {
38408 /* C code for the stuff we're doing below:
38409 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
38410 return (long)tmp;
38411 */
38415 rtx adj;
38417 /* load nextafter (0.5, 0.0) */
38422 /* adj = copysign (0.5, op1) */
38426 /* adj = op1 + adj */
38429 /* op0 = (imode)adj */
38431 }
38433 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
38434 into OPERAND0. */
38435 void
38437 {
38438 /* C code for the stuff we're doing below (for do_floor):
38439 xi = (long)op1;
38440 xi -= (double)xi > op1 ? 1 : 0;
38441 return xi;
38442 */
38447 /* reg = (long)op1 */
38451 /* freg = (double)reg */
38455 /* ireg = (freg > op1) ? ireg - 1 : ireg */
38466 }
38468 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
38469 result in OPERAND0. */
38470 void
38472 {
38473 /* C code for the stuff we're doing below:
38474 xa = fabs (operand1);
38475 if (!isless (xa, 2**52))
38476 return operand1;
38477 xa = xa + 2**52 - 2**52;
38478 return copysign (xa, operand1);
38479 */
38486 /* xa = abs (operand1) */
38489 /* if (!isless (xa, TWO52)) goto label; */
38502 }
38504 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38505 into OPERAND0. */
38506 void
38508 {
38509 /* C code for the stuff we expand below.
38510 double xa = fabs (x), x2;
38511 if (!isless (xa, TWO52))
38512 return x;
38513 xa = xa + TWO52 - TWO52;
38514 x2 = copysign (xa, x);
38515 Compensate. Floor:
38516 if (x2 > x)
38517 x2 -= 1;
38518 Compensate. Ceil:
38519 if (x2 < x)
38520 x2 -= -1;
38521 return x2;
38522 */
38528 /* Temporary for holding the result, initialized to the input
38529 operand to ease control flow. */
38533 /* xa = abs (operand1) */
38536 /* if (!isless (xa, TWO52)) goto label; */
38539 /* xa = xa + TWO52 - TWO52; */
38543 /* xa = copysign (xa, operand1) */
38546 /* generate 1.0 or -1.0 */
38551 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38555 /* We always need to subtract here to preserve signed zero. */
38564 }
38566 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38567 into OPERAND0. */
38568 void
38570 {
38571 /* C code for the stuff we expand below.
38572 double xa = fabs (x), x2;
38573 if (!isless (xa, TWO52))
38574 return x;
38575 x2 = (double)(long)x;
38576 Compensate. Floor:
38577 if (x2 > x)
38578 x2 -= 1;
38579 Compensate. Ceil:
38580 if (x2 < x)
38581 x2 += 1;
38582 if (HONOR_SIGNED_ZEROS (mode))
38583 return copysign (x2, x);
38584 return x2;
38585 */
38591 /* Temporary for holding the result, initialized to the input
38592 operand to ease control flow. */
38596 /* xa = abs (operand1) */
38599 /* if (!isless (xa, TWO52)) goto label; */
38602 /* xa = (double)(long)x */
38607 /* generate 1.0 */
38610 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38625 }
38627 /* Expand SSE sequence for computing round from OPERAND1 storing
38628 into OPERAND0. Sequence that works without relying on DImode truncation
38629 via cvttsd2siq that is only available on 64bit targets. */
38630 void
38632 {
38633 /* C code for the stuff we expand below.
38634 double xa = fabs (x), xa2, x2;
38635 if (!isless (xa, TWO52))
38636 return x;
38637 Using the absolute value and copying back sign makes
38638 -0.0 -> -0.0 correct.
38639 xa2 = xa + TWO52 - TWO52;
38640 Compensate.
38641 dxa = xa2 - xa;
38642 if (dxa <= -0.5)
38643 xa2 += 1;
38644 else if (dxa > 0.5)
38645 xa2 -= 1;
38646 x2 = copysign (xa2, x);
38647 return x2;
38648 */
38654 /* Temporary for holding the result, initialized to the input
38655 operand to ease control flow. */
38659 /* xa = abs (operand1) */
38662 /* if (!isless (xa, TWO52)) goto label; */
38665 /* xa2 = xa + TWO52 - TWO52; */
38669 /* dxa = xa2 - xa; */
38672 /* generate 0.5, 1.0 and -0.5 */
38678 /* Compensate. */
38680 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
38685 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
38691 /* res = copysign (xa2, operand1) */
38698 }
38700 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38701 into OPERAND0. */
38702 void
38704 {
38705 /* C code for SSE variant we expand below.
38706 double xa = fabs (x), x2;
38707 if (!isless (xa, TWO52))
38708 return x;
38709 x2 = (double)(long)x;
38710 if (HONOR_SIGNED_ZEROS (mode))
38711 return copysign (x2, x);
38712 return x2;
38713 */
38719 /* Temporary for holding the result, initialized to the input
38720 operand to ease control flow. */
38724 /* xa = abs (operand1) */
38727 /* if (!isless (xa, TWO52)) goto label; */
38730 /* x = (double)(long)x */
38742 }
38744 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38745 into OPERAND0. */
38746 void
38748 {
38752 /* C code for SSE variant we expand below.
38753 double xa = fabs (x), x2;
38754 if (!isless (xa, TWO52))
38755 return x;
38756 xa2 = xa + TWO52 - TWO52;
38757 Compensate:
38758 if (xa2 > xa)
38759 xa2 -= 1.0;
38760 x2 = copysign (xa2, x);
38761 return x2;
38762 */
38766 /* Temporary for holding the result, initialized to the input
38767 operand to ease control flow. */
38771 /* xa = abs (operand1) */
38774 /* if (!isless (xa, TWO52)) goto label; */
38777 /* res = xa + TWO52 - TWO52; */
38782 /* generate 1.0 */
38785 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38793 /* res = copysign (res, operand1) */
38800 }
38802 /* Expand SSE sequence for computing round from OPERAND1 storing
38803 into OPERAND0. */
38804 void
38806 {
38807 /* C code for the stuff we're doing below:
38808 double xa = fabs (x);
38809 if (!isless (xa, TWO52))
38810 return x;
38811 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38812 return copysign (xa, x);
38813 */
38819 /* Temporary for holding the result, initialized to the input
38820 operand to ease control flow. */
38828 /* load nextafter (0.5, 0.0) */
38833 /* xa = xa + 0.5 */
38837 /* xa = (double)(int64_t)xa */
38842 /* res = copysign (xa, operand1) */
38849 }
38851 /* Expand SSE sequence for computing round
38852 from OP1 storing into OP0 using sse4 round insn. */
38853 void
38855 {
38864 {
38875 }
38877 /* round (a) = trunc (a + copysign (0.5, a)) */
38879 /* load nextafter (0.5, 0.0) */
38885 /* e1 = copysign (0.5, op1) */
38889 /* e2 = op1 + e1 */
38892 /* res = trunc (e2) */
38897 }
38898 \f
38900 /* Table of valid machine attributes. */
38902 {
38903 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38904 affects_type_identity } */
38905 /* Stdcall attribute says callee is responsible for popping arguments
38906 if they are not variable. */
38909 /* Fastcall attribute says callee is responsible for popping arguments
38910 if they are not variable. */
38913 /* Thiscall attribute says callee is responsible for popping arguments
38914 if they are not variable. */
38917 /* Cdecl attribute says the callee is a normal C declaration */
38920 /* Regparm attribute specifies how many integer arguments are to be
38921 passed in registers. */
38924 /* Sseregparm attribute says we are using x86_64 calling conventions
38925 for FP arguments. */
38928 /* The transactional memory builtins are implicitly regparm or fastcall
38929 depending on the ABI. Override the generic do-nothing attribute that
38930 these builtins were declared with. */
38933 /* force_align_arg_pointer says this function realigns the stack at entry. */
38936 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38941 #endif
38946 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38947 SUBTARGET_ATTRIBUTE_TABLE,
38948 #endif
38949 /* ms_abi and sysv_abi calling convention function attributes. */
38956 /* End element. */
38958 };
38960 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38961 static int
38963 tree vectype,
38965 {
38969 {
39014 }
39015 }
39017 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
39018 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
39019 insn every time. */
39023 /* Initialize vselect_insn. */
39025 static void
39027 {
39029 rtx x;
39040 }
39042 /* Construct (set target (vec_select op0 (parallel perm))) and
39043 return true if that's a valid instruction in the active ISA. */
39045 static bool
39048 {
39074 }
39076 /* Similar, but generate a vec_concat from op0 and op1 as well. */
39078 static bool
39082 {
39084 rtx x;
39099 }
39101 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39102 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
39104 static bool
39106 {
39115 ;
39117 ;
39119 ;
39120 else
39123 /* This is a blend, not a permute. Elements must stay in their
39124 respective lanes. */
39126 {
39130 }
39135 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
39136 decision should be extracted elsewhere, so that we only try that
39137 sequence once all budget==3 options have been tried. */
39144 {
39168 /* See if bytes move in pairs so we can use pblendw with
39169 an immediate argument, rather than pblendvb with a vector
39170 argument. */
39173 {
39174 use_pblendvb:
39178 finish_pblendvb:
39184 else
39187 }
39192 /* FALLTHRU */
39194 do_subreg:
39201 /* See if bytes move in pairs. If not, vpblendvb must be used. */
39205 /* See if bytes move in quadruplets. If yes, vpblendd
39206 with immediate can be used. */
39211 {
39212 /* See if bytes move the same in both lanes. If yes,
39213 vpblendw with immediate can be used. */
39218 /* Use vpblendw. */
39223 }
39225 /* Use vpblendd. */
39232 /* See if words move in pairs. If yes, vpblendd can be used. */
39237 {
39238 /* See if words move the same in both lanes. If not,
39239 vpblendvb must be used. */
39242 {
39243 /* Use vpblendvb. */
39253 }
39255 /* Use vpblendw. */
39259 }
39261 /* Use vpblendd. */
39268 /* Use vpblendd. */
39276 }
39278 /* This matches five different patterns with the different modes. */
39284 }
39286 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39287 in terms of the variable form of vpermilps.
39289 Note that we will have already failed the immediate input vpermilps,
39290 which requires that the high and low part shuffle be identical; the
39291 variable form doesn't require that. */
39293 static bool
39295 {
39302 /* We can only permute within the 128-bit lane. */
39304 {
39308 }
39314 {
39317 /* Within each 128-bit lane, the elements of op0 are numbered
39318 from 0 and the elements of op1 are numbered from 4. */
39325 }
39332 }
39334 /* Return true if permutation D can be performed as VMODE permutation
39335 instead. */
39337 static bool
39339 {
39354 else
39360 }
39362 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39363 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
39365 static bool
39367 {
39376 {
39378 {
39381 {
39385 /* Use vperm2i128 insn. The pattern uses
39386 V4DImode instead of V2TImode. */
39395 }
39397 }
39398 }
39399 else
39400 {
39402 {
39405 }
39407 {
39411 /* V4DImode should be already handled through
39412 expand_vselect by vpermq instruction. */
39419 {
39420 /* First see if vpermq can be used for
39421 V8SImode/V16HImode/V32QImode. */
39423 {
39431 }
39433 /* Next see if vpermd can be used. */
39436 }
39437 /* Or if vpermps can be used. */
39442 {
39443 /* vpshufb only works intra lanes, it is not
39444 possible to shuffle bytes in between the lanes. */
39448 }
39449 }
39450 else
39452 }
39460 else
39461 {
39467 else
39471 {
39475 }
39476 }
39485 {
39492 else
39494 }
39495 else
39496 {
39499 }
39502 }
39504 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
39505 in a single instruction. */
39507 static bool
39509 {
39513 /* Check plain VEC_SELECT first, because AVX has instructions that could
39514 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
39515 input where SEL+CONCAT may not. */
39517 {
39523 {
39529 }
39532 {
39536 }
39538 {
39539 /* Use vpbroadcast{b,w,d}. */
39542 {
39561 /* For other modes prefer other shuffles this function creates. */
39563 }
39565 {
39569 }
39570 }
39575 /* There are plenty of patterns in sse.md that are written for
39576 SEL+CONCAT and are not replicated for a single op. Perhaps
39577 that should be changed, to avoid the nastiness here. */
39579 /* Recognize interleave style patterns, which means incrementing
39580 every other permutation operand. */
39582 {
39585 }
39590 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
39592 {
39594 {
39599 }
39604 }
39605 }
39607 /* Finally, try the fully general two operand permute. */
39612 /* Recognize interleave style patterns with reversed operands. */
39614 {
39616 {
39620 else
39623 }
39628 }
39630 /* Try the SSE4.1 blend variable merge instructions. */
39634 /* Try one of the AVX vpermil variable permutations. */
39638 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
39639 vpshufb, vpermd, vpermps or vpermq variable permutation. */
39644 }
39646 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39647 in terms of a pair of pshuflw + pshufhw instructions. */
39649 static bool
39651 {
39659 /* The two permutations only operate in 64-bit lanes. */
39670 /* Emit the pshuflw. */
39677 /* Emit the pshufhw. */
39685 }
39687 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39688 the permutation using the SSSE3 palignr instruction. This succeeds
39689 when all of the elements in PERM fit within one vector and we merely
39690 need to shift them down so that a single vector permutation has a
39691 chance to succeed. */
39693 static bool
39695 {
39699 rtx shift;
39701 /* Even with AVX, palignr only operates on 128-bit vectors. */
39707 {
39713 }
39717 /* Given that we have SSSE3, we know we'll be able to implement the
39718 single operand permutation after the palignr with pshufb. */
39732 {
39737 }
39739 /* Test for the degenerate case where the alignment by itself
39740 produces the desired permutation. */
39748 }
39752 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39753 a two vector permutation into a single vector permutation by using
39754 an interleave operation to merge the vectors. */
39756 static bool
39758 {
39763 rtx seq;
39767 {
39770 }
39772 {
39775 /* For 32-byte modes allow even d->one_operand_p.
39776 The lack of cross-lane shuffling in some instructions
39777 might prevent a single insn shuffle. */
39780 /* If expand_vec_perm_interleave3 can expand this into
39781 a 3 insn sequence, give up and let it be expanded as
39782 3 insn sequence. While that is one insn longer,
39783 it doesn't need a memory operand and in the common
39784 case that both interleave low and high permutations
39785 with the same operands are adjacent needs 4 insns
39786 for both after CSE. */
39789 }
39790 else
39793 /* Examine from whence the elements come. */
39802 {
39805 /* Split the two input vectors into 4 halves. */
39811 /* If the elements from the low halves use interleave low, and similarly
39812 for interleave high. If the elements are from mis-matched halves, we
39813 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39815 {
39816 /* punpckl* */
39818 {
39823 }
39826 }
39828 {
39829 /* punpckh* */
39831 {
39836 }
39839 }
39841 {
39842 /* shufps */
39844 {
39849 }
39851 {
39852 /* shufpd */
39857 }
39858 }
39860 {
39861 /* shufps */
39863 {
39868 }
39870 {
39871 /* shufpd */
39876 }
39877 }
39878 else
39880 }
39881 else
39882 {
39887 /* Split the two input vectors into 8 quarters. */
39893 {
39896 }
39899 {
39903 }
39905 {
39908 }
39911 {
39913 {
39914 /* Attempt to increase the likelihood that dfinal
39915 shuffle will be intra-lane. */
39919 }
39921 /* vperm2f128 or vperm2i128. */
39923 {
39928 }
39933 {
39937 {
39940 }
39941 }
39942 }
39947 {
39948 /* vpunpckl* */
39950 {
39959 }
39960 }
39963 {
39964 /* vpunpckh* */
39966 {
39975 }
39976 }
39977 else
39979 }
39981 /* Use the remapping array set up above to move the elements from their
39982 swizzled locations into their final destinations. */
39985 {
39988 /* If same_halves is true, both halves of the remapped vector are the
39989 same. Avoid cross-lane accesses if possible. */
39991 {
39994 }
39995 else
39997 }
40003 /* Test if the final remap can be done with a single insn. For V4SFmode or
40004 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
40017 {
40021 }
40028 }
40030 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
40031 a single vector cross-lane permutation into vpermq followed
40032 by any of the single insn permutations. */
40034 static bool
40036 {
40050 {
40053 }
40056 {
40061 }
40074 {
40081 }
40088 {
40093 ;
40096 else
40098 }
40107 }
40109 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
40110 a vector permutation using two instructions, vperm2f128 resp.
40111 vperm2i128 followed by any single in-lane permutation. */
40113 static bool
40115 {
40129 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
40130 immediate. For perm < 16 the second permutation uses
40131 d->op0 as first operand, for perm >= 16 it uses d->op1
40132 as first operand. The second operand is the result of
40133 vperm2[fi]128. */
40135 {
40136 /* Ignore permutations which do not move anything cross-lane. */
40138 {
40139 /* The second shuffle for e.g. V4DFmode has
40140 0123 and ABCD operands.
40141 Ignore AB23, as 23 is already in the second lane
40142 of the first operand. */
40144 /* And 01CD, as 01 is in the first lane of the first
40145 operand. */
40147 /* And 4567, as then the vperm2[fi]128 doesn't change
40148 anything on the original 4567 second operand. */
40150 }
40151 else
40152 {
40153 /* The second shuffle for e.g. V4DFmode has
40154 4567 and ABCD operands.
40155 Ignore AB67, as 67 is already in the second lane
40156 of the first operand. */
40158 /* And 45CD, as 45 is in the first lane of the first
40159 operand. */
40161 /* And 0123, as then the vperm2[fi]128 doesn't change
40162 anything on the original 0123 first operand. */
40164 }
40167 {
40173 else
40175 }
40178 {
40182 }
40183 else
40187 {
40191 /* Found a usable second shuffle. dfirst will be
40192 vperm2f128 on d->op0 and d->op1. */
40203 /* And dsecond is some single insn shuffle, taking
40204 d->op0 and result of vperm2f128 (if perm < 16) or
40205 d->op1 and result of vperm2f128 (otherwise). */
40214 }
40216 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
40219 }
40222 }
40224 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
40225 a two vector permutation using 2 intra-lane interleave insns
40226 and cross-lane shuffle for 32-byte vectors. */
40228 static bool
40230 {
40237 ;
40239 ;
40240 else
40255 {
40259 else
40265 else
40271 else
40277 else
40283 else
40289 else
40294 }
40298 }
40300 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
40301 a single vector permutation using a single intra-lane vector
40302 permutation, vperm2f128 swapping the lanes and vblend* insn blending
40303 the non-swapped and swapped vectors together. */
40305 static bool
40307 {
40310 rtx seq;
40315 || TARGET_AVX2
40324 {
40331 }
40366 }
40368 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
40369 permutation using two vperm2f128, followed by a vshufpd insn blending
40370 the two vectors together. */
40372 static bool
40374 {
40417 }
40419 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
40420 permutation with two pshufb insns and an ior. We should have already
40421 failed all two instruction sequences. */
40423 static bool
40425 {
40436 /* Generate two permutation masks. If the required element is within
40437 the given vector it is shuffled into the proper lane. If the required
40438 element is in the other vector, force a zero into the lane by setting
40439 bit 7 in the permutation mask. */
40442 {
40449 {
40452 }
40453 }
40473 }
40475 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
40476 with two vpshufb insns, vpermq and vpor. We should have already failed
40477 all two or three instruction sequences. */
40479 static bool
40481 {
40496 /* Generate two permutation masks. If the required element is within
40497 the same lane, it is shuffled in. If the required element from the
40498 other lane, force a zero by setting bit 7 in the permutation mask.
40499 In the other mask the mask has non-negative elements if element
40500 is requested from the other lane, but also moved to the other lane,
40501 so that the result of vpshufb can have the two V2TImode halves
40502 swapped. */
40505 {
40510 {
40513 }
40514 }
40523 /* Swap the 128-byte lanes of h into hp. */
40527 const1_rtx));
40540 }
40542 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
40543 and extract-odd permutations of two V32QImode and V16QImode operand
40544 with two vpshufb insns, vpor and vpermq. We should have already
40545 failed all two or three instruction sequences. */
40547 static bool
40549 {
40568 /* Generate two permutation masks. In the first permutation mask
40569 the first quarter will contain indexes for the first half
40570 of the op0, the second quarter will contain bit 7 set, third quarter
40571 will contain indexes for the second half of the op0 and the
40572 last quarter bit 7 set. In the second permutation mask
40573 the first quarter will contain bit 7 set, the second quarter
40574 indexes for the first half of the op1, the third quarter bit 7 set
40575 and last quarter indexes for the second half of the op1.
40576 I.e. the first mask e.g. for V32QImode extract even will be:
40577 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
40578 (all values masked with 0xf except for -128) and second mask
40579 for extract even will be
40580 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
40583 {
40589 {
40592 }
40593 }
40612 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
40619 }
40621 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
40622 and extract-odd permutations. */
40624 static bool
40626 {
40630 {
40635 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40639 /* Now an unpck[lh]pd will produce the result required. */
40642 else
40648 {
40655 /* Shuffle within the 128-bit lanes to produce:
40656 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
40660 /* Shuffle the lanes around to produce:
40661 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
40665 /* Shuffle within the 128-bit lanes to produce:
40666 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
40669 /* Shuffle within the 128-bit lanes to produce:
40670 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
40673 /* Shuffle the lanes around to produce:
40674 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
40677 }
40684 /* These are always directly implementable by expand_vec_perm_1. */
40690 else
40691 {
40692 /* We need 2*log2(N)-1 operations to achieve odd/even
40693 with interleave. */
40702 else
40705 }
40711 else
40712 {
40724 else
40727 }
40736 {
40743 }
40748 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40752 /* Now an vpunpck[lh]qdq will produce the result required. */
40755 else
40762 {
40769 }
40774 /* Shuffle the lanes around into
40775 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40785 /* Swap the 2nd and 3rd position in each lane into
40786 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40792 /* Now an vpunpck[lh]qdq will produce
40793 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40798 else
40807 }
40810 }
40812 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40813 extract-even and extract-odd permutations. */
40815 static bool
40817 {
40829 }
40831 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40832 permutations. We assume that expand_vec_perm_1 has already failed. */
40834 static bool
40836 {
40844 {
40847 /* These are special-cased in sse.md so that we can optionally
40848 use the vbroadcast instruction. They expand to two insns
40849 if the input happens to be in a register. */
40856 /* These are always implementable using standard shuffle patterns. */
40861 /* These can be implemented via interleave. We save one insn by
40862 stopping once we have promoted to V4SImode and then use pshufd. */
40863 do
40864 {
40865 rtx dest;
40871 {
40875 }
40882 }
40895 /* For AVX2 broadcasts of the first element vpbroadcast* or
40896 vpermq should be used by expand_vec_perm_1. */
40902 }
40903 }
40905 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40906 broadcast permutations. */
40908 static bool
40910 {
40922 }
40924 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40925 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40926 all the shorter instruction sequences. */
40928 static bool
40930 {
40946 /* Generate 4 permutation masks. If the required element is within
40947 the same lane, it is shuffled in. If the required element from the
40948 other lane, force a zero by setting bit 7 in the permutation mask.
40949 In the other mask the mask has non-negative elements if element
40950 is requested from the other lane, but also moved to the other lane,
40951 so that the result of vpshufb can have the two V2TImode halves
40952 swapped. */
40955 {
40960 }
40966 {
40974 }
40977 {
40979 {
40982 }
40989 }
40991 /* Swap the 128-byte lanes of h[X]. */
40993 {
40999 const1_rtx));
41001 }
41004 {
41006 {
41009 }
41015 }
41018 {
41020 {
41024 }
41027 }
41033 }
41035 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
41036 With all of the interface bits taken care of, perform the expansion
41037 in D and return true on success. */
41039 static bool
41041 {
41042 /* Try a single instruction expansion. */
41046 /* Try sequences of two instructions. */
41066 /* Try sequences of three instructions. */
41080 /* Try sequences of four instructions. */
41088 /* ??? Look for narrow permutations whose element orderings would
41089 allow the promotion to a wider mode. */
41091 /* ??? Look for sequences of interleave or a wider permute that place
41092 the data into the correct lanes for a half-vector shuffle like
41093 pshuf[lh]w or vpermilps. */
41095 /* ??? Look for sequences of interleave that produce the desired results.
41096 The combinatorics of punpck[lh] get pretty ugly... */
41101 /* Even longer sequences. */
41106 }
41108 /* If a permutation only uses one operand, make it clear. Returns true
41109 if the permutation references both operands. */
41111 static bool
41113 {
41121 {
41127 {
41130 }
41131 /* The elements of PERM do not suggest that only the first operand
41132 is used, but both operands are identical. Allow easier matching
41133 of the permutation by folding the permutation into the single
41134 input vector. */
41135 /* FALLTHRU */
41146 }
41149 }
41151 bool
41153 {
41158 rtx sel;
41175 {
41180 }
41187 /* If the selector says both arguments are needed, but the operands are the
41188 same, the above tried to expand with one_operand_p and flattened selector.
41189 If that didn't work, retry without one_operand_p; we succeeded with that
41190 during testing. */
41192 {
41196 }
41199 }
41201 /* Implement targetm.vectorize.vec_perm_const_ok. */
41203 static bool
41206 {
41215 /* Given sufficient ISA support we can just return true here
41216 for selected vector modes. */
41218 {
41219 /* All implementable with a single vpperm insn. */
41222 /* All implementable with 2 pshufb + 1 ior. */
41225 /* All implementable with shufpd or unpck[lh]pd. */
41228 }
41230 /* Extract the values from the vector CST into the permutation
41231 array in D. */
41234 {
41238 }
41240 /* For all elements from second vector, fold the elements to first. */
41245 /* Check whether the mask can be applied to the vector type. */
41248 /* Implementable with shufps or pshufd. */
41252 /* Otherwise we have to go through the motions and see if we can
41253 figure out how to generate the requested permutation. */
41264 }
41266 void
41268 {
41283 /* We'll either be able to implement the permutation directly... */
41287 /* ... or we use the special-case patterns. */
41289 }
41291 static void
41293 {
41308 {
41311 }
41313 /* Note that for AVX this isn't one instruction. */
41316 }
41319 /* Expand a vector operation CODE for a V*QImode in terms of the
41320 same operation on V*HImode. */
41322 void
41324 {
41336 {
41349 }
41353 {
41355 /* Unpack data such that we've got a source byte in each low byte of
41356 each word. We don't care what goes into the high byte of each word.
41357 Rather than trying to get zero in there, most convenient is to let
41358 it be a copy of the low byte. */
41363 /* FALLTHRU */
41375 /* FALLTHRU */
41385 }
41387 /* Perform the operation. */
41394 /* Merge the data back into the right place. */
41404 {
41405 /* For SSE2, we used an full interleave, so the desired
41406 results are in the even elements. */
41409 }
41410 else
41411 {
41412 /* For AVX, the interleave used above was not cross-lane. So the
41413 extraction is evens but with the second and third quarter swapped.
41414 Happily, that is even one insn shorter than even extraction. */
41417 }
41424 }
41426 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
41427 if op is CONST_VECTOR with all odd elements equal to their
41428 preceding element. */
41430 static bool
41432 {
41442 }
41444 void
41447 {
41450 rtx x;
41458 /* We only play even/odd games with vectors of SImode. */
41461 /* If we're looking for the odd results, shift those members down to
41462 the even slots. For some cpus this is faster than a PSHUFD. */
41464 {
41465 /* For XOP use vpmacsdqh, but only for smult, as it is only
41466 signed. */
41468 {
41472 }
41483 }
41486 {
41489 else
41491 }
41496 else
41497 {
41500 /* The easiest way to implement this without PMULDQ is to go through
41501 the motions as if we are performing a full 64-bit multiply. With
41502 the exception that we need to do less shuffling of the elements. */
41504 /* Compute the sign-extension, aka highparts, of the two operands. */
41510 /* Multiply LO(A) * HI(B), and vice-versa. */
41516 /* Multiply LO(A) * LO(B). */
41520 /* Combine and shift the highparts into place. */
41525 /* Combine high and low parts. */
41528 }
41530 }
41532 void
41535 {
41541 {
41546 {
41547 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
41548 shuffle the elements once so that all elements are in the right
41549 place for immediate use: { A C B D }. */
41554 }
41555 else
41556 {
41557 /* Put the elements into place for the multiply. */
41561 }
41566 /* Shuffle the elements between the lanes. After this we
41567 have { A B E F | C D G H } for each operand. */
41577 /* Shuffle the elements within the lanes. After this we
41578 have { A A B B | C C D D } or { E E F F | G G H H }. */
41614 }
41615 }
41617 void
41619 {
41629 /* Move the results in element 2 down to element 1; we don't care
41630 what goes in elements 2 and 3. Then we can merge the parts
41631 back together with an interleave.
41633 Note that two other sequences were tried:
41634 (1) Use interleaves at the start instead of psrldq, which allows
41635 us to use a single shufps to merge things back at the end.
41636 (2) Use shufps here to combine the two vectors, then pshufd to
41637 put the elements in the correct order.
41638 In both cases the cost of the reformatting stall was too high
41639 and the overall sequence slower. */
41648 }
41650 void
41652 {
41657 {
41658 /* op1: A,B,C,D, op2: E,F,G,H */
41667 /* t1: B,A,D,C */
41674 /* t2: (B*E),(A*F),(D*G),(C*H) */
41677 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
41680 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
41683 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
41685 }
41686 else
41687 {
41692 {
41695 }
41697 {
41700 }
41701 else
41705 /* Multiply low parts. */
41709 /* Shift input vectors right 32 bits so we can multiply high parts. */
41714 /* Multiply high parts by low parts. */
41720 /* Combine and shift the highparts back. */
41724 /* Combine high and low parts. */
41726 }
41730 }
41732 /* Expand an insert into a vector register through pinsr insn.
41733 Return true if successful. */
41735 bool
41737 {
41745 {
41748 }
41754 {
41759 {
41766 {
41798 }
41807 }
41811 }
41812 }
41813 \f
41814 /* This function returns the calling abi specific va_list type node.
41815 It returns the FNDECL specific va_list type. */
41817 static tree
41819 {
41826 else
41828 }
41830 /* Returns the canonical va_list type specified by TYPE. If there
41831 is no valid TYPE provided, it return NULL_TREE. */
41833 static tree
41835 {
41838 /* Resolve references and pointers to va_list type. */
41847 {
41852 {
41853 /* If va_list is an array type, the argument may have decayed
41854 to a pointer type, e.g. by being passed to another function.
41855 In that case, unwrap both types so that we can compare the
41856 underlying records. */
41859 {
41862 }
41863 }
41870 {
41871 /* If va_list is an array type, the argument may have decayed
41872 to a pointer type, e.g. by being passed to another function.
41873 In that case, unwrap both types so that we can compare the
41874 underlying records. */
41877 {
41880 }
41881 }
41888 {
41889 /* If va_list is an array type, the argument may have decayed
41890 to a pointer type, e.g. by being passed to another function.
41891 In that case, unwrap both types so that we can compare the
41892 underlying records. */
41895 {
41898 }
41899 }
41903 }
41905 }
41907 /* Iterate through the target-specific builtin types for va_list.
41908 IDX denotes the iterator, *PTREE is set to the result type of
41909 the va_list builtin, and *PNAME to its internal type.
41910 Returns zero if there is no element for this index, otherwise
41911 IDX should be increased upon the next call.
41912 Note, do not iterate a base builtin's name like __builtin_va_list.
41913 Used from c_common_nodes_and_builtins. */
41915 static int
41917 {
41919 {
41921 {
41934 }
41935 }
41938 }
41940 #undef TARGET_SCHED_DISPATCH
41941 #define TARGET_SCHED_DISPATCH has_dispatch
41942 #undef TARGET_SCHED_DISPATCH_DO
41943 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41944 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41945 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41946 #undef TARGET_SCHED_REORDER
41947 #define TARGET_SCHED_REORDER ix86_sched_reorder
41948 #undef TARGET_SCHED_ADJUST_PRIORITY
41949 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41950 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41951 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
41952 ix86_dependencies_evaluation_hook
41954 /* The size of the dispatch window is the total number of bytes of
41955 object code allowed in a window. */
41956 #define DISPATCH_WINDOW_SIZE 16
41958 /* Number of dispatch windows considered for scheduling. */
41959 #define MAX_DISPATCH_WINDOWS 3
41961 /* Maximum number of instructions in a window. */
41962 #define MAX_INSN 4
41964 /* Maximum number of immediate operands in a window. */
41965 #define MAX_IMM 4
41967 /* Maximum number of immediate bits allowed in a window. */
41968 #define MAX_IMM_SIZE 128
41970 /* Maximum number of 32 bit immediates allowed in a window. */
41971 #define MAX_IMM_32 4
41973 /* Maximum number of 64 bit immediates allowed in a window. */
41974 #define MAX_IMM_64 2
41976 /* Maximum total of loads or prefetches allowed in a window. */
41977 #define MAX_LOAD 2
41979 /* Maximum total of stores allowed in a window. */
41980 #define MAX_STORE 1
41982 #undef BIG
41983 #define BIG 100
41986 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41989 disp_load,
41990 disp_store,
41991 disp_load_store,
41992 disp_prefetch,
41993 disp_imm,
41994 disp_imm_32,
41995 disp_imm_64,
41996 disp_branch,
41997 disp_cmp,
41998 disp_jcc,
41999 disp_last
42000 };
42002 /* Number of allowable groups in a dispatch window. It is an array
42003 indexed by dispatch_group enum. 100 is used as a big number,
42004 because the number of these kind of operations does not have any
42005 effect in dispatch window, but we need them for other reasons in
42006 the table. */
42009 };
42015 };
42017 /* Instruction path. */
42023 last_path
42024 };
42026 /* sched_insn_info defines a window to the instructions scheduled in
42027 the basic block. It contains a pointer to the insn_info table and
42028 the instruction scheduled.
42030 Windows are allocated for each basic block and are linked
42031 together. */
42033 rtx insn;
42040 /* Linked list of dispatch windows. This is a two way list of
42041 dispatch windows of a basic block. It contains information about
42042 the number of uops in the window and the total number of
42043 instructions and of bytes in the object code for this dispatch
42044 window. */
42062 /* Immediate valuse used in an insn. */
42064 {
42073 /* Get dispatch group of insn. */
42075 static enum dispatch_group
42077 {
42093 }
42095 /* Return true if insn is a compare instruction. */
42097 static bool
42099 {
42107 }
42109 /* Return true if a dispatch violation encountered. */
42111 static bool
42113 {
42117 }
42119 /* Return true if insn is a branch instruction. */
42121 static bool
42123 {
42125 }
42127 /* Return true if insn is a prefetch instruction. */
42129 static bool
42131 {
42133 }
42135 /* This function initializes a dispatch window and the list container holding a
42136 pointer to the window. */
42138 static void
42140 {
42146 else
42164 {
42170 }
42172 }
42174 /* This function allocates and initializes a dispatch window and the
42175 list container holding a pointer to the window. */
42179 {
42184 }
42186 /* This routine initializes the dispatch scheduling information. It
42187 initiates building dispatch scheduler tables and constructs the
42188 first dispatch window. */
42190 static void
42192 {
42193 /* Allocate a dispatch list and a window. */
42198 }
42200 /* This function returns true if a branch is detected. End of a basic block
42201 does not have to be a branch, but here we assume only branches end a
42202 window. */
42204 static bool
42206 {
42208 }
42210 /* This function is called when the end of a window processing is reached. */
42212 static void
42214 {
42217 {
42222 }
42224 }
42226 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
42227 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
42228 for 48 bytes of instructions. Note that these windows are not dispatch
42229 windows that their sizes are DISPATCH_WINDOW_SIZE. */
42233 {
42235 {
42240 }
42246 }
42248 /* Increment the number of immediate operands of an instruction. */
42250 static int
42252 {
42257 {
42264 else
42275 {
42278 }
42283 }
42286 }
42288 /* Compute number of immediate operands of an instruction. */
42290 static void
42292 {
42295 }
42297 /* Return total size of immediate operands of an instruction along with number
42298 of corresponding immediate-operands. It initializes its parameters to zero
42299 befor calling FIND_CONSTANT.
42300 INSN is the input instruction. IMM is the total of immediates.
42301 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
42302 bit immediates. */
42304 static int
42306 {
42314 }
42316 /* This function indicates if an operand of an instruction is an
42317 immediate. */
42319 static bool
42321 {
42330 }
42332 /* Return single or double path for instructions. */
42334 static enum insn_path
42336 {
42346 }
42348 /* Return insn dispatch group. */
42350 static enum dispatch_group
42352 {
42370 }
42372 /* Count number of GROUP restricted instructions in a dispatch
42373 window WINDOW_LIST. */
42375 static int
42377 {
42388 {
42407 }
42420 }
42422 /* This function returns true if insn satisfies dispatch rules on the
42423 last window scheduled. */
42425 static bool
42427 {
42435 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
42436 instructions should be given the lowest priority in the
42437 scheduling process in Haifa scheduler to make sure they will be
42438 scheduled in the same dispatch window as the reference to them. */
42442 /* Check nonrestricted. */
42446 /* Get last dispatch window. */
42451 {
42456 /* Window 1 is full. Go for next window. */
42458 }
42465 /* See if it fits in the first window. */
42467 {
42468 /* The first widow should have only single and double path
42469 uops. */
42475 }
42477 }
42479 /* Add an instruction INSN with NUM_UOPS micro-operations to the
42480 dispatch window WINDOW_LIST. */
42482 static void
42484 {
42502 /* Initialize window with new instruction. */
42523 {
42526 }
42527 }
42529 /* Adds a scheduled instruction, INSN, to the current dispatch window.
42530 If the total bytes of instructions or the number of instructions in
42531 the window exceed allowable, it allocates a new window. */
42533 static void
42535 {
42558 /* Get the last dispatch window. */
42566 else
42569 /* If current window is full, get a new window.
42570 Window number zero is full, if MAX_INSN uops are scheduled in it.
42571 Window number one is full, if window zero's bytes plus window
42572 one's bytes is 32, or if the bytes of the new instruction added
42573 to the total makes it greater than 48, or it has already MAX_INSN
42574 instructions in it. */
42583 {
42586 }
42589 {
42593 {
42596 }
42597 }
42599 {
42604 {
42607 }
42610 }
42611 else
42615 {
42616 /* End of basic block is reached do end-basic-block process. */
42619 }
42620 }
42622 /* Print the dispatch window, WINDOW_NUM, to FILE. */
42624 DEBUG_FUNCTION static void
42626 {
42632 else
42646 {
42649 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
42655 }
42656 }
42658 /* Print to stdout a dispatch window. */
42660 DEBUG_FUNCTION void
42662 {
42664 }
42666 /* Print INSN dispatch information to FILE. */
42668 DEBUG_FUNCTION static void
42670 {
42693 }
42695 /* Print to STDERR the status of the ready list with respect to
42696 dispatch windows. */
42698 DEBUG_FUNCTION void
42700 {
42708 }
42710 /* This routine is the driver of the dispatch scheduler. */
42712 static void
42714 {
42719 }
42721 /* Return TRUE if Dispatch Scheduling is supported. */
42723 static bool
42725 {
42729 {
42745 }
42748 }
42750 /* Implementation of reassociation_width target hook used by
42751 reassoc phase to identify parallelism level in reassociated
42752 tree. Statements tree_code is passed in OPC. Arguments type
42753 is passed in MODE.
42755 Currently parallel reassociation is enabled for Atom
42756 processors only and we set reassociation width to be 2
42757 because Atom may issue up to 2 instructions per cycle.
42759 Return value should be fixed if parallel reassociation is
42760 enabled for other processors. */
42762 static int
42765 {
42774 }
42776 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42777 place emms and femms instructions. */
42779 static enum machine_mode
42781 {
42786 {
42799 else
42809 /* FALLTHRU */
42813 }
42814 }
42816 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42817 vectors. */
42819 static unsigned int
42821 {
42823 }
42825 \f
42827 /* Return class of registers which could be used for pseudo of MODE
42828 and of class RCLASS for spilling instead of memory. Return NO_REGS
42829 if it is not possible or non-profitable. */
42830 static reg_class_t
42832 {
42838 }
42840 /* Implement targetm.vectorize.init_cost. */
42844 {
42848 }
42850 /* Implement targetm.vectorize.add_stmt_cost. */
42852 static unsigned
42856 {
42863 /* Statements in an inner loop relative to the loop being
42864 vectorized are weighted more heavily. The value here is
42865 arbitrary and could potentially be improved with analysis. */
42873 }
42875 /* Implement targetm.vectorize.finish_cost. */
42877 static void
42880 {
42885 }
42887 /* Implement targetm.vectorize.destroy_cost_data. */
42889 static void
42891 {
42893 }
42895 /* Validate target specific memory model bits in VAL. */
42897 static unsigned HOST_WIDE_INT
42899 {
42906 {
42910 }
42913 {
42917 }
42919 {
42923 }
42925 }
42927 /* Initialize the GCC target structure. */
42928 #undef TARGET_RETURN_IN_MEMORY
42929 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42931 #undef TARGET_LEGITIMIZE_ADDRESS
42932 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42934 #undef TARGET_ATTRIBUTE_TABLE
42935 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42936 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
42937 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
42938 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42939 # undef TARGET_MERGE_DECL_ATTRIBUTES
42940 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42941 #endif
42943 #undef TARGET_COMP_TYPE_ATTRIBUTES
42944 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42946 #undef TARGET_INIT_BUILTINS
42947 #define TARGET_INIT_BUILTINS ix86_init_builtins
42948 #undef TARGET_BUILTIN_DECL
42949 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42950 #undef TARGET_EXPAND_BUILTIN
42951 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42953 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42954 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42955 ix86_builtin_vectorized_function
42957 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42958 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42960 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42961 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42963 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42964 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42966 #undef TARGET_BUILTIN_RECIPROCAL
42967 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42969 #undef TARGET_ASM_FUNCTION_EPILOGUE
42970 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42972 #undef TARGET_ENCODE_SECTION_INFO
42973 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42974 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42975 #else
42976 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42977 #endif
42979 #undef TARGET_ASM_OPEN_PAREN
42981 #undef TARGET_ASM_CLOSE_PAREN
42984 #undef TARGET_ASM_BYTE_OP
42985 #define TARGET_ASM_BYTE_OP ASM_BYTE
42987 #undef TARGET_ASM_ALIGNED_HI_OP
42988 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42989 #undef TARGET_ASM_ALIGNED_SI_OP
42990 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42991 #ifdef ASM_QUAD
42992 #undef TARGET_ASM_ALIGNED_DI_OP
42993 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42994 #endif
42996 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42997 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42999 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
43000 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
43002 #undef TARGET_ASM_UNALIGNED_HI_OP
43003 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
43004 #undef TARGET_ASM_UNALIGNED_SI_OP
43005 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
43006 #undef TARGET_ASM_UNALIGNED_DI_OP
43007 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
43009 #undef TARGET_PRINT_OPERAND
43010 #define TARGET_PRINT_OPERAND ix86_print_operand
43011 #undef TARGET_PRINT_OPERAND_ADDRESS
43012 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
43013 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
43014 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
43015 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
43016 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
43018 #undef TARGET_SCHED_INIT_GLOBAL
43019 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
43020 #undef TARGET_SCHED_ADJUST_COST
43021 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
43022 #undef TARGET_SCHED_ISSUE_RATE
43023 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
43024 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
43025 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
43026 ia32_multipass_dfa_lookahead
43028 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
43029 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
43031 #undef TARGET_MEMMODEL_CHECK
43032 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
43034 #ifdef HAVE_AS_TLS
43035 #undef TARGET_HAVE_TLS
43036 #define TARGET_HAVE_TLS true
43037 #endif
43038 #undef TARGET_CANNOT_FORCE_CONST_MEM
43039 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
43040 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
43041 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
43043 #undef TARGET_DELEGITIMIZE_ADDRESS
43044 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
43046 #undef TARGET_MS_BITFIELD_LAYOUT_P
43047 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
43049 #if TARGET_MACHO
43050 #undef TARGET_BINDS_LOCAL_P
43051 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
43052 #endif
43053 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
43054 #undef TARGET_BINDS_LOCAL_P
43055 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
43056 #endif
43058 #undef TARGET_ASM_OUTPUT_MI_THUNK
43059 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
43060 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
43061 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
43063 #undef TARGET_ASM_FILE_START
43064 #define TARGET_ASM_FILE_START x86_file_start
43066 #undef TARGET_OPTION_OVERRIDE
43067 #define TARGET_OPTION_OVERRIDE ix86_option_override
43069 #undef TARGET_REGISTER_MOVE_COST
43070 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
43071 #undef TARGET_MEMORY_MOVE_COST
43072 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
43073 #undef TARGET_RTX_COSTS
43074 #define TARGET_RTX_COSTS ix86_rtx_costs
43075 #undef TARGET_ADDRESS_COST
43076 #define TARGET_ADDRESS_COST ix86_address_cost
43078 #undef TARGET_FIXED_CONDITION_CODE_REGS
43079 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
43080 #undef TARGET_CC_MODES_COMPATIBLE
43081 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
43083 #undef TARGET_MACHINE_DEPENDENT_REORG
43084 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
43086 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
43087 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
43089 #undef TARGET_BUILD_BUILTIN_VA_LIST
43090 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
43092 #undef TARGET_FOLD_BUILTIN
43093 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
43095 #undef TARGET_COMPARE_VERSION_PRIORITY
43096 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
43098 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
43099 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
43100 ix86_generate_version_dispatcher_body
43102 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
43103 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
43104 ix86_get_function_versions_dispatcher
43106 #undef TARGET_ENUM_VA_LIST_P
43107 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
43109 #undef TARGET_FN_ABI_VA_LIST
43110 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
43112 #undef TARGET_CANONICAL_VA_LIST_TYPE
43113 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
43115 #undef TARGET_EXPAND_BUILTIN_VA_START
43116 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
43118 #undef TARGET_MD_ASM_CLOBBERS
43119 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
43121 #undef TARGET_PROMOTE_PROTOTYPES
43122 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
43123 #undef TARGET_STRUCT_VALUE_RTX
43124 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
43125 #undef TARGET_SETUP_INCOMING_VARARGS
43126 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
43127 #undef TARGET_MUST_PASS_IN_STACK
43128 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
43129 #undef TARGET_FUNCTION_ARG_ADVANCE
43130 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
43131 #undef TARGET_FUNCTION_ARG
43132 #define TARGET_FUNCTION_ARG ix86_function_arg
43133 #undef TARGET_FUNCTION_ARG_BOUNDARY
43134 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
43135 #undef TARGET_PASS_BY_REFERENCE
43136 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
43137 #undef TARGET_INTERNAL_ARG_POINTER
43138 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
43139 #undef TARGET_UPDATE_STACK_BOUNDARY
43140 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
43141 #undef TARGET_GET_DRAP_RTX
43142 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
43143 #undef TARGET_STRICT_ARGUMENT_NAMING
43144 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
43145 #undef TARGET_STATIC_CHAIN
43146 #define TARGET_STATIC_CHAIN ix86_static_chain
43147 #undef TARGET_TRAMPOLINE_INIT
43148 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
43149 #undef TARGET_RETURN_POPS_ARGS
43150 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
43152 #undef TARGET_LEGITIMATE_COMBINED_INSN
43153 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
43155 #undef TARGET_ASAN_SHADOW_OFFSET
43156 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
43158 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
43159 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
43161 #undef TARGET_SCALAR_MODE_SUPPORTED_P
43162 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
43164 #undef TARGET_VECTOR_MODE_SUPPORTED_P
43165 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
43167 #undef TARGET_C_MODE_FOR_SUFFIX
43168 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
43170 #ifdef HAVE_AS_TLS
43171 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
43172 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
43173 #endif
43175 #ifdef SUBTARGET_INSERT_ATTRIBUTES
43176 #undef TARGET_INSERT_ATTRIBUTES
43177 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
43178 #endif
43180 #undef TARGET_MANGLE_TYPE
43181 #define TARGET_MANGLE_TYPE ix86_mangle_type
43183 #if !TARGET_MACHO
43184 #undef TARGET_STACK_PROTECT_FAIL
43185 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
43186 #endif
43188 #undef TARGET_FUNCTION_VALUE
43189 #define TARGET_FUNCTION_VALUE ix86_function_value
43191 #undef TARGET_FUNCTION_VALUE_REGNO_P
43192 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
43194 #undef TARGET_PROMOTE_FUNCTION_MODE
43195 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
43197 #undef TARGET_MEMBER_TYPE_FORCES_BLK
43198 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
43200 #undef TARGET_INSTANTIATE_DECLS
43201 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
43203 #undef TARGET_SECONDARY_RELOAD
43204 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
43206 #undef TARGET_CLASS_MAX_NREGS
43207 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
43209 #undef TARGET_PREFERRED_RELOAD_CLASS
43210 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
43211 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
43212 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
43213 #undef TARGET_CLASS_LIKELY_SPILLED_P
43214 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
43216 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
43217 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
43218 ix86_builtin_vectorization_cost
43219 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
43220 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
43221 ix86_vectorize_vec_perm_const_ok
43222 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
43223 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
43224 ix86_preferred_simd_mode
43225 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
43226 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
43227 ix86_autovectorize_vector_sizes
43228 #undef TARGET_VECTORIZE_INIT_COST
43229 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
43230 #undef TARGET_VECTORIZE_ADD_STMT_COST
43231 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
43232 #undef TARGET_VECTORIZE_FINISH_COST
43233 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
43234 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
43235 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
43237 #undef TARGET_SET_CURRENT_FUNCTION
43238 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
43240 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
43241 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
43243 #undef TARGET_OPTION_SAVE
43244 #define TARGET_OPTION_SAVE ix86_function_specific_save
43246 #undef TARGET_OPTION_RESTORE
43247 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
43249 #undef TARGET_OPTION_PRINT
43250 #define TARGET_OPTION_PRINT ix86_function_specific_print
43252 #undef TARGET_OPTION_FUNCTION_VERSIONS
43253 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
43255 #undef TARGET_CAN_INLINE_P
43256 #define TARGET_CAN_INLINE_P ix86_can_inline_p
43258 #undef TARGET_EXPAND_TO_RTL_HOOK
43259 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
43261 #undef TARGET_LEGITIMATE_ADDRESS_P
43262 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
43264 #undef TARGET_LRA_P
43265 #define TARGET_LRA_P hook_bool_void_true
43267 #undef TARGET_REGISTER_PRIORITY
43268 #define TARGET_REGISTER_PRIORITY ix86_register_priority
43270 #undef TARGET_REGISTER_USAGE_LEVELING_P
43271 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
43273 #undef TARGET_LEGITIMATE_CONSTANT_P
43274 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
43276 #undef TARGET_FRAME_POINTER_REQUIRED
43277 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
43279 #undef TARGET_CAN_ELIMINATE
43280 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
43282 #undef TARGET_EXTRA_LIVE_ON_ENTRY
43283 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
43285 #undef TARGET_ASM_CODE_END
43286 #define TARGET_ASM_CODE_END ix86_code_end
43288 #undef TARGET_CONDITIONAL_REGISTER_USAGE
43289 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
43291 #if TARGET_MACHO
43292 #undef TARGET_INIT_LIBFUNCS
43293 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
43294 #endif
43296 #undef TARGET_SPILL_CLASS
43297 #define TARGET_SPILL_CLASS ix86_spill_class
43300 \f