1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
40 #include "tree-pass.h"
41 #include "sched-int.h"
45 #include "langhooks.h"
46 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename
;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg
*rtx_search_arg_p
;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode
[NUM_MACHINE_MODES
];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok
[NUM_MACHINE_MODES
];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename
[FIRST_PSEUDO_REGISTER
];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered
[NUM_MACHINE_MODES
];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used
;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs
;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs
;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming
;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd
;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged
, c_expr_local
;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns
;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn
: 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t
*original_insns
;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params
*fur_static_params_p
;
405 typedef struct cmpd_local_params
*cmpd_local_params_p
;
406 typedef struct moveop_static_params
*moveop_static_params_p
;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter
) (insn_t
, cmpd_local_params_p
, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found
) (insn_t
, expr_t
, cmpd_local_params_p
, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found
) (insn_t
, av_set_t
, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs
) (insn_t
, insn_t
, int, cmpd_local_params_p
, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs
) (cmpd_local_params_p
, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend
) (insn_t
, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn
) (insn_t
, cmpd_local_params_p
, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name
;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def
*code_motion_path_driver_info
;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 struct code_motion_path_driver_info_def move_op_hooks
, fur_hooks
;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p
;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p
;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence
;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid
;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads
;
484 bitmap_head
*forced_ebb_heads
= &_forced_ebb_heads
;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule
= NULL
;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first
= false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size
= 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more
;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled
;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t
,heap
);
508 static VEC(expr_t
, heap
) *vec_av_set
= NULL
;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t
,heap
);
513 typedef VEC(vinsn_t
, heap
) *vinsn_vec_t
;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns
= NULL
;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns
= NULL
;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t
,heap
);
530 static VEC(insn_t
, heap
) *vec_temp_moveop_nops
= NULL
;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators
= NULL
;
535 static bitmap current_copies
= NULL
;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks
= NULL
;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies
;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping
;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled
;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total
;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx
, rtx
);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t
find_sequential_best_exprs (bnd_t
, expr_t
, bool);
561 static rtx
get_dest_from_orig_ops (av_set_t
);
562 static basic_block
generate_bookkeeping_insn (expr_t
, edge
, edge
);
563 static bool find_used_regs (insn_t
, av_set_t
, regset
, struct reg_rename
*,
565 static bool move_op (insn_t
, av_set_t
, expr_t
, rtx
, expr_t
);
566 static bool code_motion_path_driver (insn_t
, av_set_t
, ilist_t
,
567 cmpd_local_params_p
, void *);
568 static void sel_sched_region_1 (void);
569 static void sel_sched_region_2 (int);
570 static av_set_t
compute_av_set_inside_bb (insn_t
, ilist_t
, int, bool);
572 static void debug_state (state_t
);
575 /* Functions that work with fences. */
577 /* Advance one cycle on FENCE. */
579 advance_one_cycle (fence_t fence
)
585 advance_state (FENCE_STATE (fence
));
586 cycle
= ++FENCE_CYCLE (fence
);
587 FENCE_ISSUED_INSNS (fence
) = 0;
588 FENCE_STARTS_CYCLE_P (fence
) = 1;
589 can_issue_more
= issue_rate
;
591 for (i
= 0; VEC_iterate (rtx
, FENCE_EXECUTING_INSNS (fence
), i
, insn
); )
593 if (INSN_READY_CYCLE (insn
) < cycle
)
595 remove_from_deps (FENCE_DC (fence
), insn
);
596 VEC_unordered_remove (rtx
, FENCE_EXECUTING_INSNS (fence
), i
);
601 if (sched_verbose
>= 2)
603 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence
));
604 debug_state (FENCE_STATE (fence
));
608 /* Returns true when SUCC in a fallthru bb of INSN, possibly
609 skipping empty basic blocks. */
611 in_fallthru_bb_p (rtx insn
, rtx succ
)
613 basic_block bb
= BLOCK_FOR_INSN (insn
);
615 if (bb
== BLOCK_FOR_INSN (succ
))
618 if (find_fallthru_edge (bb
))
619 bb
= find_fallthru_edge (bb
)->dest
;
623 while (sel_bb_empty_p (bb
))
626 return bb
== BLOCK_FOR_INSN (succ
);
629 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
630 When a successor will continue a ebb, transfer all parameters of a fence
631 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
632 of scheduling helping to distinguish between the old and the new code. */
634 extract_new_fences_from (flist_t old_fences
, flist_tail_t new_fences
,
637 bool was_here_p
= false;
638 insn_t insn
= NULL_RTX
;
642 fence_t fence
= FLIST_FENCE (old_fences
);
645 /* Get the only element of FENCE_BNDS (fence). */
646 FOR_EACH_INSN (insn
, ii
, FENCE_BNDS (fence
))
648 gcc_assert (!was_here_p
);
651 gcc_assert (was_here_p
&& insn
!= NULL_RTX
);
653 /* When in the "middle" of the block, just move this fence
655 bb
= BLOCK_FOR_INSN (insn
);
656 if (! sel_bb_end_p (insn
)
657 || (single_succ_p (bb
)
658 && single_pred_p (single_succ (bb
))))
662 succ
= (sel_bb_end_p (insn
)
663 ? sel_bb_head (single_succ (bb
))
666 if (INSN_SEQNO (succ
) > 0
667 && INSN_SEQNO (succ
) <= orig_max_seqno
668 && INSN_SCHED_TIMES (succ
) <= 0)
670 FENCE_INSN (fence
) = succ
;
671 move_fence_to_fences (old_fences
, new_fences
);
673 if (sched_verbose
>= 1)
674 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
675 INSN_UID (insn
), INSN_UID (succ
), BLOCK_NUM (succ
));
680 /* Otherwise copy fence's structures to (possibly) multiple successors. */
681 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
683 int seqno
= INSN_SEQNO (succ
);
685 if (0 < seqno
&& seqno
<= orig_max_seqno
686 && (pipelining_p
|| INSN_SCHED_TIMES (succ
) <= 0))
688 bool b
= (in_same_ebb_p (insn
, succ
)
689 || in_fallthru_bb_p (insn
, succ
));
691 if (sched_verbose
>= 1)
692 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
693 INSN_UID (insn
), INSN_UID (succ
),
694 BLOCK_NUM (succ
), b
? "continue" : "reset");
697 add_dirty_fence_to_fences (new_fences
, succ
, fence
);
700 /* Mark block of the SUCC as head of the new ebb. */
701 bitmap_set_bit (forced_ebb_heads
, BLOCK_NUM (succ
));
702 add_clean_fence_to_fences (new_fences
, succ
, fence
);
709 /* Functions to support substitution. */
711 /* Returns whether INSN with dependence status DS is eligible for
712 substitution, i.e. it's a copy operation x := y, and RHS that is
713 moved up through this insn should be substituted. */
715 can_substitute_through_p (insn_t insn
, ds_t ds
)
717 /* We can substitute only true dependencies. */
718 if ((ds
& DEP_OUTPUT
)
721 || ! INSN_LHS (insn
))
724 /* Now we just need to make sure the INSN_RHS consists of only one
726 if (REG_P (INSN_LHS (insn
))
727 && REG_P (INSN_RHS (insn
)))
732 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
733 source (if INSN is eligible for substitution). Returns TRUE if
734 substitution was actually performed, FALSE otherwise. Substitution might
735 be not performed because it's either EXPR' vinsn doesn't contain INSN's
736 destination or the resulting insn is invalid for the target machine.
737 When UNDO is true, perform unsubstitution instead (the difference is in
738 the part of rtx on which validate_replace_rtx is called). */
740 substitute_reg_in_expr (expr_t expr
, insn_t insn
, bool undo
)
744 vinsn_t
*vi
= &EXPR_VINSN (expr
);
745 bool has_rhs
= VINSN_RHS (*vi
) != NULL
;
748 /* Do not try to replace in SET_DEST. Although we'll choose new
749 register for the RHS, we don't want to change RHS' original reg.
750 If the insn is not SET, we may still be able to substitute something
751 in it, and if we're here (don't have deps), it doesn't write INSN's
755 : &PATTERN (VINSN_INSN_RTX (*vi
)));
756 old
= undo
? INSN_RHS (insn
) : INSN_LHS (insn
);
758 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
759 if (rtx_ok_for_substitution_p (old
, *where
))
764 /* We should copy these rtxes before substitution. */
765 new_rtx
= copy_rtx (undo
? INSN_LHS (insn
) : INSN_RHS (insn
));
766 new_insn
= create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi
));
768 /* Where we'll replace.
769 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
770 used instead of SET_SRC. */
771 where_replace
= (has_rhs
772 ? &SET_SRC (PATTERN (new_insn
))
773 : &PATTERN (new_insn
));
776 = validate_replace_rtx_part_nosimplify (old
, new_rtx
, where_replace
,
779 /* ??? Actually, constrain_operands result depends upon choice of
780 destination register. E.g. if we allow single register to be an rhs,
781 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
782 in invalid insn dx=dx, so we'll loose this rhs here.
783 Just can't come up with significant testcase for this, so just
784 leaving it for now. */
787 change_vinsn_in_expr (expr
,
788 create_vinsn_from_insn_rtx (new_insn
, false));
790 /* Do not allow clobbering the address register of speculative
792 if ((EXPR_SPEC_DONE_DS (expr
) & SPECULATIVE
)
793 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr
)),
794 expr_dest_regno (expr
)))
795 EXPR_TARGET_AVAILABLE (expr
) = false;
806 /* Helper function for count_occurences_equiv. */
808 count_occurrences_1 (rtx
*cur_rtx
, void *arg
)
810 rtx_search_arg_p p
= (rtx_search_arg_p
) arg
;
812 /* The last param FOR_GCSE is true, because otherwise it performs excessive
816 for the last insn it presumes r33 equivalent to r8, so it changes it to
817 r33. Actually, there's no change, but it spoils debugging. */
818 if (exp_equiv_p (*cur_rtx
, p
->x
, 0, true))
820 /* Bail out if we occupy more than one register. */
822 && hard_regno_nregs
[REGNO(*cur_rtx
)][GET_MODE (*cur_rtx
)] > 1)
830 /* Do not traverse subexprs. */
834 if (GET_CODE (*cur_rtx
) == SUBREG
836 && REGNO (SUBREG_REG (*cur_rtx
)) == REGNO (p
->x
))
838 /* ??? Do not support substituting regs inside subregs. In that case,
839 simplify_subreg will be called by validate_replace_rtx, and
840 unsubstitution will fail later. */
845 /* Continue search. */
849 /* Return the number of places WHAT appears within WHERE.
850 Bail out when we found a reference occupying several hard registers. */
852 count_occurrences_equiv (rtx what
, rtx where
)
854 struct rtx_search_arg arg
;
859 for_each_rtx (&where
, &count_occurrences_1
, (void *) &arg
);
864 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
866 rtx_ok_for_substitution_p (rtx what
, rtx where
)
868 return (count_occurrences_equiv (what
, where
) > 0);
872 /* Functions to support register renaming. */
874 /* Substitute VI's set source with REGNO. Returns newly created pattern
875 that has REGNO as its source. */
877 create_insn_rtx_with_rhs (vinsn_t vi
, rtx rhs_rtx
)
883 lhs_rtx
= copy_rtx (VINSN_LHS (vi
));
885 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
886 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
891 /* Returns whether INSN's src can be replaced with register number
892 NEW_SRC_REG. E.g. the following insn is valid for i386:
894 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
895 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
896 (reg:SI 0 ax [orig:770 c1 ] [770]))
897 (const_int 288 [0x120])) [0 str S1 A8])
898 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
901 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
902 because of operand constraints:
904 (define_insn "*movqi_1"
905 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
906 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
909 So do constrain_operands here, before choosing NEW_SRC_REG as best
913 replace_src_with_reg_ok_p (insn_t insn
, rtx new_src_reg
)
915 vinsn_t vi
= INSN_VINSN (insn
);
916 enum machine_mode mode
;
920 gcc_assert (VINSN_SEPARABLE_P (vi
));
922 get_dest_and_mode (insn
, &dst_loc
, &mode
);
923 gcc_assert (mode
== GET_MODE (new_src_reg
));
925 if (REG_P (dst_loc
) && REGNO (new_src_reg
) == REGNO (dst_loc
))
928 /* See whether SET_SRC can be replaced with this register. */
929 validate_change (insn
, &SET_SRC (PATTERN (insn
)), new_src_reg
, 1);
930 res
= verify_changes (0);
936 /* Returns whether INSN still be valid after replacing it's DEST with
939 replace_dest_with_reg_ok_p (insn_t insn
, rtx new_reg
)
941 vinsn_t vi
= INSN_VINSN (insn
);
944 /* We should deal here only with separable insns. */
945 gcc_assert (VINSN_SEPARABLE_P (vi
));
946 gcc_assert (GET_MODE (VINSN_LHS (vi
)) == GET_MODE (new_reg
));
948 /* See whether SET_DEST can be replaced with this register. */
949 validate_change (insn
, &SET_DEST (PATTERN (insn
)), new_reg
, 1);
950 res
= verify_changes (0);
956 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
958 create_insn_rtx_with_lhs (vinsn_t vi
, rtx lhs_rtx
)
964 rhs_rtx
= copy_rtx (VINSN_RHS (vi
));
966 pattern
= gen_rtx_SET (VOIDmode
, lhs_rtx
, rhs_rtx
);
967 insn_rtx
= create_insn_rtx_from_pattern (pattern
, NULL_RTX
);
972 /* Substitute lhs in the given expression EXPR for the register with number
973 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
975 replace_dest_with_reg_in_expr (expr_t expr
, rtx new_reg
)
980 insn_rtx
= create_insn_rtx_with_lhs (EXPR_VINSN (expr
), new_reg
);
981 vinsn
= create_vinsn_from_insn_rtx (insn_rtx
, false);
983 change_vinsn_in_expr (expr
, vinsn
);
984 EXPR_WAS_RENAMED (expr
) = 1;
985 EXPR_TARGET_AVAILABLE (expr
) = 1;
988 /* Returns whether VI writes either one of the USED_REGS registers or,
989 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
991 vinsn_writes_one_of_regs_p (vinsn_t vi
, regset used_regs
,
992 HARD_REG_SET unavailable_hard_regs
)
995 reg_set_iterator rsi
;
997 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi
), 0, regno
, rsi
)
999 if (REGNO_REG_SET_P (used_regs
, regno
))
1001 if (HARD_REGISTER_NUM_P (regno
)
1002 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1006 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi
), 0, regno
, rsi
)
1008 if (REGNO_REG_SET_P (used_regs
, regno
))
1010 if (HARD_REGISTER_NUM_P (regno
)
1011 && TEST_HARD_REG_BIT (unavailable_hard_regs
, regno
))
1018 /* Returns register class of the output register in INSN.
1019 Returns NO_REGS for call insns because some targets have constraints on
1020 destination register of a call insn.
1022 Code adopted from regrename.c::build_def_use. */
1023 static enum reg_class
1024 get_reg_class (rtx insn
)
1028 extract_insn (insn
);
1029 if (! constrain_operands (1))
1030 fatal_insn_not_found (insn
);
1031 preprocess_constraints ();
1032 alt
= which_alternative
;
1033 n_ops
= recog_data
.n_operands
;
1035 for (i
= 0; i
< n_ops
; ++i
)
1037 int matches
= recog_op_alt
[i
][alt
].matches
;
1039 recog_op_alt
[i
][alt
].cl
= recog_op_alt
[matches
][alt
].cl
;
1042 if (asm_noperands (PATTERN (insn
)) > 0)
1044 for (i
= 0; i
< n_ops
; i
++)
1045 if (recog_data
.operand_type
[i
] == OP_OUT
)
1047 rtx
*loc
= recog_data
.operand_loc
[i
];
1049 enum reg_class cl
= recog_op_alt
[i
][alt
].cl
;
1052 && REGNO (op
) == ORIGINAL_REGNO (op
))
1058 else if (!CALL_P (insn
))
1060 for (i
= 0; i
< n_ops
+ recog_data
.n_dups
; i
++)
1062 int opn
= i
< n_ops
? i
: recog_data
.dup_num
[i
- n_ops
];
1063 enum reg_class cl
= recog_op_alt
[opn
][alt
].cl
;
1065 if (recog_data
.operand_type
[opn
] == OP_OUT
||
1066 recog_data
.operand_type
[opn
] == OP_INOUT
)
1072 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1073 may result in returning NO_REGS, cause flags is written implicitly through
1074 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1078 #ifdef HARD_REGNO_RENAME_OK
1079 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1081 init_hard_regno_rename (int regno
)
1085 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], regno
);
1087 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1089 /* We are not interested in renaming in other regs. */
1090 if (!TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
))
1093 if (HARD_REGNO_RENAME_OK (regno
, cur_reg
))
1094 SET_HARD_REG_BIT (sel_hrd
.regs_for_rename
[regno
], cur_reg
);
1099 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1102 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED
, int to ATTRIBUTE_UNUSED
)
1104 #ifdef HARD_REGNO_RENAME_OK
1105 /* Check whether this is all calculated. */
1106 if (TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], from
))
1107 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1109 init_hard_regno_rename (from
);
1111 return TEST_HARD_REG_BIT (sel_hrd
.regs_for_rename
[from
], to
);
1117 /* Calculate set of registers that are capable of holding MODE. */
1119 init_regs_for_mode (enum machine_mode mode
)
1123 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_mode
[mode
]);
1124 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_call_clobbered
[mode
]);
1126 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1128 int nregs
= hard_regno_nregs
[cur_reg
][mode
];
1131 for (i
= nregs
- 1; i
>= 0; --i
)
1132 if (fixed_regs
[cur_reg
+ i
]
1133 || global_regs
[cur_reg
+ i
]
1134 /* Can't use regs which aren't saved by
1136 || !TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
+ i
)
1137 #ifdef LEAF_REGISTERS
1138 /* We can't use a non-leaf register if we're in a
1140 || (current_function_is_leaf
1141 && !LEAF_REGISTERS
[cur_reg
+ i
])
1149 /* See whether it accepts all modes that occur in
1151 if (! HARD_REGNO_MODE_OK (cur_reg
, mode
))
1154 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg
, mode
))
1155 SET_HARD_REG_BIT (sel_hrd
.regs_for_call_clobbered
[mode
],
1158 /* If the CUR_REG passed all the checks above,
1160 SET_HARD_REG_BIT (sel_hrd
.regs_for_mode
[mode
], cur_reg
);
1163 sel_hrd
.regs_for_mode_ok
[mode
] = true;
1166 /* Init all register sets gathered in HRD. */
1168 init_hard_regs_data (void)
1171 enum machine_mode cur_mode
= 0;
1173 CLEAR_HARD_REG_SET (sel_hrd
.regs_ever_used
);
1174 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1175 if (df_regs_ever_live_p (cur_reg
) || call_used_regs
[cur_reg
])
1176 SET_HARD_REG_BIT (sel_hrd
.regs_ever_used
, cur_reg
);
1178 /* Initialize registers that are valid based on mode when this is
1180 for (cur_mode
= 0; cur_mode
< NUM_MACHINE_MODES
; cur_mode
++)
1181 sel_hrd
.regs_for_mode_ok
[cur_mode
] = false;
1183 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1184 for (cur_reg
= 0; cur_reg
< FIRST_PSEUDO_REGISTER
; cur_reg
++)
1185 CLEAR_HARD_REG_SET (sel_hrd
.regs_for_rename
[cur_reg
]);
1188 CLEAR_HARD_REG_SET (sel_hrd
.stack_regs
);
1190 for (cur_reg
= FIRST_STACK_REG
; cur_reg
<= LAST_STACK_REG
; cur_reg
++)
1191 SET_HARD_REG_BIT (sel_hrd
.stack_regs
, cur_reg
);
1195 /* Mark hardware regs in REG_RENAME_P that are not suitable
1196 for renaming rhs in INSN due to hardware restrictions (register class,
1197 modes compatibility etc). This doesn't affect original insn's dest reg,
1198 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1199 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1200 Registers that are in used_regs are always marked in
1201 unavailable_hard_regs as well. */
1204 mark_unavailable_hard_regs (def_t def
, struct reg_rename
*reg_rename_p
,
1205 regset used_regs ATTRIBUTE_UNUSED
)
1207 enum machine_mode mode
;
1208 enum reg_class cl
= NO_REGS
;
1210 unsigned cur_reg
, regno
;
1211 hard_reg_set_iterator hrsi
;
1213 gcc_assert (GET_CODE (PATTERN (def
->orig_insn
)) == SET
);
1214 gcc_assert (reg_rename_p
);
1216 orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1218 /* We have decided not to rename 'mem = something;' insns, as 'something'
1219 is usually a register. */
1220 if (!REG_P (orig_dest
))
1223 regno
= REGNO (orig_dest
);
1225 /* If before reload, don't try to work with pseudos. */
1226 if (!reload_completed
&& !HARD_REGISTER_NUM_P (regno
))
1229 mode
= GET_MODE (orig_dest
);
1231 /* Stop when mode is not supported for renaming. Also can't proceed
1232 if the original register is one of the fixed_regs, global_regs or
1234 if (fixed_regs
[regno
]
1235 || global_regs
[regno
]
1236 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1237 || (frame_pointer_needed
&& regno
== HARD_FRAME_POINTER_REGNUM
)
1239 || (frame_pointer_needed
&& regno
== FRAME_POINTER_REGNUM
)
1243 SET_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
);
1245 /* Give a chance for original register, if it isn't in used_regs. */
1246 if (!def
->crosses_call
)
1247 CLEAR_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
);
1252 /* If something allocated on stack in this function, mark frame pointer
1253 register unavailable, considering also modes.
1254 FIXME: it is enough to do this once per all original defs. */
1255 if (frame_pointer_needed
)
1259 for (i
= hard_regno_nregs
[FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1260 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1261 FRAME_POINTER_REGNUM
+ i
);
1263 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1264 for (i
= hard_regno_nregs
[HARD_FRAME_POINTER_REGNUM
][Pmode
]; i
--;)
1265 SET_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1266 HARD_FRAME_POINTER_REGNUM
+ i
);
1271 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1272 is equivalent to as if all stack regs were in this set.
1273 I.e. no stack register can be renamed, and even if it's an original
1274 register here we make sure it won't be lifted over it's previous def
1275 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1276 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1277 if (IN_RANGE (REGNO (orig_dest
), FIRST_STACK_REG
, LAST_STACK_REG
)
1278 && REGNO_REG_SET_P (used_regs
, FIRST_STACK_REG
))
1279 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1280 sel_hrd
.stack_regs
);
1283 /* If there's a call on this path, make regs from call_used_reg_set
1285 if (def
->crosses_call
)
1286 IOR_HARD_REG_SET (reg_rename_p
->unavailable_hard_regs
,
1289 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1290 but not register classes. */
1291 if (!reload_completed
)
1294 /* Leave regs as 'available' only from the current
1296 cl
= get_reg_class (def
->orig_insn
);
1297 gcc_assert (cl
!= NO_REGS
);
1298 COPY_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1299 reg_class_contents
[cl
]);
1301 /* Leave only registers available for this mode. */
1302 if (!sel_hrd
.regs_for_mode_ok
[mode
])
1303 init_regs_for_mode (mode
);
1304 AND_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1305 sel_hrd
.regs_for_mode
[mode
]);
1307 /* Exclude registers that are partially call clobbered. */
1308 if (def
->crosses_call
1309 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
1310 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1311 sel_hrd
.regs_for_call_clobbered
[mode
]);
1313 /* Leave only those that are ok to rename. */
1314 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1320 nregs
= hard_regno_nregs
[cur_reg
][mode
];
1321 gcc_assert (nregs
> 0);
1323 for (i
= nregs
- 1; i
>= 0; --i
)
1324 if (! sel_hard_regno_rename_ok (regno
+ i
, cur_reg
+ i
))
1328 CLEAR_HARD_REG_BIT (reg_rename_p
->available_for_renaming
,
1332 AND_COMPL_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1333 reg_rename_p
->unavailable_hard_regs
);
1335 /* Regno is always ok from the renaming part of view, but it really
1336 could be in *unavailable_hard_regs already, so set it here instead
1338 SET_HARD_REG_BIT (reg_rename_p
->available_for_renaming
, regno
);
1341 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1342 best register more recently than REG2. */
1343 static int reg_rename_tick
[FIRST_PSEUDO_REGISTER
];
1345 /* Indicates the number of times renaming happened before the current one. */
1346 static int reg_rename_this_tick
;
1348 /* Choose the register among free, that is suitable for storing
1351 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1352 originally appears. There could be multiple original operations
1353 for single rhs since we moving it up and merging along different
1356 Some code is adapted from regrename.c (regrename_optimize).
1357 If original register is available, function returns it.
1358 Otherwise it performs the checks, so the new register should
1359 comply with the following:
1360 - it should not violate any live ranges (such registers are in
1361 REG_RENAME_P->available_for_renaming set);
1362 - it should not be in the HARD_REGS_USED regset;
1363 - it should be in the class compatible with original uses;
1364 - it should not be clobbered through reference with different mode;
1365 - if we're in the leaf function, then the new register should
1366 not be in the LEAF_REGISTERS;
1369 If several registers meet the conditions, the register with smallest
1370 tick is returned to achieve more even register allocation.
1372 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1374 If no register satisfies the above conditions, NULL_RTX is returned. */
1376 choose_best_reg_1 (HARD_REG_SET hard_regs_used
,
1377 struct reg_rename
*reg_rename_p
,
1378 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1382 enum machine_mode mode
= VOIDmode
;
1383 unsigned regno
, i
, n
;
1384 hard_reg_set_iterator hrsi
;
1385 def_list_iterator di
;
1388 /* If original register is available, return it. */
1389 *is_orig_reg_p_ptr
= true;
1391 FOR_EACH_DEF (def
, di
, original_insns
)
1393 rtx orig_dest
= SET_DEST (PATTERN (def
->orig_insn
));
1395 gcc_assert (REG_P (orig_dest
));
1397 /* Check that all original operations have the same mode.
1398 This is done for the next loop; if we'd return from this
1399 loop, we'd check only part of them, but in this case
1400 it doesn't matter. */
1401 if (mode
== VOIDmode
)
1402 mode
= GET_MODE (orig_dest
);
1403 gcc_assert (mode
== GET_MODE (orig_dest
));
1405 regno
= REGNO (orig_dest
);
1406 for (i
= 0, n
= hard_regno_nregs
[regno
][mode
]; i
< n
; i
++)
1407 if (TEST_HARD_REG_BIT (hard_regs_used
, regno
+ i
))
1410 /* All hard registers are available. */
1413 gcc_assert (mode
!= VOIDmode
);
1415 /* Hard registers should not be shared. */
1416 return gen_rtx_REG (mode
, regno
);
1420 *is_orig_reg_p_ptr
= false;
1423 /* Among all available regs choose the register that was
1424 allocated earliest. */
1425 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p
->available_for_renaming
,
1427 if (! TEST_HARD_REG_BIT (hard_regs_used
, cur_reg
))
1429 /* All hard registers are available. */
1430 if (best_new_reg
< 0
1431 || reg_rename_tick
[cur_reg
] < reg_rename_tick
[best_new_reg
])
1433 best_new_reg
= cur_reg
;
1435 /* Return immediately when we know there's no better reg. */
1436 if (! reg_rename_tick
[best_new_reg
])
1441 if (best_new_reg
>= 0)
1443 /* Use the check from the above loop. */
1444 gcc_assert (mode
!= VOIDmode
);
1445 return gen_rtx_REG (mode
, best_new_reg
);
1451 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1452 assumptions about available registers in the function. */
1454 choose_best_reg (HARD_REG_SET hard_regs_used
, struct reg_rename
*reg_rename_p
,
1455 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1457 rtx best_reg
= choose_best_reg_1 (hard_regs_used
, reg_rename_p
,
1458 original_insns
, is_orig_reg_p_ptr
);
1460 gcc_assert (best_reg
== NULL_RTX
1461 || TEST_HARD_REG_BIT (sel_hrd
.regs_ever_used
, REGNO (best_reg
)));
1466 /* Choose the pseudo register for storing rhs value. As this is supposed
1467 to work before reload, we return either the original register or make
1468 the new one. The parameters are the same that in choose_nest_reg_1
1469 functions, except that USED_REGS may contain pseudos.
1470 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1472 TODO: take into account register pressure while doing this. Up to this
1473 moment, this function would never return NULL for pseudos, but we should
1474 not rely on this. */
1476 choose_best_pseudo_reg (regset used_regs
,
1477 struct reg_rename
*reg_rename_p
,
1478 def_list_t original_insns
, bool *is_orig_reg_p_ptr
)
1480 def_list_iterator i
;
1482 enum machine_mode mode
= VOIDmode
;
1483 bool bad_hard_regs
= false;
1485 /* We should not use this after reload. */
1486 gcc_assert (!reload_completed
);
1488 /* If original register is available, return it. */
1489 *is_orig_reg_p_ptr
= true;
1491 FOR_EACH_DEF (def
, i
, original_insns
)
1493 rtx dest
= SET_DEST (PATTERN (def
->orig_insn
));
1496 gcc_assert (REG_P (dest
));
1498 /* Check that all original operations have the same mode. */
1499 if (mode
== VOIDmode
)
1500 mode
= GET_MODE (dest
);
1502 gcc_assert (mode
== GET_MODE (dest
));
1503 orig_regno
= REGNO (dest
);
1505 if (!REGNO_REG_SET_P (used_regs
, orig_regno
))
1507 if (orig_regno
< FIRST_PSEUDO_REGISTER
)
1509 gcc_assert (df_regs_ever_live_p (orig_regno
));
1511 /* For hard registers, we have to check hardware imposed
1512 limitations (frame/stack registers, calls crossed). */
1513 if (!TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
,
1516 /* Don't let register cross a call if it doesn't already
1517 cross one. This condition is written in accordance with
1518 that in sched-deps.c sched_analyze_reg(). */
1519 if (!reg_rename_p
->crosses_call
1520 || REG_N_CALLS_CROSSED (orig_regno
) > 0)
1521 return gen_rtx_REG (mode
, orig_regno
);
1524 bad_hard_regs
= true;
1531 *is_orig_reg_p_ptr
= false;
1533 /* We had some original hard registers that couldn't be used.
1534 Those were likely special. Don't try to create a pseudo. */
1538 /* We haven't found a register from original operations. Get a new one.
1539 FIXME: control register pressure somehow. */
1541 rtx new_reg
= gen_reg_rtx (mode
);
1543 gcc_assert (mode
!= VOIDmode
);
1545 max_regno
= max_reg_num ();
1546 maybe_extend_reg_info_p ();
1547 REG_N_CALLS_CROSSED (REGNO (new_reg
)) = reg_rename_p
->crosses_call
? 1 : 0;
1553 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1554 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1556 verify_target_availability (expr_t expr
, regset used_regs
,
1557 struct reg_rename
*reg_rename_p
)
1559 unsigned n
, i
, regno
;
1560 enum machine_mode mode
;
1561 bool target_available
, live_available
, hard_available
;
1563 if (!REG_P (EXPR_LHS (expr
)) || EXPR_TARGET_AVAILABLE (expr
) < 0)
1566 regno
= expr_dest_regno (expr
);
1567 mode
= GET_MODE (EXPR_LHS (expr
));
1568 target_available
= EXPR_TARGET_AVAILABLE (expr
) == 1;
1569 n
= reload_completed
? hard_regno_nregs
[regno
][mode
] : 1;
1571 live_available
= hard_available
= true;
1572 for (i
= 0; i
< n
; i
++)
1574 if (bitmap_bit_p (used_regs
, regno
+ i
))
1575 live_available
= false;
1576 if (TEST_HARD_REG_BIT (reg_rename_p
->unavailable_hard_regs
, regno
+ i
))
1577 hard_available
= false;
1580 /* When target is not available, it may be due to hard register
1581 restrictions, e.g. crosses calls, so we check hard_available too. */
1582 if (target_available
)
1583 gcc_assert (live_available
);
1585 /* Check only if we haven't scheduled something on the previous fence,
1586 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1587 and having more than one fence, we may end having targ_un in a block
1588 in which successors target register is actually available.
1590 The last condition handles the case when a dependence from a call insn
1591 was created in sched-deps.c for insns with destination registers that
1592 never crossed a call before, but do cross one after our code motion.
1594 FIXME: in the latter case, we just uselessly called find_used_regs,
1595 because we can't move this expression with any other register
1597 gcc_assert (scheduled_something_on_previous_fence
|| !live_available
1599 || (!reload_completed
&& reg_rename_p
->crosses_call
1600 && REG_N_CALLS_CROSSED (regno
) == 0));
1603 /* Collect unavailable registers due to liveness for EXPR from BNDS
1604 into USED_REGS. Save additional information about available
1605 registers and unavailable due to hardware restriction registers
1606 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1609 collect_unavailable_regs_from_bnds (expr_t expr
, blist_t bnds
, regset used_regs
,
1610 struct reg_rename
*reg_rename_p
,
1611 def_list_t
*original_insns
)
1613 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
1616 av_set_t orig_ops
= NULL
;
1617 bnd_t bnd
= BLIST_BND (bnds
);
1619 /* If the chosen best expr doesn't belong to current boundary,
1621 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr
)))
1624 /* Put in ORIG_OPS all exprs from this boundary that became
1626 orig_ops
= find_sequential_best_exprs (bnd
, expr
, false);
1628 /* Compute used regs and OR it into the USED_REGS. */
1629 res
= find_used_regs (BND_TO (bnd
), orig_ops
, used_regs
,
1630 reg_rename_p
, original_insns
);
1632 /* FIXME: the assert is true until we'd have several boundaries. */
1634 av_set_clear (&orig_ops
);
1638 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1639 If BEST_REG is valid, replace LHS of EXPR with it. */
1641 try_replace_dest_reg (ilist_t orig_insns
, rtx best_reg
, expr_t expr
)
1643 if (expr_dest_regno (expr
) == REGNO (best_reg
))
1645 EXPR_TARGET_AVAILABLE (expr
) = 1;
1649 gcc_assert (orig_insns
);
1651 /* Try whether we'll be able to generate the insn
1652 'dest := best_reg' at the place of the original operation. */
1653 for (; orig_insns
; orig_insns
= ILIST_NEXT (orig_insns
))
1655 insn_t orig_insn
= DEF_LIST_DEF (orig_insns
)->orig_insn
;
1657 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn
)));
1659 if (!replace_src_with_reg_ok_p (orig_insn
, best_reg
)
1660 || !replace_dest_with_reg_ok_p (orig_insn
, best_reg
))
1664 /* Make sure that EXPR has the right destination
1666 replace_dest_with_reg_in_expr (expr
, best_reg
);
1670 /* Select and assign best register to EXPR searching from BNDS.
1671 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1672 Return FALSE if no register can be chosen, which could happen when:
1673 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1674 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1675 that are used on the moving path. */
1677 find_best_reg_for_expr (expr_t expr
, blist_t bnds
, bool *is_orig_reg_p
)
1679 static struct reg_rename reg_rename_data
;
1682 def_list_t original_insns
= NULL
;
1685 *is_orig_reg_p
= false;
1687 /* Don't bother to do anything if this insn doesn't set any registers. */
1688 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr
)))
1689 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr
))))
1692 used_regs
= get_clear_regset_from_pool ();
1693 CLEAR_HARD_REG_SET (reg_rename_data
.unavailable_hard_regs
);
1695 collect_unavailable_regs_from_bnds (expr
, bnds
, used_regs
, ®_rename_data
,
1698 #ifdef ENABLE_CHECKING
1699 /* If after reload, make sure we're working with hard regs here. */
1700 if (reload_completed
)
1702 reg_set_iterator rsi
;
1705 EXECUTE_IF_SET_IN_REG_SET (used_regs
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1710 if (EXPR_SEPARABLE_P (expr
))
1712 rtx best_reg
= NULL_RTX
;
1713 /* Check that we have computed availability of a target register
1715 verify_target_availability (expr
, used_regs
, ®_rename_data
);
1717 /* Turn everything in hard regs after reload. */
1718 if (reload_completed
)
1720 HARD_REG_SET hard_regs_used
;
1721 REG_SET_TO_HARD_REG_SET (hard_regs_used
, used_regs
);
1723 /* Join hard registers unavailable due to register class
1724 restrictions and live range intersection. */
1725 IOR_HARD_REG_SET (hard_regs_used
,
1726 reg_rename_data
.unavailable_hard_regs
);
1728 best_reg
= choose_best_reg (hard_regs_used
, ®_rename_data
,
1729 original_insns
, is_orig_reg_p
);
1732 best_reg
= choose_best_pseudo_reg (used_regs
, ®_rename_data
,
1733 original_insns
, is_orig_reg_p
);
1737 else if (*is_orig_reg_p
)
1739 /* In case of unification BEST_REG may be different from EXPR's LHS
1740 when EXPR's LHS is unavailable, and there is another LHS among
1742 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1746 /* Forbid renaming of low-cost insns. */
1747 if (sel_vinsn_cost (EXPR_VINSN (expr
)) < 2)
1750 reg_ok
= try_replace_dest_reg (original_insns
, best_reg
, expr
);
1755 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1756 any of the HARD_REGS_USED set. */
1757 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr
), used_regs
,
1758 reg_rename_data
.unavailable_hard_regs
))
1761 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) <= 0);
1766 gcc_assert (EXPR_TARGET_AVAILABLE (expr
) != 0);
1770 ilist_clear (&original_insns
);
1771 return_regset_to_pool (used_regs
);
1777 /* Return true if dependence described by DS can be overcomed. */
1779 can_speculate_dep_p (ds_t ds
)
1781 if (spec_info
== NULL
)
1784 /* Leave only speculative data. */
1791 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1792 that we can overcome. */
1793 ds_t spec_mask
= spec_info
->mask
;
1795 if ((ds
& spec_mask
) != ds
)
1799 if (ds_weak (ds
) < spec_info
->data_weakness_cutoff
)
1805 /* Get a speculation check instruction.
1806 C_EXPR is a speculative expression,
1807 CHECK_DS describes speculations that should be checked,
1808 ORIG_INSN is the original non-speculative insn in the stream. */
1810 create_speculation_check (expr_t c_expr
, ds_t check_ds
, insn_t orig_insn
)
1815 basic_block recovery_block
;
1818 /* Create a recovery block if target is going to emit branchy check, or if
1819 ORIG_INSN was speculative already. */
1820 if (targetm
.sched
.needs_block_p (check_ds
)
1821 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn
)) != 0)
1823 recovery_block
= sel_create_recovery_block (orig_insn
);
1824 label
= BB_HEAD (recovery_block
);
1828 recovery_block
= NULL
;
1832 /* Get pattern of the check. */
1833 check_pattern
= targetm
.sched
.gen_spec_check (EXPR_INSN_RTX (c_expr
), label
,
1836 gcc_assert (check_pattern
!= NULL
);
1839 insn_rtx
= create_insn_rtx_from_pattern (check_pattern
, label
);
1841 insn
= sel_gen_insn_from_rtx_after (insn_rtx
, INSN_EXPR (orig_insn
),
1842 INSN_SEQNO (orig_insn
), orig_insn
);
1844 /* Make check to be non-speculative. */
1845 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
1846 INSN_SPEC_CHECKED_DS (insn
) = check_ds
;
1848 /* Decrease priority of check by difference of load/check instruction
1850 EXPR_PRIORITY (INSN_EXPR (insn
)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn
))
1851 - sel_vinsn_cost (INSN_VINSN (insn
)));
1853 /* Emit copy of original insn (though with replaced target register,
1854 if needed) to the recovery block. */
1855 if (recovery_block
!= NULL
)
1860 twin_rtx
= copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr
)));
1861 twin_rtx
= create_insn_rtx_from_pattern (twin_rtx
, NULL_RTX
);
1862 twin
= sel_gen_recovery_insn_from_rtx_after (twin_rtx
,
1863 INSN_EXPR (orig_insn
),
1865 bb_note (recovery_block
));
1868 /* If we've generated a data speculation check, make sure
1869 that all the bookkeeping instruction we'll create during
1870 this move_op () will allocate an ALAT entry so that the
1872 In case of control speculation we must convert C_EXPR to control
1873 speculative mode, because failing to do so will bring us an exception
1874 thrown by the non-control-speculative load. */
1875 check_ds
= ds_get_max_dep_weak (check_ds
);
1876 speculate_expr (c_expr
, check_ds
);
1881 /* True when INSN is a "regN = regN" copy. */
1883 identical_copy_p (rtx insn
)
1887 pat
= PATTERN (insn
);
1889 if (GET_CODE (pat
) != SET
)
1892 lhs
= SET_DEST (pat
);
1896 rhs
= SET_SRC (pat
);
1900 return REGNO (lhs
) == REGNO (rhs
);
1903 /* Undo all transformations on *AV_PTR that were done when
1904 moving through INSN. */
1906 undo_transformations (av_set_t
*av_ptr
, rtx insn
)
1908 av_set_iterator av_iter
;
1910 av_set_t new_set
= NULL
;
1912 /* First, kill any EXPR that uses registers set by an insn. This is
1913 required for correctness. */
1914 FOR_EACH_EXPR_1 (expr
, av_iter
, av_ptr
)
1915 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (expr
))
1916 && bitmap_intersect_p (INSN_REG_SETS (insn
),
1917 VINSN_REG_USES (EXPR_VINSN (expr
)))
1918 /* When an insn looks like 'r1 = r1', we could substitute through
1919 it, but the above condition will still hold. This happened with
1920 gcc.c-torture/execute/961125-1.c. */
1921 && !identical_copy_p (insn
))
1923 if (sched_verbose
>= 6)
1924 sel_print ("Expr %d removed due to use/set conflict\n",
1925 INSN_UID (EXPR_INSN_RTX (expr
)));
1926 av_set_iter_remove (&av_iter
);
1929 /* Undo transformations looking at the history vector. */
1930 FOR_EACH_EXPR (expr
, av_iter
, *av_ptr
)
1932 int index
= find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr
),
1933 insn
, EXPR_VINSN (expr
), true);
1937 expr_history_def
*phist
;
1939 phist
= VEC_index (expr_history_def
,
1940 EXPR_HISTORY_OF_CHANGES (expr
),
1943 switch (phist
->type
)
1945 case TRANS_SPECULATION
:
1947 ds_t old_ds
, new_ds
;
1949 /* Compute the difference between old and new speculative
1950 statuses: that's what we need to check.
1951 Earlier we used to assert that the status will really
1952 change. This no longer works because only the probability
1953 bits in the status may have changed during compute_av_set,
1954 and in the case of merging different probabilities of the
1955 same speculative status along different paths we do not
1956 record this in the history vector. */
1957 old_ds
= phist
->spec_ds
;
1958 new_ds
= EXPR_SPEC_DONE_DS (expr
);
1960 old_ds
&= SPECULATIVE
;
1961 new_ds
&= SPECULATIVE
;
1964 EXPR_SPEC_TO_CHECK_DS (expr
) |= new_ds
;
1967 case TRANS_SUBSTITUTION
:
1969 expr_def _tmp_expr
, *tmp_expr
= &_tmp_expr
;
1973 new_vi
= phist
->old_expr_vinsn
;
1975 gcc_assert (VINSN_SEPARABLE_P (new_vi
)
1976 == EXPR_SEPARABLE_P (expr
));
1977 copy_expr (tmp_expr
, expr
);
1979 if (vinsn_equal_p (phist
->new_expr_vinsn
,
1980 EXPR_VINSN (tmp_expr
)))
1981 change_vinsn_in_expr (tmp_expr
, new_vi
);
1983 /* This happens when we're unsubstituting on a bookkeeping
1984 copy, which was in turn substituted. The history is wrong
1985 in this case. Do it the hard way. */
1986 add
= substitute_reg_in_expr (tmp_expr
, insn
, true);
1988 av_set_add (&new_set
, tmp_expr
);
1989 clear_expr (tmp_expr
);
1999 av_set_union_and_clear (av_ptr
, &new_set
, NULL
);
2003 /* Moveup_* helpers for code motion and computing av sets. */
2005 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2006 The difference from the below function is that only substitution is
2008 static enum MOVEUP_EXPR_CODE
2009 moveup_expr_inside_insn_group (expr_t expr
, insn_t through_insn
)
2011 vinsn_t vi
= EXPR_VINSN (expr
);
2015 /* Do this only inside insn group. */
2016 gcc_assert (INSN_SCHED_CYCLE (through_insn
) > 0);
2018 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2020 return MOVEUP_EXPR_SAME
;
2022 /* Substitution is the possible choice in this case. */
2023 if (has_dep_p
[DEPS_IN_RHS
])
2025 /* Can't substitute UNIQUE VINSNs. */
2026 gcc_assert (!VINSN_UNIQUE_P (vi
));
2028 if (can_substitute_through_p (through_insn
,
2029 has_dep_p
[DEPS_IN_RHS
])
2030 && substitute_reg_in_expr (expr
, through_insn
, false))
2032 EXPR_WAS_SUBSTITUTED (expr
) = true;
2033 return MOVEUP_EXPR_CHANGED
;
2036 /* Don't care about this, as even true dependencies may be allowed
2037 in an insn group. */
2038 return MOVEUP_EXPR_SAME
;
2041 /* This can catch output dependencies in COND_EXECs. */
2042 if (has_dep_p
[DEPS_IN_INSN
])
2043 return MOVEUP_EXPR_NULL
;
2045 /* This is either an output or an anti dependence, which usually have
2046 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2048 gcc_assert (has_dep_p
[DEPS_IN_LHS
]);
2049 return MOVEUP_EXPR_AS_RHS
;
2052 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2053 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2054 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2055 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2056 && !sel_insn_is_speculation_check (through_insn))
2058 /* True when a conflict on a target register was found during moveup_expr. */
2059 static bool was_target_conflict
= false;
2061 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2062 performing necessary transformations. Record the type of transformation
2063 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2064 permit all dependencies except true ones, and try to remove those
2065 too via forward substitution. All cases when a non-eliminable
2066 non-zero cost dependency exists inside an insn group will be fixed
2067 in tick_check_p instead. */
2068 static enum MOVEUP_EXPR_CODE
2069 moveup_expr (expr_t expr
, insn_t through_insn
, bool inside_insn_group
,
2070 enum local_trans_type
*ptrans_type
)
2072 vinsn_t vi
= EXPR_VINSN (expr
);
2073 insn_t insn
= VINSN_INSN_RTX (vi
);
2074 bool was_changed
= false;
2075 bool as_rhs
= false;
2079 /* When inside_insn_group, delegate to the helper. */
2080 if (inside_insn_group
)
2081 return moveup_expr_inside_insn_group (expr
, through_insn
);
2083 /* Deal with unique insns and control dependencies. */
2084 if (VINSN_UNIQUE_P (vi
))
2086 /* We can move jumps without side-effects or jumps that are
2087 mutually exclusive with instruction THROUGH_INSN (all in cases
2088 dependencies allow to do so and jump is not speculative). */
2089 if (control_flow_insn_p (insn
))
2091 basic_block fallthru_bb
;
2093 /* Do not move checks and do not move jumps through other
2095 if (control_flow_insn_p (through_insn
)
2096 || sel_insn_is_speculation_check (insn
))
2097 return MOVEUP_EXPR_NULL
;
2099 /* Don't move jumps through CFG joins. */
2100 if (bookkeeping_can_be_created_if_moved_through_p (through_insn
))
2101 return MOVEUP_EXPR_NULL
;
2103 /* The jump should have a clear fallthru block, and
2104 this block should be in the current region. */
2105 if ((fallthru_bb
= fallthru_bb_of_jump (insn
)) == NULL
2106 || ! in_current_region_p (fallthru_bb
))
2107 return MOVEUP_EXPR_NULL
;
2109 /* And it should be mutually exclusive with through_insn, or
2110 be an unconditional jump. */
2111 if (! any_uncondjump_p (insn
)
2112 && ! sched_insns_conditions_mutex_p (insn
, through_insn
))
2113 return MOVEUP_EXPR_NULL
;
2116 /* Don't move what we can't move. */
2117 if (EXPR_CANT_MOVE (expr
)
2118 && BLOCK_FOR_INSN (through_insn
) != BLOCK_FOR_INSN (insn
))
2119 return MOVEUP_EXPR_NULL
;
2121 /* Don't move SCHED_GROUP instruction through anything.
2122 If we don't force this, then it will be possible to start
2123 scheduling a sched_group before all its dependencies are
2125 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2126 as late as possible through rank_for_schedule. */
2127 if (SCHED_GROUP_P (insn
))
2128 return MOVEUP_EXPR_NULL
;
2131 gcc_assert (!control_flow_insn_p (insn
));
2133 /* Deal with data dependencies. */
2134 was_target_conflict
= false;
2135 full_ds
= has_dependence_p (expr
, through_insn
, &has_dep_p
);
2138 if (!CANT_MOVE_TRAPPING (expr
, through_insn
))
2139 return MOVEUP_EXPR_SAME
;
2143 /* We can move UNIQUE insn up only as a whole and unchanged,
2144 so it shouldn't have any dependencies. */
2145 if (VINSN_UNIQUE_P (vi
))
2146 return MOVEUP_EXPR_NULL
;
2149 if (full_ds
!= 0 && can_speculate_dep_p (full_ds
))
2153 res
= speculate_expr (expr
, full_ds
);
2156 /* Speculation was successful. */
2158 was_changed
= (res
> 0);
2160 was_target_conflict
= true;
2162 *ptrans_type
= TRANS_SPECULATION
;
2163 sel_clear_has_dependence ();
2167 if (has_dep_p
[DEPS_IN_INSN
])
2168 /* We have some dependency that cannot be discarded. */
2169 return MOVEUP_EXPR_NULL
;
2171 if (has_dep_p
[DEPS_IN_LHS
])
2173 /* Only separable insns can be moved up with the new register.
2174 Anyways, we should mark that the original register is
2176 if (!enable_schedule_as_rhs_p
|| !EXPR_SEPARABLE_P (expr
))
2177 return MOVEUP_EXPR_NULL
;
2179 EXPR_TARGET_AVAILABLE (expr
) = false;
2180 was_target_conflict
= true;
2184 /* At this point we have either separable insns, that will be lifted
2185 up only as RHSes, or non-separable insns with no dependency in lhs.
2186 If dependency is in RHS, then try to perform substitution and move up
2193 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2194 moved above y=x assignment as z=x*2.
2196 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2197 side can be moved because of the output dependency. The operation was
2198 cropped to its rhs above. */
2199 if (has_dep_p
[DEPS_IN_RHS
])
2201 ds_t
*rhs_dsp
= &has_dep_p
[DEPS_IN_RHS
];
2203 /* Can't substitute UNIQUE VINSNs. */
2204 gcc_assert (!VINSN_UNIQUE_P (vi
));
2206 if (can_speculate_dep_p (*rhs_dsp
))
2210 res
= speculate_expr (expr
, *rhs_dsp
);
2213 /* Speculation was successful. */
2215 was_changed
= (res
> 0);
2217 was_target_conflict
= true;
2219 *ptrans_type
= TRANS_SPECULATION
;
2222 return MOVEUP_EXPR_NULL
;
2224 else if (can_substitute_through_p (through_insn
,
2226 && substitute_reg_in_expr (expr
, through_insn
, false))
2228 /* ??? We cannot perform substitution AND speculation on the same
2230 gcc_assert (!was_changed
);
2233 *ptrans_type
= TRANS_SUBSTITUTION
;
2234 EXPR_WAS_SUBSTITUTED (expr
) = true;
2237 return MOVEUP_EXPR_NULL
;
2240 /* Don't move trapping insns through jumps.
2241 This check should be at the end to give a chance to control speculation
2242 to perform its duties. */
2243 if (CANT_MOVE_TRAPPING (expr
, through_insn
))
2244 return MOVEUP_EXPR_NULL
;
2247 ? MOVEUP_EXPR_CHANGED
2249 ? MOVEUP_EXPR_AS_RHS
2250 : MOVEUP_EXPR_SAME
));
2253 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2254 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2255 that can exist within a parallel group. Write to RES the resulting
2256 code for moveup_expr. */
2258 try_bitmap_cache (expr_t expr
, insn_t insn
,
2259 bool inside_insn_group
,
2260 enum MOVEUP_EXPR_CODE
*res
)
2262 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2264 /* First check whether we've analyzed this situation already. */
2265 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn
), expr_uid
))
2267 if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2269 if (sched_verbose
>= 6)
2270 sel_print ("removed (cached)\n");
2271 *res
= MOVEUP_EXPR_NULL
;
2276 if (sched_verbose
>= 6)
2277 sel_print ("unchanged (cached)\n");
2278 *res
= MOVEUP_EXPR_SAME
;
2282 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn
), expr_uid
))
2284 if (inside_insn_group
)
2286 if (sched_verbose
>= 6)
2287 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2288 *res
= MOVEUP_EXPR_SAME
;
2293 EXPR_TARGET_AVAILABLE (expr
) = false;
2295 /* This is the only case when propagation result can change over time,
2296 as we can dynamically switch off scheduling as RHS. In this case,
2297 just check the flag to reach the correct decision. */
2298 if (enable_schedule_as_rhs_p
)
2300 if (sched_verbose
>= 6)
2301 sel_print ("unchanged (as RHS, cached)\n");
2302 *res
= MOVEUP_EXPR_AS_RHS
;
2307 if (sched_verbose
>= 6)
2308 sel_print ("removed (cached as RHS, but renaming"
2309 " is now disabled)\n");
2310 *res
= MOVEUP_EXPR_NULL
;
2318 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2319 if successful. Write to RES the resulting code for moveup_expr. */
2321 try_transformation_cache (expr_t expr
, insn_t insn
,
2322 enum MOVEUP_EXPR_CODE
*res
)
2324 struct transformed_insns
*pti
2325 = (struct transformed_insns
*)
2326 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2328 VINSN_HASH_RTX (EXPR_VINSN (expr
)));
2331 /* This EXPR was already moved through this insn and was
2332 changed as a result. Fetch the proper data from
2334 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2335 INSN_UID (insn
), pti
->type
,
2336 pti
->vinsn_old
, pti
->vinsn_new
,
2337 EXPR_SPEC_DONE_DS (expr
));
2339 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti
->vinsn_new
)))
2340 pti
->vinsn_new
= vinsn_copy (pti
->vinsn_new
, true);
2341 change_vinsn_in_expr (expr
, pti
->vinsn_new
);
2342 if (pti
->was_target_conflict
)
2343 EXPR_TARGET_AVAILABLE (expr
) = false;
2344 if (pti
->type
== TRANS_SPECULATION
)
2348 ds
= EXPR_SPEC_DONE_DS (expr
);
2350 EXPR_SPEC_DONE_DS (expr
) = pti
->ds
;
2351 EXPR_NEEDS_SPEC_CHECK_P (expr
) |= pti
->needs_check
;
2354 if (sched_verbose
>= 6)
2356 sel_print ("changed (cached): ");
2361 *res
= MOVEUP_EXPR_CHANGED
;
2368 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2370 update_bitmap_cache (expr_t expr
, insn_t insn
, bool inside_insn_group
,
2371 enum MOVEUP_EXPR_CODE res
)
2373 int expr_uid
= INSN_UID (EXPR_INSN_RTX (expr
));
2375 /* Do not cache result of propagating jumps through an insn group,
2376 as it is always true, which is not useful outside the group. */
2377 if (inside_insn_group
)
2380 if (res
== MOVEUP_EXPR_NULL
)
2382 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2383 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2385 else if (res
== MOVEUP_EXPR_SAME
)
2387 bitmap_set_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2388 bitmap_clear_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2390 else if (res
== MOVEUP_EXPR_AS_RHS
)
2392 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn
), expr_uid
);
2393 bitmap_set_bit (INSN_FOUND_DEPS (insn
), expr_uid
);
2399 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2400 and transformation type TRANS_TYPE. */
2402 update_transformation_cache (expr_t expr
, insn_t insn
,
2403 bool inside_insn_group
,
2404 enum local_trans_type trans_type
,
2405 vinsn_t expr_old_vinsn
)
2407 struct transformed_insns
*pti
;
2409 if (inside_insn_group
)
2412 pti
= XNEW (struct transformed_insns
);
2413 pti
->vinsn_old
= expr_old_vinsn
;
2414 pti
->vinsn_new
= EXPR_VINSN (expr
);
2415 pti
->type
= trans_type
;
2416 pti
->was_target_conflict
= was_target_conflict
;
2417 pti
->ds
= EXPR_SPEC_DONE_DS (expr
);
2418 pti
->needs_check
= EXPR_NEEDS_SPEC_CHECK_P (expr
);
2419 vinsn_attach (pti
->vinsn_old
);
2420 vinsn_attach (pti
->vinsn_new
);
2421 *((struct transformed_insns
**)
2422 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn
),
2423 pti
, VINSN_HASH_RTX (expr_old_vinsn
),
2427 /* Same as moveup_expr, but first looks up the result of
2428 transformation in caches. */
2429 static enum MOVEUP_EXPR_CODE
2430 moveup_expr_cached (expr_t expr
, insn_t insn
, bool inside_insn_group
)
2432 enum MOVEUP_EXPR_CODE res
;
2433 bool got_answer
= false;
2435 if (sched_verbose
>= 6)
2437 sel_print ("Moving ");
2439 sel_print (" through %d: ", INSN_UID (insn
));
2442 if (try_bitmap_cache (expr
, insn
, inside_insn_group
, &res
))
2443 /* When inside insn group, we do not want remove stores conflicting
2444 with previosly issued loads. */
2445 got_answer
= ! inside_insn_group
|| res
!= MOVEUP_EXPR_NULL
;
2446 else if (try_transformation_cache (expr
, insn
, &res
))
2451 /* Invoke moveup_expr and record the results. */
2452 vinsn_t expr_old_vinsn
= EXPR_VINSN (expr
);
2453 ds_t expr_old_spec_ds
= EXPR_SPEC_DONE_DS (expr
);
2454 int expr_uid
= INSN_UID (VINSN_INSN_RTX (expr_old_vinsn
));
2455 bool unique_p
= VINSN_UNIQUE_P (expr_old_vinsn
);
2456 enum local_trans_type trans_type
= TRANS_SUBSTITUTION
;
2458 /* ??? Invent something better than this. We can't allow old_vinsn
2459 to go, we need it for the history vector. */
2460 vinsn_attach (expr_old_vinsn
);
2462 res
= moveup_expr (expr
, insn
, inside_insn_group
,
2466 case MOVEUP_EXPR_NULL
:
2467 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2468 if (sched_verbose
>= 6)
2469 sel_print ("removed\n");
2472 case MOVEUP_EXPR_SAME
:
2473 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2474 if (sched_verbose
>= 6)
2475 sel_print ("unchanged\n");
2478 case MOVEUP_EXPR_AS_RHS
:
2479 gcc_assert (!unique_p
|| inside_insn_group
);
2480 update_bitmap_cache (expr
, insn
, inside_insn_group
, res
);
2481 if (sched_verbose
>= 6)
2482 sel_print ("unchanged (as RHS)\n");
2485 case MOVEUP_EXPR_CHANGED
:
2486 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr
)) != expr_uid
2487 || EXPR_SPEC_DONE_DS (expr
) != expr_old_spec_ds
);
2488 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr
),
2489 INSN_UID (insn
), trans_type
,
2490 expr_old_vinsn
, EXPR_VINSN (expr
),
2492 update_transformation_cache (expr
, insn
, inside_insn_group
,
2493 trans_type
, expr_old_vinsn
);
2494 if (sched_verbose
>= 6)
2496 sel_print ("changed: ");
2505 vinsn_detach (expr_old_vinsn
);
2511 /* Moves an av set AVP up through INSN, performing necessary
2514 moveup_set_expr (av_set_t
*avp
, insn_t insn
, bool inside_insn_group
)
2519 FOR_EACH_EXPR_1 (expr
, i
, avp
)
2522 switch (moveup_expr_cached (expr
, insn
, inside_insn_group
))
2524 case MOVEUP_EXPR_SAME
:
2525 case MOVEUP_EXPR_AS_RHS
:
2528 case MOVEUP_EXPR_NULL
:
2529 av_set_iter_remove (&i
);
2532 case MOVEUP_EXPR_CHANGED
:
2533 expr
= merge_with_other_exprs (avp
, &i
, expr
);
2542 /* Moves AVP set along PATH. */
2544 moveup_set_inside_insn_group (av_set_t
*avp
, ilist_t path
)
2548 if (sched_verbose
>= 6)
2549 sel_print ("Moving expressions up in the insn group...\n");
2552 last_cycle
= INSN_SCHED_CYCLE (ILIST_INSN (path
));
2554 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2556 moveup_set_expr (avp
, ILIST_INSN (path
), true);
2557 path
= ILIST_NEXT (path
);
2561 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2563 equal_after_moveup_path_p (expr_t expr
, ilist_t path
, expr_t expr_vliw
)
2565 expr_def _tmp
, *tmp
= &_tmp
;
2569 copy_expr_onside (tmp
, expr
);
2570 last_cycle
= path
? INSN_SCHED_CYCLE (ILIST_INSN (path
)) : 0;
2573 && INSN_SCHED_CYCLE (ILIST_INSN (path
)) == last_cycle
)
2575 res
= (moveup_expr_cached (tmp
, ILIST_INSN (path
), true)
2576 != MOVEUP_EXPR_NULL
);
2577 path
= ILIST_NEXT (path
);
2582 vinsn_t tmp_vinsn
= EXPR_VINSN (tmp
);
2583 vinsn_t expr_vliw_vinsn
= EXPR_VINSN (expr_vliw
);
2585 if (tmp_vinsn
!= expr_vliw_vinsn
)
2586 res
= vinsn_equal_p (tmp_vinsn
, expr_vliw_vinsn
);
2594 /* Functions that compute av and lv sets. */
2596 /* Returns true if INSN is not a downward continuation of the given path P in
2597 the current stage. */
2599 is_ineligible_successor (insn_t insn
, ilist_t p
)
2603 /* Check if insn is not deleted. */
2604 if (PREV_INSN (insn
) && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2606 else if (NEXT_INSN (insn
) && PREV_INSN (NEXT_INSN (insn
)) != insn
)
2609 /* If it's the first insn visited, then the successor is ok. */
2613 prev_insn
= ILIST_INSN (p
);
2615 if (/* a backward edge. */
2616 INSN_SEQNO (insn
) < INSN_SEQNO (prev_insn
)
2617 /* is already visited. */
2618 || (INSN_SEQNO (insn
) == INSN_SEQNO (prev_insn
)
2619 && (ilist_is_in_p (p
, insn
)
2620 /* We can reach another fence here and still seqno of insn
2621 would be equal to seqno of prev_insn. This is possible
2622 when prev_insn is a previously created bookkeeping copy.
2623 In that case it'd get a seqno of insn. Thus, check here
2624 whether insn is in current fence too. */
2625 || IN_CURRENT_FENCE_P (insn
)))
2626 /* Was already scheduled on this round. */
2627 || (INSN_SEQNO (insn
) > INSN_SEQNO (prev_insn
)
2628 && IN_CURRENT_FENCE_P (insn
))
2629 /* An insn from another fence could also be
2630 scheduled earlier even if this insn is not in
2631 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2633 && INSN_SCHED_TIMES (insn
) > 0))
2639 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2640 of handling multiple successors and properly merging its av_sets. P is
2641 the current path traversed. WS is the size of lookahead window.
2642 Return the av set computed. */
2644 compute_av_set_at_bb_end (insn_t insn
, ilist_t p
, int ws
)
2646 struct succs_info
*sinfo
;
2647 av_set_t expr_in_all_succ_branches
= NULL
;
2649 insn_t succ
, zero_succ
= NULL
;
2650 av_set_t av1
= NULL
;
2652 gcc_assert (sel_bb_end_p (insn
));
2654 /* Find different kind of successors needed for correct computing of
2655 SPEC and TARGET_AVAILABLE attributes. */
2656 sinfo
= compute_succs_info (insn
, SUCCS_NORMAL
);
2659 if (sched_verbose
>= 6)
2661 sel_print ("successors of bb end (%d): ", INSN_UID (insn
));
2662 dump_insn_vector (sinfo
->succs_ok
);
2664 if (sinfo
->succs_ok_n
!= sinfo
->all_succs_n
)
2665 sel_print ("real successors num: %d\n", sinfo
->all_succs_n
);
2668 /* Add insn to to the tail of current path. */
2669 ilist_add (&p
, insn
);
2671 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_ok
, is
, succ
); is
++)
2675 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2676 succ_set
= compute_av_set_inside_bb (succ
, p
, ws
, true);
2678 av_set_split_usefulness (succ_set
,
2679 VEC_index (int, sinfo
->probs_ok
, is
),
2682 if (sinfo
->all_succs_n
> 1
2683 && sinfo
->all_succs_n
== sinfo
->succs_ok_n
)
2685 /* Find EXPR'es that came from *all* successors and save them
2686 into expr_in_all_succ_branches. This set will be used later
2687 for calculating speculation attributes of EXPR'es. */
2690 expr_in_all_succ_branches
= av_set_copy (succ_set
);
2692 /* Remember the first successor for later. */
2700 FOR_EACH_EXPR_1 (expr
, i
, &expr_in_all_succ_branches
)
2701 if (!av_set_is_in_p (succ_set
, EXPR_VINSN (expr
)))
2702 av_set_iter_remove (&i
);
2706 /* Union the av_sets. Check liveness restrictions on target registers
2707 in special case of two successors. */
2708 if (sinfo
->succs_ok_n
== 2 && is
== 1)
2710 basic_block bb0
= BLOCK_FOR_INSN (zero_succ
);
2711 basic_block bb1
= BLOCK_FOR_INSN (succ
);
2713 gcc_assert (BB_LV_SET_VALID_P (bb0
) && BB_LV_SET_VALID_P (bb1
));
2714 av_set_union_and_live (&av1
, &succ_set
,
2720 av_set_union_and_clear (&av1
, &succ_set
, insn
);
2723 /* Check liveness restrictions via hard way when there are more than
2725 if (sinfo
->succs_ok_n
> 2)
2726 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_ok
, is
, succ
); is
++)
2728 basic_block succ_bb
= BLOCK_FOR_INSN (succ
);
2730 gcc_assert (BB_LV_SET_VALID_P (succ_bb
));
2731 mark_unavailable_targets (av1
, BB_AV_SET (succ_bb
),
2732 BB_LV_SET (succ_bb
));
2735 /* Finally, check liveness restrictions on paths leaving the region. */
2736 if (sinfo
->all_succs_n
> sinfo
->succs_ok_n
)
2737 for (is
= 0; VEC_iterate (rtx
, sinfo
->succs_other
, is
, succ
); is
++)
2738 mark_unavailable_targets
2739 (av1
, NULL
, BB_LV_SET (BLOCK_FOR_INSN (succ
)));
2741 if (sinfo
->all_succs_n
> 1)
2746 /* Increase the spec attribute of all EXPR'es that didn't come
2747 from all successors. */
2748 FOR_EACH_EXPR (expr
, i
, av1
)
2749 if (!av_set_is_in_p (expr_in_all_succ_branches
, EXPR_VINSN (expr
)))
2752 av_set_clear (&expr_in_all_succ_branches
);
2754 /* Do not move conditional branches through other
2755 conditional branches. So, remove all conditional
2756 branches from av_set if current operator is a conditional
2758 av_set_substract_cond_branches (&av1
);
2762 free_succs_info (sinfo
);
2764 if (sched_verbose
>= 6)
2766 sel_print ("av_succs (%d): ", INSN_UID (insn
));
2774 /* This function computes av_set for the FIRST_INSN by dragging valid
2775 av_set through all basic block insns either from the end of basic block
2776 (computed using compute_av_set_at_bb_end) or from the insn on which
2777 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2778 below the basic block and handling conditional branches.
2779 FIRST_INSN - the basic block head, P - path consisting of the insns
2780 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2781 and bb ends are added to the path), WS - current window size,
2782 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2784 compute_av_set_inside_bb (insn_t first_insn
, ilist_t p
, int ws
,
2789 insn_t bb_end
= sel_bb_end (BLOCK_FOR_INSN (first_insn
));
2790 insn_t after_bb_end
= NEXT_INSN (bb_end
);
2793 basic_block cur_bb
= BLOCK_FOR_INSN (first_insn
);
2795 /* Return NULL if insn is not on the legitimate downward path. */
2796 if (is_ineligible_successor (first_insn
, p
))
2798 if (sched_verbose
>= 6)
2799 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn
));
2804 /* If insn already has valid av(insn) computed, just return it. */
2805 if (AV_SET_VALID_P (first_insn
))
2809 if (sel_bb_head_p (first_insn
))
2810 av_set
= BB_AV_SET (BLOCK_FOR_INSN (first_insn
));
2814 if (sched_verbose
>= 6)
2816 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn
));
2817 dump_av_set (av_set
);
2821 return need_copy_p
? av_set_copy (av_set
) : av_set
;
2824 ilist_add (&p
, first_insn
);
2826 /* As the result after this loop have completed, in LAST_INSN we'll
2827 have the insn which has valid av_set to start backward computation
2828 from: it either will be NULL because on it the window size was exceeded
2829 or other valid av_set as returned by compute_av_set for the last insn
2830 of the basic block. */
2831 for (last_insn
= first_insn
; last_insn
!= after_bb_end
;
2832 last_insn
= NEXT_INSN (last_insn
))
2834 /* We may encounter valid av_set not only on bb_head, but also on
2835 those insns on which previously MAX_WS was exceeded. */
2836 if (AV_SET_VALID_P (last_insn
))
2838 if (sched_verbose
>= 6)
2839 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn
));
2843 /* The special case: the last insn of the BB may be an
2844 ineligible_successor due to its SEQ_NO that was set on
2845 it as a bookkeeping. */
2846 if (last_insn
!= first_insn
2847 && is_ineligible_successor (last_insn
, p
))
2849 if (sched_verbose
>= 6)
2850 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn
));
2854 if (end_ws
> max_ws
)
2856 /* We can reach max lookahead size at bb_header, so clean av_set
2858 INSN_WS_LEVEL (last_insn
) = global_level
;
2860 if (sched_verbose
>= 6)
2861 sel_print ("Insn %d is beyond the software lookahead window size\n",
2862 INSN_UID (last_insn
));
2869 /* Get the valid av_set into AV above the LAST_INSN to start backward
2870 computation from. It either will be empty av_set or av_set computed from
2871 the successors on the last insn of the current bb. */
2872 if (last_insn
!= after_bb_end
)
2876 /* This is needed only to obtain av_sets that are identical to
2877 those computed by the old compute_av_set version. */
2878 if (last_insn
== first_insn
&& !INSN_NOP_P (last_insn
))
2879 av_set_add (&av
, INSN_EXPR (last_insn
));
2882 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2883 av
= compute_av_set_at_bb_end (bb_end
, p
, end_ws
);
2885 /* Compute av_set in AV starting from below the LAST_INSN up to
2886 location above the FIRST_INSN. */
2887 for (cur_insn
= PREV_INSN (last_insn
); cur_insn
!= PREV_INSN (first_insn
);
2888 cur_insn
= PREV_INSN (cur_insn
))
2889 if (!INSN_NOP_P (cur_insn
))
2893 moveup_set_expr (&av
, cur_insn
, false);
2895 /* If the expression for CUR_INSN is already in the set,
2896 replace it by the new one. */
2897 expr
= av_set_lookup (av
, INSN_VINSN (cur_insn
));
2901 copy_expr (expr
, INSN_EXPR (cur_insn
));
2904 av_set_add (&av
, INSN_EXPR (cur_insn
));
2907 /* Clear stale bb_av_set. */
2908 if (sel_bb_head_p (first_insn
))
2910 av_set_clear (&BB_AV_SET (cur_bb
));
2911 BB_AV_SET (cur_bb
) = need_copy_p
? av_set_copy (av
) : av
;
2912 BB_AV_LEVEL (cur_bb
) = global_level
;
2915 if (sched_verbose
>= 6)
2917 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn
));
2926 /* Compute av set before INSN.
2927 INSN - the current operation (actual rtx INSN)
2928 P - the current path, which is list of insns visited so far
2929 WS - software lookahead window size.
2930 UNIQUE_P - TRUE, if returned av_set will be changed, hence
2931 if we want to save computed av_set in s_i_d, we should make a copy of it.
2933 In the resulting set we will have only expressions that don't have delay
2934 stalls and nonsubstitutable dependences. */
2936 compute_av_set (insn_t insn
, ilist_t p
, int ws
, bool unique_p
)
2938 return compute_av_set_inside_bb (insn
, p
, ws
, unique_p
);
2941 /* Propagate a liveness set LV through INSN. */
2943 propagate_lv_set (regset lv
, insn_t insn
)
2945 gcc_assert (INSN_P (insn
));
2947 if (INSN_NOP_P (insn
))
2950 df_simulate_one_insn (BLOCK_FOR_INSN (insn
), insn
, lv
);
2953 /* Return livness set at the end of BB. */
2955 compute_live_after_bb (basic_block bb
)
2959 regset lv
= get_clear_regset_from_pool ();
2961 gcc_assert (!ignore_first
);
2963 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
2964 if (sel_bb_empty_p (e
->dest
))
2966 if (! BB_LV_SET_VALID_P (e
->dest
))
2969 gcc_assert (BB_LV_SET (e
->dest
) == NULL
);
2970 BB_LV_SET (e
->dest
) = compute_live_after_bb (e
->dest
);
2971 BB_LV_SET_VALID_P (e
->dest
) = true;
2973 IOR_REG_SET (lv
, BB_LV_SET (e
->dest
));
2976 IOR_REG_SET (lv
, compute_live (sel_bb_head (e
->dest
)));
2981 /* Compute the set of all live registers at the point before INSN and save
2982 it at INSN if INSN is bb header. */
2984 compute_live (insn_t insn
)
2986 basic_block bb
= BLOCK_FOR_INSN (insn
);
2990 /* Return the valid set if we're already on it. */
2995 if (sel_bb_head_p (insn
) && BB_LV_SET_VALID_P (bb
))
2996 src
= BB_LV_SET (bb
);
2999 gcc_assert (in_current_region_p (bb
));
3000 if (INSN_LIVE_VALID_P (insn
))
3001 src
= INSN_LIVE (insn
);
3006 lv
= get_regset_from_pool ();
3007 COPY_REG_SET (lv
, src
);
3009 if (sel_bb_head_p (insn
) && ! BB_LV_SET_VALID_P (bb
))
3011 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3012 BB_LV_SET_VALID_P (bb
) = true;
3015 return_regset_to_pool (lv
);
3020 /* We've skipped the wrong lv_set. Don't skip the right one. */
3021 ignore_first
= false;
3022 gcc_assert (in_current_region_p (bb
));
3024 /* Find a valid LV set in this block or below, if needed.
3025 Start searching from the next insn: either ignore_first is true, or
3026 INSN doesn't have a correct live set. */
3027 temp
= NEXT_INSN (insn
);
3028 final
= NEXT_INSN (BB_END (bb
));
3029 while (temp
!= final
&& ! INSN_LIVE_VALID_P (temp
))
3030 temp
= NEXT_INSN (temp
);
3033 lv
= compute_live_after_bb (bb
);
3034 temp
= PREV_INSN (temp
);
3038 lv
= get_regset_from_pool ();
3039 COPY_REG_SET (lv
, INSN_LIVE (temp
));
3042 /* Put correct lv sets on the insns which have bad sets. */
3043 final
= PREV_INSN (insn
);
3044 while (temp
!= final
)
3046 propagate_lv_set (lv
, temp
);
3047 COPY_REG_SET (INSN_LIVE (temp
), lv
);
3048 INSN_LIVE_VALID_P (temp
) = true;
3049 temp
= PREV_INSN (temp
);
3052 /* Also put it in a BB. */
3053 if (sel_bb_head_p (insn
))
3055 basic_block bb
= BLOCK_FOR_INSN (insn
);
3057 COPY_REG_SET (BB_LV_SET (bb
), lv
);
3058 BB_LV_SET_VALID_P (bb
) = true;
3061 /* We return LV to the pool, but will not clear it there. Thus we can
3062 legimatelly use LV till the next use of regset_pool_get (). */
3063 return_regset_to_pool (lv
);
3067 /* Update liveness sets for INSN. */
3069 update_liveness_on_insn (rtx insn
)
3071 ignore_first
= true;
3072 compute_live (insn
);
3075 /* Compute liveness below INSN and write it into REGS. */
3077 compute_live_below_insn (rtx insn
, regset regs
)
3082 FOR_EACH_SUCC_1 (succ
, si
, insn
, SUCCS_ALL
)
3083 IOR_REG_SET (regs
, compute_live (succ
));
3086 /* Update the data gathered in av and lv sets starting from INSN. */
3088 update_data_sets (rtx insn
)
3090 update_liveness_on_insn (insn
);
3091 if (sel_bb_head_p (insn
))
3093 gcc_assert (AV_LEVEL (insn
) != 0);
3094 BB_AV_LEVEL (BLOCK_FOR_INSN (insn
)) = -1;
3095 compute_av_set (insn
, NULL
, 0, 0);
3100 /* Helper for move_op () and find_used_regs ().
3101 Return speculation type for which a check should be created on the place
3102 of INSN. EXPR is one of the original ops we are searching for. */
3104 get_spec_check_type_for_insn (insn_t insn
, expr_t expr
)
3107 ds_t already_checked_ds
= EXPR_SPEC_DONE_DS (INSN_EXPR (insn
));
3109 to_check_ds
= EXPR_SPEC_TO_CHECK_DS (expr
);
3111 if (targetm
.sched
.get_insn_checked_ds
)
3112 already_checked_ds
|= targetm
.sched
.get_insn_checked_ds (insn
);
3114 if (spec_info
!= NULL
3115 && (spec_info
->flags
& SEL_SCHED_SPEC_DONT_CHECK_CONTROL
))
3116 already_checked_ds
|= BEGIN_CONTROL
;
3118 already_checked_ds
= ds_get_speculation_types (already_checked_ds
);
3120 to_check_ds
&= ~already_checked_ds
;
3125 /* Find the set of registers that are unavailable for storing expres
3126 while moving ORIG_OPS up on the path starting from INSN due to
3127 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3129 All the original operations found during the traversal are saved in the
3130 ORIGINAL_INSNS list.
3132 REG_RENAME_P denotes the set of hardware registers that
3133 can not be used with renaming due to the register class restrictions,
3134 mode restrictions and other (the register we'll choose should be
3135 compatible class with the original uses, shouldn't be in call_used_regs,
3136 should be HARD_REGNO_RENAME_OK etc).
3138 Returns TRUE if we've found all original insns, FALSE otherwise.
3140 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3141 to traverse the code motion paths. This helper function finds registers
3142 that are not available for storing expres while moving ORIG_OPS up on the
3143 path starting from INSN. A register considered as used on the moving path,
3144 if one of the following conditions is not satisfied:
3146 (1) a register not set or read on any path from xi to an instance of
3147 the original operation,
3148 (2) not among the live registers of the point immediately following the
3149 first original operation on a given downward path, except for the
3150 original target register of the operation,
3151 (3) not live on the other path of any conditional branch that is passed
3152 by the operation, in case original operations are not present on
3153 both paths of the conditional branch.
3155 All the original operations found during the traversal are saved in the
3156 ORIGINAL_INSNS list.
3158 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3159 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3160 to unavailable hard regs at the point original operation is found. */
3163 find_used_regs (insn_t insn
, av_set_t orig_ops
, regset used_regs
,
3164 struct reg_rename
*reg_rename_p
, def_list_t
*original_insns
)
3166 def_list_iterator i
;
3169 bool needs_spec_check_p
= false;
3171 av_set_iterator expr_iter
;
3172 struct fur_static_params sparams
;
3173 struct cmpd_local_params lparams
;
3175 /* We haven't visited any blocks yet. */
3176 bitmap_clear (code_motion_visited_blocks
);
3178 /* Init parameters for code_motion_path_driver. */
3179 sparams
.crosses_call
= false;
3180 sparams
.original_insns
= original_insns
;
3181 sparams
.used_regs
= used_regs
;
3183 /* Set the appropriate hooks and data. */
3184 code_motion_path_driver_info
= &fur_hooks
;
3186 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
3188 reg_rename_p
->crosses_call
|= sparams
.crosses_call
;
3190 gcc_assert (res
== 1);
3191 gcc_assert (original_insns
&& *original_insns
);
3193 /* ??? We calculate whether an expression needs a check when computing
3194 av sets. This information is not as precise as it could be due to
3195 merging this bit in merge_expr. We can do better in find_used_regs,
3196 but we want to avoid multiple traversals of the same code motion
3198 FOR_EACH_EXPR (expr
, expr_iter
, orig_ops
)
3199 needs_spec_check_p
|= EXPR_NEEDS_SPEC_CHECK_P (expr
);
3201 /* Mark hardware regs in REG_RENAME_P that are not suitable
3202 for renaming expr in INSN due to hardware restrictions (register class,
3203 modes compatibility etc). */
3204 FOR_EACH_DEF (def
, i
, *original_insns
)
3206 vinsn_t vinsn
= INSN_VINSN (def
->orig_insn
);
3208 if (VINSN_SEPARABLE_P (vinsn
))
3209 mark_unavailable_hard_regs (def
, reg_rename_p
, used_regs
);
3211 /* Do not allow clobbering of ld.[sa] address in case some of the
3212 original operations need a check. */
3213 if (needs_spec_check_p
)
3214 IOR_REG_SET (used_regs
, VINSN_REG_USES (vinsn
));
3221 /* Functions to choose the best insn from available ones. */
3223 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3225 sel_target_adjust_priority (expr_t expr
)
3227 int priority
= EXPR_PRIORITY (expr
);
3230 if (targetm
.sched
.adjust_priority
)
3231 new_priority
= targetm
.sched
.adjust_priority (EXPR_INSN_RTX (expr
), priority
);
3233 new_priority
= priority
;
3235 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3236 EXPR_PRIORITY_ADJ (expr
) = new_priority
- EXPR_PRIORITY (expr
);
3238 gcc_assert (EXPR_PRIORITY_ADJ (expr
) >= 0);
3240 if (sched_verbose
>= 2)
3241 sel_print ("sel_target_adjust_priority: insn %d, %d +%d = %d.\n",
3242 INSN_UID (EXPR_INSN_RTX (expr
)), EXPR_PRIORITY (expr
),
3243 EXPR_PRIORITY_ADJ (expr
), new_priority
);
3245 return new_priority
;
3248 /* Rank two available exprs for schedule. Never return 0 here. */
3250 sel_rank_for_schedule (const void *x
, const void *y
)
3252 expr_t tmp
= *(const expr_t
*) y
;
3253 expr_t tmp2
= *(const expr_t
*) x
;
3254 insn_t tmp_insn
, tmp2_insn
;
3255 vinsn_t tmp_vinsn
, tmp2_vinsn
;
3258 tmp_vinsn
= EXPR_VINSN (tmp
);
3259 tmp2_vinsn
= EXPR_VINSN (tmp2
);
3260 tmp_insn
= EXPR_INSN_RTX (tmp
);
3261 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3263 /* Prefer SCHED_GROUP_P insns to any others. */
3264 if (SCHED_GROUP_P (tmp_insn
) != SCHED_GROUP_P (tmp2_insn
))
3266 if (VINSN_UNIQUE_P (tmp_vinsn
) && VINSN_UNIQUE_P (tmp2_vinsn
))
3267 return SCHED_GROUP_P (tmp2_insn
) ? 1 : -1;
3269 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3270 cannot be cloned. */
3271 if (VINSN_UNIQUE_P (tmp2_vinsn
))
3276 /* Discourage scheduling of speculative checks. */
3277 val
= (sel_insn_is_speculation_check (tmp_insn
)
3278 - sel_insn_is_speculation_check (tmp2_insn
));
3282 /* Prefer not scheduled insn over scheduled one. */
3283 if (EXPR_SCHED_TIMES (tmp
) > 0 || EXPR_SCHED_TIMES (tmp2
) > 0)
3285 val
= EXPR_SCHED_TIMES (tmp
) - EXPR_SCHED_TIMES (tmp2
);
3290 /* Prefer jump over non-jump instruction. */
3291 if (control_flow_insn_p (tmp_insn
) && !control_flow_insn_p (tmp2_insn
))
3293 else if (control_flow_insn_p (tmp2_insn
) && !control_flow_insn_p (tmp_insn
))
3296 /* Prefer an expr with greater priority. */
3297 if (EXPR_USEFULNESS (tmp
) != 0 && EXPR_USEFULNESS (tmp2
) != 0)
3299 int p2
= EXPR_PRIORITY (tmp2
) + EXPR_PRIORITY_ADJ (tmp2
),
3300 p1
= EXPR_PRIORITY (tmp
) + EXPR_PRIORITY_ADJ (tmp
);
3302 val
= p2
* EXPR_USEFULNESS (tmp2
) - p1
* EXPR_USEFULNESS (tmp
);
3305 val
= EXPR_PRIORITY (tmp2
) - EXPR_PRIORITY (tmp
)
3306 + EXPR_PRIORITY_ADJ (tmp2
) - EXPR_PRIORITY_ADJ (tmp
);
3310 if (spec_info
!= NULL
&& spec_info
->mask
!= 0)
3311 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3317 ds1
= EXPR_SPEC_DONE_DS (tmp
);
3319 dw1
= ds_weak (ds1
);
3323 ds2
= EXPR_SPEC_DONE_DS (tmp2
);
3325 dw2
= ds_weak (ds2
);
3330 if (dw
> (NO_DEP_WEAK
/ 8) || dw
< -(NO_DEP_WEAK
/ 8))
3334 tmp_insn
= EXPR_INSN_RTX (tmp
);
3335 tmp2_insn
= EXPR_INSN_RTX (tmp2
);
3337 /* Prefer an old insn to a bookkeeping insn. */
3338 if (INSN_UID (tmp_insn
) < first_emitted_uid
3339 && INSN_UID (tmp2_insn
) >= first_emitted_uid
)
3341 if (INSN_UID (tmp_insn
) >= first_emitted_uid
3342 && INSN_UID (tmp2_insn
) < first_emitted_uid
)
3345 /* Prefer an insn with smaller UID, as a last resort.
3346 We can't safely use INSN_LUID as it is defined only for those insns
3347 that are in the stream. */
3348 return INSN_UID (tmp_insn
) - INSN_UID (tmp2_insn
);
3351 /* Filter out expressions from av set pointed to by AV_PTR
3352 that are pipelined too many times. */
3354 process_pipelined_exprs (av_set_t
*av_ptr
)
3359 /* Don't pipeline already pipelined code as that would increase
3360 number of unnecessary register moves. */
3361 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3363 if (EXPR_SCHED_TIMES (expr
)
3364 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES
))
3365 av_set_iter_remove (&si
);
3369 /* Filter speculative insns from AV_PTR if we don't want them. */
3371 process_spec_exprs (av_set_t
*av_ptr
)
3373 bool try_data_p
= true;
3374 bool try_control_p
= true;
3378 if (spec_info
== NULL
)
3381 /* Scan *AV_PTR to find out if we want to consider speculative
3382 instructions for scheduling. */
3383 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3387 ds
= EXPR_SPEC_DONE_DS (expr
);
3389 /* The probability of a success is too low - don't speculate. */
3390 if ((ds
& SPECULATIVE
)
3391 && (ds_weak (ds
) < spec_info
->data_weakness_cutoff
3392 || EXPR_USEFULNESS (expr
) < spec_info
->control_weakness_cutoff
3393 || (pipelining_p
&& false
3395 && (ds
& CONTROL_SPEC
))))
3397 av_set_iter_remove (&si
);
3401 if ((spec_info
->flags
& PREFER_NON_DATA_SPEC
)
3402 && !(ds
& BEGIN_DATA
))
3405 if ((spec_info
->flags
& PREFER_NON_CONTROL_SPEC
)
3406 && !(ds
& BEGIN_CONTROL
))
3407 try_control_p
= false;
3410 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3414 ds
= EXPR_SPEC_DONE_DS (expr
);
3416 if (ds
& SPECULATIVE
)
3418 if ((ds
& BEGIN_DATA
) && !try_data_p
)
3419 /* We don't want any data speculative instructions right
3421 av_set_iter_remove (&si
);
3423 if ((ds
& BEGIN_CONTROL
) && !try_control_p
)
3424 /* We don't want any control speculative instructions right
3426 av_set_iter_remove (&si
);
3431 /* Search for any use-like insns in AV_PTR and decide on scheduling
3432 them. Return one when found, and NULL otherwise.
3433 Note that we check here whether a USE could be scheduled to avoid
3434 an infinite loop later. */
3436 process_use_exprs (av_set_t
*av_ptr
)
3440 bool uses_present_p
= false;
3441 bool try_uses_p
= true;
3443 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3445 /* This will also initialize INSN_CODE for later use. */
3446 if (recog_memoized (EXPR_INSN_RTX (expr
)) < 0)
3448 /* If we have a USE in *AV_PTR that was not scheduled yet,
3449 do so because it will do good only. */
3450 if (EXPR_SCHED_TIMES (expr
) <= 0)
3452 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3455 av_set_iter_remove (&si
);
3459 gcc_assert (pipelining_p
);
3461 uses_present_p
= true;
3470 /* If we don't want to schedule any USEs right now and we have some
3471 in *AV_PTR, remove them, else just return the first one found. */
3474 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3475 if (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0)
3476 av_set_iter_remove (&si
);
3480 FOR_EACH_EXPR_1 (expr
, si
, av_ptr
)
3482 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr
)) < 0);
3484 if (EXPR_TARGET_AVAILABLE (expr
) == 1)
3487 av_set_iter_remove (&si
);
3495 /* Lookup EXPR in VINSN_VEC and return TRUE if found. */
3497 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec
, expr_t expr
)
3502 for (n
= 0; VEC_iterate (vinsn_t
, vinsn_vec
, n
, vinsn
); n
++)
3503 if (VINSN_SEPARABLE_P (vinsn
))
3505 if (vinsn_equal_p (vinsn
, EXPR_VINSN (expr
)))
3510 /* For non-separable instructions, the blocking insn can have
3511 another pattern due to substitution, and we can't choose
3512 different register as in the above case. Check all registers
3513 being written instead. */
3514 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn
),
3515 VINSN_REG_SETS (EXPR_VINSN (expr
))))
3522 #ifdef ENABLE_CHECKING
3523 /* Return true if either of expressions from ORIG_OPS can be blocked
3524 by previously created bookkeeping code. STATIC_PARAMS points to static
3525 parameters of move_op. */
3527 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops
, void *static_params
)
3530 av_set_iterator iter
;
3531 moveop_static_params_p sparams
;
3533 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3534 created while scheduling on another fence. */
3535 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3536 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3539 gcc_assert (code_motion_path_driver_info
== &move_op_hooks
);
3540 sparams
= (moveop_static_params_p
) static_params
;
3542 /* Expressions can be also blocked by bookkeeping created during current
3544 if (bitmap_bit_p (current_copies
, INSN_UID (sparams
->failed_insn
)))
3545 FOR_EACH_EXPR (expr
, iter
, orig_ops
)
3546 if (moveup_expr_cached (expr
, sparams
->failed_insn
, false) != MOVEUP_EXPR_NULL
)
3549 /* Expressions in ORIG_OPS may have wrong destination register due to
3550 renaming. Check with the right register instead. */
3551 if (sparams
->dest
&& REG_P (sparams
->dest
))
3553 unsigned regno
= REGNO (sparams
->dest
);
3554 vinsn_t failed_vinsn
= INSN_VINSN (sparams
->failed_insn
);
3556 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn
), regno
)
3557 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn
), regno
)
3558 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn
), regno
))
3566 /* Clear VINSN_VEC and detach vinsns. */
3568 vinsn_vec_clear (vinsn_vec_t
*vinsn_vec
)
3570 unsigned len
= VEC_length (vinsn_t
, *vinsn_vec
);
3576 for (n
= 0; VEC_iterate (vinsn_t
, *vinsn_vec
, n
, vinsn
); n
++)
3577 vinsn_detach (vinsn
);
3578 VEC_block_remove (vinsn_t
, *vinsn_vec
, 0, len
);
3582 /* Add the vinsn of EXPR to the VINSN_VEC. */
3584 vinsn_vec_add (vinsn_vec_t
*vinsn_vec
, expr_t expr
)
3586 vinsn_attach (EXPR_VINSN (expr
));
3587 VEC_safe_push (vinsn_t
, heap
, *vinsn_vec
, EXPR_VINSN (expr
));
3590 /* Free the vector representing blocked expressions. */
3592 vinsn_vec_free (vinsn_vec_t
*vinsn_vec
)
3595 VEC_free (vinsn_t
, heap
, *vinsn_vec
);
3598 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3600 void sel_add_to_insn_priority (rtx insn
, int amount
)
3602 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)) += amount
;
3604 if (sched_verbose
>= 2)
3605 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3606 INSN_UID (insn
), amount
, EXPR_PRIORITY (INSN_EXPR (insn
)),
3607 EXPR_PRIORITY_ADJ (INSN_EXPR (insn
)));
3610 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3611 true if there is something to schedule. BNDS and FENCE are current
3612 boundaries and fence, respectively. If we need to stall for some cycles
3613 before an expr from AV would become available, write this number to
3616 fill_vec_av_set (av_set_t av
, blist_t bnds
, fence_t fence
,
3621 int sched_next_worked
= 0, stalled
, n
;
3622 static int av_max_prio
, est_ticks_till_branch
;
3623 int min_need_stall
= -1;
3624 deps_t dc
= BND_DC (BLIST_BND (bnds
));
3626 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3627 already scheduled. */
3631 /* Empty vector from the previous stuff. */
3632 if (VEC_length (expr_t
, vec_av_set
) > 0)
3633 VEC_block_remove (expr_t
, vec_av_set
, 0, VEC_length (expr_t
, vec_av_set
));
3635 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3637 gcc_assert (VEC_empty (expr_t
, vec_av_set
));
3638 FOR_EACH_EXPR (expr
, si
, av
)
3640 VEC_safe_push (expr_t
, heap
, vec_av_set
, expr
);
3642 gcc_assert (EXPR_PRIORITY_ADJ (expr
) == 0 || *pneed_stall
);
3644 /* Adjust priority using target backend hook. */
3645 sel_target_adjust_priority (expr
);
3648 /* Sort the vector. */
3649 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3650 sizeof (expr_t
), sel_rank_for_schedule
);
3652 /* We record maximal priority of insns in av set for current instruction
3654 if (FENCE_STARTS_CYCLE_P (fence
))
3655 av_max_prio
= est_ticks_till_branch
= INT_MIN
;
3657 /* Filter out inappropriate expressions. Loop's direction is reversed to
3658 visit "best" instructions first. We assume that VEC_unordered_remove
3659 moves last element in place of one being deleted. */
3660 for (n
= VEC_length (expr_t
, vec_av_set
) - 1, stalled
= 0; n
>= 0; n
--)
3662 expr_t expr
= VEC_index (expr_t
, vec_av_set
, n
);
3663 insn_t insn
= EXPR_INSN_RTX (expr
);
3664 char target_available
;
3665 bool is_orig_reg_p
= true;
3666 int need_cycles
, new_prio
;
3668 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3669 if (FENCE_SCHED_NEXT (fence
) && insn
!= FENCE_SCHED_NEXT (fence
))
3671 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3675 /* Set number of sched_next insns (just in case there
3676 could be several). */
3677 if (FENCE_SCHED_NEXT (fence
))
3678 sched_next_worked
++;
3680 /* Check all liveness requirements and try renaming.
3681 FIXME: try to minimize calls to this. */
3682 target_available
= EXPR_TARGET_AVAILABLE (expr
);
3684 /* If insn was already scheduled on the current fence,
3685 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3686 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns
, expr
))
3687 target_available
= -1;
3689 /* If the availability of the EXPR is invalidated by the insertion of
3690 bookkeeping earlier, make sure that we won't choose this expr for
3691 scheduling if it's not separable, and if it is separable, then
3692 we have to recompute the set of available registers for it. */
3693 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns
, expr
))
3695 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3696 if (sched_verbose
>= 4)
3697 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3702 if (target_available
== true)
3704 /* Do nothing -- we can use an existing register. */
3705 is_orig_reg_p
= EXPR_SEPARABLE_P (expr
);
3707 else if (/* Non-separable instruction will never
3708 get another register. */
3709 (target_available
== false
3710 && !EXPR_SEPARABLE_P (expr
))
3711 /* Don't try to find a register for low-priority expression. */
3712 || (int) VEC_length (expr_t
, vec_av_set
) - 1 - n
>= max_insns_to_rename
3713 /* ??? FIXME: Don't try to rename data speculation. */
3714 || (EXPR_SPEC_DONE_DS (expr
) & BEGIN_DATA
)
3715 || ! find_best_reg_for_expr (expr
, bnds
, &is_orig_reg_p
))
3717 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3718 if (sched_verbose
>= 4)
3719 sel_print ("Expr %d has no suitable target register\n",
3724 /* Filter expressions that need to be renamed or speculated when
3725 pipelining, because compensating register copies or speculation
3726 checks are likely to be placed near the beginning of the loop,
3728 if (pipelining_p
&& EXPR_ORIG_SCHED_CYCLE (expr
) > 0
3729 && (!is_orig_reg_p
|| EXPR_SPEC_DONE_DS (expr
) != 0))
3731 /* Estimation of number of cycles until loop branch for
3732 renaming/speculation to be successful. */
3733 int need_n_ticks_till_branch
= sel_vinsn_cost (EXPR_VINSN (expr
));
3735 if ((int) current_loop_nest
->ninsns
< 9)
3737 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3738 if (sched_verbose
>= 4)
3739 sel_print ("Pipelining expr %d will likely cause stall\n",
3744 if ((int) current_loop_nest
->ninsns
- num_insns_scheduled
3745 < need_n_ticks_till_branch
* issue_rate
/ 2
3746 && est_ticks_till_branch
< need_n_ticks_till_branch
)
3748 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3749 if (sched_verbose
>= 4)
3750 sel_print ("Pipelining expr %d will likely cause stall\n",
3756 /* We want to schedule speculation checks as late as possible. Discard
3757 them from av set if there are instructions with higher priority. */
3758 if (sel_insn_is_speculation_check (insn
)
3759 && EXPR_PRIORITY (expr
) < av_max_prio
)
3762 min_need_stall
= min_need_stall
< 0 ? 1 : MIN (min_need_stall
, 1);
3763 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3764 if (sched_verbose
>= 4)
3765 sel_print ("Delaying speculation check %d until its first use\n",
3770 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3771 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3772 av_max_prio
= MAX (av_max_prio
, EXPR_PRIORITY (expr
));
3774 /* Don't allow any insns whose data is not yet ready.
3775 Check first whether we've already tried them and failed. */
3776 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
3778 need_cycles
= (FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3779 - FENCE_CYCLE (fence
));
3780 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3781 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3782 EXPR_PRIORITY (expr
) + need_cycles
);
3784 if (need_cycles
> 0)
3787 min_need_stall
= (min_need_stall
< 0
3789 : MIN (min_need_stall
, need_cycles
));
3790 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3792 if (sched_verbose
>= 4)
3793 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3795 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3800 /* Now resort to dependence analysis to find whether EXPR might be
3801 stalled due to dependencies from FENCE's context. */
3802 need_cycles
= tick_check_p (expr
, dc
, fence
);
3803 new_prio
= EXPR_PRIORITY (expr
) + EXPR_PRIORITY_ADJ (expr
) + need_cycles
;
3805 if (EXPR_ORIG_SCHED_CYCLE (expr
) <= 0)
3806 est_ticks_till_branch
= MAX (est_ticks_till_branch
,
3809 if (need_cycles
> 0)
3811 if (INSN_UID (insn
) >= FENCE_READY_TICKS_SIZE (fence
))
3813 int new_size
= INSN_UID (insn
) * 3 / 2;
3815 FENCE_READY_TICKS (fence
)
3816 = (int *) xrecalloc (FENCE_READY_TICKS (fence
),
3817 new_size
, FENCE_READY_TICKS_SIZE (fence
),
3820 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]
3821 = FENCE_CYCLE (fence
) + need_cycles
;
3824 min_need_stall
= (min_need_stall
< 0
3826 : MIN (min_need_stall
, need_cycles
));
3828 VEC_unordered_remove (expr_t
, vec_av_set
, n
);
3830 if (sched_verbose
>= 4)
3831 sel_print ("Expr %d is not ready yet until cycle %d\n",
3833 FENCE_READY_TICKS (fence
)[INSN_UID (insn
)]);
3837 if (sched_verbose
>= 4)
3838 sel_print ("Expr %d is ok\n", INSN_UID (insn
));
3842 /* Clear SCHED_NEXT. */
3843 if (FENCE_SCHED_NEXT (fence
))
3845 gcc_assert (sched_next_worked
== 1);
3846 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
3849 /* No need to stall if this variable was not initialized. */
3850 if (min_need_stall
< 0)
3853 if (VEC_empty (expr_t
, vec_av_set
))
3855 /* We need to set *pneed_stall here, because later we skip this code
3856 when ready list is empty. */
3857 *pneed_stall
= min_need_stall
;
3861 gcc_assert (min_need_stall
== 0);
3863 /* Sort the vector. */
3864 qsort (VEC_address (expr_t
, vec_av_set
), VEC_length (expr_t
, vec_av_set
),
3865 sizeof (expr_t
), sel_rank_for_schedule
);
3867 if (sched_verbose
>= 4)
3869 sel_print ("Total ready exprs: %d, stalled: %d\n",
3870 VEC_length (expr_t
, vec_av_set
), stalled
);
3871 sel_print ("Sorted av set (%d): ", VEC_length (expr_t
, vec_av_set
));
3872 for (n
= 0; VEC_iterate (expr_t
, vec_av_set
, n
, expr
); n
++)
3881 /* Convert a vectored and sorted av set to the ready list that
3882 the rest of the backend wants to see. */
3884 convert_vec_av_set_to_ready (void)
3889 /* Allocate and fill the ready list from the sorted vector. */
3890 ready
.n_ready
= VEC_length (expr_t
, vec_av_set
);
3891 ready
.first
= ready
.n_ready
- 1;
3893 gcc_assert (ready
.n_ready
> 0);
3895 if (ready
.n_ready
> max_issue_size
)
3897 max_issue_size
= ready
.n_ready
;
3898 sched_extend_ready_list (ready
.n_ready
);
3901 for (n
= 0; VEC_iterate (expr_t
, vec_av_set
, n
, expr
); n
++)
3903 vinsn_t vi
= EXPR_VINSN (expr
);
3904 insn_t insn
= VINSN_INSN_RTX (vi
);
3907 ready
.vec
[n
] = insn
;
3911 /* Initialize ready list from *AV_PTR for the max_issue () call.
3912 If any unrecognizable insn found in *AV_PTR, return it (and skip
3913 max_issue). BND and FENCE are current boundary and fence,
3914 respectively. If we need to stall for some cycles before an expr
3915 from *AV_PTR would become available, write this number to *PNEED_STALL. */
3917 fill_ready_list (av_set_t
*av_ptr
, blist_t bnds
, fence_t fence
,
3922 /* We do not support multiple boundaries per fence. */
3923 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
3925 /* Process expressions required special handling, i.e. pipelined,
3926 speculative and recog() < 0 expressions first. */
3927 process_pipelined_exprs (av_ptr
);
3928 process_spec_exprs (av_ptr
);
3930 /* A USE could be scheduled immediately. */
3931 expr
= process_use_exprs (av_ptr
);
3938 /* Turn the av set to a vector for sorting. */
3939 if (! fill_vec_av_set (*av_ptr
, bnds
, fence
, pneed_stall
))
3945 /* Build the final ready list. */
3946 convert_vec_av_set_to_ready ();
3950 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
3952 sel_dfa_new_cycle (insn_t insn
, fence_t fence
)
3954 int last_scheduled_cycle
= FENCE_LAST_SCHEDULED_INSN (fence
)
3955 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence
))
3956 : FENCE_CYCLE (fence
) - 1;
3960 if (!targetm
.sched
.dfa_new_cycle
)
3963 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
3965 while (!sort_p
&& targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
,
3966 insn
, last_scheduled_cycle
,
3967 FENCE_CYCLE (fence
), &sort_p
))
3969 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
3970 advance_one_cycle (fence
);
3971 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
3978 /* Invoke reorder* target hooks on the ready list. Return the number of insns
3979 we can issue. FENCE is the current fence. */
3981 invoke_reorder_hooks (fence_t fence
)
3984 bool ran_hook
= false;
3986 /* Call the reorder hook at the beginning of the cycle, and call
3987 the reorder2 hook in the middle of the cycle. */
3988 if (FENCE_ISSUED_INSNS (fence
) == 0)
3990 if (targetm
.sched
.reorder
3991 && !SCHED_GROUP_P (ready_element (&ready
, 0))
3992 && ready
.n_ready
> 1)
3994 /* Don't give reorder the most prioritized insn as it can break
4000 = targetm
.sched
.reorder (sched_dump
, sched_verbose
,
4001 ready_lastpos (&ready
),
4002 &ready
.n_ready
, FENCE_CYCLE (fence
));
4010 /* Initialize can_issue_more for variable_issue. */
4011 issue_more
= issue_rate
;
4013 else if (targetm
.sched
.reorder2
4014 && !SCHED_GROUP_P (ready_element (&ready
, 0)))
4016 if (ready
.n_ready
== 1)
4018 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4019 ready_lastpos (&ready
),
4020 &ready
.n_ready
, FENCE_CYCLE (fence
));
4027 targetm
.sched
.reorder2 (sched_dump
, sched_verbose
,
4029 ? ready_lastpos (&ready
) : NULL
,
4030 &ready
.n_ready
, FENCE_CYCLE (fence
));
4039 issue_more
= issue_rate
;
4041 /* Ensure that ready list and vec_av_set are in line with each other,
4042 i.e. vec_av_set[i] == ready_element (&ready, i). */
4043 if (issue_more
&& ran_hook
)
4046 rtx
*arr
= ready
.vec
;
4047 expr_t
*vec
= VEC_address (expr_t
, vec_av_set
);
4049 for (i
= 0, n
= ready
.n_ready
; i
< n
; i
++)
4050 if (EXPR_INSN_RTX (vec
[i
]) != arr
[i
])
4054 for (j
= i
; j
< n
; j
++)
4055 if (EXPR_INSN_RTX (vec
[j
]) == arr
[i
])
4068 /* Return an EXPR correponding to INDEX element of ready list, if
4069 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4070 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4071 ready.vec otherwise. */
4072 static inline expr_t
4073 find_expr_for_ready (int index
, bool follow_ready_element
)
4078 real_index
= follow_ready_element
? ready
.first
- index
: index
;
4080 expr
= VEC_index (expr_t
, vec_av_set
, real_index
);
4081 gcc_assert (ready
.vec
[real_index
] == EXPR_INSN_RTX (expr
));
4086 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4087 of such insns found. */
4089 invoke_dfa_lookahead_guard (void)
4093 = targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard
!= NULL
;
4095 if (sched_verbose
>= 2)
4096 sel_print ("ready after reorder: ");
4098 for (i
= 0, n
= 0; i
< ready
.n_ready
; i
++)
4104 /* In this loop insn is Ith element of the ready list given by
4105 ready_element, not Ith element of ready.vec. */
4106 insn
= ready_element (&ready
, i
);
4108 if (! have_hook
|| i
== 0)
4111 r
= !targetm
.sched
.first_cycle_multipass_dfa_lookahead_guard (insn
);
4113 gcc_assert (INSN_CODE (insn
) >= 0);
4115 /* Only insns with ready_try = 0 can get here
4116 from fill_ready_list. */
4117 gcc_assert (ready_try
[i
] == 0);
4122 expr
= find_expr_for_ready (i
, true);
4124 if (sched_verbose
>= 2)
4126 dump_vinsn (EXPR_VINSN (expr
));
4127 sel_print (":%d; ", ready_try
[i
]);
4131 if (sched_verbose
>= 2)
4136 /* Calculate the number of privileged insns and return it. */
4138 calculate_privileged_insns (void)
4140 expr_t cur_expr
, min_spec_expr
= NULL
;
4141 insn_t cur_insn
, min_spec_insn
;
4142 int privileged_n
= 0, i
;
4144 for (i
= 0; i
< ready
.n_ready
; i
++)
4149 if (! min_spec_expr
)
4151 min_spec_insn
= ready_element (&ready
, i
);
4152 min_spec_expr
= find_expr_for_ready (i
, true);
4155 cur_insn
= ready_element (&ready
, i
);
4156 cur_expr
= find_expr_for_ready (i
, true);
4158 if (EXPR_SPEC (cur_expr
) > EXPR_SPEC (min_spec_expr
))
4164 if (i
== ready
.n_ready
)
4167 if (sched_verbose
>= 2)
4168 sel_print ("privileged_n: %d insns with SPEC %d\n",
4169 privileged_n
, privileged_n
? EXPR_SPEC (min_spec_expr
) : -1);
4170 return privileged_n
;
4173 /* Call the rest of the hooks after the choice was made. Return
4174 the number of insns that still can be issued given that the current
4175 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4176 and the insn chosen for scheduling, respectively. */
4178 invoke_aftermath_hooks (fence_t fence
, rtx best_insn
, int issue_more
)
4180 gcc_assert (INSN_P (best_insn
));
4182 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4183 sel_dfa_new_cycle (best_insn
, fence
);
4185 if (targetm
.sched
.variable_issue
)
4187 memcpy (curr_state
, FENCE_STATE (fence
), dfa_state_size
);
4189 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, best_insn
,
4191 memcpy (FENCE_STATE (fence
), curr_state
, dfa_state_size
);
4193 else if (GET_CODE (PATTERN (best_insn
)) != USE
4194 && GET_CODE (PATTERN (best_insn
)) != CLOBBER
)
4200 /* Estimate the cost of issuing INSN on DFA state STATE. */
4202 estimate_insn_cost (rtx insn
, state_t state
)
4204 static state_t temp
= NULL
;
4208 temp
= xmalloc (dfa_state_size
);
4210 memcpy (temp
, state
, dfa_state_size
);
4211 cost
= state_transition (temp
, insn
);
4220 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4221 This function properly handles ASMs, USEs etc. */
4223 get_expr_cost (expr_t expr
, fence_t fence
)
4225 rtx insn
= EXPR_INSN_RTX (expr
);
4227 if (recog_memoized (insn
) < 0)
4229 if (!FENCE_STARTS_CYCLE_P (fence
)
4230 /* FIXME: Is this condition necessary? */
4231 && VINSN_UNIQUE_P (EXPR_VINSN (expr
))
4232 && INSN_ASM_P (insn
))
4233 /* This is asm insn which is tryed to be issued on the
4234 cycle not first. Issue it on the next cycle. */
4237 /* A USE insn, or something else we don't need to
4238 understand. We can't pass these directly to
4239 state_transition because it will trigger a
4240 fatal error for unrecognizable insns. */
4244 return estimate_insn_cost (insn
, FENCE_STATE (fence
));
4247 /* Find the best insn for scheduling, either via max_issue or just take
4248 the most prioritized available. */
4250 choose_best_insn (fence_t fence
, int privileged_n
, int *index
)
4254 if (dfa_lookahead
> 0)
4256 cycle_issued_insns
= FENCE_ISSUED_INSNS (fence
);
4257 can_issue
= max_issue (&ready
, privileged_n
,
4258 FENCE_STATE (fence
), index
);
4259 if (sched_verbose
>= 2)
4260 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4261 can_issue
, FENCE_ISSUED_INSNS (fence
));
4265 /* We can't use max_issue; just return the first available element. */
4268 for (i
= 0; i
< ready
.n_ready
; i
++)
4270 expr_t expr
= find_expr_for_ready (i
, true);
4272 if (get_expr_cost (expr
, fence
) < 1)
4274 can_issue
= can_issue_more
;
4277 if (sched_verbose
>= 2)
4278 sel_print ("using %dth insn from the ready list\n", i
+ 1);
4284 if (i
== ready
.n_ready
)
4294 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4295 BNDS and FENCE are current boundaries and scheduling fence respectively.
4296 Return the expr found and NULL if nothing can be issued atm.
4297 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4299 find_best_expr (av_set_t
*av_vliw_ptr
, blist_t bnds
, fence_t fence
,
4304 /* Choose the best insn for scheduling via:
4305 1) sorting the ready list based on priority;
4306 2) calling the reorder hook;
4307 3) calling max_issue. */
4308 best
= fill_ready_list (av_vliw_ptr
, bnds
, fence
, pneed_stall
);
4309 if (best
== NULL
&& ready
.n_ready
> 0)
4311 int privileged_n
, index
, avail_n
;
4313 can_issue_more
= invoke_reorder_hooks (fence
);
4314 if (can_issue_more
> 0)
4316 /* Try choosing the best insn until we find one that is could be
4317 scheduled due to liveness restrictions on its destination register.
4318 In the future, we'd like to choose once and then just probe insns
4319 in the order of their priority. */
4320 avail_n
= invoke_dfa_lookahead_guard ();
4321 privileged_n
= calculate_privileged_insns ();
4322 can_issue_more
= choose_best_insn (fence
, privileged_n
, &index
);
4324 best
= find_expr_for_ready (index
, true);
4326 /* We had some available insns, so if we can't issue them,
4328 if (can_issue_more
== 0)
4337 can_issue_more
= invoke_aftermath_hooks (fence
, EXPR_INSN_RTX (best
),
4339 if (can_issue_more
== 0)
4343 if (sched_verbose
>= 2)
4347 sel_print ("Best expression (vliw form): ");
4349 sel_print ("; cycle %d\n", FENCE_CYCLE (fence
));
4352 sel_print ("No best expr found!\n");
4359 /* Functions that implement the core of the scheduler. */
4362 /* Emit an instruction from EXPR with SEQNO and VINSN after
4365 emit_insn_from_expr_after (expr_t expr
, vinsn_t vinsn
, int seqno
,
4366 insn_t place_to_insert
)
4368 /* This assert fails when we have identical instructions
4369 one of which dominates the other. In this case move_op ()
4370 finds the first instruction and doesn't search for second one.
4371 The solution would be to compute av_set after the first found
4372 insn and, if insn present in that set, continue searching.
4373 For now we workaround this issue in move_op. */
4374 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr
)));
4376 if (EXPR_WAS_RENAMED (expr
))
4378 unsigned regno
= expr_dest_regno (expr
);
4380 if (HARD_REGISTER_NUM_P (regno
))
4382 df_set_regs_ever_live (regno
, true);
4383 reg_rename_tick
[regno
] = ++reg_rename_this_tick
;
4387 return sel_gen_insn_from_expr_after (expr
, vinsn
, seqno
,
4391 /* Return TRUE if BB can hold bookkeeping code. */
4393 block_valid_for_bookkeeping_p (basic_block bb
)
4395 insn_t bb_end
= BB_END (bb
);
4397 if (!in_current_region_p (bb
) || EDGE_COUNT (bb
->succs
) > 1)
4400 if (INSN_P (bb_end
))
4402 if (INSN_SCHED_TIMES (bb_end
) > 0)
4406 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end
));
4411 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4412 into E2->dest, except from E1->src (there may be a sequence of empty basic
4413 blocks between E1->src and E2->dest). Return found block, or NULL if new
4414 one must be created. */
4416 find_block_for_bookkeeping (edge e1
, edge e2
)
4418 basic_block candidate_block
= NULL
;
4421 /* Loop over edges from E1 to E2, inclusive. */
4422 for (e
= e1
; ; e
= EDGE_SUCC (e
->dest
, 0))
4424 if (EDGE_COUNT (e
->dest
->preds
) == 2)
4426 if (candidate_block
== NULL
)
4427 candidate_block
= (EDGE_PRED (e
->dest
, 0) == e
4428 ? EDGE_PRED (e
->dest
, 1)->src
4429 : EDGE_PRED (e
->dest
, 0)->src
);
4431 /* Found additional edge leading to path from e1 to e2
4435 else if (EDGE_COUNT (e
->dest
->preds
) > 2)
4436 /* Several edges leading to path from e1 to e2 from aside. */
4440 return (block_valid_for_bookkeeping_p (candidate_block
)
4447 /* Create new basic block for bookkeeping code for path(s) incoming into
4448 E2->dest, except from E1->src. Return created block. */
4450 create_block_for_bookkeeping (edge e1
, edge e2
)
4452 basic_block new_bb
, bb
= e2
->dest
;
4454 /* Check that we don't spoil the loop structure. */
4455 if (current_loop_nest
)
4457 basic_block latch
= current_loop_nest
->latch
;
4459 /* We do not split header. */
4460 gcc_assert (e2
->dest
!= current_loop_nest
->header
);
4462 /* We do not redirect the only edge to the latch block. */
4463 gcc_assert (e1
->dest
!= latch
4464 || !single_pred_p (latch
)
4465 || e1
!= single_pred_edge (latch
));
4468 /* Split BB to insert BOOK_INSN there. */
4469 new_bb
= sched_split_block (bb
, NULL
);
4471 /* Move note_list from the upper bb. */
4472 gcc_assert (BB_NOTE_LIST (new_bb
) == NULL_RTX
);
4473 BB_NOTE_LIST (new_bb
) = BB_NOTE_LIST (bb
);
4474 BB_NOTE_LIST (bb
) = NULL_RTX
;
4476 gcc_assert (e2
->dest
== bb
);
4478 /* Skip block for bookkeeping copy when leaving E1->src. */
4479 if (e1
->flags
& EDGE_FALLTHRU
)
4480 sel_redirect_edge_and_branch_force (e1
, new_bb
);
4482 sel_redirect_edge_and_branch (e1
, new_bb
);
4484 gcc_assert (e1
->dest
== new_bb
);
4485 gcc_assert (sel_bb_empty_p (bb
));
4490 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4491 into E2->dest, except from E1->src. */
4493 find_place_for_bookkeeping (edge e1
, edge e2
)
4495 insn_t place_to_insert
;
4496 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4497 create new basic block, but insert bookkeeping there. */
4498 basic_block book_block
= find_block_for_bookkeeping (e1
, e2
);
4501 book_block
= create_block_for_bookkeeping (e1
, e2
);
4503 place_to_insert
= BB_END (book_block
);
4505 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4506 if (INSN_P (place_to_insert
) && control_flow_insn_p (place_to_insert
))
4507 place_to_insert
= PREV_INSN (place_to_insert
);
4509 return place_to_insert
;
4512 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4515 find_seqno_for_bookkeeping (insn_t place_to_insert
, insn_t join_point
)
4520 /* Check if we are about to insert bookkeeping copy before a jump, and use
4521 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4522 next
= NEXT_INSN (place_to_insert
);
4525 && BLOCK_FOR_INSN (next
) == BLOCK_FOR_INSN (place_to_insert
))
4526 seqno
= INSN_SEQNO (next
);
4527 else if (INSN_SEQNO (join_point
) > 0)
4528 seqno
= INSN_SEQNO (join_point
);
4530 seqno
= get_seqno_by_preds (place_to_insert
);
4532 gcc_assert (seqno
> 0);
4536 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4537 NEW_SEQNO to it. Return created insn. */
4539 emit_bookkeeping_insn (insn_t place_to_insert
, expr_t c_expr
, int new_seqno
)
4541 rtx new_insn_rtx
= create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr
));
4544 = create_vinsn_from_insn_rtx (new_insn_rtx
,
4545 VINSN_UNIQUE_P (EXPR_VINSN (c_expr
)));
4547 insn_t new_insn
= emit_insn_from_expr_after (c_expr
, new_vinsn
, new_seqno
,
4550 INSN_SCHED_TIMES (new_insn
) = 0;
4551 bitmap_set_bit (current_copies
, INSN_UID (new_insn
));
4556 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4557 E2->dest, except from E1->src (there may be a sequence of empty blocks
4558 between E1->src and E2->dest). Return block containing the copy.
4559 All scheduler data is initialized for the newly created insn. */
4561 generate_bookkeeping_insn (expr_t c_expr
, edge e1
, edge e2
)
4563 insn_t join_point
, place_to_insert
, new_insn
;
4565 bool need_to_exchange_data_sets
;
4567 if (sched_verbose
>= 4)
4568 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1
->src
->index
,
4571 join_point
= sel_bb_head (e2
->dest
);
4572 place_to_insert
= find_place_for_bookkeeping (e1
, e2
);
4573 new_seqno
= find_seqno_for_bookkeeping (place_to_insert
, join_point
);
4574 need_to_exchange_data_sets
4575 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert
));
4577 new_insn
= emit_bookkeeping_insn (place_to_insert
, c_expr
, new_seqno
);
4579 /* When inserting bookkeeping insn in new block, av sets should be
4580 following: old basic block (that now holds bookkeeping) data sets are
4581 the same as was before generation of bookkeeping, and new basic block
4582 (that now hold all other insns of old basic block) data sets are
4583 invalid. So exchange data sets for these basic blocks as sel_split_block
4584 mistakenly exchanges them in this case. Cannot do it earlier because
4585 when single instruction is added to new basic block it should hold NULL
4587 if (need_to_exchange_data_sets
)
4588 exchange_data_sets (BLOCK_FOR_INSN (new_insn
),
4589 BLOCK_FOR_INSN (join_point
));
4591 stat_bookkeeping_copies
++;
4592 return BLOCK_FOR_INSN (new_insn
);
4595 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4596 on FENCE, but we are unable to copy them. */
4598 remove_insns_that_need_bookkeeping (fence_t fence
, av_set_t
*av_ptr
)
4603 /* An expression does not need bookkeeping if it is available on all paths
4604 from current block to original block and current block dominates
4605 original block. We check availability on all paths by examining
4606 EXPR_SPEC; this is not equivalent, because it may be positive even
4607 if expr is available on all paths (but if expr is not available on
4608 any path, EXPR_SPEC will be positive). */
4610 FOR_EACH_EXPR_1 (expr
, i
, av_ptr
)
4612 if (!control_flow_insn_p (EXPR_INSN_RTX (expr
))
4613 && (!bookkeeping_p
|| VINSN_UNIQUE_P (EXPR_VINSN (expr
)))
4614 && (EXPR_SPEC (expr
)
4615 || !EXPR_ORIG_BB_INDEX (expr
)
4616 || !dominated_by_p (CDI_DOMINATORS
,
4617 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr
)),
4618 BLOCK_FOR_INSN (FENCE_INSN (fence
)))))
4620 if (sched_verbose
>= 4)
4621 sel_print ("Expr %d removed because it would need bookkeeping, which "
4622 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr
)));
4623 av_set_iter_remove (&i
);
4628 /* Moving conditional jump through some instructions.
4632 ... <- current scheduling point
4633 NOTE BASIC BLOCK: <- bb header
4634 (p8) add r14=r14+0x9;;
4640 We can schedule jump one cycle earlier, than mov, because they cannot be
4641 executed together as their predicates are mutually exclusive.
4643 This is done in this way: first, new fallthrough basic block is created
4644 after jump (it is always can be done, because there already should be a
4645 fallthrough block, where control flow goes in case of predicate being true -
4646 in our example; otherwise there should be a dependence between those
4647 instructions and jump and we cannot schedule jump right now);
4648 next, all instructions between jump and current scheduling point are moved
4649 to this new block. And the result is this:
4652 (!p8) jump L1 <- current scheduling point
4653 NOTE BASIC BLOCK: <- bb header
4654 (p8) add r14=r14+0x9;;
4660 move_cond_jump (rtx insn
, bnd_t bnd
)
4663 basic_block block_from
, block_next
, block_new
;
4664 rtx next
, prev
, link
;
4666 /* BLOCK_FROM holds basic block of the jump. */
4667 block_from
= BLOCK_FOR_INSN (insn
);
4669 /* Moving of jump should not cross any other jumps or
4670 beginnings of new basic blocks. */
4671 gcc_assert (block_from
== BLOCK_FOR_INSN (BND_TO (bnd
)));
4673 /* Jump is moved to the boundary. */
4674 prev
= BND_TO (bnd
);
4675 next
= PREV_INSN (insn
);
4676 BND_TO (bnd
) = insn
;
4678 ft_edge
= find_fallthru_edge (block_from
);
4679 block_next
= ft_edge
->dest
;
4680 /* There must be a fallthrough block (or where should go
4681 control flow in case of false jump predicate otherwise?). */
4682 gcc_assert (block_next
);
4684 /* Create new empty basic block after source block. */
4685 block_new
= sel_split_edge (ft_edge
);
4686 gcc_assert (block_new
->next_bb
== block_next
4687 && block_from
->next_bb
== block_new
);
4689 gcc_assert (BB_END (block_from
) == insn
);
4691 /* Move all instructions except INSN from BLOCK_FROM to
4693 for (link
= prev
; link
!= insn
; link
= NEXT_INSN (link
))
4695 EXPR_ORIG_BB_INDEX (INSN_EXPR (link
)) = block_new
->index
;
4696 df_insn_change_bb (link
, block_new
);
4699 /* Set correct basic block and instructions properties. */
4700 BB_END (block_new
) = PREV_INSN (insn
);
4702 NEXT_INSN (PREV_INSN (prev
)) = insn
;
4703 PREV_INSN (insn
) = PREV_INSN (prev
);
4705 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4706 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new
)));
4707 PREV_INSN (prev
) = BB_HEAD (block_new
);
4708 NEXT_INSN (next
) = NEXT_INSN (BB_HEAD (block_new
));
4709 NEXT_INSN (BB_HEAD (block_new
)) = prev
;
4710 PREV_INSN (NEXT_INSN (next
)) = next
;
4712 gcc_assert (!sel_bb_empty_p (block_from
)
4713 && !sel_bb_empty_p (block_new
));
4715 /* Update data sets for BLOCK_NEW to represent that INSN and
4716 instructions from the other branch of INSN is no longer
4717 available at BLOCK_NEW. */
4718 BB_AV_LEVEL (block_new
) = global_level
;
4719 gcc_assert (BB_LV_SET (block_new
) == NULL
);
4720 BB_LV_SET (block_new
) = get_clear_regset_from_pool ();
4721 update_data_sets (sel_bb_head (block_new
));
4723 /* INSN is a new basic block header - so prepare its data
4724 structures and update availability and liveness sets. */
4725 update_data_sets (insn
);
4727 if (sched_verbose
>= 4)
4728 sel_print ("Moving jump %d\n", INSN_UID (insn
));
4731 /* Remove nops generated during move_op for preventing removal of empty
4734 remove_temp_moveop_nops (void)
4739 for (i
= 0; VEC_iterate (insn_t
, vec_temp_moveop_nops
, i
, insn
); i
++)
4741 gcc_assert (INSN_NOP_P (insn
));
4742 return_nop_to_pool (insn
);
4745 /* Empty the vector. */
4746 if (VEC_length (insn_t
, vec_temp_moveop_nops
) > 0)
4747 VEC_block_remove (insn_t
, vec_temp_moveop_nops
, 0,
4748 VEC_length (insn_t
, vec_temp_moveop_nops
));
4751 /* Records the maximal UID before moving up an instruction. Used for
4752 distinguishing between bookkeeping copies and original insns. */
4753 static int max_uid_before_move_op
= 0;
4755 /* Remove from AV_VLIW_P all instructions but next when debug counter
4756 tells us so. Next instruction is fetched from BNDS. */
4758 remove_insns_for_debug (blist_t bnds
, av_set_t
*av_vliw_p
)
4760 if (! dbg_cnt (sel_sched_insn_cnt
))
4761 /* Leave only the next insn in av_vliw. */
4763 av_set_iterator av_it
;
4765 bnd_t bnd
= BLIST_BND (bnds
);
4766 insn_t next
= BND_TO (bnd
);
4768 gcc_assert (BLIST_NEXT (bnds
) == NULL
);
4770 FOR_EACH_EXPR_1 (expr
, av_it
, av_vliw_p
)
4771 if (EXPR_INSN_RTX (expr
) != next
)
4772 av_set_iter_remove (&av_it
);
4776 /* Compute available instructions on BNDS. FENCE is the current fence. Write
4777 the computed set to *AV_VLIW_P. */
4779 compute_av_set_on_boundaries (fence_t fence
, blist_t bnds
, av_set_t
*av_vliw_p
)
4781 if (sched_verbose
>= 2)
4783 sel_print ("Boundaries: ");
4788 for (; bnds
; bnds
= BLIST_NEXT (bnds
))
4790 bnd_t bnd
= BLIST_BND (bnds
);
4792 insn_t bnd_to
= BND_TO (bnd
);
4794 /* Rewind BND->TO to the basic block header in case some bookkeeping
4795 instructions were inserted before BND->TO and it needs to be
4797 if (sel_bb_head_p (bnd_to
))
4798 gcc_assert (INSN_SCHED_TIMES (bnd_to
) == 0);
4800 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to
)) == 0)
4802 bnd_to
= PREV_INSN (bnd_to
);
4803 if (sel_bb_head_p (bnd_to
))
4807 if (BND_TO (bnd
) != bnd_to
)
4809 gcc_assert (FENCE_INSN (fence
) == BND_TO (bnd
));
4810 FENCE_INSN (fence
) = bnd_to
;
4811 BND_TO (bnd
) = bnd_to
;
4814 av_set_clear (&BND_AV (bnd
));
4815 BND_AV (bnd
) = compute_av_set (BND_TO (bnd
), NULL
, 0, true);
4817 av_set_clear (&BND_AV1 (bnd
));
4818 BND_AV1 (bnd
) = av_set_copy (BND_AV (bnd
));
4820 moveup_set_inside_insn_group (&BND_AV1 (bnd
), NULL
);
4822 av1_copy
= av_set_copy (BND_AV1 (bnd
));
4823 av_set_union_and_clear (av_vliw_p
, &av1_copy
, NULL
);
4826 if (sched_verbose
>= 2)
4828 sel_print ("Available exprs (vliw form): ");
4829 dump_av_set (*av_vliw_p
);
4834 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
4835 expression. When FOR_MOVEOP is true, also replace the register of
4836 expressions found with the register from EXPR_VLIW. */
4838 find_sequential_best_exprs (bnd_t bnd
, expr_t expr_vliw
, bool for_moveop
)
4840 av_set_t expr_seq
= NULL
;
4844 FOR_EACH_EXPR (expr
, i
, BND_AV (bnd
))
4846 if (equal_after_moveup_path_p (expr
, NULL
, expr_vliw
))
4850 /* The sequential expression has the right form to pass
4851 to move_op except when renaming happened. Put the
4852 correct register in EXPR then. */
4853 if (EXPR_SEPARABLE_P (expr
) && REG_P (EXPR_LHS (expr
)))
4855 if (expr_dest_regno (expr
) != expr_dest_regno (expr_vliw
))
4857 replace_dest_with_reg_in_expr (expr
, EXPR_LHS (expr_vliw
));
4858 stat_renamed_scheduled
++;
4860 /* Also put the correct TARGET_AVAILABLE bit on the expr.
4861 This is needed when renaming came up with original
4863 else if (EXPR_TARGET_AVAILABLE (expr
)
4864 != EXPR_TARGET_AVAILABLE (expr_vliw
))
4866 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw
) == 1);
4867 EXPR_TARGET_AVAILABLE (expr
) = 1;
4870 if (EXPR_WAS_SUBSTITUTED (expr
))
4871 stat_substitutions_total
++;
4874 av_set_add (&expr_seq
, expr
);
4876 /* With substitution inside insn group, it is possible
4877 that more than one expression in expr_seq will correspond
4878 to expr_vliw. In this case, choose one as the attempt to
4879 move both leads to miscompiles. */
4884 if (for_moveop
&& sched_verbose
>= 2)
4886 sel_print ("Best expression(s) (sequential form): ");
4887 dump_av_set (expr_seq
);
4895 /* Move nop to previous block. */
4896 static void ATTRIBUTE_UNUSED
4897 move_nop_to_previous_block (insn_t nop
, basic_block prev_bb
)
4899 insn_t prev_insn
, next_insn
, note
;
4901 gcc_assert (sel_bb_head_p (nop
)
4902 && prev_bb
== BLOCK_FOR_INSN (nop
)->prev_bb
);
4903 note
= bb_note (BLOCK_FOR_INSN (nop
));
4904 prev_insn
= sel_bb_end (prev_bb
);
4905 next_insn
= NEXT_INSN (nop
);
4906 gcc_assert (prev_insn
!= NULL_RTX
4907 && PREV_INSN (note
) == prev_insn
);
4909 NEXT_INSN (prev_insn
) = nop
;
4910 PREV_INSN (nop
) = prev_insn
;
4912 PREV_INSN (note
) = nop
;
4913 NEXT_INSN (note
) = next_insn
;
4915 NEXT_INSN (nop
) = note
;
4916 PREV_INSN (next_insn
) = note
;
4918 BB_END (prev_bb
) = nop
;
4919 BLOCK_FOR_INSN (nop
) = prev_bb
;
4922 /* Prepare a place to insert the chosen expression on BND. */
4924 prepare_place_to_insert (bnd_t bnd
)
4926 insn_t place_to_insert
;
4928 /* Init place_to_insert before calling move_op, as the later
4929 can possibly remove BND_TO (bnd). */
4930 if (/* If this is not the first insn scheduled. */
4933 /* Add it after last scheduled. */
4934 place_to_insert
= ILIST_INSN (BND_PTR (bnd
));
4938 /* Add it before BND_TO. The difference is in the
4939 basic block, where INSN will be added. */
4940 place_to_insert
= get_nop_from_pool (BND_TO (bnd
));
4941 gcc_assert (BLOCK_FOR_INSN (place_to_insert
)
4942 == BLOCK_FOR_INSN (BND_TO (bnd
)));
4945 return place_to_insert
;
4948 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
4949 Return the expression to emit in C_EXPR. */
4951 move_exprs_to_boundary (bnd_t bnd
, expr_t expr_vliw
,
4952 av_set_t expr_seq
, expr_t c_expr
)
4957 int n_bookkeeping_copies_before_moveop
;
4959 /* Make a move. This call will remove the original operation,
4960 insert all necessary bookkeeping instructions and update the
4961 data sets. After that all we have to do is add the operation
4962 at before BND_TO (BND). */
4963 n_bookkeeping_copies_before_moveop
= stat_bookkeeping_copies
;
4964 max_uid_before_move_op
= get_max_uid ();
4965 bitmap_clear (current_copies
);
4966 bitmap_clear (current_originators
);
4968 b
= move_op (BND_TO (bnd
), expr_seq
, expr_vliw
,
4969 get_dest_from_orig_ops (expr_seq
), c_expr
);
4971 /* We should be able to find the expression we've chosen for
4973 gcc_assert (b
== 1);
4975 if (stat_bookkeeping_copies
> n_bookkeeping_copies_before_moveop
)
4976 stat_insns_needed_bookkeeping
++;
4978 EXECUTE_IF_SET_IN_BITMAP (current_copies
, 0, book_uid
, bi
)
4980 /* We allocate these bitmaps lazily. */
4981 if (! INSN_ORIGINATORS_BY_UID (book_uid
))
4982 INSN_ORIGINATORS_BY_UID (book_uid
) = BITMAP_ALLOC (NULL
);
4984 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid
),
4985 current_originators
);
4990 /* Debug a DFA state as an array of bytes. */
4992 debug_state (state_t state
)
4995 unsigned int i
, size
= dfa_state_size
;
4997 sel_print ("state (%u):", size
);
4998 for (i
= 0, p
= (unsigned char *) state
; i
< size
; i
++)
4999 sel_print (" %d", p
[i
]);
5003 /* Advance state on FENCE with INSN. Return true if INSN is
5004 an ASM, and we should advance state once more. */
5006 advance_state_on_fence (fence_t fence
, insn_t insn
)
5010 if (recog_memoized (insn
) >= 0)
5013 state_t temp_state
= alloca (dfa_state_size
);
5015 gcc_assert (!INSN_ASM_P (insn
));
5018 memcpy (temp_state
, FENCE_STATE (fence
), dfa_state_size
);
5019 res
= state_transition (FENCE_STATE (fence
), insn
);
5020 gcc_assert (res
< 0);
5022 if (memcmp (temp_state
, FENCE_STATE (fence
), dfa_state_size
))
5024 FENCE_ISSUED_INSNS (fence
)++;
5026 /* We should never issue more than issue_rate insns. */
5027 if (FENCE_ISSUED_INSNS (fence
) > issue_rate
)
5033 /* This could be an ASM insn which we'd like to schedule
5034 on the next cycle. */
5035 asm_p
= INSN_ASM_P (insn
);
5036 if (!FENCE_STARTS_CYCLE_P (fence
) && asm_p
)
5037 advance_one_cycle (fence
);
5040 if (sched_verbose
>= 2)
5041 debug_state (FENCE_STATE (fence
));
5042 FENCE_STARTS_CYCLE_P (fence
) = 0;
5046 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5047 is nonzero if we need to stall after issuing INSN. */
5049 update_fence_and_insn (fence_t fence
, insn_t insn
, int need_stall
)
5053 /* First, reflect that something is scheduled on this fence. */
5054 asm_p
= advance_state_on_fence (fence
, insn
);
5055 FENCE_LAST_SCHEDULED_INSN (fence
) = insn
;
5056 VEC_safe_push (rtx
, gc
, FENCE_EXECUTING_INSNS (fence
), insn
);
5057 if (SCHED_GROUP_P (insn
))
5059 FENCE_SCHED_NEXT (fence
) = INSN_SCHED_NEXT (insn
);
5060 SCHED_GROUP_P (insn
) = 0;
5063 FENCE_SCHED_NEXT (fence
) = NULL_RTX
;
5064 if (INSN_UID (insn
) < FENCE_READY_TICKS_SIZE (fence
))
5065 FENCE_READY_TICKS (fence
) [INSN_UID (insn
)] = 0;
5067 /* Set instruction scheduling info. This will be used in bundling,
5068 pipelining, tick computations etc. */
5069 ++INSN_SCHED_TIMES (insn
);
5070 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn
)) = true;
5071 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn
)) = FENCE_CYCLE (fence
);
5072 INSN_AFTER_STALL_P (insn
) = FENCE_AFTER_STALL_P (fence
);
5073 INSN_SCHED_CYCLE (insn
) = FENCE_CYCLE (fence
);
5075 /* This does not account for adjust_cost hooks, just add the biggest
5076 constant the hook may add to the latency. TODO: make this
5077 a target dependent constant. */
5078 INSN_READY_CYCLE (insn
)
5079 = INSN_SCHED_CYCLE (insn
) + (INSN_CODE (insn
) < 0
5081 : maximal_insn_latency (insn
) + 1);
5083 /* Change these fields last, as they're used above. */
5084 FENCE_AFTER_STALL_P (fence
) = 0;
5085 if (asm_p
|| need_stall
)
5086 advance_one_cycle (fence
);
5088 /* Indicate that we've scheduled something on this fence. */
5089 FENCE_SCHEDULED_P (fence
) = true;
5090 scheduled_something_on_previous_fence
= true;
5092 /* Print debug information when insn's fields are updated. */
5093 if (sched_verbose
>= 2)
5095 sel_print ("Scheduling insn: ");
5096 dump_insn_1 (insn
, 1);
5101 /* Update boundary BND with INSN, remove the old boundary from
5102 BNDSP, add new boundaries to BNDS_TAIL_P and return it. */
5104 update_boundaries (bnd_t bnd
, insn_t insn
, blist_t
*bndsp
,
5105 blist_t
*bnds_tailp
)
5110 advance_deps_context (BND_DC (bnd
), insn
);
5111 FOR_EACH_SUCC_1 (succ
, si
, insn
,
5112 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
5114 ilist_t ptr
= ilist_copy (BND_PTR (bnd
));
5116 ilist_add (&ptr
, insn
);
5117 blist_add (bnds_tailp
, succ
, ptr
, BND_DC (bnd
));
5118 bnds_tailp
= &BLIST_NEXT (*bnds_tailp
);
5121 blist_remove (bndsp
);
5125 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5127 schedule_expr_on_boundary (bnd_t bnd
, expr_t expr_vliw
, int seqno
)
5130 expr_t c_expr
= XALLOCA (expr_def
);
5131 insn_t place_to_insert
;
5135 expr_seq
= find_sequential_best_exprs (bnd
, expr_vliw
, true);
5137 /* In case of scheduling a jump skipping some other instructions,
5138 prepare CFG. After this, jump is at the boundary and can be
5139 scheduled as usual insn by MOVE_OP. */
5140 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw
)))
5142 insn
= EXPR_INSN_RTX (expr_vliw
);
5144 /* Speculative jumps are not handled. */
5145 if (insn
!= BND_TO (bnd
)
5146 && !sel_insn_is_speculation_check (insn
))
5147 move_cond_jump (insn
, bnd
);
5150 /* Calculate cant_move now as EXPR_WAS_RENAMED can change after move_op
5151 meaning that there was *any* renaming somewhere. */
5152 cant_move
= EXPR_WAS_CHANGED (expr_vliw
) || EXPR_WAS_RENAMED (expr_vliw
);
5154 /* Find a place for C_EXPR to schedule. */
5155 place_to_insert
= prepare_place_to_insert (bnd
);
5156 move_exprs_to_boundary (bnd
, expr_vliw
, expr_seq
, c_expr
);
5157 clear_expr (c_expr
);
5159 /* Add the instruction. The corner case to care about is when
5160 the expr_seq set has more than one expr, and we chose the one that
5161 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5162 we can't use it. Generate the new vinsn. */
5163 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw
)))
5167 vinsn_new
= vinsn_copy (EXPR_VINSN (expr_vliw
), false);
5168 change_vinsn_in_expr (expr_vliw
, vinsn_new
);
5172 insn
= emit_insn_from_expr_after (expr_vliw
, NULL
, seqno
,
5175 insn
= sel_move_insn (expr_vliw
, seqno
, place_to_insert
);
5177 /* Return the nops generated for preserving of data sets back
5179 if (INSN_NOP_P (place_to_insert
))
5180 return_nop_to_pool (place_to_insert
);
5181 remove_temp_moveop_nops ();
5183 av_set_clear (&expr_seq
);
5185 /* Save the expression scheduled so to reset target availability if we'll
5186 meet it later on the same fence. */
5187 if (EXPR_WAS_RENAMED (expr_vliw
))
5188 vinsn_vec_add (&vec_target_unavailable_vinsns
, INSN_EXPR (insn
));
5190 /* Check that the recent movement didn't destroyed loop
5192 gcc_assert (!pipelining_p
5193 || current_loop_nest
== NULL
5194 || loop_latch_edge (current_loop_nest
));
5198 /* Stall for N cycles on FENCE. */
5200 stall_for_cycles (fence_t fence
, int n
)
5204 could_more
= n
> 1 || FENCE_ISSUED_INSNS (fence
) < issue_rate
;
5206 advance_one_cycle (fence
);
5208 FENCE_AFTER_STALL_P (fence
) = 1;
5211 /* Gather a parallel group of insns at FENCE and assign their seqno
5212 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5213 list for later recalculation of seqnos. */
5215 fill_insns (fence_t fence
, int seqno
, ilist_t
**scheduled_insns_tailpp
)
5217 blist_t bnds
= NULL
, *bnds_tailp
;
5218 av_set_t av_vliw
= NULL
;
5219 insn_t insn
= FENCE_INSN (fence
);
5221 if (sched_verbose
>= 2)
5222 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5223 INSN_UID (insn
), FENCE_CYCLE (fence
));
5225 blist_add (&bnds
, insn
, NULL
, FENCE_DC (fence
));
5226 bnds_tailp
= &BLIST_NEXT (bnds
);
5227 set_target_context (FENCE_TC (fence
));
5228 target_bb
= INSN_BB (insn
);
5230 /* Do while we can add any operation to the current group. */
5233 blist_t
*bnds_tailp1
, *bndsp
;
5236 int was_stall
= 0, scheduled_insns
= 0, stall_iterations
= 0;
5237 int max_insns
= pipelining_p
? issue_rate
: 2 * issue_rate
;
5238 int max_stall
= pipelining_p
? 1 : 3;
5240 compute_av_set_on_boundaries (fence
, bnds
, &av_vliw
);
5241 remove_insns_that_need_bookkeeping (fence
, &av_vliw
);
5242 remove_insns_for_debug (bnds
, &av_vliw
);
5244 /* Return early if we have nothing to schedule. */
5245 if (av_vliw
== NULL
)
5248 /* Choose the best expression and, if needed, destination register
5252 expr_vliw
= find_best_expr (&av_vliw
, bnds
, fence
, &need_stall
);
5253 if (!expr_vliw
&& need_stall
)
5255 /* All expressions required a stall. Do not recompute av sets
5256 as we'll get the same answer (modulo the insns between
5257 the fence and its boundary, which will not be available for
5259 gcc_assert (! expr_vliw
&& stall_iterations
< 2);
5261 /* If we are going to stall for too long, break to recompute av
5262 sets and bring more insns for pipelining. */
5263 if (need_stall
<= 3)
5264 stall_for_cycles (fence
, need_stall
);
5267 stall_for_cycles (fence
, 1);
5272 while (! expr_vliw
&& need_stall
);
5274 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5277 av_set_clear (&av_vliw
);
5282 bnds_tailp1
= bnds_tailp
;
5285 /* This code will be executed only once until we'd have several
5286 boundaries per fence. */
5288 bnd_t bnd
= BLIST_BND (*bndsp
);
5290 if (!av_set_is_in_p (BND_AV1 (bnd
), EXPR_VINSN (expr_vliw
)))
5292 bndsp
= &BLIST_NEXT (*bndsp
);
5296 insn
= schedule_expr_on_boundary (bnd
, expr_vliw
, seqno
);
5297 update_fence_and_insn (fence
, insn
, need_stall
);
5298 bnds_tailp
= update_boundaries (bnd
, insn
, bndsp
, bnds_tailp
);
5300 /* Add insn to the list of scheduled on this cycle instructions. */
5301 ilist_add (*scheduled_insns_tailpp
, insn
);
5302 *scheduled_insns_tailpp
= &ILIST_NEXT (**scheduled_insns_tailpp
);
5304 while (*bndsp
!= *bnds_tailp1
);
5306 av_set_clear (&av_vliw
);
5309 /* We currently support information about candidate blocks only for
5310 one 'target_bb' block. Hence we can't schedule after jump insn,
5311 as this will bring two boundaries and, hence, necessity to handle
5312 information for two or more blocks concurrently. */
5313 if (sel_bb_end_p (insn
)
5315 && (was_stall
>= max_stall
5316 || scheduled_insns
>= max_insns
)))
5321 gcc_assert (!FENCE_BNDS (fence
));
5323 /* Update boundaries of the FENCE. */
5326 ilist_t ptr
= BND_PTR (BLIST_BND (bnds
));
5330 insn
= ILIST_INSN (ptr
);
5332 if (!ilist_is_in_p (FENCE_BNDS (fence
), insn
))
5333 ilist_add (&FENCE_BNDS (fence
), insn
);
5336 blist_remove (&bnds
);
5339 /* Update target context on the fence. */
5340 reset_target_context (FENCE_TC (fence
), false);
5343 /* All exprs in ORIG_OPS must have the same destination register or memory.
5344 Return that destination. */
5346 get_dest_from_orig_ops (av_set_t orig_ops
)
5348 rtx dest
= NULL_RTX
;
5349 av_set_iterator av_it
;
5351 bool first_p
= true;
5353 FOR_EACH_EXPR (expr
, av_it
, orig_ops
)
5355 rtx x
= EXPR_LHS (expr
);
5363 gcc_assert (dest
== x
5364 || (dest
!= NULL_RTX
&& x
!= NULL_RTX
5365 && rtx_equal_p (dest
, x
)));
5371 /* Update data sets for the bookkeeping block and record those expressions
5372 which become no longer available after inserting this bookkeeping. */
5374 update_and_record_unavailable_insns (basic_block book_block
)
5377 av_set_t old_av_set
= NULL
;
5379 rtx bb_end
= sel_bb_end (book_block
);
5381 /* First, get correct liveness in the bookkeeping block. The problem is
5382 the range between the bookeeping insn and the end of block. */
5383 update_liveness_on_insn (bb_end
);
5384 if (control_flow_insn_p (bb_end
))
5385 update_liveness_on_insn (PREV_INSN (bb_end
));
5387 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5388 fence above, where we may choose to schedule an insn which is
5389 actually blocked from moving up with the bookkeeping we create here. */
5390 if (AV_SET_VALID_P (sel_bb_head (book_block
)))
5392 old_av_set
= av_set_copy (BB_AV_SET (book_block
));
5393 update_data_sets (sel_bb_head (book_block
));
5395 /* Traverse all the expressions in the old av_set and check whether
5396 CUR_EXPR is in new AV_SET. */
5397 FOR_EACH_EXPR (cur_expr
, i
, old_av_set
)
5399 expr_t new_expr
= av_set_lookup (BB_AV_SET (book_block
),
5400 EXPR_VINSN (cur_expr
));
5403 /* In this case, we can just turn off the E_T_A bit, but we can't
5404 represent this information with the current vector. */
5405 || EXPR_TARGET_AVAILABLE (new_expr
)
5406 != EXPR_TARGET_AVAILABLE (cur_expr
))
5407 /* Unfortunately, the below code could be also fired up on
5409 FIXME: add an example of how this could happen. */
5410 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns
, cur_expr
);
5413 av_set_clear (&old_av_set
);
5417 /* The main effect of this function is that sparams->c_expr is merged
5418 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5419 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5420 lparams->c_expr_merged is copied back to sparams->c_expr after all
5421 successors has been traversed. lparams->c_expr_local is an expr allocated
5422 on stack in the caller function, and is used if there is more than one
5425 SUCC is one of the SUCCS_NORMAL successors of INSN,
5426 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5427 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5429 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED
,
5430 insn_t succ ATTRIBUTE_UNUSED
,
5431 int moveop_drv_call_res
,
5432 cmpd_local_params_p lparams
, void *static_params
)
5434 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5436 /* Nothing to do, if original expr wasn't found below. */
5437 if (moveop_drv_call_res
!= 1)
5440 /* If this is a first successor. */
5441 if (!lparams
->c_expr_merged
)
5443 lparams
->c_expr_merged
= sparams
->c_expr
;
5444 sparams
->c_expr
= lparams
->c_expr_local
;
5448 /* We must merge all found expressions to get reasonable
5449 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5450 do so then we can first find the expr with epsilon
5451 speculation success probability and only then with the
5452 good probability. As a result the insn will get epsilon
5453 probability and will never be scheduled because of
5454 weakness_cutoff in find_best_expr.
5456 We call merge_expr_data here instead of merge_expr
5457 because due to speculation C_EXPR and X may have the
5458 same insns with different speculation types. And as of
5459 now such insns are considered non-equal.
5461 However, EXPR_SCHED_TIMES is different -- we must get
5462 SCHED_TIMES from a real insn, not a bookkeeping copy.
5463 We force this here. Instead, we may consider merging
5464 SCHED_TIMES to the maximum instead of minimum in the
5466 int old_times
= EXPR_SCHED_TIMES (lparams
->c_expr_merged
);
5468 merge_expr_data (lparams
->c_expr_merged
, sparams
->c_expr
, NULL
);
5469 if (EXPR_SCHED_TIMES (sparams
->c_expr
) == 0)
5470 EXPR_SCHED_TIMES (lparams
->c_expr_merged
) = old_times
;
5472 clear_expr (sparams
->c_expr
);
5476 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5478 SUCC is one of the SUCCS_NORMAL successors of INSN,
5479 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5480 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5481 STATIC_PARAMS contain USED_REGS set. */
5483 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED
, insn_t succ
,
5484 int moveop_drv_call_res
,
5485 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5486 void *static_params
)
5489 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5491 /* Here we compute live regsets only for branches that do not lie
5492 on the code motion paths. These branches correspond to value
5493 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5494 for such branches code_motion_path_driver is not called. */
5495 if (moveop_drv_call_res
!= 0)
5498 /* Mark all registers that do not meet the following condition:
5499 (3) not live on the other path of any conditional branch
5500 that is passed by the operation, in case original
5501 operations are not present on both paths of the
5502 conditional branch. */
5503 succ_live
= compute_live (succ
);
5504 IOR_REG_SET (sparams
->used_regs
, succ_live
);
5507 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5510 move_op_after_merge_succs (cmpd_local_params_p lp
, void *sparams
)
5512 moveop_static_params_p sp
= (moveop_static_params_p
) sparams
;
5514 sp
->c_expr
= lp
->c_expr_merged
;
5517 /* Track bookkeeping copies created, insns scheduled, and blocks for
5518 rescheduling when INSN is found by move_op. */
5520 track_scheduled_insns_and_blocks (rtx insn
)
5522 /* Even if this insn can be a copy that will be removed during current move_op,
5523 we still need to count it as an originator. */
5524 bitmap_set_bit (current_originators
, INSN_UID (insn
));
5526 if (!bitmap_bit_p (current_copies
, INSN_UID (insn
)))
5528 /* Note that original block needs to be rescheduled, as we pulled an
5529 instruction out of it. */
5530 if (INSN_SCHED_TIMES (insn
) > 0)
5531 bitmap_set_bit (blocks_to_reschedule
, BLOCK_FOR_INSN (insn
)->index
);
5532 else if (INSN_UID (insn
) < first_emitted_uid
)
5533 num_insns_scheduled
++;
5536 bitmap_clear_bit (current_copies
, INSN_UID (insn
));
5538 /* For instructions we must immediately remove insn from the
5539 stream, so subsequent update_data_sets () won't include this
5541 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5542 if (INSN_UID (insn
) > max_uid_before_move_op
)
5543 stat_bookkeeping_copies
--;
5546 /* Emit a register-register copy for INSN if needed. Return true if
5547 emitted one. PARAMS is the move_op static parameters. */
5549 maybe_emit_renaming_copy (rtx insn
,
5550 moveop_static_params_p params
)
5552 bool insn_emitted
= false;
5553 rtx cur_reg
= expr_dest_reg (params
->c_expr
);
5555 gcc_assert (!cur_reg
|| (params
->dest
&& REG_P (params
->dest
)));
5557 /* If original operation has expr and the register chosen for
5558 that expr is not original operation's dest reg, substitute
5559 operation's right hand side with the register chosen. */
5560 if (cur_reg
!= NULL_RTX
&& REGNO (params
->dest
) != REGNO (cur_reg
))
5562 insn_t reg_move_insn
, reg_move_insn_rtx
;
5564 reg_move_insn_rtx
= create_insn_rtx_with_rhs (INSN_VINSN (insn
),
5566 reg_move_insn
= sel_gen_insn_from_rtx_after (reg_move_insn_rtx
,
5570 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn
)) = 0;
5571 replace_dest_with_reg_in_expr (params
->c_expr
, params
->dest
);
5573 insn_emitted
= true;
5574 params
->was_renamed
= true;
5577 return insn_emitted
;
5580 /* Emit a speculative check for INSN speculated as EXPR if needed.
5581 Return true if we've emitted one. PARAMS is the move_op static
5584 maybe_emit_speculative_check (rtx insn
, expr_t expr
,
5585 moveop_static_params_p params
)
5587 bool insn_emitted
= false;
5591 check_ds
= get_spec_check_type_for_insn (insn
, expr
);
5594 /* A speculation check should be inserted. */
5595 x
= create_speculation_check (params
->c_expr
, check_ds
, insn
);
5596 insn_emitted
= true;
5600 EXPR_SPEC_DONE_DS (INSN_EXPR (insn
)) = 0;
5604 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x
)) == 0
5605 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x
)) == 0);
5606 return insn_emitted
;
5609 /* Handle transformations that leave an insn in place of original
5610 insn such as renaming/speculation. Return true if one of such
5611 transformations actually happened, and we have emitted this insn. */
5613 handle_emitting_transformations (rtx insn
, expr_t expr
,
5614 moveop_static_params_p params
)
5616 bool insn_emitted
= false;
5618 insn_emitted
= maybe_emit_renaming_copy (insn
, params
);
5619 insn_emitted
|= maybe_emit_speculative_check (insn
, expr
, params
);
5621 return insn_emitted
;
5624 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5625 is not removed but reused when INSN is re-emitted. */
5627 remove_insn_from_stream (rtx insn
, bool only_disconnect
)
5629 insn_t nop
, bb_head
, bb_end
;
5630 bool need_nop_to_preserve_bb
;
5631 basic_block bb
= BLOCK_FOR_INSN (insn
);
5633 /* If INSN is the only insn in the basic block (not counting JUMP,
5634 which may be a jump to next insn), leave NOP there till the
5635 return to fill_insns. */
5636 bb_head
= sel_bb_head (bb
);
5637 bb_end
= sel_bb_end (bb
);
5638 need_nop_to_preserve_bb
= ((bb_head
== bb_end
)
5639 || (NEXT_INSN (bb_head
) == bb_end
5641 || IN_CURRENT_FENCE_P (NEXT_INSN (insn
)));
5643 /* If there's only one insn in the BB, make sure that a nop is
5644 inserted into it, so the basic block won't disappear when we'll
5645 delete INSN below with sel_remove_insn. It should also survive
5646 till the return to fill_insns. */
5647 if (need_nop_to_preserve_bb
)
5649 nop
= get_nop_from_pool (insn
);
5650 gcc_assert (INSN_NOP_P (nop
));
5651 VEC_safe_push (insn_t
, heap
, vec_temp_moveop_nops
, nop
);
5654 sel_remove_insn (insn
, only_disconnect
, false);
5657 /* This function is called when original expr is found.
5658 INSN - current insn traversed, EXPR - the corresponding expr found.
5659 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
5660 is static parameters of move_op. */
5662 move_op_orig_expr_found (insn_t insn
, expr_t expr
,
5663 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5664 void *static_params
)
5666 bool only_disconnect
, insn_emitted
;
5667 moveop_static_params_p params
= (moveop_static_params_p
) static_params
;
5669 copy_expr_onside (params
->c_expr
, INSN_EXPR (insn
));
5670 track_scheduled_insns_and_blocks (insn
);
5671 insn_emitted
= handle_emitting_transformations (insn
, expr
, params
);
5672 only_disconnect
= (params
->uid
== INSN_UID (insn
)
5673 && ! insn_emitted
&& ! EXPR_WAS_CHANGED (expr
));
5674 remove_insn_from_stream (insn
, only_disconnect
);
5677 /* The function is called when original expr is found.
5678 INSN - current insn traversed, EXPR - the corresponding expr found,
5679 crosses_call and original_insns in STATIC_PARAMS are updated. */
5681 fur_orig_expr_found (insn_t insn
, expr_t expr ATTRIBUTE_UNUSED
,
5682 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5683 void *static_params
)
5685 fur_static_params_p params
= (fur_static_params_p
) static_params
;
5689 params
->crosses_call
= true;
5691 def_list_add (params
->original_insns
, insn
, params
->crosses_call
);
5693 /* Mark the registers that do not meet the following condition:
5694 (2) not among the live registers of the point
5695 immediately following the first original operation on
5696 a given downward path, except for the original target
5697 register of the operation. */
5698 tmp
= get_clear_regset_from_pool ();
5699 compute_live_below_insn (insn
, tmp
);
5700 AND_COMPL_REG_SET (tmp
, INSN_REG_SETS (insn
));
5701 AND_COMPL_REG_SET (tmp
, INSN_REG_CLOBBERS (insn
));
5702 IOR_REG_SET (params
->used_regs
, tmp
);
5703 return_regset_to_pool (tmp
);
5705 /* (*1) We need to add to USED_REGS registers that are read by
5706 INSN's lhs. This may lead to choosing wrong src register.
5707 E.g. (scheduling const expr enabled):
5709 429: ax=0x0 <- Can't use AX for this expr (0x0)
5716 /* FIXME: see comment above and enable MEM_P
5717 in vinsn_separable_p. */
5718 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn
))
5719 || !MEM_P (INSN_LHS (insn
)));
5722 /* This function is called on the ascending pass, before returning from
5723 current basic block. */
5725 move_op_at_first_insn (insn_t insn
, cmpd_local_params_p lparams
,
5726 void *static_params
)
5728 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5729 basic_block book_block
= NULL
;
5731 /* When we have removed the boundary insn for scheduling, which also
5732 happened to be the end insn in its bb, we don't need to update sets. */
5733 if (!lparams
->removed_last_insn
5735 && sel_bb_head_p (insn
))
5737 /* We should generate bookkeeping code only if we are not at the
5738 top level of the move_op. */
5739 if (sel_num_cfg_preds_gt_1 (insn
))
5740 book_block
= generate_bookkeeping_insn (sparams
->c_expr
,
5741 lparams
->e1
, lparams
->e2
);
5742 /* Update data sets for the current insn. */
5743 update_data_sets (insn
);
5746 /* If bookkeeping code was inserted, we need to update av sets of basic
5747 block that received bookkeeping. After generation of bookkeeping insn,
5748 bookkeeping block does not contain valid av set because we are not following
5749 the original algorithm in every detail with regards to e.g. renaming
5750 simple reg-reg copies. Consider example:
5752 bookkeeping block scheduling fence
5762 We try to schedule insn "r1 := r3" on the current
5763 scheduling fence. Also, note that av set of bookkeeping block
5764 contain both insns "r1 := r2" and "r1 := r3". When the insn has
5765 been scheduled, the CFG is as follows:
5768 bookkeeping block scheduling fence
5778 Here, insn "r1 := r3" was scheduled at the current scheduling point
5779 and bookkeeping code was generated at the bookeeping block. This
5780 way insn "r1 := r2" is no longer available as a whole instruction
5781 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
5782 This situation is handled by calling update_data_sets.
5784 Since update_data_sets is called only on the bookkeeping block, and
5785 it also may have predecessors with av_sets, containing instructions that
5786 are no longer available, we save all such expressions that become
5787 unavailable during data sets update on the bookkeeping block in
5788 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
5789 expressions for scheduling. This allows us to avoid recomputation of
5790 av_sets outside the code motion path. */
5793 update_and_record_unavailable_insns (book_block
);
5795 /* If INSN was previously marked for deletion, it's time to do it. */
5796 if (lparams
->removed_last_insn
)
5797 insn
= PREV_INSN (insn
);
5799 /* Do not tidy control flow at the topmost moveop, as we can erroneously
5800 kill a block with a single nop in which the insn should be emitted. */
5802 tidy_control_flow (BLOCK_FOR_INSN (insn
), true);
5805 /* This function is called on the ascending pass, before returning from the
5806 current basic block. */
5808 fur_at_first_insn (insn_t insn
,
5809 cmpd_local_params_p lparams ATTRIBUTE_UNUSED
,
5810 void *static_params ATTRIBUTE_UNUSED
)
5812 gcc_assert (!sel_bb_head_p (insn
) || AV_SET_VALID_P (insn
)
5813 || AV_LEVEL (insn
) == -1);
5816 /* Called on the backward stage of recursion to call moveup_expr for insn
5817 and sparams->c_expr. */
5819 move_op_ascend (insn_t insn
, void *static_params
)
5821 enum MOVEUP_EXPR_CODE res
;
5822 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5824 if (! INSN_NOP_P (insn
))
5826 res
= moveup_expr_cached (sparams
->c_expr
, insn
, false);
5827 gcc_assert (res
!= MOVEUP_EXPR_NULL
);
5830 /* Update liveness for this insn as it was invalidated. */
5831 update_liveness_on_insn (insn
);
5834 /* This function is called on enter to the basic block.
5835 Returns TRUE if this block already have been visited and
5836 code_motion_path_driver should return 1, FALSE otherwise. */
5838 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED
, cmpd_local_params_p local_params
,
5839 void *static_params
, bool visited_p
)
5841 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5845 /* If we have found something below this block, there should be at
5846 least one insn in ORIGINAL_INSNS. */
5847 gcc_assert (*sparams
->original_insns
);
5849 /* Adjust CROSSES_CALL, since we may have come to this block along
5851 DEF_LIST_DEF (*sparams
->original_insns
)->crosses_call
5852 |= sparams
->crosses_call
;
5855 local_params
->old_original_insns
= *sparams
->original_insns
;
5860 /* Same as above but for move_op. */
5862 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED
,
5863 cmpd_local_params_p local_params ATTRIBUTE_UNUSED
,
5864 void *static_params ATTRIBUTE_UNUSED
, bool visited_p
)
5871 /* This function is called while descending current basic block if current
5872 insn is not the original EXPR we're searching for.
5874 Return value: FALSE, if code_motion_path_driver should perform a local
5875 cleanup and return 0 itself;
5876 TRUE, if code_motion_path_driver should continue. */
5878 move_op_orig_expr_not_found (insn_t insn
, av_set_t orig_ops ATTRIBUTE_UNUSED
,
5879 void *static_params
)
5881 moveop_static_params_p sparams
= (moveop_static_params_p
) static_params
;
5883 #ifdef ENABLE_CHECKING
5884 sparams
->failed_insn
= insn
;
5887 /* If we're scheduling separate expr, in order to generate correct code
5888 we need to stop the search at bookkeeping code generated with the
5889 same destination register or memory. */
5890 if (lhs_of_insn_equals_to_dest_p (insn
, sparams
->dest
))
5895 /* This function is called while descending current basic block if current
5896 insn is not the original EXPR we're searching for.
5898 Return value: TRUE (code_motion_path_driver should continue). */
5900 fur_orig_expr_not_found (insn_t insn
, av_set_t orig_ops
, void *static_params
)
5904 av_set_iterator avi
;
5905 fur_static_params_p sparams
= (fur_static_params_p
) static_params
;
5908 sparams
->crosses_call
= true;
5910 /* If current insn we are looking at cannot be executed together
5911 with original insn, then we can skip it safely.
5913 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
5914 INSN = (!p6) r14 = r14 + 1;
5916 Here we can schedule ORIG_OP with lhs = r14, though only
5917 looking at the set of used and set registers of INSN we must
5918 forbid it. So, add set/used in INSN registers to the
5919 untouchable set only if there is an insn in ORIG_OPS that can
5922 FOR_EACH_EXPR (r
, avi
, orig_ops
)
5923 if (!sched_insns_conditions_mutex_p (insn
, EXPR_INSN_RTX (r
)))
5929 /* Mark all registers that do not meet the following condition:
5930 (1) Not set or read on any path from xi to an instance of the
5931 original operation. */
5934 IOR_REG_SET (sparams
->used_regs
, INSN_REG_SETS (insn
));
5935 IOR_REG_SET (sparams
->used_regs
, INSN_REG_USES (insn
));
5936 IOR_REG_SET (sparams
->used_regs
, INSN_REG_CLOBBERS (insn
));
5942 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
5943 struct code_motion_path_driver_info_def move_op_hooks
= {
5945 move_op_orig_expr_found
,
5946 move_op_orig_expr_not_found
,
5947 move_op_merge_succs
,
5948 move_op_after_merge_succs
,
5950 move_op_at_first_insn
,
5955 /* Hooks and data to perform find_used_regs operations
5956 with code_motion_path_driver. */
5957 struct code_motion_path_driver_info_def fur_hooks
= {
5959 fur_orig_expr_found
,
5960 fur_orig_expr_not_found
,
5962 NULL
, /* fur_after_merge_succs */
5963 NULL
, /* fur_ascend */
5969 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
5970 code_motion_path_driver is called recursively. Original operation
5971 was found at least on one path that is starting with one of INSN's
5972 successors (this fact is asserted). ORIG_OPS is expressions we're looking
5973 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
5974 of either move_op or find_used_regs depending on the caller.
5976 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
5977 know for sure at this point. */
5979 code_motion_process_successors (insn_t insn
, av_set_t orig_ops
,
5980 ilist_t path
, void *static_params
)
5983 succ_iterator succ_i
;
5989 struct cmpd_local_params lparams
;
5992 lparams
.c_expr_local
= &_x
;
5993 lparams
.c_expr_merged
= NULL
;
5995 /* We need to process only NORMAL succs for move_op, and collect live
5996 registers from ALL branches (including those leading out of the
5997 region) for find_used_regs.
5999 In move_op, there can be a case when insn's bb number has changed
6000 due to created bookkeeping. This happens very rare, as we need to
6001 move expression from the beginning to the end of the same block.
6002 Rescan successors in this case. */
6005 bb
= BLOCK_FOR_INSN (insn
);
6006 old_index
= bb
->index
;
6007 old_succs
= EDGE_COUNT (bb
->succs
);
6009 FOR_EACH_SUCC_1 (succ
, succ_i
, insn
, code_motion_path_driver_info
->succ_flags
)
6013 lparams
.e1
= succ_i
.e1
;
6014 lparams
.e2
= succ_i
.e2
;
6016 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6018 if (succ_i
.current_flags
== SUCCS_NORMAL
)
6019 b
= code_motion_path_driver (succ
, orig_ops
, path
, &lparams
,
6024 /* Merge c_expres found or unify live register sets from different
6026 code_motion_path_driver_info
->merge_succs (insn
, succ
, b
, &lparams
,
6030 else if (b
== -1 && res
!= 1)
6033 /* We have simplified the control flow below this point. In this case,
6034 the iterator becomes invalid. We need to try again. */
6035 if (BLOCK_FOR_INSN (insn
)->index
!= old_index
6036 || EDGE_COUNT (bb
->succs
) != old_succs
)
6040 #ifdef ENABLE_CHECKING
6041 /* Here, RES==1 if original expr was found at least for one of the
6042 successors. After the loop, RES may happen to have zero value
6043 only if at some point the expr searched is present in av_set, but is
6044 not found below. In most cases, this situation is an error.
6045 The exception is when the original operation is blocked by
6046 bookkeeping generated for another fence or for another path in current
6048 gcc_assert (res
== 1
6050 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops
,
6055 /* Merge data, clean up, etc. */
6056 if (code_motion_path_driver_info
->after_merge_succs
)
6057 code_motion_path_driver_info
->after_merge_succs (&lparams
, static_params
);
6063 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6064 is the pointer to the av set with expressions we were looking for,
6065 PATH_P is the pointer to the traversed path. */
6067 code_motion_path_driver_cleanup (av_set_t
*orig_ops_p
, ilist_t
*path_p
)
6069 ilist_remove (path_p
);
6070 av_set_clear (orig_ops_p
);
6073 /* The driver function that implements move_op or find_used_regs
6074 functionality dependent whether code_motion_path_driver_INFO is set to
6075 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6076 of code (CFG traversal etc) that are shared among both functions. INSN
6077 is the insn we're starting the search from, ORIG_OPS are the expressions
6078 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6079 parameters of the driver, and STATIC_PARAMS are static parameters of
6082 Returns whether original instructions were found. Note that top-level
6083 code_motion_path_driver always returns true. */
6085 code_motion_path_driver (insn_t insn
, av_set_t orig_ops
, ilist_t path
,
6086 cmpd_local_params_p local_params_in
,
6087 void *static_params
)
6090 basic_block bb
= BLOCK_FOR_INSN (insn
);
6091 insn_t first_insn
, bb_tail
, before_first
;
6092 bool removed_last_insn
= false;
6094 if (sched_verbose
>= 6)
6096 sel_print ("%s (", code_motion_path_driver_info
->routine_name
);
6099 dump_av_set (orig_ops
);
6103 gcc_assert (orig_ops
);
6105 /* If no original operations exist below this insn, return immediately. */
6106 if (is_ineligible_successor (insn
, path
))
6108 if (sched_verbose
>= 6)
6109 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn
));
6113 /* The block can have invalid av set, in which case it was created earlier
6114 during move_op. Return immediately. */
6115 if (sel_bb_head_p (insn
))
6117 if (! AV_SET_VALID_P (insn
))
6119 if (sched_verbose
>= 6)
6120 sel_print ("Returned from block %d as it had invalid av set\n",
6125 if (bitmap_bit_p (code_motion_visited_blocks
, bb
->index
))
6127 /* We have already found an original operation on this branch, do not
6128 go any further and just return TRUE here. If we don't stop here,
6129 function can have exponential behaviour even on the small code
6130 with many different paths (e.g. with data speculation and
6131 recovery blocks). */
6132 if (sched_verbose
>= 6)
6133 sel_print ("Block %d already visited in this traversal\n", bb
->index
);
6134 if (code_motion_path_driver_info
->on_enter
)
6135 return code_motion_path_driver_info
->on_enter (insn
,
6142 if (code_motion_path_driver_info
->on_enter
)
6143 code_motion_path_driver_info
->on_enter (insn
, local_params_in
,
6144 static_params
, false);
6145 orig_ops
= av_set_copy (orig_ops
);
6147 /* Filter the orig_ops set. */
6148 if (AV_SET_VALID_P (insn
))
6149 av_set_intersect (&orig_ops
, AV_SET (insn
));
6151 /* If no more original ops, return immediately. */
6154 if (sched_verbose
>= 6)
6155 sel_print ("No intersection with av set of block %d\n", bb
->index
);
6159 /* For non-speculative insns we have to leave only one form of the
6160 original operation, because if we don't, we may end up with
6161 different C_EXPRes and, consequently, with bookkeepings for different
6162 expression forms along the same code motion path. That may lead to
6163 generation of incorrect code. So for each code motion we stick to
6164 the single form of the instruction, except for speculative insns
6165 which we need to keep in different forms with all speculation
6167 av_set_leave_one_nonspec (&orig_ops
);
6169 /* It is not possible that all ORIG_OPS are filtered out. */
6170 gcc_assert (orig_ops
);
6172 /* It is enough to place only heads and tails of visited basic blocks into
6174 ilist_add (&path
, insn
);
6176 bb_tail
= sel_bb_end (bb
);
6178 /* Descend the basic block in search of the original expr; this part
6179 corresponds to the part of the original move_op procedure executed
6180 before the recursive call. */
6183 /* Look at the insn and decide if it could be an ancestor of currently
6184 scheduling operation. If it is so, then the insn "dest = op" could
6185 either be replaced with "dest = reg", because REG now holds the result
6186 of OP, or just removed, if we've scheduled the insn as a whole.
6188 If this insn doesn't contain currently scheduling OP, then proceed
6189 with searching and look at its successors. Operations we're searching
6190 for could have changed when moving up through this insn via
6191 substituting. In this case, perform unsubstitution on them first.
6193 When traversing the DAG below this insn is finished, insert
6194 bookkeeping code, if the insn is a joint point, and remove
6197 expr
= av_set_lookup (orig_ops
, INSN_VINSN (insn
));
6200 insn_t last_insn
= PREV_INSN (insn
);
6202 /* We have found the original operation. */
6203 if (sched_verbose
>= 6)
6204 sel_print ("Found original operation at insn %d\n", INSN_UID (insn
));
6206 code_motion_path_driver_info
->orig_expr_found
6207 (insn
, expr
, local_params_in
, static_params
);
6209 /* Step back, so on the way back we'll start traversing from the
6210 previous insn (or we'll see that it's bb_note and skip that
6212 if (insn
== first_insn
)
6214 first_insn
= NEXT_INSN (last_insn
);
6215 removed_last_insn
= sel_bb_end_p (last_insn
);
6222 /* We haven't found the original expr, continue descending the basic
6224 if (code_motion_path_driver_info
->orig_expr_not_found
6225 (insn
, orig_ops
, static_params
))
6227 /* Av set ops could have been changed when moving through this
6228 insn. To find them below it, we have to un-substitute them. */
6229 undo_transformations (&orig_ops
, insn
);
6233 /* Clean up and return, if the hook tells us to do so. It may
6234 happen if we've encountered the previously created
6236 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6240 gcc_assert (orig_ops
);
6243 /* Stop at insn if we got to the end of BB. */
6244 if (insn
== bb_tail
)
6247 insn
= NEXT_INSN (insn
);
6250 /* Here INSN either points to the insn before the original insn (may be
6251 bb_note, if original insn was a bb_head) or to the bb_end. */
6256 gcc_assert (insn
== sel_bb_end (bb
));
6258 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6259 it's already in PATH then). */
6260 if (insn
!= first_insn
)
6261 ilist_add (&path
, insn
);
6263 /* Process_successors should be able to find at least one
6264 successor for which code_motion_path_driver returns TRUE. */
6265 res
= code_motion_process_successors (insn
, orig_ops
,
6266 path
, static_params
);
6268 /* Remove bb tail from path. */
6269 if (insn
!= first_insn
)
6270 ilist_remove (&path
);
6274 /* This is the case when one of the original expr is no longer available
6275 due to bookkeeping created on this branch with the same register.
6276 In the original algorithm, which doesn't have update_data_sets call
6277 on a bookkeeping block, it would simply result in returning
6278 FALSE when we've encountered a previously generated bookkeeping
6279 insn in moveop_orig_expr_not_found. */
6280 code_motion_path_driver_cleanup (&orig_ops
, &path
);
6285 /* Don't need it any more. */
6286 av_set_clear (&orig_ops
);
6288 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6289 the beginning of the basic block. */
6290 before_first
= PREV_INSN (first_insn
);
6291 while (insn
!= before_first
)
6293 if (code_motion_path_driver_info
->ascend
)
6294 code_motion_path_driver_info
->ascend (insn
, static_params
);
6296 insn
= PREV_INSN (insn
);
6299 /* Now we're at the bb head. */
6301 ilist_remove (&path
);
6302 local_params_in
->removed_last_insn
= removed_last_insn
;
6303 code_motion_path_driver_info
->at_first_insn (insn
, local_params_in
, static_params
);
6305 /* This should be the very last operation as at bb head we could change
6306 the numbering by creating bookkeeping blocks. */
6307 if (removed_last_insn
)
6308 insn
= PREV_INSN (insn
);
6309 bitmap_set_bit (code_motion_visited_blocks
, BLOCK_FOR_INSN (insn
)->index
);
6313 /* Move up the operations from ORIG_OPS set traversing the dag starting
6314 from INSN. PATH represents the edges traversed so far.
6315 DEST is the register chosen for scheduling the current expr. Insert
6316 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6317 C_EXPR is how it looks like at the given cfg point.
6319 Returns whether original instructions were found, which is asserted
6320 to be true in the caller. */
6322 move_op (insn_t insn
, av_set_t orig_ops
, expr_t expr_vliw
,
6323 rtx dest
, expr_t c_expr
)
6325 struct moveop_static_params sparams
;
6326 struct cmpd_local_params lparams
;
6329 /* Init params for code_motion_path_driver. */
6330 sparams
.dest
= dest
;
6331 sparams
.c_expr
= c_expr
;
6332 sparams
.uid
= INSN_UID (EXPR_INSN_RTX (expr_vliw
));
6333 #ifdef ENABLE_CHECKING
6334 sparams
.failed_insn
= NULL
;
6336 sparams
.was_renamed
= false;
6339 /* We haven't visited any blocks yet. */
6340 bitmap_clear (code_motion_visited_blocks
);
6342 /* Set appropriate hooks and data. */
6343 code_motion_path_driver_info
= &move_op_hooks
;
6344 res
= code_motion_path_driver (insn
, orig_ops
, NULL
, &lparams
, &sparams
);
6346 if (sparams
.was_renamed
)
6347 EXPR_WAS_RENAMED (expr_vliw
) = true;
6353 /* Functions that work with regions. */
6355 /* Current number of seqno used in init_seqno and init_seqno_1. */
6356 static int cur_seqno
;
6358 /* A helper for init_seqno. Traverse the region starting from BB and
6359 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6360 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6362 init_seqno_1 (basic_block bb
, sbitmap visited_bbs
, bitmap blocks_to_reschedule
)
6364 int bbi
= BLOCK_TO_BB (bb
->index
);
6365 insn_t insn
, note
= bb_note (bb
);
6369 SET_BIT (visited_bbs
, bbi
);
6370 if (blocks_to_reschedule
)
6371 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
6373 FOR_EACH_SUCC_1 (succ_insn
, si
, BB_END (bb
),
6374 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6376 basic_block succ
= BLOCK_FOR_INSN (succ_insn
);
6377 int succ_bbi
= BLOCK_TO_BB (succ
->index
);
6379 gcc_assert (in_current_region_p (succ
));
6381 if (!TEST_BIT (visited_bbs
, succ_bbi
))
6383 gcc_assert (succ_bbi
> bbi
);
6385 init_seqno_1 (succ
, visited_bbs
, blocks_to_reschedule
);
6389 for (insn
= BB_END (bb
); insn
!= note
; insn
= PREV_INSN (insn
))
6390 INSN_SEQNO (insn
) = cur_seqno
--;
6393 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6394 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6395 which we're rescheduling when pipelining, FROM is the block where
6396 traversing region begins (it may not be the head of the region when
6397 pipelining, but the head of the loop instead).
6399 Returns the maximal seqno found. */
6401 init_seqno (int number_of_insns
, bitmap blocks_to_reschedule
, basic_block from
)
6403 sbitmap visited_bbs
;
6407 visited_bbs
= sbitmap_alloc (current_nr_blocks
);
6409 if (blocks_to_reschedule
)
6411 sbitmap_ones (visited_bbs
);
6412 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule
, 0, bbi
, bi
)
6414 gcc_assert (BLOCK_TO_BB (bbi
) < current_nr_blocks
);
6415 RESET_BIT (visited_bbs
, BLOCK_TO_BB (bbi
));
6420 sbitmap_zero (visited_bbs
);
6421 from
= EBB_FIRST_BB (0);
6424 cur_seqno
= number_of_insns
> 0 ? number_of_insns
: sched_max_luid
- 1;
6425 init_seqno_1 (from
, visited_bbs
, blocks_to_reschedule
);
6426 gcc_assert (cur_seqno
== 0 || number_of_insns
== 0);
6428 sbitmap_free (visited_bbs
);
6429 return sched_max_luid
- 1;
6432 /* Initialize scheduling parameters for current region. */
6434 sel_setup_region_sched_flags (void)
6436 enable_schedule_as_rhs_p
= 1;
6438 pipelining_p
= (bookkeeping_p
6439 && (flag_sel_sched_pipelining
!= 0)
6440 && current_loop_nest
!= NULL
);
6441 max_insns_to_rename
= PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME
);
6445 /* Return true if all basic blocks of current region are empty. */
6447 current_region_empty_p (void)
6450 for (i
= 0; i
< current_nr_blocks
; i
++)
6451 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i
))))
6457 /* Prepare and verify loop nest for pipelining. */
6459 setup_current_loop_nest (int rgn
)
6461 current_loop_nest
= get_loop_nest_for_rgn (rgn
);
6463 if (!current_loop_nest
)
6466 /* If this loop has any saved loop preheaders from nested loops,
6467 add these basic blocks to the current region. */
6468 sel_add_loop_preheaders ();
6470 /* Check that we're starting with a valid information. */
6471 gcc_assert (loop_latch_edge (current_loop_nest
));
6472 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest
));
6475 /* Purge meaningless empty blocks in the middle of a region. */
6477 purge_empty_blocks (void)
6481 for (i
= 1; i
< current_nr_blocks
; )
6483 basic_block b
= BASIC_BLOCK (BB_TO_BLOCK (i
));
6485 if (maybe_tidy_empty_bb (b
))
6492 /* Compute instruction priorities for current region. */
6494 sel_compute_priorities (int rgn
)
6496 sched_rgn_compute_dependencies (rgn
);
6498 /* Compute insn priorities in haifa style. Then free haifa style
6499 dependencies that we've calculated for this. */
6500 compute_priorities ();
6502 if (sched_verbose
>= 5)
6503 debug_rgn_dependencies (0);
6508 /* Init scheduling data for RGN. Returns true when this region should not
6511 sel_region_init (int rgn
)
6516 rgn_setup_region (rgn
);
6518 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6519 do region initialization here so the region can be bundled correctly,
6520 but we'll skip the scheduling in sel_sched_region (). */
6521 if (current_region_empty_p ())
6524 if (flag_sel_sched_pipelining
)
6525 setup_current_loop_nest (rgn
);
6527 sel_setup_region_sched_flags ();
6529 bbs
= VEC_alloc (basic_block
, heap
, current_nr_blocks
);
6531 for (i
= 0; i
< current_nr_blocks
; i
++)
6532 VEC_quick_push (basic_block
, bbs
, BASIC_BLOCK (BB_TO_BLOCK (i
)));
6534 sel_init_bbs (bbs
, NULL
);
6536 /* Initialize luids and dependence analysis which both sel-sched and haifa
6538 sched_init_luids (bbs
, NULL
, NULL
, NULL
);
6539 sched_deps_init (false);
6541 /* Initialize haifa data. */
6542 rgn_setup_sched_infos ();
6543 sel_set_sched_flags ();
6544 haifa_init_h_i_d (bbs
, NULL
, NULL
, NULL
);
6546 sel_compute_priorities (rgn
);
6547 init_deps_global ();
6549 /* Main initialization. */
6550 sel_setup_sched_infos ();
6551 sel_init_global_and_expr (bbs
);
6553 VEC_free (basic_block
, heap
, bbs
);
6555 blocks_to_reschedule
= BITMAP_ALLOC (NULL
);
6557 /* Init correct liveness sets on each instruction of a single-block loop.
6558 This is the only situation when we can't update liveness when calling
6559 compute_live for the first insn of the loop. */
6560 if (current_loop_nest
)
6562 int header
= (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6566 if (current_nr_blocks
== header
+ 1)
6567 update_liveness_on_insn
6568 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header
))));
6571 /* Set hooks so that no newly generated insn will go out unnoticed. */
6572 sel_register_cfg_hooks ();
6574 /* !!! We call target.sched.md_init () for the whole region, but we invoke
6575 targetm.sched.md_finish () for every ebb. */
6576 if (targetm
.sched
.md_init
)
6577 /* None of the arguments are actually used in any target. */
6578 targetm
.sched
.md_init (sched_dump
, sched_verbose
, -1);
6580 first_emitted_uid
= get_max_uid () + 1;
6581 preheader_removed
= false;
6583 /* Reset register allocation ticks array. */
6584 memset (reg_rename_tick
, 0, sizeof reg_rename_tick
);
6585 reg_rename_this_tick
= 0;
6587 bitmap_initialize (forced_ebb_heads
, 0);
6588 bitmap_clear (forced_ebb_heads
);
6591 current_copies
= BITMAP_ALLOC (NULL
);
6592 current_originators
= BITMAP_ALLOC (NULL
);
6593 code_motion_visited_blocks
= BITMAP_ALLOC (NULL
);
6598 /* Simplify insns after the scheduling. */
6600 simplify_changed_insns (void)
6604 for (i
= 0; i
< current_nr_blocks
; i
++)
6606 basic_block bb
= BASIC_BLOCK (BB_TO_BLOCK (i
));
6609 FOR_BB_INSNS (bb
, insn
)
6612 expr_t expr
= INSN_EXPR (insn
);
6614 if (EXPR_WAS_SUBSTITUTED (expr
))
6615 validate_simplify_insn (insn
);
6620 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6621 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6622 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6624 find_ebb_boundaries (basic_block bb
, bitmap scheduled_blocks
)
6627 basic_block bb1
= bb
;
6628 if (sched_verbose
>= 2)
6629 sel_print ("Finishing schedule in bbs: ");
6633 bitmap_set_bit (scheduled_blocks
, BLOCK_TO_BB (bb1
->index
));
6635 if (sched_verbose
>= 2)
6636 sel_print ("%d; ", bb1
->index
);
6638 while (!bb_ends_ebb_p (bb1
) && (bb1
= bb_next_bb (bb1
)));
6640 if (sched_verbose
>= 2)
6643 get_ebb_head_tail (bb
, bb1
, &head
, &tail
);
6645 current_sched_info
->head
= head
;
6646 current_sched_info
->tail
= tail
;
6647 current_sched_info
->prev_head
= PREV_INSN (head
);
6648 current_sched_info
->next_tail
= NEXT_INSN (tail
);
6651 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6653 reset_sched_cycles_in_current_ebb (void)
6656 int haifa_last_clock
= -1;
6657 int haifa_clock
= 0;
6660 if (targetm
.sched
.md_init
)
6662 /* None of the arguments are actually used in any target.
6663 NB: We should have md_reset () hook for cases like this. */
6664 targetm
.sched
.md_init (sched_dump
, sched_verbose
, -1);
6667 state_reset (curr_state
);
6668 advance_state (curr_state
);
6670 for (insn
= current_sched_info
->head
;
6671 insn
!= current_sched_info
->next_tail
;
6672 insn
= NEXT_INSN (insn
))
6674 int cost
, haifa_cost
;
6676 bool asm_p
, real_insn
, after_stall
;
6683 real_insn
= recog_memoized (insn
) >= 0;
6684 clock
= INSN_SCHED_CYCLE (insn
);
6686 cost
= clock
- last_clock
;
6688 /* Initialize HAIFA_COST. */
6691 asm_p
= INSN_ASM_P (insn
);
6694 /* This is asm insn which *had* to be scheduled first
6698 /* This is a use/clobber insn. It should not change
6703 haifa_cost
= estimate_insn_cost (insn
, curr_state
);
6705 /* Stall for whatever cycles we've stalled before. */
6707 if (INSN_AFTER_STALL_P (insn
) && cost
> haifa_cost
)
6717 while (haifa_cost
--)
6719 advance_state (curr_state
);
6722 if (sched_verbose
>= 2)
6724 sel_print ("advance_state (state_transition)\n");
6725 debug_state (curr_state
);
6728 /* The DFA may report that e.g. insn requires 2 cycles to be
6729 issued, but on the next cycle it says that insn is ready
6730 to go. Check this here. */
6734 && estimate_insn_cost (insn
, curr_state
) == 0)
6741 gcc_assert (haifa_cost
== 0);
6743 if (sched_verbose
>= 2)
6744 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn
), haifa_cost
);
6746 if (targetm
.sched
.dfa_new_cycle
)
6747 while (targetm
.sched
.dfa_new_cycle (sched_dump
, sched_verbose
, insn
,
6748 haifa_last_clock
, haifa_clock
,
6751 advance_state (curr_state
);
6753 if (sched_verbose
>= 2)
6755 sel_print ("advance_state (dfa_new_cycle)\n");
6756 debug_state (curr_state
);
6762 cost
= state_transition (curr_state
, insn
);
6764 if (sched_verbose
>= 2)
6765 debug_state (curr_state
);
6767 gcc_assert (cost
< 0);
6770 if (targetm
.sched
.variable_issue
)
6771 targetm
.sched
.variable_issue (sched_dump
, sched_verbose
, insn
, 0);
6773 INSN_SCHED_CYCLE (insn
) = haifa_clock
;
6776 haifa_last_clock
= haifa_clock
;
6780 /* Put TImode markers on insns starting a new issue group. */
6784 int last_clock
= -1;
6787 for (insn
= current_sched_info
->head
; insn
!= current_sched_info
->next_tail
;
6788 insn
= NEXT_INSN (insn
))
6795 clock
= INSN_SCHED_CYCLE (insn
);
6796 cost
= (last_clock
== -1) ? 1 : clock
- last_clock
;
6798 gcc_assert (cost
>= 0);
6801 && GET_CODE (PATTERN (insn
)) != USE
6802 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6804 if (reload_completed
&& cost
> 0)
6805 PUT_MODE (insn
, TImode
);
6810 if (sched_verbose
>= 2)
6811 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn
), cost
);
6815 /* Perform MD_FINISH on EBBs comprising current region. When
6816 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
6817 to produce correct sched cycles on insns. */
6819 sel_region_target_finish (bool reset_sched_cycles_p
)
6822 bitmap scheduled_blocks
= BITMAP_ALLOC (NULL
);
6824 for (i
= 0; i
< current_nr_blocks
; i
++)
6826 if (bitmap_bit_p (scheduled_blocks
, i
))
6829 /* While pipelining outer loops, skip bundling for loop
6830 preheaders. Those will be rescheduled in the outer loop. */
6831 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i
)))
6834 find_ebb_boundaries (EBB_FIRST_BB (i
), scheduled_blocks
);
6836 if (no_real_insns_p (current_sched_info
->head
, current_sched_info
->tail
))
6839 if (reset_sched_cycles_p
)
6840 reset_sched_cycles_in_current_ebb ();
6842 if (targetm
.sched
.md_init
)
6843 targetm
.sched
.md_init (sched_dump
, sched_verbose
, -1);
6847 if (targetm
.sched
.md_finish
)
6849 targetm
.sched
.md_finish (sched_dump
, sched_verbose
);
6851 /* Extend luids so that insns generated by the target will
6853 sched_init_luids (NULL
, NULL
, NULL
, NULL
);
6857 BITMAP_FREE (scheduled_blocks
);
6860 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
6861 is true, make an additional pass emulating scheduler to get correct insn
6862 cycles for md_finish calls. */
6864 sel_region_finish (bool reset_sched_cycles_p
)
6866 simplify_changed_insns ();
6867 sched_finish_ready_list ();
6870 /* Free the vectors. */
6872 VEC_free (expr_t
, heap
, vec_av_set
);
6873 BITMAP_FREE (current_copies
);
6874 BITMAP_FREE (current_originators
);
6875 BITMAP_FREE (code_motion_visited_blocks
);
6876 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns
);
6877 vinsn_vec_free (&vec_target_unavailable_vinsns
);
6879 /* If LV_SET of the region head should be updated, do it now because
6880 there will be no other chance. */
6885 FOR_EACH_SUCC_1 (insn
, si
, bb_note (EBB_FIRST_BB (0)),
6886 SUCCS_NORMAL
| SUCCS_SKIP_TO_LOOP_EXITS
)
6888 basic_block bb
= BLOCK_FOR_INSN (insn
);
6890 if (!BB_LV_SET_VALID_P (bb
))
6891 compute_live (insn
);
6895 /* Emulate the Haifa scheduler for bundling. */
6896 if (reload_completed
)
6897 sel_region_target_finish (reset_sched_cycles_p
);
6899 sel_finish_global_and_expr ();
6901 bitmap_clear (forced_ebb_heads
);
6905 finish_deps_global ();
6906 sched_finish_luids ();
6909 BITMAP_FREE (blocks_to_reschedule
);
6911 sel_unregister_cfg_hooks ();
6917 /* Functions that implement the scheduler driver. */
6919 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
6920 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
6921 of insns scheduled -- these would be postprocessed later. */
6923 schedule_on_fences (flist_t fences
, int max_seqno
,
6924 ilist_t
**scheduled_insns_tailpp
)
6926 flist_t old_fences
= fences
;
6928 if (sched_verbose
>= 1)
6930 sel_print ("\nScheduling on fences: ");
6931 dump_flist (fences
);
6935 scheduled_something_on_previous_fence
= false;
6936 for (; fences
; fences
= FLIST_NEXT (fences
))
6938 fence_t fence
= NULL
;
6941 bool first_p
= true;
6943 /* Choose the next fence group to schedule.
6944 The fact that insn can be scheduled only once
6945 on the cycle is guaranteed by two properties:
6946 1. seqnos of parallel groups decrease with each iteration.
6947 2. If is_ineligible_successor () sees the larger seqno, it
6948 checks if candidate insn is_in_current_fence_p (). */
6949 for (fences2
= old_fences
; fences2
; fences2
= FLIST_NEXT (fences2
))
6951 fence_t f
= FLIST_FENCE (fences2
);
6953 if (!FENCE_PROCESSED_P (f
))
6955 int i
= INSN_SEQNO (FENCE_INSN (f
));
6957 if (first_p
|| i
> seqno
)
6964 /* ??? Seqnos of different groups should be different. */
6965 gcc_assert (1 || i
!= seqno
);
6971 /* As FENCE is nonnull, SEQNO is initialized. */
6972 seqno
-= max_seqno
+ 1;
6973 fill_insns (fence
, seqno
, scheduled_insns_tailpp
);
6974 FENCE_PROCESSED_P (fence
) = true;
6977 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
6978 don't need to keep bookkeeping-invalidated and target-unavailable
6980 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns
);
6981 vinsn_vec_clear (&vec_target_unavailable_vinsns
);
6984 /* Calculate MIN_SEQNO and MAX_SEQNO. */
6986 find_min_max_seqno (flist_t fences
, int *min_seqno
, int *max_seqno
)
6988 *min_seqno
= *max_seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
6990 /* The first element is already processed. */
6991 while ((fences
= FLIST_NEXT (fences
)))
6993 int seqno
= INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences
)));
6995 if (*min_seqno
> seqno
)
6997 else if (*max_seqno
< seqno
)
7002 /* Calculate new fences from FENCES. */
7004 calculate_new_fences (flist_t fences
, int orig_max_seqno
)
7006 flist_t old_fences
= fences
;
7007 struct flist_tail_def _new_fences
, *new_fences
= &_new_fences
;
7009 flist_tail_init (new_fences
);
7010 for (; fences
; fences
= FLIST_NEXT (fences
))
7012 fence_t fence
= FLIST_FENCE (fences
);
7015 if (!FENCE_BNDS (fence
))
7017 /* This fence doesn't have any successors. */
7018 if (!FENCE_SCHEDULED_P (fence
))
7020 /* Nothing was scheduled on this fence. */
7023 insn
= FENCE_INSN (fence
);
7024 seqno
= INSN_SEQNO (insn
);
7025 gcc_assert (seqno
> 0 && seqno
<= orig_max_seqno
);
7027 if (sched_verbose
>= 1)
7028 sel_print ("Fence %d[%d] has not changed\n",
7031 move_fence_to_fences (fences
, new_fences
);
7035 extract_new_fences_from (fences
, new_fences
, orig_max_seqno
);
7038 flist_clear (&old_fences
);
7039 return FLIST_TAIL_HEAD (new_fences
);
7042 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7043 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7044 the highest seqno used in a region. Return the updated highest seqno. */
7046 update_seqnos_and_stage (int min_seqno
, int max_seqno
,
7047 int highest_seqno_in_use
,
7048 ilist_t
*pscheduled_insns
)
7054 /* Actually, new_hs is the seqno of the instruction, that was
7055 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7056 if (*pscheduled_insns
)
7058 new_hs
= (INSN_SEQNO (ILIST_INSN (*pscheduled_insns
))
7059 + highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2);
7060 gcc_assert (new_hs
> highest_seqno_in_use
);
7063 new_hs
= highest_seqno_in_use
;
7065 FOR_EACH_INSN (insn
, ii
, *pscheduled_insns
)
7067 gcc_assert (INSN_SEQNO (insn
) < 0);
7068 INSN_SEQNO (insn
) += highest_seqno_in_use
+ max_seqno
- min_seqno
+ 2;
7069 gcc_assert (INSN_SEQNO (insn
) <= new_hs
);
7072 ilist_clear (pscheduled_insns
);
7078 /* The main driver for scheduling a region. This function is responsible
7079 for correct propagation of fences (i.e. scheduling points) and creating
7080 a group of parallel insns at each of them. It also supports
7081 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7084 sel_sched_region_2 (int orig_max_seqno
)
7086 int highest_seqno_in_use
= orig_max_seqno
;
7088 stat_bookkeeping_copies
= 0;
7089 stat_insns_needed_bookkeeping
= 0;
7090 stat_renamed_scheduled
= 0;
7091 stat_substitutions_total
= 0;
7092 num_insns_scheduled
= 0;
7096 int min_seqno
, max_seqno
;
7097 ilist_t scheduled_insns
= NULL
;
7098 ilist_t
*scheduled_insns_tailp
= &scheduled_insns
;
7100 find_min_max_seqno (fences
, &min_seqno
, &max_seqno
);
7101 schedule_on_fences (fences
, max_seqno
, &scheduled_insns_tailp
);
7102 fences
= calculate_new_fences (fences
, orig_max_seqno
);
7103 highest_seqno_in_use
= update_seqnos_and_stage (min_seqno
, max_seqno
,
7104 highest_seqno_in_use
,
7108 if (sched_verbose
>= 1)
7109 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7110 "bookkeeping, %d insns renamed, %d insns substituted\n",
7111 stat_bookkeeping_copies
,
7112 stat_insns_needed_bookkeeping
,
7113 stat_renamed_scheduled
,
7114 stat_substitutions_total
);
7117 /* Schedule a region. When pipelining, search for possibly never scheduled
7118 bookkeeping code and schedule it. Reschedule pipelined code without
7119 pipelining after. */
7121 sel_sched_region_1 (void)
7123 int number_of_insns
;
7126 /* Remove empty blocks that might be in the region from the beginning.
7127 We need to do save sched_max_luid before that, as it actually shows
7128 the number of insns in the region, and purge_empty_blocks can
7130 number_of_insns
= sched_max_luid
- 1;
7131 purge_empty_blocks ();
7133 orig_max_seqno
= init_seqno (number_of_insns
, NULL
, NULL
);
7134 gcc_assert (orig_max_seqno
>= 1);
7136 /* When pipelining outer loops, create fences on the loop header,
7139 if (current_loop_nest
)
7140 init_fences (BB_END (EBB_FIRST_BB (0)));
7142 init_fences (bb_note (EBB_FIRST_BB (0)));
7145 sel_sched_region_2 (orig_max_seqno
);
7147 gcc_assert (fences
== NULL
);
7153 struct flist_tail_def _new_fences
;
7154 flist_tail_t new_fences
= &_new_fences
;
7157 pipelining_p
= false;
7158 max_ws
= MIN (max_ws
, issue_rate
* 3 / 2);
7159 bookkeeping_p
= false;
7160 enable_schedule_as_rhs_p
= false;
7162 /* Schedule newly created code, that has not been scheduled yet. */
7169 for (i
= 0; i
< current_nr_blocks
; i
++)
7171 basic_block bb
= EBB_FIRST_BB (i
);
7173 if (sel_bb_empty_p (bb
))
7175 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7179 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7181 clear_outdated_rtx_info (bb
);
7182 if (sel_insn_is_speculation_check (BB_END (bb
))
7183 && JUMP_P (BB_END (bb
)))
7184 bitmap_set_bit (blocks_to_reschedule
,
7185 BRANCH_EDGE (bb
)->dest
->index
);
7187 else if (INSN_SCHED_TIMES (sel_bb_head (bb
)) <= 0)
7188 bitmap_set_bit (blocks_to_reschedule
, bb
->index
);
7191 for (i
= 0; i
< current_nr_blocks
; i
++)
7193 bb
= EBB_FIRST_BB (i
);
7195 /* While pipelining outer loops, skip bundling for loop
7196 preheaders. Those will be rescheduled in the outer
7198 if (sel_is_loop_preheader_p (bb
))
7200 clear_outdated_rtx_info (bb
);
7204 if (bitmap_bit_p (blocks_to_reschedule
, bb
->index
))
7206 flist_tail_init (new_fences
);
7208 orig_max_seqno
= init_seqno (0, blocks_to_reschedule
, bb
);
7210 /* Mark BB as head of the new ebb. */
7211 bitmap_set_bit (forced_ebb_heads
, bb
->index
);
7213 bitmap_clear_bit (blocks_to_reschedule
, bb
->index
);
7215 gcc_assert (fences
== NULL
);
7217 init_fences (bb_note (bb
));
7219 sel_sched_region_2 (orig_max_seqno
);
7229 /* Schedule the RGN region. */
7231 sel_sched_region (int rgn
)
7234 bool reset_sched_cycles_p
;
7236 if (sel_region_init (rgn
))
7239 if (sched_verbose
>= 1)
7240 sel_print ("Scheduling region %d\n", rgn
);
7242 schedule_p
= (!sched_is_disabled_for_current_region_p ()
7243 && dbg_cnt (sel_sched_region_cnt
));
7244 reset_sched_cycles_p
= pipelining_p
;
7246 sel_sched_region_1 ();
7248 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7249 reset_sched_cycles_p
= true;
7251 sel_region_finish (reset_sched_cycles_p
);
7254 /* Perform global init for the scheduler. */
7256 sel_global_init (void)
7258 calculate_dominance_info (CDI_DOMINATORS
);
7259 alloc_sched_pools ();
7261 /* Setup the infos for sched_init. */
7262 sel_setup_sched_infos ();
7263 setup_sched_dump ();
7265 sched_rgn_init (false);
7269 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7271 can_issue_more
= issue_rate
;
7273 sched_extend_target ();
7274 sched_deps_init (true);
7275 setup_nop_and_exit_insns ();
7276 sel_extend_global_bb_info ();
7278 init_hard_regs_data ();
7281 /* Free the global data of the scheduler. */
7283 sel_global_finish (void)
7285 free_bb_note_pool ();
7287 sel_finish_global_bb_info ();
7289 free_regset_pool ();
7290 free_nop_and_exit_insns ();
7292 sched_rgn_finish ();
7293 sched_deps_finish ();
7297 sel_finish_pipelining ();
7299 free_sched_pools ();
7300 free_dominance_info (CDI_DOMINATORS
);
7303 /* Return true when we need to skip selective scheduling. Used for debugging. */
7305 maybe_skip_selective_scheduling (void)
7307 return ! dbg_cnt (sel_sched_cnt
);
7310 /* The entry point. */
7312 run_selective_scheduling (void)
7316 if (n_basic_blocks
== NUM_FIXED_BLOCKS
)
7321 for (rgn
= 0; rgn
< nr_regions
; rgn
++)
7322 sel_sched_region (rgn
);
7324 sel_global_finish ();