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c-common.c (c_expand_decl): Remove.
[official-gcc.git] / gcc / longlong.h
blob45a95c40eb55bfd14cd5d45a37a38c67061c0e45
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005, 2007 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 3, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING3. If not see
17 <http://www.gnu.org/licenses/>. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 UQItype -- Unsigned 8 bit type.
27 SItype, USItype -- Signed and unsigned 32 bit types.
28 DItype, UDItype -- Signed and unsigned 64 bit types.
29
30 On a 32 bit machine UWtype should typically be USItype;
31 on a 64 bit machine, UWtype should typically be UDItype. */
32
33 #define __BITS4 (W_TYPE_SIZE / 4)
34 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
35 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
36 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
37
38 #ifndef W_TYPE_SIZE
39 #define W_TYPE_SIZE 32
40 #define UWtype USItype
41 #define UHWtype USItype
42 #define UDWtype UDItype
43 #endif
44
45 extern const UQItype __clz_tab[256];
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
50 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 (ph) = __builtin_alpha_umulh (__m0, __m1); \
115 (pl) = __m0 * __m1; \
116 } while (0)
117 #define UMUL_TIME 46
118 #ifndef LONGLONG_STANDALONE
119 #define udiv_qrnnd(q, r, n1, n0, d) \
120 do { UDItype __r; \
121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
122 (r) = __r; \
123 } while (0)
124 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
125 #define UDIV_TIME 220
126 #endif /* LONGLONG_STANDALONE */
127 #ifdef __alpha_cix__
128 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
129 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
130 #define COUNT_LEADING_ZEROS_0 64
131 #else
132 #define count_leading_zeros(COUNT,X) \
133 do { \
134 UDItype __xr = (X), __t, __a; \
135 __t = __builtin_alpha_cmpbge (0, __xr); \
136 __a = __clz_tab[__t ^ 0xff] - 1; \
137 __t = __builtin_alpha_extbl (__xr, __a); \
138 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
139 } while (0)
140 #define count_trailing_zeros(COUNT,X) \
141 do { \
142 UDItype __xr = (X), __t, __a; \
143 __t = __builtin_alpha_cmpbge (0, __xr); \
144 __t = ~__t & -~__t; \
145 __a = ((__t & 0xCC) != 0) * 2; \
146 __a += ((__t & 0xF0) != 0) * 4; \
147 __a += ((__t & 0xAA) != 0); \
148 __t = __builtin_alpha_extbl (__xr, __a); \
149 __a <<= 3; \
150 __t &= -__t; \
151 __a += ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 (COUNT) = __a; \
155 } while (0)
156 #endif /* __alpha_cix__ */
157 #endif /* __alpha */
158
159 #if defined (__arc__) && W_TYPE_SIZE == 32
160 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
161 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
162 : "=r" ((USItype) (sh)), \
163 "=&r" ((USItype) (sl)) \
164 : "%r" ((USItype) (ah)), \
165 "rIJ" ((USItype) (bh)), \
166 "%r" ((USItype) (al)), \
167 "rIJ" ((USItype) (bl)))
168 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
169 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
170 : "=r" ((USItype) (sh)), \
171 "=&r" ((USItype) (sl)) \
172 : "r" ((USItype) (ah)), \
173 "rIJ" ((USItype) (bh)), \
174 "r" ((USItype) (al)), \
175 "rIJ" ((USItype) (bl)))
176 /* Call libgcc routine. */
177 #define umul_ppmm(w1, w0, u, v) \
178 do { \
179 DWunion __w; \
180 __w.ll = __umulsidi3 (u, v); \
181 w1 = __w.s.high; \
182 w0 = __w.s.low; \
183 } while (0)
184 #define __umulsidi3 __umulsidi3
185 UDItype __umulsidi3 (USItype, USItype);
186 #endif
187
188 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
189 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
190 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
191 : "=r" ((USItype) (sh)), \
192 "=&r" ((USItype) (sl)) \
193 : "%r" ((USItype) (ah)), \
194 "rI" ((USItype) (bh)), \
195 "%r" ((USItype) (al)), \
196 "rI" ((USItype) (bl)) __CLOBBER_CC)
197 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
198 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
199 : "=r" ((USItype) (sh)), \
200 "=&r" ((USItype) (sl)) \
201 : "r" ((USItype) (ah)), \
202 "rI" ((USItype) (bh)), \
203 "r" ((USItype) (al)), \
204 "rI" ((USItype) (bl)) __CLOBBER_CC)
205 #define umul_ppmm(xh, xl, a, b) \
206 {register USItype __t0, __t1, __t2; \
207 __asm__ ("%@ Inlined umul_ppmm\n" \
208 " mov %2, %5, lsr #16\n" \
209 " mov %0, %6, lsr #16\n" \
210 " bic %3, %5, %2, lsl #16\n" \
211 " bic %4, %6, %0, lsl #16\n" \
212 " mul %1, %3, %4\n" \
213 " mul %4, %2, %4\n" \
214 " mul %3, %0, %3\n" \
215 " mul %0, %2, %0\n" \
216 " adds %3, %4, %3\n" \
217 " addcs %0, %0, #65536\n" \
218 " adds %1, %1, %3, lsl #16\n" \
219 " adc %0, %0, %3, lsr #16" \
220 : "=&r" ((USItype) (xh)), \
221 "=r" ((USItype) (xl)), \
222 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
223 : "r" ((USItype) (a)), \
224 "r" ((USItype) (b)) __CLOBBER_CC );}
225 #define UMUL_TIME 20
226 #define UDIV_TIME 100
227 #endif /* __arm__ */
228
229 #if defined(__arm__)
230 /* Let gcc decide how best to implement count_leading_zeros. */
231 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
232 #define COUNT_LEADING_ZEROS_0 32
233 #endif
234
235 #if defined (__CRIS__) && __CRIS_arch_version >= 3
236 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
237 #if __CRIS_arch_version >= 8
238 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
239 #endif
240 #endif /* __CRIS__ */
241
242 #if defined (__hppa) && W_TYPE_SIZE == 32
243 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
244 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
245 : "=r" ((USItype) (sh)), \
246 "=&r" ((USItype) (sl)) \
247 : "%rM" ((USItype) (ah)), \
248 "rM" ((USItype) (bh)), \
249 "%rM" ((USItype) (al)), \
250 "rM" ((USItype) (bl)))
251 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
252 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
253 : "=r" ((USItype) (sh)), \
254 "=&r" ((USItype) (sl)) \
255 : "rM" ((USItype) (ah)), \
256 "rM" ((USItype) (bh)), \
257 "rM" ((USItype) (al)), \
258 "rM" ((USItype) (bl)))
259 #if defined (_PA_RISC1_1)
260 #define umul_ppmm(w1, w0, u, v) \
261 do { \
262 union \
263 { \
264 UDItype __f; \
265 struct {USItype __w1, __w0;} __w1w0; \
266 } __t; \
267 __asm__ ("xmpyu %1,%2,%0" \
268 : "=x" (__t.__f) \
269 : "x" ((USItype) (u)), \
270 "x" ((USItype) (v))); \
271 (w1) = __t.__w1w0.__w1; \
272 (w0) = __t.__w1w0.__w0; \
273 } while (0)
274 #define UMUL_TIME 8
275 #else
276 #define UMUL_TIME 30
277 #endif
278 #define UDIV_TIME 40
279 #define count_leading_zeros(count, x) \
280 do { \
281 USItype __tmp; \
282 __asm__ ( \
283 "ldi 1,%0\n" \
284 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
285 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
286 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
287 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
288 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
289 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
290 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
291 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
292 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
293 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
294 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
295 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
296 " extru %1,30,1,%1 ; Extract bit 1.\n" \
297 " sub %0,%1,%0 ; Subtract it.\n" \
298 : "=r" (count), "=r" (__tmp) : "1" (x)); \
299 } while (0)
300 #endif
301
302 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
303 #define smul_ppmm(xh, xl, m0, m1) \
304 do { \
305 union {DItype __ll; \
306 struct {USItype __h, __l;} __i; \
307 } __x; \
308 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
309 : "=&r" (__x.__ll) \
310 : "r" (m0), "r" (m1)); \
311 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
312 } while (0)
313 #define sdiv_qrnnd(q, r, n1, n0, d) \
314 do { \
315 union {DItype __ll; \
316 struct {USItype __h, __l;} __i; \
317 } __x; \
318 __x.__i.__h = n1; __x.__i.__l = n0; \
319 __asm__ ("dr %0,%2" \
320 : "=r" (__x.__ll) \
321 : "0" (__x.__ll), "r" (d)); \
322 (q) = __x.__i.__l; (r) = __x.__i.__h; \
323 } while (0)
324 #endif
325
326 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
327 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
328 __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
329 : "=r" ((USItype) (sh)), \
330 "=&r" ((USItype) (sl)) \
331 : "%0" ((USItype) (ah)), \
332 "g" ((USItype) (bh)), \
333 "%1" ((USItype) (al)), \
334 "g" ((USItype) (bl)))
335 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
336 __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
337 : "=r" ((USItype) (sh)), \
338 "=&r" ((USItype) (sl)) \
339 : "0" ((USItype) (ah)), \
340 "g" ((USItype) (bh)), \
341 "1" ((USItype) (al)), \
342 "g" ((USItype) (bl)))
343 #define umul_ppmm(w1, w0, u, v) \
344 __asm__ ("mul{l} %3" \
345 : "=a" ((USItype) (w0)), \
346 "=d" ((USItype) (w1)) \
347 : "%0" ((USItype) (u)), \
348 "rm" ((USItype) (v)))
349 #define udiv_qrnnd(q, r, n1, n0, dv) \
350 __asm__ ("div{l} %4" \
351 : "=a" ((USItype) (q)), \
352 "=d" ((USItype) (r)) \
353 : "0" ((USItype) (n0)), \
354 "1" ((USItype) (n1)), \
355 "rm" ((USItype) (dv)))
356 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
357 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
358 #define UMUL_TIME 40
359 #define UDIV_TIME 40
360 #endif /* 80x86 */
361
362 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
363 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
364 __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
365 : "=r" ((UDItype) (sh)), \
366 "=&r" ((UDItype) (sl)) \
367 : "%0" ((UDItype) (ah)), \
368 "rme" ((UDItype) (bh)), \
369 "%1" ((UDItype) (al)), \
370 "rme" ((UDItype) (bl)))
371 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
372 __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
373 : "=r" ((UDItype) (sh)), \
374 "=&r" ((UDItype) (sl)) \
375 : "0" ((UDItype) (ah)), \
376 "rme" ((UDItype) (bh)), \
377 "1" ((UDItype) (al)), \
378 "rme" ((UDItype) (bl)))
379 #define umul_ppmm(w1, w0, u, v) \
380 __asm__ ("mul{q} %3" \
381 : "=a" ((UDItype) (w0)), \
382 "=d" ((UDItype) (w1)) \
383 : "%0" ((UDItype) (u)), \
384 "rm" ((UDItype) (v)))
385 #define udiv_qrnnd(q, r, n1, n0, dv) \
386 __asm__ ("div{q} %4" \
387 : "=a" ((UDItype) (q)), \
388 "=d" ((UDItype) (r)) \
389 : "0" ((UDItype) (n0)), \
390 "1" ((UDItype) (n1)), \
391 "rm" ((UDItype) (dv)))
392 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
393 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
394 #define UMUL_TIME 40
395 #define UDIV_TIME 40
396 #endif /* x86_64 */
397
398 #if defined (__i960__) && W_TYPE_SIZE == 32
399 #define umul_ppmm(w1, w0, u, v) \
400 ({union {UDItype __ll; \
401 struct {USItype __l, __h;} __i; \
402 } __xx; \
403 __asm__ ("emul %2,%1,%0" \
404 : "=d" (__xx.__ll) \
405 : "%dI" ((USItype) (u)), \
406 "dI" ((USItype) (v))); \
407 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
408 #define __umulsidi3(u, v) \
409 ({UDItype __w; \
410 __asm__ ("emul %2,%1,%0" \
411 : "=d" (__w) \
412 : "%dI" ((USItype) (u)), \
413 "dI" ((USItype) (v))); \
414 __w; })
415 #endif /* __i960__ */
416
417 #if defined (__M32R__) && W_TYPE_SIZE == 32
418 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
419 /* The cmp clears the condition bit. */ \
420 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
421 : "=r" ((USItype) (sh)), \
422 "=&r" ((USItype) (sl)) \
423 : "0" ((USItype) (ah)), \
424 "r" ((USItype) (bh)), \
425 "1" ((USItype) (al)), \
426 "r" ((USItype) (bl)) \
427 : "cbit")
428 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
429 /* The cmp clears the condition bit. */ \
430 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
431 : "=r" ((USItype) (sh)), \
432 "=&r" ((USItype) (sl)) \
433 : "0" ((USItype) (ah)), \
434 "r" ((USItype) (bh)), \
435 "1" ((USItype) (al)), \
436 "r" ((USItype) (bl)) \
437 : "cbit")
438 #endif /* __M32R__ */
439
440 #if defined (__mc68000__) && W_TYPE_SIZE == 32
441 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
442 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
443 : "=d" ((USItype) (sh)), \
444 "=&d" ((USItype) (sl)) \
445 : "%0" ((USItype) (ah)), \
446 "d" ((USItype) (bh)), \
447 "%1" ((USItype) (al)), \
448 "g" ((USItype) (bl)))
449 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
450 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
451 : "=d" ((USItype) (sh)), \
452 "=&d" ((USItype) (sl)) \
453 : "0" ((USItype) (ah)), \
454 "d" ((USItype) (bh)), \
455 "1" ((USItype) (al)), \
456 "g" ((USItype) (bl)))
457
458 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
459 #if (defined (__mc68020__) && !defined (__mc68060__))
460 #define umul_ppmm(w1, w0, u, v) \
461 __asm__ ("mulu%.l %3,%1:%0" \
462 : "=d" ((USItype) (w0)), \
463 "=d" ((USItype) (w1)) \
464 : "%0" ((USItype) (u)), \
465 "dmi" ((USItype) (v)))
466 #define UMUL_TIME 45
467 #define udiv_qrnnd(q, r, n1, n0, d) \
468 __asm__ ("divu%.l %4,%1:%0" \
469 : "=d" ((USItype) (q)), \
470 "=d" ((USItype) (r)) \
471 : "0" ((USItype) (n0)), \
472 "1" ((USItype) (n1)), \
473 "dmi" ((USItype) (d)))
474 #define UDIV_TIME 90
475 #define sdiv_qrnnd(q, r, n1, n0, d) \
476 __asm__ ("divs%.l %4,%1:%0" \
477 : "=d" ((USItype) (q)), \
478 "=d" ((USItype) (r)) \
479 : "0" ((USItype) (n0)), \
480 "1" ((USItype) (n1)), \
481 "dmi" ((USItype) (d)))
482
483 #elif defined (__mcoldfire__) /* not mc68020 */
484
485 #define umul_ppmm(xh, xl, a, b) \
486 __asm__ ("| Inlined umul_ppmm\n" \
487 " move%.l %2,%/d0\n" \
488 " move%.l %3,%/d1\n" \
489 " move%.l %/d0,%/d2\n" \
490 " swap %/d0\n" \
491 " move%.l %/d1,%/d3\n" \
492 " swap %/d1\n" \
493 " move%.w %/d2,%/d4\n" \
494 " mulu %/d3,%/d4\n" \
495 " mulu %/d1,%/d2\n" \
496 " mulu %/d0,%/d3\n" \
497 " mulu %/d0,%/d1\n" \
498 " move%.l %/d4,%/d0\n" \
499 " clr%.w %/d0\n" \
500 " swap %/d0\n" \
501 " add%.l %/d0,%/d2\n" \
502 " add%.l %/d3,%/d2\n" \
503 " jcc 1f\n" \
504 " add%.l %#65536,%/d1\n" \
505 "1: swap %/d2\n" \
506 " moveq %#0,%/d0\n" \
507 " move%.w %/d2,%/d0\n" \
508 " move%.w %/d4,%/d2\n" \
509 " move%.l %/d2,%1\n" \
510 " add%.l %/d1,%/d0\n" \
511 " move%.l %/d0,%0" \
512 : "=g" ((USItype) (xh)), \
513 "=g" ((USItype) (xl)) \
514 : "g" ((USItype) (a)), \
515 "g" ((USItype) (b)) \
516 : "d0", "d1", "d2", "d3", "d4")
517 #define UMUL_TIME 100
518 #define UDIV_TIME 400
519 #else /* not ColdFire */
520 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
521 #define umul_ppmm(xh, xl, a, b) \
522 __asm__ ("| Inlined umul_ppmm\n" \
523 " move%.l %2,%/d0\n" \
524 " move%.l %3,%/d1\n" \
525 " move%.l %/d0,%/d2\n" \
526 " swap %/d0\n" \
527 " move%.l %/d1,%/d3\n" \
528 " swap %/d1\n" \
529 " move%.w %/d2,%/d4\n" \
530 " mulu %/d3,%/d4\n" \
531 " mulu %/d1,%/d2\n" \
532 " mulu %/d0,%/d3\n" \
533 " mulu %/d0,%/d1\n" \
534 " move%.l %/d4,%/d0\n" \
535 " eor%.w %/d0,%/d0\n" \
536 " swap %/d0\n" \
537 " add%.l %/d0,%/d2\n" \
538 " add%.l %/d3,%/d2\n" \
539 " jcc 1f\n" \
540 " add%.l %#65536,%/d1\n" \
541 "1: swap %/d2\n" \
542 " moveq %#0,%/d0\n" \
543 " move%.w %/d2,%/d0\n" \
544 " move%.w %/d4,%/d2\n" \
545 " move%.l %/d2,%1\n" \
546 " add%.l %/d1,%/d0\n" \
547 " move%.l %/d0,%0" \
548 : "=g" ((USItype) (xh)), \
549 "=g" ((USItype) (xl)) \
550 : "g" ((USItype) (a)), \
551 "g" ((USItype) (b)) \
552 : "d0", "d1", "d2", "d3", "d4")
553 #define UMUL_TIME 100
554 #define UDIV_TIME 400
555
556 #endif /* not mc68020 */
557
558 /* The '020, '030, '040 and '060 have bitfield insns.
559 cpu32 disguises as a 68020, but lacks them. */
560 #if defined (__mc68020__) && !defined (__mcpu32__)
561 #define count_leading_zeros(count, x) \
562 __asm__ ("bfffo %1{%b2:%b2},%0" \
563 : "=d" ((USItype) (count)) \
564 : "od" ((USItype) (x)), "n" (0))
565 /* Some ColdFire architectures have a ff1 instruction supported via
566 __builtin_clz. */
567 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
568 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
569 #define COUNT_LEADING_ZEROS_0 32
570 #endif
571 #endif /* mc68000 */
572
573 #if defined (__m88000__) && W_TYPE_SIZE == 32
574 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
575 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
576 : "=r" ((USItype) (sh)), \
577 "=&r" ((USItype) (sl)) \
578 : "%rJ" ((USItype) (ah)), \
579 "rJ" ((USItype) (bh)), \
580 "%rJ" ((USItype) (al)), \
581 "rJ" ((USItype) (bl)))
582 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
583 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
584 : "=r" ((USItype) (sh)), \
585 "=&r" ((USItype) (sl)) \
586 : "rJ" ((USItype) (ah)), \
587 "rJ" ((USItype) (bh)), \
588 "rJ" ((USItype) (al)), \
589 "rJ" ((USItype) (bl)))
590 #define count_leading_zeros(count, x) \
591 do { \
592 USItype __cbtmp; \
593 __asm__ ("ff1 %0,%1" \
594 : "=r" (__cbtmp) \
595 : "r" ((USItype) (x))); \
596 (count) = __cbtmp ^ 31; \
597 } while (0)
598 #define COUNT_LEADING_ZEROS_0 63 /* sic */
599 #if defined (__mc88110__)
600 #define umul_ppmm(wh, wl, u, v) \
601 do { \
602 union {UDItype __ll; \
603 struct {USItype __h, __l;} __i; \
604 } __xx; \
605 __asm__ ("mulu.d %0,%1,%2" \
606 : "=r" (__xx.__ll) \
607 : "r" ((USItype) (u)), \
608 "r" ((USItype) (v))); \
609 (wh) = __xx.__i.__h; \
610 (wl) = __xx.__i.__l; \
611 } while (0)
612 #define udiv_qrnnd(q, r, n1, n0, d) \
613 ({union {UDItype __ll; \
614 struct {USItype __h, __l;} __i; \
615 } __xx; \
616 USItype __q; \
617 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
618 __asm__ ("divu.d %0,%1,%2" \
619 : "=r" (__q) \
620 : "r" (__xx.__ll), \
621 "r" ((USItype) (d))); \
622 (r) = (n0) - __q * (d); (q) = __q; })
623 #define UMUL_TIME 5
624 #define UDIV_TIME 25
625 #else
626 #define UMUL_TIME 17
627 #define UDIV_TIME 150
628 #endif /* __mc88110__ */
629 #endif /* __m88000__ */
630
631 #if defined (__mips__) && W_TYPE_SIZE == 32
632 #define umul_ppmm(w1, w0, u, v) \
633 do { \
634 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
635 (w1) = (USItype) (__x >> 32); \
636 (w0) = (USItype) (__x); \
637 } while (0)
638 #define UMUL_TIME 10
639 #define UDIV_TIME 100
640
641 #if (__mips == 32 || __mips == 64) && ! __mips16
642 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
643 #define COUNT_LEADING_ZEROS_0 32
644 #endif
645 #endif /* __mips__ */
646
647 #if defined (__ns32000__) && W_TYPE_SIZE == 32
648 #define umul_ppmm(w1, w0, u, v) \
649 ({union {UDItype __ll; \
650 struct {USItype __l, __h;} __i; \
651 } __xx; \
652 __asm__ ("meid %2,%0" \
653 : "=g" (__xx.__ll) \
654 : "%0" ((USItype) (u)), \
655 "g" ((USItype) (v))); \
656 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
657 #define __umulsidi3(u, v) \
658 ({UDItype __w; \
659 __asm__ ("meid %2,%0" \
660 : "=g" (__w) \
661 : "%0" ((USItype) (u)), \
662 "g" ((USItype) (v))); \
663 __w; })
664 #define udiv_qrnnd(q, r, n1, n0, d) \
665 ({union {UDItype __ll; \
666 struct {USItype __l, __h;} __i; \
667 } __xx; \
668 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
669 __asm__ ("deid %2,%0" \
670 : "=g" (__xx.__ll) \
671 : "0" (__xx.__ll), \
672 "g" ((USItype) (d))); \
673 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
674 #define count_trailing_zeros(count,x) \
675 do { \
676 __asm__ ("ffsd %2,%0" \
677 : "=r" ((USItype) (count)) \
678 : "0" ((USItype) 0), \
679 "r" ((USItype) (x))); \
680 } while (0)
681 #endif /* __ns32000__ */
682
683 /* FIXME: We should test _IBMR2 here when we add assembly support for the
684 system vendor compilers.
685 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
686 enough, since that hits ARM and m68k too. */
687 #if (defined (_ARCH_PPC) /* AIX */ \
688 || defined (_ARCH_PWR) /* AIX */ \
689 || defined (_ARCH_COM) /* AIX */ \
690 || defined (__powerpc__) /* gcc */ \
691 || defined (__POWERPC__) /* BEOS */ \
692 || defined (__ppc__) /* Darwin */ \
693 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
694 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
695 && CPU_FAMILY == PPC) \
696 ) && W_TYPE_SIZE == 32
697 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
698 do { \
699 if (__builtin_constant_p (bh) && (bh) == 0) \
700 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
701 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
702 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
703 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
704 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
705 else \
706 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
707 : "=r" (sh), "=&r" (sl) \
708 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
709 } while (0)
710 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
711 do { \
712 if (__builtin_constant_p (ah) && (ah) == 0) \
713 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
714 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
715 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
716 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
717 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
718 else if (__builtin_constant_p (bh) && (bh) == 0) \
719 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
720 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
721 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
722 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
723 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
724 else \
725 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
726 : "=r" (sh), "=&r" (sl) \
727 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
728 } while (0)
729 #define count_leading_zeros(count, x) \
730 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
731 #define COUNT_LEADING_ZEROS_0 32
732 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
733 || defined (__ppc__) \
734 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
735 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
736 && CPU_FAMILY == PPC)
737 #define umul_ppmm(ph, pl, m0, m1) \
738 do { \
739 USItype __m0 = (m0), __m1 = (m1); \
740 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
741 (pl) = __m0 * __m1; \
742 } while (0)
743 #define UMUL_TIME 15
744 #define smul_ppmm(ph, pl, m0, m1) \
745 do { \
746 SItype __m0 = (m0), __m1 = (m1); \
747 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
748 (pl) = __m0 * __m1; \
749 } while (0)
750 #define SMUL_TIME 14
751 #define UDIV_TIME 120
752 #elif defined (_ARCH_PWR)
753 #define UMUL_TIME 8
754 #define smul_ppmm(xh, xl, m0, m1) \
755 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
756 #define SMUL_TIME 4
757 #define sdiv_qrnnd(q, r, nh, nl, d) \
758 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
759 #define UDIV_TIME 100
760 #endif
761 #endif /* 32-bit POWER architecture variants. */
762
763 /* We should test _IBMR2 here when we add assembly support for the system
764 vendor compilers. */
765 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
766 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
767 do { \
768 if (__builtin_constant_p (bh) && (bh) == 0) \
769 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
770 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
771 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
772 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
773 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
774 else \
775 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
776 : "=r" (sh), "=&r" (sl) \
777 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
778 } while (0)
779 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
780 do { \
781 if (__builtin_constant_p (ah) && (ah) == 0) \
782 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
783 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
784 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
785 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
786 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
787 else if (__builtin_constant_p (bh) && (bh) == 0) \
788 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
789 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
790 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
791 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
792 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
793 else \
794 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
795 : "=r" (sh), "=&r" (sl) \
796 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
797 } while (0)
798 #define count_leading_zeros(count, x) \
799 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
800 #define COUNT_LEADING_ZEROS_0 64
801 #define umul_ppmm(ph, pl, m0, m1) \
802 do { \
803 UDItype __m0 = (m0), __m1 = (m1); \
804 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
805 (pl) = __m0 * __m1; \
806 } while (0)
807 #define UMUL_TIME 15
808 #define smul_ppmm(ph, pl, m0, m1) \
809 do { \
810 DItype __m0 = (m0), __m1 = (m1); \
811 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
812 (pl) = __m0 * __m1; \
813 } while (0)
814 #define SMUL_TIME 14 /* ??? */
815 #define UDIV_TIME 120 /* ??? */
816 #endif /* 64-bit PowerPC. */
817
818 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
819 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
820 __asm__ ("a %1,%5\n\tae %0,%3" \
821 : "=r" ((USItype) (sh)), \
822 "=&r" ((USItype) (sl)) \
823 : "%0" ((USItype) (ah)), \
824 "r" ((USItype) (bh)), \
825 "%1" ((USItype) (al)), \
826 "r" ((USItype) (bl)))
827 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
828 __asm__ ("s %1,%5\n\tse %0,%3" \
829 : "=r" ((USItype) (sh)), \
830 "=&r" ((USItype) (sl)) \
831 : "0" ((USItype) (ah)), \
832 "r" ((USItype) (bh)), \
833 "1" ((USItype) (al)), \
834 "r" ((USItype) (bl)))
835 #define umul_ppmm(ph, pl, m0, m1) \
836 do { \
837 USItype __m0 = (m0), __m1 = (m1); \
838 __asm__ ( \
839 "s r2,r2\n" \
840 " mts r10,%2\n" \
841 " m r2,%3\n" \
842 " m r2,%3\n" \
843 " m r2,%3\n" \
844 " m r2,%3\n" \
845 " m r2,%3\n" \
846 " m r2,%3\n" \
847 " m r2,%3\n" \
848 " m r2,%3\n" \
849 " m r2,%3\n" \
850 " m r2,%3\n" \
851 " m r2,%3\n" \
852 " m r2,%3\n" \
853 " m r2,%3\n" \
854 " m r2,%3\n" \
855 " m r2,%3\n" \
856 " m r2,%3\n" \
857 " cas %0,r2,r0\n" \
858 " mfs r10,%1" \
859 : "=r" ((USItype) (ph)), \
860 "=r" ((USItype) (pl)) \
861 : "%r" (__m0), \
862 "r" (__m1) \
863 : "r2"); \
864 (ph) += ((((SItype) __m0 >> 31) & __m1) \
865 + (((SItype) __m1 >> 31) & __m0)); \
866 } while (0)
867 #define UMUL_TIME 20
868 #define UDIV_TIME 200
869 #define count_leading_zeros(count, x) \
870 do { \
871 if ((x) >= 0x10000) \
872 __asm__ ("clz %0,%1" \
873 : "=r" ((USItype) (count)) \
874 : "r" ((USItype) (x) >> 16)); \
875 else \
876 { \
877 __asm__ ("clz %0,%1" \
878 : "=r" ((USItype) (count)) \
879 : "r" ((USItype) (x))); \
880 (count) += 16; \
881 } \
882 } while (0)
883 #endif
884
885 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
886 #ifndef __sh1__
887 #define umul_ppmm(w1, w0, u, v) \
888 __asm__ ( \
889 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
890 : "=r<" ((USItype)(w1)), \
891 "=r<" ((USItype)(w0)) \
892 : "r" ((USItype)(u)), \
893 "r" ((USItype)(v)) \
894 : "macl", "mach")
895 #define UMUL_TIME 5
896 #endif
897
898 /* This is the same algorithm as __udiv_qrnnd_c. */
899 #define UDIV_NEEDS_NORMALIZATION 1
900
901 #define udiv_qrnnd(q, r, n1, n0, d) \
902 do { \
903 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
904 __attribute__ ((visibility ("hidden"))); \
905 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
906 __asm__ ( \
907 "mov%M4 %4,r5\n" \
908 " swap.w %3,r4\n" \
909 " swap.w r5,r6\n" \
910 " jsr @%5\n" \
911 " shll16 r6\n" \
912 " swap.w r4,r4\n" \
913 " jsr @%5\n" \
914 " swap.w r1,%0\n" \
915 " or r1,%0" \
916 : "=r" (q), "=&z" (r) \
917 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
918 : "r1", "r2", "r4", "r5", "r6", "pr"); \
919 } while (0)
920
921 #define UDIV_TIME 80
922
923 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
924 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
925 : "=r" (sh), "=r" (sl) \
926 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
927
928 #endif /* __sh__ */
929
930 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
931 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
932 #define count_leading_zeros(count, x) \
933 do \
934 { \
935 UDItype x_ = (USItype)(x); \
936 SItype c_; \
937 \
938 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
939 (count) = c_ - 31; \
940 } \
941 while (0)
942 #define COUNT_LEADING_ZEROS_0 32
943 #endif
944
945 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
946 && W_TYPE_SIZE == 32
947 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
948 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
949 : "=r" ((USItype) (sh)), \
950 "=&r" ((USItype) (sl)) \
951 : "%rJ" ((USItype) (ah)), \
952 "rI" ((USItype) (bh)), \
953 "%rJ" ((USItype) (al)), \
954 "rI" ((USItype) (bl)) \
955 __CLOBBER_CC)
956 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
957 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
958 : "=r" ((USItype) (sh)), \
959 "=&r" ((USItype) (sl)) \
960 : "rJ" ((USItype) (ah)), \
961 "rI" ((USItype) (bh)), \
962 "rJ" ((USItype) (al)), \
963 "rI" ((USItype) (bl)) \
964 __CLOBBER_CC)
965 #if defined (__sparc_v8__)
966 #define umul_ppmm(w1, w0, u, v) \
967 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
968 : "=r" ((USItype) (w1)), \
969 "=r" ((USItype) (w0)) \
970 : "r" ((USItype) (u)), \
971 "r" ((USItype) (v)))
972 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
973 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
974 : "=&r" ((USItype) (__q)), \
975 "=&r" ((USItype) (__r)) \
976 : "r" ((USItype) (__n1)), \
977 "r" ((USItype) (__n0)), \
978 "r" ((USItype) (__d)))
979 #else
980 #if defined (__sparclite__)
981 /* This has hardware multiply but not divide. It also has two additional
982 instructions scan (ffs from high bit) and divscc. */
983 #define umul_ppmm(w1, w0, u, v) \
984 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
985 : "=r" ((USItype) (w1)), \
986 "=r" ((USItype) (w0)) \
987 : "r" ((USItype) (u)), \
988 "r" ((USItype) (v)))
989 #define udiv_qrnnd(q, r, n1, n0, d) \
990 __asm__ ("! Inlined udiv_qrnnd\n" \
991 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
992 " tst %%g0\n" \
993 " divscc %3,%4,%%g1\n" \
994 " divscc %%g1,%4,%%g1\n" \
995 " divscc %%g1,%4,%%g1\n" \
996 " divscc %%g1,%4,%%g1\n" \
997 " divscc %%g1,%4,%%g1\n" \
998 " divscc %%g1,%4,%%g1\n" \
999 " divscc %%g1,%4,%%g1\n" \
1000 " divscc %%g1,%4,%%g1\n" \
1001 " divscc %%g1,%4,%%g1\n" \
1002 " divscc %%g1,%4,%%g1\n" \
1003 " divscc %%g1,%4,%%g1\n" \
1004 " divscc %%g1,%4,%%g1\n" \
1005 " divscc %%g1,%4,%%g1\n" \
1006 " divscc %%g1,%4,%%g1\n" \
1007 " divscc %%g1,%4,%%g1\n" \
1008 " divscc %%g1,%4,%%g1\n" \
1009 " divscc %%g1,%4,%%g1\n" \
1010 " divscc %%g1,%4,%%g1\n" \
1011 " divscc %%g1,%4,%%g1\n" \
1012 " divscc %%g1,%4,%%g1\n" \
1013 " divscc %%g1,%4,%%g1\n" \
1014 " divscc %%g1,%4,%%g1\n" \
1015 " divscc %%g1,%4,%%g1\n" \
1016 " divscc %%g1,%4,%%g1\n" \
1017 " divscc %%g1,%4,%%g1\n" \
1018 " divscc %%g1,%4,%%g1\n" \
1019 " divscc %%g1,%4,%%g1\n" \
1020 " divscc %%g1,%4,%%g1\n" \
1021 " divscc %%g1,%4,%%g1\n" \
1022 " divscc %%g1,%4,%%g1\n" \
1023 " divscc %%g1,%4,%%g1\n" \
1024 " divscc %%g1,%4,%0\n" \
1025 " rd %%y,%1\n" \
1026 " bl,a 1f\n" \
1027 " add %1,%4,%1\n" \
1028 "1: ! End of inline udiv_qrnnd" \
1029 : "=r" ((USItype) (q)), \
1030 "=r" ((USItype) (r)) \
1031 : "r" ((USItype) (n1)), \
1032 "r" ((USItype) (n0)), \
1033 "rI" ((USItype) (d)) \
1034 : "g1" __AND_CLOBBER_CC)
1035 #define UDIV_TIME 37
1036 #define count_leading_zeros(count, x) \
1037 do { \
1038 __asm__ ("scan %1,1,%0" \
1039 : "=r" ((USItype) (count)) \
1040 : "r" ((USItype) (x))); \
1041 } while (0)
1042 /* Early sparclites return 63 for an argument of 0, but they warn that future
1043 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1044 undefined. */
1045 #else
1046 /* SPARC without integer multiplication and divide instructions.
1047 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1048 #define umul_ppmm(w1, w0, u, v) \
1049 __asm__ ("! Inlined umul_ppmm\n" \
1050 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1051 " sra %3,31,%%o5 ! Don't move this insn\n" \
1052 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1053 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1054 " mulscc %%g1,%3,%%g1\n" \
1055 " mulscc %%g1,%3,%%g1\n" \
1056 " mulscc %%g1,%3,%%g1\n" \
1057 " mulscc %%g1,%3,%%g1\n" \
1058 " mulscc %%g1,%3,%%g1\n" \
1059 " mulscc %%g1,%3,%%g1\n" \
1060 " mulscc %%g1,%3,%%g1\n" \
1061 " mulscc %%g1,%3,%%g1\n" \
1062 " mulscc %%g1,%3,%%g1\n" \
1063 " mulscc %%g1,%3,%%g1\n" \
1064 " mulscc %%g1,%3,%%g1\n" \
1065 " mulscc %%g1,%3,%%g1\n" \
1066 " mulscc %%g1,%3,%%g1\n" \
1067 " mulscc %%g1,%3,%%g1\n" \
1068 " mulscc %%g1,%3,%%g1\n" \
1069 " mulscc %%g1,%3,%%g1\n" \
1070 " mulscc %%g1,%3,%%g1\n" \
1071 " mulscc %%g1,%3,%%g1\n" \
1072 " mulscc %%g1,%3,%%g1\n" \
1073 " mulscc %%g1,%3,%%g1\n" \
1074 " mulscc %%g1,%3,%%g1\n" \
1075 " mulscc %%g1,%3,%%g1\n" \
1076 " mulscc %%g1,%3,%%g1\n" \
1077 " mulscc %%g1,%3,%%g1\n" \
1078 " mulscc %%g1,%3,%%g1\n" \
1079 " mulscc %%g1,%3,%%g1\n" \
1080 " mulscc %%g1,%3,%%g1\n" \
1081 " mulscc %%g1,%3,%%g1\n" \
1082 " mulscc %%g1,%3,%%g1\n" \
1083 " mulscc %%g1,%3,%%g1\n" \
1084 " mulscc %%g1,%3,%%g1\n" \
1085 " mulscc %%g1,%3,%%g1\n" \
1086 " mulscc %%g1,0,%%g1\n" \
1087 " add %%g1,%%o5,%0\n" \
1088 " rd %%y,%1" \
1089 : "=r" ((USItype) (w1)), \
1090 "=r" ((USItype) (w0)) \
1091 : "%rI" ((USItype) (u)), \
1092 "r" ((USItype) (v)) \
1093 : "g1", "o5" __AND_CLOBBER_CC)
1094 #define UMUL_TIME 39 /* 39 instructions */
1095 /* It's quite necessary to add this much assembler for the sparc.
1096 The default udiv_qrnnd (in C) is more than 10 times slower! */
1097 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1098 __asm__ ("! Inlined udiv_qrnnd\n" \
1099 " mov 32,%%g1\n" \
1100 " subcc %1,%2,%%g0\n" \
1101 "1: bcs 5f\n" \
1102 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1103 " sub %1,%2,%1 ! this kills msb of n\n" \
1104 " addx %1,%1,%1 ! so this can't give carry\n" \
1105 " subcc %%g1,1,%%g1\n" \
1106 "2: bne 1b\n" \
1107 " subcc %1,%2,%%g0\n" \
1108 " bcs 3f\n" \
1109 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1110 " b 3f\n" \
1111 " sub %1,%2,%1 ! this kills msb of n\n" \
1112 "4: sub %1,%2,%1\n" \
1113 "5: addxcc %1,%1,%1\n" \
1114 " bcc 2b\n" \
1115 " subcc %%g1,1,%%g1\n" \
1116 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1117 " bne 4b\n" \
1118 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1119 " sub %1,%2,%1\n" \
1120 "3: xnor %0,0,%0\n" \
1121 " ! End of inline udiv_qrnnd" \
1122 : "=&r" ((USItype) (__q)), \
1123 "=&r" ((USItype) (__r)) \
1124 : "r" ((USItype) (__d)), \
1125 "1" ((USItype) (__n1)), \
1126 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1127 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1128 #endif /* __sparclite__ */
1129 #endif /* __sparc_v8__ */
1130 #endif /* sparc32 */
1131
1132 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1133 && W_TYPE_SIZE == 64
1134 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1135 __asm__ ("addcc %r4,%5,%1\n\t" \
1136 "add %r2,%3,%0\n\t" \
1137 "bcs,a,pn %%xcc, 1f\n\t" \
1138 "add %0, 1, %0\n" \
1139 "1:" \
1140 : "=r" ((UDItype)(sh)), \
1141 "=&r" ((UDItype)(sl)) \
1142 : "%rJ" ((UDItype)(ah)), \
1143 "rI" ((UDItype)(bh)), \
1144 "%rJ" ((UDItype)(al)), \
1145 "rI" ((UDItype)(bl)) \
1146 __CLOBBER_CC)
1147
1148 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1149 __asm__ ("subcc %r4,%5,%1\n\t" \
1150 "sub %r2,%3,%0\n\t" \
1151 "bcs,a,pn %%xcc, 1f\n\t" \
1152 "sub %0, 1, %0\n\t" \
1153 "1:" \
1154 : "=r" ((UDItype)(sh)), \
1155 "=&r" ((UDItype)(sl)) \
1156 : "rJ" ((UDItype)(ah)), \
1157 "rI" ((UDItype)(bh)), \
1158 "rJ" ((UDItype)(al)), \
1159 "rI" ((UDItype)(bl)) \
1160 __CLOBBER_CC)
1161
1162 #define umul_ppmm(wh, wl, u, v) \
1163 do { \
1164 UDItype tmp1, tmp2, tmp3, tmp4; \
1165 __asm__ __volatile__ ( \
1166 "srl %7,0,%3\n\t" \
1167 "mulx %3,%6,%1\n\t" \
1168 "srlx %6,32,%2\n\t" \
1169 "mulx %2,%3,%4\n\t" \
1170 "sllx %4,32,%5\n\t" \
1171 "srl %6,0,%3\n\t" \
1172 "sub %1,%5,%5\n\t" \
1173 "srlx %5,32,%5\n\t" \
1174 "addcc %4,%5,%4\n\t" \
1175 "srlx %7,32,%5\n\t" \
1176 "mulx %3,%5,%3\n\t" \
1177 "mulx %2,%5,%5\n\t" \
1178 "sethi %%hi(0x80000000),%2\n\t" \
1179 "addcc %4,%3,%4\n\t" \
1180 "srlx %4,32,%4\n\t" \
1181 "add %2,%2,%2\n\t" \
1182 "movcc %%xcc,%%g0,%2\n\t" \
1183 "addcc %5,%4,%5\n\t" \
1184 "sllx %3,32,%3\n\t" \
1185 "add %1,%3,%1\n\t" \
1186 "add %5,%2,%0" \
1187 : "=r" ((UDItype)(wh)), \
1188 "=&r" ((UDItype)(wl)), \
1189 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1190 : "r" ((UDItype)(u)), \
1191 "r" ((UDItype)(v)) \
1192 __CLOBBER_CC); \
1193 } while (0)
1194 #define UMUL_TIME 96
1195 #define UDIV_TIME 230
1196 #endif /* sparc64 */
1197
1198 #if defined (__vax__) && W_TYPE_SIZE == 32
1199 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1200 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1201 : "=g" ((USItype) (sh)), \
1202 "=&g" ((USItype) (sl)) \
1203 : "%0" ((USItype) (ah)), \
1204 "g" ((USItype) (bh)), \
1205 "%1" ((USItype) (al)), \
1206 "g" ((USItype) (bl)))
1207 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1208 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1209 : "=g" ((USItype) (sh)), \
1210 "=&g" ((USItype) (sl)) \
1211 : "0" ((USItype) (ah)), \
1212 "g" ((USItype) (bh)), \
1213 "1" ((USItype) (al)), \
1214 "g" ((USItype) (bl)))
1215 #define umul_ppmm(xh, xl, m0, m1) \
1216 do { \
1217 union { \
1218 UDItype __ll; \
1219 struct {USItype __l, __h;} __i; \
1220 } __xx; \
1221 USItype __m0 = (m0), __m1 = (m1); \
1222 __asm__ ("emul %1,%2,$0,%0" \
1223 : "=r" (__xx.__ll) \
1224 : "g" (__m0), \
1225 "g" (__m1)); \
1226 (xh) = __xx.__i.__h; \
1227 (xl) = __xx.__i.__l; \
1228 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1229 + (((SItype) __m1 >> 31) & __m0)); \
1230 } while (0)
1231 #define sdiv_qrnnd(q, r, n1, n0, d) \
1232 do { \
1233 union {DItype __ll; \
1234 struct {SItype __l, __h;} __i; \
1235 } __xx; \
1236 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1237 __asm__ ("ediv %3,%2,%0,%1" \
1238 : "=g" (q), "=g" (r) \
1239 : "g" (__xx.__ll), "g" (d)); \
1240 } while (0)
1241 #endif /* __vax__ */
1242
1243 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1244 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1245 to expand builtin functions depending on what configuration features
1246 are available. This avoids library calls when the operation can be
1247 performed in-line. */
1248 #define umul_ppmm(w1, w0, u, v) \
1249 do { \
1250 DWunion __w; \
1251 __w.ll = __builtin_umulsidi3 (u, v); \
1252 w1 = __w.s.high; \
1253 w0 = __w.s.low; \
1254 } while (0)
1255 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1256 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1257 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1258 #endif /* __xtensa__ */
1259
1260 #if defined (__z8000__) && W_TYPE_SIZE == 16
1261 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1262 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1263 : "=r" ((unsigned int)(sh)), \
1264 "=&r" ((unsigned int)(sl)) \
1265 : "%0" ((unsigned int)(ah)), \
1266 "r" ((unsigned int)(bh)), \
1267 "%1" ((unsigned int)(al)), \
1268 "rQR" ((unsigned int)(bl)))
1269 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1270 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1271 : "=r" ((unsigned int)(sh)), \
1272 "=&r" ((unsigned int)(sl)) \
1273 : "0" ((unsigned int)(ah)), \
1274 "r" ((unsigned int)(bh)), \
1275 "1" ((unsigned int)(al)), \
1276 "rQR" ((unsigned int)(bl)))
1277 #define umul_ppmm(xh, xl, m0, m1) \
1278 do { \
1279 union {long int __ll; \
1280 struct {unsigned int __h, __l;} __i; \
1281 } __xx; \
1282 unsigned int __m0 = (m0), __m1 = (m1); \
1283 __asm__ ("mult %S0,%H3" \
1284 : "=r" (__xx.__i.__h), \
1285 "=r" (__xx.__i.__l) \
1286 : "%1" (__m0), \
1287 "rQR" (__m1)); \
1288 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1289 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1290 + (((signed int) __m1 >> 15) & __m0)); \
1291 } while (0)
1292 #endif /* __z8000__ */
1293
1294 #endif /* __GNUC__ */
1295
1296 /* If this machine has no inline assembler, use C macros. */
1297
1298 #if !defined (add_ssaaaa)
1299 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1300 do { \
1301 UWtype __x; \
1302 __x = (al) + (bl); \
1303 (sh) = (ah) + (bh) + (__x < (al)); \
1304 (sl) = __x; \
1305 } while (0)
1306 #endif
1307
1308 #if !defined (sub_ddmmss)
1309 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1310 do { \
1311 UWtype __x; \
1312 __x = (al) - (bl); \
1313 (sh) = (ah) - (bh) - (__x > (al)); \
1314 (sl) = __x; \
1315 } while (0)
1316 #endif
1317
1318 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1319 smul_ppmm. */
1320 #if !defined (umul_ppmm) && defined (smul_ppmm)
1321 #define umul_ppmm(w1, w0, u, v) \
1322 do { \
1323 UWtype __w1; \
1324 UWtype __xm0 = (u), __xm1 = (v); \
1325 smul_ppmm (__w1, w0, __xm0, __xm1); \
1326 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1327 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1328 } while (0)
1329 #endif
1330
1331 /* If we still don't have umul_ppmm, define it using plain C. */
1332 #if !defined (umul_ppmm)
1333 #define umul_ppmm(w1, w0, u, v) \
1334 do { \
1335 UWtype __x0, __x1, __x2, __x3; \
1336 UHWtype __ul, __vl, __uh, __vh; \
1337 \
1338 __ul = __ll_lowpart (u); \
1339 __uh = __ll_highpart (u); \
1340 __vl = __ll_lowpart (v); \
1341 __vh = __ll_highpart (v); \
1342 \
1343 __x0 = (UWtype) __ul * __vl; \
1344 __x1 = (UWtype) __ul * __vh; \
1345 __x2 = (UWtype) __uh * __vl; \
1346 __x3 = (UWtype) __uh * __vh; \
1347 \
1348 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1349 __x1 += __x2; /* but this indeed can */ \
1350 if (__x1 < __x2) /* did we get it? */ \
1351 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1352 \
1353 (w1) = __x3 + __ll_highpart (__x1); \
1354 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1355 } while (0)
1356 #endif
1357
1358 #if !defined (__umulsidi3)
1359 #define __umulsidi3(u, v) \
1360 ({DWunion __w; \
1361 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1362 __w.ll; })
1363 #endif
1364
1365 /* Define this unconditionally, so it can be used for debugging. */
1366 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1367 do { \
1368 UWtype __d1, __d0, __q1, __q0; \
1369 UWtype __r1, __r0, __m; \
1370 __d1 = __ll_highpart (d); \
1371 __d0 = __ll_lowpart (d); \
1372 \
1373 __r1 = (n1) % __d1; \
1374 __q1 = (n1) / __d1; \
1375 __m = (UWtype) __q1 * __d0; \
1376 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1377 if (__r1 < __m) \
1378 { \
1379 __q1--, __r1 += (d); \
1380 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1381 if (__r1 < __m) \
1382 __q1--, __r1 += (d); \
1383 } \
1384 __r1 -= __m; \
1385 \
1386 __r0 = __r1 % __d1; \
1387 __q0 = __r1 / __d1; \
1388 __m = (UWtype) __q0 * __d0; \
1389 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1390 if (__r0 < __m) \
1391 { \
1392 __q0--, __r0 += (d); \
1393 if (__r0 >= (d)) \
1394 if (__r0 < __m) \
1395 __q0--, __r0 += (d); \
1396 } \
1397 __r0 -= __m; \
1398 \
1399 (q) = (UWtype) __q1 * __ll_B | __q0; \
1400 (r) = __r0; \
1401 } while (0)
1402
1403 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1404 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1405 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1406 #define udiv_qrnnd(q, r, nh, nl, d) \
1407 do { \
1408 USItype __r; \
1409 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1410 (r) = __r; \
1411 } while (0)
1412 #endif
1413
1414 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1415 #if !defined (udiv_qrnnd)
1416 #define UDIV_NEEDS_NORMALIZATION 1
1417 #define udiv_qrnnd __udiv_qrnnd_c
1418 #endif
1419
1420 #if !defined (count_leading_zeros)
1421 #define count_leading_zeros(count, x) \
1422 do { \
1423 UWtype __xr = (x); \
1424 UWtype __a; \
1425 \
1426 if (W_TYPE_SIZE <= 32) \
1427 { \
1428 __a = __xr < ((UWtype)1<<2*__BITS4) \
1429 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1430 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1431 } \
1432 else \
1433 { \
1434 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1435 if (((__xr >> __a) & 0xff) != 0) \
1436 break; \
1437 } \
1438 \
1439 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1440 } while (0)
1441 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1442 #endif
1443
1444 #if !defined (count_trailing_zeros)
1445 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1446 defined in asm, but if it is not, the C version above is good enough. */
1447 #define count_trailing_zeros(count, x) \
1448 do { \
1449 UWtype __ctz_x = (x); \
1450 UWtype __ctz_c; \
1451 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1452 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1453 } while (0)
1454 #endif
1455
1456 #ifndef UDIV_NEEDS_NORMALIZATION
1457 #define UDIV_NEEDS_NORMALIZATION 0
1458 #endif
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