1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "hash-table.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
55 #include "diagnostic.h"
56 #include "target-globals.h"
58 #include "tree-pass.h"
60 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save and restore registers.
77 The value for normal-mode code must be a SMALL_OPERAND and must
78 preserve the maximum stack alignment. We therefore use a value
79 of 0x7ff0 in this case.
81 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
82 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_COMPRESSION ? 0x7ff0 \
95 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 /* ??? This test exists through the compiler, perhaps it should be
101 #define USEFUL_INSN_P(INSN) \
102 (NONDEBUG_INSN_P (INSN) \
103 && GET_CODE (PATTERN (INSN)) != USE \
104 && GET_CODE (PATTERN (INSN)) != CLOBBER)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type
{
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type
{
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type
{
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET
,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY
,
228 MIPS_BUILTIN_CMP_ALL
,
229 MIPS_BUILTIN_CMP_UPPER
,
230 MIPS_BUILTIN_CMP_LOWER
,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE
,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition
{
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions
[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY
)
270 /* Tuning information that is automatically derived from other sources
271 (such as the scheduler). */
273 /* The architecture and tuning settings that this structure describes. */
277 /* True if this structure describes MIPS16 settings. */
280 /* True if the structure has been initialized. */
283 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
284 when optimizing for speed. */
285 bool fast_mult_zero_zero_p
;
288 /* Information about a function's frame layout. */
289 struct GTY(()) mips_frame_info
{
290 /* The size of the frame in bytes. */
291 HOST_WIDE_INT total_size
;
293 /* The number of bytes allocated to variables. */
294 HOST_WIDE_INT var_size
;
296 /* The number of bytes allocated to outgoing function arguments. */
297 HOST_WIDE_INT args_size
;
299 /* The number of bytes allocated to the .cprestore slot, or 0 if there
301 HOST_WIDE_INT cprestore_size
;
303 /* Bit X is set if the function saves or restores GPR X. */
306 /* Likewise FPR X. */
309 /* Likewise doubleword accumulator X ($acX). */
310 unsigned int acc_mask
;
312 /* The number of GPRs, FPRs, doubleword accumulators and COP0
316 unsigned int num_acc
;
317 unsigned int num_cop0_regs
;
319 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
320 save slots from the top of the frame, or zero if no such slots are
322 HOST_WIDE_INT gp_save_offset
;
323 HOST_WIDE_INT fp_save_offset
;
324 HOST_WIDE_INT acc_save_offset
;
325 HOST_WIDE_INT cop0_save_offset
;
327 /* Likewise, but giving offsets from the bottom of the frame. */
328 HOST_WIDE_INT gp_sp_offset
;
329 HOST_WIDE_INT fp_sp_offset
;
330 HOST_WIDE_INT acc_sp_offset
;
331 HOST_WIDE_INT cop0_sp_offset
;
333 /* Similar, but the value passed to _mcount. */
334 HOST_WIDE_INT ra_fp_offset
;
336 /* The offset of arg_pointer_rtx from the bottom of the frame. */
337 HOST_WIDE_INT arg_pointer_offset
;
339 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
340 HOST_WIDE_INT hard_frame_pointer_offset
;
343 struct GTY(()) machine_function
{
344 /* The next floating-point condition-code register to allocate
345 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
346 unsigned int next_fcc
;
348 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
349 rtx mips16_gp_pseudo_rtx
;
351 /* The number of extra stack bytes taken up by register varargs.
352 This area is allocated by the callee at the very top of the frame. */
355 /* The current frame information, calculated by mips_compute_frame_info. */
356 struct mips_frame_info frame
;
358 /* The register to use as the function's global pointer, or INVALID_REGNUM
359 if the function doesn't need one. */
360 unsigned int global_pointer
;
362 /* How many instructions it takes to load a label into $AT, or 0 if
363 this property hasn't yet been calculated. */
364 unsigned int load_label_num_insns
;
366 /* True if mips_adjust_insn_length should ignore an instruction's
368 bool ignore_hazard_length_p
;
370 /* True if the whole function is suitable for .set noreorder and
372 bool all_noreorder_p
;
374 /* True if the function has "inflexible" and "flexible" references
375 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
376 and mips_cfun_has_flexible_gp_ref_p for details. */
377 bool has_inflexible_gp_insn_p
;
378 bool has_flexible_gp_insn_p
;
380 /* True if the function's prologue must load the global pointer
381 value into pic_offset_table_rtx and store the same value in
382 the function's cprestore slot (if any). Even if this value
383 is currently false, we may decide to set it to true later;
384 see mips_must_initialize_gp_p () for details. */
385 bool must_initialize_gp_p
;
387 /* True if the current function must restore $gp after any potential
388 clobber. This value is only meaningful during the first post-epilogue
389 split_insns pass; see mips_must_initialize_gp_p () for details. */
390 bool must_restore_gp_when_clobbered_p
;
392 /* True if this is an interrupt handler. */
393 bool interrupt_handler_p
;
395 /* True if this is an interrupt handler that uses shadow registers. */
396 bool use_shadow_register_set_p
;
398 /* True if this is an interrupt handler that should keep interrupts
400 bool keep_interrupts_masked_p
;
402 /* True if this is an interrupt handler that should use DERET
404 bool use_debug_exception_return_p
;
407 /* Information about a single argument. */
408 struct mips_arg_info
{
409 /* True if the argument is passed in a floating-point register, or
410 would have been if we hadn't run out of registers. */
413 /* The number of words passed in registers, rounded up. */
414 unsigned int reg_words
;
416 /* For EABI, the offset of the first register from GP_ARG_FIRST or
417 FP_ARG_FIRST. For other ABIs, the offset of the first register from
418 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
419 comment for details).
421 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
423 unsigned int reg_offset
;
425 /* The number of words that must be passed on the stack, rounded up. */
426 unsigned int stack_words
;
428 /* The offset from the start of the stack overflow area of the argument's
429 first stack word. Only meaningful when STACK_WORDS is nonzero. */
430 unsigned int stack_offset
;
433 /* Information about an address described by mips_address_type.
439 REG is the base register and OFFSET is the constant offset.
442 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
443 is the type of symbol it references.
446 SYMBOL_TYPE is the type of symbol that the address references. */
447 struct mips_address_info
{
448 enum mips_address_type type
;
451 enum mips_symbol_type symbol_type
;
454 /* One stage in a constant building sequence. These sequences have
458 A = A CODE[1] VALUE[1]
459 A = A CODE[2] VALUE[2]
462 where A is an accumulator, each CODE[i] is a binary rtl operation
463 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
464 struct mips_integer_op
{
466 unsigned HOST_WIDE_INT value
;
469 /* The largest number of operations needed to load an integer constant.
470 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
471 When the lowest bit is clear, we can try, but reject a sequence with
472 an extra SLL at the end. */
473 #define MIPS_MAX_INTEGER_OPS 7
475 /* Information about a MIPS16e SAVE or RESTORE instruction. */
476 struct mips16e_save_restore_info
{
477 /* The number of argument registers saved by a SAVE instruction.
478 0 for RESTORE instructions. */
481 /* Bit X is set if the instruction saves or restores GPR X. */
484 /* The total number of bytes to allocate. */
488 /* Costs of various operations on the different architectures. */
490 struct mips_rtx_cost_data
492 unsigned short fp_add
;
493 unsigned short fp_mult_sf
;
494 unsigned short fp_mult_df
;
495 unsigned short fp_div_sf
;
496 unsigned short fp_div_df
;
497 unsigned short int_mult_si
;
498 unsigned short int_mult_di
;
499 unsigned short int_div_si
;
500 unsigned short int_div_di
;
501 unsigned short branch_cost
;
502 unsigned short memory_latency
;
505 /* Global variables for machine-dependent things. */
507 /* The -G setting, or the configuration's default small-data limit if
508 no -G option is given. */
509 static unsigned int mips_small_data_threshold
;
511 /* The number of file directives written by mips_output_filename. */
512 int num_source_filenames
;
514 /* The name that appeared in the last .file directive written by
515 mips_output_filename, or "" if mips_output_filename hasn't
516 written anything yet. */
517 const char *current_function_file
= "";
519 /* Arrays that map GCC register numbers to debugger register numbers. */
520 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
521 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
523 /* Information about the current function's epilogue, used only while
526 /* A list of queued REG_CFA_RESTORE notes. */
529 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
531 HOST_WIDE_INT cfa_offset
;
533 /* The offset of the CFA from the stack pointer while restoring
535 HOST_WIDE_INT cfa_restore_sp_offset
;
538 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
539 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
540 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
541 struct mips_asm_switch mips_noat
= { "at", 0 };
543 /* True if we're writing out a branch-likely instruction rather than a
545 static bool mips_branch_likely
;
547 /* The current instruction-set architecture. */
548 enum processor mips_arch
;
549 const struct mips_cpu_info
*mips_arch_info
;
551 /* The processor that we should tune the code for. */
552 enum processor mips_tune
;
553 const struct mips_cpu_info
*mips_tune_info
;
555 /* The ISA level associated with mips_arch. */
558 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
559 static const struct mips_cpu_info
*mips_isa_option_info
;
561 /* Which cost information to use. */
562 static const struct mips_rtx_cost_data
*mips_cost
;
564 /* The ambient target flags, excluding MASK_MIPS16. */
565 static int mips_base_target_flags
;
567 /* The default compression mode. */
568 unsigned int mips_base_compression_flags
;
570 /* The ambient values of other global variables. */
571 static int mips_base_schedule_insns
; /* flag_schedule_insns */
572 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
573 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
574 static int mips_base_align_loops
; /* align_loops */
575 static int mips_base_align_jumps
; /* align_jumps */
576 static int mips_base_align_functions
; /* align_functions */
578 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
579 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
581 /* Index C is true if character C is a valid PRINT_OPERAND punctation
583 static bool mips_print_operand_punct
[256];
585 static GTY (()) int mips_output_filename_first_time
= 1;
587 /* mips_split_p[X] is true if symbols of type X can be split by
588 mips_split_symbol. */
589 bool mips_split_p
[NUM_SYMBOL_TYPES
];
591 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
592 can be split by mips_split_symbol. */
593 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
595 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
596 forced into a PC-relative constant pool. */
597 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
599 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
600 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
601 if they are matched by a special .md file pattern. */
602 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
604 /* Likewise for HIGHs. */
605 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
607 /* Target state for MIPS16. */
608 struct target_globals
*mips16_globals
;
610 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
611 and returned from mips_sched_reorder2. */
612 static int cached_can_issue_more
;
614 /* True if the output uses __mips16_rdhwr. */
615 static bool mips_need_mips16_rdhwr_p
;
617 /* Index R is the smallest register class that contains register R. */
618 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
619 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
620 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
621 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
622 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
623 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
624 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
625 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
626 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
627 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
628 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
629 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
630 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
631 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
632 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
633 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
634 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
635 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
636 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
637 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
638 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
639 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
640 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
641 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
642 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
643 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
644 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
645 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
646 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
647 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
648 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
649 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
650 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
651 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
652 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
653 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
654 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
655 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
656 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
657 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
658 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
659 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
660 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
661 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
662 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
663 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
664 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
665 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
668 /* The value of TARGET_ATTRIBUTE_TABLE. */
669 static const struct attribute_spec mips_attribute_table
[] = {
670 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
672 { "long_call", 0, 0, false, true, true, NULL
, false },
673 { "far", 0, 0, false, true, true, NULL
, false },
674 { "near", 0, 0, false, true, true, NULL
, false },
675 /* We would really like to treat "mips16" and "nomips16" as type
676 attributes, but GCC doesn't provide the hooks we need to support
677 the right conversion rules. As declaration attributes, they affect
678 code generation but don't carry other semantics. */
679 { "mips16", 0, 0, true, false, false, NULL
, false },
680 { "nomips16", 0, 0, true, false, false, NULL
, false },
681 { "micromips", 0, 0, true, false, false, NULL
, false },
682 { "nomicromips", 0, 0, true, false, false, NULL
, false },
683 { "nocompression", 0, 0, true, false, false, NULL
, false },
684 /* Allow functions to be specified as interrupt handlers */
685 { "interrupt", 0, 0, false, true, true, NULL
, false },
686 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
687 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
688 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
689 { NULL
, 0, 0, false, false, false, NULL
, false }
692 /* A table describing all the processors GCC knows about; see
693 mips-cpus.def for details. */
694 static const struct mips_cpu_info mips_cpu_info_table
[] = {
695 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
696 { NAME, CPU, ISA, FLAGS },
697 #include "mips-cpus.def"
701 /* Default costs. If these are used for a processor we should look
702 up the actual costs. */
703 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
704 COSTS_N_INSNS (7), /* fp_mult_sf */ \
705 COSTS_N_INSNS (8), /* fp_mult_df */ \
706 COSTS_N_INSNS (23), /* fp_div_sf */ \
707 COSTS_N_INSNS (36), /* fp_div_df */ \
708 COSTS_N_INSNS (10), /* int_mult_si */ \
709 COSTS_N_INSNS (10), /* int_mult_di */ \
710 COSTS_N_INSNS (69), /* int_div_si */ \
711 COSTS_N_INSNS (69), /* int_div_di */ \
712 2, /* branch_cost */ \
713 4 /* memory_latency */
715 /* Floating-point costs for processors without an FPU. Just assume that
716 all floating-point libcalls are very expensive. */
717 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
718 COSTS_N_INSNS (256), /* fp_mult_sf */ \
719 COSTS_N_INSNS (256), /* fp_mult_df */ \
720 COSTS_N_INSNS (256), /* fp_div_sf */ \
721 COSTS_N_INSNS (256) /* fp_div_df */
723 /* Costs to use when optimizing for size. */
724 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
725 COSTS_N_INSNS (1), /* fp_add */
726 COSTS_N_INSNS (1), /* fp_mult_sf */
727 COSTS_N_INSNS (1), /* fp_mult_df */
728 COSTS_N_INSNS (1), /* fp_div_sf */
729 COSTS_N_INSNS (1), /* fp_div_df */
730 COSTS_N_INSNS (1), /* int_mult_si */
731 COSTS_N_INSNS (1), /* int_mult_di */
732 COSTS_N_INSNS (1), /* int_div_si */
733 COSTS_N_INSNS (1), /* int_div_di */
735 4 /* memory_latency */
738 /* Costs to use when optimizing for speed, indexed by processor. */
739 static const struct mips_rtx_cost_data
740 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
742 COSTS_N_INSNS (2), /* fp_add */
743 COSTS_N_INSNS (4), /* fp_mult_sf */
744 COSTS_N_INSNS (5), /* fp_mult_df */
745 COSTS_N_INSNS (12), /* fp_div_sf */
746 COSTS_N_INSNS (19), /* fp_div_df */
747 COSTS_N_INSNS (12), /* int_mult_si */
748 COSTS_N_INSNS (12), /* int_mult_di */
749 COSTS_N_INSNS (35), /* int_div_si */
750 COSTS_N_INSNS (35), /* int_div_di */
752 4 /* memory_latency */
756 COSTS_N_INSNS (6), /* int_mult_si */
757 COSTS_N_INSNS (6), /* int_mult_di */
758 COSTS_N_INSNS (36), /* int_div_si */
759 COSTS_N_INSNS (36), /* int_div_di */
761 4 /* memory_latency */
765 COSTS_N_INSNS (36), /* int_mult_si */
766 COSTS_N_INSNS (36), /* int_mult_di */
767 COSTS_N_INSNS (37), /* int_div_si */
768 COSTS_N_INSNS (37), /* int_div_di */
770 4 /* memory_latency */
774 COSTS_N_INSNS (4), /* int_mult_si */
775 COSTS_N_INSNS (11), /* int_mult_di */
776 COSTS_N_INSNS (36), /* int_div_si */
777 COSTS_N_INSNS (68), /* int_div_di */
779 4 /* memory_latency */
782 COSTS_N_INSNS (4), /* fp_add */
783 COSTS_N_INSNS (4), /* fp_mult_sf */
784 COSTS_N_INSNS (5), /* fp_mult_df */
785 COSTS_N_INSNS (17), /* fp_div_sf */
786 COSTS_N_INSNS (32), /* fp_div_df */
787 COSTS_N_INSNS (4), /* int_mult_si */
788 COSTS_N_INSNS (11), /* int_mult_di */
789 COSTS_N_INSNS (36), /* int_div_si */
790 COSTS_N_INSNS (68), /* int_div_di */
792 4 /* memory_latency */
795 COSTS_N_INSNS (4), /* fp_add */
796 COSTS_N_INSNS (4), /* fp_mult_sf */
797 COSTS_N_INSNS (5), /* fp_mult_df */
798 COSTS_N_INSNS (17), /* fp_div_sf */
799 COSTS_N_INSNS (32), /* fp_div_df */
800 COSTS_N_INSNS (4), /* int_mult_si */
801 COSTS_N_INSNS (7), /* int_mult_di */
802 COSTS_N_INSNS (42), /* int_div_si */
803 COSTS_N_INSNS (72), /* int_div_di */
805 4 /* memory_latency */
809 COSTS_N_INSNS (5), /* int_mult_si */
810 COSTS_N_INSNS (5), /* int_mult_di */
811 COSTS_N_INSNS (41), /* int_div_si */
812 COSTS_N_INSNS (41), /* int_div_di */
814 4 /* memory_latency */
817 COSTS_N_INSNS (8), /* fp_add */
818 COSTS_N_INSNS (8), /* fp_mult_sf */
819 COSTS_N_INSNS (10), /* fp_mult_df */
820 COSTS_N_INSNS (34), /* fp_div_sf */
821 COSTS_N_INSNS (64), /* fp_div_df */
822 COSTS_N_INSNS (5), /* int_mult_si */
823 COSTS_N_INSNS (5), /* int_mult_di */
824 COSTS_N_INSNS (41), /* int_div_si */
825 COSTS_N_INSNS (41), /* int_div_di */
827 4 /* memory_latency */
830 COSTS_N_INSNS (4), /* fp_add */
831 COSTS_N_INSNS (4), /* fp_mult_sf */
832 COSTS_N_INSNS (5), /* fp_mult_df */
833 COSTS_N_INSNS (17), /* fp_div_sf */
834 COSTS_N_INSNS (32), /* fp_div_df */
835 COSTS_N_INSNS (5), /* int_mult_si */
836 COSTS_N_INSNS (5), /* int_mult_di */
837 COSTS_N_INSNS (41), /* int_div_si */
838 COSTS_N_INSNS (41), /* int_div_di */
840 4 /* memory_latency */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (8), /* fp_add */
853 COSTS_N_INSNS (8), /* fp_mult_sf */
854 COSTS_N_INSNS (10), /* fp_mult_df */
855 COSTS_N_INSNS (34), /* fp_div_sf */
856 COSTS_N_INSNS (64), /* fp_div_df */
857 COSTS_N_INSNS (5), /* int_mult_si */
858 COSTS_N_INSNS (5), /* int_mult_di */
859 COSTS_N_INSNS (41), /* int_div_si */
860 COSTS_N_INSNS (41), /* int_div_di */
862 4 /* memory_latency */
865 COSTS_N_INSNS (4), /* fp_add */
866 COSTS_N_INSNS (4), /* fp_mult_sf */
867 COSTS_N_INSNS (5), /* fp_mult_df */
868 COSTS_N_INSNS (17), /* fp_div_sf */
869 COSTS_N_INSNS (32), /* fp_div_df */
870 COSTS_N_INSNS (5), /* int_mult_si */
871 COSTS_N_INSNS (5), /* int_mult_di */
872 COSTS_N_INSNS (41), /* int_div_si */
873 COSTS_N_INSNS (41), /* int_div_di */
875 4 /* memory_latency */
878 COSTS_N_INSNS (6), /* fp_add */
879 COSTS_N_INSNS (6), /* fp_mult_sf */
880 COSTS_N_INSNS (7), /* fp_mult_df */
881 COSTS_N_INSNS (25), /* fp_div_sf */
882 COSTS_N_INSNS (48), /* fp_div_df */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (72), /* int_div_si */
908 COSTS_N_INSNS (72), /* int_div_di */
910 4 /* memory_latency */
915 COSTS_N_INSNS (6), /* int_mult_si */
916 COSTS_N_INSNS (6), /* int_mult_di */
917 COSTS_N_INSNS (18), /* int_div_si */
918 COSTS_N_INSNS (35), /* int_div_di */
920 4 /* memory_latency */
923 COSTS_N_INSNS (2), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (12), /* fp_div_sf */
927 COSTS_N_INSNS (19), /* fp_div_df */
928 COSTS_N_INSNS (2), /* int_mult_si */
929 COSTS_N_INSNS (2), /* int_mult_di */
930 COSTS_N_INSNS (35), /* int_div_si */
931 COSTS_N_INSNS (35), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (3), /* fp_add */
937 COSTS_N_INSNS (5), /* fp_mult_sf */
938 COSTS_N_INSNS (6), /* fp_mult_df */
939 COSTS_N_INSNS (15), /* fp_div_sf */
940 COSTS_N_INSNS (16), /* fp_div_df */
941 COSTS_N_INSNS (17), /* int_mult_si */
942 COSTS_N_INSNS (17), /* int_mult_di */
943 COSTS_N_INSNS (38), /* int_div_si */
944 COSTS_N_INSNS (38), /* int_div_di */
946 6 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (7), /* fp_mult_sf */
951 COSTS_N_INSNS (8), /* fp_mult_df */
952 COSTS_N_INSNS (23), /* fp_div_sf */
953 COSTS_N_INSNS (36), /* fp_div_df */
954 COSTS_N_INSNS (10), /* int_mult_si */
955 COSTS_N_INSNS (10), /* int_mult_di */
956 COSTS_N_INSNS (69), /* int_div_si */
957 COSTS_N_INSNS (69), /* int_div_di */
959 6 /* memory_latency */
971 /* The only costs that appear to be updated here are
972 integer multiplication. */
974 COSTS_N_INSNS (4), /* int_mult_si */
975 COSTS_N_INSNS (6), /* int_mult_di */
976 COSTS_N_INSNS (69), /* int_div_si */
977 COSTS_N_INSNS (69), /* int_div_di */
979 4 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (5), /* fp_mult_df */
997 COSTS_N_INSNS (23), /* fp_div_sf */
998 COSTS_N_INSNS (36), /* fp_div_df */
999 COSTS_N_INSNS (5), /* int_mult_si */
1000 COSTS_N_INSNS (5), /* int_mult_di */
1001 COSTS_N_INSNS (36), /* int_div_si */
1002 COSTS_N_INSNS (36), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (30), /* fp_div_sf */
1011 COSTS_N_INSNS (59), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (4), /* int_mult_di */
1014 COSTS_N_INSNS (42), /* int_div_si */
1015 COSTS_N_INSNS (74), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (5), /* fp_mult_sf */
1022 COSTS_N_INSNS (6), /* fp_mult_df */
1023 COSTS_N_INSNS (30), /* fp_div_sf */
1024 COSTS_N_INSNS (59), /* fp_div_df */
1025 COSTS_N_INSNS (5), /* int_mult_si */
1026 COSTS_N_INSNS (9), /* int_mult_di */
1027 COSTS_N_INSNS (42), /* int_div_si */
1028 COSTS_N_INSNS (74), /* int_div_di */
1029 1, /* branch_cost */
1030 4 /* memory_latency */
1033 COSTS_N_INSNS (4), /* fp_add */
1034 COSTS_N_INSNS (4), /* fp_mult_sf */
1035 COSTS_N_INSNS (256), /* fp_mult_df */
1036 COSTS_N_INSNS (8), /* fp_div_sf */
1037 COSTS_N_INSNS (256), /* fp_div_df */
1038 COSTS_N_INSNS (4), /* int_mult_si */
1039 COSTS_N_INSNS (256), /* int_mult_di */
1040 COSTS_N_INSNS (37), /* int_div_si */
1041 COSTS_N_INSNS (256), /* int_div_di */
1042 1, /* branch_cost */
1043 4 /* memory_latency */
1046 /* The only costs that are changed here are
1047 integer multiplication. */
1048 COSTS_N_INSNS (6), /* fp_add */
1049 COSTS_N_INSNS (7), /* fp_mult_sf */
1050 COSTS_N_INSNS (8), /* fp_mult_df */
1051 COSTS_N_INSNS (23), /* fp_div_sf */
1052 COSTS_N_INSNS (36), /* fp_div_df */
1053 COSTS_N_INSNS (5), /* int_mult_si */
1054 COSTS_N_INSNS (9), /* int_mult_di */
1055 COSTS_N_INSNS (69), /* int_div_si */
1056 COSTS_N_INSNS (69), /* int_div_di */
1057 1, /* branch_cost */
1058 4 /* memory_latency */
1064 /* The only costs that are changed here are
1065 integer multiplication. */
1066 COSTS_N_INSNS (6), /* fp_add */
1067 COSTS_N_INSNS (7), /* fp_mult_sf */
1068 COSTS_N_INSNS (8), /* fp_mult_df */
1069 COSTS_N_INSNS (23), /* fp_div_sf */
1070 COSTS_N_INSNS (36), /* fp_div_df */
1071 COSTS_N_INSNS (3), /* int_mult_si */
1072 COSTS_N_INSNS (8), /* int_mult_di */
1073 COSTS_N_INSNS (69), /* int_div_si */
1074 COSTS_N_INSNS (69), /* int_div_di */
1075 1, /* branch_cost */
1076 4 /* memory_latency */
1079 COSTS_N_INSNS (2), /* fp_add */
1080 COSTS_N_INSNS (2), /* fp_mult_sf */
1081 COSTS_N_INSNS (2), /* fp_mult_df */
1082 COSTS_N_INSNS (12), /* fp_div_sf */
1083 COSTS_N_INSNS (19), /* fp_div_df */
1084 COSTS_N_INSNS (5), /* int_mult_si */
1085 COSTS_N_INSNS (9), /* int_mult_di */
1086 COSTS_N_INSNS (34), /* int_div_si */
1087 COSTS_N_INSNS (66), /* int_div_di */
1088 1, /* branch_cost */
1089 4 /* memory_latency */
1092 /* These costs are the same as the SB-1A below. */
1093 COSTS_N_INSNS (4), /* fp_add */
1094 COSTS_N_INSNS (4), /* fp_mult_sf */
1095 COSTS_N_INSNS (4), /* fp_mult_df */
1096 COSTS_N_INSNS (24), /* fp_div_sf */
1097 COSTS_N_INSNS (32), /* fp_div_df */
1098 COSTS_N_INSNS (3), /* int_mult_si */
1099 COSTS_N_INSNS (4), /* int_mult_di */
1100 COSTS_N_INSNS (36), /* int_div_si */
1101 COSTS_N_INSNS (68), /* int_div_di */
1102 1, /* branch_cost */
1103 4 /* memory_latency */
1106 /* These costs are the same as the SB-1 above. */
1107 COSTS_N_INSNS (4), /* fp_add */
1108 COSTS_N_INSNS (4), /* fp_mult_sf */
1109 COSTS_N_INSNS (4), /* fp_mult_df */
1110 COSTS_N_INSNS (24), /* fp_div_sf */
1111 COSTS_N_INSNS (32), /* fp_div_df */
1112 COSTS_N_INSNS (3), /* int_mult_si */
1113 COSTS_N_INSNS (4), /* int_mult_di */
1114 COSTS_N_INSNS (36), /* int_div_si */
1115 COSTS_N_INSNS (68), /* int_div_di */
1116 1, /* branch_cost */
1117 4 /* memory_latency */
1124 COSTS_N_INSNS (8), /* int_mult_si */
1125 COSTS_N_INSNS (8), /* int_mult_di */
1126 COSTS_N_INSNS (72), /* int_div_si */
1127 COSTS_N_INSNS (72), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1132 /* These costs are the same as 5KF above. */
1133 COSTS_N_INSNS (4), /* fp_add */
1134 COSTS_N_INSNS (4), /* fp_mult_sf */
1135 COSTS_N_INSNS (5), /* fp_mult_df */
1136 COSTS_N_INSNS (17), /* fp_div_sf */
1137 COSTS_N_INSNS (32), /* fp_div_df */
1138 COSTS_N_INSNS (4), /* int_mult_si */
1139 COSTS_N_INSNS (11), /* int_mult_di */
1140 COSTS_N_INSNS (36), /* int_div_si */
1141 COSTS_N_INSNS (68), /* int_div_di */
1142 1, /* branch_cost */
1143 4 /* memory_latency */
1147 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1148 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1150 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1152 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1153 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1154 struct GTY (()) mflip_mips16_entry
{
1158 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1160 /* Hash table callbacks for mflip_mips16_htab. */
1163 mflip_mips16_htab_hash (const void *entry
)
1165 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1169 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1171 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1172 (const char *) name
) == 0;
1175 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1176 mode, false if it should next add an attribute for the opposite mode. */
1177 static GTY(()) bool mips16_flipper
;
1179 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1180 for -mflip-mips16. Return true if it should use "mips16" and false if
1181 it should use "nomips16". */
1184 mflip_mips16_use_mips16_p (tree decl
)
1186 struct mflip_mips16_entry
*entry
;
1190 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1192 /* Use the opposite of the command-line setting for anonymous decls. */
1193 if (!DECL_NAME (decl
))
1194 return !base_is_mips16
;
1196 if (!mflip_mips16_htab
)
1197 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1198 mflip_mips16_htab_eq
, NULL
);
1200 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1201 hash
= htab_hash_string (name
);
1202 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1203 entry
= (struct mflip_mips16_entry
*) *slot
;
1206 mips16_flipper
= !mips16_flipper
;
1207 entry
= ggc_alloc_mflip_mips16_entry ();
1209 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1212 return entry
->mips16_p
;
1215 /* Predicates to test for presence of "near" and "far"/"long_call"
1216 attributes on the given TYPE. */
1219 mips_near_type_p (const_tree type
)
1221 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1225 mips_far_type_p (const_tree type
)
1227 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1228 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1232 /* Check if the interrupt attribute is set for a function. */
1235 mips_interrupt_type_p (tree type
)
1237 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1240 /* Check if the attribute to use shadow register set is set for a function. */
1243 mips_use_shadow_register_set_p (tree type
)
1245 return lookup_attribute ("use_shadow_register_set",
1246 TYPE_ATTRIBUTES (type
)) != NULL
;
1249 /* Check if the attribute to keep interrupts masked is set for a function. */
1252 mips_keep_interrupts_masked_p (tree type
)
1254 return lookup_attribute ("keep_interrupts_masked",
1255 TYPE_ATTRIBUTES (type
)) != NULL
;
1258 /* Check if the attribute to use debug exception return is set for
1262 mips_use_debug_exception_return_p (tree type
)
1264 return lookup_attribute ("use_debug_exception_return",
1265 TYPE_ATTRIBUTES (type
)) != NULL
;
1268 /* Return the set of compression modes that are explicitly required
1269 by the attributes in ATTRIBUTES. */
1272 mips_get_compress_on_flags (tree attributes
)
1274 unsigned int flags
= 0;
1276 if (lookup_attribute ("mips16", attributes
) != NULL
)
1277 flags
|= MASK_MIPS16
;
1279 if (lookup_attribute ("micromips", attributes
) != NULL
)
1280 flags
|= MASK_MICROMIPS
;
1285 /* Return the set of compression modes that are explicitly forbidden
1286 by the attributes in ATTRIBUTES. */
1289 mips_get_compress_off_flags (tree attributes
)
1291 unsigned int flags
= 0;
1293 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1294 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1296 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1297 flags
|= MASK_MIPS16
;
1299 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1300 flags
|= MASK_MICROMIPS
;
1305 /* Return the compression mode that should be used for function DECL.
1306 Return the ambient setting if DECL is null. */
1309 mips_get_compress_mode (tree decl
)
1311 unsigned int flags
, force_on
;
1313 flags
= mips_base_compression_flags
;
1316 /* Nested functions must use the same frame pointer as their
1317 parent and must therefore use the same ISA mode. */
1318 tree parent
= decl_function_context (decl
);
1321 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1324 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1329 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1333 mips_get_compress_on_name (unsigned int flags
)
1335 if (flags
== MASK_MIPS16
)
1340 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1344 mips_get_compress_off_name (unsigned int flags
)
1346 if (flags
== MASK_MIPS16
)
1348 if (flags
== MASK_MICROMIPS
)
1349 return "nomicromips";
1350 return "nocompression";
1353 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1356 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1358 /* Disallow mixed near/far attributes. */
1359 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1361 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1366 /* Implement TARGET_INSERT_ATTRIBUTES. */
1369 mips_insert_attributes (tree decl
, tree
*attributes
)
1372 unsigned int compression_flags
, nocompression_flags
;
1374 /* Check for "mips16" and "nomips16" attributes. */
1375 compression_flags
= mips_get_compress_on_flags (*attributes
);
1376 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1378 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1380 if (nocompression_flags
)
1381 error ("%qs attribute only applies to functions",
1382 mips_get_compress_off_name (nocompression_flags
));
1384 if (compression_flags
)
1385 error ("%qs attribute only applies to functions",
1386 mips_get_compress_on_name (nocompression_flags
));
1390 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1391 nocompression_flags
|=
1392 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1394 if (compression_flags
&& nocompression_flags
)
1395 error ("%qE cannot have both %qs and %qs attributes",
1396 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1397 mips_get_compress_off_name (nocompression_flags
));
1399 if (compression_flags
& MASK_MIPS16
1400 && compression_flags
& MASK_MICROMIPS
)
1401 error ("%qE cannot have both %qs and %qs attributes",
1402 DECL_NAME (decl
), "mips16", "micromips");
1404 if (TARGET_FLIP_MIPS16
1405 && !DECL_ARTIFICIAL (decl
)
1406 && compression_flags
== 0
1407 && nocompression_flags
== 0)
1409 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1410 "mips16" attribute, arbitrarily pick one. We must pick the same
1411 setting for duplicate declarations of a function. */
1412 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1413 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1414 name
= "nomicromips";
1415 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1420 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1423 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1427 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1428 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1430 error ("%qE redeclared with conflicting %qs attributes",
1431 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1433 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1434 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1436 error ("%qE redeclared with conflicting %qs attributes",
1437 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1439 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1440 DECL_ATTRIBUTES (newdecl
));
1443 /* Implement TARGET_CAN_INLINE_P. */
1446 mips_can_inline_p (tree caller
, tree callee
)
1448 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1450 return default_target_can_inline_p (caller
, callee
);
1453 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1454 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1457 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1459 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1461 *base_ptr
= XEXP (x
, 0);
1462 *offset_ptr
= INTVAL (XEXP (x
, 1));
1471 static unsigned int mips_build_integer (struct mips_integer_op
*,
1472 unsigned HOST_WIDE_INT
);
1474 /* A subroutine of mips_build_integer, with the same interface.
1475 Assume that the final action in the sequence should be a left shift. */
1478 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1480 unsigned int i
, shift
;
1482 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1483 since signed numbers are easier to load than unsigned ones. */
1485 while ((value
& 1) == 0)
1486 value
/= 2, shift
++;
1488 i
= mips_build_integer (codes
, value
);
1489 codes
[i
].code
= ASHIFT
;
1490 codes
[i
].value
= shift
;
1494 /* As for mips_build_shift, but assume that the final action will be
1495 an IOR or PLUS operation. */
1498 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1500 unsigned HOST_WIDE_INT high
;
1503 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1504 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1506 /* The constant is too complex to load with a simple LUI/ORI pair,
1507 so we want to give the recursive call as many trailing zeros as
1508 possible. In this case, we know bit 16 is set and that the
1509 low 16 bits form a negative number. If we subtract that number
1510 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1511 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1512 codes
[i
].code
= PLUS
;
1513 codes
[i
].value
= CONST_LOW_PART (value
);
1517 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1518 bits gives a value with at least 17 trailing zeros. */
1519 i
= mips_build_integer (codes
, high
);
1520 codes
[i
].code
= IOR
;
1521 codes
[i
].value
= value
& 0xffff;
1526 /* Fill CODES with a sequence of rtl operations to load VALUE.
1527 Return the number of operations needed. */
1530 mips_build_integer (struct mips_integer_op
*codes
,
1531 unsigned HOST_WIDE_INT value
)
1533 if (SMALL_OPERAND (value
)
1534 || SMALL_OPERAND_UNSIGNED (value
)
1535 || LUI_OPERAND (value
))
1537 /* The value can be loaded with a single instruction. */
1538 codes
[0].code
= UNKNOWN
;
1539 codes
[0].value
= value
;
1542 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1544 /* Either the constant is a simple LUI/ORI combination or its
1545 lowest bit is set. We don't want to shift in this case. */
1546 return mips_build_lower (codes
, value
);
1548 else if ((value
& 0xffff) == 0)
1550 /* The constant will need at least three actions. The lowest
1551 16 bits are clear, so the final action will be a shift. */
1552 return mips_build_shift (codes
, value
);
1556 /* The final action could be a shift, add or inclusive OR.
1557 Rather than use a complex condition to select the best
1558 approach, try both mips_build_shift and mips_build_lower
1559 and pick the one that gives the shortest sequence.
1560 Note that this case is only used once per constant. */
1561 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1562 unsigned int cost
, alt_cost
;
1564 cost
= mips_build_shift (codes
, value
);
1565 alt_cost
= mips_build_lower (alt_codes
, value
);
1566 if (alt_cost
< cost
)
1568 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1575 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1578 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1580 return mips_const_insns (x
) > 0;
1583 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1586 mips16_stub_function (const char *name
)
1590 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1591 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1595 /* Return true if symbols of type TYPE require a GOT access. */
1598 mips_got_symbol_type_p (enum mips_symbol_type type
)
1602 case SYMBOL_GOT_PAGE_OFST
:
1603 case SYMBOL_GOT_DISP
:
1611 /* Return true if X is a thread-local symbol. */
1614 mips_tls_symbol_p (rtx x
)
1616 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1619 /* Return true if SYMBOL_REF X is associated with a global symbol
1620 (in the STB_GLOBAL sense). */
1623 mips_global_symbol_p (const_rtx x
)
1625 const_tree decl
= SYMBOL_REF_DECL (x
);
1628 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1630 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1631 or weak symbols. Relocations in the object file will be against
1632 the target symbol, so it's that symbol's binding that matters here. */
1633 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1636 /* Return true if function X is a libgcc MIPS16 stub function. */
1639 mips16_stub_function_p (const_rtx x
)
1641 return (GET_CODE (x
) == SYMBOL_REF
1642 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1645 /* Return true if function X is a locally-defined and locally-binding
1649 mips16_local_function_p (const_rtx x
)
1651 return (GET_CODE (x
) == SYMBOL_REF
1652 && SYMBOL_REF_LOCAL_P (x
)
1653 && !SYMBOL_REF_EXTERNAL_P (x
)
1654 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1657 /* Return true if SYMBOL_REF X binds locally. */
1660 mips_symbol_binds_local_p (const_rtx x
)
1662 return (SYMBOL_REF_DECL (x
)
1663 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1664 : SYMBOL_REF_LOCAL_P (x
));
1667 /* Return true if rtx constants of mode MODE should be put into a small
1671 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1673 return (!TARGET_EMBEDDED_DATA
1674 && TARGET_LOCAL_SDATA
1675 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1678 /* Return true if X should not be moved directly into register $25.
1679 We need this because many versions of GAS will treat "la $25,foo" as
1680 part of a call sequence and so allow a global "foo" to be lazily bound. */
1683 mips_dangerous_for_la25_p (rtx x
)
1685 return (!TARGET_EXPLICIT_RELOCS
1687 && GET_CODE (x
) == SYMBOL_REF
1688 && mips_global_symbol_p (x
));
1691 /* Return true if calls to X might need $25 to be valid on entry. */
1694 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1696 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1699 /* MIPS16 stub functions are guaranteed not to use $25. */
1700 if (mips16_stub_function_p (x
))
1703 if (GET_CODE (x
) == SYMBOL_REF
)
1705 /* If PLTs and copy relocations are available, the static linker
1706 will make sure that $25 is valid on entry to the target function. */
1707 if (TARGET_ABICALLS_PIC0
)
1710 /* Locally-defined functions use absolute accesses to set up
1711 the global pointer. */
1712 if (TARGET_ABSOLUTE_ABICALLS
1713 && mips_symbol_binds_local_p (x
)
1714 && !SYMBOL_REF_EXTERNAL_P (x
))
1721 /* Return the method that should be used to access SYMBOL_REF or
1722 LABEL_REF X in context CONTEXT. */
1724 static enum mips_symbol_type
1725 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1728 return SYMBOL_GOT_DISP
;
1730 if (GET_CODE (x
) == LABEL_REF
)
1732 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1733 code and if we know that the label is in the current function's
1734 text section. LABEL_REFs are used for jump tables as well as
1735 text labels, so we must check whether jump tables live in the
1737 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1738 && !LABEL_REF_NONLOCAL_P (x
))
1739 return SYMBOL_PC_RELATIVE
;
1741 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1742 return SYMBOL_GOT_PAGE_OFST
;
1744 return SYMBOL_ABSOLUTE
;
1747 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1749 if (SYMBOL_REF_TLS_MODEL (x
))
1752 if (CONSTANT_POOL_ADDRESS_P (x
))
1754 if (TARGET_MIPS16_TEXT_LOADS
)
1755 return SYMBOL_PC_RELATIVE
;
1757 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1758 return SYMBOL_PC_RELATIVE
;
1760 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1761 return SYMBOL_GP_RELATIVE
;
1764 /* Do not use small-data accesses for weak symbols; they may end up
1766 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1767 return SYMBOL_GP_RELATIVE
;
1769 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1771 if (TARGET_ABICALLS_PIC2
1772 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1774 /* There are three cases to consider:
1776 - o32 PIC (either with or without explicit relocs)
1777 - n32/n64 PIC without explicit relocs
1778 - n32/n64 PIC with explicit relocs
1780 In the first case, both local and global accesses will use an
1781 R_MIPS_GOT16 relocation. We must correctly predict which of
1782 the two semantics (local or global) the assembler and linker
1783 will apply. The choice depends on the symbol's binding rather
1784 than its visibility.
1786 In the second case, the assembler will not use R_MIPS_GOT16
1787 relocations, but it chooses between local and global accesses
1788 in the same way as for o32 PIC.
1790 In the third case we have more freedom since both forms of
1791 access will work for any kind of symbol. However, there seems
1792 little point in doing things differently. */
1793 if (mips_global_symbol_p (x
))
1794 return SYMBOL_GOT_DISP
;
1796 return SYMBOL_GOT_PAGE_OFST
;
1799 return SYMBOL_ABSOLUTE
;
1802 /* Classify the base of symbolic expression X, given that X appears in
1805 static enum mips_symbol_type
1806 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1810 split_const (x
, &x
, &offset
);
1811 if (UNSPEC_ADDRESS_P (x
))
1812 return UNSPEC_ADDRESS_TYPE (x
);
1814 return mips_classify_symbol (x
, context
);
1817 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1818 is the alignment in bytes of SYMBOL_REF X. */
1821 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1823 HOST_WIDE_INT align
;
1825 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1826 return IN_RANGE (offset
, 0, align
- 1);
1829 /* Return true if X is a symbolic constant that can be used in context
1830 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1833 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1834 enum mips_symbol_type
*symbol_type
)
1838 split_const (x
, &x
, &offset
);
1839 if (UNSPEC_ADDRESS_P (x
))
1841 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1842 x
= UNSPEC_ADDRESS (x
);
1844 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1846 *symbol_type
= mips_classify_symbol (x
, context
);
1847 if (*symbol_type
== SYMBOL_TLS
)
1853 if (offset
== const0_rtx
)
1856 /* Check whether a nonzero offset is valid for the underlying
1858 switch (*symbol_type
)
1860 case SYMBOL_ABSOLUTE
:
1861 case SYMBOL_64_HIGH
:
1864 /* If the target has 64-bit pointers and the object file only
1865 supports 32-bit symbols, the values of those symbols will be
1866 sign-extended. In this case we can't allow an arbitrary offset
1867 in case the 32-bit value X + OFFSET has a different sign from X. */
1868 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1869 return offset_within_block_p (x
, INTVAL (offset
));
1871 /* In other cases the relocations can handle any offset. */
1874 case SYMBOL_PC_RELATIVE
:
1875 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1876 In this case, we no longer have access to the underlying constant,
1877 but the original symbol-based access was known to be valid. */
1878 if (GET_CODE (x
) == LABEL_REF
)
1883 case SYMBOL_GP_RELATIVE
:
1884 /* Make sure that the offset refers to something within the
1885 same object block. This should guarantee that the final
1886 PC- or GP-relative offset is within the 16-bit limit. */
1887 return offset_within_block_p (x
, INTVAL (offset
));
1889 case SYMBOL_GOT_PAGE_OFST
:
1890 case SYMBOL_GOTOFF_PAGE
:
1891 /* If the symbol is global, the GOT entry will contain the symbol's
1892 address, and we will apply a 16-bit offset after loading it.
1893 If the symbol is local, the linker should provide enough local
1894 GOT entries for a 16-bit offset, but larger offsets may lead
1896 return SMALL_INT (offset
);
1900 /* There is no carry between the HI and LO REL relocations, so the
1901 offset is only valid if we know it won't lead to such a carry. */
1902 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1904 case SYMBOL_GOT_DISP
:
1905 case SYMBOL_GOTOFF_DISP
:
1906 case SYMBOL_GOTOFF_CALL
:
1907 case SYMBOL_GOTOFF_LOADGP
:
1910 case SYMBOL_GOTTPREL
:
1918 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1919 single instruction. We rely on the fact that, in the worst case,
1920 all instructions involved in a MIPS16 address calculation are usually
1924 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1926 if (mips_use_pcrel_pool_p
[(int) type
])
1928 if (mode
== MAX_MACHINE_MODE
)
1929 /* LEAs will be converted into constant-pool references by
1931 type
= SYMBOL_PC_RELATIVE
;
1933 /* The constant must be loaded and then dereferenced. */
1939 case SYMBOL_ABSOLUTE
:
1940 /* When using 64-bit symbols, we need 5 preparatory instructions,
1943 lui $at,%highest(symbol)
1944 daddiu $at,$at,%higher(symbol)
1946 daddiu $at,$at,%hi(symbol)
1949 The final address is then $at + %lo(symbol). With 32-bit
1950 symbols we just need a preparatory LUI for normal mode and
1951 a preparatory LI and SLL for MIPS16. */
1952 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1954 case SYMBOL_GP_RELATIVE
:
1955 /* Treat GP-relative accesses as taking a single instruction on
1956 MIPS16 too; the copy of $gp can often be shared. */
1959 case SYMBOL_PC_RELATIVE
:
1960 /* PC-relative constants can be only be used with ADDIUPC,
1961 DADDIUPC, LWPC and LDPC. */
1962 if (mode
== MAX_MACHINE_MODE
1963 || GET_MODE_SIZE (mode
) == 4
1964 || GET_MODE_SIZE (mode
) == 8)
1967 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1970 case SYMBOL_GOT_DISP
:
1971 /* The constant will have to be loaded from the GOT before it
1972 is used in an address. */
1973 if (mode
!= MAX_MACHINE_MODE
)
1978 case SYMBOL_GOT_PAGE_OFST
:
1979 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1980 local/global classification is accurate. The worst cases are:
1982 (1) For local symbols when generating o32 or o64 code. The assembler
1988 ...and the final address will be $at + %lo(symbol).
1990 (2) For global symbols when -mxgot. The assembler will use:
1992 lui $at,%got_hi(symbol)
1995 ...and the final address will be $at + %got_lo(symbol). */
1998 case SYMBOL_GOTOFF_PAGE
:
1999 case SYMBOL_GOTOFF_DISP
:
2000 case SYMBOL_GOTOFF_CALL
:
2001 case SYMBOL_GOTOFF_LOADGP
:
2002 case SYMBOL_64_HIGH
:
2008 case SYMBOL_GOTTPREL
:
2011 /* A 16-bit constant formed by a single relocation, or a 32-bit
2012 constant formed from a high 16-bit relocation and a low 16-bit
2013 relocation. Use mips_split_p to determine which. 32-bit
2014 constants need an "lui; addiu" sequence for normal mode and
2015 an "li; sll; addiu" sequence for MIPS16 mode. */
2016 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2019 /* We don't treat a bare TLS symbol as a constant. */
2025 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2026 to load symbols of type TYPE into a register. Return 0 if the given
2027 type of symbol cannot be used as an immediate operand.
2029 Otherwise, return the number of instructions needed to load or store
2030 values of mode MODE to or from addresses of type TYPE. Return 0 if
2031 the given type of symbol is not valid in addresses.
2033 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2036 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2038 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2041 /* A for_each_rtx callback. Stop the search if *X references a
2042 thread-local symbol. */
2045 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2047 return mips_tls_symbol_p (*x
);
2050 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2053 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2055 enum mips_symbol_type type
;
2058 /* There is no assembler syntax for expressing an address-sized
2060 if (GET_CODE (x
) == HIGH
)
2063 /* As an optimization, reject constants that mips_legitimize_move
2066 Suppose we have a multi-instruction sequence that loads constant C
2067 into register R. If R does not get allocated a hard register, and
2068 R is used in an operand that allows both registers and memory
2069 references, reload will consider forcing C into memory and using
2070 one of the instruction's memory alternatives. Returning false
2071 here will force it to use an input reload instead. */
2072 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2075 split_const (x
, &base
, &offset
);
2076 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2078 /* See whether we explicitly want these symbols in the pool. */
2079 if (mips_use_pcrel_pool_p
[(int) type
])
2082 /* The same optimization as for CONST_INT. */
2083 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2086 /* If MIPS16 constant pools live in the text section, they should
2087 not refer to anything that might need run-time relocation. */
2088 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2092 /* TLS symbols must be computed by mips_legitimize_move. */
2093 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2099 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2100 constants when we're using a per-function constant pool. */
2103 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2104 const_rtx x ATTRIBUTE_UNUSED
)
2106 return !TARGET_MIPS16_PCREL_LOADS
;
2109 /* Return true if register REGNO is a valid base register for mode MODE.
2110 STRICT_P is true if REG_OK_STRICT is in effect. */
2113 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2116 if (!HARD_REGISTER_NUM_P (regno
))
2120 regno
= reg_renumber
[regno
];
2123 /* These fake registers will be eliminated to either the stack or
2124 hard frame pointer, both of which are usually valid base registers.
2125 Reload deals with the cases where the eliminated form isn't valid. */
2126 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2129 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2130 values, nothing smaller. There are two problems here:
2132 (a) Instantiating virtual registers can introduce new uses of the
2133 stack pointer. If these virtual registers are valid addresses,
2134 the stack pointer should be too.
2136 (b) Most uses of the stack pointer are not made explicit until
2137 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2138 We don't know until that stage whether we'll be eliminating to the
2139 stack pointer (which needs the restriction) or the hard frame
2140 pointer (which doesn't).
2142 All in all, it seems more consistent to only enforce this restriction
2143 during and after reload. */
2144 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2145 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2147 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2150 /* Return true if X is a valid base register for mode MODE.
2151 STRICT_P is true if REG_OK_STRICT is in effect. */
2154 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2156 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2160 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2163 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2164 can address a value of mode MODE. */
2167 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2169 /* Check that X is a signed 16-bit number. */
2170 if (!const_arith_operand (x
, Pmode
))
2173 /* We may need to split multiword moves, so make sure that every word
2175 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2176 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2182 /* Return true if a LO_SUM can address a value of mode MODE when the
2183 LO_SUM symbol has type SYMBOL_TYPE. */
2186 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2188 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2190 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2193 /* Check that there is a known low-part relocation. */
2194 if (mips_lo_relocs
[symbol_type
] == NULL
)
2197 /* We may need to split multiword moves, so make sure that each word
2198 can be accessed without inducing a carry. This is mainly needed
2199 for o64, which has historically only guaranteed 64-bit alignment
2200 for 128-bit types. */
2201 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2202 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2208 /* Return true if X is a valid address for machine mode MODE. If it is,
2209 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2213 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2214 enum machine_mode mode
, bool strict_p
)
2216 switch (GET_CODE (x
))
2220 info
->type
= ADDRESS_REG
;
2222 info
->offset
= const0_rtx
;
2223 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2226 info
->type
= ADDRESS_REG
;
2227 info
->reg
= XEXP (x
, 0);
2228 info
->offset
= XEXP (x
, 1);
2229 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2230 && mips_valid_offset_p (info
->offset
, mode
));
2233 info
->type
= ADDRESS_LO_SUM
;
2234 info
->reg
= XEXP (x
, 0);
2235 info
->offset
= XEXP (x
, 1);
2236 /* We have to trust the creator of the LO_SUM to do something vaguely
2237 sane. Target-independent code that creates a LO_SUM should also
2238 create and verify the matching HIGH. Target-independent code that
2239 adds an offset to a LO_SUM must prove that the offset will not
2240 induce a carry. Failure to do either of these things would be
2241 a bug, and we are not required to check for it here. The MIPS
2242 backend itself should only create LO_SUMs for valid symbolic
2243 constants, with the high part being either a HIGH or a copy
2246 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2247 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2248 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2251 /* Small-integer addresses don't occur very often, but they
2252 are legitimate if $0 is a valid base register. */
2253 info
->type
= ADDRESS_CONST_INT
;
2254 return !TARGET_MIPS16
&& SMALL_INT (x
);
2259 info
->type
= ADDRESS_SYMBOLIC
;
2260 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2262 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2263 && !mips_split_p
[info
->symbol_type
]);
2270 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2273 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2275 struct mips_address_info addr
;
2277 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2280 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2283 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2285 struct mips_address_info addr
;
2287 return (mips_classify_address (&addr
, x
, mode
, false)
2288 && addr
.type
== ADDRESS_REG
2289 && addr
.reg
== stack_pointer_rtx
);
2292 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2293 address instruction. Note that such addresses are not considered
2294 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2295 is so restricted. */
2298 mips_lwxs_address_p (rtx addr
)
2301 && GET_CODE (addr
) == PLUS
2302 && REG_P (XEXP (addr
, 1)))
2304 rtx offset
= XEXP (addr
, 0);
2305 if (GET_CODE (offset
) == MULT
2306 && REG_P (XEXP (offset
, 0))
2307 && CONST_INT_P (XEXP (offset
, 1))
2308 && INTVAL (XEXP (offset
, 1)) == 4)
2314 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2315 indexed address instruction. Note that such addresses are
2316 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2317 sense, because their use is so restricted. */
2320 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2322 if (GET_CODE (addr
) != PLUS
2323 || !REG_P (XEXP (addr
, 0))
2324 || !REG_P (XEXP (addr
, 1)))
2326 if (ISA_HAS_LBX
&& mode
== QImode
)
2328 if (ISA_HAS_LHX
&& mode
== HImode
)
2330 if (ISA_HAS_LWX
&& mode
== SImode
)
2332 if (ISA_HAS_LDX
&& mode
== DImode
)
2337 /* Return true if a value at OFFSET bytes from base register BASE can be
2338 accessed using an unextended MIPS16 instruction. MODE is the mode of
2341 Usually the offset in an unextended instruction is a 5-bit field.
2342 The offset is unsigned and shifted left once for LH and SH, twice
2343 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2344 an 8-bit immediate field that's shifted left twice. */
2347 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2348 unsigned HOST_WIDE_INT offset
)
2350 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2352 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2353 return offset
< 256U * GET_MODE_SIZE (mode
);
2354 return offset
< 32U * GET_MODE_SIZE (mode
);
2359 /* Return the number of instructions needed to load or store a value
2360 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2361 length of one instruction. Return 0 if X isn't valid for MODE.
2362 Assume that multiword moves may need to be split into word moves
2363 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2367 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2369 struct mips_address_info addr
;
2372 /* BLKmode is used for single unaligned loads and stores and should
2373 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2374 meaningless, so we have to single it out as a special case one way
2376 if (mode
!= BLKmode
&& might_split_p
)
2377 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2381 if (mips_classify_address (&addr
, x
, mode
, false))
2386 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2387 UINTVAL (addr
.offset
)))
2391 case ADDRESS_LO_SUM
:
2392 return TARGET_MIPS16
? factor
* 2 : factor
;
2394 case ADDRESS_CONST_INT
:
2397 case ADDRESS_SYMBOLIC
:
2398 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2403 /* Return true if X fits within an unsigned field of BITS bits that is
2404 shifted left SHIFT bits before being used. */
2407 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2409 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2412 /* Return true if X fits within a signed field of BITS bits that is
2413 shifted left SHIFT bits before being used. */
2416 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2418 x
+= 1 << (bits
+ shift
- 1);
2419 return mips_unsigned_immediate_p (x
, bits
, shift
);
2422 /* Return true if X is legitimate for accessing values of mode MODE,
2423 if it is based on a MIPS16 register, and if the offset satisfies
2424 OFFSET_PREDICATE. */
2427 m16_based_address_p (rtx x
, enum machine_mode mode
,
2428 insn_operand_predicate_fn offset_predicate
)
2430 struct mips_address_info addr
;
2432 return (mips_classify_address (&addr
, x
, mode
, false)
2433 && addr
.type
== ADDRESS_REG
2434 && M16_REG_P (REGNO (addr
.reg
))
2435 && offset_predicate (addr
.offset
, mode
));
2438 /* Return true if X is a legitimate address that conforms to the requirements
2439 for a microMIPS LWSP or SWSP insn. */
2442 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2444 struct mips_address_info addr
;
2446 return (mips_classify_address (&addr
, x
, mode
, false)
2447 && addr
.type
== ADDRESS_REG
2448 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2449 && uw5_operand (addr
.offset
, mode
));
2452 /* Return true if X is a legitimate address with a 12-bit offset.
2453 MODE is the mode of the value being accessed. */
2456 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2458 struct mips_address_info addr
;
2460 return (mips_classify_address (&addr
, x
, mode
, false)
2461 && addr
.type
== ADDRESS_REG
2462 && CONST_INT_P (addr
.offset
)
2463 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2466 /* Return the number of instructions needed to load constant X,
2467 assuming that BASE_INSN_LENGTH is the length of one instruction.
2468 Return 0 if X isn't a valid constant. */
2471 mips_const_insns (rtx x
)
2473 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2474 enum mips_symbol_type symbol_type
;
2477 switch (GET_CODE (x
))
2480 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2482 || !mips_split_p
[symbol_type
])
2485 /* This is simply an LUI for normal mode. It is an extended
2486 LI followed by an extended SLL for MIPS16. */
2487 return TARGET_MIPS16
? 4 : 1;
2491 /* Unsigned 8-bit constants can be loaded using an unextended
2492 LI instruction. Unsigned 16-bit constants can be loaded
2493 using an extended LI. Negative constants must be loaded
2494 using LI and then negated. */
2495 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2496 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2497 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2498 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2501 return mips_build_integer (codes
, INTVAL (x
));
2505 /* Allow zeros for normal mode, where we can use $0. */
2506 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2512 /* See if we can refer to X directly. */
2513 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2514 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2516 /* Otherwise try splitting the constant into a base and offset.
2517 If the offset is a 16-bit value, we can load the base address
2518 into a register and then use (D)ADDIU to add in the offset.
2519 If the offset is larger, we can load the base and offset
2520 into separate registers and add them together with (D)ADDU.
2521 However, the latter is only possible before reload; during
2522 and after reload, we must have the option of forcing the
2523 constant into the pool instead. */
2524 split_const (x
, &x
, &offset
);
2527 int n
= mips_const_insns (x
);
2530 if (SMALL_INT (offset
))
2532 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2533 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2540 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2548 /* X is a doubleword constant that can be handled by splitting it into
2549 two words and loading each word separately. Return the number of
2550 instructions required to do this, assuming that BASE_INSN_LENGTH
2551 is the length of one instruction. */
2554 mips_split_const_insns (rtx x
)
2556 unsigned int low
, high
;
2558 low
= mips_const_insns (mips_subword (x
, false));
2559 high
= mips_const_insns (mips_subword (x
, true));
2560 gcc_assert (low
> 0 && high
> 0);
2564 /* Return the number of instructions needed to implement INSN,
2565 given that it loads from or stores to MEM. Assume that
2566 BASE_INSN_LENGTH is the length of one instruction. */
2569 mips_load_store_insns (rtx mem
, rtx insn
)
2571 enum machine_mode mode
;
2575 gcc_assert (MEM_P (mem
));
2576 mode
= GET_MODE (mem
);
2578 /* Try to prove that INSN does not need to be split. */
2579 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2582 set
= single_set (insn
);
2583 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2584 might_split_p
= false;
2587 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2590 /* Return the number of instructions needed for an integer division,
2591 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2594 mips_idiv_insns (void)
2599 if (TARGET_CHECK_ZERO_DIV
)
2601 if (GENERATE_DIVIDE_TRAPS
)
2607 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2612 /* Emit a move from SRC to DEST. Assume that the move expanders can
2613 handle all moves if !can_create_pseudo_p (). The distinction is
2614 important because, unlike emit_move_insn, the move expanders know
2615 how to force Pmode objects into the constant pool even when the
2616 constant pool address is not itself legitimate. */
2619 mips_emit_move (rtx dest
, rtx src
)
2621 return (can_create_pseudo_p ()
2622 ? emit_move_insn (dest
, src
)
2623 : emit_move_insn_1 (dest
, src
));
2626 /* Emit a move from SRC to DEST, splitting compound moves into individual
2627 instructions. SPLIT_TYPE is the type of split to perform. */
2630 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2632 if (mips_split_move_p (dest
, src
, split_type
))
2633 mips_split_move (dest
, src
, split_type
);
2635 mips_emit_move (dest
, src
);
2638 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2641 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2643 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2644 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2647 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2648 Return that new register. */
2651 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2655 reg
= gen_reg_rtx (mode
);
2656 mips_emit_unary (code
, reg
, op0
);
2660 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2663 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2665 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2666 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2669 /* Compute (CODE OP0 OP1) and store the result in a new register
2670 of mode MODE. Return that new register. */
2673 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2677 reg
= gen_reg_rtx (mode
);
2678 mips_emit_binary (code
, reg
, op0
, op1
);
2682 /* Copy VALUE to a register and return that register. If new pseudos
2683 are allowed, copy it into a new register, otherwise use DEST. */
2686 mips_force_temporary (rtx dest
, rtx value
)
2688 if (can_create_pseudo_p ())
2689 return force_reg (Pmode
, value
);
2692 mips_emit_move (dest
, value
);
2697 /* Emit a call sequence with call pattern PATTERN and return the call
2698 instruction itself (which is not necessarily the last instruction
2699 emitted). ORIG_ADDR is the original, unlegitimized address,
2700 ADDR is the legitimized form, and LAZY_P is true if the call
2701 address is lazily-bound. */
2704 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2708 insn
= emit_call_insn (pattern
);
2710 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2712 /* MIPS16 JALRs only take MIPS16 registers. If the target
2713 function requires $25 to be valid on entry, we must copy it
2714 there separately. The move instruction can be put in the
2715 call's delay slot. */
2716 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2717 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2718 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2722 /* Lazy-binding stubs require $gp to be valid on entry. */
2723 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2727 /* See the comment above load_call<mode> for details. */
2728 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2729 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2730 emit_insn (gen_update_got_version ());
2735 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2736 then add CONST_INT OFFSET to the result. */
2739 mips_unspec_address_offset (rtx base
, rtx offset
,
2740 enum mips_symbol_type symbol_type
)
2742 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2743 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2744 if (offset
!= const0_rtx
)
2745 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2746 return gen_rtx_CONST (Pmode
, base
);
2749 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2750 type SYMBOL_TYPE. */
2753 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2757 split_const (address
, &base
, &offset
);
2758 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2761 /* If OP is an UNSPEC address, return the address to which it refers,
2762 otherwise return OP itself. */
2765 mips_strip_unspec_address (rtx op
)
2769 split_const (op
, &base
, &offset
);
2770 if (UNSPEC_ADDRESS_P (base
))
2771 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2775 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2776 high part to BASE and return the result. Just return BASE otherwise.
2777 TEMP is as for mips_force_temporary.
2779 The returned expression can be used as the first operand to a LO_SUM. */
2782 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2783 enum mips_symbol_type symbol_type
)
2785 if (mips_split_p
[symbol_type
])
2787 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2788 addr
= mips_force_temporary (temp
, addr
);
2789 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2794 /* Return an instruction that copies $gp into register REG. We want
2795 GCC to treat the register's value as constant, so that its value
2796 can be rematerialized on demand. */
2799 gen_load_const_gp (rtx reg
)
2801 return PMODE_INSN (gen_load_const_gp
, (reg
));
2804 /* Return a pseudo register that contains the value of $gp throughout
2805 the current function. Such registers are needed by MIPS16 functions,
2806 for which $gp itself is not a valid base register or addition operand. */
2809 mips16_gp_pseudo_reg (void)
2811 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2815 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2817 push_topmost_sequence ();
2819 scan
= get_insns ();
2820 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2821 scan
= NEXT_INSN (scan
);
2823 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2824 insn
= emit_insn_after (insn
, scan
);
2825 INSN_LOCATION (insn
) = 0;
2827 pop_topmost_sequence ();
2830 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2833 /* Return a base register that holds pic_offset_table_rtx.
2834 TEMP, if nonnull, is a scratch Pmode base register. */
2837 mips_pic_base_register (rtx temp
)
2840 return pic_offset_table_rtx
;
2842 if (currently_expanding_to_rtl
)
2843 return mips16_gp_pseudo_reg ();
2845 if (can_create_pseudo_p ())
2846 temp
= gen_reg_rtx (Pmode
);
2849 /* The first post-reload split exposes all references to $gp
2850 (both uses and definitions). All references must remain
2851 explicit after that point.
2853 It is safe to introduce uses of $gp at any time, so for
2854 simplicity, we do that before the split too. */
2855 mips_emit_move (temp
, pic_offset_table_rtx
);
2857 emit_insn (gen_load_const_gp (temp
));
2861 /* Return the RHS of a load_call<mode> insn. */
2864 mips_unspec_call (rtx reg
, rtx symbol
)
2868 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2869 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2872 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2873 reference. Return NULL_RTX otherwise. */
2876 mips_strip_unspec_call (rtx src
)
2878 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2879 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2883 /* Create and return a GOT reference of type TYPE for address ADDR.
2884 TEMP, if nonnull, is a scratch Pmode base register. */
2887 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2889 rtx base
, high
, lo_sum_symbol
;
2891 base
= mips_pic_base_register (temp
);
2893 /* If we used the temporary register to load $gp, we can't use
2894 it for the high part as well. */
2895 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2898 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2899 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2901 if (type
== SYMBOL_GOTOFF_CALL
)
2902 return mips_unspec_call (high
, lo_sum_symbol
);
2904 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2907 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2908 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2909 constant in that context and can be split into high and low parts.
2910 If so, and if LOW_OUT is nonnull, emit the high part and store the
2911 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2913 TEMP is as for mips_force_temporary and is used to load the high
2914 part into a register.
2916 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2917 a legitimize SET_SRC for an .md pattern, otherwise the low part
2918 is guaranteed to be a legitimate address for mode MODE. */
2921 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2923 enum mips_symbol_context context
;
2924 enum mips_symbol_type symbol_type
;
2927 context
= (mode
== MAX_MACHINE_MODE
2928 ? SYMBOL_CONTEXT_LEA
2929 : SYMBOL_CONTEXT_MEM
);
2930 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2932 addr
= XEXP (addr
, 0);
2933 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2934 && mips_symbol_insns (symbol_type
, mode
) > 0
2935 && mips_split_hi_p
[symbol_type
])
2938 switch (symbol_type
)
2940 case SYMBOL_GOT_PAGE_OFST
:
2941 /* The high part of a page/ofst pair is loaded from the GOT. */
2942 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2953 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2954 && mips_symbol_insns (symbol_type
, mode
) > 0
2955 && mips_split_p
[symbol_type
])
2958 switch (symbol_type
)
2960 case SYMBOL_GOT_DISP
:
2961 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2962 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2965 case SYMBOL_GP_RELATIVE
:
2966 high
= mips_pic_base_register (temp
);
2967 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2971 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2972 high
= mips_force_temporary (temp
, high
);
2973 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2982 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2983 mips_force_temporary; it is only needed when OFFSET is not a
2987 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2989 if (!SMALL_OPERAND (offset
))
2995 /* Load the full offset into a register so that we can use
2996 an unextended instruction for the address itself. */
2997 high
= GEN_INT (offset
);
3002 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3003 The addition inside the macro CONST_HIGH_PART may cause an
3004 overflow, so we need to force a sign-extension check. */
3005 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3006 offset
= CONST_LOW_PART (offset
);
3008 high
= mips_force_temporary (temp
, high
);
3009 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3011 return plus_constant (Pmode
, reg
, offset
);
3014 /* The __tls_get_attr symbol. */
3015 static GTY(()) rtx mips_tls_symbol
;
3017 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3018 the TLS symbol we are referencing and TYPE is the symbol type to use
3019 (either global dynamic or local dynamic). V0 is an RTX for the
3020 return value location. */
3023 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3027 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3029 if (!mips_tls_symbol
)
3030 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3032 loc
= mips_unspec_address (sym
, type
);
3036 emit_insn (gen_rtx_SET (Pmode
, a0
,
3037 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3038 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3039 const0_rtx
, NULL_RTX
, false);
3040 RTL_CONST_CALL_P (insn
) = 1;
3041 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3042 insn
= get_insns ();
3049 /* Return a pseudo register that contains the current thread pointer. */
3052 mips_expand_thread_pointer (rtx tp
)
3058 mips_need_mips16_rdhwr_p
= true;
3059 fn
= mips16_stub_function ("__mips16_rdhwr");
3060 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
3061 if (!call_insn_operand (fn
, VOIDmode
))
3062 fn
= force_reg (Pmode
, fn
);
3063 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3066 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3073 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3076 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3077 its address. The return value will be both a valid address and a valid
3078 SET_SRC (either a REG or a LO_SUM). */
3081 mips_legitimize_tls_address (rtx loc
)
3083 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3084 enum tls_model model
;
3086 model
= SYMBOL_REF_TLS_MODEL (loc
);
3087 /* Only TARGET_ABICALLS code can have more than one module; other
3088 code must be be static and should not use a GOT. All TLS models
3089 reduce to local exec in this situation. */
3090 if (!TARGET_ABICALLS
)
3091 model
= TLS_MODEL_LOCAL_EXEC
;
3095 case TLS_MODEL_GLOBAL_DYNAMIC
:
3096 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3097 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3098 dest
= gen_reg_rtx (Pmode
);
3099 emit_libcall_block (insn
, dest
, v0
, loc
);
3102 case TLS_MODEL_LOCAL_DYNAMIC
:
3103 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3104 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3105 tmp1
= gen_reg_rtx (Pmode
);
3107 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3108 share the LDM result with other LD model accesses. */
3109 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3111 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3113 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3114 if (mips_split_p
[SYMBOL_DTPREL
])
3116 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3117 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3120 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3121 0, 0, OPTAB_DIRECT
);
3124 case TLS_MODEL_INITIAL_EXEC
:
3125 tp
= mips_get_tp ();
3126 tmp1
= gen_reg_rtx (Pmode
);
3127 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3128 if (Pmode
== DImode
)
3129 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3131 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3132 dest
= gen_reg_rtx (Pmode
);
3133 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3136 case TLS_MODEL_LOCAL_EXEC
:
3137 tmp1
= mips_get_tp ();
3138 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3139 if (mips_split_p
[SYMBOL_TPREL
])
3141 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3142 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3145 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3146 0, 0, OPTAB_DIRECT
);
3155 /* If X is not a valid address for mode MODE, force it into a register. */
3158 mips_force_address (rtx x
, enum machine_mode mode
)
3160 if (!mips_legitimate_address_p (mode
, x
, false))
3161 x
= force_reg (Pmode
, x
);
3165 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3166 be legitimized in a way that the generic machinery might not expect,
3167 return a new address, otherwise return NULL. MODE is the mode of
3168 the memory being accessed. */
3171 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3172 enum machine_mode mode
)
3175 HOST_WIDE_INT offset
;
3177 if (mips_tls_symbol_p (x
))
3178 return mips_legitimize_tls_address (x
);
3180 /* See if the address can split into a high part and a LO_SUM. */
3181 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3182 return mips_force_address (addr
, mode
);
3184 /* Handle BASE + OFFSET using mips_add_offset. */
3185 mips_split_plus (x
, &base
, &offset
);
3188 if (!mips_valid_base_register_p (base
, mode
, false))
3189 base
= copy_to_mode_reg (Pmode
, base
);
3190 addr
= mips_add_offset (NULL
, base
, offset
);
3191 return mips_force_address (addr
, mode
);
3197 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3200 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3202 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3203 enum machine_mode mode
;
3204 unsigned int i
, num_ops
;
3207 mode
= GET_MODE (dest
);
3208 num_ops
= mips_build_integer (codes
, value
);
3210 /* Apply each binary operation to X. Invariant: X is a legitimate
3211 source operand for a SET pattern. */
3212 x
= GEN_INT (codes
[0].value
);
3213 for (i
= 1; i
< num_ops
; i
++)
3215 if (!can_create_pseudo_p ())
3217 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3221 x
= force_reg (mode
, x
);
3222 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3225 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3228 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3229 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3233 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3237 /* Split moves of big integers into smaller pieces. */
3238 if (splittable_const_int_operand (src
, mode
))
3240 mips_move_integer (dest
, dest
, INTVAL (src
));
3244 /* Split moves of symbolic constants into high/low pairs. */
3245 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3247 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3251 /* Generate the appropriate access sequences for TLS symbols. */
3252 if (mips_tls_symbol_p (src
))
3254 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3258 /* If we have (const (plus symbol offset)), and that expression cannot
3259 be forced into memory, load the symbol first and add in the offset.
3260 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3261 forced into memory, as it usually produces better code. */
3262 split_const (src
, &base
, &offset
);
3263 if (offset
!= const0_rtx
3264 && (targetm
.cannot_force_const_mem (mode
, src
)
3265 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3267 base
= mips_force_temporary (dest
, base
);
3268 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3272 src
= force_const_mem (mode
, src
);
3274 /* When using explicit relocs, constant pool references are sometimes
3275 not legitimate addresses. */
3276 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3277 mips_emit_move (dest
, src
);
3280 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3281 sequence that is valid. */
3284 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3286 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3288 mips_emit_move (dest
, force_reg (mode
, src
));
3292 /* We need to deal with constants that would be legitimate
3293 immediate_operands but aren't legitimate move_operands. */
3294 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3296 mips_legitimize_const_move (mode
, dest
, src
);
3297 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3303 /* Return true if value X in context CONTEXT is a small-data address
3304 that can be rewritten as a LO_SUM. */
3307 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3309 enum mips_symbol_type symbol_type
;
3311 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3312 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3313 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3314 && symbol_type
== SYMBOL_GP_RELATIVE
);
3317 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3318 containing MEM, or null if none. */
3321 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3323 enum mips_symbol_context context
;
3325 /* Ignore things like "g" constraints in asms. We make no particular
3326 guarantee about which symbolic constants are acceptable as asm operands
3327 versus which must be forced into a GPR. */
3328 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3333 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3338 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3339 return mips_rewrite_small_data_p (*loc
, context
);
3342 /* Return true if OP refers to small data symbols directly, not through
3346 mips_small_data_pattern_p (rtx op
)
3348 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3351 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3352 DATA is the containing MEM, or null if none. */
3355 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3357 enum mips_symbol_context context
;
3361 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3365 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3366 if (mips_rewrite_small_data_p (*loc
, context
))
3367 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3369 if (GET_CODE (*loc
) == LO_SUM
)
3375 /* Rewrite instruction pattern PATTERN so that it refers to small data
3376 using explicit relocations. */
3379 mips_rewrite_small_data (rtx pattern
)
3381 pattern
= copy_insn (pattern
);
3382 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3386 /* The cost of loading values from the constant pool. It should be
3387 larger than the cost of any constant we want to synthesize inline. */
3388 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3390 /* Return the cost of X when used as an operand to the MIPS16 instruction
3391 that implements CODE. Return -1 if there is no such instruction, or if
3392 X is not a valid immediate operand for it. */
3395 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3402 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3403 other shifts are extended. The shift patterns truncate the shift
3404 count to the right size, so there are no out-of-range values. */
3405 if (IN_RANGE (x
, 1, 8))
3407 return COSTS_N_INSNS (1);
3410 if (IN_RANGE (x
, -128, 127))
3412 if (SMALL_OPERAND (x
))
3413 return COSTS_N_INSNS (1);
3417 /* Like LE, but reject the always-true case. */
3421 /* We add 1 to the immediate and use SLT. */
3424 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3427 if (IN_RANGE (x
, 0, 255))
3429 if (SMALL_OPERAND_UNSIGNED (x
))
3430 return COSTS_N_INSNS (1);
3435 /* Equality comparisons with 0 are cheap. */
3445 /* Return true if there is a non-MIPS16 instruction that implements CODE
3446 and if that instruction accepts X as an immediate operand. */
3449 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3456 /* All shift counts are truncated to a valid constant. */
3461 /* Likewise rotates, if the target supports rotates at all. */
3467 /* These instructions take 16-bit unsigned immediates. */
3468 return SMALL_OPERAND_UNSIGNED (x
);
3473 /* These instructions take 16-bit signed immediates. */
3474 return SMALL_OPERAND (x
);
3480 /* The "immediate" forms of these instructions are really
3481 implemented as comparisons with register 0. */
3486 /* Likewise, meaning that the only valid immediate operand is 1. */
3490 /* We add 1 to the immediate and use SLT. */
3491 return SMALL_OPERAND (x
+ 1);
3494 /* Likewise SLTU, but reject the always-true case. */
3495 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3499 /* The bit position and size are immediate operands. */
3500 return ISA_HAS_EXT_INS
;
3503 /* By default assume that $0 can be used for 0. */
3508 /* Return the cost of binary operation X, given that the instruction
3509 sequence for a word-sized or smaller operation has cost SINGLE_COST
3510 and that the sequence of a double-word operation has cost DOUBLE_COST.
3511 If SPEED is true, optimize for speed otherwise optimize for size. */
3514 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3518 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3523 + set_src_cost (XEXP (x
, 0), speed
)
3524 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3527 /* Return the cost of floating-point multiplications of mode MODE. */
3530 mips_fp_mult_cost (enum machine_mode mode
)
3532 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3535 /* Return the cost of floating-point divisions of mode MODE. */
3538 mips_fp_div_cost (enum machine_mode mode
)
3540 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3543 /* Return the cost of sign-extending OP to mode MODE, not including the
3544 cost of OP itself. */
3547 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3550 /* Extended loads are as cheap as unextended ones. */
3553 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3554 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3557 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3558 /* We can use SEB or SEH. */
3559 return COSTS_N_INSNS (1);
3561 /* We need to use a shift left and a shift right. */
3562 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3565 /* Return the cost of zero-extending OP to mode MODE, not including the
3566 cost of OP itself. */
3569 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3572 /* Extended loads are as cheap as unextended ones. */
3575 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3576 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3577 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3579 if (GENERATE_MIPS16E
)
3580 /* We can use ZEB or ZEH. */
3581 return COSTS_N_INSNS (1);
3584 /* We need to load 0xff or 0xffff into a register and use AND. */
3585 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3587 /* We can use ANDI. */
3588 return COSTS_N_INSNS (1);
3591 /* Return the cost of moving between two registers of mode MODE,
3592 assuming that the move will be in pieces of at most UNITS bytes. */
3595 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3597 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3600 /* Return the cost of moving between two registers of mode MODE. */
3603 mips_set_reg_reg_cost (enum machine_mode mode
)
3605 switch (GET_MODE_CLASS (mode
))
3608 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3611 case MODE_COMPLEX_FLOAT
:
3612 case MODE_VECTOR_FLOAT
:
3613 if (TARGET_HARD_FLOAT
)
3614 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3618 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3622 /* Return the cost of an operand X that can be trucated for free.
3623 SPEED says whether we're optimizing for size or speed. */
3626 mips_truncated_op_cost (rtx x
, bool speed
)
3628 if (GET_CODE (x
) == TRUNCATE
)
3630 return set_src_cost (x
, speed
);
3633 /* Implement TARGET_RTX_COSTS. */
3636 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3637 int *total
, bool speed
)
3639 enum machine_mode mode
= GET_MODE (x
);
3640 bool float_mode_p
= FLOAT_MODE_P (mode
);
3644 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3645 appear in the instruction stream, and the cost of a comparison is
3646 really the cost of the branch or scc condition. At the time of
3647 writing, GCC only uses an explicit outer COMPARE code when optabs
3648 is testing whether a constant is expensive enough to force into a
3649 register. We want optabs to pass such constants through the MIPS
3650 expanders instead, so make all constants very cheap here. */
3651 if (outer_code
== COMPARE
)
3653 gcc_assert (CONSTANT_P (x
));
3661 /* Treat *clear_upper32-style ANDs as having zero cost in the
3662 second operand. The cost is entirely in the first operand.
3664 ??? This is needed because we would otherwise try to CSE
3665 the constant operand. Although that's the right thing for
3666 instructions that continue to be a register operation throughout
3667 compilation, it is disastrous for instructions that could
3668 later be converted into a memory operation. */
3670 && outer_code
== AND
3671 && UINTVAL (x
) == 0xffffffff)
3679 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3688 /* When not optimizing for size, we care more about the cost
3689 of hot code, and hot code is often in a loop. If a constant
3690 operand needs to be forced into a register, we will often be
3691 able to hoist the constant load out of the loop, so the load
3692 should not contribute to the cost. */
3693 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3705 if (force_to_mem_operand (x
, VOIDmode
))
3707 *total
= COSTS_N_INSNS (1);
3710 cost
= mips_const_insns (x
);
3713 /* If the constant is likely to be stored in a GPR, SETs of
3714 single-insn constants are as cheap as register sets; we
3715 never want to CSE them.
3717 Don't reduce the cost of storing a floating-point zero in
3718 FPRs. If we have a zero in an FPR for other reasons, we
3719 can get better cfg-cleanup and delayed-branch results by
3720 using it consistently, rather than using $0 sometimes and
3721 an FPR at other times. Also, moves between floating-point
3722 registers are sometimes cheaper than (D)MTC1 $0. */
3724 && outer_code
== SET
3725 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3727 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3728 want to CSE the constant itself. It is usually better to
3729 have N copies of the last operation in the sequence and one
3730 shared copy of the other operations. (Note that this is
3731 not true for MIPS16 code, where the final operation in the
3732 sequence is often an extended instruction.)
3734 Also, if we have a CONST_INT, we don't know whether it is
3735 for a word or doubleword operation, so we cannot rely on
3736 the result of mips_build_integer. */
3737 else if (!TARGET_MIPS16
3738 && (outer_code
== SET
|| mode
== VOIDmode
))
3740 *total
= COSTS_N_INSNS (cost
);
3743 /* The value will need to be fetched from the constant pool. */
3744 *total
= CONSTANT_POOL_COST
;
3748 /* If the address is legitimate, return the number of
3749 instructions it needs. */
3751 cost
= mips_address_insns (addr
, mode
, true);
3754 *total
= COSTS_N_INSNS (cost
+ 1);
3757 /* Check for a scaled indexed address. */
3758 if (mips_lwxs_address_p (addr
)
3759 || mips_lx_address_p (addr
, mode
))
3761 *total
= COSTS_N_INSNS (2);
3764 /* Otherwise use the default handling. */
3768 *total
= COSTS_N_INSNS (6);
3772 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3776 /* Check for a *clear_upper32 pattern and treat it like a zero
3777 extension. See the pattern's comment for details. */
3780 && CONST_INT_P (XEXP (x
, 1))
3781 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3783 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3784 + set_src_cost (XEXP (x
, 0), speed
));
3787 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3789 rtx op
= XEXP (x
, 0);
3790 if (GET_CODE (op
) == ASHIFT
3791 && CONST_INT_P (XEXP (op
, 1))
3792 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3794 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3803 /* Double-word operations use two single-word operations. */
3804 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3813 if (CONSTANT_P (XEXP (x
, 1)))
3814 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3817 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3823 *total
= mips_cost
->fp_add
;
3825 *total
= COSTS_N_INSNS (4);
3829 /* Low-part immediates need an extended MIPS16 instruction. */
3830 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3831 + set_src_cost (XEXP (x
, 0), speed
));
3846 /* Branch comparisons have VOIDmode, so use the first operand's
3848 mode
= GET_MODE (XEXP (x
, 0));
3849 if (FLOAT_MODE_P (mode
))
3851 *total
= mips_cost
->fp_add
;
3854 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3860 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3861 && TARGET_FUSED_MADD
3862 && !HONOR_NANS (mode
)
3863 && !HONOR_SIGNED_ZEROS (mode
))
3865 /* See if we can use NMADD or NMSUB. See mips.md for the
3866 associated patterns. */
3867 rtx op0
= XEXP (x
, 0);
3868 rtx op1
= XEXP (x
, 1);
3869 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3871 *total
= (mips_fp_mult_cost (mode
)
3872 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3873 + set_src_cost (XEXP (op0
, 1), speed
)
3874 + set_src_cost (op1
, speed
));
3877 if (GET_CODE (op1
) == MULT
)
3879 *total
= (mips_fp_mult_cost (mode
)
3880 + set_src_cost (op0
, speed
)
3881 + set_src_cost (XEXP (op1
, 0), speed
)
3882 + set_src_cost (XEXP (op1
, 1), speed
));
3891 /* If this is part of a MADD or MSUB, treat the PLUS as
3893 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
3894 && TARGET_FUSED_MADD
3895 && GET_CODE (XEXP (x
, 0)) == MULT
)
3898 *total
= mips_cost
->fp_add
;
3902 /* Double-word operations require three single-word operations and
3903 an SLTU. The MIPS16 version then needs to move the result of
3904 the SLTU from $24 to a MIPS16 register. */
3905 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3906 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3912 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3913 && TARGET_FUSED_MADD
3914 && !HONOR_NANS (mode
)
3915 && HONOR_SIGNED_ZEROS (mode
))
3917 /* See if we can use NMADD or NMSUB. See mips.md for the
3918 associated patterns. */
3919 rtx op
= XEXP (x
, 0);
3920 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3921 && GET_CODE (XEXP (op
, 0)) == MULT
)
3923 *total
= (mips_fp_mult_cost (mode
)
3924 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3925 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3926 + set_src_cost (XEXP (op
, 1), speed
));
3932 *total
= mips_cost
->fp_add
;
3934 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3939 *total
= mips_fp_mult_cost (mode
);
3940 else if (mode
== DImode
&& !TARGET_64BIT
)
3941 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3942 where the mulsidi3 always includes an MFHI and an MFLO. */
3944 ? mips_cost
->int_mult_si
* 3 + 6
3945 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3947 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
3948 else if (mode
== DImode
)
3949 *total
= mips_cost
->int_mult_di
;
3951 *total
= mips_cost
->int_mult_si
;
3955 /* Check for a reciprocal. */
3958 && flag_unsafe_math_optimizations
3959 && XEXP (x
, 0) == CONST1_RTX (mode
))
3961 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3962 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3963 division as being free. */
3964 *total
= set_src_cost (XEXP (x
, 1), speed
);
3966 *total
= (mips_fp_div_cost (mode
)
3967 + set_src_cost (XEXP (x
, 1), speed
));
3976 *total
= mips_fp_div_cost (mode
);
3985 /* It is our responsibility to make division by a power of 2
3986 as cheap as 2 register additions if we want the division
3987 expanders to be used for such operations; see the setting
3988 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3989 should always produce shorter code than using
3990 expand_sdiv2_pow2. */
3992 && CONST_INT_P (XEXP (x
, 1))
3993 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3995 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3998 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4000 else if (mode
== DImode
)
4001 *total
= mips_cost
->int_div_di
;
4003 *total
= mips_cost
->int_div_si
;
4007 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4011 if (outer_code
== SET
4013 && GET_MODE (XEXP (x
, 0)) == QImode
4014 && GET_CODE (XEXP (x
, 0)) == PLUS
)
4016 rtx plus
= XEXP (x
, 0);
4017 *total
= (COSTS_N_INSNS (1)
4018 + mips_truncated_op_cost (XEXP (plus
, 0), speed
)
4019 + mips_truncated_op_cost (XEXP (plus
, 1), speed
));
4022 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4026 case UNSIGNED_FLOAT
:
4029 case FLOAT_TRUNCATE
:
4030 *total
= mips_cost
->fp_add
;
4034 if (register_operand (SET_DEST (x
), VOIDmode
)
4035 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4037 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4047 /* Implement TARGET_ADDRESS_COST. */
4050 mips_address_cost (rtx addr
, enum machine_mode mode
,
4051 addr_space_t as ATTRIBUTE_UNUSED
,
4052 bool speed ATTRIBUTE_UNUSED
)
4054 return mips_address_insns (addr
, mode
, false);
4057 /* Information about a single instruction in a multi-instruction
4059 struct mips_multi_member
{
4060 /* True if this is a label, false if it is code. */
4063 /* The output_asm_insn format of the instruction. */
4066 /* The operands to the instruction. */
4067 rtx operands
[MAX_RECOG_OPERANDS
];
4069 typedef struct mips_multi_member mips_multi_member
;
4071 /* The instructions that make up the current multi-insn sequence. */
4072 static vec
<mips_multi_member
> mips_multi_members
;
4074 /* How many instructions (as opposed to labels) are in the current
4075 multi-insn sequence. */
4076 static unsigned int mips_multi_num_insns
;
4078 /* Start a new multi-insn sequence. */
4081 mips_multi_start (void)
4083 mips_multi_members
.truncate (0);
4084 mips_multi_num_insns
= 0;
4087 /* Add a new, uninitialized member to the current multi-insn sequence. */
4089 static struct mips_multi_member
*
4090 mips_multi_add (void)
4092 mips_multi_member empty
;
4093 return mips_multi_members
.safe_push (empty
);
4096 /* Add a normal insn with the given asm format to the current multi-insn
4097 sequence. The other arguments are a null-terminated list of operands. */
4100 mips_multi_add_insn (const char *format
, ...)
4102 struct mips_multi_member
*member
;
4107 member
= mips_multi_add ();
4108 member
->is_label_p
= false;
4109 member
->format
= format
;
4110 va_start (ap
, format
);
4112 while ((op
= va_arg (ap
, rtx
)))
4113 member
->operands
[i
++] = op
;
4115 mips_multi_num_insns
++;
4118 /* Add the given label definition to the current multi-insn sequence.
4119 The definition should include the colon. */
4122 mips_multi_add_label (const char *label
)
4124 struct mips_multi_member
*member
;
4126 member
= mips_multi_add ();
4127 member
->is_label_p
= true;
4128 member
->format
= label
;
4131 /* Return the index of the last member of the current multi-insn sequence. */
4134 mips_multi_last_index (void)
4136 return mips_multi_members
.length () - 1;
4139 /* Add a copy of an existing instruction to the current multi-insn
4140 sequence. I is the index of the instruction that should be copied. */
4143 mips_multi_copy_insn (unsigned int i
)
4145 struct mips_multi_member
*member
;
4147 member
= mips_multi_add ();
4148 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4149 gcc_assert (!member
->is_label_p
);
4152 /* Change the operand of an existing instruction in the current
4153 multi-insn sequence. I is the index of the instruction,
4154 OP is the index of the operand, and X is the new value. */
4157 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4159 mips_multi_members
[i
].operands
[op
] = x
;
4162 /* Write out the asm code for the current multi-insn sequence. */
4165 mips_multi_write (void)
4167 struct mips_multi_member
*member
;
4170 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4171 if (member
->is_label_p
)
4172 fprintf (asm_out_file
, "%s\n", member
->format
);
4174 output_asm_insn (member
->format
, member
->operands
);
4177 /* Return one word of double-word value OP, taking into account the fixed
4178 endianness of certain registers. HIGH_P is true to select the high part,
4179 false to select the low part. */
4182 mips_subword (rtx op
, bool high_p
)
4184 unsigned int byte
, offset
;
4185 enum machine_mode mode
;
4187 mode
= GET_MODE (op
);
4188 if (mode
== VOIDmode
)
4189 mode
= TARGET_64BIT
? TImode
: DImode
;
4191 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4192 byte
= UNITS_PER_WORD
;
4196 if (FP_REG_RTX_P (op
))
4198 /* Paired FPRs are always ordered little-endian. */
4199 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4200 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4204 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4206 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4209 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4210 SPLIT_TYPE is the condition under which moves should be split. */
4213 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4215 return ((split_type
!= SPLIT_FOR_SPEED
4216 || mips_tuning_info
.fast_mult_zero_zero_p
)
4217 && src
== const0_rtx
4219 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4220 && (ISA_HAS_DSP_MULT
4221 ? ACC_REG_P (REGNO (dest
))
4222 : MD_REG_P (REGNO (dest
))));
4225 /* Return true if a move from SRC to DEST should be split into two.
4226 SPLIT_TYPE describes the split condition. */
4229 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4231 /* Check whether the move can be done using some variant of MULT $0,$0. */
4232 if (mips_mult_move_p (dest
, src
, split_type
))
4235 /* FPR-to-FPR moves can be done in a single instruction, if they're
4237 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4238 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4241 /* Check for floating-point loads and stores. */
4242 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4244 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4246 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4250 /* Otherwise split all multiword moves. */
4251 return size
> UNITS_PER_WORD
;
4254 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4255 SPLIT_TYPE describes the split condition. */
4258 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4262 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4263 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4265 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4266 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4267 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4268 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4269 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4270 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4271 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4272 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4273 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4274 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4275 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4276 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4277 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4278 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4282 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4284 low_dest
= mips_subword (dest
, false);
4285 mips_emit_move (low_dest
, mips_subword (src
, false));
4287 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4289 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4291 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4293 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4295 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4297 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4301 /* The operation can be split into two normal moves. Decide in
4302 which order to do them. */
4303 low_dest
= mips_subword (dest
, false);
4304 if (REG_P (low_dest
)
4305 && reg_overlap_mentioned_p (low_dest
, src
))
4307 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4308 mips_emit_move (low_dest
, mips_subword (src
, false));
4312 mips_emit_move (low_dest
, mips_subword (src
, false));
4313 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4318 /* Return the split type for instruction INSN. */
4320 static enum mips_split_type
4321 mips_insn_split_type (rtx insn
)
4323 basic_block bb
= BLOCK_FOR_INSN (insn
);
4326 if (optimize_bb_for_speed_p (bb
))
4327 return SPLIT_FOR_SPEED
;
4329 return SPLIT_FOR_SIZE
;
4331 /* Once CFG information has been removed, we should trust the optimization
4332 decisions made by previous passes and only split where necessary. */
4333 return SPLIT_IF_NECESSARY
;
4336 /* Return true if a move from SRC to DEST in INSN should be split. */
4339 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4341 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4344 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4348 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4350 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4353 /* Return the appropriate instructions to move SRC into DEST. Assume
4354 that SRC is operand 1 and DEST is operand 0. */
4357 mips_output_move (rtx dest
, rtx src
)
4359 enum rtx_code dest_code
, src_code
;
4360 enum machine_mode mode
;
4361 enum mips_symbol_type symbol_type
;
4364 dest_code
= GET_CODE (dest
);
4365 src_code
= GET_CODE (src
);
4366 mode
= GET_MODE (dest
);
4367 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4369 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4372 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4373 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4375 if (dest_code
== REG
)
4377 if (GP_REG_P (REGNO (dest
)))
4378 return "move\t%0,%z1";
4380 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4382 if (ISA_HAS_DSP_MULT
)
4383 return "mult\t%q0,%.,%.";
4385 return "mult\t%.,%.";
4388 /* Moves to HI are handled by special .md insns. */
4389 if (REGNO (dest
) == LO_REGNUM
)
4392 if (DSP_ACC_REG_P (REGNO (dest
)))
4394 static char retval
[] = "mt__\t%z1,%q0";
4396 retval
[2] = reg_names
[REGNO (dest
)][4];
4397 retval
[3] = reg_names
[REGNO (dest
)][5];
4401 if (FP_REG_P (REGNO (dest
)))
4402 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4404 if (ALL_COP_REG_P (REGNO (dest
)))
4406 static char retval
[] = "dmtc_\t%z1,%0";
4408 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4409 return dbl_p
? retval
: retval
+ 1;
4412 if (dest_code
== MEM
)
4413 switch (GET_MODE_SIZE (mode
))
4415 case 1: return "sb\t%z1,%0";
4416 case 2: return "sh\t%z1,%0";
4417 case 4: return "sw\t%z1,%0";
4418 case 8: return "sd\t%z1,%0";
4421 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4423 if (src_code
== REG
)
4425 /* Moves from HI are handled by special .md insns. */
4426 if (REGNO (src
) == LO_REGNUM
)
4428 /* When generating VR4120 or VR4130 code, we use MACC and
4429 DMACC instead of MFLO. This avoids both the normal
4430 MIPS III HI/LO hazards and the errata related to
4433 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4437 if (DSP_ACC_REG_P (REGNO (src
)))
4439 static char retval
[] = "mf__\t%0,%q1";
4441 retval
[2] = reg_names
[REGNO (src
)][4];
4442 retval
[3] = reg_names
[REGNO (src
)][5];
4446 if (FP_REG_P (REGNO (src
)))
4447 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4449 if (ALL_COP_REG_P (REGNO (src
)))
4451 static char retval
[] = "dmfc_\t%0,%1";
4453 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4454 return dbl_p
? retval
: retval
+ 1;
4458 if (src_code
== MEM
)
4459 switch (GET_MODE_SIZE (mode
))
4461 case 1: return "lbu\t%0,%1";
4462 case 2: return "lhu\t%0,%1";
4463 case 4: return "lw\t%0,%1";
4464 case 8: return "ld\t%0,%1";
4467 if (src_code
== CONST_INT
)
4469 /* Don't use the X format for the operand itself, because that
4470 will give out-of-range numbers for 64-bit hosts and 32-bit
4473 return "li\t%0,%1\t\t\t# %X1";
4475 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4478 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4482 if (src_code
== HIGH
)
4483 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4485 if (CONST_GP_P (src
))
4486 return "move\t%0,%1";
4488 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4489 && mips_lo_relocs
[symbol_type
] != 0)
4491 /* A signed 16-bit constant formed by applying a relocation
4492 operator to a symbolic address. */
4493 gcc_assert (!mips_split_p
[symbol_type
]);
4494 return "li\t%0,%R1";
4497 if (symbolic_operand (src
, VOIDmode
))
4499 gcc_assert (TARGET_MIPS16
4500 ? TARGET_MIPS16_TEXT_LOADS
4501 : !TARGET_EXPLICIT_RELOCS
);
4502 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4505 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4507 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4509 if (GET_MODE (dest
) == V2SFmode
)
4510 return "mov.ps\t%0,%1";
4512 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4515 if (dest_code
== MEM
)
4516 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4518 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4520 if (src_code
== MEM
)
4521 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4523 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4525 static char retval
[] = "l_c_\t%0,%1";
4527 retval
[1] = (dbl_p
? 'd' : 'w');
4528 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4531 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4533 static char retval
[] = "s_c_\t%1,%0";
4535 retval
[1] = (dbl_p
? 'd' : 'w');
4536 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4542 /* Return true if CMP1 is a suitable second operand for integer ordering
4543 test CODE. See also the *sCC patterns in mips.md. */
4546 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4552 return reg_or_0_operand (cmp1
, VOIDmode
);
4556 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4560 return arith_operand (cmp1
, VOIDmode
);
4563 return sle_operand (cmp1
, VOIDmode
);
4566 return sleu_operand (cmp1
, VOIDmode
);
4573 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4574 integer ordering test *CODE, or if an equivalent combination can
4575 be formed by adjusting *CODE and *CMP1. When returning true, update
4576 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4580 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4581 enum machine_mode mode
)
4583 HOST_WIDE_INT plus_one
;
4585 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4588 if (CONST_INT_P (*cmp1
))
4592 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4593 if (INTVAL (*cmp1
) < plus_one
)
4596 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4602 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4606 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4617 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4618 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4619 is nonnull, it's OK to set TARGET to the inverse of the result and
4620 flip *INVERT_PTR instead. */
4623 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4624 rtx target
, rtx cmp0
, rtx cmp1
)
4626 enum machine_mode mode
;
4628 /* First see if there is a MIPS instruction that can do this operation.
4629 If not, try doing the same for the inverse operation. If that also
4630 fails, force CMP1 into a register and try again. */
4631 mode
= GET_MODE (cmp0
);
4632 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4633 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4636 enum rtx_code inv_code
= reverse_condition (code
);
4637 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4639 cmp1
= force_reg (mode
, cmp1
);
4640 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4642 else if (invert_ptr
== 0)
4646 inv_target
= mips_force_binary (GET_MODE (target
),
4647 inv_code
, cmp0
, cmp1
);
4648 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4652 *invert_ptr
= !*invert_ptr
;
4653 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4658 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4659 The register will have the same mode as CMP0. */
4662 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4664 if (cmp1
== const0_rtx
)
4667 if (uns_arith_operand (cmp1
, VOIDmode
))
4668 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4669 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4671 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4672 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4675 /* Convert *CODE into a code that can be used in a floating-point
4676 scc instruction (C.cond.fmt). Return true if the values of
4677 the condition code registers will be inverted, with 0 indicating
4678 that the condition holds. */
4681 mips_reversed_fp_cond (enum rtx_code
*code
)
4688 *code
= reverse_condition_maybe_unordered (*code
);
4696 /* Allocate a floating-point condition-code register of mode MODE.
4698 These condition code registers are used for certain kinds
4699 of compound operation, such as compare and branches, vconds,
4700 and built-in functions. At expand time, their use is entirely
4701 controlled by MIPS-specific code and is entirely internal
4702 to these compound operations.
4704 We could (and did in the past) expose condition-code values
4705 as pseudo registers and leave the register allocator to pick
4706 appropriate registers. The problem is that it is not practically
4707 possible for the rtl optimizers to guarantee that no spills will
4708 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4709 therefore need spill and reload sequences to handle the worst case.
4711 Although such sequences do exist, they are very expensive and are
4712 not something we'd want to use. This is especially true of CCV2 and
4713 CCV4, where all the shuffling would greatly outweigh whatever benefit
4714 the vectorization itself provides.
4716 The main benefit of having more than one condition-code register
4717 is to allow the pipelining of operations, especially those involving
4718 comparisons and conditional moves. We don't really expect the
4719 registers to be live for long periods, and certainly never want
4720 them to be live across calls.
4722 Also, there should be no penalty attached to using all the available
4723 registers. They are simply bits in the same underlying FPU control
4726 We therefore expose the hardware registers from the outset and use
4727 a simple round-robin allocation scheme. */
4730 mips_allocate_fcc (enum machine_mode mode
)
4732 unsigned int regno
, count
;
4734 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4738 else if (mode
== CCV2mode
)
4740 else if (mode
== CCV4mode
)
4745 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4746 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4747 cfun
->machine
->next_fcc
= 0;
4748 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4749 cfun
->machine
->next_fcc
+= count
;
4750 return gen_rtx_REG (mode
, regno
);
4753 /* Convert a comparison into something that can be used in a branch or
4754 conditional move. On entry, *OP0 and *OP1 are the values being
4755 compared and *CODE is the code used to compare them.
4757 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4758 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4759 otherwise any standard branch condition can be used. The standard branch
4762 - EQ or NE between two registers.
4763 - any comparison between a register and zero. */
4766 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4771 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4773 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4775 else if (*code
== EQ
|| *code
== NE
)
4779 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4783 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4787 /* The comparison needs a separate scc instruction. Store the
4788 result of the scc in *OP0 and compare it against zero. */
4789 bool invert
= false;
4790 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4791 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4792 *code
= (invert
? EQ
: NE
);
4796 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4798 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4799 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4805 enum rtx_code cmp_code
;
4807 /* Floating-point tests use a separate C.cond.fmt comparison to
4808 set a condition code register. The branch or conditional move
4809 will then compare that register against zero.
4811 Set CMP_CODE to the code of the comparison instruction and
4812 *CODE to the code that the branch or move should use. */
4814 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4816 ? mips_allocate_fcc (CCmode
)
4817 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4819 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4823 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4824 and OPERAND[3]. Store the result in OPERANDS[0].
4826 On 64-bit targets, the mode of the comparison and target will always be
4827 SImode, thus possibly narrower than that of the comparison's operands. */
4830 mips_expand_scc (rtx operands
[])
4832 rtx target
= operands
[0];
4833 enum rtx_code code
= GET_CODE (operands
[1]);
4834 rtx op0
= operands
[2];
4835 rtx op1
= operands
[3];
4837 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4839 if (code
== EQ
|| code
== NE
)
4842 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4843 mips_emit_binary (code
, target
, op0
, op1
);
4846 rtx zie
= mips_zero_if_equal (op0
, op1
);
4847 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4851 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4854 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4855 CODE and jump to OPERANDS[3] if the condition holds. */
4858 mips_expand_conditional_branch (rtx
*operands
)
4860 enum rtx_code code
= GET_CODE (operands
[0]);
4861 rtx op0
= operands
[1];
4862 rtx op1
= operands
[2];
4865 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4866 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4867 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4872 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4873 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4876 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4877 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4882 reversed_p
= mips_reversed_fp_cond (&cond
);
4883 cmp_result
= mips_allocate_fcc (CCV2mode
);
4884 emit_insn (gen_scc_ps (cmp_result
,
4885 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4887 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4890 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4894 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4895 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4898 mips_expand_conditional_move (rtx
*operands
)
4901 enum rtx_code code
= GET_CODE (operands
[1]);
4902 rtx op0
= XEXP (operands
[1], 0);
4903 rtx op1
= XEXP (operands
[1], 1);
4905 mips_emit_compare (&code
, &op0
, &op1
, true);
4906 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4907 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4908 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4909 operands
[2], operands
[3])));
4912 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4915 mips_expand_conditional_trap (rtx comparison
)
4918 enum machine_mode mode
;
4921 /* MIPS conditional trap instructions don't have GT or LE flavors,
4922 so we must swap the operands and convert to LT and GE respectively. */
4923 code
= GET_CODE (comparison
);
4930 code
= swap_condition (code
);
4931 op0
= XEXP (comparison
, 1);
4932 op1
= XEXP (comparison
, 0);
4936 op0
= XEXP (comparison
, 0);
4937 op1
= XEXP (comparison
, 1);
4941 mode
= GET_MODE (XEXP (comparison
, 0));
4942 op0
= force_reg (mode
, op0
);
4943 if (!arith_operand (op1
, mode
))
4944 op1
= force_reg (mode
, op1
);
4946 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4947 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4951 /* Initialize *CUM for a call to a function of type FNTYPE. */
4954 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4956 memset (cum
, 0, sizeof (*cum
));
4957 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4958 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4961 /* Fill INFO with information about a single argument. CUM is the
4962 cumulative state for earlier arguments. MODE is the mode of this
4963 argument and TYPE is its type (if known). NAMED is true if this
4964 is a named (fixed) argument rather than a variable one. */
4967 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4968 enum machine_mode mode
, const_tree type
, bool named
)
4970 bool doubleword_aligned_p
;
4971 unsigned int num_bytes
, num_words
, max_regs
;
4973 /* Work out the size of the argument. */
4974 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4975 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4977 /* Decide whether it should go in a floating-point register, assuming
4978 one is free. Later code checks for availability.
4980 The checks against UNITS_PER_FPVALUE handle the soft-float and
4981 single-float cases. */
4985 /* The EABI conventions have traditionally been defined in terms
4986 of TYPE_MODE, regardless of the actual type. */
4987 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4988 || mode
== V2SFmode
)
4989 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4994 /* Only leading floating-point scalars are passed in
4995 floating-point registers. We also handle vector floats the same
4996 say, which is OK because they are not covered by the standard ABI. */
4997 info
->fpr_p
= (!cum
->gp_reg_found
4998 && cum
->arg_number
< 2
5000 || SCALAR_FLOAT_TYPE_P (type
)
5001 || VECTOR_FLOAT_TYPE_P (type
))
5002 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5003 || mode
== V2SFmode
)
5004 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5009 /* Scalar, complex and vector floating-point types are passed in
5010 floating-point registers, as long as this is a named rather
5011 than a variable argument. */
5012 info
->fpr_p
= (named
5013 && (type
== 0 || FLOAT_TYPE_P (type
))
5014 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5015 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5016 || mode
== V2SFmode
)
5017 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5019 /* ??? According to the ABI documentation, the real and imaginary
5020 parts of complex floats should be passed in individual registers.
5021 The real and imaginary parts of stack arguments are supposed
5022 to be contiguous and there should be an extra word of padding
5025 This has two problems. First, it makes it impossible to use a
5026 single "void *" va_list type, since register and stack arguments
5027 are passed differently. (At the time of writing, MIPSpro cannot
5028 handle complex float varargs correctly.) Second, it's unclear
5029 what should happen when there is only one register free.
5031 For now, we assume that named complex floats should go into FPRs
5032 if there are two FPRs free, otherwise they should be passed in the
5033 same way as a struct containing two floats. */
5035 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5036 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5038 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5039 info
->fpr_p
= false;
5049 /* See whether the argument has doubleword alignment. */
5050 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5053 /* Set REG_OFFSET to the register count we're interested in.
5054 The EABI allocates the floating-point registers separately,
5055 but the other ABIs allocate them like integer registers. */
5056 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5060 /* Advance to an even register if the argument is doubleword-aligned. */
5061 if (doubleword_aligned_p
)
5062 info
->reg_offset
+= info
->reg_offset
& 1;
5064 /* Work out the offset of a stack argument. */
5065 info
->stack_offset
= cum
->stack_words
;
5066 if (doubleword_aligned_p
)
5067 info
->stack_offset
+= info
->stack_offset
& 1;
5069 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5071 /* Partition the argument between registers and stack. */
5072 info
->reg_words
= MIN (num_words
, max_regs
);
5073 info
->stack_words
= num_words
- info
->reg_words
;
5076 /* INFO describes a register argument that has the normal format for the
5077 argument's mode. Return the register it uses, assuming that FPRs are
5078 available if HARD_FLOAT_P. */
5081 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5083 if (!info
->fpr_p
|| !hard_float_p
)
5084 return GP_ARG_FIRST
+ info
->reg_offset
;
5085 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5086 /* In o32, the second argument is always passed in $f14
5087 for TARGET_DOUBLE_FLOAT, regardless of whether the
5088 first argument was a word or doubleword. */
5089 return FP_ARG_FIRST
+ 2;
5091 return FP_ARG_FIRST
+ info
->reg_offset
;
5094 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5097 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5099 return !TARGET_OLDABI
;
5102 /* Implement TARGET_FUNCTION_ARG. */
5105 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5106 const_tree type
, bool named
)
5108 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5109 struct mips_arg_info info
;
5111 /* We will be called with a mode of VOIDmode after the last argument
5112 has been seen. Whatever we return will be passed to the call expander.
5113 If we need a MIPS16 fp_code, return a REG with the code stored as
5115 if (mode
== VOIDmode
)
5117 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5118 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5123 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5125 /* Return straight away if the whole argument is passed on the stack. */
5126 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5129 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5130 contains a double in its entirety, then that 64-bit chunk is passed
5131 in a floating-point register. */
5133 && TARGET_HARD_FLOAT
5136 && TREE_CODE (type
) == RECORD_TYPE
5137 && TYPE_SIZE_UNIT (type
)
5138 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5142 /* First check to see if there is any such field. */
5143 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5144 if (TREE_CODE (field
) == FIELD_DECL
5145 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5146 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5147 && host_integerp (bit_position (field
), 0)
5148 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5153 /* Now handle the special case by returning a PARALLEL
5154 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5155 chunks are passed in registers. */
5157 HOST_WIDE_INT bitpos
;
5160 /* assign_parms checks the mode of ENTRY_PARM, so we must
5161 use the actual mode here. */
5162 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5165 field
= TYPE_FIELDS (type
);
5166 for (i
= 0; i
< info
.reg_words
; i
++)
5170 for (; field
; field
= DECL_CHAIN (field
))
5171 if (TREE_CODE (field
) == FIELD_DECL
5172 && int_bit_position (field
) >= bitpos
)
5176 && int_bit_position (field
) == bitpos
5177 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5178 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5179 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5181 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5184 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5185 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5187 bitpos
+= BITS_PER_WORD
;
5193 /* Handle the n32/n64 conventions for passing complex floating-point
5194 arguments in FPR pairs. The real part goes in the lower register
5195 and the imaginary part goes in the upper register. */
5198 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5201 enum machine_mode inner
;
5204 inner
= GET_MODE_INNER (mode
);
5205 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5206 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5208 /* Real part in registers, imaginary part on stack. */
5209 gcc_assert (info
.stack_words
== info
.reg_words
);
5210 return gen_rtx_REG (inner
, regno
);
5214 gcc_assert (info
.stack_words
== 0);
5215 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5216 gen_rtx_REG (inner
, regno
),
5218 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5220 regno
+ info
.reg_words
/ 2),
5221 GEN_INT (GET_MODE_SIZE (inner
)));
5222 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5226 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5229 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5232 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5233 const_tree type
, bool named
)
5235 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5236 struct mips_arg_info info
;
5238 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5241 cum
->gp_reg_found
= true;
5243 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5244 an explanation of what this code does. It assumes that we're using
5245 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5247 if (cum
->arg_number
< 2 && info
.fpr_p
)
5248 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5250 /* Advance the register count. This has the effect of setting
5251 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5252 argument required us to skip the final GPR and pass the whole
5253 argument on the stack. */
5254 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5255 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5256 else if (info
.reg_words
> 0)
5257 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5259 /* Advance the stack word count. */
5260 if (info
.stack_words
> 0)
5261 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5266 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5269 mips_arg_partial_bytes (cumulative_args_t cum
,
5270 enum machine_mode mode
, tree type
, bool named
)
5272 struct mips_arg_info info
;
5274 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5275 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5278 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5279 least PARM_BOUNDARY bits of alignment, but will be given anything up
5280 to STACK_BOUNDARY bits if the type requires it. */
5283 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5285 unsigned int alignment
;
5287 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5288 if (alignment
< PARM_BOUNDARY
)
5289 alignment
= PARM_BOUNDARY
;
5290 if (alignment
> STACK_BOUNDARY
)
5291 alignment
= STACK_BOUNDARY
;
5295 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5296 upward rather than downward. In other words, return true if the
5297 first byte of the stack slot has useful data, false if the last
5301 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5303 /* On little-endian targets, the first byte of every stack argument
5304 is passed in the first byte of the stack slot. */
5305 if (!BYTES_BIG_ENDIAN
)
5308 /* Otherwise, integral types are padded downward: the last byte of a
5309 stack argument is passed in the last byte of the stack slot. */
5311 ? (INTEGRAL_TYPE_P (type
)
5312 || POINTER_TYPE_P (type
)
5313 || FIXED_POINT_TYPE_P (type
))
5314 : (SCALAR_INT_MODE_P (mode
)
5315 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5318 /* Big-endian o64 pads floating-point arguments downward. */
5319 if (mips_abi
== ABI_O64
)
5320 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5323 /* Other types are padded upward for o32, o64, n32 and n64. */
5324 if (mips_abi
!= ABI_EABI
)
5327 /* Arguments smaller than a stack slot are padded downward. */
5328 if (mode
!= BLKmode
)
5329 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5331 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5334 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5335 if the least significant byte of the register has useful data. Return
5336 the opposite if the most significant byte does. */
5339 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5341 /* No shifting is required for floating-point arguments. */
5342 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5343 return !BYTES_BIG_ENDIAN
;
5345 /* Otherwise, apply the same padding to register arguments as we do
5346 to stack arguments. */
5347 return mips_pad_arg_upward (mode
, type
);
5350 /* Return nonzero when an argument must be passed by reference. */
5353 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5354 enum machine_mode mode
, const_tree type
,
5355 bool named ATTRIBUTE_UNUSED
)
5357 if (mips_abi
== ABI_EABI
)
5361 /* ??? How should SCmode be handled? */
5362 if (mode
== DImode
|| mode
== DFmode
5363 || mode
== DQmode
|| mode
== UDQmode
5364 || mode
== DAmode
|| mode
== UDAmode
)
5367 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5368 return size
== -1 || size
> UNITS_PER_WORD
;
5372 /* If we have a variable-sized parameter, we have no choice. */
5373 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5377 /* Implement TARGET_CALLEE_COPIES. */
5380 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5381 enum machine_mode mode ATTRIBUTE_UNUSED
,
5382 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5384 return mips_abi
== ABI_EABI
&& named
;
5387 /* See whether VALTYPE is a record whose fields should be returned in
5388 floating-point registers. If so, return the number of fields and
5389 list them in FIELDS (which should have two elements). Return 0
5392 For n32 & n64, a structure with one or two fields is returned in
5393 floating-point registers as long as every field has a floating-point
5397 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5405 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5409 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5411 if (TREE_CODE (field
) != FIELD_DECL
)
5414 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5420 fields
[i
++] = field
;
5425 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5426 a value in the most significant part of $2/$3 if:
5428 - the target is big-endian;
5430 - the value has a structure or union type (we generalize this to
5431 cover aggregates from other languages too); and
5433 - the structure is not returned in floating-point registers. */
5436 mips_return_in_msb (const_tree valtype
)
5440 return (TARGET_NEWABI
5441 && TARGET_BIG_ENDIAN
5442 && AGGREGATE_TYPE_P (valtype
)
5443 && mips_fpr_return_fields (valtype
, fields
) == 0);
5446 /* Return true if the function return value MODE will get returned in a
5447 floating-point register. */
5450 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5452 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5454 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5455 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5458 /* Return the representation of an FPR return register when the
5459 value being returned in FP_RETURN has mode VALUE_MODE and the
5460 return type itself has mode TYPE_MODE. On NewABI targets,
5461 the two modes may be different for structures like:
5463 struct __attribute__((packed)) foo { float f; }
5465 where we return the SFmode value of "f" in FP_RETURN, but where
5466 the structure itself has mode BLKmode. */
5469 mips_return_fpr_single (enum machine_mode type_mode
,
5470 enum machine_mode value_mode
)
5474 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5475 if (type_mode
!= value_mode
)
5477 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5478 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5483 /* Return a composite value in a pair of floating-point registers.
5484 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5485 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5488 For n32 & n64, $f0 always holds the first value and $f2 the second.
5489 Otherwise the values are packed together as closely as possible. */
5492 mips_return_fpr_pair (enum machine_mode mode
,
5493 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5494 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5498 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5499 return gen_rtx_PARALLEL
5502 gen_rtx_EXPR_LIST (VOIDmode
,
5503 gen_rtx_REG (mode1
, FP_RETURN
),
5505 gen_rtx_EXPR_LIST (VOIDmode
,
5506 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5507 GEN_INT (offset2
))));
5511 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5512 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5513 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5516 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5517 enum machine_mode mode
)
5525 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5526 func
= fn_decl_or_type
;
5530 mode
= TYPE_MODE (valtype
);
5531 unsigned_p
= TYPE_UNSIGNED (valtype
);
5533 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5534 return values, promote the mode here too. */
5535 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5537 /* Handle structures whose fields are returned in $f0/$f2. */
5538 switch (mips_fpr_return_fields (valtype
, fields
))
5541 return mips_return_fpr_single (mode
,
5542 TYPE_MODE (TREE_TYPE (fields
[0])));
5545 return mips_return_fpr_pair (mode
,
5546 TYPE_MODE (TREE_TYPE (fields
[0])),
5547 int_byte_position (fields
[0]),
5548 TYPE_MODE (TREE_TYPE (fields
[1])),
5549 int_byte_position (fields
[1]));
5552 /* If a value is passed in the most significant part of a register, see
5553 whether we have to round the mode up to a whole number of words. */
5554 if (mips_return_in_msb (valtype
))
5556 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5557 if (size
% UNITS_PER_WORD
!= 0)
5559 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5560 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5564 /* For EABI, the class of return register depends entirely on MODE.
5565 For example, "struct { some_type x; }" and "union { some_type x; }"
5566 are returned in the same way as a bare "some_type" would be.
5567 Other ABIs only use FPRs for scalar, complex or vector types. */
5568 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5569 return gen_rtx_REG (mode
, GP_RETURN
);
5574 /* Handle long doubles for n32 & n64. */
5576 return mips_return_fpr_pair (mode
,
5578 DImode
, GET_MODE_SIZE (mode
) / 2);
5580 if (mips_return_mode_in_fpr_p (mode
))
5582 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5583 return mips_return_fpr_pair (mode
,
5584 GET_MODE_INNER (mode
), 0,
5585 GET_MODE_INNER (mode
),
5586 GET_MODE_SIZE (mode
) / 2);
5588 return gen_rtx_REG (mode
, FP_RETURN
);
5592 return gen_rtx_REG (mode
, GP_RETURN
);
5595 /* Implement TARGET_FUNCTION_VALUE. */
5598 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5599 bool outgoing ATTRIBUTE_UNUSED
)
5601 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5604 /* Implement TARGET_LIBCALL_VALUE. */
5607 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5609 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5612 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5614 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5615 Currently, R2 and F0 are only implemented here (C has no complex type). */
5618 mips_function_value_regno_p (const unsigned int regno
)
5620 if (regno
== GP_RETURN
5621 || regno
== FP_RETURN
5622 || (LONG_DOUBLE_TYPE_SIZE
== 128
5623 && FP_RETURN
!= GP_RETURN
5624 && regno
== FP_RETURN
+ 2))
5630 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5631 all BLKmode objects are returned in memory. Under the n32, n64
5632 and embedded ABIs, small structures are returned in a register.
5633 Objects with varying size must still be returned in memory, of
5637 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5639 return (TARGET_OLDABI
5640 ? TYPE_MODE (type
) == BLKmode
5641 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5644 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5647 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5648 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5651 CUMULATIVE_ARGS local_cum
;
5652 int gp_saved
, fp_saved
;
5654 /* The caller has advanced CUM up to, but not beyond, the last named
5655 argument. Advance a local copy of CUM past the last "real" named
5656 argument, to find out how many registers are left over. */
5657 local_cum
= *get_cumulative_args (cum
);
5658 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5661 /* Found out how many registers we need to save. */
5662 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5663 fp_saved
= (EABI_FLOAT_VARARGS_P
5664 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5673 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5674 REG_PARM_STACK_SPACE (cfun
->decl
)
5675 - gp_saved
* UNITS_PER_WORD
);
5676 mem
= gen_frame_mem (BLKmode
, ptr
);
5677 set_mem_alias_set (mem
, get_varargs_alias_set ());
5679 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5684 /* We can't use move_block_from_reg, because it will use
5686 enum machine_mode mode
;
5689 /* Set OFF to the offset from virtual_incoming_args_rtx of
5690 the first float register. The FP save area lies below
5691 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5692 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5693 off
-= fp_saved
* UNITS_PER_FPREG
;
5695 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5697 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5698 i
+= MAX_FPRS_PER_FMT
)
5702 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5703 mem
= gen_frame_mem (mode
, ptr
);
5704 set_mem_alias_set (mem
, get_varargs_alias_set ());
5705 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5706 off
+= UNITS_PER_HWFPVALUE
;
5710 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5711 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5712 + fp_saved
* UNITS_PER_FPREG
);
5715 /* Implement TARGET_BUILTIN_VA_LIST. */
5718 mips_build_builtin_va_list (void)
5720 if (EABI_FLOAT_VARARGS_P
)
5722 /* We keep 3 pointers, and two offsets.
5724 Two pointers are to the overflow area, which starts at the CFA.
5725 One of these is constant, for addressing into the GPR save area
5726 below it. The other is advanced up the stack through the
5729 The third pointer is to the bottom of the GPR save area.
5730 Since the FPR save area is just below it, we can address
5731 FPR slots off this pointer.
5733 We also keep two one-byte offsets, which are to be subtracted
5734 from the constant pointers to yield addresses in the GPR and
5735 FPR save areas. These are downcounted as float or non-float
5736 arguments are used, and when they get to zero, the argument
5737 must be obtained from the overflow region. */
5738 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5741 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5743 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5744 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5746 f_gtop
= build_decl (BUILTINS_LOCATION
,
5747 FIELD_DECL
, get_identifier ("__gpr_top"),
5749 f_ftop
= build_decl (BUILTINS_LOCATION
,
5750 FIELD_DECL
, get_identifier ("__fpr_top"),
5752 f_goff
= build_decl (BUILTINS_LOCATION
,
5753 FIELD_DECL
, get_identifier ("__gpr_offset"),
5754 unsigned_char_type_node
);
5755 f_foff
= build_decl (BUILTINS_LOCATION
,
5756 FIELD_DECL
, get_identifier ("__fpr_offset"),
5757 unsigned_char_type_node
);
5758 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5759 warn on every user file. */
5760 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5761 array
= build_array_type (unsigned_char_type_node
,
5762 build_index_type (index
));
5763 f_res
= build_decl (BUILTINS_LOCATION
,
5764 FIELD_DECL
, get_identifier ("__reserved"), array
);
5766 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5767 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5768 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5769 DECL_FIELD_CONTEXT (f_goff
) = record
;
5770 DECL_FIELD_CONTEXT (f_foff
) = record
;
5771 DECL_FIELD_CONTEXT (f_res
) = record
;
5773 TYPE_FIELDS (record
) = f_ovfl
;
5774 DECL_CHAIN (f_ovfl
) = f_gtop
;
5775 DECL_CHAIN (f_gtop
) = f_ftop
;
5776 DECL_CHAIN (f_ftop
) = f_goff
;
5777 DECL_CHAIN (f_goff
) = f_foff
;
5778 DECL_CHAIN (f_foff
) = f_res
;
5780 layout_type (record
);
5784 /* Otherwise, we use 'void *'. */
5785 return ptr_type_node
;
5788 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5791 mips_va_start (tree valist
, rtx nextarg
)
5793 if (EABI_FLOAT_VARARGS_P
)
5795 const CUMULATIVE_ARGS
*cum
;
5796 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5797 tree ovfl
, gtop
, ftop
, goff
, foff
;
5799 int gpr_save_area_size
;
5800 int fpr_save_area_size
;
5803 cum
= &crtl
->args
.info
;
5805 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5807 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5809 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5810 f_gtop
= DECL_CHAIN (f_ovfl
);
5811 f_ftop
= DECL_CHAIN (f_gtop
);
5812 f_goff
= DECL_CHAIN (f_ftop
);
5813 f_foff
= DECL_CHAIN (f_goff
);
5815 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5817 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5819 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5821 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5823 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5826 /* Emit code to initialize OVFL, which points to the next varargs
5827 stack argument. CUM->STACK_WORDS gives the number of stack
5828 words used by named arguments. */
5829 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5830 if (cum
->stack_words
> 0)
5831 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5832 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5833 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5835 /* Emit code to initialize GTOP, the top of the GPR save area. */
5836 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5837 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5838 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5840 /* Emit code to initialize FTOP, the top of the FPR save area.
5841 This address is gpr_save_area_bytes below GTOP, rounded
5842 down to the next fp-aligned boundary. */
5843 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5844 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5845 fpr_offset
&= -UNITS_PER_FPVALUE
;
5847 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5848 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5849 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5851 /* Emit code to initialize GOFF, the offset from GTOP of the
5852 next GPR argument. */
5853 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5854 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5855 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5857 /* Likewise emit code to initialize FOFF, the offset from FTOP
5858 of the next FPR argument. */
5859 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5860 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5861 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5865 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5866 std_expand_builtin_va_start (valist
, nextarg
);
5870 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5874 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5877 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5878 unsigned HOST_WIDE_INT align
, boundary
;
5881 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5883 type
= build_pointer_type (type
);
5885 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5886 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5888 /* When we align parameter on stack for caller, if the parameter
5889 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5890 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5891 here with caller. */
5892 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5893 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5895 boundary
/= BITS_PER_UNIT
;
5897 /* Hoist the valist value into a temporary for the moment. */
5898 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5900 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5901 requires greater alignment, we must perform dynamic alignment. */
5902 if (boundary
> align
)
5904 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5905 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5906 gimplify_and_add (t
, pre_p
);
5908 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5909 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5911 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5912 gimplify_and_add (t
, pre_p
);
5917 /* If the actual alignment is less than the alignment of the type,
5918 adjust the type accordingly so that we don't assume strict alignment
5919 when dereferencing the pointer. */
5920 boundary
*= BITS_PER_UNIT
;
5921 if (boundary
< TYPE_ALIGN (type
))
5923 type
= build_variant_type_copy (type
);
5924 TYPE_ALIGN (type
) = boundary
;
5927 /* Compute the rounded size of the type. */
5928 type_size
= size_in_bytes (type
);
5929 rounded_size
= round_up (type_size
, align
);
5931 /* Reduce rounded_size so it's sharable with the postqueue. */
5932 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5936 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5938 /* Small args are padded downward. */
5939 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5940 rounded_size
, size_int (align
));
5941 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5942 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5943 addr
= fold_build_pointer_plus (addr
, t
);
5946 /* Compute new value for AP. */
5947 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5948 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5949 gimplify_and_add (t
, pre_p
);
5951 addr
= fold_convert (build_pointer_type (type
), addr
);
5954 addr
= build_va_arg_indirect_ref (addr
);
5956 return build_va_arg_indirect_ref (addr
);
5959 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5962 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5968 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5970 type
= build_pointer_type (type
);
5972 if (!EABI_FLOAT_VARARGS_P
)
5973 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5976 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5977 tree ovfl
, top
, off
, align
;
5978 HOST_WIDE_INT size
, rsize
, osize
;
5981 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5982 f_gtop
= DECL_CHAIN (f_ovfl
);
5983 f_ftop
= DECL_CHAIN (f_gtop
);
5984 f_goff
= DECL_CHAIN (f_ftop
);
5985 f_foff
= DECL_CHAIN (f_goff
);
5989 TOP be the top of the GPR or FPR save area;
5990 OFF be the offset from TOP of the next register;
5991 ADDR_RTX be the address of the argument;
5992 SIZE be the number of bytes in the argument type;
5993 RSIZE be the number of bytes used to store the argument
5994 when it's in the register save area; and
5995 OSIZE be the number of bytes used to store it when it's
5996 in the stack overflow area.
5998 The code we want is:
6000 1: off &= -rsize; // round down
6003 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6008 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6009 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6013 [1] and [9] can sometimes be optimized away. */
6015 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6017 size
= int_size_in_bytes (type
);
6019 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6020 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6022 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6023 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6024 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6025 unshare_expr (valist
), f_foff
, NULL_TREE
);
6027 /* When va_start saves FPR arguments to the stack, each slot
6028 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6029 argument's precision. */
6030 rsize
= UNITS_PER_HWFPVALUE
;
6032 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6033 (= PARM_BOUNDARY bits). This can be different from RSIZE
6036 (1) On 32-bit targets when TYPE is a structure such as:
6038 struct s { float f; };
6040 Such structures are passed in paired FPRs, so RSIZE
6041 will be 8 bytes. However, the structure only takes
6042 up 4 bytes of memory, so OSIZE will only be 4.
6044 (2) In combinations such as -mgp64 -msingle-float
6045 -fshort-double. Doubles passed in registers will then take
6046 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6047 stack take up UNITS_PER_WORD bytes. */
6048 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6052 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6053 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6054 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6055 unshare_expr (valist
), f_goff
, NULL_TREE
);
6056 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6057 if (rsize
> UNITS_PER_WORD
)
6059 /* [1] Emit code for: off &= -rsize. */
6060 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6061 build_int_cst (TREE_TYPE (off
), -rsize
));
6062 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6067 /* [2] Emit code to branch if off == 0. */
6068 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6069 build_int_cst (TREE_TYPE (off
), 0));
6070 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6072 /* [5] Emit code for: off -= rsize. We do this as a form of
6073 post-decrement not available to C. */
6074 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6075 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6077 /* [4] Emit code for:
6078 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6079 t
= fold_convert (sizetype
, t
);
6080 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6081 t
= fold_build_pointer_plus (top
, t
);
6082 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6083 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6084 COND_EXPR_THEN (addr
) = t
;
6086 if (osize
> UNITS_PER_WORD
)
6088 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6089 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6090 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6091 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6092 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6093 unshare_expr (ovfl
), t
);
6098 /* [10, 11] Emit code for:
6099 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6101 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6102 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6103 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6104 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6106 /* String [9] and [10, 11] together. */
6108 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6109 COND_EXPR_ELSE (addr
) = t
;
6111 addr
= fold_convert (build_pointer_type (type
), addr
);
6112 addr
= build_va_arg_indirect_ref (addr
);
6116 addr
= build_va_arg_indirect_ref (addr
);
6121 /* Declare a unique, locally-binding function called NAME, then start
6125 mips_start_unique_function (const char *name
)
6129 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6130 get_identifier (name
),
6131 build_function_type_list (void_type_node
, NULL_TREE
));
6132 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6133 NULL_TREE
, void_type_node
);
6134 TREE_PUBLIC (decl
) = 1;
6135 TREE_STATIC (decl
) = 1;
6137 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6139 targetm
.asm_out
.unique_section (decl
, 0);
6140 switch_to_section (get_named_section (decl
, NULL
, 0));
6142 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6143 fputs ("\t.hidden\t", asm_out_file
);
6144 assemble_name (asm_out_file
, name
);
6145 putc ('\n', asm_out_file
);
6148 /* Start a definition of function NAME. MIPS16_P indicates whether the
6149 function contains MIPS16 code. */
6152 mips_start_function_definition (const char *name
, bool mips16_p
)
6155 fprintf (asm_out_file
, "\t.set\tmips16\n");
6157 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6159 if (TARGET_MICROMIPS
)
6160 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6161 #ifdef HAVE_GAS_MICROMIPS
6163 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6166 if (!flag_inhibit_size_directive
)
6168 fputs ("\t.ent\t", asm_out_file
);
6169 assemble_name (asm_out_file
, name
);
6170 fputs ("\n", asm_out_file
);
6173 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6175 /* Start the definition proper. */
6176 assemble_name (asm_out_file
, name
);
6177 fputs (":\n", asm_out_file
);
6180 /* End a function definition started by mips_start_function_definition. */
6183 mips_end_function_definition (const char *name
)
6185 if (!flag_inhibit_size_directive
)
6187 fputs ("\t.end\t", asm_out_file
);
6188 assemble_name (asm_out_file
, name
);
6189 fputs ("\n", asm_out_file
);
6193 /* Output a definition of the __mips16_rdhwr function. */
6196 mips_output_mips16_rdhwr (void)
6200 name
= "__mips16_rdhwr";
6201 mips_start_unique_function (name
);
6202 mips_start_function_definition (name
, false);
6203 fprintf (asm_out_file
,
6205 "\t.set\tmips32r2\n"
6206 "\t.set\tnoreorder\n"
6210 mips_end_function_definition (name
);
6213 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6216 mips_ok_for_lazy_binding_p (rtx x
)
6218 return (TARGET_USE_GOT
6219 && GET_CODE (x
) == SYMBOL_REF
6220 && !SYMBOL_REF_BIND_NOW_P (x
)
6221 && !mips_symbol_binds_local_p (x
));
6224 /* Load function address ADDR into register DEST. TYPE is as for
6225 mips_expand_call. Return true if we used an explicit lazy-binding
6229 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6231 /* If we're generating PIC, and this call is to a global function,
6232 try to allow its address to be resolved lazily. This isn't
6233 possible for sibcalls when $gp is call-saved because the value
6234 of $gp on entry to the stub would be our caller's gp, not ours. */
6235 if (TARGET_EXPLICIT_RELOCS
6236 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6237 && mips_ok_for_lazy_binding_p (addr
))
6239 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6240 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6245 mips_emit_move (dest
, addr
);
6250 /* Each locally-defined hard-float MIPS16 function has a local symbol
6251 associated with it. This hash table maps the function symbol (FUNC)
6252 to the local symbol (LOCAL). */
6253 struct GTY(()) mips16_local_alias
{
6257 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6259 /* Hash table callbacks for mips16_local_aliases. */
6262 mips16_local_aliases_hash (const void *entry
)
6264 const struct mips16_local_alias
*alias
;
6266 alias
= (const struct mips16_local_alias
*) entry
;
6267 return htab_hash_string (XSTR (alias
->func
, 0));
6271 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6273 const struct mips16_local_alias
*alias1
, *alias2
;
6275 alias1
= (const struct mips16_local_alias
*) entry1
;
6276 alias2
= (const struct mips16_local_alias
*) entry2
;
6277 return rtx_equal_p (alias1
->func
, alias2
->func
);
6280 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6281 Return a local alias for it, creating a new one if necessary. */
6284 mips16_local_alias (rtx func
)
6286 struct mips16_local_alias
*alias
, tmp_alias
;
6289 /* Create the hash table if this is the first call. */
6290 if (mips16_local_aliases
== NULL
)
6291 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6292 mips16_local_aliases_eq
, NULL
);
6294 /* Look up the function symbol, creating a new entry if need be. */
6295 tmp_alias
.func
= func
;
6296 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6297 gcc_assert (slot
!= NULL
);
6299 alias
= (struct mips16_local_alias
*) *slot
;
6302 const char *func_name
, *local_name
;
6305 /* Create a new SYMBOL_REF for the local symbol. The choice of
6306 __fn_local_* is based on the __fn_stub_* names that we've
6307 traditionally used for the non-MIPS16 stub. */
6308 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6309 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6310 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6311 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6313 /* Create a new structure to represent the mapping. */
6314 alias
= ggc_alloc_mips16_local_alias ();
6316 alias
->local
= local
;
6319 return alias
->local
;
6322 /* A chained list of functions for which mips16_build_call_stub has already
6323 generated a stub. NAME is the name of the function and FP_RET_P is true
6324 if the function returns a value in floating-point registers. */
6325 struct mips16_stub
{
6326 struct mips16_stub
*next
;
6330 static struct mips16_stub
*mips16_stubs
;
6332 /* Return the two-character string that identifies floating-point
6333 return mode MODE in the name of a MIPS16 function stub. */
6336 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6340 else if (mode
== DFmode
)
6342 else if (mode
== SCmode
)
6344 else if (mode
== DCmode
)
6346 else if (mode
== V2SFmode
)
6352 /* Write instructions to move a 32-bit value between general register
6353 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6354 from GPREG to FPREG and 'f' to move in the opposite direction. */
6357 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6359 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6360 reg_names
[gpreg
], reg_names
[fpreg
]);
6363 /* Likewise for 64-bit values. */
6366 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6369 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6370 reg_names
[gpreg
], reg_names
[fpreg
]);
6371 else if (TARGET_FLOAT64
)
6373 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6374 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6375 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6376 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6380 /* Move the least-significant word. */
6381 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6382 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6383 /* ...then the most significant word. */
6384 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6385 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6389 /* Write out code to move floating-point arguments into or out of
6390 general registers. FP_CODE is the code describing which arguments
6391 are present (see the comment above the definition of CUMULATIVE_ARGS
6392 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6395 mips_output_args_xfer (int fp_code
, char direction
)
6397 unsigned int gparg
, fparg
, f
;
6398 CUMULATIVE_ARGS cum
;
6400 /* This code only works for o32 and o64. */
6401 gcc_assert (TARGET_OLDABI
);
6403 mips_init_cumulative_args (&cum
, NULL
);
6405 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6407 enum machine_mode mode
;
6408 struct mips_arg_info info
;
6412 else if ((f
& 3) == 2)
6417 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6418 gparg
= mips_arg_regno (&info
, false);
6419 fparg
= mips_arg_regno (&info
, true);
6422 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6424 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6426 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6430 /* Write a MIPS16 stub for the current function. This stub is used
6431 for functions which take arguments in the floating-point registers.
6432 It is normal-mode code that moves the floating-point arguments
6433 into the general registers and then jumps to the MIPS16 code. */
6436 mips16_build_function_stub (void)
6438 const char *fnname
, *alias_name
, *separator
;
6439 char *secname
, *stubname
;
6444 /* Create the name of the stub, and its unique section. */
6445 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6446 alias
= mips16_local_alias (symbol
);
6448 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6449 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6450 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6451 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6453 /* Build a decl for the stub. */
6454 stubdecl
= build_decl (BUILTINS_LOCATION
,
6455 FUNCTION_DECL
, get_identifier (stubname
),
6456 build_function_type_list (void_type_node
, NULL_TREE
));
6457 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6458 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6459 RESULT_DECL
, NULL_TREE
, void_type_node
);
6461 /* Output a comment. */
6462 fprintf (asm_out_file
, "\t# Stub function for %s (",
6463 current_function_name ());
6465 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6467 fprintf (asm_out_file
, "%s%s", separator
,
6468 (f
& 3) == 1 ? "float" : "double");
6471 fprintf (asm_out_file
, ")\n");
6473 /* Start the function definition. */
6474 assemble_start_function (stubdecl
, stubname
);
6475 mips_start_function_definition (stubname
, false);
6477 /* If generating pic2 code, either set up the global pointer or
6479 if (TARGET_ABICALLS_PIC2
)
6481 if (TARGET_ABSOLUTE_ABICALLS
)
6482 fprintf (asm_out_file
, "\t.option\tpic0\n");
6485 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6486 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6487 target function is. Use a local GOT access when loading the
6488 symbol, to cut down on the number of unnecessary GOT entries
6489 for stubs that aren't needed. */
6490 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6495 /* Load the address of the MIPS16 function into $25. Do this first so
6496 that targets with coprocessor interlocks can use an MFC1 to fill the
6498 output_asm_insn ("la\t%^,%0", &symbol
);
6500 /* Move the arguments from floating-point registers to general registers. */
6501 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6503 /* Jump to the MIPS16 function. */
6504 output_asm_insn ("jr\t%^", NULL
);
6506 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6507 fprintf (asm_out_file
, "\t.option\tpic2\n");
6509 mips_end_function_definition (stubname
);
6511 /* If the linker needs to create a dynamic symbol for the target
6512 function, it will associate the symbol with the stub (which,
6513 unlike the target function, follows the proper calling conventions).
6514 It is therefore useful to have a local alias for the target function,
6515 so that it can still be identified as MIPS16 code. As an optimization,
6516 this symbol can also be used for indirect MIPS16 references from
6517 within this file. */
6518 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6520 switch_to_section (function_section (current_function_decl
));
6523 /* The current function is a MIPS16 function that returns a value in an FPR.
6524 Copy the return value from its soft-float to its hard-float location.
6525 libgcc2 has special non-MIPS16 helper functions for each case. */
6528 mips16_copy_fpr_return_value (void)
6530 rtx fn
, insn
, retval
;
6532 enum machine_mode return_mode
;
6535 return_type
= DECL_RESULT (current_function_decl
);
6536 return_mode
= DECL_MODE (return_type
);
6538 name
= ACONCAT (("__mips16_ret_",
6539 mips16_call_stub_mode_suffix (return_mode
),
6541 fn
= mips16_stub_function (name
);
6543 /* The function takes arguments in $2 (and possibly $3), so calls
6544 to it cannot be lazily bound. */
6545 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6547 /* Model the call as something that takes the GPR return value as
6548 argument and returns an "updated" value. */
6549 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6550 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6551 const0_rtx
, NULL_RTX
, false);
6552 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6555 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6556 RETVAL is the location of the return value, or null if this is
6557 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6558 arguments and FP_CODE is the code built by mips_function_arg;
6559 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6561 There are three alternatives:
6563 - If a stub was needed, emit the call and return the call insn itself.
6565 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6566 to the new target and return null.
6568 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6571 A stub is needed for calls to functions that, in normal mode,
6572 receive arguments in FPRs or return values in FPRs. The stub
6573 copies the arguments from their soft-float positions to their
6574 hard-float positions, calls the real function, then copies the
6575 return value from its hard-float position to its soft-float
6578 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6579 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6580 automatically redirects the JAL to the stub, otherwise the JAL
6581 continues to call FN directly. */
6584 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6588 struct mips16_stub
*l
;
6591 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6592 we were invoked with the -msoft-float option. */
6593 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6596 /* Figure out whether the value might come back in a floating-point
6598 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6600 /* We don't need to do anything if there were no floating-point
6601 arguments and the value will not be returned in a floating-point
6603 if (fp_code
== 0 && !fp_ret_p
)
6606 /* We don't need to do anything if this is a call to a special
6607 MIPS16 support function. */
6609 if (mips16_stub_function_p (fn
))
6612 /* If we're calling a locally-defined MIPS16 function, we know that
6613 it will return values in both the "soft-float" and "hard-float"
6614 registers. There is no need to use a stub to move the latter
6616 if (fp_code
== 0 && mips16_local_function_p (fn
))
6619 /* This code will only work for o32 and o64 abis. The other ABI's
6620 require more sophisticated support. */
6621 gcc_assert (TARGET_OLDABI
);
6623 /* If we're calling via a function pointer, use one of the magic
6624 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6625 Each stub expects the function address to arrive in register $2. */
6626 if (GET_CODE (fn
) != SYMBOL_REF
6627 || !call_insn_operand (fn
, VOIDmode
))
6630 rtx stub_fn
, insn
, addr
;
6633 /* If this is a locally-defined and locally-binding function,
6634 avoid the stub by calling the local alias directly. */
6635 if (mips16_local_function_p (fn
))
6637 *fn_ptr
= mips16_local_alias (fn
);
6641 /* Create a SYMBOL_REF for the libgcc.a function. */
6643 sprintf (buf
, "__mips16_call_stub_%s_%d",
6644 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6647 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6648 stub_fn
= mips16_stub_function (buf
);
6650 /* The function uses $2 as an argument, so calls to it
6651 cannot be lazily bound. */
6652 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6654 /* Load the target function into $2. */
6655 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6656 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6658 /* Emit the call. */
6659 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6660 args_size
, NULL_RTX
, lazy_p
);
6662 /* Tell GCC that this call does indeed use the value of $2. */
6663 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6665 /* If we are handling a floating-point return value, we need to
6666 save $18 in the function prologue. Putting a note on the
6667 call will mean that df_regs_ever_live_p ($18) will be true if the
6668 call is not eliminated, and we can check that in the prologue
6671 CALL_INSN_FUNCTION_USAGE (insn
) =
6672 gen_rtx_EXPR_LIST (VOIDmode
,
6673 gen_rtx_CLOBBER (VOIDmode
,
6674 gen_rtx_REG (word_mode
, 18)),
6675 CALL_INSN_FUNCTION_USAGE (insn
));
6680 /* We know the function we are going to call. If we have already
6681 built a stub, we don't need to do anything further. */
6682 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6683 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6684 if (strcmp (l
->name
, fnname
) == 0)
6689 const char *separator
;
6690 char *secname
, *stubname
;
6691 tree stubid
, stubdecl
;
6694 /* If the function does not return in FPRs, the special stub
6698 If the function does return in FPRs, the stub section is named
6699 .mips16.call.fp.FNNAME
6701 Build a decl for the stub. */
6702 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6704 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6706 stubid
= get_identifier (stubname
);
6707 stubdecl
= build_decl (BUILTINS_LOCATION
,
6708 FUNCTION_DECL
, stubid
,
6709 build_function_type_list (void_type_node
,
6711 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6712 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6713 RESULT_DECL
, NULL_TREE
,
6716 /* Output a comment. */
6717 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6719 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6723 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6725 fprintf (asm_out_file
, "%s%s", separator
,
6726 (f
& 3) == 1 ? "float" : "double");
6729 fprintf (asm_out_file
, ")\n");
6731 /* Start the function definition. */
6732 assemble_start_function (stubdecl
, stubname
);
6733 mips_start_function_definition (stubname
, false);
6737 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6739 /* Create a fake CFA 4 bytes below the stack pointer.
6740 This works around unwinders (like libgcc's) that expect
6741 the CFA for non-signal frames to be unique. */
6742 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6744 /* "Save" $sp in itself so we don't use the fake CFA.
6745 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6746 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6750 /* Load the address of the MIPS16 function into $25. Do this
6751 first so that targets with coprocessor interlocks can use
6752 an MFC1 to fill the delay slot. */
6753 if (TARGET_EXPLICIT_RELOCS
)
6755 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6756 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6759 output_asm_insn ("la\t%^,%0", &fn
);
6762 /* Move the arguments from general registers to floating-point
6764 mips_output_args_xfer (fp_code
, 't');
6768 /* Save the return address in $18 and call the non-MIPS16 function.
6769 The stub's caller knows that $18 might be clobbered, even though
6770 $18 is usually a call-saved register. */
6771 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6772 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6773 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6774 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6776 /* Move the result from floating-point registers to
6777 general registers. */
6778 switch (GET_MODE (retval
))
6781 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6783 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6785 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6786 TARGET_LITTLE_ENDIAN
6787 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6789 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6791 /* On 64-bit targets, complex floats are returned in
6792 a single GPR, such that "sd" on a suitably-aligned
6793 target would store the value correctly. */
6794 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6795 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6796 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6797 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6798 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6799 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6800 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6801 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6802 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6803 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6804 reg_names
[GP_RETURN
],
6805 reg_names
[GP_RETURN
],
6806 reg_names
[GP_RETURN
+ 1]);
6811 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6815 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6816 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6820 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6826 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6827 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6831 /* Jump to the previously-loaded address. */
6832 output_asm_insn ("jr\t%^", NULL
);
6835 #ifdef ASM_DECLARE_FUNCTION_SIZE
6836 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6839 mips_end_function_definition (stubname
);
6841 /* Record this stub. */
6842 l
= XNEW (struct mips16_stub
);
6843 l
->name
= xstrdup (fnname
);
6844 l
->fp_ret_p
= fp_ret_p
;
6845 l
->next
= mips16_stubs
;
6849 /* If we expect a floating-point return value, but we've built a
6850 stub which does not expect one, then we're in trouble. We can't
6851 use the existing stub, because it won't handle the floating-point
6852 value. We can't build a new stub, because the linker won't know
6853 which stub to use for the various calls in this object file.
6854 Fortunately, this case is illegal, since it means that a function
6855 was declared in two different ways in a single compilation. */
6856 if (fp_ret_p
&& !l
->fp_ret_p
)
6857 error ("cannot handle inconsistent calls to %qs", fnname
);
6859 if (retval
== NULL_RTX
)
6860 insn
= gen_call_internal_direct (fn
, args_size
);
6862 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6863 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6865 /* If we are calling a stub which handles a floating-point return
6866 value, we need to arrange to save $18 in the prologue. We do this
6867 by marking the function call as using the register. The prologue
6868 will later see that it is used, and emit code to save it. */
6870 CALL_INSN_FUNCTION_USAGE (insn
) =
6871 gen_rtx_EXPR_LIST (VOIDmode
,
6872 gen_rtx_CLOBBER (VOIDmode
,
6873 gen_rtx_REG (word_mode
, 18)),
6874 CALL_INSN_FUNCTION_USAGE (insn
));
6879 /* Expand a call of type TYPE. RESULT is where the result will go (null
6880 for "call"s and "sibcall"s), ADDR is the address of the function,
6881 ARGS_SIZE is the size of the arguments and AUX is the value passed
6882 to us by mips_function_arg. LAZY_P is true if this call already
6883 involves a lazily-bound function address (such as when calling
6884 functions through a MIPS16 hard-float stub).
6886 Return the call itself. */
6889 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6890 rtx args_size
, rtx aux
, bool lazy_p
)
6892 rtx orig_addr
, pattern
, insn
;
6895 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6896 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6899 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6904 if (!call_insn_operand (addr
, VOIDmode
))
6906 if (type
== MIPS_CALL_EPILOGUE
)
6907 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6909 addr
= gen_reg_rtx (Pmode
);
6910 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6915 rtx (*fn
) (rtx
, rtx
);
6917 if (type
== MIPS_CALL_SIBCALL
)
6918 fn
= gen_sibcall_internal
;
6920 fn
= gen_call_internal
;
6922 pattern
= fn (addr
, args_size
);
6924 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6926 /* Handle return values created by mips_return_fpr_pair. */
6927 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6930 if (type
== MIPS_CALL_SIBCALL
)
6931 fn
= gen_sibcall_value_multiple_internal
;
6933 fn
= gen_call_value_multiple_internal
;
6935 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6936 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6937 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6941 rtx (*fn
) (rtx
, rtx
, rtx
);
6943 if (type
== MIPS_CALL_SIBCALL
)
6944 fn
= gen_sibcall_value_internal
;
6946 fn
= gen_call_value_internal
;
6948 /* Handle return values created by mips_return_fpr_single. */
6949 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6950 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6951 pattern
= fn (result
, addr
, args_size
);
6954 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6957 /* Split call instruction INSN into a $gp-clobbering call and
6958 (where necessary) an instruction to restore $gp from its save slot.
6959 CALL_PATTERN is the pattern of the new call. */
6962 mips_split_call (rtx insn
, rtx call_pattern
)
6964 emit_call_insn (call_pattern
);
6965 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6966 /* Pick a temporary register that is suitable for both MIPS16 and
6967 non-MIPS16 code. $4 and $5 are used for returning complex double
6968 values in soft-float code, so $6 is the first suitable candidate. */
6969 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6972 /* Return true if a call to DECL may need to use JALX. */
6975 mips_call_may_need_jalx_p (tree decl
)
6977 /* If the current translation unit would use a different mode for DECL,
6978 assume that the call needs JALX. */
6979 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
6982 /* mips_get_compress_mode is always accurate for locally-binding
6983 functions in the current translation unit. */
6984 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
6987 /* When -minterlink-compressed is in effect, assume that functions
6988 could use a different encoding mode unless an attribute explicitly
6989 tells us otherwise. */
6990 if (TARGET_INTERLINK_COMPRESSED
)
6992 if (!TARGET_COMPRESSION
6993 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
6995 if (TARGET_COMPRESSION
6996 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7003 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7006 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7008 if (!TARGET_SIBCALLS
)
7011 /* Interrupt handlers need special epilogue code and therefore can't
7013 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7016 /* Direct Js are only possible to functions that use the same ISA encoding.
7017 There is no JX counterpoart of JALX. */
7019 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7020 && mips_call_may_need_jalx_p (decl
))
7023 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7024 require $gp to be valid on entry, so sibcalls can only use stubs
7025 if $gp is call-clobbered. */
7027 && TARGET_CALL_SAVED_GP
7028 && !TARGET_ABICALLS_PIC0
7029 && !targetm
.binds_local_p (decl
))
7036 /* Emit code to move general operand SRC into condition-code
7037 register DEST given that SCRATCH is a scratch TFmode FPR.
7044 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7047 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7051 /* Change the source to SFmode. */
7053 src
= adjust_address (src
, SFmode
, 0);
7054 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7055 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7057 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7058 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7060 mips_emit_move (copy_rtx (fp1
), src
);
7061 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7062 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7065 /* Implement MOVE_BY_PIECES_P. */
7068 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7072 /* movmemsi is meant to generate code that is at least as good as
7073 move_by_pieces. However, movmemsi effectively uses a by-pieces
7074 implementation both for moves smaller than a word and for
7075 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7076 bytes. We should allow the tree-level optimisers to do such
7077 moves by pieces, as it often exposes other optimization
7078 opportunities. We might as well continue to use movmemsi at
7079 the rtl level though, as it produces better code when
7080 scheduling is disabled (such as at -O). */
7081 if (currently_expanding_to_rtl
)
7083 if (align
< BITS_PER_WORD
)
7084 return size
< UNITS_PER_WORD
;
7085 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7087 /* The default value. If this becomes a target hook, we should
7088 call the default definition instead. */
7089 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7090 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7093 /* Implement STORE_BY_PIECES_P. */
7096 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7098 /* Storing by pieces involves moving constants into registers
7099 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7100 We need to decide whether it is cheaper to load the address of
7101 constant data into a register and use a block move instead. */
7103 /* If the data is only byte aligned, then:
7105 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7106 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7109 (a2) A block move of 4 bytes from aligned source data can use an
7110 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7111 4 SBs that we would generate when storing by pieces. */
7112 if (align
<= BITS_PER_UNIT
)
7115 /* If the data is 2-byte aligned, then:
7117 (b1) A block move of less than 4 bytes would use a combination of LBs,
7118 LHs, SBs and SHs. We get better code by using single-instruction
7119 LIs, SBs and SHs instead.
7121 (b2) A block move of 4 bytes from aligned source data would again use
7122 an LW/SWL/SWR sequence. In most cases, loading the address of
7123 the source data would require at least one extra instruction.
7124 It is often more efficient to use 2 single-instruction LIs and
7127 (b3) A block move of up to 3 additional bytes would be like (b1).
7129 (b4) A block move of 8 bytes from aligned source data can use two
7130 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7131 sequences are better than the 4 LIs and 4 SHs that we'd generate
7132 when storing by pieces.
7134 The reasoning for higher alignments is similar:
7136 (c1) A block move of less than 4 bytes would be the same as (b1).
7138 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7139 loading the address of the source data would typically require
7140 at least one extra instruction. It is generally better to use
7143 (c3) A block move of up to 3 additional bytes would be like (b1).
7145 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7146 LD/SD sequence, and in these cases we've traditionally preferred
7147 the memory copy over the more bulky constant moves. */
7151 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7152 Assume that the areas do not overlap. */
7155 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7157 HOST_WIDE_INT offset
, delta
;
7158 unsigned HOST_WIDE_INT bits
;
7160 enum machine_mode mode
;
7163 /* Work out how many bits to move at a time. If both operands have
7164 half-word alignment, it is usually better to move in half words.
7165 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7166 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7167 Otherwise move word-sized chunks. */
7168 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7169 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7170 bits
= BITS_PER_WORD
/ 2;
7172 bits
= BITS_PER_WORD
;
7174 mode
= mode_for_size (bits
, MODE_INT
, 0);
7175 delta
= bits
/ BITS_PER_UNIT
;
7177 /* Allocate a buffer for the temporary registers. */
7178 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7180 /* Load as many BITS-sized chunks as possible. Use a normal load if
7181 the source has enough alignment, otherwise use left/right pairs. */
7182 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7184 regs
[i
] = gen_reg_rtx (mode
);
7185 if (MEM_ALIGN (src
) >= bits
)
7186 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7189 rtx part
= adjust_address (src
, BLKmode
, offset
);
7190 set_mem_size (part
, delta
);
7191 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7196 /* Copy the chunks to the destination. */
7197 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7198 if (MEM_ALIGN (dest
) >= bits
)
7199 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7202 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7203 set_mem_size (part
, delta
);
7204 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7208 /* Mop up any left-over bytes. */
7209 if (offset
< length
)
7211 src
= adjust_address (src
, BLKmode
, offset
);
7212 dest
= adjust_address (dest
, BLKmode
, offset
);
7213 move_by_pieces (dest
, src
, length
- offset
,
7214 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7218 /* Helper function for doing a loop-based block operation on memory
7219 reference MEM. Each iteration of the loop will operate on LENGTH
7222 Create a new base register for use within the loop and point it to
7223 the start of MEM. Create a new memory reference that uses this
7224 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7227 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7228 rtx
*loop_reg
, rtx
*loop_mem
)
7230 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7232 /* Although the new mem does not refer to a known location,
7233 it does keep up to LENGTH bytes of alignment. */
7234 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7235 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7238 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7239 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7240 the memory regions do not overlap. */
7243 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7244 HOST_WIDE_INT bytes_per_iter
)
7246 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7247 HOST_WIDE_INT leftover
;
7249 leftover
= length
% bytes_per_iter
;
7252 /* Create registers and memory references for use within the loop. */
7253 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7254 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7256 /* Calculate the value that SRC_REG should have after the last iteration
7258 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7261 /* Emit the start of the loop. */
7262 label
= gen_label_rtx ();
7265 /* Emit the loop body. */
7266 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7268 /* Move on to the next block. */
7269 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7270 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7272 /* Emit the loop condition. */
7273 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7274 if (Pmode
== DImode
)
7275 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7277 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7279 /* Mop up any left-over bytes. */
7281 mips_block_move_straight (dest
, src
, leftover
);
7284 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7285 memory reference SRC to memory reference DEST. */
7288 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7290 if (CONST_INT_P (length
))
7292 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7294 mips_block_move_straight (dest
, src
, INTVAL (length
));
7299 mips_block_move_loop (dest
, src
, INTVAL (length
),
7300 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7307 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7310 mips_expand_synci_loop (rtx begin
, rtx end
)
7312 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7314 /* Create end_label. */
7315 end_label
= gen_label_rtx ();
7317 /* Check if begin equals end. */
7318 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7319 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7321 /* Load INC with the cache line size (rdhwr INC,$1). */
7322 inc
= gen_reg_rtx (Pmode
);
7323 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7325 /* Check if inc is 0. */
7326 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7327 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7329 /* Calculate mask. */
7330 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7332 /* Mask out begin by mask. */
7333 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7335 /* Calculate length. */
7336 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7338 /* Loop back to here. */
7339 label
= gen_label_rtx ();
7342 emit_insn (gen_synci (begin
));
7344 /* Update length. */
7345 mips_emit_binary (MINUS
, length
, length
, inc
);
7348 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7350 /* Check if length is greater than 0. */
7351 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7352 emit_jump_insn (gen_condjump (cmp_result
, label
));
7354 emit_label (end_label
);
7357 /* Expand a QI or HI mode atomic memory operation.
7359 GENERATOR contains a pointer to the gen_* function that generates
7360 the SI mode underlying atomic operation using masks that we
7363 RESULT is the return register for the operation. Its value is NULL
7366 MEM is the location of the atomic access.
7368 OLDVAL is the first operand for the operation.
7370 NEWVAL is the optional second operand for the operation. Its value
7371 is NULL if unused. */
7374 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7375 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7377 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7378 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7380 enum machine_mode mode
;
7382 mode
= GET_MODE (mem
);
7384 /* Compute the address of the containing SImode value. */
7385 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7386 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7387 force_reg (Pmode
, GEN_INT (-4)));
7389 /* Create a memory reference for it. */
7390 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7391 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7392 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7394 /* Work out the byte offset of the QImode or HImode value,
7395 counting from the least significant byte. */
7396 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7397 if (TARGET_BIG_ENDIAN
)
7398 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7400 /* Multiply by eight to convert the shift value from bytes to bits. */
7401 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7403 /* Make the final shift an SImode value, so that it can be used in
7404 SImode operations. */
7405 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7407 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7408 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7409 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7410 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7412 /* Compute the equivalent exclusive mask. */
7413 inverted_mask
= gen_reg_rtx (SImode
);
7414 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7415 gen_rtx_NOT (SImode
, mask
)));
7417 /* Shift the old value into place. */
7418 if (oldval
!= const0_rtx
)
7420 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7421 oldval
= force_reg (SImode
, oldval
);
7422 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7425 /* Do the same for the new value. */
7426 if (newval
&& newval
!= const0_rtx
)
7428 newval
= convert_modes (SImode
, mode
, newval
, true);
7429 newval
= force_reg (SImode
, newval
);
7430 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7433 /* Do the SImode atomic access. */
7435 res
= gen_reg_rtx (SImode
);
7437 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7439 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7441 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7447 /* Shift and convert the result. */
7448 mips_emit_binary (AND
, res
, res
, mask
);
7449 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7450 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7454 /* Return true if it is possible to use left/right accesses for a
7455 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7456 When returning true, update *LEFT and *RIGHT as follows:
7458 *LEFT is a QImode reference to the first byte if big endian or
7459 the last byte if little endian. This address can be used in the
7460 left-side instructions (LWL, SWL, LDL, SDL).
7462 *RIGHT is a QImode reference to the opposite end of the field and
7463 can be used in the patterning right-side instruction. */
7466 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7467 rtx
*left
, rtx
*right
)
7471 /* Check that the size is valid. */
7472 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7475 /* We can only access byte-aligned values. Since we are always passed
7476 a reference to the first byte of the field, it is not necessary to
7477 do anything with BITPOS after this check. */
7478 if (bitpos
% BITS_PER_UNIT
!= 0)
7481 /* Reject aligned bitfields: we want to use a normal load or store
7482 instead of a left/right pair. */
7483 if (MEM_ALIGN (op
) >= width
)
7486 /* Get references to both ends of the field. */
7487 first
= adjust_address (op
, QImode
, 0);
7488 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7490 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7491 correspond to the MSB and RIGHT to the LSB. */
7492 if (TARGET_BIG_ENDIAN
)
7493 *left
= first
, *right
= last
;
7495 *left
= last
, *right
= first
;
7500 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7501 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7502 the operation is the equivalent of:
7504 (set DEST (*_extract SRC WIDTH BITPOS))
7506 Return true on success. */
7509 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7510 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7512 rtx left
, right
, temp
;
7513 rtx dest1
= NULL_RTX
;
7515 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7516 be a DImode, create a new temp and emit a zero extend at the end. */
7517 if (GET_MODE (dest
) == DImode
7519 && GET_MODE_BITSIZE (SImode
) == width
)
7522 dest
= gen_reg_rtx (SImode
);
7525 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7528 temp
= gen_reg_rtx (GET_MODE (dest
));
7529 if (GET_MODE (dest
) == DImode
)
7531 emit_insn (gen_mov_ldl (temp
, src
, left
));
7532 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7536 emit_insn (gen_mov_lwl (temp
, src
, left
));
7537 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7540 /* If we were loading 32bits and the original register was DI then
7541 sign/zero extend into the orignal dest. */
7545 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7547 emit_insn (gen_extendsidi2 (dest1
, dest
));
7552 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7553 BITPOS and SRC are the operands passed to the expander; the operation
7554 is the equivalent of:
7556 (set (zero_extract DEST WIDTH BITPOS) SRC)
7558 Return true on success. */
7561 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7562 HOST_WIDE_INT bitpos
)
7565 enum machine_mode mode
;
7567 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7570 mode
= mode_for_size (width
, MODE_INT
, 0);
7571 src
= gen_lowpart (mode
, src
);
7574 emit_insn (gen_mov_sdl (dest
, src
, left
));
7575 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7579 emit_insn (gen_mov_swl (dest
, src
, left
));
7580 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7585 /* Return true if X is a MEM with the same size as MODE. */
7588 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7591 && MEM_SIZE_KNOWN_P (x
)
7592 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7595 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7596 source of an "ext" instruction or the destination of an "ins"
7597 instruction. OP must be a register operand and the following
7598 conditions must hold:
7600 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7601 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7602 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7604 Also reject lengths equal to a word as they are better handled
7605 by the move patterns. */
7608 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7610 if (!ISA_HAS_EXT_INS
7611 || !register_operand (op
, VOIDmode
)
7612 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7615 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7618 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7624 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7625 operation if MAXLEN is the maxium length of consecutive bits that
7626 can make up MASK. MODE is the mode of the operation. See
7627 mask_low_and_shift_len for the actual definition. */
7630 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7632 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7635 /* Return true iff OP1 and OP2 are valid operands together for the
7636 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7637 see the table in the comment before the pattern. */
7640 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7642 return (memory_operand (op1
, mode
)
7643 ? and_load_operand (op2
, mode
)
7644 : and_reg_operand (op2
, mode
));
7647 /* The canonical form of a mask-low-and-shift-left operation is
7648 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7649 cleared. Thus we need to shift MASK to the right before checking if it
7650 is a valid mask value. MODE is the mode of the operation. If true
7651 return the length of the mask, otherwise return -1. */
7654 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7656 HOST_WIDE_INT shval
;
7658 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7659 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7662 /* Return true if -msplit-addresses is selected and should be honored.
7664 -msplit-addresses is a half-way house between explicit relocations
7665 and the traditional assembler macros. It can split absolute 32-bit
7666 symbolic constants into a high/lo_sum pair but uses macros for other
7669 Like explicit relocation support for REL targets, it relies
7670 on GNU extensions in the assembler and the linker.
7672 Although this code should work for -O0, it has traditionally
7673 been treated as an optimization. */
7676 mips_split_addresses_p (void)
7678 return (TARGET_SPLIT_ADDRESSES
7682 && !ABI_HAS_64BIT_SYMBOLS
);
7685 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7688 mips_init_relocs (void)
7690 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7691 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7692 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7693 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7694 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7696 if (TARGET_MIPS16_PCREL_LOADS
)
7697 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7700 if (ABI_HAS_64BIT_SYMBOLS
)
7702 if (TARGET_EXPLICIT_RELOCS
)
7704 mips_split_p
[SYMBOL_64_HIGH
] = true;
7705 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7706 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7708 mips_split_p
[SYMBOL_64_MID
] = true;
7709 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7710 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7712 mips_split_p
[SYMBOL_64_LOW
] = true;
7713 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7714 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7716 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7717 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7722 if (TARGET_EXPLICIT_RELOCS
7723 || mips_split_addresses_p ()
7726 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7727 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7728 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7735 /* The high part is provided by a pseudo copy of $gp. */
7736 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7737 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7739 else if (TARGET_EXPLICIT_RELOCS
)
7740 /* Small data constants are kept whole until after reload,
7741 then lowered by mips_rewrite_small_data. */
7742 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7744 if (TARGET_EXPLICIT_RELOCS
)
7746 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7749 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7750 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7754 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7755 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7758 /* Expose the use of $28 as soon as possible. */
7759 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7763 /* The HIGH and LO_SUM are matched by special .md patterns. */
7764 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7766 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7767 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7768 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7770 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7771 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7772 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7777 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7779 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7780 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7782 /* Expose the use of $28 as soon as possible. */
7783 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7789 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7790 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7791 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7794 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7795 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7797 if (TARGET_MIPS16_PCREL_LOADS
)
7799 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7800 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7804 mips_split_p
[SYMBOL_DTPREL
] = true;
7805 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7806 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7808 mips_split_p
[SYMBOL_TPREL
] = true;
7809 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7810 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7813 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7814 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7817 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7818 in context CONTEXT. RELOCS is the array of relocations to use. */
7821 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7822 const char **relocs
)
7824 enum mips_symbol_type symbol_type
;
7827 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7828 gcc_assert (relocs
[symbol_type
]);
7830 fputs (relocs
[symbol_type
], file
);
7831 output_addr_const (file
, mips_strip_unspec_address (op
));
7832 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7837 /* Start a new block with the given asm switch enabled. If we need
7838 to print a directive, emit PREFIX before it and SUFFIX after it. */
7841 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7842 const char *prefix
, const char *suffix
)
7844 if (asm_switch
->nesting_level
== 0)
7845 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7846 asm_switch
->nesting_level
++;
7849 /* Likewise, but end a block. */
7852 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7853 const char *prefix
, const char *suffix
)
7855 gcc_assert (asm_switch
->nesting_level
);
7856 asm_switch
->nesting_level
--;
7857 if (asm_switch
->nesting_level
== 0)
7858 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7861 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7862 that either print a complete line or print nothing. */
7865 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7867 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7871 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7873 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7876 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7877 The punctuation characters are:
7879 '(' Start a nested ".set noreorder" block.
7880 ')' End a nested ".set noreorder" block.
7881 '[' Start a nested ".set noat" block.
7882 ']' End a nested ".set noat" block.
7883 '<' Start a nested ".set nomacro" block.
7884 '>' End a nested ".set nomacro" block.
7885 '*' Behave like %(%< if generating a delayed-branch sequence.
7886 '#' Print a nop if in a ".set noreorder" block.
7887 '/' Like '#', but do nothing within a delayed-branch sequence.
7888 '?' Print "l" if mips_branch_likely is true
7889 '~' Print a nop if mips_branch_likely is true
7890 '.' Print the name of the register with a hard-wired zero (zero or $0).
7891 '@' Print the name of the assembler temporary register (at or $1).
7892 '^' Print the name of the pic call-through register (t9 or $25).
7893 '+' Print the name of the gp register (usually gp or $28).
7894 '$' Print the name of the stack pointer register (sp or $29).
7895 ':' Print "c" to use the compact version if the delay slot is a nop.
7896 '!' Print "s" to use the short version if the delay slot contains a
7899 See also mips_init_print_operand_pucnt. */
7902 mips_print_operand_punctuation (FILE *file
, int ch
)
7907 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7911 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7915 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7919 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7923 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7927 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7931 if (final_sequence
!= 0)
7933 mips_print_operand_punctuation (file
, '(');
7934 mips_print_operand_punctuation (file
, '<');
7939 if (mips_noreorder
.nesting_level
> 0)
7940 fputs ("\n\tnop", file
);
7944 /* Print an extra newline so that the delayed insn is separated
7945 from the following ones. This looks neater and is consistent
7946 with non-nop delayed sequences. */
7947 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7948 fputs ("\n\tnop\n", file
);
7952 if (mips_branch_likely
)
7957 if (mips_branch_likely
)
7958 fputs ("\n\tnop", file
);
7962 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7966 fputs (reg_names
[AT_REGNUM
], file
);
7970 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7974 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7978 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7982 /* When final_sequence is 0, the delay slot will be a nop. We can
7983 use the compact version for microMIPS. */
7984 if (final_sequence
== 0)
7989 /* If the delay slot instruction is short, then use the
7991 if (final_sequence
== 0
7992 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8002 /* Initialize mips_print_operand_punct. */
8005 mips_init_print_operand_punct (void)
8009 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8010 mips_print_operand_punct
[(unsigned char) *p
] = true;
8013 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8014 associated with condition CODE. Print the condition part of the
8018 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8032 /* Conveniently, the MIPS names for these conditions are the same
8033 as their RTL equivalents. */
8034 fputs (GET_RTX_NAME (code
), file
);
8038 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8043 /* Likewise floating-point branches. */
8046 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8051 fputs ("c1f", file
);
8055 fputs ("c1t", file
);
8059 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8064 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8067 mips_print_operand_punct_valid_p (unsigned char code
)
8069 return mips_print_operand_punct
[code
];
8072 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8074 'X' Print CONST_INT OP in hexadecimal format.
8075 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8076 'd' Print CONST_INT OP in decimal.
8077 'm' Print one less than CONST_INT OP in decimal.
8078 'h' Print the high-part relocation associated with OP, after stripping
8080 'R' Print the low-part relocation associated with OP.
8081 'C' Print the integer branch condition for comparison OP.
8082 'N' Print the inverse of the integer branch condition for comparison OP.
8083 'F' Print the FPU branch condition for comparison OP.
8084 'W' Print the inverse of the FPU branch condition for comparison OP.
8085 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8086 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8087 't' Like 'T', but with the EQ/NE cases reversed
8088 'Y' Print mips_fp_conditions[INTVAL (OP)]
8089 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8090 'q' Print a DSP accumulator register.
8091 'D' Print the second part of a double-word register or memory operand.
8092 'L' Print the low-order register in a double-word register operand.
8093 'M' Print high-order register in a double-word register operand.
8094 'z' Print $0 if OP is zero, otherwise print OP normally.
8095 'b' Print the address of a memory operand, without offset. */
8098 mips_print_operand (FILE *file
, rtx op
, int letter
)
8102 if (mips_print_operand_punct_valid_p (letter
))
8104 mips_print_operand_punctuation (file
, letter
);
8109 code
= GET_CODE (op
);
8114 if (CONST_INT_P (op
))
8115 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8117 output_operand_lossage ("invalid use of '%%%c'", letter
);
8121 if (CONST_INT_P (op
))
8122 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8124 output_operand_lossage ("invalid use of '%%%c'", letter
);
8128 if (CONST_INT_P (op
))
8129 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8131 output_operand_lossage ("invalid use of '%%%c'", letter
);
8135 if (CONST_INT_P (op
))
8136 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8138 output_operand_lossage ("invalid use of '%%%c'", letter
);
8144 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8148 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8152 mips_print_int_branch_condition (file
, code
, letter
);
8156 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8160 mips_print_float_branch_condition (file
, code
, letter
);
8164 mips_print_float_branch_condition (file
, reverse_condition (code
),
8171 int truth
= (code
== NE
) == (letter
== 'T');
8172 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
8177 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8178 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8180 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8187 mips_print_operand (file
, op
, 0);
8193 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8194 fprintf (file
, "$ac0");
8195 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8196 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8198 output_operand_lossage ("invalid use of '%%%c'", letter
);
8206 unsigned int regno
= REGNO (op
);
8207 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8208 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8211 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8212 output_operand_lossage ("invalid use of '%%%c'", letter
);
8213 /* We need to print $0 .. $31 for COP0 registers. */
8214 if (COP0_REG_P (regno
))
8215 fprintf (file
, "$%s", ®_names
[regno
][4]);
8217 fprintf (file
, "%s", reg_names
[regno
]);
8223 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8224 else if (letter
== 'b')
8226 gcc_assert (REG_P (XEXP (op
, 0)));
8227 mips_print_operand (file
, XEXP (op
, 0), 0);
8229 else if (letter
&& letter
!= 'z')
8230 output_operand_lossage ("invalid use of '%%%c'", letter
);
8232 output_address (XEXP (op
, 0));
8236 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8237 fputs (reg_names
[GP_REG_FIRST
], file
);
8238 else if (letter
&& letter
!= 'z')
8239 output_operand_lossage ("invalid use of '%%%c'", letter
);
8240 else if (CONST_GP_P (op
))
8241 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8243 output_addr_const (file
, mips_strip_unspec_address (op
));
8249 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8252 mips_print_operand_address (FILE *file
, rtx x
)
8254 struct mips_address_info addr
;
8256 if (mips_classify_address (&addr
, x
, word_mode
, true))
8260 mips_print_operand (file
, addr
.offset
, 0);
8261 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8264 case ADDRESS_LO_SUM
:
8265 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8267 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8270 case ADDRESS_CONST_INT
:
8271 output_addr_const (file
, x
);
8272 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8275 case ADDRESS_SYMBOLIC
:
8276 output_addr_const (file
, mips_strip_unspec_address (x
));
8282 /* Implement TARGET_ENCODE_SECTION_INFO. */
8285 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8287 default_encode_section_info (decl
, rtl
, first
);
8289 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8291 rtx symbol
= XEXP (rtl
, 0);
8292 tree type
= TREE_TYPE (decl
);
8294 /* Encode whether the symbol is short or long. */
8295 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8296 || mips_far_type_p (type
))
8297 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8301 /* Implement TARGET_SELECT_RTX_SECTION. */
8304 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8305 unsigned HOST_WIDE_INT align
)
8307 /* ??? Consider using mergeable small data sections. */
8308 if (mips_rtx_constant_in_small_data_p (mode
))
8309 return get_named_section (NULL
, ".sdata", 0);
8311 return default_elf_select_rtx_section (mode
, x
, align
);
8314 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8316 The complication here is that, with the combination TARGET_ABICALLS
8317 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8318 absolute addresses, and should therefore not be included in the
8319 read-only part of a DSO. Handle such cases by selecting a normal
8320 data section instead of a read-only one. The logic apes that in
8321 default_function_rodata_section. */
8324 mips_function_rodata_section (tree decl
)
8326 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8327 return default_function_rodata_section (decl
);
8329 if (decl
&& DECL_SECTION_NAME (decl
))
8331 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8332 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8334 char *rname
= ASTRDUP (name
);
8336 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8338 else if (flag_function_sections
8339 && flag_data_sections
8340 && strncmp (name
, ".text.", 6) == 0)
8342 char *rname
= ASTRDUP (name
);
8343 memcpy (rname
+ 1, "data", 4);
8344 return get_section (rname
, SECTION_WRITE
, decl
);
8347 return data_section
;
8350 /* Implement TARGET_IN_SMALL_DATA_P. */
8353 mips_in_small_data_p (const_tree decl
)
8355 unsigned HOST_WIDE_INT size
;
8357 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8360 /* We don't yet generate small-data references for -mabicalls
8361 or VxWorks RTP code. See the related -G handling in
8362 mips_option_override. */
8363 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8366 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8370 /* Reject anything that isn't in a known small-data section. */
8371 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8372 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8375 /* If a symbol is defined externally, the assembler will use the
8376 usual -G rules when deciding how to implement macros. */
8377 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8380 else if (TARGET_EMBEDDED_DATA
)
8382 /* Don't put constants into the small data section: we want them
8383 to be in ROM rather than RAM. */
8384 if (TREE_CODE (decl
) != VAR_DECL
)
8387 if (TREE_READONLY (decl
)
8388 && !TREE_SIDE_EFFECTS (decl
)
8389 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8393 /* Enforce -mlocal-sdata. */
8394 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8397 /* Enforce -mextern-sdata. */
8398 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8400 if (DECL_EXTERNAL (decl
))
8402 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8406 /* We have traditionally not treated zero-sized objects as small data,
8407 so this is now effectively part of the ABI. */
8408 size
= int_size_in_bytes (TREE_TYPE (decl
));
8409 return size
> 0 && size
<= mips_small_data_threshold
;
8412 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8413 anchors for small data: the GP register acts as an anchor in that
8414 case. We also don't want to use them for PC-relative accesses,
8415 where the PC acts as an anchor. */
8418 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8420 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8422 case SYMBOL_PC_RELATIVE
:
8423 case SYMBOL_GP_RELATIVE
:
8427 return default_use_anchors_for_symbol_p (symbol
);
8431 /* The MIPS debug format wants all automatic variables and arguments
8432 to be in terms of the virtual frame pointer (stack pointer before
8433 any adjustment in the function), while the MIPS 3.0 linker wants
8434 the frame pointer to be the stack pointer after the initial
8435 adjustment. So, we do the adjustment here. The arg pointer (which
8436 is eliminated) points to the virtual frame pointer, while the frame
8437 pointer (which may be eliminated) points to the stack pointer after
8438 the initial adjustments. */
8441 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8443 rtx offset2
= const0_rtx
;
8444 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8447 offset
= INTVAL (offset2
);
8449 if (reg
== stack_pointer_rtx
8450 || reg
== frame_pointer_rtx
8451 || reg
== hard_frame_pointer_rtx
)
8453 offset
-= cfun
->machine
->frame
.total_size
;
8454 if (reg
== hard_frame_pointer_rtx
)
8455 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8461 /* Implement ASM_OUTPUT_EXTERNAL. */
8464 mips_output_external (FILE *file
, tree decl
, const char *name
)
8466 default_elf_asm_output_external (file
, decl
, name
);
8468 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8469 set in order to avoid putting out names that are never really
8471 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8473 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8475 /* When using assembler macros, emit .extern directives for
8476 all small-data externs so that the assembler knows how
8479 In most cases it would be safe (though pointless) to emit
8480 .externs for other symbols too. One exception is when an
8481 object is within the -G limit but declared by the user to
8482 be in a section other than .sbss or .sdata. */
8483 fputs ("\t.extern\t", file
);
8484 assemble_name (file
, name
);
8485 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8486 int_size_in_bytes (TREE_TYPE (decl
)));
8491 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8494 mips_output_filename (FILE *stream
, const char *name
)
8496 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8498 if (write_symbols
== DWARF2_DEBUG
)
8500 else if (mips_output_filename_first_time
)
8502 mips_output_filename_first_time
= 0;
8503 num_source_filenames
+= 1;
8504 current_function_file
= name
;
8505 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8506 output_quoted_string (stream
, name
);
8507 putc ('\n', stream
);
8509 /* If we are emitting stabs, let dbxout.c handle this (except for
8510 the mips_output_filename_first_time case). */
8511 else if (write_symbols
== DBX_DEBUG
)
8513 else if (name
!= current_function_file
8514 && strcmp (name
, current_function_file
) != 0)
8516 num_source_filenames
+= 1;
8517 current_function_file
= name
;
8518 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8519 output_quoted_string (stream
, name
);
8520 putc ('\n', stream
);
8524 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8526 static void ATTRIBUTE_UNUSED
8527 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8532 fputs ("\t.dtprelword\t", file
);
8536 fputs ("\t.dtpreldword\t", file
);
8542 output_addr_const (file
, x
);
8543 fputs ("+0x8000", file
);
8546 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8549 mips_dwarf_register_span (rtx reg
)
8552 enum machine_mode mode
;
8554 /* By default, GCC maps increasing register numbers to increasing
8555 memory locations, but paired FPRs are always little-endian,
8556 regardless of the prevailing endianness. */
8557 mode
= GET_MODE (reg
);
8558 if (FP_REG_P (REGNO (reg
))
8559 && TARGET_BIG_ENDIAN
8560 && MAX_FPRS_PER_FMT
> 1
8561 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8563 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8564 high
= mips_subword (reg
, true);
8565 low
= mips_subword (reg
, false);
8566 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8572 /* DSP ALU can bypass data with no delays for the following pairs. */
8573 enum insn_code dspalu_bypass_table
[][2] =
8575 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8576 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8577 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8578 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8579 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8580 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8581 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8582 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8586 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8589 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8590 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8591 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8593 for (i
= 0; i
< num_bypass
; i
++)
8595 if (out_icode
== dspalu_bypass_table
[i
][0]
8596 && in_icode
== dspalu_bypass_table
[i
][1])
8602 /* Implement ASM_OUTPUT_ASCII. */
8605 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8611 fprintf (stream
, "\t.ascii\t\"");
8612 for (i
= 0; i
< len
; i
++)
8616 c
= (unsigned char) string
[i
];
8619 if (c
== '\\' || c
== '\"')
8621 putc ('\\', stream
);
8629 fprintf (stream
, "\\%03o", c
);
8633 if (cur_pos
> 72 && i
+1 < len
)
8636 fprintf (stream
, "\"\n\t.ascii\t\"");
8639 fprintf (stream
, "\"\n");
8642 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8643 Update *ADDR with the operand that should be printed. */
8646 mips_output_tls_reloc_directive (rtx
*addr
)
8648 enum mips_symbol_type type
;
8650 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8651 *addr
= mips_strip_unspec_address (*addr
);
8655 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8658 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8665 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8666 macros, mark the symbol as written so that mips_asm_output_external
8667 won't emit an .extern for it. STREAM is the output file, NAME is the
8668 name of the symbol, INIT_STRING is the string that should be written
8669 before the symbol and FINAL_STRING is the string that should be
8670 written after it. FINAL_STRING is a printf format that consumes the
8671 remaining arguments. */
8674 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8675 const char *final_string
, ...)
8679 fputs (init_string
, stream
);
8680 assemble_name (stream
, name
);
8681 va_start (ap
, final_string
);
8682 vfprintf (stream
, final_string
, ap
);
8685 if (!TARGET_EXPLICIT_RELOCS
)
8687 tree name_tree
= get_identifier (name
);
8688 TREE_ASM_WRITTEN (name_tree
) = 1;
8692 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8693 NAME is the name of the object and ALIGN is the required alignment
8694 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8695 alignment argument. */
8698 mips_declare_common_object (FILE *stream
, const char *name
,
8699 const char *init_string
,
8700 unsigned HOST_WIDE_INT size
,
8701 unsigned int align
, bool takes_alignment_p
)
8703 if (!takes_alignment_p
)
8705 size
+= (align
/ BITS_PER_UNIT
) - 1;
8706 size
-= size
% (align
/ BITS_PER_UNIT
);
8707 mips_declare_object (stream
, name
, init_string
,
8708 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8711 mips_declare_object (stream
, name
, init_string
,
8712 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8713 size
, align
/ BITS_PER_UNIT
);
8716 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8717 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8720 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8721 unsigned HOST_WIDE_INT size
,
8724 /* If the target wants uninitialized const declarations in
8725 .rdata then don't put them in .comm. */
8726 if (TARGET_EMBEDDED_DATA
8727 && TARGET_UNINIT_CONST_IN_RODATA
8728 && TREE_CODE (decl
) == VAR_DECL
8729 && TREE_READONLY (decl
)
8730 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8732 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8733 targetm
.asm_out
.globalize_label (stream
, name
);
8735 switch_to_section (readonly_data_section
);
8736 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8737 mips_declare_object (stream
, name
, "",
8738 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8742 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8746 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8747 extern int size_directive_output
;
8749 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8750 definitions except that it uses mips_declare_object to emit the label. */
8753 mips_declare_object_name (FILE *stream
, const char *name
,
8754 tree decl ATTRIBUTE_UNUSED
)
8756 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8757 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8760 size_directive_output
= 0;
8761 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8765 size_directive_output
= 1;
8766 size
= int_size_in_bytes (TREE_TYPE (decl
));
8767 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8770 mips_declare_object (stream
, name
, "", ":\n");
8773 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8776 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8780 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8781 if (!flag_inhibit_size_directive
8782 && DECL_SIZE (decl
) != 0
8785 && DECL_INITIAL (decl
) == error_mark_node
8786 && !size_directive_output
)
8790 size_directive_output
= 1;
8791 size
= int_size_in_bytes (TREE_TYPE (decl
));
8792 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8797 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8798 with the current ABI. */
8801 mips_mdebug_abi_name (void)
8814 return TARGET_64BIT
? "eabi64" : "eabi32";
8820 /* Implement TARGET_ASM_FILE_START. */
8823 mips_file_start (void)
8825 default_file_start ();
8827 /* Generate a special section to describe the ABI switches used to
8828 produce the resultant binary. */
8830 /* Record the ABI itself. Modern versions of binutils encode
8831 this information in the ELF header flags, but GDB needs the
8832 information in order to correctly debug binaries produced by
8833 older binutils. See the function mips_gdbarch_init in
8835 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8836 mips_mdebug_abi_name ());
8838 /* There is no ELF header flag to distinguish long32 forms of the
8839 EABI from long64 forms. Emit a special section to help tools
8840 such as GDB. Do the same for o64, which is sometimes used with
8842 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8843 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8844 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8846 /* Record the NaN encoding. */
8847 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8848 fprintf (asm_out_file
, "\t.nan\t%s\n",
8849 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8851 #ifdef HAVE_AS_GNU_ATTRIBUTE
8855 /* No floating-point operations, -mno-float. */
8856 if (TARGET_NO_FLOAT
)
8858 /* Soft-float code, -msoft-float. */
8859 else if (!TARGET_HARD_FLOAT_ABI
)
8861 /* Single-float code, -msingle-float. */
8862 else if (!TARGET_DOUBLE_FLOAT
)
8864 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8865 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8867 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8871 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8875 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8876 if (TARGET_ABICALLS
)
8878 fprintf (asm_out_file
, "\t.abicalls\n");
8879 if (TARGET_ABICALLS_PIC0
)
8880 fprintf (asm_out_file
, "\t.option\tpic0\n");
8883 if (flag_verbose_asm
)
8884 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8886 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8889 /* Implement TARGET_ASM_CODE_END. */
8892 mips_code_end (void)
8894 if (mips_need_mips16_rdhwr_p
)
8895 mips_output_mips16_rdhwr ();
8898 /* Make the last instruction frame-related and note that it performs
8899 the operation described by FRAME_PATTERN. */
8902 mips_set_frame_expr (rtx frame_pattern
)
8906 insn
= get_last_insn ();
8907 RTX_FRAME_RELATED_P (insn
) = 1;
8908 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8913 /* Return a frame-related rtx that stores REG at MEM.
8914 REG must be a single register. */
8917 mips_frame_set (rtx mem
, rtx reg
)
8921 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8922 RTX_FRAME_RELATED_P (set
) = 1;
8927 /* Record that the epilogue has restored call-saved register REG. */
8930 mips_add_cfa_restore (rtx reg
)
8932 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8933 mips_epilogue
.cfa_restores
);
8936 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8937 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8938 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8939 static const unsigned char mips16e_s2_s8_regs
[] = {
8940 30, 23, 22, 21, 20, 19, 18
8942 static const unsigned char mips16e_a0_a3_regs
[] = {
8946 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8947 ordered from the uppermost in memory to the lowest in memory. */
8948 static const unsigned char mips16e_save_restore_regs
[] = {
8949 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8952 /* Return the index of the lowest X in the range [0, SIZE) for which
8953 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8956 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8961 for (i
= 0; i
< size
; i
++)
8962 if (BITSET_P (mask
, regs
[i
]))
8968 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8969 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8970 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8971 is true for all indexes (X, SIZE). */
8974 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8975 unsigned int size
, unsigned int *num_regs_ptr
)
8979 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8980 for (i
++; i
< size
; i
++)
8981 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8984 *mask_ptr
|= 1 << regs
[i
];
8988 /* Return a simplified form of X using the register values in REG_VALUES.
8989 REG_VALUES[R] is the last value assigned to hard register R, or null
8990 if R has not been modified.
8992 This function is rather limited, but is good enough for our purposes. */
8995 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8997 x
= avoid_constant_pool_reference (x
);
9001 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9002 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9003 x0
, GET_MODE (XEXP (x
, 0)));
9006 if (ARITHMETIC_P (x
))
9008 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9009 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9010 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9014 && reg_values
[REGNO (x
)]
9015 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9016 return reg_values
[REGNO (x
)];
9021 /* Return true if (set DEST SRC) stores an argument register into its
9022 caller-allocated save slot, storing the number of that argument
9023 register in *REGNO_PTR if so. REG_VALUES is as for
9024 mips16e_collect_propagate_value. */
9027 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9028 unsigned int *regno_ptr
)
9030 unsigned int argno
, regno
;
9031 HOST_WIDE_INT offset
, required_offset
;
9034 /* Check that this is a word-mode store. */
9035 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9038 /* Check that the register being saved is an unmodified argument
9040 regno
= REGNO (src
);
9041 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9043 argno
= regno
- GP_ARG_FIRST
;
9045 /* Check whether the address is an appropriate stack-pointer or
9046 frame-pointer access. */
9047 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9048 mips_split_plus (addr
, &base
, &offset
);
9049 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9050 if (base
== hard_frame_pointer_rtx
)
9051 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9052 else if (base
!= stack_pointer_rtx
)
9054 if (offset
!= required_offset
)
9061 /* A subroutine of mips_expand_prologue, called only when generating
9062 MIPS16e SAVE instructions. Search the start of the function for any
9063 instructions that save argument registers into their caller-allocated
9064 save slots. Delete such instructions and return a value N such that
9065 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9066 instructions redundant. */
9069 mips16e_collect_argument_saves (void)
9071 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9072 rtx insn
, next
, set
, dest
, src
;
9073 unsigned int nargs
, regno
;
9075 push_topmost_sequence ();
9077 memset (reg_values
, 0, sizeof (reg_values
));
9078 for (insn
= get_insns (); insn
; insn
= next
)
9080 next
= NEXT_INSN (insn
);
9081 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9087 set
= PATTERN (insn
);
9088 if (GET_CODE (set
) != SET
)
9091 dest
= SET_DEST (set
);
9092 src
= SET_SRC (set
);
9093 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9095 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9098 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9101 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9102 reg_values
[REGNO (dest
)]
9103 = mips16e_collect_propagate_value (src
, reg_values
);
9107 pop_topmost_sequence ();
9112 /* Return a move between register REGNO and memory location SP + OFFSET.
9113 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9114 Make the move a load if RESTORE_P, otherwise make it a store. */
9117 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9118 HOST_WIDE_INT offset
, unsigned int regno
)
9122 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9124 reg
= gen_rtx_REG (SImode
, regno
);
9127 mips_add_cfa_restore (reg
);
9128 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9131 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9132 return mips_frame_set (mem
, reg
);
9135 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9136 The instruction must:
9138 - Allocate or deallocate SIZE bytes in total; SIZE is known
9141 - Save or restore as many registers in *MASK_PTR as possible.
9142 The instruction saves the first registers at the top of the
9143 allocated area, with the other registers below it.
9145 - Save NARGS argument registers above the allocated area.
9147 (NARGS is always zero if RESTORE_P.)
9149 The SAVE and RESTORE instructions cannot save and restore all general
9150 registers, so there may be some registers left over for the caller to
9151 handle. Destructively modify *MASK_PTR so that it contains the registers
9152 that still need to be saved or restored. The caller can save these
9153 registers in the memory immediately below *OFFSET_PTR, which is a
9154 byte offset from the bottom of the allocated stack area. */
9157 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9158 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9162 HOST_WIDE_INT offset
, top_offset
;
9163 unsigned int i
, regno
;
9166 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9168 /* Calculate the number of elements in the PARALLEL. We need one element
9169 for the stack adjustment, one for each argument register save, and one
9170 for each additional register move. */
9172 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9173 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9176 /* Create the final PARALLEL. */
9177 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9180 /* Add the stack pointer adjustment. */
9181 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9182 plus_constant (Pmode
, stack_pointer_rtx
,
9183 restore_p
? size
: -size
));
9184 RTX_FRAME_RELATED_P (set
) = 1;
9185 XVECEXP (pattern
, 0, n
++) = set
;
9187 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9188 top_offset
= restore_p
? size
: 0;
9190 /* Save the arguments. */
9191 for (i
= 0; i
< nargs
; i
++)
9193 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9194 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9196 XVECEXP (pattern
, 0, n
++) = set
;
9199 /* Then fill in the other register moves. */
9200 offset
= top_offset
;
9201 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9203 regno
= mips16e_save_restore_regs
[i
];
9204 if (BITSET_P (*mask_ptr
, regno
))
9206 offset
-= UNITS_PER_WORD
;
9207 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9208 XVECEXP (pattern
, 0, n
++) = set
;
9209 *mask_ptr
&= ~(1 << regno
);
9213 /* Tell the caller what offset it should use for the remaining registers. */
9214 *offset_ptr
= size
+ (offset
- top_offset
);
9216 gcc_assert (n
== XVECLEN (pattern
, 0));
9221 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9222 pointer. Return true if PATTERN matches the kind of instruction
9223 generated by mips16e_build_save_restore. If INFO is nonnull,
9224 initialize it when returning true. */
9227 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9228 struct mips16e_save_restore_info
*info
)
9230 unsigned int i
, nargs
, mask
, extra
;
9231 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9232 rtx set
, reg
, mem
, base
;
9235 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9238 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9239 top_offset
= adjust
> 0 ? adjust
: 0;
9241 /* Interpret all other members of the PARALLEL. */
9242 save_offset
= top_offset
- UNITS_PER_WORD
;
9246 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9248 /* Check that we have a SET. */
9249 set
= XVECEXP (pattern
, 0, n
);
9250 if (GET_CODE (set
) != SET
)
9253 /* Check that the SET is a load (if restoring) or a store
9255 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9259 /* Check that the address is the sum of the stack pointer and a
9260 possibly-zero constant offset. */
9261 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9262 if (base
!= stack_pointer_rtx
)
9265 /* Check that SET's other operand is a register. */
9266 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9270 /* Check for argument saves. */
9271 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9272 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9274 else if (offset
== save_offset
)
9276 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9277 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9280 mask
|= 1 << REGNO (reg
);
9281 save_offset
-= UNITS_PER_WORD
;
9287 /* Check that the restrictions on register ranges are met. */
9289 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9290 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9291 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9292 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9296 /* Make sure that the topmost argument register is not saved twice.
9297 The checks above ensure that the same is then true for the other
9298 argument registers. */
9299 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9302 /* Pass back information, if requested. */
9305 info
->nargs
= nargs
;
9307 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9313 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9314 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9315 the null terminator. */
9318 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9319 unsigned int max_reg
)
9321 if (min_reg
!= max_reg
)
9322 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9324 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9328 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9329 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9332 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9334 static char buffer
[300];
9336 struct mips16e_save_restore_info info
;
9337 unsigned int i
, end
;
9340 /* Parse the pattern. */
9341 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9344 /* Add the mnemonic. */
9345 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9348 /* Save the arguments. */
9350 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9351 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9352 else if (info
.nargs
== 1)
9353 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9355 /* Emit the amount of stack space to allocate or deallocate. */
9356 s
+= sprintf (s
, "%d", (int) info
.size
);
9358 /* Save or restore $16. */
9359 if (BITSET_P (info
.mask
, 16))
9360 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9362 /* Save or restore $17. */
9363 if (BITSET_P (info
.mask
, 17))
9364 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9366 /* Save or restore registers in the range $s2...$s8, which
9367 mips16e_s2_s8_regs lists in decreasing order. Note that this
9368 is a software register range; the hardware registers are not
9369 numbered consecutively. */
9370 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9371 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9373 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9374 mips16e_s2_s8_regs
[i
]);
9376 /* Save or restore registers in the range $a0...$a3. */
9377 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9378 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9380 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9381 mips16e_a0_a3_regs
[end
- 1]);
9383 /* Save or restore $31. */
9384 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9385 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9390 /* Return true if the current function returns its value in a floating-point
9391 register in MIPS16 mode. */
9394 mips16_cfun_returns_in_fpr_p (void)
9396 tree return_type
= DECL_RESULT (current_function_decl
);
9397 return (TARGET_MIPS16
9398 && TARGET_HARD_FLOAT_ABI
9399 && !aggregate_value_p (return_type
, current_function_decl
)
9400 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9403 /* Return true if predicate PRED is true for at least one instruction.
9404 Cache the result in *CACHE, and assume that the result is true
9405 if *CACHE is already true. */
9408 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9414 push_topmost_sequence ();
9415 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9416 if (USEFUL_INSN_P (insn
) && pred (insn
))
9421 pop_topmost_sequence ();
9426 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9427 See mips_cfun_has_inflexible_gp_ref_p for details. */
9430 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9432 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9433 indicate that the target could be a traditional MIPS
9434 lazily-binding stub. */
9435 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9438 /* Return true if the current function refers to the global pointer
9439 in a way that forces $28 to be valid. This means that we can't
9440 change the choice of global pointer, even for NewABI code.
9442 One example of this (and one which needs several checks) is that
9443 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9444 (This restriction does not apply to PLTs.) */
9447 mips_cfun_has_inflexible_gp_ref_p (void)
9449 /* If the function has a nonlocal goto, $28 must hold the correct
9450 global pointer for the target function. That is, the target
9451 of the goto implicitly uses $28. */
9452 if (crtl
->has_nonlocal_goto
)
9455 if (TARGET_ABICALLS_PIC2
)
9457 /* Symbolic accesses implicitly use the global pointer unless
9458 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9459 might go to traditional MIPS lazy-binding stubs. */
9460 if (!TARGET_EXPLICIT_RELOCS
)
9463 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9464 can be lazily-bound. */
9468 /* MIPS16 functions that return in FPRs need to call an
9469 external libgcc routine. This call is only made explict
9470 during mips_expand_epilogue, and it too might be lazily bound. */
9471 if (mips16_cfun_returns_in_fpr_p ())
9475 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9476 mips_insn_has_inflexible_gp_ref_p
);
9479 /* Return true if INSN refers to the global pointer in a "flexible" way.
9480 See mips_cfun_has_flexible_gp_ref_p for details. */
9483 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9485 return (get_attr_got (insn
) != GOT_UNSET
9486 || mips_small_data_pattern_p (PATTERN (insn
))
9487 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9490 /* Return true if the current function references the global pointer,
9491 but if those references do not inherently require the global pointer
9492 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9495 mips_cfun_has_flexible_gp_ref_p (void)
9497 /* Reload can sometimes introduce constant pool references
9498 into a function that otherwise didn't need them. For example,
9499 suppose we have an instruction like:
9501 (set (reg:DF R1) (float:DF (reg:SI R2)))
9503 If R2 turns out to be a constant such as 1, the instruction may
9504 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9505 the option of using this constant if R2 doesn't get allocated
9508 In cases like these, reload will have added the constant to the
9509 pool but no instruction will yet refer to it. */
9510 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9513 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9514 mips_insn_has_flexible_gp_ref_p
);
9517 /* Return the register that should be used as the global pointer
9518 within this function. Return INVALID_REGNUM if the function
9519 doesn't need a global pointer. */
9522 mips_global_pointer (void)
9526 /* $gp is always available unless we're using a GOT. */
9527 if (!TARGET_USE_GOT
)
9528 return GLOBAL_POINTER_REGNUM
;
9530 /* If there are inflexible references to $gp, we must use the
9531 standard register. */
9532 if (mips_cfun_has_inflexible_gp_ref_p ())
9533 return GLOBAL_POINTER_REGNUM
;
9535 /* If there are no current references to $gp, then the only uses
9536 we can introduce later are those involved in long branches. */
9537 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9538 return INVALID_REGNUM
;
9540 /* If the global pointer is call-saved, try to use a call-clobbered
9542 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9543 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9544 if (!df_regs_ever_live_p (regno
)
9545 && call_really_used_regs
[regno
]
9546 && !fixed_regs
[regno
]
9547 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9550 return GLOBAL_POINTER_REGNUM
;
9553 /* Return true if the current function's prologue must load the global
9554 pointer value into pic_offset_table_rtx and store the same value in
9555 the function's cprestore slot (if any).
9557 One problem we have to deal with is that, when emitting GOT-based
9558 position independent code, long-branch sequences will need to load
9559 the address of the branch target from the GOT. We don't know until
9560 the very end of compilation whether (and where) the function needs
9561 long branches, so we must ensure that _any_ branch can access the
9562 global pointer in some form. However, we do not want to pessimize
9563 the usual case in which all branches are short.
9565 We handle this as follows:
9567 (1) During reload, we set cfun->machine->global_pointer to
9568 INVALID_REGNUM if we _know_ that the current function
9569 doesn't need a global pointer. This is only valid if
9570 long branches don't need the GOT.
9572 Otherwise, we assume that we might need a global pointer
9573 and pick an appropriate register.
9575 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9576 we ensure that the global pointer is available at every
9577 block boundary bar entry and exit. We do this in one of two ways:
9579 - If the function has a cprestore slot, we ensure that this
9580 slot is valid at every branch. However, as explained in
9581 point (6) below, there is no guarantee that pic_offset_table_rtx
9582 itself is valid if new uses of the global pointer are introduced
9583 after the first post-epilogue split.
9585 We guarantee that the cprestore slot is valid by loading it
9586 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9587 this register live at every block boundary bar function entry
9588 and exit. It is then invalid to move the load (and thus the
9589 preceding store) across a block boundary.
9591 - If the function has no cprestore slot, we guarantee that
9592 pic_offset_table_rtx itself is valid at every branch.
9594 See mips_eh_uses for the handling of the register liveness.
9596 (3) During prologue and epilogue generation, we emit "ghost"
9597 placeholder instructions to manipulate the global pointer.
9599 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9600 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9601 that the function needs a global pointer. (There is no need to set
9602 them earlier than this, and doing it as late as possible leads to
9603 fewer false positives.)
9605 (5) If cfun->machine->must_initialize_gp_p is true during a
9606 split_insns pass, we split the ghost instructions into real
9607 instructions. These split instructions can then be optimized in
9608 the usual way. Otherwise, we keep the ghost instructions intact,
9609 and optimize for the case where they aren't needed. We still
9610 have the option of splitting them later, if we need to introduce
9611 new uses of the global pointer.
9613 For example, the scheduler ignores a ghost instruction that
9614 stores $28 to the stack, but it handles the split form of
9615 the ghost instruction as an ordinary store.
9617 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9618 is true during the first post-epilogue split_insns pass, we split
9619 calls and restore_gp patterns into instructions that explicitly
9620 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9621 we split these patterns into instructions that _don't_ load from
9624 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9625 time of the split, then any instructions that exist at that time
9626 can make free use of pic_offset_table_rtx. However, if we want
9627 to introduce new uses of the global pointer after the split,
9628 we must explicitly load the value from the cprestore slot, since
9629 pic_offset_table_rtx itself might not be valid at a given point
9632 The idea is that we want to be able to delete redundant
9633 loads from the cprestore slot in the usual case where no
9634 long branches are needed.
9636 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9637 of md_reorg, we decide whether the global pointer is needed for
9638 long branches. If so, we set cfun->machine->must_initialize_gp_p
9639 to true and split the ghost instructions into real instructions
9642 Note that the ghost instructions must have a zero length for three reasons:
9644 - Giving the length of the underlying $gp sequence might cause
9645 us to use long branches in cases where they aren't really needed.
9647 - They would perturb things like alignment calculations.
9649 - More importantly, the hazard detection in md_reorg relies on
9650 empty instructions having a zero length.
9652 If we find a long branch and split the ghost instructions at the
9653 end of md_reorg, the split could introduce more long branches.
9654 That isn't a problem though, because we still do the split before
9655 the final shorten_branches pass.
9657 This is extremely ugly, but it seems like the best compromise between
9658 correctness and efficiency. */
9661 mips_must_initialize_gp_p (void)
9663 return cfun
->machine
->must_initialize_gp_p
;
9666 /* Return true if REGNO is a register that is ordinarily call-clobbered
9667 but must nevertheless be preserved by an interrupt handler. */
9670 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9672 if (MD_REG_P (regno
))
9675 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9678 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9680 /* $0 is hard-wired. */
9681 if (regno
== GP_REG_FIRST
)
9684 /* The interrupt handler can treat kernel registers as
9685 scratch registers. */
9686 if (KERNEL_REG_P (regno
))
9689 /* The function will return the stack pointer to its original value
9691 if (regno
== STACK_POINTER_REGNUM
)
9694 /* Otherwise, return true for registers that aren't ordinarily
9696 return call_really_used_regs
[regno
];
9702 /* Return true if the current function should treat register REGNO
9706 mips_cfun_call_saved_reg_p (unsigned int regno
)
9708 /* If the user makes an ordinarily-call-saved register global,
9709 that register is no longer call-saved. */
9710 if (global_regs
[regno
])
9713 /* Interrupt handlers need to save extra registers. */
9714 if (cfun
->machine
->interrupt_handler_p
9715 && mips_interrupt_extra_call_saved_reg_p (regno
))
9718 /* call_insns preserve $28 unless they explicitly say otherwise,
9719 so call_really_used_regs[] treats $28 as call-saved. However,
9720 we want the ABI property rather than the default call_insn
9722 return (regno
== GLOBAL_POINTER_REGNUM
9723 ? TARGET_CALL_SAVED_GP
9724 : !call_really_used_regs
[regno
]);
9727 /* Return true if the function body might clobber register REGNO.
9728 We know that REGNO is call-saved. */
9731 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9733 /* Some functions should be treated as clobbering all call-saved
9735 if (crtl
->saves_all_registers
)
9738 /* DF handles cases where a register is explicitly referenced in
9739 the rtl. Incoming values are passed in call-clobbered registers,
9740 so we can assume that any live call-saved register is set within
9742 if (df_regs_ever_live_p (regno
))
9745 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9746 These clobbers are not explicit in the rtl. */
9747 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9750 /* If we're using a call-saved global pointer, the function's
9751 prologue will need to set it up. */
9752 if (cfun
->machine
->global_pointer
== regno
)
9755 /* The function's prologue will need to set the frame pointer if
9756 frame_pointer_needed. */
9757 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9760 /* If a MIPS16 function returns a value in FPRs, its epilogue
9761 will need to call an external libgcc routine. This yet-to-be
9762 generated call_insn will clobber $31. */
9763 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9766 /* If REGNO is ordinarily call-clobbered, we must assume that any
9767 called function could modify it. */
9768 if (cfun
->machine
->interrupt_handler_p
9770 && mips_interrupt_extra_call_saved_reg_p (regno
))
9776 /* Return true if the current function must save register REGNO. */
9779 mips_save_reg_p (unsigned int regno
)
9781 if (mips_cfun_call_saved_reg_p (regno
))
9783 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9786 /* Save both registers in an FPR pair if either one is used. This is
9787 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9788 register to be used without the even register. */
9789 if (FP_REG_P (regno
)
9790 && MAX_FPRS_PER_FMT
== 2
9791 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9795 /* We need to save the incoming return address if __builtin_eh_return
9796 is being used to set a different return address. */
9797 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9803 /* Populate the current function's mips_frame_info structure.
9805 MIPS stack frames look like:
9807 +-------------------------------+
9809 | incoming stack arguments |
9811 +-------------------------------+
9813 | caller-allocated save area |
9814 A | for register arguments |
9816 +-------------------------------+ <-- incoming stack pointer
9818 | callee-allocated save area |
9819 B | for arguments that are |
9820 | split between registers and |
9823 +-------------------------------+ <-- arg_pointer_rtx
9825 C | callee-allocated save area |
9826 | for register varargs |
9828 +-------------------------------+ <-- frame_pointer_rtx
9829 | | + cop0_sp_offset
9830 | COP0 reg save area | + UNITS_PER_WORD
9832 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9833 | | + UNITS_PER_WORD
9834 | accumulator save area |
9836 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9837 | | + UNITS_PER_HWFPVALUE
9840 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9841 | | + UNITS_PER_WORD
9844 +-------------------------------+ <-- frame_pointer_rtx with
9845 | | \ -fstack-protector
9846 | local variables | | var_size
9848 +-------------------------------+
9850 | $gp save area | | cprestore_size
9852 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9854 | outgoing stack arguments | |
9856 +-------------------------------+ | args_size
9858 | caller-allocated save area | |
9859 | for register arguments | |
9861 +-------------------------------+ <-- stack_pointer_rtx
9862 frame_pointer_rtx without
9864 hard_frame_pointer_rtx for
9867 At least two of A, B and C will be empty.
9869 Dynamic stack allocations such as alloca insert data at point P.
9870 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9871 hard_frame_pointer_rtx unchanged. */
9874 mips_compute_frame_info (void)
9876 struct mips_frame_info
*frame
;
9877 HOST_WIDE_INT offset
, size
;
9878 unsigned int regno
, i
;
9880 /* Set this function's interrupt properties. */
9881 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9884 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9885 else if (TARGET_HARD_FLOAT
)
9886 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9887 else if (TARGET_MIPS16
)
9888 error ("interrupt handlers cannot be MIPS16 functions");
9891 cfun
->machine
->interrupt_handler_p
= true;
9892 cfun
->machine
->use_shadow_register_set_p
=
9893 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9894 cfun
->machine
->keep_interrupts_masked_p
=
9895 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9896 cfun
->machine
->use_debug_exception_return_p
=
9897 mips_use_debug_exception_return_p (TREE_TYPE
9898 (current_function_decl
));
9902 frame
= &cfun
->machine
->frame
;
9903 memset (frame
, 0, sizeof (*frame
));
9904 size
= get_frame_size ();
9906 cfun
->machine
->global_pointer
= mips_global_pointer ();
9908 /* The first two blocks contain the outgoing argument area and the $gp save
9909 slot. This area isn't needed in leaf functions, but if the
9910 target-independent frame size is nonzero, we have already committed to
9911 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9912 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9914 /* The MIPS 3.0 linker does not like functions that dynamically
9915 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9916 looks like we are trying to create a second frame pointer to the
9917 function, so allocate some stack space to make it happy. */
9918 if (cfun
->calls_alloca
)
9919 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9921 frame
->args_size
= 0;
9922 frame
->cprestore_size
= 0;
9926 frame
->args_size
= crtl
->outgoing_args_size
;
9927 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9929 offset
= frame
->args_size
+ frame
->cprestore_size
;
9931 /* Move above the local variables. */
9932 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9933 offset
+= frame
->var_size
;
9935 /* Find out which GPRs we need to save. */
9936 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9937 if (mips_save_reg_p (regno
))
9940 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9943 /* If this function calls eh_return, we must also save and restore the
9944 EH data registers. */
9945 if (crtl
->calls_eh_return
)
9946 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9949 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9952 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9953 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9954 save all later registers too. */
9955 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9957 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9958 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9959 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9960 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9963 /* Move above the GPR save area. */
9964 if (frame
->num_gp
> 0)
9966 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9967 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9970 /* Find out which FPRs we need to save. This loop must iterate over
9971 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9972 if (TARGET_HARD_FLOAT
)
9973 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9974 if (mips_save_reg_p (regno
))
9976 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9977 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9980 /* Move above the FPR save area. */
9981 if (frame
->num_fp
> 0)
9983 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9984 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9987 /* Add in space for the interrupt context information. */
9988 if (cfun
->machine
->interrupt_handler_p
)
9991 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9994 frame
->acc_mask
|= (1 << 0);
9997 /* Check accumulators 1, 2, 3. */
9998 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9999 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10002 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10005 /* All interrupt context functions need space to preserve STATUS. */
10006 frame
->num_cop0_regs
++;
10008 /* If we don't keep interrupts masked, we need to save EPC. */
10009 if (!cfun
->machine
->keep_interrupts_masked_p
)
10010 frame
->num_cop0_regs
++;
10013 /* Move above the accumulator save area. */
10014 if (frame
->num_acc
> 0)
10016 /* Each accumulator needs 2 words. */
10017 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10018 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10021 /* Move above the COP0 register save area. */
10022 if (frame
->num_cop0_regs
> 0)
10024 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10025 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10028 /* Move above the callee-allocated varargs save area. */
10029 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10030 frame
->arg_pointer_offset
= offset
;
10032 /* Move above the callee-allocated area for pretend stack arguments. */
10033 offset
+= crtl
->args
.pretend_args_size
;
10034 frame
->total_size
= offset
;
10036 /* Work out the offsets of the save areas from the top of the frame. */
10037 if (frame
->gp_sp_offset
> 0)
10038 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10039 if (frame
->fp_sp_offset
> 0)
10040 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10041 if (frame
->acc_sp_offset
> 0)
10042 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10043 if (frame
->num_cop0_regs
> 0)
10044 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10046 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10047 arguments. This tends to increase the chances of using unextended
10048 instructions for local variables and incoming arguments. */
10050 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10053 /* Return the style of GP load sequence that is being used for the
10054 current function. */
10056 enum mips_loadgp_style
10057 mips_current_loadgp_style (void)
10059 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10060 return LOADGP_NONE
;
10062 if (TARGET_RTP_PIC
)
10065 if (TARGET_ABSOLUTE_ABICALLS
)
10066 return LOADGP_ABSOLUTE
;
10068 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10071 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10074 mips_frame_pointer_required (void)
10076 /* If the function contains dynamic stack allocations, we need to
10077 use the frame pointer to access the static parts of the frame. */
10078 if (cfun
->calls_alloca
)
10081 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10082 reload may be unable to compute the address of a local variable,
10083 since there is no way to add a large constant to the stack pointer
10084 without using a second temporary register. */
10087 mips_compute_frame_info ();
10088 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10095 /* Make sure that we're not trying to eliminate to the wrong hard frame
10099 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10101 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10104 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10105 or argument pointer. TO is either the stack pointer or hard frame
10109 mips_initial_elimination_offset (int from
, int to
)
10111 HOST_WIDE_INT offset
;
10113 mips_compute_frame_info ();
10115 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10118 case FRAME_POINTER_REGNUM
:
10119 if (FRAME_GROWS_DOWNWARD
)
10120 offset
= (cfun
->machine
->frame
.args_size
10121 + cfun
->machine
->frame
.cprestore_size
10122 + cfun
->machine
->frame
.var_size
);
10127 case ARG_POINTER_REGNUM
:
10128 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10132 gcc_unreachable ();
10135 if (to
== HARD_FRAME_POINTER_REGNUM
)
10136 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10141 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10144 mips_extra_live_on_entry (bitmap regs
)
10146 if (TARGET_USE_GOT
)
10148 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10149 the global pointer. */
10150 if (!TARGET_ABSOLUTE_ABICALLS
)
10151 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10153 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10154 the global pointer. */
10156 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10158 /* See the comment above load_call<mode> for details. */
10159 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10163 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10167 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10172 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10175 /* Emit code to change the current function's return address to
10176 ADDRESS. SCRATCH is available as a scratch register, if needed.
10177 ADDRESS and SCRATCH are both word-mode GPRs. */
10180 mips_set_return_address (rtx address
, rtx scratch
)
10184 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10185 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10186 cfun
->machine
->frame
.gp_sp_offset
);
10187 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10190 /* Return true if the current function has a cprestore slot. */
10193 mips_cfun_has_cprestore_slot_p (void)
10195 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10196 && cfun
->machine
->frame
.cprestore_size
> 0);
10199 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10200 cprestore slot. LOAD_P is true if the caller wants to load from
10201 the cprestore slot; it is false if the caller wants to store to
10205 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10208 const struct mips_frame_info
*frame
;
10210 frame
= &cfun
->machine
->frame
;
10211 /* .cprestore always uses the stack pointer instead of the frame pointer.
10212 We have a free choice for direct stores for non-MIPS16 functions,
10213 and for MIPS16 functions whose cprestore slot is in range of the
10214 stack pointer. Using the stack pointer would sometimes give more
10215 (early) scheduling freedom, but using the frame pointer would
10216 sometimes give more (late) scheduling freedom. It's hard to
10217 predict which applies to a given function, so let's keep things
10220 Loads must always use the frame pointer in functions that call
10221 alloca, and there's little benefit to using the stack pointer
10223 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10225 *base
= hard_frame_pointer_rtx
;
10226 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10230 *base
= stack_pointer_rtx
;
10231 *offset
= frame
->args_size
;
10235 /* Return true if X is the load or store address of the cprestore slot;
10236 LOAD_P says which. */
10239 mips_cprestore_address_p (rtx x
, bool load_p
)
10241 rtx given_base
, required_base
;
10242 HOST_WIDE_INT given_offset
, required_offset
;
10244 mips_split_plus (x
, &given_base
, &given_offset
);
10245 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10246 return given_base
== required_base
&& given_offset
== required_offset
;
10249 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10250 going to load from it, false if we are going to store to it.
10251 Use TEMP as a temporary register if need be. */
10254 mips_cprestore_slot (rtx temp
, bool load_p
)
10257 HOST_WIDE_INT offset
;
10259 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10260 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10263 /* Emit instructions to save global pointer value GP into cprestore
10264 slot MEM. OFFSET is the offset that MEM applies to the base register.
10266 MEM may not be a legitimate address. If it isn't, TEMP is a
10267 temporary register that can be used, otherwise it is a SCRATCH. */
10270 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10272 if (TARGET_CPRESTORE_DIRECTIVE
)
10274 gcc_assert (gp
== pic_offset_table_rtx
);
10275 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10278 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10281 /* Restore $gp from its save slot, using TEMP as a temporary base register
10282 if need be. This function is for o32 and o64 abicalls only.
10284 See mips_must_initialize_gp_p for details about how we manage the
10288 mips_restore_gp_from_cprestore_slot (rtx temp
)
10290 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10292 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10294 emit_note (NOTE_INSN_DELETED
);
10300 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10301 mips_emit_move (pic_offset_table_rtx
, temp
);
10304 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10305 if (!TARGET_EXPLICIT_RELOCS
)
10306 emit_insn (gen_blockage ());
10309 /* A function to save or store a register. The first argument is the
10310 register and the second is the stack slot. */
10311 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10313 /* Use FN to save or restore register REGNO. MODE is the register's
10314 mode and OFFSET is the offset of its save slot from the current
10318 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10319 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10323 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10325 fn (gen_rtx_REG (mode
, regno
), mem
);
10328 /* Call FN for each accumlator that is saved by the current function.
10329 SP_OFFSET is the offset of the current stack pointer from the start
10333 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10335 HOST_WIDE_INT offset
;
10338 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10339 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10341 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10342 offset
-= UNITS_PER_WORD
;
10343 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10344 offset
-= UNITS_PER_WORD
;
10347 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10348 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10349 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10351 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10352 offset
-= UNITS_PER_WORD
;
10356 /* Save register REG to MEM. Make the instruction frame-related. */
10359 mips_save_reg (rtx reg
, rtx mem
)
10361 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10365 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10367 x1
= mips_frame_set (mips_subword (mem
, false),
10368 mips_subword (reg
, false));
10369 x2
= mips_frame_set (mips_subword (mem
, true),
10370 mips_subword (reg
, true));
10371 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10374 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10377 /* Capture the register combinations that are allowed in a SWM or LWM
10378 instruction. The entries are ordered by number of registers set in
10379 the mask. We also ignore the single register encodings because a
10380 normal SW/LW is preferred. */
10382 static const unsigned int umips_swm_mask
[17] = {
10383 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10384 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10385 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10386 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10390 static const unsigned int umips_swm_encoding
[17] = {
10391 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10394 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10395 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10396 stack pointer of the topmost save slot.
10398 Remove from *MASK all registers that were handled using LWM and SWM.
10399 Update *OFFSET so that it points to the first unused save slot. */
10402 umips_build_save_restore (mips_save_restore_fn fn
,
10403 unsigned *mask
, HOST_WIDE_INT
*offset
)
10407 rtx pattern
, set
, reg
, mem
;
10408 HOST_WIDE_INT this_offset
;
10411 /* Try matching $16 to $31 (s0 to ra). */
10412 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10413 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10416 if (i
== ARRAY_SIZE (umips_swm_mask
))
10419 /* Get the offset of the lowest save slot. */
10420 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10421 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10423 /* LWM/SWM can only support offsets from -2048 to 2047. */
10424 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10427 /* Create the final PARALLEL. */
10428 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10429 this_base
= stack_pointer_rtx
;
10431 /* For registers $16-$23 and $30. */
10432 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10434 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10435 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10436 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10437 *mask
&= ~(1 << regno
);
10438 reg
= gen_rtx_REG (SImode
, regno
);
10439 if (fn
== mips_save_reg
)
10440 set
= mips_frame_set (mem
, reg
);
10443 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10444 mips_add_cfa_restore (reg
);
10446 XVECEXP (pattern
, 0, j
) = set
;
10449 /* For register $31. */
10450 if (umips_swm_encoding
[i
] >> 4)
10452 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10453 *mask
&= ~(1 << 31);
10454 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10455 reg
= gen_rtx_REG (SImode
, 31);
10456 if (fn
== mips_save_reg
)
10457 set
= mips_frame_set (mem
, reg
);
10460 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10461 mips_add_cfa_restore (reg
);
10463 XVECEXP (pattern
, 0, j
) = set
;
10466 pattern
= emit_insn (pattern
);
10467 if (fn
== mips_save_reg
)
10468 RTX_FRAME_RELATED_P (pattern
) = 1;
10470 /* Adjust the last offset. */
10471 *offset
-= UNITS_PER_WORD
* nregs
;
10476 /* Call FN for each register that is saved by the current function.
10477 SP_OFFSET is the offset of the current stack pointer from the start
10481 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10482 mips_save_restore_fn fn
)
10484 enum machine_mode fpr_mode
;
10486 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10487 HOST_WIDE_INT offset
;
10490 /* Save registers starting from high to low. The debuggers prefer at least
10491 the return register be stored at func+4, and also it allows us not to
10492 need a nop in the epilogue if at least one register is reloaded in
10493 addition to return address. */
10494 offset
= frame
->gp_sp_offset
- sp_offset
;
10495 mask
= frame
->mask
;
10497 if (TARGET_MICROMIPS
)
10498 umips_build_save_restore (fn
, &mask
, &offset
);
10500 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10501 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10503 /* Record the ra offset for use by mips_function_profiler. */
10504 if (regno
== RETURN_ADDR_REGNUM
)
10505 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10506 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10507 offset
-= UNITS_PER_WORD
;
10510 /* This loop must iterate over the same space as its companion in
10511 mips_compute_frame_info. */
10512 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10513 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10514 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10515 regno
>= FP_REG_FIRST
;
10516 regno
-= MAX_FPRS_PER_FMT
)
10517 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10519 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10520 offset
-= GET_MODE_SIZE (fpr_mode
);
10524 /* Return true if a move between register REGNO and its save slot (MEM)
10525 can be done in a single move. LOAD_P is true if we are loading
10526 from the slot, false if we are storing to it. */
10529 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10531 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10532 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10535 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10536 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10539 /* Emit a move from SRC to DEST, given that one of them is a register
10540 save slot and that the other is a register. TEMP is a temporary
10541 GPR of the same mode that is available if need be. */
10544 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10546 unsigned int regno
;
10551 regno
= REGNO (src
);
10556 regno
= REGNO (dest
);
10560 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10562 /* We don't yet know whether we'll need this instruction or not.
10563 Postpone the decision by emitting a ghost move. This move
10564 is specifically not frame-related; only the split version is. */
10566 emit_insn (gen_move_gpdi (dest
, src
));
10568 emit_insn (gen_move_gpsi (dest
, src
));
10572 if (regno
== HI_REGNUM
)
10576 mips_emit_move (temp
, src
);
10578 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10579 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10581 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10582 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10587 emit_insn (gen_mfhidi_ti (temp
,
10588 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10590 emit_insn (gen_mfhisi_di (temp
,
10591 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10592 mips_emit_move (dest
, temp
);
10595 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10596 mips_emit_move (dest
, src
);
10599 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10600 mips_emit_move (temp
, src
);
10601 mips_emit_move (dest
, temp
);
10604 mips_set_frame_expr (mips_frame_set (dest
, src
));
10607 /* If we're generating n32 or n64 abicalls, and the current function
10608 does not use $28 as its global pointer, emit a cplocal directive.
10609 Use pic_offset_table_rtx as the argument to the directive. */
10612 mips_output_cplocal (void)
10614 if (!TARGET_EXPLICIT_RELOCS
10615 && mips_must_initialize_gp_p ()
10616 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10617 output_asm_insn (".cplocal %+", 0);
10620 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10623 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10625 const char *fnname
;
10627 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10628 floating-point arguments. */
10630 && TARGET_HARD_FLOAT_ABI
10631 && crtl
->args
.info
.fp_code
!= 0)
10632 mips16_build_function_stub ();
10634 /* Get the function name the same way that toplev.c does before calling
10635 assemble_start_function. This is needed so that the name used here
10636 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10637 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10638 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10640 /* Output MIPS-specific frame information. */
10641 if (!flag_inhibit_size_directive
)
10643 const struct mips_frame_info
*frame
;
10645 frame
= &cfun
->machine
->frame
;
10647 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10649 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10650 "# vars= " HOST_WIDE_INT_PRINT_DEC
10652 ", args= " HOST_WIDE_INT_PRINT_DEC
10653 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10654 reg_names
[frame_pointer_needed
10655 ? HARD_FRAME_POINTER_REGNUM
10656 : STACK_POINTER_REGNUM
],
10657 (frame_pointer_needed
10658 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10659 : frame
->total_size
),
10660 reg_names
[RETURN_ADDR_REGNUM
],
10662 frame
->num_gp
, frame
->num_fp
,
10664 frame
->cprestore_size
);
10666 /* .mask MASK, OFFSET. */
10667 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10668 frame
->mask
, frame
->gp_save_offset
);
10670 /* .fmask MASK, OFFSET. */
10671 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10672 frame
->fmask
, frame
->fp_save_offset
);
10675 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10676 Also emit the ".set noreorder; .set nomacro" sequence for functions
10678 if (mips_must_initialize_gp_p ()
10679 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10683 /* This is a fixed-form sequence. The position of the
10684 first two instructions is important because of the
10685 way _gp_disp is defined. */
10686 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10687 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10688 output_asm_insn ("sll\t$2,16", 0);
10689 output_asm_insn ("addu\t$2,$3", 0);
10693 /* .cpload must be in a .set noreorder but not a
10694 .set nomacro block. */
10695 mips_push_asm_switch (&mips_noreorder
);
10696 output_asm_insn (".cpload\t%^", 0);
10697 if (!cfun
->machine
->all_noreorder_p
)
10698 mips_pop_asm_switch (&mips_noreorder
);
10700 mips_push_asm_switch (&mips_nomacro
);
10703 else if (cfun
->machine
->all_noreorder_p
)
10705 mips_push_asm_switch (&mips_noreorder
);
10706 mips_push_asm_switch (&mips_nomacro
);
10709 /* Tell the assembler which register we're using as the global
10710 pointer. This is needed for thunks, since they can use either
10711 explicit relocs or assembler macros. */
10712 mips_output_cplocal ();
10715 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10718 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10719 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10721 const char *fnname
;
10723 /* Reinstate the normal $gp. */
10724 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10725 mips_output_cplocal ();
10727 if (cfun
->machine
->all_noreorder_p
)
10729 mips_pop_asm_switch (&mips_nomacro
);
10730 mips_pop_asm_switch (&mips_noreorder
);
10733 /* Get the function name the same way that toplev.c does before calling
10734 assemble_start_function. This is needed so that the name used here
10735 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10736 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10737 mips_end_function_definition (fnname
);
10740 /* Emit an optimisation barrier for accesses to the current frame. */
10743 mips_frame_barrier (void)
10745 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10749 /* The __gnu_local_gp symbol. */
10751 static GTY(()) rtx mips_gnu_local_gp
;
10753 /* If we're generating n32 or n64 abicalls, emit instructions
10754 to set up the global pointer. */
10757 mips_emit_loadgp (void)
10759 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10761 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10762 switch (mips_current_loadgp_style ())
10764 case LOADGP_ABSOLUTE
:
10765 if (mips_gnu_local_gp
== NULL
)
10767 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10768 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10770 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10771 (pic_reg
, mips_gnu_local_gp
)));
10774 case LOADGP_OLDABI
:
10775 /* Added by mips_output_function_prologue. */
10778 case LOADGP_NEWABI
:
10779 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10780 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10781 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10782 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10783 (pic_reg
, offset
, incoming_address
)));
10787 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10788 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10789 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10797 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10798 (pic_offset_table_rtx
, pic_reg
)));
10800 /* Emit a blockage if there are implicit uses of the GP register.
10801 This includes profiled functions, because FUNCTION_PROFILE uses
10803 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10804 emit_insn (gen_loadgp_blockage ());
10807 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10809 #if PROBE_INTERVAL > 32768
10810 #error Cannot use indexed addressing mode for stack probing
10813 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10814 inclusive. These are offsets from the current stack pointer. */
10817 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10820 sorry ("-fstack-check=specific not implemented for MIPS16");
10822 /* See if we have a constant small number of probes to generate. If so,
10823 that's the easy case. */
10824 if (first
+ size
<= 32768)
10828 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10829 it exceeds SIZE. If only one probe is needed, this will not
10830 generate any code. Then probe at FIRST + SIZE. */
10831 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10832 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10835 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10839 /* Otherwise, do the same as above, but in a loop. Note that we must be
10840 extra careful with variables wrapping around because we might be at
10841 the very top (or the very bottom) of the address space and we have
10842 to be able to handle this case properly; in particular, we use an
10843 equality test for the loop condition. */
10846 HOST_WIDE_INT rounded_size
;
10847 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10848 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10850 /* Sanity check for the addressing mode we're going to use. */
10851 gcc_assert (first
<= 32768);
10854 /* Step 1: round SIZE to the previous multiple of the interval. */
10856 rounded_size
= size
& -PROBE_INTERVAL
;
10859 /* Step 2: compute initial and final value of the loop counter. */
10861 /* TEST_ADDR = SP + FIRST. */
10862 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10863 plus_constant (Pmode
, stack_pointer_rtx
,
10866 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10867 if (rounded_size
> 32768)
10869 emit_move_insn (r12
, GEN_INT (rounded_size
));
10870 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10871 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10874 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10875 plus_constant (Pmode
, r3
, -rounded_size
)));
10878 /* Step 3: the loop
10880 while (TEST_ADDR != LAST_ADDR)
10882 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10886 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10887 until it is equal to ROUNDED_SIZE. */
10889 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10892 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10893 that SIZE is equal to ROUNDED_SIZE. */
10895 if (size
!= rounded_size
)
10896 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10899 /* Make sure nothing is scheduled before we are done. */
10900 emit_insn (gen_blockage ());
10903 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10904 absolute addresses. */
10907 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10909 static int labelno
= 0;
10910 char loop_lab
[32], end_lab
[32], tmp
[64];
10913 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10914 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10916 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10918 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10921 strcpy (tmp
, "%(%<beq\t%0,%1,");
10922 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10924 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10925 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10926 if (TARGET_64BIT
&& TARGET_LONG64
)
10927 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10929 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10931 /* Probe at TEST_ADDR and branch. */
10932 fprintf (asm_out_file
, "\tb\t");
10933 assemble_name_raw (asm_out_file
, loop_lab
);
10934 fputc ('\n', asm_out_file
);
10936 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
10938 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
10940 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
10945 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10948 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10950 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10953 /* Expand the "prologue" pattern. */
10956 mips_expand_prologue (void)
10958 const struct mips_frame_info
*frame
;
10959 HOST_WIDE_INT size
;
10960 unsigned int nargs
;
10963 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10965 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10966 or implicitly. If so, we can commit to using a global pointer
10967 straight away, otherwise we need to defer the decision. */
10968 if (mips_cfun_has_inflexible_gp_ref_p ()
10969 || mips_cfun_has_flexible_gp_ref_p ())
10971 cfun
->machine
->must_initialize_gp_p
= true;
10972 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10975 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10978 frame
= &cfun
->machine
->frame
;
10979 size
= frame
->total_size
;
10981 if (flag_stack_usage_info
)
10982 current_function_static_stack_size
= size
;
10984 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
10985 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
10987 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10988 bytes beforehand; this is enough to cover the register save area
10989 without going out of range. */
10990 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10991 || frame
->num_cop0_regs
> 0)
10993 HOST_WIDE_INT step1
;
10995 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10996 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10998 HOST_WIDE_INT offset
;
10999 unsigned int mask
, regno
;
11001 /* Try to merge argument stores into the save instruction. */
11002 nargs
= mips16e_collect_argument_saves ();
11004 /* Build the save instruction. */
11005 mask
= frame
->mask
;
11006 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11008 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11009 mips_frame_barrier ();
11012 /* Check if we need to save other registers. */
11013 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11014 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11016 offset
-= UNITS_PER_WORD
;
11017 mips_save_restore_reg (word_mode
, regno
,
11018 offset
, mips_save_reg
);
11023 if (cfun
->machine
->interrupt_handler_p
)
11025 HOST_WIDE_INT offset
;
11028 /* If this interrupt is using a shadow register set, we need to
11029 get the stack pointer from the previous register set. */
11030 if (cfun
->machine
->use_shadow_register_set_p
)
11031 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11032 stack_pointer_rtx
));
11034 if (!cfun
->machine
->keep_interrupts_masked_p
)
11036 /* Move from COP0 Cause to K0. */
11037 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11038 gen_rtx_REG (SImode
,
11039 COP0_CAUSE_REG_NUM
)));
11040 /* Move from COP0 EPC to K1. */
11041 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11042 gen_rtx_REG (SImode
,
11043 COP0_EPC_REG_NUM
)));
11046 /* Allocate the first part of the frame. */
11047 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11049 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11050 mips_frame_barrier ();
11053 /* Start at the uppermost location for saving. */
11054 offset
= frame
->cop0_sp_offset
- size
;
11055 if (!cfun
->machine
->keep_interrupts_masked_p
)
11057 /* Push EPC into its stack slot. */
11058 mem
= gen_frame_mem (word_mode
,
11059 plus_constant (Pmode
, stack_pointer_rtx
,
11061 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11062 offset
-= UNITS_PER_WORD
;
11065 /* Move from COP0 Status to K1. */
11066 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11067 gen_rtx_REG (SImode
,
11068 COP0_STATUS_REG_NUM
)));
11070 /* Right justify the RIPL in k0. */
11071 if (!cfun
->machine
->keep_interrupts_masked_p
)
11072 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11073 gen_rtx_REG (SImode
, K0_REG_NUM
),
11074 GEN_INT (CAUSE_IPL
)));
11076 /* Push Status into its stack slot. */
11077 mem
= gen_frame_mem (word_mode
,
11078 plus_constant (Pmode
, stack_pointer_rtx
,
11080 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11081 offset
-= UNITS_PER_WORD
;
11083 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11084 if (!cfun
->machine
->keep_interrupts_masked_p
)
11085 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11088 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11090 if (!cfun
->machine
->keep_interrupts_masked_p
)
11091 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11092 IE is already the correct value, so we don't have to do
11093 anything explicit. */
11094 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11097 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11099 /* Disable interrupts by clearing the KSU, ERL, EXL,
11101 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11104 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11108 insn
= gen_add3_insn (stack_pointer_rtx
,
11111 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11112 mips_frame_barrier ();
11115 mips_for_each_saved_acc (size
, mips_save_reg
);
11116 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11120 /* Allocate the rest of the frame. */
11123 if (SMALL_OPERAND (-size
))
11124 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11126 GEN_INT (-size
)))) = 1;
11129 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11132 /* There are no instructions to add or subtract registers
11133 from the stack pointer, so use the frame pointer as a
11134 temporary. We should always be using a frame pointer
11135 in this case anyway. */
11136 gcc_assert (frame_pointer_needed
);
11137 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11138 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11139 hard_frame_pointer_rtx
,
11140 MIPS_PROLOGUE_TEMP (Pmode
)));
11141 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11144 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11146 MIPS_PROLOGUE_TEMP (Pmode
)));
11148 /* Describe the combined effect of the previous instructions. */
11149 mips_set_frame_expr
11150 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11151 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11153 mips_frame_barrier ();
11156 /* Set up the frame pointer, if we're using one. */
11157 if (frame_pointer_needed
)
11159 HOST_WIDE_INT offset
;
11161 offset
= frame
->hard_frame_pointer_offset
;
11164 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11165 RTX_FRAME_RELATED_P (insn
) = 1;
11167 else if (SMALL_OPERAND (offset
))
11169 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11170 stack_pointer_rtx
, GEN_INT (offset
));
11171 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11175 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11176 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11177 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11178 hard_frame_pointer_rtx
,
11179 MIPS_PROLOGUE_TEMP (Pmode
)));
11180 mips_set_frame_expr
11181 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11182 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11186 mips_emit_loadgp ();
11188 /* Initialize the $gp save slot. */
11189 if (mips_cfun_has_cprestore_slot_p ())
11191 rtx base
, mem
, gp
, temp
;
11192 HOST_WIDE_INT offset
;
11194 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11195 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11196 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11197 temp
= (SMALL_OPERAND (offset
)
11198 ? gen_rtx_SCRATCH (Pmode
)
11199 : MIPS_PROLOGUE_TEMP (Pmode
));
11200 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11201 (mem
, GEN_INT (offset
), gp
, temp
)));
11203 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11204 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11205 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11208 /* We need to search back to the last use of K0 or K1. */
11209 if (cfun
->machine
->interrupt_handler_p
)
11211 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11213 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11215 /* Emit a move from K1 to COP0 Status after insn. */
11216 gcc_assert (insn
!= NULL_RTX
);
11217 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11218 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11222 /* If we are profiling, make sure no instructions are scheduled before
11223 the call to mcount. */
11225 emit_insn (gen_blockage ());
11228 /* Attach all pending register saves to the previous instruction.
11229 Return that instruction. */
11232 mips_epilogue_emit_cfa_restores (void)
11236 insn
= get_last_insn ();
11237 gcc_assert (insn
&& !REG_NOTES (insn
));
11238 if (mips_epilogue
.cfa_restores
)
11240 RTX_FRAME_RELATED_P (insn
) = 1;
11241 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11242 mips_epilogue
.cfa_restores
= 0;
11247 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11248 now at REG + OFFSET. */
11251 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11255 insn
= mips_epilogue_emit_cfa_restores ();
11256 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11258 RTX_FRAME_RELATED_P (insn
) = 1;
11259 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11260 plus_constant (Pmode
, reg
, offset
),
11262 mips_epilogue
.cfa_reg
= reg
;
11263 mips_epilogue
.cfa_offset
= offset
;
11267 /* Emit instructions to restore register REG from slot MEM. Also update
11268 the cfa_restores list. */
11271 mips_restore_reg (rtx reg
, rtx mem
)
11273 /* There's no MIPS16 instruction to load $31 directly. Load into
11274 $7 instead and adjust the return insn appropriately. */
11275 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11276 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11277 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11279 mips_add_cfa_restore (mips_subword (reg
, true));
11280 mips_add_cfa_restore (mips_subword (reg
, false));
11283 mips_add_cfa_restore (reg
);
11285 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11286 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11287 /* The CFA is currently defined in terms of the register whose
11288 value we have just restored. Redefine the CFA in terms of
11289 the stack pointer. */
11290 mips_epilogue_set_cfa (stack_pointer_rtx
,
11291 mips_epilogue
.cfa_restore_sp_offset
);
11294 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11295 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11296 BASE, if not the stack pointer, is available as a temporary. */
11299 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11301 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11304 mips_frame_barrier ();
11305 if (offset
== const0_rtx
)
11307 emit_move_insn (stack_pointer_rtx
, base
);
11308 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11310 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11312 emit_insn (gen_add3_insn (base
, base
, offset
));
11313 mips_epilogue_set_cfa (base
, new_frame_size
);
11314 emit_move_insn (stack_pointer_rtx
, base
);
11318 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11319 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11323 /* Emit any instructions needed before a return. */
11326 mips_expand_before_return (void)
11328 /* When using a call-clobbered gp, we start out with unified call
11329 insns that include instructions to restore the gp. We then split
11330 these unified calls after reload. These split calls explicitly
11331 clobber gp, so there is no need to define
11332 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11334 For consistency, we should also insert an explicit clobber of $28
11335 before return insns, so that the post-reload optimizers know that
11336 the register is not live on exit. */
11337 if (TARGET_CALL_CLOBBERED_GP
)
11338 emit_clobber (pic_offset_table_rtx
);
11341 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11345 mips_expand_epilogue (bool sibcall_p
)
11347 const struct mips_frame_info
*frame
;
11348 HOST_WIDE_INT step1
, step2
;
11349 rtx base
, adjust
, insn
;
11350 bool use_jraddiusp_p
= false;
11352 if (!sibcall_p
&& mips_can_use_return_insn ())
11354 emit_jump_insn (gen_return ());
11358 /* In MIPS16 mode, if the return value should go into a floating-point
11359 register, we need to call a helper routine to copy it over. */
11360 if (mips16_cfun_returns_in_fpr_p ())
11361 mips16_copy_fpr_return_value ();
11363 /* Split the frame into two. STEP1 is the amount of stack we should
11364 deallocate before restoring the registers. STEP2 is the amount we
11365 should deallocate afterwards.
11367 Start off by assuming that no registers need to be restored. */
11368 frame
= &cfun
->machine
->frame
;
11369 step1
= frame
->total_size
;
11372 /* Work out which register holds the frame address. */
11373 if (!frame_pointer_needed
)
11374 base
= stack_pointer_rtx
;
11377 base
= hard_frame_pointer_rtx
;
11378 step1
-= frame
->hard_frame_pointer_offset
;
11380 mips_epilogue
.cfa_reg
= base
;
11381 mips_epilogue
.cfa_offset
= step1
;
11382 mips_epilogue
.cfa_restores
= NULL_RTX
;
11384 /* If we need to restore registers, deallocate as much stack as
11385 possible in the second step without going out of range. */
11386 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11387 || frame
->num_cop0_regs
> 0)
11389 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11393 /* Get an rtx for STEP1 that we can add to BASE. */
11394 adjust
= GEN_INT (step1
);
11395 if (!SMALL_OPERAND (step1
))
11397 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11398 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11400 mips_deallocate_stack (base
, adjust
, step2
);
11402 /* If we're using addressing macros, $gp is implicitly used by all
11403 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11405 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11406 emit_insn (gen_blockage ());
11408 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11409 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11411 unsigned int regno
, mask
;
11412 HOST_WIDE_INT offset
;
11415 /* Generate the restore instruction. */
11416 mask
= frame
->mask
;
11417 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11419 /* Restore any other registers manually. */
11420 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11421 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11423 offset
-= UNITS_PER_WORD
;
11424 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11427 /* Restore the remaining registers and deallocate the final bit
11429 mips_frame_barrier ();
11430 emit_insn (restore
);
11431 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11435 /* Restore the registers. */
11436 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11437 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11440 if (cfun
->machine
->interrupt_handler_p
)
11442 HOST_WIDE_INT offset
;
11445 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11446 if (!cfun
->machine
->keep_interrupts_masked_p
)
11448 /* Restore the original EPC. */
11449 mem
= gen_frame_mem (word_mode
,
11450 plus_constant (Pmode
, stack_pointer_rtx
,
11452 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11453 offset
-= UNITS_PER_WORD
;
11455 /* Move to COP0 EPC. */
11456 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11457 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11460 /* Restore the original Status. */
11461 mem
= gen_frame_mem (word_mode
,
11462 plus_constant (Pmode
, stack_pointer_rtx
,
11464 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11465 offset
-= UNITS_PER_WORD
;
11467 /* If we don't use shadow register set, we need to update SP. */
11468 if (!cfun
->machine
->use_shadow_register_set_p
)
11469 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11471 /* The choice of position is somewhat arbitrary in this case. */
11472 mips_epilogue_emit_cfa_restores ();
11474 /* Move to COP0 Status. */
11475 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11476 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11478 else if (TARGET_MICROMIPS
11479 && !crtl
->calls_eh_return
11482 && mips_unsigned_immediate_p (step2
, 5, 2))
11483 use_jraddiusp_p
= true;
11485 /* Deallocate the final bit of the frame. */
11486 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11489 if (!use_jraddiusp_p
)
11490 gcc_assert (!mips_epilogue
.cfa_restores
);
11492 /* Add in the __builtin_eh_return stack adjustment. We need to
11493 use a temporary in MIPS16 code. */
11494 if (crtl
->calls_eh_return
)
11498 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11499 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11500 MIPS_EPILOGUE_TEMP (Pmode
),
11501 EH_RETURN_STACKADJ_RTX
));
11502 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11505 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11507 EH_RETURN_STACKADJ_RTX
));
11512 mips_expand_before_return ();
11513 if (cfun
->machine
->interrupt_handler_p
)
11515 /* Interrupt handlers generate eret or deret. */
11516 if (cfun
->machine
->use_debug_exception_return_p
)
11517 emit_jump_insn (gen_mips_deret ());
11519 emit_jump_insn (gen_mips_eret ());
11525 /* When generating MIPS16 code, the normal
11526 mips_for_each_saved_gpr_and_fpr path will restore the return
11527 address into $7 rather than $31. */
11529 && !GENERATE_MIPS16E_SAVE_RESTORE
11530 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11532 /* simple_returns cannot rely on values that are only available
11533 on paths through the epilogue (because return paths that do
11534 not pass through the epilogue may nevertheless reuse a
11535 simple_return that occurs at the end of the epilogue).
11536 Use a normal return here instead. */
11537 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11538 pat
= gen_return_internal (reg
);
11540 else if (use_jraddiusp_p
)
11541 pat
= gen_jraddiusp (GEN_INT (step2
));
11544 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11545 pat
= gen_simple_return_internal (reg
);
11547 emit_jump_insn (pat
);
11548 if (use_jraddiusp_p
)
11549 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11553 /* Search from the beginning to the first use of K0 or K1. */
11554 if (cfun
->machine
->interrupt_handler_p
11555 && !cfun
->machine
->keep_interrupts_masked_p
)
11557 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11559 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11561 gcc_assert (insn
!= NULL_RTX
);
11562 /* Insert disable interrupts before the first use of K0 or K1. */
11563 emit_insn_before (gen_mips_di (), insn
);
11564 emit_insn_before (gen_mips_ehb (), insn
);
11568 /* Return nonzero if this function is known to have a null epilogue.
11569 This allows the optimizer to omit jumps to jumps if no stack
11573 mips_can_use_return_insn (void)
11575 /* Interrupt handlers need to go through the epilogue. */
11576 if (cfun
->machine
->interrupt_handler_p
)
11579 if (!reload_completed
)
11585 /* In MIPS16 mode, a function that returns a floating-point value
11586 needs to arrange to copy the return value into the floating-point
11588 if (mips16_cfun_returns_in_fpr_p ())
11591 return cfun
->machine
->frame
.total_size
== 0;
11594 /* Return true if register REGNO can store a value of mode MODE.
11595 The result of this function is cached in mips_hard_regno_mode_ok. */
11598 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11601 enum mode_class mclass
;
11603 if (mode
== CCV2mode
)
11604 return (ISA_HAS_8CC
11605 && ST_REG_P (regno
)
11606 && (regno
- ST_REG_FIRST
) % 2 == 0);
11608 if (mode
== CCV4mode
)
11609 return (ISA_HAS_8CC
11610 && ST_REG_P (regno
)
11611 && (regno
- ST_REG_FIRST
) % 4 == 0);
11613 if (mode
== CCmode
)
11614 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11616 size
= GET_MODE_SIZE (mode
);
11617 mclass
= GET_MODE_CLASS (mode
);
11619 if (GP_REG_P (regno
))
11620 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11622 if (FP_REG_P (regno
)
11623 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11624 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11626 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11627 if (TARGET_LOONGSON_VECTORS
11628 && (mode
== V2SImode
11629 || mode
== V4HImode
11630 || mode
== V8QImode
11631 || mode
== DImode
))
11634 if (mclass
== MODE_FLOAT
11635 || mclass
== MODE_COMPLEX_FLOAT
11636 || mclass
== MODE_VECTOR_FLOAT
)
11637 return size
<= UNITS_PER_FPVALUE
;
11639 /* Allow integer modes that fit into a single register. We need
11640 to put integers into FPRs when using instructions like CVT
11641 and TRUNC. There's no point allowing sizes smaller than a word,
11642 because the FPU has no appropriate load/store instructions. */
11643 if (mclass
== MODE_INT
)
11644 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11647 if (ACC_REG_P (regno
)
11648 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11650 if (MD_REG_P (regno
))
11652 /* After a multiplication or division, clobbering HI makes
11653 the value of LO unpredictable, and vice versa. This means
11654 that, for all interesting cases, HI and LO are effectively
11657 We model this by requiring that any value that uses HI
11659 if (size
<= UNITS_PER_WORD
* 2)
11660 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11664 /* DSP accumulators do not have the same restrictions as
11665 HI and LO, so we can treat them as normal doubleword
11667 if (size
<= UNITS_PER_WORD
)
11670 if (size
<= UNITS_PER_WORD
* 2
11671 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11676 if (ALL_COP_REG_P (regno
))
11677 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11679 if (regno
== GOT_VERSION_REGNUM
)
11680 return mode
== SImode
;
11685 /* Implement HARD_REGNO_NREGS. */
11688 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11690 if (ST_REG_P (regno
))
11691 /* The size of FP status registers is always 4, because they only hold
11692 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11693 return (GET_MODE_SIZE (mode
) + 3) / 4;
11695 if (FP_REG_P (regno
))
11696 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11698 /* All other registers are word-sized. */
11699 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11702 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11703 in mips_hard_regno_nregs. */
11706 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11712 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11713 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11715 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11716 size
= MIN (size
, 4);
11717 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11719 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11721 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11722 size
= MIN (size
, UNITS_PER_FPREG
);
11723 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11725 if (!hard_reg_set_empty_p (left
))
11726 size
= MIN (size
, UNITS_PER_WORD
);
11727 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11730 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11733 mips_cannot_change_mode_class (enum machine_mode from
,
11734 enum machine_mode to
,
11735 enum reg_class rclass
)
11737 /* Allow conversions between different Loongson integer vectors,
11738 and between those vectors and DImode. */
11739 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11740 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11743 /* Otherwise, there are several problems with changing the modes of
11744 values in floating-point registers:
11746 - When a multi-word value is stored in paired floating-point
11747 registers, the first register always holds the low word. We
11748 therefore can't allow FPRs to change between single-word and
11749 multi-word modes on big-endian targets.
11751 - GCC assumes that each word of a multiword register can be
11752 accessed individually using SUBREGs. This is not true for
11753 floating-point registers if they are bigger than a word.
11755 - Loading a 32-bit value into a 64-bit floating-point register
11756 will not sign-extend the value, despite what LOAD_EXTEND_OP
11757 says. We can't allow FPRs to change from SImode to a wider
11758 mode on 64-bit targets.
11760 - If the FPU has already interpreted a value in one format, we
11761 must not ask it to treat the value as having a different
11764 We therefore disallow all mode changes involving FPRs. */
11766 return reg_classes_intersect_p (FP_REGS
, rclass
);
11769 /* Implement target hook small_register_classes_for_mode_p. */
11772 mips_small_register_classes_for_mode_p (enum machine_mode mode
11775 return TARGET_MIPS16
;
11778 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11781 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11786 return TARGET_HARD_FLOAT
;
11789 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11792 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11799 /* Implement MODES_TIEABLE_P. */
11802 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11804 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11805 prefer to put one of them in FPRs. */
11806 return (mode1
== mode2
11807 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11808 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11811 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11814 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11816 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11819 if (reg_class_subset_p (FP_REGS
, rclass
)
11820 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11823 if (reg_class_subset_p (GR_REGS
, rclass
))
11826 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11832 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11833 Return a "canonical" class to represent it in later calculations. */
11836 mips_canonicalize_move_class (reg_class_t rclass
)
11838 /* All moves involving accumulator registers have the same cost. */
11839 if (reg_class_subset_p (rclass
, ACC_REGS
))
11842 /* Likewise promote subclasses of general registers to the most
11843 interesting containing class. */
11844 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11846 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11847 rclass
= GENERAL_REGS
;
11852 /* Return the cost of moving a value of mode MODE from a register of
11853 class FROM to a GPR. Return 0 for classes that are unions of other
11854 classes handled by this function. */
11857 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11863 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11867 /* MFLO and MFHI. */
11875 /* LUI followed by MOVF. */
11881 /* This choice of value is historical. */
11889 /* Return the cost of moving a value of mode MODE from a GPR to a
11890 register of class TO. Return 0 for classes that are unions of
11891 other classes handled by this function. */
11894 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11899 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11903 /* MTLO and MTHI. */
11911 /* A secondary reload through an FPR scratch. */
11912 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11913 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11918 /* This choice of value is historical. */
11926 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11927 maximum of the move costs for subclasses; regclass will work out
11928 the maximum for us. */
11931 mips_register_move_cost (enum machine_mode mode
,
11932 reg_class_t from
, reg_class_t to
)
11937 from
= mips_canonicalize_move_class (from
);
11938 to
= mips_canonicalize_move_class (to
);
11940 /* Handle moves that can be done without using general-purpose registers. */
11941 if (from
== FP_REGS
)
11943 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11947 /* The sequence generated by mips_expand_fcc_reload. */
11951 /* Handle cases in which only one class deviates from the ideal. */
11952 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11954 return mips_move_from_gpr_cost (mode
, to
);
11956 return mips_move_to_gpr_cost (mode
, from
);
11958 /* Handles cases that require a GPR temporary. */
11959 cost1
= mips_move_to_gpr_cost (mode
, from
);
11962 cost2
= mips_move_from_gpr_cost (mode
, to
);
11964 return cost1
+ cost2
;
11970 /* Implement TARGET_MEMORY_MOVE_COST. */
11973 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11975 return (mips_cost
->memory_latency
11976 + memory_move_secondary_cost (mode
, rclass
, in
));
11979 /* Return the register class required for a secondary register when
11980 copying between one of the registers in RCLASS and value X, which
11981 has mode MODE. X is the source of the move if IN_P, otherwise it
11982 is the destination. Return NO_REGS if no secondary register is
11986 mips_secondary_reload_class (enum reg_class rclass
,
11987 enum machine_mode mode
, rtx x
, bool in_p
)
11991 /* If X is a constant that cannot be loaded into $25, it must be loaded
11992 into some other GPR. No other register class allows a direct move. */
11993 if (mips_dangerous_for_la25_p (x
))
11994 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11996 regno
= true_regnum (x
);
11999 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12000 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12006 /* Copying from accumulator registers to anywhere other than a general
12007 register requires a temporary general register. */
12008 if (reg_class_subset_p (rclass
, ACC_REGS
))
12009 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12010 if (ACC_REG_P (regno
))
12011 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12013 /* We can only copy a value to a condition code register from a
12014 floating-point register, and even then we require a scratch
12015 floating-point register. We can only copy a value out of a
12016 condition-code register into a general register. */
12017 if (reg_class_subset_p (rclass
, ST_REGS
))
12021 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12023 if (ST_REG_P (regno
))
12027 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12030 if (reg_class_subset_p (rclass
, FP_REGS
))
12033 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12034 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12035 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12038 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12039 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12042 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12043 /* We can force the constant to memory and use lwc1
12044 and ldc1. As above, we will use pairs of lwc1s if
12045 ldc1 is not supported. */
12048 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12049 /* In this case we can use mov.fmt. */
12052 /* Otherwise, we need to reload through an integer register. */
12055 if (FP_REG_P (regno
))
12056 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12061 /* Implement TARGET_MODE_REP_EXTENDED. */
12064 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12066 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12067 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12068 return SIGN_EXTEND
;
12073 /* Implement TARGET_VALID_POINTER_MODE. */
12076 mips_valid_pointer_mode (enum machine_mode mode
)
12078 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12081 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12084 mips_vector_mode_supported_p (enum machine_mode mode
)
12089 return TARGET_PAIRED_SINGLE_FLOAT
;
12104 return TARGET_LOONGSON_VECTORS
;
12111 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12114 mips_scalar_mode_supported_p (enum machine_mode mode
)
12116 if (ALL_FIXED_POINT_MODE_P (mode
)
12117 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12120 return default_scalar_mode_supported_p (mode
);
12123 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12125 static enum machine_mode
12126 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12128 if (TARGET_PAIRED_SINGLE_FLOAT
12134 /* Implement TARGET_INIT_LIBFUNCS. */
12137 mips_init_libfuncs (void)
12139 if (TARGET_FIX_VR4120
)
12141 /* Register the special divsi3 and modsi3 functions needed to work
12142 around VR4120 division errata. */
12143 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12144 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12147 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12149 /* Register the MIPS16 -mhard-float stubs. */
12150 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12151 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12152 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12153 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12155 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12156 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12157 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12158 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12159 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12160 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12161 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12163 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12164 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12165 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12167 if (TARGET_DOUBLE_FLOAT
)
12169 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12170 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12171 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12172 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12174 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12175 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12176 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12177 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12178 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12179 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12180 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12182 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12183 "__mips16_extendsfdf2");
12184 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12185 "__mips16_truncdfsf2");
12186 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12187 "__mips16_fix_truncdfsi");
12188 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12189 "__mips16_floatsidf");
12190 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12191 "__mips16_floatunsidf");
12195 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12196 on an external non-MIPS16 routine to implement __sync_synchronize.
12197 Similarly for the rest of the ll/sc libfuncs. */
12200 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12201 init_sync_libfuncs (UNITS_PER_WORD
);
12205 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12208 mips_process_load_label (rtx target
)
12210 rtx base
, gp
, intop
;
12211 HOST_WIDE_INT offset
;
12213 mips_multi_start ();
12217 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12218 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12222 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12223 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12227 gp
= pic_offset_table_rtx
;
12228 if (mips_cfun_has_cprestore_slot_p ())
12230 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12231 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12232 if (!SMALL_OPERAND (offset
))
12234 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12235 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12236 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12239 offset
= CONST_LOW_PART (offset
);
12241 intop
= GEN_INT (offset
);
12242 if (ISA_HAS_LOAD_DELAY
)
12243 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12245 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12247 if (ISA_HAS_LOAD_DELAY
)
12248 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12250 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12251 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12256 /* Return the number of instructions needed to load a label into $AT. */
12258 static unsigned int
12259 mips_load_label_num_insns (void)
12261 if (cfun
->machine
->load_label_num_insns
== 0)
12263 mips_process_load_label (pc_rtx
);
12264 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12266 return cfun
->machine
->load_label_num_insns
;
12269 /* Emit an asm sequence to start a noat block and load the address
12270 of a label into $1. */
12273 mips_output_load_label (rtx target
)
12275 mips_push_asm_switch (&mips_noat
);
12276 if (TARGET_EXPLICIT_RELOCS
)
12278 mips_process_load_label (target
);
12279 mips_multi_write ();
12283 if (Pmode
== DImode
)
12284 output_asm_insn ("dla\t%@,%0", &target
);
12286 output_asm_insn ("la\t%@,%0", &target
);
12290 /* Return the length of INSN. LENGTH is the initial length computed by
12291 attributes in the machine-description file. */
12294 mips_adjust_insn_length (rtx insn
, int length
)
12296 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12297 of a PIC long-branch sequence. Substitute the correct value. */
12298 if (length
== MAX_PIC_BRANCH_LENGTH
12299 && INSN_CODE (insn
) >= 0
12300 && get_attr_type (insn
) == TYPE_BRANCH
)
12302 /* Add the branch-over instruction and its delay slot, if this
12303 is a conditional branch. */
12304 length
= simplejump_p (insn
) ? 0 : 8;
12306 /* Add the size of a load into $AT. */
12307 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12309 /* Add the length of an indirect jump, ignoring the delay slot. */
12310 length
+= TARGET_COMPRESSION
? 2 : 4;
12313 /* A unconditional jump has an unfilled delay slot if it is not part
12314 of a sequence. A conditional jump normally has a delay slot, but
12315 does not on MIPS16. */
12316 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12317 length
+= TARGET_MIPS16
? 2 : 4;
12319 /* See how many nops might be needed to avoid hardware hazards. */
12320 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
12321 switch (get_attr_hazard (insn
))
12327 length
+= NOP_INSN_LENGTH
;
12331 length
+= NOP_INSN_LENGTH
* 2;
12338 /* Return the assembly code for INSN, which has the operands given by
12339 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12340 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12341 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12342 version of BRANCH_IF_TRUE. */
12345 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12346 const char *branch_if_true
,
12347 const char *branch_if_false
)
12349 unsigned int length
;
12350 rtx taken
, not_taken
;
12352 gcc_assert (LABEL_P (operands
[0]));
12354 length
= get_attr_length (insn
);
12357 /* Just a simple conditional branch. */
12358 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12359 return branch_if_true
;
12362 /* Generate a reversed branch around a direct jump. This fallback does
12363 not use branch-likely instructions. */
12364 mips_branch_likely
= false;
12365 not_taken
= gen_label_rtx ();
12366 taken
= operands
[0];
12368 /* Generate the reversed branch to NOT_TAKEN. */
12369 operands
[0] = not_taken
;
12370 output_asm_insn (branch_if_false
, operands
);
12372 /* If INSN has a delay slot, we must provide delay slots for both the
12373 branch to NOT_TAKEN and the conditional jump. We must also ensure
12374 that INSN's delay slot is executed in the appropriate cases. */
12375 if (final_sequence
)
12377 /* This first delay slot will always be executed, so use INSN's
12378 delay slot if is not annulled. */
12379 if (!INSN_ANNULLED_BRANCH_P (insn
))
12381 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12382 asm_out_file
, optimize
, 1, NULL
);
12383 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12386 output_asm_insn ("nop", 0);
12387 fprintf (asm_out_file
, "\n");
12390 /* Output the unconditional branch to TAKEN. */
12391 if (TARGET_ABSOLUTE_JUMPS
)
12392 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12395 mips_output_load_label (taken
);
12396 output_asm_insn ("jr\t%@%]%/", 0);
12399 /* Now deal with its delay slot; see above. */
12400 if (final_sequence
)
12402 /* This delay slot will only be executed if the branch is taken.
12403 Use INSN's delay slot if is annulled. */
12404 if (INSN_ANNULLED_BRANCH_P (insn
))
12406 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12407 asm_out_file
, optimize
, 1, NULL
);
12408 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12411 output_asm_insn ("nop", 0);
12412 fprintf (asm_out_file
, "\n");
12415 /* Output NOT_TAKEN. */
12416 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12417 CODE_LABEL_NUMBER (not_taken
));
12421 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12422 if some ordering condition is true. The condition is given by
12423 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12424 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12425 its second is always zero. */
12428 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12430 const char *branch
[2];
12432 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12433 Make BRANCH[0] branch on the inverse condition. */
12434 switch (GET_CODE (operands
[1]))
12436 /* These cases are equivalent to comparisons against zero. */
12438 inverted_p
= !inverted_p
;
12439 /* Fall through. */
12441 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12442 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12445 /* These cases are always true or always false. */
12447 inverted_p
= !inverted_p
;
12448 /* Fall through. */
12450 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12451 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12455 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12456 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12459 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12462 /* Start a block of code that needs access to the LL, SC and SYNC
12466 mips_start_ll_sc_sync_block (void)
12468 if (!ISA_HAS_LL_SC
)
12470 output_asm_insn (".set\tpush", 0);
12472 output_asm_insn (".set\tmips3", 0);
12474 output_asm_insn (".set\tmips2", 0);
12478 /* End a block started by mips_start_ll_sc_sync_block. */
12481 mips_end_ll_sc_sync_block (void)
12483 if (!ISA_HAS_LL_SC
)
12484 output_asm_insn (".set\tpop", 0);
12487 /* Output and/or return the asm template for a sync instruction. */
12490 mips_output_sync (void)
12492 mips_start_ll_sc_sync_block ();
12493 output_asm_insn ("sync", 0);
12494 mips_end_ll_sc_sync_block ();
12498 /* Return the asm template associated with sync_insn1 value TYPE.
12499 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12501 static const char *
12502 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12506 case SYNC_INSN1_MOVE
:
12507 return "move\t%0,%z2";
12508 case SYNC_INSN1_LI
:
12509 return "li\t%0,%2";
12510 case SYNC_INSN1_ADDU
:
12511 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12512 case SYNC_INSN1_ADDIU
:
12513 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12514 case SYNC_INSN1_SUBU
:
12515 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12516 case SYNC_INSN1_AND
:
12517 return "and\t%0,%1,%z2";
12518 case SYNC_INSN1_ANDI
:
12519 return "andi\t%0,%1,%2";
12520 case SYNC_INSN1_OR
:
12521 return "or\t%0,%1,%z2";
12522 case SYNC_INSN1_ORI
:
12523 return "ori\t%0,%1,%2";
12524 case SYNC_INSN1_XOR
:
12525 return "xor\t%0,%1,%z2";
12526 case SYNC_INSN1_XORI
:
12527 return "xori\t%0,%1,%2";
12529 gcc_unreachable ();
12532 /* Return the asm template associated with sync_insn2 value TYPE. */
12534 static const char *
12535 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12539 case SYNC_INSN2_NOP
:
12540 gcc_unreachable ();
12541 case SYNC_INSN2_AND
:
12542 return "and\t%0,%1,%z2";
12543 case SYNC_INSN2_XOR
:
12544 return "xor\t%0,%1,%z2";
12545 case SYNC_INSN2_NOT
:
12546 return "nor\t%0,%1,%.";
12548 gcc_unreachable ();
12551 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12552 the value of the one of the sync_* attributes. Return the operand
12553 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12554 have the associated attribute. */
12557 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12560 default_value
= operands
[index
- 1];
12561 return default_value
;
12564 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12565 sequence for it. */
12568 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12570 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12571 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12572 unsigned int tmp3_insn
;
12573 enum attr_sync_insn1 insn1
;
12574 enum attr_sync_insn2 insn2
;
12577 enum memmodel model
;
12579 /* Read an operand from the sync_WHAT attribute and store it in
12580 variable WHAT. DEFAULT is the default value if no attribute
12582 #define READ_OPERAND(WHAT, DEFAULT) \
12583 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12586 /* Read the memory. */
12587 READ_OPERAND (mem
, 0);
12589 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12591 /* Read the other attributes. */
12592 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12593 READ_OPERAND (oldval
, at
);
12594 READ_OPERAND (cmp
, 0);
12595 READ_OPERAND (newval
, at
);
12596 READ_OPERAND (inclusive_mask
, 0);
12597 READ_OPERAND (exclusive_mask
, 0);
12598 READ_OPERAND (required_oldval
, 0);
12599 READ_OPERAND (insn1_op2
, 0);
12600 insn1
= get_attr_sync_insn1 (insn
);
12601 insn2
= get_attr_sync_insn2 (insn
);
12603 /* Don't bother setting CMP result that is never used. */
12604 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12607 memmodel_attr
= get_attr_sync_memmodel (insn
);
12608 switch (memmodel_attr
)
12611 model
= MEMMODEL_ACQ_REL
;
12614 model
= MEMMODEL_ACQUIRE
;
12617 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12620 mips_multi_start ();
12622 /* Output the release side of the memory barrier. */
12623 if (need_atomic_barrier_p (model
, true))
12625 if (required_oldval
== 0 && TARGET_OCTEON
)
12627 /* Octeon doesn't reorder reads, so a full barrier can be
12628 created by using SYNCW to order writes combined with the
12629 write from the following SC. When the SC successfully
12630 completes, we know that all preceding writes are also
12631 committed to the coherent memory system. It is possible
12632 for a single SYNCW to fail, but a pair of them will never
12633 fail, so we use two. */
12634 mips_multi_add_insn ("syncw", NULL
);
12635 mips_multi_add_insn ("syncw", NULL
);
12638 mips_multi_add_insn ("sync", NULL
);
12641 /* Output the branch-back label. */
12642 mips_multi_add_label ("1:");
12644 /* OLDVAL = *MEM. */
12645 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12646 oldval
, mem
, NULL
);
12648 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12649 if (required_oldval
)
12651 if (inclusive_mask
== 0)
12655 gcc_assert (oldval
!= at
);
12656 mips_multi_add_insn ("and\t%0,%1,%2",
12657 at
, oldval
, inclusive_mask
, NULL
);
12660 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12662 /* CMP = 0 [delay slot]. */
12664 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12667 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12668 if (exclusive_mask
== 0)
12672 gcc_assert (oldval
!= at
);
12673 mips_multi_add_insn ("and\t%0,%1,%z2",
12674 at
, oldval
, exclusive_mask
, NULL
);
12678 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12680 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12681 at least one instruction in that case. */
12682 if (insn1
== SYNC_INSN1_MOVE
12683 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12687 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12688 newval
, oldval
, insn1_op2
, NULL
);
12692 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12693 if (insn2
== SYNC_INSN2_NOP
)
12697 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12698 newval
, tmp2
, inclusive_mask
, NULL
);
12701 tmp3_insn
= mips_multi_last_index ();
12703 /* $AT = $TMP1 | $TMP3. */
12704 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12706 mips_multi_set_operand (tmp3_insn
, 0, at
);
12711 gcc_assert (tmp1
!= tmp3
);
12712 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12715 /* if (!commit (*MEM = $AT)) goto 1.
12717 This will sometimes be a delayed branch; see the write code below
12719 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12720 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12722 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12723 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12725 mips_multi_copy_insn (tmp3_insn
);
12726 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12728 else if (!(required_oldval
&& cmp
))
12729 mips_multi_add_insn ("nop", NULL
);
12731 /* CMP = 1 -- either standalone or in a delay slot. */
12732 if (required_oldval
&& cmp
)
12733 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12735 /* Output the acquire side of the memory barrier. */
12736 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12737 mips_multi_add_insn ("sync", NULL
);
12739 /* Output the exit label, if needed. */
12740 if (required_oldval
)
12741 mips_multi_add_label ("2:");
12743 #undef READ_OPERAND
12746 /* Output and/or return the asm template for sync loop INSN, which has
12747 the operands given by OPERANDS. */
12750 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12752 mips_process_sync_loop (insn
, operands
);
12754 /* Use branch-likely instructions to work around the LL/SC R10000
12756 mips_branch_likely
= TARGET_FIX_R10000
;
12758 mips_push_asm_switch (&mips_noreorder
);
12759 mips_push_asm_switch (&mips_nomacro
);
12760 mips_push_asm_switch (&mips_noat
);
12761 mips_start_ll_sc_sync_block ();
12763 mips_multi_write ();
12765 mips_end_ll_sc_sync_block ();
12766 mips_pop_asm_switch (&mips_noat
);
12767 mips_pop_asm_switch (&mips_nomacro
);
12768 mips_pop_asm_switch (&mips_noreorder
);
12773 /* Return the number of individual instructions in sync loop INSN,
12774 which has the operands given by OPERANDS. */
12777 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12779 mips_process_sync_loop (insn
, operands
);
12780 return mips_multi_num_insns
;
12783 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12784 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12786 When working around R4000 and R4400 errata, we need to make sure that
12787 the division is not immediately followed by a shift[1][2]. We also
12788 need to stop the division from being put into a branch delay slot[3].
12789 The easiest way to avoid both problems is to add a nop after the
12790 division. When a divide-by-zero check is needed, this nop can be
12791 used to fill the branch delay slot.
12793 [1] If a double-word or a variable shift executes immediately
12794 after starting an integer division, the shift may give an
12795 incorrect result. See quotations of errata #16 and #28 from
12796 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12797 in mips.md for details.
12799 [2] A similar bug to [1] exists for all revisions of the
12800 R4000 and the R4400 when run in an MC configuration.
12801 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12803 "19. In this following sequence:
12805 ddiv (or ddivu or div or divu)
12806 dsll32 (or dsrl32, dsra32)
12808 if an MPT stall occurs, while the divide is slipping the cpu
12809 pipeline, then the following double shift would end up with an
12812 Workaround: The compiler needs to avoid generating any
12813 sequence with divide followed by extended double shift."
12815 This erratum is also present in "MIPS R4400MC Errata, Processor
12816 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12817 & 3.0" as errata #10 and #4, respectively.
12819 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12820 (also valid for MIPS R4000MC processors):
12822 "52. R4000SC: This bug does not apply for the R4000PC.
12824 There are two flavors of this bug:
12826 1) If the instruction just after divide takes an RF exception
12827 (tlb-refill, tlb-invalid) and gets an instruction cache
12828 miss (both primary and secondary) and the line which is
12829 currently in secondary cache at this index had the first
12830 data word, where the bits 5..2 are set, then R4000 would
12831 get a wrong result for the div.
12836 ------------------- # end-of page. -tlb-refill
12841 ------------------- # end-of page. -tlb-invalid
12844 2) If the divide is in the taken branch delay slot, where the
12845 target takes RF exception and gets an I-cache miss for the
12846 exception vector or where I-cache miss occurs for the
12847 target address, under the above mentioned scenarios, the
12848 div would get wrong results.
12851 j r2 # to next page mapped or unmapped
12852 div r8,r9 # this bug would be there as long
12853 # as there is an ICache miss and
12854 nop # the "data pattern" is present
12857 beq r0, r0, NextPage # to Next page
12861 This bug is present for div, divu, ddiv, and ddivu
12864 Workaround: For item 1), OS could make sure that the next page
12865 after the divide instruction is also mapped. For item 2), the
12866 compiler could make sure that the divide instruction is not in
12867 the branch delay slot."
12869 These processors have PRId values of 0x00004220 and 0x00004300 for
12870 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12873 mips_output_division (const char *division
, rtx
*operands
)
12878 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12880 output_asm_insn (s
, operands
);
12883 if (TARGET_CHECK_ZERO_DIV
)
12887 output_asm_insn (s
, operands
);
12888 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12890 else if (GENERATE_DIVIDE_TRAPS
)
12892 /* Avoid long replay penalty on load miss by putting the trap before
12895 output_asm_insn ("teq\t%2,%.,7", operands
);
12898 output_asm_insn (s
, operands
);
12899 s
= "teq\t%2,%.,7";
12904 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12905 output_asm_insn (s
, operands
);
12906 s
= "break\t7%)\n1:";
12912 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12913 instruction and if OUT_INSN assigns to the accumulator operand. */
12916 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12918 enum attr_accum_in accum_in
;
12919 int accum_in_opnum
;
12922 if (recog_memoized (in_insn
) < 0)
12925 accum_in
= get_attr_accum_in (in_insn
);
12926 if (accum_in
== ACCUM_IN_NONE
)
12929 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12931 extract_insn (in_insn
);
12932 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12933 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12935 return reg_set_p (accum_in_op
, out_insn
);
12938 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12939 data rather than the address. We need this because the cprestore
12940 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12941 which causes the default routine to abort. We just return false
12945 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12947 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12950 return !store_data_bypass_p (out_insn
, in_insn
);
12954 /* Variables and flags used in scheduler hooks when tuning for
12958 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12961 /* If true, then next ALU1/2 instruction will go to ALU1. */
12964 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12967 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12968 int alu1_core_unit_code
;
12969 int alu2_core_unit_code
;
12970 int falu1_core_unit_code
;
12971 int falu2_core_unit_code
;
12973 /* True if current cycle has a multi instruction.
12974 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12975 bool cycle_has_multi_p
;
12977 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12978 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12980 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12981 instruction to go ALU1. */
12982 rtx alu1_turn_enabled_insn
;
12983 rtx alu2_turn_enabled_insn
;
12984 rtx falu1_turn_enabled_insn
;
12985 rtx falu2_turn_enabled_insn
;
12988 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12989 dependencies have no cost, except on the 20Kc where output-dependence
12990 is treated like input-dependence. */
12993 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12994 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12996 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
12999 if (REG_NOTE_KIND (link
) != 0)
13004 /* Return the number of instructions that can be issued per cycle. */
13007 mips_issue_rate (void)
13011 case PROCESSOR_74KC
:
13012 case PROCESSOR_74KF2_1
:
13013 case PROCESSOR_74KF1_1
:
13014 case PROCESSOR_74KF3_2
:
13015 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13016 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13017 but in reality only a maximum of 3 insns can be issued as
13018 floating-point loads and stores also require a slot in the
13020 case PROCESSOR_R10000
:
13021 /* All R10K Processors are quad-issue (being the first MIPS
13022 processors to support this feature). */
13025 case PROCESSOR_20KC
:
13026 case PROCESSOR_R4130
:
13027 case PROCESSOR_R5400
:
13028 case PROCESSOR_R5500
:
13029 case PROCESSOR_R5900
:
13030 case PROCESSOR_R7000
:
13031 case PROCESSOR_R9000
:
13032 case PROCESSOR_OCTEON
:
13033 case PROCESSOR_OCTEON2
:
13036 case PROCESSOR_SB1
:
13037 case PROCESSOR_SB1A
:
13038 /* This is actually 4, but we get better performance if we claim 3.
13039 This is partly because of unwanted speculative code motion with the
13040 larger number, and partly because in most common cases we can't
13041 reach the theoretical max of 4. */
13044 case PROCESSOR_LOONGSON_2E
:
13045 case PROCESSOR_LOONGSON_2F
:
13046 case PROCESSOR_LOONGSON_3A
:
13049 case PROCESSOR_XLP
:
13050 return (reload_completed
? 4 : 3);
13057 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13060 mips_ls2_init_dfa_post_cycle_insn (void)
13063 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13064 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13068 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13069 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13073 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13074 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13078 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13079 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13082 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13083 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13084 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13085 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13088 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13089 Init data used in mips_dfa_post_advance_cycle. */
13092 mips_init_dfa_post_cycle_insn (void)
13094 if (TUNE_LOONGSON_2EF
)
13095 mips_ls2_init_dfa_post_cycle_insn ();
13098 /* Initialize STATE when scheduling for Loongson 2E/2F.
13099 Support round-robin dispatch scheme by enabling only one of
13100 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13104 mips_ls2_dfa_post_advance_cycle (state_t state
)
13106 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13108 /* Though there are no non-pipelined ALU1 insns,
13109 we can get an instruction of type 'multi' before reload. */
13110 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13111 mips_ls2
.alu1_turn_p
= false;
13114 mips_ls2
.cycle_has_multi_p
= false;
13116 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13117 /* We have a non-pipelined alu instruction in the core,
13118 adjust round-robin counter. */
13119 mips_ls2
.alu1_turn_p
= true;
13121 if (mips_ls2
.alu1_turn_p
)
13123 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13124 gcc_unreachable ();
13128 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13129 gcc_unreachable ();
13132 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13134 /* There are no non-pipelined FALU1 insns. */
13135 gcc_unreachable ();
13136 mips_ls2
.falu1_turn_p
= false;
13139 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13140 /* We have a non-pipelined falu instruction in the core,
13141 adjust round-robin counter. */
13142 mips_ls2
.falu1_turn_p
= true;
13144 if (mips_ls2
.falu1_turn_p
)
13146 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13147 gcc_unreachable ();
13151 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13152 gcc_unreachable ();
13156 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13157 This hook is being called at the start of each cycle. */
13160 mips_dfa_post_advance_cycle (void)
13162 if (TUNE_LOONGSON_2EF
)
13163 mips_ls2_dfa_post_advance_cycle (curr_state
);
13166 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13167 be as wide as the scheduling freedom in the DFA. */
13170 mips_multipass_dfa_lookahead (void)
13172 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13176 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13185 /* Remove the instruction at index LOWER from ready queue READY and
13186 reinsert it in front of the instruction at index HIGHER. LOWER must
13190 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13195 new_head
= ready
[lower
];
13196 for (i
= lower
; i
< higher
; i
++)
13197 ready
[i
] = ready
[i
+ 1];
13198 ready
[i
] = new_head
;
13201 /* If the priority of the instruction at POS2 in the ready queue READY
13202 is within LIMIT units of that of the instruction at POS1, swap the
13203 instructions if POS2 is not already less than POS1. */
13206 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13209 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13213 temp
= ready
[pos1
];
13214 ready
[pos1
] = ready
[pos2
];
13215 ready
[pos2
] = temp
;
13219 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13220 that may clobber hi or lo. */
13221 static rtx mips_macc_chains_last_hilo
;
13223 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13224 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13227 mips_macc_chains_record (rtx insn
)
13229 if (get_attr_may_clobber_hilo (insn
))
13230 mips_macc_chains_last_hilo
= insn
;
13233 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13234 has NREADY elements, looking for a multiply-add or multiply-subtract
13235 instruction that is cumulative with mips_macc_chains_last_hilo.
13236 If there is one, promote it ahead of anything else that might
13237 clobber hi or lo. */
13240 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13244 if (mips_macc_chains_last_hilo
!= 0)
13245 for (i
= nready
- 1; i
>= 0; i
--)
13246 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13248 for (j
= nready
- 1; j
> i
; j
--)
13249 if (recog_memoized (ready
[j
]) >= 0
13250 && get_attr_may_clobber_hilo (ready
[j
]))
13252 mips_promote_ready (ready
, i
, j
);
13259 /* The last instruction to be scheduled. */
13260 static rtx vr4130_last_insn
;
13262 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13263 points to an rtx that is initially an instruction. Nullify the rtx
13264 if the instruction uses the value of register X. */
13267 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13272 insn_ptr
= (rtx
*) data
;
13275 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13279 /* Return true if there is true register dependence between vr4130_last_insn
13283 vr4130_true_reg_dependence_p (rtx insn
)
13285 note_stores (PATTERN (vr4130_last_insn
),
13286 vr4130_true_reg_dependence_p_1
, &insn
);
13290 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13291 the ready queue and that INSN2 is the instruction after it, return
13292 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13293 in which INSN1 and INSN2 can probably issue in parallel, but for
13294 which (INSN2, INSN1) should be less sensitive to instruction
13295 alignment than (INSN1, INSN2). See 4130.md for more details. */
13298 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13300 sd_iterator_def sd_it
;
13303 /* Check for the following case:
13305 1) there is some other instruction X with an anti dependence on INSN1;
13306 2) X has a higher priority than INSN2; and
13307 3) X is an arithmetic instruction (and thus has no unit restrictions).
13309 If INSN1 is the last instruction blocking X, it would better to
13310 choose (INSN1, X) over (INSN2, INSN1). */
13311 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13312 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13313 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13314 && recog_memoized (DEP_CON (dep
)) >= 0
13315 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13318 if (vr4130_last_insn
!= 0
13319 && recog_memoized (insn1
) >= 0
13320 && recog_memoized (insn2
) >= 0)
13322 /* See whether INSN1 and INSN2 use different execution units,
13323 or if they are both ALU-type instructions. If so, they can
13324 probably execute in parallel. */
13325 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13326 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13327 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13329 /* If only one of the instructions has a dependence on
13330 vr4130_last_insn, prefer to schedule the other one first. */
13331 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13332 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13333 if (dep1_p
!= dep2_p
)
13336 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13337 is not an ALU-type instruction and if INSN1 uses the same
13338 execution unit. (Note that if this condition holds, we already
13339 know that INSN2 uses a different execution unit.) */
13340 if (class1
!= VR4130_CLASS_ALU
13341 && recog_memoized (vr4130_last_insn
) >= 0
13342 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13349 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13350 queue with at least two instructions. Swap the first two if
13351 vr4130_swap_insns_p says that it could be worthwhile. */
13354 vr4130_reorder (rtx
*ready
, int nready
)
13356 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13357 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13360 /* Record whether last 74k AGEN instruction was a load or store. */
13361 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13363 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13364 resets to TYPE_UNKNOWN state. */
13367 mips_74k_agen_init (rtx insn
)
13369 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13370 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13373 enum attr_type type
= get_attr_type (insn
);
13374 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13375 mips_last_74k_agen_insn
= type
;
13379 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13380 loads to be grouped together, and multiple stores to be grouped
13381 together. Swap things around in the ready queue to make this happen. */
13384 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13387 int store_pos
, load_pos
;
13392 for (i
= nready
- 1; i
>= 0; i
--)
13394 rtx insn
= ready
[i
];
13395 if (USEFUL_INSN_P (insn
))
13396 switch (get_attr_type (insn
))
13399 if (store_pos
== -1)
13404 if (load_pos
== -1)
13413 if (load_pos
== -1 || store_pos
== -1)
13416 switch (mips_last_74k_agen_insn
)
13419 /* Prefer to schedule loads since they have a higher latency. */
13421 /* Swap loads to the front of the queue. */
13422 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13425 /* Swap stores to the front of the queue. */
13426 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13433 /* Implement TARGET_SCHED_INIT. */
13436 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13437 int max_ready ATTRIBUTE_UNUSED
)
13439 mips_macc_chains_last_hilo
= 0;
13440 vr4130_last_insn
= 0;
13441 mips_74k_agen_init (NULL_RTX
);
13443 /* When scheduling for Loongson2, branch instructions go to ALU1,
13444 therefore basic block is most likely to start with round-robin counter
13445 pointed to ALU2. */
13446 mips_ls2
.alu1_turn_p
= false;
13447 mips_ls2
.falu1_turn_p
= true;
13450 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13453 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13454 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13456 if (!reload_completed
13457 && TUNE_MACC_CHAINS
13459 mips_macc_chains_reorder (ready
, *nreadyp
);
13461 if (reload_completed
13463 && !TARGET_VR4130_ALIGN
13465 vr4130_reorder (ready
, *nreadyp
);
13468 mips_74k_agen_reorder (ready
, *nreadyp
);
13471 /* Implement TARGET_SCHED_REORDER. */
13474 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13475 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13477 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13478 return mips_issue_rate ();
13481 /* Implement TARGET_SCHED_REORDER2. */
13484 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13485 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13487 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13488 return cached_can_issue_more
;
13491 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13494 mips_ls2_variable_issue (rtx insn
)
13496 if (mips_ls2
.alu1_turn_p
)
13498 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13499 mips_ls2
.alu1_turn_p
= false;
13503 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13504 mips_ls2
.alu1_turn_p
= true;
13507 if (mips_ls2
.falu1_turn_p
)
13509 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13510 mips_ls2
.falu1_turn_p
= false;
13514 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13515 mips_ls2
.falu1_turn_p
= true;
13518 if (recog_memoized (insn
) >= 0)
13519 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13522 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13525 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13526 rtx insn
, int more
)
13528 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13529 if (USEFUL_INSN_P (insn
))
13531 if (get_attr_type (insn
) != TYPE_GHOST
)
13533 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13534 mips_macc_chains_record (insn
);
13535 vr4130_last_insn
= insn
;
13537 mips_74k_agen_init (insn
);
13538 else if (TUNE_LOONGSON_2EF
)
13539 mips_ls2_variable_issue (insn
);
13542 /* Instructions of type 'multi' should all be split before
13543 the second scheduling pass. */
13544 gcc_assert (!reload_completed
13545 || recog_memoized (insn
) < 0
13546 || get_attr_type (insn
) != TYPE_MULTI
);
13548 cached_can_issue_more
= more
;
13552 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13553 return the first operand of the associated PREF or PREFX insn. */
13556 mips_prefetch_cookie (rtx write
, rtx locality
)
13558 /* store_streamed / load_streamed. */
13559 if (INTVAL (locality
) <= 0)
13560 return GEN_INT (INTVAL (write
) + 4);
13562 /* store / load. */
13563 if (INTVAL (locality
) <= 2)
13566 /* store_retained / load_retained. */
13567 return GEN_INT (INTVAL (write
) + 6);
13570 /* Flags that indicate when a built-in function is available.
13572 BUILTIN_AVAIL_NON_MIPS16
13573 The function is available on the current target, but only
13574 in non-MIPS16 mode. */
13575 #define BUILTIN_AVAIL_NON_MIPS16 1
13577 /* Declare an availability predicate for built-in functions that
13578 require non-MIPS16 mode and also require COND to be true.
13579 NAME is the main part of the predicate's name. */
13580 #define AVAIL_NON_MIPS16(NAME, COND) \
13581 static unsigned int \
13582 mips_builtin_avail_##NAME (void) \
13584 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13587 /* This structure describes a single built-in function. */
13588 struct mips_builtin_description
{
13589 /* The code of the main .md file instruction. See mips_builtin_type
13590 for more information. */
13591 enum insn_code icode
;
13593 /* The floating-point comparison code to use with ICODE, if any. */
13594 enum mips_fp_condition cond
;
13596 /* The name of the built-in function. */
13599 /* Specifies how the function should be expanded. */
13600 enum mips_builtin_type builtin_type
;
13602 /* The function's prototype. */
13603 enum mips_function_type function_type
;
13605 /* Whether the function is available. */
13606 unsigned int (*avail
) (void);
13609 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13610 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13611 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13612 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13613 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13614 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13615 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13616 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13617 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13618 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13620 /* Construct a mips_builtin_description from the given arguments.
13622 INSN is the name of the associated instruction pattern, without the
13623 leading CODE_FOR_mips_.
13625 CODE is the floating-point condition code associated with the
13626 function. It can be 'f' if the field is not applicable.
13628 NAME is the name of the function itself, without the leading
13631 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13633 AVAIL is the name of the availability predicate, without the leading
13634 mips_builtin_avail_. */
13635 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13636 FUNCTION_TYPE, AVAIL) \
13637 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13638 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13639 mips_builtin_avail_ ## AVAIL }
13641 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13642 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13643 are as for MIPS_BUILTIN. */
13644 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13645 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13647 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13648 are subject to mips_builtin_avail_<AVAIL>. */
13649 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13650 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13651 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13652 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13653 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13655 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13656 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13657 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13658 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13659 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13660 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13662 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13663 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13665 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13666 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13668 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13669 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13672 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13673 are subject to mips_builtin_avail_mips3d. */
13674 #define CMP_4S_BUILTINS(INSN, COND) \
13675 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13676 MIPS_BUILTIN_CMP_ANY, \
13677 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13678 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13679 MIPS_BUILTIN_CMP_ALL, \
13680 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13682 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13683 instruction requires mips_builtin_avail_<AVAIL>. */
13684 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13685 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13686 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13688 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13689 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13692 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13693 #define CMP_BUILTINS(COND) \
13694 MOVTF_BUILTINS (c, COND, paired_single), \
13695 MOVTF_BUILTINS (cabs, COND, mips3d), \
13696 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13697 CMP_PS_BUILTINS (c, COND, paired_single), \
13698 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13699 CMP_4S_BUILTINS (c, COND), \
13700 CMP_4S_BUILTINS (cabs, COND)
13702 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13703 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13704 and AVAIL are as for MIPS_BUILTIN. */
13705 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13706 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13707 FUNCTION_TYPE, AVAIL)
13709 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13710 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13711 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13712 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13713 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13715 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13716 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13717 builtin_description field. */
13718 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13719 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13720 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13721 FUNCTION_TYPE, mips_builtin_avail_loongson }
13723 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13724 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13725 builtin_description field. */
13726 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13727 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13729 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13730 We use functions of this form when the same insn can be usefully applied
13731 to more than one datatype. */
13732 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13733 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13735 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13736 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13737 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13738 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13739 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13740 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13741 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13742 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13744 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13745 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13746 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13747 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13748 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13749 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13750 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13751 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13752 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13753 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13754 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13755 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13756 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13757 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13758 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13759 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13760 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13761 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13762 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13763 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13764 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13765 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13766 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13767 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13768 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13769 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13770 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13771 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13772 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13773 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13775 static const struct mips_builtin_description mips_builtins
[] = {
13776 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13777 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13778 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13779 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13780 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13781 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13782 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13783 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13785 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13786 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13787 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13788 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13789 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13791 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13792 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13793 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13794 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13795 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13796 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13798 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13799 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13800 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13801 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13802 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13803 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13805 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13807 /* Built-in functions for the SB-1 processor. */
13808 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13810 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13811 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13812 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13813 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13814 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13815 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13816 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13817 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13818 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13819 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13820 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13821 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13822 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13823 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13824 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13825 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13826 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13827 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13828 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13829 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13830 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13831 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13832 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13833 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13834 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13835 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13836 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13837 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13838 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13839 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13840 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13841 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13842 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13843 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13844 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13845 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13846 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13847 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13848 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13849 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13850 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13851 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13852 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13853 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13854 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13855 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13856 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13857 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13858 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13859 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13860 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13861 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13862 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13863 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13864 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13865 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13866 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13867 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13868 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13869 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13870 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13871 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13872 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13873 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13874 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13875 BPOSGE_BUILTIN (32, dsp
),
13877 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13878 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13879 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13880 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13881 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13882 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13883 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13884 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13885 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13886 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13887 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13888 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13889 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13890 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13891 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13892 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13893 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13894 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13895 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13896 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13897 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13898 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13899 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13900 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13901 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13902 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13903 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13904 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13905 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13906 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13907 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13908 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13909 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13910 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13911 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13913 /* Built-in functions for the DSP ASE (32-bit only). */
13914 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13915 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13916 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13917 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13918 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13919 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13920 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13921 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13922 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13923 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13924 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13925 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13926 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13927 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13928 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13929 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13930 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13931 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13932 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13933 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13934 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13935 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13936 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13937 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13938 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13939 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13940 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13942 /* Built-in functions for the DSP ASE (64-bit only). */
13943 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13945 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13946 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13947 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13948 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13949 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13950 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13951 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13952 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13953 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13954 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13956 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13957 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13958 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13959 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13960 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13961 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13962 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13963 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13964 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13965 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13966 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13967 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13968 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13969 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13970 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13971 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13972 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13973 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13974 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13975 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13976 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13977 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13978 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13979 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13980 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13981 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13982 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13983 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13984 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13985 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13986 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13987 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13988 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13989 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13990 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13991 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13992 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13993 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13994 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13995 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13996 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13997 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13998 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13999 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14000 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14001 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14002 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14003 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14004 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14005 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14006 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14007 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14008 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14009 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14010 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14011 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14012 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14013 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14014 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14015 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14016 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14017 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14018 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14019 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14020 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14021 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14022 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14023 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14024 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14025 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14026 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14027 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14028 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14029 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14030 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14031 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14032 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14033 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14034 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14035 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14036 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14037 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14038 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14039 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14040 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14041 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14042 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14043 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14044 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14045 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14046 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14047 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14048 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14049 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14050 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14051 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14052 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14053 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14054 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14055 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14057 /* Sundry other built-in functions. */
14058 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14061 /* Index I is the function declaration for mips_builtins[I], or null if the
14062 function isn't defined on this target. */
14063 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14065 /* MODE is a vector mode whose elements have type TYPE. Return the type
14066 of the vector itself. */
14069 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14071 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14074 mode_index
= (int) mode
;
14076 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14077 mode_index
+= MAX_MACHINE_MODE
;
14079 if (types
[mode_index
] == NULL_TREE
)
14080 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14081 return types
[mode_index
];
14084 /* Return a type for 'const volatile void *'. */
14087 mips_build_cvpointer_type (void)
14091 if (cache
== NULL_TREE
)
14092 cache
= build_pointer_type (build_qualified_type
14094 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14098 /* Source-level argument types. */
14099 #define MIPS_ATYPE_VOID void_type_node
14100 #define MIPS_ATYPE_INT integer_type_node
14101 #define MIPS_ATYPE_POINTER ptr_type_node
14102 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14104 /* Standard mode-based argument types. */
14105 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14106 #define MIPS_ATYPE_SI intSI_type_node
14107 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14108 #define MIPS_ATYPE_DI intDI_type_node
14109 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14110 #define MIPS_ATYPE_SF float_type_node
14111 #define MIPS_ATYPE_DF double_type_node
14113 /* Vector argument types. */
14114 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14115 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14116 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14117 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14118 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14119 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14120 #define MIPS_ATYPE_UV2SI \
14121 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14122 #define MIPS_ATYPE_UV4HI \
14123 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14124 #define MIPS_ATYPE_UV8QI \
14125 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14127 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14128 their associated MIPS_ATYPEs. */
14129 #define MIPS_FTYPE_ATYPES1(A, B) \
14130 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14132 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14133 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14135 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14136 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14138 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14139 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14142 /* Return the function type associated with function prototype TYPE. */
14145 mips_build_function_type (enum mips_function_type type
)
14147 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14149 if (types
[(int) type
] == NULL_TREE
)
14152 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14153 case MIPS_FTYPE_NAME##NUM ARGS: \
14154 types[(int) type] \
14155 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14158 #include "config/mips/mips-ftypes.def"
14159 #undef DEF_MIPS_FTYPE
14161 gcc_unreachable ();
14164 return types
[(int) type
];
14167 /* Implement TARGET_INIT_BUILTINS. */
14170 mips_init_builtins (void)
14172 const struct mips_builtin_description
*d
;
14175 /* Iterate through all of the bdesc arrays, initializing all of the
14176 builtin functions. */
14177 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14179 d
= &mips_builtins
[i
];
14181 mips_builtin_decls
[i
]
14182 = add_builtin_function (d
->name
,
14183 mips_build_function_type (d
->function_type
),
14184 i
, BUILT_IN_MD
, NULL
, NULL
);
14188 /* Implement TARGET_BUILTIN_DECL. */
14191 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14193 if (code
>= ARRAY_SIZE (mips_builtins
))
14194 return error_mark_node
;
14195 return mips_builtin_decls
[code
];
14198 /* Take argument ARGNO from EXP's argument list and convert it into
14199 an expand operand. Store the operand in *OP. */
14202 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14203 unsigned int argno
)
14208 arg
= CALL_EXPR_ARG (exp
, argno
);
14209 value
= expand_normal (arg
);
14210 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14213 /* Expand instruction ICODE as part of a built-in function sequence.
14214 Use the first NOPS elements of OPS as the instruction's operands.
14215 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14216 instruction has no target.
14218 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14221 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14222 struct expand_operand
*ops
, bool has_target_p
)
14224 if (!maybe_expand_insn (icode
, nops
, ops
))
14226 error ("invalid argument to built-in function");
14227 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14229 return has_target_p
? ops
[0].value
: const0_rtx
;
14232 /* Expand a floating-point comparison for built-in function call EXP.
14233 The first NARGS arguments are the values to be compared. ICODE is
14234 the .md pattern that does the comparison and COND is the condition
14235 that is being tested. Return an rtx for the result. */
14238 mips_expand_builtin_compare_1 (enum insn_code icode
,
14239 enum mips_fp_condition cond
,
14240 tree exp
, int nargs
)
14242 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14246 /* The instruction should have a target operand, an operand for each
14247 argument, and an operand for COND. */
14248 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14250 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14252 create_fixed_operand (&ops
[opno
++], output
);
14253 for (argno
= 0; argno
< nargs
; argno
++)
14254 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14255 create_integer_operand (&ops
[opno
++], (int) cond
);
14256 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14259 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14260 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14261 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14262 suggests a good place to put the result. */
14265 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14268 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14271 /* Map any target to operand 0. */
14274 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14276 /* Map the arguments to the other operands. */
14277 gcc_assert (opno
+ call_expr_nargs (exp
)
14278 == insn_data
[icode
].n_generator_args
);
14279 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14280 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14282 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14285 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14286 function; TYPE says which. EXP is the CALL_EXPR that calls the
14287 function, ICODE is the instruction that should be used to compare
14288 the first two arguments, and COND is the condition it should test.
14289 TARGET, if nonnull, suggests a good place to put the result. */
14292 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14293 enum insn_code icode
, enum mips_fp_condition cond
,
14294 rtx target
, tree exp
)
14296 struct expand_operand ops
[4];
14299 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14300 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14301 if (type
== MIPS_BUILTIN_MOVT
)
14303 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14304 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14308 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14309 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14311 create_fixed_operand (&ops
[3], cmp_result
);
14312 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14316 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14317 into TARGET otherwise. Return TARGET. */
14320 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14321 rtx value_if_true
, rtx value_if_false
)
14323 rtx true_label
, done_label
;
14325 true_label
= gen_label_rtx ();
14326 done_label
= gen_label_rtx ();
14328 /* First assume that CONDITION is false. */
14329 mips_emit_move (target
, value_if_false
);
14331 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14332 emit_jump_insn (gen_condjump (condition
, true_label
));
14333 emit_jump_insn (gen_jump (done_label
));
14336 /* Fix TARGET if CONDITION is true. */
14337 emit_label (true_label
);
14338 mips_emit_move (target
, value_if_true
);
14340 emit_label (done_label
);
14344 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14345 the CALL_EXPR that calls the function, ICODE is the code of the
14346 comparison instruction, and COND is the condition it should test.
14347 TARGET, if nonnull, suggests a good place to put the boolean result. */
14350 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14351 enum insn_code icode
, enum mips_fp_condition cond
,
14352 rtx target
, tree exp
)
14354 rtx offset
, condition
, cmp_result
;
14356 if (target
== 0 || GET_MODE (target
) != SImode
)
14357 target
= gen_reg_rtx (SImode
);
14358 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14359 call_expr_nargs (exp
));
14361 /* If the comparison sets more than one register, we define the result
14362 to be 0 if all registers are false and -1 if all registers are true.
14363 The value of the complete result is indeterminate otherwise. */
14364 switch (builtin_type
)
14366 case MIPS_BUILTIN_CMP_ALL
:
14367 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14368 return mips_builtin_branch_and_move (condition
, target
,
14369 const0_rtx
, const1_rtx
);
14371 case MIPS_BUILTIN_CMP_UPPER
:
14372 case MIPS_BUILTIN_CMP_LOWER
:
14373 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14374 condition
= gen_single_cc (cmp_result
, offset
);
14375 return mips_builtin_branch_and_move (condition
, target
,
14376 const1_rtx
, const0_rtx
);
14379 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14380 return mips_builtin_branch_and_move (condition
, target
,
14381 const1_rtx
, const0_rtx
);
14385 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14386 if nonnull, suggests a good place to put the boolean result. */
14389 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14391 rtx condition
, cmp_result
;
14394 if (target
== 0 || GET_MODE (target
) != SImode
)
14395 target
= gen_reg_rtx (SImode
);
14397 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14399 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14404 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14405 return mips_builtin_branch_and_move (condition
, target
,
14406 const1_rtx
, const0_rtx
);
14409 /* Implement TARGET_EXPAND_BUILTIN. */
14412 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14413 enum machine_mode mode
, int ignore
)
14416 unsigned int fcode
, avail
;
14417 const struct mips_builtin_description
*d
;
14419 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14420 fcode
= DECL_FUNCTION_CODE (fndecl
);
14421 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14422 d
= &mips_builtins
[fcode
];
14423 avail
= d
->avail ();
14424 gcc_assert (avail
!= 0);
14427 error ("built-in function %qE not supported for MIPS16",
14428 DECL_NAME (fndecl
));
14429 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14431 switch (d
->builtin_type
)
14433 case MIPS_BUILTIN_DIRECT
:
14434 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14436 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14437 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14439 case MIPS_BUILTIN_MOVT
:
14440 case MIPS_BUILTIN_MOVF
:
14441 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14442 d
->cond
, target
, exp
);
14444 case MIPS_BUILTIN_CMP_ANY
:
14445 case MIPS_BUILTIN_CMP_ALL
:
14446 case MIPS_BUILTIN_CMP_UPPER
:
14447 case MIPS_BUILTIN_CMP_LOWER
:
14448 case MIPS_BUILTIN_CMP_SINGLE
:
14449 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14450 d
->cond
, target
, exp
);
14452 case MIPS_BUILTIN_BPOSGE32
:
14453 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14455 gcc_unreachable ();
14458 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14459 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14460 struct mips16_constant
{
14461 struct mips16_constant
*next
;
14464 enum machine_mode mode
;
14467 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14468 first constant, HIGHEST_ADDRESS is the highest address that the first
14469 byte of the pool can have, and INSN_ADDRESS is the current instruction
14471 struct mips16_constant_pool
{
14472 struct mips16_constant
*first
;
14473 int highest_address
;
14477 /* Add constant VALUE to POOL and return its label. MODE is the
14478 value's mode (used for CONST_INTs, etc.). */
14481 mips16_add_constant (struct mips16_constant_pool
*pool
,
14482 rtx value
, enum machine_mode mode
)
14484 struct mips16_constant
**p
, *c
;
14485 bool first_of_size_p
;
14487 /* See whether the constant is already in the pool. If so, return the
14488 existing label, otherwise leave P pointing to the place where the
14489 constant should be added.
14491 Keep the pool sorted in increasing order of mode size so that we can
14492 reduce the number of alignments needed. */
14493 first_of_size_p
= true;
14494 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14496 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14497 return (*p
)->label
;
14498 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14500 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14501 first_of_size_p
= false;
14504 /* In the worst case, the constant needed by the earliest instruction
14505 will end up at the end of the pool. The entire pool must then be
14506 accessible from that instruction.
14508 When adding the first constant, set the pool's highest address to
14509 the address of the first out-of-range byte. Adjust this address
14510 downwards each time a new constant is added. */
14511 if (pool
->first
== 0)
14512 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14513 of the instruction with the lowest two bits clear. The base PC
14514 value for LDPC has the lowest three bits clear. Assume the worst
14515 case here; namely that the PC-relative instruction occupies the
14516 last 2 bytes in an aligned word. */
14517 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14518 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14519 if (first_of_size_p
)
14520 /* Take into account the worst possible padding due to alignment. */
14521 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14523 /* Create a new entry. */
14524 c
= XNEW (struct mips16_constant
);
14527 c
->label
= gen_label_rtx ();
14534 /* Output constant VALUE after instruction INSN and return the last
14535 instruction emitted. MODE is the mode of the constant. */
14538 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14540 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14542 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14543 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14546 if (SCALAR_FLOAT_MODE_P (mode
))
14547 return emit_insn_after (gen_consttable_float (value
), insn
);
14549 if (VECTOR_MODE_P (mode
))
14553 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14554 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14555 CONST_VECTOR_ELT (value
, i
), insn
);
14559 gcc_unreachable ();
14562 /* Dump out the constants in CONSTANTS after INSN. */
14565 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14567 struct mips16_constant
*c
, *next
;
14571 for (c
= constants
; c
!= NULL
; c
= next
)
14573 /* If necessary, increase the alignment of PC. */
14574 if (align
< GET_MODE_SIZE (c
->mode
))
14576 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14577 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14579 align
= GET_MODE_SIZE (c
->mode
);
14581 insn
= emit_label_after (c
->label
, insn
);
14582 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14588 emit_barrier_after (insn
);
14591 /* Return the length of instruction INSN. */
14594 mips16_insn_length (rtx insn
)
14596 if (JUMP_TABLE_DATA_P (insn
))
14598 rtx body
= PATTERN (insn
);
14599 if (GET_CODE (body
) == ADDR_VEC
)
14600 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14601 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14602 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14604 gcc_unreachable ();
14606 return get_attr_length (insn
);
14609 /* If *X is a symbolic constant that refers to the constant pool, add
14610 the constant to POOL and rewrite *X to use the constant's label. */
14613 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14615 rtx base
, offset
, label
;
14617 split_const (*x
, &base
, &offset
);
14618 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14620 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14621 get_pool_mode (base
));
14622 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14623 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14627 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14628 INSN is the instruction we're rewriting and POOL points to the current
14630 struct mips16_rewrite_pool_refs_info
{
14632 struct mips16_constant_pool
*pool
;
14635 /* Rewrite *X so that constant pool references refer to the constant's
14636 label instead. DATA points to a mips16_rewrite_pool_refs_info
14640 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14642 struct mips16_rewrite_pool_refs_info
*info
=
14643 (struct mips16_rewrite_pool_refs_info
*) data
;
14645 if (force_to_mem_operand (*x
, Pmode
))
14647 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14648 validate_change (info
->insn
, x
, mem
, false);
14653 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14657 /* Don't rewrite the __mips16_rdwr symbol. */
14658 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14661 if (TARGET_MIPS16_TEXT_LOADS
)
14662 mips16_rewrite_pool_constant (info
->pool
, x
);
14664 return GET_CODE (*x
) == CONST
? -1 : 0;
14667 /* Return whether CFG is used in mips_reorg. */
14670 mips_cfg_in_reorg (void)
14672 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14673 || TARGET_RELAX_PIC_CALLS
);
14676 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14677 otherwise assume that they are already split. */
14680 mips16_lay_out_constants (bool split_p
)
14682 struct mips16_constant_pool pool
;
14683 struct mips16_rewrite_pool_refs_info info
;
14686 if (!TARGET_MIPS16_PCREL_LOADS
)
14691 if (mips_cfg_in_reorg ())
14692 split_all_insns ();
14694 split_all_insns_noflow ();
14697 memset (&pool
, 0, sizeof (pool
));
14698 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14700 /* Rewrite constant pool references in INSN. */
14701 if (USEFUL_INSN_P (insn
))
14705 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14708 pool
.insn_address
+= mips16_insn_length (insn
);
14710 if (pool
.first
!= NULL
)
14712 /* If there are no natural barriers between the first user of
14713 the pool and the highest acceptable address, we'll need to
14714 create a new instruction to jump around the constant pool.
14715 In the worst case, this instruction will be 4 bytes long.
14717 If it's too late to do this transformation after INSN,
14718 do it immediately before INSN. */
14719 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14723 label
= gen_label_rtx ();
14725 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14726 JUMP_LABEL (jump
) = label
;
14727 LABEL_NUSES (label
) = 1;
14728 barrier
= emit_barrier_after (jump
);
14730 emit_label_after (label
, barrier
);
14731 pool
.insn_address
+= 4;
14734 /* See whether the constant pool is now out of range of the first
14735 user. If so, output the constants after the previous barrier.
14736 Note that any instructions between BARRIER and INSN (inclusive)
14737 will use negative offsets to refer to the pool. */
14738 if (pool
.insn_address
> pool
.highest_address
)
14740 mips16_emit_constants (pool
.first
, barrier
);
14744 else if (BARRIER_P (insn
))
14748 mips16_emit_constants (pool
.first
, get_last_insn ());
14751 /* Return true if it is worth r10k_simplify_address's while replacing
14752 an address with X. We are looking for constants, and for addresses
14753 at a known offset from the incoming stack pointer. */
14756 r10k_simplified_address_p (rtx x
)
14758 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14760 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14763 /* X is an expression that appears in INSN. Try to use the UD chains
14764 to simplify it, returning the simplified form on success and the
14765 original form otherwise. Replace the incoming value of $sp with
14766 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14769 r10k_simplify_address (rtx x
, rtx insn
)
14771 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14773 struct df_link
*defs
;
14778 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14779 if (op0
!= XEXP (x
, 0))
14780 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14781 op0
, GET_MODE (XEXP (x
, 0)));
14783 else if (BINARY_P (x
))
14785 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14786 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14787 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14788 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14790 else if (GET_CODE (x
) == LO_SUM
)
14792 /* LO_SUMs can be offset from HIGHs, if we know they won't
14793 overflow. See mips_classify_address for the rationale behind
14795 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14796 if (GET_CODE (op0
) == HIGH
)
14797 newx
= XEXP (x
, 1);
14799 else if (REG_P (x
))
14801 /* Uses are recorded by regno_reg_rtx, not X itself. */
14802 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14804 defs
= DF_REF_CHAIN (use
);
14806 /* Require a single definition. */
14807 if (defs
&& defs
->next
== NULL
)
14810 if (DF_REF_IS_ARTIFICIAL (def
))
14812 /* Replace the incoming value of $sp with
14813 virtual_incoming_args_rtx. */
14814 if (x
== stack_pointer_rtx
14815 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14816 newx
= virtual_incoming_args_rtx
;
14818 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14821 /* Make sure that DEF_INSN is a single set of REG. */
14822 def_insn
= DF_REF_INSN (def
);
14823 if (NONJUMP_INSN_P (def_insn
))
14825 set
= single_set (def_insn
);
14826 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14828 /* Prefer to use notes, since the def-use chains
14829 are often shorter. */
14830 note
= find_reg_equal_equiv_note (def_insn
);
14832 newx
= XEXP (note
, 0);
14834 newx
= SET_SRC (set
);
14835 newx
= r10k_simplify_address (newx
, def_insn
);
14841 if (newx
&& r10k_simplified_address_p (newx
))
14846 /* Return true if ADDRESS is known to be an uncached address
14847 on R10K systems. */
14850 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14852 unsigned HOST_WIDE_INT upper
;
14854 /* Check for KSEG1. */
14855 if (address
+ 0x60000000 < 0x20000000)
14858 /* Check for uncached XKPHYS addresses. */
14859 if (Pmode
== DImode
)
14861 upper
= (address
>> 40) & 0xf9ffff;
14862 if (upper
== 0x900000 || upper
== 0xb80000)
14868 /* Return true if we can prove that an access to address X in instruction
14869 INSN would be safe from R10K speculation. This X is a general
14870 expression; it might not be a legitimate address. */
14873 r10k_safe_address_p (rtx x
, rtx insn
)
14876 HOST_WIDE_INT offset_val
;
14878 x
= r10k_simplify_address (x
, insn
);
14880 /* Check for references to the stack frame. It doesn't really matter
14881 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14882 allows us to assume that accesses to any part of the eventual frame
14883 is safe from speculation at any point in the function. */
14884 mips_split_plus (x
, &base
, &offset_val
);
14885 if (base
== virtual_incoming_args_rtx
14886 && offset_val
>= -cfun
->machine
->frame
.total_size
14887 && offset_val
< cfun
->machine
->frame
.args_size
)
14890 /* Check for uncached addresses. */
14891 if (CONST_INT_P (x
))
14892 return r10k_uncached_address_p (INTVAL (x
));
14894 /* Check for accesses to a static object. */
14895 split_const (x
, &base
, &offset
);
14896 return offset_within_block_p (base
, INTVAL (offset
));
14899 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14900 an in-range access to an automatic variable, or to an object with
14901 a link-time-constant address. */
14904 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14906 HOST_WIDE_INT bitoffset
, bitsize
;
14907 tree inner
, var_offset
;
14908 enum machine_mode mode
;
14909 int unsigned_p
, volatile_p
;
14911 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14912 &unsigned_p
, &volatile_p
, false);
14913 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14916 offset
+= bitoffset
/ BITS_PER_UNIT
;
14917 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14920 /* A for_each_rtx callback for which DATA points to the instruction
14921 containing *X. Stop the search if we find a MEM that is not safe
14922 from R10K speculation. */
14925 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14934 && MEM_OFFSET_KNOWN_P (mem
)
14935 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14938 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14944 /* A note_stores callback for which DATA points to an instruction pointer.
14945 If *DATA is nonnull, make it null if it X contains a MEM that is not
14946 safe from R10K speculation. */
14949 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14954 insn_ptr
= (rtx
*) data
;
14955 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14956 *insn_ptr
= NULL_RTX
;
14959 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14960 Return nonzero if the call is not to a declared function. */
14963 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14972 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14978 /* Return true if instruction INSN needs to be protected by an R10K
14982 r10k_needs_protection_p (rtx insn
)
14985 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14987 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14989 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14990 return insn
== NULL_RTX
;
14993 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14996 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14997 edge is unconditional. */
15000 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15005 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15006 if (!single_succ_p (e
->src
)
15007 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15008 || (e
->flags
& EDGE_COMPLEX
) != 0)
15013 /* Implement -mr10k-cache-barrier= for the current function. */
15016 r10k_insert_cache_barriers (void)
15018 int *rev_post_order
;
15021 sbitmap protected_bbs
;
15022 rtx insn
, end
, unprotected_region
;
15026 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15030 /* Calculate dominators. */
15031 calculate_dominance_info (CDI_DOMINATORS
);
15033 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15034 X is protected by a cache barrier. */
15035 protected_bbs
= sbitmap_alloc (last_basic_block
);
15036 bitmap_clear (protected_bbs
);
15038 /* Iterate over the basic blocks in reverse post-order. */
15039 rev_post_order
= XNEWVEC (int, last_basic_block
);
15040 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15041 for (i
= 0; i
< n
; i
++)
15043 bb
= BASIC_BLOCK (rev_post_order
[i
]);
15045 /* If this block is only reached by unconditional edges, and if the
15046 source of every edge is protected, the beginning of the block is
15048 if (r10k_protected_bb_p (bb
, protected_bbs
))
15049 unprotected_region
= NULL_RTX
;
15051 unprotected_region
= pc_rtx
;
15052 end
= NEXT_INSN (BB_END (bb
));
15054 /* UNPROTECTED_REGION is:
15056 - null if we are processing a protected region,
15057 - pc_rtx if we are processing an unprotected region but have
15058 not yet found the first instruction in it
15059 - the first instruction in an unprotected region otherwise. */
15060 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15062 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15064 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15065 /* This CACHE instruction protects the following code. */
15066 unprotected_region
= NULL_RTX
;
15069 /* See if INSN is the first instruction in this
15070 unprotected region. */
15071 if (unprotected_region
== pc_rtx
)
15072 unprotected_region
= insn
;
15074 /* See if INSN needs to be protected. If so,
15075 we must insert a cache barrier somewhere between
15076 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15077 clear which position is better performance-wise,
15078 but as a tie-breaker, we assume that it is better
15079 to allow delay slots to be back-filled where
15080 possible, and that it is better not to insert
15081 barriers in the middle of already-scheduled code.
15082 We therefore insert the barrier at the beginning
15084 if (r10k_needs_protection_p (insn
))
15086 emit_insn_before (gen_r10k_cache_barrier (),
15087 unprotected_region
);
15088 unprotected_region
= NULL_RTX
;
15094 /* The called function is not required to protect the exit path.
15095 The code that follows a call is therefore unprotected. */
15096 unprotected_region
= pc_rtx
;
15099 /* Record whether the end of this block is protected. */
15100 if (unprotected_region
== NULL_RTX
)
15101 bitmap_set_bit (protected_bbs
, bb
->index
);
15103 XDELETEVEC (rev_post_order
);
15105 sbitmap_free (protected_bbs
);
15107 free_dominance_info (CDI_DOMINATORS
);
15110 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15111 otherwise. If INSN has two call rtx, then store the second one in
15115 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15120 if (!CALL_P (insn
))
15123 x
= PATTERN (insn
);
15124 if (GET_CODE (x
) == PARALLEL
)
15126 /* Calls returning complex values have two CALL rtx. Look for the second
15127 one here, and return it via the SECOND_CALL arg. */
15128 x2
= XVECEXP (x
, 0, 1);
15129 if (GET_CODE (x2
) == SET
)
15131 if (GET_CODE (x2
) == CALL
)
15134 x
= XVECEXP (x
, 0, 0);
15136 if (GET_CODE (x
) == SET
)
15138 gcc_assert (GET_CODE (x
) == CALL
);
15143 /* REG is set in DEF. See if the definition is one of the ways we load a
15144 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15145 If it is, return the symbol reference of the function, otherwise return
15148 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15149 the values of source registers, otherwise treat such registers as
15150 having an unknown value. */
15153 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15157 if (DF_REF_IS_ARTIFICIAL (def
))
15160 def_insn
= DF_REF_INSN (def
);
15161 set
= single_set (def_insn
);
15162 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15164 rtx note
, src
, symbol
;
15166 /* First see whether the source is a plain symbol. This is used
15167 when calling symbols that are not lazily bound. */
15168 src
= SET_SRC (set
);
15169 if (GET_CODE (src
) == SYMBOL_REF
)
15172 /* Handle %call16 references. */
15173 symbol
= mips_strip_unspec_call (src
);
15176 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15180 /* If we have something more complicated, look for a
15181 REG_EQUAL or REG_EQUIV note. */
15182 note
= find_reg_equal_equiv_note (def_insn
);
15183 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15184 return XEXP (note
, 0);
15186 /* Follow at most one simple register copy. Such copies are
15187 interesting in cases like:
15191 locally_binding_fn (...);
15196 locally_binding_fn (...);
15198 locally_binding_fn (...);
15200 where the load of locally_binding_fn can legitimately be
15201 hoisted or shared. However, we do not expect to see complex
15202 chains of copies, so a full worklist solution to the problem
15203 would probably be overkill. */
15204 if (recurse_p
&& REG_P (src
))
15205 return mips_find_pic_call_symbol (def_insn
, src
, false);
15211 /* Find the definition of the use of REG in INSN. See if the definition
15212 is one of the ways we load a register with a symbol address for a
15213 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15214 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15215 mips_pic_call_symbol_from_set. */
15218 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15221 struct df_link
*defs
;
15224 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15227 defs
= DF_REF_CHAIN (use
);
15230 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15234 /* If we have more than one definition, they need to be identical. */
15235 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15239 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15240 if (!rtx_equal_p (symbol
, other
))
15247 /* Replace the args_size operand of the call expression CALL with the
15248 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15251 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15255 args_size
= XEXP (call
, 1);
15256 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15257 gen_rtvec (2, args_size
, symbol
),
15261 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15262 if instead of the arg_size argument it contains the call attributes. If
15263 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15264 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15268 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15270 rtx args_size
, symbol
;
15272 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15275 args_size
= operands
[args_size_opno
];
15276 if (GET_CODE (args_size
) != UNSPEC
)
15278 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15280 symbol
= XVECEXP (args_size
, 0, 1);
15281 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15283 operands
[args_size_opno
] = symbol
;
15287 /* Use DF to annotate PIC indirect calls with the function symbol they
15291 mips_annotate_pic_calls (void)
15297 FOR_BB_INSNS (bb
, insn
)
15299 rtx call
, reg
, symbol
, second_call
;
15302 call
= mips_call_expr_from_insn (insn
, &second_call
);
15305 gcc_assert (MEM_P (XEXP (call
, 0)));
15306 reg
= XEXP (XEXP (call
, 0), 0);
15310 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15313 mips_annotate_pic_call_expr (call
, symbol
);
15315 mips_annotate_pic_call_expr (second_call
, symbol
);
15320 /* A temporary variable used by for_each_rtx callbacks, etc. */
15321 static rtx mips_sim_insn
;
15323 /* A structure representing the state of the processor pipeline.
15324 Used by the mips_sim_* family of functions. */
15326 /* The maximum number of instructions that can be issued in a cycle.
15327 (Caches mips_issue_rate.) */
15328 unsigned int issue_rate
;
15330 /* The current simulation time. */
15333 /* How many more instructions can be issued in the current cycle. */
15334 unsigned int insns_left
;
15336 /* LAST_SET[X].INSN is the last instruction to set register X.
15337 LAST_SET[X].TIME is the time at which that instruction was issued.
15338 INSN is null if no instruction has yet set register X. */
15342 } last_set
[FIRST_PSEUDO_REGISTER
];
15344 /* The pipeline's current DFA state. */
15348 /* Reset STATE to the initial simulation state. */
15351 mips_sim_reset (struct mips_sim
*state
)
15353 curr_state
= state
->dfa_state
;
15356 state
->insns_left
= state
->issue_rate
;
15357 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15358 state_reset (curr_state
);
15360 targetm
.sched
.init (0, false, 0);
15361 advance_state (curr_state
);
15364 /* Initialize STATE before its first use. DFA_STATE points to an
15365 allocated but uninitialized DFA state. */
15368 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15370 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15371 targetm
.sched
.init_dfa_pre_cycle_insn ();
15373 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15374 targetm
.sched
.init_dfa_post_cycle_insn ();
15376 state
->issue_rate
= mips_issue_rate ();
15377 state
->dfa_state
= dfa_state
;
15378 mips_sim_reset (state
);
15381 /* Advance STATE by one clock cycle. */
15384 mips_sim_next_cycle (struct mips_sim
*state
)
15386 curr_state
= state
->dfa_state
;
15389 state
->insns_left
= state
->issue_rate
;
15390 advance_state (curr_state
);
15393 /* Advance simulation state STATE until instruction INSN can read
15397 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15399 unsigned int regno
, end_regno
;
15401 end_regno
= END_REGNO (reg
);
15402 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15403 if (state
->last_set
[regno
].insn
!= 0)
15407 t
= (state
->last_set
[regno
].time
15408 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15409 while (state
->time
< t
)
15410 mips_sim_next_cycle (state
);
15414 /* A for_each_rtx callback. If *X is a register, advance simulation state
15415 DATA until mips_sim_insn can read the register's value. */
15418 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15421 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15425 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15428 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15430 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15433 /* Advance simulation state STATE until all of INSN's register
15434 dependencies are satisfied. */
15437 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15439 mips_sim_insn
= insn
;
15440 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15443 /* Advance simulation state STATE until the units required by
15444 instruction INSN are available. */
15447 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15451 tmp_state
= alloca (state_size ());
15452 while (state
->insns_left
== 0
15453 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15454 state_transition (tmp_state
, insn
) >= 0))
15455 mips_sim_next_cycle (state
);
15458 /* Advance simulation state STATE until INSN is ready to issue. */
15461 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15463 mips_sim_wait_regs (state
, insn
);
15464 mips_sim_wait_units (state
, insn
);
15467 /* mips_sim_insn has just set X. Update the LAST_SET array
15468 in simulation state DATA. */
15471 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15473 struct mips_sim
*state
;
15475 state
= (struct mips_sim
*) data
;
15478 unsigned int regno
, end_regno
;
15480 end_regno
= END_REGNO (x
);
15481 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15483 state
->last_set
[regno
].insn
= mips_sim_insn
;
15484 state
->last_set
[regno
].time
= state
->time
;
15489 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15490 can issue immediately (i.e., that mips_sim_wait_insn has already
15494 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15496 curr_state
= state
->dfa_state
;
15498 state_transition (curr_state
, insn
);
15499 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15500 state
->insns_left
);
15502 mips_sim_insn
= insn
;
15503 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15506 /* Simulate issuing a NOP in state STATE. */
15509 mips_sim_issue_nop (struct mips_sim
*state
)
15511 if (state
->insns_left
== 0)
15512 mips_sim_next_cycle (state
);
15513 state
->insns_left
--;
15516 /* Update simulation state STATE so that it's ready to accept the instruction
15517 after INSN. INSN should be part of the main rtl chain, not a member of a
15521 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15523 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15525 mips_sim_issue_nop (state
);
15527 switch (GET_CODE (SEQ_BEGIN (insn
)))
15531 /* We can't predict the processor state after a call or label. */
15532 mips_sim_reset (state
);
15536 /* The delay slots of branch likely instructions are only executed
15537 when the branch is taken. Therefore, if the caller has simulated
15538 the delay slot instruction, STATE does not really reflect the state
15539 of the pipeline for the instruction after the delay slot. Also,
15540 branch likely instructions tend to incur a penalty when not taken,
15541 so there will probably be an extra delay between the branch and
15542 the instruction after the delay slot. */
15543 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15544 mips_sim_reset (state
);
15552 /* Use simulator state STATE to calculate the execution time of
15553 instruction sequence SEQ. */
15555 static unsigned int
15556 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15558 mips_sim_reset (state
);
15559 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15561 mips_sim_wait_insn (state
, insn
);
15562 mips_sim_issue_insn (state
, insn
);
15564 return state
->time
;
15567 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15568 setting SETTING, using STATE to simulate instruction sequences. */
15570 static unsigned int
15571 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15573 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15576 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15577 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15578 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15580 /* If the target provides mulsidi3_32bit then that's the most likely
15581 consumer of the result. Test for bypasses. */
15582 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15584 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15585 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15588 unsigned int time
= mips_seq_time (state
, get_insns ());
15593 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15594 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15595 Prefer MULT -- which is shorter -- in the event of a tie. */
15598 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15601 /* No MTLO or MTHI available. */
15602 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15605 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15606 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15607 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15611 /* Set up costs based on the current architecture and tuning settings. */
15614 mips_set_tuning_info (void)
15616 if (mips_tuning_info
.initialized_p
15617 && mips_tuning_info
.arch
== mips_arch
15618 && mips_tuning_info
.tune
== mips_tune
15619 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15622 mips_tuning_info
.arch
= mips_arch
;
15623 mips_tuning_info
.tune
= mips_tune
;
15624 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15625 mips_tuning_info
.initialized_p
= true;
15629 struct mips_sim state
;
15630 mips_sim_init (&state
, alloca (state_size ()));
15632 mips_set_fast_mult_zero_zero_p (&state
);
15637 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15640 mips_expand_to_rtl_hook (void)
15642 /* We need to call this at a point where we can safely create sequences
15643 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15644 need to call it at a point where the DFA infrastructure is not
15645 already in use, so we can't just call it lazily on demand.
15647 At present, mips_tuning_info is only needed during post-expand
15648 RTL passes such as split_insns, so this hook should be early enough.
15649 We may need to move the call elsewhere if mips_tuning_info starts
15650 to be used for other things (such as rtx_costs, or expanders that
15651 could be called during gimple optimization). */
15652 mips_set_tuning_info ();
15655 /* The VR4130 pipeline issues aligned pairs of instructions together,
15656 but it stalls the second instruction if it depends on the first.
15657 In order to cut down the amount of logic required, this dependence
15658 check is not based on a full instruction decode. Instead, any non-SPECIAL
15659 instruction is assumed to modify the register specified by bits 20-16
15660 (which is usually the "rt" field).
15662 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15663 input, so we can end up with a false dependence between the branch
15664 and its delay slot. If this situation occurs in instruction INSN,
15665 try to avoid it by swapping rs and rt. */
15668 vr4130_avoid_branch_rt_conflict (rtx insn
)
15672 first
= SEQ_BEGIN (insn
);
15673 second
= SEQ_END (insn
);
15675 && NONJUMP_INSN_P (second
)
15676 && GET_CODE (PATTERN (first
)) == SET
15677 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15678 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15680 /* Check for the right kind of condition. */
15681 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15682 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15683 && REG_P (XEXP (cond
, 0))
15684 && REG_P (XEXP (cond
, 1))
15685 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15686 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15688 /* SECOND mentions the rt register but not the rs register. */
15689 rtx tmp
= XEXP (cond
, 0);
15690 XEXP (cond
, 0) = XEXP (cond
, 1);
15691 XEXP (cond
, 1) = tmp
;
15696 /* Implement -mvr4130-align. Go through each basic block and simulate the
15697 processor pipeline. If we find that a pair of instructions could execute
15698 in parallel, and the first of those instructions is not 8-byte aligned,
15699 insert a nop to make it aligned. */
15702 vr4130_align_insns (void)
15704 struct mips_sim state
;
15705 rtx insn
, subinsn
, last
, last2
, next
;
15710 /* LAST is the last instruction before INSN to have a nonzero length.
15711 LAST2 is the last such instruction before LAST. */
15715 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15718 mips_sim_init (&state
, alloca (state_size ()));
15719 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15721 unsigned int length
;
15723 next
= NEXT_INSN (insn
);
15725 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15726 This isn't really related to the alignment pass, but we do it on
15727 the fly to avoid a separate instruction walk. */
15728 vr4130_avoid_branch_rt_conflict (insn
);
15730 length
= get_attr_length (insn
);
15731 if (length
> 0 && USEFUL_INSN_P (insn
))
15732 FOR_EACH_SUBINSN (subinsn
, insn
)
15734 mips_sim_wait_insn (&state
, subinsn
);
15736 /* If we want this instruction to issue in parallel with the
15737 previous one, make sure that the previous instruction is
15738 aligned. There are several reasons why this isn't worthwhile
15739 when the second instruction is a call:
15741 - Calls are less likely to be performance critical,
15742 - There's a good chance that the delay slot can execute
15743 in parallel with the call.
15744 - The return address would then be unaligned.
15746 In general, if we're going to insert a nop between instructions
15747 X and Y, it's better to insert it immediately after X. That
15748 way, if the nop makes Y aligned, it will also align any labels
15749 between X and Y. */
15750 if (state
.insns_left
!= state
.issue_rate
15751 && !CALL_P (subinsn
))
15753 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15755 /* SUBINSN is the first instruction in INSN and INSN is
15756 aligned. We want to align the previous instruction
15757 instead, so insert a nop between LAST2 and LAST.
15759 Note that LAST could be either a single instruction
15760 or a branch with a delay slot. In the latter case,
15761 LAST, like INSN, is already aligned, but the delay
15762 slot must have some extra delay that stops it from
15763 issuing at the same time as the branch. We therefore
15764 insert a nop before the branch in order to align its
15766 gcc_assert (last2
);
15767 emit_insn_after (gen_nop (), last2
);
15770 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15772 /* SUBINSN is the delay slot of INSN, but INSN is
15773 currently unaligned. Insert a nop between
15774 LAST and INSN to align it. */
15776 emit_insn_after (gen_nop (), last
);
15780 mips_sim_issue_insn (&state
, subinsn
);
15782 mips_sim_finish_insn (&state
, insn
);
15784 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15785 length
= get_attr_length (insn
);
15788 /* If the instruction is an asm statement or multi-instruction
15789 mips.md patern, the length is only an estimate. Insert an
15790 8 byte alignment after it so that the following instructions
15791 can be handled correctly. */
15792 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15793 && (recog_memoized (insn
) < 0 || length
>= 8))
15795 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15796 next
= NEXT_INSN (next
);
15797 mips_sim_next_cycle (&state
);
15800 else if (length
& 4)
15801 aligned_p
= !aligned_p
;
15806 /* See whether INSN is an aligned label. */
15807 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15813 /* This structure records that the current function has a LO_SUM
15814 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15815 the largest offset applied to BASE by all such LO_SUMs. */
15816 struct mips_lo_sum_offset
{
15818 HOST_WIDE_INT offset
;
15821 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15824 mips_hash_base (rtx base
)
15826 int do_not_record_p
;
15828 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15831 /* Hashtable helpers. */
15833 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15835 typedef mips_lo_sum_offset value_type
;
15836 typedef rtx_def compare_type
;
15837 static inline hashval_t
hash (const value_type
*);
15838 static inline bool equal (const value_type
*, const compare_type
*);
15841 /* Hash-table callbacks for mips_lo_sum_offsets. */
15844 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15846 return mips_hash_base (entry
->base
);
15850 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
15851 const compare_type
*value
)
15853 return rtx_equal_p (entry
->base
, value
);
15856 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
15858 /* Look up symbolic constant X in HTAB, which is a hash table of
15859 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15860 paired with a recorded LO_SUM, otherwise record X in the table. */
15863 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
15864 enum insert_option option
)
15867 mips_lo_sum_offset
**slot
;
15868 struct mips_lo_sum_offset
*entry
;
15870 /* Split X into a base and offset. */
15871 split_const (x
, &base
, &offset
);
15872 if (UNSPEC_ADDRESS_P (base
))
15873 base
= UNSPEC_ADDRESS (base
);
15875 /* Look up the base in the hash table. */
15876 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
15880 entry
= (struct mips_lo_sum_offset
*) *slot
;
15881 if (option
== INSERT
)
15885 entry
= XNEW (struct mips_lo_sum_offset
);
15886 entry
->base
= base
;
15887 entry
->offset
= INTVAL (offset
);
15892 if (INTVAL (offset
) > entry
->offset
)
15893 entry
->offset
= INTVAL (offset
);
15896 return INTVAL (offset
) <= entry
->offset
;
15899 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15900 Record every LO_SUM in *LOC. */
15903 mips_record_lo_sum (rtx
*loc
, void *data
)
15905 if (GET_CODE (*loc
) == LO_SUM
)
15906 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
15907 XEXP (*loc
, 1), INSERT
);
15911 /* Return true if INSN is a SET of an orphaned high-part relocation.
15912 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15913 LO_SUMs in the current function. */
15916 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
15918 enum mips_symbol_type type
;
15921 set
= single_set (insn
);
15924 /* Check for %his. */
15926 if (GET_CODE (x
) == HIGH
15927 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15928 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15930 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15931 if (GET_CODE (x
) == UNSPEC
15932 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15933 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15934 SYMBOL_CONTEXT_LEA
, &type
)
15935 && type
== SYMBOL_GOTOFF_PAGE
)
15936 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15941 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15942 INSN and a previous instruction, avoid it by inserting nops after
15945 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15946 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15947 before using the value of that register. *HILO_DELAY counts the
15948 number of instructions since the last hilo hazard (that is,
15949 the number of instructions since the last MFLO or MFHI).
15951 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15952 for the next instruction.
15954 LO_REG is an rtx for the LO register, used in dependence checking. */
15957 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15958 rtx
*delayed_reg
, rtx lo_reg
)
15963 pattern
= PATTERN (insn
);
15965 /* Do not put the whole function in .set noreorder if it contains
15966 an asm statement. We don't know whether there will be hazards
15967 between the asm statement and the gcc-generated code. */
15968 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15969 cfun
->machine
->all_noreorder_p
= false;
15971 /* Ignore zero-length instructions (barriers and the like). */
15972 ninsns
= get_attr_length (insn
) / 4;
15976 /* Work out how many nops are needed. Note that we only care about
15977 registers that are explicitly mentioned in the instruction's pattern.
15978 It doesn't matter that calls use the argument registers or that they
15979 clobber hi and lo. */
15980 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15981 nops
= 2 - *hilo_delay
;
15982 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15987 /* Insert the nops between this instruction and the previous one.
15988 Each new nop takes us further from the last hilo hazard. */
15989 *hilo_delay
+= nops
;
15991 emit_insn_after (gen_hazard_nop (), after
);
15993 /* Set up the state for the next instruction. */
15994 *hilo_delay
+= ninsns
;
15996 if (INSN_CODE (insn
) >= 0)
15997 switch (get_attr_hazard (insn
))
16007 set
= single_set (insn
);
16009 *delayed_reg
= SET_DEST (set
);
16014 /* Go through the instruction stream and insert nops where necessary.
16015 Also delete any high-part relocations whose partnering low parts
16016 are now all dead. See if the whole function can then be put into
16017 .set noreorder and .set nomacro. */
16020 mips_reorg_process_insns (void)
16022 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16024 mips_offset_table htab
;
16026 /* Force all instructions to be split into their final form. */
16027 split_all_insns_noflow ();
16029 /* Recalculate instruction lengths without taking nops into account. */
16030 cfun
->machine
->ignore_hazard_length_p
= true;
16031 shorten_branches (get_insns ());
16033 cfun
->machine
->all_noreorder_p
= true;
16035 /* We don't track MIPS16 PC-relative offsets closely enough to make
16036 a good job of "set .noreorder" code in MIPS16 mode. */
16038 cfun
->machine
->all_noreorder_p
= false;
16040 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16041 if (!TARGET_EXPLICIT_RELOCS
)
16042 cfun
->machine
->all_noreorder_p
= false;
16044 /* Profiled functions can't be all noreorder because the profiler
16045 support uses assembler macros. */
16047 cfun
->machine
->all_noreorder_p
= false;
16049 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16050 because we rely on the assembler to work around some errata.
16051 The r5900 too has several bugs. */
16052 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
|| TARGET_MIPS5900
)
16053 cfun
->machine
->all_noreorder_p
= false;
16055 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16056 MFHI instructions. Note that we avoid using MFLO and MFHI if
16057 the VR4130 MACC and DMACC instructions are available instead;
16058 see the *mfhilo_{si,di}_macc patterns. */
16059 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16060 cfun
->machine
->all_noreorder_p
= false;
16064 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16065 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16066 FOR_EACH_SUBINSN (subinsn
, insn
)
16067 if (USEFUL_INSN_P (subinsn
))
16068 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16073 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16075 /* Make a second pass over the instructions. Delete orphaned
16076 high-part relocations or turn them into NOPs. Avoid hazards
16077 by inserting NOPs. */
16078 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16080 next_insn
= NEXT_INSN (insn
);
16081 if (USEFUL_INSN_P (insn
))
16083 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16085 /* If we find an orphaned high-part relocation in a delay
16086 slot, it's easier to turn that instruction into a NOP than
16087 to delete it. The delay slot will be a NOP either way. */
16088 FOR_EACH_SUBINSN (subinsn
, insn
)
16089 if (INSN_P (subinsn
))
16091 if (mips_orphaned_high_part_p (htab
, subinsn
))
16093 PATTERN (subinsn
) = gen_nop ();
16094 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16096 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16097 &delayed_reg
, lo_reg
);
16103 /* INSN is a single instruction. Delete it if it's an
16104 orphaned high-part relocation. */
16105 if (mips_orphaned_high_part_p (htab
, insn
))
16106 delete_insn (insn
);
16107 /* Also delete cache barriers if the last instruction
16108 was an annulled branch. INSN will not be speculatively
16110 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16112 && JUMP_P (SEQ_BEGIN (last_insn
))
16113 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16114 delete_insn (insn
);
16117 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16118 &delayed_reg
, lo_reg
);
16128 /* Return true if the function has a long branch instruction. */
16131 mips_has_long_branch_p (void)
16136 /* We need up-to-date instruction lengths. */
16137 shorten_branches (get_insns ());
16139 /* Look for a branch that is longer than normal. The normal length for
16140 non-MIPS16 branches is 8, because the length includes the delay slot.
16141 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16142 but they have no delay slot. */
16143 normal_length
= (TARGET_MIPS16
? 4 : 8);
16144 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16145 FOR_EACH_SUBINSN (subinsn
, insn
)
16146 if (JUMP_P (subinsn
)
16147 && get_attr_length (subinsn
) > normal_length
16148 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16154 /* If we are using a GOT, but have not decided to use a global pointer yet,
16155 see whether we need one to implement long branches. Convert the ghost
16156 global-pointer instructions into real ones if so. */
16159 mips_expand_ghost_gp_insns (void)
16161 /* Quick exit if we already know that we will or won't need a
16163 if (!TARGET_USE_GOT
16164 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16165 || mips_must_initialize_gp_p ())
16168 /* Run a full check for long branches. */
16169 if (!mips_has_long_branch_p ())
16172 /* We've now established that we need $gp. */
16173 cfun
->machine
->must_initialize_gp_p
= true;
16174 split_all_insns_noflow ();
16179 /* Subroutine of mips_reorg to manage passes that require DF. */
16182 mips_df_reorg (void)
16184 /* Create def-use chains. */
16185 df_set_flags (DF_EQ_NOTES
);
16186 df_chain_add_problem (DF_UD_CHAIN
);
16189 if (TARGET_RELAX_PIC_CALLS
)
16190 mips_annotate_pic_calls ();
16192 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16193 r10k_insert_cache_barriers ();
16195 df_finish_pass (false);
16198 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16199 called very late in mips_reorg, but the caller is required to run
16200 mips16_lay_out_constants on the result. */
16203 mips16_load_branch_target (rtx dest
, rtx src
)
16205 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16209 if (mips_cfun_has_cprestore_slot_p ())
16210 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16212 mips_emit_move (dest
, pic_offset_table_rtx
);
16213 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16214 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16215 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16216 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16217 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16218 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16222 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16223 mips_emit_move (dest
, src
);
16227 /* If we're compiling a MIPS16 function, look for and split any long branches.
16228 This must be called after all other instruction modifications in
16232 mips16_split_long_branches (void)
16234 bool something_changed
;
16236 if (!TARGET_MIPS16
)
16239 /* Loop until the alignments for all targets are sufficient. */
16244 shorten_branches (get_insns ());
16245 something_changed
= false;
16246 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16248 && get_attr_length (insn
) > 4
16249 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16251 rtx old_label
, new_label
, temp
, saved_temp
;
16252 rtx target
, jump
, jump_sequence
;
16256 /* Free up a MIPS16 register by saving it in $1. */
16257 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16258 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16259 emit_move_insn (saved_temp
, temp
);
16261 /* Load the branch target into TEMP. */
16262 old_label
= JUMP_LABEL (insn
);
16263 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16264 mips16_load_branch_target (temp
, target
);
16266 /* Jump to the target and restore the register's
16268 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16269 (temp
, temp
, saved_temp
)));
16270 JUMP_LABEL (jump
) = old_label
;
16271 LABEL_NUSES (old_label
)++;
16273 /* Rewrite any symbolic references that are supposed to use
16274 a PC-relative constant pool. */
16275 mips16_lay_out_constants (false);
16277 if (simplejump_p (insn
))
16278 /* We're going to replace INSN with a longer form. */
16279 new_label
= NULL_RTX
;
16282 /* Create a branch-around label for the original
16284 new_label
= gen_label_rtx ();
16285 emit_label (new_label
);
16288 jump_sequence
= get_insns ();
16291 emit_insn_after (jump_sequence
, insn
);
16293 invert_jump (insn
, new_label
, false);
16295 delete_insn (insn
);
16296 something_changed
= true;
16299 while (something_changed
);
16302 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16307 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16308 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16309 to date if the CFG is available. */
16310 if (mips_cfg_in_reorg ())
16311 compute_bb_for_insn ();
16312 mips16_lay_out_constants (true);
16313 if (mips_cfg_in_reorg ())
16316 free_bb_for_insn ();
16320 /* We use a machine specific pass to do a second machine dependent reorg
16321 pass after delay branch scheduling. */
16323 static unsigned int
16324 mips_machine_reorg2 (void)
16326 mips_reorg_process_insns ();
16328 && TARGET_EXPLICIT_RELOCS
16330 && TARGET_VR4130_ALIGN
)
16331 vr4130_align_insns ();
16332 if (mips_expand_ghost_gp_insns ())
16333 /* The expansion could invalidate some of the VR4130 alignment
16334 optimizations, but this should be an extremely rare case anyhow. */
16335 mips_reorg_process_insns ();
16336 mips16_split_long_branches ();
16340 struct rtl_opt_pass pass_mips_machine_reorg2
=
16344 "mach2", /* name */
16345 OPTGROUP_NONE
, /* optinfo_flags */
16347 mips_machine_reorg2
, /* execute */
16350 0, /* static_pass_number */
16351 TV_MACH_DEP
, /* tv_id */
16352 0, /* properties_required */
16353 0, /* properties_provided */
16354 0, /* properties_destroyed */
16355 0, /* todo_flags_start */
16356 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16360 struct register_pass_info insert_pass_mips_machine_reorg2
=
16362 &pass_mips_machine_reorg2
.pass
, /* pass */
16363 "dbr", /* reference_pass_name */
16364 1, /* ref_pass_instance_number */
16365 PASS_POS_INSERT_AFTER
/* po_op */
16368 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16369 in order to avoid duplicating too much logic from elsewhere. */
16372 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16373 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16376 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16377 bool use_sibcall_p
;
16379 /* Pretend to be a post-reload pass while generating rtl. */
16380 reload_completed
= 1;
16382 /* Mark the end of the (empty) prologue. */
16383 emit_note (NOTE_INSN_PROLOGUE_END
);
16385 /* Determine if we can use a sibcall to call FUNCTION directly. */
16386 fnaddr
= XEXP (DECL_RTL (function
), 0);
16387 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16388 && const_call_insn_operand (fnaddr
, Pmode
));
16390 /* Determine if we need to load FNADDR from the GOT. */
16392 && (mips_got_symbol_type_p
16393 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16395 /* Pick a global pointer. Use a call-clobbered register if
16396 TARGET_CALL_SAVED_GP. */
16397 cfun
->machine
->global_pointer
16398 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16399 cfun
->machine
->must_initialize_gp_p
= true;
16400 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16402 /* Set up the global pointer for n32 or n64 abicalls. */
16403 mips_emit_loadgp ();
16406 /* We need two temporary registers in some cases. */
16407 temp1
= gen_rtx_REG (Pmode
, 2);
16408 temp2
= gen_rtx_REG (Pmode
, 3);
16410 /* Find out which register contains the "this" pointer. */
16411 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16412 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16414 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16416 /* Add DELTA to THIS_RTX. */
16419 rtx offset
= GEN_INT (delta
);
16420 if (!SMALL_OPERAND (delta
))
16422 mips_emit_move (temp1
, offset
);
16425 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16428 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16429 if (vcall_offset
!= 0)
16433 /* Set TEMP1 to *THIS_RTX. */
16434 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16436 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16437 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16439 /* Load the offset and add it to THIS_RTX. */
16440 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16441 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16444 /* Jump to the target function. Use a sibcall if direct jumps are
16445 allowed, otherwise load the address into a register first. */
16448 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16449 SIBLING_CALL_P (insn
) = 1;
16453 /* This is messy. GAS treats "la $25,foo" as part of a call
16454 sequence and may allow a global "foo" to be lazily bound.
16455 The general move patterns therefore reject this combination.
16457 In this context, lazy binding would actually be OK
16458 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16459 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16460 We must therefore load the address via a temporary
16461 register if mips_dangerous_for_la25_p.
16463 If we jump to the temporary register rather than $25,
16464 the assembler can use the move insn to fill the jump's
16467 We can use the same technique for MIPS16 code, where $25
16468 is not a valid JR register. */
16469 if (TARGET_USE_PIC_FN_ADDR_REG
16471 && !mips_dangerous_for_la25_p (fnaddr
))
16472 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16473 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16475 if (TARGET_USE_PIC_FN_ADDR_REG
16476 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16477 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16478 emit_jump_insn (gen_indirect_jump (temp1
));
16481 /* Run just enough of rest_of_compilation. This sequence was
16482 "borrowed" from alpha.c. */
16483 insn
= get_insns ();
16484 split_all_insns_noflow ();
16485 mips16_lay_out_constants (true);
16486 shorten_branches (insn
);
16487 final_start_function (insn
, file
, 1);
16488 final (insn
, file
, 1);
16489 final_end_function ();
16491 /* Clean up the vars set above. Note that final_end_function resets
16492 the global pointer for us. */
16493 reload_completed
= 0;
16497 /* The last argument passed to mips_set_compression_mode,
16498 or negative if the function hasn't been called yet. */
16499 static unsigned int old_compression_mode
= -1;
16501 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16502 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16505 mips_set_compression_mode (unsigned int compression_mode
)
16508 if (compression_mode
== old_compression_mode
)
16511 /* Restore base settings of various flags. */
16512 target_flags
= mips_base_target_flags
;
16513 flag_schedule_insns
= mips_base_schedule_insns
;
16514 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16515 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16516 align_loops
= mips_base_align_loops
;
16517 align_jumps
= mips_base_align_jumps
;
16518 align_functions
= mips_base_align_functions
;
16519 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16520 target_flags
|= compression_mode
;
16522 if (compression_mode
& MASK_MIPS16
)
16524 /* Switch to MIPS16 mode. */
16525 target_flags
|= MASK_MIPS16
;
16527 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16528 target_flags
&= ~MASK_SYNCI
;
16530 /* Don't run the scheduler before reload, since it tends to
16531 increase register pressure. */
16532 flag_schedule_insns
= 0;
16534 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16535 the whole function to be in a single section. */
16536 flag_reorder_blocks_and_partition
= 0;
16538 /* Don't move loop invariants, because it tends to increase
16539 register pressure. It also introduces an extra move in cases
16540 where the constant is the first operand in a two-operand binary
16541 instruction, or when it forms a register argument to a functon
16543 flag_move_loop_invariants
= 0;
16545 target_flags
|= MASK_EXPLICIT_RELOCS
;
16547 /* Experiments suggest we get the best overall section-anchor
16548 results from using the range of an unextended LW or SW. Code
16549 that makes heavy use of byte or short accesses can do better
16550 with ranges of 0...31 and 0...63 respectively, but most code is
16551 sensitive to the range of LW and SW instead. */
16552 targetm
.min_anchor_offset
= 0;
16553 targetm
.max_anchor_offset
= 127;
16555 targetm
.const_anchor
= 0;
16557 /* MIPS16 has no BAL instruction. */
16558 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16560 /* The R4000 errata don't apply to any known MIPS16 cores.
16561 It's simpler to make the R4000 fixes and MIPS16 mode
16562 mutually exclusive. */
16563 target_flags
&= ~MASK_FIX_R4000
;
16565 if (flag_pic
&& !TARGET_OLDABI
)
16566 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16569 sorry ("MIPS16 -mxgot code");
16571 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16572 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16576 /* Switch to microMIPS or the standard encoding. */
16578 if (TARGET_MICROMIPS
)
16579 /* Avoid branch likely. */
16580 target_flags
&= ~MASK_BRANCHLIKELY
;
16582 /* Provide default values for align_* for 64-bit targets. */
16585 if (align_loops
== 0)
16587 if (align_jumps
== 0)
16589 if (align_functions
== 0)
16590 align_functions
= 8;
16593 targetm
.min_anchor_offset
= -32768;
16594 targetm
.max_anchor_offset
= 32767;
16596 targetm
.const_anchor
= 0x8000;
16599 /* (Re)initialize MIPS target internals for new ISA. */
16600 mips_init_relocs ();
16602 if (compression_mode
& MASK_MIPS16
)
16604 if (!mips16_globals
)
16605 mips16_globals
= save_target_globals_default_opts ();
16607 restore_target_globals (mips16_globals
);
16610 restore_target_globals (&default_target_globals
);
16612 old_compression_mode
= compression_mode
;
16615 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16616 function should use the MIPS16 or microMIPS ISA and switch modes
16620 mips_set_current_function (tree fndecl
)
16622 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16625 /* Allocate a chunk of memory for per-function machine-dependent data. */
16627 static struct machine_function
*
16628 mips_init_machine_status (void)
16630 return ggc_alloc_cleared_machine_function ();
16633 /* Return the processor associated with the given ISA level, or null
16634 if the ISA isn't valid. */
16636 static const struct mips_cpu_info
*
16637 mips_cpu_info_from_isa (int isa
)
16641 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16642 if (mips_cpu_info_table
[i
].isa
== isa
)
16643 return mips_cpu_info_table
+ i
;
16648 /* Return a mips_cpu_info entry determined by an option valued
16651 static const struct mips_cpu_info
*
16652 mips_cpu_info_from_opt (int opt
)
16656 case MIPS_ARCH_OPTION_FROM_ABI
:
16657 /* 'from-abi' selects the most compatible architecture for the
16658 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16659 ABIs. For the EABIs, we have to decide whether we're using
16660 the 32-bit or 64-bit version. */
16661 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16662 : ABI_NEEDS_64BIT_REGS
? 3
16663 : (TARGET_64BIT
? 3 : 1));
16665 case MIPS_ARCH_OPTION_NATIVE
:
16666 gcc_unreachable ();
16669 return &mips_cpu_info_table
[opt
];
16673 /* Return a default mips_cpu_info entry, given that no -march= option
16674 was explicitly specified. */
16676 static const struct mips_cpu_info
*
16677 mips_default_arch (void)
16679 #if defined (MIPS_CPU_STRING_DEFAULT)
16681 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16682 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16683 return mips_cpu_info_table
+ i
;
16684 gcc_unreachable ();
16685 #elif defined (MIPS_ISA_DEFAULT)
16686 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16688 /* 'from-abi' makes a good default: you get whatever the ABI
16690 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16694 /* Set up globals to generate code for the ISA or processor
16695 described by INFO. */
16698 mips_set_architecture (const struct mips_cpu_info
*info
)
16702 mips_arch_info
= info
;
16703 mips_arch
= info
->cpu
;
16704 mips_isa
= info
->isa
;
16708 /* Likewise for tuning. */
16711 mips_set_tune (const struct mips_cpu_info
*info
)
16715 mips_tune_info
= info
;
16716 mips_tune
= info
->cpu
;
16720 /* Implement TARGET_OPTION_OVERRIDE. */
16723 mips_option_override (void)
16725 int i
, start
, regno
, mode
;
16727 if (global_options_set
.x_mips_isa_option
)
16728 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16730 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16731 SUBTARGET_OVERRIDE_OPTIONS
;
16734 /* MIPS16 and microMIPS cannot coexist. */
16735 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16736 error ("unsupported combination: %s", "-mips16 -mmicromips");
16738 /* Save the base compression state and process flags as though we
16739 were generating uncompressed code. */
16740 mips_base_compression_flags
= TARGET_COMPRESSION
;
16741 target_flags
&= ~TARGET_COMPRESSION
;
16743 /* -mno-float overrides -mhard-float and -msoft-float. */
16744 if (TARGET_NO_FLOAT
)
16746 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16747 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16750 if (TARGET_FLIP_MIPS16
)
16751 TARGET_INTERLINK_COMPRESSED
= 1;
16753 /* Set the small data limit. */
16754 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16756 : MIPS_DEFAULT_GVALUE
);
16758 /* The following code determines the architecture and register size.
16759 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16760 The GAS and GCC code should be kept in sync as much as possible. */
16762 if (global_options_set
.x_mips_arch_option
)
16763 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16765 if (mips_isa_option_info
!= 0)
16767 if (mips_arch_info
== 0)
16768 mips_set_architecture (mips_isa_option_info
);
16769 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16770 error ("%<-%s%> conflicts with the other architecture options, "
16771 "which specify a %s processor",
16772 mips_isa_option_info
->name
,
16773 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16776 if (mips_arch_info
== 0)
16777 mips_set_architecture (mips_default_arch ());
16779 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16780 error ("%<-march=%s%> is not compatible with the selected ABI",
16781 mips_arch_info
->name
);
16783 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16784 if (global_options_set
.x_mips_tune_option
)
16785 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16787 if (mips_tune_info
== 0)
16788 mips_set_tune (mips_arch_info
);
16790 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16792 /* The user specified the size of the integer registers. Make sure
16793 it agrees with the ABI and ISA. */
16794 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16795 error ("%<-mgp64%> used with a 32-bit processor");
16796 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16797 error ("%<-mgp32%> used with a 64-bit ABI");
16798 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16799 error ("%<-mgp64%> used with a 32-bit ABI");
16803 /* Infer the integer register size from the ABI and processor.
16804 Restrict ourselves to 32-bit registers if that's all the
16805 processor has, or if the ABI cannot handle 64-bit registers. */
16806 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16807 target_flags
&= ~MASK_64BIT
;
16809 target_flags
|= MASK_64BIT
;
16812 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16814 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16815 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16816 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16817 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16818 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16820 if (!ISA_HAS_MXHC1
)
16821 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16822 " the target supports the mfhc1 and mthc1 instructions");
16823 else if (mips_abi
!= ABI_32
)
16824 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16830 /* -msingle-float selects 32-bit float registers. Otherwise the
16831 float registers should be the same size as the integer ones. */
16832 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16833 target_flags
|= MASK_FLOAT64
;
16835 target_flags
&= ~MASK_FLOAT64
;
16838 /* End of code shared with GAS. */
16840 /* The R5900 FPU only supports single precision. */
16841 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
16842 error ("unsupported combination: %s",
16843 "-march=r5900 -mhard-float -mdouble-float");
16845 /* If a -mlong* option was given, check that it matches the ABI,
16846 otherwise infer the -mlong* setting from the other options. */
16847 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16851 if (mips_abi
== ABI_N32
)
16852 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16853 else if (mips_abi
== ABI_32
)
16854 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16855 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16856 /* We have traditionally allowed non-abicalls code to use
16857 an LP64 form of o64. However, it would take a bit more
16858 effort to support the combination of 32-bit GOT entries
16859 and 64-bit pointers, so we treat the abicalls case as
16861 error ("the combination of %qs and %qs is incompatible with %qs",
16862 "-mabi=o64", "-mabicalls", "-mlong64");
16866 if (mips_abi
== ABI_64
)
16867 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16872 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16873 target_flags
|= MASK_LONG64
;
16875 target_flags
&= ~MASK_LONG64
;
16878 if (!TARGET_OLDABI
)
16879 flag_pcc_struct_return
= 0;
16881 /* Decide which rtx_costs structure to use. */
16883 mips_cost
= &mips_rtx_cost_optimize_size
;
16885 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16887 /* If the user hasn't specified a branch cost, use the processor's
16889 if (mips_branch_cost
== 0)
16890 mips_branch_cost
= mips_cost
->branch_cost
;
16892 /* If neither -mbranch-likely nor -mno-branch-likely was given
16893 on the command line, set MASK_BRANCHLIKELY based on the target
16894 architecture and tuning flags. Annulled delay slots are a
16895 size win, so we only consider the processor-specific tuning
16896 for !optimize_size. */
16897 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16899 if (ISA_HAS_BRANCHLIKELY
16901 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16902 target_flags
|= MASK_BRANCHLIKELY
;
16904 target_flags
&= ~MASK_BRANCHLIKELY
;
16906 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16907 warning (0, "the %qs architecture does not support branch-likely"
16908 " instructions", mips_arch_info
->name
);
16910 /* If the user hasn't specified -mimadd or -mno-imadd set
16911 MASK_IMADD based on the target architecture and tuning
16913 if ((target_flags_explicit
& MASK_IMADD
) == 0)
16915 if (ISA_HAS_MADD_MSUB
&&
16916 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
16917 target_flags
|= MASK_IMADD
;
16919 target_flags
&= ~MASK_IMADD
;
16921 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
16922 warning (0, "the %qs architecture does not support madd or msub"
16923 " instructions", mips_arch_info
->name
);
16925 /* The effect of -mabicalls isn't defined for the EABI. */
16926 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16928 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16929 target_flags
&= ~MASK_ABICALLS
;
16932 /* PIC requires -mabicalls. */
16935 if (mips_abi
== ABI_EABI
)
16936 error ("cannot generate position-independent code for %qs",
16938 else if (!TARGET_ABICALLS
)
16939 error ("position-independent code requires %qs", "-mabicalls");
16942 if (TARGET_ABICALLS_PIC2
)
16943 /* We need to set flag_pic for executables as well as DSOs
16944 because we may reference symbols that are not defined in
16945 the final executable. (MIPS does not use things like
16946 copy relocs, for example.)
16948 There is a body of code that uses __PIC__ to distinguish
16949 between -mabicalls and -mno-abicalls code. The non-__PIC__
16950 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16951 long as any indirect jumps use $25. */
16954 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16955 faster code, but at the expense of more nops. Enable it at -O3 and
16957 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16958 target_flags
|= MASK_VR4130_ALIGN
;
16960 /* Prefer a call to memcpy over inline code when optimizing for size,
16961 though see MOVE_RATIO in mips.h. */
16962 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16963 target_flags
|= MASK_MEMCPY
;
16965 /* If we have a nonzero small-data limit, check that the -mgpopt
16966 setting is consistent with the other target flags. */
16967 if (mips_small_data_threshold
> 0)
16971 if (!TARGET_EXPLICIT_RELOCS
)
16972 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16974 TARGET_LOCAL_SDATA
= false;
16975 TARGET_EXTERN_SDATA
= false;
16979 if (TARGET_VXWORKS_RTP
)
16980 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16982 if (TARGET_ABICALLS
)
16983 warning (0, "cannot use small-data accesses for %qs",
16988 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
16989 for all its floating point. */
16990 if (mips_nan
!= MIPS_IEEE_754_2008
)
16992 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
16993 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
16994 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
16997 /* Make sure that the user didn't turn off paired single support when
16998 MIPS-3D support is requested. */
17000 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17001 && !TARGET_PAIRED_SINGLE_FLOAT
)
17002 error ("%<-mips3d%> requires %<-mpaired-single%>");
17004 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17006 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17008 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17009 and TARGET_HARD_FLOAT_ABI are both true. */
17010 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17011 error ("%qs must be used with %qs",
17012 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17013 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17015 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17017 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17018 warning (0, "the %qs architecture does not support paired-single"
17019 " instructions", mips_arch_info
->name
);
17021 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17022 && !TARGET_CACHE_BUILTIN
)
17024 error ("%qs requires a target that provides the %qs instruction",
17025 "-mr10k-cache-barrier", "cache");
17026 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17029 /* If TARGET_DSPR2, enable MASK_DSP. */
17031 target_flags
|= MASK_DSP
;
17033 /* .eh_frame addresses should be the same width as a C pointer.
17034 Most MIPS ABIs support only one pointer size, so the assembler
17035 will usually know exactly how big an .eh_frame address is.
17037 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17038 originally defined to use 64-bit pointers (i.e. it is LP64), and
17039 this is still the default mode. However, we also support an n32-like
17040 ILP32 mode, which is selected by -mlong32. The problem is that the
17041 assembler has traditionally not had an -mlong option, so it has
17042 traditionally not known whether we're using the ILP32 or LP64 form.
17044 As it happens, gas versions up to and including 2.19 use _32-bit_
17045 addresses for EABI64 .cfi_* directives. This is wrong for the
17046 default LP64 mode, so we can't use the directives by default.
17047 Moreover, since gas's current behavior is at odds with gcc's
17048 default behavior, it seems unwise to rely on future versions
17049 of gas behaving the same way. We therefore avoid using .cfi
17050 directives for -mlong32 as well. */
17051 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17052 flag_dwarf2_cfi_asm
= 0;
17054 /* .cfi_* directives generate a read-only section, so fall back on
17055 manual .eh_frame creation if we need the section to be writable. */
17056 if (TARGET_WRITABLE_EH_FRAME
)
17057 flag_dwarf2_cfi_asm
= 0;
17059 mips_init_print_operand_punct ();
17061 /* Set up array to map GCC register number to debug register number.
17062 Ignore the special purpose register numbers. */
17064 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17066 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17067 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17068 mips_dwarf_regno
[i
] = i
;
17070 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17073 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17074 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17075 mips_dbx_regno
[i
] = i
+ start
;
17077 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17078 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17079 mips_dbx_regno
[i
] = i
+ start
;
17081 /* Accumulator debug registers use big-endian ordering. */
17082 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17083 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17084 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17085 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17086 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17088 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17089 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17092 /* Set up mips_hard_regno_mode_ok. */
17093 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17094 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17095 mips_hard_regno_mode_ok
[mode
][regno
]
17096 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17098 /* Function to allocate machine-dependent function status. */
17099 init_machine_status
= &mips_init_machine_status
;
17101 /* Default to working around R4000 errata only if the processor
17102 was selected explicitly. */
17103 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17104 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17105 target_flags
|= MASK_FIX_R4000
;
17107 /* Default to working around R4400 errata only if the processor
17108 was selected explicitly. */
17109 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17110 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17111 target_flags
|= MASK_FIX_R4400
;
17113 /* Default to working around R10000 errata only if the processor
17114 was selected explicitly. */
17115 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17116 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17117 target_flags
|= MASK_FIX_R10000
;
17119 /* Make sure that branch-likely instructions available when using
17120 -mfix-r10000. The instructions are not available if either:
17122 1. -mno-branch-likely was passed.
17123 2. The selected ISA does not support branch-likely and
17124 the command line does not include -mbranch-likely. */
17125 if (TARGET_FIX_R10000
17126 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17127 ? !ISA_HAS_BRANCHLIKELY
17128 : !TARGET_BRANCHLIKELY
))
17129 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17131 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17133 warning (0, "the %qs architecture does not support the synci "
17134 "instruction", mips_arch_info
->name
);
17135 target_flags
&= ~MASK_SYNCI
;
17138 /* Only optimize PIC indirect calls if they are actually required. */
17139 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17140 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17142 /* Save base state of options. */
17143 mips_base_target_flags
= target_flags
;
17144 mips_base_schedule_insns
= flag_schedule_insns
;
17145 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17146 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17147 mips_base_align_loops
= align_loops
;
17148 mips_base_align_jumps
= align_jumps
;
17149 mips_base_align_functions
= align_functions
;
17151 /* Now select the ISA mode.
17153 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17154 later if required. */
17155 mips_set_compression_mode (0);
17157 /* We register a second machine specific reorg pass after delay slot
17158 filling. Registering the pass must be done at start up. It's
17159 convenient to do it here. */
17160 register_pass (&insert_pass_mips_machine_reorg2
);
17162 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17163 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17166 /* Swap the register information for registers I and I + 1, which
17167 currently have the wrong endianness. Note that the registers'
17168 fixedness and call-clobberedness might have been set on the
17172 mips_swap_registers (unsigned int i
)
17177 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17178 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17180 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17181 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17182 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17183 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17189 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17192 mips_conditional_register_usage (void)
17197 /* These DSP control register fields are global. */
17198 global_regs
[CCDSP_PO_REGNUM
] = 1;
17199 global_regs
[CCDSP_SC_REGNUM
] = 1;
17202 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17203 reg_class_contents
[(int) DSP_ACC_REGS
]);
17205 if (!TARGET_HARD_FLOAT
)
17207 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17208 reg_class_contents
[(int) FP_REGS
]);
17209 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17210 reg_class_contents
[(int) ST_REGS
]);
17212 else if (!ISA_HAS_8CC
)
17214 /* We only have a single condition-code register. We implement
17215 this by fixing all the condition-code registers and generating
17216 RTL that refers directly to ST_REG_FIRST. */
17217 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17218 reg_class_contents
[(int) ST_REGS
]);
17219 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17220 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17224 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17225 are call-saved, and saving them via a MIPS16 register would
17226 probably waste more time than just reloading the value.
17228 We permit the $t temporary registers when optimizing for speed
17229 but not when optimizing for space because using them results in
17230 code that is larger (but faster) then not using them. We do
17231 allow $24 (t8) because it is used in CMP and CMPI instructions
17232 and $25 (t9) because it is used as the function call address in
17235 fixed_regs
[18] = call_used_regs
[18] = 1;
17236 fixed_regs
[19] = call_used_regs
[19] = 1;
17237 fixed_regs
[20] = call_used_regs
[20] = 1;
17238 fixed_regs
[21] = call_used_regs
[21] = 1;
17239 fixed_regs
[22] = call_used_regs
[22] = 1;
17240 fixed_regs
[23] = call_used_regs
[23] = 1;
17241 fixed_regs
[26] = call_used_regs
[26] = 1;
17242 fixed_regs
[27] = call_used_regs
[27] = 1;
17243 fixed_regs
[30] = call_used_regs
[30] = 1;
17246 fixed_regs
[8] = call_used_regs
[8] = 1;
17247 fixed_regs
[9] = call_used_regs
[9] = 1;
17248 fixed_regs
[10] = call_used_regs
[10] = 1;
17249 fixed_regs
[11] = call_used_regs
[11] = 1;
17250 fixed_regs
[12] = call_used_regs
[12] = 1;
17251 fixed_regs
[13] = call_used_regs
[13] = 1;
17252 fixed_regs
[14] = call_used_regs
[14] = 1;
17253 fixed_regs
[15] = call_used_regs
[15] = 1;
17256 /* Do not allow HI and LO to be treated as register operands.
17257 There are no MTHI or MTLO instructions (or any real need
17258 for them) and one-way registers cannot easily be reloaded. */
17259 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17260 reg_class_contents
[(int) MD_REGS
]);
17262 /* $f20-$f23 are call-clobbered for n64. */
17263 if (mips_abi
== ABI_64
)
17266 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17267 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17269 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17271 if (mips_abi
== ABI_N32
)
17274 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17275 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17277 /* Make sure that double-register accumulator values are correctly
17278 ordered for the current endianness. */
17279 if (TARGET_LITTLE_ENDIAN
)
17281 unsigned int regno
;
17283 mips_swap_registers (MD_REG_FIRST
);
17284 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17285 mips_swap_registers (regno
);
17289 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17290 other registers for instructions for which it is possible. This
17291 encourages the compiler to use CMP in cases where an XOR would
17292 require some register shuffling. */
17295 mips_order_regs_for_local_alloc (void)
17299 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17300 reg_alloc_order
[i
] = i
;
17304 /* It really doesn't matter where we put register 0, since it is
17305 a fixed register anyhow. */
17306 reg_alloc_order
[0] = 24;
17307 reg_alloc_order
[24] = 0;
17311 /* Implement EH_USES. */
17314 mips_eh_uses (unsigned int regno
)
17316 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17318 /* We need to force certain registers to be live in order to handle
17319 PIC long branches correctly. See mips_must_initialize_gp_p for
17321 if (mips_cfun_has_cprestore_slot_p ())
17323 if (regno
== CPRESTORE_SLOT_REGNUM
)
17328 if (cfun
->machine
->global_pointer
== regno
)
17336 /* Implement EPILOGUE_USES. */
17339 mips_epilogue_uses (unsigned int regno
)
17341 /* Say that the epilogue uses the return address register. Note that
17342 in the case of sibcalls, the values "used by the epilogue" are
17343 considered live at the start of the called function. */
17344 if (regno
== RETURN_ADDR_REGNUM
)
17347 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17348 See the comment above load_call<mode> for details. */
17349 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17352 /* An interrupt handler must preserve some registers that are
17353 ordinarily call-clobbered. */
17354 if (cfun
->machine
->interrupt_handler_p
17355 && mips_interrupt_extra_call_saved_reg_p (regno
))
17361 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17364 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17366 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17369 /* Return true if INSN needs to be wrapped in ".set noat".
17370 INSN has NOPERANDS operands, stored in OPVEC. */
17373 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17377 if (recog_memoized (insn
) >= 0)
17378 for (i
= 0; i
< noperands
; i
++)
17379 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17384 /* Implement FINAL_PRESCAN_INSN. */
17387 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17389 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17390 mips_push_asm_switch (&mips_noat
);
17393 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17396 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17397 rtx
*opvec
, int noperands
)
17399 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17400 mips_pop_asm_switch (&mips_noat
);
17403 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17404 EXT_CODE is the code of the extension used. Return NULL if widening
17405 multiplication shouldn't be used. */
17408 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17412 signed_p
= ext_code
== SIGN_EXTEND
;
17415 /* Don't use widening multiplication with MULT when we have DMUL. Even
17416 with the extension of its input operands DMUL is faster. Note that
17417 the extension is not needed for signed multiplication. In order to
17418 ensure that we always remove the redundant sign-extension in this
17419 case we still expand mulsidi3 for DMUL. */
17421 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17424 ? gen_mulsidi3_64bit_mips16
17425 : gen_umulsidi3_64bit_mips16
);
17426 if (TARGET_FIX_R4000
)
17428 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17434 ? gen_mulsidi3_32bit_mips16
17435 : gen_umulsidi3_32bit_mips16
);
17436 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17437 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17438 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17442 /* Return true if PATTERN matches the kind of instruction generated by
17443 umips_build_save_restore. SAVE_P is true for store. */
17446 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17450 HOST_WIDE_INT first_offset
= 0;
17451 rtx first_base
= 0;
17452 unsigned int regmask
= 0;
17454 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17456 rtx set
, reg
, mem
, this_base
;
17457 HOST_WIDE_INT this_offset
;
17459 /* Check that we have a SET. */
17460 set
= XVECEXP (pattern
, 0, n
);
17461 if (GET_CODE (set
) != SET
)
17464 /* Check that the SET is a load (if restoring) or a store
17466 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17467 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17470 /* Check that the address is the sum of base and a possibly-zero
17471 constant offset. Determine if the offset is in range. */
17472 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17473 if (!REG_P (this_base
))
17478 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17480 first_base
= this_base
;
17481 first_offset
= this_offset
;
17485 /* Check that the save slots are consecutive. */
17486 if (REGNO (this_base
) != REGNO (first_base
)
17487 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17491 /* Check that SET's other operand is a register. */
17492 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17496 regmask
|= 1 << REGNO (reg
);
17499 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17500 if (regmask
== umips_swm_mask
[i
])
17506 /* Return the assembly instruction for microMIPS LWM or SWM.
17507 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17510 umips_output_save_restore (bool save_p
, rtx pattern
)
17512 static char buffer
[300];
17515 HOST_WIDE_INT offset
;
17516 rtx base
, mem
, set
, last_set
, last_reg
;
17518 /* Parse the pattern. */
17519 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17521 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17523 n
= XVECLEN (pattern
, 0);
17525 set
= XVECEXP (pattern
, 0, 0);
17526 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17527 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17529 last_set
= XVECEXP (pattern
, 0, n
- 1);
17530 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17532 if (REGNO (last_reg
) == 31)
17535 gcc_assert (n
<= 9);
17539 s
+= sprintf (s
, "%s,", reg_names
[16]);
17541 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17543 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17546 if (REGNO (last_reg
) == 31)
17547 s
+= sprintf (s
, "%s,", reg_names
[31]);
17549 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17553 /* Return true if MEM1 and MEM2 use the same base register, and the
17554 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17555 register into (from) which the contents of MEM1 will be loaded
17556 (stored), depending on the value of LOAD_P.
17557 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17560 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17561 rtx first_reg
, rtx mem1
, rtx mem2
)
17564 HOST_WIDE_INT offset1
, offset2
;
17566 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17569 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17570 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17572 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17575 /* Avoid invalid load pair instructions. */
17576 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17579 /* We must avoid this case for anti-dependence.
17582 first_reg is $2, but the base is $3. */
17585 && REGNO (first_reg
) + 1 == REGNO (base1
))
17588 if (offset2
!= offset1
+ 4)
17591 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17597 /* OPERANDS describes the operands to a pair of SETs, in the order
17598 dest1, src1, dest2, src2. Return true if the operands can be used
17599 in an LWP or SWP instruction; LOAD_P says which. */
17602 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17604 rtx reg1
, reg2
, mem1
, mem2
;
17608 reg1
= operands
[0];
17609 reg2
= operands
[2];
17610 mem1
= operands
[1];
17611 mem2
= operands
[3];
17615 reg1
= operands
[1];
17616 reg2
= operands
[3];
17617 mem1
= operands
[0];
17618 mem2
= operands
[2];
17621 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17622 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17624 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17625 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17630 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17631 the first register is REG and the first memory slot is MEM.
17632 LOAD_P is true for LWP. */
17635 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17637 rtx ops
[] = {reg
, mem
};
17640 output_asm_insn ("lwp\t%0,%1", ops
);
17642 output_asm_insn ("swp\t%0,%1", ops
);
17645 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17646 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17649 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17651 rtx reg1
, reg2
, mem1
, mem2
;
17654 reg1
= operands
[0];
17655 reg2
= operands
[2];
17656 mem1
= operands
[1];
17657 mem2
= operands
[3];
17661 reg1
= operands
[1];
17662 reg2
= operands
[3];
17663 mem1
= operands
[0];
17664 mem2
= operands
[2];
17667 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17669 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17673 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17674 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17677 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17680 umips_movep_target_p (rtx reg1
, rtx reg2
)
17682 int regno1
, regno2
, pair
;
17684 static const int match
[8] = {
17685 0x00000060, /* 5, 6 */
17686 0x000000a0, /* 5, 7 */
17687 0x000000c0, /* 6, 7 */
17688 0x00200010, /* 4, 21 */
17689 0x00400010, /* 4, 22 */
17690 0x00000030, /* 4, 5 */
17691 0x00000050, /* 4, 6 */
17692 0x00000090 /* 4, 7 */
17695 if (!REG_P (reg1
) || !REG_P (reg2
))
17698 regno1
= REGNO (reg1
);
17699 regno2
= REGNO (reg2
);
17701 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17704 pair
= (1 << regno1
) | (1 << regno2
);
17706 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17707 if (pair
== match
[i
])
17713 /* Return the size in bytes of the trampoline code, padded to
17714 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17715 function address immediately follow. */
17718 mips_trampoline_code_size (void)
17720 if (TARGET_USE_PIC_FN_ADDR_REG
)
17722 else if (ptr_mode
== DImode
)
17724 else if (ISA_HAS_LOAD_DELAY
)
17730 /* Implement TARGET_TRAMPOLINE_INIT. */
17733 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17735 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17738 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17740 /* Work out the offsets of the pointers from the start of the
17741 trampoline code. */
17742 end_addr_offset
= mips_trampoline_code_size ();
17743 static_chain_offset
= end_addr_offset
;
17744 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17746 /* Get pointers to the beginning and end of the code block. */
17747 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17748 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17750 #define OP(X) gen_int_mode (X, SImode)
17752 /* Build up the code in TRAMPOLINE. */
17754 if (TARGET_USE_PIC_FN_ADDR_REG
)
17756 /* $25 contains the address of the trampoline. Emit code of the form:
17758 l[wd] $1, target_function_offset($25)
17759 l[wd] $static_chain, static_chain_offset($25)
17762 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17763 target_function_offset
,
17764 PIC_FUNCTION_ADDR_REGNUM
));
17765 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17766 static_chain_offset
,
17767 PIC_FUNCTION_ADDR_REGNUM
));
17768 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17769 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17771 else if (ptr_mode
== DImode
)
17773 /* It's too cumbersome to create the full 64-bit address, so let's
17779 1: l[wd] $25, target_function_offset - 12($31)
17780 l[wd] $static_chain, static_chain_offset - 12($31)
17784 where 12 is the offset of "1:" from the start of the code block. */
17785 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17786 trampoline
[i
++] = OP (MIPS_BAL (1));
17787 trampoline
[i
++] = OP (MIPS_NOP
);
17788 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17789 target_function_offset
- 12,
17790 RETURN_ADDR_REGNUM
));
17791 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17792 static_chain_offset
- 12,
17793 RETURN_ADDR_REGNUM
));
17794 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17795 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17799 /* If the target has load delays, emit:
17801 lui $1, %hi(end_addr)
17802 lw $25, %lo(end_addr + ...)($1)
17803 lw $static_chain, %lo(end_addr + ...)($1)
17809 lui $1, %hi(end_addr)
17810 lw $25, %lo(end_addr + ...)($1)
17812 lw $static_chain, %lo(end_addr + ...)($1). */
17814 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17815 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17816 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17817 NULL
, false, OPTAB_WIDEN
);
17818 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17819 NULL
, false, OPTAB_WIDEN
);
17820 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17822 /* Emit the LUI. */
17823 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17824 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17825 NULL
, false, OPTAB_WIDEN
);
17827 /* Emit the load of the target function. */
17828 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17829 target_function_offset
- end_addr_offset
,
17831 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17832 NULL
, false, OPTAB_WIDEN
);
17834 /* Emit the JR here, if we can. */
17835 if (!ISA_HAS_LOAD_DELAY
)
17836 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17838 /* Emit the load of the static chain register. */
17839 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17840 static_chain_offset
- end_addr_offset
,
17842 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17843 NULL
, false, OPTAB_WIDEN
);
17845 /* Emit the JR, if we couldn't above. */
17846 if (ISA_HAS_LOAD_DELAY
)
17848 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17849 trampoline
[i
++] = OP (MIPS_NOP
);
17855 /* Copy the trampoline code. Leave any padding uninitialized. */
17856 for (j
= 0; j
< i
; j
++)
17858 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17859 mips_emit_move (mem
, trampoline
[j
]);
17862 /* Set up the static chain pointer field. */
17863 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17864 mips_emit_move (mem
, chain_value
);
17866 /* Set up the target function field. */
17867 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17868 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17870 /* Flush the code part of the trampoline. */
17871 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17872 emit_insn (gen_clear_cache (addr
, end_addr
));
17875 /* Implement FUNCTION_PROFILER. */
17877 void mips_function_profiler (FILE *file
)
17880 sorry ("mips16 function profiling");
17881 if (TARGET_LONG_CALLS
)
17883 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17884 if (Pmode
== DImode
)
17885 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
17887 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
17889 mips_push_asm_switch (&mips_noat
);
17890 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
17891 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
17892 /* _mcount treats $2 as the static chain register. */
17893 if (cfun
->static_chain_decl
!= NULL
)
17894 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
17895 reg_names
[STATIC_CHAIN_REGNUM
]);
17896 if (TARGET_MCOUNT_RA_ADDRESS
)
17898 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17899 ra save location. */
17900 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
17901 /* ra not saved, pass zero. */
17902 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
17904 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
17905 Pmode
== DImode
? "dla" : "la", reg_names
[12],
17906 cfun
->machine
->frame
.ra_fp_offset
,
17907 reg_names
[STACK_POINTER_REGNUM
]);
17909 if (!TARGET_NEWABI
)
17911 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17912 TARGET_64BIT
? "dsubu" : "subu",
17913 reg_names
[STACK_POINTER_REGNUM
],
17914 reg_names
[STACK_POINTER_REGNUM
],
17915 Pmode
== DImode
? 16 : 8);
17917 if (TARGET_LONG_CALLS
)
17918 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
17920 fprintf (file
, "\tjal\t_mcount\n");
17921 mips_pop_asm_switch (&mips_noat
);
17922 /* _mcount treats $2 as the static chain register. */
17923 if (cfun
->static_chain_decl
!= NULL
)
17924 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
17928 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17929 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17930 when TARGET_LOONGSON_VECTORS is true. */
17932 static unsigned HOST_WIDE_INT
17933 mips_shift_truncation_mask (enum machine_mode mode
)
17935 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
17938 return GET_MODE_BITSIZE (mode
) - 1;
17941 /* Implement TARGET_PREPARE_PCH_SAVE. */
17944 mips_prepare_pch_save (void)
17946 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17947 setting should be irrelevant. The question then is: which setting
17948 makes most sense at load time?
17950 The PCH is loaded before the first token is read. We should never
17951 have switched into MIPS16 mode by that point, and thus should not
17952 have populated mips16_globals. Nor can we load the entire contents
17953 of mips16_globals from the PCH file, because mips16_globals contains
17954 a combination of GGC and non-GGC data.
17956 There is therefore no point in trying save the GGC part of
17957 mips16_globals to the PCH file, or to preserve MIPS16ness across
17958 the PCH save and load. The loading compiler would not have access
17959 to the non-GGC parts of mips16_globals (either from the PCH file,
17960 or from a copy that the loading compiler generated itself) and would
17961 have to call target_reinit anyway.
17963 It therefore seems best to switch back to non-MIPS16 mode at
17964 save time, and to ensure that mips16_globals remains null after
17966 mips_set_compression_mode (0);
17967 mips16_globals
= 0;
17970 /* Generate or test for an insn that supports a constant permutation. */
17972 #define MAX_VECT_LEN 8
17974 struct expand_vec_perm_d
17976 rtx target
, op0
, op1
;
17977 unsigned char perm
[MAX_VECT_LEN
];
17978 enum machine_mode vmode
;
17979 unsigned char nelt
;
17984 /* Construct (set target (vec_select op0 (parallel perm))) and
17985 return true if that's a valid instruction in the active ISA. */
17988 mips_expand_vselect (rtx target
, rtx op0
,
17989 const unsigned char *perm
, unsigned nelt
)
17991 rtx rperm
[MAX_VECT_LEN
], x
;
17994 for (i
= 0; i
< nelt
; ++i
)
17995 rperm
[i
] = GEN_INT (perm
[i
]);
17997 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
17998 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
17999 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18002 if (recog_memoized (x
) < 0)
18010 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18013 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18014 const unsigned char *perm
, unsigned nelt
)
18016 enum machine_mode v2mode
;
18019 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18020 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18021 return mips_expand_vselect (target
, x
, perm
, nelt
);
18024 /* Recognize patterns for even-odd extraction. */
18027 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18029 unsigned i
, odd
, nelt
= d
->nelt
;
18030 rtx t0
, t1
, t2
, t3
;
18032 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18034 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18041 for (i
= 1; i
< nelt
; ++i
)
18042 if (d
->perm
[i
] != i
* 2 + odd
)
18048 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18049 t0
= gen_reg_rtx (d
->vmode
);
18050 t1
= gen_reg_rtx (d
->vmode
);
18054 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18055 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18057 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18059 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18063 t2
= gen_reg_rtx (d
->vmode
);
18064 t3
= gen_reg_rtx (d
->vmode
);
18065 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18066 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18067 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18068 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18070 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18072 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18076 gcc_unreachable ();
18081 /* Recognize patterns for the Loongson PSHUFH instruction. */
18084 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18089 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18091 if (d
->vmode
!= V4HImode
)
18096 /* Convert the selector into the packed 8-bit form for pshufh. */
18097 /* Recall that loongson is little-endian only. No big-endian
18098 adjustment required. */
18099 for (i
= mask
= 0; i
< 4; i
++)
18100 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18101 rmask
= force_reg (SImode
, GEN_INT (mask
));
18103 if (d
->one_vector_p
)
18104 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18107 rtx t0
, t1
, x
, merge
, rmerge
[4];
18109 t0
= gen_reg_rtx (V4HImode
);
18110 t1
= gen_reg_rtx (V4HImode
);
18111 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18112 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18114 for (i
= 0; i
< 4; ++i
)
18115 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18116 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18117 merge
= force_reg (V4HImode
, merge
);
18119 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18120 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18122 x
= gen_rtx_NOT (V4HImode
, merge
);
18123 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18124 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18126 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18127 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18133 /* Recognize broadcast patterns for the Loongson. */
18136 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18141 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18143 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18144 if (d
->vmode
!= V8QImode
)
18146 if (!d
->one_vector_p
)
18150 for (i
= 1; i
< 8; ++i
)
18151 if (d
->perm
[i
] != elt
)
18157 /* With one interleave we put two of the desired element adjacent. */
18158 t0
= gen_reg_rtx (V8QImode
);
18160 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18162 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18164 /* Shuffle that one HImode element into all locations. */
18167 t1
= gen_reg_rtx (V4HImode
);
18168 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18169 force_reg (SImode
, GEN_INT (elt
))));
18171 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18176 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18178 unsigned int i
, nelt
= d
->nelt
;
18179 unsigned char perm2
[MAX_VECT_LEN
];
18181 if (d
->one_vector_p
)
18183 /* Try interleave with alternating operands. */
18184 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18185 for (i
= 1; i
< nelt
; i
+= 2)
18187 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18192 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18196 /* Try again with swapped operands. */
18197 for (i
= 0; i
< nelt
; ++i
)
18198 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18199 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18203 if (mips_expand_vpc_loongson_even_odd (d
))
18205 if (mips_expand_vpc_loongson_pshufh (d
))
18207 if (mips_expand_vpc_loongson_bcast (d
))
18212 /* Expand a vec_perm_const pattern. */
18215 mips_expand_vec_perm_const (rtx operands
[4])
18217 struct expand_vec_perm_d d
;
18218 int i
, nelt
, which
;
18219 unsigned char orig_perm
[MAX_VECT_LEN
];
18223 d
.target
= operands
[0];
18224 d
.op0
= operands
[1];
18225 d
.op1
= operands
[2];
18228 d
.vmode
= GET_MODE (d
.target
);
18229 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18230 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18231 d
.testing_p
= false;
18233 for (i
= which
= 0; i
< nelt
; ++i
)
18235 rtx e
= XVECEXP (sel
, 0, i
);
18236 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18237 which
|= (ei
< nelt
? 1 : 2);
18240 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18248 d
.one_vector_p
= false;
18249 if (!rtx_equal_p (d
.op0
, d
.op1
))
18254 for (i
= 0; i
< nelt
; ++i
)
18255 d
.perm
[i
] &= nelt
- 1;
18257 d
.one_vector_p
= true;
18262 d
.one_vector_p
= true;
18266 ok
= mips_expand_vec_perm_const_1 (&d
);
18268 /* If we were given a two-vector permutation which just happened to
18269 have both input vectors equal, we folded this into a one-vector
18270 permutation. There are several loongson patterns that are matched
18271 via direct vec_select+vec_concat expansion, but we do not have
18272 support in mips_expand_vec_perm_const_1 to guess the adjustment
18273 that should be made for a single operand. Just try again with
18274 the original permutation. */
18275 if (!ok
&& which
== 3)
18277 d
.op0
= operands
[1];
18278 d
.op1
= operands
[2];
18279 d
.one_vector_p
= false;
18280 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18281 ok
= mips_expand_vec_perm_const_1 (&d
);
18287 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18290 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18291 const unsigned char *sel
)
18293 struct expand_vec_perm_d d
;
18294 unsigned int i
, nelt
, which
;
18298 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18299 d
.testing_p
= true;
18300 memcpy (d
.perm
, sel
, nelt
);
18302 /* Categorize the set of elements in the selector. */
18303 for (i
= which
= 0; i
< nelt
; ++i
)
18305 unsigned char e
= d
.perm
[i
];
18306 gcc_assert (e
< 2 * nelt
);
18307 which
|= (e
< nelt
? 1 : 2);
18310 /* For all elements from second vector, fold the elements to first. */
18312 for (i
= 0; i
< nelt
; ++i
)
18315 /* Check whether the mask can be applied to the vector type. */
18316 d
.one_vector_p
= (which
!= 3);
18318 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18319 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18320 if (!d
.one_vector_p
)
18321 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18324 ret
= mips_expand_vec_perm_const_1 (&d
);
18330 /* Expand an integral vector unpack operation. */
18333 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18335 enum machine_mode imode
= GET_MODE (operands
[1]);
18336 rtx (*unpack
) (rtx
, rtx
, rtx
);
18337 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18338 rtx tmp
, dest
, zero
;
18344 unpack
= gen_loongson_punpckhbh
;
18346 unpack
= gen_loongson_punpcklbh
;
18347 cmpgt
= gen_loongson_pcmpgtb
;
18351 unpack
= gen_loongson_punpckhhw
;
18353 unpack
= gen_loongson_punpcklhw
;
18354 cmpgt
= gen_loongson_pcmpgth
;
18357 gcc_unreachable ();
18360 zero
= force_reg (imode
, CONST0_RTX (imode
));
18365 tmp
= gen_reg_rtx (imode
);
18366 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18369 dest
= gen_reg_rtx (imode
);
18370 emit_insn (unpack (dest
, operands
[1], tmp
));
18372 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18375 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18378 mips_constant_elt_p (rtx x
)
18380 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18383 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18386 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18388 struct expand_vec_perm_d d
;
18392 if (elt
!= const0_rtx
)
18393 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18395 elt
= gen_lowpart (DImode
, elt
);
18397 t1
= gen_reg_rtx (vmode
);
18401 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18404 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18407 gcc_unreachable ();
18410 memset (&d
, 0, sizeof (d
));
18415 d
.nelt
= GET_MODE_NUNITS (vmode
);
18416 d
.one_vector_p
= true;
18418 ok
= mips_expand_vec_perm_const_1 (&d
);
18422 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18423 elements of VALS with zeros, copy the constant vector to TARGET. */
18426 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18427 rtx target
, rtx vals
)
18429 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18432 for (i
= 0; i
< nelt
; ++i
)
18434 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18435 RTVEC_ELT (vec
, i
) = const0_rtx
;
18438 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18442 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18445 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18447 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18449 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18450 GEN_INT (one_var
)));
18453 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18456 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18457 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18459 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18460 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18463 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18465 for (i
= 0; i
< nelt
; ++i
)
18467 rtx x
= XVECEXP (vals
, 0, i
);
18468 if (!mips_constant_elt_p (x
))
18469 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18472 emit_move_insn (target
, mem
);
18475 /* Expand a vector initialization. */
18478 mips_expand_vector_init (rtx target
, rtx vals
)
18480 enum machine_mode vmode
= GET_MODE (target
);
18481 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18482 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18483 unsigned nvar
= 0, one_var
= -1u;
18484 bool all_same
= true;
18487 for (i
= 0; i
< nelt
; ++i
)
18489 x
= XVECEXP (vals
, 0, i
);
18490 if (!mips_constant_elt_p (x
))
18491 nvar
++, one_var
= i
;
18492 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18496 /* Load constants from the pool, or whatever's handy. */
18499 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18503 /* For two-part initialization, always use CONCAT. */
18506 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18507 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18508 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18509 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18513 /* Loongson is the only cpu with vectors with more elements. */
18514 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18516 /* If all values are identical, broadcast the value. */
18519 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18523 /* If we've only got one non-variable V4HImode, use PINSRH. */
18524 if (nvar
== 1 && vmode
== V4HImode
)
18526 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18530 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18533 /* Expand a vector reduction. */
18536 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18538 enum machine_mode vmode
= GET_MODE (in
);
18539 unsigned char perm2
[2];
18540 rtx last
, next
, fold
, x
;
18544 fold
= gen_reg_rtx (vmode
);
18548 /* Use PUL/PLU to produce { L, H } op { H, L }.
18549 By reversing the pair order, rather than a pure interleave high,
18550 we avoid erroneous exceptional conditions that we might otherwise
18551 produce from the computation of H op H. */
18554 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18559 /* Use interleave to produce { H, L } op { H, H }. */
18560 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18564 /* Perform the first reduction with interleave,
18565 and subsequent reductions with shifts. */
18566 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18568 next
= gen_reg_rtx (vmode
);
18569 emit_insn (gen (next
, last
, fold
));
18572 fold
= gen_reg_rtx (vmode
);
18573 x
= force_reg (SImode
, GEN_INT (16));
18574 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18578 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18580 next
= gen_reg_rtx (vmode
);
18581 emit_insn (gen (next
, last
, fold
));
18584 fold
= gen_reg_rtx (vmode
);
18585 x
= force_reg (SImode
, GEN_INT (16));
18586 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18588 next
= gen_reg_rtx (vmode
);
18589 emit_insn (gen (next
, last
, fold
));
18592 fold
= gen_reg_rtx (vmode
);
18593 x
= force_reg (SImode
, GEN_INT (8));
18594 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18598 gcc_unreachable ();
18601 emit_insn (gen (target
, last
, fold
));
18604 /* Expand a vector minimum/maximum. */
18607 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18608 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18610 enum machine_mode vmode
= GET_MODE (target
);
18613 tc
= gen_reg_rtx (vmode
);
18614 t0
= gen_reg_rtx (vmode
);
18615 t1
= gen_reg_rtx (vmode
);
18618 emit_insn (cmp (tc
, op0
, op1
));
18620 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18621 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18623 x
= gen_rtx_NOT (vmode
, tc
);
18624 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18625 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18627 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18628 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18631 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18634 mips_case_values_threshold (void)
18636 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18637 if (TARGET_MIPS16
&& optimize_size
)
18640 return default_case_values_threshold ();
18643 /* Initialize the GCC target structure. */
18644 #undef TARGET_ASM_ALIGNED_HI_OP
18645 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18646 #undef TARGET_ASM_ALIGNED_SI_OP
18647 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18648 #undef TARGET_ASM_ALIGNED_DI_OP
18649 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18651 #undef TARGET_OPTION_OVERRIDE
18652 #define TARGET_OPTION_OVERRIDE mips_option_override
18654 #undef TARGET_LEGITIMIZE_ADDRESS
18655 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18657 #undef TARGET_ASM_FUNCTION_PROLOGUE
18658 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18659 #undef TARGET_ASM_FUNCTION_EPILOGUE
18660 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18661 #undef TARGET_ASM_SELECT_RTX_SECTION
18662 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18663 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18664 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18666 #undef TARGET_SCHED_INIT
18667 #define TARGET_SCHED_INIT mips_sched_init
18668 #undef TARGET_SCHED_REORDER
18669 #define TARGET_SCHED_REORDER mips_sched_reorder
18670 #undef TARGET_SCHED_REORDER2
18671 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18672 #undef TARGET_SCHED_VARIABLE_ISSUE
18673 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18674 #undef TARGET_SCHED_ADJUST_COST
18675 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18676 #undef TARGET_SCHED_ISSUE_RATE
18677 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18678 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18679 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18680 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18681 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18682 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18683 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18684 mips_multipass_dfa_lookahead
18685 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18686 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18687 mips_small_register_classes_for_mode_p
18689 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18690 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18692 #undef TARGET_INSERT_ATTRIBUTES
18693 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18694 #undef TARGET_MERGE_DECL_ATTRIBUTES
18695 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18696 #undef TARGET_CAN_INLINE_P
18697 #define TARGET_CAN_INLINE_P mips_can_inline_p
18698 #undef TARGET_SET_CURRENT_FUNCTION
18699 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18701 #undef TARGET_VALID_POINTER_MODE
18702 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18703 #undef TARGET_REGISTER_MOVE_COST
18704 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18705 #undef TARGET_MEMORY_MOVE_COST
18706 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18707 #undef TARGET_RTX_COSTS
18708 #define TARGET_RTX_COSTS mips_rtx_costs
18709 #undef TARGET_ADDRESS_COST
18710 #define TARGET_ADDRESS_COST mips_address_cost
18712 #undef TARGET_IN_SMALL_DATA_P
18713 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18715 #undef TARGET_MACHINE_DEPENDENT_REORG
18716 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18718 #undef TARGET_PREFERRED_RELOAD_CLASS
18719 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18721 #undef TARGET_EXPAND_TO_RTL_HOOK
18722 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18723 #undef TARGET_ASM_FILE_START
18724 #define TARGET_ASM_FILE_START mips_file_start
18725 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18726 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18727 #undef TARGET_ASM_CODE_END
18728 #define TARGET_ASM_CODE_END mips_code_end
18730 #undef TARGET_INIT_LIBFUNCS
18731 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18733 #undef TARGET_BUILD_BUILTIN_VA_LIST
18734 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18735 #undef TARGET_EXPAND_BUILTIN_VA_START
18736 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18737 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18738 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18740 #undef TARGET_PROMOTE_FUNCTION_MODE
18741 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18742 #undef TARGET_PROMOTE_PROTOTYPES
18743 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18745 #undef TARGET_FUNCTION_VALUE
18746 #define TARGET_FUNCTION_VALUE mips_function_value
18747 #undef TARGET_LIBCALL_VALUE
18748 #define TARGET_LIBCALL_VALUE mips_libcall_value
18749 #undef TARGET_FUNCTION_VALUE_REGNO_P
18750 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18751 #undef TARGET_RETURN_IN_MEMORY
18752 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18753 #undef TARGET_RETURN_IN_MSB
18754 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18756 #undef TARGET_ASM_OUTPUT_MI_THUNK
18757 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18758 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18759 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18761 #undef TARGET_PRINT_OPERAND
18762 #define TARGET_PRINT_OPERAND mips_print_operand
18763 #undef TARGET_PRINT_OPERAND_ADDRESS
18764 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18765 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18766 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18768 #undef TARGET_SETUP_INCOMING_VARARGS
18769 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18770 #undef TARGET_STRICT_ARGUMENT_NAMING
18771 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18772 #undef TARGET_MUST_PASS_IN_STACK
18773 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18774 #undef TARGET_PASS_BY_REFERENCE
18775 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18776 #undef TARGET_CALLEE_COPIES
18777 #define TARGET_CALLEE_COPIES mips_callee_copies
18778 #undef TARGET_ARG_PARTIAL_BYTES
18779 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18780 #undef TARGET_FUNCTION_ARG
18781 #define TARGET_FUNCTION_ARG mips_function_arg
18782 #undef TARGET_FUNCTION_ARG_ADVANCE
18783 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18784 #undef TARGET_FUNCTION_ARG_BOUNDARY
18785 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18787 #undef TARGET_MODE_REP_EXTENDED
18788 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18790 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18791 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18793 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18794 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18796 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18797 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18799 #undef TARGET_INIT_BUILTINS
18800 #define TARGET_INIT_BUILTINS mips_init_builtins
18801 #undef TARGET_BUILTIN_DECL
18802 #define TARGET_BUILTIN_DECL mips_builtin_decl
18803 #undef TARGET_EXPAND_BUILTIN
18804 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18806 #undef TARGET_HAVE_TLS
18807 #define TARGET_HAVE_TLS HAVE_AS_TLS
18809 #undef TARGET_CANNOT_FORCE_CONST_MEM
18810 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18812 #undef TARGET_LEGITIMATE_CONSTANT_P
18813 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18815 #undef TARGET_ENCODE_SECTION_INFO
18816 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18818 #undef TARGET_ATTRIBUTE_TABLE
18819 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18820 /* All our function attributes are related to how out-of-line copies should
18821 be compiled or called. They don't in themselves prevent inlining. */
18822 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18823 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18825 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18826 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18828 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18829 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18830 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18831 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18833 #undef TARGET_COMP_TYPE_ATTRIBUTES
18834 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18836 #ifdef HAVE_AS_DTPRELWORD
18837 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18838 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18840 #undef TARGET_DWARF_REGISTER_SPAN
18841 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18843 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18844 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18846 #undef TARGET_LEGITIMATE_ADDRESS_P
18847 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18849 #undef TARGET_FRAME_POINTER_REQUIRED
18850 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18852 #undef TARGET_CAN_ELIMINATE
18853 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18855 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18856 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18858 #undef TARGET_TRAMPOLINE_INIT
18859 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18861 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18862 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18864 #undef TARGET_SHIFT_TRUNCATION_MASK
18865 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18867 #undef TARGET_PREPARE_PCH_SAVE
18868 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18870 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18871 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18873 #undef TARGET_CASE_VALUES_THRESHOLD
18874 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18876 struct gcc_target targetm
= TARGET_INITIALIZER
;
18878 #include "gt-mips.h"