| blob | b99fe2ae34573363a97576e6c2a82b1990aee3ea |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
63 #endif
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
71 : 4)
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 const
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
107 in SFmode, DFmode and XFmode */
109 in SFmode, DFmode and XFmode */
112 in SImode and DImode */
114 in SImode and DImode */
117 in SImode, DImode and TImode */
119 in SImode, DImode and TImode */
147 };
149 /* Processor costs (relative to an add) */
150 static const
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
178 in SFmode, DFmode and XFmode */
180 in SFmode, DFmode and XFmode */
183 in SImode and DImode */
185 in SImode and DImode */
188 in SImode, DImode and TImode */
190 in SImode, DImode and TImode */
204 DUMMY_STRINGOP_ALGS},
206 DUMMY_STRINGOP_ALGS},
218 };
220 static const
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
248 in SFmode, DFmode and XFmode */
250 in SFmode, DFmode and XFmode */
253 in SImode and DImode */
255 in SImode and DImode */
258 in SImode, DImode and TImode */
260 in SImode, DImode and TImode */
263 shared for code and data, so 4kB is
264 not really precise. */
276 DUMMY_STRINGOP_ALGS},
278 DUMMY_STRINGOP_ALGS},
290 };
292 static const
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
320 in SFmode, DFmode and XFmode */
322 in SFmode, DFmode and XFmode */
325 in SImode and DImode */
327 in SImode and DImode */
330 in SImode, DImode and TImode */
332 in SImode, DImode and TImode */
346 DUMMY_STRINGOP_ALGS},
348 DUMMY_STRINGOP_ALGS},
360 };
362 static const
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
390 in SFmode, DFmode and XFmode */
392 in SFmode, DFmode and XFmode */
395 in SImode and DImode */
397 in SImode and DImode */
400 in SImode, DImode and TImode */
402 in SImode, DImode and TImode */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 */
422 DUMMY_STRINGOP_ALGS},
425 DUMMY_STRINGOP_ALGS},
437 };
439 static const
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
467 in SFmode, DFmode and XFmode */
469 in SFmode, DFmode and XFmode */
473 in SImode and DImode */
475 in SImode and DImode */
478 in SImode, DImode and TImode */
480 in SImode, DImode and TImode */
494 DUMMY_STRINGOP_ALGS},
496 DUMMY_STRINGOP_ALGS},
508 };
510 static const
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
538 in SFmode, DFmode and XFmode */
540 in SFmode, DFmode and XFmode */
543 in SImode and DImode */
545 in SImode and DImode */
548 in SImode, DImode and TImode */
550 in SImode, DImode and TImode */
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
567 DUMMY_STRINGOP_ALGS},
569 DUMMY_STRINGOP_ALGS},
581 };
583 static const
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
611 in SFmode, DFmode and XFmode */
613 in SFmode, DFmode and XFmode */
616 in SImode and DImode */
618 in SImode and DImode */
621 in SImode, DImode and TImode */
623 in SImode, DImode and TImode */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
640 DUMMY_STRINGOP_ALGS},
642 DUMMY_STRINGOP_ALGS},
654 };
656 static const
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
684 in SFmode, DFmode and XFmode */
686 in SFmode, DFmode and XFmode */
689 in SImode and DImode */
691 in SImode and DImode */
694 in SImode, DImode and TImode */
696 in SImode, DImode and TImode */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
705 time). */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
733 };
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
762 in SFmode, DFmode and XFmode */
764 in SFmode, DFmode and XFmode */
767 in SImode and DImode */
769 in SImode and DImode */
772 in SImode, DImode and TImode */
774 in SImode, DImode and TImode */
776 /* On K8
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
779 On AMDFAM10
780 MOVD reg64, xmmreg Double FADD 3
781 1/1 1/1
782 MOVD reg32, xmmreg Double FADD 3
783 1/1 1/1 */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
791 time). */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
820 };
822 static const
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
850 in SFmode, DFmode and XFmode */
852 in SFmode, DFmode and XFmode */
855 in SImode and DImode */
857 in SImode and DImode */
860 in SImode, DImode and TImode */
862 in SImode, DImode and TImode */
876 DUMMY_STRINGOP_ALGS},
879 DUMMY_STRINGOP_ALGS},
891 };
893 static const
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
921 in SFmode, DFmode and XFmode */
923 in SFmode, DFmode and XFmode */
926 in SImode and DImode */
928 in SImode and DImode */
931 in SImode, DImode and TImode */
933 in SImode, DImode and TImode */
964 };
966 static const
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
994 in SFmode, DFmode and XFmode */
996 in SFmode, DFmode and XFmode */
999 in SImode and DImode */
1001 in SImode and DImode */
1004 in SImode, DImode and TImode */
1006 in SImode, DImode and TImode */
1037 };
1039 static const
1062 in QImode, HImode and SImode.
1063 Relative to reg-reg move (2). */
1067 in SFmode, DFmode and XFmode */
1069 in SFmode, DFmode and XFmode */
1072 in SImode and DImode */
1074 in SImode and DImode */
1077 in SImode, DImode and TImode */
1079 in SImode, DImode and TImode */
1110 };
1112 /* Generic64 should produce code tuned for Nocona and K8. */
1113 static const
1116 /* On all chips taken into consideration lea is 2 cycles and more. With
1117 this cost however our current implementation of synth_mult results in
1118 use of unnecessary temporary registers causing regression on several
1119 SPECfp benchmarks. */
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1145 in SFmode, DFmode and XFmode */
1147 in SFmode, DFmode and XFmode */
1150 in SImode and DImode */
1152 in SImode and DImode */
1155 in SImode, DImode and TImode */
1157 in SImode, DImode and TImode */
1163 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1164 is increased to perhaps more appropriate value of 5. */
1187 };
1189 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 static const
1213 in QImode, HImode and SImode.
1214 Relative to reg-reg move (2). */
1218 in SFmode, DFmode and XFmode */
1220 in SFmode, DFmode and XFmode */
1223 in SImode and DImode */
1225 in SImode and DImode */
1228 in SImode, DImode and TImode */
1230 in SImode, DImode and TImode */
1244 DUMMY_STRINGOP_ALGS},
1246 DUMMY_STRINGOP_ALGS},
1258 };
1262 /* Processor feature/optimization bitmasks. */
1263 #define m_386 (1<<PROCESSOR_I386)
1264 #define m_486 (1<<PROCESSOR_I486)
1265 #define m_PENT (1<<PROCESSOR_PENTIUM)
1266 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1267 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1268 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1269 #define m_CORE2 (1<<PROCESSOR_CORE2)
1270 #define m_ATOM (1<<PROCESSOR_ATOM)
1272 #define m_GEODE (1<<PROCESSOR_GEODE)
1273 #define m_K6 (1<<PROCESSOR_K6)
1274 #define m_K6_GEODE (m_K6 | m_GEODE)
1275 #define m_K8 (1<<PROCESSOR_K8)
1276 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1277 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1278 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1279 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1281 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1282 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1284 /* Generic instruction choice should be common subset of supported CPUs
1285 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1286 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1288 /* Feature tests against the various tunings. */
1291 /* Feature tests against the various tunings used to create ix86_tune_features
1292 based on the processor mask. */
1294 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1295 negatively, so enabling for Generic64 seems like good code size
1296 tradeoff. We can't enable it for 32bit generic because it does not
1297 work well with PPro base chips. */
1300 /* X86_TUNE_PUSH_MEMORY */
1304 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1307 /* X86_TUNE_UNROLL_STRLEN */
1311 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1314 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1315 on simulation result. But after P4 was made, no performance benefit
1316 was observed with branch hints. It also increases the code size.
1317 As a result, icc never generates branch hints. */
1320 /* X86_TUNE_DOUBLE_WITH_ADD */
1323 /* X86_TUNE_USE_SAHF */
1327 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1328 partial dependencies. */
1332 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1333 register stalls on Generic32 compilation setting as well. However
1334 in current implementation the partial register stalls are not eliminated
1335 very well - they can be introduced via subregs synthesized by combine
1336 and can happen in caller/callee saving sequences. Because this option
1337 pays back little on PPro based chips and is in conflict with partial reg
1338 dependencies used by Athlon/P4 based chips, it is better to leave it off
1339 for generic32 for now. */
1340 m_PPRO,
1342 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1345 /* X86_TUNE_USE_HIMODE_FIOP */
1348 /* X86_TUNE_USE_SIMODE_FIOP */
1351 /* X86_TUNE_USE_MOV0 */
1352 m_K6,
1354 /* X86_TUNE_USE_CLTD */
1357 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1358 m_PENT4,
1360 /* X86_TUNE_SPLIT_LONG_MOVES */
1361 m_PPRO,
1363 /* X86_TUNE_READ_MODIFY_WRITE */
1366 /* X86_TUNE_READ_MODIFY */
1369 /* X86_TUNE_PROMOTE_QIMODE */
1373 /* X86_TUNE_FAST_PREFIX */
1376 /* X86_TUNE_SINGLE_STRINGOP */
1379 /* X86_TUNE_QIMODE_MATH */
1382 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1383 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1384 might be considered for Generic32 if our scheme for avoiding partial
1385 stalls was more effective. */
1388 /* X86_TUNE_PROMOTE_QI_REGS */
1391 /* X86_TUNE_PROMOTE_HI_REGS */
1392 m_PPRO,
1394 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1398 /* X86_TUNE_ADD_ESP_8 */
1402 /* X86_TUNE_SUB_ESP_4 */
1406 /* X86_TUNE_SUB_ESP_8 */
1410 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1411 for DFmode copies */
1415 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1418 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1419 conflict here in between PPro/Pentium4 based chips that thread 128bit
1420 SSE registers as single units versus K8 based chips that divide SSE
1421 registers to two 64bit halves. This knob promotes all store destinations
1422 to be 128bit to allow register renaming on 128bit SSE units, but usually
1423 results in one extra microop on 64bit SSE units. Experimental results
1424 shows that disabling this option on P4 brings over 20% SPECfp regression,
1425 while enabling it on K8 brings roughly 2.4% regression that can be partly
1426 masked by careful scheduling of moves. */
1430 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1431 m_AMDFAM10,
1433 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1434 are resolved on SSE register parts instead of whole registers, so we may
1435 maintain just lower part of scalar values in proper format leaving the
1436 upper part undefined. */
1437 m_ATHLON_K8,
1439 /* X86_TUNE_SSE_TYPELESS_STORES */
1440 m_AMD_MULTIPLE,
1442 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1445 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1448 /* X86_TUNE_PROLOGUE_USING_MOVE */
1451 /* X86_TUNE_EPILOGUE_USING_MOVE */
1454 /* X86_TUNE_SHIFT1 */
1457 /* X86_TUNE_USE_FFREEP */
1458 m_AMD_MULTIPLE,
1460 /* X86_TUNE_INTER_UNIT_MOVES */
1463 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1466 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1467 than 4 branch instructions in the 16 byte window. */
1471 /* X86_TUNE_SCHEDULE */
1475 /* X86_TUNE_USE_BT */
1478 /* X86_TUNE_USE_INCDEC */
1481 /* X86_TUNE_PAD_RETURNS */
1484 /* X86_TUNE_EXT_80387_CONSTANTS */
1488 /* X86_TUNE_SHORTEN_X87_SSE */
1491 /* X86_TUNE_AVOID_VECTOR_DECODE */
1494 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1495 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1498 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1499 vector path on AMD machines. */
1502 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 machines. */
1506 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1507 than a MOV. */
1508 m_PENT,
1510 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1511 but one byte longer. */
1512 m_PENT,
1514 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1515 operand that cannot be represented using a modRM byte. The XOR
1516 replacement is long decoded, so this split helps here as well. */
1517 m_K6,
1519 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 from FP to FP. */
1523 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1524 from integer to FP. */
1525 m_AMDFAM10,
1527 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1528 with a subsequent conditional jump instruction into a single
1529 compare-and-branch uop. */
1530 m_CORE2,
1532 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1533 will impact LEA instruction selection. */
1534 m_ATOM,
1535 };
1537 /* Feature tests against the various architecture variations. */
1540 /* Feature tests against the various architecture variations, used to create
1541 ix86_arch_features based on the processor mask. */
1543 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1546 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1549 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1552 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1555 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1557 };
1559 static const unsigned int x86_accumulate_outgoing_args
1563 static const unsigned int x86_arch_always_fancy_math_387
1569 /* In case the average insn count for single function invocation is
1570 lower than this constant, emit fast (but longer) prologue and
1571 epilogue code. */
1572 #define FAST_PROLOGUE_INSN_COUNT 20
1574 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1579 /* Array of the smallest class containing reg number REGNO, indexed by
1580 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1583 {
1584 /* ax, dx, cx, bx */
1586 /* si, di, bp, sp */
1588 /* FP registers */
1591 /* arg pointer */
1592 NON_Q_REGS,
1593 /* flags, fpsr, fpcr, frame */
1595 /* SSE registers */
1598 /* MMX registers */
1601 /* REX registers */
1604 /* SSE REX registers */
1607 };
1609 /* The "default" register map used in 32bit mode. */
1612 {
1620 };
1622 /* The "default" register map used in 64bit mode. */
1625 {
1633 };
1635 /* Define the register numbers to be used in Dwarf debugging information.
1636 The SVR4 reference port C compiler uses the following register numbers
1637 in its Dwarf output code:
1638 0 for %eax (gcc regno = 0)
1639 1 for %ecx (gcc regno = 2)
1640 2 for %edx (gcc regno = 1)
1641 3 for %ebx (gcc regno = 3)
1642 4 for %esp (gcc regno = 7)
1643 5 for %ebp (gcc regno = 6)
1644 6 for %esi (gcc regno = 4)
1645 7 for %edi (gcc regno = 5)
1646 The following three DWARF register numbers are never generated by
1647 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1648 believes these numbers have these meanings.
1649 8 for %eip (no gcc equivalent)
1650 9 for %eflags (gcc regno = 17)
1651 10 for %trapno (no gcc equivalent)
1652 It is not at all clear how we should number the FP stack registers
1653 for the x86 architecture. If the version of SDB on x86/svr4 were
1654 a bit less brain dead with respect to floating-point then we would
1655 have a precedent to follow with respect to DWARF register numbers
1656 for x86 FP registers, but the SDB on x86/svr4 is so completely
1657 broken with respect to FP registers that it is hardly worth thinking
1658 of it as something to strive for compatibility with.
1659 The version of x86/svr4 SDB I have at the moment does (partially)
1660 seem to believe that DWARF register number 11 is associated with
1661 the x86 register %st(0), but that's about all. Higher DWARF
1662 register numbers don't seem to be associated with anything in
1663 particular, and even for DWARF regno 11, SDB only seems to under-
1664 stand that it should say that a variable lives in %st(0) (when
1665 asked via an `=' command) if we said it was in DWARF regno 11,
1666 but SDB still prints garbage when asked for the value of the
1667 variable in question (via a `/' command).
1668 (Also note that the labels SDB prints for various FP stack regs
1669 when doing an `x' command are all wrong.)
1670 Note that these problems generally don't affect the native SVR4
1671 C compiler because it doesn't allow the use of -O with -g and
1672 because when it is *not* optimizing, it allocates a memory
1673 location for each floating-point variable, and the memory
1674 location is what gets described in the DWARF AT_location
1675 attribute for the variable in question.
1676 Regardless of the severe mental illness of the x86/svr4 SDB, we
1677 do something sensible here and we use the following DWARF
1678 register numbers. Note that these are all stack-top-relative
1679 numbers.
1680 11 for %st(0) (gcc regno = 8)
1681 12 for %st(1) (gcc regno = 9)
1682 13 for %st(2) (gcc regno = 10)
1683 14 for %st(3) (gcc regno = 11)
1684 15 for %st(4) (gcc regno = 12)
1685 16 for %st(5) (gcc regno = 13)
1686 17 for %st(6) (gcc regno = 14)
1687 18 for %st(7) (gcc regno = 15)
1688 */
1690 {
1698 };
1700 /* Test and compare insns in i386.md store the information needed to
1701 generate branch and scc insns here. */
1706 /* Define parameter passing and return registers. */
1709 {
1711 };
1714 {
1716 };
1719 {
1721 };
1723 /* Define the structure for the machine field in struct function. */
1728 rtx rtl;
1730 };
1732 /* Structure describing stack frame layout.
1733 Stack grows downward:
1735 [arguments]
1736 <- ARG_POINTER
1737 saved pc
1739 saved frame pointer if frame_pointer_needed
1740 <- HARD_FRAME_POINTER
1741 [saved regs]
1743 [padding0]
1745 [saved SSE regs]
1747 [padding1] \
1748 )
1749 [va_arg registers] (
1750 > to_allocate <- FRAME_POINTER
1751 [frame] (
1752 )
1753 [padding2] /
1754 */
1755 struct ix86_frame
1756 {
1762 HOST_WIDE_INT frame;
1767 HOST_WIDE_INT to_allocate;
1768 /* The offsets relative to ARG_POINTER. */
1769 HOST_WIDE_INT frame_pointer_offset;
1770 HOST_WIDE_INT hard_frame_pointer_offset;
1771 HOST_WIDE_INT stack_pointer_offset;
1773 /* When save_regs_using_mov is set, emit prologue using
1774 move instead of push instructions. */
1776 };
1778 /* Code model option. */
1780 /* Asm dialect. */
1782 /* TLS dialects. */
1785 /* Which unit we are generating floating point math for. */
1788 /* Which cpu are we scheduling for. */
1791 /* Which cpu are we optimizing for. */
1794 /* Which instruction set architecture to use. */
1797 /* true if sse prefetch instruction is not NOOP. */
1800 /* ix86_regparm_string as a number */
1803 /* -mstackrealign option */
1817 /* Preferred alignment for stack boundary in bits. */
1820 /* Alignment for incoming stack boundary in bits specified at
1821 command line. */
1824 /* Default alignment for incoming stack boundary in bits. */
1827 /* Alignment for incoming stack boundary in bits. */
1830 /* The abi used by target. */
1833 /* Values 1-5: see jump.c */
1836 /* Calling abi specific va_list type nodes. */
1840 /* Variables which are this size or smaller are put in the data/bss
1841 or ldata/lbss sections. */
1845 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1849 /* Fence to use after loop using movnt. */
1850 tree x86_mfence;
1852 /* Register class used for passing given 64bit part of the argument.
1853 These represent classes as documented by the PS ABI, with the exception
1854 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1855 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1857 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1858 whenever possible (upper half does contain padding). */
1859 enum x86_64_reg_class
1860 {
1861 X86_64_NO_CLASS,
1862 X86_64_INTEGER_CLASS,
1863 X86_64_INTEGERSI_CLASS,
1864 X86_64_SSE_CLASS,
1865 X86_64_SSESF_CLASS,
1866 X86_64_SSEDF_CLASS,
1867 X86_64_SSEUP_CLASS,
1868 X86_64_X87_CLASS,
1869 X86_64_X87UP_CLASS,
1870 X86_64_COMPLEX_X87_CLASS,
1871 X86_64_MEMORY_CLASS
1872 };
1874 #define MAX_CLASSES 4
1876 /* Table of constants used by fldpi, fldln2, etc.... */
1880 \f
1891 enum ix86_function_specific_strings
1892 {
1893 IX86_FUNCTION_SPECIFIC_ARCH,
1894 IX86_FUNCTION_SPECIFIC_TUNE,
1895 IX86_FUNCTION_SPECIFIC_FPMATH,
1896 IX86_FUNCTION_SPECIFIC_MAX
1897 };
1914 \f
1915 #ifndef SUBTARGET32_DEFAULT_CPU
1917 #endif
1919 /* The svr4 ABI for the i386 says that records and unions are returned
1920 in memory. */
1921 #ifndef DEFAULT_PCC_STRUCT_RETURN
1922 #define DEFAULT_PCC_STRUCT_RETURN 1
1923 #endif
1925 /* Whether -mtune= or -march= were specified */
1929 /* Bit flags that specify the ISA we are compiling for. */
1932 /* A mask of ix86_isa_flags that includes bit X if X
1933 was set or cleared on the command line. */
1936 /* Define a set of ISAs which are available when a given ISA is
1937 enabled. MMX and SSE ISAs are handled separately. */
1939 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1940 #define OPTION_MASK_ISA_3DNOW_SET \
1941 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1943 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1944 #define OPTION_MASK_ISA_SSE2_SET \
1945 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1946 #define OPTION_MASK_ISA_SSE3_SET \
1947 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1948 #define OPTION_MASK_ISA_SSSE3_SET \
1949 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1950 #define OPTION_MASK_ISA_SSE4_1_SET \
1951 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1952 #define OPTION_MASK_ISA_SSE4_2_SET \
1953 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1954 #define OPTION_MASK_ISA_AVX_SET \
1955 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1956 #define OPTION_MASK_ISA_FMA_SET \
1957 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1959 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1960 as -msse4.2. */
1961 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1963 #define OPTION_MASK_ISA_SSE4A_SET \
1964 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1965 #define OPTION_MASK_ISA_FMA4_SET \
1966 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1967 | OPTION_MASK_ISA_AVX_SET)
1968 #define OPTION_MASK_ISA_XOP_SET \
1969 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
1970 #define OPTION_MASK_ISA_LWP_SET \
1971 OPTION_MASK_ISA_LWP
1973 /* AES and PCLMUL need SSE2 because they use xmm registers */
1974 #define OPTION_MASK_ISA_AES_SET \
1975 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1976 #define OPTION_MASK_ISA_PCLMUL_SET \
1977 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1979 #define OPTION_MASK_ISA_ABM_SET \
1980 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1982 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1983 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1984 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1985 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1986 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1988 /* Define a set of ISAs which aren't available when a given ISA is
1989 disabled. MMX and SSE ISAs are handled separately. */
1991 #define OPTION_MASK_ISA_MMX_UNSET \
1992 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1993 #define OPTION_MASK_ISA_3DNOW_UNSET \
1994 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1995 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1997 #define OPTION_MASK_ISA_SSE_UNSET \
1998 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1999 #define OPTION_MASK_ISA_SSE2_UNSET \
2000 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2001 #define OPTION_MASK_ISA_SSE3_UNSET \
2002 (OPTION_MASK_ISA_SSE3 \
2003 | OPTION_MASK_ISA_SSSE3_UNSET \
2004 | OPTION_MASK_ISA_SSE4A_UNSET )
2005 #define OPTION_MASK_ISA_SSSE3_UNSET \
2006 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2007 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2008 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2009 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2010 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2011 #define OPTION_MASK_ISA_AVX_UNSET \
2012 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2013 | OPTION_MASK_ISA_FMA4_UNSET)
2014 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2016 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2017 as -mno-sse4.1. */
2018 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2020 #define OPTION_MASK_ISA_SSE4A_UNSET \
2021 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2023 #define OPTION_MASK_ISA_FMA4_UNSET \
2024 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2025 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2026 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2028 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2029 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2030 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2031 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2032 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2033 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2034 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2035 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2037 /* Vectorization library interface and handlers. */
2042 /* Processor target table, indexed by processor number */
2043 struct ptt
2044 {
2051 };
2054 {
2070 };
2073 {
2095 "amdfam10"
2096 };
2097 \f
2098 /* Implement TARGET_HANDLE_OPTION. */
2100 static bool
2102 {
2104 {
2107 {
2110 }
2111 else
2112 {
2115 }
2120 {
2123 }
2124 else
2125 {
2128 }
2136 {
2139 }
2140 else
2141 {
2144 }
2149 {
2152 }
2153 else
2154 {
2157 }
2162 {
2165 }
2166 else
2167 {
2170 }
2175 {
2178 }
2179 else
2180 {
2183 }
2188 {
2191 }
2192 else
2193 {
2196 }
2201 {
2204 }
2205 else
2206 {
2209 }
2214 {
2217 }
2218 else
2219 {
2222 }
2227 {
2230 }
2231 else
2232 {
2235 }
2250 {
2253 }
2254 else
2255 {
2258 }
2263 {
2266 }
2267 else
2268 {
2271 }
2276 {
2279 }
2280 else
2281 {
2284 }
2289 {
2292 }
2293 else
2294 {
2297 }
2302 {
2305 }
2306 else
2307 {
2310 }
2315 {
2318 }
2319 else
2320 {
2323 }
2328 {
2331 }
2332 else
2333 {
2336 }
2341 {
2344 }
2345 else
2346 {
2349 }
2354 {
2357 }
2358 else
2359 {
2362 }
2367 {
2370 }
2371 else
2372 {
2375 }
2380 {
2383 }
2384 else
2385 {
2388 }
2393 {
2396 }
2397 else
2398 {
2401 }
2406 }
2407 }
2408 \f
2409 /* Return a string that documents the current -m options. The caller is
2410 responsible for freeing the string. */
2415 {
2416 struct ix86_target_opts
2417 {
2420 };
2422 /* This table is ordered so that options like -msse4.2 that imply
2423 preceding options while match those first. */
2425 {
2447 };
2449 /* Flag options. */
2451 {
2472 };
2488 /* Add -march= option. */
2490 {
2493 }
2495 /* Add -mtune= option. */
2497 {
2500 }
2502 /* Pick out the options in isa options. */
2504 {
2506 {
2509 }
2510 }
2513 {
2516 }
2518 /* Add flag options. */
2520 {
2522 {
2525 }
2526 }
2529 {
2532 }
2534 /* Add -fpmath= option. */
2536 {
2539 }
2541 /* Any options? */
2547 /* Size the string. */
2551 {
2556 }
2558 /* Build the string. */
2563 {
2570 {
2572 line_len++;
2575 {
2579 }
2580 }
2584 {
2588 }
2589 }
2595 }
2597 /* Function that is callable from the debugger to print the current
2598 options. */
2599 void
2601 {
2607 {
2610 }
2611 else
2615 }
2616 \f
2617 /* Sometimes certain combinations of command options do not make
2618 sense on a particular target machine. You can define a macro
2619 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2620 defined, is executed once just after all the command options have
2621 been parsed.
2623 Don't use this macro to turn on various extra optimizations for
2624 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2626 void
2628 {
2636 /* Comes from final.c -- no real reason to change it. */
2637 #define MAX_CODE_ALIGN 16
2639 enum pta_flags
2640 {
2665 };
2667 static struct pta
2668 {
2673 }
2675 {
2757 };
2761 /* Set up prefix/suffix so the error messages refer to either the command
2762 line argument, or the attribute(target). */
2764 {
2768 }
2769 else
2770 {
2774 }
2776 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2777 SUBTARGET_OVERRIDE_OPTIONS;
2778 #endif
2780 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2781 SUBSUBTARGET_OVERRIDE_OPTIONS;
2782 #endif
2784 /* -fPIC is the default for x86_64. */
2788 /* Set the default values for switches whose default depends on TARGET_64BIT
2789 in case they weren't overwritten by command line options. */
2791 {
2792 /* Mach-O doesn't support omitting the frame pointer for now. */
2799 }
2800 else
2801 {
2808 }
2810 /* Need to check -mtune=generic first. */
2812 {
2815 /* As special support for cross compilers we read -mtune=native
2816 as -mtune=generic. With native compilers we won't see the
2817 -mtune=native, as it was changed by the driver. */
2819 {
2822 else
2824 }
2825 /* If this call is for setting the option attribute, allow the
2826 generic32/generic64 that was previously set. */
2830 ;
2838 }
2839 else
2840 {
2844 {
2847 }
2849 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2850 need to use a sensible tune option. */
2854 {
2857 else
2859 }
2860 }
2863 {
2872 /* rep; movq isn't available in 32-bit code. */
2880 else
2883 }
2887 else
2890 /* Validate -mabi= value. */
2892 {
2897 else
2900 }
2901 else
2905 {
2918 else
2921 }
2922 else
2923 {
2924 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2925 use of rip-relative addressing. This eliminates fixups that
2926 would otherwise be needed if this object is to be placed in a
2927 DLL, and is essentially just as efficient as direct addressing. */
2932 else
2934 }
2936 {
2942 else
2945 }
2955 {
2958 /* Default cpu tuning to the architecture. */
3035 }
3050 {
3054 {
3056 {
3064 }
3065 else
3068 }
3069 /* Intel CPUs have always interpreted SSE prefetch instructions as
3070 NOPs; so, we can enable SSE prefetch instructions even when
3071 -mtune (rather than -march) points us to a processor that has them.
3072 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3073 higher processors. */
3078 }
3090 else
3093 /* Arrange to set up i386_stack_locals for all functions. */
3096 /* Validate -mregparm= value. */
3098 {
3105 else
3107 }
3111 /* If the user has provided any of the -malign-* options,
3112 warn and use that value only if -falign-* is not set.
3113 Remove this code in GCC 3.2 or later. */
3115 {
3119 {
3124 else
3126 }
3127 }
3130 {
3134 {
3139 else
3141 }
3142 }
3145 {
3149 {
3154 else
3156 }
3157 }
3159 /* Default align_* from the processor table. */
3161 {
3164 }
3166 {
3169 }
3171 {
3173 }
3175 /* Validate -mbranch-cost= value, or provide default. */
3178 {
3182 else
3184 }
3186 {
3190 else
3192 }
3195 {
3200 else
3203 }
3206 {
3210 }
3213 {
3216 /* Enable by default the SSE and MMX builtins. Do allow the user to
3217 explicitly disable any of these. In particular, disabling SSE and
3218 MMX for kernel code is extremely useful. */
3220 ix86_isa_flags
3226 }
3227 else
3228 {
3232 ix86_isa_flags
3235 /* i386 ABI does not specify red zone. It still makes sense to use it
3236 when programmer takes care to stack from being destroyed. */
3239 }
3241 /* Keep nonleaf frame pointers. */
3247 /* If we're doing fast math, we don't care about comparison order
3248 wrt NaNs. This lets us use a shorter comparison sequence. */
3252 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3253 since the insns won't need emulation. */
3257 /* Likewise, if the target doesn't have a 387, or we've specified
3258 software floating point, don't use 387 inline intrinsics. */
3262 /* Turn on MMX builtins for -msse. */
3264 {
3267 }
3269 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3273 /* Validate -mpreferred-stack-boundary= value or default it to
3274 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3277 {
3282 else
3284 }
3286 /* Set the default value for -mstackrealign. */
3292 /* Validate -mincoming-stack-boundary= value or default it to
3293 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3296 {
3301 else
3302 {
3304 ix86_incoming_stack_boundary
3306 }
3307 }
3309 /* Accept -msseregparm only if at least SSE support is enabled. */
3316 {
3320 {
3322 {
3325 }
3326 else
3328 }
3334 {
3336 {
3339 }
3341 {
3344 }
3345 else
3347 }
3348 else
3351 }
3353 /* If the i387 is disabled, then do not return values in it. */
3357 /* Use external vectorized library in vectorizing intrinsics. */
3359 {
3364 else
3368 }
3375 /* ??? Unwind info is not correct around the CFG unless either a frame
3376 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3377 unwind info generation to be aware of the CFG and propagating states
3378 around edges. */
3381 && flag_omit_frame_pointer
3383 {
3389 }
3391 /* If stack probes are required, the space used for large function
3392 arguments on the stack must also be probed, so enable
3393 -maccumulate-outgoing-args so this happens in the prologue. */
3396 {
3401 }
3403 /* For sane SSE instruction set generation we need fcomi instruction.
3404 It is safe to enable all CMOVE instructions. */
3408 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3409 {
3415 }
3417 /* When scheduling description is not available, disable scheduler pass
3418 so it won't slow down the compilation and make x87 code slower. */
3432 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3433 can be optimized to ap = __builtin_next_arg (0). */
3438 {
3447 }
3448 else
3449 {
3458 }
3460 #ifdef USE_IX86_CLD
3461 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3464 #endif
3466 /* Save the initial options in case the user does function specific options */
3468 target_option_default_node = target_option_current_node
3470 }
3472 /* Update register usage after having seen the compiler flags. */
3474 void
3476 {
3481 {
3486 }
3488 /* The PIC register, if it exists, is fixed. */
3493 /* The MS_ABI changes the set of call-used registers. */
3495 {
3502 }
3504 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3505 other call-clobbered regs for 64-bit. */
3507 {
3514 }
3516 /* If MMX is disabled, squash the registers. */
3522 /* If SSE is disabled, squash the registers. */
3528 /* If the FPU is disabled, squash the registers. */
3534 /* If 32-bit, squash the 64-bit registers. */
3536 {
3541 }
3542 }
3544 \f
3545 /* Save the current options */
3547 static void
3549 {
3560 /* The fields are char but the variables are not; make sure the
3561 values fit in the fields. */
3567 }
3569 /* Restore the current options */
3571 static void
3573 {
3589 /* Recreate the arch feature tests if the arch changed */
3591 {
3596 }
3598 /* Recreate the tune optimization tests */
3600 {
3605 }
3606 }
3608 /* Print the current options */
3610 static void
3613 {
3638 {
3641 }
3642 }
3644 \f
3645 /* Inner function to process the attribute((target(...))), take an argument and
3646 set the current options from the argument. If we have a list, recursively go
3647 over the list. */
3649 static bool
3651 {
3655 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3656 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3657 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3658 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3660 enum ix86_opt_type
3661 {
3662 ix86_opt_unknown,
3663 ix86_opt_yes,
3664 ix86_opt_no,
3665 ix86_opt_str,
3666 ix86_opt_isa
3667 };
3669 static const struct
3670 {
3677 /* isa options */
3697 /* string options */
3702 /* flag options */
3704 OPT_mcld,
3705 MASK_CLD),
3708 OPT_mfancy_math_387,
3709 MASK_NO_FANCY_MATH_387),
3712 OPT_mieee_fp,
3713 MASK_IEEE_FP),
3716 OPT_minline_all_stringops,
3717 MASK_INLINE_ALL_STRINGOPS),
3720 OPT_minline_stringops_dynamically,
3721 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3724 OPT_mno_align_stringops,
3725 MASK_NO_ALIGN_STRINGOPS),
3728 OPT_mrecip,
3729 MASK_RECIP),
3731 };
3733 /* If this is a list, recurse to get the options. */
3735 {
3744 }
3749 /* Handle multiple arguments separated by commas. */
3753 {
3767 {
3771 }
3772 else
3773 {
3776 }
3778 /* Recognize no-xxx. */
3780 {
3784 }
3785 else
3788 /* Find the option. */
3792 {
3798 {
3803 }
3804 }
3806 /* Process the option. */
3808 {
3811 }
3817 {
3823 else
3825 }
3828 {
3830 {
3833 }
3834 else
3836 }
3838 else
3840 }
3843 }
3845 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3847 tree
3849 {
3861 /* Process each of the options on the chain. */
3865 /* If the changed options are different from the default, rerun override_options,
3866 and then save the options away. The string options are are attribute options,
3867 and will be undone when we copy the save structure. */
3873 {
3874 /* If we are using the default tune= or arch=, undo the string assigned,
3875 and use the default. */
3886 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3892 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3895 /* Add any builtin functions with the new isa if any. */
3898 /* Save the current options unless we are validating options for
3899 #pragma. */
3906 /* Free up memory allocated to hold the strings */
3910 }
3913 }
3915 /* Hook to validate attribute((target("string"))). */
3917 static bool
3920 tree args,
3922 {
3929 /* If the function changed the optimization levels as well as setting target
3930 options, start with the optimizations specified. */
3934 /* The target attributes may also change some optimization flags, so update
3935 the optimization options if necessary. */
3944 {
3949 }
3957 }
3959 \f
3960 /* Hook to determine if one function can safely inline another. */
3962 static bool
3964 {
3969 /* If callee has no option attributes, then it is ok to inline. */
3973 /* If caller has no option attributes, but callee does then it is not ok to
3974 inline. */
3978 else
3979 {
3983 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3984 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3985 function. */
3990 /* See if we have the same non-isa options. */
3994 /* See if arch, tune, etc. are the same. */
4007 else
4009 }
4012 }
4014 \f
4015 /* Remember the last target of ix86_set_current_function. */
4018 /* Establish appropriate back-end context for processing the function
4019 FNDECL. The argument might be NULL to indicate processing at top
4020 level, outside of any function scope. */
4021 static void
4023 {
4024 /* Only change the context if the function changes. This hook is called
4025 several times in the course of compiling a function, and we don't want to
4026 slow things down too much or call target_reinit when it isn't safe. */
4028 {
4029 tree old_tree = (ix86_previous_fndecl
4033 tree new_tree = (fndecl
4039 ;
4042 {
4045 }
4048 {
4054 }
4055 }
4056 }
4058 \f
4059 /* Return true if this goes in large data/bss. */
4061 static bool
4063 {
4067 /* Functions are never large data. */
4072 {
4078 }
4079 else
4080 {
4083 /* If this is an incomplete type with size 0, then we can't put it
4084 in data because it might be too big when completed. */
4087 }
4090 }
4092 /* Switch to the appropriate section for output of DECL.
4093 DECL is either a `VAR_DECL' node or a constant of some sort.
4094 RELOC indicates whether forming the initial value of DECL requires
4095 link-time relocations. */
4098 ATTRIBUTE_UNUSED;
4103 {
4106 {
4110 {
4144 /* We don't split these for medium model. Place them into
4145 default sections and hope for best. */
4150 }
4152 {
4153 /* We might get called with string constants, but get_named_section
4154 doesn't like them as they are not DECLs. Also, we need to set
4155 flags in that case. */
4159 }
4160 }
4162 }
4164 /* Build up a unique section name, expressed as a
4165 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4166 RELOC indicates whether the initial value of EXP requires
4167 link-time relocations. */
4169 static void ATTRIBUTE_UNUSED
4171 {
4174 {
4176 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4180 {
4204 /* We don't split these for medium model. Place them into
4205 default sections and hope for best. */
4213 }
4215 {
4222 /* If we're using one_only, then there needs to be a .gnu.linkonce
4223 prefix to the section name. */
4230 }
4231 }
4233 }
4235 #ifdef COMMON_ASM_OP
4236 /* This says how to output assembler code to declare an
4237 uninitialized external linkage data object.
4239 For medium model x86-64 we need to use .largecomm opcode for
4240 large objects. */
4241 void
4245 {
4249 else
4254 }
4255 #endif
4257 /* Utility function for targets to use in implementing
4258 ASM_OUTPUT_ALIGNED_BSS. */
4260 void
4264 {
4268 else
4271 #ifdef ASM_DECLARE_OBJECT_NAME
4274 #else
4275 /* Standard thing is just output label for the object. */
4279 }
4280 \f
4281 void
4283 {
4284 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4285 make the problem with not enough registers even worse. */
4286 #ifdef INSN_SCHEDULING
4289 #endif
4292 /* The Darwin libraries never set errno, so we might as well
4293 avoid calling them when that's the only reason we would. */
4296 /* The default values of these switches depend on the TARGET_64BIT
4297 that is not known at this moment. Mark these values with 2 and
4298 let user the to override these. In case there is no command line option
4299 specifying them, we will set the defaults in override_options. */
4305 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4306 SUBTARGET_OPTIMIZATION_OPTIONS;
4307 #endif
4308 }
4309 \f
4310 /* Decide whether we can make a sibling call to a function. DECL is the
4311 declaration of the function being targeted by the call and EXP is the
4312 CALL_EXPR representing the call. */
4314 static bool
4316 {
4320 /* If we are generating position-independent code, we cannot sibcall
4321 optimize any indirect call, or a direct call to a global function,
4322 as the PLT requires %ebx be live. */
4326 /* If we need to align the outgoing stack, then sibcalling would
4327 unalign the stack, which may break the called function. */
4333 {
4336 }
4337 else
4338 {
4339 /* We're looking at the CALL_EXPR, we need the type of the function. */
4344 }
4346 /* Check that the return value locations are the same. Like
4347 if we are returning floats on the 80387 register stack, we cannot
4348 make a sibcall from a function that doesn't return a float to a
4349 function that does or, conversely, from a function that does return
4350 a float to a function that doesn't; the necessary stack adjustment
4351 would not be executed. This is also the place we notice
4352 differences in the return value ABI. Note that it is ok for one
4353 of the functions to have void return type as long as the return
4354 value of the other is passed in a register. */
4359 {
4362 }
4364 ;
4369 {
4370 /* The SYSV ABI has more call-clobbered registers;
4371 disallow sibcalls from MS to SYSV. */
4375 }
4376 else
4377 {
4378 /* If this call is indirect, we'll need to be able to use a
4379 call-clobbered register for the address of the target function.
4380 Make sure that all such registers are not used for passing
4381 parameters. Note that DLLIMPORT functions are indirect. */
4384 {
4386 {
4387 /* ??? Need to count the actual number of registers to be used,
4388 not the possible number of registers. Fix later. */
4390 }
4391 }
4392 }
4394 /* Otherwise okay. That also includes certain types of indirect calls. */
4396 }
4398 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4399 and "sseregparm" calling convention attributes;
4400 arguments as in struct attribute_spec.handler. */
4402 static tree
4404 tree args,
4407 {
4412 {
4414 name);
4417 }
4419 /* Can combine regparm with all attributes but fastcall. */
4421 {
4422 tree cst;
4425 {
4427 }
4430 {
4432 }
4436 {
4439 name);
4441 }
4443 {
4447 }
4450 }
4453 {
4454 /* Do not warn when emulating the MS ABI. */
4459 name);
4462 }
4464 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4466 {
4468 {
4470 }
4472 {
4474 }
4476 {
4478 }
4480 {
4482 }
4483 }
4485 /* Can combine stdcall with fastcall (redundant), regparm and
4486 sseregparm. */
4488 {
4490 {
4492 }
4494 {
4496 }
4498 {
4500 }
4501 }
4503 /* Can combine cdecl with regparm and sseregparm. */
4505 {
4507 {
4509 }
4511 {
4513 }
4515 {
4517 }
4518 }
4520 {
4523 name);
4525 {
4527 }
4529 {
4531 }
4533 {
4535 }
4536 }
4538 /* Can combine sseregparm with all attributes. */
4541 }
4543 /* Return 0 if the attributes for two types are incompatible, 1 if they
4544 are compatible, and 2 if they are nearly compatible (which causes a
4545 warning to be generated). */
4547 static int
4549 {
4550 /* Check for mismatch of non-default calling convention. */
4557 /* Check for mismatched fastcall/regparm types. */
4564 /* Check for mismatched sseregparm types. */
4569 /* Check for mismatched thiscall types. */
4574 /* Check for mismatched return types (cdecl vs stdcall). */
4580 }
4581 \f
4582 /* Return the regparm value for a function with the indicated TYPE and DECL.
4583 DECL may be NULL when calling function indirectly
4584 or considering a libcall. */
4586 static int
4588 {
4589 tree attr;
4599 {
4602 }
4610 /* Use register calling convention for local functions when possible. */
4613 && optimize
4615 {
4616 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4619 {
4622 /* Make sure no regparm register is taken by a
4623 fixed register variable. */
4628 /* We don't want to use regparm(3) for nested functions as
4629 these use a static chain pointer in the third argument. */
4633 /* Each fixed register usage increases register pressure,
4634 so less registers should be used for argument passing.
4635 This functionality can be overriden by an explicit
4636 regparm value. */
4639 globals++;
4641 local_regparm
4646 }
4647 }
4650 }
4652 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4653 DFmode (2) arguments in SSE registers for a function with the
4654 indicated TYPE and DECL. DECL may be NULL when calling function
4655 indirectly or considering a libcall. Otherwise return 0. */
4657 static int
4659 {
4662 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4663 by the sseregparm attribute. */
4666 {
4668 {
4670 {
4674 else
4677 }
4679 }
4682 }
4684 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4685 (and DFmode for SSE2) arguments in SSE registers. */
4687 {
4688 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4692 }
4695 }
4697 /* Return true if EAX is live at the start of the function. Used by
4698 ix86_expand_prologue to determine if we need special help before
4699 calling allocate_stack_worker. */
4701 static bool
4703 {
4704 /* Cheat. Don't bother working forward from ix86_function_regparm
4705 to the function type to whether an actual argument is located in
4706 eax. Instead just look at cfg info, which is still close enough
4707 to correct at this point. This gives false positives for broken
4708 functions that might use uninitialized data that happens to be
4709 allocated in eax, but who cares? */
4711 }
4713 /* Value is the number of bytes of arguments automatically
4714 popped when returning from a subroutine call.
4715 FUNDECL is the declaration node of the function (as a tree),
4716 FUNTYPE is the data type of the function (as a tree),
4717 or for a library call it is an identifier node for the subroutine name.
4718 SIZE is the number of bytes of arguments passed on the stack.
4720 On the 80386, the RTD insn may be used to pop them if the number
4721 of args is fixed, but if the number is variable then the caller
4722 must pop them all. RTD can't be used for library calls now
4723 because the library is compiled with the Unix compiler.
4724 Use of RTD is a selectable option, since it is incompatible with
4725 standard Unix calling sequences. If the option is not selected,
4726 the caller must always pop the args.
4728 The attribute stdcall is equivalent to RTD on a per module basis. */
4730 int
4732 {
4735 /* None of the 64-bit ABIs pop arguments. */
4741 /* Cdecl functions override -mrtd, and never pop the stack. */
4743 {
4744 /* Stdcall and fastcall functions will pop the stack if not
4745 variable args. */
4753 }
4755 /* Lose any fake structure return argument if it is passed on the stack. */
4758 {
4762 }
4765 }
4766 \f
4767 /* Argument support functions. */
4769 /* Return true when register may be used to pass function parameters. */
4770 bool
4772 {
4777 {
4781 else
4787 }
4790 {
4793 }
4794 else
4795 {
4799 }
4801 /* TODO: The function should depend on current function ABI but
4802 builtins.c would need updating then. Therefore we use the
4803 default ABI. */
4805 /* RAX is used as hidden argument to va_arg functions. */
4811 else
4818 }
4820 /* Return if we do not know how to pass TYPE solely in registers. */
4822 static bool
4824 {
4828 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4829 The layout_type routine is crafty and tries to trick us into passing
4830 currently unsupported vector types on the stack by using TImode. */
4833 }
4835 /* It returns the size, in bytes, of the area reserved for arguments passed
4836 in registers for the function represented by fndecl dependent to the used
4837 abi format. */
4838 int
4840 {
4844 else
4849 }
4851 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4852 call abi used. */
4853 enum calling_abi
4855 {
4857 {
4860 {
4863 }
4867 }
4869 }
4871 static bool
4873 {
4875 {
4877 {
4879 {
4882 }
4885 }
4886 }
4888 }
4890 static enum calling_abi
4892 {
4896 }
4898 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4899 call abi used. */
4900 enum calling_abi
4902 {
4906 }
4908 /* regclass.c */
4911 /* Implementation of call abi switching target hook. Specific to FNDECL
4912 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4913 for more details. */
4914 void
4916 {
4919 else
4921 }
4923 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4924 re-initialization of init_regs each time we switch function context since
4925 this is needed only during RTL expansion. */
4926 static void
4928 {
4932 }
4934 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4935 for a call to a function whose data type is FNTYPE.
4936 For a library call, FNTYPE is 0. */
4938 void
4942 tree fndecl)
4943 {
4949 else
4951 /* Set up the number of registers to use for passing arguments. */
4958 {
4962 }
4964 {
4967 {
4970 ? X86_64_SSE_REGPARM_MAX
4972 }
4973 }
4980 /* Because type might mismatch in between caller and callee, we need to
4981 use actual type of function for local calls.
4982 FIXME: cgraph_analyze can be told to actually record if function uses
4983 va_start so for local functions maybe_vaarg can be made aggressive
4984 helping K&R code.
4985 FIXME: once typesytem is fixed, we won't need this code anymore. */
4993 {
4994 /* If there are variable arguments, then we won't pass anything
4995 in registers in 32-bit mode. */
4997 {
5005 }
5007 /* Use ecx and edx registers if function has fastcall attribute,
5008 else look for regparm information. */
5010 {
5012 {
5015 }
5017 {
5020 }
5021 else
5023 }
5025 /* Set up the number of SSE registers used for passing SFmode
5026 and DFmode arguments. Warn for mismatching ABI. */
5028 }
5029 }
5031 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5032 But in the case of vector types, it is some vector mode.
5034 When we have only some of our vector isa extensions enabled, then there
5035 are some modes for which vector_mode_supported_p is false. For these
5036 modes, the generic vector support in gcc will choose some non-vector mode
5037 in order to implement the type. By computing the natural mode, we'll
5038 select the proper ABI location for the operand and not depend on whatever
5039 the middle-end decides to do with these vector types.
5041 The midde-end can't deal with the vector types > 16 bytes. In this
5042 case, we return the original mode and warn ABI change if CUM isn't
5043 NULL. */
5045 static enum machine_mode
5047 {
5051 {
5054 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5056 {
5061 else
5064 /* Get the mode which has this inner mode and number of units. */
5068 {
5070 {
5074 && !warnedavx
5076 {
5080 }
5082 }
5083 else
5085 }
5088 }
5089 }
5092 }
5094 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5095 this may not agree with the mode that the type system has chosen for the
5096 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5097 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5099 static rtx
5102 {
5103 rtx tmp;
5107 else
5108 {
5112 }
5115 }
5117 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5118 of this code is to classify each 8bytes of incoming argument by the register
5119 class and assign registers accordingly. */
5121 /* Return the union class of CLASS1 and CLASS2.
5122 See the x86-64 PS ABI for details. */
5124 static enum x86_64_reg_class
5126 {
5127 /* Rule #1: If both classes are equal, this is the resulting class. */
5131 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5132 the other class. */
5138 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5142 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5150 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5151 MEMORY is used. */
5160 /* Rule #6: Otherwise class SSE is used. */
5162 }
5164 /* Classify the argument of type TYPE and mode MODE.
5165 CLASSES will be filled by the register class used to pass each word
5166 of the operand. The number of words is returned. In case the parameter
5167 should be passed in memory, 0 is returned. As a special case for zero
5168 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5170 BIT_OFFSET is used internally for handling records and specifies offset
5171 of the offset in bits modulo 256 to avoid overflow cases.
5173 See the x86-64 PS ABI for details.
5174 */
5176 static int
5179 {
5180 HOST_WIDE_INT bytes =
5184 /* Variable sized entities are always passed/returned in memory. */
5193 {
5195 tree field;
5198 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5205 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5206 signalize memory class, so handle it as special case. */
5208 {
5211 }
5213 /* Classify each field of record and merge classes. */
5215 {
5217 /* And now merge the fields of structure. */
5219 {
5221 {
5227 /* Bitfields are always classified as integer. Handle them
5228 early, since later code would consider them to be
5229 misaligned integers. */
5231 {
5239 }
5240 else
5241 {
5246 /* Flexible array member is ignored. */
5253 {
5257 {
5260 "The ABI of passing struct with"
5261 " a flexible array member has"
5263 }
5265 }
5267 subclasses,
5276 }
5277 }
5278 }
5282 /* Arrays are handled as small records. */
5283 {
5290 /* The partial classes are now full classes. */
5301 }
5304 /* Unions are similar to RECORD_TYPE but offset is always 0.
5305 */
5307 {
5309 {
5317 bit_offset);
5322 }
5323 }
5328 }
5331 {
5332 /* When size > 16 bytes, if the first one isn't
5333 X86_64_SSE_CLASS or any other ones aren't
5334 X86_64_SSEUP_CLASS, everything should be passed in
5335 memory. */
5342 }
5344 /* Final merger cleanup. */
5346 {
5347 /* If one class is MEMORY, everything should be passed in
5348 memory. */
5352 /* The X86_64_SSEUP_CLASS should be always preceded by
5353 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5357 {
5358 /* The first one should never be X86_64_SSEUP_CLASS. */
5361 }
5363 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5364 everything should be passed in memory. */
5367 {
5370 /* The first one should never be X86_64_X87UP_CLASS. */
5373 {
5376 "The ABI of passing union with long double"
5378 }
5380 }
5381 }
5383 }
5385 /* Compute alignment needed. We align all types to natural boundaries with
5386 exception of XFmode that is aligned to 64bits. */
5388 {
5397 /* Misaligned fields are always returned in memory. */
5400 }
5402 /* for V1xx modes, just use the base mode */
5407 /* Classification of atomic types. */
5409 {
5425 {
5429 {
5432 }
5434 {
5437 }
5439 {
5443 }
5445 {
5448 }
5449 else
5451 }
5458 /* OImode shouldn't be used directly. */
5465 else
5483 else
5484 {
5488 {
5491 "The ABI of passing structure with complex float"
5493 }
5496 }
5505 /* This modes is larger than 16 bytes. */
5548 else
5552 }
5553 }
5555 /* Examine the argument and return set number of register required in each
5556 class. Return 0 iff parameter should be passed in memory. */
5557 static int
5560 {
5570 {
5592 }
5594 }
5596 /* Construct container for the argument used by GCC interface. See
5597 FUNCTION_ARG for the detailed description. */
5599 static rtx
5603 {
5604 /* The following variables hold the static issued_error state. */
5618 rtx ret;
5629 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5630 some less clueful developer tries to use floating-point anyway. */
5632 {
5634 {
5636 {
5639 }
5640 }
5642 {
5645 }
5647 }
5649 /* Likewise, error if the ABI requires us to return values in the
5650 x87 registers and the user specified -mno-80387. */
5656 {
5658 {
5661 }
5663 }
5665 /* First construct simple cases. Avoid SCmode, since we want to use
5666 single register to pass this type. */
5669 {
5684 /* Zero sized array, struct or class. */
5688 }
5709 /* Otherwise figure out the entries of the PARALLEL. */
5711 {
5715 {
5720 /* Merge TImodes on aligned occasions here too. */
5725 else
5727 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5733 intreg++;
5740 sse_regno++;
5747 sse_regno++;
5752 {
5758 {
5760 i++;
5761 }
5762 else
5775 }
5780 sse_regno++;
5784 }
5785 }
5787 /* Empty aligned struct, union or class. */
5795 }
5797 /* Update the data in CUM to advance over an argument of mode MODE
5798 and data type TYPE. (TYPE is null for libcalls where that information
5799 may not be available.) */
5801 static void
5804 {
5806 {
5813 /* FALLTHRU */
5824 {
5827 }
5831 /* OImode shouldn't be used directly. */
5840 /* FALLTHRU */
5856 {
5861 {
5864 }
5865 }
5875 {
5880 {
5883 }
5884 }
5886 }
5887 }
5889 static void
5892 {
5895 /* Unnamed 256bit vector mode parameters are passed on stack. */
5902 {
5907 }
5908 else
5910 }
5912 static void
5914 HOST_WIDE_INT words)
5915 {
5916 /* Otherwise, this should be passed indirect. */
5921 {
5924 }
5925 }
5927 void
5930 {
5935 else
5946 else
5948 }
5950 /* Define where to put the arguments to a function.
5951 Value is zero to push the argument on the stack,
5952 or a hard register in which to store the argument.
5954 MODE is the argument's machine mode.
5955 TYPE is the data type of the argument (as a tree).
5956 This is null for libcalls where that information may
5957 not be available.
5958 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5959 the preceding args and about the function being called.
5960 NAMED is nonzero if this argument is a named parameter
5961 (otherwise it is an extra parameter matching an ellipsis). */
5963 static rtx
5967 {
5970 /* Avoid the AL settings for the Unix64 ABI. */
5975 {
5982 /* FALLTHRU */
5988 {
5991 /* Fastcall allocates the first two DWORD (SImode) or
5992 smaller arguments to ECX and EDX if it isn't an
5993 aggregate type . */
5995 {
6001 /* ECX not EAX is the first allocated register. */
6004 }
6006 }
6015 /* FALLTHRU */
6017 /* In 32bit, we pass TImode in xmm registers. */
6025 {
6027 {
6031 }
6035 }
6039 /* OImode shouldn't be used directly. */
6049 {
6053 }
6063 {
6065 {
6069 }
6073 }
6075 }
6078 }
6080 static rtx
6083 {
6084 /* Handle a hidden AL argument containing number of registers
6085 for varargs x86-64 functions. */
6090 ? SSE_REGPARM_MAX
6092 ? X86_64_SSE_REGPARM_MAX
6098 {
6108 /* Unnamed 256bit vector mode parameters are passed on stack. */
6112 }
6118 }
6120 static rtx
6123 HOST_WIDE_INT bytes)
6124 {
6127 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6128 We use value of -2 to specify that current function call is MSABI. */
6132 /* If we've run out of registers, it goes on the stack. */
6138 /* Only floating point modes are passed in anything but integer regs. */
6140 {
6143 else
6144 {
6147 /* Unnamed floating parameters are passed in both the
6148 SSE and integer registers. */
6154 }
6155 }
6156 /* Handle aggregated types passed in register. */
6158 {
6163 }
6166 }
6168 rtx
6171 {
6177 else
6181 /* To simplify the code below, represent vector types with a vector mode
6182 even if MMX/SSE are not active. */
6190 else
6192 }
6194 /* A C expression that indicates when an argument must be passed by
6195 reference. If nonzero for an argument, a copy of that argument is
6196 made in memory and a pointer to the argument is passed instead of
6197 the argument itself. The pointer is passed in whatever way is
6198 appropriate for passing a pointer to that type. */
6200 static bool
6204 {
6205 /* See Windows x64 Software Convention. */
6207 {
6210 {
6211 /* Arrays are passed by reference. */
6216 {
6217 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6218 are passed by reference. */
6220 }
6221 }
6223 /* __m128 is passed by reference. */
6229 }
6230 }
6235 }
6237 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6238 ABI. */
6239 static bool
6241 {
6253 {
6254 /* Walk the aggregates recursively. */
6256 {
6260 {
6261 tree field;
6263 /* Walk all the structure fields. */
6265 {
6269 }
6271 }
6274 /* Just for use if some languages passes arrays by value. */
6281 }
6282 }
6284 }
6286 /* Gives the alignment boundary, in bits, of an argument with the
6287 specified mode and type. */
6289 int
6291 {
6294 {
6295 /* Since canonical type is used for call, we convert it to
6296 canonical type if needed. */
6300 }
6301 else
6305 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6306 natural boundaries. */
6308 {
6309 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6310 make an exception for SSE modes since these require 128bit
6311 alignment.
6313 The handling here differs from field_alignment. ICC aligns MMX
6314 arguments to 4 byte boundaries, while structure fields are aligned
6315 to 8 byte boundaries. */
6317 {
6320 }
6321 else
6322 {
6325 }
6326 }
6330 }
6332 /* Return true if N is a possible register number of function value. */
6334 bool
6336 {
6338 {
6343 /* TODO: The function should depend on current function ABI but
6344 builtins.c would need updating then. Therefore we use the
6345 default ABI. */
6357 }
6360 }
6362 /* Define how to find the value returned by a function.
6363 VALTYPE is the data type of the value (as a tree).
6364 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6365 otherwise, FUNC is 0. */
6367 static rtx
6370 {
6373 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6374 we normally prevent this case when mmx is not available. However
6375 some ABIs may require the result to be returned like DImode. */
6379 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6380 we prevent this case when sse is not available. However some ABIs
6381 may require the result to be returned like integer TImode. */
6386 /* 32-byte vector modes in %ymm0. */
6390 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6393 else
6394 /* Most things go in %eax. */
6397 /* Override FP return register with %xmm0 for local functions when
6398 SSE math is enabled or for functions with sseregparm attribute. */
6400 {
6405 }
6407 /* OImode shouldn't be used directly. */
6411 }
6413 static rtx
6415 const_tree valtype)
6416 {
6417 rtx ret;
6419 /* Handle libcalls, which don't provide a type node. */
6421 {
6423 {
6440 }
6441 }
6447 /* For zero sized structures, construct_container returns NULL, but we
6448 need to keep rest of compiler happy by returning meaningful value. */
6453 }
6455 static rtx
6457 {
6461 {
6463 {
6476 }
6477 }
6479 }
6481 static rtx
6484 {
6496 else
6498 }
6500 static rtx
6503 {
6509 }
6511 rtx
6513 {
6515 }
6517 /* Return true iff type is returned in memory. */
6519 static int ATTRIBUTE_UNUSED
6521 {
6522 HOST_WIDE_INT size;
6533 {
6534 /* User-created vectors small enough to fit in EAX. */
6538 /* MMX/3dNow values are returned in MM0,
6539 except when it doesn't exits. */
6543 /* SSE values are returned in XMM0, except when it doesn't exist. */
6547 /* AVX values are returned in YMM0, except when it doesn't exist. */
6550 }
6558 /* OImode shouldn't be used directly. */
6562 }
6564 static int ATTRIBUTE_UNUSED
6566 {
6569 }
6571 static int ATTRIBUTE_UNUSED
6573 {
6576 /* __m128 is returned in xmm0. */
6581 /* Otherwise, the size must be exactly in [1248]. */
6583 }
6585 static bool
6587 {
6588 #ifdef SUBTARGET_RETURN_IN_MEMORY
6590 #else
6594 {
6597 else
6599 }
6600 else
6602 #endif
6603 }
6605 /* Return false iff TYPE is returned in memory. This version is used
6606 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6607 but differs notably in that when MMX is available, 8-byte vectors
6608 are returned in memory, rather than in MMX registers. */
6610 bool
6612 {
6625 {
6626 /* Return in memory only if MMX registers *are* available. This
6627 seems backwards, but it is consistent with the existing
6628 Solaris x86 ABI. */
6633 }
6640 }
6642 /* When returning SSE vector types, we have a choice of either
6643 (1) being abi incompatible with a -march switch, or
6644 (2) generating an error.
6645 Given no good solution, I think the safest thing is one warning.
6646 The user won't be able to use -Werror, but....
6648 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6649 called in response to actually generating a caller or callee that
6650 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6651 via aggregate_value_p for general type probing from tree-ssa. */
6653 static rtx
6655 {
6659 {
6660 /* Look at the return type of the function, not the function type. */
6664 {
6667 {
6671 }
6672 }
6675 {
6677 {
6681 }
6682 }
6683 }
6686 }
6688 \f
6689 /* Create the va_list data type. */
6691 /* Returns the calling convention specific va_list date type.
6692 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6694 static tree
6696 {
6699 /* For i386 we use plain pointer to argument area. */
6709 unsigned_type_node);
6712 unsigned_type_node);
6715 ptr_type_node);
6718 ptr_type_node);
6737 /* The correct type is an array type of one element. */
6739 }
6741 /* Setup the builtin va_list data type and for 64-bit the additional
6742 calling convention specific va_list data types. */
6744 static tree
6746 {
6749 /* Initialize abi specific va_list builtin types. */
6751 {
6752 tree t;
6754 {
6759 }
6760 else
6761 {
6766 }
6768 {
6773 }
6774 else
6775 {
6780 }
6781 }
6784 }
6786 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6788 static void
6790 {
6792 rtx label;
6793 rtx label_ref;
6794 rtx tmp_reg;
6795 rtx nsse_reg;
6796 alias_set_type set;
6804 /* GPR size of varargs save area. */
6807 else
6810 /* FPR size of varargs save area. We don't need it if we don't pass
6811 anything in SSE registers. */
6814 else
6824 i < regparm
6826 i++)
6827 {
6834 }
6837 {
6838 /* Now emit code to save SSE registers. The AX parameter contains number
6839 of SSE parameter registers used to call this function. We use
6840 sse_prologue_save insn template that produces computed jump across
6841 SSE saves. We need some preparation work to get this working. */
6846 /* Compute address to jump to :
6847 label - eax*4 + nnamed_sse_arguments*4 Or
6848 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6856 /* vmovaps is one byte longer than movaps. */
6860 nsse_reg)));
6863 emit_move_insn
6867 label_ref,
6870 else
6874 /* Compute address of memory block we save into. We always use pointer
6875 pointing 127 bytes after first byte to store - this is needed to keep
6876 instruction size limited by 4 bytes (5 bytes for AVX) with one
6877 byte displacement. */
6887 /* And finally do the dirty job! */
6890 }
6891 }
6893 static void
6895 {
6900 {
6911 }
6912 }
6914 static void
6918 {
6919 CUMULATIVE_ARGS next_cum;
6920 tree fntype;
6922 /* This argument doesn't appear to be used anymore. Which is good,
6923 because the old code here didn't suppress rtl generation. */
6931 /* For varargs, we do not want to skip the dummy va_dcl argument.
6932 For stdargs, we do want to skip the last named argument. */
6939 else
6941 }
6943 /* Checks if TYPE is of kind va_list char *. */
6945 static bool
6947 {
6948 tree canonic;
6950 /* For 32-bit it is always true. */
6956 }
6958 /* Implement va_start. */
6960 static void
6962 {
6966 tree type;
6968 /* Only 64bit target needs something special. */
6970 {
6973 }
6986 /* Count number of gp and fp argument registers used. */
6992 {
6998 }
7001 {
7007 }
7009 /* Find the overflow area. */
7020 {
7021 /* Find the register save area.
7022 Prologue of the function save it right above stack frame. */
7031 }
7032 }
7034 /* Implement va_arg. */
7036 static tree
7039 {
7046 rtx container;
7048 tree ptrtype;
7052 /* Only 64bit target needs something special. */
7076 {
7083 /* Unnamed 256bit vector mode parameters are passed on stack. */
7085 {
7088 }
7096 }
7098 /* Pull the value out of the saved registers. */
7103 {
7117 /* In case we are passing structure, verify that it is consecutive block
7118 on the register save area. If not we need to do moves. */
7120 {
7121 /* Verify that all registers are strictly consecutive */
7123 {
7127 {
7132 }
7133 }
7134 else
7135 {
7139 {
7144 }
7145 }
7146 }
7148 {
7151 }
7152 else
7153 {
7156 }
7158 /* First ensure that we fit completely in registers. */
7160 {
7167 }
7169 {
7177 }
7179 /* Compute index to start of area used for integer regs. */
7181 {
7182 /* int_addr = gpr + sav; */
7186 }
7188 {
7189 /* sse_addr = fpr + sav; */
7193 }
7195 {
7199 /* addr = &temp; */
7204 {
7217 {
7220 }
7221 else
7222 {
7225 }
7237 }
7238 }
7241 {
7245 }
7248 {
7252 }
7257 }
7259 /* ... otherwise out of the overflow area. */
7261 /* When we align parameter on stack for caller, if the parameter
7262 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7263 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7264 here with caller. */
7269 /* Care for on-stack alignment if needed. */
7273 else
7274 {
7282 }
7299 }
7300 \f
7301 /* Return nonzero if OPNUM's MEM should be matched
7302 in movabs* patterns. */
7304 int
7306 {
7318 }
7319 \f
7320 /* Initialize the table of extra 80387 mathematical constants. */
7322 static void
7324 {
7326 {
7332 };
7336 {
7338 /* Ensure each constant is rounded to XFmode precision. */
7341 }
7344 }
7346 /* Return true if the constant is something that can be loaded with
7347 a special instruction. */
7349 int
7351 {
7354 REAL_VALUE_TYPE r;
7366 /* For XFmode constants, try to find a special 80387 instruction when
7367 optimizing for size or on those CPUs that benefit from them. */
7370 {
7379 }
7381 /* Load of the constant -0.0 or -1.0 will be split as
7382 fldz;fchs or fld1;fchs sequence. */
7389 }
7391 /* Return the opcode of the special instruction to be used to load
7392 the constant X. */
7396 {
7398 {
7418 }
7419 }
7421 /* Return the CONST_DOUBLE representing the 80387 constant that is
7422 loaded by the specified special instruction. The argument IDX
7423 matches the return value from standard_80387_constant_p. */
7425 rtx
7427 {
7434 {
7445 }
7448 XFmode);
7449 }
7451 /* Return 1 if X is all 0s and 2 if x is all 1s
7452 in supported SSE vector mode. */
7454 int
7456 {
7463 {
7472 }
7475 }
7477 /* Return the opcode of the special instruction to be used to load
7478 the constant X. */
7482 {
7484 {
7487 {
7502 }
7507 }
7509 }
7511 /* Returns 1 if OP contains a symbol reference */
7513 int
7515 {
7524 {
7526 {
7532 }
7536 }
7539 }
7541 /* Return 1 if it is appropriate to emit `ret' instructions in the
7542 body of a function. Do this only if the epilogue is simple, needing a
7543 couple of insns. Prior to reloading, we can't tell how many registers
7544 must be saved, so return 0 then. Return 0 if there is no frame
7545 marker to de-allocate. */
7547 int
7549 {
7555 /* Don't allow more than 32 pop, since that's all we can do
7556 with one instruction. */
7564 }
7565 \f
7566 /* Value should be nonzero if functions must have frame pointers.
7567 Zero means the frame pointer need not be set up (and parms may
7568 be accessed via the stack pointer) in functions that seem suitable. */
7570 static bool
7572 {
7573 /* If we accessed previous frames, then the generated code expects
7574 to be able to access the saved ebp value in our frame. */
7578 /* Several x86 os'es need a frame pointer for other reasons,
7579 usually pertaining to setjmp. */
7583 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7584 the frame pointer by default. Turn it back on now if we've not
7585 got a leaf function. */
7587 && (!current_function_is_leaf
7595 }
7597 /* Record that the current function accesses previous call frames. */
7599 void
7601 {
7603 }
7604 \f
7605 #ifndef USE_HIDDEN_LINKONCE
7606 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7607 # define USE_HIDDEN_LINKONCE 1
7608 # else
7609 # define USE_HIDDEN_LINKONCE 0
7610 # endif
7611 #endif
7615 /* Fills in the label name that should be used for a pc thunk for
7616 the given register. */
7618 static void
7620 {
7625 else
7627 }
7630 /* This function generates code for -fpic that loads %ebx with
7631 the return address of the caller and then returns. */
7633 static void
7635 {
7640 {
7642 tree decl;
7657 #if TARGET_MACHO
7659 {
7668 }
7669 else
7670 #endif
7672 {
7683 }
7684 else
7685 {
7688 }
7694 /* Make sure unwind info is emitted for the thunk if needed. */
7706 }
7707 }
7709 /* Emit code for the SET_GOT patterns. */
7713 {
7719 {
7720 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7725 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7726 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7727 an unadorned address. */
7732 }
7737 {
7742 else
7743 {
7745 #ifdef DWARF2_UNWIND_INFO
7746 /* The call to next label acts as a push. */
7748 {
7749 rtx insn;
7753 stack_pointer_rtx,
7758 }
7759 #endif
7760 }
7762 #if TARGET_MACHO
7763 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7764 is what will be referenced by the Mach-O PIC subsystem. */
7767 #endif
7773 {
7775 #ifdef DWARF2_UNWIND_INFO
7776 /* The pop is a pop and clobbers dest, but doesn't restore it
7777 for unwind info purposes. */
7779 {
7780 rtx insn;
7786 stack_pointer_rtx,
7791 }
7792 #endif
7793 }
7794 }
7795 else
7796 {
7801 #ifdef DWARF2_UNWIND_INFO
7802 /* Ensure all queued register saves are flushed before the
7803 call. */
7805 {
7806 rtx insn;
7811 }
7812 #endif
7816 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7817 is what will be referenced by the Mach-O PIC subsystem. */
7818 #if TARGET_MACHO
7821 else
7824 #endif
7825 }
7832 else
7836 }
7838 /* Generate an "push" pattern for input ARG. */
7840 static rtx
7842 {
7849 stack_pointer_rtx)),
7850 arg);
7851 }
7853 /* Return >= 0 if there is an unused call-clobbered register available
7854 for the entire function. */
7856 static unsigned int
7858 {
7861 {
7863 /* Can't use the same register for both PIC and DRAP. */
7866 else
7871 }
7874 }
7876 /* Return 1 if we need to save REGNO. */
7877 static int
7879 {
7886 {
7890 }
7893 {
7896 {
7902 }
7903 }
7912 }
7914 /* Return number of saved general prupose registers. */
7916 static int
7918 {
7924 nregs ++;
7926 }
7928 /* Return number of saved SSE registrers. */
7930 static int
7932 {
7940 nregs ++;
7942 }
7944 /* Given FROM and TO register numbers, say whether this elimination is
7945 allowed. If stack alignment is needed, we can only replace argument
7946 pointer with hard frame pointer, or replace frame pointer with stack
7947 pointer. Otherwise, frame pointer elimination is automatically
7948 handled and all other eliminations are valid. */
7950 static bool
7952 {
7958 else
7960 }
7962 /* Return the offset between two registers, one to be eliminated, and the other
7963 its replacement, at the start of a routine. */
7965 HOST_WIDE_INT
7967 {
7976 else
7977 {
7985 }
7986 }
7988 /* In a dynamically-aligned function, we can't know the offset from
7989 stack pointer to frame pointer, so we must ensure that setjmp
7990 eliminates fp against the hard fp (%ebp) rather than trying to
7991 index from %esp up to the top of the frame across a gap that is
7992 of unknown (at compile-time) size. */
7993 static rtx
7995 {
7997 }
7999 /* Fill structure ix86_frame about frame of currently computed function. */
8001 static void
8003 {
8005 HOST_WIDE_INT offset;
8015 /* MS ABI seem to require stack alignment to be always 16 except for function
8016 prologues. */
8018 {
8023 }
8029 /* During reload iteration the amount of registers saved can change.
8030 Recompute the value as needed. Do not recompute when amount of registers
8031 didn't change as reload does multiple calls to the function and does not
8032 expect the decision to change within single iteration. */
8035 {
8039 /* The fast prologue uses move instead of push to save registers. This
8040 is significantly longer, but also executes faster as modern hardware
8041 can execute the moves in parallel, but can't do that for push/pop.
8043 Be careful about choosing what prologue to emit: When function takes
8044 many instructions to execute we may use slow version as well as in
8045 case function is known to be outside hot spot (this is known with
8046 feedback only). Weight the size of function by number of registers
8047 to save as it is cheap to use one or two push instructions but very
8048 slow to use many of them. */
8052 || (flag_branch_probabilities
8055 else
8058 }
8062 else
8065 /* Skip return address. */
8068 /* Skip pushed static chain. */
8072 /* Skip saved base pointer. */
8078 /* Set offset to aligned because the realigned frame starts from
8079 here. */
8083 /* Register save area */
8086 /* Align SSE reg save area. */
8089 else
8092 /* SSE register save area. */
8095 /* Va-arg area */
8099 /* Align start of frame for local function. */
8105 /* Frame pointer points here. */
8110 /* Add outgoing arguments area. Can be skipped if we eliminated
8111 all the function calls as dead code.
8112 Skipping is however impossible when function calls alloca. Alloca
8113 expander assumes that last crtl->outgoing_args_size
8114 of stack frame are unused. */
8118 {
8121 }
8122 else
8125 /* Align stack boundary. Only needed if we're calling another function
8126 or using alloca. */
8131 else
8136 /* We've reached end of stack frame. */
8139 /* Size prologue needs to allocate. */
8149 && current_function_sp_is_unchanging
8150 && current_function_is_leaf
8152 {
8158 }
8159 else
8163 }
8165 /* Emit code to save registers in the prologue. */
8167 static void
8169 {
8171 rtx insn;
8175 {
8178 }
8179 }
8181 /* Emit code to save registers using MOV insns. First register
8182 is restored from POINTER + OFFSET. */
8183 static void
8185 {
8187 rtx insn;
8191 {
8197 }
8198 }
8200 /* Emit code to save registers using MOV insns. First register
8201 is restored from POINTER + OFFSET. */
8202 static void
8204 {
8206 rtx insn;
8207 rtx mem;
8211 {
8217 }
8218 }
8222 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8223 manipulation insn. Don't add it if the previously
8224 saved value will be left untouched within stack red-zone till return,
8225 as unwinders can find the same value in the register and
8226 on the stack. */
8228 static void
8230 {
8232 && !TARGET_64BIT_MS_ABI
8238 {
8241 }
8242 else
8243 queued_cfa_restores
8245 }
8247 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8249 static void
8251 {
8252 rtx last;
8256 ;
8261 }
8263 /* Expand prologue or epilogue stack adjustment.
8264 The pattern exist to put a dependency on all ebp-based memory accesses.
8265 STYLE should be negative if instructions should be marked as frame related,
8266 zero if %r11 register is live and cannot be freely used and positive
8267 otherwise. */
8269 static void
8272 {
8273 rtx insn;
8279 else
8280 {
8281 rtx r11;
8282 /* r11 is used by indirect sibcall return as well, set before the
8283 epilogue and used after the epilogue. ATM indirect sibcall
8284 shouldn't be used together with huge frame sizes in one
8285 function because of the frame_size check in sibcall.c. */
8292 offset));
8293 }
8299 {
8300 rtx r;
8310 }
8313 }
8315 /* Find an available register to be used as dynamic realign argument
8316 pointer regsiter. Such a register will be written in prologue and
8317 used in begin of body, so it must not be
8318 1. parameter passing register.
8319 2. GOT pointer.
8320 We reuse static-chain register if it is available. Otherwise, we
8321 use DI for i386 and R13 for x86-64. We chose R13 since it has
8322 shorter encoding.
8324 Return: the regno of chosen register. */
8326 static unsigned int
8328 {
8332 {
8333 /* Use R13 for nested function or function need static chain.
8334 Since function with tail call may use any caller-saved
8335 registers in epilogue, DRAP must not use caller-saved
8336 register in such case. */
8341 }
8342 else
8343 {
8344 /* Use DI for nested function or function need static chain.
8345 Since function with tail call may use any caller-saved
8346 registers in epilogue, DRAP must not use caller-saved
8347 register in such case. */
8351 /* Reuse static chain register if it isn't used for parameter
8352 passing. */
8359 else
8361 }
8362 }
8364 /* Return minimum incoming stack alignment. */
8366 static unsigned int
8368 {
8371 /* Prefer the one specified at command line. */
8374 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8375 if -mstackrealign is used, it isn't used for sibcall check and
8376 estimated stack alignment is 128bit. */
8378 && !TARGET_64BIT
8379 && ix86_force_align_arg_pointer
8382 else
8385 /* Incoming stack alignment can be changed on individual functions
8386 via force_align_arg_pointer attribute. We use the smallest
8387 incoming stack boundary. */
8393 /* The incoming stack frame has to be aligned at least at
8394 parm_stack_boundary. */
8398 /* Stack at entrance of main is aligned by runtime. We use the
8399 smallest incoming stack boundary. */
8407 }
8409 /* Update incoming stack boundary and estimated stack alignment. */
8411 static void
8413 {
8414 ix86_incoming_stack_boundary
8417 /* x86_64 vararg needs 16byte stack alignment for register save
8418 area. */
8423 }
8425 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8426 needed or an rtx for DRAP otherwise. */
8428 static rtx
8430 {
8435 {
8436 /* Assign DRAP to vDRAP and returns vDRAP */
8438 rtx drap_vreg;
8439 rtx arg_ptr;
8452 {
8455 }
8457 }
8458 else
8460 }
8462 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8464 static rtx
8466 {
8468 }
8470 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8471 to be generated in correct form. */
8472 static void
8474 {
8475 /* Check if stack realign is really needed after reload, and
8476 stores result in cfun */
8477 unsigned int incoming_stack_boundary
8481 < (current_function_is_leaf
8486 {
8487 /* After stack_realign_needed is finalized, we can't no longer
8488 change it. */
8490 }
8491 else
8492 {
8495 }
8496 }
8498 /* Expand the prologue into a bunch of separate insns. */
8500 void
8502 {
8503 rtx insn;
8506 HOST_WIDE_INT allocate;
8511 /* DRAP should not coexist with stack_realign_fp */
8514 /* Initialize CFA state for before the prologue. */
8521 {
8524 /* Make sure the function starts with
8525 8b ff movl.s %edi,%edi
8526 55 push %ebp
8527 8b ec movl.s %esp,%ebp
8529 This matches the hookable function prologue in Win32 API
8530 functions in Microsoft Windows XP Service Pack 2 and newer.
8531 Wine uses this to enable Windows apps to hook the Win32 API
8532 functions provided by Wine. */
8537 stack_pointer_rtx));
8541 {
8542 /* The push %ebp and movl.s %esp, %ebp already set up
8543 the frame pointer. No need to do this again. */
8549 }
8550 else
8551 /* If the frame pointer is not needed, pop %ebp again. This
8552 could be optimized for cases where ebp needs to be backed up
8553 for some other reason. If stack realignment is needed, pop
8554 the base pointer again, align the stack, and later regenerate
8555 the frame pointer setup. The frame pointer generated by the
8556 hook prologue is not aligned, so it can't be used. */
8558 }
8560 /* The first insn of a function that accepts its static chain on the
8561 stack is to push the register that would be filled in by a direct
8562 call. This insn will be skipped by the trampoline. */
8564 {
8565 rtx t;
8570 /* We don't want to interpret this push insn as a register save,
8571 only as a stack adjustment. The real copy of the register as
8572 a save will be done later, if needed. */
8577 }
8579 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8580 of DRAP is needed and stack realignment is really needed after reload */
8582 {
8594 /* Grab the argument pointer. */
8598 /* Only need to push parameter pointer reg if it is caller
8599 saved reg */
8601 {
8602 /* Push arg pointer reg */
8605 }
8611 /* Align the stack. */
8613 stack_pointer_rtx,
8617 /* Replicate the return address on the stack so that return
8618 address can be reached via (argp - 1) slot. This is needed
8619 to implement macro RETURN_ADDR_RTX and intrinsic function
8620 expand_builtin_return_addr etc. */
8626 }
8628 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8629 slower on all targets. Also sdb doesn't like it. */
8632 {
8641 }
8644 {
8648 /* Align the stack. */
8650 stack_pointer_rtx,
8653 }
8659 else
8662 /* When using red zone we may start register saving before allocating
8663 the stack frame saving one cycle of the prologue. However I will
8664 avoid doing this if I am going to have to probe the stack since
8665 at least on x86_64 the stack probe can turn into a call that clobbers
8666 a red zone location */
8671 ? hard_frame_pointer_rtx
8676 ;
8681 else
8682 {
8685 rtx t;
8689 else
8693 {
8696 }
8702 else
8707 {
8713 }
8716 {
8719 allocate
8722 else
8725 }
8726 }
8731 {
8736 frame.to_allocate
8738 else
8741 }
8747 else
8757 {
8764 }
8767 {
8769 {
8771 {
8781 }
8782 else
8784 }
8785 else
8787 }
8789 /* In the pic_reg_used case, make sure that the got load isn't deleted
8790 when mcount needs it. Blockage to avoid call movement across mcount
8791 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8792 note. */
8797 {
8798 /* vDRAP is setup but after reload it turns out stack realign
8799 isn't necessary, here we will emit prologue to setup DRAP
8800 without stack realign adjustment */
8801 rtx x;
8808 }
8810 /* Prevent instructions from being scheduled into register save push
8811 sequence when access to the redzone area is done through frame pointer.
8812 The offset between the frame pointer and the stack pointer is calculated
8813 relative to the value of the stack pointer at the end of the function
8814 prologue, and moving instructions that access redzone area via frame
8815 pointer inside push sequence violates this assumption. */
8819 /* Emit cld instruction if stringops are used in the function. */
8822 }
8824 /* Emit code to restore REG using a POP insn. */
8826 static void
8828 {
8833 {
8834 /* Previously we'd represented the CFA as an expression
8835 like *(%ebp - 8). We've just popped that value from
8836 the stack, which means we need to reset the CFA to
8837 the drap register. This will remain until we restore
8838 the stack pointer. */
8842 }
8845 {
8850 }
8852 /* When the frame pointer is the CFA, and we pop it, we are
8853 swapping back to the stack pointer as the CFA. This happens
8854 for stack frames that don't allocate other data, so we assume
8855 the stack pointer is now pointing at the return address, i.e.
8856 the function entry state, which makes the offset be 1 word. */
8859 {
8867 }
8870 }
8872 /* Emit code to restore saved registers using POP insns. */
8874 static void
8876 {
8881 {
8883 red_offset);
8885 }
8886 }
8888 /* Emit code and notes for the LEAVE instruction. */
8890 static void
8892 {
8898 {
8906 }
8907 }
8909 /* Emit code to restore saved registers using MOV insns. First register
8910 is restored from POINTER + OFFSET. */
8911 static void
8913 HOST_WIDE_INT red_offset,
8915 {
8918 rtx insn;
8922 {
8925 /* Ensure that adjust_address won't be forced to produce pointer
8926 out of range allowed by x86-64 instruction set. */
8928 {
8929 rtx r11;
8936 }
8943 {
8944 /* Previously we'd represented the CFA as an expression
8945 like *(%ebp - 8). We've just popped that value from
8946 the stack, which means we need to reset the CFA to
8947 the drap register. This will remain until we restore
8948 the stack pointer. */
8951 }
8952 else
8956 }
8957 }
8959 /* Emit code to restore saved registers using MOV insns. First register
8960 is restored from POINTER + OFFSET. */
8961 static void
8963 HOST_WIDE_INT red_offset,
8965 {
8968 rtx mem;
8972 {
8975 /* Ensure that adjust_address won't be forced to produce pointer
8976 out of range allowed by x86-64 instruction set. */
8978 {
8979 rtx r11;
8986 }
8995 }
8996 }
8998 /* Restore function stack, frame, and registers. */
9000 void
9002 {
9011 /* When stack is realigned, SP must be valid. */
9012 sp_valid = (!frame_pointer_needed
9013 || current_function_sp_is_unchanging
9018 /* See the comment about red zone and frame
9019 pointer usage in ix86_expand_prologue. */
9026 /* Calculate start of saved registers relative to ebp. Special care
9027 must be taken for the normal return case of a function using
9028 eh_return: the eax and edx registers are marked as saved, but not
9029 restored along this path. */
9036 /* Calculate start of saved registers relative to esp on entry of the
9037 function. When realigning stack, this needs to be the most negative
9038 value possible at runtime. */
9051 /* If we're only restoring one register and sp is not valid then
9052 using a move instruction to restore the register since it's
9053 less work than reloading sp and popping the register.
9055 The default code result in stack adjustment using add/lea instruction,
9056 while this code results in LEAVE instruction (or discrete equivalent),
9057 so it is profitable in some other cases as well. Especially when there
9058 are no registers to restore. We also use this code when TARGET_USE_LEAVE
9059 and there is exactly one register to pop. This heuristic may need some
9060 tuning in future. */
9062 || (TARGET_EPILOGUE_USING_MOVE
9072 {
9073 /* Restore registers. We can use ebp or esp to address the memory
9074 locations. If both are available, default to ebp, since offsets
9075 are known to be small. Only exception is esp pointing directly
9076 to the end of block of saved registers, where we may simplify
9077 addressing mode.
9079 If we are realigning stack with bp and sp, regs restore can't
9080 be addressed by bp. sp must be used instead. */
9085 {
9090 frame.to_allocate
9093 red_offset
9096 }
9097 else
9098 {
9103 offset
9106 red_offset
9109 }
9113 /* eh_return epilogues need %ecx added to the stack pointer. */
9115 {
9118 /* Stack align doesn't work with eh_return. */
9120 /* Neither does regparm nested functions. */
9124 {
9132 /* Note that we use SA as a temporary CFA, as the return
9133 address is at the proper place relative to it. We
9134 pretend this happens at the FP restore insn because
9135 prior to this insn the FP would be stored at the wrong
9136 offset relative to SA, and after this insn we have no
9137 other reasonable register to use for the CFA. We don't
9138 bother resetting the CFA to the SP for the duration of
9139 the return insn. */
9150 }
9151 else
9152 {
9163 {
9167 UNITS_PER_WORD));
9169 }
9170 }
9171 }
9179 /* If not an i386, mov & pop is faster than "leave". */
9183 else
9184 {
9186 hard_frame_pointer_rtx,
9190 }
9191 }
9192 else
9193 {
9194 /* First step is to deallocate the stack frame so that we can
9195 pop the registers.
9197 If we realign stack with frame pointer, then stack pointer
9198 won't be able to recover via lea $offset(%bp), %sp, because
9199 there is a padding area between bp and sp for realign.
9200 "add $to_allocate, %sp" must be used instead. */
9202 {
9206 hard_frame_pointer_rtx,
9215 }
9217 {
9226 }
9233 {
9234 /* Leave results in shorter dependency chains on CPUs that are
9235 able to grok it fast. */
9238 else
9239 {
9240 /* For stack realigned really happens, recover stack
9241 pointer to hard frame pointer is a must, if not using
9242 leave. */
9245 hard_frame_pointer_rtx,
9248 red_offset);
9249 }
9250 }
9251 }
9254 {
9256 rtx insn;
9279 }
9281 /* Remove the saved static chain from the stack. The use of ECX is
9282 merely as a scratch register, not as the actual static chain. */
9284 {
9297 }
9299 /* Sibcall epilogues don't want a return instruction. */
9301 {
9304 }
9307 {
9310 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9311 address, do explicit add, and jump indirectly to the caller. */
9314 {
9316 rtx insn;
9318 /* There is no "pascal" calling convention in any 64bit ABI. */
9333 }
9334 else
9336 }
9337 else
9340 /* Restore the state back to the state from the prologue,
9341 so that it's correct for the next epilogue. */
9343 }
9345 /* Reset from the function's potential modifications. */
9347 static void
9349 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9350 {
9353 #if TARGET_MACHO
9354 /* Mach-O doesn't support labels at the end of objects, so if
9355 it looks like we might want one, insert a NOP. */
9356 {
9367 }
9368 #endif
9370 }
9371 \f
9372 /* Extract the parts of an RTL expression that is a valid memory address
9373 for an instruction. Return 0 if the structure of the address is
9374 grossly off. Return -1 if the address contains ASHIFT, so it is not
9375 strictly valid, but still used for computing length of lea instruction. */
9377 int
9379 {
9390 {
9395 do
9396 {
9401 }
9408 {
9411 {
9421 && TARGET_TLS_DIRECT_SEG_REFS
9424 else
9434 else
9449 }
9450 }
9451 }
9453 {
9456 }
9458 {
9459 rtx tmp;
9461 /* We're called for lea too, which implements ashift on occasion. */
9471 }
9472 else
9475 /* Extract the integral value of scale. */
9477 {
9481 }
9486 /* Avoid useless 0 displacement. */
9490 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9495 {
9496 rtx tmp;
9499 }
9501 /* Special case: %ebp cannot be encoded as a base without a displacement.
9502 Similarly %r13. */
9504 && base_reg
9513 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9514 Avoid this by transforming to [%esi+0].
9515 Reload calls address legitimization without cfun defined, so we need
9516 to test cfun for being non-NULL. */
9523 /* Special case: encode reg+reg instead of reg*2. */
9527 /* Special case: scaling cannot be encoded without base or displacement. */
9538 }
9539 \f
9540 /* Return cost of the memory address x.
9541 For i386, it is better to use a complex address than let gcc copy
9542 the address into a reg and make a new pseudo. But not if the address
9543 requires to two regs - that would mean more pseudos with longer
9544 lifetimes. */
9545 static int
9547 {
9559 /* Attempt to minimize number of registers in the address. */
9565 cost++;
9572 cost++;
9574 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9575 since it's predecode logic can't detect the length of instructions
9576 and it degenerates to vector decoded. Increase cost of such
9577 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9578 to split such addresses or even refuse such addresses at all.
9580 Following addressing modes are affected:
9581 [base+scale*index]
9582 [scale*index+disp]
9583 [base+index]
9585 The first and last case may be avoidable by explicitly coding the zero in
9586 memory address, but I don't have AMD-K6 machine handy to check this
9587 theory. */
9596 }
9597 \f
9598 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9599 this is used for to form addresses to local data when -fPIC is in
9600 use. */
9602 static bool
9604 {
9607 }
9609 /* Determine if a given RTX is a valid constant. We already know this
9610 satisfies CONSTANT_P. */
9612 bool
9614 {
9616 {
9621 {
9625 }
9630 /* Only some unspecs are valid as "constants". */
9633 {
9649 }
9651 /* We must have drilled down to a symbol. */
9656 /* FALLTHRU */
9659 /* TLS symbols are never valid. */
9663 /* DLLIMPORT symbols are never valid. */
9682 }
9684 /* Otherwise we handle everything else in the move patterns. */
9686 }
9688 /* Determine if it's legal to put X into the constant pool. This
9689 is not possible for the address of thread-local symbols, which
9690 is checked above. */
9692 static bool
9694 {
9695 /* We can always put integral constants and vectors in memory. */
9697 {
9705 }
9707 }
9710 /* Nonzero if the constant value X is a legitimate general operand
9711 when generating PIC code. It is given that flag_pic is on and
9712 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9714 bool
9716 {
9717 rtx inner;
9720 {
9727 /* Only some unspecs are valid as "constants". */
9730 {
9743 }
9744 /* FALLTHRU */
9752 }
9753 }
9755 /* Determine if a given CONST RTX is a valid memory displacement
9756 in PIC mode. */
9758 int
9760 {
9763 /* In 64bit mode we can allow direct addresses of symbols and labels
9764 when they are not dynamic symbols. */
9766 {
9770 {
9787 /* FALLTHRU */
9790 /* TLS references should always be enclosed in UNSPEC. */
9800 }
9801 }
9807 {
9808 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9809 of GOT tables. We should not need these anyway. */
9820 }
9824 {
9829 }
9838 {
9842 /* We need to check for both symbols and labels because VxWorks loads
9843 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9844 details. */
9848 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9849 While ABI specify also 32bit relocation but we don't produce it in
9850 small PIC model at all. */
9872 }
9875 }
9877 /* Recognizes RTL expressions that are valid memory addresses for an
9878 instruction. The MODE argument is the machine mode for the MEM
9879 expression that wants to use this address.
9881 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9882 convert common non-canonical forms to canonical form so that they will
9883 be recognized. */
9885 static bool
9888 {
9891 HOST_WIDE_INT scale;
9894 /* Decomposition failed. */
9902 /* Validate base register.
9904 Don't allow SUBREG's that span more than a word here. It can lead to spill
9905 failures when the base is one word out of a two word structure, which is
9906 represented internally as a DImode int. */
9909 {
9910 rtx reg;
9919 else
9920 /* Base is not a register. */
9924 /* Base is not in Pmode. */
9929 /* Base is not valid. */
9931 }
9933 /* Validate index register.
9935 Don't allow SUBREG's that span more than a word here -- same as above. */
9938 {
9939 rtx reg;
9948 else
9949 /* Index is not a register. */
9953 /* Index is not in Pmode. */
9958 /* Index is not valid. */
9960 }
9962 /* Validate scale factor. */
9964 {
9966 /* Scale without index. */
9970 /* Scale is not a valid multiplier. */
9972 }
9974 /* Validate displacement. */
9976 {
9981 {
9982 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9983 used. While ABI specify also 32bit relocations, we don't produce
9984 them at all and use IP relative instead. */
9991 /* 64bit address unspec. */
10006 /* Invalid address unspec. */
10008 }
10011 && (flag_pic
10012 || (TARGET_MACHO
10013 #if TARGET_MACHO
10014 && MACHOPIC_INDIRECT
10016 #endif
10017 )))
10018 {
10020 is_legitimate_pic:
10022 {
10023 /* foo@dtpoff(%rX) is ok. */
10030 /* Non-constant pic memory reference. */
10032 }
10034 /* Displacement is an invalid pic construct. */
10037 /* This code used to verify that a symbolic pic displacement
10038 includes the pic_offset_table_rtx register.
10040 While this is good idea, unfortunately these constructs may
10041 be created by "adds using lea" optimization for incorrect
10042 code like:
10044 int a;
10045 int foo(int i)
10046 {
10047 return *(&a+i);
10048 }
10050 This code is nonsensical, but results in addressing
10051 GOT table with pic_offset_table_rtx base. We can't
10052 just refuse it easily, since it gets matched by
10053 "addsi3" pattern, that later gets split to lea in the
10054 case output register differs from input. While this
10055 can be handled by separate addsi pattern for this case
10056 that never results in lea, this seems to be easier and
10057 correct fix for crash to disable this test. */
10058 }
10065 /* Displacement is not constant. */
10069 /* Displacement is out of range. */
10071 }
10073 /* Everything looks valid. */
10075 }
10077 /* Determine if a given RTX is a valid constant address. */
10079 bool
10081 {
10083 }
10084 \f
10085 /* Return a unique alias set for the GOT. */
10087 static alias_set_type
10089 {
10094 }
10096 /* Return a legitimate reference for ORIG (an address) using the
10097 register REG. If REG is 0, a new pseudo is generated.
10099 There are two types of references that must be handled:
10101 1. Global data references must load the address from the GOT, via
10102 the PIC reg. An insn is emitted to do this load, and the reg is
10103 returned.
10105 2. Static data references, constant pool addresses, and code labels
10106 compute the address as an offset from the GOT, whose base is in
10107 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
10108 differentiate them from global data objects. The returned
10109 address is the PIC reg + an unspec constant.
10111 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
10112 reg also appears in the address. */
10114 static rtx
10116 {
10119 rtx base;
10121 #if TARGET_MACHO
10123 {
10126 /* Use the generic Mach-O PIC machinery. */
10128 }
10129 #endif
10136 {
10137 rtx tmpreg;
10138 /* This symbol may be referenced via a displacement from the PIC
10139 base address (@GOTOFF). */
10146 {
10148 UNSPEC_GOTOFF);
10150 }
10151 else
10156 else
10161 {
10165 }
10167 }
10169 {
10170 /* This symbol may be referenced via a displacement from the PIC
10171 base address (@GOTOFF). */
10178 {
10180 UNSPEC_GOTOFF);
10182 }
10183 else
10189 {
10192 }
10193 }
10195 /* We can't use @GOTOFF for text labels on VxWorks;
10196 see gotoff_operand. */
10198 {
10200 {
10206 {
10209 }
10210 }
10213 {
10221 /* Use directly gen_movsi, otherwise the address is loaded
10222 into register for CSE. We don't want to CSE this addresses,
10223 instead we CSE addresses from the GOT table, so skip this. */
10226 }
10227 else
10228 {
10229 /* This symbol must be referenced via a load from the
10230 Global Offset Table (@GOT). */
10246 }
10247 }
10248 else
10249 {
10252 {
10254 {
10257 }
10258 else
10260 }
10262 {
10265 /* We must match stuff we generate before. Assume the only
10266 unspecs that can get here are ours. Not that we could do
10267 anything with them anyway.... */
10273 }
10275 {
10278 /* Check first to see if this is a constant offset from a @GOTOFF
10279 symbol reference. */
10282 {
10284 {
10288 UNSPEC_GOTOFF);
10294 {
10297 }
10298 }
10299 else
10300 {
10303 {
10307 }
10308 }
10309 }
10310 else
10311 {
10318 else
10319 {
10321 {
10324 }
10326 }
10327 }
10328 }
10329 }
10331 }
10332 \f
10333 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10335 static rtx
10337 {
10349 }
10351 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10352 false if we expect this to be used for a memory address and true if
10353 we expect to load the address into a register. */
10355 static rtx
10357 {
10362 {
10368 {
10378 }
10381 else
10385 {
10389 }
10397 {
10409 }
10412 else
10416 {
10421 }
10429 {
10433 }
10439 {
10442 }
10444 {
10449 }
10451 {
10455 }
10456 else
10457 {
10460 }
10470 {
10474 }
10475 else
10476 {
10480 }
10490 {
10493 }
10494 else
10495 {
10499 }
10504 }
10507 }
10509 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10510 to symbol DECL. */
10513 htab_t dllimport_map;
10515 static tree
10517 {
10524 tree to;
10525 rtx rtl;
10569 }
10571 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10572 true if we require the result be a register. */
10574 static rtx
10576 {
10577 tree imp_decl;
10578 rtx x;
10587 }
10589 /* Try machine-dependent ways of modifying an illegitimate address
10590 to be legitimate. If we find one, return the new, valid address.
10591 This macro is used in only one place: `memory_address' in explow.c.
10593 OLDX is the address as it was before break_out_memory_refs was called.
10594 In some cases it is useful to look at this to decide what needs to be done.
10596 It is always safe for this macro to do nothing. It exists to recognize
10597 opportunities to optimize the output.
10599 For the 80386, we handle X+REG by loading X into a register R and
10600 using R+REG. R will go in a general reg and indexing will be used.
10601 However, if REG is a broken-out memory address or multiplication,
10602 nothing needs to be done because REG can certainly go in a general reg.
10604 When -fpic is used, special handling is needed for symbolic references.
10605 See comments by legitimize_pic_address in i386.c for details. */
10607 static rtx
10610 {
10621 {
10625 }
10628 {
10635 {
10638 }
10639 }
10644 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10648 {
10653 }
10656 {
10657 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10662 {
10668 }
10673 {
10679 }
10681 /* Put multiply first if it isn't already. */
10683 {
10688 }
10690 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10691 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10692 created by virtual register instantiation, register elimination, and
10693 similar optimizations. */
10695 {
10701 }
10703 /* Canonicalize
10704 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10705 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10710 {
10711 rtx constant;
10715 {
10718 }
10720 {
10723 }
10724 else
10728 {
10734 }
10735 }
10741 {
10744 }
10747 {
10750 }
10758 {
10761 }
10767 {
10775 }
10778 {
10786 }
10787 }
10790 }
10791 \f
10792 /* Print an integer constant expression in assembler syntax. Addition
10793 and subtraction are the only arithmetic that may appear in these
10794 expressions. FILE is the stdio stream to write to, X is the rtx, and
10795 CODE is the operand print code from the output string. */
10797 static void
10799 {
10803 {
10812 else
10813 {
10816 /* Mark the decl as referenced so that cgraph will
10817 output the function. */
10821 #if TARGET_MACHO
10825 #endif
10827 }
10835 /* FALLTHRU */
10846 /* This used to output parentheses around the expression,
10847 but that does not work on the 386 (either ATT or BSD assembler). */
10853 {
10854 /* We can use %d if the number is <32 bits and positive. */
10859 else
10861 }
10862 else
10863 /* We can't handle floating point constants;
10864 PRINT_OPERAND must handle them. */
10869 /* Some assemblers need integer constants to appear first. */
10871 {
10875 }
10876 else
10877 {
10882 }
10899 {
10914 /* FIXME: This might be @TPOFF in Sun ld too. */
10923 else
10933 else
10939 #if TARGET_MACHO
10944 #endif
10948 }
10953 }
10954 }
10956 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10957 We need to emit DTP-relative relocations. */
10959 static void ATTRIBUTE_UNUSED
10961 {
10966 {
10974 }
10975 }
10977 /* Return true if X is a representation of the PIC register. This copes
10978 with calls from ix86_find_base_term, where the register might have
10979 been replaced by a cselib value. */
10981 static bool
10983 {
10987 else
10989 }
10991 /* In the name of slightly smaller debug output, and to cater to
10992 general assembler lossage, recognize PIC+GOTOFF and turn it back
10993 into a direct symbol reference.
10995 On Darwin, this is necessary to avoid a crash, because Darwin
10996 has a different PIC label for each routine but the DWARF debugging
10997 information is not associated with any particular routine, so it's
10998 necessary to remove references to the PIC label from RTL stored by
10999 the DWARF output code. */
11001 static rtx
11003 {
11005 /* addend is NULL or some rtx if x is something+GOTOFF where
11006 something doesn't include the PIC register. */
11008 /* reg_addend is NULL or a multiple of some register. */
11010 /* const_addend is NULL or a const_int. */
11012 /* This is the result, or NULL. */
11021 {
11028 }
11035 /* %ebx + GOT/GOTOFF */
11036 ;
11038 {
11039 /* %ebx + %reg * scale + GOT/GOTOFF */
11045 else
11046 {
11049 }
11050 }
11051 else
11057 {
11060 }
11079 {
11080 /* If the rest of original X doesn't involve the PIC register, add
11081 addend and subtract pic_offset_table_rtx. This can happen e.g.
11082 for code like:
11083 leal (%ebx, %ecx, 4), %ecx
11084 ...
11085 movl foo@GOTOFF(%ecx), %edx
11086 in which case we return (%ecx - %ebx) + foo. */
11089 pic_offset_table_rtx),
11090 result);
11091 else
11093 }
11095 }
11097 /* If X is a machine specific address (i.e. a symbol or label being
11098 referenced as a displacement from the GOT implemented using an
11099 UNSPEC), then return the base term. Otherwise return X. */
11101 rtx
11103 {
11104 rtx term;
11107 {
11120 }
11123 }
11124 \f
11125 static void
11128 {
11132 {
11135 }
11140 {
11143 {
11162 }
11166 {
11185 }
11192 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11193 Those same assemblers have the same but opposite lossage on cmov. */
11198 else
11203 {
11216 }
11224 {
11237 }
11240 /* ??? As above. */
11249 /* ??? As above. */
11254 else
11265 }
11267 }
11269 /* Print the name of register X to FILE based on its machine mode and number.
11270 If CODE is 'w', pretend the mode is HImode.
11271 If CODE is 'b', pretend the mode is QImode.
11272 If CODE is 'k', pretend the mode is SImode.
11273 If CODE is 'q', pretend the mode is DImode.
11274 If CODE is 'x', pretend the mode is V4SFmode.
11275 If CODE is 't', pretend the mode is V8SFmode.
11276 If CODE is 'h', pretend the reg is the 'high' byte register.
11277 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11278 If CODE is 'd', duplicate the operand for AVX instruction.
11279 */
11281 void
11283 {
11298 {
11302 }
11320 else
11323 /* Irritatingly, AMD extended registers use different naming convention
11324 from the normal registers. */
11326 {
11329 {
11348 }
11350 }
11354 {
11357 {
11360 }
11361 /* FALLTHRU */
11367 /* FALLTHRU */
11370 normal:
11385 {
11390 }
11394 }
11398 {
11401 else
11403 }
11404 }
11406 /* Locate some local-dynamic symbol still in use by this function
11407 so that we can print its name in some tls_local_dynamic_base
11408 pattern. */
11410 static int
11412 {
11417 {
11420 }
11423 }
11427 {
11428 rtx insn;
11439 }
11441 /* Meaning of CODE:
11442 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11443 C -- print opcode suffix for set/cmov insn.
11444 c -- like C, but print reversed condition
11445 F,f -- likewise, but for floating-point.
11446 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11447 otherwise nothing
11448 R -- print the prefix for register names.
11449 z -- print the opcode suffix for the size of the current operand.
11450 Z -- likewise, with special suffixes for x87 instructions.
11451 * -- print a star (in certain assembler syntax)
11452 A -- print an absolute memory reference.
11453 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11454 s -- print a shift double count, followed by the assemblers argument
11455 delimiter.
11456 b -- print the QImode name of the register for the indicated operand.
11457 %b0 would print %al if operands[0] is reg 0.
11458 w -- likewise, print the HImode name of the register.
11459 k -- likewise, print the SImode name of the register.
11460 q -- likewise, print the DImode name of the register.
11461 x -- likewise, print the V4SFmode name of the register.
11462 t -- likewise, print the V8SFmode name of the register.
11463 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11464 y -- print "st(0)" instead of "st" as a register.
11465 d -- print duplicated register operand for AVX instruction.
11466 D -- print condition for SSE cmp instruction.
11467 P -- if PIC, print an @PLT suffix.
11468 X -- don't print any sort of PIC '@' suffix for a symbol.
11469 & -- print some in-use local-dynamic symbol name.
11470 H -- print a memory address offset by 8; used for sse high-parts
11471 Y -- print condition for XOP pcom* instruction.
11472 + -- print a branch hint as 'cs' or 'ds' prefix
11473 ; -- print a semicolon (after prefixes due to bug in older gas).
11474 */
11476 void
11478 {
11480 {
11482 {
11489 {
11494 else
11497 }
11501 {
11507 /* Intel syntax. For absolute addresses, registers should not
11508 be surrounded by braces. */
11510 {
11515 }
11520 }
11558 {
11559 /* Opcodes don't get size suffixes if using Intel opcodes. */
11564 {
11582 output_operand_lossage
11585 }
11586 }
11589 warning
11591 /* FALLTHRU */
11594 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11599 {
11601 {
11603 #ifdef HAVE_AS_IX86_FILDS
11605 #endif
11613 #ifdef HAVE_AS_IX86_FILDQ
11615 #else
11617 #endif
11622 }
11623 }
11625 {
11626 /* 387 opcodes don't get size suffixes
11627 if the operands are registers. */
11632 {
11648 }
11649 }
11650 else
11651 {
11652 output_operand_lossage
11655 }
11657 output_operand_lossage
11676 {
11679 }
11683 /* Little bit of braindamage here. The SSE compare instructions
11684 does use completely different names for the comparisons that the
11685 fp conditional moves. */
11687 {
11689 {
11736 }
11737 }
11738 else
11739 {
11741 {
11776 }
11777 }
11780 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11782 {
11784 {
11791 }
11793 }
11794 #endif
11798 {
11800 "condition code, invalid operand code "
11803 }
11808 {
11810 "condition code, invalid operand code "
11813 }
11814 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11817 #endif
11821 /* Like above, but reverse condition */
11823 /* Check to see if argument to %c is really a constant
11824 and not a condition code which needs to be reversed. */
11826 {
11828 "condition code, invalid operand "
11831 }
11836 {
11838 "condition code, invalid operand "
11841 }
11842 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11845 #endif
11850 /* It doesn't actually matter what mode we use here, as we're
11851 only going to use this for printing. */
11856 {
11857 rtx x;
11865 {
11870 {
11874 /* Emit hints only in the case default branch prediction
11875 heuristics would fail. */
11877 {
11878 /* We use 3e (DS) prefix for taken branches and
11879 2e (CS) prefix for not taken branches. */
11882 else
11884 }
11885 }
11886 }
11888 }
11892 {
11943 }
11947 #if TARGET_MACHO
11949 #else
11951 #endif
11956 }
11957 }
11963 {
11964 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11967 {
11970 {
11979 else
11985 }
11987 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11997 }
12000 /* Avoid (%rip) for call operands. */
12006 else
12008 }
12011 {
12012 REAL_VALUE_TYPE r;
12021 }
12023 /* These float cases don't actually occur as immediate operands. */
12025 {
12030 }
12034 {
12039 }
12041 else
12042 {
12043 /* We have patterns that allow zero sets of memory, for instance.
12044 In 64-bit mode, we should probably support all 8-byte vectors,
12045 since we can in fact encode that into an immediate. */
12047 {
12050 }
12053 {
12055 {
12058 }
12061 {
12064 else
12066 }
12067 }
12072 else
12074 }
12075 }
12076 \f
12077 /* Print a memory operand whose address is ADDR. */
12079 void
12081 {
12095 {
12106 }
12108 /* Use one byte shorter RIP relative addressing for 64bit mode. */
12110 {
12122 }
12124 {
12125 /* Displacement only requires special attention. */
12128 {
12132 }
12135 else
12137 }
12138 else
12139 {
12141 {
12143 {
12148 else
12150 }
12156 {
12161 }
12163 }
12164 else
12165 {
12169 {
12170 /* Pull out the offset of a symbol; print any symbol itself. */
12174 {
12178 }
12186 else
12188 }
12192 {
12195 {
12199 }
12200 }
12203 else
12207 {
12212 }
12214 }
12215 }
12216 }
12218 bool
12220 {
12221 rtx op;
12228 {
12231 /* FIXME: This might be @TPOFF in Sun ld. */
12242 else
12254 else
12261 #if TARGET_MACHO
12267 #endif
12271 }
12274 }
12275 \f
12276 /* Split one or more DImode RTL references into pairs of SImode
12277 references. The RTL can be REG, offsettable MEM, integer constant, or
12278 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12279 split and "num" is its length. lo_half and hi_half are output arrays
12280 that parallel "operands". */
12282 void
12284 {
12286 {
12289 /* simplify_subreg refuse to split volatile memory addresses,
12290 but we still have to handle it. */
12292 {
12295 }
12296 else
12297 {
12304 }
12305 }
12306 }
12307 /* Split one or more TImode RTL references into pairs of DImode
12308 references. The RTL can be REG, offsettable MEM, integer constant, or
12309 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12310 split and "num" is its length. lo_half and hi_half are output arrays
12311 that parallel "operands". */
12313 void
12315 {
12317 {
12320 /* simplify_subreg refuse to split volatile memory addresses, but we
12321 still have to handle it. */
12323 {
12326 }
12327 else
12328 {
12331 }
12332 }
12333 }
12334 \f
12335 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12336 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12337 is the expression of the binary operation. The output may either be
12338 emitted here, or returned to the caller, like all output_* functions.
12340 There is no guarantee that the operands are the same mode, as they
12341 might be within FLOAT or FLOAT_EXTEND expressions. */
12343 #ifndef SYSV386_COMPAT
12344 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12345 wants to fix the assemblers because that causes incompatibility
12346 with gcc. No-one wants to fix gcc because that causes
12347 incompatibility with assemblers... You can use the option of
12348 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12349 #define SYSV386_COMPAT 1
12350 #endif
12354 {
12360 #ifdef ENABLE_CHECKING
12361 /* Even if we do not want to check the inputs, this documents input
12362 constraints. Which helps in understanding the following code. */
12372 else
12374 #endif
12377 {
12382 else
12391 else
12400 else
12409 else
12416 }
12419 {
12421 {
12425 else
12427 }
12428 else
12429 {
12433 else
12435 }
12437 }
12441 {
12445 {
12449 }
12451 /* know operands[0] == operands[1]. */
12454 {
12457 }
12460 {
12462 /* How is it that we are storing to a dead operand[2]?
12463 Well, presumably operands[1] is dead too. We can't
12464 store the result to st(0) as st(0) gets popped on this
12465 instruction. Instead store to operands[2] (which I
12466 think has to be st(1)). st(1) will be popped later.
12467 gcc <= 2.8.1 didn't have this check and generated
12468 assembly code that the Unixware assembler rejected. */
12470 else
12473 }
12477 else
12484 {
12487 }
12490 {
12493 }
12496 {
12497 #if SYSV386_COMPAT
12498 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12499 derived assemblers, confusingly reverse the direction of
12500 the operation for fsub{r} and fdiv{r} when the
12501 destination register is not st(0). The Intel assembler
12502 doesn't have this brain damage. Read !SYSV386_COMPAT to
12503 figure out what the hardware really does. */
12506 else
12508 #else
12510 /* As above for fmul/fadd, we can't store to st(0). */
12512 else
12514 #endif
12516 }
12519 {
12520 #if SYSV386_COMPAT
12523 else
12525 #else
12528 else
12530 #endif
12532 }
12535 {
12538 else
12541 }
12543 {
12544 #if SYSV386_COMPAT
12546 #else
12548 #endif
12549 }
12550 else
12551 {
12552 #if SYSV386_COMPAT
12554 #else
12556 #endif
12557 }
12562 }
12566 }
12568 /* Return needed mode for entity in optimize_mode_switching pass. */
12570 int
12572 {
12575 /* The mode UNINITIALIZED is used to store control word after a
12576 function call or ASM pattern. The mode ANY specify that function
12577 has no requirements on the control word and make no changes in the
12578 bits we are interested in. */
12592 {
12615 }
12618 }
12620 /* Output code to initialize control word copies used by trunc?f?i and
12621 rounding patterns. CURRENT_MODE is set to current control word,
12622 while NEW_MODE is set to new control word. */
12624 void
12626 {
12628 rtx new_mode;
12639 {
12641 {
12643 /* round toward zero (truncate) */
12649 /* round down toward -oo */
12656 /* round up toward +oo */
12663 /* mask precision exception for nearbyint() */
12670 }
12671 }
12672 else
12673 {
12675 {
12677 /* round toward zero (truncate) */
12683 /* round down toward -oo */
12689 /* round up toward +oo */
12695 /* mask precision exception for nearbyint() */
12702 }
12703 }
12709 }
12711 /* Output code for INSN to convert a float to a signed int. OPERANDS
12712 are the insn operands. The output may be [HSD]Imode and the input
12713 operand may be [SDX]Fmode. */
12717 {
12722 /* Jump through a hoop or two for DImode, since the hardware has no
12723 non-popping instruction. We used to do this a different way, but
12724 that was somewhat fragile and broke with post-reload splitters. */
12734 else
12735 {
12740 else
12744 }
12747 }
12749 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12750 have the values zero or one, indicates the ffreep insn's operand
12751 from the OPERANDS array. */
12755 {
12757 #ifdef HAVE_AS_IX86_FFREEP
12759 #else
12760 {
12770 }
12771 #endif
12774 }
12777 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12778 should be used. UNORDERED_P is true when fucom should be used. */
12782 {
12788 {
12791 }
12792 else
12793 {
12796 }
12799 {
12808 else
12810 else
12813 else
12815 }
12822 {
12824 {
12827 }
12828 else
12830 }
12833 && stack_top_dies
12836 {
12837 /* If both the top of the 387 stack dies, and the other operand
12838 is also a stack register that dies, then this must be a
12839 `fcompp' float compare */
12842 {
12843 /* There is no double popping fcomi variant. Fortunately,
12844 eflags is immune from the fstp's cc clobbering. */
12847 else
12850 }
12851 else
12852 {
12855 else
12857 }
12858 }
12859 else
12860 {
12861 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12864 {
12872 NULL,
12873 NULL,
12880 NULL,
12881 NULL,
12882 NULL,
12883 NULL
12884 };
12899 }
12900 }
12902 void
12904 {
12907 #ifdef ASM_QUAD
12910 #else
12912 #endif
12915 }
12917 void
12919 {
12922 #ifdef ASM_QUAD
12925 #else
12927 #endif
12928 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12934 #if TARGET_MACHO
12936 {
12940 }
12941 #endif
12942 else
12945 }
12946 \f
12947 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12948 for the target. */
12950 void
12952 {
12953 rtx tmp;
12955 /* We play register width games, which are only valid after reload. */
12958 /* Avoid HImode and its attendant prefix byte. */
12963 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12965 {
12968 }
12971 }
12973 /* X is an unchanging MEM. If it is a constant pool reference, return
12974 the constant pool rtx, else NULL. */
12976 rtx
12978 {
12985 }
12987 void
12989 {
12997 {
13000 {
13005 }
13009 }
13013 {
13026 {
13032 }
13033 }
13036 {
13038 {
13039 #if TARGET_MACHO
13041 {
13042 rtx temp = ((reload_in_progress
13049 }
13054 #endif
13055 }
13056 else
13057 {
13061 {
13066 }
13067 }
13068 }
13069 else
13070 {
13081 /* Force large constants in 64bit compilation into register
13082 to get them CSEed. */
13094 {
13095 /* If we are loading a floating point constant to a register,
13096 force the value to memory now, since we'll get better code
13097 out the back end. */
13101 {
13106 }
13107 }
13108 }
13111 }
13113 void
13115 {
13119 /* Force constants other than zero into memory. We do not know how
13120 the instructions used to build constants modify the upper 64 bits
13121 of the register, once we have that information we may be able
13122 to handle some of them more efficiently. */
13131 /* We need to check memory alignment for SSE mode since attribute
13132 can make operands unaligned. */
13137 {
13140 /* ix86_expand_vector_move_misalign() does not like constants ... */
13146 /* ... nor both arguments in memory. */
13154 }
13156 /* Make operand1 a register if it isn't already. */
13160 {
13163 }
13166 }
13168 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13169 straight to ix86_expand_vector_move. */
13170 /* Code generation for scalar reg-reg moves of single and double precision data:
13171 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13172 movaps reg, reg
13173 else
13174 movss reg, reg
13175 if (x86_sse_partial_reg_dependency == true)
13176 movapd reg, reg
13177 else
13178 movsd reg, reg
13180 Code generation for scalar loads of double precision data:
13181 if (x86_sse_split_regs == true)
13182 movlpd mem, reg (gas syntax)
13183 else
13184 movsd mem, reg
13186 Code generation for unaligned packed loads of single precision data
13187 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13188 if (x86_sse_unaligned_move_optimal)
13189 movups mem, reg
13191 if (x86_sse_partial_reg_dependency == true)
13192 {
13193 xorps reg, reg
13194 movlps mem, reg
13195 movhps mem+8, reg
13196 }
13197 else
13198 {
13199 movlps mem, reg
13200 movhps mem+8, reg
13201 }
13203 Code generation for unaligned packed loads of double precision data
13204 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13205 if (x86_sse_unaligned_move_optimal)
13206 movupd mem, reg
13208 if (x86_sse_split_regs == true)
13209 {
13210 movlpd mem, reg
13211 movhpd mem+8, reg
13212 }
13213 else
13214 {
13215 movsd mem, reg
13216 movhpd mem+8, reg
13217 }
13218 */
13220 void
13222 {
13229 {
13231 {
13235 {
13248 }
13255 {
13270 }
13275 }
13278 }
13281 {
13282 /* If we're optimizing for size, movups is the smallest. */
13284 {
13289 }
13291 /* ??? If we have typed data, then it would appear that using
13292 movdqu is the only way to get unaligned data loaded with
13293 integer type. */
13295 {
13300 }
13303 {
13304 rtx zero;
13307 {
13312 }
13314 /* When SSE registers are split into halves, we can avoid
13315 writing to the top half twice. */
13317 {
13320 }
13321 else
13322 {
13323 /* ??? Not sure about the best option for the Intel chips.
13324 The following would seem to satisfy; the register is
13325 entirely cleared, breaking the dependency chain. We
13326 then store to the upper half, with a dependency depth
13327 of one. A rumor has it that Intel recommends two movsd
13328 followed by an unpacklpd, but this is unconfirmed. And
13329 given that the dependency depth of the unpacklpd would
13330 still be one, I'm not sure why this would be better. */
13332 }
13338 }
13339 else
13340 {
13342 {
13347 }
13351 else
13360 }
13361 }
13363 {
13364 /* If we're optimizing for size, movups is the smallest. */
13366 {
13371 }
13373 /* ??? Similar to above, only less clear because of quote
13374 typeless stores unquote. */
13377 {
13382 }
13385 {
13390 }
13391 else
13392 {
13399 }
13400 }
13401 else
13403 }
13405 /* Expand a push in MODE. This is some mode for which we do not support
13406 proper push instructions, at least from the registers that we expect
13407 the value to live in. */
13409 void
13411 {
13412 rtx tmp;
13422 /* When we push an operand onto stack, it has to be aligned at least
13423 at the function argument boundary. However since we don't have
13424 the argument type, we can't determine the actual argument
13425 boundary. */
13427 }
13429 /* Helper function of ix86_fixup_binary_operands to canonicalize
13430 operand order. Returns true if the operands should be swapped. */
13432 static bool
13434 rtx operands[])
13435 {
13440 /* If the operation is not commutative, we can't do anything. */
13444 /* Highest priority is that src1 should match dst. */
13450 /* Next highest priority is that immediate constants come second. */
13456 /* Lowest priority is that memory references should come second. */
13463 }
13466 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13467 destination to use for the operation. If different from the true
13468 destination in operands[0], a copy operation will be required. */
13470 rtx
13472 rtx operands[])
13473 {
13478 /* Canonicalize operand order. */
13480 {
13481 rtx temp;
13483 /* It is invalid to swap operands of different modes. */
13489 }
13491 /* Both source operands cannot be in memory. */
13493 {
13494 /* Optimization: Only read from memory once. */
13496 {
13499 }
13500 else
13502 }
13504 /* If the destination is memory, and we do not have matching source
13505 operands, do things in registers. */
13509 /* Source 1 cannot be a constant. */
13513 /* Source 1 cannot be a non-matching memory. */
13520 }
13522 /* Similarly, but assume that the destination has already been
13523 set up properly. */
13525 void
13528 {
13531 }
13533 /* Attempt to expand a binary operator. Make the expansion closer to the
13534 actual machine, then just general_operand, which will allow 3 separate
13535 memory references (one output, two input) in a single insn. */
13537 void
13539 rtx operands[])
13540 {
13547 /* Emit the instruction. */
13551 {
13552 /* Reload doesn't know about the flags register, and doesn't know that
13553 it doesn't want to clobber it. We can only do this with PLUS. */
13556 }
13557 else
13558 {
13561 }
13563 /* Fix up the destination if needed. */
13566 }
13568 /* Return TRUE or FALSE depending on whether the binary operator meets the
13569 appropriate constraints. */
13571 int
13574 {
13579 /* Both source operands cannot be in memory. */
13583 /* Canonicalize operand order for commutative operators. */
13585 {
13589 }
13591 /* If the destination is memory, we must have a matching source operand. */
13595 /* Source 1 cannot be a constant. */
13599 /* Source 1 cannot be a non-matching memory. */
13604 }
13606 /* Attempt to expand a unary operator. Make the expansion closer to the
13607 actual machine, then just general_operand, which will allow 2 separate
13608 memory references (one output, one input) in a single insn. */
13610 void
13612 rtx operands[])
13613 {
13620 /* If the destination is memory, and we do not have matching source
13621 operands, do things in registers. */
13624 {
13627 else
13629 }
13631 /* When source operand is memory, destination must match. */
13635 /* Emit the instruction. */
13639 {
13640 /* Reload doesn't know about the flags register, and doesn't know that
13641 it doesn't want to clobber it. */
13644 }
13645 else
13646 {
13649 }
13651 /* Fix up the destination if needed. */
13654 }
13656 #define LEA_SEARCH_THRESHOLD 12
13658 /* Search backward for non-agu definition of register number REGNO1
13659 or register number REGNO2 in INSN's basic block until
13660 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13661 2. Reach BB boundary, or
13662 3. Reach agu definition.
13663 Returns the distance between the non-agu definition point and INSN.
13664 If no definition point, returns -1. */
13666 static int
13668 rtx insn)
13669 {
13676 {
13679 {
13681 {
13682 distance++;
13688 {
13692 }
13693 }
13697 }
13698 }
13701 {
13702 edge e;
13703 edge_iterator ei;
13708 {
13711 }
13714 {
13719 {
13721 {
13722 distance++;
13728 {
13732 }
13733 }
13735 }
13736 }
13737 }
13741 done:
13742 /* get_attr_type may modify recog data. We want to make sure
13743 that recog data is valid for instruction INSN, on which
13744 distance_non_agu_define is called. INSN is unchanged here. */
13747 }
13749 /* Return the distance between INSN and the next insn that uses
13750 register number REGNO0 in memory address. Return -1 if no such
13751 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13753 static int
13755 {
13762 {
13765 {
13767 {
13768 distance++;
13774 {
13775 /* Return DISTANCE if OP0 is used in memory
13776 address in NEXT. */
13778 }
13784 {
13785 /* Return -1 if OP0 is set in NEXT. */
13787 }
13788 }
13792 }
13793 }
13796 {
13797 edge e;
13798 edge_iterator ei;
13803 {
13806 }
13809 {
13814 {
13816 {
13817 distance++;
13823 {
13824 /* Return DISTANCE if OP0 is used in memory
13825 address in NEXT. */
13827 }
13833 {
13834 /* Return -1 if OP0 is set in NEXT. */
13836 }
13838 }
13840 }
13841 }
13842 }
13845 }
13847 /* Define this macro to tune LEA priority vs ADD, it take effect when
13848 there is a dilemma of choicing LEA or ADD
13849 Negative value: ADD is more preferred than LEA
13850 Zero: Netrual
13851 Positive value: LEA is more preferred than ADD*/
13852 #define IX86_LEA_PRIORITY 2
13854 /* Return true if it is ok to optimize an ADD operation to LEA
13855 operation to avoid flag register consumation. For the processors
13856 like ATOM, if the destination register of LEA holds an actual
13857 address which will be used soon, LEA is better and otherwise ADD
13858 is better. */
13860 bool
13863 {
13873 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13876 else
13877 {
13883 /* If this insn has both backward non-agu dependence and forward
13884 agu dependence, the one with short distance take effect. */
13891 }
13892 }
13894 /* Return true if destination reg of SET_BODY is shift count of
13895 USE_BODY. */
13897 static bool
13899 {
13900 rtx set_dest;
13901 rtx shift_rtx;
13904 /* Retrieve destination of SET_BODY. */
13906 {
13915 use_body))
13920 }
13922 /* Retrieve shift count of USE_BODY. */
13924 {
13936 }
13944 {
13947 /* Return true if shift count is dest of SET_BODY. */
13951 }
13954 }
13956 /* Return true if destination reg of SET_INSN is shift count of
13957 USE_INSN. */
13959 bool
13961 {
13964 }
13966 /* Return TRUE or FALSE depending on whether the unary operator meets the
13967 appropriate constraints. */
13969 int
13973 {
13974 /* If one of operands is memory, source and destination must match. */
13980 }
13982 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
13983 are ok, keeping in mind the possible movddup alternative. */
13985 bool
13987 {
13993 }
13995 /* Post-reload splitter for converting an SF or DFmode value in an
13996 SSE register into an unsigned SImode. */
13998 void
14000 {
14011 /* Load up the value into the low element. We must ensure that the other
14012 elements are valid floats -- zero is the easiest such value. */
14014 {
14017 else
14019 }
14020 else
14021 {
14026 else
14028 }
14048 else
14053 }
14055 /* Convert an unsigned DImode value into a DFmode, using only SSE.
14056 Expects the 64-bit DImode to be supplied in a pair of integral
14057 registers. Requires SSE2; will use SSE3 if available. For x86_32,
14058 -mfpmath=sse, !optimize_size only. */
14060 void
14062 {
14066 rtx x;
14072 {
14075 }
14076 else
14077 {
14081 }
14089 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
14092 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
14093 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
14094 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
14095 (0x1.0p84 + double(fp_value_hi_xmm)).
14096 Note these exponents differ by 32. */
14100 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
14101 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
14110 /* Add the upper and lower DFmode values together. */
14113 else
14114 {
14118 }
14121 }
14123 /* Not used, but eases macroization of patterns. */
14124 void
14126 rtx input ATTRIBUTE_UNUSED)
14127 {
14129 }
14131 /* Convert an unsigned SImode value into a DFmode. Only currently used
14132 for SSE, but applicable anywhere. */
14134 void
14136 {
14137 REAL_VALUE_TYPE TWO31r;
14152 }
14154 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14155 32-bit mode; otherwise we have a direct convert instruction. */
14157 void
14159 {
14160 REAL_VALUE_TYPE TWO32r;
14178 }
14180 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14181 For x86_32, -mfpmath=sse, !optimize_size only. */
14182 void
14184 {
14185 REAL_VALUE_TYPE ONE16r;
14204 }
14206 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14207 then replicate the value for all elements of the vector
14208 register. */
14210 rtx
14212 {
14213 rtvec v;
14215 {
14229 else
14237 else
14243 }
14244 }
14246 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14247 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14248 for an SSE register. If VECT is true, then replicate the mask for
14249 all elements of the vector register. If INVERT is true, then create
14250 a mask excluding the sign bit. */
14252 rtx
14254 {
14258 rtx v;
14259 rtx mask;
14261 /* Find the sign bit, sign extended to 2*HWI. */
14263 {
14277 else
14285 {
14288 }
14289 else
14290 {
14291 rtvec vec;
14297 {
14300 }
14301 else
14311 }
14316 }
14321 /* Force this value into the low part of a fp vector constant. */
14330 }
14332 /* Generate code for floating point ABS or NEG. */
14334 void
14336 rtx operands[])
14337 {
14344 {
14347 }
14353 /* NEG and ABS performed with SSE use bitwise mask operations.
14354 Create the appropriate mask now. */
14357 else
14364 {
14368 }
14369 else
14370 {
14374 {
14379 }
14380 else
14382 }
14383 }
14385 /* Expand a copysign operation. Special case operand 0 being a constant. */
14387 void
14389 {
14400 {
14407 {
14414 else
14415 {
14419 }
14420 }
14430 else
14434 }
14435 else
14436 {
14446 else
14450 }
14451 }
14453 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14454 be a constant, and so has already been expanded into a vector constant. */
14456 void
14458 {
14474 {
14477 }
14478 }
14480 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14481 so we have to do two masks. */
14483 void
14485 {
14500 {
14501 /* Shouldn't happen often (it's useless, obviously), but when it does
14502 we'd generate incorrect code if we continue below. */
14505 }
14508 {
14519 }
14520 else
14521 {
14523 {
14525 }
14527 {
14531 }
14535 {
14538 }
14540 {
14545 }
14547 }
14551 }
14553 /* Return TRUE or FALSE depending on whether the first SET in INSN
14554 has source and destination with matching CC modes, and that the
14555 CC mode is at least as constrained as REQ_MODE. */
14557 int
14559 {
14560 rtx set;
14571 {
14581 /* FALLTHRU */
14585 /* FALLTHRU */
14589 /* FALLTHRU */
14599 }
14602 }
14604 /* Generate insn patterns to do an integer compare of OPERANDS. */
14606 static rtx
14608 {
14615 /* This is very simple, but making the interface the same as in the
14616 FP case makes the rest of the code easier. */
14620 /* Return the test that should be put into the flags user, i.e.
14621 the bcc, scc, or cmov instruction. */
14623 }
14625 /* Figure out whether to use ordered or unordered fp comparisons.
14626 Return the appropriate mode to use. */
14628 enum machine_mode
14630 {
14631 /* ??? In order to make all comparisons reversible, we do all comparisons
14632 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14633 all forms trapping and nontrapping comparisons, we can make inequality
14634 comparisons trapping again, since it results in better code when using
14635 FCOM based compares. */
14637 }
14639 enum machine_mode
14641 {
14645 {
14648 }
14651 {
14652 /* Only zero flag is needed. */
14656 /* Codes needing carry flag. */
14659 /* Detect overflow checks. They need just the carry flag. */
14663 else
14667 /* Detect overflow checks. They need just the carry flag. */
14671 else
14673 /* Codes possibly doable only with sign flag when
14674 comparing against zero. */
14679 else
14680 /* For other cases Carry flag is not required. */
14682 /* Codes doable only with sign flag when comparing
14683 against zero, but we miss jump instruction for it
14684 so we need to use relational tests against overflow
14685 that thus needs to be zero. */
14690 else
14692 /* strcmp pattern do (use flags) and combine may ask us for proper
14693 mode. */
14698 }
14699 }
14701 /* Return the fixed registers used for condition codes. */
14703 static bool
14705 {
14709 }
14711 /* If two condition code modes are compatible, return a condition code
14712 mode which is compatible with both. Otherwise, return
14713 VOIDmode. */
14715 static enum machine_mode
14717 {
14729 {
14743 {
14757 }
14761 /* These are only compatible with themselves, which we already
14762 checked above. */
14764 }
14765 }
14768 /* Return a comparison we can do and that it is equivalent to
14769 swap_condition (code) apart possibly from orderedness.
14770 But, never change orderedness if TARGET_IEEE_FP, returning
14771 UNKNOWN in that case if necessary. */
14773 static enum rtx_code
14775 {
14777 {
14788 }
14789 }
14791 /* Return cost of comparison CODE using the best strategy for performance.
14792 All following functions do use number of instructions as a cost metrics.
14793 In future this should be tweaked to compute bytes for optimize_size and
14794 take into account performance of various instructions on various CPUs. */
14796 static int
14798 {
14801 /* The cost of code using bit-twiddling on %ah. */
14803 {
14826 }
14829 {
14836 }
14837 }
14839 /* Return strategy to use for floating-point. We assume that fcomi is always
14840 preferrable where available, since that is also true when looking at size
14841 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14843 enum ix86_fpcmp_strategy
14845 {
14846 /* Do fcomi/sahf based test when profitable. */
14855 }
14857 /* Swap, force into registers, or otherwise massage the two operands
14858 to a fp comparison. The operands are updated in place; the new
14859 comparison code is returned. */
14861 static enum rtx_code
14863 {
14869 /* All of the unordered compare instructions only work on registers.
14870 The same is true of the fcomi compare instructions. The XFmode
14871 compare instructions require registers except when comparing
14872 against zero or when converting operand 1 from fixed point to
14873 floating point. */
14882 {
14885 }
14886 else
14887 {
14888 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14889 things around if they appear profitable, otherwise force op0
14890 into a register. */
14896 {
14899 {
14900 rtx tmp;
14903 }
14904 }
14910 {
14915 {
14918 }
14919 else
14921 }
14922 }
14924 /* Try to rearrange the comparison to make it cheaper. */
14928 {
14929 rtx tmp;
14934 }
14939 }
14941 /* Convert comparison codes we use to represent FP comparison to integer
14942 code that will result in proper branch. Return UNKNOWN if no such code
14943 is available. */
14945 enum rtx_code
14947 {
14949 {
14972 }
14973 }
14975 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14977 static rtx
14979 {
14986 /* Do fcomi/sahf based test when profitable. */
14988 {
14993 tmp);
15001 tmp);
15010 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
15017 /* In the unordered case, we have to check C2 for NaN's, which
15018 doesn't happen to work out to anything nice combination-wise.
15019 So do some bit twiddling on the value we've got in AH to come
15020 up with an appropriate set of condition codes. */
15024 {
15028 {
15031 }
15032 else
15033 {
15039 }
15044 {
15049 }
15050 else
15051 {
15054 }
15059 {
15062 }
15063 else
15064 {
15068 }
15073 {
15079 }
15080 else
15081 {
15084 }
15089 {
15094 }
15095 else
15096 {
15099 }
15104 {
15109 }
15110 else
15111 {
15114 }
15128 }
15133 }
15135 /* Return the test that should be put into the flags user, i.e.
15136 the bcc, scc, or cmov instruction. */
15139 const0_rtx);
15140 }
15142 rtx
15144 {
15153 {
15156 }
15157 else
15161 }
15163 void
15165 {
15166 rtx tmp;
15169 {
15176 simple:
15180 pc_rtx);
15188 /* Expand DImode branch into multiple compare+branch. */
15189 {
15195 {
15200 }
15202 {
15206 }
15207 else
15208 {
15212 }
15214 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15215 avoid two branches. This costs one extra insn, so disable when
15216 optimizing for size. */
15221 {
15241 }
15243 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15244 op1 is a constant and the low word is zero, then we can just
15245 examine the high word. Similarly for low word -1 and
15246 less-or-equal-than or greater-than. */
15250 {
15253 {
15258 }
15262 {
15267 }
15271 }
15273 /* Otherwise, we need two or three jumps. */
15282 {
15296 }
15298 /*
15299 * a < b =>
15300 * if (hi(a) < hi(b)) goto true;
15301 * if (hi(a) > hi(b)) goto false;
15302 * if (lo(a) < lo(b)) goto true;
15303 * false:
15304 */
15321 }
15324 /* If we have already emitted a compare insn, go straight to simple.
15325 ix86_expand_compare won't emit anything if ix86_compare_emitted
15326 is non NULL. */
15329 }
15330 }
15332 /* Split branch based on floating point condition. */
15333 void
15336 {
15337 rtx condition;
15338 rtx i;
15341 {
15346 }
15349 tmp);
15351 /* Remove pushed operand from stack. */
15361 }
15363 void
15365 {
15366 rtx ret;
15373 }
15375 /* Expand comparison setting or clearing carry flag. Return true when
15376 successful and set pop for the operation. */
15377 static bool
15379 {
15383 /* Do not handle DImode compares that go through special path. */
15388 {
15393 /* Shortcut: following common codes never translate
15394 into carry flag compares. */
15399 /* These comparisons require zero flag; swap operands so they won't. */
15402 {
15407 }
15409 /* Try to expand the comparison and verify that we end up with
15410 carry flag based comparison. This fails to be true only when
15411 we decide to expand comparison using arithmetic that is not
15412 too common scenario. */
15421 else
15430 }
15436 {
15441 /* Convert a==0 into (unsigned)a<1. */
15450 /* Convert a>b into b<a or a>=b-1. */
15454 {
15456 /* Bail out on overflow. We still can swap operands but that
15457 would force loading of the constant into register. */
15462 }
15463 else
15464 {
15469 }
15472 /* Convert a>=0 into (unsigned)a<0x80000000. */
15490 }
15491 /* Swapping operands may cause constant to appear as first operand. */
15493 {
15497 }
15503 }
15505 int
15507 {
15526 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15527 HImode insns, we'd be swallowed in word prefix ops. */
15533 {
15537 HOST_WIDE_INT diff;
15540 /* Sign bit compares are better done using shifts than we do by using
15541 sbb. */
15545 {
15546 /* Detect overlap between destination and compare sources. */
15550 {
15551 rtx flags;
15560 {
15562 compare_code
15564 }
15566 /* To simplify rest of code, restrict to the GEU case. */
15568 {
15574 }
15575 else
15576 {
15579 reverse_condition_maybe_unordered
15581 else
15584 }
15593 else
15596 }
15597 else
15598 {
15601 else
15602 {
15607 }
15610 }
15613 {
15614 /*
15615 * cmpl op0,op1
15616 * sbbl dest,dest
15617 * [addl dest, ct]
15618 *
15619 * Size 5 - 8.
15620 */
15625 }
15627 {
15628 /*
15629 * cmpl op0,op1
15630 * sbbl dest,dest
15631 * orl $ct, dest
15632 *
15633 * Size 8.
15634 */
15638 }
15640 {
15641 /*
15642 * cmpl op0,op1
15643 * sbbl dest,dest
15644 * notl dest
15645 * [addl dest, cf]
15646 *
15647 * Size 8 - 11.
15648 */
15654 }
15655 else
15656 {
15657 /*
15658 * cmpl op0,op1
15659 * sbbl dest,dest
15660 * [notl dest]
15661 * andl cf - ct, dest
15662 * [addl dest, ct]
15663 *
15664 * Size 8 - 11.
15665 */
15668 {
15672 }
15682 }
15688 }
15691 {
15694 HOST_WIDE_INT tmp;
15699 {
15702 /* We may be reversing unordered compare to normal compare, that
15703 is not valid in general (we may convert non-trapping condition
15704 to trapping one), however on i386 we currently emit all
15705 comparisons unordered. */
15708 }
15709 else
15710 {
15713 }
15714 }
15719 {
15724 {
15729 }
15730 }
15732 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15736 {
15737 /* If lea code below could be used, only optimize
15738 if it results in a 2 insn sequence. */
15744 {
15745 /*
15746 * notl op1 (if necessary)
15747 * sarl $31, op1
15748 * orl cf, op1
15749 */
15751 {
15755 }
15767 }
15768 }
15776 {
15777 /*
15778 * xorl dest,dest
15779 * cmpl op1,op2
15780 * setcc dest
15781 * lea cf(dest*(ct-cf)),dest
15782 *
15783 * Size 14.
15784 *
15785 * This also catches the degenerate setcc-only case.
15786 */
15788 rtx tmp;
15795 /* On x86_64 the lea instruction operates on Pmode, so we need
15796 to get arithmetics done in proper mode to match. */
15799 else
15800 {
15801 rtx out1;
15804 nops++;
15806 {
15808 nops++;
15809 }
15810 }
15812 {
15814 nops++;
15815 }
15817 {
15820 else
15822 }
15827 }
15829 /*
15830 * General case: Jumpful:
15831 * xorl dest,dest cmpl op1, op2
15832 * cmpl op1, op2 movl ct, dest
15833 * setcc dest jcc 1f
15834 * decl dest movl cf, dest
15835 * andl (cf-ct),dest 1:
15836 * addl ct,dest
15837 *
15838 * Size 20. Size 14.
15839 *
15840 * This is reasonably steep, but branch mispredict costs are
15841 * high on modern cpus, so consider failing only if optimizing
15842 * for space.
15843 */
15848 {
15850 {
15857 {
15860 /* We may be reversing unordered compare to normal compare,
15861 that is not valid in general (we may convert non-trapping
15862 condition to trapping one), however on i386 we currently
15863 emit all comparisons unordered. */
15865 }
15866 else
15867 {
15871 }
15872 }
15875 {
15876 /* notl op1 (if needed)
15877 sarl $31, op1
15878 andl (cf-ct), op1
15879 addl ct, op1
15881 For x < 0 (resp. x <= -1) there will be no notl,
15882 so if possible swap the constants to get rid of the
15883 complement.
15884 True/false will be -1/0 while code below (store flag
15885 followed by decrement) is 0/-1, so the constants need
15886 to be exchanged once more. */
15889 {
15892 }
15893 else
15894 {
15898 }
15902 }
15903 else
15904 {
15910 }
15922 }
15923 }
15926 {
15927 /* Try a few things more with specific constants and a variable. */
15929 optab op;
15935 /* If one of the two operands is an interesting constant, load a
15936 constant with the above and mask it in with a logical operation. */
15939 {
15945 else
15947 }
15949 {
15955 else
15957 }
15958 else
15965 /* Recurse to get the constant loaded. */
15969 /* Mask in the interesting variable. */
15971 OPTAB_WIDEN);
15976 }
15978 /*
15979 * For comparison with above,
15980 *
15981 * movl cf,dest
15982 * movl ct,tmp
15983 * cmpl op1,op2
15984 * cmovcc tmp,dest
15985 *
15986 * Size 15.
15987 */
16010 }
16012 /* Swap, force into registers, or otherwise massage the two operands
16013 to an sse comparison with a mask result. Thus we differ a bit from
16014 ix86_prepare_fp_compare_args which expects to produce a flags result.
16016 The DEST operand exists to help determine whether to commute commutative
16017 operators. The POP0/POP1 operands are updated in place. The new
16018 comparison code is returned, or UNKNOWN if not implementable. */
16020 static enum rtx_code
16023 {
16024 rtx tmp;
16027 {
16030 /* We have no LTGT as an operator. We could implement it with
16031 NE & ORDERED, but this requires an extra temporary. It's
16032 not clear that it's worth it. */
16039 /* These are supported directly. */
16046 /* For commutative operators, try to canonicalize the destination
16047 operand to be first in the comparison - this helps reload to
16048 avoid extra moves. */
16051 /* FALLTHRU */
16057 /* These are not supported directly. Swap the comparison operands
16058 to transform into something that is supported. */
16067 }
16070 }
16072 /* Detect conditional moves that exactly match min/max operational
16073 semantics. Note that this is IEEE safe, as long as we don't
16074 interchange the operands.
16076 Returns FALSE if this conditional move doesn't match a MIN/MAX,
16077 and TRUE if the operation is successful and instructions are emitted. */
16079 static bool
16082 {
16085 rtx tmp;
16088 ;
16090 {
16094 }
16095 else
16102 else
16107 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
16108 but MODE may be a vector mode and thus not appropriate. */
16110 {
16112 rtvec v;
16117 }
16118 else
16119 {
16122 }
16126 }
16128 /* Expand an sse vector comparison. Return the register with the result. */
16130 static rtx
16133 {
16135 rtx x;
16150 }
16152 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16153 operations. This is used for both scalar and vector conditional moves. */
16155 static void
16157 {
16162 {
16166 }
16168 {
16173 }
16175 {
16178 op_true,
16179 op_false));
16181 }
16182 else
16183 {
16190 else
16202 }
16203 }
16205 /* Expand a floating-point conditional move. Return true if successful. */
16207 int
16209 {
16217 {
16220 /* Since we've no cmove for sse registers, don't force bad register
16221 allocation just to gain access to it. Deny movcc when the
16222 comparison mode doesn't match the move mode. */
16244 }
16246 /* The floating point conditional move instructions don't directly
16247 support conditions resulting from a signed integer comparison. */
16251 {
16258 }
16265 }
16267 /* Expand a floating-point vector conditional move; a vcond operation
16268 rather than a movcc operation. */
16270 bool
16272 {
16274 rtx cmp;
16289 }
16291 /* Expand a signed/unsigned integral vector conditional move. */
16293 bool
16295 {
16304 /* XOP supports all of the comparisons on all vector int types. */
16306 {
16307 /* Canonicalize the comparison to EQ, GT, GTU. */
16309 {
16326 /* FALLTHRU */
16336 }
16338 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16340 {
16342 {
16344 /* SSE4.1 supports EQ. */
16351 /* SSE4.2 supports GT/GTU. */
16358 }
16359 }
16361 /* Unsigned parallel compare is not supported by the hardware.
16362 Play some tricks to turn this into a signed comparison
16363 against 0. */
16365 {
16369 {
16372 {
16376 /* Subtract (-(INT MAX) - 1) from both operands to make
16377 them signed. */
16391 }
16396 /* Perform a parallel unsigned saturating subtraction. */
16409 }
16410 }
16411 }
16419 }
16421 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16422 true if we should do zero extension, else sign extension. HIGH_P is
16423 true if we want the N/2 high elements, else the low elements. */
16425 void
16427 {
16433 {
16437 else
16443 else
16449 else
16454 }
16460 else
16465 }
16467 /* This function performs the same task as ix86_expand_sse_unpack,
16468 but with SSE4.1 instructions. */
16470 void
16472 {
16478 {
16482 else
16488 else
16494 else
16499 }
16503 {
16504 /* Shift higher 8 bytes to lower 8 bytes. */
16509 }
16510 else
16514 }
16516 /* Expand conditional increment or decrement using adb/sbb instructions.
16517 The default case using setcc followed by the conditional move can be
16518 done by generic code. */
16519 int
16521 {
16523 rtx flags;
16525 rtx compare_op;
16544 {
16547 }
16550 {
16554 reverse_condition_maybe_unordered
16556 else
16558 }
16562 /* Construct either adc or sbb insn. */
16564 {
16566 {
16581 }
16582 }
16583 else
16584 {
16586 {
16601 }
16602 }
16606 }
16609 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16610 works for floating pointer parameters and nonoffsetable memories.
16611 For pushes, it returns just stack offsets; the values will be saved
16612 in the right order. Maximally three parts are generated. */
16614 static int
16616 {
16621 else
16627 /* Optimize constant pool reference to immediates. This is used by fp
16628 moves, that force all constants to memory to allow combining. */
16630 {
16634 }
16637 {
16638 /* The only non-offsetable memories we handle are pushes. */
16647 }
16650 {
16652 /* Caution: if we looked through a constant pool memory above,
16653 the operand may actually have a different mode now. That's
16654 ok, since we want to pun this all the way back to an integer. */
16658 }
16661 {
16664 else
16665 {
16669 {
16673 }
16675 {
16680 }
16682 {
16683 REAL_VALUE_TYPE r;
16688 {
16703 }
16706 }
16707 else
16709 }
16710 }
16711 else
16712 {
16716 {
16719 {
16723 }
16725 {
16729 }
16731 {
16732 REAL_VALUE_TYPE r;
16738 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16741 = gen_int_mode
16744 DImode);
16745 else
16752 = gen_int_mode
16755 DImode);
16756 else
16758 }
16759 else
16761 }
16762 }
16765 }
16767 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16768 Return false when normal moves are needed; true when all required
16769 insns have been emitted. Operands 2-4 contain the input values
16770 int the correct order; operands 5-7 contain the output values. */
16772 void
16774 {
16782 /* The DFmode expanders may ask us to move double.
16783 For 64bit target this is single move. By hiding the fact
16784 here we simplify i386.md splitters. */
16786 {
16787 /* Optimize constant pool reference to immediates. This is used by
16788 fp moves, that force all constants to memory to allow combining. */
16795 {
16798 }
16799 else
16804 }
16806 /* The only non-offsettable memory we handle is push. */
16809 else
16816 /* When emitting push, take care for source operands on the stack. */
16819 {
16822 /* Compensate for the stack decrement by 4. */
16827 /* src_base refers to the stack pointer and is
16828 automatically decreased by emitted push. */
16832 }
16834 /* We need to do copy in the right order in case an address register
16835 of the source overlaps the destination. */
16837 {
16838 rtx tmp;
16841 {
16845 collisions++;
16846 }
16848 /* Collision in the middle part can be handled by reordering. */
16850 {
16853 }
16857 {
16859 {
16862 }
16863 else
16864 {
16867 }
16868 }
16870 /* If there are more collisions, we can't handle it by reordering.
16871 Do an lea to the last part and use only one colliding move. */
16873 {
16874 rtx base;
16880 /* Handle the case when the last part isn't valid for lea.
16881 Happens in 64-bit mode storing the 12-byte XFmode. */
16888 {
16891 }
16892 }
16893 }
16896 {
16898 {
16900 {
16905 }
16907 {
16910 }
16911 }
16912 else
16913 {
16914 /* In 64bit mode we don't have 32bit push available. In case this is
16915 register, it is OK - we will just use larger counterpart. We also
16916 retype memory - these comes from attempt to avoid REX prefix on
16917 moving of second half of TFmode value. */
16919 {
16921 {
16932 }
16936 }
16937 }
16941 }
16943 /* Choose correct order to not overwrite the source before it is copied. */
16953 {
16955 {
16958 }
16959 }
16960 else
16961 {
16963 {
16966 }
16967 }
16969 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16971 {
16980 }
16986 }
16988 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16989 left shift by a constant, either using a single shift or
16990 a sequence of add instructions. */
16992 static void
16994 {
16996 {
16998 ? gen_addsi3
17000 }
17003 {
17006 {
17008 ? gen_addsi3
17010 }
17011 }
17012 else
17014 ? gen_ashlsi3
17016 }
17018 void
17020 {
17026 {
17031 {
17037 }
17038 else
17039 {
17043 ? gen_x86_shld
17046 }
17048 }
17053 {
17054 /* Assuming we've chosen a QImode capable registers, then 1 << N
17055 can be done with two 32/64-bit shifts, no branches, no cmoves. */
17057 {
17073 }
17075 /* Otherwise, we can get the same results by manually performing
17076 a bit extract operation on bit 5/6, and then performing the two
17077 shifts. The two methods of getting 0/1 into low/high are exactly
17078 the same size. Avoiding the shift in the bit extract case helps
17079 pentium4 a bit; no one else seems to care much either way. */
17080 else
17081 {
17082 rtx x;
17086 else
17091 ? gen_lshrsi3
17095 ? gen_andsi3
17099 ? gen_xorsi3
17101 }
17104 ? gen_ashlsi3
17107 ? gen_ashlsi3
17110 }
17113 {
17114 /* For -1 << N, we can avoid the shld instruction, because we
17115 know that we're shifting 0...31/63 ones into a -1. */
17119 else
17121 }
17122 else
17123 {
17129 ? gen_x86_shld
17131 }
17134 ? gen_ashlsi3
17138 {
17141 ? gen_x86_shiftsi_adj_1
17143 scratch));
17144 }
17145 else
17147 ? gen_x86_shiftsi_adj_2
17149 }
17151 void
17153 {
17159 {
17164 {
17167 ? gen_ashrsi3
17172 }
17174 {
17178 ? gen_ashrsi3
17183 ? gen_ashrsi3
17186 }
17187 else
17188 {
17192 ? gen_x86_shrd
17195 ? gen_ashrsi3
17197 }
17198 }
17199 else
17200 {
17207 ? gen_x86_shrd
17210 ? gen_ashrsi3
17214 {
17217 ? gen_ashrsi3
17221 ? gen_x86_shiftsi_adj_1
17223 scratch));
17224 }
17225 else
17227 ? gen_x86_shiftsi_adj_3
17229 }
17230 }
17232 void
17234 {
17240 {
17245 {
17251 ? gen_lshrsi3
17254 }
17255 else
17256 {
17260 ? gen_x86_shrd
17263 ? gen_lshrsi3
17265 }
17266 }
17267 else
17268 {
17275 ? gen_x86_shrd
17278 ? gen_lshrsi3
17281 /* Heh. By reversing the arguments, we can reuse this pattern. */
17283 {
17286 ? gen_x86_shiftsi_adj_1
17288 scratch));
17289 }
17290 else
17292 ? gen_x86_shiftsi_adj_2
17294 }
17295 }
17297 /* Predict just emitted jump instruction to be taken with probability PROB. */
17298 static void
17300 {
17304 }
17306 /* Helper function for the string operations below. Dest VARIABLE whether
17307 it is aligned to VALUE bytes. If true, jump to the label. */
17308 static rtx
17310 {
17315 else
17321 else
17324 }
17326 /* Adjust COUNTER by the VALUE. */
17327 static void
17329 {
17332 else
17334 }
17336 /* Zero extend possibly SImode EXP to Pmode register. */
17337 rtx
17339 {
17340 rtx r;
17348 }
17350 /* Divide COUNTREG by SCALE. */
17351 static rtx
17353 {
17354 rtx sc;
17366 }
17368 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17369 DImode for constant loop counts. */
17371 static enum machine_mode
17373 {
17381 }
17383 /* When SRCPTR is non-NULL, output simple loop to move memory
17384 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17385 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17386 equivalent loop to set memory by VALUE (supposed to be in MODE).
17388 The size is rounded down to whole number of chunk size moved at once.
17389 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17392 static void
17397 {
17402 rtx size;
17403 rtx x_addr;
17404 rtx y_addr;
17413 /* Those two should combine. */
17415 {
17419 }
17429 {
17433 /* When unrolling for chips that reorder memory reads and writes,
17434 we can save registers by using single temporary.
17435 Also using 4 temporaries is overkill in 32bit mode. */
17437 {
17439 {
17441 {
17442 destmem =
17444 srcmem =
17446 }
17448 }
17449 }
17450 else
17451 {
17455 {
17458 {
17459 srcmem =
17461 }
17463 }
17465 {
17467 {
17468 destmem =
17470 }
17472 }
17473 }
17474 }
17475 else
17477 {
17479 destmem =
17482 }
17492 {
17498 else
17500 }
17501 else
17509 {
17514 }
17516 }
17518 /* Output "rep; mov" instruction.
17519 Arguments have same meaning as for previous function */
17520 static void
17523 rtx count,
17525 {
17526 rtx destexp;
17527 rtx srcexp;
17528 rtx countreg;
17530 /* If the size is known, it is shorter to use rep movs. */
17541 {
17548 }
17549 else
17550 {
17553 }
17555 {
17562 }
17563 else
17564 {
17569 }
17572 }
17574 /* Output "rep; stos" instruction.
17575 Arguments have same meaning as for previous function */
17576 static void
17579 rtx orig_value)
17580 {
17581 rtx destexp;
17582 rtx countreg;
17589 {
17593 }
17594 else
17597 {
17602 }
17606 }
17608 static void
17611 {
17615 }
17617 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17618 static void
17621 {
17624 {
17629 {
17631 {
17634 }
17635 else
17638 }
17640 {
17643 else
17644 {
17647 }
17649 }
17651 {
17654 }
17656 {
17659 }
17661 {
17664 }
17666 }
17668 {
17674 }
17676 /* When there are stringops, we can cheaply increase dest and src pointers.
17677 Otherwise we save code size by maintaining offset (zero is readily
17678 available from preceding rep operation) and using x86 addressing modes.
17679 */
17681 {
17683 {
17690 }
17692 {
17699 }
17701 {
17708 }
17709 }
17710 else
17711 {
17713 rtx tmp;
17716 {
17727 }
17729 {
17742 }
17744 {
17753 }
17754 }
17755 }
17757 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17758 static void
17761 {
17762 count =
17768 }
17770 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17771 static void
17773 {
17774 rtx dest;
17777 {
17782 {
17784 {
17789 }
17790 else
17793 }
17795 {
17797 {
17800 }
17801 else
17802 {
17807 }
17809 }
17811 {
17815 }
17817 {
17821 }
17823 {
17827 }
17829 }
17831 {
17834 }
17836 {
17839 {
17843 }
17844 else
17845 {
17851 }
17854 }
17856 {
17859 {
17862 }
17863 else
17864 {
17868 }
17871 }
17873 {
17879 }
17881 {
17887 }
17889 {
17895 }
17896 }
17898 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17899 DESIRED_ALIGNMENT. */
17900 static void
17904 {
17906 {
17914 }
17916 {
17924 }
17926 {
17934 }
17936 }
17938 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17939 ALIGN_BYTES is how many bytes need to be copied. */
17940 static rtx
17943 {
17953 {
17958 }
17960 {
17971 }
17973 {
17979 {
17987 }
17990 }
17996 {
18008 }
18015 }
18017 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
18018 DESIRED_ALIGNMENT. */
18019 static void
18022 {
18024 {
18031 }
18033 {
18040 }
18042 {
18049 }
18051 }
18053 /* Set enough from DST to align DST known to by aligned by ALIGN to
18054 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
18055 static rtx
18058 {
18062 {
18067 }
18069 {
18076 }
18078 {
18085 }
18092 }
18094 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
18095 static enum stringop_alg
18098 {
18101 /* Algorithms using the rep prefix want at least edi and ecx;
18102 additionally, memset wants eax and memcpy wants esi. Don't
18103 consider such algorithms if the user has appropriated those
18104 registers for their own purposes. */
18106 || (memset
18109 #define ALG_USABLE_P(alg) (rep_prefix_usable \
18110 || (alg != rep_prefix_1_byte \
18111 && alg != rep_prefix_4_byte \
18112 && alg != rep_prefix_8_byte))
18115 /* Even if the string operation call is cold, we still might spend a lot
18116 of time processing large blocks. */
18121 else
18129 else
18133 /* rep; movq or rep; movl is the smallest variant. */
18135 {
18138 else
18140 }
18141 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
18142 */
18146 {
18150 {
18151 /* We get here if the algorithms that were not libcall-based
18152 were rep-prefix based and we are unable to use rep prefixes
18153 based on global register usage. Break out of the loop and
18154 use the heuristic below. */
18158 {
18163 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18164 last non-libcall inline algorithm. */
18166 {
18167 /* When the current size is best to be copied by a libcall,
18168 but we are still forced to inline, run the heuristic below
18169 that will pick code for medium sized blocks. */
18173 }
18176 }
18177 }
18179 }
18180 /* When asked to inline the call anyway, try to pick meaningful choice.
18181 We look for maximal size of block that is faster to copy by hand and
18182 take blocks of at most of that size guessing that average size will
18183 be roughly half of the block.
18185 If this turns out to be bad, we might simply specify the preferred
18186 choice in ix86_costs. */
18189 {
18196 {
18203 }
18204 /* If there aren't any usable algorithms, then recursing on
18205 smaller sizes isn't going to find anything. Just return the
18206 simple byte-at-a-time copy loop. */
18208 {
18209 /* Pick something reasonable. */
18213 }
18222 }
18224 #undef ALG_USABLE_P
18225 }
18227 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18228 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18229 static int
18233 {
18236 {
18247 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18248 copying whole cacheline at once. */
18251 else
18255 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18256 copying whole cacheline at once. */
18259 else
18267 }
18276 }
18278 /* Return the smallest power of 2 greater than VAL. */
18279 static int
18281 {
18286 }
18288 /* Expand string move (memcpy) operation. Use i386 string operations when
18289 profitable. expand_setmem contains similar code. The code depends upon
18290 architecture, block size and alignment, but always has the same
18291 overall structure:
18293 1) Prologue guard: Conditional that jumps up to epilogues for small
18294 blocks that can be handled by epilogue alone. This is faster but
18295 also needed for correctness, since prologue assume the block is larger
18296 than the desired alignment.
18298 Optional dynamic check for size and libcall for large
18299 blocks is emitted here too, with -minline-stringops-dynamically.
18301 2) Prologue: copy first few bytes in order to get destination aligned
18302 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18303 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18304 We emit either a jump tree on power of two sized blocks, or a byte loop.
18306 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18307 with specified algorithm.
18309 4) Epilogue: code copying tail of the block that is too small to be
18310 handled by main body (or up to size guarded by prologue guard). */
18312 int
18315 {
18316 rtx destreg;
18317 rtx srcreg;
18319 rtx tmp;
18332 /* i386 can do misaligned access on reasonably increased cost. */
18336 /* ALIGN is the minimum of destination and source alignment, but we care here
18337 just about destination alignment. */
18346 /* Make sure we don't need to care about overflow later on. */
18350 /* Step 0: Decide on preferred algorithm, desired alignment and
18351 size of chunks to be copied by main loop. */
18367 {
18392 }
18396 /* Step 1: Prologue guard. */
18398 /* Alignment code needs count to be in register. */
18400 {
18403 {
18404 align_bytes
18408 else
18410 }
18413 }
18416 /* Ensure that alignment prologue won't copy past end of block. */
18418 {
18420 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18421 Make sure it is power of 2. */
18425 {
18427 {
18428 /* If main algorithm works on QImode, no epilogue is needed.
18429 For small sizes just don't align anything. */
18432 else
18434 }
18435 }
18436 else
18437 {
18444 else
18446 }
18447 }
18449 /* Emit code to decide on runtime whether library call or inline should be
18450 used. */
18452 {
18454 {
18456 {
18460 }
18461 }
18462 else
18463 {
18472 }
18473 }
18475 /* Step 2: Alignment prologue. */
18478 {
18480 {
18481 /* Except for the first move in epilogue, we no longer know
18482 constant offset in aliasing info. It don't seems to worth
18483 the pain to maintain it for the first move, so throw away
18484 the info early. */
18488 desired_align);
18489 }
18490 else
18491 {
18492 /* If we know how many bytes need to be stored before dst is
18493 sufficiently aligned, maintain aliasing info accurately. */
18498 }
18504 {
18505 /* It is possible that we copied enough so the main loop will not
18506 execute. */
18516 else
18518 }
18519 }
18521 {
18526 }
18530 /* Step 3: Main loop. */
18533 {
18546 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18547 registers for 4 temporaries anyway. */
18550 expected_size);
18554 DImode);
18558 SImode);
18562 QImode);
18564 }
18565 /* Adjust properly the offset of src and dest memory for aliasing. */
18567 {
18572 }
18573 else
18574 {
18577 }
18579 /* Step 4: Epilogue to copy the remaining bytes. */
18580 epilogue:
18582 {
18583 /* When the main loop is done, COUNT_EXP might hold original count,
18584 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18585 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18586 bytes. Compensate if needed. */
18589 {
18590 tmp =
18593 OPTAB_DIRECT);
18596 }
18599 }
18603 epilogue_size_needed);
18607 }
18609 /* Helper function for memcpy. For QImode value 0xXY produce
18610 0xXYXYXYXY of wide specified by MODE. This is essentially
18611 a * 0x10101010, but we can do slightly better than
18612 synth_mult by unwinding the sequence by hand on CPUs with
18613 slow multiply. */
18614 static rtx
18616 {
18618 rtx tmp;
18625 {
18633 }
18642 nops--;
18647 {
18651 OPTAB_DIRECT);
18652 }
18653 else
18654 {
18660 else
18662 else
18663 {
18666 reg =
18668 }
18678 }
18679 }
18681 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18682 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18683 alignment from ALIGN to DESIRED_ALIGN. */
18684 static rtx
18686 {
18687 rtx promoted_val;
18696 else
18700 }
18702 /* Expand string clear operation (bzero). Use i386 string operations when
18703 profitable. See expand_movmem comment for explanation of individual
18704 steps performed. */
18705 int
18708 {
18709 rtx destreg;
18711 rtx tmp;
18726 /* i386 can do misaligned access on reasonably increased cost. */
18735 /* Make sure we don't need to care about overflow later on. */
18739 /* Step 0: Decide on preferred algorithm, desired alignment and
18740 size of chunks to be copied by main loop. */
18755 {
18780 }
18783 /* Step 1: Prologue guard. */
18785 /* Alignment code needs count to be in register. */
18787 {
18790 {
18791 align_bytes
18795 else
18797 }
18799 {
18804 }
18805 }
18806 /* Do the cheap promotion to allow better CSE across the
18807 main loop and epilogue (ie one load of the big constant in the
18808 front of all code. */
18812 /* Ensure that alignment prologue won't copy past end of block. */
18814 {
18816 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18817 Make sure it is power of 2. */
18820 /* To improve performance of small blocks, we jump around the VAL
18821 promoting mode. This mean that if the promoted VAL is not constant,
18822 we might not use it in the epilogue and have to use byte
18823 loop variant. */
18827 {
18829 {
18830 /* If main algorithm works on QImode, no epilogue is needed.
18831 For small sizes just don't align anything. */
18834 else
18836 }
18837 }
18838 else
18839 {
18846 else
18848 }
18849 }
18851 {
18860 }
18862 /* Step 2: Alignment prologue. */
18864 /* Do the expensive promotion once we branched off the small blocks. */
18871 {
18873 {
18874 /* Except for the first move in epilogue, we no longer know
18875 constant offset in aliasing info. It don't seems to worth
18876 the pain to maintain it for the first move, so throw away
18877 the info early. */
18880 desired_align);
18881 }
18882 else
18883 {
18884 /* If we know how many bytes need to be stored before dst is
18885 sufficiently aligned, maintain aliasing info accurately. */
18890 }
18896 {
18897 /* It is possible that we copied enough so the main loop will not
18898 execute. */
18908 else
18910 }
18911 }
18913 {
18919 }
18923 /* Step 3: Main loop. */
18926 {
18954 }
18955 /* Adjust properly the offset of src and dest memory for aliasing. */
18959 else
18962 /* Step 4: Epilogue to copy the remaining bytes. */
18965 {
18966 /* When the main loop is done, COUNT_EXP might hold original count,
18967 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18968 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18969 bytes. Compensate if needed. */
18972 {
18973 tmp =
18976 OPTAB_DIRECT);
18979 }
18982 }
18983 epilogue:
18985 {
18988 epilogue_size_needed);
18989 else
18991 epilogue_size_needed);
18992 }
18996 }
18998 /* Expand the appropriate insns for doing strlen if not just doing
18999 repnz; scasb
19001 out = result, initialized with the start address
19002 align_rtx = alignment of the address.
19003 scratch = scratch register, initialized with the startaddress when
19004 not aligned, otherwise undefined
19006 This is just the body. It needs the initializations mentioned above and
19007 some address computing at the end. These things are done in i386.md. */
19009 static void
19011 {
19013 rtx tmp;
19018 rtx mem;
19021 rtx cmp;
19027 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
19029 /* Is there a known alignment and is it less than 4? */
19031 {
19034 /* Is there a known alignment and is it not 2? */
19036 {
19040 /* Leave just the 3 lower bits. */
19050 }
19051 else
19052 {
19053 /* Since the alignment is 2, we have to check 2 or 0 bytes;
19054 check if is aligned to 4 - byte. */
19061 }
19065 /* Now compare the bytes. */
19067 /* Compare the first n unaligned byte on a byte per byte basis. */
19071 /* Increment the address. */
19074 /* Not needed with an alignment of 2 */
19076 {
19080 end_0_label);
19085 }
19088 end_0_label);
19091 }
19093 /* Generate loop to check 4 bytes at a time. It is not a good idea to
19094 align this loop. It gives only huge programs, but does not help to
19095 speed up. */
19102 /* This formula yields a nonzero result iff one of the bytes is zero.
19103 This saves three branches inside loop and many cycles. */
19111 align_4_label);
19114 {
19120 /* If zero is not in the first two bytes, move two bytes forward. */
19126 reg,
19127 tmpreg)));
19128 /* Emit lea manually to avoid clobbering of flags. */
19136 reg2,
19137 out)));
19138 }
19139 else
19140 {
19142 /* Is zero in the first two bytes? */
19149 pc_rtx);
19153 /* Not in the first two. Move two bytes forward. */
19159 }
19161 /* Avoid branch in fixing the byte. */
19169 }
19171 /* Expand strlen. */
19173 int
19175 {
19178 /* The generic case of strlen expander is long. Avoid it's
19179 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19182 && !TARGET_INLINE_ALL_STRINGOPS
19192 {
19193 /* Well it seems that some optimizer does not combine a call like
19194 foo(strlen(bar), strlen(bar));
19195 when the move and the subtraction is done here. It does calculate
19196 the length just once when these instructions are done inside of
19197 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19198 often used and I use one fewer register for the lifetime of
19199 output_strlen_unroll() this is better. */
19205 /* strlensi_unroll_1 returns the address of the zero at the end of
19206 the string, like memchr(), so compute the length by subtracting
19207 the start address. */
19209 }
19210 else
19211 {
19212 rtx unspec;
19214 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19227 /* If .md starts supporting :P, this can be done in .md. */
19233 }
19235 }
19237 /* For given symbol (function) construct code to compute address of it's PLT
19238 entry in large x86-64 PIC model. */
19239 rtx
19241 {
19251 }
19253 void
19255 rtx callarg2,
19257 {
19265 {
19266 #if TARGET_MACHO
19269 #endif
19270 }
19271 else
19272 {
19273 /* Static functions and indirect calls don't need the pic register. */
19278 }
19281 {
19285 }
19295 {
19298 }
19304 {
19308 }
19312 {
19313 /* We need to represent that SI and DI registers are clobbered
19314 by SYSV calls. */
19320 };
19324 UNSPEC_MS_TO_SYSV_CALL);
19331 gen_rtx_REG
19339 }
19344 }
19346 \f
19347 /* Clear stack slot assignments remembered from previous functions.
19348 This is called from INIT_EXPANDERS once before RTL is emitted for each
19349 function. */
19353 {
19362 }
19364 /* Return a MEM corresponding to a stack slot with mode MODE.
19365 Allocate a new slot if necessary.
19367 The RTL for a function can have several slots available: N is
19368 which slot to use. */
19370 rtx
19372 {
19377 /* Virtual slot is valid only before vregs are instantiated. */
19393 }
19395 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19398 rtx
19400 {
19403 {
19405 (TARGET_ANY_GNU_TLS
19409 }
19412 }
19414 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19417 rtx
19419 {
19422 {
19427 }
19430 }
19431 \f
19432 /* Calculate the length of the memory address in the instruction
19433 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19435 int
19437 {
19462 /* Rule of thumb:
19463 - esp as the base always wants an index,
19464 - ebp as the base always wants a displacement,
19465 - r12 as the base always wants an index,
19466 - r13 as the base always wants a displacement. */
19468 /* Register Indirect. */
19470 {
19471 /* esp (for its index) and ebp (for its displacement) need
19472 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19473 code. */
19482 }
19484 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19485 is not disp32, but disp32(%rip), so for disp32
19486 SIB byte is needed, unless print_operand_address
19487 optimizes it into disp32(%rip) or (%rip) is implied
19488 by UNSPEC. */
19490 {
19493 {
19509 }
19510 }
19512 else
19513 {
19514 /* Find the length of the displacement constant. */
19516 {
19519 else
19521 }
19522 /* ebp always wants a displacement. Similarly r13. */
19527 /* An index requires the two-byte modrm form.... */
19529 /* ...like esp (or r12), which always wants an index. */
19535 }
19538 {
19545 }
19548 }
19550 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19551 is set, expect that insn have 8bit immediate alternative. */
19552 int
19554 {
19560 {
19565 {
19568 {
19580 }
19582 {
19585 }
19586 }
19588 {
19598 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19604 }
19605 }
19607 }
19608 /* Compute default value for "length_address" attribute. */
19609 int
19611 {
19615 {
19625 {
19630 }
19633 }
19638 {
19641 {
19646 constraints++;
19649 ;
19650 /* Skip ignored operands. */
19653 }
19655 }
19657 }
19659 /* Compute default value for "length_vex" attribute. It includes
19660 2 or 3 byte VEX prefix and 1 opcode byte. */
19662 int
19665 {
19668 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19669 byte VEX prefix. */
19673 /* We can always use 2 byte VEX prefix in 32bit. */
19681 {
19682 /* REX.W bit uses 3 byte VEX prefix. */
19686 }
19687 else
19688 {
19689 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19693 }
19696 }
19697 \f
19698 /* Return the maximum number of instructions a cpu can issue. */
19700 static int
19702 {
19704 {
19725 }
19726 }
19728 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19729 by DEP_INSN and nothing set by DEP_INSN. */
19731 static int
19733 {
19736 /* Simplify the test for uninteresting insns. */
19744 {
19747 }
19752 {
19755 }
19756 else
19762 /* This test is true if the dependent insn reads the flags but
19763 not any other potentially set register. */
19771 }
19773 /* Return true iff USE_INSN has a memory address with operands set by
19774 SET_INSN. */
19776 bool
19778 {
19783 {
19786 }
19788 }
19790 static int
19792 {
19798 /* Anti and output dependencies have zero cost on all CPUs. */
19804 /* If we can't recognize the insns, we can't really do anything. */
19812 {
19814 /* Address Generation Interlock adds a cycle of latency. */
19816 {
19827 }
19831 /* ??? Compares pair with jump/setcc. */
19835 /* Floating point stores require value to be ready one cycle earlier. */
19845 /* INT->FP conversion is expensive. */
19849 /* There is one cycle extra latency between an FP op and a store. */
19857 /* Show ability of reorder buffer to hide latency of load by executing
19858 in parallel with previous instruction in case
19859 previous instruction is not needed to compute the address. */
19862 {
19863 /* Claim moves to take one cycle, as core can issue one load
19864 at time and the next load can start cycle later. */
19869 cost--;
19870 }
19876 /* The esp dependency is resolved before the instruction is really
19877 finished. */
19882 /* INT->FP conversion is expensive. */
19886 /* Show ability of reorder buffer to hide latency of load by executing
19887 in parallel with previous instruction in case
19888 previous instruction is not needed to compute the address. */
19891 {
19892 /* Claim moves to take one cycle, as core can issue one load
19893 at time and the next load can start cycle later. */
19899 else
19901 }
19912 /* Show ability of reorder buffer to hide latency of load by executing
19913 in parallel with previous instruction in case
19914 previous instruction is not needed to compute the address. */
19917 {
19921 /* Because of the difference between the length of integer and
19922 floating unit pipeline preparation stages, the memory operands
19923 for floating point are cheaper.
19925 ??? For Athlon it the difference is most probably 2. */
19928 else
19933 else
19935 }
19939 }
19942 }
19944 /* How many alternative schedules to try. This should be as wide as the
19945 scheduling freedom in the DFA, but no wider. Making this value too
19946 large results extra work for the scheduler. */
19948 static int
19950 {
19952 {
19962 }
19963 }
19965 \f
19966 /* Compute the alignment given to a constant that is being placed in memory.
19967 EXP is the constant and ALIGN is the alignment that the object would
19968 ordinarily have.
19969 The value of this function is used instead of that alignment to align
19970 the object. */
19972 int
19974 {
19977 {
19982 }
19988 }
19990 /* Compute the alignment for a static variable.
19991 TYPE is the data type, and ALIGN is the alignment that
19992 the object would ordinarily have. The value of this function is used
19993 instead of that alignment to align the object. */
19995 int
19997 {
20008 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20009 to 16byte boundary. */
20011 {
20018 }
20021 {
20026 }
20028 {
20035 }
20040 {
20045 }
20048 {
20053 }
20056 }
20058 /* Compute the alignment for a local variable or a stack slot. EXP is
20059 the data type or decl itself, MODE is the widest mode available and
20060 ALIGN is the alignment that the object would ordinarily have. The
20061 value of this macro is used instead of that alignment to align the
20062 object. */
20064 unsigned int
20067 {
20071 {
20074 }
20075 else
20076 {
20079 }
20081 /* Don't do dynamic stack realignment for long long objects with
20082 -mpreferred-stack-boundary=2. */
20091 /* If TYPE is NULL, we are allocating a stack slot for caller-save
20092 register in MODE. We will return the largest alignment of XF
20093 and DF. */
20095 {
20099 }
20101 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
20102 to 16byte boundary. */
20104 {
20111 }
20113 {
20118 }
20120 {
20126 }
20131 {
20136 }
20139 {
20145 }
20147 }
20149 /* Compute the minimum required alignment for dynamic stack realignment
20150 purposes for a local variable, parameter or a stack slot. EXP is
20151 the data type or decl itself, MODE is its mode and ALIGN is the
20152 alignment that the object would ordinarily have. */
20154 unsigned int
20157 {
20164 {
20167 }
20168 else
20169 {
20172 }
20174 /* Don't do dynamic stack realignment for long long objects with
20175 -mpreferred-stack-boundary=2. */
20182 }
20183 \f
20184 /* Find a location for the static chain incoming to a nested function.
20185 This is a register, unless all free registers are used by arguments. */
20187 static rtx
20189 {
20196 {
20197 /* We always use R10 in 64-bit mode. */
20199 }
20200 else
20201 {
20202 tree fntype;
20203 /* By default in 32-bit mode we use ECX to pass the static chain. */
20208 {
20209 /* Fastcall functions use ecx/edx for arguments, which leaves
20210 us with EAX for the static chain. */
20212 }
20214 {
20215 /* Thiscall functions use ecx for arguments, which leaves
20216 us with EAX for the static chain. */
20218 }
20220 {
20221 /* For regparm 3, we have no free call-clobbered registers in
20222 which to store the static chain. In order to implement this,
20223 we have the trampoline push the static chain to the stack.
20224 However, we can't push a value below the return address when
20225 we call the nested function directly, so we have to use an
20226 alternate entry point. For this we use ESI, and have the
20227 alternate entry point push ESI, so that things appear the
20228 same once we're executing the nested function. */
20230 {
20235 }
20237 }
20238 }
20241 }
20243 /* Emit RTL insns to initialize the variable parts of a trampoline.
20244 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20245 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20246 to be passed to the target function. */
20248 static void
20250 {
20256 {
20260 /* Depending on the static chain location, either load a register
20261 with a constant, or push the constant to the stack. All of the
20262 instructions are the same size. */
20265 {
20270 else
20272 }
20273 else
20282 /* Compute offset from the end of the jmp to the target function.
20283 In the case in which the trampoline stores the static chain on
20284 the stack, we need to skip the first insn which pushes the
20285 (call-saved) register static chain; this push is 1 byte. */
20296 }
20297 else
20298 {
20301 /* Load the function address to r11. Try to load address using
20302 the shorter movl instead of movabs. We may want to support
20303 movq for kernel mode, but kernel does not use trampolines at
20304 the moment. */
20306 {
20315 }
20316 else
20317 {
20324 }
20326 /* Load static chain using movabs to r10. */
20334 /* Jump to r11; the last (unused) byte is a nop, only there to
20335 pad the write out to a single 32-bit store. */
20341 }
20343 #ifdef ENABLE_EXECUTE_STACK
20344 #ifdef CHECK_EXECUTE_STACK_ENABLED
20346 #endif
20349 #endif
20350 }
20351 \f
20352 /* The following file contains several enumerations and data structures
20353 built from the definitions in i386-builtin-types.def. */
20357 /* Table for the ix86 builtin non-function types. */
20360 /* Retrieve an element from the above table, building some of
20361 the types lazily. */
20363 static tree
20365 {
20377 {
20385 }
20386 else
20387 {
20393 else
20401 }
20405 }
20407 /* Table for the ix86 builtin function types. */
20410 /* Retrieve an element from the above table, building some of
20411 the types lazily. */
20413 static tree
20415 {
20416 tree type;
20425 {
20433 {
20436 }
20439 }
20440 else
20441 {
20447 }
20451 }
20454 /* Codes for all the SSE/MMX builtins. */
20455 enum ix86_builtins
20456 {
20457 IX86_BUILTIN_ADDPS,
20458 IX86_BUILTIN_ADDSS,
20459 IX86_BUILTIN_DIVPS,
20460 IX86_BUILTIN_DIVSS,
20461 IX86_BUILTIN_MULPS,
20462 IX86_BUILTIN_MULSS,
20463 IX86_BUILTIN_SUBPS,
20464 IX86_BUILTIN_SUBSS,
20466 IX86_BUILTIN_CMPEQPS,
20467 IX86_BUILTIN_CMPLTPS,
20468 IX86_BUILTIN_CMPLEPS,
20469 IX86_BUILTIN_CMPGTPS,
20470 IX86_BUILTIN_CMPGEPS,
20471 IX86_BUILTIN_CMPNEQPS,
20472 IX86_BUILTIN_CMPNLTPS,
20473 IX86_BUILTIN_CMPNLEPS,
20474 IX86_BUILTIN_CMPNGTPS,
20475 IX86_BUILTIN_CMPNGEPS,
20476 IX86_BUILTIN_CMPORDPS,
20477 IX86_BUILTIN_CMPUNORDPS,
20478 IX86_BUILTIN_CMPEQSS,
20479 IX86_BUILTIN_CMPLTSS,
20480 IX86_BUILTIN_CMPLESS,
20481 IX86_BUILTIN_CMPNEQSS,
20482 IX86_BUILTIN_CMPNLTSS,
20483 IX86_BUILTIN_CMPNLESS,
20484 IX86_BUILTIN_CMPNGTSS,
20485 IX86_BUILTIN_CMPNGESS,
20486 IX86_BUILTIN_CMPORDSS,
20487 IX86_BUILTIN_CMPUNORDSS,
20489 IX86_BUILTIN_COMIEQSS,
20490 IX86_BUILTIN_COMILTSS,
20491 IX86_BUILTIN_COMILESS,
20492 IX86_BUILTIN_COMIGTSS,
20493 IX86_BUILTIN_COMIGESS,
20494 IX86_BUILTIN_COMINEQSS,
20495 IX86_BUILTIN_UCOMIEQSS,
20496 IX86_BUILTIN_UCOMILTSS,
20497 IX86_BUILTIN_UCOMILESS,
20498 IX86_BUILTIN_UCOMIGTSS,
20499 IX86_BUILTIN_UCOMIGESS,
20500 IX86_BUILTIN_UCOMINEQSS,
20502 IX86_BUILTIN_CVTPI2PS,
20503 IX86_BUILTIN_CVTPS2PI,
20504 IX86_BUILTIN_CVTSI2SS,
20505 IX86_BUILTIN_CVTSI642SS,
20506 IX86_BUILTIN_CVTSS2SI,
20507 IX86_BUILTIN_CVTSS2SI64,
20508 IX86_BUILTIN_CVTTPS2PI,
20509 IX86_BUILTIN_CVTTSS2SI,
20510 IX86_BUILTIN_CVTTSS2SI64,
20512 IX86_BUILTIN_MAXPS,
20513 IX86_BUILTIN_MAXSS,
20514 IX86_BUILTIN_MINPS,
20515 IX86_BUILTIN_MINSS,
20517 IX86_BUILTIN_LOADUPS,
20518 IX86_BUILTIN_STOREUPS,
20519 IX86_BUILTIN_MOVSS,
20521 IX86_BUILTIN_MOVHLPS,
20522 IX86_BUILTIN_MOVLHPS,
20523 IX86_BUILTIN_LOADHPS,
20524 IX86_BUILTIN_LOADLPS,
20525 IX86_BUILTIN_STOREHPS,
20526 IX86_BUILTIN_STORELPS,
20528 IX86_BUILTIN_MASKMOVQ,
20529 IX86_BUILTIN_MOVMSKPS,
20530 IX86_BUILTIN_PMOVMSKB,
20532 IX86_BUILTIN_MOVNTPS,
20533 IX86_BUILTIN_MOVNTQ,
20535 IX86_BUILTIN_LOADDQU,
20536 IX86_BUILTIN_STOREDQU,
20538 IX86_BUILTIN_PACKSSWB,
20539 IX86_BUILTIN_PACKSSDW,
20540 IX86_BUILTIN_PACKUSWB,
20542 IX86_BUILTIN_PADDB,
20543 IX86_BUILTIN_PADDW,
20544 IX86_BUILTIN_PADDD,
20545 IX86_BUILTIN_PADDQ,
20546 IX86_BUILTIN_PADDSB,
20547 IX86_BUILTIN_PADDSW,
20548 IX86_BUILTIN_PADDUSB,
20549 IX86_BUILTIN_PADDUSW,
20550 IX86_BUILTIN_PSUBB,
20551 IX86_BUILTIN_PSUBW,
20552 IX86_BUILTIN_PSUBD,
20553 IX86_BUILTIN_PSUBQ,
20554 IX86_BUILTIN_PSUBSB,
20555 IX86_BUILTIN_PSUBSW,
20556 IX86_BUILTIN_PSUBUSB,
20557 IX86_BUILTIN_PSUBUSW,
20559 IX86_BUILTIN_PAND,
20560 IX86_BUILTIN_PANDN,
20561 IX86_BUILTIN_POR,
20562 IX86_BUILTIN_PXOR,
20564 IX86_BUILTIN_PAVGB,
20565 IX86_BUILTIN_PAVGW,
20567 IX86_BUILTIN_PCMPEQB,
20568 IX86_BUILTIN_PCMPEQW,
20569 IX86_BUILTIN_PCMPEQD,
20570 IX86_BUILTIN_PCMPGTB,
20571 IX86_BUILTIN_PCMPGTW,
20572 IX86_BUILTIN_PCMPGTD,
20574 IX86_BUILTIN_PMADDWD,
20576 IX86_BUILTIN_PMAXSW,
20577 IX86_BUILTIN_PMAXUB,
20578 IX86_BUILTIN_PMINSW,
20579 IX86_BUILTIN_PMINUB,
20581 IX86_BUILTIN_PMULHUW,
20582 IX86_BUILTIN_PMULHW,
20583 IX86_BUILTIN_PMULLW,
20585 IX86_BUILTIN_PSADBW,
20586 IX86_BUILTIN_PSHUFW,
20588 IX86_BUILTIN_PSLLW,
20589 IX86_BUILTIN_PSLLD,
20590 IX86_BUILTIN_PSLLQ,
20591 IX86_BUILTIN_PSRAW,
20592 IX86_BUILTIN_PSRAD,
20593 IX86_BUILTIN_PSRLW,
20594 IX86_BUILTIN_PSRLD,
20595 IX86_BUILTIN_PSRLQ,
20596 IX86_BUILTIN_PSLLWI,
20597 IX86_BUILTIN_PSLLDI,
20598 IX86_BUILTIN_PSLLQI,
20599 IX86_BUILTIN_PSRAWI,
20600 IX86_BUILTIN_PSRADI,
20601 IX86_BUILTIN_PSRLWI,
20602 IX86_BUILTIN_PSRLDI,
20603 IX86_BUILTIN_PSRLQI,
20605 IX86_BUILTIN_PUNPCKHBW,
20606 IX86_BUILTIN_PUNPCKHWD,
20607 IX86_BUILTIN_PUNPCKHDQ,
20608 IX86_BUILTIN_PUNPCKLBW,
20609 IX86_BUILTIN_PUNPCKLWD,
20610 IX86_BUILTIN_PUNPCKLDQ,
20612 IX86_BUILTIN_SHUFPS,
20614 IX86_BUILTIN_RCPPS,
20615 IX86_BUILTIN_RCPSS,
20616 IX86_BUILTIN_RSQRTPS,
20617 IX86_BUILTIN_RSQRTPS_NR,
20618 IX86_BUILTIN_RSQRTSS,
20619 IX86_BUILTIN_RSQRTF,
20620 IX86_BUILTIN_SQRTPS,
20621 IX86_BUILTIN_SQRTPS_NR,
20622 IX86_BUILTIN_SQRTSS,
20624 IX86_BUILTIN_UNPCKHPS,
20625 IX86_BUILTIN_UNPCKLPS,
20627 IX86_BUILTIN_ANDPS,
20628 IX86_BUILTIN_ANDNPS,
20629 IX86_BUILTIN_ORPS,
20630 IX86_BUILTIN_XORPS,
20632 IX86_BUILTIN_EMMS,
20633 IX86_BUILTIN_LDMXCSR,
20634 IX86_BUILTIN_STMXCSR,
20635 IX86_BUILTIN_SFENCE,
20637 /* 3DNow! Original */
20638 IX86_BUILTIN_FEMMS,
20639 IX86_BUILTIN_PAVGUSB,
20640 IX86_BUILTIN_PF2ID,
20641 IX86_BUILTIN_PFACC,
20642 IX86_BUILTIN_PFADD,
20643 IX86_BUILTIN_PFCMPEQ,
20644 IX86_BUILTIN_PFCMPGE,
20645 IX86_BUILTIN_PFCMPGT,
20646 IX86_BUILTIN_PFMAX,
20647 IX86_BUILTIN_PFMIN,
20648 IX86_BUILTIN_PFMUL,
20649 IX86_BUILTIN_PFRCP,
20650 IX86_BUILTIN_PFRCPIT1,
20651 IX86_BUILTIN_PFRCPIT2,
20652 IX86_BUILTIN_PFRSQIT1,
20653 IX86_BUILTIN_PFRSQRT,
20654 IX86_BUILTIN_PFSUB,
20655 IX86_BUILTIN_PFSUBR,
20656 IX86_BUILTIN_PI2FD,
20657 IX86_BUILTIN_PMULHRW,
20659 /* 3DNow! Athlon Extensions */
20660 IX86_BUILTIN_PF2IW,
20661 IX86_BUILTIN_PFNACC,
20662 IX86_BUILTIN_PFPNACC,
20663 IX86_BUILTIN_PI2FW,
20664 IX86_BUILTIN_PSWAPDSI,
20665 IX86_BUILTIN_PSWAPDSF,
20667 /* SSE2 */
20668 IX86_BUILTIN_ADDPD,
20669 IX86_BUILTIN_ADDSD,
20670 IX86_BUILTIN_DIVPD,
20671 IX86_BUILTIN_DIVSD,
20672 IX86_BUILTIN_MULPD,
20673 IX86_BUILTIN_MULSD,
20674 IX86_BUILTIN_SUBPD,
20675 IX86_BUILTIN_SUBSD,
20677 IX86_BUILTIN_CMPEQPD,
20678 IX86_BUILTIN_CMPLTPD,
20679 IX86_BUILTIN_CMPLEPD,
20680 IX86_BUILTIN_CMPGTPD,
20681 IX86_BUILTIN_CMPGEPD,
20682 IX86_BUILTIN_CMPNEQPD,
20683 IX86_BUILTIN_CMPNLTPD,
20684 IX86_BUILTIN_CMPNLEPD,
20685 IX86_BUILTIN_CMPNGTPD,
20686 IX86_BUILTIN_CMPNGEPD,
20687 IX86_BUILTIN_CMPORDPD,
20688 IX86_BUILTIN_CMPUNORDPD,
20689 IX86_BUILTIN_CMPEQSD,
20690 IX86_BUILTIN_CMPLTSD,
20691 IX86_BUILTIN_CMPLESD,
20692 IX86_BUILTIN_CMPNEQSD,
20693 IX86_BUILTIN_CMPNLTSD,
20694 IX86_BUILTIN_CMPNLESD,
20695 IX86_BUILTIN_CMPORDSD,
20696 IX86_BUILTIN_CMPUNORDSD,
20698 IX86_BUILTIN_COMIEQSD,
20699 IX86_BUILTIN_COMILTSD,
20700 IX86_BUILTIN_COMILESD,
20701 IX86_BUILTIN_COMIGTSD,
20702 IX86_BUILTIN_COMIGESD,
20703 IX86_BUILTIN_COMINEQSD,
20704 IX86_BUILTIN_UCOMIEQSD,
20705 IX86_BUILTIN_UCOMILTSD,
20706 IX86_BUILTIN_UCOMILESD,
20707 IX86_BUILTIN_UCOMIGTSD,
20708 IX86_BUILTIN_UCOMIGESD,
20709 IX86_BUILTIN_UCOMINEQSD,
20711 IX86_BUILTIN_MAXPD,
20712 IX86_BUILTIN_MAXSD,
20713 IX86_BUILTIN_MINPD,
20714 IX86_BUILTIN_MINSD,
20716 IX86_BUILTIN_ANDPD,
20717 IX86_BUILTIN_ANDNPD,
20718 IX86_BUILTIN_ORPD,
20719 IX86_BUILTIN_XORPD,
20721 IX86_BUILTIN_SQRTPD,
20722 IX86_BUILTIN_SQRTSD,
20724 IX86_BUILTIN_UNPCKHPD,
20725 IX86_BUILTIN_UNPCKLPD,
20727 IX86_BUILTIN_SHUFPD,
20729 IX86_BUILTIN_LOADUPD,
20730 IX86_BUILTIN_STOREUPD,
20731 IX86_BUILTIN_MOVSD,
20733 IX86_BUILTIN_LOADHPD,
20734 IX86_BUILTIN_LOADLPD,
20736 IX86_BUILTIN_CVTDQ2PD,
20737 IX86_BUILTIN_CVTDQ2PS,
20739 IX86_BUILTIN_CVTPD2DQ,
20740 IX86_BUILTIN_CVTPD2PI,
20741 IX86_BUILTIN_CVTPD2PS,
20742 IX86_BUILTIN_CVTTPD2DQ,
20743 IX86_BUILTIN_CVTTPD2PI,
20745 IX86_BUILTIN_CVTPI2PD,
20746 IX86_BUILTIN_CVTSI2SD,
20747 IX86_BUILTIN_CVTSI642SD,
20749 IX86_BUILTIN_CVTSD2SI,
20750 IX86_BUILTIN_CVTSD2SI64,
20751 IX86_BUILTIN_CVTSD2SS,
20752 IX86_BUILTIN_CVTSS2SD,
20753 IX86_BUILTIN_CVTTSD2SI,
20754 IX86_BUILTIN_CVTTSD2SI64,
20756 IX86_BUILTIN_CVTPS2DQ,
20757 IX86_BUILTIN_CVTPS2PD,
20758 IX86_BUILTIN_CVTTPS2DQ,
20760 IX86_BUILTIN_MOVNTI,
20761 IX86_BUILTIN_MOVNTPD,
20762 IX86_BUILTIN_MOVNTDQ,
20764 IX86_BUILTIN_MOVQ128,
20766 /* SSE2 MMX */
20767 IX86_BUILTIN_MASKMOVDQU,
20768 IX86_BUILTIN_MOVMSKPD,
20769 IX86_BUILTIN_PMOVMSKB128,
20771 IX86_BUILTIN_PACKSSWB128,
20772 IX86_BUILTIN_PACKSSDW128,
20773 IX86_BUILTIN_PACKUSWB128,
20775 IX86_BUILTIN_PADDB128,
20776 IX86_BUILTIN_PADDW128,
20777 IX86_BUILTIN_PADDD128,
20778 IX86_BUILTIN_PADDQ128,
20779 IX86_BUILTIN_PADDSB128,
20780 IX86_BUILTIN_PADDSW128,
20781 IX86_BUILTIN_PADDUSB128,
20782 IX86_BUILTIN_PADDUSW128,
20783 IX86_BUILTIN_PSUBB128,
20784 IX86_BUILTIN_PSUBW128,
20785 IX86_BUILTIN_PSUBD128,
20786 IX86_BUILTIN_PSUBQ128,
20787 IX86_BUILTIN_PSUBSB128,
20788 IX86_BUILTIN_PSUBSW128,
20789 IX86_BUILTIN_PSUBUSB128,
20790 IX86_BUILTIN_PSUBUSW128,
20792 IX86_BUILTIN_PAND128,
20793 IX86_BUILTIN_PANDN128,
20794 IX86_BUILTIN_POR128,
20795 IX86_BUILTIN_PXOR128,
20797 IX86_BUILTIN_PAVGB128,
20798 IX86_BUILTIN_PAVGW128,
20800 IX86_BUILTIN_PCMPEQB128,
20801 IX86_BUILTIN_PCMPEQW128,
20802 IX86_BUILTIN_PCMPEQD128,
20803 IX86_BUILTIN_PCMPGTB128,
20804 IX86_BUILTIN_PCMPGTW128,
20805 IX86_BUILTIN_PCMPGTD128,
20807 IX86_BUILTIN_PMADDWD128,
20809 IX86_BUILTIN_PMAXSW128,
20810 IX86_BUILTIN_PMAXUB128,
20811 IX86_BUILTIN_PMINSW128,
20812 IX86_BUILTIN_PMINUB128,
20814 IX86_BUILTIN_PMULUDQ,
20815 IX86_BUILTIN_PMULUDQ128,
20816 IX86_BUILTIN_PMULHUW128,
20817 IX86_BUILTIN_PMULHW128,
20818 IX86_BUILTIN_PMULLW128,
20820 IX86_BUILTIN_PSADBW128,
20821 IX86_BUILTIN_PSHUFHW,
20822 IX86_BUILTIN_PSHUFLW,
20823 IX86_BUILTIN_PSHUFD,
20825 IX86_BUILTIN_PSLLDQI128,
20826 IX86_BUILTIN_PSLLWI128,
20827 IX86_BUILTIN_PSLLDI128,
20828 IX86_BUILTIN_PSLLQI128,
20829 IX86_BUILTIN_PSRAWI128,
20830 IX86_BUILTIN_PSRADI128,
20831 IX86_BUILTIN_PSRLDQI128,
20832 IX86_BUILTIN_PSRLWI128,
20833 IX86_BUILTIN_PSRLDI128,
20834 IX86_BUILTIN_PSRLQI128,
20836 IX86_BUILTIN_PSLLDQ128,
20837 IX86_BUILTIN_PSLLW128,
20838 IX86_BUILTIN_PSLLD128,
20839 IX86_BUILTIN_PSLLQ128,
20840 IX86_BUILTIN_PSRAW128,
20841 IX86_BUILTIN_PSRAD128,
20842 IX86_BUILTIN_PSRLW128,
20843 IX86_BUILTIN_PSRLD128,
20844 IX86_BUILTIN_PSRLQ128,
20846 IX86_BUILTIN_PUNPCKHBW128,
20847 IX86_BUILTIN_PUNPCKHWD128,
20848 IX86_BUILTIN_PUNPCKHDQ128,
20849 IX86_BUILTIN_PUNPCKHQDQ128,
20850 IX86_BUILTIN_PUNPCKLBW128,
20851 IX86_BUILTIN_PUNPCKLWD128,
20852 IX86_BUILTIN_PUNPCKLDQ128,
20853 IX86_BUILTIN_PUNPCKLQDQ128,
20855 IX86_BUILTIN_CLFLUSH,
20856 IX86_BUILTIN_MFENCE,
20857 IX86_BUILTIN_LFENCE,
20859 IX86_BUILTIN_BSRSI,
20860 IX86_BUILTIN_BSRDI,
20861 IX86_BUILTIN_RDPMC,
20862 IX86_BUILTIN_RDTSC,
20863 IX86_BUILTIN_RDTSCP,
20864 IX86_BUILTIN_ROLQI,
20865 IX86_BUILTIN_ROLHI,
20866 IX86_BUILTIN_RORQI,
20867 IX86_BUILTIN_RORHI,
20869 /* SSE3. */
20870 IX86_BUILTIN_ADDSUBPS,
20871 IX86_BUILTIN_HADDPS,
20872 IX86_BUILTIN_HSUBPS,
20873 IX86_BUILTIN_MOVSHDUP,
20874 IX86_BUILTIN_MOVSLDUP,
20875 IX86_BUILTIN_ADDSUBPD,
20876 IX86_BUILTIN_HADDPD,
20877 IX86_BUILTIN_HSUBPD,
20878 IX86_BUILTIN_LDDQU,
20880 IX86_BUILTIN_MONITOR,
20881 IX86_BUILTIN_MWAIT,
20883 /* SSSE3. */
20884 IX86_BUILTIN_PHADDW,
20885 IX86_BUILTIN_PHADDD,
20886 IX86_BUILTIN_PHADDSW,
20887 IX86_BUILTIN_PHSUBW,
20888 IX86_BUILTIN_PHSUBD,
20889 IX86_BUILTIN_PHSUBSW,
20890 IX86_BUILTIN_PMADDUBSW,
20891 IX86_BUILTIN_PMULHRSW,
20892 IX86_BUILTIN_PSHUFB,
20893 IX86_BUILTIN_PSIGNB,
20894 IX86_BUILTIN_PSIGNW,
20895 IX86_BUILTIN_PSIGND,
20896 IX86_BUILTIN_PALIGNR,
20897 IX86_BUILTIN_PABSB,
20898 IX86_BUILTIN_PABSW,
20899 IX86_BUILTIN_PABSD,
20901 IX86_BUILTIN_PHADDW128,
20902 IX86_BUILTIN_PHADDD128,
20903 IX86_BUILTIN_PHADDSW128,
20904 IX86_BUILTIN_PHSUBW128,
20905 IX86_BUILTIN_PHSUBD128,
20906 IX86_BUILTIN_PHSUBSW128,
20907 IX86_BUILTIN_PMADDUBSW128,
20908 IX86_BUILTIN_PMULHRSW128,
20909 IX86_BUILTIN_PSHUFB128,
20910 IX86_BUILTIN_PSIGNB128,
20911 IX86_BUILTIN_PSIGNW128,
20912 IX86_BUILTIN_PSIGND128,
20913 IX86_BUILTIN_PALIGNR128,
20914 IX86_BUILTIN_PABSB128,
20915 IX86_BUILTIN_PABSW128,
20916 IX86_BUILTIN_PABSD128,
20918 /* AMDFAM10 - SSE4A New Instructions. */
20919 IX86_BUILTIN_MOVNTSD,
20920 IX86_BUILTIN_MOVNTSS,
20921 IX86_BUILTIN_EXTRQI,
20922 IX86_BUILTIN_EXTRQ,
20923 IX86_BUILTIN_INSERTQI,
20924 IX86_BUILTIN_INSERTQ,
20926 /* SSE4.1. */
20927 IX86_BUILTIN_BLENDPD,
20928 IX86_BUILTIN_BLENDPS,
20929 IX86_BUILTIN_BLENDVPD,
20930 IX86_BUILTIN_BLENDVPS,
20931 IX86_BUILTIN_PBLENDVB128,
20932 IX86_BUILTIN_PBLENDW128,
20934 IX86_BUILTIN_DPPD,
20935 IX86_BUILTIN_DPPS,
20937 IX86_BUILTIN_INSERTPS128,
20939 IX86_BUILTIN_MOVNTDQA,
20940 IX86_BUILTIN_MPSADBW128,
20941 IX86_BUILTIN_PACKUSDW128,
20942 IX86_BUILTIN_PCMPEQQ,
20943 IX86_BUILTIN_PHMINPOSUW128,
20945 IX86_BUILTIN_PMAXSB128,
20946 IX86_BUILTIN_PMAXSD128,
20947 IX86_BUILTIN_PMAXUD128,
20948 IX86_BUILTIN_PMAXUW128,
20950 IX86_BUILTIN_PMINSB128,
20951 IX86_BUILTIN_PMINSD128,
20952 IX86_BUILTIN_PMINUD128,
20953 IX86_BUILTIN_PMINUW128,
20955 IX86_BUILTIN_PMOVSXBW128,
20956 IX86_BUILTIN_PMOVSXBD128,
20957 IX86_BUILTIN_PMOVSXBQ128,
20958 IX86_BUILTIN_PMOVSXWD128,
20959 IX86_BUILTIN_PMOVSXWQ128,
20960 IX86_BUILTIN_PMOVSXDQ128,
20962 IX86_BUILTIN_PMOVZXBW128,
20963 IX86_BUILTIN_PMOVZXBD128,
20964 IX86_BUILTIN_PMOVZXBQ128,
20965 IX86_BUILTIN_PMOVZXWD128,
20966 IX86_BUILTIN_PMOVZXWQ128,
20967 IX86_BUILTIN_PMOVZXDQ128,
20969 IX86_BUILTIN_PMULDQ128,
20970 IX86_BUILTIN_PMULLD128,
20972 IX86_BUILTIN_ROUNDPD,
20973 IX86_BUILTIN_ROUNDPS,
20974 IX86_BUILTIN_ROUNDSD,
20975 IX86_BUILTIN_ROUNDSS,
20977 IX86_BUILTIN_PTESTZ,
20978 IX86_BUILTIN_PTESTC,
20979 IX86_BUILTIN_PTESTNZC,
20981 IX86_BUILTIN_VEC_INIT_V2SI,
20982 IX86_BUILTIN_VEC_INIT_V4HI,
20983 IX86_BUILTIN_VEC_INIT_V8QI,
20984 IX86_BUILTIN_VEC_EXT_V2DF,
20985 IX86_BUILTIN_VEC_EXT_V2DI,
20986 IX86_BUILTIN_VEC_EXT_V4SF,
20987 IX86_BUILTIN_VEC_EXT_V4SI,
20988 IX86_BUILTIN_VEC_EXT_V8HI,
20989 IX86_BUILTIN_VEC_EXT_V2SI,
20990 IX86_BUILTIN_VEC_EXT_V4HI,
20991 IX86_BUILTIN_VEC_EXT_V16QI,
20992 IX86_BUILTIN_VEC_SET_V2DI,
20993 IX86_BUILTIN_VEC_SET_V4SF,
20994 IX86_BUILTIN_VEC_SET_V4SI,
20995 IX86_BUILTIN_VEC_SET_V8HI,
20996 IX86_BUILTIN_VEC_SET_V4HI,
20997 IX86_BUILTIN_VEC_SET_V16QI,
20999 IX86_BUILTIN_VEC_PACK_SFIX,
21001 /* SSE4.2. */
21002 IX86_BUILTIN_CRC32QI,
21003 IX86_BUILTIN_CRC32HI,
21004 IX86_BUILTIN_CRC32SI,
21005 IX86_BUILTIN_CRC32DI,
21007 IX86_BUILTIN_PCMPESTRI128,
21008 IX86_BUILTIN_PCMPESTRM128,
21009 IX86_BUILTIN_PCMPESTRA128,
21010 IX86_BUILTIN_PCMPESTRC128,
21011 IX86_BUILTIN_PCMPESTRO128,
21012 IX86_BUILTIN_PCMPESTRS128,
21013 IX86_BUILTIN_PCMPESTRZ128,
21014 IX86_BUILTIN_PCMPISTRI128,
21015 IX86_BUILTIN_PCMPISTRM128,
21016 IX86_BUILTIN_PCMPISTRA128,
21017 IX86_BUILTIN_PCMPISTRC128,
21018 IX86_BUILTIN_PCMPISTRO128,
21019 IX86_BUILTIN_PCMPISTRS128,
21020 IX86_BUILTIN_PCMPISTRZ128,
21022 IX86_BUILTIN_PCMPGTQ,
21024 /* AES instructions */
21025 IX86_BUILTIN_AESENC128,
21026 IX86_BUILTIN_AESENCLAST128,
21027 IX86_BUILTIN_AESDEC128,
21028 IX86_BUILTIN_AESDECLAST128,
21029 IX86_BUILTIN_AESIMC128,
21030 IX86_BUILTIN_AESKEYGENASSIST128,
21032 /* PCLMUL instruction */
21033 IX86_BUILTIN_PCLMULQDQ128,
21035 /* AVX */
21036 IX86_BUILTIN_ADDPD256,
21037 IX86_BUILTIN_ADDPS256,
21038 IX86_BUILTIN_ADDSUBPD256,
21039 IX86_BUILTIN_ADDSUBPS256,
21040 IX86_BUILTIN_ANDPD256,
21041 IX86_BUILTIN_ANDPS256,
21042 IX86_BUILTIN_ANDNPD256,
21043 IX86_BUILTIN_ANDNPS256,
21044 IX86_BUILTIN_BLENDPD256,
21045 IX86_BUILTIN_BLENDPS256,
21046 IX86_BUILTIN_BLENDVPD256,
21047 IX86_BUILTIN_BLENDVPS256,
21048 IX86_BUILTIN_DIVPD256,
21049 IX86_BUILTIN_DIVPS256,
21050 IX86_BUILTIN_DPPS256,
21051 IX86_BUILTIN_HADDPD256,
21052 IX86_BUILTIN_HADDPS256,
21053 IX86_BUILTIN_HSUBPD256,
21054 IX86_BUILTIN_HSUBPS256,
21055 IX86_BUILTIN_MAXPD256,
21056 IX86_BUILTIN_MAXPS256,
21057 IX86_BUILTIN_MINPD256,
21058 IX86_BUILTIN_MINPS256,
21059 IX86_BUILTIN_MULPD256,
21060 IX86_BUILTIN_MULPS256,
21061 IX86_BUILTIN_ORPD256,
21062 IX86_BUILTIN_ORPS256,
21063 IX86_BUILTIN_SHUFPD256,
21064 IX86_BUILTIN_SHUFPS256,
21065 IX86_BUILTIN_SUBPD256,
21066 IX86_BUILTIN_SUBPS256,
21067 IX86_BUILTIN_XORPD256,
21068 IX86_BUILTIN_XORPS256,
21069 IX86_BUILTIN_CMPSD,
21070 IX86_BUILTIN_CMPSS,
21071 IX86_BUILTIN_CMPPD,
21072 IX86_BUILTIN_CMPPS,
21073 IX86_BUILTIN_CMPPD256,
21074 IX86_BUILTIN_CMPPS256,
21075 IX86_BUILTIN_CVTDQ2PD256,
21076 IX86_BUILTIN_CVTDQ2PS256,
21077 IX86_BUILTIN_CVTPD2PS256,
21078 IX86_BUILTIN_CVTPS2DQ256,
21079 IX86_BUILTIN_CVTPS2PD256,
21080 IX86_BUILTIN_CVTTPD2DQ256,
21081 IX86_BUILTIN_CVTPD2DQ256,
21082 IX86_BUILTIN_CVTTPS2DQ256,
21083 IX86_BUILTIN_EXTRACTF128PD256,
21084 IX86_BUILTIN_EXTRACTF128PS256,
21085 IX86_BUILTIN_EXTRACTF128SI256,
21086 IX86_BUILTIN_VZEROALL,
21087 IX86_BUILTIN_VZEROUPPER,
21088 IX86_BUILTIN_VPERMILVARPD,
21089 IX86_BUILTIN_VPERMILVARPS,
21090 IX86_BUILTIN_VPERMILVARPD256,
21091 IX86_BUILTIN_VPERMILVARPS256,
21092 IX86_BUILTIN_VPERMILPD,
21093 IX86_BUILTIN_VPERMILPS,
21094 IX86_BUILTIN_VPERMILPD256,
21095 IX86_BUILTIN_VPERMILPS256,
21096 IX86_BUILTIN_VPERMIL2PD,
21097 IX86_BUILTIN_VPERMIL2PS,
21098 IX86_BUILTIN_VPERMIL2PD256,
21099 IX86_BUILTIN_VPERMIL2PS256,
21100 IX86_BUILTIN_VPERM2F128PD256,
21101 IX86_BUILTIN_VPERM2F128PS256,
21102 IX86_BUILTIN_VPERM2F128SI256,
21103 IX86_BUILTIN_VBROADCASTSS,
21104 IX86_BUILTIN_VBROADCASTSD256,
21105 IX86_BUILTIN_VBROADCASTSS256,
21106 IX86_BUILTIN_VBROADCASTPD256,
21107 IX86_BUILTIN_VBROADCASTPS256,
21108 IX86_BUILTIN_VINSERTF128PD256,
21109 IX86_BUILTIN_VINSERTF128PS256,
21110 IX86_BUILTIN_VINSERTF128SI256,
21111 IX86_BUILTIN_LOADUPD256,
21112 IX86_BUILTIN_LOADUPS256,
21113 IX86_BUILTIN_STOREUPD256,
21114 IX86_BUILTIN_STOREUPS256,
21115 IX86_BUILTIN_LDDQU256,
21116 IX86_BUILTIN_MOVNTDQ256,
21117 IX86_BUILTIN_MOVNTPD256,
21118 IX86_BUILTIN_MOVNTPS256,
21119 IX86_BUILTIN_LOADDQU256,
21120 IX86_BUILTIN_STOREDQU256,
21121 IX86_BUILTIN_MASKLOADPD,
21122 IX86_BUILTIN_MASKLOADPS,
21123 IX86_BUILTIN_MASKSTOREPD,
21124 IX86_BUILTIN_MASKSTOREPS,
21125 IX86_BUILTIN_MASKLOADPD256,
21126 IX86_BUILTIN_MASKLOADPS256,
21127 IX86_BUILTIN_MASKSTOREPD256,
21128 IX86_BUILTIN_MASKSTOREPS256,
21129 IX86_BUILTIN_MOVSHDUP256,
21130 IX86_BUILTIN_MOVSLDUP256,
21131 IX86_BUILTIN_MOVDDUP256,
21133 IX86_BUILTIN_SQRTPD256,
21134 IX86_BUILTIN_SQRTPS256,
21135 IX86_BUILTIN_SQRTPS_NR256,
21136 IX86_BUILTIN_RSQRTPS256,
21137 IX86_BUILTIN_RSQRTPS_NR256,
21139 IX86_BUILTIN_RCPPS256,
21141 IX86_BUILTIN_ROUNDPD256,
21142 IX86_BUILTIN_ROUNDPS256,
21144 IX86_BUILTIN_UNPCKHPD256,
21145 IX86_BUILTIN_UNPCKLPD256,
21146 IX86_BUILTIN_UNPCKHPS256,
21147 IX86_BUILTIN_UNPCKLPS256,
21149 IX86_BUILTIN_SI256_SI,
21150 IX86_BUILTIN_PS256_PS,
21151 IX86_BUILTIN_PD256_PD,
21152 IX86_BUILTIN_SI_SI256,
21153 IX86_BUILTIN_PS_PS256,
21154 IX86_BUILTIN_PD_PD256,
21156 IX86_BUILTIN_VTESTZPD,
21157 IX86_BUILTIN_VTESTCPD,
21158 IX86_BUILTIN_VTESTNZCPD,
21159 IX86_BUILTIN_VTESTZPS,
21160 IX86_BUILTIN_VTESTCPS,
21161 IX86_BUILTIN_VTESTNZCPS,
21162 IX86_BUILTIN_VTESTZPD256,
21163 IX86_BUILTIN_VTESTCPD256,
21164 IX86_BUILTIN_VTESTNZCPD256,
21165 IX86_BUILTIN_VTESTZPS256,
21166 IX86_BUILTIN_VTESTCPS256,
21167 IX86_BUILTIN_VTESTNZCPS256,
21168 IX86_BUILTIN_PTESTZ256,
21169 IX86_BUILTIN_PTESTC256,
21170 IX86_BUILTIN_PTESTNZC256,
21172 IX86_BUILTIN_MOVMSKPD256,
21173 IX86_BUILTIN_MOVMSKPS256,
21175 /* TFmode support builtins. */
21176 IX86_BUILTIN_INFQ,
21177 IX86_BUILTIN_HUGE_VALQ,
21178 IX86_BUILTIN_FABSQ,
21179 IX86_BUILTIN_COPYSIGNQ,
21181 /* Vectorizer support builtins. */
21182 IX86_BUILTIN_CPYSGNPS,
21183 IX86_BUILTIN_CPYSGNPD,
21185 IX86_BUILTIN_CVTUDQ2PS,
21187 IX86_BUILTIN_VEC_PERM_V2DF,
21188 IX86_BUILTIN_VEC_PERM_V4SF,
21189 IX86_BUILTIN_VEC_PERM_V2DI,
21190 IX86_BUILTIN_VEC_PERM_V4SI,
21191 IX86_BUILTIN_VEC_PERM_V8HI,
21192 IX86_BUILTIN_VEC_PERM_V16QI,
21193 IX86_BUILTIN_VEC_PERM_V2DI_U,
21194 IX86_BUILTIN_VEC_PERM_V4SI_U,
21195 IX86_BUILTIN_VEC_PERM_V8HI_U,
21196 IX86_BUILTIN_VEC_PERM_V16QI_U,
21197 IX86_BUILTIN_VEC_PERM_V4DF,
21198 IX86_BUILTIN_VEC_PERM_V8SF,
21200 /* FMA4 and XOP instructions. */
21201 IX86_BUILTIN_VFMADDSS,
21202 IX86_BUILTIN_VFMADDSD,
21203 IX86_BUILTIN_VFMADDPS,
21204 IX86_BUILTIN_VFMADDPD,
21205 IX86_BUILTIN_VFMSUBSS,
21206 IX86_BUILTIN_VFMSUBSD,
21207 IX86_BUILTIN_VFMSUBPS,
21208 IX86_BUILTIN_VFMSUBPD,
21209 IX86_BUILTIN_VFMADDSUBPS,
21210 IX86_BUILTIN_VFMADDSUBPD,
21211 IX86_BUILTIN_VFMSUBADDPS,
21212 IX86_BUILTIN_VFMSUBADDPD,
21213 IX86_BUILTIN_VFNMADDSS,
21214 IX86_BUILTIN_VFNMADDSD,
21215 IX86_BUILTIN_VFNMADDPS,
21216 IX86_BUILTIN_VFNMADDPD,
21217 IX86_BUILTIN_VFNMSUBSS,
21218 IX86_BUILTIN_VFNMSUBSD,
21219 IX86_BUILTIN_VFNMSUBPS,
21220 IX86_BUILTIN_VFNMSUBPD,
21221 IX86_BUILTIN_VFMADDPS256,
21222 IX86_BUILTIN_VFMADDPD256,
21223 IX86_BUILTIN_VFMSUBPS256,
21224 IX86_BUILTIN_VFMSUBPD256,
21225 IX86_BUILTIN_VFMADDSUBPS256,
21226 IX86_BUILTIN_VFMADDSUBPD256,
21227 IX86_BUILTIN_VFMSUBADDPS256,
21228 IX86_BUILTIN_VFMSUBADDPD256,
21229 IX86_BUILTIN_VFNMADDPS256,
21230 IX86_BUILTIN_VFNMADDPD256,
21231 IX86_BUILTIN_VFNMSUBPS256,
21232 IX86_BUILTIN_VFNMSUBPD256,
21234 IX86_BUILTIN_VPCMOV,
21235 IX86_BUILTIN_VPCMOV_V2DI,
21236 IX86_BUILTIN_VPCMOV_V4SI,
21237 IX86_BUILTIN_VPCMOV_V8HI,
21238 IX86_BUILTIN_VPCMOV_V16QI,
21239 IX86_BUILTIN_VPCMOV_V4SF,
21240 IX86_BUILTIN_VPCMOV_V2DF,
21241 IX86_BUILTIN_VPCMOV256,
21242 IX86_BUILTIN_VPCMOV_V4DI256,
21243 IX86_BUILTIN_VPCMOV_V8SI256,
21244 IX86_BUILTIN_VPCMOV_V16HI256,
21245 IX86_BUILTIN_VPCMOV_V32QI256,
21246 IX86_BUILTIN_VPCMOV_V8SF256,
21247 IX86_BUILTIN_VPCMOV_V4DF256,
21249 IX86_BUILTIN_VPPERM,
21251 IX86_BUILTIN_VPMACSSWW,
21252 IX86_BUILTIN_VPMACSWW,
21253 IX86_BUILTIN_VPMACSSWD,
21254 IX86_BUILTIN_VPMACSWD,
21255 IX86_BUILTIN_VPMACSSDD,
21256 IX86_BUILTIN_VPMACSDD,
21257 IX86_BUILTIN_VPMACSSDQL,
21258 IX86_BUILTIN_VPMACSSDQH,
21259 IX86_BUILTIN_VPMACSDQL,
21260 IX86_BUILTIN_VPMACSDQH,
21261 IX86_BUILTIN_VPMADCSSWD,
21262 IX86_BUILTIN_VPMADCSWD,
21264 IX86_BUILTIN_VPHADDBW,
21265 IX86_BUILTIN_VPHADDBD,
21266 IX86_BUILTIN_VPHADDBQ,
21267 IX86_BUILTIN_VPHADDWD,
21268 IX86_BUILTIN_VPHADDWQ,
21269 IX86_BUILTIN_VPHADDDQ,
21270 IX86_BUILTIN_VPHADDUBW,
21271 IX86_BUILTIN_VPHADDUBD,
21272 IX86_BUILTIN_VPHADDUBQ,
21273 IX86_BUILTIN_VPHADDUWD,
21274 IX86_BUILTIN_VPHADDUWQ,
21275 IX86_BUILTIN_VPHADDUDQ,
21276 IX86_BUILTIN_VPHSUBBW,
21277 IX86_BUILTIN_VPHSUBWD,
21278 IX86_BUILTIN_VPHSUBDQ,
21280 IX86_BUILTIN_VPROTB,
21281 IX86_BUILTIN_VPROTW,
21282 IX86_BUILTIN_VPROTD,
21283 IX86_BUILTIN_VPROTQ,
21284 IX86_BUILTIN_VPROTB_IMM,
21285 IX86_BUILTIN_VPROTW_IMM,
21286 IX86_BUILTIN_VPROTD_IMM,
21287 IX86_BUILTIN_VPROTQ_IMM,
21289 IX86_BUILTIN_VPSHLB,
21290 IX86_BUILTIN_VPSHLW,
21291 IX86_BUILTIN_VPSHLD,
21292 IX86_BUILTIN_VPSHLQ,
21293 IX86_BUILTIN_VPSHAB,
21294 IX86_BUILTIN_VPSHAW,
21295 IX86_BUILTIN_VPSHAD,
21296 IX86_BUILTIN_VPSHAQ,
21298 IX86_BUILTIN_VFRCZSS,
21299 IX86_BUILTIN_VFRCZSD,
21300 IX86_BUILTIN_VFRCZPS,
21301 IX86_BUILTIN_VFRCZPD,
21302 IX86_BUILTIN_VFRCZPS256,
21303 IX86_BUILTIN_VFRCZPD256,
21305 IX86_BUILTIN_VPCOMEQUB,
21306 IX86_BUILTIN_VPCOMNEUB,
21307 IX86_BUILTIN_VPCOMLTUB,
21308 IX86_BUILTIN_VPCOMLEUB,
21309 IX86_BUILTIN_VPCOMGTUB,
21310 IX86_BUILTIN_VPCOMGEUB,
21311 IX86_BUILTIN_VPCOMFALSEUB,
21312 IX86_BUILTIN_VPCOMTRUEUB,
21314 IX86_BUILTIN_VPCOMEQUW,
21315 IX86_BUILTIN_VPCOMNEUW,
21316 IX86_BUILTIN_VPCOMLTUW,
21317 IX86_BUILTIN_VPCOMLEUW,
21318 IX86_BUILTIN_VPCOMGTUW,
21319 IX86_BUILTIN_VPCOMGEUW,
21320 IX86_BUILTIN_VPCOMFALSEUW,
21321 IX86_BUILTIN_VPCOMTRUEUW,
21323 IX86_BUILTIN_VPCOMEQUD,
21324 IX86_BUILTIN_VPCOMNEUD,
21325 IX86_BUILTIN_VPCOMLTUD,
21326 IX86_BUILTIN_VPCOMLEUD,
21327 IX86_BUILTIN_VPCOMGTUD,
21328 IX86_BUILTIN_VPCOMGEUD,
21329 IX86_BUILTIN_VPCOMFALSEUD,
21330 IX86_BUILTIN_VPCOMTRUEUD,
21332 IX86_BUILTIN_VPCOMEQUQ,
21333 IX86_BUILTIN_VPCOMNEUQ,
21334 IX86_BUILTIN_VPCOMLTUQ,
21335 IX86_BUILTIN_VPCOMLEUQ,
21336 IX86_BUILTIN_VPCOMGTUQ,
21337 IX86_BUILTIN_VPCOMGEUQ,
21338 IX86_BUILTIN_VPCOMFALSEUQ,
21339 IX86_BUILTIN_VPCOMTRUEUQ,
21341 IX86_BUILTIN_VPCOMEQB,
21342 IX86_BUILTIN_VPCOMNEB,
21343 IX86_BUILTIN_VPCOMLTB,
21344 IX86_BUILTIN_VPCOMLEB,
21345 IX86_BUILTIN_VPCOMGTB,
21346 IX86_BUILTIN_VPCOMGEB,
21347 IX86_BUILTIN_VPCOMFALSEB,
21348 IX86_BUILTIN_VPCOMTRUEB,
21350 IX86_BUILTIN_VPCOMEQW,
21351 IX86_BUILTIN_VPCOMNEW,
21352 IX86_BUILTIN_VPCOMLTW,
21353 IX86_BUILTIN_VPCOMLEW,
21354 IX86_BUILTIN_VPCOMGTW,
21355 IX86_BUILTIN_VPCOMGEW,
21356 IX86_BUILTIN_VPCOMFALSEW,
21357 IX86_BUILTIN_VPCOMTRUEW,
21359 IX86_BUILTIN_VPCOMEQD,
21360 IX86_BUILTIN_VPCOMNED,
21361 IX86_BUILTIN_VPCOMLTD,
21362 IX86_BUILTIN_VPCOMLED,
21363 IX86_BUILTIN_VPCOMGTD,
21364 IX86_BUILTIN_VPCOMGED,
21365 IX86_BUILTIN_VPCOMFALSED,
21366 IX86_BUILTIN_VPCOMTRUED,
21368 IX86_BUILTIN_VPCOMEQQ,
21369 IX86_BUILTIN_VPCOMNEQ,
21370 IX86_BUILTIN_VPCOMLTQ,
21371 IX86_BUILTIN_VPCOMLEQ,
21372 IX86_BUILTIN_VPCOMGTQ,
21373 IX86_BUILTIN_VPCOMGEQ,
21374 IX86_BUILTIN_VPCOMFALSEQ,
21375 IX86_BUILTIN_VPCOMTRUEQ,
21377 /* LWP instructions. */
21378 IX86_BUILTIN_LLWPCB,
21379 IX86_BUILTIN_SLWPCB,
21380 IX86_BUILTIN_LWPVAL32,
21381 IX86_BUILTIN_LWPVAL64,
21382 IX86_BUILTIN_LWPINS32,
21383 IX86_BUILTIN_LWPINS64,
21385 IX86_BUILTIN_CLZS,
21387 IX86_BUILTIN_MAX
21388 };
21390 /* Table for the ix86 builtin decls. */
21393 /* Table of all of the builtin functions that are possible with different ISA's
21394 but are waiting to be built until a function is declared to use that
21395 ISA. */
21402 };
21407 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21408 of which isa_flags to use in the ix86_builtins_isa array. Stores the
21409 function decl in the ix86_builtins array. Returns the function decl or
21410 NULL_TREE, if the builtin was not added.
21412 If the front end has a special hook for builtin functions, delay adding
21413 builtin functions that aren't in the current ISA until the ISA is changed
21414 with function specific optimization. Doing so, can save about 300K for the
21415 default compiler. When the builtin is expanded, check at that time whether
21416 it is valid.
21418 If the front end doesn't have a special hook, record all builtins, even if
21419 it isn't an instruction set in the current ISA in case the user uses
21420 function specific options for a different ISA, so that we don't get scope
21421 errors if a builtin is added in the middle of a function scope. */
21426 {
21430 {
21438 {
21444 }
21445 else
21446 {
21452 }
21453 }
21456 }
21458 /* Like def_builtin, but also marks the function decl "const". */
21463 {
21467 else
21471 }
21473 /* Add any new builtin functions for a given ISA that may not have been
21474 declared. This saves a bit of space compared to adding all of the
21475 declarations to the tree, even if we didn't use them. */
21477 static void
21479 {
21483 {
21486 {
21489 /* Don't define the builtin again. */
21495 NULL_TREE);
21500 }
21501 }
21502 }
21504 /* Bits for builtin_description.flag. */
21506 /* Set when we don't support the comparison natively, and should
21507 swap_comparison in order to support it. */
21508 #define BUILTIN_DESC_SWAP_OPERANDS 1
21510 struct builtin_description
21511 {
21518 };
21521 {
21522 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21523 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21524 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21525 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21526 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21527 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21528 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21529 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21530 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21531 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21532 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21546 };
21549 {
21550 /* SSE4.2 */
21551 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21552 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21553 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21554 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21555 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21556 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21557 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21558 };
21561 {
21562 /* SSE4.2 */
21563 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21564 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21565 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21566 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21567 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21568 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21569 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21570 };
21572 /* Special builtins with variable number of arguments. */
21574 {
21575 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21576 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21578 /* MMX */
21579 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21581 /* 3DNow! */
21582 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21584 /* SSE */
21585 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21586 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21587 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21589 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21590 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21591 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21592 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21594 /* SSE or 3DNow!A */
21595 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21596 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
21598 /* SSE2 */
21599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21602 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21607 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21612 /* SSE3 */
21613 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21615 /* SSE4.1 */
21616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21618 /* SSE4A */
21619 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21620 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21622 /* AVX */
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21628 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21653 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
21654 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
21655 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21656 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21657 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21658 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21660 };
21662 /* Builtins with variable number of arguments. */
21664 {
21665 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21666 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21667 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21668 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21669 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21670 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21671 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21673 /* MMX */
21674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21678 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21681 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21682 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21683 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21684 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21685 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21686 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21687 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21688 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21690 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21691 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21693 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21694 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21695 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21696 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21698 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21699 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21700 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21701 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21702 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21703 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21705 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21706 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21707 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21708 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21709 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21710 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21712 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21713 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21714 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21716 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21718 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21719 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21720 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21721 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21722 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21723 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21725 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21726 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21727 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21728 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21729 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21730 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21732 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21733 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21734 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21735 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21737 /* 3DNow! */
21738 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21739 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21740 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21741 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21743 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21744 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21745 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21746 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21747 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21748 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21749 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21750 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21751 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21752 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21753 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21754 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21755 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21756 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21757 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21759 /* 3DNow!A */
21760 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21761 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21762 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21763 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21764 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21765 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21767 /* SSE */
21768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21770 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21772 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21776 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21777 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21779 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21783 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21784 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21785 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21789 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21790 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21792 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21793 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21797 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21807 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21808 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21809 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21810 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21811 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21812 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21813 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21815 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21816 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21817 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21818 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21820 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21821 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21822 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21823 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21825 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21828 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21829 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21830 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21831 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21834 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21835 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21837 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21839 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21840 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21841 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21843 /* SSE MMX or 3Dnow!A */
21844 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21845 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21846 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21848 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21849 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21850 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21851 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21853 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21854 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21856 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21858 /* SSE2 */
21859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21861 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
21862 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
21864 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
21866 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21867 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
21868 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
21869 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
21870 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
21871 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
21872 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
21874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21879 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21881 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21891 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21892 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21898 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21899 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21900 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21901 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21929 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21933 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21935 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21936 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21938 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21941 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21942 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21944 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21946 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21947 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21948 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21949 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21950 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21951 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21952 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21953 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21958 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21959 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21964 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21965 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21967 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21969 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21970 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21976 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21982 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21983 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21984 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21987 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21988 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21989 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21990 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21991 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21992 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21993 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21994 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21997 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
22000 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
22003 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
22004 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22006 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
22008 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
22009 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
22010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
22011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
22013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22014 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22015 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22016 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22017 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22018 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22019 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
22022 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22023 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22024 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
22025 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22026 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22027 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
22029 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
22030 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
22031 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
22032 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
22034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
22035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
22038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
22040 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
22041 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
22043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22045 /* SSE2 MMX */
22046 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22047 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
22049 /* SSE3 */
22050 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
22051 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
22053 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22054 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22055 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22056 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22057 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
22058 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
22060 /* SSSE3 */
22061 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
22062 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
22063 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22064 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
22065 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
22066 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
22068 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22069 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22070 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22071 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22072 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22073 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22074 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22075 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22076 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22077 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22078 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22079 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22080 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22081 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22082 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22083 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22084 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22085 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22086 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22087 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22088 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22089 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22090 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22091 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22093 /* SSSE3. */
22094 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
22095 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
22097 /* SSE4.1 */
22098 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22099 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22100 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22101 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22102 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22103 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22104 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22105 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22106 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22107 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22109 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22110 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22111 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22112 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22113 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22114 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22115 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22116 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22117 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22118 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22119 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22120 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22121 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22123 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22124 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22125 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22126 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22127 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22128 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22129 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22130 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22131 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22132 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22133 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22134 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22136 /* SSE4.1 */
22137 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22138 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22139 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22140 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22142 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22143 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22144 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22146 /* SSE4.2 */
22147 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22148 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22149 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22150 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22151 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22153 /* SSE4A */
22154 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22155 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22156 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22157 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22159 /* AES */
22160 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22161 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22163 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22164 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22165 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22166 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22168 /* PCLMUL */
22169 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22171 /* AVX */
22172 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22173 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22174 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22175 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22176 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22177 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22179 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22180 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22186 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22187 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22188 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22189 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22190 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22191 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22192 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22193 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22194 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22195 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22196 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22197 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22210 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22213 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22215 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22216 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22219 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22220 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22221 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22222 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22223 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22224 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22225 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22226 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22227 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22230 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22231 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22232 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22234 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22235 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22236 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22237 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22241 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22243 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22244 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22245 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22246 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22247 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22249 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22255 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22262 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22263 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22266 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22267 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22268 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22269 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22270 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22271 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22272 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22273 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22274 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22275 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22276 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22277 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22278 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22279 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22280 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22282 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22283 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22285 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
22286 };
22288 /* FMA4 and XOP. */
22289 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
22290 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
22291 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
22292 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
22293 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
22294 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
22295 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
22296 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
22297 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
22298 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
22299 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
22300 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
22301 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
22302 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
22303 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
22304 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
22305 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
22306 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
22307 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
22308 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
22309 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
22310 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
22311 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
22312 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
22313 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
22314 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
22315 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
22316 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
22317 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
22318 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
22319 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
22320 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
22321 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
22322 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
22323 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
22324 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
22325 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
22326 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
22327 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
22328 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
22329 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
22330 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
22331 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
22332 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
22333 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
22334 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
22335 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
22336 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
22337 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
22338 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
22339 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
22340 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
22343 {
22344 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22345 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22346 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22347 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22348 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22349 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22350 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22351 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22353 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22354 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22355 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22356 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22357 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22358 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22359 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22360 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22362 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22363 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22364 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22365 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22367 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22368 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22369 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22370 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22372 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22373 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22374 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22375 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22377 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22378 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22379 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22380 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
22536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
22537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
22538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
22540 };
22542 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22543 in the current target ISA to allow the user to compile particular modules
22544 with different target specific options that differ from the command line
22545 options. */
22546 static void
22548 {
22553 /* Add all special builtins with variable number of operands. */
22557 {
22563 }
22565 /* Add all builtins with variable number of operands. */
22569 {
22575 }
22577 /* pcmpestr[im] insns. */
22581 {
22584 else
22587 }
22589 /* pcmpistr[im] insns. */
22593 {
22596 else
22599 }
22601 /* comi/ucomi insns. */
22603 {
22606 else
22609 }
22611 /* SSE */
22617 /* SSE or 3DNow!A */
22620 IX86_BUILTIN_MASKMOVQ);
22622 /* SSE2 */
22631 /* SSE3. */
22637 /* AES */
22651 /* PCLMUL */
22655 /* MMX access to the vec_init patterns. */
22660 V4HI_FTYPE_HI_HI_HI_HI,
22661 IX86_BUILTIN_VEC_INIT_V4HI);
22664 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
22665 IX86_BUILTIN_VEC_INIT_V8QI);
22667 /* Access to the vec_extract patterns. */
22689 /* Access to the vec_set patterns. */
22710 /* Add FMA4 multi-arg argument instructions */
22712 {
22718 }
22719 }
22721 /* Internal method for ix86_init_builtins. */
22723 static void
22725 {
22737 sysv_va_ref =
22740 fnvoid_va_end_ms =
22742 fnvoid_va_start_ms =
22744 fnvoid_va_end_sysv =
22746 fnvoid_va_start_sysv =
22748 NULL_TREE);
22749 fnvoid_va_copy_ms =
22751 NULL_TREE);
22752 fnvoid_va_copy_sysv =
22768 }
22770 static void
22772 {
22775 /* The __float80 type. */
22778 {
22779 /* The __float80 type. */
22784 }
22787 /* The __float128 type. */
22793 /* This macro is built by i386-builtin-types.awk. */
22794 DEFINE_BUILTIN_PRIMITIVE_TYPES;
22795 }
22797 static void
22799 {
22800 tree t;
22804 /* TFmode support builtins. */
22810 /* We will expand them to normal call if SSE2 isn't available since
22811 they are used by libgcc. */
22828 }
22830 /* Return the ix86 builtin for CODE. */
22832 static tree
22834 {
22839 }
22841 /* Errors in the source file can cause expand_expr to return const0_rtx
22842 where we expect a vector. To avoid crashing, use one of the vector
22843 clear instructions. */
22844 static rtx
22846 {
22850 }
22852 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
22854 static rtx
22856 {
22857 rtx pat;
22877 {
22881 }
22895 }
22897 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
22899 static rtx
22903 {
22904 rtx pat;
22912 rtx op;
22919 {
22999 }
23009 {
23016 {
23018 {
23021 }
23022 }
23023 else
23024 {
23028 /* If we aren't optimizing, only allow one memory operand to be
23029 generated. */
23031 num_memory++;
23039 }
23043 }
23046 {
23057 else
23058 {
23064 }
23077 }
23084 }
23086 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23087 insns with vec_merge. */
23089 static rtx
23091 rtx target)
23092 {
23093 rtx pat;
23120 }
23122 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23124 static rtx
23127 {
23128 rtx pat;
23133 rtx op2;
23144 /* Swap operands if we have a comparison that isn't available in
23145 hardware. */
23147 {
23152 }
23172 }
23174 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23176 static rtx
23178 rtx target)
23179 {
23180 rtx pat;
23194 /* Swap operands if we have a comparison that isn't available in
23195 hardware. */
23197 {
23201 }
23222 const0_rtx)));
23225 }
23227 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23229 static rtx
23231 rtx target)
23232 {
23233 rtx pat;
23266 const0_rtx)));
23269 }
23271 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23273 static rtx
23276 {
23277 rtx pat;
23315 {
23318 }
23321 {
23330 }
23332 {
23341 }
23342 else
23343 {
23350 }
23358 {
23363 emit_insn
23367 FLAGS_REG),
23368 const0_rtx)));
23370 }
23371 else
23373 }
23376 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23378 static rtx
23381 {
23382 rtx pat;
23410 {
23413 }
23416 {
23425 }
23427 {
23436 }
23437 else
23438 {
23445 }
23453 {
23458 emit_insn
23462 FLAGS_REG),
23463 const0_rtx)));
23465 }
23466 else
23468 }
23470 /* Subroutine of ix86_expand_builtin to take care of insns with
23471 variable number of operands. */
23473 static rtx
23476 {
23481 struct
23482 {
23483 rtx op;
23495 {
23706 }
23711 {
23714 }
23717 {
23724 }
23725 else
23726 {
23729 }
23732 {
23739 {
23740 /* SIMD shift insns take either an 8-bit immediate or
23741 register as count. But builtin functions take int as
23742 count. If count doesn't match, we put it in register. */
23744 {
23748 }
23749 }
23751 {
23754 {
23796 {
23799 {
23802 }
23808 }
23810 }
23811 }
23812 else
23813 {
23817 /* If we aren't optimizing, only allow one memory operand to
23818 be generated. */
23820 num_memory++;
23823 {
23826 }
23827 else
23828 {
23831 }
23832 }
23836 }
23839 {
23856 }
23863 }
23865 /* Subroutine of ix86_expand_builtin to take care of special insns
23866 with variable number of operands. */
23868 static rtx
23871 {
23872 tree arg;
23875 struct
23876 {
23877 rtx op;
23887 {
23924 /* Reserve memory operand for target. */
23947 /* Reserve memory operand for target. */
23961 }
23966 {
23972 }
23973 else
23974 {
23981 }
23984 {
23993 {
23995 {
24001 else
24004 }
24005 }
24006 else
24007 {
24009 {
24010 /* This must be the memory operand. */
24014 }
24015 else
24016 {
24017 /* This must be register. */
24024 }
24025 }
24029 }
24032 {
24047 }
24053 }
24055 /* Return the integer constant in ARG. Constrain it to be in the range
24056 of the subparts of VEC_TYPE; issue an error if not. */
24058 static int
24060 {
24065 {
24068 }
24071 }
24073 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24074 ix86_expand_vector_init. We DO have language-level syntax for this, in
24075 the form of (type){ init-list }. Except that since we can't place emms
24076 instructions from inside the compiler, we can't allow the use of MMX
24077 registers unless the user explicitly asks for it. So we do *not* define
24078 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24079 we have builtins invoked by mmintrin.h that gives us license to emit
24080 these sorts of instructions. */
24082 static rtx
24084 {
24094 {
24097 }
24104 }
24106 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24107 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24108 had a language-level syntax for referencing vector elements. */
24110 static rtx
24112 {
24116 rtx op0;
24136 }
24138 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24139 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24140 a language-level syntax for referencing vector elements. */
24142 static rtx
24144 {
24168 /* OP0 is the source of these builtin functions and shouldn't be
24169 modified. Create a copy, use it and return it as target. */
24175 }
24177 /* Expand an expression EXP that calls a built-in function,
24178 with result going to TARGET if that's convenient
24179 (and in mode MODE if that's convenient).
24180 SUBTARGET may be used as the target for computing one of EXP's operands.
24181 IGNORE is nonzero if the value is to be ignored. */
24183 static rtx
24187 {
24197 /* Determine whether the builtin function is available under the current ISA.
24198 Originally the builtin was not created if it wasn't applicable to the
24199 current ISA based on the command line switches. With function specific
24200 options, we need to check in the context of the function making the call
24201 whether it is supported. */
24204 {
24210 else
24211 {
24215 }
24217 }
24220 {
24224 ? CODE_FOR_mmx_maskmovq
24226 /* Note the arg order is different from the operand order. */
24341 {
24342 REAL_VALUE_TYPE inf;
24343 rtx tmp;
24355 }
24376 }
24389 {
24393 /* Emit a normal call if SSE2 isn't available. */
24397 }
24422 }
24424 /* Returns a function decl for a vectorized version of the builtin function
24425 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24426 if it is not available. */
24428 static tree
24430 tree type_in)
24431 {
24447 {
24485 ;
24486 }
24488 /* Dispatch to a handler for a vectorization library. */
24491 type_in);
24494 }
24496 /* Handler for an SVML-style interface to
24497 a library with vectorized intrinsics. */
24499 static tree
24501 {
24509 /* The SVML is suitable for unsafe math only. */
24522 {
24569 }
24578 {
24581 }
24582 else
24585 /* Convert to uppercase. */
24591 arity++;
24595 else
24598 /* Build a function declaration for the vectorized function. */
24607 }
24609 /* Handler for an ACML-style interface to
24610 a library with vectorized intrinsics. */
24612 static tree
24614 {
24622 /* The ACML is 64bits only and suitable for unsafe math only as
24623 it does not correctly support parts of IEEE with the required
24624 precision such as denormals. */
24638 {
24668 }
24676 arity++;
24680 else
24683 /* Build a function declaration for the vectorized function. */
24692 }
24695 /* Returns a decl of a function that implements conversion of an integer vector
24696 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
24697 are the types involved when converting according to CODE.
24698 Return NULL_TREE if it is not available. */
24700 static tree
24703 {
24708 {
24711 {
24714 {
24721 ? NULL_TREE
24725 }
24729 {
24732 ? NULL_TREE
24736 }
24740 }
24744 {
24747 {
24750 ? NULL_TREE
24754 ? NULL_TREE
24758 }
24763 {
24766 ? NULL_TREE
24770 }
24775 }
24779 }
24782 }
24784 /* Returns a code for a target-specific builtin that implements
24785 reciprocal of the function, or NULL_TREE if not available. */
24787 static tree
24790 {
24797 /* Machine dependent builtins. */
24799 {
24800 /* Vectorized version of sqrt to rsqrt conversion. */
24806 }
24807 else
24808 /* Normal builtins. */
24810 {
24811 /* Sqrt to rsqrt conversion. */
24817 }
24818 }
24819 \f
24820 /* Helper for avx_vpermilps256_operand et al. This is also used by
24821 the expansion functions to turn the parallel back into a mask.
24822 The return value is 0 for no match and the imm8+1 for a match. */
24824 int
24826 {
24834 /* Validate that all of the elements are constants, and not totally
24835 out of range. Copy the data into an integral array to make the
24836 subsequent checks easier. */
24838 {
24848 }
24851 {
24853 /* In the 256-bit DFmode case, we can only move elements within
24854 a 128-bit lane. */
24856 {
24860 }
24862 {
24866 }
24870 /* In the 256-bit SFmode case, we have full freedom of movement
24871 within the low 128-bit lane, but the high 128-bit lane must
24872 mirror the exact same pattern. */
24877 /* FALLTHRU */
24881 /* In the 128-bit case, we've full freedom in the placement of
24882 the elements from the source operand. */
24889 }
24891 /* Make sure success has a non-zero value by adding one. */
24893 }
24895 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
24896 the expansion functions to turn the parallel back into a mask.
24897 The return value is 0 for no match and the imm8+1 for a match. */
24899 int
24901 {
24909 /* Validate that all of the elements are constants, and not totally
24910 out of range. Copy the data into an integral array to make the
24911 subsequent checks easier. */
24913 {
24923 }
24925 /* Validate that the halves of the permute are halves. */
24933 /* Reconstruct the mask. */
24935 {
24941 }
24943 /* Make sure success has a non-zero value by adding one. */
24945 }
24946 \f
24948 /* Store OPERAND to the memory after reload is completed. This means
24949 that we can't easily use assign_stack_local. */
24950 rtx
24952 {
24953 rtx result;
24957 {
24960 stack_pointer_rtx,
24963 }
24965 {
24967 {
24971 /* FALLTHRU */
24977 stack_pointer_rtx)),
24978 operand));
24982 }
24984 }
24985 else
24986 {
24988 {
24990 {
24997 stack_pointer_rtx)),
25003 stack_pointer_rtx)),
25005 }
25008 /* Store HImodes as SImodes. */
25010 /* FALLTHRU */
25016 stack_pointer_rtx)),
25017 operand));
25021 }
25023 }
25025 }
25027 /* Free operand from the memory. */
25028 void
25030 {
25032 {
25037 else
25039 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25040 to pop or add instruction if registers are available. */
25044 }
25045 }
25047 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25048 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25049 same. */
25052 {
25055 };
25058 };
25061 }
25063 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25064 QImode must go into class Q_REGS.
25065 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25066 movdf to do mem-to-mem moves through integer regs. */
25067 enum reg_class
25069 {
25072 /* We're only allowed to return a subclass of CLASS. Many of the
25073 following checks fail for NO_REGS, so eliminate that early. */
25077 /* All classes can load zeros. */
25081 /* Force constants into memory if we are loading a (nonzero) constant into
25082 an MMX or SSE register. This is because there are no MMX/SSE instructions
25083 to load from a constant. */
25088 /* Prefer SSE regs only, if we can use them for math. */
25092 /* Floating-point constants need more complex checks. */
25094 {
25095 /* General regs can load everything. */
25099 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25100 zero above. We only want to wind up preferring 80387 registers if
25101 we plan on doing computation with them. */
25104 {
25105 /* Limit class to non-sse. */
25114 }
25117 }
25119 /* Generally when we see PLUS here, it's the function invariant
25120 (plus soft-fp const_int). Which can only be computed into general
25121 regs. */
25125 /* QImode constants are easy to load, but non-constant QImode data
25126 must go into Q_REGS. */
25128 {
25134 }
25137 }
25139 /* Discourage putting floating-point values in SSE registers unless
25140 SSE math is being used, and likewise for the 387 registers. */
25141 enum reg_class
25143 {
25146 /* Restrict the output reload class to the register bank that we are doing
25147 math on. If we would like not to return a subset of CLASS, reject this
25148 alternative: if reload cannot do this, it will still use its choice. */
25154 {
25159 else
25161 }
25164 }
25166 static enum reg_class
25170 {
25171 /* QImode spills from non-QI registers require
25172 intermediate register on 32bit targets. */
25177 {
25182 else
25188 /* Return Q_REGS if the operand is in memory. */
25191 }
25194 }
25196 /* If we are copying between general and FP registers, we need a memory
25197 location. The same is true for SSE and MMX registers.
25199 To optimize register_move_cost performance, allow inline variant.
25201 The macro can't work reliably when one of the CLASSES is class containing
25202 registers from multiple units (SSE, MMX, integer). We avoid this by never
25203 combining those units in single alternative in the machine description.
25204 Ensure that this constraint holds to avoid unexpected surprises.
25206 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25207 enforce these sanity checks. */
25212 {
25219 {
25222 }
25227 /* ??? This is a lie. We do have moves between mmx/general, and for
25228 mmx/sse2. But by saying we need secondary memory we discourage the
25229 register allocator from using the mmx registers unless needed. */
25234 {
25235 /* SSE1 doesn't have any direct moves from other classes. */
25239 /* If the target says that inter-unit moves are more expensive
25240 than moving through memory, then don't generate them. */
25244 /* Between SSE and general, we have moves no larger than word size. */
25247 }
25250 }
25252 int
25255 {
25257 }
25259 /* Return true if the registers in CLASS cannot represent the change from
25260 modes FROM to TO. */
25262 bool
25265 {
25269 /* x87 registers can't do subreg at all, as all values are reformatted
25270 to extended precision. */
25275 {
25276 /* Vector registers do not support QI or HImode loads. If we don't
25277 disallow a change to these modes, reload will assume it's ok to
25278 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25279 the vec_dupv4hi pattern. */
25283 /* Vector registers do not support subreg with nonzero offsets, which
25284 are otherwise valid for integer registers. Since we can't see
25285 whether we have a nonzero offset from here, prohibit all
25286 nonparadoxical subregs changing size. */
25289 }
25292 }
25294 /* Return the cost of moving data of mode M between a
25295 register and memory. A value of 2 is the default; this cost is
25296 relative to those in `REGISTER_MOVE_COST'.
25298 This function is used extensively by register_move_cost that is used to
25299 build tables at startup. Make it inline in this case.
25300 When IN is 2, return maximum of in and out move cost.
25302 If moving between registers and memory is more expensive than
25303 between two registers, you should define this macro to express the
25304 relative cost.
25306 Model also increased moving costs of QImode registers in non
25307 Q_REGS classes.
25308 */
25312 {
25315 {
25318 {
25330 }
25334 }
25336 {
25339 {
25351 }
25355 }
25357 {
25360 {
25369 }
25373 }
25375 {
25378 {
25384 else
25389 }
25390 else
25391 {
25396 else
25398 }
25405 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25412 else
25416 }
25417 }
25419 int
25421 {
25423 }
25426 /* Return the cost of moving data from a register in class CLASS1 to
25427 one in class CLASS2.
25429 It is not required that the cost always equal 2 when FROM is the same as TO;
25430 on some machines it is expensive to move between registers if they are not
25431 general registers. */
25433 int
25436 {
25437 /* In case we require secondary memory, compute cost of the store followed
25438 by load. In order to avoid bad register allocation choices, we need
25439 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25442 {
25448 /* In case of copying from general_purpose_register we may emit multiple
25449 stores followed by single load causing memory size mismatch stall.
25450 Count this as arbitrarily high cost of 20. */
25454 /* In the case of FP/MMX moves, the registers actually overlap, and we
25455 have to switch modes in order to treat them differently. */
25461 }
25463 /* Moves between SSE/MMX and integer unit are expensive. */
25467 /* ??? By keeping returned value relatively high, we limit the number
25468 of moves between integer and MMX/SSE registers for all targets.
25469 Additionally, high value prevents problem with x86_modes_tieable_p(),
25470 where integer modes in MMX/SSE registers are not tieable
25471 because of missing QImode and HImode moves to, from or between
25472 MMX/SSE registers. */
25482 }
25484 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25486 bool
25488 {
25489 /* Flags and only flags can only hold CCmode values. */
25499 {
25500 /* We implement the move patterns for all vector modes into and
25501 out of SSE registers, even when no operation instructions
25502 are available. OImode move is available only when AVX is
25503 enabled. */
25510 }
25512 {
25513 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25514 so if the register is available at all, then we can move data of
25515 the given mode into or out of it. */
25518 }
25521 {
25522 /* Take care for QImode values - they can be in non-QI regs,
25523 but then they do cause partial register stalls. */
25529 }
25530 /* We handle both integer and floats in the general purpose registers. */
25537 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25538 on to use that value in smaller contexts, this can easily force a
25539 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25540 supporting DImode, allow it. */
25545 }
25547 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25548 tieable integer mode. */
25550 static bool
25552 {
25554 {
25567 }
25568 }
25570 /* Return true if MODE1 is accessible in a register that can hold MODE2
25571 without copying. That is, all register classes that can hold MODE2
25572 can also hold MODE1. */
25574 bool
25576 {
25584 /* MODE2 being XFmode implies fp stack or general regs, which means we
25585 can tie any smaller floating point modes to it. Note that we do not
25586 tie this with TFmode. */
25590 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25591 that we can tie it with SFmode. */
25595 /* If MODE2 is only appropriate for an SSE register, then tie with
25596 any other mode acceptable to SSE registers. */
25602 /* If MODE2 is appropriate for an MMX register, then tie
25603 with any other mode acceptable to MMX registers. */
25610 }
25612 /* Compute a (partial) cost for rtx X. Return true if the complete
25613 cost has been computed, and false if subexpressions should be
25614 scanned. In either case, *TOTAL contains the cost result. */
25616 static bool
25618 {
25624 {
25634 && (!TARGET_64BIT
25639 else
25646 else
25648 {
25657 /* Start with (MEM (SYMBOL_REF)), since that's where
25658 it'll probably end up. Add a penalty for size. */
25663 }
25667 /* The zero extensions is often completely free on x86_64, so make
25668 it as cheap as possible. */
25674 else
25685 {
25688 {
25691 }
25694 {
25697 }
25698 }
25699 /* FALLTHRU */
25706 {
25708 {
25711 else
25713 }
25714 else
25715 {
25718 else
25720 }
25721 }
25722 else
25723 {
25726 else
25728 }
25733 {
25734 /* ??? SSE scalar cost should be used here. */
25737 }
25739 {
25742 }
25744 {
25745 /* ??? SSE vector cost should be used here. */
25748 }
25749 else
25750 {
25755 {
25758 nbits++;
25759 }
25760 else
25761 /* This is arbitrary. */
25764 /* Compute costs correctly for widening multiplication. */
25768 {
25775 {
25779 else
25781 }
25785 }
25792 }
25799 /* ??? SSE cost should be used here. */
25804 /* ??? SSE vector cost should be used here. */
25806 else
25813 {
25818 {
25821 {
25828 }
25829 }
25832 {
25835 {
25840 }
25841 }
25843 {
25849 }
25850 }
25851 /* FALLTHRU */
25855 {
25856 /* ??? SSE cost should be used here. */
25859 }
25861 {
25864 }
25866 {
25867 /* ??? SSE vector cost should be used here. */
25870 }
25871 /* FALLTHRU */
25877 {
25884 }
25885 /* FALLTHRU */
25889 {
25890 /* ??? SSE cost should be used here. */
25893 }
25895 {
25898 }
25900 {
25901 /* ??? SSE vector cost should be used here. */
25904 }
25905 /* FALLTHRU */
25910 else
25919 {
25920 /* This kind of construct is implemented using test[bwl].
25921 Treat it as if we had an AND. */
25926 }
25936 /* ??? SSE cost should be used here. */
25941 /* ??? SSE vector cost should be used here. */
25947 /* ??? SSE cost should be used here. */
25952 /* ??? SSE vector cost should be used here. */
25965 /* ??? Assume all of these vector manipulation patterns are
25966 recognizable. In which case they all pretty much have the
25967 same cost. */
25973 }
25974 }
25976 #if TARGET_MACHO
25980 /* Given a symbol name and its associated stub, write out the
25981 definition of the stub. */
25983 void
25985 {
25990 /* For 64-bit we shouldn't get here. */
25993 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26008 else
26015 {
26019 }
26020 else
26026 {
26029 }
26030 else
26039 }
26042 /* Order the registers for register allocator. */
26044 void
26046 {
26050 /* First allocate the local general purpose registers. */
26055 /* Global general purpose registers. */
26060 /* x87 registers come first in case we are doing FP math
26061 using them. */
26066 /* SSE registers. */
26072 /* x87 registers. */
26080 /* Initialize the rest of array as we do not allocate some registers
26081 at all. */
26084 }
26086 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26087 struct attribute_spec.handler. */
26088 static tree
26090 tree args ATTRIBUTE_UNUSED,
26092 {
26097 {
26099 name);
26102 }
26104 {
26106 name);
26109 }
26111 /* Can combine regparm with all attributes but fastcall. */
26113 {
26115 {
26117 }
26120 }
26122 {
26124 {
26126 }
26129 }
26132 }
26134 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26135 struct attribute_spec.handler. */
26136 static tree
26138 tree args ATTRIBUTE_UNUSED,
26140 {
26143 {
26146 }
26147 else
26152 {
26154 name);
26156 }
26162 {
26164 name);
26166 }
26169 }
26171 static tree
26173 tree args ATTRIBUTE_UNUSED,
26175 {
26177 {
26179 name);
26182 }
26185 {
26187 name);
26189 }
26191 #ifndef HAVE_AS_IX86_SWAP
26193 #endif
26196 }
26198 static bool
26200 {
26204 }
26206 /* Returns an expression indicating where the this parameter is
26207 located on entry to the FUNCTION. */
26209 static rtx
26211 {
26217 {
26222 else
26225 }
26230 {
26236 {
26241 }
26242 else
26243 {
26246 {
26251 }
26252 }
26254 }
26257 }
26259 /* Determine whether x86_output_mi_thunk can succeed. */
26261 static bool
26263 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26265 {
26266 /* 64-bit can handle anything. */
26270 /* For 32-bit, everything's fine if we have one free register. */
26274 /* Need a free register for vcall_offset. */
26278 /* Need a free register for GOT references. */
26282 /* Otherwise ok. */
26284 }
26286 /* Output the assembler code for a thunk function. THUNK_DECL is the
26287 declaration for the thunk function itself, FUNCTION is the decl for
26288 the target function. DELTA is an immediate constant offset to be
26289 added to THIS. If VCALL_OFFSET is nonzero, the word at
26290 *(*this + vcall_offset) should be added to THIS. */
26292 static void
26296 {
26301 /* Make sure unwind info is emitted for the thunk if needed. */
26304 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26305 pull it in now and let DELTA benefit. */
26309 {
26310 /* Put the this parameter into %eax. */
26314 }
26315 else
26318 /* Adjust the this parameter by a fixed constant. */
26320 {
26324 {
26326 {
26332 }
26335 else
26337 }
26340 else
26342 }
26344 /* Adjust the this parameter by a value stored in the vtable. */
26346 {
26349 else
26350 {
26358 }
26364 /* Adjust the this parameter. */
26367 {
26373 }
26376 }
26378 /* If necessary, drop THIS back to its stack slot. */
26380 {
26384 }
26388 {
26391 /* All thunks should be in the same object as their target,
26392 and thus binds_local_p should be true. */
26395 else
26396 {
26402 }
26403 }
26404 else
26405 {
26408 else
26409 #if TARGET_MACHO
26411 {
26413 tmp = (gen_rtx_SYMBOL_REF
26419 }
26420 else
26422 {
26429 }
26430 }
26432 }
26434 static void
26436 {
26438 #if TARGET_MACHO
26440 #endif
26447 }
26449 int
26451 {
26463 }
26465 /* Output assembler code to FILE to increment profiler label # LABELNO
26466 for profiling a function entry. */
26467 void
26469 {
26471 {
26472 #ifndef NO_PROFILE_COUNTERS
26474 #endif
26478 else
26480 }
26482 {
26483 #ifndef NO_PROFILE_COUNTERS
26485 labelno);
26486 #endif
26488 }
26489 else
26490 {
26491 #ifndef NO_PROFILE_COUNTERS
26493 labelno);
26494 #endif
26496 }
26497 }
26499 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26500 /* We don't have exact information about the insn sizes, but we may assume
26501 quite safely that we are informed about all 1 byte insns and memory
26502 address sizes. This is enough to eliminate unnecessary padding in
26503 99% of cases. */
26505 static int
26507 {
26513 /* Discard alignments we've emit and jump instructions. */
26520 /* Important case - calls are always 5 bytes.
26521 It is common to have many calls in the row. */
26530 /* For normal instructions we rely on get_attr_length being exact,
26531 with a few exceptions. */
26533 {
26537 {
26547 /* Otherwise trust get_attr_length. */
26549 }
26554 }
26557 else
26559 }
26561 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26562 window. */
26564 static void
26566 {
26571 /* Look for all minimal intervals of instructions containing 4 jumps.
26572 The intervals are bounded by START and INSN. NBYTES is the total
26573 size of instructions in the interval including INSN and not including
26574 START. When the NBYTES is smaller than 16 bytes, it is possible
26575 that the end of START and INSN ends up in the same 16byte page.
26577 The smallest offset in the page INSN can start is the case where START
26578 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26579 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26580 */
26582 {
26586 {
26592 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26593 already in the current 16 byte page, because otherwise
26594 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26595 bytes to reach 16 byte boundary. */
26603 {
26605 {
26612 else
26615 }
26616 }
26618 }
26629 njumps++;
26630 else
26634 {
26641 else
26644 }
26651 {
26658 }
26659 }
26660 }
26661 #endif
26663 /* AMD Athlon works faster
26664 when RET is not destination of conditional jump or directly preceded
26665 by other jump instruction. We avoid the penalty by inserting NOP just
26666 before the RET instructions in such cases. */
26667 static void
26669 {
26670 edge e;
26671 edge_iterator ei;
26674 {
26677 rtx prev;
26687 {
26688 edge e;
26689 edge_iterator ei;
26695 }
26697 {
26703 /* Empty functions get branch mispredict even when the jump destination
26704 is not visible to us. */
26707 }
26709 {
26712 }
26713 }
26714 }
26716 /* Implement machine specific optimizations. We implement padding of returns
26717 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26718 static void
26720 {
26722 {
26725 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26728 #endif
26729 }
26730 }
26732 /* Return nonzero when QImode register that must be represented via REX prefix
26733 is used. */
26734 bool
26736 {
26744 }
26746 /* Return nonzero when P points to register encoded via REX prefix.
26747 Called via for_each_rtx. */
26748 static int
26750 {
26756 }
26758 /* Return true when INSN mentions register that must be encoded using REX
26759 prefix. */
26760 bool
26762 {
26765 }
26767 /* If profitable, negate (without causing overflow) integer constant
26768 of mode MODE at location LOC. Return true in this case. */
26769 bool
26771 {
26772 HOST_WIDE_INT val;
26778 {
26780 /* DImode x86_64 constants must fit in 32 bits. */
26793 }
26795 /* Avoid overflows. */
26801 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
26802 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
26805 {
26808 }
26811 }
26813 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26814 optabs would emit if we didn't have TFmode patterns. */
26816 void
26818 {
26852 }
26853 \f
26854 /* AVX does not support 32-byte integer vector operations,
26855 thus the longest vector we are faced with is V16QImode. */
26856 #define MAX_VECT_LEN 16
26858 struct expand_vec_perm_d
26859 {
26865 };
26870 /* Get a vector mode of the same size as the original but with elements
26871 twice as wide. This is only guaranteed to apply to integral vectors. */
26875 {
26876 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
26881 }
26883 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26884 with all elements equal to VAR. Return true if successful. */
26886 static bool
26889 {
26893 {
26898 /* FALLTHRU */
26908 {
26911 /* First attempt to recognize VAL as-is. */
26915 {
26916 rtx seq;
26917 /* If that fails, force VAL into a register. */
26928 }
26929 }
26936 {
26937 rtx x;
26944 }
26954 {
26958 permute:
26965 /* Extend to SImode using a paradoxical SUBREG. */
26969 /* Insert the SImode value as low element of a V4SImode vector. */
26977 }
26985 widen:
26986 /* Replicate the value once into the next wider mode and recurse. */
26987 {
26989 rtx x;
27005 }
27009 {
27018 }
27023 }
27024 }
27026 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27027 whose ONE_VAR element is VAR, and other elements are zero. Return true
27028 if successful. */
27030 static bool
27033 {
27035 rtx new_target;
27040 {
27042 /* For SSE4.1, we normally use vector set. But if the second
27043 element is zero and inter-unit moves are OK, we use movq
27044 instead. */
27045 use_vector_set = (TARGET_64BIT
27046 && TARGET_SSE4_1
27047 && !(TARGET_INTER_UNIT_MOVES
27069 /* Use ix86_expand_vector_set in 64bit mode only. */
27074 }
27077 {
27082 }
27085 {
27090 /* FALLTHRU */
27105 else
27112 {
27113 /* We need to shuffle the value to the correct position, so
27114 create a new pseudo to store the intermediate result. */
27116 /* With SSE2, we can use the integer shuffle insns. */
27118 {
27120 const1_rtx,
27127 }
27129 /* Otherwise convert the intermediate result to V4SFmode and
27130 use the SSE1 shuffle instructions. */
27132 {
27135 }
27136 else
27140 const1_rtx,
27149 }
27164 widen:
27168 /* Zero extend the variable element to SImode and recurse. */
27181 }
27182 }
27184 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27185 consisting of the values in VALS. It is known that all elements
27186 except ONE_VAR are constants. Return true if successful. */
27188 static bool
27191 {
27201 {
27206 /* For the two element vectors, it's just as easy to use
27207 the general case. */
27211 /* Use ix86_expand_vector_set in 64bit mode only. */
27233 widen:
27234 /* There's no way to set one QImode entry easily. Combine
27235 the variable value with its adjacent constant value, and
27236 promote to an HImode set. */
27239 {
27244 }
27245 else
27246 {
27249 }
27263 }
27268 }
27270 /* A subroutine of ix86_expand_vector_init_general. Use vector
27271 concatenate to handle the most general case: all values variable,
27272 and none identical. */
27274 static void
27277 {
27280 rtvec v;
27284 {
27287 {
27320 }
27333 {
27348 }
27353 {
27364 }
27367 half:
27368 /* FIXME: We process inputs backward to help RA. PR 36222. */
27372 {
27377 }
27381 {
27384 {
27388 }
27391 }
27392 else
27398 }
27399 }
27401 /* A subroutine of ix86_expand_vector_init_general. Use vector
27402 interleave to handle the most general case: all values variable,
27403 and none identical. */
27405 static void
27408 {
27417 {
27438 }
27441 {
27442 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27446 /* Insert the SImode value as low element of V4SImode vector. */
27450 op0),
27452 const1_rtx);
27455 /* Cast the V4SImode vector back to a vector in orignal mode. */
27459 /* Load even elements into the second positon. */
27463 const1_rtx));
27465 /* Cast vector to FIRST_IMODE vector. */
27468 }
27470 /* Interleave low FIRST_IMODE vectors. */
27472 {
27476 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27479 }
27481 /* Interleave low SECOND_IMODE vectors. */
27483 {
27486 {
27491 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27492 vector. */
27495 }
27498 /* FALLTHRU */
27505 /* Cast the SECOND_IMODE vector back to a vector on original
27506 mode. */
27513 }
27514 }
27516 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27517 all values variable, and none identical. */
27519 static void
27522 {
27528 {
27533 /* FALLTHRU */
27557 half:
27574 /* FALLTHRU */
27580 /* Don't use ix86_expand_vector_init_interleave if we can't
27581 move from GPR to SSE register directly. */
27597 }
27599 {
27611 {
27615 {
27621 else
27622 {
27627 }
27628 }
27631 }
27636 {
27642 }
27644 {
27650 }
27651 else
27653 }
27654 }
27656 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27657 instructions unless MMX_OK is true. */
27659 void
27661 {
27668 rtx x;
27671 {
27681 }
27683 /* Constants are best loaded from the constant pool. */
27685 {
27688 }
27690 /* If all values are identical, broadcast the value. */
27696 /* Values where only one field is non-constant are best loaded from
27697 the pool and overwritten via move later. */
27699 {
27703 one_var))
27708 }
27711 }
27713 void
27715 {
27720 rtx tmp;
27722 = {
27729 };
27731 = {
27738 };
27742 {
27746 {
27751 else
27755 }
27764 {
27767 /* For the two element vectors, we implement a VEC_CONCAT with
27768 the extraction of the other element. */
27775 else
27780 }
27789 {
27795 /* tmp = target = A B C D */
27797 /* target = A A B B */
27799 /* target = X A B B */
27801 /* target = A X C D */
27808 /* tmp = target = A B C D */
27810 /* tmp = X B C D */
27812 /* target = A B X D */
27819 /* tmp = target = A B C D */
27821 /* tmp = X B C D */
27823 /* target = A B X D */
27831 }
27839 /* Element 0 handled by vec_merge below. */
27841 {
27844 }
27847 {
27848 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27849 store into element 0, then shuffle them back. */
27866 }
27867 else
27868 {
27869 /* For SSE1, we have to reuse the V4SF code. */
27872 }
27925 half:
27926 /* Compute offset. */
27932 /* Extract the half. */
27936 /* Put val in tmp at elt. */
27939 /* Put it back. */
27945 }
27948 {
27952 }
27953 else
27954 {
27963 }
27964 }
27966 void
27968 {
27972 rtx tmp;
27975 {
27980 /* FALLTHRU */
27993 {
28013 }
28025 {
28027 {
28047 }
28051 }
28052 else
28053 {
28054 /* For SSE1, we have to reuse the V4SF code. */
28058 }
28073 /* ??? Could extract the appropriate HImode element and shift. */
28076 }
28079 {
28083 /* Let the rtl optimizers know about the zero extension performed. */
28085 {
28088 }
28091 }
28092 else
28093 {
28100 }
28101 }
28103 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28104 pattern to reduce; DEST is the destination; IN is the input vector. */
28106 void
28108 {
28122 }
28123 \f
28124 /* Target hook for scalar_mode_supported_p. */
28125 static bool
28127 {
28132 else
28134 }
28136 /* Implements target hook vector_mode_supported_p. */
28137 static bool
28139 {
28151 }
28153 /* Target hook for c_mode_for_suffix. */
28154 static enum machine_mode
28156 {
28163 }
28165 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28167 We do this in the new i386 backend to maintain source compatibility
28168 with the old cc0-based compiler. */
28170 static tree
28172 tree inputs ATTRIBUTE_UNUSED,
28173 tree clobbers)
28174 {
28176 clobbers);
28178 clobbers);
28180 }
28182 /* Implements target vector targetm.asm.encode_section_info. This
28183 is not used by netware. */
28185 static void ATTRIBUTE_UNUSED
28187 {
28194 }
28196 /* Worker function for REVERSE_CONDITION. */
28198 enum rtx_code
28200 {
28204 }
28206 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28207 to OPERANDS[0]. */
28211 {
28213 {
28216 {
28220 }
28224 }
28226 {
28230 else
28231 {
28232 /* There is no non-popping store to memory for XFmode.
28233 So if we need one, follow the store with a load. */
28236 else
28238 }
28239 }
28240 else
28242 }
28244 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28245 FP status register is set. */
28247 void
28249 {
28251 rtx temp;
28256 {
28261 }
28262 else
28263 {
28268 }
28272 pc_rtx);
28277 }
28279 /* Output code to perform a log1p XFmode calculation. */
28282 {
28288 rtx test;
28294 XFmode));
28308 }
28310 /* Output code to perform a Newton-Rhapson approximation of a single precision
28311 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28314 {
28329 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28331 /* x0 = rcp(b) estimate */
28334 UNSPEC_RCP)));
28335 /* e0 = x0 * a */
28338 /* e1 = x0 * b */
28341 /* x1 = 2. - e1 */
28344 /* res = e0 * x1 */
28347 }
28349 /* Output code to perform a Newton-Rhapson approximation of a
28350 single precision floating point [reciprocal] square root. */
28354 {
28356 REAL_VALUE_TYPE r;
28371 {
28374 }
28376 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28377 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28379 /* x0 = rsqrt(a) estimate */
28382 UNSPEC_RSQRT)));
28384 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28386 {
28398 }
28400 /* e0 = x0 * a */
28403 /* e1 = e0 * x0 */
28407 /* e2 = e1 - 3. */
28414 /* e3 = -.5 * x0 */
28417 else
28418 /* e3 = -.5 * e0 */
28421 /* ret = e2 * e3 */
28424 }
28426 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28428 static void ATTRIBUTE_UNUSED
28430 tree decl)
28431 {
28432 /* With Binutils 2.15, the "@unwind" marker must be specified on
28433 every occurrence of the ".eh_frame" section, not just the first
28434 one. */
28437 {
28441 }
28443 }
28445 /* Return the mangling of TYPE if it is an extended fundamental type. */
28449 {
28457 {
28459 /* __float128 is "g". */
28462 /* "long double" or __float80 is "e". */
28466 }
28467 }
28469 /* For 32-bit code we can save PIC register setup by using
28470 __stack_chk_fail_local hidden function instead of calling
28471 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28472 register, so it is better to call __stack_chk_fail directly. */
28474 static tree
28476 {
28477 return TARGET_64BIT
28480 }
28482 /* Select a format to encode pointers in exception handling data. CODE
28483 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28484 true if the symbol may be affected by dynamic relocations.
28486 ??? All x86 object file formats are capable of representing this.
28487 After all, the relocation needed is the same as for the call insn.
28488 Whether or not a particular assembler allows us to enter such, I
28489 guess we'll have to see. */
28490 int
28492 {
28494 {
28501 }
28506 }
28507 \f
28508 /* Expand copysign from SIGN to the positive value ABS_VALUE
28509 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28510 the sign-bit. */
28511 static void
28513 {
28517 {
28520 {
28521 /* We need to generate a scalar mode mask in this case. */
28526 }
28527 }
28528 else
28534 }
28536 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28537 mask for masking out the sign-bit is stored in *SMASK, if that is
28538 non-null. */
28539 static rtx
28541 {
28548 {
28549 /* We need to generate a scalar mode mask in this case. */
28554 }
28562 }
28564 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28565 swapping the operands if SWAP_OPERANDS is true. The expanded
28566 code is a forward jump to a newly created label in case the
28567 comparison is true. The generated label rtx is returned. */
28568 static rtx
28571 {
28575 {
28579 }
28592 }
28594 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28595 using comparison code CODE. Operands are swapped for the comparison if
28596 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28597 static rtx
28600 {
28605 {
28609 }
28614 else
28619 }
28621 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28622 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28623 static rtx
28625 {
28626 REAL_VALUE_TYPE TWO52r;
28627 rtx TWO52;
28634 }
28636 /* Expand SSE sequence for computing lround from OP1 storing
28637 into OP0. */
28638 void
28640 {
28641 /* C code for the stuff we're doing below:
28642 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28643 return (long)tmp;
28644 */
28648 rtx adj;
28650 /* load nextafter (0.5, 0.0) */
28655 /* adj = copysign (0.5, op1) */
28659 /* adj = op1 + adj */
28662 /* op0 = (imode)adj */
28664 }
28666 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28667 into OPERAND0. */
28668 void
28670 {
28671 /* C code for the stuff we're doing below (for do_floor):
28672 xi = (long)op1;
28673 xi -= (double)xi > op1 ? 1 : 0;
28674 return xi;
28675 */
28680 /* reg = (long)op1 */
28684 /* freg = (double)reg */
28688 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28699 }
28701 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28702 result in OPERAND0. */
28703 void
28705 {
28706 /* C code for the stuff we're doing below:
28707 xa = fabs (operand1);
28708 if (!isless (xa, 2**52))
28709 return operand1;
28710 xa = xa + 2**52 - 2**52;
28711 return copysign (xa, operand1);
28712 */
28719 /* xa = abs (operand1) */
28722 /* if (!isless (xa, TWO52)) goto label; */
28735 }
28737 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28738 into OPERAND0. */
28739 void
28741 {
28742 /* C code for the stuff we expand below.
28743 double xa = fabs (x), x2;
28744 if (!isless (xa, TWO52))
28745 return x;
28746 xa = xa + TWO52 - TWO52;
28747 x2 = copysign (xa, x);
28748 Compensate. Floor:
28749 if (x2 > x)
28750 x2 -= 1;
28751 Compensate. Ceil:
28752 if (x2 < x)
28753 x2 -= -1;
28754 return x2;
28755 */
28761 /* Temporary for holding the result, initialized to the input
28762 operand to ease control flow. */
28766 /* xa = abs (operand1) */
28769 /* if (!isless (xa, TWO52)) goto label; */
28772 /* xa = xa + TWO52 - TWO52; */
28776 /* xa = copysign (xa, operand1) */
28779 /* generate 1.0 or -1.0 */
28784 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28788 /* We always need to subtract here to preserve signed zero. */
28797 }
28799 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28800 into OPERAND0. */
28801 void
28803 {
28804 /* C code for the stuff we expand below.
28805 double xa = fabs (x), x2;
28806 if (!isless (xa, TWO52))
28807 return x;
28808 x2 = (double)(long)x;
28809 Compensate. Floor:
28810 if (x2 > x)
28811 x2 -= 1;
28812 Compensate. Ceil:
28813 if (x2 < x)
28814 x2 += 1;
28815 if (HONOR_SIGNED_ZEROS (mode))
28816 return copysign (x2, x);
28817 return x2;
28818 */
28824 /* Temporary for holding the result, initialized to the input
28825 operand to ease control flow. */
28829 /* xa = abs (operand1) */
28832 /* if (!isless (xa, TWO52)) goto label; */
28835 /* xa = (double)(long)x */
28840 /* generate 1.0 */
28843 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28858 }
28860 /* Expand SSE sequence for computing round from OPERAND1 storing
28861 into OPERAND0. Sequence that works without relying on DImode truncation
28862 via cvttsd2siq that is only available on 64bit targets. */
28863 void
28865 {
28866 /* C code for the stuff we expand below.
28867 double xa = fabs (x), xa2, x2;
28868 if (!isless (xa, TWO52))
28869 return x;
28870 Using the absolute value and copying back sign makes
28871 -0.0 -> -0.0 correct.
28872 xa2 = xa + TWO52 - TWO52;
28873 Compensate.
28874 dxa = xa2 - xa;
28875 if (dxa <= -0.5)
28876 xa2 += 1;
28877 else if (dxa > 0.5)
28878 xa2 -= 1;
28879 x2 = copysign (xa2, x);
28880 return x2;
28881 */
28887 /* Temporary for holding the result, initialized to the input
28888 operand to ease control flow. */
28892 /* xa = abs (operand1) */
28895 /* if (!isless (xa, TWO52)) goto label; */
28898 /* xa2 = xa + TWO52 - TWO52; */
28902 /* dxa = xa2 - xa; */
28905 /* generate 0.5, 1.0 and -0.5 */
28911 /* Compensate. */
28913 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28918 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28924 /* res = copysign (xa2, operand1) */
28931 }
28933 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28934 into OPERAND0. */
28935 void
28937 {
28938 /* C code for SSE variant we expand below.
28939 double xa = fabs (x), x2;
28940 if (!isless (xa, TWO52))
28941 return x;
28942 x2 = (double)(long)x;
28943 if (HONOR_SIGNED_ZEROS (mode))
28944 return copysign (x2, x);
28945 return x2;
28946 */
28952 /* Temporary for holding the result, initialized to the input
28953 operand to ease control flow. */
28957 /* xa = abs (operand1) */
28960 /* if (!isless (xa, TWO52)) goto label; */
28963 /* x = (double)(long)x */
28975 }
28977 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28978 into OPERAND0. */
28979 void
28981 {
28985 /* C code for SSE variant we expand below.
28986 double xa = fabs (x), x2;
28987 if (!isless (xa, TWO52))
28988 return x;
28989 xa2 = xa + TWO52 - TWO52;
28990 Compensate:
28991 if (xa2 > xa)
28992 xa2 -= 1.0;
28993 x2 = copysign (xa2, x);
28994 return x2;
28995 */
28999 /* Temporary for holding the result, initialized to the input
29000 operand to ease control flow. */
29004 /* xa = abs (operand1) */
29007 /* if (!isless (xa, TWO52)) goto label; */
29010 /* res = xa + TWO52 - TWO52; */
29015 /* generate 1.0 */
29018 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29026 /* res = copysign (res, operand1) */
29033 }
29035 /* Expand SSE sequence for computing round from OPERAND1 storing
29036 into OPERAND0. */
29037 void
29039 {
29040 /* C code for the stuff we're doing below:
29041 double xa = fabs (x);
29042 if (!isless (xa, TWO52))
29043 return x;
29044 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29045 return copysign (xa, x);
29046 */
29052 /* Temporary for holding the result, initialized to the input
29053 operand to ease control flow. */
29061 /* load nextafter (0.5, 0.0) */
29066 /* xa = xa + 0.5 */
29070 /* xa = (double)(int64_t)xa */
29075 /* res = copysign (xa, operand1) */
29082 }
29083 \f
29085 /* Table of valid machine attributes. */
29087 {
29088 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29089 /* Stdcall attribute says callee is responsible for popping arguments
29090 if they are not variable. */
29092 /* Fastcall attribute says callee is responsible for popping arguments
29093 if they are not variable. */
29095 /* Thiscall attribute says callee is responsible for popping arguments
29096 if they are not variable. */
29098 /* Cdecl attribute says the callee is a normal C declaration */
29100 /* Regparm attribute specifies how many integer arguments are to be
29101 passed in registers. */
29103 /* Sseregparm attribute says we are using x86_64 calling conventions
29104 for FP arguments. */
29106 /* force_align_arg_pointer says this function realigns the stack at entry. */
29109 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29113 #endif
29116 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29117 SUBTARGET_ATTRIBUTE_TABLE,
29118 #endif
29119 /* ms_abi and sysv_abi calling convention function attributes. */
29123 /* End element. */
29125 };
29127 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29128 static int
29130 {
29131 /* If the branch of the runtime test is taken - i.e. - the vectorized
29132 version is skipped - this incurs a misprediction cost (because the
29133 vectorized version is expected to be the fall-through). So we subtract
29134 the latency of a mispredicted branch from the costs that are incured
29135 when the vectorized version is executed.
29137 TODO: The values in individual target tables have to be tuned or new
29138 fields may be needed. For eg. on K8, the default branch path is the
29139 not-taken path. If the taken path is predicted correctly, the minimum
29140 penalty of going down the taken-path is 1 cycle. If the taken-path is
29141 not predicted correctly, then the minimum penalty is 10 cycles. */
29144 {
29146 }
29147 else
29149 }
29151 /* Implement targetm.vectorize.builtin_vec_perm. */
29153 static tree
29155 {
29163 {
29170 get_di:
29181 get_si:
29200 }
29207 }
29209 /* Return a vector mode with twice as many elements as VMODE. */
29210 /* ??? Consider moving this to a table generated by genmodes.c. */
29212 static enum machine_mode
29214 {
29216 {
29239 }
29240 }
29242 /* Construct (set target (vec_select op0 (parallel perm))) and
29243 return true if that's a valid instruction in the active ISA. */
29245 static bool
29247 {
29260 {
29263 }
29265 }
29267 /* Similar, but generate a vec_concat from op0 and op1 as well. */
29269 static bool
29272 {
29274 rtx x;
29279 }
29281 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29282 in terms of blendp[sd] / pblendw / pblendvb. */
29284 static bool
29286 {
29296 /* This is a blend, not a permute. Elements must stay in their
29297 respective lanes. */
29299 {
29303 }
29308 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
29309 decision should be extracted elsewhere, so that we only try that
29310 sequence once all budget==3 options have been tried. */
29312 /* For bytes, see if bytes move in pairs so we can use pblendw with
29313 an immediate argument, rather than pblendvb with a vector argument. */
29315 {
29321 {
29332 }
29333 }
29341 {
29365 do_subreg:
29374 }
29376 /* This matches five different patterns with the different modes. */
29382 }
29384 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29385 in terms of the variable form of vpermilps.
29387 Note that we will have already failed the immediate input vpermilps,
29388 which requires that the high and low part shuffle be identical; the
29389 variable form doesn't require that. */
29391 static bool
29393 {
29400 /* We can only permute within the 128-bit lane. */
29402 {
29406 }
29412 {
29415 /* Within each 128-bit lane, the elements of op0 are numbered
29416 from 0 and the elements of op1 are numbered from 4. */
29423 }
29430 }
29432 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29433 in terms of pshufb or vpperm. */
29435 static bool
29437 {
29453 {
29457 }
29466 else
29467 {
29470 }
29473 }
29475 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
29476 in a single instruction. */
29478 static bool
29480 {
29484 /* Check plain VEC_SELECT first, because AVX has instructions that could
29485 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
29486 input where SEL+CONCAT may not. */
29488 {
29497 /* There are plenty of patterns in sse.md that are written for
29498 SEL+CONCAT and are not replicated for a single op. Perhaps
29499 that should be changed, to avoid the nastiness here. */
29501 /* Recognize interleave style patterns, which means incrementing
29502 every other permutation operand. */
29504 {
29507 }
29511 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
29513 {
29515 {
29520 }
29524 }
29525 }
29527 /* Finally, try the fully general two operand permute. */
29531 /* Recognize interleave style patterns with reversed operands. */
29533 {
29535 {
29539 else
29542 }
29546 }
29548 /* Try the SSE4.1 blend variable merge instructions. */
29552 /* Try one of the AVX vpermil variable permutations. */
29556 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
29561 }
29563 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
29564 in terms of a pair of pshuflw + pshufhw instructions. */
29566 static bool
29568 {
29576 /* The two permutations only operate in 64-bit lanes. */
29587 /* Emit the pshuflw. */
29594 /* Emit the pshufhw. */
29602 }
29604 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29605 the permutation using the SSSE3 palignr instruction. This succeeds
29606 when all of the elements in PERM fit within one vector and we merely
29607 need to shift them down so that a single vector permutation has a
29608 chance to succeed. */
29610 static bool
29612 {
29616 rtx shift;
29618 /* Even with AVX, palignr only operates on 128-bit vectors. */
29624 {
29630 }
29634 /* Given that we have SSSE3, we know we'll be able to implement the
29635 single operand permutation after the palignr with pshufb. */
29648 {
29653 }
29655 /* Test for the degenerate case where the alignment by itself
29656 produces the desired permutation. */
29664 }
29666 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
29667 a two vector permutation into a single vector permutation by using
29668 an interleave operation to merge the vectors. */
29670 static bool
29672 {
29677 rtx seq;
29683 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
29684 lanes. We can use similar techniques with the vperm2f128 instruction,
29685 but it requires slightly different logic. */
29689 /* Examine from whence the elements come. */
29694 /* Split the two input vectors into 4 halves. */
29703 /* If the elements from the low halves use interleave low, and similarly
29704 for interleave high. If the elements are from mis-matched halves, we
29705 can use shufps for V4SF/V4SI or do a DImode shuffle. */
29707 {
29709 {
29714 }
29715 }
29717 {
29719 {
29724 }
29725 }
29727 {
29729 {
29734 }
29736 {
29741 }
29742 }
29744 {
29746 {
29751 }
29753 {
29758 }
29759 }
29760 else
29763 /* Use the remapping array set up above to move the elements from their
29764 swizzled locations into their final destinations. */
29767 {
29771 }
29776 /* Test if the final remap can be done with a single insn. For V4SFmode or
29777 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
29787 {
29791 }
29798 }
29800 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
29801 permutation with two pshufb insns and an ior. We should have already
29802 failed all two instruction sequences. */
29804 static bool
29806 {
29817 /* Generate two permutation masks. If the required element is within
29818 the given vector it is shuffled into the proper lane. If the required
29819 element is in the other vector, force a zero into the lane by setting
29820 bit 7 in the permutation mask. */
29823 {
29830 {
29833 }
29834 }
29854 }
29856 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
29857 and extract-odd permutations. */
29859 static bool
29861 {
29865 {
29870 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
29874 /* Now an unpck[lh]pd will produce the result required. */
29877 else
29883 {
29893 /* Shuffle within the 128-bit lanes to produce:
29894 { 0 2 1 3 4 6 5 7 } and { 8 a 9 b c e d f }. */
29898 /* Shuffle the lanes around to produce:
29899 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
29903 /* Now a vpermil2p will produce the result required. */
29904 /* ??? The vpermil2p requires a vector constant. Another option
29905 is a unpck[lh]ps to merge the two vectors to produce
29906 { 0 4 2 6 8 c a e } or { 1 5 3 7 9 d b f }. Then use another
29907 vpermilps to get the elements into the final order. */
29912 }
29919 /* These are always directly implementable by expand_vec_perm_1. */
29925 else
29926 {
29927 /* We need 2*log2(N)-1 operations to achieve odd/even
29928 with interleave. */
29937 else
29940 }
29946 else
29947 {
29959 else
29962 }
29967 }
29970 }
29972 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
29973 extract-even and extract-odd permutations. */
29975 static bool
29977 {
29989 }
29991 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
29992 permutations. We assume that expand_vec_perm_1 has already failed. */
29994 static bool
29996 {
30004 {
30007 /* These are special-cased in sse.md so that we can optionally
30008 use the vbroadcast instruction. They expand to two insns
30009 if the input happens to be in a register. */
30016 /* These are always implementable using standard shuffle patterns. */
30021 /* These can be implemented via interleave. We save one insn by
30022 stopping once we have promoted to V4SImode and then use pshufd. */
30023 do
30024 {
30028 {
30031 }
30037 }
30047 }
30048 }
30050 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
30051 broadcast permutations. */
30053 static bool
30055 {
30067 }
30069 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
30070 With all of the interface bits taken care of, perform the expansion
30071 in D and return true on success. */
30073 static bool
30075 {
30076 /* Try a single instruction expansion. */
30080 /* Try sequences of two instructions. */
30094 /* Try sequences of three instructions. */
30099 /* ??? Look for narrow permutations whose element orderings would
30100 allow the promotion to a wider mode. */
30102 /* ??? Look for sequences of interleave or a wider permute that place
30103 the data into the correct lanes for a half-vector shuffle like
30104 pshuf[lh]w or vpermilps. */
30106 /* ??? Look for sequences of interleave that produce the desired results.
30107 The combinatorics of punpck[lh] get pretty ugly... */
30113 }
30115 /* Extract the values from the vector CST into the permutation array in D.
30116 Return 0 on error, 1 if all values from the permutation come from the
30117 first vector, 2 if all values from the second vector, and 3 otherwise. */
30119 static int
30121 {
30127 {
30138 }
30141 /* For all elements from second vector, fold the elements to first. */
30147 }
30149 static rtx
30151 {
30165 {
30169 }
30172 {
30182 {
30188 }
30190 /* The elements of PERM do not suggest that only the first operand
30191 is used, but both operands are identical. Allow easier matching
30192 of the permutation by folding the permutation into the single
30193 input vector. */
30194 {
30199 }
30200 /* FALLTHRU */
30213 }
30219 /* For compiler generated permutations, we should never got here, because
30220 the compiler should also be checking the ok hook. But since this is a
30221 builtin the user has access too, so don't abort. */
30223 {
30246 }
30247 exit_error:
30249 }
30251 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
30253 static bool
30255 {
30264 /* Given sufficient ISA support we can just return true here
30265 for selected vector modes. */
30267 {
30268 /* All implementable with a single vpperm insn. */
30271 /* All implementable with 2 pshufb + 1 ior. */
30274 /* All implementable with shufpd or unpck[lh]pd. */
30277 }
30281 /* This hook is cannot be called in response to something that the
30282 user does (unlike the builtin expander) so we shouldn't ever see
30283 an error generated from the extract. */
30287 /* Implementable with shufps or pshufd. */
30291 /* Otherwise we have to go through the motions and see if we can
30292 figure out how to generate the requested permutation. */
30303 }
30305 void
30307 {
30321 /* We'll either be able to implement the permutation directly... */
30325 /* ... or we use the special-case patterns. */
30327 }
30328 \f
30329 /* This function returns the calling abi specific va_list type node.
30330 It returns the FNDECL specific va_list type. */
30332 tree
30334 {
30341 else
30343 }
30345 /* Returns the canonical va_list type specified by TYPE. If there
30346 is no valid TYPE provided, it return NULL_TREE. */
30348 tree
30350 {
30353 /* Resolve references and pointers to va_list type. */
30360 {
30365 {
30366 /* If va_list is an array type, the argument may have decayed
30367 to a pointer type, e.g. by being passed to another function.
30368 In that case, unwrap both types so that we can compare the
30369 underlying records. */
30372 {
30375 }
30376 }
30383 {
30384 /* If va_list is an array type, the argument may have decayed
30385 to a pointer type, e.g. by being passed to another function.
30386 In that case, unwrap both types so that we can compare the
30387 underlying records. */
30390 {
30393 }
30394 }
30401 {
30402 /* If va_list is an array type, the argument may have decayed
30403 to a pointer type, e.g. by being passed to another function.
30404 In that case, unwrap both types so that we can compare the
30405 underlying records. */
30408 {
30411 }
30412 }
30416 }
30418 }
30420 /* Iterate through the target-specific builtin types for va_list.
30421 IDX denotes the iterator, *PTREE is set to the result type of
30422 the va_list builtin, and *PNAME to its internal type.
30423 Returns zero if there is no element for this index, otherwise
30424 IDX should be increased upon the next call.
30425 Note, do not iterate a base builtin's name like __builtin_va_list.
30426 Used from c_common_nodes_and_builtins. */
30428 int
30430 {
30444 }
30446 }
30448 /* Initialize the GCC target structure. */
30449 #undef TARGET_RETURN_IN_MEMORY
30450 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30452 #undef TARGET_LEGITIMIZE_ADDRESS
30453 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30455 #undef TARGET_ATTRIBUTE_TABLE
30456 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30457 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30458 # undef TARGET_MERGE_DECL_ATTRIBUTES
30459 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30460 #endif
30462 #undef TARGET_COMP_TYPE_ATTRIBUTES
30463 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30465 #undef TARGET_INIT_BUILTINS
30466 #define TARGET_INIT_BUILTINS ix86_init_builtins
30467 #undef TARGET_BUILTIN_DECL
30468 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30469 #undef TARGET_EXPAND_BUILTIN
30470 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30472 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30473 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30474 ix86_builtin_vectorized_function
30476 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30477 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30479 #undef TARGET_BUILTIN_RECIPROCAL
30480 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30482 #undef TARGET_ASM_FUNCTION_EPILOGUE
30483 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30485 #undef TARGET_ENCODE_SECTION_INFO
30486 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30487 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30488 #else
30489 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30490 #endif
30492 #undef TARGET_ASM_OPEN_PAREN
30494 #undef TARGET_ASM_CLOSE_PAREN
30497 #undef TARGET_ASM_BYTE_OP
30498 #define TARGET_ASM_BYTE_OP ASM_BYTE
30500 #undef TARGET_ASM_ALIGNED_HI_OP
30501 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30502 #undef TARGET_ASM_ALIGNED_SI_OP
30503 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30504 #ifdef ASM_QUAD
30505 #undef TARGET_ASM_ALIGNED_DI_OP
30506 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30507 #endif
30509 #undef TARGET_ASM_UNALIGNED_HI_OP
30510 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30511 #undef TARGET_ASM_UNALIGNED_SI_OP
30512 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30513 #undef TARGET_ASM_UNALIGNED_DI_OP
30514 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30516 #undef TARGET_SCHED_ADJUST_COST
30517 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30518 #undef TARGET_SCHED_ISSUE_RATE
30519 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30520 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30521 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30522 ia32_multipass_dfa_lookahead
30524 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30525 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30527 #ifdef HAVE_AS_TLS
30528 #undef TARGET_HAVE_TLS
30529 #define TARGET_HAVE_TLS true
30530 #endif
30531 #undef TARGET_CANNOT_FORCE_CONST_MEM
30532 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30533 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30534 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30536 #undef TARGET_DELEGITIMIZE_ADDRESS
30537 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30539 #undef TARGET_MS_BITFIELD_LAYOUT_P
30540 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30542 #if TARGET_MACHO
30543 #undef TARGET_BINDS_LOCAL_P
30544 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30545 #endif
30546 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30547 #undef TARGET_BINDS_LOCAL_P
30548 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30549 #endif
30551 #undef TARGET_ASM_OUTPUT_MI_THUNK
30552 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30553 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30554 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30556 #undef TARGET_ASM_FILE_START
30557 #define TARGET_ASM_FILE_START x86_file_start
30559 #undef TARGET_DEFAULT_TARGET_FLAGS
30560 #define TARGET_DEFAULT_TARGET_FLAGS \
30561 (TARGET_DEFAULT \
30562 | TARGET_SUBTARGET_DEFAULT \
30563 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT \
30564 | MASK_FUSED_MADD)
30566 #undef TARGET_HANDLE_OPTION
30567 #define TARGET_HANDLE_OPTION ix86_handle_option
30569 #undef TARGET_RTX_COSTS
30570 #define TARGET_RTX_COSTS ix86_rtx_costs
30571 #undef TARGET_ADDRESS_COST
30572 #define TARGET_ADDRESS_COST ix86_address_cost
30574 #undef TARGET_FIXED_CONDITION_CODE_REGS
30575 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30576 #undef TARGET_CC_MODES_COMPATIBLE
30577 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30579 #undef TARGET_MACHINE_DEPENDENT_REORG
30580 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30582 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30583 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30585 #undef TARGET_BUILD_BUILTIN_VA_LIST
30586 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30588 #undef TARGET_FN_ABI_VA_LIST
30589 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30591 #undef TARGET_CANONICAL_VA_LIST_TYPE
30592 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30594 #undef TARGET_EXPAND_BUILTIN_VA_START
30595 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30597 #undef TARGET_MD_ASM_CLOBBERS
30598 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30600 #undef TARGET_PROMOTE_PROTOTYPES
30601 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30602 #undef TARGET_STRUCT_VALUE_RTX
30603 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30604 #undef TARGET_SETUP_INCOMING_VARARGS
30605 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30606 #undef TARGET_MUST_PASS_IN_STACK
30607 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30608 #undef TARGET_PASS_BY_REFERENCE
30609 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30610 #undef TARGET_INTERNAL_ARG_POINTER
30611 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30612 #undef TARGET_UPDATE_STACK_BOUNDARY
30613 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30614 #undef TARGET_GET_DRAP_RTX
30615 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30616 #undef TARGET_STRICT_ARGUMENT_NAMING
30617 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30618 #undef TARGET_STATIC_CHAIN
30619 #define TARGET_STATIC_CHAIN ix86_static_chain
30620 #undef TARGET_TRAMPOLINE_INIT
30621 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30623 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30624 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30626 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30627 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30629 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30630 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30632 #undef TARGET_C_MODE_FOR_SUFFIX
30633 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30635 #ifdef HAVE_AS_TLS
30636 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30637 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30638 #endif
30640 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30641 #undef TARGET_INSERT_ATTRIBUTES
30642 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30643 #endif
30645 #undef TARGET_MANGLE_TYPE
30646 #define TARGET_MANGLE_TYPE ix86_mangle_type
30648 #undef TARGET_STACK_PROTECT_FAIL
30649 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30651 #undef TARGET_FUNCTION_VALUE
30652 #define TARGET_FUNCTION_VALUE ix86_function_value
30654 #undef TARGET_SECONDARY_RELOAD
30655 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30657 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30658 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
30659 ix86_builtin_vectorization_cost
30660 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
30661 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
30662 ix86_vectorize_builtin_vec_perm
30663 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
30664 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
30665 ix86_vectorize_builtin_vec_perm_ok
30667 #undef TARGET_SET_CURRENT_FUNCTION
30668 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30670 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30671 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30673 #undef TARGET_OPTION_SAVE
30674 #define TARGET_OPTION_SAVE ix86_function_specific_save
30676 #undef TARGET_OPTION_RESTORE
30677 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30679 #undef TARGET_OPTION_PRINT
30680 #define TARGET_OPTION_PRINT ix86_function_specific_print
30682 #undef TARGET_CAN_INLINE_P
30683 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30685 #undef TARGET_EXPAND_TO_RTL_HOOK
30686 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30688 #undef TARGET_LEGITIMATE_ADDRESS_P
30689 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30691 #undef TARGET_IRA_COVER_CLASSES
30692 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30694 #undef TARGET_FRAME_POINTER_REQUIRED
30695 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30697 #undef TARGET_CAN_ELIMINATE
30698 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30700 #undef TARGET_ASM_CODE_END
30701 #define TARGET_ASM_CODE_END ix86_code_end
30704 \f