1 ; Options for the Synopsys DesignWare ARC port of the compiler
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5 ; This file is part of GCC.
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25 Target Report RejectNegative Mask(BIG_ENDIAN)
26 Compile code for big endian mode
29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
30 Compile code for little endian mode. This is the default
33 Target Report RejectNegative Mask(NO_COND_EXEC)
34 Disable ARCompact specific pass to generate conditional execution instructions
38 Generate ARCompact 32-bit code for ARCtangent-A5 processor
42 Generate ARCompact 32-bit code for ARC600 processor
50 Generate ARCompact 32-bit code for ARC601 processor
54 Generate ARCompact 32-bit code for ARC700 processor
61 Target Report Mask(MIXED_CODE_SET)
62 Tweak register allocation to help 16-bit instruction generation
63 ; originally this was:
64 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions for ARCtangent-A5 and higher processors
65 ; but we do that without -mmixed-code, too, it's just a different instruction
66 ; count / size tradeoff.
68 ; We use an explict definition for the negative form because that is the
69 ; actually interesting option, and we want that to have its own comment.
71 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
72 Use ordinarily cached memory accesses for volatile references
75 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
76 Enable cache bypass for volatile references
79 Target Report Mask(BARREL_SHIFTER)
80 Generate instructions supported by barrel shifter
83 Target Report Mask(NORM_SET)
84 Generate norm instruction
87 Target Report Mask(SWAP_SET)
88 Generate swap instruction
91 Target Report Mask(MUL64_SET)
92 Generate mul64 and mulu64 instructions
95 Target Report Mask(NOMPY_SET)
96 Do not generate mpy instructions for ARC700
99 Target Report Mask(EA_SET)
100 Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported
103 Target Report Mask(0)
104 Dummy flag. This is the default unless FPX switches are provided explicitly
107 Target Report Mask(LONG_CALLS_SET)
108 Generate call insns as register indirect calls
111 Target Report Mask(NO_BRCC_SET)
112 Do no generate BRcc instructions in arc_reorg.
115 Target Report InverseMask(NO_SDATA_SET)
116 Generate sdata references. This is the default, unless you compile for PIC.
119 Target Report Mask(NO_MILLICODE_THUNK_SET)
120 Do not generate millicode thunks (needed only with -Os)
123 Target Report Mask(SPFP_COMPACT_SET)
124 FPX: Generate Single Precision FPX (compact) instructions.
127 Target Report Mask(SPFP_COMPACT_SET) MaskExists
128 FPX: Generate Single Precision FPX (compact) instructions.
131 Target Report Mask(SPFP_FAST_SET)
132 FPX: Generate Single Precision FPX (fast) instructions.
135 Target Report Mask(ARGONAUT_SET)
136 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
139 Target Report Mask(DPFP_COMPACT_SET)
140 FPX: Generate Double Precision FPX (compact) instructions.
143 Target Report Mask(DPFP_COMPACT_SET) MaskExists
144 FPX: Generate Double Precision FPX (compact) instructions.
147 Target Report Mask(DPFP_FAST_SET)
148 FPX: Generate Double Precision FPX (fast) instructions.
151 Target Report Mask(DPFP_DISABLE_LRSR)
152 Disable LR and SR instructions from using FPX extension aux registers.
155 Target Report Mask(SIMD_SET)
156 Enable generation of ARC SIMD instructions via target-specific builtins.
159 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
160 -mcpu=CPU Compile code for ARC variant CPU
163 Name(processor_type) Type(enum processor_type)
166 Enum(processor_type) String(A5) Value(PROCESSOR_A5)
169 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
172 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
175 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
178 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
179 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os
182 Target Report Var(TARGET_DUMPISIZE)
183 Annotate assembler instructions with estimated addresses
186 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
187 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
190 Target RejectNegative Var(arc_tune, TUNE_ARC600)
194 Target RejectNegative Var(arc_tune, TUNE_ARC600)
198 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
199 Tune for ARC700 R4.2 Cpu with standard multiplier block.
202 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
203 Tune for ARC700 R4.2 Cpu with XMAC block.
206 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
207 Tune for ARC700 R4.2 Cpu with XMAC block.
210 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
211 Tune for ARC700 R4.2 Cpu with XMAC block.
214 Target Var(TARGET_INDEXED_LOADS)
215 Enable the use of indexed loads
218 Target Var(TARGET_AUTO_MODIFY_REG)
219 Enable the use of pre/post modify with register displacement.
222 Target Report Mask(MULMAC_32BY16_SET)
223 Generate 32x16 multiply and mac instructions
225 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
226 ; alas, basic-block.h is not included in options.c .
227 munalign-prob-threshold=
228 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
229 Set probability threshold for unaligning branches
232 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
233 Don't use less than 25 bit addressing range for calls.
236 Target Var(TARGET_ANNOTATE_ALIGN)
237 Explain what alignment considerations lead to the decision to make an insn short or long.
240 Target Var(TARGET_ALIGN_CALL)
241 Do alignment optimizations for call instructions.
244 Target Var(TARGET_Rcq)
245 Enable Rcq constraint handling - most short code generation depends on this.
248 Target Var(TARGET_Rcw)
249 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
252 Target Var(TARGET_EARLY_CBRANCHSI)
253 Enable pre-reload use of cbranchsi pattern
256 Target Var(TARGET_BBIT_PEEPHOLE)
257 Enable bbit peephole2
260 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
261 Use pc-relative switch case tables - this enables case table shortening.
264 Target Var(TARGET_COMPACT_CASESI)
265 Enable compact casesi pattern
268 Target Var(TARGET_Q_CLASS)
269 Enable 'q' instruction alternatives.
272 Target Var(TARGET_EXPAND_ADDDI)
273 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
276 ; Flags used by the assembler, but for which we define preprocessor
277 ; macro symbols as well.
280 Enable variable polynomial CRC extension
284 Enable DSP 3.1 Pack A extensions
288 Enable dual viterbi butterfly extension
291 Target Report Undocumented
294 Target Report Undocumented
297 Target Report RejectNegative
298 Enable Dual and Single Operand Instructions for Telephony
302 Enable XY Memory extension (DSP version 3)
304 ; ARC700 4.10 extension instructions
307 Enable Locked Load/Store Conditional extension
311 Enable swap byte ordering extension instruction
315 Enable 64-bit Time-Stamp Counter extension instruction
318 Target Report RejectNegative InverseMask(EPILOGUE_CFI)
319 Disable generation of cfi for epilogues.
322 Target RejectNegative Mask(EPILOGUE_CFI)
323 Enable generation of cfi for epilogues.
327 Pass -EB option through to linker.
331 Pass -EL option through to linker.
335 Pass -marclinux option through to linker.
339 Pass -marclinux_prof option through to linker.
341 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
342 ;Target InverseMask(NO_LRA)
344 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
345 ; so don't enable by default.
350 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
351 Don't indicate any priority with TARGET_REGISTER_PRIORITY
353 mlra-priority-compact
354 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
355 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY
357 mlra-priority-noncompact
358 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
359 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY
362 Target Report Var(TARGET_UCB_MCOUNT)
363 instrument with mcount calls as in the ucb code
365 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
371 Target RejectNegative Joined
373 ; Unfortunately, listing the full option name gives us clashes
374 ; with OPT_opt_name being claimed for both opt_name and opt-name,
375 ; so we leave out the last character or more.