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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
123 #ifndef CHECK_STACK_LIMIT
124 #define CHECK_STACK_LIMIT (-1)
125 #endif
127 /* Return index of given mode in mult and division cost tables. */
128 #define MODE_INDEX(mode) \
129 ((mode) == QImode ? 0 \
130 : (mode) == HImode ? 1 \
131 : (mode) == SImode ? 2 \
132 : (mode) == DImode ? 3 \
133 : 4)
135 /* Processor costs (relative to an add) */
136 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
137 #define COSTS_N_BYTES(N) ((N) * 2)
139 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
148 const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
201 ix86_size_memcpy,
202 ix86_size_memset,
214 };
216 /* Processor costs (relative to an add) */
219 DUMMY_STRINGOP_ALGS};
222 DUMMY_STRINGOP_ALGS};
224 static const
247 in QImode, HImode and SImode.
248 Relative to reg-reg move (2). */
252 in SFmode, DFmode and XFmode */
254 in SFmode, DFmode and XFmode */
257 in SImode and DImode */
259 in SImode and DImode */
262 in SImode, DImode and TImode */
264 in SImode, DImode and TImode */
277 i386_memcpy,
278 i386_memset,
290 };
294 DUMMY_STRINGOP_ALGS};
297 DUMMY_STRINGOP_ALGS};
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
342 shared for code and data, so 4kB is
343 not really precise. */
354 i486_memcpy,
355 i486_memset,
367 };
371 DUMMY_STRINGOP_ALGS};
374 DUMMY_STRINGOP_ALGS};
376 static const
399 in QImode, HImode and SImode.
400 Relative to reg-reg move (2). */
404 in SFmode, DFmode and XFmode */
406 in SFmode, DFmode and XFmode */
409 in SImode and DImode */
411 in SImode and DImode */
414 in SImode, DImode and TImode */
416 in SImode, DImode and TImode */
429 pentium_memcpy,
430 pentium_memset,
442 };
444 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
445 (we ensure the alignment). For small blocks inline loop is still a
446 noticeable win, for bigger blocks either rep movsl or rep movsb is
447 way to go. Rep movsb has apparently more expensive startup time in CPU,
448 but after 4K the difference is down in the noise. */
453 DUMMY_STRINGOP_ALGS};
458 DUMMY_STRINGOP_ALGS};
459 static const
482 in QImode, HImode and SImode.
483 Relative to reg-reg move (2). */
487 in SFmode, DFmode and XFmode */
489 in SFmode, DFmode and XFmode */
492 in SImode and DImode */
494 in SImode and DImode */
497 in SImode, DImode and TImode */
499 in SImode, DImode and TImode */
512 pentiumpro_memcpy,
513 pentiumpro_memset,
525 };
529 DUMMY_STRINGOP_ALGS};
532 DUMMY_STRINGOP_ALGS};
533 static const
556 in QImode, HImode and SImode.
557 Relative to reg-reg move (2). */
561 in SFmode, DFmode and XFmode */
563 in SFmode, DFmode and XFmode */
567 in SImode and DImode */
569 in SImode and DImode */
572 in SImode, DImode and TImode */
574 in SImode, DImode and TImode */
587 geode_memcpy,
588 geode_memset,
600 };
604 DUMMY_STRINGOP_ALGS};
607 DUMMY_STRINGOP_ALGS};
608 static const
631 in QImode, HImode and SImode.
632 Relative to reg-reg move (2). */
636 in SFmode, DFmode and XFmode */
638 in SFmode, DFmode and XFmode */
641 in SImode and DImode */
643 in SImode and DImode */
646 in SImode, DImode and TImode */
648 in SImode, DImode and TImode */
652 have integrated l2 cache, but
653 optimizing for k6 is not important
654 enough to worry about that. */
664 k6_memcpy,
665 k6_memset,
677 };
679 /* For some reason, Athlon deals better with REP prefix (relative to loops)
680 compared to K8. Alignment becomes important after 8 bytes for memcpy and
681 128 bytes for memset. */
684 DUMMY_STRINGOP_ALGS};
687 DUMMY_STRINGOP_ALGS};
688 static const
711 in QImode, HImode and SImode.
712 Relative to reg-reg move (2). */
716 in SFmode, DFmode and XFmode */
718 in SFmode, DFmode and XFmode */
721 in SImode and DImode */
723 in SImode and DImode */
726 in SImode, DImode and TImode */
728 in SImode, DImode and TImode */
741 athlon_memcpy,
742 athlon_memset,
754 };
756 /* K8 has optimized REP instruction for medium sized blocks, but for very
757 small blocks it is better to use loop. For large blocks, libcall can
758 do nontemporary accesses and beat inline considerably. */
769 static const
792 in QImode, HImode and SImode.
793 Relative to reg-reg move (2). */
797 in SFmode, DFmode and XFmode */
799 in SFmode, DFmode and XFmode */
802 in SImode and DImode */
804 in SImode and DImode */
807 in SImode, DImode and TImode */
809 in SImode, DImode and TImode */
814 /* New AMD processors never drop prefetches; if they cannot be performed
815 immediately, they are queued. We set number of simultaneous prefetches
816 to a large constant to reflect this (it probably is not a good idea not
817 to limit number of prefetches at all, as their execution also takes some
818 time). */
828 k8_memcpy,
829 k8_memset,
841 };
843 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
844 very small blocks it is better to use loop. For large blocks, libcall can
845 do nontemporary accesses and beat inline considerably. */
878 in QImode, HImode and SImode.
879 Relative to reg-reg move (2). */
883 in SFmode, DFmode and XFmode */
885 in SFmode, DFmode and XFmode */
888 in SImode and DImode */
890 in SImode and DImode */
893 in SImode, DImode and TImode */
895 in SImode, DImode and TImode */
897 /* On K8:
898 MOVD reg64, xmmreg Double FSTORE 4
899 MOVD reg32, xmmreg Double FSTORE 4
900 On AMDFAM10:
901 MOVD reg64, xmmreg Double FADD 3
902 1/1 1/1
903 MOVD reg32, xmmreg Double FADD 3
904 1/1 1/1 */
908 /* New AMD processors never drop prefetches; if they cannot be performed
909 immediately, they are queued. We set number of simultaneous prefetches
910 to a large constant to reflect this (it probably is not a good idea not
911 to limit number of prefetches at all, as their execution also takes some
912 time). */
922 amdfam10_memcpy,
923 amdfam10_memset,
935 };
937 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
938 very small blocks it is better to use loop. For large blocks, libcall
939 can do nontemporary accesses and beat inline considerably. */
973 in QImode, HImode and SImode.
974 Relative to reg-reg move (2). */
978 in SFmode, DFmode and XFmode */
980 in SFmode, DFmode and XFmode */
983 in SImode and DImode */
985 in SImode and DImode */
988 in SImode, DImode and TImode */
990 in SImode, DImode and TImode */
992 /* On K8:
993 MOVD reg64, xmmreg Double FSTORE 4
994 MOVD reg32, xmmreg Double FSTORE 4
995 On AMDFAM10:
996 MOVD reg64, xmmreg Double FADD 3
997 1/1 1/1
998 MOVD reg32, xmmreg Double FADD 3
999 1/1 1/1 */
1003 /* New AMD processors never drop prefetches; if they cannot be performed
1004 immediately, they are queued. We set number of simultaneous prefetches
1005 to a large constant to reflect this (it probably is not a good idea not
1006 to limit number of prefetches at all, as their execution also takes some
1007 time). */
1017 bdver1_memcpy,
1018 bdver1_memset,
1030 };
1032 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1033 very small blocks it is better to use loop. For large blocks, libcall
1034 can do nontemporary accesses and beat inline considerably. */
1069 in QImode, HImode and SImode.
1070 Relative to reg-reg move (2). */
1074 in SFmode, DFmode and XFmode */
1076 in SFmode, DFmode and XFmode */
1079 in SImode and DImode */
1081 in SImode and DImode */
1084 in SImode, DImode and TImode */
1086 in SImode, DImode and TImode */
1088 /* On K8:
1089 MOVD reg64, xmmreg Double FSTORE 4
1090 MOVD reg32, xmmreg Double FSTORE 4
1091 On AMDFAM10:
1092 MOVD reg64, xmmreg Double FADD 3
1093 1/1 1/1
1094 MOVD reg32, xmmreg Double FADD 3
1095 1/1 1/1 */
1099 /* New AMD processors never drop prefetches; if they cannot be performed
1100 immediately, they are queued. We set number of simultaneous prefetches
1101 to a large constant to reflect this (it probably is not a good idea not
1102 to limit number of prefetches at all, as their execution also takes some
1103 time). */
1113 bdver2_memcpy,
1114 bdver2_memset,
1126 };
1129 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1130 very small blocks it is better to use loop. For large blocks, libcall
1131 can do nontemporary accesses and beat inline considerably. */
1164 in QImode, HImode and SImode.
1165 Relative to reg-reg move (2). */
1169 in SFmode, DFmode and XFmode */
1171 in SFmode, DFmode and XFmode */
1174 in SImode and DImode */
1176 in SImode and DImode */
1179 in SImode, DImode and TImode */
1181 in SImode, DImode and TImode */
1186 /* New AMD processors never drop prefetches; if they cannot be performed
1187 immediately, they are queued. We set number of simultaneous prefetches
1188 to a large constant to reflect this (it probably is not a good idea not
1189 to limit number of prefetches at all, as their execution also takes some
1190 time). */
1200 bdver3_memcpy,
1201 bdver3_memset,
1213 };
1215 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1216 very small blocks it is better to use loop. For large blocks, libcall
1217 can do nontemporary accesses and beat inline considerably. */
1250 in QImode, HImode and SImode.
1251 Relative to reg-reg move (2). */
1255 in SFmode, DFmode and XFmode */
1257 in SFmode, DFmode and XFmode */
1260 in SImode and DImode */
1262 in SImode and DImode */
1265 in SImode, DImode and TImode */
1267 in SImode, DImode and TImode */
1272 /* New AMD processors never drop prefetches; if they cannot be performed
1273 immediately, they are queued. We set number of simultaneous prefetches
1274 to a large constant to reflect this (it probably is not a good idea not
1275 to limit number of prefetches at all, as their execution also takes some
1276 time). */
1286 bdver4_memcpy,
1287 bdver4_memset,
1299 };
1301 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1302 very small blocks it is better to use loop. For large blocks, libcall can
1303 do nontemporary accesses and beat inline considerably. */
1336 in QImode, HImode and SImode.
1337 Relative to reg-reg move (2). */
1341 in SFmode, DFmode and XFmode */
1343 in SFmode, DFmode and XFmode */
1346 in SImode and DImode */
1348 in SImode and DImode */
1351 in SImode, DImode and TImode */
1353 in SImode, DImode and TImode */
1355 /* On K8:
1356 MOVD reg64, xmmreg Double FSTORE 4
1357 MOVD reg32, xmmreg Double FSTORE 4
1358 On AMDFAM10:
1359 MOVD reg64, xmmreg Double FADD 3
1360 1/1 1/1
1361 MOVD reg32, xmmreg Double FADD 3
1362 1/1 1/1 */
1375 btver1_memcpy,
1376 btver1_memset,
1388 };
1422 in QImode, HImode and SImode.
1423 Relative to reg-reg move (2). */
1427 in SFmode, DFmode and XFmode */
1429 in SFmode, DFmode and XFmode */
1432 in SImode and DImode */
1434 in SImode and DImode */
1437 in SImode, DImode and TImode */
1439 in SImode, DImode and TImode */
1441 /* On K8:
1442 MOVD reg64, xmmreg Double FSTORE 4
1443 MOVD reg32, xmmreg Double FSTORE 4
1444 On AMDFAM10:
1445 MOVD reg64, xmmreg Double FADD 3
1446 1/1 1/1
1447 MOVD reg32, xmmreg Double FADD 3
1448 1/1 1/1 */
1460 btver2_memcpy,
1461 btver2_memset,
1473 };
1477 DUMMY_STRINGOP_ALGS};
1481 DUMMY_STRINGOP_ALGS};
1483 static const
1506 in QImode, HImode and SImode.
1507 Relative to reg-reg move (2). */
1511 in SFmode, DFmode and XFmode */
1513 in SFmode, DFmode and XFmode */
1516 in SImode and DImode */
1518 in SImode and DImode */
1521 in SImode, DImode and TImode */
1523 in SImode, DImode and TImode */
1536 pentium4_memcpy,
1537 pentium4_memset,
1549 };
1562 static const
1585 in QImode, HImode and SImode.
1586 Relative to reg-reg move (2). */
1590 in SFmode, DFmode and XFmode */
1592 in SFmode, DFmode and XFmode */
1595 in SImode and DImode */
1597 in SImode and DImode */
1600 in SImode, DImode and TImode */
1602 in SImode, DImode and TImode */
1615 nocona_memcpy,
1616 nocona_memset,
1628 };
1639 static const
1662 in QImode, HImode and SImode.
1663 Relative to reg-reg move (2). */
1667 in SFmode, DFmode and XFmode */
1669 in SFmode, DFmode and XFmode */
1672 in SImode and DImode */
1674 in SImode and DImode */
1677 in SImode, DImode and TImode */
1679 in SImode, DImode and TImode */
1692 atom_memcpy,
1693 atom_memset,
1705 };
1716 static const
1739 in QImode, HImode and SImode.
1740 Relative to reg-reg move (2). */
1744 in SFmode, DFmode and XFmode */
1746 in SFmode, DFmode and XFmode */
1749 in SImode and DImode */
1751 in SImode and DImode */
1754 in SImode, DImode and TImode */
1756 in SImode, DImode and TImode */
1769 slm_memcpy,
1770 slm_memset,
1782 };
1793 static const
1816 in QImode, HImode and SImode.
1817 Relative to reg-reg move (2). */
1821 in SFmode, DFmode and XFmode */
1823 in SFmode, DFmode and XFmode */
1826 in SImode and DImode */
1828 in SImode and DImode */
1831 in SImode, DImode and TImode */
1833 in SImode, DImode and TImode */
1846 intel_memcpy,
1847 intel_memset,
1859 };
1861 /* Generic should produce code tuned for Core-i7 (and newer chips)
1862 and btver1 (and newer chips). */
1874 static const
1877 /* On all chips taken into consideration lea is 2 cycles and more. With
1878 this cost however our current implementation of synth_mult results in
1879 use of unnecessary temporary registers causing regression on several
1880 SPECfp benchmarks. */
1901 in QImode, HImode and SImode.
1902 Relative to reg-reg move (2). */
1906 in SFmode, DFmode and XFmode */
1908 in SFmode, DFmode and XFmode */
1911 in SImode and DImode */
1913 in SImode and DImode */
1916 in SImode, DImode and TImode */
1918 in SImode, DImode and TImode */
1924 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1925 value is increased to perhaps more appropriate value of 5. */
1933 generic_memcpy,
1934 generic_memset,
1946 };
1948 /* core_cost should produce code tuned for Core familly of CPUs. */
1961 static const
1964 /* On all chips taken into consideration lea is 2 cycles and more. With
1965 this cost however our current implementation of synth_mult results in
1966 use of unnecessary temporary registers causing regression on several
1967 SPECfp benchmarks. */
1988 in QImode, HImode and SImode.
1989 Relative to reg-reg move (2). */
1993 in SFmode, DFmode and XFmode */
1995 in SFmode, DFmode and XFmode */
1998 in SImode and DImode */
2000 in SImode and DImode */
2003 in SImode, DImode and TImode */
2005 in SImode, DImode and TImode */
2011 /* FIXME perhaps more appropriate value is 5. */
2019 core_memcpy,
2020 core_memset,
2032 };
2035 /* Set by -mtune. */
2038 /* Set by -mtune or -Os. */
2041 /* Processor feature/optimization bitmasks. */
2042 #define m_386 (1<<PROCESSOR_I386)
2043 #define m_486 (1<<PROCESSOR_I486)
2044 #define m_PENT (1<<PROCESSOR_PENTIUM)
2045 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2046 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2047 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2048 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2049 #define m_CORE2 (1<<PROCESSOR_CORE2)
2050 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2051 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2052 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2053 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2054 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2055 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2056 #define m_KNL (1<<PROCESSOR_KNL)
2057 #define m_INTEL (1<<PROCESSOR_INTEL)
2059 #define m_GEODE (1<<PROCESSOR_GEODE)
2060 #define m_K6 (1<<PROCESSOR_K6)
2061 #define m_K6_GEODE (m_K6 | m_GEODE)
2062 #define m_K8 (1<<PROCESSOR_K8)
2063 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2064 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2065 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2066 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2067 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2068 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2069 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2070 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2071 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2072 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2073 #define m_BTVER (m_BTVER1 | m_BTVER2)
2074 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2076 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2079 #undef DEF_TUNE
2080 #define DEF_TUNE(tune, name, selector) name,
2082 #undef DEF_TUNE
2083 };
2085 /* Feature tests against the various tunings. */
2088 /* Feature tests against the various tunings used to create ix86_tune_features
2089 based on the processor mask. */
2091 #undef DEF_TUNE
2092 #define DEF_TUNE(tune, name, selector) selector,
2094 #undef DEF_TUNE
2095 };
2097 /* Feature tests against the various architecture variations. */
2100 /* Feature tests against the various architecture variations, used to create
2101 ix86_arch_features based on the processor mask. */
2103 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2106 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2109 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2112 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2115 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2117 };
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 /* AVX-512 SSE registers */
2162 /* Mask registers. */
2165 /* MPX bound registers */
2167 };
2169 /* The "default" register map used in 32bit mode. */
2172 {
2184 };
2186 /* The "default" register map used in 64bit mode. */
2189 {
2201 };
2203 /* Define the register numbers to be used in Dwarf debugging information.
2204 The SVR4 reference port C compiler uses the following register numbers
2205 in its Dwarf output code:
2206 0 for %eax (gcc regno = 0)
2207 1 for %ecx (gcc regno = 2)
2208 2 for %edx (gcc regno = 1)
2209 3 for %ebx (gcc regno = 3)
2210 4 for %esp (gcc regno = 7)
2211 5 for %ebp (gcc regno = 6)
2212 6 for %esi (gcc regno = 4)
2213 7 for %edi (gcc regno = 5)
2214 The following three DWARF register numbers are never generated by
2215 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2216 believes these numbers have these meanings.
2217 8 for %eip (no gcc equivalent)
2218 9 for %eflags (gcc regno = 17)
2219 10 for %trapno (no gcc equivalent)
2220 It is not at all clear how we should number the FP stack registers
2221 for the x86 architecture. If the version of SDB on x86/svr4 were
2222 a bit less brain dead with respect to floating-point then we would
2223 have a precedent to follow with respect to DWARF register numbers
2224 for x86 FP registers, but the SDB on x86/svr4 is so completely
2225 broken with respect to FP registers that it is hardly worth thinking
2226 of it as something to strive for compatibility with.
2227 The version of x86/svr4 SDB I have at the moment does (partially)
2228 seem to believe that DWARF register number 11 is associated with
2229 the x86 register %st(0), but that's about all. Higher DWARF
2230 register numbers don't seem to be associated with anything in
2231 particular, and even for DWARF regno 11, SDB only seems to under-
2232 stand that it should say that a variable lives in %st(0) (when
2233 asked via an `=' command) if we said it was in DWARF regno 11,
2234 but SDB still prints garbage when asked for the value of the
2235 variable in question (via a `/' command).
2236 (Also note that the labels SDB prints for various FP stack regs
2237 when doing an `x' command are all wrong.)
2238 Note that these problems generally don't affect the native SVR4
2239 C compiler because it doesn't allow the use of -O with -g and
2240 because when it is *not* optimizing, it allocates a memory
2241 location for each floating-point variable, and the memory
2242 location is what gets described in the DWARF AT_location
2243 attribute for the variable in question.
2244 Regardless of the severe mental illness of the x86/svr4 SDB, we
2245 do something sensible here and we use the following DWARF
2246 register numbers. Note that these are all stack-top-relative
2247 numbers.
2248 11 for %st(0) (gcc regno = 8)
2249 12 for %st(1) (gcc regno = 9)
2250 13 for %st(2) (gcc regno = 10)
2251 14 for %st(3) (gcc regno = 11)
2252 15 for %st(4) (gcc regno = 12)
2253 16 for %st(5) (gcc regno = 13)
2254 17 for %st(6) (gcc regno = 14)
2255 18 for %st(7) (gcc regno = 15)
2256 */
2258 {
2270 };
2272 /* Define parameter passing and return registers. */
2275 {
2277 };
2280 {
2282 };
2285 {
2287 };
2289 /* Additional registers that are clobbered by SYSV calls. */
2292 {
2297 };
2299 /* Define the structure for the machine field in struct function. */
2304 rtx rtl;
2306 };
2308 /* Structure describing stack frame layout.
2309 Stack grows downward:
2311 [arguments]
2312 <- ARG_POINTER
2313 saved pc
2315 saved static chain if ix86_static_chain_on_stack
2317 saved frame pointer if frame_pointer_needed
2318 <- HARD_FRAME_POINTER
2319 [saved regs]
2320 <- regs_save_offset
2321 [padding0]
2323 [saved SSE regs]
2324 <- sse_regs_save_offset
2325 [padding1] |
2326 | <- FRAME_POINTER
2327 [va_arg registers] |
2328 |
2329 [frame] |
2330 |
2331 [padding2] | = to_allocate
2332 <- STACK_POINTER
2333 */
2334 struct ix86_frame
2335 {
2342 /* The offsets relative to ARG_POINTER. */
2343 HOST_WIDE_INT frame_pointer_offset;
2344 HOST_WIDE_INT hard_frame_pointer_offset;
2345 HOST_WIDE_INT stack_pointer_offset;
2346 HOST_WIDE_INT hfp_save_offset;
2347 HOST_WIDE_INT reg_save_offset;
2348 HOST_WIDE_INT sse_reg_save_offset;
2350 /* When save_regs_using_mov is set, emit prologue using
2351 move instead of push instructions. */
2353 };
2355 /* Which cpu are we scheduling for. */
2358 /* Which cpu are we optimizing for. */
2361 /* Which instruction set architecture to use. */
2364 /* True if processor has SSE prefetch instruction. */
2367 /* -mstackrealign option */
2384 /* Preferred alignment for stack boundary in bits. */
2387 /* Alignment for incoming stack boundary in bits specified at
2388 command line. */
2391 /* Default alignment for incoming stack boundary in bits. */
2394 /* Alignment for incoming stack boundary in bits. */
2397 /* Calling abi specific va_list type nodes. */
2401 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2405 /* Fence to use after loop using movnt. */
2406 tree x86_mfence;
2408 /* Register class used for passing given 64bit part of the argument.
2409 These represent classes as documented by the PS ABI, with the exception
2410 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2411 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2413 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2414 whenever possible (upper half does contain padding). */
2415 enum x86_64_reg_class
2416 {
2417 X86_64_NO_CLASS,
2418 X86_64_INTEGER_CLASS,
2419 X86_64_INTEGERSI_CLASS,
2420 X86_64_SSE_CLASS,
2421 X86_64_SSESF_CLASS,
2422 X86_64_SSEDF_CLASS,
2423 X86_64_SSEUP_CLASS,
2424 X86_64_X87_CLASS,
2425 X86_64_X87UP_CLASS,
2426 X86_64_COMPLEX_X87_CLASS,
2427 X86_64_MEMORY_CLASS
2428 };
2430 #define MAX_CLASSES 8
2432 /* Table of constants used by fldpi, fldln2, etc.... */
2436 \f
2441 const_tree);
2453 enum ix86_function_specific_strings
2454 {
2455 IX86_FUNCTION_SPECIFIC_ARCH,
2456 IX86_FUNCTION_SPECIFIC_TUNE,
2457 IX86_FUNCTION_SPECIFIC_MAX
2458 };
2480 \f
2481 #ifndef SUBTARGET32_DEFAULT_CPU
2483 #endif
2485 /* Whether -mtune= or -march= were specified */
2489 /* Vectorization library interface and handlers. */
2495 /* Processor target table, indexed by processor number */
2496 struct ptt
2497 {
2505 };
2507 /* This table must be in sync with enum processor_type in i386.h. */
2509 {
2536 };
2537 \f
2538 static unsigned int
2540 {
2543 /* vzeroupper instructions are inserted immediately after reload to
2544 account for possible spills from 256bit registers. The pass
2545 reuses mode switching infrastructure by re-running mode insertion
2546 pass, so disable entities that have already been processed. */
2552 /* Call optimize_mode_switching. */
2555 }
2560 {
2570 };
2573 {
2577 {}
2579 /* opt_pass methods: */
2581 {
2585 }
2588 {
2590 }
2596 rtl_opt_pass *
2598 {
2600 }
2602 /* Return true if a red-zone is in use. */
2606 {
2608 }
2609 \f
2610 /* Return a string that documents the current -m options. The caller is
2611 responsible for freeing the string. */
2617 {
2618 struct ix86_target_opts
2619 {
2622 };
2624 /* This table is ordered so that options like -msse4.2 that imply
2625 preceding options while match those first. */
2627 {
2680 };
2682 /* Flag options. */
2684 {
2713 };
2730 /* Add -march= option. */
2732 {
2735 }
2737 /* Add -mtune= option. */
2739 {
2742 }
2744 /* Add -m32/-m64/-mx32. */
2746 {
2749 else
2751 isa &= ~ (OPTION_MASK_ISA_64BIT
2752 | OPTION_MASK_ABI_64
2754 }
2755 else
2759 /* Pick out the options in isa options. */
2761 {
2763 {
2766 }
2767 }
2770 {
2773 isa);
2774 }
2776 /* Add flag options. */
2778 {
2780 {
2783 }
2784 }
2787 {
2790 }
2792 /* Add -fpmath= option. */
2794 {
2797 {
2812 }
2813 }
2815 /* Any options? */
2821 /* Size the string. */
2825 {
2830 }
2832 /* Build the string. */
2837 {
2844 {
2846 line_len++;
2849 {
2853 }
2854 }
2858 {
2862 }
2863 }
2869 }
2871 /* Return true, if profiling code should be emitted before
2872 prologue. Otherwise it returns false.
2873 Note: For x86 with "hotfix" it is sorried. */
2874 static bool
2876 {
2878 }
2880 /* Function that is callable from the debugger to print the current
2881 options. */
2882 void ATTRIBUTE_UNUSED
2884 {
2890 {
2893 }
2894 else
2898 }
2901 #define DEF_ENUM
2902 #define DEF_ALG(alg, name) #name,
2904 #undef DEF_ENUM
2905 #undef DEF_ALG
2906 };
2908 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2909 The string is of the following form (or comma separated list of it):
2911 strategy_alg:max_size:[align|noalign]
2913 where the full size range for the strategy is either [0, max_size] or
2914 [min_size, max_size], in which min_size is the max_size + 1 of the
2915 preceding range. The last size range must have max_size == -1.
2917 Examples:
2919 1.
2920 -mmemcpy-strategy=libcall:-1:noalign
2922 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2925 2.
2926 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2928 This is to tell the compiler to use the following strategy for memset
2929 1) when the expected size is between [1, 16], use rep_8byte strategy;
2930 2) when the size is between [17, 2048], use vector_loop;
2931 3) when the size is > 2048, use libcall. */
2933 struct stringop_size_range
2934 {
2936 stringop_alg alg;
2938 };
2940 static void
2942 {
2950 else
2955 do
2956 {
2966 {
2970 }
2973 {
2977 }
2984 {
2986 alg_name,
2989 }
2997 else
2998 {
3002 }
3003 n++;
3005 }
3009 {
3014 }
3017 {
3021 }
3023 /* Now override the default algs array. */
3025 {
3031 }
3032 }
3034 \f
3035 /* parse -mtune-ctrl= option. When DUMP is true,
3036 print the features that are explicitly set. */
3038 static void
3040 {
3048 do
3049 {
3056 {
3057 curr_feature_string++;
3059 }
3061 {
3063 {
3069 }
3070 }
3075 }
3078 }
3080 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3081 processor type. */
3083 static void
3085 {
3090 {
3093 else
3095 }
3098 {
3103 }
3106 }
3109 /* Default align_* from the processor table. */
3111 static void
3113 {
3115 {
3118 }
3120 {
3123 }
3125 {
3127 }
3128 }
3130 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3132 static void
3134 {
3136 }
3138 /* Override various settings based on options. If MAIN_ARGS_P, the
3139 options are from the command line, otherwise they are from
3140 attributes. */
3142 static void
3146 {
3154 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3155 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3156 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3157 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3158 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3159 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3160 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3161 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3162 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3163 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3164 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3165 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3166 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3167 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3168 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3169 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3170 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3171 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3172 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3173 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3174 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3175 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3176 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3177 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3178 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3179 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3180 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3181 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3182 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3183 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3184 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3185 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3186 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3187 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3188 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3189 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3190 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3191 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3192 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3193 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3194 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3195 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3196 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3197 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3198 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3199 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3200 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3201 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3202 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3203 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3204 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3205 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3206 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3207 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3208 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3209 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3210 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3212 #define PTA_CORE2 \
3213 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3214 | PTA_CX16 | PTA_FXSR)
3215 #define PTA_NEHALEM \
3216 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3217 #define PTA_WESTMERE \
3218 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3219 #define PTA_SANDYBRIDGE \
3220 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3221 #define PTA_IVYBRIDGE \
3222 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3223 #define PTA_HASWELL \
3224 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3225 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3226 #define PTA_BROADWELL \
3227 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3228 #define PTA_KNL \
3229 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3230 #define PTA_BONNELL \
3231 (PTA_CORE2 | PTA_MOVBE)
3232 #define PTA_SILVERMONT \
3233 (PTA_WESTMERE | PTA_MOVBE)
3235 /* if this reaches 64, need to widen struct pta flags below */
3237 static struct pta
3238 {
3243 }
3245 {
3279 PTA_SANDYBRIDGE},
3281 PTA_SANDYBRIDGE},
3283 PTA_IVYBRIDGE},
3285 PTA_IVYBRIDGE},
3377 PTA_64BIT
3379 };
3381 /* -mrecip options. */
3382 static struct
3383 {
3386 }
3388 {
3395 };
3399 /* Set up prefix/suffix so the error messages refer to either the command
3400 line argument, or the attribute(target). */
3402 {
3406 }
3407 else
3408 {
3412 }
3414 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3415 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3418 #ifdef TARGET_BI_ARCH
3419 else
3420 {
3421 #if TARGET_BI_ARCH == 1
3422 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3423 is on and OPTION_MASK_ABI_X32 is off. We turn off
3424 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3425 -mx32. */
3428 #else
3429 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3430 on and OPTION_MASK_ABI_64 is off. We turn off
3431 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3432 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3436 #endif
3437 }
3438 #endif
3441 {
3442 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3443 OPTION_MASK_ABI_64 for TARGET_X32. */
3446 }
3449 | OPTION_MASK_ABI_X32
3452 {
3453 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3454 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3457 }
3459 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3460 SUBTARGET_OVERRIDE_OPTIONS;
3461 #endif
3463 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3464 SUBSUBTARGET_OVERRIDE_OPTIONS;
3465 #endif
3467 /* -fPIC is the default for x86_64. */
3471 /* Need to check -mtune=generic first. */
3473 {
3474 /* As special support for cross compilers we read -mtune=native
3475 as -mtune=generic. With native compilers we won't see the
3476 -mtune=native, as it was changed by the driver. */
3478 {
3480 }
3485 }
3486 else
3487 {
3491 {
3492 opts->x_ix86_tune_string
3495 }
3497 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3498 or defaulted. We need to use a sensible tune option. */
3500 {
3502 }
3503 }
3507 {
3508 /* rep; movq isn't available in 32-bit code. */
3511 }
3514 opts->x_ix86_arch_string
3517 else
3521 {
3529 }
3530 else
3537 /* For targets using ms ABI enable ms-extensions, if not
3538 explicit turned off. For non-ms ABI we turn off this
3539 option. */
3544 {
3546 {
3590 {
3593 }
3601 }
3602 }
3603 else
3604 {
3605 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3606 use of rip-relative addressing. This eliminates fixups that
3607 would otherwise be needed if this object is to be placed in a
3608 DLL, and is essentially just as efficient as direct addressing. */
3614 else
3616 }
3618 {
3621 }
3629 {
3632 /* Default cpu tuning to the architecture. */
3810 }
3834 {
3838 {
3840 {
3842 {
3850 }
3851 else
3854 }
3855 }
3856 /* Intel CPUs have always interpreted SSE prefetch instructions as
3857 NOPs; so, we can enable SSE prefetch instructions even when
3858 -mtune (rather than -march) points us to a processor that has them.
3859 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3860 higher processors. */
3865 }
3873 #ifndef USE_IX86_FRAME_POINTER
3874 #define USE_IX86_FRAME_POINTER 0
3875 #endif
3877 #ifndef USE_X86_64_FRAME_POINTER
3878 #define USE_X86_64_FRAME_POINTER 0
3879 #endif
3881 /* Set the default values for switches whose default depends on TARGET_64BIT
3882 in case they weren't overwritten by command line options. */
3884 {
3892 opts->x_flag_unwind_tables
3896 }
3897 else
3898 {
3900 opts->x_flag_omit_frame_pointer
3906 }
3909 /* TODO: ix86_cost should be chosen at instruction or function granuality
3910 so for cold code we use size_cost even in !optimize_size compilation. */
3913 else
3916 /* Arrange to set up i386_stack_locals for all functions. */
3919 /* Validate -mregparm= value. */
3921 {
3925 {
3929 }
3930 }
3934 /* Default align_* from the processor table. */
3937 /* Provide default for -mbranch-cost= value. */
3942 {
3943 opts->x_target_flags
3946 /* Enable by default the SSE and MMX builtins. Do allow the user to
3947 explicitly disable any of these. In particular, disabling SSE and
3948 MMX for kernel code is extremely useful. */
3950 opts->x_ix86_isa_flags
3957 }
3958 else
3959 {
3960 opts->x_target_flags
3964 opts->x_ix86_isa_flags
3967 /* i386 ABI does not specify red zone. It still makes sense to use it
3968 when programmer takes care to stack from being destroyed. */
3971 }
3973 /* Keep nonleaf frame pointers. */
3979 /* If we're doing fast math, we don't care about comparison order
3980 wrt NaNs. This lets us use a shorter comparison sequence. */
3984 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3985 since the insns won't need emulation. */
3989 /* Likewise, if the target doesn't have a 387, or we've specified
3990 software floating point, don't use 387 inline intrinsics. */
3994 /* Turn on MMX builtins for -msse. */
3996 opts->x_ix86_isa_flags
3999 /* Enable SSE prefetch. */
4004 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4007 opts->x_ix86_isa_flags
4010 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4013 opts->x_ix86_isa_flags
4016 /* Enable lzcnt instruction for -mabm. */
4018 opts->x_ix86_isa_flags
4021 /* Validate -mpreferred-stack-boundary= value or default it to
4022 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4025 {
4032 {
4036 else
4039 }
4040 else
4041 ix86_preferred_stack_boundary
4043 }
4045 /* Set the default value for -mstackrealign. */
4051 /* Validate -mincoming-stack-boundary= value or default it to
4052 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4055 {
4062 else
4063 {
4064 ix86_user_incoming_stack_boundary
4066 ix86_incoming_stack_boundary
4068 }
4069 }
4071 #ifndef NO_PROFILE_COUNTERS
4074 #endif
4078 /* Accept -msseregparm only if at least SSE support is enabled. */
4084 {
4086 {
4088 {
4091 }
4094 {
4097 }
4098 }
4099 }
4100 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4101 fpmath=387. The second is however default at many targets since the
4102 extra 80bit precision of temporaries is considered to be part of ABI.
4103 Overwrite the default at least for -ffast-math.
4104 TODO: -mfpmath=both seems to produce same performing code with bit
4105 smaller binaries. It is however not clear if register allocation is
4106 ready for this setting.
4107 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4108 codegen. We may switch to 387 with -ffast-math for size optimized
4109 functions. */
4113 else
4116 /* If the i387 is disabled, then do not return values in it. */
4120 /* Use external vectorized library in vectorizing intrinsics. */
4123 {
4134 }
4140 /* If stack probes are required, the space used for large function
4141 arguments on the stack must also be probed, so enable
4142 -maccumulate-outgoing-args so this happens in the prologue. */
4145 {
4150 }
4152 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4153 {
4159 }
4161 /* When scheduling description is not available, disable scheduler pass
4162 so it won't slow down the compilation and make x87 code slower. */
4183 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4185 && HAVE_prefetch
4191 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4192 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4197 {
4200 {
4202 ix86_gen_tls_local_dynamic_base_64
4204 }
4205 else
4206 {
4208 ix86_gen_tls_local_dynamic_base_64
4210 }
4211 }
4212 else
4216 {
4226 }
4227 else
4228 {
4238 }
4240 #ifdef USE_IX86_CLD
4241 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4244 #endif
4247 {
4252 }
4254 {
4258 }
4260 {
4261 #if defined(PROFILE_BEFORE_PROLOGUE)
4263 #else
4265 #endif
4266 }
4276 /* Enable 128-bit AVX instruction generation
4277 for the auto-vectorizer. */
4283 {
4290 {
4293 {
4295 q++;
4296 }
4297 else
4302 else
4303 {
4306 {
4309 }
4312 {
4316 }
4317 }
4322 else
4324 }
4325 }
4332 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4333 for 64-bit Bionic. */
4338 ? MASK_LONG_DOUBLE_128
4341 /* Only one of them can be active. */
4345 /* Save the initial options in case the user does function specific
4346 options. */
4348 target_option_default_node = target_option_current_node
4351 /* Handle stack protector */
4353 opts->x_ix86_stack_protector_guard
4356 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4358 {
4362 }
4365 {
4369 }
4370 }
4372 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4374 static void
4376 {
4378 struct register_pass_info insert_vzeroupper_info
4381 };
4386 /* This needs to be done at start up. It's convenient to do it here. */
4388 }
4390 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4393 {
4397 }
4399 /* Update register usage after having seen the compiler flags. */
4401 static void
4403 {
4406 /* For 32-bit targets, squash the REX registers. */
4408 {
4415 }
4417 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4425 {
4426 /* Set/reset conditionally defined registers from
4427 CALL_USED_REGISTERS initializer. */
4431 /* Calculate registers of CLOBBERED_REGS register set
4432 as call used registers from GENERAL_REGS register set. */
4436 }
4438 /* If MMX is disabled, squash the registers. */
4444 /* If SSE is disabled, squash the registers. */
4450 /* If the FPU is disabled, squash the registers. */
4456 /* If AVX512F is disabled, squash the registers. */
4458 {
4464 }
4466 /* If MPX is disabled, squash the registers. */
4470 }
4472 \f
4473 /* Save the current options */
4475 static void
4478 {
4514 /* The fields are char but the variables are not; make sure the
4515 values fit in the fields. */
4520 }
4522 /* Restore the current options */
4524 static void
4527 {
4533 /* We don't change -fPIC. */
4571 /* TODO: ix86_cost should be chosen at instruction or function granuality
4572 so for cold code we use size_cost even in !optimize_size compilation. */
4575 else
4578 /* Recreate the arch feature tests if the arch changed */
4580 {
4585 }
4587 /* Recreate the tune optimization tests */
4590 }
4592 /* Adjust target options after streaming them in. This is mainly about
4593 reconciling them with global options. */
4595 static void
4597 {
4598 /* flag_pic is a global option, but ix86_cmodel is target saved option
4599 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4600 for PIC, or error out. */
4603 {
4622 }
4623 else
4625 {
4640 }
4641 }
4643 /* Print the current options */
4645 static void
4648 {
4666 {
4669 }
4670 }
4672 \f
4673 /* Inner function to process the attribute((target(...))), take an argument and
4674 set the current options from the argument. If we have a list, recursively go
4675 over the list. */
4677 static bool
4682 {
4686 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4687 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4688 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4689 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4690 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4692 enum ix86_opt_type
4693 {
4694 ix86_opt_unknown,
4695 ix86_opt_yes,
4696 ix86_opt_no,
4697 ix86_opt_str,
4698 ix86_opt_enum,
4699 ix86_opt_isa
4700 };
4702 static const struct
4703 {
4710 /* isa options */
4763 /* enum options */
4766 /* string options */
4770 /* flag options */
4772 OPT_mcld,
4773 MASK_CLD),
4776 OPT_mfancy_math_387,
4777 MASK_NO_FANCY_MATH_387),
4780 OPT_mieee_fp,
4781 MASK_IEEE_FP),
4784 OPT_minline_all_stringops,
4785 MASK_INLINE_ALL_STRINGOPS),
4788 OPT_minline_stringops_dynamically,
4789 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4792 OPT_mno_align_stringops,
4793 MASK_NO_ALIGN_STRINGOPS),
4796 OPT_mrecip,
4797 MASK_RECIP),
4799 };
4801 /* If this is a list, recurse to get the options. */
4803 {
4810 enum_opts_set))
4814 }
4817 {
4820 }
4822 /* Handle multiple arguments separated by commas. */
4826 {
4840 {
4844 }
4845 else
4846 {
4849 }
4851 /* Recognize no-xxx. */
4853 {
4857 }
4858 else
4861 /* Find the option. */
4865 {
4873 {
4878 }
4879 }
4881 /* Process the option. */
4883 {
4886 }
4889 {
4895 }
4898 {
4904 else
4906 }
4909 {
4911 {
4914 }
4915 else
4917 }
4920 {
4928 global_dc);
4929 else
4930 {
4933 }
4934 }
4936 else
4938 }
4941 }
4943 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4945 tree
4949 {
4964 /* Process each of the options on the chain. */
4969 /* If the changed options are different from the default, rerun
4970 ix86_option_override_internal, and then save the options away.
4971 The string options are are attribute options, and will be undone
4972 when we copy the save structure. */
4978 {
4979 /* If we are using the default tune= or arch=, undo the string assigned,
4980 and use the default. */
4991 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4996 {
4999 }
5001 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5004 /* Add any builtin functions with the new isa if any. */
5007 /* Save the current options unless we are validating options for
5008 #pragma. */
5015 /* Free up memory allocated to hold the strings */
5018 }
5021 }
5023 /* Hook to validate attribute((target("string"))). */
5025 static bool
5028 tree args,
5030 {
5035 /* attribute((target("default"))) does nothing, beyond
5036 affecting multi-versioning. */
5045 /* Get the optimization options of the current function. */
5051 /* Init func_options. */
5059 /* Initialize func_options to the default before its target options can
5060 be set. */
5073 {
5078 }
5081 }
5083 \f
5084 /* Hook to determine if one function can safely inline another. */
5086 static bool
5088 {
5093 /* If callee has no option attributes, then it is ok to inline. */
5097 /* If caller has no option attributes, but callee does then it is not ok to
5098 inline. */
5102 else
5103 {
5107 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5108 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5109 function. */
5114 /* See if we have the same non-isa options. */
5118 /* See if arch, tune, etc. are the same. */
5131 else
5133 }
5136 }
5138 \f
5139 /* Remember the last target of ix86_set_current_function. */
5142 /* Set targets globals to the default (or current #pragma GCC target
5143 if active). Invalidate ix86_previous_fndecl cache. */
5145 void
5147 {
5154 else
5157 }
5159 /* Establish appropriate back-end context for processing the function
5160 FNDECL. The argument might be NULL to indicate processing at top
5161 level, outside of any function scope. */
5162 static void
5164 {
5165 /* Only change the context if the function changes. This hook is called
5166 several times in the course of compiling a function, and we don't want to
5167 slow things down too much or call target_reinit when it isn't safe. */
5171 tree old_tree;
5176 else
5180 {
5184 }
5191 {
5197 else
5199 }
5201 }
5203 \f
5204 /* Return true if this goes in large data/bss. */
5206 static bool
5208 {
5212 /* Functions are never large data. */
5216 /* Automatic variables are never large data. */
5221 {
5227 }
5228 else
5229 {
5232 /* If this is an incomplete type with size 0, then we can't put it
5233 in data because it might be too big when completed. Also,
5234 int_size_in_bytes returns -1 if size can vary or is larger than
5235 an integer in which case also it is safer to assume that it goes in
5236 large data. */
5239 }
5242 }
5244 /* Switch to the appropriate section for output of DECL.
5245 DECL is either a `VAR_DECL' node or a constant of some sort.
5246 RELOC indicates whether forming the initial value of DECL requires
5247 link-time relocations. */
5252 {
5254 {
5258 {
5292 /* We don't split these for medium model. Place them into
5293 default sections and hope for best. */
5295 }
5297 {
5298 /* We might get called with string constants, but get_named_section
5299 doesn't like them as they are not DECLs. Also, we need to set
5300 flags in that case. */
5304 }
5305 }
5307 }
5309 /* Select a set of attributes for section NAME based on the properties
5310 of DECL and whether or not RELOC indicates that DECL's initializer
5311 might contain runtime relocations. */
5313 static unsigned int ATTRIBUTE_UNUSED
5315 {
5329 }
5331 /* Build up a unique section name, expressed as a
5332 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5333 RELOC indicates whether the initial value of EXP requires
5334 link-time relocations. */
5336 static void ATTRIBUTE_UNUSED
5338 {
5340 {
5342 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5346 {
5370 /* We don't split these for medium model. Place them into
5371 default sections and hope for best. */
5373 }
5375 {
5382 /* If we're using one_only, then there needs to be a .gnu.linkonce
5383 prefix to the section name. */
5390 }
5391 }
5393 }
5395 #ifdef COMMON_ASM_OP
5396 /* This says how to output assembler code to declare an
5397 uninitialized external linkage data object.
5399 For medium model x86-64 we need to use .largecomm opcode for
5400 large objects. */
5401 void
5405 {
5409 else
5414 }
5415 #endif
5417 /* Utility function for targets to use in implementing
5418 ASM_OUTPUT_ALIGNED_BSS. */
5420 void
5423 {
5427 else
5430 #ifdef ASM_DECLARE_OBJECT_NAME
5433 #else
5434 /* Standard thing is just output label for the object. */
5438 }
5439 \f
5440 /* Decide whether we must probe the stack before any space allocation
5441 on this target. It's essentially TARGET_STACK_PROBE except when
5442 -fstack-check causes the stack to be already probed differently. */
5444 bool
5446 {
5447 /* Do not probe the stack twice if static stack checking is enabled. */
5452 }
5453 \f
5454 /* Decide whether we can make a sibling call to a function. DECL is the
5455 declaration of the function being targeted by the call and EXP is the
5456 CALL_EXPR representing the call. */
5458 static bool
5460 {
5464 /* If we are generating position-independent code, we cannot sibcall
5465 optimize any indirect call, or a direct call to a global function,
5466 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5468 && !TARGET_64BIT
5469 && flag_pic
5473 /* If we need to align the outgoing stack, then sibcalling would
5474 unalign the stack, which may break the called function. */
5480 {
5483 }
5484 else
5485 {
5486 /* We're looking at the CALL_EXPR, we need the type of the function. */
5491 }
5493 /* Check that the return value locations are the same. Like
5494 if we are returning floats on the 80387 register stack, we cannot
5495 make a sibcall from a function that doesn't return a float to a
5496 function that does or, conversely, from a function that does return
5497 a float to a function that doesn't; the necessary stack adjustment
5498 would not be executed. This is also the place we notice
5499 differences in the return value ABI. Note that it is ok for one
5500 of the functions to have void return type as long as the return
5501 value of the other is passed in a register. */
5506 {
5509 }
5511 ;
5516 {
5517 /* The SYSV ABI has more call-clobbered registers;
5518 disallow sibcalls from MS to SYSV. */
5522 }
5523 else
5524 {
5525 /* If this call is indirect, we'll need to be able to use a
5526 call-clobbered register for the address of the target function.
5527 Make sure that all such registers are not used for passing
5528 parameters. Note that DLLIMPORT functions are indirect. */
5531 {
5533 {
5534 /* ??? Need to count the actual number of registers to be used,
5535 not the possible number of registers. Fix later. */
5537 }
5538 }
5539 }
5541 /* Otherwise okay. That also includes certain types of indirect calls. */
5543 }
5545 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5546 and "sseregparm" calling convention attributes;
5547 arguments as in struct attribute_spec.handler. */
5549 static tree
5551 tree args,
5554 {
5559 {
5561 name);
5564 }
5566 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5568 {
5569 tree cst;
5572 {
5574 }
5577 {
5579 }
5583 {
5586 name);
5588 }
5590 {
5594 }
5597 }
5600 {
5601 /* Do not warn when emulating the MS ABI. */
5606 name);
5609 }
5611 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5613 {
5615 {
5617 }
5619 {
5621 }
5623 {
5625 }
5627 {
5629 }
5630 }
5632 /* Can combine stdcall with fastcall (redundant), regparm and
5633 sseregparm. */
5635 {
5637 {
5639 }
5641 {
5643 }
5645 {
5647 }
5648 }
5650 /* Can combine cdecl with regparm and sseregparm. */
5652 {
5654 {
5656 }
5658 {
5660 }
5662 {
5664 }
5665 }
5667 {
5670 name);
5672 {
5674 }
5676 {
5678 }
5680 {
5682 }
5683 }
5685 /* Can combine sseregparm with all attributes. */
5688 }
5690 /* The transactional memory builtins are implicitly regparm or fastcall
5691 depending on the ABI. Override the generic do-nothing attribute that
5692 these builtins were declared with, and replace it with one of the two
5693 attributes that we expect elsewhere. */
5695 static tree
5698 {
5699 tree alt;
5701 /* In no case do we want to add the placeholder attribute. */
5704 /* The 64-bit ABI is unchanged for transactional memory. */
5708 /* ??? Is there a better way to validate 32-bit windows? We have
5709 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5712 else
5713 {
5716 }
5720 }
5722 /* This function determines from TYPE the calling-convention. */
5724 unsigned int
5726 {
5729 tree attrs;
5736 {
5746 /* Regparam isn't allowed for thiscall and fastcall. */
5748 {
5753 }
5757 }
5764 || is_stdarg
5770 }
5772 /* Return 0 if the attributes for two types are incompatible, 1 if they
5773 are compatible, and 2 if they are nearly compatible (which causes a
5774 warning to be generated). */
5776 static int
5778 {
5794 }
5795 \f
5796 /* Return the regparm value for a function with the indicated TYPE and DECL.
5797 DECL may be NULL when calling function indirectly
5798 or considering a libcall. */
5800 static int
5802 {
5803 tree attr;
5814 {
5817 {
5820 }
5821 }
5827 /* Use register calling convention for local functions when possible. */
5830 {
5835 /* Caller and callee must agree on the calling convention, so
5836 checking here just optimize means that with
5837 __attribute__((optimize (...))) caller could use regparm convention
5838 and callee not, or vice versa. Instead look at whether the callee
5839 is optimized or not. */
5842 {
5845 {
5848 /* Make sure no regparm register is taken by a
5849 fixed register variable. */
5851 local_regparm++)
5855 /* We don't want to use regparm(3) for nested functions as
5856 these use a static chain pointer in the third argument. */
5860 /* Save a register for the split stack. */
5864 /* Each fixed register usage increases register pressure,
5865 so less registers should be used for argument passing.
5866 This functionality can be overriden by an explicit
5867 regparm value. */
5870 globals++;
5872 local_regparm
5877 }
5878 }
5879 }
5882 }
5884 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5885 DFmode (2) arguments in SSE registers for a function with the
5886 indicated TYPE and DECL. DECL may be NULL when calling function
5887 indirectly or considering a libcall. Otherwise return 0. */
5889 static int
5891 {
5894 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5895 by the sseregparm attribute. */
5898 {
5900 {
5902 {
5906 else
5909 }
5911 }
5914 }
5923 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5924 (and DFmode for SSE2) arguments in SSE registers. */
5926 /* TARGET_SSE_MATH */
5930 {
5933 {
5934 /* Refuse to produce wrong code when local function with SSE enabled
5935 is called from SSE disabled function.
5936 We may work hard to work out these scenarios but hopefully
5937 it doesnot matter in practice. */
5939 {
5943 }
5946 }
5947 }
5950 }
5952 /* Return true if EAX is live at the start of the function. Used by
5953 ix86_expand_prologue to determine if we need special help before
5954 calling allocate_stack_worker. */
5956 static bool
5958 {
5959 /* Cheat. Don't bother working forward from ix86_function_regparm
5960 to the function type to whether an actual argument is located in
5961 eax. Instead just look at cfg info, which is still close enough
5962 to correct at this point. This gives false positives for broken
5963 functions that might use uninitialized data that happens to be
5964 allocated in eax, but who cares? */
5966 }
5968 static bool
5970 {
5971 tree attr;
5974 {
5980 /* For 32-bit MS-ABI the default is to keep aggregate
5981 return pointer. */
5984 }
5986 }
5988 /* Value is the number of bytes of arguments automatically
5989 popped when returning from a subroutine call.
5990 FUNDECL is the declaration node of the function (as a tree),
5991 FUNTYPE is the data type of the function (as a tree),
5992 or for a library call it is an identifier node for the subroutine name.
5993 SIZE is the number of bytes of arguments passed on the stack.
5995 On the 80386, the RTD insn may be used to pop them if the number
5996 of args is fixed, but if the number is variable then the caller
5997 must pop them all. RTD can't be used for library calls now
5998 because the library is compiled with the Unix compiler.
5999 Use of RTD is a selectable option, since it is incompatible with
6000 standard Unix calling sequences. If the option is not selected,
6001 the caller must always pop the args.
6003 The attribute stdcall is equivalent to RTD on a per module basis. */
6005 static int
6007 {
6010 /* None of the 64-bit ABIs pop arguments. */
6021 /* Lose any fake structure return argument if it is passed on the stack. */
6024 {
6028 }
6031 }
6033 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6035 static bool
6037 {
6038 /* Check operand constraints in case hard registers were propagated
6039 into insn pattern. This check prevents combine pass from
6040 generating insn patterns with invalid hard register operands.
6041 These invalid insns can eventually confuse reload to error out
6042 with a spill failure. See also PRs 46829 and 46843. */
6044 {
6053 {
6061 /* For pre-AVX disallow unaligned loads/stores where the
6062 instructions don't support it. */
6066 {
6070 }
6072 /* A unary operator may be accepted by the predicate, but it
6073 is irrelevant for matching constraints. */
6078 {
6086 }
6093 /* Operand has no constraints, anything is OK. */
6098 {
6103 && operands_match_p
6107 {
6110 }
6111 }
6115 }
6116 }
6119 }
6120 \f
6121 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6123 static unsigned HOST_WIDE_INT
6125 {
6129 }
6130 \f
6131 /* Argument support functions. */
6133 /* Return true when register may be used to pass function parameters. */
6134 bool
6136 {
6144 {
6148 else
6154 }
6160 /* TODO: The function should depend on current function ABI but
6161 builtins.c would need updating then. Therefore we use the
6162 default ABI. */
6164 /* RAX is used as hidden argument to va_arg functions. */
6170 else
6177 }
6179 /* Return if we do not know how to pass TYPE solely in registers. */
6181 static bool
6183 {
6187 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6188 The layout_type routine is crafty and tries to trick us into passing
6189 currently unsupported vector types on the stack by using TImode. */
6192 }
6194 /* It returns the size, in bytes, of the area reserved for arguments passed
6195 in registers for the function represented by fndecl dependent to the used
6196 abi format. */
6197 int
6199 {
6203 else
6208 }
6210 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6211 call abi used. */
6212 enum calling_abi
6214 {
6216 {
6219 {
6221 {
6223 {
6226 {
6229 }
6230 }
6232 }
6233 }
6237 }
6239 }
6241 /* We add this as a workaround in order to use libc_has_function
6242 hook in i386.md. */
6243 bool
6245 {
6247 }
6249 static bool
6251 {
6253 {
6257 else
6259 }
6261 }
6263 static enum calling_abi
6265 {
6269 }
6271 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6272 call abi used. */
6273 enum calling_abi
6275 {
6279 }
6281 /* Write the extra assembler code needed to declare a function properly. */
6283 void
6285 tree decl)
6286 {
6290 {
6296 }
6298 #ifdef SUBTARGET_ASM_UNWIND_INIT
6300 #endif
6304 /* Output magic byte marker, if hot-patch attribute is set. */
6306 {
6308 {
6309 /* leaq [%rsp + 0], %rsp */
6312 }
6313 else
6314 {
6315 /* movl.s %edi, %edi
6316 push %ebp
6317 movl.s %esp, %ebp */
6320 }
6321 }
6322 }
6324 /* regclass.c */
6327 /* Implementation of call abi switching target hook. Specific to FNDECL
6328 the specific call register sets are set. See also
6329 ix86_conditional_register_usage for more details. */
6330 void
6332 {
6335 else
6337 }
6339 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6340 expensive re-initialization of init_regs each time we switch function context
6341 since this is needed only during RTL expansion. */
6342 static void
6344 {
6348 }
6350 /* Return 1 if pseudo register should be created and used to hold
6351 GOT address for PIC code. */
6352 bool
6354 {
6361 }
6363 /* Initialize large model PIC register. */
6365 static void
6367 {
6369 rtx tmp_reg;
6378 label));
6382 }
6384 /* Create and initialize PIC register if required. */
6385 static void
6387 {
6388 edge entry_edge;
6397 {
6400 else
6402 }
6403 else
6404 {
6405 /* If there is future mcount call in the function it is more profitable
6406 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6415 }
6423 }
6425 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6426 for a call to a function whose data type is FNTYPE.
6427 For a library call, FNTYPE is 0. */
6429 void
6433 tree fndecl,
6435 {
6442 {
6445 {
6449 }
6450 else
6452 }
6453 else
6458 /* Set up the number of registers to use for passing arguments. */
6461 {
6463 ? X86_64_REGPARM_MAX
6465 }
6467 {
6470 {
6472 ? X86_64_SSE_REGPARM_MAX
6474 }
6475 }
6483 /* Because type might mismatch in between caller and callee, we need to
6484 use actual type of function for local calls.
6485 FIXME: cgraph_analyze can be told to actually record if function uses
6486 va_start so for local functions maybe_vaarg can be made aggressive
6487 helping K&R code.
6488 FIXME: once typesytem is fixed, we won't need this code anymore. */
6501 {
6502 /* If there are variable arguments, then we won't pass anything
6503 in registers in 32-bit mode. */
6505 {
6514 }
6516 /* Use ecx and edx registers if function has fastcall attribute,
6517 else look for regparm information. */
6519 {
6522 {
6525 }
6527 {
6530 }
6531 else
6533 }
6535 /* Set up the number of SSE registers used for passing SFmode
6536 and DFmode arguments. Warn for mismatching ABI. */
6538 }
6539 }
6541 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6542 But in the case of vector types, it is some vector mode.
6544 When we have only some of our vector isa extensions enabled, then there
6545 are some modes for which vector_mode_supported_p is false. For these
6546 modes, the generic vector support in gcc will choose some non-vector mode
6547 in order to implement the type. By computing the natural mode, we'll
6548 select the proper ABI location for the operand and not depend on whatever
6549 the middle-end decides to do with these vector types.
6551 The midde-end can't deal with the vector types > 16 bytes. In this
6552 case, we return the original mode and warn ABI change if CUM isn't
6553 NULL.
6555 If INT_RETURN is true, warn ABI change if the vector mode isn't
6556 available for function return value. */
6558 static machine_mode
6561 {
6565 {
6568 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6570 {
6575 else
6578 /* Get the mode which has this inner mode and number of units. */
6582 {
6584 {
6589 {
6593 }
6595 {
6599 }
6602 }
6604 {
6609 {
6613 }
6615 {
6619 }
6622 }
6625 {
6630 {
6634 }
6636 {
6640 }
6641 }
6643 {
6648 {
6652 }
6654 {
6658 }
6659 }
6661 }
6664 }
6665 }
6668 }
6670 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6671 this may not agree with the mode that the type system has chosen for the
6672 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6673 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6675 static rtx
6678 {
6679 rtx tmp;
6683 else
6684 {
6688 }
6691 }
6693 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6694 of this code is to classify each 8bytes of incoming argument by the register
6695 class and assign registers accordingly. */
6697 /* Return the union class of CLASS1 and CLASS2.
6698 See the x86-64 PS ABI for details. */
6700 static enum x86_64_reg_class
6702 {
6703 /* Rule #1: If both classes are equal, this is the resulting class. */
6707 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6708 the other class. */
6714 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6718 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6726 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6727 MEMORY is used. */
6736 /* Rule #6: Otherwise class SSE is used. */
6738 }
6740 /* Classify the argument of type TYPE and mode MODE.
6741 CLASSES will be filled by the register class used to pass each word
6742 of the operand. The number of words is returned. In case the parameter
6743 should be passed in memory, 0 is returned. As a special case for zero
6744 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6746 BIT_OFFSET is used internally for handling records and specifies offset
6747 of the offset in bits modulo 512 to avoid overflow cases.
6749 See the x86-64 PS ABI for details.
6750 */
6752 static int
6755 {
6756 HOST_WIDE_INT bytes =
6758 int words
6761 /* Variable sized entities are always passed/returned in memory. */
6770 {
6772 tree field;
6775 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6782 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6783 signalize memory class, so handle it as special case. */
6785 {
6788 }
6790 /* Classify each field of record and merge classes. */
6792 {
6794 /* And now merge the fields of structure. */
6796 {
6798 {
6804 /* Bitfields are always classified as integer. Handle them
6805 early, since later code would consider them to be
6806 misaligned integers. */
6808 {
6817 }
6818 else
6819 {
6824 /* Flexible array member is ignored. */
6831 {
6835 {
6838 "the ABI of passing struct with"
6839 " a flexible array member has"
6841 }
6843 }
6845 subclasses,
6855 }
6856 }
6857 }
6861 /* Arrays are handled as small records. */
6862 {
6869 /* The partial classes are now full classes. */
6880 }
6883 /* Unions are similar to RECORD_TYPE but offset is always 0.
6884 */
6886 {
6888 {
6896 bit_offset);
6901 }
6902 }
6907 }
6910 {
6911 /* When size > 16 bytes, if the first one isn't
6912 X86_64_SSE_CLASS or any other ones aren't
6913 X86_64_SSEUP_CLASS, everything should be passed in
6914 memory. */
6921 }
6923 /* Final merger cleanup. */
6925 {
6926 /* If one class is MEMORY, everything should be passed in
6927 memory. */
6931 /* The X86_64_SSEUP_CLASS should be always preceded by
6932 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6936 {
6937 /* The first one should never be X86_64_SSEUP_CLASS. */
6940 }
6942 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6943 everything should be passed in memory. */
6946 {
6949 /* The first one should never be X86_64_X87UP_CLASS. */
6952 {
6955 "the ABI of passing union with long double"
6957 }
6959 }
6960 }
6962 }
6964 /* Compute alignment needed. We align all types to natural boundaries with
6965 exception of XFmode that is aligned to 64bits. */
6967 {
6976 /* Misaligned fields are always returned in memory. */
6979 }
6981 /* for V1xx modes, just use the base mode */
6986 /* Classification of atomic types. */
6988 {
7004 {
7007 /* Analyze last 128 bits only. */
7011 {
7014 }
7016 {
7019 }
7021 {
7025 }
7027 {
7030 }
7031 else
7033 }
7040 /* OImode shouldn't be used directly. */
7047 else
7065 else
7066 {
7070 {
7073 "the ABI of passing structure with complex float"
7075 }
7078 }
7087 /* This modes is larger than 16 bytes. */
7145 else
7149 }
7150 }
7152 /* Examine the argument and return set number of register required in each
7153 class. Return true iff parameter should be passed in memory. */
7155 static bool
7158 {
7169 {
7190 }
7193 }
7195 /* Construct container for the argument used by GCC interface. See
7196 FUNCTION_ARG for the detailed description. */
7198 static rtx
7202 {
7203 /* The following variables hold the static issued_error state. */
7208 machine_mode tmpmode;
7217 rtx ret;
7228 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7229 some less clueful developer tries to use floating-point anyway. */
7231 {
7233 {
7235 {
7238 }
7239 }
7241 {
7244 }
7246 }
7248 /* Likewise, error if the ABI requires us to return values in the
7249 x87 registers and the user specified -mno-80387. */
7255 {
7257 {
7260 }
7262 }
7264 /* First construct simple cases. Avoid SCmode, since we want to use
7265 single register to pass this type. */
7268 {
7283 /* Zero sized array, struct or class. */
7287 }
7326 /* Otherwise figure out the entries of the PARALLEL. */
7328 {
7332 {
7337 /* Merge TImodes on aligned occasions here too. */
7339 tmpmode
7343 else
7345 /* We've requested 24 bytes we
7346 don't have mode for. Use DImode. */
7353 intreg++;
7361 sse_regno++;
7369 sse_regno++;
7374 {
7380 {
7382 i++;
7383 }
7384 else
7409 }
7415 sse_regno++;
7419 }
7420 }
7422 /* Empty aligned struct, union or class. */
7430 }
7432 /* Update the data in CUM to advance over an argument of mode MODE
7433 and data type TYPE. (TYPE is null for libcalls where that information
7434 may not be available.)
7436 Return a number of integer regsiters advanced over. */
7438 static int
7441 HOST_WIDE_INT words)
7442 {
7446 {
7453 /* FALLTHRU */
7465 {
7468 }
7472 /* OImode shouldn't be used directly. */
7481 /* FALLTHRU */
7503 {
7508 {
7511 }
7512 }
7522 {
7527 {
7530 }
7531 }
7533 }
7536 }
7538 static int
7541 {
7544 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7551 {
7557 }
7558 else
7559 {
7564 }
7565 }
7567 static int
7569 HOST_WIDE_INT words)
7570 {
7571 /* Otherwise, this should be passed indirect. */
7576 {
7580 }
7582 }
7584 /* Update the data in CUM to advance over an argument of mode MODE and
7585 data type TYPE. (TYPE is null for libcalls where that information
7586 may not be available.) */
7588 static void
7591 {
7598 else
7607 {
7608 /* If we pass bounds in BT then just update remained bounds count. */
7610 {
7613 }
7615 /* Update remained number of bounds to force. */
7622 }
7624 /* The first arg not going to Bounds Tables resets this counter. */
7626 /* For unnamed args we always pass bounds to avoid bounds mess when
7627 passed and received types do not match. If bounds do not follow
7628 unnamed arg, still pretend required number of bounds were passed. */
7630 {
7633 }
7639 else
7642 /* For stdarg we expect bounds to be passed for each value passed
7643 in register. */
7646 /* For pointers passed in memory we expect bounds passed in Bounds
7647 Table. */
7650 }
7652 /* Define where to put the arguments to a function.
7653 Value is zero to push the argument on the stack,
7654 or a hard register in which to store the argument.
7656 MODE is the argument's machine mode.
7657 TYPE is the data type of the argument (as a tree).
7658 This is null for libcalls where that information may
7659 not be available.
7660 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7661 the preceding args and about the function being called.
7662 NAMED is nonzero if this argument is a named parameter
7663 (otherwise it is an extra parameter matching an ellipsis). */
7665 static rtx
7669 {
7670 /* Avoid the AL settings for the Unix64 ABI. */
7675 {
7682 /* FALLTHRU */
7688 {
7691 /* Fastcall allocates the first two DWORD (SImode) or
7692 smaller arguments to ECX and EDX if it isn't an
7693 aggregate type . */
7695 {
7701 /* ECX not EAX is the first allocated register. */
7704 }
7706 }
7715 /* FALLTHRU */
7717 /* In 32bit, we pass TImode in xmm registers. */
7725 {
7729 }
7734 /* OImode and XImode shouldn't be used directly. */
7750 {
7754 }
7764 {
7768 }
7770 }
7773 }
7775 static rtx
7778 {
7779 /* Handle a hidden AL argument containing number of registers
7780 for varargs x86-64 functions. */
7784 ? X86_64_SSE_REGPARM_MAX
7789 {
7805 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7809 }
7815 }
7817 static rtx
7820 HOST_WIDE_INT bytes)
7821 {
7824 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7825 We use value of -2 to specify that current function call is MSABI. */
7829 /* If we've run out of registers, it goes on the stack. */
7835 /* Only floating point modes are passed in anything but integer regs. */
7837 {
7840 else
7841 {
7844 /* Unnamed floating parameters are passed in both the
7845 SSE and integer registers. */
7851 }
7852 }
7853 /* Handle aggregated types passed in register. */
7855 {
7860 }
7863 }
7865 /* Return where to put the arguments to a function.
7866 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7868 MODE is the argument's machine mode. TYPE is the data type of the
7869 argument. It is null for libcalls where that information may not be
7870 available. CUM gives information about the preceding args and about
7871 the function being called. NAMED is nonzero if this argument is a
7872 named parameter (otherwise it is an extra parameter matching an
7873 ellipsis). */
7875 static rtx
7878 {
7882 rtx arg;
7884 /* All pointer bounds argumntas are handled separately here. */
7887 {
7888 /* Return NULL if bounds are forced to go in Bounds Table. */
7891 /* Return the next available bound reg if any. */
7894 /* Return the next special slot number otherwise. */
7895 else
7899 }
7903 else
7907 /* To simplify the code below, represent vector types with a vector mode
7908 even if MMX/SSE are not active. */
7916 else
7920 }
7922 /* A C expression that indicates when an argument must be passed by
7923 reference. If nonzero for an argument, a copy of that argument is
7924 made in memory and a pointer to the argument is passed instead of
7925 the argument itself. The pointer is passed in whatever way is
7926 appropriate for passing a pointer to that type. */
7928 static bool
7931 {
7934 /* Bounds are never passed by reference. */
7939 /* See Windows x64 Software Convention. */
7941 {
7944 {
7945 /* Arrays are passed by reference. */
7950 {
7951 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7952 are passed by reference. */
7954 }
7955 }
7957 /* __m128 is passed by reference. */
7963 }
7964 }
7969 }
7971 /* Return true when TYPE should be 128bit aligned for 32bit argument
7972 passing ABI. XXX: This function is obsolete and is only used for
7973 checking psABI compatibility with previous versions of GCC. */
7975 static bool
7977 {
7989 {
7990 /* Walk the aggregates recursively. */
7992 {
7996 {
7997 tree field;
7999 /* Walk all the structure fields. */
8001 {
8005 }
8007 }
8010 /* Just for use if some languages passes arrays by value. */
8017 }
8018 }
8020 }
8022 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8023 XXX: This function is obsolete and is only used for checking psABI
8024 compatibility with previous versions of GCC. */
8026 static unsigned int
8029 {
8030 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8031 natural boundaries. */
8033 {
8034 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8035 make an exception for SSE modes since these require 128bit
8036 alignment.
8038 The handling here differs from field_alignment. ICC aligns MMX
8039 arguments to 4 byte boundaries, while structure fields are aligned
8040 to 8 byte boundaries. */
8042 {
8045 }
8046 else
8047 {
8050 }
8051 }
8055 }
8057 /* Return true when TYPE should be 128bit aligned for 32bit argument
8058 passing ABI. */
8060 static bool
8062 {
8072 {
8073 /* Walk the aggregates recursively. */
8075 {
8079 {
8080 tree field;
8082 /* Walk all the structure fields. */
8084 field;
8086 {
8090 }
8092 }
8095 /* Just for use if some languages passes arrays by value. */
8102 }
8103 }
8104 else
8108 }
8110 /* Gives the alignment boundary, in bits, of an argument with the
8111 specified mode and type. */
8113 static unsigned int
8115 {
8118 {
8119 /* Since the main variant type is used for call, we convert it to
8120 the main variant type. */
8123 }
8124 else
8128 else
8129 {
8134 {
8135 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8137 {
8140 }
8146 }
8149 && !warned
8151 saved_align))
8152 {
8155 "The ABI for passing parameters with %d-byte"
8158 }
8159 }
8162 }
8164 /* Return true if N is a possible register number of function value. */
8166 static bool
8168 {
8170 {
8182 /* Complex values are returned in %st(0)/%st(1) pair. */
8185 /* TODO: The function should depend on current function ABI but
8186 builtins.c would need updating then. Therefore we use the
8187 default ABI. */
8192 /* Complex values are returned in %xmm0/%xmm1 pair. */
8201 }
8204 }
8206 /* Define how to find the value returned by a function.
8207 VALTYPE is the data type of the value (as a tree).
8208 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8209 otherwise, FUNC is 0. */
8211 static rtx
8214 {
8217 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8218 we normally prevent this case when mmx is not available. However
8219 some ABIs may require the result to be returned like DImode. */
8223 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8224 we prevent this case when sse is not available. However some ABIs
8225 may require the result to be returned like integer TImode. */
8230 /* 32-byte vector modes in %ymm0. */
8234 /* 64-byte vector modes in %zmm0. */
8238 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8241 else
8242 /* Most things go in %eax. */
8245 /* Override FP return register with %xmm0 for local functions when
8246 SSE math is enabled or for functions with sseregparm attribute. */
8248 {
8253 }
8255 /* OImode shouldn't be used directly. */
8259 }
8261 static rtx
8263 const_tree valtype)
8264 {
8265 rtx ret;
8267 /* Handle libcalls, which don't provide a type node. */
8269 {
8273 {
8292 }
8295 }
8297 {
8298 /* Pointers are always returned in word_mode. */
8300 }
8306 /* For zero sized structures, construct_container returns NULL, but we
8307 need to keep rest of compiler happy by returning meaningful value. */
8312 }
8314 static rtx
8316 const_tree valtype)
8317 {
8321 {
8323 {
8342 }
8343 }
8345 }
8347 static rtx
8350 {
8365 else
8367 }
8369 static rtx
8371 {
8377 }
8379 /* Return an RTX representing a place where a function returns
8380 or recieves pointer bounds or NULL if no bounds are returned.
8382 VALTYPE is a data type of a value returned by the function.
8384 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8385 or FUNCTION_TYPE of the function.
8387 If OUTGOING is false, return a place in which the caller will
8388 see the return value. Otherwise, return a place where a
8389 function returns a value. */
8391 static rtx
8393 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8395 {
8401 {
8402 bitmap slots;
8404 bitmap_iterator bi;
8412 {
8417 }
8423 }
8424 else
8428 }
8430 /* Pointer function arguments and return values are promoted to
8431 word_mode. */
8433 static machine_mode
8437 {
8439 {
8442 }
8444 for_return);
8445 }
8447 /* Return true if a structure, union or array with MODE containing FIELD
8448 should be accessed using BLKmode. */
8450 static bool
8452 {
8453 /* Union with XFmode must be in BLKmode. */
8457 }
8459 rtx
8461 {
8463 }
8465 /* Return true iff type is returned in memory. */
8467 static bool
8469 {
8470 #ifdef SUBTARGET_RETURN_IN_MEMORY
8472 #else
8474 HOST_WIDE_INT size;
8480 {
8482 {
8485 /* __m128 is returned in xmm0. */
8494 /* Otherwise, the size must be exactly in [1248]. */
8496 }
8497 else
8498 {
8503 }
8504 }
8505 else
8506 {
8516 {
8517 /* User-created vectors small enough to fit in EAX. */
8521 /* Unless ABI prescibes otherwise,
8522 MMX/3dNow values are returned in MM0 if available. */
8527 /* SSE values are returned in XMM0 if available. */
8531 /* AVX values are returned in YMM0 if available. */
8535 /* AVX512F values are returned in ZMM0 if available. */
8538 }
8546 /* OImode shouldn't be used directly. */
8550 }
8551 #endif
8552 }
8554 \f
8555 /* Create the va_list data type. */
8557 /* Returns the calling convention specific va_list date type.
8558 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8560 static tree
8562 {
8565 /* For i386 we use plain pointer to argument area. */
8575 unsigned_type_node);
8578 unsigned_type_node);
8581 ptr_type_node);
8584 ptr_type_node);
8603 /* The correct type is an array type of one element. */
8605 }
8607 /* Setup the builtin va_list data type and for 64-bit the additional
8608 calling convention specific va_list data types. */
8610 static tree
8612 {
8615 /* Initialize abi specific va_list builtin types. */
8617 {
8618 tree t;
8620 {
8625 }
8626 else
8627 {
8632 }
8634 {
8639 }
8640 else
8641 {
8646 }
8647 }
8650 }
8652 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8654 static void
8656 {
8658 alias_set_type set;
8661 /* GPR size of varargs save area. */
8664 else
8667 /* FPR size of varargs save area. We don't need it if we don't pass
8668 anything in SSE registers. */
8671 else
8685 {
8693 }
8696 {
8697 machine_mode smode;
8699 rtx test;
8701 /* Now emit code to save SSE registers. The AX parameter contains number
8702 of SSE parameter registers used to call this function, though all we
8703 actually check here is the zero/non-zero status. */
8708 label));
8710 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8711 we used movdqa (i.e. TImode) instead? Perhaps even better would
8712 be if we could determine the real mode of the data, via a hook
8713 into pass_stdarg. Ignore all that for now. */
8723 {
8732 }
8735 }
8736 }
8738 static void
8740 {
8744 /* Reset to zero, as there might be a sysv vaarg used
8745 before. */
8750 {
8761 }
8762 }
8764 static void
8767 {
8769 CUMULATIVE_ARGS next_cum;
8770 tree fntype;
8772 /* This argument doesn't appear to be used anymore. Which is good,
8773 because the old code here didn't suppress rtl generation. */
8781 /* For varargs, we do not want to skip the dummy va_dcl argument.
8782 For stdargs, we do want to skip the last named argument. */
8790 else
8792 }
8794 static void
8797 tree type,
8800 {
8802 CUMULATIVE_ARGS next_cum;
8803 tree fntype;
8804 rtx save_area;
8809 /* Do nothing if we use plain pointer to argument area. */
8815 /* For varargs, we do not want to skip the dummy va_dcl argument.
8816 For stdargs, we do want to skip the last named argument. */
8830 {
8835 rtx bounds;
8839 else
8840 {
8841 rtx ldx_addr =
8848 }
8854 bnd_reg++;
8855 }
8856 }
8859 /* Checks if TYPE is of kind va_list char *. */
8861 static bool
8863 {
8864 tree canonic;
8866 /* For 32-bit it is always true. */
8872 }
8874 /* Implement va_start. */
8876 static void
8878 {
8882 tree type;
8883 rtx ovf_rtx;
8887 {
8890 /* When we are splitting the stack, we can't refer to the stack
8891 arguments using internal_arg_pointer, because they may be on
8892 the old stack. The split stack prologue will arrange to
8893 leave a pointer to the old stack arguments in a scratch
8894 register, which we here copy to a pseudo-register. The split
8895 stack prologue can't set the pseudo-register directly because
8896 it (the prologue) runs before any registers have been saved. */
8900 {
8901 rtx reg;
8915 }
8916 }
8918 /* Only 64bit target needs something special. */
8920 {
8923 else
8924 {
8934 /* Store zero bounds for va_list. */
8938 next));
8940 }
8942 }
8951 /* The following should be folded into the MEM_REF offset. */
8961 /* Count number of gp and fp argument registers used. */
8967 {
8973 }
8976 {
8982 }
8984 /* Find the overflow area. */
8988 else
8994 /* Store zero bounds for overflow area pointer. */
9003 {
9004 /* Find the register save area.
9005 Prologue of the function save it right above stack frame. */
9011 /* Store zero bounds for save area pointer. */
9018 }
9019 }
9021 /* Implement va_arg. */
9023 static tree
9026 {
9033 rtx container;
9035 tree ptrtype;
9036 machine_mode nat_mode;
9039 /* Only 64bit target needs something special. */
9063 {
9076 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9078 {
9081 }
9089 }
9091 /* Pull the value out of the saved registers. */
9096 {
9110 /* In case we are passing structure, verify that it is consecutive block
9111 on the register save area. If not we need to do moves. */
9113 {
9114 /* Verify that all registers are strictly consecutive */
9116 {
9120 {
9125 }
9126 }
9127 else
9128 {
9132 {
9137 }
9138 }
9139 }
9141 {
9144 }
9145 else
9146 {
9149 }
9151 /* First ensure that we fit completely in registers. */
9153 {
9160 }
9162 {
9170 }
9172 /* Compute index to start of area used for integer regs. */
9174 {
9175 /* int_addr = gpr + sav; */
9178 }
9180 {
9181 /* sse_addr = fpr + sav; */
9184 }
9186 {
9190 /* addr = &temp; */
9195 {
9199 tree piece_type;
9200 tree addr_type;
9201 tree daddr_type;
9210 {
9215 }
9219 else
9226 {
9229 }
9230 else
9231 {
9234 }
9241 {
9246 }
9247 else
9248 {
9249 tree copy
9254 }
9256 }
9257 }
9260 {
9264 }
9267 {
9271 }
9276 }
9278 /* ... otherwise out of the overflow area. */
9280 /* When we align parameter on stack for caller, if the parameter
9281 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9282 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9283 here with caller. */
9288 /* Care for on-stack alignment if needed. */
9291 else
9292 {
9297 }
9314 }
9315 \f
9316 /* Return true if OPNUM's MEM should be matched
9317 in movabs* patterns. */
9319 bool
9321 {
9333 }
9334 \f
9335 /* Initialize the table of extra 80387 mathematical constants. */
9337 static void
9339 {
9341 {
9347 };
9351 {
9353 /* Ensure each constant is rounded to XFmode precision. */
9356 }
9359 }
9361 /* Return non-zero if the constant is something that
9362 can be loaded with a special instruction. */
9364 int
9366 {
9369 REAL_VALUE_TYPE r;
9381 /* For XFmode constants, try to find a special 80387 instruction when
9382 optimizing for size or on those CPUs that benefit from them. */
9385 {
9394 }
9396 /* Load of the constant -0.0 or -1.0 will be split as
9397 fldz;fchs or fld1;fchs sequence. */
9404 }
9406 /* Return the opcode of the special instruction to be used to load
9407 the constant X. */
9411 {
9413 {
9433 }
9434 }
9436 /* Return the CONST_DOUBLE representing the 80387 constant that is
9437 loaded by the specified special instruction. The argument IDX
9438 matches the return value from standard_80387_constant_p. */
9440 rtx
9442 {
9449 {
9460 }
9463 XFmode);
9464 }
9466 /* Return 1 if X is all 0s and 2 if x is all 1s
9467 in supported SSE/AVX vector mode. */
9469 int
9471 {
9472 machine_mode mode;
9483 {
9504 }
9507 }
9509 /* Return the opcode of the special instruction to be used to load
9510 the constant X. */
9514 {
9516 {
9519 {
9546 }
9556 else
9561 }
9563 }
9565 /* Returns true if OP contains a symbol reference */
9567 bool
9569 {
9578 {
9580 {
9586 }
9590 }
9593 }
9595 /* Return true if it is appropriate to emit `ret' instructions in the
9596 body of a function. Do this only if the epilogue is simple, needing a
9597 couple of insns. Prior to reloading, we can't tell how many registers
9598 must be saved, so return false then. Return false if there is no frame
9599 marker to de-allocate. */
9601 bool
9603 {
9609 /* Don't allow more than 32k pop, since that's all we can do
9610 with one instruction. */
9617 }
9618 \f
9619 /* Value should be nonzero if functions must have frame pointers.
9620 Zero means the frame pointer need not be set up (and parms may
9621 be accessed via the stack pointer) in functions that seem suitable. */
9623 static bool
9625 {
9626 /* If we accessed previous frames, then the generated code expects
9627 to be able to access the saved ebp value in our frame. */
9631 /* Several x86 os'es need a frame pointer for other reasons,
9632 usually pertaining to setjmp. */
9636 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9640 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9641 allocation is 4GB. */
9645 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9646 turns off the frame pointer by default. Turn it back on now if
9647 we've not got a leaf function. */
9657 }
9659 /* Record that the current function accesses previous call frames. */
9661 void
9663 {
9665 }
9666 \f
9667 #ifndef USE_HIDDEN_LINKONCE
9668 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9669 # define USE_HIDDEN_LINKONCE 1
9670 # else
9671 # define USE_HIDDEN_LINKONCE 0
9672 # endif
9673 #endif
9677 /* Fills in the label name that should be used for a pc thunk for
9678 the given register. */
9680 static void
9682 {
9687 else
9689 }
9692 /* This function generates code for -fpic that loads %ebx with
9693 the return address of the caller and then returns. */
9695 static void
9697 {
9702 {
9704 tree decl;
9720 #if TARGET_MACHO
9722 {
9731 }
9732 else
9733 #endif
9735 {
9746 }
9747 else
9748 {
9751 }
9757 /* Make sure unwind info is emitted for the thunk if needed. */
9760 /* Pad stack IP move with 4 instructions (two NOPs count
9761 as one instruction). */
9763 {
9768 }
9779 }
9783 }
9785 /* Emit code for the SET_GOT patterns. */
9789 {
9795 {
9796 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9801 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9802 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9803 an unadorned address. */
9808 }
9813 {
9815 /* We don't need a pic base, we're not producing pic. */
9822 }
9823 else
9824 {
9833 #if TARGET_MACHO
9834 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9835 This is what will be referenced by the Mach-O PIC subsystem. */
9839 /* When we are restoring the pic base at the site of a nonlocal label,
9840 and we decided to emit the pic base above, we will still output a
9841 local label used for calculating the correction offset (even though
9842 the offset will be 0 in that case). */
9846 #endif
9847 }
9853 }
9855 /* Generate an "push" pattern for input ARG. */
9857 static rtx
9859 {
9872 stack_pointer_rtx)),
9873 arg);
9874 }
9876 /* Generate an "pop" pattern for input ARG. */
9878 static rtx
9880 {
9885 arg,
9888 stack_pointer_rtx)));
9889 }
9891 /* Return >= 0 if there is an unused call-clobbered register available
9892 for the entire function. */
9894 static unsigned int
9896 {
9903 {
9905 /* Can't use the same register for both PIC and DRAP. */
9908 else
9913 }
9916 }
9918 /* Return TRUE if we need to save REGNO. */
9920 static bool
9922 {
9925 {
9927 {
9928 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9929 _mcount in prologue. */
9932 }
9939 }
9942 {
9945 {
9951 }
9952 }
9963 }
9965 /* Return number of saved general prupose registers. */
9967 static int
9969 {
9975 nregs ++;
9977 }
9979 /* Return number of saved SSE registrers. */
9981 static int
9983 {
9991 nregs ++;
9993 }
9995 /* Given FROM and TO register numbers, say whether this elimination is
9996 allowed. If stack alignment is needed, we can only replace argument
9997 pointer with hard frame pointer, or replace frame pointer with stack
9998 pointer. Otherwise, frame pointer elimination is automatically
9999 handled and all other eliminations are valid. */
10001 static bool
10003 {
10009 else
10011 }
10013 /* Return the offset between two registers, one to be eliminated, and the other
10014 its replacement, at the start of a routine. */
10016 HOST_WIDE_INT
10018 {
10027 else
10028 {
10036 }
10037 }
10039 /* In a dynamically-aligned function, we can't know the offset from
10040 stack pointer to frame pointer, so we must ensure that setjmp
10041 eliminates fp against the hard fp (%ebp) rather than trying to
10042 index from %esp up to the top of the frame across a gap that is
10043 of unknown (at compile-time) size. */
10044 static rtx
10046 {
10048 }
10050 /* When using -fsplit-stack, the allocation routines set a field in
10051 the TCB to the bottom of the stack plus this much space, measured
10052 in bytes. */
10054 #define SPLIT_STACK_AVAILABLE 256
10056 /* Fill structure ix86_frame about frame of currently computed function. */
10058 static void
10060 {
10062 HOST_WIDE_INT offset;
10065 HOST_WIDE_INT to_allocate;
10070 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10071 function prologues and leaf. */
10075 {
10078 }
10079 /* preferred_stack_boundary is never updated for call
10080 expanded from tls descriptor. Update it here. We don't update it in
10081 expand stage because according to the comments before
10082 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10083 away. */
10086 {
10090 }
10099 /* For SEH we have to limit the amount of code movement into the prologue.
10100 At present we do this via a BLOCKAGE, at which point there's very little
10101 scheduling that can be done, which means that there's very little point
10102 in doing anything except PUSHs. */
10106 /* During reload iteration the amount of registers saved can change.
10107 Recompute the value as needed. Do not recompute when amount of registers
10108 didn't change as reload does multiple calls to the function and does not
10109 expect the decision to change within single iteration. */
10112 {
10118 /* The fast prologue uses move instead of push to save registers. This
10119 is significantly longer, but also executes faster as modern hardware
10120 can execute the moves in parallel, but can't do that for push/pop.
10122 Be careful about choosing what prologue to emit: When function takes
10123 many instructions to execute we may use slow version as well as in
10124 case function is known to be outside hot spot (this is known with
10125 feedback only). Weight the size of function by number of registers
10126 to save as it is cheap to use one or two push instructions but very
10127 slow to use many of them. */
10131 || (flag_branch_probabilities
10134 else
10137 }
10139 frame->save_regs_using_mov
10141 /* If static stack checking is enabled and done with probes,
10142 the registers need to be saved before allocating the frame. */
10145 /* Skip return address. */
10148 /* Skip pushed static chain. */
10152 /* Skip saved base pointer. */
10157 /* The traditional frame pointer location is at the top of the frame. */
10160 /* Register save area */
10164 /* On SEH target, registers are pushed just before the frame pointer
10165 location. */
10169 /* Align and set SSE register save area. */
10171 {
10172 /* The only ABI that has saved SSE registers (Win64) also has a
10173 16-byte aligned default stack, and thus we don't need to be
10174 within the re-aligned local stack frame to save them. */
10178 }
10181 /* The re-aligned stack starts here. Values before this point are not
10182 directly comparable with values below this point. In order to make
10183 sure that no value happens to be the same before and after, force
10184 the alignment computation below to add a non-zero value. */
10188 /* Va-arg area */
10192 /* Align start of frame for local function. */
10201 /* Frame pointer points here. */
10206 /* Add outgoing arguments area. Can be skipped if we eliminated
10207 all the function calls as dead code.
10208 Skipping is however impossible when function calls alloca. Alloca
10209 expander assumes that last crtl->outgoing_args_size
10210 of stack frame are unused. */
10214 {
10217 }
10218 else
10221 /* Align stack boundary. Only needed if we're calling another function
10222 or using alloca. */
10227 /* We've reached end of stack frame. */
10230 /* Size prologue needs to allocate. */
10241 {
10247 }
10248 else
10252 /* The SEH frame pointer location is near the bottom of the frame.
10253 This is enforced by the fact that the difference between the
10254 stack pointer and the frame pointer is limited to 240 bytes in
10255 the unwind data structure. */
10257 {
10258 HOST_WIDE_INT diff;
10260 /* If we can leave the frame pointer where it is, do so. Also, returns
10261 the establisher frame for __builtin_frame_address (0). */
10266 {
10267 /* Ideally we'd determine what portion of the local stack frame
10268 (within the constraint of the lowest 240) is most heavily used.
10269 But without that complication, simply bias the frame pointer
10270 by 128 bytes so as to maximize the amount of the local stack
10271 frame that is addressable with 8-bit offsets. */
10273 }
10274 }
10275 }
10277 /* This is semi-inlined memory_address_length, but simplified
10278 since we know that we're always dealing with reg+offset, and
10279 to avoid having to create and discard all that rtl. */
10283 {
10287 {
10288 /* EBP and R13 cannot be encoded without an offset. */
10290 }
10294 /* ESP and R12 must be encoded with a SIB byte. */
10296 len++;
10299 }
10301 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10302 The valid base registers are taken from CFUN->MACHINE->FS. */
10304 static rtx
10306 {
10312 {
10313 /* Choose the base register most likely to allow the most scheduling
10314 opportunities. Generally FP is valid throughout the function,
10315 while DRAP must be reloaded within the epilogue. But choose either
10316 over the SP due to increased encoding size. */
10319 {
10322 }
10324 {
10327 }
10329 {
10332 }
10333 }
10334 else
10335 {
10336 HOST_WIDE_INT toffset;
10339 /* Choose the base register with the smallest address encoding.
10340 With a tie, choose FP > DRAP > SP. */
10342 {
10346 }
10348 {
10352 {
10356 }
10357 }
10359 {
10363 {
10367 }
10368 }
10369 }
10373 }
10375 /* Emit code to save registers in the prologue. */
10377 static void
10379 {
10385 {
10388 }
10389 }
10391 /* Emit a single register save at CFA - CFA_OFFSET. */
10393 static void
10395 HOST_WIDE_INT cfa_offset)
10396 {
10404 /* For SSE saves, we need to indicate the 128-bit alignment. */
10415 /* When saving registers into a re-aligned local stack frame, avoid
10416 any tricky guessing by dwarf2out. */
10418 {
10422 {
10423 /* A bit of a hack. We force the DRAP register to be saved in
10424 the re-aligned stack frame, which provides us with a copy
10425 of the CFA that will last past the prologue. Install it. */
10431 }
10432 else
10433 {
10434 /* The frame pointer is a stable reference within the
10435 aligned frame. Use it. */
10442 }
10443 }
10445 /* The memory may not be relative to the current CFA register,
10446 which means that we may need to generate a new pattern for
10447 use by the unwind info. */
10449 {
10454 }
10455 }
10457 /* Emit code to save registers using MOV insns.
10458 First register is stored at CFA - CFA_OFFSET. */
10459 static void
10461 {
10466 {
10469 }
10470 }
10472 /* Emit code to save SSE registers using MOV insns.
10473 First register is stored at CFA - CFA_OFFSET. */
10474 static void
10476 {
10481 {
10484 }
10485 }
10489 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10490 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10491 Don't add the note if the previously saved value will be left untouched
10492 within stack red-zone till return, as unwinders can find the same value
10493 in the register and on the stack. */
10495 static void
10497 {
10503 {
10506 }
10507 else
10508 queued_cfa_restores
10510 }
10512 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10514 static void
10516 {
10517 rtx last;
10521 ;
10526 }
10528 /* Expand prologue or epilogue stack adjustment.
10529 The pattern exist to put a dependency on all ebp-based memory accesses.
10530 STYLE should be negative if instructions should be marked as frame related,
10531 zero if %r11 register is live and cannot be freely used and positive
10532 otherwise. */
10534 static void
10537 {
10539 rtx insn;
10546 else
10547 {
10548 rtx tmp;
10549 /* r11 is used by indirect sibcall return as well, set before the
10550 epilogue and used after the epilogue. */
10553 else
10554 {
10558 }
10564 }
10571 {
10572 rtx r;
10582 }
10584 {
10587 {
10591 }
10592 }
10595 {
10600 {
10603 }
10605 {
10608 }
10609 else
10610 {
10611 /* Else there are two possibilities: SP itself, which we set
10612 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10613 taken care of this by hand along the eh_return path. */
10616 }
10620 }
10621 }
10623 /* Find an available register to be used as dynamic realign argument
10624 pointer regsiter. Such a register will be written in prologue and
10625 used in begin of body, so it must not be
10626 1. parameter passing register.
10627 2. GOT pointer.
10628 We reuse static-chain register if it is available. Otherwise, we
10629 use DI for i386 and R13 for x86-64. We chose R13 since it has
10630 shorter encoding.
10632 Return: the regno of chosen register. */
10634 static unsigned int
10636 {
10640 {
10641 /* Use R13 for nested function or function need static chain.
10642 Since function with tail call may use any caller-saved
10643 registers in epilogue, DRAP must not use caller-saved
10644 register in such case. */
10649 }
10650 else
10651 {
10652 /* Use DI for nested function or function need static chain.
10653 Since function with tail call may use any caller-saved
10654 registers in epilogue, DRAP must not use caller-saved
10655 register in such case. */
10659 /* Reuse static chain register if it isn't used for parameter
10660 passing. */
10662 {
10666 }
10668 }
10669 }
10671 /* Return minimum incoming stack alignment. */
10673 static unsigned int
10675 {
10678 /* Prefer the one specified at command line. */
10681 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10682 if -mstackrealign is used, it isn't used for sibcall check and
10683 estimated stack alignment is 128bit. */
10685 && !TARGET_64BIT
10686 && ix86_force_align_arg_pointer
10689 else
10692 /* Incoming stack alignment can be changed on individual functions
10693 via force_align_arg_pointer attribute. We use the smallest
10694 incoming stack boundary. */
10700 /* The incoming stack frame has to be aligned at least at
10701 parm_stack_boundary. */
10705 /* Stack at entrance of main is aligned by runtime. We use the
10706 smallest incoming stack boundary. */
10714 }
10716 /* Update incoming stack boundary and estimated stack alignment. */
10718 static void
10720 {
10721 ix86_incoming_stack_boundary
10724 /* x86_64 vararg needs 16byte stack alignment for register save
10725 area. */
10730 }
10732 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10733 needed or an rtx for DRAP otherwise. */
10735 static rtx
10737 {
10742 {
10743 /* Assign DRAP to vDRAP and returns vDRAP */
10745 rtx drap_vreg;
10746 rtx arg_ptr;
10759 {
10762 }
10764 }
10765 else
10767 }
10769 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10771 static rtx
10773 {
10775 }
10778 rtx reg;
10780 };
10782 /* Return a short-lived scratch register for use on function entry.
10783 In 32-bit mode, it is valid only after the registers are saved
10784 in the prologue. This register must be released by means of
10785 release_scratch_register_on_entry once it is dead. */
10787 static void
10789 {
10795 {
10796 /* We always use R11 in 64-bit mode. */
10798 }
10799 else
10800 {
10802 bool fastcall_p
10804 bool thiscall_p
10808 int drap_regno
10811 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10812 for the static chain register. */
10816 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10817 for the static chain register. */
10822 /* ecx is the static chain register. */
10824 && !static_chain_p
10829 /* esi is the static chain register. */
10835 else
10836 {
10839 }
10840 }
10844 {
10847 }
10848 }
10850 /* Release a scratch register obtained from the preceding function. */
10852 static void
10854 {
10856 {
10860 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10866 }
10867 }
10869 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10871 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10873 static void
10875 {
10876 /* We skip the probe for the first interval + a small dope of 4 words and
10877 probe that many bytes past the specified size to maintain a protection
10878 area at the botton of the stack. */
10882 /* See if we have a constant small number of probes to generate. If so,
10883 that's the easy case. The run-time loop is made up of 11 insns in the
10884 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10885 for n # of intervals. */
10887 {
10891 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10892 values of N from 1 until it exceeds SIZE. If only one probe is
10893 needed, this will not generate any code. Then adjust and probe
10894 to PROBE_INTERVAL + SIZE. */
10896 {
10898 {
10901 }
10902 else
10909 }
10913 else
10921 /* Adjust back to account for the additional first interval. */
10925 }
10927 /* Otherwise, do the same as above, but in a loop. Note that we must be
10928 extra careful with variables wrapping around because we might be at
10929 the very top (or the very bottom) of the address space and we have
10930 to be able to handle this case properly; in particular, we use an
10931 equality test for the loop condition. */
10932 else
10933 {
10934 HOST_WIDE_INT rounded_size;
10940 /* Step 1: round SIZE to the previous multiple of the interval. */
10945 /* Step 2: compute initial and final value of the loop counter. */
10947 /* SP = SP_0 + PROBE_INTERVAL. */
10952 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10956 stack_pointer_rtx)));
10959 /* Step 3: the loop
10961 while (SP != LAST_ADDR)
10962 {
10963 SP = SP + PROBE_INTERVAL
10964 probe at SP
10965 }
10967 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10968 values of N from 1 until it is equal to ROUNDED_SIZE. */
10973 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10974 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10977 {
10982 }
10984 /* Adjust back to account for the additional first interval. */
10990 }
10994 /* Even if the stack pointer isn't the CFA register, we need to correctly
10995 describe the adjustments made to it, in particular differentiate the
10996 frame-related ones from the frame-unrelated ones. */
10998 {
11011 }
11013 /* Make sure nothing is scheduled before we are done. */
11015 }
11017 /* Adjust the stack pointer up to REG while probing it. */
11021 {
11031 /* Jump to END_LAB if SP == LAST_ADDR. */
11039 /* SP = SP + PROBE_INTERVAL. */
11043 /* Probe at SP. */
11054 }
11056 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11057 inclusive. These are offsets from the current stack pointer. */
11059 static void
11061 {
11062 /* See if we have a constant small number of probes to generate. If so,
11063 that's the easy case. The run-time loop is made up of 7 insns in the
11064 generic case while the compile-time loop is made up of n insns for n #
11065 of intervals. */
11067 {
11068 HOST_WIDE_INT i;
11070 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11071 it exceeds SIZE. If only one probe is needed, this will not
11072 generate any code. Then probe at FIRST + SIZE. */
11079 }
11081 /* Otherwise, do the same as above, but in a loop. Note that we must be
11082 extra careful with variables wrapping around because we might be at
11083 the very top (or the very bottom) of the address space and we have
11084 to be able to handle this case properly; in particular, we use an
11085 equality test for the loop condition. */
11086 else
11087 {
11094 /* Step 1: round SIZE to the previous multiple of the interval. */
11099 /* Step 2: compute initial and final value of the loop counter. */
11101 /* TEST_OFFSET = FIRST. */
11104 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11108 /* Step 3: the loop
11110 while (TEST_ADDR != LAST_ADDR)
11111 {
11112 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11113 probe at TEST_ADDR
11114 }
11116 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11117 until it is equal to ROUNDED_SIZE. */
11122 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11123 that SIZE is equal to ROUNDED_SIZE. */
11128 stack_pointer_rtx,
11133 }
11135 /* Make sure nothing is scheduled before we are done. */
11137 }
11139 /* Probe a range of stack addresses from REG to END, inclusive. These are
11140 offsets from the current stack pointer. */
11144 {
11154 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11162 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11166 /* Probe at TEST_ADDR. */
11179 }
11181 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11182 to be generated in correct form. */
11183 static void
11185 {
11186 /* Check if stack realign is really needed after reload, and
11187 stores result in cfun */
11188 unsigned int incoming_stack_boundary
11197 {
11198 /* After stack_realign_needed is finalized, we can't no longer
11199 change it. */
11202 }
11204 /* If the only reason for frame_pointer_needed is that we conservatively
11205 assumed stack realignment might be needed, but in the end nothing that
11206 needed the stack alignment had been spilled, clear frame_pointer_needed
11207 and say we don't need stack realignment. */
11209 && frame_pointer_needed
11211 && flag_omit_frame_pointer
11213 && !ix86_current_function_calls_tls_descriptor
11222 {
11224 basic_block bb;
11231 HARD_FRAME_POINTER_REGNUM);
11233 {
11238 set_up_by_prologue))
11239 {
11243 }
11244 }
11246 /* If drap has been set, but it actually isn't live at the start
11247 of the function, there is no reason to set it up. */
11249 {
11252 {
11255 }
11256 }
11257 else
11272 }
11276 }
11278 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11280 static void
11282 {
11288 {
11291 {
11297 }
11298 }
11299 }
11301 /* Expand the prologue into a bunch of separate insns. */
11303 void
11305 {
11309 HOST_WIDE_INT allocate;
11315 /* DRAP should not coexist with stack_realign_fp */
11320 /* Initialize CFA state for before the prologue. */
11324 /* Track SP offset to the CFA. We continue tracking this after we've
11325 swapped the CFA register away from SP. In the case of re-alignment
11326 this is fudged; we're interested to offsets within the local frame. */
11333 {
11334 /* We should have already generated an error for any use of
11335 ms_hook on a nested function. */
11338 /* Check if profiling is active and we shall use profiling before
11339 prologue variant. If so sorry. */
11344 /* In ix86_asm_output_function_label we emitted:
11345 8b ff movl.s %edi,%edi
11346 55 push %ebp
11347 8b ec movl.s %esp,%ebp
11349 This matches the hookable function prologue in Win32 API
11350 functions in Microsoft Windows XP Service Pack 2 and newer.
11351 Wine uses this to enable Windows apps to hook the Win32 API
11352 functions provided by Wine.
11354 What that means is that we've already set up the frame pointer. */
11358 {
11361 /* We've decided to use the frame pointer already set up.
11362 Describe this to the unwinder by pretending that both
11363 push and mov insns happen right here.
11365 Putting the unwind info here at the end of the ms_hook
11366 is done so that we can make absolutely certain we get
11367 the required byte sequence at the start of the function,
11368 rather than relying on an assembler that can produce
11369 the exact encoding required.
11371 However it does mean (in the unpatched case) that we have
11372 a 1 insn window where the asynchronous unwind info is
11373 incorrect. However, if we placed the unwind info at
11374 its correct location we would have incorrect unwind info
11375 in the patched case. Which is probably all moot since
11376 I don't expect Wine generates dwarf2 unwind info for the
11377 system libraries that use this feature. */
11383 stack_pointer_rtx);
11391 /* Note that gen_push incremented m->fs.cfa_offset, even
11392 though we didn't emit the push insn here. */
11396 }
11397 else
11398 {
11399 /* The frame pointer is not needed so pop %ebp again.
11400 This leaves us with a pristine state. */
11402 }
11403 }
11405 /* The first insn of a function that accepts its static chain on the
11406 stack is to push the register that would be filled in by a direct
11407 call. This insn will be skipped by the trampoline. */
11409 {
11413 /* We don't want to interpret this push insn as a register save,
11414 only as a stack adjustment. The real copy of the register as
11415 a save will be done later, if needed. */
11420 }
11422 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11423 of DRAP is needed and stack realignment is really needed after reload */
11425 {
11428 /* Only need to push parameter pointer reg if it is caller saved. */
11430 {
11431 /* Push arg pointer reg */
11434 }
11436 /* Grab the argument pointer. */
11443 /* Align the stack. */
11445 stack_pointer_rtx,
11449 /* Replicate the return address on the stack so that return
11450 address can be reached via (argp - 1) slot. This is needed
11451 to implement macro RETURN_ADDR_RTX and intrinsic function
11452 expand_builtin_return_addr etc. */
11458 /* For the purposes of frame and register save area addressing,
11459 we've started over with a new frame. */
11462 }
11468 {
11469 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11470 slower on all targets. Also sdb doesn't like it. */
11474 /* Push registers now, before setting the frame pointer
11475 on SEH target. */
11477 && TARGET_SEH
11479 {
11483 }
11486 {
11494 }
11495 }
11498 {
11499 /* If saving registers via PUSH, do so now. */
11501 {
11505 }
11507 /* When using red zone we may start register saving before allocating
11508 the stack frame saving one cycle of the prologue. However, avoid
11509 doing this if we have to probe the stack; at least on x86_64 the
11510 stack probe can turn into a call that clobbers a red zone location. */
11512 && (! TARGET_STACK_PROBE
11514 {
11517 }
11518 }
11521 {
11525 /* The computation of the size of the re-aligned stack frame means
11526 that we must allocate the size of the register save area before
11527 performing the actual alignment. Otherwise we cannot guarantee
11528 that there's enough storage above the realignment point. */
11535 /* Align the stack. */
11537 stack_pointer_rtx,
11540 /* For the purposes of register save area addressing, the stack
11541 pointer is no longer valid. As for the value of sp_offset,
11542 see ix86_compute_frame_layout, which we need to match in order
11543 to pass verification of stack_pointer_offset at the end. */
11546 }
11551 {
11552 /* We start to count from ARG_POINTER. */
11555 /* If it was realigned, take into account the fake frame. */
11557 {
11564 /* This over-estimates by 1 minimal-stack-alignment-unit but
11565 mitigates that by counting in the new return address slot. */
11566 current_function_dynamic_stack_size
11568 }
11571 }
11573 /* On SEH target with very large frame size, allocate an area to save
11574 SSE registers (as the very large allocation won't be described). */
11578 {
11579 HOST_WIDE_INT sse_size =
11584 /* No need to do stack checking as the area will be immediately
11585 written. */
11592 }
11594 /* The stack has already been decremented by the instruction calling us
11595 so probe if the size is non-negative to preserve the protection area. */
11597 {
11598 /* We expect the registers to be saved when probes are used. */
11602 {
11605 {
11608 }
11609 }
11610 else
11611 {
11618 {
11620 {
11623 }
11624 else
11626 }
11627 else
11628 {
11630 {
11634 }
11635 else
11637 }
11638 }
11639 }
11642 ;
11645 {
11649 }
11650 else
11651 {
11663 {
11666 /* Note that SEH directives need to continue tracking the stack
11667 pointer even after the frame pointer has been set up. */
11669 {
11677 }
11678 }
11681 {
11686 {
11694 }
11695 }
11700 /* Use the fact that AX still contains ALLOCATE. */
11702 ? gen_pro_epilogue_adjust_stack_di_sub
11709 {
11717 }
11720 /* Use stack_pointer_rtx for relative addressing so that code
11721 works for realigned stack, too. */
11723 {
11730 }
11732 {
11737 }
11738 }
11741 /* If we havn't already set up the frame pointer, do so now. */
11743 {
11755 }
11762 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11763 in PROLOGUE. */
11765 {
11771 /* Deleting already emmitted SET_GOT if exist and allocated to
11772 REAL_PIC_OFFSET_TABLE_REGNUM. */
11774 }
11777 {
11778 /* vDRAP is setup but after reload it turns out stack realign
11779 isn't necessary, here we will emit prologue to setup DRAP
11780 without stack realign adjustment */
11783 }
11785 /* Prevent instructions from being scheduled into register save push
11786 sequence when access to the redzone area is done through frame pointer.
11787 The offset between the frame pointer and the stack pointer is calculated
11788 relative to the value of the stack pointer at the end of the function
11789 prologue, and moving instructions that access redzone area via frame
11790 pointer inside push sequence violates this assumption. */
11794 /* Emit cld instruction if stringops are used in the function. */
11798 /* SEH requires that the prologue end within 256 bytes of the start of
11799 the function. Prevent instruction schedules that would extend that.
11800 Further, prevent alloca modifications to the stack pointer from being
11801 combined with prologue modifications. */
11804 }
11806 /* Emit code to restore REG using a POP insn. */
11808 static void
11810 {
11819 {
11820 /* Previously we'd represented the CFA as an expression
11821 like *(%ebp - 8). We've just popped that value from
11822 the stack, which means we need to reset the CFA to
11823 the drap register. This will remain until we restore
11824 the stack pointer. */
11828 /* This means that the DRAP register is valid for addressing too. */
11831 }
11834 {
11841 }
11843 /* When the frame pointer is the CFA, and we pop it, we are
11844 swapping back to the stack pointer as the CFA. This happens
11845 for stack frames that don't allocate other data, so we assume
11846 the stack pointer is now pointing at the return address, i.e.
11847 the function entry state, which makes the offset be 1 word. */
11849 {
11852 {
11860 }
11861 }
11862 }
11864 /* Emit code to restore saved registers using POP insns. */
11866 static void
11868 {
11874 }
11876 /* Emit code and notes for the LEAVE instruction. */
11878 static void
11880 {
11892 {
11900 }
11903 }
11905 /* Emit code to restore saved registers using MOV insns.
11906 First register is restored from CFA - CFA_OFFSET. */
11907 static void
11910 {
11916 {
11918 rtx mem;
11926 {
11927 /* Previously we'd represented the CFA as an expression
11928 like *(%ebp - 8). We've just popped that value from
11929 the stack, which means we need to reset the CFA to
11930 the drap register. This will remain until we restore
11931 the stack pointer. */
11935 /* This means that the DRAP register is valid for addressing. */
11937 }
11938 else
11942 }
11943 }
11945 /* Emit code to restore saved registers using MOV insns.
11946 First register is restored from CFA - CFA_OFFSET. */
11947 static void
11950 {
11955 {
11957 rtx mem;
11967 }
11968 }
11970 /* Restore function stack, frame, and registers. */
11972 void
11974 {
11990 /* The FP must be valid if the frame pointer is present. */
11995 /* We must have *some* valid pointer to the stack frame. */
11998 /* The DRAP is never valid at this point. */
12001 /* See the comment about red zone and frame
12002 pointer usage in ix86_expand_prologue. */
12009 /* Determine the CFA offset of the end of the red-zone. */
12012 {
12013 /* The red-zone begins below the return address. */
12016 /* When the register save area is in the aligned portion of
12017 the stack, determine the maximum runtime displacement that
12018 matches up with the aligned frame. */
12022 }
12024 /* Special care must be taken for the normal return case of a function
12025 using eh_return: the eax and edx registers are marked as saved, but
12026 not restored along this path. Adjust the save location to match. */
12030 /* EH_RETURN requires the use of moves to function properly. */
12033 /* SEH requires the use of pops to identify the epilogue. */
12036 /* If we're only restoring one register and sp is not valid then
12037 using a move instruction to restore the register since it's
12038 less work than reloading sp and popping the register. */
12051 && TARGET_USE_LEAVE
12055 else
12059 {
12060 /* Ensure that the entire register save area is addressable via
12061 the stack pointer, if we will restore via sp. */
12066 {
12070 style,
12072 }
12073 }
12075 /* If there are any SSE registers to restore, then we have to do it
12076 via moves, since there's obviously no pop for SSE regs. */
12082 {
12083 rtx t;
12088 /* eh_return epilogues need %ecx added to the stack pointer. */
12090 {
12094 /* Stack align doesn't work with eh_return. */
12096 /* Neither does regparm nested functions. */
12100 {
12108 /* Note that we use SA as a temporary CFA, as the return
12109 address is at the proper place relative to it. We
12110 pretend this happens at the FP restore insn because
12111 prior to this insn the FP would be stored at the wrong
12112 offset relative to SA, and after this insn we have no
12113 other reasonable register to use for the CFA. We don't
12114 bother resetting the CFA to the SP for the duration of
12115 the return insn. */
12128 }
12129 else
12130 {
12138 {
12142 UNITS_PER_WORD));
12144 }
12145 }
12148 }
12149 }
12150 else
12151 {
12152 /* SEH requires that the function end with (1) a stack adjustment
12153 if necessary, (2) a sequence of pops, and (3) a return or
12154 jump instruction. Prevent insns from the function body from
12155 being scheduled into this sequence. */
12157 {
12158 /* Prevent a catch region from being adjacent to the standard
12159 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12160 several other flags that would be interesting to test are
12161 not yet set up. */
12164 else
12166 }
12168 /* First step is to deallocate the stack frame so that we can
12169 pop the registers. Also do it on SEH target for very large
12170 frame as the emitted instructions aren't allowed by the ABI in
12171 epilogues. */
12173 || (TARGET_SEH
12176 {
12181 }
12183 {
12187 style,
12189 }
12192 }
12194 /* If we used a stack pointer and haven't already got rid of it,
12195 then do so now. */
12197 {
12198 /* If the stack pointer is valid and pointing at the frame
12199 pointer store address, then we only need a pop. */
12202 /* Leave results in shorter dependency chains on CPUs that are
12203 able to grok it fast. */
12208 else
12209 {
12211 hard_frame_pointer_rtx,
12214 }
12215 }
12218 {
12246 }
12248 /* At this point the stack pointer must be valid, and we must have
12249 restored all of the registers. We may not have deallocated the
12250 entire stack frame. We've delayed this until now because it may
12251 be possible to merge the local stack deallocation with the
12252 deallocation forced by ix86_static_chain_on_stack. */
12257 {
12261 }
12262 else
12265 /* Sibcall epilogues don't want a return instruction. */
12267 {
12270 }
12273 {
12276 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12277 address, do explicit add, and jump indirectly to the caller. */
12280 {
12284 /* There is no "pascal" calling convention in any 64bit ABI. */
12301 }
12302 else
12304 }
12305 else
12308 /* Restore the state back to the state from the prologue,
12309 so that it's correct for the next epilogue. */
12311 }
12313 /* Reset from the function's potential modifications. */
12315 static void
12317 {
12321 #if TARGET_MACHO
12322 /* Mach-O doesn't support labels at the end of objects, so if
12323 it looks like we might want one, insert a NOP. */
12324 {
12330 {
12331 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12332 notes only, instead set their CODE_LABEL_NUMBER to -1,
12333 otherwise there would be code generation differences
12334 in between -g and -g0. */
12338 }
12348 }
12349 #endif
12351 }
12353 /* Return a scratch register to use in the split stack prologue. The
12354 split stack prologue is used for -fsplit-stack. It is the first
12355 instructions in the function, even before the regular prologue.
12356 The scratch register can be any caller-saved register which is not
12357 used for parameters or for the static chain. */
12359 static unsigned int
12361 {
12364 else
12365 {
12378 {
12380 {
12384 }
12386 }
12388 {
12392 }
12394 {
12397 else
12398 {
12400 {
12404 }
12406 }
12407 }
12408 else
12409 {
12410 /* FIXME: We could make this work by pushing a register
12411 around the addition and comparison. */
12414 }
12415 }
12416 }
12418 /* A SYMBOL_REF for the function which allocates new stackspace for
12419 -fsplit-stack. */
12423 /* A SYMBOL_REF for the more stack function when using the large
12424 model. */
12428 /* Handle -fsplit-stack. These are the first instructions in the
12429 function, even before the regular prologue. */
12431 void
12433 {
12435 HOST_WIDE_INT allocate;
12441 rtx fn;
12449 /* This is the label we will branch to if we have enough stack
12450 space. We expect the basic block reordering pass to reverse this
12451 branch if optimizing, so that we branch in the unlikely case. */
12454 /* We need to compare the stack pointer minus the frame size with
12455 the stack boundary in the TCB. The stack boundary always gives
12456 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12457 can compare directly. Otherwise we need to do an addition. */
12460 UNSPEC_STACK_CHECK);
12465 else
12466 {
12468 rtx offset;
12470 /* We need a scratch register to hold the stack pointer minus
12471 the required frame size. Since this is the very start of the
12472 function, the scratch register can be any caller-saved
12473 register which is not used for parameters. */
12480 {
12481 /* We don't use ix86_gen_add3 in this case because it will
12482 want to split to lea, but when not optimizing the insn
12483 will not be split after this point. */
12486 offset)));
12487 }
12488 else
12489 {
12492 stack_pointer_rtx));
12493 }
12495 }
12501 /* Mark the jump as very likely to be taken. */
12506 {
12509 }
12512 /* Get more stack space. We pass in the desired stack space and the
12513 size of the arguments to copy to the new stack. In 32-bit mode
12514 we push the parameters; __morestack will return on a new stack
12515 anyhow. In 64-bit mode we pass the parameters in r10 and
12516 r11. */
12521 {
12527 /* If this function uses a static chain, it will be in %r10.
12528 Preserve it across the call to __morestack. */
12530 {
12531 rtx rax;
12536 }
12540 {
12541 HOST_WIDE_INT argval;
12544 /* When using the large model we need to load the address
12545 into a register, and we've run out of registers. So we
12546 switch to a different calling convention, and we call a
12547 different function: __morestack_large. We pass the
12548 argument size in the upper 32 bits of r10 and pass the
12549 frame size in the lower 32 bits. */
12554 {
12555 split_stack_fn_large =
12558 }
12560 {
12562 rtx x;
12571 UNSPEC_GOT);
12577 }
12578 else
12585 }
12586 else
12587 {
12591 }
12594 }
12595 else
12596 {
12599 }
12605 /* In order to make call/return prediction work right, we now need
12606 to execute a return instruction. See
12607 libgcc/config/i386/morestack.S for the details on how this works.
12609 For flow purposes gcc must not see this as a return
12610 instruction--we need control flow to continue at the subsequent
12611 label. Therefore, we use an unspec. */
12615 /* If we are in 64-bit mode and this function uses a static chain,
12616 we saved %r10 in %rax before calling _morestack. */
12621 /* If this function calls va_start, we need to store a pointer to
12622 the arguments on the old stack, because they may not have been
12623 all copied to the new stack. At this point the old stack can be
12624 found at the frame pointer value used by __morestack, because
12625 __morestack has set that up before calling back to us. Here we
12626 store that pointer in a scratch register, and in
12627 ix86_expand_prologue we store the scratch register in a stack
12628 slot. */
12630 {
12632 rtx frame_reg;
12639 /* 64-bit:
12640 fp -> old fp value
12641 return address within this function
12642 return address of caller of this function
12643 stack arguments
12644 So we add three words to get to the stack arguments.
12646 32-bit:
12647 fp -> old fp value
12648 return address within this function
12649 first argument to __morestack
12650 second argument to __morestack
12651 return address of caller of this function
12652 stack arguments
12653 So we add five words to get to the stack arguments.
12654 */
12665 }
12670 /* If this function calls va_start, we now have to set the scratch
12671 register for the case where we do not call __morestack. In this
12672 case we need to set it based on the stack pointer. */
12674 {
12681 }
12682 }
12684 /* We may have to tell the dataflow pass that the split stack prologue
12685 is initializing a scratch register. */
12687 static void
12689 {
12691 {
12694 }
12695 }
12696 \f
12697 /* Extract the parts of an RTL expression that is a valid memory address
12698 for an instruction. Return 0 if the structure of the address is
12699 grossly off. Return -1 if the address contains ASHIFT, so it is not
12700 strictly valid, but still used for computing length of lea instruction. */
12702 int
12704 {
12709 rtx tmp;
12713 /* Allow zero-extended SImode addresses,
12714 they will be emitted with addr32 prefix. */
12716 {
12719 {
12723 }
12726 {
12733 }
12734 }
12736 /* Allow SImode subregs of DImode addresses,
12737 they will be emitted with addr32 prefix. */
12739 {
12742 {
12746 }
12747 }
12752 {
12755 else
12757 }
12759 {
12764 do
12765 {
12770 }
12777 {
12780 {
12805 /* FALLTHRU */
12809 && TARGET_TLS_DIRECT_SEG_REFS
12812 else
12819 /* FALLTHRU */
12826 else
12841 }
12842 }
12843 }
12845 {
12848 }
12850 {
12851 /* We're called for lea too, which implements ashift on occasion. */
12861 }
12862 else
12866 {
12868 ;
12871 ;
12872 else
12874 }
12876 /* Extract the integral value of scale. */
12878 {
12882 }
12887 /* Avoid useless 0 displacement. */
12891 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12896 {
12899 }
12901 /* Special case: %ebp cannot be encoded as a base without a displacement.
12902 Similarly %r13. */
12904 && base_reg
12913 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12914 Avoid this by transforming to [%esi+0].
12915 Reload calls address legitimization without cfun defined, so we need
12916 to test cfun for being non-NULL. */
12922 /* Special case: encode reg+reg instead of reg*2. */
12926 /* Special case: scaling cannot be encoded without base or displacement. */
12937 }
12938 \f
12939 /* Return cost of the memory address x.
12940 For i386, it is better to use a complex address than let gcc copy
12941 the address into a reg and make a new pseudo. But not if the address
12942 requires to two regs - that would mean more pseudos with longer
12943 lifetimes. */
12944 static int
12946 {
12958 /* Attempt to minimize number of registers in the address by increasing
12959 address cost for each used register. We don't increase address cost
12960 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
12961 is not invariant itself it most likely means that base or index is not
12962 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
12963 which is not profitable for x86. */
12967 || !pic_offset_table_rtx
12970 cost++;
12975 || !pic_offset_table_rtx
12978 cost++;
12980 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12981 since it's predecode logic can't detect the length of instructions
12982 and it degenerates to vector decoded. Increase cost of such
12983 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12984 to split such addresses or even refuse such addresses at all.
12986 Following addressing modes are affected:
12987 [base+scale*index]
12988 [scale*index+disp]
12989 [base+index]
12991 The first and last case may be avoidable by explicitly coding the zero in
12992 memory address, but I don't have AMD-K6 machine handy to check this
12993 theory. */
13002 }
13003 \f
13004 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13005 this is used for to form addresses to local data when -fPIC is in
13006 use. */
13008 static bool
13010 {
13013 }
13015 /* Determine if a given RTX is a valid constant. We already know this
13016 satisfies CONSTANT_P. */
13018 static bool
13020 {
13021 /* Pointer bounds constants are not valid. */
13026 {
13031 {
13035 }
13040 /* Only some unspecs are valid as "constants". */
13043 {
13059 }
13061 /* We must have drilled down to a symbol. */
13066 /* FALLTHRU */
13069 /* TLS symbols are never valid. */
13073 /* DLLIMPORT symbols are never valid. */
13078 #if TARGET_MACHO
13079 /* mdynamic-no-pic */
13082 #endif
13096 }
13098 /* Otherwise we handle everything else in the move patterns. */
13100 }
13102 /* Determine if it's legal to put X into the constant pool. This
13103 is not possible for the address of thread-local symbols, which
13104 is checked above. */
13106 static bool
13108 {
13109 /* We can always put integral constants and vectors in memory. */
13111 {
13120 }
13122 }
13124 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13125 otherwise zero. */
13127 static bool
13129 {
13135 }
13138 /* Nonzero if the constant value X is a legitimate general operand
13139 when generating PIC code. It is given that flag_pic is on and
13140 that X satisfies CONSTANT_P. */
13142 bool
13144 {
13145 rtx inner;
13148 {
13155 /* Only some unspecs are valid as "constants". */
13158 {
13171 }
13172 /* FALLTHRU */
13180 }
13181 }
13183 /* Determine if a given CONST RTX is a valid memory displacement
13184 in PIC mode. */
13186 bool
13188 {
13191 /* In 64bit mode we can allow direct addresses of symbols and labels
13192 when they are not dynamic symbols. */
13194 {
13198 {
13222 /* FALLTHRU */
13225 /* TLS references should always be enclosed in UNSPEC.
13226 The dllimported symbol needs always to be resolved. */
13232 {
13240 /* Function-symbols need to be resolved only for
13241 large-model.
13242 For the small-model we don't need to resolve anything
13243 here. */
13248 /* Non-external symbols don't need to be resolved for
13249 large, and medium-model. */
13254 }
13257 || (HAVE_LD_PIE_COPYRELOC
13258 && flag_pie
13267 }
13268 }
13274 {
13275 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13276 of GOT tables. We should not need these anyway. */
13288 }
13292 {
13297 }
13306 {
13310 /* We need to check for both symbols and labels because VxWorks loads
13311 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13312 details. */
13316 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13317 While ABI specify also 32bit relocation but we don't produce it in
13318 small PIC model at all. */
13340 }
13343 }
13345 /* Determine if op is suitable RTX for an address register.
13346 Return naked register if a register or a register subreg is
13347 found, otherwise return NULL_RTX. */
13349 static rtx
13351 {
13354 /* Only SImode or DImode registers can form the address. */
13361 {
13369 /* Don't allow SUBREGs that span more than a word. It can
13370 lead to spill failures when the register is one word out
13371 of a two word structure. */
13375 /* Allow only SUBREGs of non-eliminable hard registers. */
13378 }
13380 /* Op is not a register. */
13382 }
13384 /* Recognizes RTL expressions that are valid memory addresses for an
13385 instruction. The MODE argument is the machine mode for the MEM
13386 expression that wants to use this address.
13388 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13389 convert common non-canonical forms to canonical form so that they will
13390 be recognized. */
13392 static bool
13394 {
13397 HOST_WIDE_INT scale;
13401 /* Decomposition failed. */
13410 /* Validate base register. */
13412 {
13420 /* Base is not valid. */
13422 }
13424 /* Validate index register. */
13426 {
13434 /* Index is not valid. */
13436 }
13438 /* Index and base should have the same mode. */
13443 /* Address override works only on the (%reg) part of %fs:(%reg). */
13449 /* Validate scale factor. */
13451 {
13453 /* Scale without index. */
13457 /* Scale is not a valid multiplier. */
13459 }
13461 /* Validate displacement. */
13463 {
13468 {
13469 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13470 used. While ABI specify also 32bit relocations, we don't produce
13471 them at all and use IP relative instead. */
13478 /* 64bit address unspec. */
13498 /* Invalid address unspec. */
13500 }
13503 && (flag_pic
13504 || (TARGET_MACHO
13505 #if TARGET_MACHO
13506 && MACHOPIC_INDIRECT
13508 #endif
13509 )))
13510 {
13512 is_legitimate_pic:
13514 {
13515 /* foo@dtpoff(%rX) is ok. */
13522 /* Non-constant pic memory reference. */
13524 }
13527 /* Displacement is an invalid pic construct. */
13529 #if TARGET_MACHO
13532 /* displacment must be referenced via non_lazy_pointer */
13534 #endif
13536 /* This code used to verify that a symbolic pic displacement
13537 includes the pic_offset_table_rtx register.
13539 While this is good idea, unfortunately these constructs may
13540 be created by "adds using lea" optimization for incorrect
13541 code like:
13543 int a;
13544 int foo(int i)
13545 {
13546 return *(&a+i);
13547 }
13549 This code is nonsensical, but results in addressing
13550 GOT table with pic_offset_table_rtx base. We can't
13551 just refuse it easily, since it gets matched by
13552 "addsi3" pattern, that later gets split to lea in the
13553 case output register differs from input. While this
13554 can be handled by separate addsi pattern for this case
13555 that never results in lea, this seems to be easier and
13556 correct fix for crash to disable this test. */
13557 }
13564 /* Displacement is not constant. */
13568 /* Displacement is out of range. */
13570 /* In x32 mode, constant addresses are sign extended to 64bit, so
13571 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13576 }
13578 /* Everything looks valid. */
13580 }
13582 /* Determine if a given RTX is a valid constant address. */
13584 bool
13586 {
13588 }
13589 \f
13590 /* Return a unique alias set for the GOT. */
13592 static alias_set_type
13594 {
13599 }
13601 /* Return a legitimate reference for ORIG (an address) using the
13602 register REG. If REG is 0, a new pseudo is generated.
13604 There are two types of references that must be handled:
13606 1. Global data references must load the address from the GOT, via
13607 the PIC reg. An insn is emitted to do this load, and the reg is
13608 returned.
13610 2. Static data references, constant pool addresses, and code labels
13611 compute the address as an offset from the GOT, whose base is in
13612 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13613 differentiate them from global data objects. The returned
13614 address is the PIC reg + an unspec constant.
13616 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13617 reg also appears in the address. */
13619 static rtx
13621 {
13625 #if TARGET_MACHO
13627 {
13630 /* Use the generic Mach-O PIC machinery. */
13632 }
13633 #endif
13636 {
13640 }
13646 {
13647 rtx tmpreg;
13648 /* This symbol may be referenced via a displacement from the PIC
13649 base address (@GOTOFF). */
13654 {
13656 UNSPEC_GOTOFF);
13658 }
13659 else
13664 else
13669 {
13673 }
13674 else
13676 }
13678 {
13679 /* This symbol may be referenced via a displacement from the PIC
13680 base address (@GOTOFF). */
13685 {
13687 UNSPEC_GOTOFF);
13689 }
13690 else
13696 {
13699 }
13700 }
13702 /* We can't use @GOTOFF for text labels on VxWorks;
13703 see gotoff_operand. */
13705 {
13710 /* For x64 PE-COFF there is no GOT table. So we use address
13711 directly. */
13713 {
13721 }
13723 {
13731 /* Use directly gen_movsi, otherwise the address is loaded
13732 into register for CSE. We don't want to CSE this addresses,
13733 instead we CSE addresses from the GOT table, so skip this. */
13736 }
13737 else
13738 {
13739 /* This symbol must be referenced via a load from the
13740 Global Offset Table (@GOT). */
13754 }
13755 }
13756 else
13757 {
13760 {
13762 {
13765 }
13766 else
13768 }
13770 {
13773 /* We must match stuff we generate before. Assume the only
13774 unspecs that can get here are ours. Not that we could do
13775 anything with them anyway.... */
13781 }
13783 {
13786 /* Check first to see if this is a constant offset from a @GOTOFF
13787 symbol reference. */
13790 {
13792 {
13794 UNSPEC_GOTOFF);
13800 {
13803 }
13804 }
13805 else
13806 {
13809 {
13813 }
13814 }
13815 }
13816 else
13817 {
13820 new_rtx
13824 {
13827 {
13830 new_rtx
13832 }
13833 else
13835 }
13836 else
13837 {
13838 /* For %rip addressing, we have to use just disp32, not
13839 base nor index. */
13846 {
13849 }
13851 }
13852 }
13853 }
13854 }
13856 }
13857 \f
13858 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13860 static rtx
13862 {
13866 {
13871 }
13877 }
13879 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13883 static rtx
13885 {
13887 {
13893 }
13896 {
13898 UNSPEC_PLTOFF);
13901 }
13904 }
13906 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13910 rtx
13912 {
13914 {
13915 ix86_tls_module_base_symbol
13920 }
13923 }
13925 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13926 false if we expect this to be used for a memory address and true if
13927 we expect to load the address into a register. */
13929 static rtx
13931 {
13937 /* Fall back to global dynamic model if tool chain cannot support local
13938 dynamic. */
13945 {
13950 {
13953 else
13954 {
13957 }
13958 }
13961 {
13964 else
13974 }
13975 else
13976 {
13980 {
13985 emit_call_insn
13995 }
13996 else
13998 }
14005 {
14008 else
14009 {
14012 }
14013 }
14016 {
14021 else
14027 }
14028 else
14029 {
14033 {
14036 rtx eqv;
14039 emit_call_insn
14044 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14045 share the LD_BASE result with other LD model accesses. */
14047 UNSPEC_TLS_LD_BASE);
14051 }
14052 else
14054 }
14062 {
14069 }
14074 {
14076 {
14077 /* The Sun linker took the AMD64 TLS spec literally
14078 and can only handle %rax as destination of the
14079 initial executable code sequence. */
14084 }
14086 /* Generate DImode references to avoid %fs:(%reg32)
14087 problems and linker IE->LE relaxation bug. */
14091 }
14093 {
14096 }
14098 {
14102 }
14103 else
14104 {
14107 }
14117 {
14122 }
14123 else
14124 {
14128 }
14138 {
14142 }
14143 else
14144 {
14148 }
14153 }
14156 }
14158 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14159 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14160 unique refptr-DECL symbol corresponding to symbol DECL. */
14163 {
14167 {
14169 }
14171 static void
14173 {
14179 else
14181 }
14182 };
14186 static tree
14188 {
14194 tree to;
14195 rtx rtl;
14222 else
14235 {
14237 #ifdef SUB_TARGET_RECORD_STUB
14239 #endif
14240 }
14249 }
14251 /* Expand SYMBOL into its corresponding far-addresse symbol.
14252 WANT_REG is true if we require the result be a register. */
14254 static rtx
14256 {
14257 tree imp_decl;
14258 rtx x;
14267 }
14269 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14270 true if we require the result be a register. */
14272 static rtx
14274 {
14275 tree imp_decl;
14276 rtx x;
14285 }
14287 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14288 is true if we require the result be a register. */
14290 static rtx
14292 {
14297 {
14304 {
14307 }
14308 }
14324 {
14327 }
14329 }
14331 /* Try machine-dependent ways of modifying an illegitimate address
14332 to be legitimate. If we find one, return the new, valid address.
14333 This macro is used in only one place: `memory_address' in explow.c.
14335 OLDX is the address as it was before break_out_memory_refs was called.
14336 In some cases it is useful to look at this to decide what needs to be done.
14338 It is always safe for this macro to do nothing. It exists to recognize
14339 opportunities to optimize the output.
14341 For the 80386, we handle X+REG by loading X into a register R and
14342 using R+REG. R will go in a general reg and indexing will be used.
14343 However, if REG is a broken-out memory address or multiplication,
14344 nothing needs to be done because REG can certainly go in a general reg.
14346 When -fpic is used, special handling is needed for symbolic references.
14347 See comments by legitimize_pic_address in i386.c for details. */
14349 static rtx
14351 {
14362 {
14366 }
14369 {
14373 }
14378 #if TARGET_MACHO
14381 #endif
14383 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14387 {
14392 }
14395 {
14396 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14401 {
14407 }
14412 {
14418 }
14420 /* Put multiply first if it isn't already. */
14422 {
14425 }
14427 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14428 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14429 created by virtual register instantiation, register elimination, and
14430 similar optimizations. */
14432 {
14438 }
14440 /* Canonicalize
14441 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14442 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14447 {
14448 rtx constant;
14452 {
14455 }
14457 {
14460 }
14461 else
14465 {
14472 }
14473 }
14479 {
14482 }
14485 {
14488 }
14496 {
14499 }
14505 {
14509 {
14512 }
14516 }
14519 {
14523 {
14526 }
14530 }
14531 }
14534 }
14535 \f
14536 /* Print an integer constant expression in assembler syntax. Addition
14537 and subtraction are the only arithmetic that may appear in these
14538 expressions. FILE is the stdio stream to write to, X is the rtx, and
14539 CODE is the operand print code from the output string. */
14541 static void
14543 {
14547 {
14556 else
14557 {
14560 /* Mark the decl as referenced so that cgraph will
14561 output the function. */
14565 #if TARGET_MACHO
14569 #endif
14571 }
14579 /* FALLTHRU */
14590 /* This used to output parentheses around the expression,
14591 but that does not work on the 386 (either ATT or BSD assembler). */
14596 /* We can't handle floating point constants;
14597 TARGET_PRINT_OPERAND must handle them. */
14602 /* Some assemblers need integer constants to appear first. */
14604 {
14608 }
14609 else
14610 {
14615 }
14630 {
14634 }
14639 {
14658 /* FIXME: This might be @TPOFF in Sun ld too. */
14667 else
14677 else
14683 #if TARGET_MACHO
14688 #endif
14692 }
14697 }
14698 }
14700 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14701 We need to emit DTP-relative relocations. */
14703 static void ATTRIBUTE_UNUSED
14705 {
14710 {
14718 }
14719 }
14721 /* Return true if X is a representation of the PIC register. This copes
14722 with calls from ix86_find_base_term, where the register might have
14723 been replaced by a cselib value. */
14725 static bool
14727 {
14734 {
14742 }
14743 else
14745 }
14747 /* Helper function for ix86_delegitimize_address.
14748 Attempt to delegitimize TLS local-exec accesses. */
14750 static rtx
14752 {
14777 {
14782 }
14788 }
14790 /* In the name of slightly smaller debug output, and to cater to
14791 general assembler lossage, recognize PIC+GOTOFF and turn it back
14792 into a direct symbol reference.
14794 On Darwin, this is necessary to avoid a crash, because Darwin
14795 has a different PIC label for each routine but the DWARF debugging
14796 information is not associated with any particular routine, so it's
14797 necessary to remove references to the PIC label from RTL stored by
14798 the DWARF output code. */
14800 static rtx
14802 {
14804 /* addend is NULL or some rtx if x is something+GOTOFF where
14805 something doesn't include the PIC register. */
14807 /* reg_addend is NULL or a multiple of some register. */
14809 /* const_addend is NULL or a const_int. */
14811 /* This is the result, or NULL. */
14820 {
14827 {
14833 }
14840 {
14843 {
14848 }
14850 }
14855 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14856 and -mcmodel=medium -fpic. */
14857 }
14864 /* %ebx + GOT/GOTOFF */
14865 ;
14867 {
14868 /* %ebx + %reg * scale + GOT/GOTOFF */
14874 else
14875 {
14878 }
14879 }
14880 else
14886 {
14889 }
14910 {
14911 /* If the rest of original X doesn't involve the PIC register, add
14912 addend and subtract pic_offset_table_rtx. This can happen e.g.
14913 for code like:
14914 leal (%ebx, %ecx, 4), %ecx
14915 ...
14916 movl foo@GOTOFF(%ecx), %edx
14917 in which case we return (%ecx - %ebx) + foo
14918 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14919 and reload has completed. */
14923 pic_offset_table_rtx),
14924 result);
14926 {
14930 }
14931 else
14933 }
14935 {
14939 }
14941 }
14943 /* If X is a machine specific address (i.e. a symbol or label being
14944 referenced as a displacement from the GOT implemented using an
14945 UNSPEC), then return the base term. Otherwise return X. */
14947 rtx
14949 {
14950 rtx term;
14953 {
14966 }
14969 }
14970 \f
14971 static void
14974 {
14978 {
14981 }
14986 {
14989 {
15008 }
15012 {
15031 }
15038 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15039 Those same assemblers have the same but opposite lossage on cmov. */
15042 else
15047 {
15060 }
15067 else
15072 {
15085 }
15092 else
15102 else
15113 }
15115 }
15117 /* Print the name of register X to FILE based on its machine mode and number.
15118 If CODE is 'w', pretend the mode is HImode.
15119 If CODE is 'b', pretend the mode is QImode.
15120 If CODE is 'k', pretend the mode is SImode.
15121 If CODE is 'q', pretend the mode is DImode.
15122 If CODE is 'x', pretend the mode is V4SFmode.
15123 If CODE is 't', pretend the mode is V8SFmode.
15124 If CODE is 'g', pretend the mode is V16SFmode.
15125 If CODE is 'h', pretend the reg is the 'high' byte register.
15126 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15127 If CODE is 'd', duplicate the operand for AVX instruction.
15128 */
15130 void
15132 {
15142 {
15146 }
15149 {
15152 }
15170 else
15184 {
15192 normal:
15208 {
15213 }
15217 }
15221 /* Irritatingly, AMD extended registers use
15222 different naming convention: "r%d[bwd]" */
15224 {
15227 {
15241 /* no suffix */
15246 }
15248 }
15251 {
15254 else
15256 }
15257 }
15259 /* Meaning of CODE:
15260 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15261 C -- print opcode suffix for set/cmov insn.
15262 c -- like C, but print reversed condition
15263 F,f -- likewise, but for floating-point.
15264 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15265 otherwise nothing
15266 R -- print embeded rounding and sae.
15267 r -- print only sae.
15268 z -- print the opcode suffix for the size of the current operand.
15269 Z -- likewise, with special suffixes for x87 instructions.
15270 * -- print a star (in certain assembler syntax)
15271 A -- print an absolute memory reference.
15272 E -- print address with DImode register names if TARGET_64BIT.
15273 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15274 s -- print a shift double count, followed by the assemblers argument
15275 delimiter.
15276 b -- print the QImode name of the register for the indicated operand.
15277 %b0 would print %al if operands[0] is reg 0.
15278 w -- likewise, print the HImode name of the register.
15279 k -- likewise, print the SImode name of the register.
15280 q -- likewise, print the DImode name of the register.
15281 x -- likewise, print the V4SFmode name of the register.
15282 t -- likewise, print the V8SFmode name of the register.
15283 g -- likewise, print the V16SFmode name of the register.
15284 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15285 y -- print "st(0)" instead of "st" as a register.
15286 d -- print duplicated register operand for AVX instruction.
15287 D -- print condition for SSE cmp instruction.
15288 P -- if PIC, print an @PLT suffix.
15289 p -- print raw symbol name.
15290 X -- don't print any sort of PIC '@' suffix for a symbol.
15291 & -- print some in-use local-dynamic symbol name.
15292 H -- print a memory address offset by 8; used for sse high-parts
15293 Y -- print condition for XOP pcom* instruction.
15294 + -- print a branch hint as 'cs' or 'ds' prefix
15295 ; -- print a semicolon (after prefixes due to bug in older gas).
15296 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15297 @ -- print a segment register of thread base pointer load
15298 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15299 ! -- print MPX prefix for jxx/call/ret instructions if required.
15300 */
15302 void
15304 {
15306 {
15308 {
15311 {
15317 /* Intel syntax. For absolute addresses, registers should not
15318 be surrounded by braces. */
15320 {
15325 }
15330 }
15336 /* Wrap address in an UNSPEC to declare special handling. */
15374 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15379 {
15393 output_operand_lossage
15396 }
15399 #endif
15404 {
15405 /* Opcodes don't get size suffixes if using Intel opcodes. */
15410 {
15428 output_operand_lossage
15431 }
15432 }
15435 warning
15437 /* FALLTHRU */
15440 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15445 {
15447 {
15449 #ifdef HAVE_AS_IX86_FILDS
15451 #endif
15459 #ifdef HAVE_AS_IX86_FILDQ
15461 #else
15463 #endif
15468 }
15469 }
15471 {
15472 /* 387 opcodes don't get size suffixes
15473 if the operands are registers. */
15478 {
15494 }
15495 }
15496 else
15497 {
15498 output_operand_lossage
15501 }
15503 output_operand_lossage
15524 {
15527 }
15532 {
15583 }
15587 /* Little bit of braindamage here. The SSE compare instructions
15588 does use completely different names for the comparisons that the
15589 fp conditional moves. */
15591 {
15594 {
15597 }
15603 {
15606 }
15612 {
15615 }
15624 {
15627 }
15633 {
15636 }
15642 {
15645 }
15656 }
15661 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15664 #endif
15669 {
15673 }
15677 file);
15682 {
15686 }
15687 /* It doesn't actually matter what mode we use here, as we're
15688 only going to use this for printing. */
15690 /* Output 'qword ptr' for intel assembler dialect. */
15699 #ifdef HAVE_AS_IX86_HLE
15701 #else
15703 #endif
15705 #ifdef HAVE_AS_IX86_HLE
15707 #else
15709 #endif
15710 /* We do not want to print value of the operand. */
15739 {
15754 }
15767 {
15772 else
15775 }
15778 {
15779 rtx x;
15788 {
15793 {
15795 bool cputaken
15798 /* Emit hints only in the case default branch prediction
15799 heuristics would fail. */
15801 {
15802 /* We use 3e (DS) prefix for taken branches and
15803 2e (CS) prefix for not taken branches. */
15806 else
15808 }
15809 }
15810 }
15812 }
15815 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15817 #endif
15824 /* The kernel uses a different segment register for performance
15825 reasons; a system call would not have to trash the userspace
15826 segment register, which would be expensive. */
15829 else
15849 }
15850 }
15856 {
15857 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15860 {
15863 {
15872 else
15879 }
15881 /* Check for explicit size override (codes 'b', 'w', 'k',
15882 'q' and 'x') */
15896 }
15899 /* Avoid (%rip) for call operands. */
15905 else
15907 }
15910 {
15911 REAL_VALUE_TYPE r;
15919 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15923 else
15925 }
15928 {
15929 REAL_VALUE_TYPE r;
15938 }
15940 /* These float cases don't actually occur as immediate operands. */
15942 {
15947 }
15949 else
15950 {
15951 /* We have patterns that allow zero sets of memory, for instance.
15952 In 64-bit mode, we should probably support all 8-byte vectors,
15953 since we can in fact encode that into an immediate. */
15955 {
15958 }
15961 {
15963 {
15966 }
15969 {
15972 else
15974 }
15975 }
15980 else
15982 }
15983 }
15985 static bool
15987 {
15990 }
15991 \f
15992 /* Print a memory operand whose address is ADDR. */
15994 static void
15996 {
16005 {
16012 }
16014 {
16018 }
16020 {
16024 {
16027 }
16030 }
16032 {
16037 }
16038 else
16049 {
16060 }
16062 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16064 {
16076 }
16078 {
16079 /* Displacement only requires special attention. */
16082 {
16086 }
16089 else
16091 }
16092 else
16093 {
16094 /* Print SImode register names to force addr32 prefix. */
16096 {
16097 #ifdef ENABLE_CHECKING
16100 {
16111 }
16112 #endif
16115 }
16117 && TARGET_X32
16118 && disp
16121 {
16122 /* X32 runs in 64-bit mode, where displacement, DISP, in
16123 address DISP(%r64), is encoded as 32-bit immediate sign-
16124 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16125 address is %r64 + 0xffffffffbffffd00. When %r64 <
16126 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16127 which is invalid for x32. The correct address is %r64
16128 - 0x40000300 == 0xf7ffdd64. To properly encode
16129 -0x40000300(%r64) for x32, we zero-extend negative
16130 displacement by forcing addr32 prefix which truncates
16131 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16132 zero-extend all negative displacements, including -1(%rsp).
16133 However, for small negative displacements, sign-extension
16134 won't cause overflow. We only zero-extend negative
16135 displacements if they < -16*1024*1024, which is also used
16136 to check legitimate address displacements for PIC. */
16138 }
16141 {
16143 {
16148 else
16150 }
16156 {
16161 }
16163 }
16164 else
16165 {
16169 {
16170 /* Pull out the offset of a symbol; print any symbol itself. */
16174 {
16178 }
16186 else
16188 }
16192 {
16195 {
16199 }
16200 }
16203 else
16207 {
16212 }
16214 }
16215 }
16216 }
16218 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16220 static bool
16222 {
16223 rtx op;
16230 {
16233 /* FIXME: This might be @TPOFF in Sun ld. */
16244 else
16256 else
16263 #if TARGET_MACHO
16269 #endif
16272 {
16277 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16279 #else
16281 #endif
16284 }
16289 }
16292 }
16293 \f
16294 /* Split one or more double-mode RTL references into pairs of half-mode
16295 references. The RTL can be REG, offsettable MEM, integer constant, or
16296 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16297 split and "num" is its length. lo_half and hi_half are output arrays
16298 that parallel "operands". */
16300 void
16303 {
16304 machine_mode half_mode;
16308 {
16317 }
16322 {
16325 /* simplify_subreg refuse to split volatile memory addresses,
16326 but we still have to handle it. */
16328 {
16331 }
16332 else
16333 {
16340 }
16341 }
16342 }
16343 \f
16344 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16345 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16346 is the expression of the binary operation. The output may either be
16347 emitted here, or returned to the caller, like all output_* functions.
16349 There is no guarantee that the operands are the same mode, as they
16350 might be within FLOAT or FLOAT_EXTEND expressions. */
16352 #ifndef SYSV386_COMPAT
16353 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16354 wants to fix the assemblers because that causes incompatibility
16355 with gcc. No-one wants to fix gcc because that causes
16356 incompatibility with assemblers... You can use the option of
16357 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16358 #define SYSV386_COMPAT 1
16359 #endif
16363 {
16369 #ifdef ENABLE_CHECKING
16370 /* Even if we do not want to check the inputs, this documents input
16371 constraints. Which helps in understanding the following code. */
16381 else
16383 #endif
16386 {
16391 else
16400 else
16409 else
16418 else
16425 }
16428 {
16430 {
16434 else
16436 }
16437 else
16438 {
16442 else
16444 }
16446 }
16450 {
16456 /* know operands[0] == operands[1]. */
16459 {
16462 }
16465 {
16467 /* How is it that we are storing to a dead operand[2]?
16468 Well, presumably operands[1] is dead too. We can't
16469 store the result to st(0) as st(0) gets popped on this
16470 instruction. Instead store to operands[2] (which I
16471 think has to be st(1)). st(1) will be popped later.
16472 gcc <= 2.8.1 didn't have this check and generated
16473 assembly code that the Unixware assembler rejected. */
16475 else
16478 }
16482 else
16489 {
16492 }
16495 {
16498 }
16501 {
16502 #if SYSV386_COMPAT
16503 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16504 derived assemblers, confusingly reverse the direction of
16505 the operation for fsub{r} and fdiv{r} when the
16506 destination register is not st(0). The Intel assembler
16507 doesn't have this brain damage. Read !SYSV386_COMPAT to
16508 figure out what the hardware really does. */
16511 else
16513 #else
16515 /* As above for fmul/fadd, we can't store to st(0). */
16517 else
16519 #endif
16521 }
16524 {
16525 #if SYSV386_COMPAT
16528 else
16530 #else
16533 else
16535 #endif
16537 }
16540 {
16543 else
16546 }
16548 {
16549 #if SYSV386_COMPAT
16551 #else
16553 #endif
16554 }
16555 else
16556 {
16557 #if SYSV386_COMPAT
16559 #else
16561 #endif
16562 }
16567 }
16571 }
16573 /* Check if a 256bit AVX register is referenced inside of EXP. */
16575 static bool
16577 {
16583 }
16585 /* Return needed mode for entity in optimize_mode_switching pass. */
16587 static int
16589 {
16591 {
16592 rtx link;
16594 /* Needed mode is set to AVX_U128_CLEAN if there are
16595 no 256bit modes used in function arguments. */
16597 link;
16599 {
16601 {
16606 }
16607 }
16610 }
16612 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16613 changes state only when a 256bit register is written to, but we need
16614 to prevent the compiler from moving optimal insertion point above
16615 eventual read from 256bit register. */
16622 }
16624 /* Return mode that i387 must be switched into
16625 prior to the execution of insn. */
16627 static int
16629 {
16632 /* The mode UNINITIALIZED is used to store control word after a
16633 function call or ASM pattern. The mode ANY specify that function
16634 has no requirements on the control word and make no changes in the
16635 bits we are interested in. */
16649 {
16672 }
16675 }
16677 /* Return mode that entity must be switched into
16678 prior to the execution of insn. */
16680 static int
16682 {
16684 {
16694 }
16696 }
16698 /* Check if a 256bit AVX register is referenced in stores. */
16700 static void
16702 {
16704 {
16707 }
16708 }
16710 /* Calculate mode of upper 128bit AVX registers after the insn. */
16712 static int
16714 {
16721 /* We know that state is clean after CALL insn if there are no
16722 256bit registers used in the function return register. */
16724 {
16729 }
16731 /* Otherwise, return current mode. Remember that if insn
16732 references AVX 256bit registers, the mode was already changed
16733 to DIRTY from MODE_NEEDED. */
16735 }
16737 /* Return the mode that an insn results in. */
16739 static int
16741 {
16743 {
16753 }
16754 }
16756 static int
16758 {
16759 tree arg;
16761 /* Entry mode is set to AVX_U128_DIRTY if there are
16762 256bit modes used in function arguments. */
16765 {
16770 }
16773 }
16775 /* Return a mode that ENTITY is assumed to be
16776 switched to at function entry. */
16778 static int
16780 {
16782 {
16792 }
16793 }
16795 static int
16797 {
16800 /* Exit mode is set to AVX_U128_DIRTY if there are
16801 256bit modes used in the function return register. */
16806 }
16808 /* Return a mode that ENTITY is assumed to be
16809 switched to at function exit. */
16811 static int
16813 {
16815 {
16825 }
16826 }
16828 static int
16830 {
16832 }
16834 /* Output code to initialize control word copies used by trunc?f?i and
16835 rounding patterns. CURRENT_MODE is set to current control word,
16836 while NEW_MODE is set to new control word. */
16838 static void
16840 {
16842 rtx new_mode;
16853 {
16855 {
16857 /* round toward zero (truncate) */
16863 /* round down toward -oo */
16870 /* round up toward +oo */
16877 /* mask precision exception for nearbyint() */
16884 }
16885 }
16886 else
16887 {
16889 {
16891 /* round toward zero (truncate) */
16897 /* round down toward -oo */
16903 /* round up toward +oo */
16909 /* mask precision exception for nearbyint() */
16916 }
16917 }
16923 }
16925 /* Emit vzeroupper. */
16927 void
16929 {
16932 /* Cancel automatic vzeroupper insertion if there are
16933 live call-saved SSE registers at the insertion point. */
16945 }
16947 /* Generate one or more insns to set ENTITY to MODE. */
16949 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16950 is the set of hard registers live at the point where the insn(s)
16951 are to be inserted. */
16953 static void
16955 HARD_REG_SET regs_live)
16956 {
16958 {
16973 }
16974 }
16976 /* Output code for INSN to convert a float to a signed int. OPERANDS
16977 are the insn operands. The output may be [HSD]Imode and the input
16978 operand may be [SDX]Fmode. */
16982 {
16987 /* Jump through a hoop or two for DImode, since the hardware has no
16988 non-popping instruction. We used to do this a different way, but
16989 that was somewhat fragile and broke with post-reload splitters. */
16999 else
17000 {
17005 else
17009 }
17012 }
17014 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17015 have the values zero or one, indicates the ffreep insn's operand
17016 from the OPERANDS array. */
17020 {
17022 #ifdef HAVE_AS_IX86_FFREEP
17024 #else
17025 {
17035 }
17036 #endif
17039 }
17042 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17043 should be used. UNORDERED_P is true when fucom should be used. */
17047 {
17053 {
17056 }
17057 else
17058 {
17061 }
17064 {
17068 else
17070 else
17073 else
17075 }
17082 {
17084 {
17087 }
17088 else
17090 }
17093 && stack_top_dies
17096 {
17097 /* If both the top of the 387 stack dies, and the other operand
17098 is also a stack register that dies, then this must be a
17099 `fcompp' float compare */
17102 {
17103 /* There is no double popping fcomi variant. Fortunately,
17104 eflags is immune from the fstp's cc clobbering. */
17107 else
17110 }
17111 else
17112 {
17115 else
17117 }
17118 }
17119 else
17120 {
17121 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17124 {
17132 NULL,
17133 NULL,
17140 NULL,
17141 NULL,
17142 NULL,
17143 NULL
17144 };
17159 }
17160 }
17162 void
17164 {
17167 #ifdef ASM_QUAD
17170 #else
17172 #endif
17175 }
17177 void
17179 {
17182 #ifdef ASM_QUAD
17185 #else
17187 #endif
17188 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17194 #if TARGET_MACHO
17196 {
17200 }
17201 #endif
17202 else
17205 }
17206 \f
17207 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17208 for the target. */
17210 void
17212 {
17213 rtx tmp;
17215 /* We play register width games, which are only valid after reload. */
17218 /* Avoid HImode and its attendant prefix byte. */
17224 {
17227 }
17230 }
17232 /* X is an unchanging MEM. If it is a constant pool reference, return
17233 the constant pool rtx, else NULL. */
17235 rtx
17237 {
17244 }
17246 void
17248 {
17256 {
17257 rtx tmp;
17261 {
17267 }
17270 }
17274 {
17277 rtx tmp;
17282 else
17286 {
17293 }
17294 }
17298 {
17300 {
17301 #if TARGET_MACHO
17302 /* dynamic-no-pic */
17304 {
17311 }
17313 {
17317 }
17320 else
17321 {
17329 }
17330 /* dynamic-no-pic */
17331 #endif
17332 }
17333 else
17334 {
17338 {
17344 }
17345 }
17346 }
17347 else
17348 {
17359 /* Force large constants in 64bit compilation into register
17360 to get them CSEed. */
17371 {
17372 /* If we are loading a floating point constant to a register,
17373 force the value to memory now, since we'll get better code
17374 out the back end. */
17378 {
17383 }
17384 }
17385 }
17388 }
17390 void
17392 {
17399 /* Force constants other than zero into memory. We do not know how
17400 the instructions used to build constants modify the upper 64 bits
17401 of the register, once we have that information we may be able
17402 to handle some of them more efficiently. */
17411 /* We need to check memory alignment for SSE mode since attribute
17412 can make operands unaligned. */
17417 {
17420 /* ix86_expand_vector_move_misalign() does not like constants ... */
17426 /* ... nor both arguments in memory. */
17434 }
17436 /* Make operand1 a register if it isn't already. */
17440 {
17443 }
17446 }
17448 /* Split 32-byte AVX unaligned load and store if needed. */
17450 static void
17452 {
17453 rtx m;
17457 machine_mode mode;
17460 {
17481 }
17484 {
17487 {
17494 }
17495 /* Normal *mov<mode>_internal pattern will handle
17496 unaligned loads just fine if misaligned_operand
17497 is true, and without the UNSPEC it can be combined
17498 with arithmetic instructions. */
17501 else
17503 }
17505 {
17508 {
17513 }
17514 else
17516 }
17517 else
17519 }
17521 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17522 straight to ix86_expand_vector_move. */
17523 /* Code generation for scalar reg-reg moves of single and double precision data:
17524 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17525 movaps reg, reg
17526 else
17527 movss reg, reg
17528 if (x86_sse_partial_reg_dependency == true)
17529 movapd reg, reg
17530 else
17531 movsd reg, reg
17533 Code generation for scalar loads of double precision data:
17534 if (x86_sse_split_regs == true)
17535 movlpd mem, reg (gas syntax)
17536 else
17537 movsd mem, reg
17539 Code generation for unaligned packed loads of single precision data
17540 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17541 if (x86_sse_unaligned_move_optimal)
17542 movups mem, reg
17544 if (x86_sse_partial_reg_dependency == true)
17545 {
17546 xorps reg, reg
17547 movlps mem, reg
17548 movhps mem+8, reg
17549 }
17550 else
17551 {
17552 movlps mem, reg
17553 movhps mem+8, reg
17554 }
17556 Code generation for unaligned packed loads of double precision data
17557 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17558 if (x86_sse_unaligned_move_optimal)
17559 movupd mem, reg
17561 if (x86_sse_split_regs == true)
17562 {
17563 movlpd mem, reg
17564 movhpd mem+8, reg
17565 }
17566 else
17567 {
17568 movsd mem, reg
17569 movhpd mem+8, reg
17570 }
17571 */
17573 void
17575 {
17584 {
17586 {
17590 {
17592 {
17595 }
17596 else
17598 }
17600 /* FALLTHRU */
17604 {
17619 }
17625 else
17633 }
17636 }
17640 {
17642 {
17646 {
17648 {
17651 }
17652 else
17654 }
17656 /* FALLTHRU */
17666 }
17669 }
17672 {
17673 /* Normal *mov<mode>_internal pattern will handle
17674 unaligned loads just fine if misaligned_operand
17675 is true, and without the UNSPEC it can be combined
17676 with arithmetic instructions. */
17682 /* ??? If we have typed data, then it would appear that using
17683 movdqu is the only way to get unaligned data loaded with
17684 integer type. */
17686 {
17688 {
17691 }
17693 /* We will eventually emit movups based on insn attributes. */
17697 }
17699 {
17700 rtx zero;
17703 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17704 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17706 {
17707 /* We will eventually emit movups based on insn attributes. */
17710 }
17712 /* When SSE registers are split into halves, we can avoid
17713 writing to the top half twice. */
17715 {
17718 }
17719 else
17720 {
17721 /* ??? Not sure about the best option for the Intel chips.
17722 The following would seem to satisfy; the register is
17723 entirely cleared, breaking the dependency chain. We
17724 then store to the upper half, with a dependency depth
17725 of one. A rumor has it that Intel recommends two movsd
17726 followed by an unpacklpd, but this is unconfirmed. And
17727 given that the dependency depth of the unpacklpd would
17728 still be one, I'm not sure why this would be better. */
17730 }
17736 }
17737 else
17738 {
17739 rtx t;
17742 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17743 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17745 {
17747 {
17750 }
17757 }
17761 else
17766 else
17775 }
17776 }
17778 {
17780 {
17783 /* We will eventually emit movups based on insn attributes. */
17785 }
17787 {
17789 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17790 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17792 /* We will eventually emit movups based on insn attributes. */
17794 else
17795 {
17800 }
17801 }
17802 else
17803 {
17808 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17809 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17811 {
17814 }
17815 else
17816 {
17821 }
17822 }
17823 }
17824 else
17826 }
17828 /* Helper function of ix86_fixup_binary_operands to canonicalize
17829 operand order. Returns true if the operands should be swapped. */
17831 static bool
17833 rtx operands[])
17834 {
17839 /* If the operation is not commutative, we can't do anything. */
17843 /* Highest priority is that src1 should match dst. */
17849 /* Next highest priority is that immediate constants come second. */
17855 /* Lowest priority is that memory references should come second. */
17862 }
17865 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17866 destination to use for the operation. If different from the true
17867 destination in operands[0], a copy operation will be required. */
17869 rtx
17871 rtx operands[])
17872 {
17877 /* Canonicalize operand order. */
17879 {
17880 /* It is invalid to swap operands of different modes. */
17884 }
17886 /* Both source operands cannot be in memory. */
17888 {
17889 /* Optimization: Only read from memory once. */
17891 {
17894 }
17897 else
17899 }
17901 /* If the destination is memory, and we do not have matching source
17902 operands, do things in registers. */
17906 /* Source 1 cannot be a constant. */
17910 /* Source 1 cannot be a non-matching memory. */
17914 /* Improve address combine. */
17923 }
17925 /* Similarly, but assume that the destination has already been
17926 set up properly. */
17928 void
17931 {
17934 }
17936 /* Attempt to expand a binary operator. Make the expansion closer to the
17937 actual machine, then just general_operand, which will allow 3 separate
17938 memory references (one output, two input) in a single insn. */
17940 void
17942 rtx operands[])
17943 {
17950 /* Emit the instruction. */
17957 {
17958 /* This is going to be an LEA; avoid splitting it later. */
17960 }
17961 else
17962 {
17965 }
17967 /* Fix up the destination if needed. */
17970 }
17972 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17973 the given OPERANDS. */
17975 void
17977 rtx operands[])
17978 {
17981 {
17984 }
17986 {
17989 }
17990 /* Optimize (__m128i) d | (__m128i) e and similar code
17991 when d and e are float vectors into float vector logical
17992 insn. In C/C++ without using intrinsics there is no other way
17993 to express vector logical operation on float vectors than
17994 to cast them temporarily to integer vectors. */
17996 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18005 {
18006 rtx dst;
18008 {
18017 {
18020 }
18021 else
18022 {
18027 }
18038 }
18039 }
18048 }
18050 /* Return TRUE or FALSE depending on whether the binary operator meets the
18051 appropriate constraints. */
18053 bool
18056 {
18061 /* Both source operands cannot be in memory. */
18065 /* Canonicalize operand order for commutative operators. */
18069 /* If the destination is memory, we must have a matching source operand. */
18073 /* Source 1 cannot be a constant. */
18077 /* Source 1 cannot be a non-matching memory. */
18079 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18087 }
18089 /* Attempt to expand a unary operator. Make the expansion closer to the
18090 actual machine, then just general_operand, which will allow 2 separate
18091 memory references (one output, one input) in a single insn. */
18093 void
18095 rtx operands[])
18096 {
18103 /* If the destination is memory, and we do not have matching source
18104 operands, do things in registers. */
18106 {
18109 else
18111 }
18113 /* When source operand is memory, destination must match. */
18117 /* Emit the instruction. */
18123 else
18124 {
18127 }
18129 /* Fix up the destination if needed. */
18132 }
18134 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18135 divisor are within the range [0-255]. */
18137 void
18140 {
18149 {
18162 }
18169 /* Use 8bit unsigned divimod if dividend and divisor are within
18170 the range [0-255]. */
18179 pc_rtx);
18184 /* Generate original signed/unsigned divimod. */
18189 /* Branch to the end. */
18193 /* Generate 8bit unsigned divide. */
18195 /* Don't use operands[0] for result of 8bit divide since not all
18196 registers support QImode ZERO_EXTRACT. */
18203 {
18206 }
18207 else
18208 {
18211 }
18213 /* Extract remainder from AH. */
18217 else
18218 {
18219 /* Need a new scratch register since the old one has result
18220 of 8bit divide. */
18224 }
18227 /* Zero extend quotient from AL. */
18233 }
18235 #define LEA_MAX_STALL (3)
18236 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18238 /* Increase given DISTANCE in half-cycles according to
18239 dependencies between PREV and NEXT instructions.
18240 Add 1 half-cycle if there is no dependency and
18241 go to next cycle if there is some dependecy. */
18243 static unsigned int
18245 {
18261 }
18263 /* Function checks if instruction INSN defines register number
18264 REGNO1 or REGNO2. */
18266 static bool
18269 {
18270 df_ref def;
18280 }
18282 /* Function checks if instruction INSN uses register number
18283 REGNO as a part of address expression. */
18285 static bool
18287 {
18288 df_ref use;
18295 }
18297 /* Search backward for non-agu definition of register number REGNO1
18298 or register number REGNO2 in basic block starting from instruction
18299 START up to head of basic block or instruction INSN.
18301 Function puts true value into *FOUND var if definition was found
18302 and false otherwise.
18304 Distance in half-cycles between START and found instruction or head
18305 of BB is added to DISTANCE and returned. */
18307 static int
18311 {
18321 {
18323 {
18326 {
18329 {
18332 }
18333 }
18336 }
18341 }
18344 }
18346 /* Search backward for non-agu definition of register number REGNO1
18347 or register number REGNO2 in INSN's basic block until
18348 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18349 2. Reach neighbour BBs boundary, or
18350 3. Reach agu definition.
18351 Returns the distance between the non-agu definition point and INSN.
18352 If no definition point, returns -1. */
18354 static int
18357 {
18368 {
18369 edge e;
18370 edge_iterator ei;
18375 {
18378 }
18384 else
18385 {
18390 {
18391 int bb_dist
18397 {
18404 }
18405 }
18408 }
18409 }
18411 /* get_attr_type may modify recog data. We want to make sure
18412 that recog data is valid for instruction INSN, on which
18413 distance_non_agu_define is called. INSN is unchanged here. */
18420 }
18422 /* Return the distance in half-cycles between INSN and the next
18423 insn that uses register number REGNO in memory address added
18424 to DISTANCE. Return -1 if REGNO0 is set.
18426 Put true value into *FOUND if register usage was found and
18427 false otherwise.
18428 Put true value into *REDEFINED if register redefinition was
18429 found and false otherwise. */
18431 static int
18435 {
18444 {
18447 /* If insn and start belong to the same bb, set prev to insn,
18448 so the call to increase_distance will increase the distance
18449 between insns by 1. */
18451 }
18456 {
18458 {
18461 {
18462 /* Return DISTANCE if OP0 is used in memory
18463 address in NEXT. */
18466 }
18469 {
18470 /* Return -1 if OP0 is set in NEXT. */
18473 }
18476 }
18482 }
18485 }
18487 /* Return the distance between INSN and the next insn that uses
18488 register number REGNO0 in memory address. Return -1 if no such
18489 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18491 static int
18493 {
18505 {
18506 edge e;
18507 edge_iterator ei;
18512 {
18515 }
18521 else
18522 {
18528 {
18529 int bb_dist
18534 {
18541 }
18542 }
18545 }
18546 }
18552 }
18554 /* Define this macro to tune LEA priority vs ADD, it take effect when
18555 there is a dilemma of choicing LEA or ADD
18556 Negative value: ADD is more preferred than LEA
18557 Zero: Netrual
18558 Positive value: LEA is more preferred than ADD*/
18559 #define IX86_LEA_PRIORITY 0
18561 /* Return true if usage of lea INSN has performance advantage
18562 over a sequence of instructions. Instructions sequence has
18563 SPLIT_COST cycles higher latency than lea latency. */
18565 static bool
18568 {
18571 /* For Silvermont if using a 2-source or 3-source LEA for
18572 non-destructive destination purposes, or due to wanting
18573 ability to use SCALE, the use of LEA is justified. */
18575 {
18583 }
18589 {
18590 /* If there is no non AGU operand definition, no AGU
18591 operand usage and split cost is 0 then both lea
18592 and non lea variants have same priority. Currently
18593 we prefer lea for 64 bit code and non lea on 32 bit
18594 code. */
18597 else
18599 }
18601 /* With longer definitions distance lea is more preferable.
18602 Here we change it to take into account splitting cost and
18603 lea priority. */
18606 /* If there is no use in memory addess then we just check
18607 that split cost exceeds AGU stall. */
18611 /* If this insn has both backward non-agu dependence and forward
18612 agu dependence, the one with short distance takes effect. */
18614 }
18616 /* Return true if it is legal to clobber flags by INSN and
18617 false otherwise. */
18619 static bool
18621 {
18623 df_ref use;
18624 bitmap live;
18627 {
18629 {
18636 }
18642 }
18646 }
18648 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18649 move and add to avoid AGU stalls. */
18651 bool
18653 {
18656 /* Check if we need to optimize. */
18660 /* Check it is correct to split here. */
18668 /* We need to split only adds with non destructive
18669 destination operand. */
18672 else
18674 }
18676 /* Return true if we should emit lea instruction instead of mov
18677 instruction. */
18679 bool
18681 {
18684 /* Check if we need to optimize. */
18688 /* Use lea for reg to reg moves only. */
18696 }
18698 /* Return true if we need to split lea into a sequence of
18699 instructions to avoid AGU stalls. */
18701 bool
18703 {
18709 /* Check we need to optimize. */
18713 /* The "at least two components" test below might not catch simple
18714 move or zero extension insns if parts.base is non-NULL and parts.disp
18715 is const0_rtx as the only components in the address, e.g. if the
18716 register is %rbp or %r13. As this test is much cheaper and moves or
18717 zero extensions are the common case, do this check first. */
18723 /* Check if it is OK to split here. */
18730 /* There should be at least two components in the address. */
18735 /* We should not split into add if non legitimate pic
18736 operand is used as displacement. */
18751 /* Compute how many cycles we will add to execution time
18752 if split lea into a sequence of instructions. */
18754 {
18755 /* Have to use mov instruction if non desctructive
18756 destination form is used. */
18760 /* Have to add index to base if both exist. */
18764 /* Have to use shift and adds if scale is 2 or greater. */
18766 {
18771 else
18773 }
18775 /* Have to use add instruction with immediate if
18776 disp is non zero. */
18780 /* Subtract the price of lea. */
18782 }
18786 }
18788 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18789 matches destination. RTX includes clobber of FLAGS_REG. */
18791 static void
18794 {
18801 }
18803 /* Return true if regno1 def is nearest to the insn. */
18805 static bool
18807 {
18814 {
18816 {
18819 }
18825 }
18827 /* None of the regs is defined in the bb. */
18829 }
18831 /* Split lea instructions into a sequence of instructions
18832 which are executed on ALU to avoid AGU stalls.
18833 It is assumed that it is allowed to clobber flags register
18834 at lea position. */
18836 void
18838 {
18854 {
18857 }
18860 {
18863 }
18869 {
18870 /* Case r1 = r1 + ... */
18872 {
18873 /* If we have a case r1 = r1 + C * r2 then we
18874 should use multiplication which is very
18875 expensive. Assume cost model is wrong if we
18876 have such case here. */
18881 }
18882 else
18883 {
18884 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18888 /* Use shift for scaling. */
18897 }
18898 }
18900 {
18903 }
18904 else
18905 {
18907 {
18910 }
18912 {
18915 }
18916 else
18917 {
18922 else
18923 {
18924 rtx tmp1;
18926 /* Find better operand for SET instruction, depending
18927 on which definition is farther from the insn. */
18930 else
18940 }
18943 }
18947 }
18948 }
18950 /* Return true if it is ok to optimize an ADD operation to LEA
18951 operation to avoid flag register consumation. For most processors,
18952 ADD is faster than LEA. For the processors like BONNELL, if the
18953 destination register of LEA holds an actual address which will be
18954 used soon, LEA is better and otherwise ADD is better. */
18956 bool
18958 {
18963 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18971 }
18973 /* Return true if destination reg of SET_BODY is shift count of
18974 USE_BODY. */
18976 static bool
18978 {
18979 rtx set_dest;
18980 rtx shift_rtx;
18983 /* Retrieve destination of SET_BODY. */
18985 {
18994 use_body))
18999 }
19001 /* Retrieve shift count of USE_BODY. */
19003 {
19015 }
19023 {
19026 /* Return true if shift count is dest of SET_BODY. */
19028 {
19029 /* Add check since it can be invoked before register
19030 allocation in pre-reload schedule. */
19036 }
19037 }
19040 }
19042 /* Return true if destination reg of SET_INSN is shift count of
19043 USE_INSN. */
19045 bool
19047 {
19050 }
19052 /* Return TRUE or FALSE depending on whether the unary operator meets the
19053 appropriate constraints. */
19055 bool
19057 machine_mode,
19059 {
19060 /* If one of operands is memory, source and destination must match. */
19066 }
19068 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19069 are ok, keeping in mind the possible movddup alternative. */
19071 bool
19073 {
19079 }
19081 /* Post-reload splitter for converting an SF or DFmode value in an
19082 SSE register into an unsigned SImode. */
19084 void
19086 {
19087 machine_mode vecmode;
19097 /* Load up the value into the low element. We must ensure that the other
19098 elements are valid floats -- zero is the easiest such value. */
19100 {
19103 else
19105 }
19106 else
19107 {
19112 else
19114 }
19134 else
19139 }
19141 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19142 Expects the 64-bit DImode to be supplied in a pair of integral
19143 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19144 -mfpmath=sse, !optimize_size only. */
19146 void
19148 {
19152 rtx x;
19158 {
19161 }
19162 else
19163 {
19167 }
19175 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19178 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19179 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19180 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19181 (0x1.0p84 + double(fp_value_hi_xmm)).
19182 Note these exponents differ by 32. */
19186 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19187 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19196 /* Add the upper and lower DFmode values together. */
19199 else
19200 {
19204 }
19207 }
19209 /* Not used, but eases macroization of patterns. */
19210 void
19212 {
19214 }
19216 /* Convert an unsigned SImode value into a DFmode. Only currently used
19217 for SSE, but applicable anywhere. */
19219 void
19221 {
19222 REAL_VALUE_TYPE TWO31r;
19237 }
19239 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19240 32-bit mode; otherwise we have a direct convert instruction. */
19242 void
19244 {
19245 REAL_VALUE_TYPE TWO32r;
19263 }
19265 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19266 For x86_32, -mfpmath=sse, !optimize_size only. */
19267 void
19269 {
19270 REAL_VALUE_TYPE ONE16r;
19289 }
19291 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19292 a vector of unsigned ints VAL to vector of floats TARGET. */
19294 void
19296 {
19298 REAL_VALUE_TYPE TWO16r;
19305 else
19310 OPTAB_DIRECT);
19321 OPTAB_DIRECT);
19323 OPTAB_DIRECT);
19326 }
19328 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19329 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19330 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19331 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19333 rtx
19335 {
19336 REAL_VALUE_TYPE TWO31r;
19351 {
19357 }
19366 OPTAB_DIRECT);
19367 else
19368 {
19374 OPTAB_DIRECT);
19375 }
19378 }
19380 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19381 then replicate the value for all elements of the vector
19382 register. */
19384 rtx
19386 {
19388 rtvec v;
19389 machine_mode scalar_mode;
19392 {
19425 }
19426 }
19428 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19429 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19430 for an SSE register. If VECT is true, then replicate the mask for
19431 all elements of the vector register. If INVERT is true, then create
19432 a mask excluding the sign bit. */
19434 rtx
19436 {
19438 wide_int w;
19442 {
19473 }
19480 /* Force this value into the low part of a fp vector constant. */
19489 }
19491 /* Generate code for floating point ABS or NEG. */
19493 void
19495 rtx operands[])
19496 {
19507 {
19513 }
19515 /* NEG and ABS performed with SSE use bitwise mask operations.
19516 Create the appropriate mask now. */
19519 else
19529 {
19531 rtvec par;
19536 else
19537 {
19540 }
19542 }
19543 else
19545 }
19547 /* Expand a copysign operation. Special case operand 0 being a constant. */
19549 void
19551 {
19565 else
19569 {
19576 {
19579 else
19580 {
19584 }
19585 }
19595 else
19599 }
19600 else
19601 {
19611 else
19615 }
19616 }
19618 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19619 be a constant, and so has already been expanded into a vector constant. */
19621 void
19623 {
19639 {
19642 }
19643 }
19645 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19646 so we have to do two masks. */
19648 void
19650 {
19665 {
19666 /* Shouldn't happen often (it's useless, obviously), but when it does
19667 we'd generate incorrect code if we continue below. */
19670 }
19673 {
19684 }
19685 else
19686 {
19688 {
19690 }
19692 {
19696 }
19700 {
19703 }
19705 {
19710 }
19712 }
19716 }
19718 /* Return TRUE or FALSE depending on whether the first SET in INSN
19719 has source and destination with matching CC modes, and that the
19720 CC mode is at least as constrained as REQ_MODE. */
19722 bool
19724 {
19725 rtx set;
19726 machine_mode set_mode;
19736 {
19746 /* FALLTHRU */
19750 /* FALLTHRU */
19754 /* FALLTHRU */
19768 }
19771 }
19773 /* Generate insn patterns to do an integer compare of OPERANDS. */
19775 static rtx
19777 {
19778 machine_mode cmpmode;
19784 /* This is very simple, but making the interface the same as in the
19785 FP case makes the rest of the code easier. */
19789 /* Return the test that should be put into the flags user, i.e.
19790 the bcc, scc, or cmov instruction. */
19792 }
19794 /* Figure out whether to use ordered or unordered fp comparisons.
19795 Return the appropriate mode to use. */
19797 machine_mode
19799 {
19800 /* ??? In order to make all comparisons reversible, we do all comparisons
19801 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19802 all forms trapping and nontrapping comparisons, we can make inequality
19803 comparisons trapping again, since it results in better code when using
19804 FCOM based compares. */
19806 }
19808 machine_mode
19810 {
19814 {
19817 }
19820 {
19821 /* Only zero flag is needed. */
19825 /* Codes needing carry flag. */
19828 /* Detect overflow checks. They need just the carry flag. */
19832 else
19837 /* Codes possibly doable only with sign flag when
19838 comparing against zero. */
19843 else
19844 /* For other cases Carry flag is not required. */
19846 /* Codes doable only with sign flag when comparing
19847 against zero, but we miss jump instruction for it
19848 so we need to use relational tests against overflow
19849 that thus needs to be zero. */
19854 else
19856 /* strcmp pattern do (use flags) and combine may ask us for proper
19857 mode. */
19862 }
19863 }
19865 /* Return the fixed registers used for condition codes. */
19867 static bool
19869 {
19873 }
19875 /* If two condition code modes are compatible, return a condition code
19876 mode which is compatible with both. Otherwise, return
19877 VOIDmode. */
19879 static machine_mode
19881 {
19898 {
19912 {
19926 }
19930 /* These are only compatible with themselves, which we already
19931 checked above. */
19933 }
19934 }
19937 /* Return a comparison we can do and that it is equivalent to
19938 swap_condition (code) apart possibly from orderedness.
19939 But, never change orderedness if TARGET_IEEE_FP, returning
19940 UNKNOWN in that case if necessary. */
19942 static enum rtx_code
19944 {
19946 {
19957 }
19958 }
19960 /* Return cost of comparison CODE using the best strategy for performance.
19961 All following functions do use number of instructions as a cost metrics.
19962 In future this should be tweaked to compute bytes for optimize_size and
19963 take into account performance of various instructions on various CPUs. */
19965 static int
19967 {
19970 /* The cost of code using bit-twiddling on %ah. */
19972 {
19995 }
19998 {
20005 }
20006 }
20008 /* Return strategy to use for floating-point. We assume that fcomi is always
20009 preferrable where available, since that is also true when looking at size
20010 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20012 enum ix86_fpcmp_strategy
20014 {
20015 /* Do fcomi/sahf based test when profitable. */
20024 }
20026 /* Swap, force into registers, or otherwise massage the two operands
20027 to a fp comparison. The operands are updated in place; the new
20028 comparison code is returned. */
20030 static enum rtx_code
20032 {
20038 /* All of the unordered compare instructions only work on registers.
20039 The same is true of the fcomi compare instructions. The XFmode
20040 compare instructions require registers except when comparing
20041 against zero or when converting operand 1 from fixed point to
20042 floating point. */
20051 {
20054 }
20055 else
20056 {
20057 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20058 things around if they appear profitable, otherwise force op0
20059 into a register. */
20065 {
20068 {
20071 }
20072 }
20078 {
20083 {
20086 }
20087 else
20089 }
20090 }
20092 /* Try to rearrange the comparison to make it cheaper. */
20096 {
20101 }
20106 }
20108 /* Convert comparison codes we use to represent FP comparison to integer
20109 code that will result in proper branch. Return UNKNOWN if no such code
20110 is available. */
20112 enum rtx_code
20114 {
20116 {
20139 }
20140 }
20142 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20144 static rtx
20146 {
20153 /* Do fcomi/sahf based test when profitable. */
20155 {
20160 tmp);
20168 tmp);
20177 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20184 /* In the unordered case, we have to check C2 for NaN's, which
20185 doesn't happen to work out to anything nice combination-wise.
20186 So do some bit twiddling on the value we've got in AH to come
20187 up with an appropriate set of condition codes. */
20191 {
20195 {
20198 }
20199 else
20200 {
20206 }
20211 {
20216 }
20217 else
20218 {
20221 }
20226 {
20229 }
20230 else
20231 {
20235 }
20240 {
20246 }
20247 else
20248 {
20251 }
20256 {
20261 }
20262 else
20263 {
20266 }
20271 {
20276 }
20277 else
20278 {
20281 }
20295 }
20300 }
20302 /* Return the test that should be put into the flags user, i.e.
20303 the bcc, scc, or cmov instruction. */
20306 const0_rtx);
20307 }
20309 static rtx
20311 {
20312 rtx ret;
20318 {
20321 }
20322 else
20326 }
20328 void
20330 {
20332 rtx tmp;
20335 {
20342 simple:
20346 pc_rtx);
20354 /* Expand DImode branch into multiple compare+branch. */
20355 {
20359 machine_mode submode;
20362 {
20365 }
20372 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20373 avoid two branches. This costs one extra insn, so disable when
20374 optimizing for size. */
20379 {
20397 }
20399 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20400 op1 is a constant and the low word is zero, then we can just
20401 examine the high word. Similarly for low word -1 and
20402 less-or-equal-than or greater-than. */
20406 {
20409 {
20412 }
20416 {
20419 }
20423 }
20425 /* Otherwise, we need two or three jumps. */
20434 {
20448 }
20450 /*
20451 * a < b =>
20452 * if (hi(a) < hi(b)) goto true;
20453 * if (hi(a) > hi(b)) goto false;
20454 * if (lo(a) < lo(b)) goto true;
20455 * false:
20456 */
20468 }
20473 }
20474 }
20476 /* Split branch based on floating point condition. */
20477 void
20480 {
20481 rtx condition;
20482 rtx i;
20485 {
20488 }
20491 tmp);
20499 }
20501 void
20503 {
20504 rtx ret;
20511 }
20513 /* Expand comparison setting or clearing carry flag. Return true when
20514 successful and set pop for the operation. */
20515 static bool
20517 {
20518 machine_mode mode =
20521 /* Do not handle double-mode compares that go through special path. */
20526 {
20527 rtx compare_op;
20532 /* Shortcut: following common codes never translate
20533 into carry flag compares. */
20538 /* These comparisons require zero flag; swap operands so they won't. */
20541 {
20544 }
20546 /* Try to expand the comparison and verify that we end up with
20547 carry flag based comparison. This fails to be true only when
20548 we decide to expand comparison using arithmetic that is not
20549 too common scenario. */
20558 else
20567 }
20573 {
20578 /* Convert a==0 into (unsigned)a<1. */
20587 /* Convert a>b into b<a or a>=b-1. */
20591 {
20593 /* Bail out on overflow. We still can swap operands but that
20594 would force loading of the constant into register. */
20599 }
20600 else
20601 {
20604 }
20607 /* Convert a>=0 into (unsigned)a<0x80000000. */
20625 }
20626 /* Swapping operands may cause constant to appear as first operand. */
20628 {
20632 }
20636 }
20638 bool
20640 {
20643 rtx compare_op;
20665 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20666 HImode insns, we'd be swallowed in word prefix ops. */
20672 {
20676 HOST_WIDE_INT diff;
20679 /* Sign bit compares are better done using shifts than we do by using
20680 sbb. */
20683 {
20684 /* Detect overlap between destination and compare sources. */
20688 {
20689 rtx flags;
20698 {
20700 compare_code
20702 }
20704 /* To simplify rest of code, restrict to the GEU case. */
20706 {
20710 }
20711 else
20712 {
20715 reverse_condition_maybe_unordered
20717 else
20720 }
20729 else
20732 }
20733 else
20734 {
20737 else
20738 {
20741 }
20743 }
20746 {
20747 /*
20748 * cmpl op0,op1
20749 * sbbl dest,dest
20750 * [addl dest, ct]
20751 *
20752 * Size 5 - 8.
20753 */
20758 }
20760 {
20761 /*
20762 * cmpl op0,op1
20763 * sbbl dest,dest
20764 * orl $ct, dest
20765 *
20766 * Size 8.
20767 */
20771 }
20773 {
20774 /*
20775 * cmpl op0,op1
20776 * sbbl dest,dest
20777 * notl dest
20778 * [addl dest, cf]
20779 *
20780 * Size 8 - 11.
20781 */
20787 }
20788 else
20789 {
20790 /*
20791 * cmpl op0,op1
20792 * sbbl dest,dest
20793 * [notl dest]
20794 * andl cf - ct, dest
20795 * [addl dest, ct]
20796 *
20797 * Size 8 - 11.
20798 */
20801 {
20805 }
20815 }
20821 }
20824 {
20829 {
20832 /* We may be reversing unordered compare to normal compare, that
20833 is not valid in general (we may convert non-trapping condition
20834 to trapping one), however on i386 we currently emit all
20835 comparisons unordered. */
20837 }
20838 else
20841 {
20845 }
20846 }
20851 {
20856 {
20861 }
20862 }
20864 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20868 {
20869 /* If lea code below could be used, only optimize
20870 if it results in a 2 insn sequence. */
20876 {
20877 /*
20878 * notl op1 (if necessary)
20879 * sarl $31, op1
20880 * orl cf, op1
20881 */
20883 {
20887 }
20898 }
20899 }
20907 {
20908 /*
20909 * xorl dest,dest
20910 * cmpl op1,op2
20911 * setcc dest
20912 * lea cf(dest*(ct-cf)),dest
20913 *
20914 * Size 14.
20915 *
20916 * This also catches the degenerate setcc-only case.
20917 */
20919 rtx tmp;
20925 /* On x86_64 the lea instruction operates on Pmode, so we need
20926 to get arithmetics done in proper mode to match. */
20929 else
20930 {
20931 rtx out1;
20934 nops++;
20936 {
20938 nops++;
20939 }
20940 }
20942 {
20944 nops++;
20945 }
20947 {
20950 else
20952 }
20957 }
20959 /*
20960 * General case: Jumpful:
20961 * xorl dest,dest cmpl op1, op2
20962 * cmpl op1, op2 movl ct, dest
20963 * setcc dest jcc 1f
20964 * decl dest movl cf, dest
20965 * andl (cf-ct),dest 1:
20966 * addl ct,dest
20967 *
20968 * Size 20. Size 14.
20969 *
20970 * This is reasonably steep, but branch mispredict costs are
20971 * high on modern cpus, so consider failing only if optimizing
20972 * for space.
20973 */
20978 {
20980 {
20985 {
20988 /* We may be reversing unordered compare to normal compare,
20989 that is not valid in general (we may convert non-trapping
20990 condition to trapping one), however on i386 we currently
20991 emit all comparisons unordered. */
20993 }
20994 else
20995 {
20999 }
21002 {
21006 }
21007 }
21010 {
21011 /* notl op1 (if needed)
21012 sarl $31, op1
21013 andl (cf-ct), op1
21014 addl ct, op1
21016 For x < 0 (resp. x <= -1) there will be no notl,
21017 so if possible swap the constants to get rid of the
21018 complement.
21019 True/false will be -1/0 while code below (store flag
21020 followed by decrement) is 0/-1, so the constants need
21021 to be exchanged once more. */
21024 {
21027 }
21028 else
21032 }
21033 else
21034 {
21038 constm1_rtx,
21040 }
21052 }
21053 }
21056 {
21057 /* Try a few things more with specific constants and a variable. */
21059 optab op;
21065 /* If one of the two operands is an interesting constant, load a
21066 constant with the above and mask it in with a logical operation. */
21069 {
21075 else
21077 }
21079 {
21085 else
21087 }
21088 else
21095 /* Recurse to get the constant loaded. */
21099 /* Mask in the interesting variable. */
21101 OPTAB_WIDEN);
21106 }
21108 /*
21109 * For comparison with above,
21110 *
21111 * movl cf,dest
21112 * movl ct,tmp
21113 * cmpl op1,op2
21114 * cmovcc tmp,dest
21115 *
21116 * Size 15.
21117 */
21139 }
21141 /* Swap, force into registers, or otherwise massage the two operands
21142 to an sse comparison with a mask result. Thus we differ a bit from
21143 ix86_prepare_fp_compare_args which expects to produce a flags result.
21145 The DEST operand exists to help determine whether to commute commutative
21146 operators. The POP0/POP1 operands are updated in place. The new
21147 comparison code is returned, or UNKNOWN if not implementable. */
21149 static enum rtx_code
21152 {
21154 {
21157 /* AVX supports all the needed comparisons. */
21160 /* We have no LTGT as an operator. We could implement it with
21161 NE & ORDERED, but this requires an extra temporary. It's
21162 not clear that it's worth it. */
21169 /* These are supported directly. */
21176 /* AVX has 3 operand comparisons, no need to swap anything. */
21179 /* For commutative operators, try to canonicalize the destination
21180 operand to be first in the comparison - this helps reload to
21181 avoid extra moves. */
21184 /* FALLTHRU */
21190 /* These are not supported directly before AVX, and furthermore
21191 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21192 comparison operands to transform into something that is
21193 supported. */
21200 }
21203 }
21205 /* Detect conditional moves that exactly match min/max operational
21206 semantics. Note that this is IEEE safe, as long as we don't
21207 interchange the operands.
21209 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21210 and TRUE if the operation is successful and instructions are emitted. */
21212 static bool
21215 {
21216 machine_mode mode;
21218 rtx tmp;
21221 ;
21224 else
21231 else
21236 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21237 but MODE may be a vector mode and thus not appropriate. */
21239 {
21241 rtvec v;
21246 }
21247 else
21248 {
21251 }
21255 }
21257 /* Expand an sse vector comparison. Return the register with the result. */
21259 static rtx
21262 {
21266 /* In general case result of comparison can differ from operands' type. */
21267 machine_mode cmp_mode;
21269 /* In AVX512F the result of comparison is an integer mask. */
21271 rtx x;
21274 {
21279 }
21280 else
21293 /* Compare patterns for int modes are unspec in AVX512F only. */
21295 {
21299 {
21316 }
21319 {
21322 }
21323 }
21327 {
21330 }
21331 else
21335 }
21337 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21338 operations. This is used for both scalar and vector conditional moves. */
21340 static void
21342 {
21346 /* In AVX512F the result of comparison is an integer mask. */
21354 {
21356 }
21359 {
21363 }
21366 {
21371 }
21374 {
21378 }
21381 {
21389 op_true,
21390 op_false)));
21391 }
21392 else
21393 {
21403 {
21417 {
21424 }
21439 {
21446 }
21470 }
21473 {
21477 }
21478 else
21479 {
21485 else
21497 }
21498 }
21499 }
21501 /* Expand a floating-point conditional move. Return true if successful. */
21503 bool
21505 {
21513 {
21514 machine_mode cmode;
21516 /* Since we've no cmove for sse registers, don't force bad register
21517 allocation just to gain access to it. Deny movcc when the
21518 comparison mode doesn't match the move mode. */
21537 }
21544 /* The floating point conditional move instructions don't directly
21545 support conditions resulting from a signed integer comparison. */
21549 {
21554 }
21561 }
21563 /* Expand a floating-point vector conditional move; a vcond operation
21564 rather than a movcc operation. */
21566 bool
21568 {
21570 rtx cmp;
21575 {
21576 rtx temp;
21578 {
21595 }
21597 OPTAB_DIRECT);
21600 }
21610 }
21612 /* Expand a signed/unsigned integral vector conditional move. */
21614 bool
21616 {
21626 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21627 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21636 {
21640 {
21646 }
21649 {
21655 }
21656 }
21665 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21669 ;
21670 else
21671 {
21672 /* Canonicalize the comparison to EQ, GT, GTU. */
21674 {
21691 /* FALLTHRU */
21701 }
21703 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21705 {
21707 {
21709 /* SSE4.1 supports EQ. */
21716 /* SSE4.2 supports GT/GTU. */
21723 }
21724 }
21726 /* Unsigned parallel compare is not supported by the hardware.
21727 Play some tricks to turn this into a signed comparison
21728 against 0. */
21730 {
21734 {
21741 {
21746 {
21755 }
21756 /* Subtract (-(INT MAX) - 1) from both operands to make
21757 them signed. */
21768 }
21777 /* Perform a parallel unsigned saturating subtraction. */
21790 }
21791 }
21792 }
21794 /* Allow the comparison to be done in one mode, but the movcc to
21795 happen in another mode. */
21797 {
21800 }
21801 else
21802 {
21808 }
21813 }
21815 /* AVX512F does support 64-byte integer vector operations,
21816 thus the longest vector we are faced with is V64QImode. */
21817 #define MAX_VECT_LEN 64
21819 struct expand_vec_perm_d
21820 {
21823 machine_mode vmode;
21827 };
21829 static bool
21832 {
21833 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21834 expander, so args are either in d, or in op0, op1 etc. */
21840 {
21871 {
21874 }
21878 {
21881 }
21885 {
21888 }
21904 {
21907 }
21911 {
21914 }
21918 {
21921 }
21925 }
21930 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21931 expander, so args are either in d, or in op0, op1 etc. */
21933 {
21941 }
21945 }
21947 /* Expand a variable vector permutation. */
21949 void
21951 {
21962 /* Number of elements in the vector. */
21971 {
21973 {
21974 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21975 an constant shuffle operand. With a tiny bit of effort we can
21976 use VPERMD instead. A re-interpretation stall for V4DFmode is
21977 unfortunate but there's no avoiding it.
21978 Similarly for V16HImode we don't have instructions for variable
21979 shuffling, while for V32QImode we can use after preparing suitable
21980 masks vpshufb; vpshufb; vpermq; vpor. */
21983 {
21987 }
21988 else
21989 {
21993 }
21996 /* Replicate the low bits of the V4DImode mask into V8SImode:
21997 mask = { A B C D }
21998 t1 = { A A B B C C D D }. */
22006 else
22009 /* Multiply the shuffle indicies by two. */
22011 OPTAB_DIRECT);
22013 /* Add one to the odd shuffle indicies:
22014 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22016 {
22019 }
22023 OPTAB_DIRECT);
22025 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22030 }
22033 {
22035 /* The VPERMD and VPERMPS instructions already properly ignore
22036 the high bits of the shuffle elements. No need for us to
22037 perform an AND ourselves. */
22039 {
22044 }
22045 else
22046 {
22052 }
22059 else
22060 {
22066 }
22070 /* By combining the two 128-bit input vectors into one 256-bit
22071 input vector, we can use VPERMD and VPERMPS for the full
22072 two-operand shuffle. */
22104 /* From mask create two adjusted masks, which contain the same
22105 bits as mask in the low 7 bits of each vector element.
22106 The first mask will have the most significant bit clear
22107 if it requests element from the same 128-bit lane
22108 and MSB set if it requests element from the other 128-bit lane.
22109 The second mask will have the opposite values of the MSB,
22110 and additionally will have its 128-bit lanes swapped.
22111 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22112 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22113 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22114 stands for other 12 bytes. */
22115 /* The bit whether element is from the same lane or the other
22116 lane is bit 4, so shift it up by 3 to the MSB position. */
22120 /* Clear MSB bits from the mask just in case it had them set. */
22122 /* After this t1 will have MSB set for elements from other lane. */
22124 /* Clear bits other than MSB. */
22126 /* Or in the lower bits from mask into t3. */
22128 /* And invert MSB bits in t1, so MSB is set for elements from the same
22129 lane. */
22131 /* Swap 128-bit lanes in t3. */
22136 /* And or in the lower bits from mask into t1. */
22139 {
22140 /* Each of these shuffles will put 0s in places where
22141 element from the other 128-bit lane is needed, otherwise
22142 will shuffle in the requested value. */
22146 /* For t3 the 128-bit lanes are swapped again. */
22151 /* And oring both together leads to the result. */
22158 }
22161 /* Similarly to the above one_operand_shuffle code,
22162 just for repeated twice for each operand. merge_two:
22163 code will merge the two results together. */
22187 }
22188 }
22191 {
22192 /* The XOP VPPERM insn supports three inputs. By ignoring the
22193 one_operand_shuffle special case, we avoid creating another
22194 set of constant vectors in memory. */
22197 /* mask = mask & {2*w-1, ...} */
22199 }
22200 else
22201 {
22202 /* mask = mask & {w-1, ...} */
22204 }
22212 /* For non-QImode operations, convert the word permutation control
22213 into a byte permutation control. */
22215 {
22220 /* Convert mask to vector of chars. */
22223 /* Replicate each of the input bytes into byte positions:
22224 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22225 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22226 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22233 else
22236 /* Convert it into the byte positions by doing
22237 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22243 }
22245 /* The actual shuffle operations all operate on V16QImode. */
22250 {
22257 }
22259 {
22266 }
22267 else
22268 {
22272 /* Shuffle the two input vectors independently. */
22278 merge_two:
22279 /* Then merge them together. The key is whether any given control
22280 element contained a bit set that indicates the second word. */
22284 {
22285 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22286 more shuffle to convert the V2DI input mask into a V4SI
22287 input mask. At which point the masking that expand_int_vcond
22288 will work as desired. */
22296 }
22318 }
22319 }
22321 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22322 true if we should do zero extension, else sign extension. HIGH_P is
22323 true if we want the N/2 high elements, else the low elements. */
22325 void
22327 {
22329 rtx tmp;
22332 {
22338 {
22342 else
22345 extract
22351 else
22354 extract
22360 else
22363 extract
22369 else
22372 extract
22378 else
22381 extract
22387 else
22390 extract
22396 else
22402 else
22408 else
22413 }
22416 {
22419 }
22421 {
22422 /* Shift higher 8 bytes to lower 8 bytes. */
22427 }
22428 else
22432 }
22433 else
22434 {
22438 {
22442 else
22448 else
22454 else
22459 }
22463 else
22470 }
22471 }
22473 /* Expand conditional increment or decrement using adb/sbb instructions.
22474 The default case using setcc followed by the conditional move can be
22475 done by generic code. */
22476 bool
22478 {
22480 rtx flags;
22482 rtx compare_op;
22485 machine_mode mode;
22500 {
22503 }
22506 {
22510 reverse_condition_maybe_unordered
22512 else
22514 }
22518 /* Construct either adc or sbb insn. */
22520 {
22522 {
22537 }
22538 }
22539 else
22540 {
22542 {
22557 }
22558 }
22562 }
22565 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22566 but works for floating pointer parameters and nonoffsetable memories.
22567 For pushes, it returns just stack offsets; the values will be saved
22568 in the right order. Maximally three parts are generated. */
22570 static int
22572 {
22577 else
22583 /* Optimize constant pool reference to immediates. This is used by fp
22584 moves, that force all constants to memory to allow combining. */
22586 {
22590 }
22593 {
22594 /* The only non-offsetable memories we handle are pushes. */
22603 }
22606 {
22608 /* Caution: if we looked through a constant pool memory above,
22609 the operand may actually have a different mode now. That's
22610 ok, since we want to pun this all the way back to an integer. */
22614 }
22617 {
22620 else
22621 {
22625 {
22629 }
22631 {
22636 }
22638 {
22639 REAL_VALUE_TYPE r;
22644 {
22651 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22652 long double may not be 80-bit. */
22661 }
22664 }
22665 else
22667 }
22668 }
22669 else
22670 {
22674 {
22677 {
22681 }
22683 {
22687 }
22689 {
22690 REAL_VALUE_TYPE r;
22696 /* real_to_target puts 32-bit pieces in each long. */
22698 gen_int_mode
22701 DImode);
22705 else
22707 gen_int_mode
22710 DImode);
22711 }
22712 else
22714 }
22715 }
22718 }
22720 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22721 Return false when normal moves are needed; true when all required
22722 insns have been emitted. Operands 2-4 contain the input values
22723 int the correct order; operands 5-7 contain the output values. */
22725 void
22727 {
22735 /* The DFmode expanders may ask us to move double.
22736 For 64bit target this is single move. By hiding the fact
22737 here we simplify i386.md splitters. */
22739 {
22740 /* Optimize constant pool reference to immediates. This is used by
22741 fp moves, that force all constants to memory to allow combining. */
22748 {
22751 }
22752 else
22757 }
22759 /* The only non-offsettable memory we handle is push. */
22762 else
22769 /* When emitting push, take care for source operands on the stack. */
22772 {
22775 /* Compensate for the stack decrement by 4. */
22780 /* src_base refers to the stack pointer and is
22781 automatically decreased by emitted push. */
22785 }
22787 /* We need to do copy in the right order in case an address register
22788 of the source overlaps the destination. */
22790 {
22791 rtx tmp;
22794 {
22798 collisions++;
22799 }
22801 /* Collision in the middle part can be handled by reordering. */
22803 {
22806 }
22810 {
22812 {
22815 }
22816 else
22817 {
22820 }
22821 }
22823 /* If there are more collisions, we can't handle it by reordering.
22824 Do an lea to the last part and use only one colliding move. */
22826 {
22827 rtx base;
22833 /* Handle the case when the last part isn't valid for lea.
22834 Happens in 64-bit mode storing the 12-byte XFmode. */
22841 {
22844 }
22845 }
22846 }
22849 {
22851 {
22853 {
22858 }
22860 {
22863 }
22864 }
22865 else
22866 {
22867 /* In 64bit mode we don't have 32bit push available. In case this is
22868 register, it is OK - we will just use larger counterpart. We also
22869 retype memory - these comes from attempt to avoid REX prefix on
22870 moving of second half of TFmode value. */
22872 {
22874 {
22885 }
22889 }
22890 }
22894 }
22896 /* Choose correct order to not overwrite the source before it is copied. */
22906 {
22908 {
22911 }
22912 }
22913 else
22914 {
22916 {
22919 }
22920 }
22922 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22924 {
22933 }
22939 }
22941 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22942 left shift by a constant, either using a single shift or
22943 a sequence of add instructions. */
22945 static void
22947 {
22953 {
22957 }
22958 else
22959 {
22962 }
22963 }
22965 void
22967 {
22976 {
22981 {
22987 }
22988 else
22989 {
22997 }
22999 }
23006 {
23007 /* Assuming we've chosen a QImode capable registers, then 1 << N
23008 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23010 {
23026 }
23028 /* Otherwise, we can get the same results by manually performing
23029 a bit extract operation on bit 5/6, and then performing the two
23030 shifts. The two methods of getting 0/1 into low/high are exactly
23031 the same size. Avoiding the shift in the bit extract case helps
23032 pentium4 a bit; no one else seems to care much either way. */
23033 else
23034 {
23035 machine_mode half_mode;
23039 HOST_WIDE_INT bits;
23040 rtx x;
23043 {
23049 }
23050 else
23051 {
23057 }
23061 else
23069 }
23074 }
23077 {
23078 /* For -1 << N, we can avoid the shld instruction, because we
23079 know that we're shifting 0...31/63 ones into a -1. */
23083 else
23085 }
23086 else
23087 {
23095 }
23100 {
23106 }
23107 else
23108 {
23113 }
23114 }
23116 void
23118 {
23128 {
23133 {
23139 }
23141 {
23150 }
23151 else
23152 {
23160 }
23161 }
23162 else
23163 {
23175 {
23183 scratch));
23184 }
23185 else
23186 {
23191 }
23192 }
23193 }
23195 void
23197 {
23207 {
23212 {
23219 }
23220 else
23221 {
23229 }
23230 }
23231 else
23232 {
23244 {
23250 scratch));
23251 }
23252 else
23253 {
23258 }
23259 }
23260 }
23262 /* Predict just emitted jump instruction to be taken with probability PROB. */
23263 static void
23265 {
23269 }
23271 /* Helper function for the string operations below. Dest VARIABLE whether
23272 it is aligned to VALUE bytes. If true, jump to the label. */
23275 {
23280 else
23286 else
23289 }
23291 /* Adjust COUNTER by the VALUE. */
23292 static void
23294 {
23299 }
23301 /* Zero extend possibly SImode EXP to Pmode register. */
23302 rtx
23304 {
23306 }
23308 /* Divide COUNTREG by SCALE. */
23309 static rtx
23311 {
23312 rtx sc;
23324 }
23326 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23327 DImode for constant loop counts. */
23329 static machine_mode
23331 {
23339 }
23341 /* Copy the address to a Pmode register. This is used for x32 to
23342 truncate DImode TLS address to a SImode register. */
23344 static rtx
23346 {
23347 rtx reg;
23349 {
23353 }
23354 else
23355 {
23360 }
23361 }
23363 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23364 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23365 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23366 memory by VALUE (supposed to be in MODE).
23368 The size is rounded down to whole number of chunk size moved at once.
23369 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23372 static void
23377 {
23384 rtx size;
23393 /* Those two should combine. */
23395 {
23399 }
23406 /* This assert could be relaxed - in this case we'll need to compute
23407 smallest power of two, containing in PIECE_SIZE_N and pass it to
23408 offset_address. */
23414 {
23418 /* When unrolling for chips that reorder memory reads and writes,
23419 we can save registers by using single temporary.
23420 Also using 4 temporaries is overkill in 32bit mode. */
23422 {
23424 {
23426 {
23427 destmem =
23429 srcmem =
23431 }
23433 }
23434 }
23435 else
23436 {
23440 {
23443 {
23444 srcmem =
23446 }
23448 }
23450 {
23452 {
23453 destmem =
23455 }
23457 }
23458 }
23459 }
23460 else
23462 {
23464 destmem =
23467 }
23477 {
23483 else
23485 }
23486 else
23494 {
23499 }
23501 }
23503 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23504 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23505 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23506 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23507 ORIG_VALUE is the original value passed to memset to fill the memory with.
23508 Other arguments have same meaning as for previous function. */
23510 static void
23513 rtx count,
23515 {
23516 rtx destexp;
23517 rtx srcexp;
23518 rtx countreg;
23519 HOST_WIDE_INT rounded_count;
23521 /* If possible, it is shorter to use rep movs.
23522 TODO: Maybe it is better to move this logic to decide_alg. */
23533 {
23537 }
23538 else
23541 {
23546 }
23551 {
23554 }
23555 else
23556 {
23560 {
23564 }
23565 else
23568 {
23573 }
23574 else
23575 {
23578 }
23581 }
23582 }
23584 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23585 DESTMEM.
23586 SRC is passed by pointer to be updated on return.
23587 Return value is updated DST. */
23588 static rtx
23590 HOST_WIDE_INT size_to_move)
23591 {
23594 machine_mode move_mode;
23597 /* Find the widest mode in which we could perform moves.
23598 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23599 it until move of such size is supported. */
23604 {
23608 }
23610 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23611 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23613 {
23618 {
23622 }
23623 }
23629 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23633 {
23634 /* We move from memory to memory, so we'll need to do it via
23635 a temporary register. */
23646 piece_size);
23648 piece_size);
23649 }
23651 /* Update DST and SRC rtx. */
23654 }
23656 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23657 static void
23660 {
23663 {
23668 /* For now MAX_SIZE should be a power of 2. This assert could be
23669 relaxed, but it'll require a bit more complicated epilogue
23670 expanding. */
23673 {
23676 }
23678 }
23680 {
23686 }
23688 /* When there are stringops, we can cheaply increase dest and src pointers.
23689 Otherwise we save code size by maintaining offset (zero is readily
23690 available from preceding rep operation) and using x86 addressing modes.
23691 */
23693 {
23695 {
23702 }
23704 {
23711 }
23713 {
23720 }
23721 }
23722 else
23723 {
23725 rtx tmp;
23728 {
23739 }
23741 {
23754 }
23756 {
23765 }
23766 }
23767 }
23769 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23770 with value PROMOTED_VAL.
23771 SRC is passed by pointer to be updated on return.
23772 Return value is updated DST. */
23773 static rtx
23775 HOST_WIDE_INT size_to_move)
23776 {
23779 machine_mode move_mode;
23782 /* Find the widest mode in which we could perform moves.
23783 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23784 it until move of such size is supported. */
23789 {
23792 }
23799 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23803 {
23805 {
23808 piece_size);
23810 }
23818 piece_size);
23819 }
23821 /* Update DST rtx. */
23823 }
23824 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23825 static void
23828 {
23829 count =
23835 }
23837 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23838 static void
23841 {
23842 rtx dest;
23845 {
23850 /* For now MAX_SIZE should be a power of 2. This assert could be
23851 relaxed, but it'll require a bit more complicated epilogue
23852 expanding. */
23855 {
23857 {
23860 else
23862 }
23863 }
23865 }
23867 {
23870 }
23872 {
23875 {
23880 }
23881 else
23882 {
23891 }
23894 }
23896 {
23899 {
23902 }
23903 else
23904 {
23909 }
23912 }
23914 {
23920 }
23922 {
23928 }
23930 {
23936 }
23937 }
23939 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23940 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23941 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23942 ignored.
23943 Return value is updated DESTMEM. */
23944 static rtx
23949 {
23952 {
23954 {
23957 {
23960 else
23962 }
23963 else
23969 }
23970 }
23972 }
23974 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23975 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23976 and jump to DONE_LABEL. */
23977 static void
23983 {
23986 rtx modesize;
23989 /* If we do not have vector value to copy, we must reduce size. */
23991 {
23993 {
23998 }
23999 else
24001 }
24002 else
24003 {
24004 /* Choose appropriate vector mode. */
24010 }
24015 {
24018 else
24019 {
24022 }
24024 }
24030 {
24034 }
24036 {
24039 else
24040 {
24043 }
24045 }
24051 }
24053 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24054 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24055 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24056 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24057 DONE_LABEL is a label after the whole copying sequence. The label is created
24058 on demand if *DONE_LABEL is NULL.
24059 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24060 bounds after the initial copies.
24062 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24063 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24064 we will dispatch to a library call for large blocks.
24066 In pseudocode we do:
24068 if (COUNT < SIZE)
24069 {
24070 Assume that SIZE is 4. Bigger sizes are handled analogously
24071 if (COUNT & 4)
24072 {
24073 copy 4 bytes from SRCPTR to DESTPTR
24074 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24075 goto done_label
24076 }
24077 if (!COUNT)
24078 goto done_label;
24079 copy 1 byte from SRCPTR to DESTPTR
24080 if (COUNT & 2)
24081 {
24082 copy 2 bytes from SRCPTR to DESTPTR
24083 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24084 }
24085 }
24086 else
24087 {
24088 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24089 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24091 OLD_DESPTR = DESTPTR;
24092 Align DESTPTR up to DESIRED_ALIGN
24093 SRCPTR += DESTPTR - OLD_DESTPTR
24094 COUNT -= DEST_PTR - OLD_DESTPTR
24095 if (DYNAMIC_CHECK)
24096 Round COUNT down to multiple of SIZE
24097 << optional caller supplied zero size guard is here >>
24098 << optional caller suppplied dynamic check is here >>
24099 << caller supplied main copy loop is here >>
24100 }
24101 done_label:
24102 */
24103 static void
24106 machine_mode mode,
24116 {
24119 rtx modesize;
24121 rtx mode_value;
24123 /* Chose proper value to copy. */
24126 else
24130 /* See if block is big or small, handle small blocks. */
24132 {
24143 /* Handle sizes > 3. */
24150 /* Nothing to copy? Jump to DONE_LABEL if so */
24154 /* Do a byte copy. */
24158 else
24159 {
24162 }
24164 /* Handle sizes 2 and 3. */
24171 else
24172 {
24177 }
24183 }
24184 else
24188 /* Start memcpy for COUNT >= SIZE. */
24190 {
24193 }
24195 /* Copy first desired_align bytes. */
24201 {
24204 else
24205 {
24208 }
24211 }
24214 /* Copy last SIZE bytes. */
24221 else
24222 {
24228 }
24230 {
24234 else
24235 {
24238 }
24239 }
24241 /* Align destination. */
24243 {
24247 /* Align destptr up, place it to new register. */
24256 /* See how many bytes we skipped. */
24260 /* Adjust srcptr and count. */
24266 /* We copied at most size + prolog_size. */
24269 else
24272 /* Our loops always round down the bock size, but for dispatch to library
24273 we need precise value. */
24277 }
24278 else
24279 {
24281 /* Decrease count, so we won't end up copying last word twice. */
24285 else
24289 }
24290 }
24293 /* This function is like the previous one, except here we know how many bytes
24294 need to be copied. That allows us to update alignment not only of DST, which
24295 is returned, but also of SRC, which is passed as a pointer for that
24296 reason. */
24297 static rtx
24302 {
24310 {
24314 }
24319 {
24321 {
24323 {
24326 else
24328 }
24329 else
24332 }
24333 }
24340 {
24346 {
24349 {
24353 }
24358 }
24362 }
24365 }
24367 /* Return true if ALG can be used in current context.
24368 Assume we expand memset if MEMSET is true. */
24369 static bool
24371 {
24376 /* Algorithms using the rep prefix want at least edi and ecx;
24377 additionally, memset wants eax and memcpy wants esi. Don't
24378 consider such algorithms if the user has appropriated those
24379 registers for their own purposes. */
24386 }
24388 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24389 static enum stringop_alg
24393 {
24404 /* Even if the string operation call is cold, we still might spend a lot
24405 of time processing large blocks. */
24411 else
24417 else
24420 /* See maximal size for user defined algorithm. */
24422 {
24429 }
24431 /* If expected size is not known but max size is small enough
24432 so inline version is a win, set expected size into
24433 the range. */
24438 /* If user specified the algorithm, honnor it if possible. */
24442 /* rep; movq or rep; movl is the smallest variant. */
24444 {
24449 else
24452 }
24453 /* Very tiny blocks are best handled via the loop, REP is expensive to
24454 setup. */
24458 {
24462 {
24463 /* We get here if the algorithms that were not libcall-based
24464 were rep-prefix based and we are unable to use rep prefixes
24465 based on global register usage. Break out of the loop and
24466 use the heuristic below. */
24470 {
24474 {
24477 }
24478 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24479 last non-libcall inline algorithm. */
24481 {
24482 /* When the current size is best to be copied by a libcall,
24483 but we are still forced to inline, run the heuristic below
24484 that will pick code for medium sized blocks. */
24486 {
24489 }
24492 }
24494 {
24497 }
24498 }
24499 }
24500 }
24501 /* When asked to inline the call anyway, try to pick meaningful choice.
24502 We look for maximal size of block that is faster to copy by hand and
24503 take blocks of at most of that size guessing that average size will
24504 be roughly half of the block.
24506 If this turns out to be bad, we might simply specify the preferred
24507 choice in ix86_costs. */
24511 {
24514 /* If there aren't any usable algorithms, then recursing on
24515 smaller sizes isn't going to find anything. Just return the
24516 simple byte-at-a-time copy loop. */
24518 {
24519 /* Pick something reasonable. */
24523 }
24531 else
24534 }
24537 }
24539 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24540 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24541 static int
24545 machine_mode move_mode)
24546 {
24557 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24558 copying whole cacheline at once. */
24571 }
24574 /* Helper function for memcpy. For QImode value 0xXY produce
24575 0xXYXYXYXY of wide specified by MODE. This is essentially
24576 a * 0x10101010, but we can do slightly better than
24577 synth_mult by unwinding the sequence by hand on CPUs with
24578 slow multiply. */
24579 static rtx
24581 {
24583 rtx tmp;
24590 {
24598 }
24607 nops--;
24612 {
24616 OPTAB_DIRECT);
24617 }
24618 else
24619 {
24625 else
24627 else
24628 {
24631 reg =
24633 }
24643 }
24644 }
24646 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24647 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24648 alignment from ALIGN to DESIRED_ALIGN. */
24649 static rtx
24652 {
24653 rtx promoted_val;
24662 else
24666 }
24668 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24669 operations when profitable. The code depends upon architecture, block size
24670 and alignment, but always has one of the following overall structures:
24672 Aligned move sequence:
24674 1) Prologue guard: Conditional that jumps up to epilogues for small
24675 blocks that can be handled by epilogue alone. This is faster
24676 but also needed for correctness, since prologue assume the block
24677 is larger than the desired alignment.
24679 Optional dynamic check for size and libcall for large
24680 blocks is emitted here too, with -minline-stringops-dynamically.
24682 2) Prologue: copy first few bytes in order to get destination
24683 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24684 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24685 copied. We emit either a jump tree on power of two sized
24686 blocks, or a byte loop.
24688 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24689 with specified algorithm.
24691 4) Epilogue: code copying tail of the block that is too small to be
24692 handled by main body (or up to size guarded by prologue guard).
24694 Misaligned move sequence
24696 1) missaligned move prologue/epilogue containing:
24697 a) Prologue handling small memory blocks and jumping to done_label
24698 (skipped if blocks are known to be large enough)
24699 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24700 needed by single possibly misaligned move
24701 (skipped if alignment is not needed)
24702 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24704 2) Zero size guard dispatching to done_label, if needed
24706 3) dispatch to library call, if needed,
24708 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24709 with specified algorithm. */
24710 bool
24716 {
24717 rtx destreg;
24720 rtx tmp;
24736 /* TODO: Once value ranges are available, fill in proper data. */
24744 /* i386 can do misaligned access on reasonably increased cost. */
24748 /* ALIGN is the minimum of destination and source alignment, but we care here
24749 just about destination alignment. */
24755 {
24758 /* When COUNT is 0, there is nothing to do. */
24761 }
24762 else
24763 {
24772 }
24774 /* Make sure we don't need to care about overflow later on. */
24778 /* Step 0: Decide on preferred algorithm, desired alignment and
24779 size of chunks to be copied by main loop. */
24781 issetmem,
24788 /* For now vector-version of memset is generated only for memory zeroing, as
24789 creating of promoted vector value is very cheap in this case. */
24802 {
24821 /* Find the widest supported mode. */
24827 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24828 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24830 {
24835 }
24847 }
24855 /* Step 1: Prologue guard. */
24857 /* Alignment code needs count to be in register. */
24859 {
24862 {
24863 align_bytes
24867 else
24869 }
24872 }
24875 /* Misaligned move sequences handle both prologue and epilogue at once.
24876 Default code generation results in a smaller code for large alignments
24877 and also avoids redundant job when sizes are known precisely. */
24878 misaligned_prologue_used
24879 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24885 /* Do the cheap promotion to allow better CSE across the
24886 main loop and epilogue (ie one load of the big constant in the
24887 front of all code.
24888 For now the misaligned move sequences do not have fast path
24889 without broadcasting. */
24891 {
24893 {
24899 }
24900 else
24901 {
24904 }
24905 }
24906 /* Misaligned move sequences handles both prologues and epilogues at once.
24907 Default code generation results in smaller code for large alignments and
24908 also avoids redundant job when sizes are known precisely. */
24910 {
24911 /* Misaligned move prologue handled small blocks by itself. */
24912 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24917 desired_align < align
24926 {
24927 /* It is possible that we copied enough so the main loop will not
24928 execute. */
24938 else
24940 }
24941 }
24942 /* Ensure that alignment prologue won't copy past end of block. */
24944 {
24946 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24947 Make sure it is power of 2. */
24950 /* To improve performance of small blocks, we jump around the VAL
24951 promoting mode. This mean that if the promoted VAL is not constant,
24952 we might not use it in the epilogue and have to use byte
24953 loop variant. */
24958 {
24959 /* If main algorithm works on QImode, no epilogue is needed.
24960 For small sizes just don't align anything. */
24963 else
24965 }
24968 {
24975 else
24977 }
24978 }
24980 /* Emit code to decide on runtime whether library call or inline should be
24981 used. */
24983 {
24985 {
24987 {
24991 }
24992 }
24993 else
24994 {
25004 else
25008 }
25009 }
25011 /* Step 2: Alignment prologue. */
25012 /* Do the expensive promotion once we branched off the small blocks. */
25018 {
25020 {
25021 /* Except for the first move in prologue, we no longer know
25022 constant offset in aliasing info. It don't seems to worth
25023 the pain to maintain it for the first move, so throw away
25024 the info early. */
25031 issetmem);
25032 /* At most desired_align - align bytes are copied. */
25035 else
25037 }
25038 else
25039 {
25040 /* If we know how many bytes need to be stored before dst is
25041 sufficiently aligned, maintain aliasing info accurately. */
25043 srcreg,
25044 promoted_val,
25045 vec_promoted_val,
25046 desired_align,
25047 align_bytes,
25048 issetmem);
25055 }
25057 && !min_size
25062 {
25063 /* It is possible that we copied enough so the main loop will not
25064 execute. */
25074 else
25076 }
25077 }
25079 {
25086 }
25090 /* Step 3: Main loop. */
25093 {
25116 }
25117 /* Adjust properly the offset of src and dest memory for aliasing. */
25119 {
25125 }
25126 else
25127 {
25131 }
25133 /* Step 4: Epilogue to copy the remaining bytes. */
25134 epilogue:
25136 {
25137 /* When the main loop is done, COUNT_EXP might hold original count,
25138 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25139 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25140 bytes. Compensate if needed. */
25143 {
25144 tmp =
25147 OPTAB_DIRECT);
25150 }
25153 }
25156 {
25159 epilogue_size_needed);
25160 else
25161 {
25165 epilogue_size_needed);
25166 else
25168 epilogue_size_needed);
25169 }
25170 }
25174 }
25177 /* Expand the appropriate insns for doing strlen if not just doing
25178 repnz; scasb
25180 out = result, initialized with the start address
25181 align_rtx = alignment of the address.
25182 scratch = scratch register, initialized with the startaddress when
25183 not aligned, otherwise undefined
25185 This is just the body. It needs the initializations mentioned above and
25186 some address computing at the end. These things are done in i386.md. */
25188 static void
25190 {
25192 rtx tmp;
25197 rtx mem;
25200 rtx cmp;
25206 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25208 /* Is there a known alignment and is it less than 4? */
25210 {
25213 /* Is there a known alignment and is it not 2? */
25215 {
25219 /* Leave just the 3 lower bits. */
25229 }
25230 else
25231 {
25232 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25233 check if is aligned to 4 - byte. */
25240 }
25244 /* Now compare the bytes. */
25246 /* Compare the first n unaligned byte on a byte per byte basis. */
25250 /* Increment the address. */
25253 /* Not needed with an alignment of 2 */
25255 {
25259 end_0_label);
25264 }
25267 end_0_label);
25270 }
25272 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25273 align this loop. It gives only huge programs, but does not help to
25274 speed up. */
25281 /* This formula yields a nonzero result iff one of the bytes is zero.
25282 This saves three branches inside loop and many cycles. */
25290 align_4_label);
25293 {
25299 /* If zero is not in the first two bytes, move two bytes forward. */
25305 reg,
25306 tmpreg)));
25307 /* Emit lea manually to avoid clobbering of flags. */
25315 reg2,
25316 out)));
25317 }
25318 else
25319 {
25321 /* Is zero in the first two bytes? */
25328 pc_rtx);
25332 /* Not in the first two. Move two bytes forward. */
25338 }
25340 /* Avoid branch in fixing the byte. */
25348 }
25350 /* Expand strlen. */
25352 bool
25354 {
25357 /* The generic case of strlen expander is long. Avoid it's
25358 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25361 && !TARGET_INLINE_ALL_STRINGOPS
25371 {
25372 /* Well it seems that some optimizer does not combine a call like
25373 foo(strlen(bar), strlen(bar));
25374 when the move and the subtraction is done here. It does calculate
25375 the length just once when these instructions are done inside of
25376 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25377 often used and I use one fewer register for the lifetime of
25378 output_strlen_unroll() this is better. */
25384 /* strlensi_unroll_1 returns the address of the zero at the end of
25385 the string, like memchr(), so compute the length by subtracting
25386 the start address. */
25388 }
25389 else
25390 {
25391 rtx unspec;
25393 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25406 /* If .md starts supporting :P, this can be done in .md. */
25412 }
25414 }
25416 /* For given symbol (function) construct code to compute address of it's PLT
25417 entry in large x86-64 PIC model. */
25418 static rtx
25420 {
25433 }
25435 rtx
25437 rtx callarg2,
25439 {
25449 {
25450 #if TARGET_MACHO
25453 #endif
25454 }
25455 else
25456 {
25457 /* Static functions and indirect calls don't need the pic register. */
25459 && (!TARGET_64BIT
25464 {
25468 pic_offset_table_rtx);
25469 }
25470 }
25472 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25473 parameters passed in vector registers. */
25478 {
25482 }
25485 && !TARGET_PECOFF
25493 {
25496 }
25501 {
25502 /* We should add bounds as destination register in case
25503 pointer with bounds may be returned. */
25505 {
25509 {
25514 }
25515 else
25516 {
25520 }
25521 }
25524 }
25528 {
25532 }
25536 {
25537 int const cregs_size
25542 {
25547 }
25548 }
25557 }
25559 /* Output the assembly for a call instruction. */
25563 {
25569 {
25572 /* SEH epilogue detection requires the indirect branch case
25573 to include REX.W. */
25576 else
25581 }
25583 /* SEH unwinding can require an extra nop to be emitted in several
25584 circumstances. Determine if we have one of those. */
25586 {
25590 {
25591 /* If we get to another real insn, we don't need the nop. */
25595 /* If we get to the epilogue note, prevent a catch region from
25596 being adjacent to the standard epilogue sequence. If non-
25597 call-exceptions, we'll have done this during epilogue emission. */
25599 && !flag_non_call_exceptions
25601 {
25604 }
25605 }
25607 /* If we didn't find a real insn following the call, prevent the
25608 unwinder from looking into the next function. */
25611 }
25615 else
25624 }
25625 \f
25626 /* Clear stack slot assignments remembered from previous functions.
25627 This is called from INIT_EXPANDERS once before RTL is emitted for each
25628 function. */
25632 {
25640 }
25642 /* Return a MEM corresponding to a stack slot with mode MODE.
25643 Allocate a new slot if necessary.
25645 The RTL for a function can have several slots available: N is
25646 which slot to use. */
25648 rtx
25650 {
25667 }
25669 static void
25671 {
25677 }
25678 \f
25679 /* Check whether x86 address PARTS is a pc-relative address. */
25681 static bool
25683 {
25691 {
25693 {
25710 }
25711 }
25713 }
25715 /* Calculate the length of the memory address in the instruction encoding.
25716 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25717 or other prefixes. We never generate addr32 prefix for LEA insn. */
25719 int
25721 {
25738 /* If this is not LEA instruction, add the length of addr32 prefix. */
25743 len++;
25757 /* Rule of thumb:
25758 - esp as the base always wants an index,
25759 - ebp as the base always wants a displacement,
25760 - r12 as the base always wants an index,
25761 - r13 as the base always wants a displacement. */
25763 /* Register Indirect. */
25765 {
25766 /* esp (for its index) and ebp (for its displacement) need
25767 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25768 code. */
25775 len++;
25776 }
25778 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25779 is not disp32, but disp32(%rip), so for disp32
25780 SIB byte is needed, unless print_operand_address
25781 optimizes it into disp32(%rip) or (%rip) is implied
25782 by UNSPEC. */
25784 {
25787 len++;
25788 }
25789 else
25790 {
25791 /* Find the length of the displacement constant. */
25793 {
25796 else
25798 }
25799 /* ebp always wants a displacement. Similarly r13. */
25801 len++;
25803 /* An index requires the two-byte modrm form.... */
25805 /* ...like esp (or r12), which always wants an index. */
25809 len++;
25810 }
25813 }
25815 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25816 is set, expect that insn have 8bit immediate alternative. */
25817 int
25819 {
25825 {
25830 {
25833 {
25845 }
25847 {
25850 }
25851 }
25853 {
25863 /* Immediates for DImode instructions are encoded
25864 as 32bit sign extended values. */
25870 }
25871 }
25873 }
25875 /* Compute default value for "length_address" attribute. */
25876 int
25878 {
25882 {
25893 }
25898 {
25901 {
25906 constraints++;
25909 ;
25910 /* Skip ignored operands. */
25913 }
25915 }
25917 }
25919 /* Compute default value for "length_vex" attribute. It includes
25920 2 or 3 byte VEX prefix and 1 opcode byte. */
25922 int
25925 {
25928 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25929 byte VEX prefix. */
25933 /* We can always use 2 byte VEX prefix in 32bit. */
25941 {
25942 /* REX.W bit uses 3 byte VEX prefix. */
25946 }
25947 else
25948 {
25949 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25953 }
25956 }
25957 \f
25958 /* Return the maximum number of instructions a cpu can issue. */
25960 static int
25962 {
25964 {
25996 }
25997 }
25999 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26000 by DEP_INSN and nothing set by DEP_INSN. */
26002 static bool
26004 {
26007 /* Simplify the test for uninteresting insns. */
26015 {
26018 }
26023 {
26026 }
26027 else
26033 /* This test is true if the dependent insn reads the flags but
26034 not any other potentially set register. */
26042 }
26044 /* Return true iff USE_INSN has a memory address with operands set by
26045 SET_INSN. */
26047 bool
26049 {
26054 {
26057 }
26059 }
26061 /* Helper function for exact_store_load_dependency.
26062 Return true if addr is found in insn. */
26063 static bool
26065 {
26072 {
26078 CASE_CONST_ANY:
26087 }
26091 {
26093 {
26103 }
26104 }
26106 }
26108 /* Return true if there exists exact dependency for store & load, i.e.
26109 the same memory address is used in them. */
26110 static bool
26112 {
26126 }
26128 static int
26130 {
26136 /* Anti and output dependencies have zero cost on all CPUs. */
26142 /* If we can't recognize the insns, we can't really do anything. */
26150 {
26152 /* Address Generation Interlock adds a cycle of latency. */
26154 {
26165 }
26169 /* ??? Compares pair with jump/setcc. */
26173 /* Floating point stores require value to be ready one cycle earlier. */
26181 /* INT->FP conversion is expensive. */
26185 /* There is one cycle extra latency between an FP op and a store. */
26195 /* Show ability of reorder buffer to hide latency of load by executing
26196 in parallel with previous instruction in case
26197 previous instruction is not needed to compute the address. */
26200 {
26201 /* Claim moves to take one cycle, as core can issue one load
26202 at time and the next load can start cycle later. */
26207 cost--;
26208 }
26212 /* The esp dependency is resolved before
26213 the instruction is really finished. */
26218 /* INT->FP conversion is expensive. */
26224 /* Show ability of reorder buffer to hide latency of load by executing
26225 in parallel with previous instruction in case
26226 previous instruction is not needed to compute the address. */
26229 {
26230 /* Claim moves to take one cycle, as core can issue one load
26231 at time and the next load can start cycle later. */
26237 else
26239 }
26250 /* Stack engine allows to execute push&pop instructions in parall. */
26254 /* FALLTHRU */
26260 /* Show ability of reorder buffer to hide latency of load by executing
26261 in parallel with previous instruction in case
26262 previous instruction is not needed to compute the address. */
26265 {
26269 /* Because of the difference between the length of integer and
26270 floating unit pipeline preparation stages, the memory operands
26271 for floating point are cheaper.
26273 ??? For Athlon it the difference is most probably 2. */
26276 else
26281 else
26283 }
26290 /* Stack engine allows to execute push&pop instructions in parall. */
26297 /* Show ability of reorder buffer to hide latency of load by executing
26298 in parallel with previous instruction in case
26299 previous instruction is not needed to compute the address. */
26302 {
26305 else
26307 }
26316 /* Increase cost of integer loads. */
26319 {
26322 {
26325 else
26326 {
26327 /* Increase cost of ld/st for short int types only
26328 because of store forwarding issue. */
26332 {
26333 /* Increase cost of store/load insn if exact
26334 dependence exists and it is load insn. */
26339 }
26340 }
26341 }
26342 }
26346 }
26349 }
26351 /* How many alternative schedules to try. This should be as wide as the
26352 scheduling freedom in the DFA, but no wider. Making this value too
26353 large results extra work for the scheduler. */
26355 static int
26357 {
26359 {
26371 /* We use lookahead value 4 for BD both before and after reload
26372 schedules. Plan is to have value 8 included for O3. */
26383 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26384 as many instructions can be executed on a cycle, i.e.,
26385 issue_rate. I wonder why tuning for many CPUs does not do this. */
26388 /* Don't use lookahead for pre-reload schedule to save compile time. */
26393 }
26394 }
26396 /* Return true if target platform supports macro-fusion. */
26398 static bool
26400 {
26402 }
26404 /* Check whether current microarchitecture support macro fusion
26405 for insn pair "CONDGEN + CONDJMP". Refer to
26406 "Intel Architectures Optimization Reference Manual". */
26408 static bool
26410 {
26431 {
26436 {
26440 else
26442 }
26443 }
26450 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26451 supported. */
26458 /* No fusion for RIP-relative address. */
26465 ix86_address parts;
26471 }
26476 /* Check whether conditional jump use Sign or Overflow Flags. */
26484 /* Return true for TYPE_TEST and TYPE_ICMP. */
26489 /* The following is the case that macro-fusion for alu + jmp. */
26493 /* No fusion for alu op with memory destination operand. */
26498 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26499 supported. */
26508 }
26510 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26511 execution. It is applied if
26512 (1) IMUL instruction is on the top of list;
26513 (2) There exists the only producer of independent IMUL instruction in
26514 ready list.
26515 Return index of IMUL producer if it was found and -1 otherwise. */
26516 static int
26518 {
26521 sd_iterator_def sd_it;
26522 dep_t dep;
26529 /* Check that IMUL instruction is on the top of ready list. */
26538 /* Search for producer of independent IMUL instruction. */
26540 {
26544 /* Skip IMUL instruction. */
26554 {
26555 rtx con;
26566 {
26567 sd_iterator_def sd_it1;
26568 dep_t dep1;
26569 /* Check if there is no other dependee for IMUL. */
26572 {
26573 rtx pro;
26579 }
26582 }
26583 }
26586 }
26588 }
26590 /* Try to find the best candidate on the top of ready list if two insns
26591 have the same priority - candidate is best if its dependees were
26592 scheduled earlier. Applied for Silvermont only.
26593 Return true if top 2 insns must be interchanged. */
26594 static bool
26596 {
26599 rtx set;
26600 sd_iterator_def sd_it;
26601 dep_t dep;
26604 #define INSN_TICK(INSN) (HID (INSN)->tick)
26625 {
26628 /* Determine winner more precise. */
26630 {
26631 rtx pro;
26637 }
26639 {
26640 rtx pro;
26646 }
26649 {
26650 /* Determine winner - load must win. */
26656 }
26658 }
26660 #undef INSN_TICK
26661 }
26663 /* Perform possible reodering of ready list for Atom/Silvermont only.
26664 Return issue rate. */
26665 static int
26668 {
26675 /* Set up issue rate. */
26678 /* Do reodering for BONNELL/SILVERMONT only. */
26682 /* Nothing to do if ready list contains only 1 instruction. */
26686 /* Do reodering for post-reload scheduler only. */
26691 {
26696 /* Put IMUL producer (ready[index]) at the top of ready list. */
26702 }
26704 /* Skip selective scheduling since HID is not populated in it. */
26708 {
26712 /* Swap 2 top elements of ready list. */
26716 }
26718 }
26720 static bool
26723 /* Returns true if lhs of insn is HW function argument register and set up
26724 is_spilled to true if it is likely spilled HW register. */
26725 static bool
26727 {
26728 rtx dst;
26732 /* Call instructions are not movable, ignore it. */
26743 {
26744 /* Is it likely spilled HW register? */
26749 }
26751 }
26753 /* Add output dependencies for chain of function adjacent arguments if only
26754 there is a move to likely spilled HW register. Return first argument
26755 if at least one dependence was added or NULL otherwise. */
26758 {
26766 /* Find nearest to call argument passing instruction. */
26768 {
26777 }
26781 {
26788 {
26791 }
26793 {
26794 /* Add output depdendence between two function arguments if chain
26795 of output arguments contains likely spilled HW registers. */
26799 }
26800 else
26802 }
26806 }
26808 /* Add output or anti dependency from insn to first_arg to restrict its code
26809 motion. */
26810 static void
26812 {
26813 rtx set;
26814 rtx tmp;
26816 /* Add anti dependencies for bounds stores. */
26821 {
26824 }
26831 {
26832 /* Add output dependency to the first function argument. */
26835 }
26836 /* Add anti dependency. */
26838 }
26840 /* Avoid cross block motion of function argument through adding dependency
26841 from the first non-jump instruction in bb. */
26842 static void
26844 {
26848 {
26850 {
26853 {
26856 }
26857 }
26861 }
26862 }
26864 /* Hook for pre-reload schedule - avoid motion of function arguments
26865 passed in likely spilled HW registers. */
26866 static void
26868 {
26877 {
26880 {
26881 /* Add dependee for first argument to predecessors if only
26882 region contains more than one block. */
26886 /* Skip trivial regions and region head blocks that can have
26887 predecessors outside of region. */
26889 {
26890 edge e;
26891 edge_iterator ei;
26893 /* Regions are SCCs with the exception of selective
26894 scheduling with pipelining of outer blocks enabled.
26895 So also check that immediate predecessors of a non-head
26896 block are in the same region. */
26898 {
26899 /* Avoid creating of loop-carried dependencies through
26900 using topological ordering in the region. */
26904 }
26905 }
26909 }
26910 }
26913 }
26915 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26916 HW registers to maximum, to schedule them at soon as possible. These are
26917 moves from function argument registers at the top of the function entry
26918 and moves from function return value registers after call. */
26919 static int
26921 {
26922 rtx set;
26932 {
26939 }
26942 }
26944 /* Model decoder of Core 2/i7.
26945 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26946 track the instruction fetch block boundaries and make sure that long
26947 (9+ bytes) instructions are assigned to D0. */
26949 /* Maximum length of an insn that can be handled by
26950 a secondary decoder unit. '8' for Core 2/i7. */
26953 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26954 '16' for Core 2/i7. */
26957 /* Maximum number of instructions decoder can handle per cycle.
26958 '6' for Core 2/i7. */
26962 ix86_first_cycle_multipass_data_t;
26964 const_ix86_first_cycle_multipass_data_t;
26966 /* A variable to store target state across calls to max_issue within
26967 one cycle. */
26971 /* Initialize DATA. */
26972 static void
26974 {
26975 ix86_first_cycle_multipass_data_t data
26982 }
26984 /* Advancing the cycle; reset ifetch block counts. */
26985 static void
26987 {
26994 }
26998 /* Filter out insns from ready_try that the core will not be able to issue
26999 on current cycle due to decoder. */
27000 static void
27001 core2i7_first_cycle_multipass_filter_ready_try
27004 {
27006 {
27017 (!first_cycle_insn_p
27019 /* ... or it would not fit into the ifetch block ... */
27021 /* ... or the decoder is full already ... */
27023 /* ... mask the insn out. */
27024 {
27029 }
27030 }
27031 }
27033 /* Prepare for a new round of multipass lookahead scheduling. */
27034 static void
27038 {
27039 ix86_first_cycle_multipass_data_t data
27041 const_ix86_first_cycle_multipass_data_t prev_data
27044 /* Restore the state from the end of the previous round. */
27048 /* Filter instructions that cannot be issued on current cycle due to
27049 decoder restrictions. */
27051 first_cycle_insn_p);
27052 }
27054 /* INSN is being issued in current solution. Account for its impact on
27055 the decoder model. */
27056 static void
27060 {
27061 ix86_first_cycle_multipass_data_t data
27063 const_ix86_first_cycle_multipass_data_t prev_data
27073 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27075 {
27078 }
27080 {
27084 }
27087 /* Filter out insns from ready_try that the core will not be able to issue
27088 on current cycle due to decoder. */
27091 }
27093 /* Revert the effect on ready_try. */
27094 static void
27098 {
27099 const_ix86_first_cycle_multipass_data_t data
27102 sbitmap_iterator sbi;
27106 {
27108 }
27109 }
27111 /* Save the result of multipass lookahead scheduling for the next round. */
27112 static void
27114 {
27115 const_ix86_first_cycle_multipass_data_t data
27117 ix86_first_cycle_multipass_data_t next_data
27121 {
27124 }
27125 }
27127 /* Deallocate target data. */
27128 static void
27130 {
27131 ix86_first_cycle_multipass_data_t data
27135 {
27139 }
27140 }
27142 /* Prepare for scheduling pass. */
27143 static void
27145 {
27146 /* Install scheduling hooks for current CPU. Some of these hooks are used
27147 in time-critical parts of the scheduler, so we only set them up when
27148 they are actually used. */
27150 {
27155 /* Do not perform multipass scheduling for pre-reload schedule
27156 to save compile time. */
27158 {
27174 /* Set decoder parameters. */
27179 }
27180 /* ... Fall through ... */
27190 }
27191 }
27193 \f
27194 /* Compute the alignment given to a constant that is being placed in memory.
27195 EXP is the constant and ALIGN is the alignment that the object would
27196 ordinarily have.
27197 The value of this function is used instead of that alignment to align
27198 the object. */
27200 int
27202 {
27205 {
27210 }
27216 }
27218 /* Compute the alignment for a static variable.
27219 TYPE is the data type, and ALIGN is the alignment that
27220 the object would ordinarily have. The value of this function is used
27221 instead of that alignment to align the object. */
27223 int
27225 {
27226 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27227 for symbols from other compilation units or symbols that don't need
27228 to bind locally. In order to preserve some ABI compatibility with
27229 those compilers, ensure we don't decrease alignment from what we
27230 used to assume. */
27234 /* A data structure, equal or greater than the size of a cache line
27235 (64 bytes in the Pentium 4 and other recent Intel processors, including
27236 processors based on Intel Core microarchitecture) should be aligned
27237 so that its base address is a multiple of a cache line size. */
27239 int max_align
27246 {
27250 }
27256 {
27263 }
27265 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27266 to 16byte boundary. */
27268 {
27275 }
27281 {
27286 }
27288 {
27295 }
27300 {
27305 }
27308 {
27313 }
27316 }
27318 /* Compute the alignment for a local variable or a stack slot. EXP is
27319 the data type or decl itself, MODE is the widest mode available and
27320 ALIGN is the alignment that the object would ordinarily have. The
27321 value of this macro is used instead of that alignment to align the
27322 object. */
27324 unsigned int
27327 {
27331 {
27334 }
27335 else
27336 {
27339 }
27341 /* Don't do dynamic stack realignment for long long objects with
27342 -mpreferred-stack-boundary=2. */
27351 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27352 register in MODE. We will return the largest alignment of XF
27353 and DF. */
27355 {
27359 }
27361 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27362 to 16byte boundary. Exact wording is:
27364 An array uses the same alignment as its elements, except that a local or
27365 global array variable of length at least 16 bytes or
27366 a C99 variable-length array variable always has alignment of at least 16 bytes.
27368 This was added to allow use of aligned SSE instructions at arrays. This
27369 rule is meant for static storage (where compiler can not do the analysis
27370 by itself). We follow it for automatic variables only when convenient.
27371 We fully control everything in the function compiled and functions from
27372 other unit can not rely on the alignment.
27374 Exclude va_list type. It is the common case of local array where
27375 we can not benefit from the alignment.
27377 TODO: Probably one should optimize for size only when var is not escaping. */
27380 {
27390 }
27392 {
27397 }
27399 {
27405 }
27410 {
27415 }
27418 {
27424 }
27426 }
27428 /* Compute the minimum required alignment for dynamic stack realignment
27429 purposes for a local variable, parameter or a stack slot. EXP is
27430 the data type or decl itself, MODE is its mode and ALIGN is the
27431 alignment that the object would ordinarily have. */
27433 unsigned int
27436 {
27440 {
27443 }
27444 else
27445 {
27448 }
27453 /* Don't do dynamic stack realignment for long long objects with
27454 -mpreferred-stack-boundary=2. */
27461 }
27462 \f
27463 /* Find a location for the static chain incoming to a nested function.
27464 This is a register, unless all free registers are used by arguments. */
27466 static rtx
27468 {
27471 /* While this function won't be called by the middle-end when a static
27472 chain isn't needed, it's also used throughout the backend so it's
27473 easiest to keep this check centralized. */
27478 {
27479 /* We always use R10 in 64-bit mode. */
27481 }
27482 else
27483 {
27487 /* By default in 32-bit mode we use ECX to pass the static chain. */
27491 {
27494 }
27495 else
27496 {
27499 }
27503 {
27504 /* Fastcall functions use ecx/edx for arguments, which leaves
27505 us with EAX for the static chain.
27506 Thiscall functions use ecx for arguments, which also
27507 leaves us with EAX for the static chain. */
27509 }
27511 {
27512 /* Thiscall functions use ecx for arguments, which leaves
27513 us with EAX and EDX for the static chain.
27514 We are using for abi-compatibility EAX. */
27516 }
27518 {
27519 /* For regparm 3, we have no free call-clobbered registers in
27520 which to store the static chain. In order to implement this,
27521 we have the trampoline push the static chain to the stack.
27522 However, we can't push a value below the return address when
27523 we call the nested function directly, so we have to use an
27524 alternate entry point. For this we use ESI, and have the
27525 alternate entry point push ESI, so that things appear the
27526 same once we're executing the nested function. */
27528 {
27534 }
27536 }
27537 }
27540 }
27542 /* Emit RTL insns to initialize the variable parts of a trampoline.
27543 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27544 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27545 to be passed to the target function. */
27547 static void
27549 {
27557 {
27560 /* Load the function address to r11. Try to load address using
27561 the shorter movl instead of movabs. We may want to support
27562 movq for kernel mode, but kernel does not use trampolines at
27563 the moment. FNADDR is a 32bit address and may not be in
27564 DImode when ptr_mode == SImode. Always use movl in this
27565 case. */
27568 {
27577 }
27578 else
27579 {
27586 }
27588 /* Load static chain using movabs to r10. Use the shorter movl
27589 instead of movabs when ptr_mode == SImode. */
27591 {
27594 }
27595 else
27596 {
27599 }
27608 /* Jump to r11; the last (unused) byte is a nop, only there to
27609 pad the write out to a single 32-bit store. */
27613 }
27614 else
27615 {
27618 /* Depending on the static chain location, either load a register
27619 with a constant, or push the constant to the stack. All of the
27620 instructions are the same size. */
27623 {
27625 {
27632 }
27633 }
27634 else
27649 /* Compute offset from the end of the jmp to the target function.
27650 In the case in which the trampoline stores the static chain on
27651 the stack, we need to skip the first insn which pushes the
27652 (call-saved) register static chain; this push is 1 byte. */
27659 }
27663 #ifdef HAVE_ENABLE_EXECUTE_STACK
27664 #ifdef CHECK_EXECUTE_STACK_ENABLED
27666 #endif
27669 #endif
27670 }
27671 \f
27672 /* The following file contains several enumerations and data structures
27673 built from the definitions in i386-builtin-types.def. */
27677 /* Table for the ix86 builtin non-function types. */
27680 /* Retrieve an element from the above table, building some of
27681 the types lazily. */
27683 static tree
27685 {
27697 {
27698 machine_mode mode;
27705 }
27706 else
27707 {
27713 else
27721 }
27725 }
27727 /* Table for the ix86 builtin function types. */
27730 /* Retrieve an element from the above table, building some of
27731 the types lazily. */
27733 static tree
27735 {
27736 tree type;
27745 {
27753 {
27756 }
27759 }
27760 else
27761 {
27767 }
27771 }
27774 /* Codes for all the SSE/MMX builtins. */
27775 enum ix86_builtins
27776 {
27777 IX86_BUILTIN_ADDPS,
27778 IX86_BUILTIN_ADDSS,
27779 IX86_BUILTIN_DIVPS,
27780 IX86_BUILTIN_DIVSS,
27781 IX86_BUILTIN_MULPS,
27782 IX86_BUILTIN_MULSS,
27783 IX86_BUILTIN_SUBPS,
27784 IX86_BUILTIN_SUBSS,
27786 IX86_BUILTIN_CMPEQPS,
27787 IX86_BUILTIN_CMPLTPS,
27788 IX86_BUILTIN_CMPLEPS,
27789 IX86_BUILTIN_CMPGTPS,
27790 IX86_BUILTIN_CMPGEPS,
27791 IX86_BUILTIN_CMPNEQPS,
27792 IX86_BUILTIN_CMPNLTPS,
27793 IX86_BUILTIN_CMPNLEPS,
27794 IX86_BUILTIN_CMPNGTPS,
27795 IX86_BUILTIN_CMPNGEPS,
27796 IX86_BUILTIN_CMPORDPS,
27797 IX86_BUILTIN_CMPUNORDPS,
27798 IX86_BUILTIN_CMPEQSS,
27799 IX86_BUILTIN_CMPLTSS,
27800 IX86_BUILTIN_CMPLESS,
27801 IX86_BUILTIN_CMPNEQSS,
27802 IX86_BUILTIN_CMPNLTSS,
27803 IX86_BUILTIN_CMPNLESS,
27804 IX86_BUILTIN_CMPORDSS,
27805 IX86_BUILTIN_CMPUNORDSS,
27807 IX86_BUILTIN_COMIEQSS,
27808 IX86_BUILTIN_COMILTSS,
27809 IX86_BUILTIN_COMILESS,
27810 IX86_BUILTIN_COMIGTSS,
27811 IX86_BUILTIN_COMIGESS,
27812 IX86_BUILTIN_COMINEQSS,
27813 IX86_BUILTIN_UCOMIEQSS,
27814 IX86_BUILTIN_UCOMILTSS,
27815 IX86_BUILTIN_UCOMILESS,
27816 IX86_BUILTIN_UCOMIGTSS,
27817 IX86_BUILTIN_UCOMIGESS,
27818 IX86_BUILTIN_UCOMINEQSS,
27820 IX86_BUILTIN_CVTPI2PS,
27821 IX86_BUILTIN_CVTPS2PI,
27822 IX86_BUILTIN_CVTSI2SS,
27823 IX86_BUILTIN_CVTSI642SS,
27824 IX86_BUILTIN_CVTSS2SI,
27825 IX86_BUILTIN_CVTSS2SI64,
27826 IX86_BUILTIN_CVTTPS2PI,
27827 IX86_BUILTIN_CVTTSS2SI,
27828 IX86_BUILTIN_CVTTSS2SI64,
27830 IX86_BUILTIN_MAXPS,
27831 IX86_BUILTIN_MAXSS,
27832 IX86_BUILTIN_MINPS,
27833 IX86_BUILTIN_MINSS,
27835 IX86_BUILTIN_LOADUPS,
27836 IX86_BUILTIN_STOREUPS,
27837 IX86_BUILTIN_MOVSS,
27839 IX86_BUILTIN_MOVHLPS,
27840 IX86_BUILTIN_MOVLHPS,
27841 IX86_BUILTIN_LOADHPS,
27842 IX86_BUILTIN_LOADLPS,
27843 IX86_BUILTIN_STOREHPS,
27844 IX86_BUILTIN_STORELPS,
27846 IX86_BUILTIN_MASKMOVQ,
27847 IX86_BUILTIN_MOVMSKPS,
27848 IX86_BUILTIN_PMOVMSKB,
27850 IX86_BUILTIN_MOVNTPS,
27851 IX86_BUILTIN_MOVNTQ,
27853 IX86_BUILTIN_LOADDQU,
27854 IX86_BUILTIN_STOREDQU,
27856 IX86_BUILTIN_PACKSSWB,
27857 IX86_BUILTIN_PACKSSDW,
27858 IX86_BUILTIN_PACKUSWB,
27860 IX86_BUILTIN_PADDB,
27861 IX86_BUILTIN_PADDW,
27862 IX86_BUILTIN_PADDD,
27863 IX86_BUILTIN_PADDQ,
27864 IX86_BUILTIN_PADDSB,
27865 IX86_BUILTIN_PADDSW,
27866 IX86_BUILTIN_PADDUSB,
27867 IX86_BUILTIN_PADDUSW,
27868 IX86_BUILTIN_PSUBB,
27869 IX86_BUILTIN_PSUBW,
27870 IX86_BUILTIN_PSUBD,
27871 IX86_BUILTIN_PSUBQ,
27872 IX86_BUILTIN_PSUBSB,
27873 IX86_BUILTIN_PSUBSW,
27874 IX86_BUILTIN_PSUBUSB,
27875 IX86_BUILTIN_PSUBUSW,
27877 IX86_BUILTIN_PAND,
27878 IX86_BUILTIN_PANDN,
27879 IX86_BUILTIN_POR,
27880 IX86_BUILTIN_PXOR,
27882 IX86_BUILTIN_PAVGB,
27883 IX86_BUILTIN_PAVGW,
27885 IX86_BUILTIN_PCMPEQB,
27886 IX86_BUILTIN_PCMPEQW,
27887 IX86_BUILTIN_PCMPEQD,
27888 IX86_BUILTIN_PCMPGTB,
27889 IX86_BUILTIN_PCMPGTW,
27890 IX86_BUILTIN_PCMPGTD,
27892 IX86_BUILTIN_PMADDWD,
27894 IX86_BUILTIN_PMAXSW,
27895 IX86_BUILTIN_PMAXUB,
27896 IX86_BUILTIN_PMINSW,
27897 IX86_BUILTIN_PMINUB,
27899 IX86_BUILTIN_PMULHUW,
27900 IX86_BUILTIN_PMULHW,
27901 IX86_BUILTIN_PMULLW,
27903 IX86_BUILTIN_PSADBW,
27904 IX86_BUILTIN_PSHUFW,
27906 IX86_BUILTIN_PSLLW,
27907 IX86_BUILTIN_PSLLD,
27908 IX86_BUILTIN_PSLLQ,
27909 IX86_BUILTIN_PSRAW,
27910 IX86_BUILTIN_PSRAD,
27911 IX86_BUILTIN_PSRLW,
27912 IX86_BUILTIN_PSRLD,
27913 IX86_BUILTIN_PSRLQ,
27914 IX86_BUILTIN_PSLLWI,
27915 IX86_BUILTIN_PSLLDI,
27916 IX86_BUILTIN_PSLLQI,
27917 IX86_BUILTIN_PSRAWI,
27918 IX86_BUILTIN_PSRADI,
27919 IX86_BUILTIN_PSRLWI,
27920 IX86_BUILTIN_PSRLDI,
27921 IX86_BUILTIN_PSRLQI,
27923 IX86_BUILTIN_PUNPCKHBW,
27924 IX86_BUILTIN_PUNPCKHWD,
27925 IX86_BUILTIN_PUNPCKHDQ,
27926 IX86_BUILTIN_PUNPCKLBW,
27927 IX86_BUILTIN_PUNPCKLWD,
27928 IX86_BUILTIN_PUNPCKLDQ,
27930 IX86_BUILTIN_SHUFPS,
27932 IX86_BUILTIN_RCPPS,
27933 IX86_BUILTIN_RCPSS,
27934 IX86_BUILTIN_RSQRTPS,
27935 IX86_BUILTIN_RSQRTPS_NR,
27936 IX86_BUILTIN_RSQRTSS,
27937 IX86_BUILTIN_RSQRTF,
27938 IX86_BUILTIN_SQRTPS,
27939 IX86_BUILTIN_SQRTPS_NR,
27940 IX86_BUILTIN_SQRTSS,
27942 IX86_BUILTIN_UNPCKHPS,
27943 IX86_BUILTIN_UNPCKLPS,
27945 IX86_BUILTIN_ANDPS,
27946 IX86_BUILTIN_ANDNPS,
27947 IX86_BUILTIN_ORPS,
27948 IX86_BUILTIN_XORPS,
27950 IX86_BUILTIN_EMMS,
27951 IX86_BUILTIN_LDMXCSR,
27952 IX86_BUILTIN_STMXCSR,
27953 IX86_BUILTIN_SFENCE,
27955 IX86_BUILTIN_FXSAVE,
27956 IX86_BUILTIN_FXRSTOR,
27957 IX86_BUILTIN_FXSAVE64,
27958 IX86_BUILTIN_FXRSTOR64,
27960 IX86_BUILTIN_XSAVE,
27961 IX86_BUILTIN_XRSTOR,
27962 IX86_BUILTIN_XSAVE64,
27963 IX86_BUILTIN_XRSTOR64,
27965 IX86_BUILTIN_XSAVEOPT,
27966 IX86_BUILTIN_XSAVEOPT64,
27968 IX86_BUILTIN_XSAVEC,
27969 IX86_BUILTIN_XSAVEC64,
27971 IX86_BUILTIN_XSAVES,
27972 IX86_BUILTIN_XRSTORS,
27973 IX86_BUILTIN_XSAVES64,
27974 IX86_BUILTIN_XRSTORS64,
27976 /* 3DNow! Original */
27977 IX86_BUILTIN_FEMMS,
27978 IX86_BUILTIN_PAVGUSB,
27979 IX86_BUILTIN_PF2ID,
27980 IX86_BUILTIN_PFACC,
27981 IX86_BUILTIN_PFADD,
27982 IX86_BUILTIN_PFCMPEQ,
27983 IX86_BUILTIN_PFCMPGE,
27984 IX86_BUILTIN_PFCMPGT,
27985 IX86_BUILTIN_PFMAX,
27986 IX86_BUILTIN_PFMIN,
27987 IX86_BUILTIN_PFMUL,
27988 IX86_BUILTIN_PFRCP,
27989 IX86_BUILTIN_PFRCPIT1,
27990 IX86_BUILTIN_PFRCPIT2,
27991 IX86_BUILTIN_PFRSQIT1,
27992 IX86_BUILTIN_PFRSQRT,
27993 IX86_BUILTIN_PFSUB,
27994 IX86_BUILTIN_PFSUBR,
27995 IX86_BUILTIN_PI2FD,
27996 IX86_BUILTIN_PMULHRW,
27998 /* 3DNow! Athlon Extensions */
27999 IX86_BUILTIN_PF2IW,
28000 IX86_BUILTIN_PFNACC,
28001 IX86_BUILTIN_PFPNACC,
28002 IX86_BUILTIN_PI2FW,
28003 IX86_BUILTIN_PSWAPDSI,
28004 IX86_BUILTIN_PSWAPDSF,
28006 /* SSE2 */
28007 IX86_BUILTIN_ADDPD,
28008 IX86_BUILTIN_ADDSD,
28009 IX86_BUILTIN_DIVPD,
28010 IX86_BUILTIN_DIVSD,
28011 IX86_BUILTIN_MULPD,
28012 IX86_BUILTIN_MULSD,
28013 IX86_BUILTIN_SUBPD,
28014 IX86_BUILTIN_SUBSD,
28016 IX86_BUILTIN_CMPEQPD,
28017 IX86_BUILTIN_CMPLTPD,
28018 IX86_BUILTIN_CMPLEPD,
28019 IX86_BUILTIN_CMPGTPD,
28020 IX86_BUILTIN_CMPGEPD,
28021 IX86_BUILTIN_CMPNEQPD,
28022 IX86_BUILTIN_CMPNLTPD,
28023 IX86_BUILTIN_CMPNLEPD,
28024 IX86_BUILTIN_CMPNGTPD,
28025 IX86_BUILTIN_CMPNGEPD,
28026 IX86_BUILTIN_CMPORDPD,
28027 IX86_BUILTIN_CMPUNORDPD,
28028 IX86_BUILTIN_CMPEQSD,
28029 IX86_BUILTIN_CMPLTSD,
28030 IX86_BUILTIN_CMPLESD,
28031 IX86_BUILTIN_CMPNEQSD,
28032 IX86_BUILTIN_CMPNLTSD,
28033 IX86_BUILTIN_CMPNLESD,
28034 IX86_BUILTIN_CMPORDSD,
28035 IX86_BUILTIN_CMPUNORDSD,
28037 IX86_BUILTIN_COMIEQSD,
28038 IX86_BUILTIN_COMILTSD,
28039 IX86_BUILTIN_COMILESD,
28040 IX86_BUILTIN_COMIGTSD,
28041 IX86_BUILTIN_COMIGESD,
28042 IX86_BUILTIN_COMINEQSD,
28043 IX86_BUILTIN_UCOMIEQSD,
28044 IX86_BUILTIN_UCOMILTSD,
28045 IX86_BUILTIN_UCOMILESD,
28046 IX86_BUILTIN_UCOMIGTSD,
28047 IX86_BUILTIN_UCOMIGESD,
28048 IX86_BUILTIN_UCOMINEQSD,
28050 IX86_BUILTIN_MAXPD,
28051 IX86_BUILTIN_MAXSD,
28052 IX86_BUILTIN_MINPD,
28053 IX86_BUILTIN_MINSD,
28055 IX86_BUILTIN_ANDPD,
28056 IX86_BUILTIN_ANDNPD,
28057 IX86_BUILTIN_ORPD,
28058 IX86_BUILTIN_XORPD,
28060 IX86_BUILTIN_SQRTPD,
28061 IX86_BUILTIN_SQRTSD,
28063 IX86_BUILTIN_UNPCKHPD,
28064 IX86_BUILTIN_UNPCKLPD,
28066 IX86_BUILTIN_SHUFPD,
28068 IX86_BUILTIN_LOADUPD,
28069 IX86_BUILTIN_STOREUPD,
28070 IX86_BUILTIN_MOVSD,
28072 IX86_BUILTIN_LOADHPD,
28073 IX86_BUILTIN_LOADLPD,
28075 IX86_BUILTIN_CVTDQ2PD,
28076 IX86_BUILTIN_CVTDQ2PS,
28078 IX86_BUILTIN_CVTPD2DQ,
28079 IX86_BUILTIN_CVTPD2PI,
28080 IX86_BUILTIN_CVTPD2PS,
28081 IX86_BUILTIN_CVTTPD2DQ,
28082 IX86_BUILTIN_CVTTPD2PI,
28084 IX86_BUILTIN_CVTPI2PD,
28085 IX86_BUILTIN_CVTSI2SD,
28086 IX86_BUILTIN_CVTSI642SD,
28088 IX86_BUILTIN_CVTSD2SI,
28089 IX86_BUILTIN_CVTSD2SI64,
28090 IX86_BUILTIN_CVTSD2SS,
28091 IX86_BUILTIN_CVTSS2SD,
28092 IX86_BUILTIN_CVTTSD2SI,
28093 IX86_BUILTIN_CVTTSD2SI64,
28095 IX86_BUILTIN_CVTPS2DQ,
28096 IX86_BUILTIN_CVTPS2PD,
28097 IX86_BUILTIN_CVTTPS2DQ,
28099 IX86_BUILTIN_MOVNTI,
28100 IX86_BUILTIN_MOVNTI64,
28101 IX86_BUILTIN_MOVNTPD,
28102 IX86_BUILTIN_MOVNTDQ,
28104 IX86_BUILTIN_MOVQ128,
28106 /* SSE2 MMX */
28107 IX86_BUILTIN_MASKMOVDQU,
28108 IX86_BUILTIN_MOVMSKPD,
28109 IX86_BUILTIN_PMOVMSKB128,
28111 IX86_BUILTIN_PACKSSWB128,
28112 IX86_BUILTIN_PACKSSDW128,
28113 IX86_BUILTIN_PACKUSWB128,
28115 IX86_BUILTIN_PADDB128,
28116 IX86_BUILTIN_PADDW128,
28117 IX86_BUILTIN_PADDD128,
28118 IX86_BUILTIN_PADDQ128,
28119 IX86_BUILTIN_PADDSB128,
28120 IX86_BUILTIN_PADDSW128,
28121 IX86_BUILTIN_PADDUSB128,
28122 IX86_BUILTIN_PADDUSW128,
28123 IX86_BUILTIN_PSUBB128,
28124 IX86_BUILTIN_PSUBW128,
28125 IX86_BUILTIN_PSUBD128,
28126 IX86_BUILTIN_PSUBQ128,
28127 IX86_BUILTIN_PSUBSB128,
28128 IX86_BUILTIN_PSUBSW128,
28129 IX86_BUILTIN_PSUBUSB128,
28130 IX86_BUILTIN_PSUBUSW128,
28132 IX86_BUILTIN_PAND128,
28133 IX86_BUILTIN_PANDN128,
28134 IX86_BUILTIN_POR128,
28135 IX86_BUILTIN_PXOR128,
28137 IX86_BUILTIN_PAVGB128,
28138 IX86_BUILTIN_PAVGW128,
28140 IX86_BUILTIN_PCMPEQB128,
28141 IX86_BUILTIN_PCMPEQW128,
28142 IX86_BUILTIN_PCMPEQD128,
28143 IX86_BUILTIN_PCMPGTB128,
28144 IX86_BUILTIN_PCMPGTW128,
28145 IX86_BUILTIN_PCMPGTD128,
28147 IX86_BUILTIN_PMADDWD128,
28149 IX86_BUILTIN_PMAXSW128,
28150 IX86_BUILTIN_PMAXUB128,
28151 IX86_BUILTIN_PMINSW128,
28152 IX86_BUILTIN_PMINUB128,
28154 IX86_BUILTIN_PMULUDQ,
28155 IX86_BUILTIN_PMULUDQ128,
28156 IX86_BUILTIN_PMULHUW128,
28157 IX86_BUILTIN_PMULHW128,
28158 IX86_BUILTIN_PMULLW128,
28160 IX86_BUILTIN_PSADBW128,
28161 IX86_BUILTIN_PSHUFHW,
28162 IX86_BUILTIN_PSHUFLW,
28163 IX86_BUILTIN_PSHUFD,
28165 IX86_BUILTIN_PSLLDQI128,
28166 IX86_BUILTIN_PSLLWI128,
28167 IX86_BUILTIN_PSLLDI128,
28168 IX86_BUILTIN_PSLLQI128,
28169 IX86_BUILTIN_PSRAWI128,
28170 IX86_BUILTIN_PSRADI128,
28171 IX86_BUILTIN_PSRLDQI128,
28172 IX86_BUILTIN_PSRLWI128,
28173 IX86_BUILTIN_PSRLDI128,
28174 IX86_BUILTIN_PSRLQI128,
28176 IX86_BUILTIN_PSLLDQ128,
28177 IX86_BUILTIN_PSLLW128,
28178 IX86_BUILTIN_PSLLD128,
28179 IX86_BUILTIN_PSLLQ128,
28180 IX86_BUILTIN_PSRAW128,
28181 IX86_BUILTIN_PSRAD128,
28182 IX86_BUILTIN_PSRLW128,
28183 IX86_BUILTIN_PSRLD128,
28184 IX86_BUILTIN_PSRLQ128,
28186 IX86_BUILTIN_PUNPCKHBW128,
28187 IX86_BUILTIN_PUNPCKHWD128,
28188 IX86_BUILTIN_PUNPCKHDQ128,
28189 IX86_BUILTIN_PUNPCKHQDQ128,
28190 IX86_BUILTIN_PUNPCKLBW128,
28191 IX86_BUILTIN_PUNPCKLWD128,
28192 IX86_BUILTIN_PUNPCKLDQ128,
28193 IX86_BUILTIN_PUNPCKLQDQ128,
28195 IX86_BUILTIN_CLFLUSH,
28196 IX86_BUILTIN_MFENCE,
28197 IX86_BUILTIN_LFENCE,
28198 IX86_BUILTIN_PAUSE,
28200 IX86_BUILTIN_FNSTENV,
28201 IX86_BUILTIN_FLDENV,
28202 IX86_BUILTIN_FNSTSW,
28203 IX86_BUILTIN_FNCLEX,
28205 IX86_BUILTIN_BSRSI,
28206 IX86_BUILTIN_BSRDI,
28207 IX86_BUILTIN_RDPMC,
28208 IX86_BUILTIN_RDTSC,
28209 IX86_BUILTIN_RDTSCP,
28210 IX86_BUILTIN_ROLQI,
28211 IX86_BUILTIN_ROLHI,
28212 IX86_BUILTIN_RORQI,
28213 IX86_BUILTIN_RORHI,
28215 /* SSE3. */
28216 IX86_BUILTIN_ADDSUBPS,
28217 IX86_BUILTIN_HADDPS,
28218 IX86_BUILTIN_HSUBPS,
28219 IX86_BUILTIN_MOVSHDUP,
28220 IX86_BUILTIN_MOVSLDUP,
28221 IX86_BUILTIN_ADDSUBPD,
28222 IX86_BUILTIN_HADDPD,
28223 IX86_BUILTIN_HSUBPD,
28224 IX86_BUILTIN_LDDQU,
28226 IX86_BUILTIN_MONITOR,
28227 IX86_BUILTIN_MWAIT,
28229 /* SSSE3. */
28230 IX86_BUILTIN_PHADDW,
28231 IX86_BUILTIN_PHADDD,
28232 IX86_BUILTIN_PHADDSW,
28233 IX86_BUILTIN_PHSUBW,
28234 IX86_BUILTIN_PHSUBD,
28235 IX86_BUILTIN_PHSUBSW,
28236 IX86_BUILTIN_PMADDUBSW,
28237 IX86_BUILTIN_PMULHRSW,
28238 IX86_BUILTIN_PSHUFB,
28239 IX86_BUILTIN_PSIGNB,
28240 IX86_BUILTIN_PSIGNW,
28241 IX86_BUILTIN_PSIGND,
28242 IX86_BUILTIN_PALIGNR,
28243 IX86_BUILTIN_PABSB,
28244 IX86_BUILTIN_PABSW,
28245 IX86_BUILTIN_PABSD,
28247 IX86_BUILTIN_PHADDW128,
28248 IX86_BUILTIN_PHADDD128,
28249 IX86_BUILTIN_PHADDSW128,
28250 IX86_BUILTIN_PHSUBW128,
28251 IX86_BUILTIN_PHSUBD128,
28252 IX86_BUILTIN_PHSUBSW128,
28253 IX86_BUILTIN_PMADDUBSW128,
28254 IX86_BUILTIN_PMULHRSW128,
28255 IX86_BUILTIN_PSHUFB128,
28256 IX86_BUILTIN_PSIGNB128,
28257 IX86_BUILTIN_PSIGNW128,
28258 IX86_BUILTIN_PSIGND128,
28259 IX86_BUILTIN_PALIGNR128,
28260 IX86_BUILTIN_PABSB128,
28261 IX86_BUILTIN_PABSW128,
28262 IX86_BUILTIN_PABSD128,
28264 /* AMDFAM10 - SSE4A New Instructions. */
28265 IX86_BUILTIN_MOVNTSD,
28266 IX86_BUILTIN_MOVNTSS,
28267 IX86_BUILTIN_EXTRQI,
28268 IX86_BUILTIN_EXTRQ,
28269 IX86_BUILTIN_INSERTQI,
28270 IX86_BUILTIN_INSERTQ,
28272 /* SSE4.1. */
28273 IX86_BUILTIN_BLENDPD,
28274 IX86_BUILTIN_BLENDPS,
28275 IX86_BUILTIN_BLENDVPD,
28276 IX86_BUILTIN_BLENDVPS,
28277 IX86_BUILTIN_PBLENDVB128,
28278 IX86_BUILTIN_PBLENDW128,
28280 IX86_BUILTIN_DPPD,
28281 IX86_BUILTIN_DPPS,
28283 IX86_BUILTIN_INSERTPS128,
28285 IX86_BUILTIN_MOVNTDQA,
28286 IX86_BUILTIN_MPSADBW128,
28287 IX86_BUILTIN_PACKUSDW128,
28288 IX86_BUILTIN_PCMPEQQ,
28289 IX86_BUILTIN_PHMINPOSUW128,
28291 IX86_BUILTIN_PMAXSB128,
28292 IX86_BUILTIN_PMAXSD128,
28293 IX86_BUILTIN_PMAXUD128,
28294 IX86_BUILTIN_PMAXUW128,
28296 IX86_BUILTIN_PMINSB128,
28297 IX86_BUILTIN_PMINSD128,
28298 IX86_BUILTIN_PMINUD128,
28299 IX86_BUILTIN_PMINUW128,
28301 IX86_BUILTIN_PMOVSXBW128,
28302 IX86_BUILTIN_PMOVSXBD128,
28303 IX86_BUILTIN_PMOVSXBQ128,
28304 IX86_BUILTIN_PMOVSXWD128,
28305 IX86_BUILTIN_PMOVSXWQ128,
28306 IX86_BUILTIN_PMOVSXDQ128,
28308 IX86_BUILTIN_PMOVZXBW128,
28309 IX86_BUILTIN_PMOVZXBD128,
28310 IX86_BUILTIN_PMOVZXBQ128,
28311 IX86_BUILTIN_PMOVZXWD128,
28312 IX86_BUILTIN_PMOVZXWQ128,
28313 IX86_BUILTIN_PMOVZXDQ128,
28315 IX86_BUILTIN_PMULDQ128,
28316 IX86_BUILTIN_PMULLD128,
28318 IX86_BUILTIN_ROUNDSD,
28319 IX86_BUILTIN_ROUNDSS,
28321 IX86_BUILTIN_ROUNDPD,
28322 IX86_BUILTIN_ROUNDPS,
28324 IX86_BUILTIN_FLOORPD,
28325 IX86_BUILTIN_CEILPD,
28326 IX86_BUILTIN_TRUNCPD,
28327 IX86_BUILTIN_RINTPD,
28328 IX86_BUILTIN_ROUNDPD_AZ,
28330 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28331 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28332 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28334 IX86_BUILTIN_FLOORPS,
28335 IX86_BUILTIN_CEILPS,
28336 IX86_BUILTIN_TRUNCPS,
28337 IX86_BUILTIN_RINTPS,
28338 IX86_BUILTIN_ROUNDPS_AZ,
28340 IX86_BUILTIN_FLOORPS_SFIX,
28341 IX86_BUILTIN_CEILPS_SFIX,
28342 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28344 IX86_BUILTIN_PTESTZ,
28345 IX86_BUILTIN_PTESTC,
28346 IX86_BUILTIN_PTESTNZC,
28348 IX86_BUILTIN_VEC_INIT_V2SI,
28349 IX86_BUILTIN_VEC_INIT_V4HI,
28350 IX86_BUILTIN_VEC_INIT_V8QI,
28351 IX86_BUILTIN_VEC_EXT_V2DF,
28352 IX86_BUILTIN_VEC_EXT_V2DI,
28353 IX86_BUILTIN_VEC_EXT_V4SF,
28354 IX86_BUILTIN_VEC_EXT_V4SI,
28355 IX86_BUILTIN_VEC_EXT_V8HI,
28356 IX86_BUILTIN_VEC_EXT_V2SI,
28357 IX86_BUILTIN_VEC_EXT_V4HI,
28358 IX86_BUILTIN_VEC_EXT_V16QI,
28359 IX86_BUILTIN_VEC_SET_V2DI,
28360 IX86_BUILTIN_VEC_SET_V4SF,
28361 IX86_BUILTIN_VEC_SET_V4SI,
28362 IX86_BUILTIN_VEC_SET_V8HI,
28363 IX86_BUILTIN_VEC_SET_V4HI,
28364 IX86_BUILTIN_VEC_SET_V16QI,
28366 IX86_BUILTIN_VEC_PACK_SFIX,
28367 IX86_BUILTIN_VEC_PACK_SFIX256,
28369 /* SSE4.2. */
28370 IX86_BUILTIN_CRC32QI,
28371 IX86_BUILTIN_CRC32HI,
28372 IX86_BUILTIN_CRC32SI,
28373 IX86_BUILTIN_CRC32DI,
28375 IX86_BUILTIN_PCMPESTRI128,
28376 IX86_BUILTIN_PCMPESTRM128,
28377 IX86_BUILTIN_PCMPESTRA128,
28378 IX86_BUILTIN_PCMPESTRC128,
28379 IX86_BUILTIN_PCMPESTRO128,
28380 IX86_BUILTIN_PCMPESTRS128,
28381 IX86_BUILTIN_PCMPESTRZ128,
28382 IX86_BUILTIN_PCMPISTRI128,
28383 IX86_BUILTIN_PCMPISTRM128,
28384 IX86_BUILTIN_PCMPISTRA128,
28385 IX86_BUILTIN_PCMPISTRC128,
28386 IX86_BUILTIN_PCMPISTRO128,
28387 IX86_BUILTIN_PCMPISTRS128,
28388 IX86_BUILTIN_PCMPISTRZ128,
28390 IX86_BUILTIN_PCMPGTQ,
28392 /* AES instructions */
28393 IX86_BUILTIN_AESENC128,
28394 IX86_BUILTIN_AESENCLAST128,
28395 IX86_BUILTIN_AESDEC128,
28396 IX86_BUILTIN_AESDECLAST128,
28397 IX86_BUILTIN_AESIMC128,
28398 IX86_BUILTIN_AESKEYGENASSIST128,
28400 /* PCLMUL instruction */
28401 IX86_BUILTIN_PCLMULQDQ128,
28403 /* AVX */
28404 IX86_BUILTIN_ADDPD256,
28405 IX86_BUILTIN_ADDPS256,
28406 IX86_BUILTIN_ADDSUBPD256,
28407 IX86_BUILTIN_ADDSUBPS256,
28408 IX86_BUILTIN_ANDPD256,
28409 IX86_BUILTIN_ANDPS256,
28410 IX86_BUILTIN_ANDNPD256,
28411 IX86_BUILTIN_ANDNPS256,
28412 IX86_BUILTIN_BLENDPD256,
28413 IX86_BUILTIN_BLENDPS256,
28414 IX86_BUILTIN_BLENDVPD256,
28415 IX86_BUILTIN_BLENDVPS256,
28416 IX86_BUILTIN_DIVPD256,
28417 IX86_BUILTIN_DIVPS256,
28418 IX86_BUILTIN_DPPS256,
28419 IX86_BUILTIN_HADDPD256,
28420 IX86_BUILTIN_HADDPS256,
28421 IX86_BUILTIN_HSUBPD256,
28422 IX86_BUILTIN_HSUBPS256,
28423 IX86_BUILTIN_MAXPD256,
28424 IX86_BUILTIN_MAXPS256,
28425 IX86_BUILTIN_MINPD256,
28426 IX86_BUILTIN_MINPS256,
28427 IX86_BUILTIN_MULPD256,
28428 IX86_BUILTIN_MULPS256,
28429 IX86_BUILTIN_ORPD256,
28430 IX86_BUILTIN_ORPS256,
28431 IX86_BUILTIN_SHUFPD256,
28432 IX86_BUILTIN_SHUFPS256,
28433 IX86_BUILTIN_SUBPD256,
28434 IX86_BUILTIN_SUBPS256,
28435 IX86_BUILTIN_XORPD256,
28436 IX86_BUILTIN_XORPS256,
28437 IX86_BUILTIN_CMPSD,
28438 IX86_BUILTIN_CMPSS,
28439 IX86_BUILTIN_CMPPD,
28440 IX86_BUILTIN_CMPPS,
28441 IX86_BUILTIN_CMPPD256,
28442 IX86_BUILTIN_CMPPS256,
28443 IX86_BUILTIN_CVTDQ2PD256,
28444 IX86_BUILTIN_CVTDQ2PS256,
28445 IX86_BUILTIN_CVTPD2PS256,
28446 IX86_BUILTIN_CVTPS2DQ256,
28447 IX86_BUILTIN_CVTPS2PD256,
28448 IX86_BUILTIN_CVTTPD2DQ256,
28449 IX86_BUILTIN_CVTPD2DQ256,
28450 IX86_BUILTIN_CVTTPS2DQ256,
28451 IX86_BUILTIN_EXTRACTF128PD256,
28452 IX86_BUILTIN_EXTRACTF128PS256,
28453 IX86_BUILTIN_EXTRACTF128SI256,
28454 IX86_BUILTIN_VZEROALL,
28455 IX86_BUILTIN_VZEROUPPER,
28456 IX86_BUILTIN_VPERMILVARPD,
28457 IX86_BUILTIN_VPERMILVARPS,
28458 IX86_BUILTIN_VPERMILVARPD256,
28459 IX86_BUILTIN_VPERMILVARPS256,
28460 IX86_BUILTIN_VPERMILPD,
28461 IX86_BUILTIN_VPERMILPS,
28462 IX86_BUILTIN_VPERMILPD256,
28463 IX86_BUILTIN_VPERMILPS256,
28464 IX86_BUILTIN_VPERMIL2PD,
28465 IX86_BUILTIN_VPERMIL2PS,
28466 IX86_BUILTIN_VPERMIL2PD256,
28467 IX86_BUILTIN_VPERMIL2PS256,
28468 IX86_BUILTIN_VPERM2F128PD256,
28469 IX86_BUILTIN_VPERM2F128PS256,
28470 IX86_BUILTIN_VPERM2F128SI256,
28471 IX86_BUILTIN_VBROADCASTSS,
28472 IX86_BUILTIN_VBROADCASTSD256,
28473 IX86_BUILTIN_VBROADCASTSS256,
28474 IX86_BUILTIN_VBROADCASTPD256,
28475 IX86_BUILTIN_VBROADCASTPS256,
28476 IX86_BUILTIN_VINSERTF128PD256,
28477 IX86_BUILTIN_VINSERTF128PS256,
28478 IX86_BUILTIN_VINSERTF128SI256,
28479 IX86_BUILTIN_LOADUPD256,
28480 IX86_BUILTIN_LOADUPS256,
28481 IX86_BUILTIN_STOREUPD256,
28482 IX86_BUILTIN_STOREUPS256,
28483 IX86_BUILTIN_LDDQU256,
28484 IX86_BUILTIN_MOVNTDQ256,
28485 IX86_BUILTIN_MOVNTPD256,
28486 IX86_BUILTIN_MOVNTPS256,
28487 IX86_BUILTIN_LOADDQU256,
28488 IX86_BUILTIN_STOREDQU256,
28489 IX86_BUILTIN_MASKLOADPD,
28490 IX86_BUILTIN_MASKLOADPS,
28491 IX86_BUILTIN_MASKSTOREPD,
28492 IX86_BUILTIN_MASKSTOREPS,
28493 IX86_BUILTIN_MASKLOADPD256,
28494 IX86_BUILTIN_MASKLOADPS256,
28495 IX86_BUILTIN_MASKSTOREPD256,
28496 IX86_BUILTIN_MASKSTOREPS256,
28497 IX86_BUILTIN_MOVSHDUP256,
28498 IX86_BUILTIN_MOVSLDUP256,
28499 IX86_BUILTIN_MOVDDUP256,
28501 IX86_BUILTIN_SQRTPD256,
28502 IX86_BUILTIN_SQRTPS256,
28503 IX86_BUILTIN_SQRTPS_NR256,
28504 IX86_BUILTIN_RSQRTPS256,
28505 IX86_BUILTIN_RSQRTPS_NR256,
28507 IX86_BUILTIN_RCPPS256,
28509 IX86_BUILTIN_ROUNDPD256,
28510 IX86_BUILTIN_ROUNDPS256,
28512 IX86_BUILTIN_FLOORPD256,
28513 IX86_BUILTIN_CEILPD256,
28514 IX86_BUILTIN_TRUNCPD256,
28515 IX86_BUILTIN_RINTPD256,
28516 IX86_BUILTIN_ROUNDPD_AZ256,
28518 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28519 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28520 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28522 IX86_BUILTIN_FLOORPS256,
28523 IX86_BUILTIN_CEILPS256,
28524 IX86_BUILTIN_TRUNCPS256,
28525 IX86_BUILTIN_RINTPS256,
28526 IX86_BUILTIN_ROUNDPS_AZ256,
28528 IX86_BUILTIN_FLOORPS_SFIX256,
28529 IX86_BUILTIN_CEILPS_SFIX256,
28530 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28532 IX86_BUILTIN_UNPCKHPD256,
28533 IX86_BUILTIN_UNPCKLPD256,
28534 IX86_BUILTIN_UNPCKHPS256,
28535 IX86_BUILTIN_UNPCKLPS256,
28537 IX86_BUILTIN_SI256_SI,
28538 IX86_BUILTIN_PS256_PS,
28539 IX86_BUILTIN_PD256_PD,
28540 IX86_BUILTIN_SI_SI256,
28541 IX86_BUILTIN_PS_PS256,
28542 IX86_BUILTIN_PD_PD256,
28544 IX86_BUILTIN_VTESTZPD,
28545 IX86_BUILTIN_VTESTCPD,
28546 IX86_BUILTIN_VTESTNZCPD,
28547 IX86_BUILTIN_VTESTZPS,
28548 IX86_BUILTIN_VTESTCPS,
28549 IX86_BUILTIN_VTESTNZCPS,
28550 IX86_BUILTIN_VTESTZPD256,
28551 IX86_BUILTIN_VTESTCPD256,
28552 IX86_BUILTIN_VTESTNZCPD256,
28553 IX86_BUILTIN_VTESTZPS256,
28554 IX86_BUILTIN_VTESTCPS256,
28555 IX86_BUILTIN_VTESTNZCPS256,
28556 IX86_BUILTIN_PTESTZ256,
28557 IX86_BUILTIN_PTESTC256,
28558 IX86_BUILTIN_PTESTNZC256,
28560 IX86_BUILTIN_MOVMSKPD256,
28561 IX86_BUILTIN_MOVMSKPS256,
28563 /* AVX2 */
28564 IX86_BUILTIN_MPSADBW256,
28565 IX86_BUILTIN_PABSB256,
28566 IX86_BUILTIN_PABSW256,
28567 IX86_BUILTIN_PABSD256,
28568 IX86_BUILTIN_PACKSSDW256,
28569 IX86_BUILTIN_PACKSSWB256,
28570 IX86_BUILTIN_PACKUSDW256,
28571 IX86_BUILTIN_PACKUSWB256,
28572 IX86_BUILTIN_PADDB256,
28573 IX86_BUILTIN_PADDW256,
28574 IX86_BUILTIN_PADDD256,
28575 IX86_BUILTIN_PADDQ256,
28576 IX86_BUILTIN_PADDSB256,
28577 IX86_BUILTIN_PADDSW256,
28578 IX86_BUILTIN_PADDUSB256,
28579 IX86_BUILTIN_PADDUSW256,
28580 IX86_BUILTIN_PALIGNR256,
28581 IX86_BUILTIN_AND256I,
28582 IX86_BUILTIN_ANDNOT256I,
28583 IX86_BUILTIN_PAVGB256,
28584 IX86_BUILTIN_PAVGW256,
28585 IX86_BUILTIN_PBLENDVB256,
28586 IX86_BUILTIN_PBLENDVW256,
28587 IX86_BUILTIN_PCMPEQB256,
28588 IX86_BUILTIN_PCMPEQW256,
28589 IX86_BUILTIN_PCMPEQD256,
28590 IX86_BUILTIN_PCMPEQQ256,
28591 IX86_BUILTIN_PCMPGTB256,
28592 IX86_BUILTIN_PCMPGTW256,
28593 IX86_BUILTIN_PCMPGTD256,
28594 IX86_BUILTIN_PCMPGTQ256,
28595 IX86_BUILTIN_PHADDW256,
28596 IX86_BUILTIN_PHADDD256,
28597 IX86_BUILTIN_PHADDSW256,
28598 IX86_BUILTIN_PHSUBW256,
28599 IX86_BUILTIN_PHSUBD256,
28600 IX86_BUILTIN_PHSUBSW256,
28601 IX86_BUILTIN_PMADDUBSW256,
28602 IX86_BUILTIN_PMADDWD256,
28603 IX86_BUILTIN_PMAXSB256,
28604 IX86_BUILTIN_PMAXSW256,
28605 IX86_BUILTIN_PMAXSD256,
28606 IX86_BUILTIN_PMAXUB256,
28607 IX86_BUILTIN_PMAXUW256,
28608 IX86_BUILTIN_PMAXUD256,
28609 IX86_BUILTIN_PMINSB256,
28610 IX86_BUILTIN_PMINSW256,
28611 IX86_BUILTIN_PMINSD256,
28612 IX86_BUILTIN_PMINUB256,
28613 IX86_BUILTIN_PMINUW256,
28614 IX86_BUILTIN_PMINUD256,
28615 IX86_BUILTIN_PMOVMSKB256,
28616 IX86_BUILTIN_PMOVSXBW256,
28617 IX86_BUILTIN_PMOVSXBD256,
28618 IX86_BUILTIN_PMOVSXBQ256,
28619 IX86_BUILTIN_PMOVSXWD256,
28620 IX86_BUILTIN_PMOVSXWQ256,
28621 IX86_BUILTIN_PMOVSXDQ256,
28622 IX86_BUILTIN_PMOVZXBW256,
28623 IX86_BUILTIN_PMOVZXBD256,
28624 IX86_BUILTIN_PMOVZXBQ256,
28625 IX86_BUILTIN_PMOVZXWD256,
28626 IX86_BUILTIN_PMOVZXWQ256,
28627 IX86_BUILTIN_PMOVZXDQ256,
28628 IX86_BUILTIN_PMULDQ256,
28629 IX86_BUILTIN_PMULHRSW256,
28630 IX86_BUILTIN_PMULHUW256,
28631 IX86_BUILTIN_PMULHW256,
28632 IX86_BUILTIN_PMULLW256,
28633 IX86_BUILTIN_PMULLD256,
28634 IX86_BUILTIN_PMULUDQ256,
28635 IX86_BUILTIN_POR256,
28636 IX86_BUILTIN_PSADBW256,
28637 IX86_BUILTIN_PSHUFB256,
28638 IX86_BUILTIN_PSHUFD256,
28639 IX86_BUILTIN_PSHUFHW256,
28640 IX86_BUILTIN_PSHUFLW256,
28641 IX86_BUILTIN_PSIGNB256,
28642 IX86_BUILTIN_PSIGNW256,
28643 IX86_BUILTIN_PSIGND256,
28644 IX86_BUILTIN_PSLLDQI256,
28645 IX86_BUILTIN_PSLLWI256,
28646 IX86_BUILTIN_PSLLW256,
28647 IX86_BUILTIN_PSLLDI256,
28648 IX86_BUILTIN_PSLLD256,
28649 IX86_BUILTIN_PSLLQI256,
28650 IX86_BUILTIN_PSLLQ256,
28651 IX86_BUILTIN_PSRAWI256,
28652 IX86_BUILTIN_PSRAW256,
28653 IX86_BUILTIN_PSRADI256,
28654 IX86_BUILTIN_PSRAD256,
28655 IX86_BUILTIN_PSRLDQI256,
28656 IX86_BUILTIN_PSRLWI256,
28657 IX86_BUILTIN_PSRLW256,
28658 IX86_BUILTIN_PSRLDI256,
28659 IX86_BUILTIN_PSRLD256,
28660 IX86_BUILTIN_PSRLQI256,
28661 IX86_BUILTIN_PSRLQ256,
28662 IX86_BUILTIN_PSUBB256,
28663 IX86_BUILTIN_PSUBW256,
28664 IX86_BUILTIN_PSUBD256,
28665 IX86_BUILTIN_PSUBQ256,
28666 IX86_BUILTIN_PSUBSB256,
28667 IX86_BUILTIN_PSUBSW256,
28668 IX86_BUILTIN_PSUBUSB256,
28669 IX86_BUILTIN_PSUBUSW256,
28670 IX86_BUILTIN_PUNPCKHBW256,
28671 IX86_BUILTIN_PUNPCKHWD256,
28672 IX86_BUILTIN_PUNPCKHDQ256,
28673 IX86_BUILTIN_PUNPCKHQDQ256,
28674 IX86_BUILTIN_PUNPCKLBW256,
28675 IX86_BUILTIN_PUNPCKLWD256,
28676 IX86_BUILTIN_PUNPCKLDQ256,
28677 IX86_BUILTIN_PUNPCKLQDQ256,
28678 IX86_BUILTIN_PXOR256,
28679 IX86_BUILTIN_MOVNTDQA256,
28680 IX86_BUILTIN_VBROADCASTSS_PS,
28681 IX86_BUILTIN_VBROADCASTSS_PS256,
28682 IX86_BUILTIN_VBROADCASTSD_PD256,
28683 IX86_BUILTIN_VBROADCASTSI256,
28684 IX86_BUILTIN_PBLENDD256,
28685 IX86_BUILTIN_PBLENDD128,
28686 IX86_BUILTIN_PBROADCASTB256,
28687 IX86_BUILTIN_PBROADCASTW256,
28688 IX86_BUILTIN_PBROADCASTD256,
28689 IX86_BUILTIN_PBROADCASTQ256,
28690 IX86_BUILTIN_PBROADCASTB128,
28691 IX86_BUILTIN_PBROADCASTW128,
28692 IX86_BUILTIN_PBROADCASTD128,
28693 IX86_BUILTIN_PBROADCASTQ128,
28694 IX86_BUILTIN_VPERMVARSI256,
28695 IX86_BUILTIN_VPERMDF256,
28696 IX86_BUILTIN_VPERMVARSF256,
28697 IX86_BUILTIN_VPERMDI256,
28698 IX86_BUILTIN_VPERMTI256,
28699 IX86_BUILTIN_VEXTRACT128I256,
28700 IX86_BUILTIN_VINSERT128I256,
28701 IX86_BUILTIN_MASKLOADD,
28702 IX86_BUILTIN_MASKLOADQ,
28703 IX86_BUILTIN_MASKLOADD256,
28704 IX86_BUILTIN_MASKLOADQ256,
28705 IX86_BUILTIN_MASKSTORED,
28706 IX86_BUILTIN_MASKSTOREQ,
28707 IX86_BUILTIN_MASKSTORED256,
28708 IX86_BUILTIN_MASKSTOREQ256,
28709 IX86_BUILTIN_PSLLVV4DI,
28710 IX86_BUILTIN_PSLLVV2DI,
28711 IX86_BUILTIN_PSLLVV8SI,
28712 IX86_BUILTIN_PSLLVV4SI,
28713 IX86_BUILTIN_PSRAVV8SI,
28714 IX86_BUILTIN_PSRAVV4SI,
28715 IX86_BUILTIN_PSRLVV4DI,
28716 IX86_BUILTIN_PSRLVV2DI,
28717 IX86_BUILTIN_PSRLVV8SI,
28718 IX86_BUILTIN_PSRLVV4SI,
28720 IX86_BUILTIN_GATHERSIV2DF,
28721 IX86_BUILTIN_GATHERSIV4DF,
28722 IX86_BUILTIN_GATHERDIV2DF,
28723 IX86_BUILTIN_GATHERDIV4DF,
28724 IX86_BUILTIN_GATHERSIV4SF,
28725 IX86_BUILTIN_GATHERSIV8SF,
28726 IX86_BUILTIN_GATHERDIV4SF,
28727 IX86_BUILTIN_GATHERDIV8SF,
28728 IX86_BUILTIN_GATHERSIV2DI,
28729 IX86_BUILTIN_GATHERSIV4DI,
28730 IX86_BUILTIN_GATHERDIV2DI,
28731 IX86_BUILTIN_GATHERDIV4DI,
28732 IX86_BUILTIN_GATHERSIV4SI,
28733 IX86_BUILTIN_GATHERSIV8SI,
28734 IX86_BUILTIN_GATHERDIV4SI,
28735 IX86_BUILTIN_GATHERDIV8SI,
28737 /* AVX512F */
28738 IX86_BUILTIN_SI512_SI256,
28739 IX86_BUILTIN_PD512_PD256,
28740 IX86_BUILTIN_PS512_PS256,
28741 IX86_BUILTIN_SI512_SI,
28742 IX86_BUILTIN_PD512_PD,
28743 IX86_BUILTIN_PS512_PS,
28744 IX86_BUILTIN_ADDPD512,
28745 IX86_BUILTIN_ADDPS512,
28746 IX86_BUILTIN_ADDSD_ROUND,
28747 IX86_BUILTIN_ADDSS_ROUND,
28748 IX86_BUILTIN_ALIGND512,
28749 IX86_BUILTIN_ALIGNQ512,
28750 IX86_BUILTIN_BLENDMD512,
28751 IX86_BUILTIN_BLENDMPD512,
28752 IX86_BUILTIN_BLENDMPS512,
28753 IX86_BUILTIN_BLENDMQ512,
28754 IX86_BUILTIN_BROADCASTF32X4_512,
28755 IX86_BUILTIN_BROADCASTF64X4_512,
28756 IX86_BUILTIN_BROADCASTI32X4_512,
28757 IX86_BUILTIN_BROADCASTI64X4_512,
28758 IX86_BUILTIN_BROADCASTSD512,
28759 IX86_BUILTIN_BROADCASTSS512,
28760 IX86_BUILTIN_CMPD512,
28761 IX86_BUILTIN_CMPPD512,
28762 IX86_BUILTIN_CMPPS512,
28763 IX86_BUILTIN_CMPQ512,
28764 IX86_BUILTIN_CMPSD_MASK,
28765 IX86_BUILTIN_CMPSS_MASK,
28766 IX86_BUILTIN_COMIDF,
28767 IX86_BUILTIN_COMISF,
28768 IX86_BUILTIN_COMPRESSPD512,
28769 IX86_BUILTIN_COMPRESSPDSTORE512,
28770 IX86_BUILTIN_COMPRESSPS512,
28771 IX86_BUILTIN_COMPRESSPSSTORE512,
28772 IX86_BUILTIN_CVTDQ2PD512,
28773 IX86_BUILTIN_CVTDQ2PS512,
28774 IX86_BUILTIN_CVTPD2DQ512,
28775 IX86_BUILTIN_CVTPD2PS512,
28776 IX86_BUILTIN_CVTPD2UDQ512,
28777 IX86_BUILTIN_CVTPH2PS512,
28778 IX86_BUILTIN_CVTPS2DQ512,
28779 IX86_BUILTIN_CVTPS2PD512,
28780 IX86_BUILTIN_CVTPS2PH512,
28781 IX86_BUILTIN_CVTPS2UDQ512,
28782 IX86_BUILTIN_CVTSD2SS_ROUND,
28783 IX86_BUILTIN_CVTSI2SD64,
28784 IX86_BUILTIN_CVTSI2SS32,
28785 IX86_BUILTIN_CVTSI2SS64,
28786 IX86_BUILTIN_CVTSS2SD_ROUND,
28787 IX86_BUILTIN_CVTTPD2DQ512,
28788 IX86_BUILTIN_CVTTPD2UDQ512,
28789 IX86_BUILTIN_CVTTPS2DQ512,
28790 IX86_BUILTIN_CVTTPS2UDQ512,
28791 IX86_BUILTIN_CVTUDQ2PD512,
28792 IX86_BUILTIN_CVTUDQ2PS512,
28793 IX86_BUILTIN_CVTUSI2SD32,
28794 IX86_BUILTIN_CVTUSI2SD64,
28795 IX86_BUILTIN_CVTUSI2SS32,
28796 IX86_BUILTIN_CVTUSI2SS64,
28797 IX86_BUILTIN_DIVPD512,
28798 IX86_BUILTIN_DIVPS512,
28799 IX86_BUILTIN_DIVSD_ROUND,
28800 IX86_BUILTIN_DIVSS_ROUND,
28801 IX86_BUILTIN_EXPANDPD512,
28802 IX86_BUILTIN_EXPANDPD512Z,
28803 IX86_BUILTIN_EXPANDPDLOAD512,
28804 IX86_BUILTIN_EXPANDPDLOAD512Z,
28805 IX86_BUILTIN_EXPANDPS512,
28806 IX86_BUILTIN_EXPANDPS512Z,
28807 IX86_BUILTIN_EXPANDPSLOAD512,
28808 IX86_BUILTIN_EXPANDPSLOAD512Z,
28809 IX86_BUILTIN_EXTRACTF32X4,
28810 IX86_BUILTIN_EXTRACTF64X4,
28811 IX86_BUILTIN_EXTRACTI32X4,
28812 IX86_BUILTIN_EXTRACTI64X4,
28813 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28814 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28815 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28816 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28817 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28818 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28819 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28820 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28821 IX86_BUILTIN_GETEXPPD512,
28822 IX86_BUILTIN_GETEXPPS512,
28823 IX86_BUILTIN_GETEXPSD128,
28824 IX86_BUILTIN_GETEXPSS128,
28825 IX86_BUILTIN_GETMANTPD512,
28826 IX86_BUILTIN_GETMANTPS512,
28827 IX86_BUILTIN_GETMANTSD128,
28828 IX86_BUILTIN_GETMANTSS128,
28829 IX86_BUILTIN_INSERTF32X4,
28830 IX86_BUILTIN_INSERTF64X4,
28831 IX86_BUILTIN_INSERTI32X4,
28832 IX86_BUILTIN_INSERTI64X4,
28833 IX86_BUILTIN_LOADAPD512,
28834 IX86_BUILTIN_LOADAPS512,
28835 IX86_BUILTIN_LOADDQUDI512,
28836 IX86_BUILTIN_LOADDQUSI512,
28837 IX86_BUILTIN_LOADUPD512,
28838 IX86_BUILTIN_LOADUPS512,
28839 IX86_BUILTIN_MAXPD512,
28840 IX86_BUILTIN_MAXPS512,
28841 IX86_BUILTIN_MAXSD_ROUND,
28842 IX86_BUILTIN_MAXSS_ROUND,
28843 IX86_BUILTIN_MINPD512,
28844 IX86_BUILTIN_MINPS512,
28845 IX86_BUILTIN_MINSD_ROUND,
28846 IX86_BUILTIN_MINSS_ROUND,
28847 IX86_BUILTIN_MOVAPD512,
28848 IX86_BUILTIN_MOVAPS512,
28849 IX86_BUILTIN_MOVDDUP512,
28850 IX86_BUILTIN_MOVDQA32LOAD512,
28851 IX86_BUILTIN_MOVDQA32STORE512,
28852 IX86_BUILTIN_MOVDQA32_512,
28853 IX86_BUILTIN_MOVDQA64LOAD512,
28854 IX86_BUILTIN_MOVDQA64STORE512,
28855 IX86_BUILTIN_MOVDQA64_512,
28856 IX86_BUILTIN_MOVNTDQ512,
28857 IX86_BUILTIN_MOVNTDQA512,
28858 IX86_BUILTIN_MOVNTPD512,
28859 IX86_BUILTIN_MOVNTPS512,
28860 IX86_BUILTIN_MOVSHDUP512,
28861 IX86_BUILTIN_MOVSLDUP512,
28862 IX86_BUILTIN_MULPD512,
28863 IX86_BUILTIN_MULPS512,
28864 IX86_BUILTIN_MULSD_ROUND,
28865 IX86_BUILTIN_MULSS_ROUND,
28866 IX86_BUILTIN_PABSD512,
28867 IX86_BUILTIN_PABSQ512,
28868 IX86_BUILTIN_PADDD512,
28869 IX86_BUILTIN_PADDQ512,
28870 IX86_BUILTIN_PANDD512,
28871 IX86_BUILTIN_PANDND512,
28872 IX86_BUILTIN_PANDNQ512,
28873 IX86_BUILTIN_PANDQ512,
28874 IX86_BUILTIN_PBROADCASTD512,
28875 IX86_BUILTIN_PBROADCASTD512_GPR,
28876 IX86_BUILTIN_PBROADCASTMB512,
28877 IX86_BUILTIN_PBROADCASTMW512,
28878 IX86_BUILTIN_PBROADCASTQ512,
28879 IX86_BUILTIN_PBROADCASTQ512_GPR,
28880 IX86_BUILTIN_PCMPEQD512_MASK,
28881 IX86_BUILTIN_PCMPEQQ512_MASK,
28882 IX86_BUILTIN_PCMPGTD512_MASK,
28883 IX86_BUILTIN_PCMPGTQ512_MASK,
28884 IX86_BUILTIN_PCOMPRESSD512,
28885 IX86_BUILTIN_PCOMPRESSDSTORE512,
28886 IX86_BUILTIN_PCOMPRESSQ512,
28887 IX86_BUILTIN_PCOMPRESSQSTORE512,
28888 IX86_BUILTIN_PEXPANDD512,
28889 IX86_BUILTIN_PEXPANDD512Z,
28890 IX86_BUILTIN_PEXPANDDLOAD512,
28891 IX86_BUILTIN_PEXPANDDLOAD512Z,
28892 IX86_BUILTIN_PEXPANDQ512,
28893 IX86_BUILTIN_PEXPANDQ512Z,
28894 IX86_BUILTIN_PEXPANDQLOAD512,
28895 IX86_BUILTIN_PEXPANDQLOAD512Z,
28896 IX86_BUILTIN_PMAXSD512,
28897 IX86_BUILTIN_PMAXSQ512,
28898 IX86_BUILTIN_PMAXUD512,
28899 IX86_BUILTIN_PMAXUQ512,
28900 IX86_BUILTIN_PMINSD512,
28901 IX86_BUILTIN_PMINSQ512,
28902 IX86_BUILTIN_PMINUD512,
28903 IX86_BUILTIN_PMINUQ512,
28904 IX86_BUILTIN_PMOVDB512,
28905 IX86_BUILTIN_PMOVDB512_MEM,
28906 IX86_BUILTIN_PMOVDW512,
28907 IX86_BUILTIN_PMOVDW512_MEM,
28908 IX86_BUILTIN_PMOVQB512,
28909 IX86_BUILTIN_PMOVQB512_MEM,
28910 IX86_BUILTIN_PMOVQD512,
28911 IX86_BUILTIN_PMOVQD512_MEM,
28912 IX86_BUILTIN_PMOVQW512,
28913 IX86_BUILTIN_PMOVQW512_MEM,
28914 IX86_BUILTIN_PMOVSDB512,
28915 IX86_BUILTIN_PMOVSDB512_MEM,
28916 IX86_BUILTIN_PMOVSDW512,
28917 IX86_BUILTIN_PMOVSDW512_MEM,
28918 IX86_BUILTIN_PMOVSQB512,
28919 IX86_BUILTIN_PMOVSQB512_MEM,
28920 IX86_BUILTIN_PMOVSQD512,
28921 IX86_BUILTIN_PMOVSQD512_MEM,
28922 IX86_BUILTIN_PMOVSQW512,
28923 IX86_BUILTIN_PMOVSQW512_MEM,
28924 IX86_BUILTIN_PMOVSXBD512,
28925 IX86_BUILTIN_PMOVSXBQ512,
28926 IX86_BUILTIN_PMOVSXDQ512,
28927 IX86_BUILTIN_PMOVSXWD512,
28928 IX86_BUILTIN_PMOVSXWQ512,
28929 IX86_BUILTIN_PMOVUSDB512,
28930 IX86_BUILTIN_PMOVUSDB512_MEM,
28931 IX86_BUILTIN_PMOVUSDW512,
28932 IX86_BUILTIN_PMOVUSDW512_MEM,
28933 IX86_BUILTIN_PMOVUSQB512,
28934 IX86_BUILTIN_PMOVUSQB512_MEM,
28935 IX86_BUILTIN_PMOVUSQD512,
28936 IX86_BUILTIN_PMOVUSQD512_MEM,
28937 IX86_BUILTIN_PMOVUSQW512,
28938 IX86_BUILTIN_PMOVUSQW512_MEM,
28939 IX86_BUILTIN_PMOVZXBD512,
28940 IX86_BUILTIN_PMOVZXBQ512,
28941 IX86_BUILTIN_PMOVZXDQ512,
28942 IX86_BUILTIN_PMOVZXWD512,
28943 IX86_BUILTIN_PMOVZXWQ512,
28944 IX86_BUILTIN_PMULDQ512,
28945 IX86_BUILTIN_PMULLD512,
28946 IX86_BUILTIN_PMULUDQ512,
28947 IX86_BUILTIN_PORD512,
28948 IX86_BUILTIN_PORQ512,
28949 IX86_BUILTIN_PROLD512,
28950 IX86_BUILTIN_PROLQ512,
28951 IX86_BUILTIN_PROLVD512,
28952 IX86_BUILTIN_PROLVQ512,
28953 IX86_BUILTIN_PRORD512,
28954 IX86_BUILTIN_PRORQ512,
28955 IX86_BUILTIN_PRORVD512,
28956 IX86_BUILTIN_PRORVQ512,
28957 IX86_BUILTIN_PSHUFD512,
28958 IX86_BUILTIN_PSLLD512,
28959 IX86_BUILTIN_PSLLDI512,
28960 IX86_BUILTIN_PSLLQ512,
28961 IX86_BUILTIN_PSLLQI512,
28962 IX86_BUILTIN_PSLLVV16SI,
28963 IX86_BUILTIN_PSLLVV8DI,
28964 IX86_BUILTIN_PSRAD512,
28965 IX86_BUILTIN_PSRADI512,
28966 IX86_BUILTIN_PSRAQ512,
28967 IX86_BUILTIN_PSRAQI512,
28968 IX86_BUILTIN_PSRAVV16SI,
28969 IX86_BUILTIN_PSRAVV8DI,
28970 IX86_BUILTIN_PSRLD512,
28971 IX86_BUILTIN_PSRLDI512,
28972 IX86_BUILTIN_PSRLQ512,
28973 IX86_BUILTIN_PSRLQI512,
28974 IX86_BUILTIN_PSRLVV16SI,
28975 IX86_BUILTIN_PSRLVV8DI,
28976 IX86_BUILTIN_PSUBD512,
28977 IX86_BUILTIN_PSUBQ512,
28978 IX86_BUILTIN_PTESTMD512,
28979 IX86_BUILTIN_PTESTMQ512,
28980 IX86_BUILTIN_PTESTNMD512,
28981 IX86_BUILTIN_PTESTNMQ512,
28982 IX86_BUILTIN_PUNPCKHDQ512,
28983 IX86_BUILTIN_PUNPCKHQDQ512,
28984 IX86_BUILTIN_PUNPCKLDQ512,
28985 IX86_BUILTIN_PUNPCKLQDQ512,
28986 IX86_BUILTIN_PXORD512,
28987 IX86_BUILTIN_PXORQ512,
28988 IX86_BUILTIN_RCP14PD512,
28989 IX86_BUILTIN_RCP14PS512,
28990 IX86_BUILTIN_RCP14SD,
28991 IX86_BUILTIN_RCP14SS,
28992 IX86_BUILTIN_RNDSCALEPD,
28993 IX86_BUILTIN_RNDSCALEPS,
28994 IX86_BUILTIN_RNDSCALESD,
28995 IX86_BUILTIN_RNDSCALESS,
28996 IX86_BUILTIN_RSQRT14PD512,
28997 IX86_BUILTIN_RSQRT14PS512,
28998 IX86_BUILTIN_RSQRT14SD,
28999 IX86_BUILTIN_RSQRT14SS,
29000 IX86_BUILTIN_SCALEFPD512,
29001 IX86_BUILTIN_SCALEFPS512,
29002 IX86_BUILTIN_SCALEFSD,
29003 IX86_BUILTIN_SCALEFSS,
29004 IX86_BUILTIN_SHUFPD512,
29005 IX86_BUILTIN_SHUFPS512,
29006 IX86_BUILTIN_SHUF_F32x4,
29007 IX86_BUILTIN_SHUF_F64x2,
29008 IX86_BUILTIN_SHUF_I32x4,
29009 IX86_BUILTIN_SHUF_I64x2,
29010 IX86_BUILTIN_SQRTPD512,
29011 IX86_BUILTIN_SQRTPD512_MASK,
29012 IX86_BUILTIN_SQRTPS512_MASK,
29013 IX86_BUILTIN_SQRTPS_NR512,
29014 IX86_BUILTIN_SQRTSD_ROUND,
29015 IX86_BUILTIN_SQRTSS_ROUND,
29016 IX86_BUILTIN_STOREAPD512,
29017 IX86_BUILTIN_STOREAPS512,
29018 IX86_BUILTIN_STOREDQUDI512,
29019 IX86_BUILTIN_STOREDQUSI512,
29020 IX86_BUILTIN_STOREUPD512,
29021 IX86_BUILTIN_STOREUPS512,
29022 IX86_BUILTIN_SUBPD512,
29023 IX86_BUILTIN_SUBPS512,
29024 IX86_BUILTIN_SUBSD_ROUND,
29025 IX86_BUILTIN_SUBSS_ROUND,
29026 IX86_BUILTIN_UCMPD512,
29027 IX86_BUILTIN_UCMPQ512,
29028 IX86_BUILTIN_UNPCKHPD512,
29029 IX86_BUILTIN_UNPCKHPS512,
29030 IX86_BUILTIN_UNPCKLPD512,
29031 IX86_BUILTIN_UNPCKLPS512,
29032 IX86_BUILTIN_VCVTSD2SI32,
29033 IX86_BUILTIN_VCVTSD2SI64,
29034 IX86_BUILTIN_VCVTSD2USI32,
29035 IX86_BUILTIN_VCVTSD2USI64,
29036 IX86_BUILTIN_VCVTSS2SI32,
29037 IX86_BUILTIN_VCVTSS2SI64,
29038 IX86_BUILTIN_VCVTSS2USI32,
29039 IX86_BUILTIN_VCVTSS2USI64,
29040 IX86_BUILTIN_VCVTTSD2SI32,
29041 IX86_BUILTIN_VCVTTSD2SI64,
29042 IX86_BUILTIN_VCVTTSD2USI32,
29043 IX86_BUILTIN_VCVTTSD2USI64,
29044 IX86_BUILTIN_VCVTTSS2SI32,
29045 IX86_BUILTIN_VCVTTSS2SI64,
29046 IX86_BUILTIN_VCVTTSS2USI32,
29047 IX86_BUILTIN_VCVTTSS2USI64,
29048 IX86_BUILTIN_VFMADDPD512_MASK,
29049 IX86_BUILTIN_VFMADDPD512_MASK3,
29050 IX86_BUILTIN_VFMADDPD512_MASKZ,
29051 IX86_BUILTIN_VFMADDPS512_MASK,
29052 IX86_BUILTIN_VFMADDPS512_MASK3,
29053 IX86_BUILTIN_VFMADDPS512_MASKZ,
29054 IX86_BUILTIN_VFMADDSD3_ROUND,
29055 IX86_BUILTIN_VFMADDSS3_ROUND,
29056 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29057 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29058 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29059 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29060 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29061 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29062 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29063 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29064 IX86_BUILTIN_VFMSUBPD512_MASK3,
29065 IX86_BUILTIN_VFMSUBPS512_MASK3,
29066 IX86_BUILTIN_VFMSUBSD3_MASK3,
29067 IX86_BUILTIN_VFMSUBSS3_MASK3,
29068 IX86_BUILTIN_VFNMADDPD512_MASK,
29069 IX86_BUILTIN_VFNMADDPS512_MASK,
29070 IX86_BUILTIN_VFNMSUBPD512_MASK,
29071 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29072 IX86_BUILTIN_VFNMSUBPS512_MASK,
29073 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29074 IX86_BUILTIN_VPCLZCNTD512,
29075 IX86_BUILTIN_VPCLZCNTQ512,
29076 IX86_BUILTIN_VPCONFLICTD512,
29077 IX86_BUILTIN_VPCONFLICTQ512,
29078 IX86_BUILTIN_VPERMDF512,
29079 IX86_BUILTIN_VPERMDI512,
29080 IX86_BUILTIN_VPERMI2VARD512,
29081 IX86_BUILTIN_VPERMI2VARPD512,
29082 IX86_BUILTIN_VPERMI2VARPS512,
29083 IX86_BUILTIN_VPERMI2VARQ512,
29084 IX86_BUILTIN_VPERMILPD512,
29085 IX86_BUILTIN_VPERMILPS512,
29086 IX86_BUILTIN_VPERMILVARPD512,
29087 IX86_BUILTIN_VPERMILVARPS512,
29088 IX86_BUILTIN_VPERMT2VARD512,
29089 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29090 IX86_BUILTIN_VPERMT2VARPD512,
29091 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29092 IX86_BUILTIN_VPERMT2VARPS512,
29093 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29094 IX86_BUILTIN_VPERMT2VARQ512,
29095 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29096 IX86_BUILTIN_VPERMVARDF512,
29097 IX86_BUILTIN_VPERMVARDI512,
29098 IX86_BUILTIN_VPERMVARSF512,
29099 IX86_BUILTIN_VPERMVARSI512,
29100 IX86_BUILTIN_VTERNLOGD512_MASK,
29101 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29102 IX86_BUILTIN_VTERNLOGQ512_MASK,
29103 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29105 /* Mask arithmetic operations */
29106 IX86_BUILTIN_KAND16,
29107 IX86_BUILTIN_KANDN16,
29108 IX86_BUILTIN_KNOT16,
29109 IX86_BUILTIN_KOR16,
29110 IX86_BUILTIN_KORTESTC16,
29111 IX86_BUILTIN_KORTESTZ16,
29112 IX86_BUILTIN_KUNPCKBW,
29113 IX86_BUILTIN_KXNOR16,
29114 IX86_BUILTIN_KXOR16,
29115 IX86_BUILTIN_KMOV16,
29117 /* AVX512VL. */
29118 IX86_BUILTIN_PMOVUSQD256_MEM,
29119 IX86_BUILTIN_PMOVUSQD128_MEM,
29120 IX86_BUILTIN_PMOVSQD256_MEM,
29121 IX86_BUILTIN_PMOVSQD128_MEM,
29122 IX86_BUILTIN_PMOVQD256_MEM,
29123 IX86_BUILTIN_PMOVQD128_MEM,
29124 IX86_BUILTIN_PMOVUSQW256_MEM,
29125 IX86_BUILTIN_PMOVUSQW128_MEM,
29126 IX86_BUILTIN_PMOVSQW256_MEM,
29127 IX86_BUILTIN_PMOVSQW128_MEM,
29128 IX86_BUILTIN_PMOVQW256_MEM,
29129 IX86_BUILTIN_PMOVQW128_MEM,
29130 IX86_BUILTIN_PMOVUSQB256_MEM,
29131 IX86_BUILTIN_PMOVUSQB128_MEM,
29132 IX86_BUILTIN_PMOVSQB256_MEM,
29133 IX86_BUILTIN_PMOVSQB128_MEM,
29134 IX86_BUILTIN_PMOVQB256_MEM,
29135 IX86_BUILTIN_PMOVQB128_MEM,
29136 IX86_BUILTIN_PMOVUSDW256_MEM,
29137 IX86_BUILTIN_PMOVUSDW128_MEM,
29138 IX86_BUILTIN_PMOVSDW256_MEM,
29139 IX86_BUILTIN_PMOVSDW128_MEM,
29140 IX86_BUILTIN_PMOVDW256_MEM,
29141 IX86_BUILTIN_PMOVDW128_MEM,
29142 IX86_BUILTIN_PMOVUSDB256_MEM,
29143 IX86_BUILTIN_PMOVUSDB128_MEM,
29144 IX86_BUILTIN_PMOVSDB256_MEM,
29145 IX86_BUILTIN_PMOVSDB128_MEM,
29146 IX86_BUILTIN_PMOVDB256_MEM,
29147 IX86_BUILTIN_PMOVDB128_MEM,
29148 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29149 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29150 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29151 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29152 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29153 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29154 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29155 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29156 IX86_BUILTIN_LOADAPD256_MASK,
29157 IX86_BUILTIN_LOADAPD128_MASK,
29158 IX86_BUILTIN_LOADAPS256_MASK,
29159 IX86_BUILTIN_LOADAPS128_MASK,
29160 IX86_BUILTIN_STOREAPD256_MASK,
29161 IX86_BUILTIN_STOREAPD128_MASK,
29162 IX86_BUILTIN_STOREAPS256_MASK,
29163 IX86_BUILTIN_STOREAPS128_MASK,
29164 IX86_BUILTIN_LOADUPD256_MASK,
29165 IX86_BUILTIN_LOADUPD128_MASK,
29166 IX86_BUILTIN_LOADUPS256_MASK,
29167 IX86_BUILTIN_LOADUPS128_MASK,
29168 IX86_BUILTIN_STOREUPD256_MASK,
29169 IX86_BUILTIN_STOREUPD128_MASK,
29170 IX86_BUILTIN_STOREUPS256_MASK,
29171 IX86_BUILTIN_STOREUPS128_MASK,
29172 IX86_BUILTIN_LOADDQUDI256_MASK,
29173 IX86_BUILTIN_LOADDQUDI128_MASK,
29174 IX86_BUILTIN_LOADDQUSI256_MASK,
29175 IX86_BUILTIN_LOADDQUSI128_MASK,
29176 IX86_BUILTIN_LOADDQUHI256_MASK,
29177 IX86_BUILTIN_LOADDQUHI128_MASK,
29178 IX86_BUILTIN_LOADDQUQI256_MASK,
29179 IX86_BUILTIN_LOADDQUQI128_MASK,
29180 IX86_BUILTIN_STOREDQUDI256_MASK,
29181 IX86_BUILTIN_STOREDQUDI128_MASK,
29182 IX86_BUILTIN_STOREDQUSI256_MASK,
29183 IX86_BUILTIN_STOREDQUSI128_MASK,
29184 IX86_BUILTIN_STOREDQUHI256_MASK,
29185 IX86_BUILTIN_STOREDQUHI128_MASK,
29186 IX86_BUILTIN_STOREDQUQI256_MASK,
29187 IX86_BUILTIN_STOREDQUQI128_MASK,
29188 IX86_BUILTIN_COMPRESSPDSTORE256,
29189 IX86_BUILTIN_COMPRESSPDSTORE128,
29190 IX86_BUILTIN_COMPRESSPSSTORE256,
29191 IX86_BUILTIN_COMPRESSPSSTORE128,
29192 IX86_BUILTIN_PCOMPRESSQSTORE256,
29193 IX86_BUILTIN_PCOMPRESSQSTORE128,
29194 IX86_BUILTIN_PCOMPRESSDSTORE256,
29195 IX86_BUILTIN_PCOMPRESSDSTORE128,
29196 IX86_BUILTIN_EXPANDPDLOAD256,
29197 IX86_BUILTIN_EXPANDPDLOAD128,
29198 IX86_BUILTIN_EXPANDPSLOAD256,
29199 IX86_BUILTIN_EXPANDPSLOAD128,
29200 IX86_BUILTIN_PEXPANDQLOAD256,
29201 IX86_BUILTIN_PEXPANDQLOAD128,
29202 IX86_BUILTIN_PEXPANDDLOAD256,
29203 IX86_BUILTIN_PEXPANDDLOAD128,
29204 IX86_BUILTIN_EXPANDPDLOAD256Z,
29205 IX86_BUILTIN_EXPANDPDLOAD128Z,
29206 IX86_BUILTIN_EXPANDPSLOAD256Z,
29207 IX86_BUILTIN_EXPANDPSLOAD128Z,
29208 IX86_BUILTIN_PEXPANDQLOAD256Z,
29209 IX86_BUILTIN_PEXPANDQLOAD128Z,
29210 IX86_BUILTIN_PEXPANDDLOAD256Z,
29211 IX86_BUILTIN_PEXPANDDLOAD128Z,
29212 IX86_BUILTIN_PALIGNR256_MASK,
29213 IX86_BUILTIN_PALIGNR128_MASK,
29214 IX86_BUILTIN_MOVDQA64_256_MASK,
29215 IX86_BUILTIN_MOVDQA64_128_MASK,
29216 IX86_BUILTIN_MOVDQA32_256_MASK,
29217 IX86_BUILTIN_MOVDQA32_128_MASK,
29218 IX86_BUILTIN_MOVAPD256_MASK,
29219 IX86_BUILTIN_MOVAPD128_MASK,
29220 IX86_BUILTIN_MOVAPS256_MASK,
29221 IX86_BUILTIN_MOVAPS128_MASK,
29222 IX86_BUILTIN_MOVDQUHI256_MASK,
29223 IX86_BUILTIN_MOVDQUHI128_MASK,
29224 IX86_BUILTIN_MOVDQUQI256_MASK,
29225 IX86_BUILTIN_MOVDQUQI128_MASK,
29226 IX86_BUILTIN_MINPS128_MASK,
29227 IX86_BUILTIN_MAXPS128_MASK,
29228 IX86_BUILTIN_MINPD128_MASK,
29229 IX86_BUILTIN_MAXPD128_MASK,
29230 IX86_BUILTIN_MAXPD256_MASK,
29231 IX86_BUILTIN_MAXPS256_MASK,
29232 IX86_BUILTIN_MINPD256_MASK,
29233 IX86_BUILTIN_MINPS256_MASK,
29234 IX86_BUILTIN_MULPS128_MASK,
29235 IX86_BUILTIN_DIVPS128_MASK,
29236 IX86_BUILTIN_MULPD128_MASK,
29237 IX86_BUILTIN_DIVPD128_MASK,
29238 IX86_BUILTIN_DIVPD256_MASK,
29239 IX86_BUILTIN_DIVPS256_MASK,
29240 IX86_BUILTIN_MULPD256_MASK,
29241 IX86_BUILTIN_MULPS256_MASK,
29242 IX86_BUILTIN_ADDPD128_MASK,
29243 IX86_BUILTIN_ADDPD256_MASK,
29244 IX86_BUILTIN_ADDPS128_MASK,
29245 IX86_BUILTIN_ADDPS256_MASK,
29246 IX86_BUILTIN_SUBPD128_MASK,
29247 IX86_BUILTIN_SUBPD256_MASK,
29248 IX86_BUILTIN_SUBPS128_MASK,
29249 IX86_BUILTIN_SUBPS256_MASK,
29250 IX86_BUILTIN_XORPD256_MASK,
29251 IX86_BUILTIN_XORPD128_MASK,
29252 IX86_BUILTIN_XORPS256_MASK,
29253 IX86_BUILTIN_XORPS128_MASK,
29254 IX86_BUILTIN_ORPD256_MASK,
29255 IX86_BUILTIN_ORPD128_MASK,
29256 IX86_BUILTIN_ORPS256_MASK,
29257 IX86_BUILTIN_ORPS128_MASK,
29258 IX86_BUILTIN_BROADCASTF32x2_256,
29259 IX86_BUILTIN_BROADCASTI32x2_256,
29260 IX86_BUILTIN_BROADCASTI32x2_128,
29261 IX86_BUILTIN_BROADCASTF64X2_256,
29262 IX86_BUILTIN_BROADCASTI64X2_256,
29263 IX86_BUILTIN_BROADCASTF32X4_256,
29264 IX86_BUILTIN_BROADCASTI32X4_256,
29265 IX86_BUILTIN_EXTRACTF32X4_256,
29266 IX86_BUILTIN_EXTRACTI32X4_256,
29267 IX86_BUILTIN_DBPSADBW256,
29268 IX86_BUILTIN_DBPSADBW128,
29269 IX86_BUILTIN_CVTTPD2QQ256,
29270 IX86_BUILTIN_CVTTPD2QQ128,
29271 IX86_BUILTIN_CVTTPD2UQQ256,
29272 IX86_BUILTIN_CVTTPD2UQQ128,
29273 IX86_BUILTIN_CVTPD2QQ256,
29274 IX86_BUILTIN_CVTPD2QQ128,
29275 IX86_BUILTIN_CVTPD2UQQ256,
29276 IX86_BUILTIN_CVTPD2UQQ128,
29277 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29278 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29279 IX86_BUILTIN_CVTTPS2QQ256,
29280 IX86_BUILTIN_CVTTPS2QQ128,
29281 IX86_BUILTIN_CVTTPS2UQQ256,
29282 IX86_BUILTIN_CVTTPS2UQQ128,
29283 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29284 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29285 IX86_BUILTIN_CVTTPS2UDQ256,
29286 IX86_BUILTIN_CVTTPS2UDQ128,
29287 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29288 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29289 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29290 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29291 IX86_BUILTIN_CVTPD2DQ256_MASK,
29292 IX86_BUILTIN_CVTPD2DQ128_MASK,
29293 IX86_BUILTIN_CVTDQ2PD256_MASK,
29294 IX86_BUILTIN_CVTDQ2PD128_MASK,
29295 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29296 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29297 IX86_BUILTIN_CVTDQ2PS256_MASK,
29298 IX86_BUILTIN_CVTDQ2PS128_MASK,
29299 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29300 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29301 IX86_BUILTIN_CVTPS2PD256_MASK,
29302 IX86_BUILTIN_CVTPS2PD128_MASK,
29303 IX86_BUILTIN_PBROADCASTB256_MASK,
29304 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29305 IX86_BUILTIN_PBROADCASTB128_MASK,
29306 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29307 IX86_BUILTIN_PBROADCASTW256_MASK,
29308 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29309 IX86_BUILTIN_PBROADCASTW128_MASK,
29310 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29311 IX86_BUILTIN_PBROADCASTD256_MASK,
29312 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29313 IX86_BUILTIN_PBROADCASTD128_MASK,
29314 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29315 IX86_BUILTIN_PBROADCASTQ256_MASK,
29316 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29317 IX86_BUILTIN_PBROADCASTQ128_MASK,
29318 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29319 IX86_BUILTIN_BROADCASTSS256,
29320 IX86_BUILTIN_BROADCASTSS128,
29321 IX86_BUILTIN_BROADCASTSD256,
29322 IX86_BUILTIN_EXTRACTF64X2_256,
29323 IX86_BUILTIN_EXTRACTI64X2_256,
29324 IX86_BUILTIN_INSERTF32X4_256,
29325 IX86_BUILTIN_INSERTI32X4_256,
29326 IX86_BUILTIN_PMOVSXBW256_MASK,
29327 IX86_BUILTIN_PMOVSXBW128_MASK,
29328 IX86_BUILTIN_PMOVSXBD256_MASK,
29329 IX86_BUILTIN_PMOVSXBD128_MASK,
29330 IX86_BUILTIN_PMOVSXBQ256_MASK,
29331 IX86_BUILTIN_PMOVSXBQ128_MASK,
29332 IX86_BUILTIN_PMOVSXWD256_MASK,
29333 IX86_BUILTIN_PMOVSXWD128_MASK,
29334 IX86_BUILTIN_PMOVSXWQ256_MASK,
29335 IX86_BUILTIN_PMOVSXWQ128_MASK,
29336 IX86_BUILTIN_PMOVSXDQ256_MASK,
29337 IX86_BUILTIN_PMOVSXDQ128_MASK,
29338 IX86_BUILTIN_PMOVZXBW256_MASK,
29339 IX86_BUILTIN_PMOVZXBW128_MASK,
29340 IX86_BUILTIN_PMOVZXBD256_MASK,
29341 IX86_BUILTIN_PMOVZXBD128_MASK,
29342 IX86_BUILTIN_PMOVZXBQ256_MASK,
29343 IX86_BUILTIN_PMOVZXBQ128_MASK,
29344 IX86_BUILTIN_PMOVZXWD256_MASK,
29345 IX86_BUILTIN_PMOVZXWD128_MASK,
29346 IX86_BUILTIN_PMOVZXWQ256_MASK,
29347 IX86_BUILTIN_PMOVZXWQ128_MASK,
29348 IX86_BUILTIN_PMOVZXDQ256_MASK,
29349 IX86_BUILTIN_PMOVZXDQ128_MASK,
29350 IX86_BUILTIN_REDUCEPD256_MASK,
29351 IX86_BUILTIN_REDUCEPD128_MASK,
29352 IX86_BUILTIN_REDUCEPS256_MASK,
29353 IX86_BUILTIN_REDUCEPS128_MASK,
29354 IX86_BUILTIN_REDUCESD_MASK,
29355 IX86_BUILTIN_REDUCESS_MASK,
29356 IX86_BUILTIN_VPERMVARHI256_MASK,
29357 IX86_BUILTIN_VPERMVARHI128_MASK,
29358 IX86_BUILTIN_VPERMT2VARHI256,
29359 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29360 IX86_BUILTIN_VPERMT2VARHI128,
29361 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29362 IX86_BUILTIN_VPERMI2VARHI256,
29363 IX86_BUILTIN_VPERMI2VARHI128,
29364 IX86_BUILTIN_RCP14PD256,
29365 IX86_BUILTIN_RCP14PD128,
29366 IX86_BUILTIN_RCP14PS256,
29367 IX86_BUILTIN_RCP14PS128,
29368 IX86_BUILTIN_RSQRT14PD256_MASK,
29369 IX86_BUILTIN_RSQRT14PD128_MASK,
29370 IX86_BUILTIN_RSQRT14PS256_MASK,
29371 IX86_BUILTIN_RSQRT14PS128_MASK,
29372 IX86_BUILTIN_SQRTPD256_MASK,
29373 IX86_BUILTIN_SQRTPD128_MASK,
29374 IX86_BUILTIN_SQRTPS256_MASK,
29375 IX86_BUILTIN_SQRTPS128_MASK,
29376 IX86_BUILTIN_PADDB128_MASK,
29377 IX86_BUILTIN_PADDW128_MASK,
29378 IX86_BUILTIN_PADDD128_MASK,
29379 IX86_BUILTIN_PADDQ128_MASK,
29380 IX86_BUILTIN_PSUBB128_MASK,
29381 IX86_BUILTIN_PSUBW128_MASK,
29382 IX86_BUILTIN_PSUBD128_MASK,
29383 IX86_BUILTIN_PSUBQ128_MASK,
29384 IX86_BUILTIN_PADDSB128_MASK,
29385 IX86_BUILTIN_PADDSW128_MASK,
29386 IX86_BUILTIN_PSUBSB128_MASK,
29387 IX86_BUILTIN_PSUBSW128_MASK,
29388 IX86_BUILTIN_PADDUSB128_MASK,
29389 IX86_BUILTIN_PADDUSW128_MASK,
29390 IX86_BUILTIN_PSUBUSB128_MASK,
29391 IX86_BUILTIN_PSUBUSW128_MASK,
29392 IX86_BUILTIN_PADDB256_MASK,
29393 IX86_BUILTIN_PADDW256_MASK,
29394 IX86_BUILTIN_PADDD256_MASK,
29395 IX86_BUILTIN_PADDQ256_MASK,
29396 IX86_BUILTIN_PADDSB256_MASK,
29397 IX86_BUILTIN_PADDSW256_MASK,
29398 IX86_BUILTIN_PADDUSB256_MASK,
29399 IX86_BUILTIN_PADDUSW256_MASK,
29400 IX86_BUILTIN_PSUBB256_MASK,
29401 IX86_BUILTIN_PSUBW256_MASK,
29402 IX86_BUILTIN_PSUBD256_MASK,
29403 IX86_BUILTIN_PSUBQ256_MASK,
29404 IX86_BUILTIN_PSUBSB256_MASK,
29405 IX86_BUILTIN_PSUBSW256_MASK,
29406 IX86_BUILTIN_PSUBUSB256_MASK,
29407 IX86_BUILTIN_PSUBUSW256_MASK,
29408 IX86_BUILTIN_SHUF_F64x2_256,
29409 IX86_BUILTIN_SHUF_I64x2_256,
29410 IX86_BUILTIN_SHUF_I32x4_256,
29411 IX86_BUILTIN_SHUF_F32x4_256,
29412 IX86_BUILTIN_PMOVWB128,
29413 IX86_BUILTIN_PMOVWB256,
29414 IX86_BUILTIN_PMOVSWB128,
29415 IX86_BUILTIN_PMOVSWB256,
29416 IX86_BUILTIN_PMOVUSWB128,
29417 IX86_BUILTIN_PMOVUSWB256,
29418 IX86_BUILTIN_PMOVDB128,
29419 IX86_BUILTIN_PMOVDB256,
29420 IX86_BUILTIN_PMOVSDB128,
29421 IX86_BUILTIN_PMOVSDB256,
29422 IX86_BUILTIN_PMOVUSDB128,
29423 IX86_BUILTIN_PMOVUSDB256,
29424 IX86_BUILTIN_PMOVDW128,
29425 IX86_BUILTIN_PMOVDW256,
29426 IX86_BUILTIN_PMOVSDW128,
29427 IX86_BUILTIN_PMOVSDW256,
29428 IX86_BUILTIN_PMOVUSDW128,
29429 IX86_BUILTIN_PMOVUSDW256,
29430 IX86_BUILTIN_PMOVQB128,
29431 IX86_BUILTIN_PMOVQB256,
29432 IX86_BUILTIN_PMOVSQB128,
29433 IX86_BUILTIN_PMOVSQB256,
29434 IX86_BUILTIN_PMOVUSQB128,
29435 IX86_BUILTIN_PMOVUSQB256,
29436 IX86_BUILTIN_PMOVQW128,
29437 IX86_BUILTIN_PMOVQW256,
29438 IX86_BUILTIN_PMOVSQW128,
29439 IX86_BUILTIN_PMOVSQW256,
29440 IX86_BUILTIN_PMOVUSQW128,
29441 IX86_BUILTIN_PMOVUSQW256,
29442 IX86_BUILTIN_PMOVQD128,
29443 IX86_BUILTIN_PMOVQD256,
29444 IX86_BUILTIN_PMOVSQD128,
29445 IX86_BUILTIN_PMOVSQD256,
29446 IX86_BUILTIN_PMOVUSQD128,
29447 IX86_BUILTIN_PMOVUSQD256,
29448 IX86_BUILTIN_RANGEPD256,
29449 IX86_BUILTIN_RANGEPD128,
29450 IX86_BUILTIN_RANGEPS256,
29451 IX86_BUILTIN_RANGEPS128,
29452 IX86_BUILTIN_GETEXPPS256,
29453 IX86_BUILTIN_GETEXPPD256,
29454 IX86_BUILTIN_GETEXPPS128,
29455 IX86_BUILTIN_GETEXPPD128,
29456 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29457 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29458 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29459 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29460 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29461 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29462 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29463 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29464 IX86_BUILTIN_PABSQ256,
29465 IX86_BUILTIN_PABSQ128,
29466 IX86_BUILTIN_PABSD256_MASK,
29467 IX86_BUILTIN_PABSD128_MASK,
29468 IX86_BUILTIN_PMULHRSW256_MASK,
29469 IX86_BUILTIN_PMULHRSW128_MASK,
29470 IX86_BUILTIN_PMULHUW128_MASK,
29471 IX86_BUILTIN_PMULHUW256_MASK,
29472 IX86_BUILTIN_PMULHW256_MASK,
29473 IX86_BUILTIN_PMULHW128_MASK,
29474 IX86_BUILTIN_PMULLW256_MASK,
29475 IX86_BUILTIN_PMULLW128_MASK,
29476 IX86_BUILTIN_PMULLQ256,
29477 IX86_BUILTIN_PMULLQ128,
29478 IX86_BUILTIN_ANDPD256_MASK,
29479 IX86_BUILTIN_ANDPD128_MASK,
29480 IX86_BUILTIN_ANDPS256_MASK,
29481 IX86_BUILTIN_ANDPS128_MASK,
29482 IX86_BUILTIN_ANDNPD256_MASK,
29483 IX86_BUILTIN_ANDNPD128_MASK,
29484 IX86_BUILTIN_ANDNPS256_MASK,
29485 IX86_BUILTIN_ANDNPS128_MASK,
29486 IX86_BUILTIN_PSLLWI128_MASK,
29487 IX86_BUILTIN_PSLLDI128_MASK,
29488 IX86_BUILTIN_PSLLQI128_MASK,
29489 IX86_BUILTIN_PSLLW128_MASK,
29490 IX86_BUILTIN_PSLLD128_MASK,
29491 IX86_BUILTIN_PSLLQ128_MASK,
29492 IX86_BUILTIN_PSLLWI256_MASK ,
29493 IX86_BUILTIN_PSLLW256_MASK,
29494 IX86_BUILTIN_PSLLDI256_MASK,
29495 IX86_BUILTIN_PSLLD256_MASK,
29496 IX86_BUILTIN_PSLLQI256_MASK,
29497 IX86_BUILTIN_PSLLQ256_MASK,
29498 IX86_BUILTIN_PSRADI128_MASK,
29499 IX86_BUILTIN_PSRAD128_MASK,
29500 IX86_BUILTIN_PSRADI256_MASK,
29501 IX86_BUILTIN_PSRAD256_MASK,
29502 IX86_BUILTIN_PSRAQI128_MASK,
29503 IX86_BUILTIN_PSRAQ128_MASK,
29504 IX86_BUILTIN_PSRAQI256_MASK,
29505 IX86_BUILTIN_PSRAQ256_MASK,
29506 IX86_BUILTIN_PANDD256,
29507 IX86_BUILTIN_PANDD128,
29508 IX86_BUILTIN_PSRLDI128_MASK,
29509 IX86_BUILTIN_PSRLD128_MASK,
29510 IX86_BUILTIN_PSRLDI256_MASK,
29511 IX86_BUILTIN_PSRLD256_MASK,
29512 IX86_BUILTIN_PSRLQI128_MASK,
29513 IX86_BUILTIN_PSRLQ128_MASK,
29514 IX86_BUILTIN_PSRLQI256_MASK,
29515 IX86_BUILTIN_PSRLQ256_MASK,
29516 IX86_BUILTIN_PANDQ256,
29517 IX86_BUILTIN_PANDQ128,
29518 IX86_BUILTIN_PANDND256,
29519 IX86_BUILTIN_PANDND128,
29520 IX86_BUILTIN_PANDNQ256,
29521 IX86_BUILTIN_PANDNQ128,
29522 IX86_BUILTIN_PORD256,
29523 IX86_BUILTIN_PORD128,
29524 IX86_BUILTIN_PORQ256,
29525 IX86_BUILTIN_PORQ128,
29526 IX86_BUILTIN_PXORD256,
29527 IX86_BUILTIN_PXORD128,
29528 IX86_BUILTIN_PXORQ256,
29529 IX86_BUILTIN_PXORQ128,
29530 IX86_BUILTIN_PACKSSWB256_MASK,
29531 IX86_BUILTIN_PACKSSWB128_MASK,
29532 IX86_BUILTIN_PACKUSWB256_MASK,
29533 IX86_BUILTIN_PACKUSWB128_MASK,
29534 IX86_BUILTIN_RNDSCALEPS256,
29535 IX86_BUILTIN_RNDSCALEPD256,
29536 IX86_BUILTIN_RNDSCALEPS128,
29537 IX86_BUILTIN_RNDSCALEPD128,
29538 IX86_BUILTIN_VTERNLOGQ256_MASK,
29539 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29540 IX86_BUILTIN_VTERNLOGD256_MASK,
29541 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29542 IX86_BUILTIN_VTERNLOGQ128_MASK,
29543 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29544 IX86_BUILTIN_VTERNLOGD128_MASK,
29545 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29546 IX86_BUILTIN_SCALEFPD256,
29547 IX86_BUILTIN_SCALEFPS256,
29548 IX86_BUILTIN_SCALEFPD128,
29549 IX86_BUILTIN_SCALEFPS128,
29550 IX86_BUILTIN_VFMADDPD256_MASK,
29551 IX86_BUILTIN_VFMADDPD256_MASK3,
29552 IX86_BUILTIN_VFMADDPD256_MASKZ,
29553 IX86_BUILTIN_VFMADDPD128_MASK,
29554 IX86_BUILTIN_VFMADDPD128_MASK3,
29555 IX86_BUILTIN_VFMADDPD128_MASKZ,
29556 IX86_BUILTIN_VFMADDPS256_MASK,
29557 IX86_BUILTIN_VFMADDPS256_MASK3,
29558 IX86_BUILTIN_VFMADDPS256_MASKZ,
29559 IX86_BUILTIN_VFMADDPS128_MASK,
29560 IX86_BUILTIN_VFMADDPS128_MASK3,
29561 IX86_BUILTIN_VFMADDPS128_MASKZ,
29562 IX86_BUILTIN_VFMSUBPD256_MASK3,
29563 IX86_BUILTIN_VFMSUBPD128_MASK3,
29564 IX86_BUILTIN_VFMSUBPS256_MASK3,
29565 IX86_BUILTIN_VFMSUBPS128_MASK3,
29566 IX86_BUILTIN_VFNMADDPD256_MASK,
29567 IX86_BUILTIN_VFNMADDPD128_MASK,
29568 IX86_BUILTIN_VFNMADDPS256_MASK,
29569 IX86_BUILTIN_VFNMADDPS128_MASK,
29570 IX86_BUILTIN_VFNMSUBPD256_MASK,
29571 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29572 IX86_BUILTIN_VFNMSUBPD128_MASK,
29573 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29574 IX86_BUILTIN_VFNMSUBPS256_MASK,
29575 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29576 IX86_BUILTIN_VFNMSUBPS128_MASK,
29577 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29578 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29579 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29580 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29581 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29582 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29583 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29584 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29585 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29586 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29587 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29588 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29589 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29590 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29591 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29592 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29593 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29594 IX86_BUILTIN_INSERTF64X2_256,
29595 IX86_BUILTIN_INSERTI64X2_256,
29596 IX86_BUILTIN_PSRAVV16HI,
29597 IX86_BUILTIN_PSRAVV8HI,
29598 IX86_BUILTIN_PMADDUBSW256_MASK,
29599 IX86_BUILTIN_PMADDUBSW128_MASK,
29600 IX86_BUILTIN_PMADDWD256_MASK,
29601 IX86_BUILTIN_PMADDWD128_MASK,
29602 IX86_BUILTIN_PSRLVV16HI,
29603 IX86_BUILTIN_PSRLVV8HI,
29604 IX86_BUILTIN_CVTPS2DQ256_MASK,
29605 IX86_BUILTIN_CVTPS2DQ128_MASK,
29606 IX86_BUILTIN_CVTPS2UDQ256,
29607 IX86_BUILTIN_CVTPS2UDQ128,
29608 IX86_BUILTIN_CVTPS2QQ256,
29609 IX86_BUILTIN_CVTPS2QQ128,
29610 IX86_BUILTIN_CVTPS2UQQ256,
29611 IX86_BUILTIN_CVTPS2UQQ128,
29612 IX86_BUILTIN_GETMANTPS256,
29613 IX86_BUILTIN_GETMANTPS128,
29614 IX86_BUILTIN_GETMANTPD256,
29615 IX86_BUILTIN_GETMANTPD128,
29616 IX86_BUILTIN_MOVDDUP256_MASK,
29617 IX86_BUILTIN_MOVDDUP128_MASK,
29618 IX86_BUILTIN_MOVSHDUP256_MASK,
29619 IX86_BUILTIN_MOVSHDUP128_MASK,
29620 IX86_BUILTIN_MOVSLDUP256_MASK,
29621 IX86_BUILTIN_MOVSLDUP128_MASK,
29622 IX86_BUILTIN_CVTQQ2PS256,
29623 IX86_BUILTIN_CVTQQ2PS128,
29624 IX86_BUILTIN_CVTUQQ2PS256,
29625 IX86_BUILTIN_CVTUQQ2PS128,
29626 IX86_BUILTIN_CVTQQ2PD256,
29627 IX86_BUILTIN_CVTQQ2PD128,
29628 IX86_BUILTIN_CVTUQQ2PD256,
29629 IX86_BUILTIN_CVTUQQ2PD128,
29630 IX86_BUILTIN_VPERMT2VARQ256,
29631 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29632 IX86_BUILTIN_VPERMT2VARD256,
29633 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29634 IX86_BUILTIN_VPERMI2VARQ256,
29635 IX86_BUILTIN_VPERMI2VARD256,
29636 IX86_BUILTIN_VPERMT2VARPD256,
29637 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29638 IX86_BUILTIN_VPERMT2VARPS256,
29639 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29640 IX86_BUILTIN_VPERMI2VARPD256,
29641 IX86_BUILTIN_VPERMI2VARPS256,
29642 IX86_BUILTIN_VPERMT2VARQ128,
29643 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29644 IX86_BUILTIN_VPERMT2VARD128,
29645 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29646 IX86_BUILTIN_VPERMI2VARQ128,
29647 IX86_BUILTIN_VPERMI2VARD128,
29648 IX86_BUILTIN_VPERMT2VARPD128,
29649 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29650 IX86_BUILTIN_VPERMT2VARPS128,
29651 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29652 IX86_BUILTIN_VPERMI2VARPD128,
29653 IX86_BUILTIN_VPERMI2VARPS128,
29654 IX86_BUILTIN_PSHUFB256_MASK,
29655 IX86_BUILTIN_PSHUFB128_MASK,
29656 IX86_BUILTIN_PSHUFHW256_MASK,
29657 IX86_BUILTIN_PSHUFHW128_MASK,
29658 IX86_BUILTIN_PSHUFLW256_MASK,
29659 IX86_BUILTIN_PSHUFLW128_MASK,
29660 IX86_BUILTIN_PSHUFD256_MASK,
29661 IX86_BUILTIN_PSHUFD128_MASK,
29662 IX86_BUILTIN_SHUFPD256_MASK,
29663 IX86_BUILTIN_SHUFPD128_MASK,
29664 IX86_BUILTIN_SHUFPS256_MASK,
29665 IX86_BUILTIN_SHUFPS128_MASK,
29666 IX86_BUILTIN_PROLVQ256,
29667 IX86_BUILTIN_PROLVQ128,
29668 IX86_BUILTIN_PROLQ256,
29669 IX86_BUILTIN_PROLQ128,
29670 IX86_BUILTIN_PRORVQ256,
29671 IX86_BUILTIN_PRORVQ128,
29672 IX86_BUILTIN_PRORQ256,
29673 IX86_BUILTIN_PRORQ128,
29674 IX86_BUILTIN_PSRAVQ128,
29675 IX86_BUILTIN_PSRAVQ256,
29676 IX86_BUILTIN_PSLLVV4DI_MASK,
29677 IX86_BUILTIN_PSLLVV2DI_MASK,
29678 IX86_BUILTIN_PSLLVV8SI_MASK,
29679 IX86_BUILTIN_PSLLVV4SI_MASK,
29680 IX86_BUILTIN_PSRAVV8SI_MASK,
29681 IX86_BUILTIN_PSRAVV4SI_MASK,
29682 IX86_BUILTIN_PSRLVV4DI_MASK,
29683 IX86_BUILTIN_PSRLVV2DI_MASK,
29684 IX86_BUILTIN_PSRLVV8SI_MASK,
29685 IX86_BUILTIN_PSRLVV4SI_MASK,
29686 IX86_BUILTIN_PSRAWI256_MASK,
29687 IX86_BUILTIN_PSRAW256_MASK,
29688 IX86_BUILTIN_PSRAWI128_MASK,
29689 IX86_BUILTIN_PSRAW128_MASK,
29690 IX86_BUILTIN_PSRLWI256_MASK,
29691 IX86_BUILTIN_PSRLW256_MASK,
29692 IX86_BUILTIN_PSRLWI128_MASK,
29693 IX86_BUILTIN_PSRLW128_MASK,
29694 IX86_BUILTIN_PRORVD256,
29695 IX86_BUILTIN_PROLVD256,
29696 IX86_BUILTIN_PRORD256,
29697 IX86_BUILTIN_PROLD256,
29698 IX86_BUILTIN_PRORVD128,
29699 IX86_BUILTIN_PROLVD128,
29700 IX86_BUILTIN_PRORD128,
29701 IX86_BUILTIN_PROLD128,
29702 IX86_BUILTIN_FPCLASSPD256,
29703 IX86_BUILTIN_FPCLASSPD128,
29704 IX86_BUILTIN_FPCLASSSD,
29705 IX86_BUILTIN_FPCLASSPS256,
29706 IX86_BUILTIN_FPCLASSPS128,
29707 IX86_BUILTIN_FPCLASSSS,
29708 IX86_BUILTIN_CVTB2MASK128,
29709 IX86_BUILTIN_CVTB2MASK256,
29710 IX86_BUILTIN_CVTW2MASK128,
29711 IX86_BUILTIN_CVTW2MASK256,
29712 IX86_BUILTIN_CVTD2MASK128,
29713 IX86_BUILTIN_CVTD2MASK256,
29714 IX86_BUILTIN_CVTQ2MASK128,
29715 IX86_BUILTIN_CVTQ2MASK256,
29716 IX86_BUILTIN_CVTMASK2B128,
29717 IX86_BUILTIN_CVTMASK2B256,
29718 IX86_BUILTIN_CVTMASK2W128,
29719 IX86_BUILTIN_CVTMASK2W256,
29720 IX86_BUILTIN_CVTMASK2D128,
29721 IX86_BUILTIN_CVTMASK2D256,
29722 IX86_BUILTIN_CVTMASK2Q128,
29723 IX86_BUILTIN_CVTMASK2Q256,
29724 IX86_BUILTIN_PCMPEQB128_MASK,
29725 IX86_BUILTIN_PCMPEQB256_MASK,
29726 IX86_BUILTIN_PCMPEQW128_MASK,
29727 IX86_BUILTIN_PCMPEQW256_MASK,
29728 IX86_BUILTIN_PCMPEQD128_MASK,
29729 IX86_BUILTIN_PCMPEQD256_MASK,
29730 IX86_BUILTIN_PCMPEQQ128_MASK,
29731 IX86_BUILTIN_PCMPEQQ256_MASK,
29732 IX86_BUILTIN_PCMPGTB128_MASK,
29733 IX86_BUILTIN_PCMPGTB256_MASK,
29734 IX86_BUILTIN_PCMPGTW128_MASK,
29735 IX86_BUILTIN_PCMPGTW256_MASK,
29736 IX86_BUILTIN_PCMPGTD128_MASK,
29737 IX86_BUILTIN_PCMPGTD256_MASK,
29738 IX86_BUILTIN_PCMPGTQ128_MASK,
29739 IX86_BUILTIN_PCMPGTQ256_MASK,
29740 IX86_BUILTIN_PTESTMB128,
29741 IX86_BUILTIN_PTESTMB256,
29742 IX86_BUILTIN_PTESTMW128,
29743 IX86_BUILTIN_PTESTMW256,
29744 IX86_BUILTIN_PTESTMD128,
29745 IX86_BUILTIN_PTESTMD256,
29746 IX86_BUILTIN_PTESTMQ128,
29747 IX86_BUILTIN_PTESTMQ256,
29748 IX86_BUILTIN_PTESTNMB128,
29749 IX86_BUILTIN_PTESTNMB256,
29750 IX86_BUILTIN_PTESTNMW128,
29751 IX86_BUILTIN_PTESTNMW256,
29752 IX86_BUILTIN_PTESTNMD128,
29753 IX86_BUILTIN_PTESTNMD256,
29754 IX86_BUILTIN_PTESTNMQ128,
29755 IX86_BUILTIN_PTESTNMQ256,
29756 IX86_BUILTIN_PBROADCASTMB128,
29757 IX86_BUILTIN_PBROADCASTMB256,
29758 IX86_BUILTIN_PBROADCASTMW128,
29759 IX86_BUILTIN_PBROADCASTMW256,
29760 IX86_BUILTIN_COMPRESSPD256,
29761 IX86_BUILTIN_COMPRESSPD128,
29762 IX86_BUILTIN_COMPRESSPS256,
29763 IX86_BUILTIN_COMPRESSPS128,
29764 IX86_BUILTIN_PCOMPRESSQ256,
29765 IX86_BUILTIN_PCOMPRESSQ128,
29766 IX86_BUILTIN_PCOMPRESSD256,
29767 IX86_BUILTIN_PCOMPRESSD128,
29768 IX86_BUILTIN_EXPANDPD256,
29769 IX86_BUILTIN_EXPANDPD128,
29770 IX86_BUILTIN_EXPANDPS256,
29771 IX86_BUILTIN_EXPANDPS128,
29772 IX86_BUILTIN_PEXPANDQ256,
29773 IX86_BUILTIN_PEXPANDQ128,
29774 IX86_BUILTIN_PEXPANDD256,
29775 IX86_BUILTIN_PEXPANDD128,
29776 IX86_BUILTIN_EXPANDPD256Z,
29777 IX86_BUILTIN_EXPANDPD128Z,
29778 IX86_BUILTIN_EXPANDPS256Z,
29779 IX86_BUILTIN_EXPANDPS128Z,
29780 IX86_BUILTIN_PEXPANDQ256Z,
29781 IX86_BUILTIN_PEXPANDQ128Z,
29782 IX86_BUILTIN_PEXPANDD256Z,
29783 IX86_BUILTIN_PEXPANDD128Z,
29784 IX86_BUILTIN_PMAXSD256_MASK,
29785 IX86_BUILTIN_PMINSD256_MASK,
29786 IX86_BUILTIN_PMAXUD256_MASK,
29787 IX86_BUILTIN_PMINUD256_MASK,
29788 IX86_BUILTIN_PMAXSD128_MASK,
29789 IX86_BUILTIN_PMINSD128_MASK,
29790 IX86_BUILTIN_PMAXUD128_MASK,
29791 IX86_BUILTIN_PMINUD128_MASK,
29792 IX86_BUILTIN_PMAXSQ256_MASK,
29793 IX86_BUILTIN_PMINSQ256_MASK,
29794 IX86_BUILTIN_PMAXUQ256_MASK,
29795 IX86_BUILTIN_PMINUQ256_MASK,
29796 IX86_BUILTIN_PMAXSQ128_MASK,
29797 IX86_BUILTIN_PMINSQ128_MASK,
29798 IX86_BUILTIN_PMAXUQ128_MASK,
29799 IX86_BUILTIN_PMINUQ128_MASK,
29800 IX86_BUILTIN_PMINSB256_MASK,
29801 IX86_BUILTIN_PMINUB256_MASK,
29802 IX86_BUILTIN_PMAXSB256_MASK,
29803 IX86_BUILTIN_PMAXUB256_MASK,
29804 IX86_BUILTIN_PMINSB128_MASK,
29805 IX86_BUILTIN_PMINUB128_MASK,
29806 IX86_BUILTIN_PMAXSB128_MASK,
29807 IX86_BUILTIN_PMAXUB128_MASK,
29808 IX86_BUILTIN_PMINSW256_MASK,
29809 IX86_BUILTIN_PMINUW256_MASK,
29810 IX86_BUILTIN_PMAXSW256_MASK,
29811 IX86_BUILTIN_PMAXUW256_MASK,
29812 IX86_BUILTIN_PMINSW128_MASK,
29813 IX86_BUILTIN_PMINUW128_MASK,
29814 IX86_BUILTIN_PMAXSW128_MASK,
29815 IX86_BUILTIN_PMAXUW128_MASK,
29816 IX86_BUILTIN_VPCONFLICTQ256,
29817 IX86_BUILTIN_VPCONFLICTD256,
29818 IX86_BUILTIN_VPCLZCNTQ256,
29819 IX86_BUILTIN_VPCLZCNTD256,
29820 IX86_BUILTIN_UNPCKHPD256_MASK,
29821 IX86_BUILTIN_UNPCKHPD128_MASK,
29822 IX86_BUILTIN_UNPCKHPS256_MASK,
29823 IX86_BUILTIN_UNPCKHPS128_MASK,
29824 IX86_BUILTIN_UNPCKLPD256_MASK,
29825 IX86_BUILTIN_UNPCKLPD128_MASK,
29826 IX86_BUILTIN_UNPCKLPS256_MASK,
29827 IX86_BUILTIN_VPCONFLICTQ128,
29828 IX86_BUILTIN_VPCONFLICTD128,
29829 IX86_BUILTIN_VPCLZCNTQ128,
29830 IX86_BUILTIN_VPCLZCNTD128,
29831 IX86_BUILTIN_UNPCKLPS128_MASK,
29832 IX86_BUILTIN_ALIGND256,
29833 IX86_BUILTIN_ALIGNQ256,
29834 IX86_BUILTIN_ALIGND128,
29835 IX86_BUILTIN_ALIGNQ128,
29836 IX86_BUILTIN_CVTPS2PH256_MASK,
29837 IX86_BUILTIN_CVTPS2PH_MASK,
29838 IX86_BUILTIN_CVTPH2PS_MASK,
29839 IX86_BUILTIN_CVTPH2PS256_MASK,
29840 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29841 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29842 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29843 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29844 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29845 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29846 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29847 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29848 IX86_BUILTIN_PUNPCKHBW128_MASK,
29849 IX86_BUILTIN_PUNPCKHBW256_MASK,
29850 IX86_BUILTIN_PUNPCKHWD128_MASK,
29851 IX86_BUILTIN_PUNPCKHWD256_MASK,
29852 IX86_BUILTIN_PUNPCKLBW128_MASK,
29853 IX86_BUILTIN_PUNPCKLBW256_MASK,
29854 IX86_BUILTIN_PUNPCKLWD128_MASK,
29855 IX86_BUILTIN_PUNPCKLWD256_MASK,
29856 IX86_BUILTIN_PSLLVV16HI,
29857 IX86_BUILTIN_PSLLVV8HI,
29858 IX86_BUILTIN_PACKSSDW256_MASK,
29859 IX86_BUILTIN_PACKSSDW128_MASK,
29860 IX86_BUILTIN_PACKUSDW256_MASK,
29861 IX86_BUILTIN_PACKUSDW128_MASK,
29862 IX86_BUILTIN_PAVGB256_MASK,
29863 IX86_BUILTIN_PAVGW256_MASK,
29864 IX86_BUILTIN_PAVGB128_MASK,
29865 IX86_BUILTIN_PAVGW128_MASK,
29866 IX86_BUILTIN_VPERMVARSF256_MASK,
29867 IX86_BUILTIN_VPERMVARDF256_MASK,
29868 IX86_BUILTIN_VPERMDF256_MASK,
29869 IX86_BUILTIN_PABSB256_MASK,
29870 IX86_BUILTIN_PABSB128_MASK,
29871 IX86_BUILTIN_PABSW256_MASK,
29872 IX86_BUILTIN_PABSW128_MASK,
29873 IX86_BUILTIN_VPERMILVARPD_MASK,
29874 IX86_BUILTIN_VPERMILVARPS_MASK,
29875 IX86_BUILTIN_VPERMILVARPD256_MASK,
29876 IX86_BUILTIN_VPERMILVARPS256_MASK,
29877 IX86_BUILTIN_VPERMILPD_MASK,
29878 IX86_BUILTIN_VPERMILPS_MASK,
29879 IX86_BUILTIN_VPERMILPD256_MASK,
29880 IX86_BUILTIN_VPERMILPS256_MASK,
29881 IX86_BUILTIN_BLENDMQ256,
29882 IX86_BUILTIN_BLENDMD256,
29883 IX86_BUILTIN_BLENDMPD256,
29884 IX86_BUILTIN_BLENDMPS256,
29885 IX86_BUILTIN_BLENDMQ128,
29886 IX86_BUILTIN_BLENDMD128,
29887 IX86_BUILTIN_BLENDMPD128,
29888 IX86_BUILTIN_BLENDMPS128,
29889 IX86_BUILTIN_BLENDMW256,
29890 IX86_BUILTIN_BLENDMB256,
29891 IX86_BUILTIN_BLENDMW128,
29892 IX86_BUILTIN_BLENDMB128,
29893 IX86_BUILTIN_PMULLD256_MASK,
29894 IX86_BUILTIN_PMULLD128_MASK,
29895 IX86_BUILTIN_PMULUDQ256_MASK,
29896 IX86_BUILTIN_PMULDQ256_MASK,
29897 IX86_BUILTIN_PMULDQ128_MASK,
29898 IX86_BUILTIN_PMULUDQ128_MASK,
29899 IX86_BUILTIN_CVTPD2PS256_MASK,
29900 IX86_BUILTIN_CVTPD2PS_MASK,
29901 IX86_BUILTIN_VPERMVARSI256_MASK,
29902 IX86_BUILTIN_VPERMVARDI256_MASK,
29903 IX86_BUILTIN_VPERMDI256_MASK,
29904 IX86_BUILTIN_CMPQ256,
29905 IX86_BUILTIN_CMPD256,
29906 IX86_BUILTIN_UCMPQ256,
29907 IX86_BUILTIN_UCMPD256,
29908 IX86_BUILTIN_CMPB256,
29909 IX86_BUILTIN_CMPW256,
29910 IX86_BUILTIN_UCMPB256,
29911 IX86_BUILTIN_UCMPW256,
29912 IX86_BUILTIN_CMPPD256_MASK,
29913 IX86_BUILTIN_CMPPS256_MASK,
29914 IX86_BUILTIN_CMPQ128,
29915 IX86_BUILTIN_CMPD128,
29916 IX86_BUILTIN_UCMPQ128,
29917 IX86_BUILTIN_UCMPD128,
29918 IX86_BUILTIN_CMPB128,
29919 IX86_BUILTIN_CMPW128,
29920 IX86_BUILTIN_UCMPB128,
29921 IX86_BUILTIN_UCMPW128,
29922 IX86_BUILTIN_CMPPD128_MASK,
29923 IX86_BUILTIN_CMPPS128_MASK,
29925 IX86_BUILTIN_GATHER3SIV8SF,
29926 IX86_BUILTIN_GATHER3SIV4SF,
29927 IX86_BUILTIN_GATHER3SIV4DF,
29928 IX86_BUILTIN_GATHER3SIV2DF,
29929 IX86_BUILTIN_GATHER3DIV8SF,
29930 IX86_BUILTIN_GATHER3DIV4SF,
29931 IX86_BUILTIN_GATHER3DIV4DF,
29932 IX86_BUILTIN_GATHER3DIV2DF,
29933 IX86_BUILTIN_GATHER3SIV8SI,
29934 IX86_BUILTIN_GATHER3SIV4SI,
29935 IX86_BUILTIN_GATHER3SIV4DI,
29936 IX86_BUILTIN_GATHER3SIV2DI,
29937 IX86_BUILTIN_GATHER3DIV8SI,
29938 IX86_BUILTIN_GATHER3DIV4SI,
29939 IX86_BUILTIN_GATHER3DIV4DI,
29940 IX86_BUILTIN_GATHER3DIV2DI,
29941 IX86_BUILTIN_SCATTERSIV8SF,
29942 IX86_BUILTIN_SCATTERSIV4SF,
29943 IX86_BUILTIN_SCATTERSIV4DF,
29944 IX86_BUILTIN_SCATTERSIV2DF,
29945 IX86_BUILTIN_SCATTERDIV8SF,
29946 IX86_BUILTIN_SCATTERDIV4SF,
29947 IX86_BUILTIN_SCATTERDIV4DF,
29948 IX86_BUILTIN_SCATTERDIV2DF,
29949 IX86_BUILTIN_SCATTERSIV8SI,
29950 IX86_BUILTIN_SCATTERSIV4SI,
29951 IX86_BUILTIN_SCATTERSIV4DI,
29952 IX86_BUILTIN_SCATTERSIV2DI,
29953 IX86_BUILTIN_SCATTERDIV8SI,
29954 IX86_BUILTIN_SCATTERDIV4SI,
29955 IX86_BUILTIN_SCATTERDIV4DI,
29956 IX86_BUILTIN_SCATTERDIV2DI,
29958 /* AVX512DQ. */
29959 IX86_BUILTIN_RANGESD128,
29960 IX86_BUILTIN_RANGESS128,
29961 IX86_BUILTIN_KUNPCKWD,
29962 IX86_BUILTIN_KUNPCKDQ,
29963 IX86_BUILTIN_BROADCASTF32x2_512,
29964 IX86_BUILTIN_BROADCASTI32x2_512,
29965 IX86_BUILTIN_BROADCASTF64X2_512,
29966 IX86_BUILTIN_BROADCASTI64X2_512,
29967 IX86_BUILTIN_BROADCASTF32X8_512,
29968 IX86_BUILTIN_BROADCASTI32X8_512,
29969 IX86_BUILTIN_EXTRACTF64X2_512,
29970 IX86_BUILTIN_EXTRACTF32X8,
29971 IX86_BUILTIN_EXTRACTI64X2_512,
29972 IX86_BUILTIN_EXTRACTI32X8,
29973 IX86_BUILTIN_REDUCEPD512_MASK,
29974 IX86_BUILTIN_REDUCEPS512_MASK,
29975 IX86_BUILTIN_PMULLQ512,
29976 IX86_BUILTIN_XORPD512,
29977 IX86_BUILTIN_XORPS512,
29978 IX86_BUILTIN_ORPD512,
29979 IX86_BUILTIN_ORPS512,
29980 IX86_BUILTIN_ANDPD512,
29981 IX86_BUILTIN_ANDPS512,
29982 IX86_BUILTIN_ANDNPD512,
29983 IX86_BUILTIN_ANDNPS512,
29984 IX86_BUILTIN_INSERTF32X8,
29985 IX86_BUILTIN_INSERTI32X8,
29986 IX86_BUILTIN_INSERTF64X2_512,
29987 IX86_BUILTIN_INSERTI64X2_512,
29988 IX86_BUILTIN_FPCLASSPD512,
29989 IX86_BUILTIN_FPCLASSPS512,
29990 IX86_BUILTIN_CVTD2MASK512,
29991 IX86_BUILTIN_CVTQ2MASK512,
29992 IX86_BUILTIN_CVTMASK2D512,
29993 IX86_BUILTIN_CVTMASK2Q512,
29994 IX86_BUILTIN_CVTPD2QQ512,
29995 IX86_BUILTIN_CVTPS2QQ512,
29996 IX86_BUILTIN_CVTPD2UQQ512,
29997 IX86_BUILTIN_CVTPS2UQQ512,
29998 IX86_BUILTIN_CVTQQ2PS512,
29999 IX86_BUILTIN_CVTUQQ2PS512,
30000 IX86_BUILTIN_CVTQQ2PD512,
30001 IX86_BUILTIN_CVTUQQ2PD512,
30002 IX86_BUILTIN_CVTTPS2QQ512,
30003 IX86_BUILTIN_CVTTPS2UQQ512,
30004 IX86_BUILTIN_CVTTPD2QQ512,
30005 IX86_BUILTIN_CVTTPD2UQQ512,
30006 IX86_BUILTIN_RANGEPS512,
30007 IX86_BUILTIN_RANGEPD512,
30009 /* AVX512BW. */
30010 IX86_BUILTIN_PACKUSDW512,
30011 IX86_BUILTIN_PACKSSDW512,
30012 IX86_BUILTIN_LOADDQUHI512_MASK,
30013 IX86_BUILTIN_LOADDQUQI512_MASK,
30014 IX86_BUILTIN_PSLLDQ512,
30015 IX86_BUILTIN_PSRLDQ512,
30016 IX86_BUILTIN_STOREDQUHI512_MASK,
30017 IX86_BUILTIN_STOREDQUQI512_MASK,
30018 IX86_BUILTIN_PALIGNR512,
30019 IX86_BUILTIN_PALIGNR512_MASK,
30020 IX86_BUILTIN_MOVDQUHI512_MASK,
30021 IX86_BUILTIN_MOVDQUQI512_MASK,
30022 IX86_BUILTIN_PSADBW512,
30023 IX86_BUILTIN_DBPSADBW512,
30024 IX86_BUILTIN_PBROADCASTB512,
30025 IX86_BUILTIN_PBROADCASTB512_GPR,
30026 IX86_BUILTIN_PBROADCASTW512,
30027 IX86_BUILTIN_PBROADCASTW512_GPR,
30028 IX86_BUILTIN_PMOVSXBW512_MASK,
30029 IX86_BUILTIN_PMOVZXBW512_MASK,
30030 IX86_BUILTIN_VPERMVARHI512_MASK,
30031 IX86_BUILTIN_VPERMT2VARHI512,
30032 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30033 IX86_BUILTIN_VPERMI2VARHI512,
30034 IX86_BUILTIN_PAVGB512,
30035 IX86_BUILTIN_PAVGW512,
30036 IX86_BUILTIN_PADDB512,
30037 IX86_BUILTIN_PSUBB512,
30038 IX86_BUILTIN_PSUBSB512,
30039 IX86_BUILTIN_PADDSB512,
30040 IX86_BUILTIN_PSUBUSB512,
30041 IX86_BUILTIN_PADDUSB512,
30042 IX86_BUILTIN_PSUBW512,
30043 IX86_BUILTIN_PADDW512,
30044 IX86_BUILTIN_PSUBSW512,
30045 IX86_BUILTIN_PADDSW512,
30046 IX86_BUILTIN_PSUBUSW512,
30047 IX86_BUILTIN_PADDUSW512,
30048 IX86_BUILTIN_PMAXUW512,
30049 IX86_BUILTIN_PMAXSW512,
30050 IX86_BUILTIN_PMINUW512,
30051 IX86_BUILTIN_PMINSW512,
30052 IX86_BUILTIN_PMAXUB512,
30053 IX86_BUILTIN_PMAXSB512,
30054 IX86_BUILTIN_PMINUB512,
30055 IX86_BUILTIN_PMINSB512,
30056 IX86_BUILTIN_PMOVWB512,
30057 IX86_BUILTIN_PMOVSWB512,
30058 IX86_BUILTIN_PMOVUSWB512,
30059 IX86_BUILTIN_PMULHRSW512_MASK,
30060 IX86_BUILTIN_PMULHUW512_MASK,
30061 IX86_BUILTIN_PMULHW512_MASK,
30062 IX86_BUILTIN_PMULLW512_MASK,
30063 IX86_BUILTIN_PSLLWI512_MASK,
30064 IX86_BUILTIN_PSLLW512_MASK,
30065 IX86_BUILTIN_PACKSSWB512,
30066 IX86_BUILTIN_PACKUSWB512,
30067 IX86_BUILTIN_PSRAVV32HI,
30068 IX86_BUILTIN_PMADDUBSW512_MASK,
30069 IX86_BUILTIN_PMADDWD512_MASK,
30070 IX86_BUILTIN_PSRLVV32HI,
30071 IX86_BUILTIN_PUNPCKHBW512,
30072 IX86_BUILTIN_PUNPCKHWD512,
30073 IX86_BUILTIN_PUNPCKLBW512,
30074 IX86_BUILTIN_PUNPCKLWD512,
30075 IX86_BUILTIN_PSHUFB512,
30076 IX86_BUILTIN_PSHUFHW512,
30077 IX86_BUILTIN_PSHUFLW512,
30078 IX86_BUILTIN_PSRAWI512,
30079 IX86_BUILTIN_PSRAW512,
30080 IX86_BUILTIN_PSRLWI512,
30081 IX86_BUILTIN_PSRLW512,
30082 IX86_BUILTIN_CVTB2MASK512,
30083 IX86_BUILTIN_CVTW2MASK512,
30084 IX86_BUILTIN_CVTMASK2B512,
30085 IX86_BUILTIN_CVTMASK2W512,
30086 IX86_BUILTIN_PCMPEQB512_MASK,
30087 IX86_BUILTIN_PCMPEQW512_MASK,
30088 IX86_BUILTIN_PCMPGTB512_MASK,
30089 IX86_BUILTIN_PCMPGTW512_MASK,
30090 IX86_BUILTIN_PTESTMB512,
30091 IX86_BUILTIN_PTESTMW512,
30092 IX86_BUILTIN_PTESTNMB512,
30093 IX86_BUILTIN_PTESTNMW512,
30094 IX86_BUILTIN_PSLLVV32HI,
30095 IX86_BUILTIN_PABSB512,
30096 IX86_BUILTIN_PABSW512,
30097 IX86_BUILTIN_BLENDMW512,
30098 IX86_BUILTIN_BLENDMB512,
30099 IX86_BUILTIN_CMPB512,
30100 IX86_BUILTIN_CMPW512,
30101 IX86_BUILTIN_UCMPB512,
30102 IX86_BUILTIN_UCMPW512,
30104 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30105 where all operands are 32-byte or 64-byte wide respectively. */
30106 IX86_BUILTIN_GATHERALTSIV4DF,
30107 IX86_BUILTIN_GATHERALTDIV8SF,
30108 IX86_BUILTIN_GATHERALTSIV4DI,
30109 IX86_BUILTIN_GATHERALTDIV8SI,
30110 IX86_BUILTIN_GATHER3ALTDIV16SF,
30111 IX86_BUILTIN_GATHER3ALTDIV16SI,
30112 IX86_BUILTIN_GATHER3ALTSIV4DF,
30113 IX86_BUILTIN_GATHER3ALTDIV8SF,
30114 IX86_BUILTIN_GATHER3ALTSIV4DI,
30115 IX86_BUILTIN_GATHER3ALTDIV8SI,
30116 IX86_BUILTIN_GATHER3ALTSIV8DF,
30117 IX86_BUILTIN_GATHER3ALTSIV8DI,
30118 IX86_BUILTIN_GATHER3DIV16SF,
30119 IX86_BUILTIN_GATHER3DIV16SI,
30120 IX86_BUILTIN_GATHER3DIV8DF,
30121 IX86_BUILTIN_GATHER3DIV8DI,
30122 IX86_BUILTIN_GATHER3SIV16SF,
30123 IX86_BUILTIN_GATHER3SIV16SI,
30124 IX86_BUILTIN_GATHER3SIV8DF,
30125 IX86_BUILTIN_GATHER3SIV8DI,
30126 IX86_BUILTIN_SCATTERDIV16SF,
30127 IX86_BUILTIN_SCATTERDIV16SI,
30128 IX86_BUILTIN_SCATTERDIV8DF,
30129 IX86_BUILTIN_SCATTERDIV8DI,
30130 IX86_BUILTIN_SCATTERSIV16SF,
30131 IX86_BUILTIN_SCATTERSIV16SI,
30132 IX86_BUILTIN_SCATTERSIV8DF,
30133 IX86_BUILTIN_SCATTERSIV8DI,
30135 /* AVX512PF */
30136 IX86_BUILTIN_GATHERPFQPD,
30137 IX86_BUILTIN_GATHERPFDPS,
30138 IX86_BUILTIN_GATHERPFDPD,
30139 IX86_BUILTIN_GATHERPFQPS,
30140 IX86_BUILTIN_SCATTERPFDPD,
30141 IX86_BUILTIN_SCATTERPFDPS,
30142 IX86_BUILTIN_SCATTERPFQPD,
30143 IX86_BUILTIN_SCATTERPFQPS,
30145 /* AVX-512ER */
30146 IX86_BUILTIN_EXP2PD_MASK,
30147 IX86_BUILTIN_EXP2PS_MASK,
30148 IX86_BUILTIN_EXP2PS,
30149 IX86_BUILTIN_RCP28PD,
30150 IX86_BUILTIN_RCP28PS,
30151 IX86_BUILTIN_RCP28SD,
30152 IX86_BUILTIN_RCP28SS,
30153 IX86_BUILTIN_RSQRT28PD,
30154 IX86_BUILTIN_RSQRT28PS,
30155 IX86_BUILTIN_RSQRT28SD,
30156 IX86_BUILTIN_RSQRT28SS,
30158 /* AVX-512IFMA */
30159 IX86_BUILTIN_VPMADD52LUQ512,
30160 IX86_BUILTIN_VPMADD52HUQ512,
30161 IX86_BUILTIN_VPMADD52LUQ256,
30162 IX86_BUILTIN_VPMADD52HUQ256,
30163 IX86_BUILTIN_VPMADD52LUQ128,
30164 IX86_BUILTIN_VPMADD52HUQ128,
30165 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30166 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30167 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30168 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30169 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30170 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30172 /* AVX-512VBMI */
30173 IX86_BUILTIN_VPMULTISHIFTQB512,
30174 IX86_BUILTIN_VPMULTISHIFTQB256,
30175 IX86_BUILTIN_VPMULTISHIFTQB128,
30176 IX86_BUILTIN_VPERMVARQI512_MASK,
30177 IX86_BUILTIN_VPERMT2VARQI512,
30178 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30179 IX86_BUILTIN_VPERMI2VARQI512,
30180 IX86_BUILTIN_VPERMVARQI256_MASK,
30181 IX86_BUILTIN_VPERMVARQI128_MASK,
30182 IX86_BUILTIN_VPERMT2VARQI256,
30183 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30184 IX86_BUILTIN_VPERMT2VARQI128,
30185 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30186 IX86_BUILTIN_VPERMI2VARQI256,
30187 IX86_BUILTIN_VPERMI2VARQI128,
30189 /* SHA builtins. */
30190 IX86_BUILTIN_SHA1MSG1,
30191 IX86_BUILTIN_SHA1MSG2,
30192 IX86_BUILTIN_SHA1NEXTE,
30193 IX86_BUILTIN_SHA1RNDS4,
30194 IX86_BUILTIN_SHA256MSG1,
30195 IX86_BUILTIN_SHA256MSG2,
30196 IX86_BUILTIN_SHA256RNDS2,
30198 /* CLWB instructions. */
30199 IX86_BUILTIN_CLWB,
30201 /* PCOMMIT instructions. */
30202 IX86_BUILTIN_PCOMMIT,
30204 /* CLFLUSHOPT instructions. */
30205 IX86_BUILTIN_CLFLUSHOPT,
30207 /* TFmode support builtins. */
30208 IX86_BUILTIN_INFQ,
30209 IX86_BUILTIN_HUGE_VALQ,
30210 IX86_BUILTIN_FABSQ,
30211 IX86_BUILTIN_COPYSIGNQ,
30213 /* Vectorizer support builtins. */
30214 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30215 IX86_BUILTIN_CPYSGNPS,
30216 IX86_BUILTIN_CPYSGNPD,
30217 IX86_BUILTIN_CPYSGNPS256,
30218 IX86_BUILTIN_CPYSGNPS512,
30219 IX86_BUILTIN_CPYSGNPD256,
30220 IX86_BUILTIN_CPYSGNPD512,
30221 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30222 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30225 /* FMA4 instructions. */
30226 IX86_BUILTIN_VFMADDSS,
30227 IX86_BUILTIN_VFMADDSD,
30228 IX86_BUILTIN_VFMADDPS,
30229 IX86_BUILTIN_VFMADDPD,
30230 IX86_BUILTIN_VFMADDPS256,
30231 IX86_BUILTIN_VFMADDPD256,
30232 IX86_BUILTIN_VFMADDSUBPS,
30233 IX86_BUILTIN_VFMADDSUBPD,
30234 IX86_BUILTIN_VFMADDSUBPS256,
30235 IX86_BUILTIN_VFMADDSUBPD256,
30237 /* FMA3 instructions. */
30238 IX86_BUILTIN_VFMADDSS3,
30239 IX86_BUILTIN_VFMADDSD3,
30241 /* XOP instructions. */
30242 IX86_BUILTIN_VPCMOV,
30243 IX86_BUILTIN_VPCMOV_V2DI,
30244 IX86_BUILTIN_VPCMOV_V4SI,
30245 IX86_BUILTIN_VPCMOV_V8HI,
30246 IX86_BUILTIN_VPCMOV_V16QI,
30247 IX86_BUILTIN_VPCMOV_V4SF,
30248 IX86_BUILTIN_VPCMOV_V2DF,
30249 IX86_BUILTIN_VPCMOV256,
30250 IX86_BUILTIN_VPCMOV_V4DI256,
30251 IX86_BUILTIN_VPCMOV_V8SI256,
30252 IX86_BUILTIN_VPCMOV_V16HI256,
30253 IX86_BUILTIN_VPCMOV_V32QI256,
30254 IX86_BUILTIN_VPCMOV_V8SF256,
30255 IX86_BUILTIN_VPCMOV_V4DF256,
30257 IX86_BUILTIN_VPPERM,
30259 IX86_BUILTIN_VPMACSSWW,
30260 IX86_BUILTIN_VPMACSWW,
30261 IX86_BUILTIN_VPMACSSWD,
30262 IX86_BUILTIN_VPMACSWD,
30263 IX86_BUILTIN_VPMACSSDD,
30264 IX86_BUILTIN_VPMACSDD,
30265 IX86_BUILTIN_VPMACSSDQL,
30266 IX86_BUILTIN_VPMACSSDQH,
30267 IX86_BUILTIN_VPMACSDQL,
30268 IX86_BUILTIN_VPMACSDQH,
30269 IX86_BUILTIN_VPMADCSSWD,
30270 IX86_BUILTIN_VPMADCSWD,
30272 IX86_BUILTIN_VPHADDBW,
30273 IX86_BUILTIN_VPHADDBD,
30274 IX86_BUILTIN_VPHADDBQ,
30275 IX86_BUILTIN_VPHADDWD,
30276 IX86_BUILTIN_VPHADDWQ,
30277 IX86_BUILTIN_VPHADDDQ,
30278 IX86_BUILTIN_VPHADDUBW,
30279 IX86_BUILTIN_VPHADDUBD,
30280 IX86_BUILTIN_VPHADDUBQ,
30281 IX86_BUILTIN_VPHADDUWD,
30282 IX86_BUILTIN_VPHADDUWQ,
30283 IX86_BUILTIN_VPHADDUDQ,
30284 IX86_BUILTIN_VPHSUBBW,
30285 IX86_BUILTIN_VPHSUBWD,
30286 IX86_BUILTIN_VPHSUBDQ,
30288 IX86_BUILTIN_VPROTB,
30289 IX86_BUILTIN_VPROTW,
30290 IX86_BUILTIN_VPROTD,
30291 IX86_BUILTIN_VPROTQ,
30292 IX86_BUILTIN_VPROTB_IMM,
30293 IX86_BUILTIN_VPROTW_IMM,
30294 IX86_BUILTIN_VPROTD_IMM,
30295 IX86_BUILTIN_VPROTQ_IMM,
30297 IX86_BUILTIN_VPSHLB,
30298 IX86_BUILTIN_VPSHLW,
30299 IX86_BUILTIN_VPSHLD,
30300 IX86_BUILTIN_VPSHLQ,
30301 IX86_BUILTIN_VPSHAB,
30302 IX86_BUILTIN_VPSHAW,
30303 IX86_BUILTIN_VPSHAD,
30304 IX86_BUILTIN_VPSHAQ,
30306 IX86_BUILTIN_VFRCZSS,
30307 IX86_BUILTIN_VFRCZSD,
30308 IX86_BUILTIN_VFRCZPS,
30309 IX86_BUILTIN_VFRCZPD,
30310 IX86_BUILTIN_VFRCZPS256,
30311 IX86_BUILTIN_VFRCZPD256,
30313 IX86_BUILTIN_VPCOMEQUB,
30314 IX86_BUILTIN_VPCOMNEUB,
30315 IX86_BUILTIN_VPCOMLTUB,
30316 IX86_BUILTIN_VPCOMLEUB,
30317 IX86_BUILTIN_VPCOMGTUB,
30318 IX86_BUILTIN_VPCOMGEUB,
30319 IX86_BUILTIN_VPCOMFALSEUB,
30320 IX86_BUILTIN_VPCOMTRUEUB,
30322 IX86_BUILTIN_VPCOMEQUW,
30323 IX86_BUILTIN_VPCOMNEUW,
30324 IX86_BUILTIN_VPCOMLTUW,
30325 IX86_BUILTIN_VPCOMLEUW,
30326 IX86_BUILTIN_VPCOMGTUW,
30327 IX86_BUILTIN_VPCOMGEUW,
30328 IX86_BUILTIN_VPCOMFALSEUW,
30329 IX86_BUILTIN_VPCOMTRUEUW,
30331 IX86_BUILTIN_VPCOMEQUD,
30332 IX86_BUILTIN_VPCOMNEUD,
30333 IX86_BUILTIN_VPCOMLTUD,
30334 IX86_BUILTIN_VPCOMLEUD,
30335 IX86_BUILTIN_VPCOMGTUD,
30336 IX86_BUILTIN_VPCOMGEUD,
30337 IX86_BUILTIN_VPCOMFALSEUD,
30338 IX86_BUILTIN_VPCOMTRUEUD,
30340 IX86_BUILTIN_VPCOMEQUQ,
30341 IX86_BUILTIN_VPCOMNEUQ,
30342 IX86_BUILTIN_VPCOMLTUQ,
30343 IX86_BUILTIN_VPCOMLEUQ,
30344 IX86_BUILTIN_VPCOMGTUQ,
30345 IX86_BUILTIN_VPCOMGEUQ,
30346 IX86_BUILTIN_VPCOMFALSEUQ,
30347 IX86_BUILTIN_VPCOMTRUEUQ,
30349 IX86_BUILTIN_VPCOMEQB,
30350 IX86_BUILTIN_VPCOMNEB,
30351 IX86_BUILTIN_VPCOMLTB,
30352 IX86_BUILTIN_VPCOMLEB,
30353 IX86_BUILTIN_VPCOMGTB,
30354 IX86_BUILTIN_VPCOMGEB,
30355 IX86_BUILTIN_VPCOMFALSEB,
30356 IX86_BUILTIN_VPCOMTRUEB,
30358 IX86_BUILTIN_VPCOMEQW,
30359 IX86_BUILTIN_VPCOMNEW,
30360 IX86_BUILTIN_VPCOMLTW,
30361 IX86_BUILTIN_VPCOMLEW,
30362 IX86_BUILTIN_VPCOMGTW,
30363 IX86_BUILTIN_VPCOMGEW,
30364 IX86_BUILTIN_VPCOMFALSEW,
30365 IX86_BUILTIN_VPCOMTRUEW,
30367 IX86_BUILTIN_VPCOMEQD,
30368 IX86_BUILTIN_VPCOMNED,
30369 IX86_BUILTIN_VPCOMLTD,
30370 IX86_BUILTIN_VPCOMLED,
30371 IX86_BUILTIN_VPCOMGTD,
30372 IX86_BUILTIN_VPCOMGED,
30373 IX86_BUILTIN_VPCOMFALSED,
30374 IX86_BUILTIN_VPCOMTRUED,
30376 IX86_BUILTIN_VPCOMEQQ,
30377 IX86_BUILTIN_VPCOMNEQ,
30378 IX86_BUILTIN_VPCOMLTQ,
30379 IX86_BUILTIN_VPCOMLEQ,
30380 IX86_BUILTIN_VPCOMGTQ,
30381 IX86_BUILTIN_VPCOMGEQ,
30382 IX86_BUILTIN_VPCOMFALSEQ,
30383 IX86_BUILTIN_VPCOMTRUEQ,
30385 /* LWP instructions. */
30386 IX86_BUILTIN_LLWPCB,
30387 IX86_BUILTIN_SLWPCB,
30388 IX86_BUILTIN_LWPVAL32,
30389 IX86_BUILTIN_LWPVAL64,
30390 IX86_BUILTIN_LWPINS32,
30391 IX86_BUILTIN_LWPINS64,
30393 IX86_BUILTIN_CLZS,
30395 /* RTM */
30396 IX86_BUILTIN_XBEGIN,
30397 IX86_BUILTIN_XEND,
30398 IX86_BUILTIN_XABORT,
30399 IX86_BUILTIN_XTEST,
30401 /* MPX */
30402 IX86_BUILTIN_BNDMK,
30403 IX86_BUILTIN_BNDSTX,
30404 IX86_BUILTIN_BNDLDX,
30405 IX86_BUILTIN_BNDCL,
30406 IX86_BUILTIN_BNDCU,
30407 IX86_BUILTIN_BNDRET,
30408 IX86_BUILTIN_BNDNARROW,
30409 IX86_BUILTIN_BNDINT,
30410 IX86_BUILTIN_SIZEOF,
30411 IX86_BUILTIN_BNDLOWER,
30412 IX86_BUILTIN_BNDUPPER,
30414 /* BMI instructions. */
30415 IX86_BUILTIN_BEXTR32,
30416 IX86_BUILTIN_BEXTR64,
30417 IX86_BUILTIN_CTZS,
30419 /* TBM instructions. */
30420 IX86_BUILTIN_BEXTRI32,
30421 IX86_BUILTIN_BEXTRI64,
30423 /* BMI2 instructions. */
30424 IX86_BUILTIN_BZHI32,
30425 IX86_BUILTIN_BZHI64,
30426 IX86_BUILTIN_PDEP32,
30427 IX86_BUILTIN_PDEP64,
30428 IX86_BUILTIN_PEXT32,
30429 IX86_BUILTIN_PEXT64,
30431 /* ADX instructions. */
30432 IX86_BUILTIN_ADDCARRYX32,
30433 IX86_BUILTIN_ADDCARRYX64,
30435 /* SBB instructions. */
30436 IX86_BUILTIN_SBB32,
30437 IX86_BUILTIN_SBB64,
30439 /* FSGSBASE instructions. */
30440 IX86_BUILTIN_RDFSBASE32,
30441 IX86_BUILTIN_RDFSBASE64,
30442 IX86_BUILTIN_RDGSBASE32,
30443 IX86_BUILTIN_RDGSBASE64,
30444 IX86_BUILTIN_WRFSBASE32,
30445 IX86_BUILTIN_WRFSBASE64,
30446 IX86_BUILTIN_WRGSBASE32,
30447 IX86_BUILTIN_WRGSBASE64,
30449 /* RDRND instructions. */
30450 IX86_BUILTIN_RDRAND16_STEP,
30451 IX86_BUILTIN_RDRAND32_STEP,
30452 IX86_BUILTIN_RDRAND64_STEP,
30454 /* RDSEED instructions. */
30455 IX86_BUILTIN_RDSEED16_STEP,
30456 IX86_BUILTIN_RDSEED32_STEP,
30457 IX86_BUILTIN_RDSEED64_STEP,
30459 /* F16C instructions. */
30460 IX86_BUILTIN_CVTPH2PS,
30461 IX86_BUILTIN_CVTPH2PS256,
30462 IX86_BUILTIN_CVTPS2PH,
30463 IX86_BUILTIN_CVTPS2PH256,
30465 /* CFString built-in for darwin */
30466 IX86_BUILTIN_CFSTRING,
30468 /* Builtins to get CPU type and supported features. */
30469 IX86_BUILTIN_CPU_INIT,
30470 IX86_BUILTIN_CPU_IS,
30471 IX86_BUILTIN_CPU_SUPPORTS,
30473 /* Read/write FLAGS register built-ins. */
30474 IX86_BUILTIN_READ_FLAGS,
30475 IX86_BUILTIN_WRITE_FLAGS,
30477 IX86_BUILTIN_MAX
30478 };
30480 /* Table for the ix86 builtin decls. */
30483 /* Table of all of the builtin functions that are possible with different ISA's
30484 but are waiting to be built until a function is declared to use that
30485 ISA. */
30494 };
30498 /* Bits that can still enable any inclusion of a builtin. */
30501 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30502 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30503 function decl in the ix86_builtins array. Returns the function decl or
30504 NULL_TREE, if the builtin was not added.
30506 If the front end has a special hook for builtin functions, delay adding
30507 builtin functions that aren't in the current ISA until the ISA is changed
30508 with function specific optimization. Doing so, can save about 300K for the
30509 default compiler. When the builtin is expanded, check at that time whether
30510 it is valid.
30512 If the front end doesn't have a special hook, record all builtins, even if
30513 it isn't an instruction set in the current ISA in case the user uses
30514 function specific options for a different ISA, so that we don't get scope
30515 errors if a builtin is added in the middle of a function scope. */
30521 {
30525 {
30534 {
30540 }
30541 else
30542 {
30543 /* Just a MASK where set_and_not_built_p == true can potentially
30544 include a builtin. */
30553 }
30554 }
30557 }
30559 /* Like def_builtin, but also marks the function decl "const". */
30564 {
30568 else
30572 }
30574 /* Add any new builtin functions for a given ISA that may not have been
30575 declared. This saves a bit of space compared to adding all of the
30576 declarations to the tree, even if we didn't use them. */
30578 static void
30580 {
30584 /* Bits in ISA value can be removed from potential isa values. */
30592 {
30595 {
30598 /* Don't define the builtin again. */
30604 NULL_TREE);
30611 NULL_TREE);
30614 }
30615 }
30618 }
30620 /* Bits for builtin_description.flag. */
30622 /* Set when we don't support the comparison natively, and should
30623 swap_comparison in order to support it. */
30624 #define BUILTIN_DESC_SWAP_OPERANDS 1
30626 struct builtin_description
30627 {
30634 };
30637 {
30638 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30639 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30640 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30641 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30642 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30643 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30644 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30645 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30646 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30648 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30650 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30651 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30652 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30653 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30654 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30655 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30656 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30657 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30660 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30662 };
30665 {
30666 /* SSE4.2 */
30667 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30668 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30669 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30670 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30671 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30672 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30673 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30674 };
30677 {
30678 /* SSE4.2 */
30679 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30680 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30681 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30682 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30683 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30684 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30685 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30686 };
30688 /* Special builtins with variable number of arguments. */
30690 {
30691 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30692 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30693 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30695 /* 80387 (for use internally for atomic compound assignment). */
30696 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30697 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30698 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30699 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30701 /* MMX */
30702 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30704 /* 3DNow! */
30705 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30707 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30708 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30709 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30710 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30711 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30712 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30713 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30714 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30715 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30717 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30718 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30719 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30720 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30721 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30722 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30723 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30724 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30726 /* SSE */
30727 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30729 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30733 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30736 /* SSE or 3DNow!A */
30737 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30738 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30740 /* SSE2 */
30741 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30744 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30745 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30746 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30747 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30748 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30749 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30750 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30753 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30755 /* SSE3 */
30756 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30758 /* SSE4.1 */
30759 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30761 /* SSE4A */
30762 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30763 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30765 /* AVX */
30766 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30767 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30769 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30770 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30771 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30772 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30773 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30789 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30796 /* AVX2 */
30797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30802 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30804 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30805 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30807 /* AVX512F */
30808 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30809 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30810 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30811 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30812 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30813 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30856 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30857 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30858 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30859 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30860 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30861 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30863 /* FSGSBASE */
30864 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30865 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30866 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30867 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30868 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30869 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30870 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30871 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30873 /* RTM */
30874 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30875 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30876 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30878 /* AVX512BW */
30879 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30880 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30881 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30882 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30884 /* AVX512VL */
30885 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30886 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30887 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30888 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30921 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30922 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30923 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30924 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30962 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30963 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30980 /* PCOMMIT. */
30981 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
30982 };
30984 /* Builtins with variable number of arguments. */
30986 {
30987 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30988 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30989 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30990 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30991 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30992 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30993 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30995 /* MMX */
30996 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31005 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31008 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31013 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31020 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31027 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31031 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31054 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31059 /* 3DNow! */
31060 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31061 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31073 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31074 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31075 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31076 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31077 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31078 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31079 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31081 /* 3DNow!A */
31082 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31083 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31084 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31085 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31086 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31087 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31089 /* SSE */
31090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31092 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31094 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31095 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31096 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31098 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31099 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31100 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31101 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31105 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31106 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31107 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31132 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31135 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31136 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31138 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31140 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31141 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31142 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31143 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31145 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31147 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31150 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31151 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31153 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31154 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31155 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31157 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31161 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31163 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31164 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31166 /* SSE MMX or 3Dnow!A */
31167 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31168 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31169 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31171 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31172 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31173 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31174 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31176 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31177 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31179 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31181 /* SSE2 */
31182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31188 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31193 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31200 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31201 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31203 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31204 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31205 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31207 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31208 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31209 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31210 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31211 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31234 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31237 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31238 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31242 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31243 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31244 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31245 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31247 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31250 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31251 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31253 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31255 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31256 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31257 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31258 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31259 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31260 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31261 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31262 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31273 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31274 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31276 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31278 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31279 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31292 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31297 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31298 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31299 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31300 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31301 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31303 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31313 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31318 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31325 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31326 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31327 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31331 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31339 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31340 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31349 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31351 /* SSE2 MMX */
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31355 /* SSE3 */
31356 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31357 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31359 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31360 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31361 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31362 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31363 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31364 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31366 /* SSSE3 */
31367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31369 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31394 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31395 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31399 /* SSSE3. */
31400 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31401 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31403 /* SSE4.1 */
31404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31410 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31424 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31438 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31439 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31440 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31442 /* SSE4.1 */
31443 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31444 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31448 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31449 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31450 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31451 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31453 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31454 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31456 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31457 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31459 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31460 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31462 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31464 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31465 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31467 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31468 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31470 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31471 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31472 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31474 /* SSE4.2 */
31475 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31476 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31477 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31478 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31479 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31481 /* SSE4A */
31482 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31483 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31484 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31485 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31487 /* AES */
31488 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31489 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31496 /* PCLMUL */
31497 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31499 /* AVX */
31500 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31501 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31504 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31505 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31508 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31510 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31511 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31512 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31513 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31514 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31515 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31516 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31517 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31518 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31519 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31520 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31521 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31522 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31523 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31524 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31525 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31548 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31549 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31553 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31555 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31571 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31573 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31575 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31587 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31588 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31601 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31602 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31612 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31613 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31614 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31640 /* AVX2 */
31641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31642 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31643 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31644 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31645 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31646 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31647 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31648 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31649 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31650 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31651 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31652 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31654 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31658 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31676 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31677 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31678 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31679 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31680 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31681 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31682 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31683 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31684 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31685 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31686 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31687 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31688 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31689 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31690 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31691 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31701 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31703 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31704 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31705 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31706 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31707 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31708 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31709 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31710 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31711 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31712 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31718 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31719 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31720 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31721 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31722 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31723 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31724 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31725 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31726 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31727 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31728 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31729 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31730 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31731 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31732 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31733 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31734 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31735 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31736 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31737 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31740 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31741 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31742 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31755 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31788 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31790 /* BMI */
31791 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31792 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31793 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31795 /* TBM */
31796 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31797 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31799 /* F16C */
31800 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31801 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31802 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31803 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31805 /* BMI2 */
31806 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31807 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31808 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31809 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31810 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31811 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31813 /* AVX512F */
31814 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31815 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31816 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31817 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31818 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31819 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31820 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31821 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31822 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31823 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31824 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31825 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31826 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31827 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31828 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31829 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31830 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31831 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31832 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31833 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31834 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31835 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31836 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31837 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31838 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31839 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31840 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31841 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31842 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31843 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31844 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31845 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31846 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31847 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31848 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31849 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31850 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31851 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31852 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31853 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31854 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31855 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31856 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31857 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31858 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31859 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31860 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31861 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31862 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31863 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31864 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31865 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31866 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31867 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31868 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31869 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31870 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31871 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31872 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31873 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31874 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31875 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31876 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31877 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31878 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31879 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31880 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31881 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31882 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31883 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31884 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31885 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31886 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31887 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31888 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31889 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31890 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31891 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31892 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31893 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31894 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31895 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31896 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31897 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31898 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31899 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31900 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31901 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31902 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31903 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31904 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31980 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31981 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31982 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31983 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32015 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32020 /* Mask arithmetic operations */
32021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32032 /* SHA */
32033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32041 /* AVX512VL. */
32042 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32043 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32052 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32053 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32054 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32055 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32080 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32081 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32082 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32083 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32084 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32085 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32086 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32087 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32088 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32089 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32090 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32091 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32092 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32097 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32098 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32099 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32100 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32101 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32102 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32103 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32104 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32105 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32106 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32108 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32109 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32110 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32111 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32112 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32121 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32122 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32123 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32124 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32125 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32126 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32127 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32128 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32129 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32130 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32131 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32132 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32133 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32134 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32135 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32136 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32137 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32138 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32139 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32140 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32144 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32152 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32153 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32156 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32157 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32168 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32169 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32180 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32181 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32182 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32183 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32184 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32185 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32186 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32187 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32188 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32189 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32190 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32191 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32192 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32193 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32206 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32207 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32210 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32211 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32214 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32215 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32216 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32217 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32218 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32219 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32220 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32221 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32222 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32223 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32226 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32227 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32228 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32229 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32234 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32235 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32236 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32237 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32242 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32243 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32244 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32245 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32246 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32247 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32277 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32278 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32279 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32280 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32281 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32298 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32299 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32300 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32301 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32302 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32303 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32304 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32305 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32306 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32307 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32308 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32309 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32310 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32311 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32312 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32313 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32314 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32315 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32319 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32322 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32323 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32360 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32361 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32362 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32363 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32424 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32425 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32426 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32427 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32430 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32431 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32432 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32433 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32438 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32439 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32440 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32441 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32452 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32453 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32454 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32455 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32456 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32457 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32458 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32459 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32516 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32521 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32522 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32532 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32533 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32534 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32535 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32536 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32537 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32538 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32539 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32540 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32541 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32542 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32543 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32544 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32545 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32546 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32547 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32548 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32549 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32550 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32551 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32552 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32553 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32554 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32555 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32556 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32562 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32563 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32564 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32565 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32570 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32571 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32578 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32579 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32580 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32581 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32586 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32587 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32588 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32589 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32630 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32631 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32632 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32633 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32634 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32635 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32637 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32638 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32639 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32646 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32647 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32648 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32649 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32657 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32658 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32659 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32660 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32678 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32679 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32680 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32681 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32683 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32684 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32685 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32686 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32687 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32688 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32690 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32691 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32692 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32693 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32719 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32720 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32721 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32722 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32738 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32739 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32740 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32741 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32748 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32749 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32750 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32751 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32755 /* AVX512DQ. */
32756 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32757 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32758 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32759 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32760 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32761 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32762 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32763 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32764 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32765 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32766 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32767 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32768 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32769 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32770 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32771 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32772 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32773 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32774 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32775 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32776 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32777 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32778 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32779 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32780 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32781 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32782 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32783 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32784 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32785 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32786 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32788 /* AVX512BW. */
32789 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32790 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32791 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32792 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32793 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32794 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32795 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32796 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32797 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32798 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32799 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32800 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32801 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32802 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32803 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32804 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32805 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32806 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32807 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32808 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32809 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32810 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32811 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32812 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32813 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32814 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32815 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32816 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32817 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32818 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32819 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32820 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32821 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32822 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32823 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32824 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32825 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32826 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32827 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32828 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32829 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32830 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32831 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32832 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32833 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32834 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32835 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32836 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32837 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32838 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32839 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32840 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32841 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32842 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32843 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32844 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32845 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32846 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32847 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32848 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32849 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32850 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32851 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32852 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32853 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32854 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32855 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32856 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32857 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32858 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32859 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32860 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32861 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32862 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32863 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32864 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32865 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32866 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32867 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32868 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32869 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32870 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32871 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32872 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32873 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32874 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32875 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32876 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32877 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32878 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32879 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32881 /* AVX512IFMA */
32882 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32883 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32884 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32885 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32886 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32887 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32888 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32889 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32890 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32891 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32892 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32893 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32895 /* AVX512VBMI */
32896 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32897 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32898 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32899 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32900 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32901 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32902 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32903 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32904 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32905 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32906 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32907 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32908 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32909 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32910 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32911 };
32913 /* Builtins with rounding support. */
32915 {
32916 /* AVX512F */
32917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32936 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32938 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32945 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32947 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32997 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32999 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33001 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33003 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33005 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33007 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33009 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33011 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33037 /* AVX512ER */
33038 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33039 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33040 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33041 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33042 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33043 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33044 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33045 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33046 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33047 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33049 /* AVX512DQ. */
33050 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33051 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33055 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33056 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33057 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33058 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33059 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33060 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33061 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33062 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33063 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33064 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33065 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33066 };
33068 /* Bultins for MPX. */
33070 {
33071 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33072 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33073 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33074 };
33076 /* Const builtins for MPX. */
33078 {
33079 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33080 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33081 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33082 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33083 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33084 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33085 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33086 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33087 };
33089 /* FMA4 and XOP. */
33090 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33091 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33092 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33093 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33094 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33095 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33096 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33097 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33098 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33099 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33100 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33101 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33102 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33103 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33104 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33105 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33106 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33107 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33108 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33109 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33110 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33111 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33112 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33113 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33114 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33115 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33116 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33117 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33118 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33119 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33120 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33121 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33122 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33123 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33124 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33125 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33126 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33127 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33128 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33129 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33130 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33131 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33132 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33133 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33134 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33135 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33136 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33137 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33138 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33139 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33140 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33141 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33144 {
33185 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33186 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33187 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33188 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33189 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33190 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33191 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33193 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33194 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33195 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33196 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33197 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33198 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33199 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33201 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33203 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33204 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33205 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33206 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33207 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33208 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33209 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33210 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33211 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33212 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33213 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33214 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33216 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33217 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33218 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33219 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33220 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33221 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33222 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33223 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33224 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33225 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33226 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33227 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33228 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33229 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33230 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33231 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33233 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33234 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33235 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33236 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33237 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33238 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33240 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33241 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33242 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33243 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33244 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33245 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33246 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33247 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33248 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33249 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33250 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33251 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33252 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33253 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33254 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33256 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33257 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33258 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33259 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33260 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33261 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33262 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33264 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33265 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33266 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33267 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33268 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33269 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33270 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33272 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33273 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33274 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33275 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33276 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33277 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33278 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33280 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33281 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33289 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33297 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33299 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33300 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33343 };
33344 \f
33345 /* TM vector builtins. */
33347 /* Reuse the existing x86-specific `struct builtin_description' cause
33348 we're lazy. Add casts to make them fit. */
33350 {
33351 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33352 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33353 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33354 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33355 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33356 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33357 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33359 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33360 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33361 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33362 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33363 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33364 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33365 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33367 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33368 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33369 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33370 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33371 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33372 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33373 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33375 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33376 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33377 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33378 };
33380 /* TM callbacks. */
33382 /* Return the builtin decl needed to load a vector of TYPE. */
33384 static tree
33386 {
33388 {
33390 {
33397 }
33398 }
33400 }
33402 /* Return the builtin decl needed to store a vector of TYPE. */
33404 static tree
33406 {
33408 {
33410 {
33417 }
33418 }
33420 }
33421 \f
33422 /* Initialize the transactional memory vector load/store builtins. */
33424 static void
33426 {
33430 tree decl;
33437 /* If there are no builtins defined, we must be compiling in a
33438 language without trans-mem support. */
33442 /* Use whatever attributes a normal TM load has. */
33446 /* Use whatever attributes a normal TM store has. */
33450 /* Use whatever attributes a normal TM log has. */
33458 {
33462 {
33470 {
33473 }
33475 {
33478 }
33479 else
33480 {
33483 }
33485 /* The builtin without the prefix for
33486 calling it directly. */
33488 attrs);
33489 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33490 set the TYPE_ATTRIBUTES. */
33494 }
33495 }
33496 }
33498 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33499 in the current target ISA to allow the user to compile particular modules
33500 with different target specific options that differ from the command line
33501 options. */
33502 static void
33504 {
33509 /* Add all special builtins with variable number of operands. */
33513 {
33519 }
33521 /* Add all builtins with variable number of operands. */
33525 {
33531 }
33533 /* Add all builtins with rounding. */
33537 {
33543 }
33545 /* pcmpestr[im] insns. */
33549 {
33552 else
33555 }
33557 /* pcmpistr[im] insns. */
33561 {
33564 else
33567 }
33569 /* comi/ucomi insns. */
33571 {
33574 else
33577 }
33579 /* SSE */
33585 /* SSE or 3DNow!A */
33588 IX86_BUILTIN_MASKMOVQ);
33590 /* SSE2 */
33599 /* SSE3. */
33605 /* AES */
33619 /* PCLMUL */
33623 /* RDRND */
33630 IX86_BUILTIN_RDRAND64_STEP);
33632 /* AVX2 */
33634 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33635 IX86_BUILTIN_GATHERSIV2DF);
33638 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33639 IX86_BUILTIN_GATHERSIV4DF);
33642 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33643 IX86_BUILTIN_GATHERDIV2DF);
33646 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33647 IX86_BUILTIN_GATHERDIV4DF);
33650 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33651 IX86_BUILTIN_GATHERSIV4SF);
33654 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33655 IX86_BUILTIN_GATHERSIV8SF);
33658 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33659 IX86_BUILTIN_GATHERDIV4SF);
33662 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33663 IX86_BUILTIN_GATHERDIV8SF);
33666 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33667 IX86_BUILTIN_GATHERSIV2DI);
33670 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33671 IX86_BUILTIN_GATHERSIV4DI);
33674 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33675 IX86_BUILTIN_GATHERDIV2DI);
33678 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33679 IX86_BUILTIN_GATHERDIV4DI);
33682 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33683 IX86_BUILTIN_GATHERSIV4SI);
33686 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33687 IX86_BUILTIN_GATHERSIV8SI);
33690 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33691 IX86_BUILTIN_GATHERDIV4SI);
33694 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33695 IX86_BUILTIN_GATHERDIV8SI);
33698 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33699 IX86_BUILTIN_GATHERALTSIV4DF);
33702 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33703 IX86_BUILTIN_GATHERALTDIV8SF);
33706 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33707 IX86_BUILTIN_GATHERALTSIV4DI);
33710 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33711 IX86_BUILTIN_GATHERALTDIV8SI);
33713 /* AVX512F */
33715 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33716 IX86_BUILTIN_GATHER3SIV16SF);
33719 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33720 IX86_BUILTIN_GATHER3SIV8DF);
33723 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33724 IX86_BUILTIN_GATHER3DIV16SF);
33727 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33728 IX86_BUILTIN_GATHER3DIV8DF);
33731 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33732 IX86_BUILTIN_GATHER3SIV16SI);
33735 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33736 IX86_BUILTIN_GATHER3SIV8DI);
33739 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33740 IX86_BUILTIN_GATHER3DIV16SI);
33743 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33744 IX86_BUILTIN_GATHER3DIV8DI);
33747 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33748 IX86_BUILTIN_GATHER3ALTSIV8DF);
33751 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33752 IX86_BUILTIN_GATHER3ALTDIV16SF);
33755 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33756 IX86_BUILTIN_GATHER3ALTSIV8DI);
33759 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33760 IX86_BUILTIN_GATHER3ALTDIV16SI);
33763 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33764 IX86_BUILTIN_SCATTERSIV16SF);
33767 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33768 IX86_BUILTIN_SCATTERSIV8DF);
33771 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33772 IX86_BUILTIN_SCATTERDIV16SF);
33775 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33776 IX86_BUILTIN_SCATTERDIV8DF);
33779 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33780 IX86_BUILTIN_SCATTERSIV16SI);
33783 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33784 IX86_BUILTIN_SCATTERSIV8DI);
33787 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33788 IX86_BUILTIN_SCATTERDIV16SI);
33791 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33792 IX86_BUILTIN_SCATTERDIV8DI);
33794 /* AVX512VL */
33796 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33797 IX86_BUILTIN_GATHER3SIV2DF);
33800 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33801 IX86_BUILTIN_GATHER3SIV4DF);
33804 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33805 IX86_BUILTIN_GATHER3DIV2DF);
33808 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33809 IX86_BUILTIN_GATHER3DIV4DF);
33812 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33813 IX86_BUILTIN_GATHER3SIV4SF);
33816 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33817 IX86_BUILTIN_GATHER3SIV8SF);
33820 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33821 IX86_BUILTIN_GATHER3DIV4SF);
33824 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33825 IX86_BUILTIN_GATHER3DIV8SF);
33828 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33829 IX86_BUILTIN_GATHER3SIV2DI);
33832 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33833 IX86_BUILTIN_GATHER3SIV4DI);
33836 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33837 IX86_BUILTIN_GATHER3DIV2DI);
33840 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33841 IX86_BUILTIN_GATHER3DIV4DI);
33844 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33845 IX86_BUILTIN_GATHER3SIV4SI);
33848 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33849 IX86_BUILTIN_GATHER3SIV8SI);
33852 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33853 IX86_BUILTIN_GATHER3DIV4SI);
33856 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33857 IX86_BUILTIN_GATHER3DIV8SI);
33860 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33861 IX86_BUILTIN_GATHER3ALTSIV4DF);
33864 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33865 IX86_BUILTIN_GATHER3ALTDIV8SF);
33868 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33869 IX86_BUILTIN_GATHER3ALTSIV4DI);
33872 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33873 IX86_BUILTIN_GATHER3ALTDIV8SI);
33876 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33877 IX86_BUILTIN_SCATTERSIV8SF);
33880 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33881 IX86_BUILTIN_SCATTERSIV4SF);
33884 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33885 IX86_BUILTIN_SCATTERSIV4DF);
33888 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33889 IX86_BUILTIN_SCATTERSIV2DF);
33892 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33893 IX86_BUILTIN_SCATTERDIV8SF);
33896 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33897 IX86_BUILTIN_SCATTERDIV4SF);
33900 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33901 IX86_BUILTIN_SCATTERDIV4DF);
33904 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33905 IX86_BUILTIN_SCATTERDIV2DF);
33908 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33909 IX86_BUILTIN_SCATTERSIV8SI);
33912 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33913 IX86_BUILTIN_SCATTERSIV4SI);
33916 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33917 IX86_BUILTIN_SCATTERSIV4DI);
33920 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33921 IX86_BUILTIN_SCATTERSIV2DI);
33924 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33925 IX86_BUILTIN_SCATTERDIV8SI);
33928 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33929 IX86_BUILTIN_SCATTERDIV4SI);
33932 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33933 IX86_BUILTIN_SCATTERDIV4DI);
33936 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33937 IX86_BUILTIN_SCATTERDIV2DI);
33939 /* AVX512PF */
33941 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33942 IX86_BUILTIN_GATHERPFDPD);
33944 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33945 IX86_BUILTIN_GATHERPFDPS);
33947 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33948 IX86_BUILTIN_GATHERPFQPD);
33950 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33951 IX86_BUILTIN_GATHERPFQPS);
33953 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33954 IX86_BUILTIN_SCATTERPFDPD);
33956 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33957 IX86_BUILTIN_SCATTERPFDPS);
33959 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33960 IX86_BUILTIN_SCATTERPFQPD);
33962 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33963 IX86_BUILTIN_SCATTERPFQPS);
33965 /* SHA */
33981 /* RTM. */
33985 /* MMX access to the vec_init patterns. */
33990 V4HI_FTYPE_HI_HI_HI_HI,
33991 IX86_BUILTIN_VEC_INIT_V4HI);
33994 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33995 IX86_BUILTIN_VEC_INIT_V8QI);
33997 /* Access to the vec_extract patterns. */
34019 /* Access to the vec_set patterns. */
34040 /* RDSEED */
34049 /* ADCX */
34054 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34055 IX86_BUILTIN_ADDCARRYX64);
34057 /* SBB */
34062 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34063 IX86_BUILTIN_SBB64);
34065 /* Read/write FLAGS. */
34075 /* CLFLUSHOPT. */
34079 /* CLWB. */
34083 /* Add FMA4 multi-arg argument instructions */
34085 {
34091 }
34092 }
34094 static void
34096 {
34099 tree decl;
34105 {
34112 /* With no leaf and nothrow flags for MPX builtins
34113 abnormal edges may follow its call when setjmp
34114 presents in the function. Since we may have a lot
34115 of MPX builtins calls it causes lots of useless
34116 edges and enormous PHI nodes. To avoid this we mark
34117 MPX builtins as leaf and nothrow. */
34119 {
34121 NULL_TREE);
34123 }
34124 else
34125 {
34128 }
34129 }
34134 {
34142 {
34144 NULL_TREE);
34146 }
34147 else
34148 {
34151 }
34152 }
34153 }
34155 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34156 to return a pointer to VERSION_DECL if the outcome of the expression
34157 formed by PREDICATE_CHAIN is true. This function will be called during
34158 version dispatch to decide which function version to execute. It returns
34159 the basic block at the end, to which more conditions can be added. */
34161 static basic_block
34164 {
34165 gimple return_stmt;
34167 gimple convert_stmt;
34168 gimple call_cond_stmt;
34169 gimple if_else_stmt;
34175 gimple_seq gseq;
34192 {
34200 }
34203 {
34218 else
34219 {
34220 gimple assign_stmt;
34221 /* Use MIN_EXPR to check if any integer is zero?.
34222 and_expr_var = min_expr <cond_var, and_expr_var> */
34230 }
34231 }
34234 integer_zero_node,
34264 }
34266 /* This parses the attribute arguments to target in DECL and determines
34267 the right builtin to use to match the platform specification.
34268 It returns the priority value for this version decl. If PREDICATE_LIST
34269 is not NULL, it stores the list of cpu features that need to be checked
34270 before dispatching this function. */
34272 static unsigned int
34274 {
34275 tree attrs;
34277 tree target_node;
34284 /* Priority of i386 features, greater value is higher priority. This is
34285 used to decide the order in which function dispatch must happen. For
34286 instance, a version specialized for SSE4.2 should be checked for dispatch
34287 before a version for SSE3, as SSE4.2 implies SSE3. */
34288 enum feature_priority
34289 {
34291 P_MMX,
34292 P_SSE,
34293 P_SSE2,
34294 P_SSE3,
34295 P_SSSE3,
34296 P_PROC_SSSE3,
34297 P_SSE4_A,
34298 P_PROC_SSE4_A,
34299 P_SSE4_1,
34300 P_SSE4_2,
34301 P_PROC_SSE4_2,
34302 P_POPCNT,
34303 P_AVX,
34304 P_PROC_AVX,
34305 P_BMI,
34306 P_PROC_BMI,
34307 P_FMA4,
34308 P_XOP,
34309 P_PROC_XOP,
34310 P_FMA,
34311 P_PROC_FMA,
34312 P_BMI2,
34313 P_AVX2,
34314 P_PROC_AVX2,
34315 P_AVX512F,
34316 P_PROC_AVX512F
34317 };
34321 /* These are the target attribute strings for which a dispatcher is
34322 available, from fold_builtin_cpu. */
34324 static struct _feature_list
34325 {
34328 }
34330 {
34348 };
34351 static unsigned int NUM_FEATURES
34367 /* Return priority zero for default function. */
34371 /* Handle arch= if specified. For priority, set it to be 1 more than
34372 the best instruction set the processor can handle. For instance, if
34373 there is a version for atom and a version for ssse3 (the highest ISA
34374 priority for atom), the atom version must be checked for dispatch
34375 before the ssse3 version. */
34377 {
34387 {
34389 {
34397 else
34398 /* We translate "arch=corei7" and "arch=nehalem" to
34399 "corei7" so that it will be mapped to M_INTEL_COREI7
34400 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34407 else
34414 else
34458 }
34459 }
34464 {
34468 }
34471 {
34473 /* For a C string literal the length includes the trailing NULL. */
34476 predicate_chain);
34477 }
34478 }
34480 /* Process feature name. */
34487 {
34488 /* Do not process "arch=" */
34490 {
34493 }
34495 {
34497 {
34499 {
34504 predicate_chain);
34505 }
34506 /* Find the maximum priority feature. */
34511 }
34512 }
34514 {
34518 }
34520 }
34524 {
34527 attrs_str);
34529 }
34531 {
34534 }
34537 }
34539 /* This compares the priority of target features in function DECL1
34540 and DECL2. It returns positive value if DECL1 is higher priority,
34541 negative value if DECL2 is higher priority and 0 if they are the
34542 same. */
34544 static int
34546 {
34551 }
34553 /* V1 and V2 point to function versions with different priorities
34554 based on the target ISA. This function compares their priorities. */
34556 static int
34558 {
34560 {
34561 tree version_decl;
34562 tree predicate_chain;
34569 }
34571 /* This function generates the dispatch function for
34572 multi-versioned functions. DISPATCH_DECL is the function which will
34573 contain the dispatch logic. FNDECLS are the function choices for
34574 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34575 in DISPATCH_DECL in which the dispatch code is generated. */
34577 static int
34581 {
34582 tree default_decl;
34583 gimple ifunc_cpu_init_stmt;
34584 gimple_seq gseq;
34586 tree ele;
34592 struct _function_version_info
34593 {
34594 tree version_decl;
34595 tree predicate_chain;
34603 /*fndecls_p is actually a vector. */
34606 /* At least one more version other than the default. */
34613 /* The first version in the vector is the default decl. */
34619 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34620 constructors, so explicity call __builtin_cpu_init here. */
34631 {
34635 /* Get attribute string, parse it and find the right predicate decl.
34636 The predicate function could be a lengthy combination of many
34637 features, like arch-type and various isa-variants. */
34648 actual_versions++;
34649 }
34651 /* Sort the versions according to descending order of dispatch priority. The
34652 priority is based on the ISA. This is not a perfect solution. There
34653 could still be ambiguity. If more than one function version is suitable
34654 to execute, which one should be dispatched? In future, allow the user
34655 to specify a dispatch priority next to the version. */
34665 /* dispatch default version at the end. */
34671 }
34673 /* Comparator function to be used in qsort routine to sort attribute
34674 specification strings to "target". */
34676 static int
34678 {
34682 }
34684 /* ARGLIST is the argument to target attribute. This function tokenizes
34685 the comma separated arguments, sorts them and returns a string which
34686 is a unique identifier for the comma separated arguments. It also
34687 replaces non-identifier characters "=,-" with "_". */
34691 {
34692 tree arg;
34701 {
34706 argnum++;
34709 argnum++;
34710 }
34715 {
34721 }
34723 /* Replace "=,-" with "_". */
34736 {
34738 i++;
34740 }
34747 {
34752 }
34757 }
34759 /* This function changes the assembler name for functions that are
34760 versions. If DECL is a function version and has a "target"
34761 attribute, it appends the attribute string to its assembler name. */
34763 static tree
34765 {
34766 tree version_attr;
34774 "Function versions cannot be marked as gnu_inline,"
34783 /* target attribute string cannot be NULL. */
34787 version_string
34798 /* Allow assembler name to be modified if already set. */
34806 }
34808 /* This function returns true if FN1 and FN2 are versions of the same function,
34809 that is, the target strings of the function decls are different. This assumes
34810 that FN1 and FN2 have the same signature. */
34812 static bool
34814 {
34826 /* At least one function decl should have the target attribute specified. */
34830 /* Diagnose missing target attribute if one of the decls is already
34831 multi-versioned. */
34833 {
34835 {
34837 {
34842 }
34845 fn2);
34848 /* Prevent diagnosing of the same error multiple times. */
34853 }
34855 }
34860 /* The sorted target strings must be different for fn1 and fn2
34861 to be versions. */
34864 else
34871 }
34873 static tree
34875 {
34876 /* For function version, add the target suffix to the assembler name. */
34880 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34882 #endif
34885 }
34887 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34888 is true, append the full path name of the source file. */
34892 {
34900 /* Get a unique name that can be used globally without any chances
34901 of collision at link time. */
34911 /* Use '.' to concatenate names as it is demangler friendly. */
34914 suffix);
34915 else
34919 }
34921 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34923 /* Make a dispatcher declaration for the multi-versioned function DECL.
34924 Calls to DECL function will be replaced with calls to the dispatcher
34925 by the front-end. Return the decl created. */
34927 static tree
34929 {
34930 tree func_decl;
34950 /* Mark this func as external, the resolver will flip it again if
34951 it gets generated. */
34953 /* This will be of type IFUNCs have to be externally visible. */
34957 }
34959 #endif
34961 /* Returns true if decl is multi-versioned and DECL is the default function,
34962 that is it is not tagged with target specific optimization. */
34964 static bool
34966 {
34975 }
34977 /* Make a dispatcher declaration for the multi-versioned function DECL.
34978 Calls to DECL function will be replaced with calls to the dispatcher
34979 by the front-end. Returns the decl of the dispatcher function. */
34981 static tree
34983 {
35005 /* Find the default version and make it the first node. */
35007 /* Go to the beginning of the chain. */
35012 {
35017 }
35019 /* If there is no default node, just return NULL. */
35023 /* Make default info the first node. */
35025 {
35032 }
35036 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35038 {
35043 /* Right now, the dispatching is done via ifunc. */
35049 dispatcher_version_info
35054 /* Set the dispatcher for all the versions. */
35057 {
35060 }
35061 }
35062 else
35063 #endif
35064 {
35066 "multiversioning needs ifunc which is not supported "
35068 }
35071 }
35073 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35074 it to CHAIN. */
35076 static tree
35078 {
35079 tree attr_name;
35080 tree attr_arg_name;
35081 tree attr_args;
35082 tree attr;
35089 }
35091 /* Make the resolver function decl to dispatch the versions of
35092 a multi-versioned function, DEFAULT_DECL. Create an
35093 empty basic block in the resolver and store the pointer in
35094 EMPTY_BB. Return the decl of the resolver function. */
35096 static tree
35100 {
35105 /* IFUNC's have to be globally visible. So, if the default_decl is
35106 not, then the name of the IFUNC should be made unique. */
35110 /* Append the filename to the resolver function if the versions are
35111 not externally visible. This is because the resolver function has
35112 to be externally visible for the loader to find it. So, appending
35113 the filename will prevent conflicts with a resolver function from
35114 another module which is based on the same version name. */
35117 /* The resolver function should return a (void *). */
35128 /* IFUNC resolvers have to be externally visible. */
35132 /* Resolver is not external, body is generated. */
35142 {
35143 /* In this case, each translation unit with a call to this
35144 versioned function will put out a resolver. Ensure it
35145 is comdat to keep just one copy. */
35148 }
35149 /* Build result decl and add to function_decl. */
35165 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35169 /* Create the alias for dispatch to resolver here. */
35170 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35174 }
35176 /* Generate the dispatching code body to dispatch multi-versioned function
35177 DECL. The target hook is called to process the "target" attributes and
35178 provide the code to dispatch the right function at run-time. NODE points
35179 to the dispatcher decl whose body will be created. */
35181 static tree
35183 {
35184 tree resolver_decl;
35185 basic_block empty_bb;
35186 tree default_ver_decl;
35202 /* The first version in the chain corresponds to the default version. */
35205 /* node is going to be an alias, so remove the finalized bit. */
35219 {
35221 /* Check for virtual functions here again, as by this time it should
35222 have been determined if this function needs a vtable index or
35223 not. This happens for methods in derived classes that override
35224 virtual methods in base classes but are not explicitly marked as
35225 virtual. */
35230 }
35236 }
35237 /* This builds the processor_model struct type defined in
35238 libgcc/config/i386/cpuinfo.c */
35240 static tree
35242 {
35249 /* The first 3 fields are unsigned int. */
35251 {
35257 }
35259 /* The last field is an array of unsigned integers of size one. */
35270 }
35272 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35274 static tree
35276 {
35277 tree new_decl;
35280 VAR_DECL,
35282 type);
35295 }
35297 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35298 into an integer defined in libgcc/config/i386/cpuinfo.c */
35300 static tree
35302 {
35308 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35309 enum processor_features
35310 {
35312 F_MMX,
35313 F_POPCNT,
35314 F_SSE,
35315 F_SSE2,
35316 F_SSE3,
35317 F_SSSE3,
35318 F_SSE4_1,
35319 F_SSE4_2,
35320 F_AVX,
35321 F_AVX2,
35322 F_SSE4_A,
35323 F_FMA4,
35324 F_XOP,
35325 F_FMA,
35326 F_AVX512F,
35327 F_BMI,
35328 F_BMI2,
35329 F_MAX
35330 };
35332 /* These are the values for vendor types and cpu types and subtypes
35333 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35334 the corresponding start value. */
35335 enum processor_model
35336 {
35338 M_AMD,
35339 M_CPU_TYPE_START,
35340 M_INTEL_BONNELL,
35341 M_INTEL_CORE2,
35342 M_INTEL_COREI7,
35343 M_AMDFAM10H,
35344 M_AMDFAM15H,
35345 M_INTEL_SILVERMONT,
35346 M_INTEL_KNL,
35347 M_AMD_BTVER1,
35348 M_AMD_BTVER2,
35349 M_CPU_SUBTYPE_START,
35350 M_INTEL_COREI7_NEHALEM,
35351 M_INTEL_COREI7_WESTMERE,
35352 M_INTEL_COREI7_SANDYBRIDGE,
35353 M_AMDFAM10H_BARCELONA,
35354 M_AMDFAM10H_SHANGHAI,
35355 M_AMDFAM10H_ISTANBUL,
35356 M_AMDFAM15H_BDVER1,
35357 M_AMDFAM15H_BDVER2,
35358 M_AMDFAM15H_BDVER3,
35359 M_AMDFAM15H_BDVER4,
35360 M_INTEL_COREI7_IVYBRIDGE,
35361 M_INTEL_COREI7_HASWELL,
35362 M_INTEL_COREI7_BROADWELL
35363 };
35365 static struct _arch_names_table
35366 {
35369 }
35371 {
35398 };
35400 static struct _isa_names_table
35401 {
35404 }
35406 {
35425 };
35439 {
35440 /* *args must be a expr that can contain other EXPRS leading to a
35441 STRING_CST. */
35443 {
35446 }
35448 }
35453 {
35454 tree ref;
35455 tree field;
35456 tree final;
35459 unsigned int NUM_ARCH_NAMES
35468 {
35472 }
35477 /* CPU types are stored in the next field. */
35480 {
35483 }
35485 /* CPU subtypes are stored in the next field. */
35487 {
35490 }
35492 /* Get the appropriate field in __cpu_model. */
35496 /* Check the value. */
35500 }
35502 {
35503 tree ref;
35504 tree array_elt;
35505 tree field;
35506 tree final;
35509 unsigned int NUM_ISA_NAMES
35518 {
35522 }
35525 /* Get the last field, which is __cpu_features. */
35529 /* Get the appropriate field: __cpu_model.__cpu_features */
35533 /* Access the 0th element of __cpu_features array. */
35538 /* Return __cpu_model.__cpu_features[0] & field_val */
35542 }
35544 }
35546 static tree
35549 {
35551 {
35556 {
35559 }
35560 }
35562 #ifdef SUBTARGET_FOLD_BUILTIN
35564 #endif
35567 }
35569 /* Make builtins to detect cpu type and features supported. NAME is
35570 the builtin name, CODE is the builtin code, and FTYPE is the function
35571 type of the builtin. */
35573 static void
35576 {
35577 tree decl;
35578 tree type;
35586 }
35588 /* Make builtins to get CPU type and features supported. The created
35589 builtins are :
35591 __builtin_cpu_init (), to detect cpu type and features,
35592 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35593 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35594 */
35596 static void
35598 {
35605 }
35607 /* Internal method for ix86_init_builtins. */
35609 static void
35611 {
35623 sysv_va_ref =
35626 fnvoid_va_end_ms =
35628 fnvoid_va_start_ms =
35630 fnvoid_va_end_sysv =
35632 fnvoid_va_start_sysv =
35634 NULL_TREE);
35635 fnvoid_va_copy_ms =
35637 NULL_TREE);
35638 fnvoid_va_copy_sysv =
35654 }
35656 static void
35658 {
35661 /* The __float80 type. */
35664 {
35665 /* The __float80 type. */
35670 }
35673 /* The __float128 type. */
35679 /* This macro is built by i386-builtin-types.awk. */
35680 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35681 }
35683 static void
35685 {
35686 tree t;
35690 /* Builtins to get CPU type and features. */
35693 /* TFmode support builtins. */
35699 /* We will expand them to normal call if SSE isn't available since
35700 they are used by libgcc. */
35720 #ifdef SUBTARGET_INIT_BUILTINS
35721 SUBTARGET_INIT_BUILTINS;
35722 #endif
35723 }
35725 /* Return the ix86 builtin for CODE. */
35727 static tree
35729 {
35734 }
35736 /* Errors in the source file can cause expand_expr to return const0_rtx
35737 where we expect a vector. To avoid crashing, use one of the vector
35738 clear instructions. */
35739 static rtx
35741 {
35745 }
35747 /* Fixup modeless constants to fit required mode. */
35748 static rtx
35750 {
35754 }
35756 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35758 static rtx
35760 {
35761 rtx pat;
35781 {
35785 }
35799 }
35801 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35803 static rtx
35807 {
35808 rtx pat;
35816 rtx op;
35817 machine_mode mode;
35823 {
35903 }
35913 {
35920 {
35922 {
35925 {
35943 xop_rotl:
35945 {
35948 gcc_checking_assert
35950 }
35951 else
35952 {
35953 gcc_checking_assert
35964 }
35968 }
35969 }
35970 }
35971 else
35972 {
35973 non_constant:
35977 /* If we aren't optimizing, only allow one memory operand to be
35978 generated. */
35980 num_memory++;
35988 }
35992 }
35995 {
36006 else
36007 {
36013 }
36026 }
36033 }
36035 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36036 insns with vec_merge. */
36038 static rtx
36040 rtx target)
36041 {
36042 rtx pat;
36069 }
36071 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36073 static rtx
36076 {
36077 rtx pat;
36082 rtx op2;
36093 /* Swap operands if we have a comparison that isn't available in
36094 hardware. */
36116 }
36118 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36120 static rtx
36122 rtx target)
36123 {
36124 rtx pat;
36138 /* Swap operands if we have a comparison that isn't available in
36139 hardware. */
36162 const0_rtx)));
36165 }
36167 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36169 static rtx
36171 rtx target)
36172 {
36173 rtx pat;
36198 }
36200 static rtx
36203 {
36204 rtx pat;
36209 rtx op2;
36236 }
36238 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36240 static rtx
36242 rtx target)
36243 {
36244 rtx pat;
36277 const0_rtx)));
36280 }
36282 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36284 static rtx
36287 {
36288 rtx pat;
36326 {
36329 }
36332 {
36341 }
36343 {
36352 }
36353 else
36354 {
36361 }
36369 {
36374 emit_insn
36378 FLAGS_REG),
36379 const0_rtx)));
36381 }
36382 else
36384 }
36387 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36389 static rtx
36392 {
36393 rtx pat;
36421 {
36424 }
36427 {
36436 }
36438 {
36447 }
36448 else
36449 {
36456 }
36464 {
36469 emit_insn
36473 FLAGS_REG),
36474 const0_rtx)));
36476 }
36477 else
36479 }
36481 /* Subroutine of ix86_expand_builtin to take care of insns with
36482 variable number of operands. */
36484 static rtx
36487 {
36493 struct
36494 {
36495 rtx op;
36496 machine_mode mode;
36507 {
37217 }
37222 {
37225 }
37228 {
37235 }
37236 else
37237 {
37240 }
37243 {
37250 {
37251 /* SIMD shift insns take either an 8-bit immediate or
37252 register as count. But builtin functions take int as
37253 count. If count doesn't match, we put it in register. */
37255 {
37259 }
37260 }
37263 {
37266 {
37375 {
37379 {
37382 }
37388 }
37390 }
37391 }
37392 else
37393 {
37397 /* If we aren't optimizing, only allow one memory operand to
37398 be generated. */
37400 num_memory++;
37405 {
37408 }
37409 else
37410 {
37413 }
37414 }
37418 }
37421 {
37446 }
37453 }
37455 /* Transform pattern of following layout:
37456 (parallel [
37457 set (A B)
37458 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37459 ])
37460 into:
37461 (set (A B))
37463 Or:
37464 (parallel [ A B
37465 ...
37466 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37467 ...
37468 ])
37469 into:
37470 (parallel [ A B ... ]) */
37472 static rtx
37474 {
37481 {
37490 }
37491 else
37492 {
37498 {
37503 }
37505 /* No more than 1 occurence was removed. */
37509 }
37510 }
37512 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37513 with rounding. */
37514 static rtx
37517 {
37534 /* See avxintrin.h for values. */
37536 {
37540 };
37542 {
37547 };
37550 {
37553 }
37555 {
37558 }
37561 {
37564 }
37587 ? CODE_FOR_sse_ucomi_round
37594 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37596 {
37602 }
37603 else
37604 {
37607 }
37613 set_dst,
37614 const0_rtx)));
37617 }
37619 static rtx
37622 {
37623 rtx pat;
37625 struct
37626 {
37627 rtx op;
37628 machine_mode mode;
37637 {
37720 }
37730 {
37737 {
37739 {
37741 {
37757 }
37758 }
37759 }
37761 {
37763 {
37766 }
37768 /* If there is no rounding use normal version of the pattern. */
37771 }
37772 else
37773 {
37780 {
37783 }
37784 else
37785 {
37788 }
37789 }
37793 }
37796 {
37821 }
37831 }
37833 /* Subroutine of ix86_expand_builtin to take care of special insns
37834 with variable number of operands. */
37836 static rtx
37839 {
37840 tree arg;
37844 struct
37845 {
37846 rtx op;
37847 machine_mode mode;
37856 {
37896 {
37904 }
37923 /* Reserve memory operand for target. */
37926 {
37927 /* These builtins and instructions require the memory
37928 to be properly aligned. */
37947 }
37976 {
37977 /* These builtins and instructions require the memory
37978 to be properly aligned. */
37995 }
37996 /* FALLTHRU */
38034 /* Reserve memory operand for target. */
38061 {
38062 /* These builtins and instructions require the memory
38063 to be properly aligned. */
38086 }
38099 }
38104 {
38109 {
38112 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38113 on it. Try to improve it using get_pointer_alignment,
38114 and if the special builtin is one that requires strict
38115 mode alignment, also from it's GET_MODE_ALIGNMENT.
38116 Failure to do so could lead to ix86_legitimate_combined_insn
38117 rejecting all changes to such insns. */
38123 }
38124 else
38127 }
38128 else
38129 {
38136 }
38139 {
38148 {
38150 {
38156 else
38159 }
38160 }
38161 else
38162 {
38164 {
38165 /* This must be the memory operand. */
38168 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38169 on it. Try to improve it using get_pointer_alignment,
38170 and if the special builtin is one that requires strict
38171 mode alignment, also from it's GET_MODE_ALIGNMENT.
38172 Failure to do so could lead to ix86_legitimate_combined_insn
38173 rejecting all changes to such insns. */
38179 }
38180 else
38181 {
38182 /* This must be register. */
38190 else
38191 {
38194 }
38195 }
38196 }
38200 }
38203 {
38218 }
38224 }
38226 /* Return the integer constant in ARG. Constrain it to be in the range
38227 of the subparts of VEC_TYPE; issue an error if not. */
38229 static int
38231 {
38236 {
38239 }
38242 }
38244 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38245 ix86_expand_vector_init. We DO have language-level syntax for this, in
38246 the form of (type){ init-list }. Except that since we can't place emms
38247 instructions from inside the compiler, we can't allow the use of MMX
38248 registers unless the user explicitly asks for it. So we do *not* define
38249 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38250 we have builtins invoked by mmintrin.h that gives us license to emit
38251 these sorts of instructions. */
38253 static rtx
38255 {
38265 {
38268 }
38275 }
38277 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38278 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38279 had a language-level syntax for referencing vector elements. */
38281 static rtx
38283 {
38287 rtx op0;
38307 }
38309 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38310 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38311 a language-level syntax for referencing vector elements. */
38313 static rtx
38315 {
38339 /* OP0 is the source of these builtin functions and shouldn't be
38340 modified. Create a copy, use it and return it as target. */
38346 }
38348 /* Emit conditional move of SRC to DST with condition
38349 OP1 CODE OP2. */
38350 static void
38352 {
38353 rtx t;
38356 {
38361 }
38362 else
38363 {
38369 }
38370 }
38372 /* Choose max of DST and SRC and put it to DST. */
38373 static void
38375 {
38377 }
38379 /* Expand an expression EXP that calls a built-in function,
38380 with result going to TARGET if that's convenient
38381 (and in mode MODE if that's convenient).
38382 SUBTARGET may be used as the target for computing one of EXP's operands.
38383 IGNORE is nonzero if the value is to be ignored. */
38385 static rtx
38388 {
38398 /* For CPU builtins that can be folded, fold first and expand the fold. */
38400 {
38402 {
38403 /* Make it call __cpu_indicator_init in libgcc. */
38409 }
38412 {
38417 }
38418 }
38420 /* Determine whether the builtin function is available under the current ISA.
38421 Originally the builtin was not created if it wasn't applicable to the
38422 current ISA based on the command line switches. With function specific
38423 options, we need to check in the context of the function making the call
38424 whether it is supported. */
38427 {
38433 else
38434 {
38438 }
38440 }
38443 {
38461 /* Builtin arg1 is size of block but instruction op1 should
38462 be (size - 1). */
38553 /* If no bounds were specified for returned value,
38554 then use INIT bounds. It usually happens when
38555 some built-in function is expanded. */
38557 {
38566 }
38572 {
38575 /* Return value and lb. */
38577 /* Bounds. */
38579 /* Size. */
38586 /* Size was passed but we need to use (size - 1) as for bndmk. */
38590 /* Add LB to size and inverse to get UB. */
38600 /* We need to move bounds to memory before any computations. */
38603 else
38604 {
38607 }
38609 /* Generate mem expression to be used for access to LB and UB. */
38615 /* Compute LB. */
38620 /* Compute UB. UB is stored in 1's complement form. Therefore
38621 we also use max here. */
38630 }
38633 {
38651 /* Put first bounds to temporaries. */
38655 {
38659 }
38660 else
38661 {
38665 }
38667 /* Put second bounds to temporaries. */
38671 {
38675 }
38676 else
38677 {
38681 }
38683 /* Compute LB. */
38687 /* Compute UB. UB is stored in 1's complement form. Therefore
38688 we also use max here. */
38695 }
38698 {
38699 tree name;
38700 rtx symbol;
38718 }
38721 {
38732 /* We need to move bounds to memory first. */
38735 else
38736 {
38739 }
38741 /* Generate mem expression to access LB and load it. */
38746 }
38749 {
38760 /* We need to move bounds to memory first. */
38763 else
38764 {
38767 }
38769 /* Generate mem expression to access UB. */
38772 /* We need to inverse all bits of UB. */
38779 }
38784 ? CODE_FOR_mmx_maskmovq
38786 /* Note the arg order is different from the operand order. */
38907 {
38908 REAL_VALUE_TYPE inf;
38909 rtx tmp;
38921 }
38931 {
38937 insn = (TARGET_64BIT
38941 }
38943 {
38944 insn = (TARGET_64BIT
38948 }
38949 else
38950 {
38953 insn = (TARGET_64BIT
38961 {
38964 }
38966 }
38969 {
38970 /* mode is VOIDmode if __builtin_rd* has been called
38971 without lhs. */
38975 }
38978 {
38983 }
38996 {
39017 }
39023 {
39026 }
39052 {
39055 }
39061 {
39065 {
39104 }
39109 }
39110 else
39111 {
39113 {
39134 }
39136 }
39166 ? CODE_FOR_tbm_bextri_si
39169 {
39172 }
39173 else
39174 {
39183 }
39199 rdrand_step:
39206 {
39209 }
39215 /* Emit SImode conditional move. */
39217 {
39220 }
39223 else
39231 const0_rtx);
39250 rdseed_step:
39257 {
39260 }
39266 const0_rtx);
39295 addcarryx:
39303 /* Generate CF from input operand. */
39308 /* Gen ADCX instruction to compute X+Y+CF. */
39323 /* Store the result. */
39326 {
39329 }
39332 /* Return current CF value. */
39374 kortest:
39388 /* Emit kortest. */
39390 /* And use setcc to return result from flags. */
39648 gather_gen:
39649 rtx half;
39662 /* Note the arg order is different from the operand order. */
39673 else
39677 {
39701 else
39708 {
39713 }
39722 else
39729 {
39734 }
39738 }
39740 /* Force memory operand only with base register here. But we
39741 don't want to do it on memory operand for other builtin
39742 functions. */
39755 {
39758 }
39759 else
39760 {
39763 }
39765 {
39768 }
39770 /* Optimize. If mask is known to have all high bits set,
39771 replace op0 with pc_rtx to signal that the instruction
39772 overwrites the whole destination and doesn't use its
39773 previous contents. */
39775 {
39777 {
39780 }
39782 {
39785 {
39789 negative++;
39792 negative++;
39793 }
39796 }
39799 {
39800 /* Recognize also when mask is like:
39801 __v2df src = _mm_setzero_pd ();
39802 __v2df mask = _mm_cmpeq_pd (src, src);
39803 or
39804 __v8sf src = _mm256_setzero_ps ();
39805 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39806 as that is a cheaper way to load all ones into
39807 a register than having to load a constant from
39808 memory. */
39811 {
39816 {
39823 /* FALLTHRU */
39833 }
39834 }
39835 }
39836 }
39844 {
39870 }
39873 scatter_gen:
39889 /* Force memory operand only with base register here. But we
39890 don't want to do it on memory operand for other builtin
39891 functions. */
39900 {
39903 }
39904 else
39905 {
39908 }
39917 {
39920 }
39929 vec_prefetch_gen:
39949 {
39952 }
39954 {
39957 }
39962 /* Force memory operand only with base register here. But we
39963 don't want to do it on memory operand for other builtin
39964 functions. */
39971 {
39974 }
39977 {
39980 }
39996 {
39999 }
40005 }
40018 {
40022 /* Emit a normal call if SSE isn't available. */
40026 }
40055 }
40057 /* This returns the target-specific builtin with code CODE if
40058 current_function_decl has visibility on this builtin, which is checked
40059 using isa flags. Returns NULL_TREE otherwise. */
40062 {
40066 /* Determine the isa flags of current_function_decl. */
40078 else
40080 }
40082 /* Return function decl for target specific builtin
40083 for given MPX builtin passed i FCODE. */
40084 static tree
40086 {
40088 {
40124 }
40127 }
40129 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40131 Return an address to be used to load/store bounds for pointer
40132 passed in SLOT.
40134 SLOT_NO is an integer constant holding number of a target
40135 dependent special slot to be used in case SLOT is not a memory.
40137 SPECIAL_BASE is a pointer to be used as a base of fake address
40138 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40139 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40141 static rtx
40143 {
40146 /* NULL slot means we pass bounds for pointer not passed to the
40147 function at all. Register slot means we pass pointer in a
40148 register. In both these cases bounds are passed via Bounds
40149 Table. Since we do not have actual pointer stored in memory,
40150 we have to use fake addresses to access Bounds Table. We
40151 start with (special_base - sizeof (void*)) and decrease this
40152 address by pointer size to get addresses for other slots. */
40154 {
40158 }
40159 /* If pointer is passed in a memory then its address is used to
40160 access Bounds Table. */
40162 {
40166 }
40167 else
40171 }
40173 /* Expand pass uses this hook to load bounds for function parameter
40174 PTR passed in SLOT in case its bounds are not passed in a register.
40176 If SLOT is a memory, then bounds are loaded as for regular pointer
40177 loaded from memory. PTR may be NULL in case SLOT is a memory.
40178 In such case value of PTR (if required) may be loaded from SLOT.
40180 If SLOT is NULL or a register then SLOT_NO is an integer constant
40181 holding number of the target dependent special slot which should be
40182 used to obtain bounds.
40184 Return loaded bounds. */
40186 static rtx
40188 {
40190 rtx addr;
40192 /* Get address to be used to access Bounds Table. Special slots start
40193 at the location of return address of the current function. */
40196 /* Load pointer value from a memory if we don't have it. */
40198 {
40201 }
40208 }
40210 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40211 passed in SLOT in case BOUNDS are not passed in a register.
40213 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40214 stored in memory. PTR may be NULL in case SLOT is a memory.
40215 In such case value of PTR (if required) may be loaded from SLOT.
40217 If SLOT is NULL or a register then SLOT_NO is an integer constant
40218 holding number of the target dependent special slot which should be
40219 used to store BOUNDS. */
40221 static void
40223 {
40224 rtx addr;
40226 /* Get address to be used to access Bounds Table. Special slots start
40227 at the location of return address of a called function. */
40230 /* Load pointer value from a memory if we don't have it. */
40232 {
40235 }
40244 }
40246 /* Load and return bounds returned by function in SLOT. */
40248 static rtx
40250 {
40251 rtx res;
40258 }
40260 /* Store BOUNDS returned by function into SLOT. */
40262 static void
40264 {
40267 }
40269 /* Returns a function decl for a vectorized version of the builtin function
40270 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40271 if it is not available. */
40273 static tree
40275 tree type_in)
40276 {
40292 {
40295 {
40302 }
40307 {
40310 }
40315 {
40322 }
40328 /* The round insn does not trap on denormals. */
40333 {
40340 }
40346 /* The round insn does not trap on denormals. */
40351 {
40356 }
40362 /* The round insn does not trap on denormals. */
40367 {
40374 }
40380 /* The round insn does not trap on denormals. */
40385 {
40390 }
40397 {
40402 }
40409 {
40414 }
40420 /* The round insn does not trap on denormals. */
40425 {
40432 }
40438 /* The round insn does not trap on denormals. */
40443 {
40448 }
40453 {
40460 }
40465 {
40472 }
40476 /* The round insn does not trap on denormals. */
40481 {
40486 }
40490 /* The round insn does not trap on denormals. */
40495 {
40500 }
40504 /* The round insn does not trap on denormals. */
40509 {
40514 }
40518 /* The round insn does not trap on denormals. */
40523 {
40528 }
40532 /* The round insn does not trap on denormals. */
40537 {
40542 }
40546 /* The round insn does not trap on denormals. */
40551 {
40556 }
40560 /* The round insn does not trap on denormals. */
40565 {
40570 }
40574 /* The round insn does not trap on denormals. */
40579 {
40584 }
40588 /* The round insn does not trap on denormals. */
40593 {
40598 }
40602 /* The round insn does not trap on denormals. */
40607 {
40612 }
40617 {
40622 }
40627 {
40632 }
40637 }
40639 /* Dispatch to a handler for a vectorization library. */
40642 type_in);
40645 }
40647 /* Handler for an SVML-style interface to
40648 a library with vectorized intrinsics. */
40650 static tree
40652 {
40660 /* The SVML is suitable for unsafe math only. */
40673 {
40720 }
40729 {
40732 }
40733 else
40736 /* Convert to uppercase. */
40741 args;
40743 arity++;
40747 else
40750 /* Build a function declaration for the vectorized function. */
40759 }
40761 /* Handler for an ACML-style interface to
40762 a library with vectorized intrinsics. */
40764 static tree
40766 {
40774 /* The ACML is 64bits only and suitable for unsafe math only as
40775 it does not correctly support parts of IEEE with the required
40776 precision such as denormals. */
40790 {
40820 }
40827 args;
40829 arity++;
40833 else
40836 /* Build a function declaration for the vectorized function. */
40845 }
40847 /* Returns a decl of a function that implements gather load with
40848 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40849 Return NULL_TREE if it is not available. */
40851 static tree
40854 {
40870 /* v*gather* insn sign extends index to pointer mode. */
40882 {
40886 else
40892 else
40898 else
40904 else
40910 else
40916 else
40922 else
40928 else
40934 else
40940 else
40946 else
40952 else
40957 }
40960 }
40962 /* Returns a code for a target-specific builtin that implements
40963 reciprocal of the function, or NULL_TREE if not available. */
40965 static tree
40967 {
40974 /* Machine dependent builtins. */
40976 {
40977 /* Vectorized version of sqrt to rsqrt conversion. */
40986 }
40987 else
40988 /* Normal builtins. */
40990 {
40991 /* Sqrt to rsqrt conversion. */
40997 }
40998 }
40999 \f
41000 /* Helper for avx_vpermilps256_operand et al. This is also used by
41001 the expansion functions to turn the parallel back into a mask.
41002 The return value is 0 for no match and the imm8+1 for a match. */
41004 int
41006 {
41014 /* Validate that all of the elements are constants, and not totally
41015 out of range. Copy the data into an integral array to make the
41016 subsequent checks easier. */
41018 {
41028 }
41031 {
41033 /* In the 512-bit DFmode case, we can only move elements within
41034 a 128-bit lane. First fill the second part of the mask,
41035 then fallthru. */
41037 {
41041 }
41043 {
41047 }
41048 /* FALLTHRU */
41051 /* In the 256-bit DFmode case, we can only move elements within
41052 a 128-bit lane. */
41054 {
41058 }
41060 {
41064 }
41068 /* In 512 bit SFmode case, permutation in the upper 256 bits
41069 must mirror the permutation in the lower 256-bits. */
41073 /* FALLTHRU */
41076 /* In 256 bit SFmode case, we have full freedom of
41077 movement within the low 128-bit lane, but the high 128-bit
41078 lane must mirror the exact same pattern. */
41083 /* FALLTHRU */
41087 /* In the 128-bit case, we've full freedom in the placement of
41088 the elements from the source operand. */
41095 }
41097 /* Make sure success has a non-zero value by adding one. */
41099 }
41101 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41102 the expansion functions to turn the parallel back into a mask.
41103 The return value is 0 for no match and the imm8+1 for a match. */
41105 int
41107 {
41115 /* Validate that all of the elements are constants, and not totally
41116 out of range. Copy the data into an integral array to make the
41117 subsequent checks easier. */
41119 {
41129 }
41131 /* Validate that the halves of the permute are halves. */
41139 /* Reconstruct the mask. */
41141 {
41147 }
41149 /* Make sure success has a non-zero value by adding one. */
41151 }
41152 \f
41153 /* Return a register priority for hard reg REGNO. */
41154 static int
41156 {
41157 /* ebp and r13 as the base always wants a displacement, r12 as the
41158 base always wants an index. So discourage their usage in an
41159 address. */
41164 /* New x86-64 int registers result in bigger code size. Discourage
41165 them. */
41168 /* New x86-64 SSE registers result in bigger code size. Discourage
41169 them. */
41172 /* Usage of AX register results in smaller code. Prefer it. */
41176 }
41178 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41180 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41181 QImode must go into class Q_REGS.
41182 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41183 movdf to do mem-to-mem moves through integer regs. */
41185 static reg_class_t
41187 {
41190 /* We're only allowed to return a subclass of CLASS. Many of the
41191 following checks fail for NO_REGS, so eliminate that early. */
41195 /* All classes can load zeros. */
41199 /* Force constants into memory if we are loading a (nonzero) constant into
41200 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41201 instructions to load from a constant. */
41208 /* Prefer SSE regs only, if we can use them for math. */
41212 /* Floating-point constants need more complex checks. */
41214 {
41215 /* General regs can load everything. */
41219 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41220 zero above. We only want to wind up preferring 80387 registers if
41221 we plan on doing computation with them. */
41224 {
41225 /* Limit class to non-sse. */
41234 }
41237 }
41239 /* Generally when we see PLUS here, it's the function invariant
41240 (plus soft-fp const_int). Which can only be computed into general
41241 regs. */
41245 /* QImode constants are easy to load, but non-constant QImode data
41246 must go into Q_REGS. */
41248 {
41254 }
41257 }
41259 /* Discourage putting floating-point values in SSE registers unless
41260 SSE math is being used, and likewise for the 387 registers. */
41261 static reg_class_t
41263 {
41266 /* Restrict the output reload class to the register bank that we are doing
41267 math on. If we would like not to return a subset of CLASS, reject this
41268 alternative: if reload cannot do this, it will still use its choice. */
41274 {
41279 else
41281 }
41284 }
41286 static reg_class_t
41289 {
41290 /* Double-word spills from general registers to non-offsettable memory
41291 references (zero-extended addresses) require special handling. */
41297 {
41299 ? CODE_FOR_reload_noff_load
41301 /* Add the cost of moving address to a temporary. */
41305 }
41307 /* QImode spills from non-QI registers require
41308 intermediate register on 32bit targets. */
41314 {
41319 else
41325 /* Return Q_REGS if the operand is in memory. */
41328 }
41330 /* This condition handles corner case where an expression involving
41331 pointers gets vectorized. We're trying to use the address of a
41332 stack slot as a vector initializer.
41334 (set (reg:V2DI 74 [ vect_cst_.2 ])
41335 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41337 Eventually frame gets turned into sp+offset like this:
41339 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41340 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41341 (const_int 392 [0x188]))))
41343 That later gets turned into:
41345 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41346 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41347 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41349 We'll have the following reload recorded:
41351 Reload 0: reload_in (DI) =
41352 (plus:DI (reg/f:DI 7 sp)
41353 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41354 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41355 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41356 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41357 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41358 reload_reg_rtx: (reg:V2DI 22 xmm1)
41360 Which isn't going to work since SSE instructions can't handle scalar
41361 additions. Returning GENERAL_REGS forces the addition into integer
41362 register and reload can handle subsequent reloads without problems. */
41370 }
41372 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41374 static bool
41376 {
41378 {
41394 }
41397 }
41399 /* If we are copying between general and FP registers, we need a memory
41400 location. The same is true for SSE and MMX registers.
41402 To optimize register_move_cost performance, allow inline variant.
41404 The macro can't work reliably when one of the CLASSES is class containing
41405 registers from multiple units (SSE, MMX, integer). We avoid this by never
41406 combining those units in single alternative in the machine description.
41407 Ensure that this constraint holds to avoid unexpected surprises.
41409 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41410 enforce these sanity checks. */
41415 {
41424 {
41427 }
41432 /* Between mask and general, we have moves no larger than word size. */
41437 /* ??? This is a lie. We do have moves between mmx/general, and for
41438 mmx/sse2. But by saying we need secondary memory we discourage the
41439 register allocator from using the mmx registers unless needed. */
41444 {
41445 /* SSE1 doesn't have any direct moves from other classes. */
41449 /* If the target says that inter-unit moves are more expensive
41450 than moving through memory, then don't generate them. */
41455 /* Between SSE and general, we have moves no larger than word size. */
41458 }
41461 }
41463 bool
41466 {
41468 }
41470 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41472 On the 80386, this is the size of MODE in words,
41473 except in the FP regs, where a single reg is always enough. */
41475 static unsigned char
41477 {
41479 {
41484 else
41486 }
41487 else
41488 {
41491 else
41493 }
41494 }
41496 /* Return true if the registers in CLASS cannot represent the change from
41497 modes FROM to TO. */
41499 bool
41502 {
41506 /* x87 registers can't do subreg at all, as all values are reformatted
41507 to extended precision. */
41512 {
41513 /* Vector registers do not support QI or HImode loads. If we don't
41514 disallow a change to these modes, reload will assume it's ok to
41515 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41516 the vec_dupv4hi pattern. */
41519 }
41522 }
41524 /* Return the cost of moving data of mode M between a
41525 register and memory. A value of 2 is the default; this cost is
41526 relative to those in `REGISTER_MOVE_COST'.
41528 This function is used extensively by register_move_cost that is used to
41529 build tables at startup. Make it inline in this case.
41530 When IN is 2, return maximum of in and out move cost.
41532 If moving between registers and memory is more expensive than
41533 between two registers, you should define this macro to express the
41534 relative cost.
41536 Model also increased moving costs of QImode registers in non
41537 Q_REGS classes.
41538 */
41542 {
41545 {
41548 {
41560 }
41564 }
41566 {
41569 {
41581 }
41585 }
41587 {
41590 {
41599 }
41603 }
41605 {
41608 {
41614 else
41619 }
41620 else
41621 {
41626 else
41628 }
41635 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41642 else
41646 }
41647 }
41649 static int
41652 {
41654 }
41657 /* Return the cost of moving data from a register in class CLASS1 to
41658 one in class CLASS2.
41660 It is not required that the cost always equal 2 when FROM is the same as TO;
41661 on some machines it is expensive to move between registers if they are not
41662 general registers. */
41664 static int
41666 reg_class_t class2_i)
41667 {
41671 /* In case we require secondary memory, compute cost of the store followed
41672 by load. In order to avoid bad register allocation choices, we need
41673 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41676 {
41682 /* In case of copying from general_purpose_register we may emit multiple
41683 stores followed by single load causing memory size mismatch stall.
41684 Count this as arbitrarily high cost of 20. */
41689 /* In the case of FP/MMX moves, the registers actually overlap, and we
41690 have to switch modes in order to treat them differently. */
41696 }
41698 /* Moves between SSE/MMX and integer unit are expensive. */
41702 /* ??? By keeping returned value relatively high, we limit the number
41703 of moves between integer and MMX/SSE registers for all targets.
41704 Additionally, high value prevents problem with x86_modes_tieable_p(),
41705 where integer modes in MMX/SSE registers are not tieable
41706 because of missing QImode and HImode moves to, from or between
41707 MMX/SSE registers. */
41717 }
41719 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41720 MODE. */
41722 bool
41724 {
41725 /* Flags and only flags can only hold CCmode values. */
41736 || (TARGET_AVX512BW
41741 {
41742 /* We implement the move patterns for all vector modes into and
41743 out of SSE registers, even when no operation instructions
41744 are available. */
41746 /* For AVX-512 we allow, regardless of regno:
41747 - XI mode
41748 - any of 512-bit wide vector mode
41749 - any scalar mode. */
41756 /* TODO check for QI/HI scalars. */
41757 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41765 /* xmm16-xmm31 are only available for AVX-512. */
41769 /* OImode and AVX modes are available only when AVX is enabled. */
41776 }
41778 {
41779 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41780 so if the register is available at all, then we can move data of
41781 the given mode into or out of it. */
41784 }
41787 {
41788 /* Take care for QImode values - they can be in non-QI regs,
41789 but then they do cause partial register stalls. */
41794 /* LRA checks if the hard register is OK for the given mode.
41795 QImode values can live in non-QI regs, so we allow all
41796 registers here. */
41800 }
41801 /* We handle both integer and floats in the general purpose registers. */
41808 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41809 on to use that value in smaller contexts, this can easily force a
41810 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41811 supporting DImode, allow it. */
41816 }
41818 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41819 tieable integer mode. */
41821 static bool
41823 {
41825 {
41838 }
41839 }
41841 /* Return true if MODE1 is accessible in a register that can hold MODE2
41842 without copying. That is, all register classes that can hold MODE2
41843 can also hold MODE1. */
41845 bool
41847 {
41855 /* MODE2 being XFmode implies fp stack or general regs, which means we
41856 can tie any smaller floating point modes to it. Note that we do not
41857 tie this with TFmode. */
41861 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41862 that we can tie it with SFmode. */
41866 /* If MODE2 is only appropriate for an SSE register, then tie with
41867 any other mode acceptable to SSE registers. */
41877 /* If MODE2 is appropriate for an MMX register, then tie
41878 with any other mode acceptable to MMX registers. */
41885 }
41887 /* Return the cost of moving between two registers of mode MODE. */
41889 static int
41891 {
41895 {
41927 }
41929 /* Return the cost of moving between two registers of mode MODE,
41930 assuming that the move will be in pieces of at most UNITS bytes. */
41932 }
41934 /* Compute a (partial) cost for rtx X. Return true if the complete
41935 cost has been computed, and false if subexpressions should be
41936 scanned. In either case, *TOTAL contains the cost result. */
41938 static bool
41941 {
41942 rtx mask;
41949 {
41953 {
41956 }
41968 && !(TARGET_64BIT
41973 else
41983 {
41993 }
41995 {
41998 {
42007 }
42008 }
42009 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42010 it'll probably end up. Add a penalty for size. */
42017 /* The zero extensions is often completely free on x86_64, so make
42018 it as cheap as possible. */
42024 else
42036 {
42039 {
42042 }
42045 {
42048 }
42049 }
42050 /* FALLTHRU */
42057 {
42058 /* ??? Should be SSE vector operation cost. */
42059 /* At least for published AMD latencies, this really is the same
42060 as the latency for a simple fpu operation like fabs. */
42061 /* V*QImode is emulated with 1-11 insns. */
42063 {
42066 {
42067 /* For XOP we use vpshab, which requires a broadcast of the
42068 value to the variable shift insn. For constants this
42069 means a V16Q const in mem; even when we can perform the
42070 shift with one insn set the cost to prefer paddb. */
42072 {
42077 }
42079 }
42083 }
42084 else
42086 }
42088 {
42090 {
42093 else
42095 }
42096 else
42097 {
42100 else
42102 }
42103 }
42104 else
42105 {
42110 {
42111 /* Return the cost after shift-and truncation. */
42114 }
42115 else
42117 }
42121 {
42122 rtx sub;
42127 /* ??? SSE scalar/vector cost should be used here. */
42128 /* ??? Bald assumption that fma has the same cost as fmul. */
42132 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42143 }
42147 {
42148 /* ??? SSE scalar cost should be used here. */
42151 }
42153 {
42156 }
42158 {
42159 /* ??? SSE vector cost should be used here. */
42162 }
42164 {
42165 /* V*QImode is emulated with 7-13 insns. */
42167 {
42174 }
42175 /* V*DImode is emulated with 5-8 insns. */
42177 {
42180 else
42182 }
42183 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42184 insns, including two PMULUDQ. */
42187 else
42190 }
42191 else
42192 {
42197 {
42200 nbits++;
42201 }
42202 else
42203 /* This is arbitrary. */
42206 /* Compute costs correctly for widening multiplication. */
42210 {
42217 {
42221 else
42223 }
42227 }
42235 }
42242 /* ??? SSE cost should be used here. */
42247 /* ??? SSE vector cost should be used here. */
42249 else
42256 {
42261 {
42264 {
42272 }
42273 }
42276 {
42279 {
42285 }
42286 }
42288 {
42296 }
42297 }
42298 /* FALLTHRU */
42302 {
42303 /* ??? SSE cost should be used here. */
42306 }
42308 {
42311 }
42313 {
42314 /* ??? SSE vector cost should be used here. */
42317 }
42318 /* FALLTHRU */
42325 {
42332 }
42333 /* FALLTHRU */
42337 {
42338 /* ??? SSE cost should be used here. */
42341 }
42343 {
42346 }
42348 {
42349 /* ??? SSE vector cost should be used here. */
42352 }
42353 /* FALLTHRU */
42357 {
42358 /* ??? Should be SSE vector operation cost. */
42359 /* At least for published AMD latencies, this really is the same
42360 as the latency for a simple fpu operation like fabs. */
42362 }
42365 else
42374 {
42375 /* This kind of construct is implemented using test[bwl].
42376 Treat it as if we had an AND. */
42381 }
42391 /* ??? SSE cost should be used here. */
42396 /* ??? SSE vector cost should be used here. */
42402 /* ??? SSE cost should be used here. */
42407 /* ??? SSE vector cost should be used here. */
42419 /* ??? Assume all of these vector manipulation patterns are
42420 recognizable. In which case they all pretty much have the
42421 same cost. */
42426 /* This is masked instruction, assume the same cost,
42427 as nonmasked variant. */
42430 else
42436 }
42437 }
42439 #if TARGET_MACHO
42443 /* Given a symbol name and its associated stub, write out the
42444 definition of the stub. */
42446 void
42448 {
42453 /* For 64-bit we shouldn't get here. */
42456 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42473 else
42480 {
42482 }
42484 {
42485 /* PIC stub. */
42486 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42492 }
42493 else
42496 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42497 it needs no stub-binding-helper. */
42504 {
42507 }
42508 else
42513 /* N.B. Keep the correspondence of these
42514 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42515 old-pic/new-pic/non-pic stubs; altering this will break
42516 compatibility with existing dylibs. */
42518 {
42519 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42521 }
42522 else
42523 /* 16-byte -mdynamic-no-pic stub. */
42529 }
42532 /* Order the registers for register allocator. */
42534 void
42536 {
42540 /* First allocate the local general purpose registers. */
42545 /* Global general purpose registers. */
42550 /* x87 registers come first in case we are doing FP math
42551 using them. */
42556 /* SSE registers. */
42562 /* Extended REX SSE registers. */
42566 /* Mask register. */
42570 /* MPX bound registers. */
42574 /* x87 registers. */
42582 /* Initialize the rest of array as we do not allocate some registers
42583 at all. */
42586 }
42588 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42589 in struct attribute_spec handler. */
42590 static tree
42592 tree args,
42595 {
42600 {
42602 name);
42605 }
42607 {
42609 name);
42612 }
42614 {
42615 tree cst;
42619 {
42622 name);
42624 }
42627 {
42630 name);
42632 }
42635 }
42638 }
42640 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42641 struct attribute_spec.handler. */
42642 static tree
42645 {
42650 {
42652 name);
42655 }
42657 /* Can combine regparm with all attributes but fastcall. */
42659 {
42661 {
42663 }
42666 }
42668 {
42670 {
42672 }
42675 }
42678 }
42680 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42681 struct attribute_spec.handler. */
42682 static tree
42685 {
42688 {
42691 }
42692 else
42696 {
42698 name);
42700 }
42706 {
42708 name);
42710 }
42713 }
42715 static tree
42718 {
42720 {
42722 name);
42724 }
42726 }
42728 static bool
42730 {
42734 }
42736 /* Returns an expression indicating where the this parameter is
42737 located on entry to the FUNCTION. */
42739 static rtx
42741 {
42747 {
42752 else
42755 }
42760 {
42767 {
42772 }
42773 else
42774 {
42777 {
42783 }
42784 }
42786 }
42790 }
42792 /* Determine whether x86_output_mi_thunk can succeed. */
42794 static bool
42796 const_tree function)
42797 {
42798 /* 64-bit can handle anything. */
42802 /* For 32-bit, everything's fine if we have one free register. */
42806 /* Need a free register for vcall_offset. */
42810 /* Need a free register for GOT references. */
42814 /* Otherwise ok. */
42816 }
42818 /* Output the assembler code for a thunk function. THUNK_DECL is the
42819 declaration for the thunk function itself, FUNCTION is the decl for
42820 the target function. DELTA is an immediate constant offset to be
42821 added to THIS. If VCALL_OFFSET is nonzero, the word at
42822 *(*this + vcall_offset) should be added to THIS. */
42824 static void
42827 {
42835 else
42836 {
42842 else
42844 }
42848 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42849 pull it in now and let DELTA benefit. */
42853 {
42854 /* Put the this parameter into %eax. */
42857 }
42858 else
42861 /* Adjust the this parameter by a fixed constant. */
42863 {
42868 {
42870 {
42874 }
42875 }
42878 }
42880 /* Adjust the this parameter by a value stored in the vtable. */
42882 {
42892 /* Adjust the this parameter. */
42896 {
42900 }
42907 vcall_mem));
42908 else
42910 }
42912 /* If necessary, drop THIS back to its stack slot. */
42918 {
42921 ;
42922 else
42923 {
42927 }
42928 }
42929 else
42930 {
42932 ;
42933 #if TARGET_MACHO
42935 {
42938 }
42940 else
42941 {
42949 }
42950 }
42952 /* Our sibling call patterns do not allow memories, because we have no
42953 predicate that can distinguish between frame and non-frame memory.
42954 For our purposes here, we can get away with (ab)using a jump pattern,
42955 because we're going to do no optimization. */
42957 {
42959 {
42965 }
42966 else
42968 }
42969 else
42970 {
42972 {
42973 // CM_LARGE_PIC always uses pseudo PIC register which is
42974 // uninitialized. Since FUNCTION is local and calling it
42975 // doesn't go through PLT, we use scratch register %r11 as
42976 // PIC register and initialize it here.
42981 }
42984 {
42990 }
42996 }
42999 /* Emit just enough of rest_of_compilation to get the insns emitted.
43000 Note that use_thunk calls assemble_start_function et al. */
43006 }
43008 static void
43010 {
43014 #if TARGET_MACHO
43016 #endif
43023 }
43025 int
43027 {
43028 machine_mode mode;
43039 }
43041 /* Print call to TARGET to FILE. */
43043 static void
43045 {
43048 else
43050 }
43052 /* Output assembler code to FILE to increment profiler label # LABELNO
43053 for profiling a function entry. */
43054 void
43056 {
43060 {
43061 #ifndef NO_PROFILE_COUNTERS
43063 #endif
43067 else
43069 }
43071 {
43072 #ifndef NO_PROFILE_COUNTERS
43075 #endif
43077 }
43078 else
43079 {
43080 #ifndef NO_PROFILE_COUNTERS
43083 #endif
43085 }
43088 {
43092 }
43093 }
43095 /* We don't have exact information about the insn sizes, but we may assume
43096 quite safely that we are informed about all 1 byte insns and memory
43097 address sizes. This is enough to eliminate unnecessary padding in
43098 99% of cases. */
43100 static int
43102 {
43108 /* Discard alignments we've emit and jump instructions. */
43113 /* Important case - calls are always 5 bytes.
43114 It is common to have many calls in the row. */
43123 /* For normal instructions we rely on get_attr_length being exact,
43124 with a few exceptions. */
43126 {
43130 {
43140 /* Otherwise trust get_attr_length. */
43142 }
43147 }
43150 else
43152 }
43154 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43156 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43157 window. */
43159 static void
43161 {
43166 /* Look for all minimal intervals of instructions containing 4 jumps.
43167 The intervals are bounded by START and INSN. NBYTES is the total
43168 size of instructions in the interval including INSN and not including
43169 START. When the NBYTES is smaller than 16 bytes, it is possible
43170 that the end of START and INSN ends up in the same 16byte page.
43172 The smallest offset in the page INSN can start is the case where START
43173 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43174 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43176 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43177 have to, control transfer to label(s) can be performed through other
43178 means, and also we estimate minimum length of all asm stmts as 0. */
43180 {
43184 {
43190 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43191 already in the current 16 byte page, because otherwise
43192 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43193 bytes to reach 16 byte boundary. */
43201 {
43203 {
43208 else
43211 }
43212 }
43214 }
43223 njumps++;
43224 else
43228 {
43233 else
43236 }
43243 {
43250 }
43251 }
43252 }
43253 #endif
43255 /* AMD Athlon works faster
43256 when RET is not destination of conditional jump or directly preceded
43257 by other jump instruction. We avoid the penalty by inserting NOP just
43258 before the RET instructions in such cases. */
43259 static void
43261 {
43262 edge e;
43263 edge_iterator ei;
43266 {
43279 {
43280 edge e;
43281 edge_iterator ei;
43286 {
43289 }
43290 }
43292 {
43298 /* Empty functions get branch mispredict even when
43299 the jump destination is not visible to us. */
43302 }
43304 {
43307 }
43308 }
43309 }
43311 /* Count the minimum number of instructions in BB. Return 4 if the
43312 number of instructions >= 4. */
43314 static int
43316 {
43320 /* Count number of instructions in this block. Return 4 if the number
43321 of instructions >= 4. */
43323 {
43324 /* Only happen in exit blocks. */
43332 {
43333 insn_count++;
43336 }
43337 }
43340 }
43343 /* Count the minimum number of instructions in code path in BB.
43344 Return 4 if the number of instructions >= 4. */
43346 static int
43348 {
43349 edge e;
43350 edge_iterator ei;
43353 /* Only bother counting instructions along paths with no
43354 more than 2 basic blocks between entry and exit. Given
43355 that BB has an edge to exit, determine if a predecessor
43356 of BB has an edge from entry. If so, compute the number
43357 of instructions in the predecessor block. If there
43358 happen to be multiple such blocks, compute the minimum. */
43361 {
43362 edge prev_e;
43363 edge_iterator prev_ei;
43366 {
43369 }
43371 {
43373 {
43378 }
43379 }
43380 }
43386 }
43388 /* Pad short function to 4 instructions. */
43390 static void
43392 {
43393 edge e;
43394 edge_iterator ei;
43397 {
43400 {
43403 /* Pad short function. */
43405 {
43408 /* Find epilogue. */
43417 /* Two NOPs count as one instruction. */
43420 }
43421 }
43422 }
43423 }
43425 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43426 the epilogue, the Windows system unwinder will apply epilogue logic and
43427 produce incorrect offsets. This can be avoided by adding a nop between
43428 the last insn that can throw and the first insn of the epilogue. */
43430 static void
43432 {
43433 edge e;
43434 edge_iterator ei;
43437 {
43440 /* Find the beginning of the epilogue. */
43447 /* We only care about preceding insns that can throw. */
43452 /* Do not separate calls from their debug information. */
43458 else
43462 }
43463 }
43465 /* Implement machine specific optimizations. We implement padding of returns
43466 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43467 static void
43469 {
43470 /* We are freeing block_for_insn in the toplev to keep compatibility
43471 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43478 {
43483 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43486 #endif
43487 }
43488 }
43490 /* Return nonzero when QImode register that must be represented via REX prefix
43491 is used. */
43492 bool
43494 {
43502 }
43504 /* Return true when INSN mentions register that must be encoded using REX
43505 prefix. */
43506 bool
43508 {
43511 {
43516 }
43518 }
43520 /* If profitable, negate (without causing overflow) integer constant
43521 of mode MODE at location LOC. Return true in this case. */
43522 bool
43524 {
43525 HOST_WIDE_INT val;
43531 {
43533 /* DImode x86_64 constants must fit in 32 bits. */
43546 }
43548 /* Avoid overflows. */
43554 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43555 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43558 {
43561 }
43564 }
43566 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43567 optabs would emit if we didn't have TFmode patterns. */
43569 void
43571 {
43606 }
43607 \f
43613 /* Get a vector mode of the same size as the original but with elements
43614 twice as wide. This is only guaranteed to apply to integral vectors. */
43618 {
43619 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43624 }
43626 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43627 fill target with val via vec_duplicate. */
43629 static bool
43631 {
43634 rtx dup;
43636 /* First attempt to recognize VAL as-is. */
43640 {
43642 /* If that fails, force VAL into a register. */
43653 }
43655 }
43657 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43658 with all elements equal to VAR. Return true if successful. */
43660 static bool
43663 {
43667 {
43672 /* FALLTHRU */
43692 {
43693 rtx x;
43700 }
43713 {
43717 permute:
43725 /* Extend to SImode using a paradoxical SUBREG. */
43729 /* Insert the SImode value as low element of a V4SImode vector. */
43738 }
43749 widen:
43750 /* Replicate the value once into the next wider mode and recurse. */
43751 {
43753 rtx x;
43770 }
43776 else
43777 {
43786 }
43793 else
43794 {
43803 }
43808 }
43809 }
43811 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43812 whose ONE_VAR element is VAR, and other elements are zero. Return true
43813 if successful. */
43815 static bool
43818 {
43819 machine_mode vsimode;
43820 rtx new_target;
43825 {
43827 /* For SSE4.1, we normally use vector set. But if the second
43828 element is zero and inter-unit moves are OK, we use movq
43829 instead. */
43831 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43853 /* Use ix86_expand_vector_set in 64bit mode only. */
43858 }
43861 {
43866 }
43869 {
43874 /* FALLTHRU */
43889 else
43896 {
43897 /* We need to shuffle the value to the correct position, so
43898 create a new pseudo to store the intermediate result. */
43900 /* With SSE2, we can use the integer shuffle insns. */
43902 {
43904 const1_rtx,
43911 }
43913 /* Otherwise convert the intermediate result to V4SFmode and
43914 use the SSE1 shuffle instructions. */
43916 {
43919 }
43920 else
43924 const1_rtx,
43933 }
43948 widen:
43952 /* Zero extend the variable element to SImode and recurse. */
43965 }
43966 }
43968 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43969 consisting of the values in VALS. It is known that all elements
43970 except ONE_VAR are constants. Return true if successful. */
43972 static bool
43975 {
43977 machine_mode wmode;
43985 {
43990 /* For the two element vectors, it's just as easy to use
43991 the general case. */
43995 /* Use ix86_expand_vector_set in 64bit mode only. */
44017 widen:
44018 /* There's no way to set one QImode entry easily. Combine
44019 the variable value with its adjacent constant value, and
44020 promote to an HImode set. */
44023 {
44028 }
44029 else
44030 {
44033 }
44047 }
44052 }
44054 /* A subroutine of ix86_expand_vector_init_general. Use vector
44055 concatenate to handle the most general case: all values variable,
44056 and none identical. */
44058 static void
44061 {
44064 rtvec v;
44068 {
44071 {
44116 }
44129 {
44144 }
44149 {
44168 }
44173 {
44186 }
44189 half:
44190 /* FIXME: We process inputs backward to help RA. PR 36222. */
44194 {
44199 }
44203 {
44207 {
44211 }
44214 {
44218 }
44221 }
44223 {
44226 {
44230 }
44233 }
44234 else
44240 }
44241 }
44243 /* A subroutine of ix86_expand_vector_init_general. Use vector
44244 interleave to handle the most general case: all values variable,
44245 and none identical. */
44247 static void
44250 {
44259 {
44280 }
44283 {
44284 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44288 /* Insert the SImode value as low element of V4SImode vector. */
44292 op0),
44294 const1_rtx);
44297 /* Cast the V4SImode vector back to a vector in orignal mode. */
44301 /* Load even elements into the second position. */
44305 const1_rtx));
44307 /* Cast vector to FIRST_IMODE vector. */
44310 }
44312 /* Interleave low FIRST_IMODE vectors. */
44314 {
44318 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44321 }
44323 /* Interleave low SECOND_IMODE vectors. */
44325 {
44328 {
44333 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44334 vector. */
44337 }
44340 /* FALLTHRU */
44347 /* Cast the SECOND_IMODE vector back to a vector on original
44348 mode. */
44355 }
44356 }
44358 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44359 all values variable, and none identical. */
44361 static void
44364 {
44371 {
44376 /* FALLTHRU */
44404 half:
44428 quarter:
44457 /* FALLTHRU */
44463 /* Don't use ix86_expand_vector_init_interleave if we can't
44464 move from GPR to SSE register directly. */
44480 }
44482 {
44484 machine_mode inner_mode;
44494 {
44498 {
44504 else
44505 {
44510 }
44511 }
44514 }
44519 {
44525 }
44527 {
44533 }
44534 else
44536 }
44537 }
44539 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44540 instructions unless MMX_OK is true. */
44542 void
44544 {
44551 rtx x;
44554 {
44564 }
44566 /* Constants are best loaded from the constant pool. */
44568 {
44571 }
44573 /* If all values are identical, broadcast the value. */
44579 /* Values where only one field is non-constant are best loaded from
44580 the pool and overwritten via move later. */
44582 {
44586 one_var))
44591 }
44594 }
44596 void
44598 {
44601 machine_mode half_mode;
44603 rtx tmp;
44605 = {
44612 };
44614 = {
44621 };
44625 {
44629 {
44634 else
44638 }
44650 else
44656 {
44659 /* For the two element vectors, we implement a VEC_CONCAT with
44660 the extraction of the other element. */
44667 else
44672 }
44681 {
44687 /* tmp = target = A B C D */
44689 /* target = A A B B */
44691 /* target = X A B B */
44693 /* target = A X C D */
44700 /* tmp = target = A B C D */
44702 /* tmp = X B C D */
44704 /* target = A B X D */
44711 /* tmp = target = A B C D */
44713 /* tmp = X B C D */
44715 /* target = A B X D */
44723 }
44731 /* Element 0 handled by vec_merge below. */
44733 {
44736 }
44739 {
44740 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44741 store into element 0, then shuffle them back. */
44758 }
44759 else
44760 {
44761 /* For SSE1, we have to reuse the V4SF code. */
44765 }
44818 half:
44819 /* Compute offset. */
44825 /* Extract the half. */
44829 /* Put val in tmp at elt. */
44832 /* Put it back. */
44838 {
44845 }
44846 else
44850 {
44857 }
44858 else
44862 {
44869 }
44870 else
44874 {
44881 }
44882 else
44886 {
44893 }
44894 else
44898 {
44905 }
44906 else
44911 }
44914 {
44918 }
44919 else
44920 {
44929 }
44930 }
44932 void
44934 {
44938 rtx tmp;
44941 {
44946 /* FALLTHRU */
44959 {
44979 }
44991 {
44993 {
45013 }
45017 }
45018 else
45019 {
45020 /* For SSE1, we have to reuse the V4SF code. */
45024 }
45040 {
45044 else
45048 }
45053 {
45057 else
45061 }
45066 {
45070 else
45074 }
45079 {
45083 else
45087 }
45092 {
45096 else
45100 }
45105 {
45109 else
45113 }
45118 {
45122 else
45126 }
45131 {
45135 else
45139 }
45146 else
45155 else
45164 else
45173 else
45179 /* ??? Could extract the appropriate HImode element and shift. */
45182 }
45185 {
45189 /* Let the rtl optimizers know about the zero extension performed. */
45191 {
45194 }
45197 }
45198 else
45199 {
45206 }
45207 }
45209 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45210 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45211 The upper bits of DEST are undefined, though they shouldn't cause
45212 exceptions (some bits from src or all zeros are ok). */
45214 static void
45216 {
45219 {
45223 else
45241 else
45248 else
45256 {
45261 const1_rtx);
45262 }
45263 else
45264 {
45268 }
45290 else
45312 }
45316 }
45318 /* Expand a vector reduction. FN is the binary pattern to reduce;
45319 DEST is the destination; IN is the input vector. */
45321 void
45323 {
45328 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45332 {
45335 }
45340 {
45345 else
45349 }
45350 }
45351 \f
45352 /* Target hook for scalar_mode_supported_p. */
45353 static bool
45355 {
45360 else
45362 }
45364 /* Implements target hook vector_mode_supported_p. */
45365 static bool
45367 {
45381 }
45383 /* Implement target hook libgcc_floating_mode_supported_p. */
45384 static bool
45386 {
45388 {
45395 #ifdef IX86_NO_LIBGCC_TFMODE
45397 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45399 #else
45401 #endif
45405 }
45406 }
45408 /* Target hook for c_mode_for_suffix. */
45409 static machine_mode
45411 {
45418 }
45420 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45422 We do this in the new i386 backend to maintain source compatibility
45423 with the old cc0-based compiler. */
45425 static tree
45427 {
45429 clobbers);
45431 clobbers);
45433 }
45435 /* Implements target vector targetm.asm.encode_section_info. */
45437 static void ATTRIBUTE_UNUSED
45439 {
45444 }
45446 /* Worker function for REVERSE_CONDITION. */
45448 enum rtx_code
45450 {
45454 }
45456 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45457 to OPERANDS[0]. */
45461 {
45463 {
45466 {
45470 }
45474 }
45476 {
45480 else
45481 {
45482 /* There is no non-popping store to memory for XFmode.
45483 So if we need one, follow the store with a load. */
45486 else
45488 }
45489 }
45490 else
45492 }
45494 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45495 FP status register is set. */
45497 void
45499 {
45501 rtx temp;
45506 {
45511 }
45512 else
45513 {
45518 }
45522 pc_rtx);
45527 }
45529 /* Output code to perform a log1p XFmode calculation. */
45532 {
45538 rtx test;
45544 XFmode));
45558 }
45560 /* Emit code for round calculation. */
45562 {
45569 rtx insn;
45574 {
45586 }
45589 {
45610 }
45618 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45620 /* scratch = fxam(op1) */
45623 UNSPEC_FXAM)));
45624 /* e1 = fabs(op1) */
45627 /* e2 = e1 + 0.5 */
45632 /* res = floor(e2) */
45634 {
45639 }
45640 else
45644 {
45647 {
45654 UNSPEC_TRUNC_NOOP)));
45655 }
45671 }
45673 /* flags = signbit(a) */
45676 /* if (flags) then res = -res */
45680 pc_rtx);
45691 }
45693 /* Output code to perform a Newton-Rhapson approximation of a single precision
45694 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45697 {
45705 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45709 /* x0 = rcp(b) estimate */
45713 UNSPEC_RCP14)));
45714 else
45717 UNSPEC_RCP)));
45719 /* e0 = x0 * b */
45723 /* e0 = x0 * e0 */
45727 /* e1 = x0 + x0 */
45731 /* x1 = e1 - e0 */
45735 /* res = a * x1 */
45738 }
45740 /* Output code to perform a Newton-Rhapson approximation of a
45741 single precision floating point [reciprocal] square root. */
45745 {
45747 REAL_VALUE_TYPE r;
45764 {
45767 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45770 }
45772 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45773 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45777 /* x0 = rsqrt(a) estimate */
45780 unspec)));
45782 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45784 {
45792 /* Handle masked compare. */
45794 {
45796 /* Imm value 0x4 corresponds to not-equal comparison. */
45799 }
45800 else
45801 {
45807 }
45808 }
45810 /* e0 = x0 * a */
45813 /* e1 = e0 * x0 */
45817 /* e2 = e1 - 3. */
45824 /* e3 = -.5 * x0 */
45827 else
45828 /* e3 = -.5 * e0 */
45831 /* ret = e2 * e3 */
45834 }
45836 #ifdef TARGET_SOLARIS
45837 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45839 static void
45841 tree decl)
45842 {
45843 /* With Binutils 2.15, the "@unwind" marker must be specified on
45844 every occurrence of the ".eh_frame" section, not just the first
45845 one. */
45848 {
45852 }
45854 #ifndef USE_GAS
45856 {
45859 }
45860 #endif
45863 }
45866 /* Return the mangling of TYPE if it is an extended fundamental type. */
45870 {
45878 {
45880 /* __float128 is "g". */
45883 /* "long double" or __float80 is "e". */
45887 }
45888 }
45890 /* For 32-bit code we can save PIC register setup by using
45891 __stack_chk_fail_local hidden function instead of calling
45892 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45893 register, so it is better to call __stack_chk_fail directly. */
45895 static tree ATTRIBUTE_UNUSED
45897 {
45898 return TARGET_64BIT
45901 }
45903 /* Select a format to encode pointers in exception handling data. CODE
45904 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45905 true if the symbol may be affected by dynamic relocations.
45907 ??? All x86 object file formats are capable of representing this.
45908 After all, the relocation needed is the same as for the call insn.
45909 Whether or not a particular assembler allows us to enter such, I
45910 guess we'll have to see. */
45911 int
45913 {
45915 {
45922 }
45927 }
45928 \f
45929 /* Expand copysign from SIGN to the positive value ABS_VALUE
45930 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
45931 the sign-bit. */
45932 static void
45934 {
45938 {
45939 machine_mode vmode;
45945 else
45950 {
45951 /* We need to generate a scalar mode mask in this case. */
45956 }
45957 }
45958 else
45964 }
45966 /* Expand fabs (OP0) and return a new rtx that holds the result. The
45967 mask for masking out the sign-bit is stored in *SMASK, if that is
45968 non-null. */
45969 static rtx
45971 {
45980 else
45984 {
45985 /* We need to generate a scalar mode mask in this case. */
45990 }
45998 }
46000 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46001 swapping the operands if SWAP_OPERANDS is true. The expanded
46002 code is a forward jump to a newly created label in case the
46003 comparison is true. The generated label rtx is returned. */
46007 {
46010 rtx tmp;
46026 }
46028 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46029 using comparison code CODE. Operands are swapped for the comparison if
46030 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46031 static rtx
46034 {
46047 }
46049 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46050 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46051 static rtx
46053 {
46054 REAL_VALUE_TYPE TWO52r;
46055 rtx TWO52;
46062 }
46064 /* Expand SSE sequence for computing lround from OP1 storing
46065 into OP0. */
46066 void
46068 {
46069 /* C code for the stuff we're doing below:
46070 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46071 return (long)tmp;
46072 */
46076 rtx adj;
46078 /* load nextafter (0.5, 0.0) */
46083 /* adj = copysign (0.5, op1) */
46087 /* adj = op1 + adj */
46090 /* op0 = (imode)adj */
46092 }
46094 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46095 into OPERAND0. */
46096 void
46098 {
46099 /* C code for the stuff we're doing below (for do_floor):
46100 xi = (long)op1;
46101 xi -= (double)xi > op1 ? 1 : 0;
46102 return xi;
46103 */
46109 /* reg = (long)op1 */
46113 /* freg = (double)reg */
46117 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46128 }
46130 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46131 result in OPERAND0. */
46132 void
46134 {
46135 /* C code for the stuff we're doing below:
46136 xa = fabs (operand1);
46137 if (!isless (xa, 2**52))
46138 return operand1;
46139 xa = xa + 2**52 - 2**52;
46140 return copysign (xa, operand1);
46141 */
46149 /* xa = abs (operand1) */
46152 /* if (!isless (xa, TWO52)) goto label; */
46165 }
46167 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46168 into OPERAND0. */
46169 void
46171 {
46172 /* C code for the stuff we expand below.
46173 double xa = fabs (x), x2;
46174 if (!isless (xa, TWO52))
46175 return x;
46176 xa = xa + TWO52 - TWO52;
46177 x2 = copysign (xa, x);
46178 Compensate. Floor:
46179 if (x2 > x)
46180 x2 -= 1;
46181 Compensate. Ceil:
46182 if (x2 < x)
46183 x2 -= -1;
46184 return x2;
46185 */
46192 /* Temporary for holding the result, initialized to the input
46193 operand to ease control flow. */
46197 /* xa = abs (operand1) */
46200 /* if (!isless (xa, TWO52)) goto label; */
46203 /* xa = xa + TWO52 - TWO52; */
46207 /* xa = copysign (xa, operand1) */
46210 /* generate 1.0 or -1.0 */
46215 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46219 /* We always need to subtract here to preserve signed zero. */
46228 }
46230 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46231 into OPERAND0. */
46232 void
46234 {
46235 /* C code for the stuff we expand below.
46236 double xa = fabs (x), x2;
46237 if (!isless (xa, TWO52))
46238 return x;
46239 x2 = (double)(long)x;
46240 Compensate. Floor:
46241 if (x2 > x)
46242 x2 -= 1;
46243 Compensate. Ceil:
46244 if (x2 < x)
46245 x2 += 1;
46246 if (HONOR_SIGNED_ZEROS (mode))
46247 return copysign (x2, x);
46248 return x2;
46249 */
46256 /* Temporary for holding the result, initialized to the input
46257 operand to ease control flow. */
46261 /* xa = abs (operand1) */
46264 /* if (!isless (xa, TWO52)) goto label; */
46267 /* xa = (double)(long)x */
46272 /* generate 1.0 */
46275 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46290 }
46292 /* Expand SSE sequence for computing round from OPERAND1 storing
46293 into OPERAND0. Sequence that works without relying on DImode truncation
46294 via cvttsd2siq that is only available on 64bit targets. */
46295 void
46297 {
46298 /* C code for the stuff we expand below.
46299 double xa = fabs (x), xa2, x2;
46300 if (!isless (xa, TWO52))
46301 return x;
46302 Using the absolute value and copying back sign makes
46303 -0.0 -> -0.0 correct.
46304 xa2 = xa + TWO52 - TWO52;
46305 Compensate.
46306 dxa = xa2 - xa;
46307 if (dxa <= -0.5)
46308 xa2 += 1;
46309 else if (dxa > 0.5)
46310 xa2 -= 1;
46311 x2 = copysign (xa2, x);
46312 return x2;
46313 */
46320 /* Temporary for holding the result, initialized to the input
46321 operand to ease control flow. */
46325 /* xa = abs (operand1) */
46328 /* if (!isless (xa, TWO52)) goto label; */
46331 /* xa2 = xa + TWO52 - TWO52; */
46335 /* dxa = xa2 - xa; */
46338 /* generate 0.5, 1.0 and -0.5 */
46344 /* Compensate. */
46346 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46351 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46357 /* res = copysign (xa2, operand1) */
46364 }
46366 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46367 into OPERAND0. */
46368 void
46370 {
46371 /* C code for SSE variant we expand below.
46372 double xa = fabs (x), x2;
46373 if (!isless (xa, TWO52))
46374 return x;
46375 x2 = (double)(long)x;
46376 if (HONOR_SIGNED_ZEROS (mode))
46377 return copysign (x2, x);
46378 return x2;
46379 */
46386 /* Temporary for holding the result, initialized to the input
46387 operand to ease control flow. */
46391 /* xa = abs (operand1) */
46394 /* if (!isless (xa, TWO52)) goto label; */
46397 /* x = (double)(long)x */
46409 }
46411 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46412 into OPERAND0. */
46413 void
46415 {
46420 /* C code for SSE variant we expand below.
46421 double xa = fabs (x), x2;
46422 if (!isless (xa, TWO52))
46423 return x;
46424 xa2 = xa + TWO52 - TWO52;
46425 Compensate:
46426 if (xa2 > xa)
46427 xa2 -= 1.0;
46428 x2 = copysign (xa2, x);
46429 return x2;
46430 */
46434 /* Temporary for holding the result, initialized to the input
46435 operand to ease control flow. */
46439 /* xa = abs (operand1) */
46442 /* if (!isless (xa, TWO52)) goto label; */
46445 /* res = xa + TWO52 - TWO52; */
46450 /* generate 1.0 */
46453 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46461 /* res = copysign (res, operand1) */
46468 }
46470 /* Expand SSE sequence for computing round from OPERAND1 storing
46471 into OPERAND0. */
46472 void
46474 {
46475 /* C code for the stuff we're doing below:
46476 double xa = fabs (x);
46477 if (!isless (xa, TWO52))
46478 return x;
46479 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46480 return copysign (xa, x);
46481 */
46488 /* Temporary for holding the result, initialized to the input
46489 operand to ease control flow. */
46497 /* load nextafter (0.5, 0.0) */
46502 /* xa = xa + 0.5 */
46506 /* xa = (double)(int64_t)xa */
46511 /* res = copysign (xa, operand1) */
46518 }
46520 /* Expand SSE sequence for computing round
46521 from OP1 storing into OP0 using sse4 round insn. */
46522 void
46524 {
46533 {
46544 }
46546 /* round (a) = trunc (a + copysign (0.5, a)) */
46548 /* load nextafter (0.5, 0.0) */
46554 /* e1 = copysign (0.5, op1) */
46558 /* e2 = op1 + e1 */
46561 /* res = trunc (e2) */
46566 }
46567 \f
46569 /* Table of valid machine attributes. */
46571 {
46572 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46573 affects_type_identity } */
46574 /* Stdcall attribute says callee is responsible for popping arguments
46575 if they are not variable. */
46578 /* Fastcall attribute says callee is responsible for popping arguments
46579 if they are not variable. */
46582 /* Thiscall attribute says callee is responsible for popping arguments
46583 if they are not variable. */
46586 /* Cdecl attribute says the callee is a normal C declaration */
46589 /* Regparm attribute specifies how many integer arguments are to be
46590 passed in registers. */
46593 /* Sseregparm attribute says we are using x86_64 calling conventions
46594 for FP arguments. */
46597 /* The transactional memory builtins are implicitly regparm or fastcall
46598 depending on the ABI. Override the generic do-nothing attribute that
46599 these builtins were declared with. */
46602 /* force_align_arg_pointer says this function realigns the stack at entry. */
46605 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46610 #endif
46615 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46616 SUBTARGET_ATTRIBUTE_TABLE,
46617 #endif
46618 /* ms_abi and sysv_abi calling convention function attributes. */
46625 /* End element. */
46627 };
46629 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46630 static int
46633 {
46637 {
46682 }
46683 }
46685 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46686 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46687 insn every time. */
46691 /* Initialize vselect_insn. */
46693 static void
46695 {
46697 rtx x;
46708 }
46710 /* Construct (set target (vec_select op0 (parallel perm))) and
46711 return true if that's a valid instruction in the active ISA. */
46713 static bool
46716 {
46742 }
46744 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46746 static bool
46750 {
46751 machine_mode v2mode;
46752 rtx x;
46767 }
46769 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46770 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46772 static bool
46774 {
46784 ;
46786 ;
46788 ;
46790 ;
46791 else
46794 /* This is a blend, not a permute. Elements must stay in their
46795 respective lanes. */
46797 {
46801 }
46806 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46807 decision should be extracted elsewhere, so that we only try that
46808 sequence once all budget==3 options have been tried. */
46815 {
46845 /* See if bytes move in pairs so we can use pblendw with
46846 an immediate argument, rather than pblendvb with a vector
46847 argument. */
46850 {
46851 use_pblendvb:
46855 finish_pblendvb:
46861 else
46866 }
46871 /* FALLTHRU */
46873 do_subreg:
46880 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46884 /* See if bytes move in quadruplets. If yes, vpblendd
46885 with immediate can be used. */
46890 {
46891 /* See if bytes move the same in both lanes. If yes,
46892 vpblendw with immediate can be used. */
46897 /* Use vpblendw. */
46902 }
46904 /* Use vpblendd. */
46911 /* See if words move in pairs. If yes, vpblendd can be used. */
46916 {
46917 /* See if words move the same in both lanes. If not,
46918 vpblendvb must be used. */
46921 {
46922 /* Use vpblendvb. */
46932 }
46934 /* Use vpblendw. */
46938 }
46940 /* Use vpblendd. */
46947 /* Use vpblendd. */
46955 }
46957 /* This matches five different patterns with the different modes. */
46965 }
46967 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46968 in terms of the variable form of vpermilps.
46970 Note that we will have already failed the immediate input vpermilps,
46971 which requires that the high and low part shuffle be identical; the
46972 variable form doesn't require that. */
46974 static bool
46976 {
46983 /* We can only permute within the 128-bit lane. */
46985 {
46989 }
46995 {
46998 /* Within each 128-bit lane, the elements of op0 are numbered
46999 from 0 and the elements of op1 are numbered from 4. */
47006 }
47013 }
47015 /* Return true if permutation D can be performed as VMODE permutation
47016 instead. */
47018 static bool
47020 {
47035 else
47041 }
47043 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47044 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47046 static bool
47048 {
47057 {
47059 {
47062 {
47066 /* Use vperm2i128 insn. The pattern uses
47067 V4DImode instead of V2TImode. */
47080 }
47082 }
47083 }
47084 else
47085 {
47087 {
47090 }
47092 {
47096 /* V4DImode should be already handled through
47097 expand_vselect by vpermq instruction. */
47104 {
47105 /* First see if vpermq can be used for
47106 V8SImode/V16HImode/V32QImode. */
47108 {
47116 {
47120 }
47122 }
47124 /* Next see if vpermd can be used. */
47127 }
47128 /* Or if vpermps can be used. */
47133 {
47134 /* vpshufb only works intra lanes, it is not
47135 possible to shuffle bytes in between the lanes. */
47139 }
47140 }
47142 {
47146 /* If vpermq didn't work, vpshufb won't work either. */
47154 {
47155 /* First see if vpermq can be used for
47156 V16SImode/V32HImode/V64QImode. */
47158 {
47166 {
47170 }
47172 }
47174 /* Next see if vpermd can be used. */
47177 }
47178 /* Or if vpermps can be used. */
47182 {
47183 /* vpshufb only works intra lanes, it is not
47184 possible to shuffle bytes in between the lanes. */
47188 }
47189 }
47190 else
47192 }
47203 else
47204 {
47212 else
47216 {
47220 }
47221 }
47232 {
47247 else
47249 }
47250 else
47251 {
47254 }
47259 }
47261 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47262 in a single instruction. */
47264 static bool
47266 {
47270 /* Check plain VEC_SELECT first, because AVX has instructions that could
47271 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47272 input where SEL+CONCAT may not. */
47274 {
47280 {
47286 }
47289 {
47293 }
47295 {
47296 /* Use vpbroadcast{b,w,d}. */
47299 {
47342 /* For other modes prefer other shuffles this function creates. */
47344 }
47346 {
47350 }
47351 }
47356 /* There are plenty of patterns in sse.md that are written for
47357 SEL+CONCAT and are not replicated for a single op. Perhaps
47358 that should be changed, to avoid the nastiness here. */
47360 /* Recognize interleave style patterns, which means incrementing
47361 every other permutation operand. */
47363 {
47366 }
47371 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47373 {
47375 {
47380 }
47385 }
47386 }
47388 /* Finally, try the fully general two operand permute. */
47393 /* Recognize interleave style patterns with reversed operands. */
47395 {
47397 {
47401 else
47404 }
47409 }
47411 /* Try the SSE4.1 blend variable merge instructions. */
47415 /* Try one of the AVX vpermil variable permutations. */
47419 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47420 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47424 /* Try the AVX2 vpalignr instruction. */
47428 /* Try the AVX512F vpermi2 instructions. */
47433 }
47435 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47436 in terms of a pair of pshuflw + pshufhw instructions. */
47438 static bool
47440 {
47448 /* The two permutations only operate in 64-bit lanes. */
47459 /* Emit the pshuflw. */
47466 /* Emit the pshufhw. */
47474 }
47476 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47477 the permutation using the SSSE3 palignr instruction. This succeeds
47478 when all of the elements in PERM fit within one vector and we merely
47479 need to shift them down so that a single vector permutation has a
47480 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47481 the vpalignr instruction itself can perform the requested permutation. */
47483 static bool
47485 {
47492 /* Even with AVX, palignr only operates on 128-bit vectors,
47493 in AVX2 palignr operates on both 128-bit lanes. */
47503 {
47507 {
47510 }
47519 }
47522 {
47531 }
47533 /* Given that we have SSSE3, we know we'll be able to implement the
47534 single operand permutation after the palignr with pshufb for
47535 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47536 first. */
47542 {
47547 }
47551 {
47557 else
47562 }
47568 /* For AVX2, test whether we can permute the result in one instruction. */
47570 {
47575 }
47579 {
47583 }
47584 else
47585 {
47590 shift));
47591 }
47595 /* Test for the degenerate case where the alignment by itself
47596 produces the desired permutation. */
47598 {
47601 }
47607 }
47609 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47610 the permutation using the SSE4_1 pblendv instruction. Potentially
47611 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47613 static bool
47615 {
47621 /* Use the same checks as in expand_vec_perm_blend. */
47625 ;
47627 ;
47629 ;
47630 else
47633 /* Figure out where permutation elements stay not in their
47634 respective lanes. */
47636 {
47640 }
47641 /* We can pblend the part where elements stay not in their
47642 respective lanes only when these elements are all in one
47643 half of a permutation.
47644 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47645 lanes, but both 8 and 9 >= 8
47646 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47647 respective lanes and 8 >= 8, but 2 not. */
47653 /* First we apply one operand permutation to the part where
47654 elements stay not in their respective lanes. */
47658 else
47670 else
47675 /* Next we put permuted elements into their positions. */
47679 else
47689 }
47693 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47694 a two vector permutation into a single vector permutation by using
47695 an interleave operation to merge the vectors. */
47697 static bool
47699 {
47708 {
47711 }
47713 {
47716 /* For 32-byte modes allow even d->one_operand_p.
47717 The lack of cross-lane shuffling in some instructions
47718 might prevent a single insn shuffle. */
47721 /* If expand_vec_perm_interleave3 can expand this into
47722 a 3 insn sequence, give up and let it be expanded as
47723 3 insn sequence. While that is one insn longer,
47724 it doesn't need a memory operand and in the common
47725 case that both interleave low and high permutations
47726 with the same operands are adjacent needs 4 insns
47727 for both after CSE. */
47730 }
47731 else
47734 /* Examine from whence the elements come. */
47743 {
47746 /* Split the two input vectors into 4 halves. */
47752 /* If the elements from the low halves use interleave low, and similarly
47753 for interleave high. If the elements are from mis-matched halves, we
47754 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47756 {
47757 /* punpckl* */
47759 {
47764 }
47767 }
47769 {
47770 /* punpckh* */
47772 {
47777 }
47780 }
47782 {
47783 /* shufps */
47785 {
47790 }
47792 {
47793 /* shufpd */
47798 }
47799 }
47801 {
47802 /* shufps */
47804 {
47809 }
47811 {
47812 /* shufpd */
47817 }
47818 }
47819 else
47821 }
47822 else
47823 {
47828 /* Split the two input vectors into 8 quarters. */
47834 {
47837 }
47840 {
47844 }
47846 {
47849 }
47852 {
47854 {
47855 /* Attempt to increase the likelihood that dfinal
47856 shuffle will be intra-lane. */
47860 }
47862 /* vperm2f128 or vperm2i128. */
47864 {
47869 }
47874 {
47878 {
47881 }
47882 }
47883 }
47888 {
47889 /* vpunpckl* */
47891 {
47900 }
47901 }
47904 {
47905 /* vpunpckh* */
47907 {
47916 }
47917 }
47918 else
47920 }
47922 /* Use the remapping array set up above to move the elements from their
47923 swizzled locations into their final destinations. */
47926 {
47929 /* If same_halves is true, both halves of the remapped vector are the
47930 same. Avoid cross-lane accesses if possible. */
47932 {
47935 }
47936 else
47938 }
47940 {
47943 }
47947 /* Test if the final remap can be done with a single insn. For V4SFmode or
47948 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
47961 {
47964 }
47971 }
47973 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47974 a single vector cross-lane permutation into vpermq followed
47975 by any of the single insn permutations. */
47977 static bool
47979 {
47993 {
47996 }
47999 {
48004 }
48017 {
48024 }
48031 {
48036 ;
48039 else
48041 }
48050 }
48052 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48053 a vector permutation using two instructions, vperm2f128 resp.
48054 vperm2i128 followed by any single in-lane permutation. */
48056 static bool
48058 {
48072 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48073 immediate. For perm < 16 the second permutation uses
48074 d->op0 as first operand, for perm >= 16 it uses d->op1
48075 as first operand. The second operand is the result of
48076 vperm2[fi]128. */
48078 {
48079 /* Ignore permutations which do not move anything cross-lane. */
48081 {
48082 /* The second shuffle for e.g. V4DFmode has
48083 0123 and ABCD operands.
48084 Ignore AB23, as 23 is already in the second lane
48085 of the first operand. */
48087 /* And 01CD, as 01 is in the first lane of the first
48088 operand. */
48090 /* And 4567, as then the vperm2[fi]128 doesn't change
48091 anything on the original 4567 second operand. */
48093 }
48094 else
48095 {
48096 /* The second shuffle for e.g. V4DFmode has
48097 4567 and ABCD operands.
48098 Ignore AB67, as 67 is already in the second lane
48099 of the first operand. */
48101 /* And 45CD, as 45 is in the first lane of the first
48102 operand. */
48104 /* And 0123, as then the vperm2[fi]128 doesn't change
48105 anything on the original 0123 first operand. */
48107 }
48110 {
48116 else
48118 }
48121 {
48125 }
48126 else
48130 {
48134 /* Found a usable second shuffle. dfirst will be
48135 vperm2f128 on d->op0 and d->op1. */
48147 /* And dsecond is some single insn shuffle, taking
48148 d->op0 and result of vperm2f128 (if perm < 16) or
48149 d->op1 and result of vperm2f128 (otherwise). */
48158 }
48160 /* For one operand, the only useful vperm2f128 permutation is 0x01
48161 aka lanes swap. */
48164 }
48167 }
48169 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48170 a two vector permutation using 2 intra-lane interleave insns
48171 and cross-lane shuffle for 32-byte vectors. */
48173 static bool
48175 {
48182 ;
48184 ;
48185 else
48200 {
48204 else
48210 else
48216 else
48222 else
48228 else
48234 else
48239 }
48243 }
48245 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48246 a single vector permutation using a single intra-lane vector
48247 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48248 the non-swapped and swapped vectors together. */
48250 static bool
48252 {
48260 || TARGET_AVX2
48269 {
48276 }
48311 }
48313 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48314 permutation using two vperm2f128, followed by a vshufpd insn blending
48315 the two vectors together. */
48317 static bool
48319 {
48362 }
48364 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48365 permutation with two pshufb insns and an ior. We should have already
48366 failed all two instruction sequences. */
48368 static bool
48370 {
48384 /* Generate two permutation masks. If the required element is within
48385 the given vector it is shuffled into the proper lane. If the required
48386 element is in the other vector, force a zero into the lane by setting
48387 bit 7 in the permutation mask. */
48390 {
48397 {
48400 }
48401 }
48425 }
48427 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48428 with two vpshufb insns, vpermq and vpor. We should have already failed
48429 all two or three instruction sequences. */
48431 static bool
48433 {
48448 /* Generate two permutation masks. If the required element is within
48449 the same lane, it is shuffled in. If the required element from the
48450 other lane, force a zero by setting bit 7 in the permutation mask.
48451 In the other mask the mask has non-negative elements if element
48452 is requested from the other lane, but also moved to the other lane,
48453 so that the result of vpshufb can have the two V2TImode halves
48454 swapped. */
48457 {
48462 {
48465 }
48466 }
48475 /* Swap the 128-byte lanes of h into hp. */
48479 const1_rtx));
48496 }
48498 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48499 and extract-odd permutations of two V32QImode and V16QImode operand
48500 with two vpshufb insns, vpor and vpermq. We should have already
48501 failed all two or three instruction sequences. */
48503 static bool
48505 {
48524 /* Generate two permutation masks. In the first permutation mask
48525 the first quarter will contain indexes for the first half
48526 of the op0, the second quarter will contain bit 7 set, third quarter
48527 will contain indexes for the second half of the op0 and the
48528 last quarter bit 7 set. In the second permutation mask
48529 the first quarter will contain bit 7 set, the second quarter
48530 indexes for the first half of the op1, the third quarter bit 7 set
48531 and last quarter indexes for the second half of the op1.
48532 I.e. the first mask e.g. for V32QImode extract even will be:
48533 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48534 (all values masked with 0xf except for -128) and second mask
48535 for extract even will be
48536 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48539 {
48545 {
48548 }
48549 }
48568 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48576 }
48578 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48579 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48580 with two "and" and "pack" or two "shift" and "pack" insns. We should
48581 have already failed all two instruction sequences. */
48583 static bool
48585 {
48589 machine_mode half_mode;
48598 {
48600 /* Required for "pack". */
48611 /* No check as all instructions are SSE2. */
48642 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48643 general shuffles. */
48645 }
48647 /* Check that permutation is even or odd. */
48662 {
48669 }
48670 else
48671 {
48678 }
48679 /* In AVX2 for 256 bit case we need to permute pack result. */
48681 {
48687 const0_rtx,
48688 const2_rtx,
48689 const1_rtx,
48692 }
48693 else
48697 }
48699 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48700 and extract-odd permutations. */
48702 static bool
48704 {
48708 {
48715 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48719 /* Now an unpck[lh]pd will produce the result required. */
48722 else
48728 {
48737 /* Shuffle within the 128-bit lanes to produce:
48738 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48742 /* Shuffle the lanes around to produce:
48743 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48747 /* Shuffle within the 128-bit lanes to produce:
48748 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48751 /* Shuffle within the 128-bit lanes to produce:
48752 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48755 /* Shuffle the lanes around to produce:
48756 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48759 }
48766 /* These are always directly implementable by expand_vec_perm_1. */
48774 else
48775 {
48778 /* We need 2*log2(N)-1 operations to achieve odd/even
48779 with interleave. */
48788 else
48791 }
48803 {
48808 else
48813 {
48818 }
48820 }
48828 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48832 /* Now an vpunpck[lh]qdq will produce the result required. */
48835 else
48842 {
48847 else
48852 {
48857 }
48859 }
48870 /* Shuffle the lanes around into
48871 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48879 /* Swap the 2nd and 3rd position in each lane into
48880 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48886 /* Now an vpunpck[lh]qdq will produce
48887 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48891 else
48900 }
48903 }
48905 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48906 extract-even and extract-odd permutations. */
48908 static bool
48910 {
48922 }
48924 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
48925 permutations. We assume that expand_vec_perm_1 has already failed. */
48927 static bool
48929 {
48937 {
48940 /* These are special-cased in sse.md so that we can optionally
48941 use the vbroadcast instruction. They expand to two insns
48942 if the input happens to be in a register. */
48949 /* These are always implementable using standard shuffle patterns. */
48954 /* These can be implemented via interleave. We save one insn by
48955 stopping once we have promoted to V4SImode and then use pshufd. */
48958 do
48959 {
48960 rtx dest;
48966 {
48970 }
48977 }
48993 /* For AVX2 broadcasts of the first element vpbroadcast* or
48994 vpermq should be used by expand_vec_perm_1. */
49000 }
49001 }
49003 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49004 broadcast permutations. */
49006 static bool
49008 {
49020 }
49022 /* Implement arbitrary permutations of two V64QImode operands
49023 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49024 static bool
49026 {
49036 machine_mode vmode;
49042 {
49049 }
49051 /* Prepare permutations such that the first one takes care of
49052 putting the even bytes into the right positions or one higher
49053 positions (ds[0]) and the second one takes care of
49054 putting the odd bytes into the right positions or one below
49055 (ds[1]). */
49058 {
49061 {
49064 }
49065 else
49066 {
49069 }
49070 }
49092 }
49094 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49095 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49096 all the shorter instruction sequences. */
49098 static bool
49100 {
49116 /* Generate 4 permutation masks. If the required element is within
49117 the same lane, it is shuffled in. If the required element from the
49118 other lane, force a zero by setting bit 7 in the permutation mask.
49119 In the other mask the mask has non-negative elements if element
49120 is requested from the other lane, but also moved to the other lane,
49121 so that the result of vpshufb can have the two V2TImode halves
49122 swapped. */
49125 {
49130 }
49136 {
49144 }
49147 {
49149 {
49152 }
49159 }
49161 /* Swap the 128-byte lanes of h[X]. */
49163 {
49169 const1_rtx));
49171 }
49174 {
49176 {
49179 }
49185 }
49188 {
49190 {
49194 }
49197 }
49207 }
49209 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49210 With all of the interface bits taken care of, perform the expansion
49211 in D and return true on success. */
49213 static bool
49215 {
49216 /* Try a single instruction expansion. */
49220 /* Try sequences of two instructions. */
49243 /* Try sequences of three instructions. */
49260 /* Try sequences of four instructions. */
49271 /* ??? Look for narrow permutations whose element orderings would
49272 allow the promotion to a wider mode. */
49274 /* ??? Look for sequences of interleave or a wider permute that place
49275 the data into the correct lanes for a half-vector shuffle like
49276 pshuf[lh]w or vpermilps. */
49278 /* ??? Look for sequences of interleave that produce the desired results.
49279 The combinatorics of punpck[lh] get pretty ugly... */
49284 /* Even longer sequences. */
49289 }
49291 /* If a permutation only uses one operand, make it clear. Returns true
49292 if the permutation references both operands. */
49294 static bool
49296 {
49304 {
49310 {
49313 }
49314 /* The elements of PERM do not suggest that only the first operand
49315 is used, but both operands are identical. Allow easier matching
49316 of the permutation by folding the permutation into the single
49317 input vector. */
49318 /* FALLTHRU */
49329 }
49332 }
49334 bool
49336 {
49341 rtx sel;
49358 {
49363 }
49370 /* If the selector says both arguments are needed, but the operands are the
49371 same, the above tried to expand with one_operand_p and flattened selector.
49372 If that didn't work, retry without one_operand_p; we succeeded with that
49373 during testing. */
49375 {
49379 }
49382 }
49384 /* Implement targetm.vectorize.vec_perm_const_ok. */
49386 static bool
49389 {
49398 /* Given sufficient ISA support we can just return true here
49399 for selected vector modes. */
49401 {
49407 /* All implementable with a single vpermi2 insn. */
49412 /* All implementable with a single vpermi2 insn. */
49417 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49425 /* All implementable with a single vpermi2 insn. */
49430 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49435 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49442 /* All implementable with a single vpperm insn. */
49445 /* All implementable with 2 pshufb + 1 ior. */
49451 /* All implementable with shufpd or unpck[lh]pd. */
49455 }
49457 /* Extract the values from the vector CST into the permutation
49458 array in D. */
49461 {
49465 }
49467 /* For all elements from second vector, fold the elements to first. */
49472 /* Check whether the mask can be applied to the vector type. */
49475 /* Implementable with shufps or pshufd. */
49479 /* Otherwise we have to go through the motions and see if we can
49480 figure out how to generate the requested permutation. */
49491 }
49493 void
49495 {
49510 /* We'll either be able to implement the permutation directly... */
49514 /* ... or we use the special-case patterns. */
49516 }
49518 static void
49520 {
49535 {
49538 }
49540 /* Note that for AVX this isn't one instruction. */
49543 }
49546 /* Expand a vector operation CODE for a V*QImode in terms of the
49547 same operation on V*HImode. */
49549 void
49551 {
49553 machine_mode himode;
49563 {
49581 }
49585 {
49587 /* Unpack data such that we've got a source byte in each low byte of
49588 each word. We don't care what goes into the high byte of each word.
49589 Rather than trying to get zero in there, most convenient is to let
49590 it be a copy of the low byte. */
49595 /* FALLTHRU */
49607 /* FALLTHRU */
49617 }
49619 /* Perform the operation. */
49626 /* Merge the data back into the right place. */
49636 {
49637 /* For SSE2, we used an full interleave, so the desired
49638 results are in the even elements. */
49641 }
49642 else
49643 {
49644 /* For AVX, the interleave used above was not cross-lane. So the
49645 extraction is evens but with the second and third quarter swapped.
49646 Happily, that is even one insn shorter than even extraction. */
49649 }
49656 }
49658 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49659 if op is CONST_VECTOR with all odd elements equal to their
49660 preceding element. */
49662 static bool
49664 {
49674 }
49676 void
49679 {
49682 rtx x;
49690 /* We only play even/odd games with vectors of SImode. */
49693 /* If we're looking for the odd results, shift those members down to
49694 the even slots. For some cpus this is faster than a PSHUFD. */
49696 {
49697 /* For XOP use vpmacsdqh, but only for smult, as it is only
49698 signed. */
49700 {
49704 }
49715 }
49718 {
49721 else
49723 }
49725 {
49728 else
49730 }
49735 else
49736 {
49739 /* The easiest way to implement this without PMULDQ is to go through
49740 the motions as if we are performing a full 64-bit multiply. With
49741 the exception that we need to do less shuffling of the elements. */
49743 /* Compute the sign-extension, aka highparts, of the two operands. */
49749 /* Multiply LO(A) * HI(B), and vice-versa. */
49755 /* Multiply LO(A) * LO(B). */
49759 /* Combine and shift the highparts into place. */
49764 /* Combine high and low parts. */
49767 }
49769 }
49771 void
49774 {
49780 {
49785 {
49786 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49787 shuffle the elements once so that all elements are in the right
49788 place for immediate use: { A C B D }. */
49793 }
49794 else
49795 {
49796 /* Put the elements into place for the multiply. */
49800 }
49805 /* Shuffle the elements between the lanes. After this we
49806 have { A B E F | C D G H } for each operand. */
49816 /* Shuffle the elements within the lanes. After this we
49817 have { A A B B | C C D D } or { E E F F | G G H H }. */
49858 }
49859 }
49861 void
49863 {
49873 /* Move the results in element 2 down to element 1; we don't care
49874 what goes in elements 2 and 3. Then we can merge the parts
49875 back together with an interleave.
49877 Note that two other sequences were tried:
49878 (1) Use interleaves at the start instead of psrldq, which allows
49879 us to use a single shufps to merge things back at the end.
49880 (2) Use shufps here to combine the two vectors, then pshufd to
49881 put the elements in the correct order.
49882 In both cases the cost of the reformatting stall was too high
49883 and the overall sequence slower. */
49894 }
49896 void
49898 {
49909 {
49910 /* op1: A,B,C,D, op2: E,F,G,H */
49919 /* t1: B,A,D,C */
49926 /* t2: (B*E),(A*F),(D*G),(C*H) */
49929 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
49932 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
49935 /* Multiply lower parts and add all */
49942 }
49943 else
49944 {
49945 machine_mode nmode;
49949 {
49952 }
49954 {
49957 }
49959 {
49962 }
49963 else
49967 /* Multiply low parts. */
49971 /* Shift input vectors right 32 bits so we can multiply high parts. */
49976 /* Multiply high parts by low parts. */
49982 /* Combine and shift the highparts back. */
49986 /* Combine high and low parts. */
49988 }
49992 }
49994 /* Return 1 if control tansfer instruction INSN
49995 should be encoded with bnd prefix.
49996 If insn is NULL then return 1 when control
49997 transfer instructions should be prefixed with
49998 bnd by default for current function. */
50000 bool
50002 {
50003 /* For call insns check special flag. */
50005 {
50009 }
50011 /* All other insns are prefixed only if function is instrumented. */
50013 }
50015 /* Calculate integer abs() using only SSE2 instructions. */
50017 void
50019 {
50024 {
50025 /* For 32-bit signed integer X, the best way to calculate the absolute
50026 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50038 /* For 16-bit signed integer X, the best way to calculate the absolute
50039 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50047 /* For 8-bit signed integer X, the best way to calculate the absolute
50048 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50049 as SSE2 provides the PMINUB insn. */
50059 }
50063 }
50065 /* Expand an insert into a vector register through pinsr insn.
50066 Return true if successful. */
50068 bool
50070 {
50078 {
50081 }
50087 {
50092 {
50099 {
50131 }
50145 }
50149 }
50150 }
50151 \f
50152 /* This function returns the calling abi specific va_list type node.
50153 It returns the FNDECL specific va_list type. */
50155 static tree
50157 {
50164 else
50166 }
50168 /* Returns the canonical va_list type specified by TYPE. If there
50169 is no valid TYPE provided, it return NULL_TREE. */
50171 static tree
50173 {
50176 /* Resolve references and pointers to va_list type. */
50185 {
50190 {
50191 /* If va_list is an array type, the argument may have decayed
50192 to a pointer type, e.g. by being passed to another function.
50193 In that case, unwrap both types so that we can compare the
50194 underlying records. */
50197 {
50200 }
50201 }
50208 {
50209 /* If va_list is an array type, the argument may have decayed
50210 to a pointer type, e.g. by being passed to another function.
50211 In that case, unwrap both types so that we can compare the
50212 underlying records. */
50215 {
50218 }
50219 }
50226 {
50227 /* If va_list is an array type, the argument may have decayed
50228 to a pointer type, e.g. by being passed to another function.
50229 In that case, unwrap both types so that we can compare the
50230 underlying records. */
50233 {
50236 }
50237 }
50241 }
50243 }
50245 /* Iterate through the target-specific builtin types for va_list.
50246 IDX denotes the iterator, *PTREE is set to the result type of
50247 the va_list builtin, and *PNAME to its internal type.
50248 Returns zero if there is no element for this index, otherwise
50249 IDX should be increased upon the next call.
50250 Note, do not iterate a base builtin's name like __builtin_va_list.
50251 Used from c_common_nodes_and_builtins. */
50253 static int
50255 {
50257 {
50259 {
50272 }
50273 }
50276 }
50278 #undef TARGET_SCHED_DISPATCH
50279 #define TARGET_SCHED_DISPATCH has_dispatch
50280 #undef TARGET_SCHED_DISPATCH_DO
50281 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50282 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50283 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50284 #undef TARGET_SCHED_REORDER
50285 #define TARGET_SCHED_REORDER ix86_sched_reorder
50286 #undef TARGET_SCHED_ADJUST_PRIORITY
50287 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50288 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50289 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50290 ix86_dependencies_evaluation_hook
50292 /* The size of the dispatch window is the total number of bytes of
50293 object code allowed in a window. */
50294 #define DISPATCH_WINDOW_SIZE 16
50296 /* Number of dispatch windows considered for scheduling. */
50297 #define MAX_DISPATCH_WINDOWS 3
50299 /* Maximum number of instructions in a window. */
50300 #define MAX_INSN 4
50302 /* Maximum number of immediate operands in a window. */
50303 #define MAX_IMM 4
50305 /* Maximum number of immediate bits allowed in a window. */
50306 #define MAX_IMM_SIZE 128
50308 /* Maximum number of 32 bit immediates allowed in a window. */
50309 #define MAX_IMM_32 4
50311 /* Maximum number of 64 bit immediates allowed in a window. */
50312 #define MAX_IMM_64 2
50314 /* Maximum total of loads or prefetches allowed in a window. */
50315 #define MAX_LOAD 2
50317 /* Maximum total of stores allowed in a window. */
50318 #define MAX_STORE 1
50320 #undef BIG
50321 #define BIG 100
50324 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50327 disp_load,
50328 disp_store,
50329 disp_load_store,
50330 disp_prefetch,
50331 disp_imm,
50332 disp_imm_32,
50333 disp_imm_64,
50334 disp_branch,
50335 disp_cmp,
50336 disp_jcc,
50337 disp_last
50338 };
50340 /* Number of allowable groups in a dispatch window. It is an array
50341 indexed by dispatch_group enum. 100 is used as a big number,
50342 because the number of these kind of operations does not have any
50343 effect in dispatch window, but we need them for other reasons in
50344 the table. */
50347 };
50353 };
50355 /* Instruction path. */
50361 last_path
50362 };
50364 /* sched_insn_info defines a window to the instructions scheduled in
50365 the basic block. It contains a pointer to the insn_info table and
50366 the instruction scheduled.
50368 Windows are allocated for each basic block and are linked
50369 together. */
50371 rtx insn;
50378 /* Linked list of dispatch windows. This is a two way list of
50379 dispatch windows of a basic block. It contains information about
50380 the number of uops in the window and the total number of
50381 instructions and of bytes in the object code for this dispatch
50382 window. */
50400 /* Immediate valuse used in an insn. */
50402 {
50411 /* Get dispatch group of insn. */
50413 static enum dispatch_group
50415 {
50431 }
50433 /* Return true if insn is a compare instruction. */
50435 static bool
50437 {
50445 }
50447 /* Return true if a dispatch violation encountered. */
50449 static bool
50451 {
50455 }
50457 /* Return true if insn is a branch instruction. */
50459 static bool
50461 {
50463 }
50465 /* Return true if insn is a prefetch instruction. */
50467 static bool
50469 {
50471 }
50473 /* This function initializes a dispatch window and the list container holding a
50474 pointer to the window. */
50476 static void
50478 {
50484 else
50502 {
50508 }
50510 }
50512 /* This function allocates and initializes a dispatch window and the
50513 list container holding a pointer to the window. */
50517 {
50522 }
50524 /* This routine initializes the dispatch scheduling information. It
50525 initiates building dispatch scheduler tables and constructs the
50526 first dispatch window. */
50528 static void
50530 {
50531 /* Allocate a dispatch list and a window. */
50536 }
50538 /* This function returns true if a branch is detected. End of a basic block
50539 does not have to be a branch, but here we assume only branches end a
50540 window. */
50542 static bool
50544 {
50546 }
50548 /* This function is called when the end of a window processing is reached. */
50550 static void
50552 {
50555 {
50560 }
50562 }
50564 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50565 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50566 for 48 bytes of instructions. Note that these windows are not dispatch
50567 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50571 {
50573 {
50578 }
50584 }
50586 /* Compute number of immediate operands of an instruction. */
50588 static void
50590 {
50597 {
50604 else
50616 {
50619 }
50624 }
50625 }
50627 /* Return total size of immediate operands of an instruction along with number
50628 of corresponding immediate-operands. It initializes its parameters to zero
50629 befor calling FIND_CONSTANT.
50630 INSN is the input instruction. IMM is the total of immediates.
50631 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50632 bit immediates. */
50634 static int
50636 {
50644 }
50646 /* This function indicates if an operand of an instruction is an
50647 immediate. */
50649 static bool
50651 {
50660 }
50662 /* Return single or double path for instructions. */
50664 static enum insn_path
50666 {
50676 }
50678 /* Return insn dispatch group. */
50680 static enum dispatch_group
50682 {
50700 }
50702 /* Count number of GROUP restricted instructions in a dispatch
50703 window WINDOW_LIST. */
50705 static int
50707 {
50718 {
50737 }
50750 }
50752 /* This function returns true if insn satisfies dispatch rules on the
50753 last window scheduled. */
50755 static bool
50757 {
50765 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50766 instructions should be given the lowest priority in the
50767 scheduling process in Haifa scheduler to make sure they will be
50768 scheduled in the same dispatch window as the reference to them. */
50772 /* Check nonrestricted. */
50776 /* Get last dispatch window. */
50781 {
50786 /* Window 1 is full. Go for next window. */
50788 }
50795 /* See if it fits in the first window. */
50797 {
50798 /* The first widow should have only single and double path
50799 uops. */
50805 }
50807 }
50809 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50810 dispatch window WINDOW_LIST. */
50812 static void
50814 {
50832 /* Initialize window with new instruction. */
50853 {
50856 }
50857 }
50859 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50860 If the total bytes of instructions or the number of instructions in
50861 the window exceed allowable, it allocates a new window. */
50863 static void
50865 {
50888 /* Get the last dispatch window. */
50896 else
50899 /* If current window is full, get a new window.
50900 Window number zero is full, if MAX_INSN uops are scheduled in it.
50901 Window number one is full, if window zero's bytes plus window
50902 one's bytes is 32, or if the bytes of the new instruction added
50903 to the total makes it greater than 48, or it has already MAX_INSN
50904 instructions in it. */
50913 {
50916 }
50919 {
50923 {
50926 }
50927 }
50929 {
50934 {
50937 }
50940 }
50941 else
50945 {
50946 /* End of basic block is reached do end-basic-block process. */
50949 }
50950 }
50952 /* Print the dispatch window, WINDOW_NUM, to FILE. */
50954 DEBUG_FUNCTION static void
50956 {
50962 else
50976 {
50979 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
50985 }
50986 }
50988 /* Print to stdout a dispatch window. */
50990 DEBUG_FUNCTION void
50992 {
50994 }
50996 /* Print INSN dispatch information to FILE. */
50998 DEBUG_FUNCTION static void
51000 {
51023 }
51025 /* Print to STDERR the status of the ready list with respect to
51026 dispatch windows. */
51028 DEBUG_FUNCTION void
51030 {
51038 }
51040 /* This routine is the driver of the dispatch scheduler. */
51042 static void
51044 {
51049 }
51051 /* Return TRUE if Dispatch Scheduling is supported. */
51053 static bool
51055 {
51059 {
51075 }
51078 }
51080 /* Implementation of reassociation_width target hook used by
51081 reassoc phase to identify parallelism level in reassociated
51082 tree. Statements tree_code is passed in OPC. Arguments type
51083 is passed in MODE.
51085 Currently parallel reassociation is enabled for Atom
51086 processors only and we set reassociation width to be 2
51087 because Atom may issue up to 2 instructions per cycle.
51089 Return value should be fixed if parallel reassociation is
51090 enabled for other processors. */
51092 static int
51094 {
51095 /* Vector part. */
51097 {
51100 else
51102 }
51104 /* Scalar part. */
51109 else
51111 }
51113 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51114 place emms and femms instructions. */
51116 static machine_mode
51118 {
51123 {
51142 else
51154 /* FALLTHRU */
51158 }
51159 }
51161 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51162 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51163 256bit and 128bit vectors. */
51165 static unsigned int
51167 {
51170 }
51172 \f
51174 /* Return class of registers which could be used for pseudo of MODE
51175 and of class RCLASS for spilling instead of memory. Return NO_REGS
51176 if it is not possible or non-profitable. */
51177 static reg_class_t
51179 {
51185 }
51187 /* Implement targetm.vectorize.init_cost. */
51191 {
51195 }
51197 /* Implement targetm.vectorize.add_stmt_cost. */
51199 static unsigned
51203 {
51210 /* Statements in an inner loop relative to the loop being
51211 vectorized are weighted more heavily. The value here is
51212 arbitrary and could potentially be improved with analysis. */
51218 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51219 for Silvermont as it has out of order integer pipeline and can execute
51220 2 scalar instruction per tick, but has in order SIMD pipeline. */
51223 {
51227 }
51232 }
51234 /* Implement targetm.vectorize.finish_cost. */
51236 static void
51239 {
51244 }
51246 /* Implement targetm.vectorize.destroy_cost_data. */
51248 static void
51250 {
51252 }
51254 /* Validate target specific memory model bits in VAL. */
51256 static unsigned HOST_WIDE_INT
51258 {
51265 {
51269 }
51272 {
51276 }
51278 {
51282 }
51284 }
51286 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51287 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51288 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51289 or number of vecsize_mangle variants that should be emitted. */
51291 static int
51295 {
51302 {
51306 }
51311 {
51318 /* case SCmode: */
51319 /* case DCmode: */
51325 }
51327 tree t;
51331 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51333 {
51340 /* case SCmode: */
51341 /* case DCmode: */
51347 }
51350 {
51351 /* Parse here processor clause. If not present, default to 'b'. */
51353 }
51355 {
51356 /* If the function isn't exported, we can pick up just one ISA
51357 for the clones. */
51362 else
51365 }
51366 else
51367 {
51370 }
51372 {
51385 }
51387 {
51390 else
51395 }
51397 }
51399 /* Add target attribute to SIMD clone NODE if needed. */
51401 static void
51403 {
51407 {
51422 }
51432 }
51434 /* If SIMD clone NODE can't be used in a vectorized loop
51435 in current function, return -1, otherwise return a badness of using it
51436 (0 if it is most desirable from vecsize_mangle point of view, 1
51437 slightly less desirable, etc.). */
51439 static int
51441 {
51443 {
51461 }
51462 }
51464 /* This function adjusts the unroll factor based on
51465 the hardware capabilities. For ex, bdver3 has
51466 a loop buffer which makes unrolling of smaller
51467 loops less important. This function decides the
51468 unroll factor using number of memory references
51469 (value 32 is used) as a heuristic. */
51471 static unsigned
51473 {
51482 /* Count the number of memory references within the loop body.
51483 This value determines the unrolling factor for bdver3 and bdver4
51484 architectures. */
51493 {
51498 else
51500 }
51507 }
51510 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51512 static bool
51514 {
51515 /* For x87 floating point with standard excess precision handling,
51516 there is no adddf3 pattern (since x87 floating point only has
51517 XFmode operations) so the default hook implementation gets this
51518 wrong. */
51520 }
51522 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51524 static void
51526 {
51531 {
51546 hold_fnclex);
51559 }
51561 {
51570 mxcsr_orig_var,
51580 ldmxcsr_hold_call);
51583 else
51588 ldmxcsr_clear_call);
51589 else
51593 stxmcsr_update_call);
51595 {
51601 exceptions_assign);
51602 }
51603 else
51608 ldmxcsr_update_call);
51609 }
51610 tree atomic_feraiseexcept
51615 atomic_feraiseexcept_call);
51616 }
51618 /* Return mode to be used for bounds or VOIDmode
51619 if bounds are not supported. */
51621 static enum machine_mode
51623 {
51624 /* Do not support pointer checker if MPX
51625 is not enabled. */
51627 {
51632 }
51635 }
51637 /* Return constant used to statically initialize constant bounds.
51639 This function is used to create special bound values. For now
51640 only INIT bounds and NONE bounds are expected. More special
51641 values may be added later. */
51643 static tree
51645 {
51651 /* This function is supposed to be used to create INIT and
51652 NONE bounds only. */
51657 }
51659 /* Generate a list of statements STMTS to initialize pointer bounds
51660 variable VAR with bounds LB and UB. Return the number of generated
51661 statements. */
51663 static int
51665 {
51683 }
51685 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
51686 /* For i386, common symbol is local only for non-PIE binaries. For
51687 x86-64, common symbol is local only for non-PIE binaries or linker
51688 supports copy reloc in PIE binaries. */
51690 static bool
51692 {
51694 (!flag_pic
51695 || (TARGET_64BIT
51697 }
51698 #endif
51700 /* If MEM is in the form of [base+offset], extract the two parts
51701 of address and set to BASE and OFFSET, otherwise return false. */
51703 static bool
51705 {
51706 rtx addr;
51716 {
51720 }
51726 {
51730 }
51733 }
51735 /* Given OPERANDS of consecutive load/store, check if we can merge
51736 them into move multiple. LOAD is true if they are load instructions.
51737 MODE is the mode of memory operands. */
51739 bool
51742 {
51747 {
51752 }
51753 else
51754 {
51759 }
51766 /* Check if the addresses are in the form of [base+offset]. */
51772 /* Check if the bases are the same. */
51779 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
51784 }
51786 /* Initialize the GCC target structure. */
51787 #undef TARGET_RETURN_IN_MEMORY
51788 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51790 #undef TARGET_LEGITIMIZE_ADDRESS
51791 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51793 #undef TARGET_ATTRIBUTE_TABLE
51794 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51795 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51796 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51797 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51798 # undef TARGET_MERGE_DECL_ATTRIBUTES
51799 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51800 #endif
51802 #undef TARGET_COMP_TYPE_ATTRIBUTES
51803 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51805 #undef TARGET_INIT_BUILTINS
51806 #define TARGET_INIT_BUILTINS ix86_init_builtins
51807 #undef TARGET_BUILTIN_DECL
51808 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51809 #undef TARGET_EXPAND_BUILTIN
51810 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51812 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51813 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51814 ix86_builtin_vectorized_function
51816 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51817 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51819 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51820 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51822 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51823 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51825 #undef TARGET_BUILTIN_RECIPROCAL
51826 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51828 #undef TARGET_ASM_FUNCTION_EPILOGUE
51829 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51831 #undef TARGET_ENCODE_SECTION_INFO
51832 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51833 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51834 #else
51835 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51836 #endif
51838 #undef TARGET_ASM_OPEN_PAREN
51840 #undef TARGET_ASM_CLOSE_PAREN
51843 #undef TARGET_ASM_BYTE_OP
51844 #define TARGET_ASM_BYTE_OP ASM_BYTE
51846 #undef TARGET_ASM_ALIGNED_HI_OP
51847 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51848 #undef TARGET_ASM_ALIGNED_SI_OP
51849 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51850 #ifdef ASM_QUAD
51851 #undef TARGET_ASM_ALIGNED_DI_OP
51852 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51853 #endif
51855 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51856 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51858 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51859 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51861 #undef TARGET_ASM_UNALIGNED_HI_OP
51862 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51863 #undef TARGET_ASM_UNALIGNED_SI_OP
51864 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51865 #undef TARGET_ASM_UNALIGNED_DI_OP
51866 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51868 #undef TARGET_PRINT_OPERAND
51869 #define TARGET_PRINT_OPERAND ix86_print_operand
51870 #undef TARGET_PRINT_OPERAND_ADDRESS
51871 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51872 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51873 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51874 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51875 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51877 #undef TARGET_SCHED_INIT_GLOBAL
51878 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51879 #undef TARGET_SCHED_ADJUST_COST
51880 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51881 #undef TARGET_SCHED_ISSUE_RATE
51882 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51883 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51884 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51885 ia32_multipass_dfa_lookahead
51886 #undef TARGET_SCHED_MACRO_FUSION_P
51887 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51888 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51889 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51891 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51892 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51894 #undef TARGET_MEMMODEL_CHECK
51895 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51897 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51898 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51900 #ifdef HAVE_AS_TLS
51901 #undef TARGET_HAVE_TLS
51902 #define TARGET_HAVE_TLS true
51903 #endif
51904 #undef TARGET_CANNOT_FORCE_CONST_MEM
51905 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51906 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51907 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51909 #undef TARGET_DELEGITIMIZE_ADDRESS
51910 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51912 #undef TARGET_MS_BITFIELD_LAYOUT_P
51913 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51915 #if TARGET_MACHO
51916 #undef TARGET_BINDS_LOCAL_P
51917 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51918 #else
51919 #undef TARGET_BINDS_LOCAL_P
51920 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
51921 #endif
51922 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51923 #undef TARGET_BINDS_LOCAL_P
51924 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51925 #endif
51927 #undef TARGET_ASM_OUTPUT_MI_THUNK
51928 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51929 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51930 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51932 #undef TARGET_ASM_FILE_START
51933 #define TARGET_ASM_FILE_START x86_file_start
51935 #undef TARGET_OPTION_OVERRIDE
51936 #define TARGET_OPTION_OVERRIDE ix86_option_override
51938 #undef TARGET_REGISTER_MOVE_COST
51939 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51940 #undef TARGET_MEMORY_MOVE_COST
51941 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51942 #undef TARGET_RTX_COSTS
51943 #define TARGET_RTX_COSTS ix86_rtx_costs
51944 #undef TARGET_ADDRESS_COST
51945 #define TARGET_ADDRESS_COST ix86_address_cost
51947 #undef TARGET_FIXED_CONDITION_CODE_REGS
51948 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51949 #undef TARGET_CC_MODES_COMPATIBLE
51950 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51952 #undef TARGET_MACHINE_DEPENDENT_REORG
51953 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51955 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51956 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51958 #undef TARGET_BUILD_BUILTIN_VA_LIST
51959 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51961 #undef TARGET_FOLD_BUILTIN
51962 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51964 #undef TARGET_COMPARE_VERSION_PRIORITY
51965 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51967 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51968 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51969 ix86_generate_version_dispatcher_body
51971 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51972 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51973 ix86_get_function_versions_dispatcher
51975 #undef TARGET_ENUM_VA_LIST_P
51976 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51978 #undef TARGET_FN_ABI_VA_LIST
51979 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51981 #undef TARGET_CANONICAL_VA_LIST_TYPE
51982 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51984 #undef TARGET_EXPAND_BUILTIN_VA_START
51985 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51987 #undef TARGET_MD_ASM_CLOBBERS
51988 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51990 #undef TARGET_PROMOTE_PROTOTYPES
51991 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51992 #undef TARGET_SETUP_INCOMING_VARARGS
51993 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51994 #undef TARGET_MUST_PASS_IN_STACK
51995 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51996 #undef TARGET_FUNCTION_ARG_ADVANCE
51997 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51998 #undef TARGET_FUNCTION_ARG
51999 #define TARGET_FUNCTION_ARG ix86_function_arg
52000 #undef TARGET_INIT_PIC_REG
52001 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52002 #undef TARGET_USE_PSEUDO_PIC_REG
52003 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52004 #undef TARGET_FUNCTION_ARG_BOUNDARY
52005 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52006 #undef TARGET_PASS_BY_REFERENCE
52007 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52008 #undef TARGET_INTERNAL_ARG_POINTER
52009 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52010 #undef TARGET_UPDATE_STACK_BOUNDARY
52011 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52012 #undef TARGET_GET_DRAP_RTX
52013 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52014 #undef TARGET_STRICT_ARGUMENT_NAMING
52015 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52016 #undef TARGET_STATIC_CHAIN
52017 #define TARGET_STATIC_CHAIN ix86_static_chain
52018 #undef TARGET_TRAMPOLINE_INIT
52019 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52020 #undef TARGET_RETURN_POPS_ARGS
52021 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52023 #undef TARGET_LEGITIMATE_COMBINED_INSN
52024 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52026 #undef TARGET_ASAN_SHADOW_OFFSET
52027 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52029 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52030 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52032 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52033 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52035 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52036 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52038 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52039 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52040 ix86_libgcc_floating_mode_supported_p
52042 #undef TARGET_C_MODE_FOR_SUFFIX
52043 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52045 #ifdef HAVE_AS_TLS
52046 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52047 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52048 #endif
52050 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52051 #undef TARGET_INSERT_ATTRIBUTES
52052 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52053 #endif
52055 #undef TARGET_MANGLE_TYPE
52056 #define TARGET_MANGLE_TYPE ix86_mangle_type
52058 #if !TARGET_MACHO
52059 #undef TARGET_STACK_PROTECT_FAIL
52060 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52061 #endif
52063 #undef TARGET_FUNCTION_VALUE
52064 #define TARGET_FUNCTION_VALUE ix86_function_value
52066 #undef TARGET_FUNCTION_VALUE_REGNO_P
52067 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52069 #undef TARGET_PROMOTE_FUNCTION_MODE
52070 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52072 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52073 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52075 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52076 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52078 #undef TARGET_INSTANTIATE_DECLS
52079 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52081 #undef TARGET_SECONDARY_RELOAD
52082 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52084 #undef TARGET_CLASS_MAX_NREGS
52085 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52087 #undef TARGET_PREFERRED_RELOAD_CLASS
52088 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52089 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52090 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52091 #undef TARGET_CLASS_LIKELY_SPILLED_P
52092 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52094 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52095 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52096 ix86_builtin_vectorization_cost
52097 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52098 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52099 ix86_vectorize_vec_perm_const_ok
52100 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52101 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52102 ix86_preferred_simd_mode
52103 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52104 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52105 ix86_autovectorize_vector_sizes
52106 #undef TARGET_VECTORIZE_INIT_COST
52107 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52108 #undef TARGET_VECTORIZE_ADD_STMT_COST
52109 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52110 #undef TARGET_VECTORIZE_FINISH_COST
52111 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52112 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52113 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52115 #undef TARGET_SET_CURRENT_FUNCTION
52116 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52118 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52119 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52121 #undef TARGET_OPTION_SAVE
52122 #define TARGET_OPTION_SAVE ix86_function_specific_save
52124 #undef TARGET_OPTION_RESTORE
52125 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52127 #undef TARGET_OPTION_POST_STREAM_IN
52128 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52130 #undef TARGET_OPTION_PRINT
52131 #define TARGET_OPTION_PRINT ix86_function_specific_print
52133 #undef TARGET_OPTION_FUNCTION_VERSIONS
52134 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52136 #undef TARGET_CAN_INLINE_P
52137 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52139 #undef TARGET_EXPAND_TO_RTL_HOOK
52140 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52142 #undef TARGET_LEGITIMATE_ADDRESS_P
52143 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52145 #undef TARGET_LRA_P
52146 #define TARGET_LRA_P hook_bool_void_true
52148 #undef TARGET_REGISTER_PRIORITY
52149 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52151 #undef TARGET_REGISTER_USAGE_LEVELING_P
52152 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52154 #undef TARGET_LEGITIMATE_CONSTANT_P
52155 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52157 #undef TARGET_FRAME_POINTER_REQUIRED
52158 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52160 #undef TARGET_CAN_ELIMINATE
52161 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52163 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52164 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52166 #undef TARGET_ASM_CODE_END
52167 #define TARGET_ASM_CODE_END ix86_code_end
52169 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52170 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52172 #if TARGET_MACHO
52173 #undef TARGET_INIT_LIBFUNCS
52174 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52175 #endif
52177 #undef TARGET_LOOP_UNROLL_ADJUST
52178 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52180 #undef TARGET_SPILL_CLASS
52181 #define TARGET_SPILL_CLASS ix86_spill_class
52183 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52184 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52185 ix86_simd_clone_compute_vecsize_and_simdlen
52187 #undef TARGET_SIMD_CLONE_ADJUST
52188 #define TARGET_SIMD_CLONE_ADJUST \
52189 ix86_simd_clone_adjust
52191 #undef TARGET_SIMD_CLONE_USABLE
52192 #define TARGET_SIMD_CLONE_USABLE \
52193 ix86_simd_clone_usable
52195 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52196 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52197 ix86_float_exceptions_rounding_supported_p
52199 #undef TARGET_MODE_EMIT
52200 #define TARGET_MODE_EMIT ix86_emit_mode_set
52202 #undef TARGET_MODE_NEEDED
52203 #define TARGET_MODE_NEEDED ix86_mode_needed
52205 #undef TARGET_MODE_AFTER
52206 #define TARGET_MODE_AFTER ix86_mode_after
52208 #undef TARGET_MODE_ENTRY
52209 #define TARGET_MODE_ENTRY ix86_mode_entry
52211 #undef TARGET_MODE_EXIT
52212 #define TARGET_MODE_EXIT ix86_mode_exit
52214 #undef TARGET_MODE_PRIORITY
52215 #define TARGET_MODE_PRIORITY ix86_mode_priority
52217 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52218 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52220 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52221 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52223 #undef TARGET_STORE_BOUNDS_FOR_ARG
52224 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52226 #undef TARGET_LOAD_RETURNED_BOUNDS
52227 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52229 #undef TARGET_STORE_RETURNED_BOUNDS
52230 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52232 #undef TARGET_CHKP_BOUND_MODE
52233 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52235 #undef TARGET_BUILTIN_CHKP_FUNCTION
52236 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52238 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52239 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52241 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52242 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52244 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52245 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52247 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52248 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52250 #undef TARGET_OFFLOAD_OPTIONS
52251 #define TARGET_OFFLOAD_OPTIONS \
52252 ix86_offload_options
52254 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52255 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52258 \f