1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
38 #include "statistics.h"
39 #include "double-int.h"
41 #include "fixed-value.h"
54 #include "insn-codes.h"
58 #include "dominance.h"
62 #include "cfgcleanup.h"
63 #include "basic-block.h"
67 #include "diagnostic-core.h"
70 #include "tree-pass.h"
74 static int reload_cse_noop_set_p (rtx
);
75 static bool reload_cse_simplify (rtx_insn
*, rtx
);
76 static void reload_cse_regs_1 (void);
77 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
78 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
80 static void reload_combine (void);
81 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
82 static void reload_combine_note_store (rtx
, const_rtx
, void *);
84 static bool reload_cse_move2add (rtx_insn
*);
85 static void move2add_note_store (rtx
, const_rtx
, void *);
87 /* Call cse / combine like post-reload optimization phases.
88 FIRST is the first instruction. */
91 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
96 moves_converted
= reload_cse_move2add (first
);
97 if (flag_expensive_optimizations
)
101 reload_cse_regs_1 ();
105 /* See whether a single set SET is a noop. */
107 reload_cse_noop_set_p (rtx set
)
109 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
112 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
115 /* Try to simplify INSN. Return true if the CFG may have changed. */
117 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
119 rtx body
= PATTERN (insn
);
120 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
121 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
123 if (GET_CODE (body
) == SET
)
127 /* Simplify even if we may think it is a no-op.
128 We may think a memory load of a value smaller than WORD_SIZE
129 is redundant because we haven't taken into account possible
130 implicit extension. reload_cse_simplify_set() will bring
131 this out, so it's safer to simplify before we delete. */
132 count
+= reload_cse_simplify_set (body
, insn
);
134 if (!count
&& reload_cse_noop_set_p (body
))
136 rtx value
= SET_DEST (body
);
138 && ! REG_FUNCTION_VALUE_P (value
))
140 if (check_for_inc_dec (insn
))
141 delete_insn_and_edges (insn
);
142 /* We're done with this insn. */
147 apply_change_group ();
149 reload_cse_simplify_operands (insn
, testreg
);
151 else if (GET_CODE (body
) == PARALLEL
)
155 rtx value
= NULL_RTX
;
157 /* Registers mentioned in the clobber list for an asm cannot be reused
158 within the body of the asm. Invalidate those registers now so that
159 we don't try to substitute values for them. */
160 if (asm_noperands (body
) >= 0)
162 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
164 rtx part
= XVECEXP (body
, 0, i
);
165 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
166 cselib_invalidate_rtx (XEXP (part
, 0));
170 /* If every action in a PARALLEL is a noop, we can delete
171 the entire PARALLEL. */
172 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
174 rtx part
= XVECEXP (body
, 0, i
);
175 if (GET_CODE (part
) == SET
)
177 if (! reload_cse_noop_set_p (part
))
179 if (REG_P (SET_DEST (part
))
180 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
184 value
= SET_DEST (part
);
187 else if (GET_CODE (part
) != CLOBBER
)
193 if (check_for_inc_dec (insn
))
194 delete_insn_and_edges (insn
);
195 /* We're done with this insn. */
199 /* It's not a no-op, but we can try to simplify it. */
200 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
201 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
202 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
205 apply_change_group ();
207 reload_cse_simplify_operands (insn
, testreg
);
211 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
214 /* Do a very simple CSE pass over the hard registers.
216 This function detects no-op moves where we happened to assign two
217 different pseudo-registers to the same hard register, and then
218 copied one to the other. Reload will generate a useless
219 instruction copying a register to itself.
221 This function also detects cases where we load a value from memory
222 into two different registers, and (if memory is more expensive than
223 registers) changes it to simply copy the first register into the
226 Another optimization is performed that scans the operands of each
227 instruction to see whether the value is already available in a
228 hard register. It then replaces the operand with the hard register
229 if possible, much like an optional reload would. */
232 reload_cse_regs_1 (void)
234 bool cfg_changed
= false;
237 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
239 cselib_init (CSELIB_RECORD_MEMORY
);
240 init_alias_analysis ();
242 FOR_EACH_BB_FN (bb
, cfun
)
243 FOR_BB_INSNS (bb
, insn
)
246 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
248 cselib_process_insn (insn
);
252 end_alias_analysis ();
258 /* Try to simplify a single SET instruction. SET is the set pattern.
259 INSN is the instruction it came from.
260 This function only handles one case: if we set a register to a value
261 which is not a register, we try to find that value in some other register
262 and change the set into a register copy. */
265 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
273 struct elt_loc_list
*l
;
274 #ifdef LOAD_EXTEND_OP
275 enum rtx_code extend_op
= UNKNOWN
;
277 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
279 dreg
= true_regnum (SET_DEST (set
));
284 if (side_effects_p (src
) || true_regnum (src
) >= 0)
287 dclass
= REGNO_REG_CLASS (dreg
);
289 #ifdef LOAD_EXTEND_OP
290 /* When replacing a memory with a register, we need to honor assumptions
291 that combine made wrt the contents of sign bits. We'll do this by
292 generating an extend instruction instead of a reg->reg copy. Thus
293 the destination must be a register that we can widen. */
295 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
296 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
297 && !REG_P (SET_DEST (set
)))
301 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
305 /* If memory loads are cheaper than register copies, don't change them. */
307 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
308 else if (REG_P (src
))
309 old_cost
= register_move_cost (GET_MODE (src
),
310 REGNO_REG_CLASS (REGNO (src
)), dclass
);
312 old_cost
= set_src_cost (src
, speed
);
314 for (l
= val
->locs
; l
; l
= l
->next
)
316 rtx this_rtx
= l
->loc
;
319 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
321 #ifdef LOAD_EXTEND_OP
322 if (extend_op
!= UNKNOWN
)
326 if (!CONST_SCALAR_INT_P (this_rtx
))
332 result
= wide_int::from (std::make_pair (this_rtx
,
334 BITS_PER_WORD
, UNSIGNED
);
337 result
= wide_int::from (std::make_pair (this_rtx
,
339 BITS_PER_WORD
, SIGNED
);
344 this_rtx
= immed_wide_int_const (result
, word_mode
);
347 this_cost
= set_src_cost (this_rtx
, speed
);
349 else if (REG_P (this_rtx
))
351 #ifdef LOAD_EXTEND_OP
352 if (extend_op
!= UNKNOWN
)
354 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
355 this_cost
= set_src_cost (this_rtx
, speed
);
359 this_cost
= register_move_cost (GET_MODE (this_rtx
),
360 REGNO_REG_CLASS (REGNO (this_rtx
)),
366 /* If equal costs, prefer registers over anything else. That
367 tends to lead to smaller instructions on some machines. */
368 if (this_cost
< old_cost
369 || (this_cost
== old_cost
371 && !REG_P (SET_SRC (set
))))
373 #ifdef LOAD_EXTEND_OP
374 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
375 && extend_op
!= UNKNOWN
376 #ifdef CANNOT_CHANGE_MODE_CLASS
377 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
379 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
383 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
384 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
385 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
389 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
390 old_cost
= this_cost
, did_change
= 1;
397 /* Try to replace operands in INSN with equivalent values that are already
398 in registers. This can be viewed as optional reloading.
400 For each non-register operand in the insn, see if any hard regs are
401 known to be equivalent to that operand. Record the alternatives which
402 can accept these hard registers. Among all alternatives, select the
403 ones which are better or equal to the one currently matching, where
404 "better" is in terms of '?' and '!' constraints. Among the remaining
405 alternatives, select the one which replaces most operands with
409 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
413 /* For each operand, all registers that are equivalent to it. */
414 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
416 const char *constraints
[MAX_RECOG_OPERANDS
];
418 /* Vector recording how bad an alternative is. */
419 int *alternative_reject
;
420 /* Vector recording how many registers can be introduced by choosing
422 int *alternative_nregs
;
423 /* Array of vectors recording, for each operand and each alternative,
424 which hard register to substitute, or -1 if the operand should be
426 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
427 /* Array of alternatives, sorted in order of decreasing desirability. */
428 int *alternative_order
;
430 extract_constrain_insn (insn
);
432 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
435 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
436 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
437 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
438 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
439 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
441 /* For each operand, find out which regs are equivalent. */
442 for (i
= 0; i
< recog_data
.n_operands
; i
++)
445 struct elt_loc_list
*l
;
448 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
450 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
451 right, so avoid the problem here. Likewise if we have a constant
452 and the insn pattern doesn't tell us the mode we need. */
453 if (LABEL_P (recog_data
.operand
[i
])
454 || (CONSTANT_P (recog_data
.operand
[i
])
455 && recog_data
.operand_mode
[i
] == VOIDmode
))
458 op
= recog_data
.operand
[i
];
459 #ifdef LOAD_EXTEND_OP
461 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
462 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
464 rtx set
= single_set (insn
);
466 /* We might have multiple sets, some of which do implicit
467 extension. Punt on this for now. */
470 /* If the destination is also a MEM or a STRICT_LOW_PART, no
472 Also, if there is an explicit extension, we don't have to
473 worry about an implicit one. */
474 else if (MEM_P (SET_DEST (set
))
475 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
476 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
477 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
478 ; /* Continue ordinary processing. */
479 #ifdef CANNOT_CHANGE_MODE_CLASS
480 /* If the register cannot change mode to word_mode, it follows that
481 it cannot have been used in word_mode. */
482 else if (REG_P (SET_DEST (set
))
483 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
485 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
486 ; /* Continue ordinary processing. */
488 /* If this is a straight load, make the extension explicit. */
489 else if (REG_P (SET_DEST (set
))
490 && recog_data
.n_operands
== 2
491 && SET_SRC (set
) == op
492 && SET_DEST (set
) == recog_data
.operand
[1-i
])
494 validate_change (insn
, recog_data
.operand_loc
[i
],
495 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
498 validate_change (insn
, recog_data
.operand_loc
[1-i
],
499 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
501 if (! apply_change_group ())
503 return reload_cse_simplify_operands (insn
, testreg
);
506 /* ??? There might be arithmetic operations with memory that are
507 safe to optimize, but is it worth the trouble? */
510 #endif /* LOAD_EXTEND_OP */
511 if (side_effects_p (op
))
513 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
517 for (l
= v
->locs
; l
; l
= l
->next
)
519 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
522 alternative_mask preferred
= get_preferred_alternatives (insn
);
523 for (i
= 0; i
< recog_data
.n_operands
; i
++)
529 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
530 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
531 op_alt_regno
[i
][j
] = -1;
533 p
= constraints
[i
] = recog_data
.constraints
[i
];
534 mode
= recog_data
.operand_mode
[i
];
536 /* Add the reject values for each alternative given by the constraints
545 alternative_reject
[j
] += 3;
547 alternative_reject
[j
] += 300;
550 /* We won't change operands which are already registers. We
551 also don't want to modify output operands. */
552 regno
= true_regnum (recog_data
.operand
[i
]);
554 || constraints
[i
][0] == '='
555 || constraints
[i
][0] == '+')
558 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
560 enum reg_class rclass
= NO_REGS
;
562 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
565 SET_REGNO_RAW (testreg
, regno
);
566 PUT_MODE (testreg
, mode
);
568 /* We found a register equal to this operand. Now look for all
569 alternatives that can accept this register and have not been
570 assigned a register they can use yet. */
580 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
585 = (reg_class_subunion
587 [reg_class_for_constraint (lookup_constraint (p
))]);
591 /* See if REGNO fits this alternative, and set it up as the
592 replacement register if we don't have one for this
593 alternative yet and the operand being replaced is not
594 a cheap CONST_INT. */
595 if (op_alt_regno
[i
][j
] == -1
596 && TEST_BIT (preferred
, j
)
597 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
598 && (!CONST_INT_P (recog_data
.operand
[i
])
599 || (set_src_cost (recog_data
.operand
[i
],
600 optimize_bb_for_speed_p
601 (BLOCK_FOR_INSN (insn
)))
602 > set_src_cost (testreg
,
603 optimize_bb_for_speed_p
604 (BLOCK_FOR_INSN (insn
))))))
606 alternative_nregs
[j
]++;
607 op_alt_regno
[i
][j
] = regno
;
613 p
+= CONSTRAINT_LEN (c
, p
);
621 /* Record all alternatives which are better or equal to the currently
622 matching one in the alternative_order array. */
623 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
624 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
625 alternative_order
[j
++] = i
;
626 recog_data
.n_alternatives
= j
;
628 /* Sort it. Given a small number of alternatives, a dumb algorithm
629 won't hurt too much. */
630 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
633 int best_reject
= alternative_reject
[alternative_order
[i
]];
634 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
636 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
638 int this_reject
= alternative_reject
[alternative_order
[j
]];
639 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
641 if (this_reject
< best_reject
642 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
645 best_reject
= this_reject
;
646 best_nregs
= this_nregs
;
650 std::swap (alternative_order
[best
], alternative_order
[i
]);
653 /* Substitute the operands as determined by op_alt_regno for the best
655 j
= alternative_order
[0];
657 for (i
= 0; i
< recog_data
.n_operands
; i
++)
659 machine_mode mode
= recog_data
.operand_mode
[i
];
660 if (op_alt_regno
[i
][j
] == -1)
663 validate_change (insn
, recog_data
.operand_loc
[i
],
664 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
667 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
669 int op
= recog_data
.dup_num
[i
];
670 machine_mode mode
= recog_data
.operand_mode
[op
];
672 if (op_alt_regno
[op
][j
] == -1)
675 validate_change (insn
, recog_data
.dup_loc
[i
],
676 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
679 return apply_change_group ();
682 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
684 This code might also be useful when reload gave up on reg+reg addressing
685 because of clashes between the return register and INDEX_REG_CLASS. */
687 /* The maximum number of uses of a register we can keep track of to
688 replace them with reg+reg addressing. */
689 #define RELOAD_COMBINE_MAX_USES 16
691 /* Describes a recorded use of a register. */
694 /* The insn where a register has been used. */
696 /* Points to the memory reference enclosing the use, if any, NULL_RTX
699 /* Location of the register within INSN. */
701 /* The reverse uid of the insn. */
705 /* If the register is used in some unknown fashion, USE_INDEX is negative.
706 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
707 indicates where it is first set or clobbered.
708 Otherwise, USE_INDEX is the index of the last encountered use of the
709 register (which is first among these we have seen since we scan backwards).
710 USE_RUID indicates the first encountered, i.e. last, of these uses.
711 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
712 with a constant offset; OFFSET contains this constant in that case.
713 STORE_RUID is always meaningful if we only want to use a value in a
714 register in a different place: it denotes the next insn in the insn
715 stream (i.e. the last encountered) that sets or clobbers the register.
716 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
719 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
725 bool all_offsets_match
;
726 } reg_state
[FIRST_PSEUDO_REGISTER
];
728 /* Reverse linear uid. This is increased in reload_combine while scanning
729 the instructions from last to first. It is used to set last_label_ruid
730 and the store_ruid / use_ruid fields in reg_state. */
731 static int reload_combine_ruid
;
733 /* The RUID of the last label we encountered in reload_combine. */
734 static int last_label_ruid
;
736 /* The RUID of the last jump we encountered in reload_combine. */
737 static int last_jump_ruid
;
739 /* The register numbers of the first and last index register. A value of
740 -1 in LAST_INDEX_REG indicates that we've previously computed these
741 values and found no suitable index registers. */
742 static int first_index_reg
= -1;
743 static int last_index_reg
;
745 #define LABEL_LIVE(LABEL) \
746 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
748 /* Subroutine of reload_combine_split_ruids, called to fix up a single
749 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
752 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
754 if (*pruid
> split_ruid
)
758 /* Called when we insert a new insn in a position we've already passed in
759 the scan. Examine all our state, increasing all ruids that are higher
760 than SPLIT_RUID by one in order to make room for a new insn. */
763 reload_combine_split_ruids (int split_ruid
)
767 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
768 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
769 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
771 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
773 int j
, idx
= reg_state
[i
].use_index
;
774 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
775 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
776 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
780 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
782 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
788 /* Called when we are about to rescan a previously encountered insn with
789 reload_combine_note_use after modifying some part of it. This clears all
790 information about uses in that particular insn. */
793 reload_combine_purge_insn_uses (rtx_insn
*insn
)
797 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
799 int j
, k
, idx
= reg_state
[i
].use_index
;
802 j
= k
= RELOAD_COMBINE_MAX_USES
;
805 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
809 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
812 reg_state
[i
].use_index
= k
;
816 /* Called when we need to forget about all uses of REGNO after an insn
817 which is identified by RUID. */
820 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
822 int j
, k
, idx
= reg_state
[regno
].use_index
;
825 j
= k
= RELOAD_COMBINE_MAX_USES
;
828 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
832 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
835 reg_state
[regno
].use_index
= k
;
838 /* Find the use of REGNO with the ruid that is highest among those
839 lower than RUID_LIMIT, and return it if it is the only use of this
840 reg in the insn. Return NULL otherwise. */
842 static struct reg_use
*
843 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
845 int i
, best_ruid
= 0;
846 int use_idx
= reg_state
[regno
].use_index
;
847 struct reg_use
*retval
;
852 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
854 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
855 int this_ruid
= use
->ruid
;
856 if (this_ruid
>= ruid_limit
)
858 if (this_ruid
> best_ruid
)
860 best_ruid
= this_ruid
;
863 else if (this_ruid
== best_ruid
)
866 if (last_label_ruid
>= best_ruid
)
871 /* After we've moved an add insn, fix up any debug insns that occur
872 between the old location of the add and the new location. REG is
873 the destination register of the add insn; REPLACEMENT is the
874 SET_SRC of the add. FROM and TO specify the range in which we
875 should make this change on debug insns. */
878 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
881 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
885 if (!DEBUG_INSN_P (insn
))
888 t
= INSN_VAR_LOCATION_LOC (insn
);
889 t
= simplify_replace_rtx (t
, reg
, replacement
);
890 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
894 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
895 with SRC in the insn described by USE, taking costs into account. Return
896 true if we made the replacement. */
899 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
901 rtx_insn
*use_insn
= use
->insn
;
902 rtx mem
= use
->containing_mem
;
903 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
907 addr_space_t as
= MEM_ADDR_SPACE (mem
);
908 rtx oldaddr
= XEXP (mem
, 0);
909 rtx newaddr
= NULL_RTX
;
910 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
913 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
914 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
916 XEXP (mem
, 0) = newaddr
;
917 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
918 XEXP (mem
, 0) = oldaddr
;
919 if (new_cost
<= old_cost
920 && validate_change (use_insn
,
921 &XEXP (mem
, 0), newaddr
, 0))
927 rtx new_set
= single_set (use_insn
);
929 && REG_P (SET_DEST (new_set
))
930 && GET_CODE (SET_SRC (new_set
)) == PLUS
931 && REG_P (XEXP (SET_SRC (new_set
), 0))
932 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
935 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
937 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
938 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
940 if (set_src_cost (new_src
, speed
) <= old_cost
941 && validate_change (use_insn
, &SET_SRC (new_set
),
949 /* Called by reload_combine when scanning INSN. This function tries to detect
950 patterns where a constant is added to a register, and the result is used
952 Return true if no further processing is needed on INSN; false if it wasn't
953 recognized and should be handled normally. */
956 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
958 int from_ruid
= reload_combine_ruid
;
959 rtx set
, pat
, reg
, src
, addreg
;
963 rtx_insn
*add_moved_after_insn
= NULL
;
964 int add_moved_after_ruid
= 0;
965 int clobbered_regno
= -1;
967 set
= single_set (insn
);
971 reg
= SET_DEST (set
);
974 || REG_NREGS (reg
) != 1
975 || GET_MODE (reg
) != Pmode
976 || reg
== stack_pointer_rtx
)
981 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
982 uses of REG1 inside an address, or inside another add insn. If
983 possible and profitable, merge the addition into subsequent
985 if (GET_CODE (src
) != PLUS
986 || !REG_P (XEXP (src
, 0))
987 || !CONSTANT_P (XEXP (src
, 1)))
990 addreg
= XEXP (src
, 0);
991 must_move_add
= rtx_equal_p (reg
, addreg
);
993 pat
= PATTERN (insn
);
994 if (must_move_add
&& set
!= pat
)
996 /* We have to be careful when moving the add; apart from the
997 single_set there may also be clobbers. Recognize one special
998 case, that of one clobber alongside the set (likely a clobber
999 of the CC register). */
1000 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
1001 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
1002 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
1003 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
1005 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
1010 use
= reload_combine_closest_single_use (regno
, from_ruid
);
1013 /* Start the search for the next use from here. */
1014 from_ruid
= use
->ruid
;
1016 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1018 bool delete_add
= false;
1019 rtx_insn
*use_insn
= use
->insn
;
1020 int use_ruid
= use
->ruid
;
1022 /* Avoid moving the add insn past a jump. */
1023 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1026 /* If the add clobbers another hard reg in parallel, don't move
1027 it past a real set of this hard reg. */
1028 if (must_move_add
&& clobbered_regno
>= 0
1029 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1032 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1033 if (HAVE_cc0
&& must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1036 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1037 /* Avoid moving a use of ADDREG past a point where it is stored. */
1038 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1041 /* We also must not move the addition past an insn that sets
1042 the same register, unless we can combine two add insns. */
1043 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1045 if (use
->containing_mem
== NULL_RTX
)
1051 if (try_replace_in_use (use
, reg
, src
))
1053 reload_combine_purge_insn_uses (use_insn
);
1054 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1055 use_ruid
, NULL_RTX
);
1059 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1065 add_moved_after_insn
= use_insn
;
1066 add_moved_after_ruid
= use_ruid
;
1071 /* If we get here, we couldn't handle this use. */
1077 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1078 /* Process the add normally. */
1081 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1083 reorder_insns (insn
, insn
, add_moved_after_insn
);
1084 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1085 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1086 reload_combine_note_use (&PATTERN (insn
), insn
,
1087 add_moved_after_ruid
, NULL_RTX
);
1088 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1093 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1094 can handle and improve. Return true if no further processing is needed on
1095 INSN; false if it wasn't recognized and should be handled normally. */
1098 reload_combine_recognize_pattern (rtx_insn
*insn
)
1103 set
= single_set (insn
);
1104 if (set
== NULL_RTX
)
1107 reg
= SET_DEST (set
);
1108 src
= SET_SRC (set
);
1109 if (!REG_P (reg
) || REG_NREGS (reg
) != 1)
1112 regno
= REGNO (reg
);
1114 /* Look for (set (REGX) (CONST_INT))
1115 (set (REGX) (PLUS (REGX) (REGY)))
1117 ... (MEM (REGX)) ...
1119 (set (REGZ) (CONST_INT))
1121 ... (MEM (PLUS (REGZ) (REGY)))... .
1123 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1124 and that we know all uses of REGX before it dies.
1125 Also, explicitly check that REGX != REGY; our life information
1126 does not yet show whether REGY changes in this insn. */
1128 if (GET_CODE (src
) == PLUS
1129 && reg_state
[regno
].all_offsets_match
1130 && last_index_reg
!= -1
1131 && REG_P (XEXP (src
, 1))
1132 && rtx_equal_p (XEXP (src
, 0), reg
)
1133 && !rtx_equal_p (XEXP (src
, 1), reg
)
1134 && reg_state
[regno
].use_index
>= 0
1135 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1136 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1138 rtx base
= XEXP (src
, 1);
1139 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1140 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1141 rtx index_reg
= NULL_RTX
;
1142 rtx reg_sum
= NULL_RTX
;
1145 /* Now we need to set INDEX_REG to an index register (denoted as
1146 REGZ in the illustration above) and REG_SUM to the expression
1147 register+register that we want to use to substitute uses of REG
1148 (typically in MEMs) with. First check REG and BASE for being
1149 index registers; we can use them even if they are not dead. */
1150 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1151 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1159 /* Otherwise, look for a free index register. Since we have
1160 checked above that neither REG nor BASE are index registers,
1161 if we find anything at all, it will be different from these
1163 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1165 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1166 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1167 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1168 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1169 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1170 && !fixed_regs
[i
] && !global_regs
[i
]
1171 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1172 && targetm
.hard_regno_scratch_ok (i
))
1174 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1175 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1181 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1182 (REGY), i.e. BASE, is not clobbered before the last use we'll
1186 && CONST_INT_P (SET_SRC (prev_set
))
1187 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1188 && (reg_state
[REGNO (base
)].store_ruid
1189 <= reg_state
[regno
].use_ruid
))
1191 /* Change destination register and, if necessary, the constant
1192 value in PREV, the constant loading instruction. */
1193 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1194 if (reg_state
[regno
].offset
!= const0_rtx
)
1195 validate_change (prev
,
1196 &SET_SRC (prev_set
),
1197 GEN_INT (INTVAL (SET_SRC (prev_set
))
1198 + INTVAL (reg_state
[regno
].offset
)),
1201 /* Now for every use of REG that we have recorded, replace REG
1203 for (i
= reg_state
[regno
].use_index
;
1204 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1205 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1206 reg_state
[regno
].reg_use
[i
].usep
,
1207 /* Each change must have its own
1211 if (apply_change_group ())
1213 struct reg_use
*lowest_ruid
= NULL
;
1215 /* For every new use of REG_SUM, we have to record the use
1216 of BASE therein, i.e. operand 1. */
1217 for (i
= reg_state
[regno
].use_index
;
1218 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1220 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1221 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1222 use
->ruid
, use
->containing_mem
);
1223 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1227 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1229 /* Delete the reg-reg addition. */
1232 if (reg_state
[regno
].offset
!= const0_rtx
)
1233 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1235 remove_reg_equal_equiv_notes (prev
);
1237 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1246 reload_combine (void)
1248 rtx_insn
*insn
, *prev
;
1251 int min_labelno
, n_labels
;
1252 HARD_REG_SET ever_live_at_start
, *label_live
;
1254 /* To avoid wasting too much time later searching for an index register,
1255 determine the minimum and maximum index register numbers. */
1256 if (INDEX_REG_CLASS
== NO_REGS
)
1257 last_index_reg
= -1;
1258 else if (first_index_reg
== -1 && last_index_reg
== 0)
1260 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1261 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1263 if (first_index_reg
== -1)
1264 first_index_reg
= r
;
1269 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1270 to -1 so we'll know to quit early the next time we get here. */
1271 if (first_index_reg
== -1)
1273 last_index_reg
= -1;
1278 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1279 information is a bit fuzzy immediately after reload, but it's
1280 still good enough to determine which registers are live at a jump
1282 min_labelno
= get_first_label_num ();
1283 n_labels
= max_label_num () - min_labelno
;
1284 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1285 CLEAR_HARD_REG_SET (ever_live_at_start
);
1287 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1289 insn
= BB_HEAD (bb
);
1293 bitmap live_in
= df_get_live_in (bb
);
1295 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1296 compute_use_by_pseudos (&live
, live_in
);
1297 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1298 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1302 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1303 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1304 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1306 reg_state
[r
].store_ruid
= 0;
1307 reg_state
[r
].real_store_ruid
= 0;
1309 reg_state
[r
].use_index
= -1;
1311 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1314 for (insn
= get_last_insn (); insn
; insn
= prev
)
1316 bool control_flow_insn
;
1319 prev
= PREV_INSN (insn
);
1321 /* We cannot do our optimization across labels. Invalidating all the use
1322 information we have would be costly, so we just note where the label
1323 is and then later disable any optimization that would cross it. */
1325 last_label_ruid
= reload_combine_ruid
;
1326 else if (BARRIER_P (insn
))
1328 /* Crossing a barrier resets all the use information. */
1329 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1330 if (! fixed_regs
[r
])
1331 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1333 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1334 /* Optimizations across insns being marked as volatile must be
1335 prevented. All the usage information is invalidated
1337 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1339 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1340 reg_state
[r
].use_index
= -1;
1342 if (! NONDEBUG_INSN_P (insn
))
1345 reload_combine_ruid
++;
1347 control_flow_insn
= control_flow_insn_p (insn
);
1348 if (control_flow_insn
)
1349 last_jump_ruid
= reload_combine_ruid
;
1351 if (reload_combine_recognize_const_pattern (insn
)
1352 || reload_combine_recognize_pattern (insn
))
1355 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1361 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1362 if (call_used_regs
[r
])
1364 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1365 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1368 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1369 link
= XEXP (link
, 1))
1371 rtx setuse
= XEXP (link
, 0);
1372 rtx usage_rtx
= XEXP (setuse
, 0);
1373 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1374 && REG_P (usage_rtx
))
1376 unsigned int end_regno
= END_REGNO (usage_rtx
);
1377 for (unsigned int i
= REGNO (usage_rtx
); i
< end_regno
; ++i
)
1378 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1380 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1381 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1384 reg_state
[i
].use_index
= -1;
1389 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1391 /* Non-spill registers might be used at the call destination in
1392 some unknown fashion, so we have to mark the unknown use. */
1395 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1396 && JUMP_LABEL (insn
))
1398 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1401 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1404 live
= &ever_live_at_start
;
1407 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1408 if (TEST_HARD_REG_BIT (*live
, r
))
1409 reg_state
[r
].use_index
= -1;
1412 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1415 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1417 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1419 int regno
= REGNO (XEXP (note
, 0));
1420 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1421 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1422 reg_state
[regno
].use_index
= -1;
1430 /* Check if DST is a register or a subreg of a register; if it is,
1431 update store_ruid, real_store_ruid and use_index in the reg_state
1432 structure accordingly. Called via note_stores from reload_combine. */
1435 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1439 machine_mode mode
= GET_MODE (dst
);
1441 if (GET_CODE (dst
) == SUBREG
)
1443 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1444 GET_MODE (SUBREG_REG (dst
)),
1447 dst
= SUBREG_REG (dst
);
1450 /* Some targets do argument pushes without adding REG_INC notes. */
1454 dst
= XEXP (dst
, 0);
1455 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1456 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1457 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1459 unsigned int end_regno
= END_REGNO (XEXP (dst
, 0));
1460 for (unsigned int i
= REGNO (XEXP (dst
, 0)); i
< end_regno
; ++i
)
1462 /* We could probably do better, but for now mark the register
1463 as used in an unknown fashion and set/clobbered at this
1465 reg_state
[i
].use_index
= -1;
1466 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1467 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1476 regno
+= REGNO (dst
);
1478 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1479 careful with registers / register parts that are not full words.
1480 Similarly for ZERO_EXTRACT. */
1481 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1482 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1484 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1486 reg_state
[i
].use_index
= -1;
1487 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1488 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1493 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1495 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1496 if (GET_CODE (set
) == SET
)
1497 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1498 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1503 /* XP points to a piece of rtl that has to be checked for any uses of
1505 *XP is the pattern of INSN, or a part of it.
1506 Called from reload_combine, and recursively by itself. */
1508 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1511 enum rtx_code code
= x
->code
;
1514 rtx offset
= const0_rtx
; /* For the REG case below. */
1519 if (REG_P (SET_DEST (x
)))
1521 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1527 /* If this is the USE of a return value, we can't change it. */
1528 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1530 /* Mark the return register as used in an unknown fashion. */
1531 rtx reg
= XEXP (x
, 0);
1532 unsigned int end_regno
= END_REGNO (reg
);
1533 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
1534 reg_state
[regno
].use_index
= -1;
1540 if (REG_P (SET_DEST (x
)))
1542 /* No spurious CLOBBERs of pseudo registers may remain. */
1543 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1549 /* We are interested in (plus (reg) (const_int)) . */
1550 if (!REG_P (XEXP (x
, 0))
1551 || !CONST_INT_P (XEXP (x
, 1)))
1553 offset
= XEXP (x
, 1);
1558 int regno
= REGNO (x
);
1562 /* No spurious USEs of pseudo registers may remain. */
1563 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1565 nregs
= REG_NREGS (x
);
1567 /* We can't substitute into multi-hard-reg uses. */
1570 while (--nregs
>= 0)
1571 reg_state
[regno
+ nregs
].use_index
= -1;
1575 /* We may be called to update uses in previously seen insns.
1576 Don't add uses beyond the last store we saw. */
1577 if (ruid
< reg_state
[regno
].store_ruid
)
1580 /* If this register is already used in some unknown fashion, we
1582 If we decrement the index from zero to -1, we can't store more
1583 uses, so this register becomes used in an unknown fashion. */
1584 use_index
= --reg_state
[regno
].use_index
;
1588 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1590 /* This is the first use of this register we have seen since we
1591 marked it as dead. */
1592 reg_state
[regno
].offset
= offset
;
1593 reg_state
[regno
].all_offsets_match
= true;
1594 reg_state
[regno
].use_ruid
= ruid
;
1598 if (reg_state
[regno
].use_ruid
> ruid
)
1599 reg_state
[regno
].use_ruid
= ruid
;
1601 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1602 reg_state
[regno
].all_offsets_match
= false;
1605 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1606 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1607 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1608 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1620 /* Recursively process the components of X. */
1621 fmt
= GET_RTX_FORMAT (code
);
1622 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1625 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1626 else if (fmt
[i
] == 'E')
1628 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1629 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1635 /* See if we can reduce the cost of a constant by replacing a move
1636 with an add. We track situations in which a register is set to a
1637 constant or to a register plus a constant. */
1638 /* We cannot do our optimization across labels. Invalidating all the
1639 information about register contents we have would be costly, so we
1640 use move2add_last_label_luid to note where the label is and then
1641 later disable any optimization that would cross it.
1642 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1643 are only valid if reg_set_luid[n] is greater than
1644 move2add_last_label_luid.
1645 For a set that established a new (potential) base register with
1646 non-constant value, we use move2add_luid from the place where the
1647 setting insn is encountered; registers based off that base then
1648 get the same reg_set_luid. Constants all get
1649 move2add_last_label_luid + 1 as their reg_set_luid. */
1650 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1652 /* If reg_base_reg[n] is negative, register n has been set to
1653 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1654 If reg_base_reg[n] is non-negative, register n has been set to the
1655 sum of reg_offset[n] and the value of register reg_base_reg[n]
1656 before reg_set_luid[n], calculated in mode reg_mode[n] .
1657 For multi-hard-register registers, all but the first one are
1658 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1659 marks it as invalid. */
1660 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1661 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1662 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1663 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1665 /* move2add_luid is linearly increased while scanning the instructions
1666 from first to last. It is used to set reg_set_luid in
1667 reload_cse_move2add and move2add_note_store. */
1668 static int move2add_luid
;
1670 /* move2add_last_label_luid is set whenever a label is found. Labels
1671 invalidate all previously collected reg_offset data. */
1672 static int move2add_last_label_luid
;
1674 /* ??? We don't know how zero / sign extension is handled, hence we
1675 can't go from a narrower to a wider mode. */
1676 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1677 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1678 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1679 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1681 /* Record that REG is being set to a value with the mode of REG. */
1684 move2add_record_mode (rtx reg
)
1687 machine_mode mode
= GET_MODE (reg
);
1689 if (GET_CODE (reg
) == SUBREG
)
1691 regno
= subreg_regno (reg
);
1692 nregs
= subreg_nregs (reg
);
1694 else if (REG_P (reg
))
1696 regno
= REGNO (reg
);
1697 nregs
= REG_NREGS (reg
);
1701 for (int i
= nregs
- 1; i
> 0; i
--)
1702 reg_mode
[regno
+ i
] = BLKmode
;
1703 reg_mode
[regno
] = mode
;
1706 /* Record that REG is being set to the sum of SYM and OFF. */
1709 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1711 int regno
= REGNO (reg
);
1713 move2add_record_mode (reg
);
1714 reg_set_luid
[regno
] = move2add_luid
;
1715 reg_base_reg
[regno
] = -1;
1716 reg_symbol_ref
[regno
] = sym
;
1717 reg_offset
[regno
] = INTVAL (off
);
1720 /* Check if REGNO contains a valid value in MODE. */
1723 move2add_valid_value_p (int regno
, machine_mode mode
)
1725 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1728 if (mode
!= reg_mode
[regno
])
1730 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1732 /* The value loaded into regno in reg_mode[regno] is also valid in
1733 mode after truncation only if (REG:mode regno) is the lowpart of
1734 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1735 regno of the lowpart might be different. */
1736 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1737 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1739 /* We could in principle adjust regno, check reg_mode[regno] to be
1740 BLKmode, and return s_off to the caller (vs. -1 for failure),
1741 but we currently have no callers that could make use of this
1746 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1747 if (reg_mode
[regno
+ i
] != BLKmode
)
1752 /* This function is called with INSN that sets REG to (SYM + OFF),
1753 while REG is known to already have value (SYM + offset).
1754 This function tries to change INSN into an add instruction
1755 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1756 It also updates the information about REG's known value.
1757 Return true if we made a change. */
1760 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1762 rtx pat
= PATTERN (insn
);
1763 rtx src
= SET_SRC (pat
);
1764 int regno
= REGNO (reg
);
1765 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1767 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1768 bool changed
= false;
1770 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1771 use (set (reg) (reg)) instead.
1772 We don't delete this insn, nor do we convert it into a
1773 note, to avoid losing register notes or the return
1774 value flag. jump2 already knows how to get rid of
1776 if (new_src
== const0_rtx
)
1778 /* If the constants are different, this is a
1779 truncation, that, if turned into (set (reg)
1780 (reg)), would be discarded. Maybe we should
1781 try a truncMN pattern? */
1782 if (INTVAL (off
) == reg_offset
[regno
])
1783 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1787 struct full_rtx_costs oldcst
, newcst
;
1788 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1790 get_full_set_rtx_cost (pat
, &oldcst
);
1791 SET_SRC (pat
) = tem
;
1792 get_full_set_rtx_cost (pat
, &newcst
);
1793 SET_SRC (pat
) = src
;
1795 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1796 && have_add2_insn (reg
, new_src
))
1797 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1798 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1800 machine_mode narrow_mode
;
1801 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1802 narrow_mode
!= VOIDmode
1803 && narrow_mode
!= GET_MODE (reg
);
1804 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1806 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1807 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1808 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1810 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1811 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1814 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode
,
1817 get_full_set_rtx_cost (new_set
, &newcst
);
1818 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1820 changed
= validate_change (insn
, &PATTERN (insn
),
1829 move2add_record_sym_value (reg
, sym
, off
);
1834 /* This function is called with INSN that sets REG to (SYM + OFF),
1835 but REG doesn't have known value (SYM + offset). This function
1836 tries to find another register which is known to already have
1837 value (SYM + offset) and change INSN into an add instruction
1838 (set (REG) (plus (the found register) (OFF - offset))) if such
1839 a register is found. It also updates the information about
1841 Return true iff we made a change. */
1844 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1846 rtx pat
= PATTERN (insn
);
1847 rtx src
= SET_SRC (pat
);
1848 int regno
= REGNO (reg
);
1850 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1852 bool changed
= false;
1853 struct full_rtx_costs oldcst
, newcst
, mincst
;
1856 init_costs_to_max (&mincst
);
1857 get_full_set_rtx_cost (pat
, &oldcst
);
1859 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1860 SET_SRC (pat
) = plus_expr
;
1862 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1863 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1864 && reg_base_reg
[i
] < 0
1865 && reg_symbol_ref
[i
] != NULL_RTX
1866 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1868 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1870 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1871 use (set (reg) (reg)) instead.
1872 We don't delete this insn, nor do we convert it into a
1873 note, to avoid losing register notes or the return
1874 value flag. jump2 already knows how to get rid of
1876 if (new_src
== const0_rtx
)
1878 init_costs_to_zero (&mincst
);
1884 XEXP (plus_expr
, 1) = new_src
;
1885 get_full_set_rtx_cost (pat
, &newcst
);
1887 if (costs_lt_p (&newcst
, &mincst
, speed
))
1894 SET_SRC (pat
) = src
;
1896 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1900 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1903 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1905 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1907 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1910 reg_set_luid
[regno
] = move2add_luid
;
1911 move2add_record_sym_value (reg
, sym
, off
);
1915 /* Convert move insns with constant inputs to additions if they are cheaper.
1916 Return true if any changes were made. */
1918 reload_cse_move2add (rtx_insn
*first
)
1922 bool changed
= false;
1924 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1926 reg_set_luid
[i
] = 0;
1928 reg_base_reg
[i
] = 0;
1929 reg_symbol_ref
[i
] = NULL_RTX
;
1930 reg_mode
[i
] = VOIDmode
;
1933 move2add_last_label_luid
= 0;
1935 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1941 move2add_last_label_luid
= move2add_luid
;
1942 /* We're going to increment move2add_luid twice after a
1943 label, so that we can use move2add_last_label_luid + 1 as
1944 the luid for constants. */
1948 if (! INSN_P (insn
))
1950 pat
= PATTERN (insn
);
1951 /* For simplicity, we only perform this optimization on
1952 straightforward SETs. */
1953 if (GET_CODE (pat
) == SET
1954 && REG_P (SET_DEST (pat
)))
1956 rtx reg
= SET_DEST (pat
);
1957 int regno
= REGNO (reg
);
1958 rtx src
= SET_SRC (pat
);
1960 /* Check if we have valid information on the contents of this
1961 register in the mode of REG. */
1962 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1963 && dbg_cnt (cse2_move2add
))
1965 /* Try to transform (set (REGX) (CONST_INT A))
1967 (set (REGX) (CONST_INT B))
1969 (set (REGX) (CONST_INT A))
1971 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1973 (set (REGX) (CONST_INT A))
1975 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1978 if (CONST_INT_P (src
)
1979 && reg_base_reg
[regno
] < 0
1980 && reg_symbol_ref
[regno
] == NULL_RTX
)
1982 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1986 /* Try to transform (set (REGX) (REGY))
1987 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1990 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1993 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1995 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1996 else if (REG_P (src
)
1997 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1998 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1999 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
2001 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
2004 set
= single_set (next
);
2006 && SET_DEST (set
) == reg
2007 && GET_CODE (SET_SRC (set
)) == PLUS
2008 && XEXP (SET_SRC (set
), 0) == reg
2009 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
2011 rtx src3
= XEXP (SET_SRC (set
), 1);
2012 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
2013 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
2014 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
2016 gen_int_mode (added_offset
2020 bool success
= false;
2021 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2023 if (new_src
== const0_rtx
)
2024 /* See above why we create (set (reg) (reg)) here. */
2026 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2029 rtx old_src
= SET_SRC (set
);
2030 struct full_rtx_costs oldcst
, newcst
;
2031 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2033 get_full_set_rtx_cost (set
, &oldcst
);
2034 SET_SRC (set
) = tem
;
2035 get_full_set_src_cost (tem
, &newcst
);
2036 SET_SRC (set
) = old_src
;
2037 costs_add_n_insns (&oldcst
, 1);
2039 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2040 && have_add2_insn (reg
, new_src
))
2042 rtx newpat
= gen_rtx_SET (reg
, tem
);
2044 = validate_change (next
, &PATTERN (next
),
2052 move2add_record_mode (reg
);
2054 = trunc_int_for_mode (added_offset
+ base_offset
,
2062 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2064 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2066 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2068 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2069 if ((GET_CODE (src
) == SYMBOL_REF
2070 || (GET_CODE (src
) == CONST
2071 && GET_CODE (XEXP (src
, 0)) == PLUS
2072 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2073 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2074 && dbg_cnt (cse2_move2add
))
2078 if (GET_CODE (src
) == SYMBOL_REF
)
2085 sym
= XEXP (XEXP (src
, 0), 0);
2086 off
= XEXP (XEXP (src
, 0), 1);
2089 /* If the reg already contains the value which is sum of
2090 sym and some constant value, we can use an add2 insn. */
2091 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2092 && reg_base_reg
[regno
] < 0
2093 && reg_symbol_ref
[regno
] != NULL_RTX
2094 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2095 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2097 /* Otherwise, we have to find a register whose value is sum
2098 of sym and some constant value. */
2100 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2106 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2108 if (REG_NOTE_KIND (note
) == REG_INC
2109 && REG_P (XEXP (note
, 0)))
2111 /* Reset the information about this register. */
2112 int regno
= REGNO (XEXP (note
, 0));
2113 if (regno
< FIRST_PSEUDO_REGISTER
)
2115 move2add_record_mode (XEXP (note
, 0));
2116 reg_mode
[regno
] = VOIDmode
;
2120 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2122 /* If INSN is a conditional branch, we try to extract an
2123 implicit set out of it. */
2124 if (any_condjump_p (insn
))
2126 rtx cnd
= fis_get_condition (insn
);
2129 && GET_CODE (cnd
) == NE
2130 && REG_P (XEXP (cnd
, 0))
2131 && !reg_set_p (XEXP (cnd
, 0), insn
)
2132 /* The following two checks, which are also in
2133 move2add_note_store, are intended to reduce the
2134 number of calls to gen_rtx_SET to avoid memory
2135 allocation if possible. */
2136 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2137 && REG_NREGS (XEXP (cnd
, 0)) == 1
2138 && CONST_INT_P (XEXP (cnd
, 1)))
2141 gen_rtx_SET (XEXP (cnd
, 0), XEXP (cnd
, 1));
2142 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2146 /* If this is a CALL_INSN, all call used registers are stored with
2150 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2152 if (call_used_regs
[i
])
2153 /* Reset the information about this register. */
2154 reg_mode
[i
] = VOIDmode
;
2161 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2163 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2164 Called from reload_cse_move2add via note_stores. */
2167 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2169 rtx_insn
*insn
= (rtx_insn
*) data
;
2170 unsigned int regno
= 0;
2171 machine_mode mode
= GET_MODE (dst
);
2173 /* Some targets do argument pushes without adding REG_INC notes. */
2177 dst
= XEXP (dst
, 0);
2178 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2179 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2180 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2184 if (GET_CODE (dst
) == SUBREG
)
2185 regno
= subreg_regno (dst
);
2186 else if (REG_P (dst
))
2187 regno
= REGNO (dst
);
2191 if (SCALAR_INT_MODE_P (mode
)
2192 && GET_CODE (set
) == SET
)
2194 rtx note
, sym
= NULL_RTX
;
2197 note
= find_reg_equal_equiv_note (insn
);
2198 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2200 sym
= XEXP (note
, 0);
2203 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2204 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2205 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2206 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2208 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2209 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2212 if (sym
!= NULL_RTX
)
2214 move2add_record_sym_value (dst
, sym
, off
);
2219 if (SCALAR_INT_MODE_P (mode
)
2220 && GET_CODE (set
) == SET
2221 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2222 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2224 rtx src
= SET_SRC (set
);
2226 unsigned HOST_WIDE_INT offset
;
2229 switch (GET_CODE (src
))
2232 if (REG_P (XEXP (src
, 0)))
2234 base_reg
= XEXP (src
, 0);
2236 if (CONST_INT_P (XEXP (src
, 1)))
2237 offset
= UINTVAL (XEXP (src
, 1));
2238 else if (REG_P (XEXP (src
, 1))
2239 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2241 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2242 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2243 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2244 /* Maybe the first register is known to be a
2246 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2247 && reg_base_reg
[REGNO (base_reg
)] < 0
2248 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2250 offset
= reg_offset
[REGNO (base_reg
)];
2251 base_reg
= XEXP (src
, 1);
2270 /* Start tracking the register as a constant. */
2271 reg_base_reg
[regno
] = -1;
2272 reg_symbol_ref
[regno
] = NULL_RTX
;
2273 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2274 /* We assign the same luid to all registers set to constants. */
2275 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2276 move2add_record_mode (dst
);
2283 base_regno
= REGNO (base_reg
);
2284 /* If information about the base register is not valid, set it
2285 up as a new base register, pretending its value is known
2286 starting from the current insn. */
2287 if (!move2add_valid_value_p (base_regno
, mode
))
2289 reg_base_reg
[base_regno
] = base_regno
;
2290 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2291 reg_offset
[base_regno
] = 0;
2292 reg_set_luid
[base_regno
] = move2add_luid
;
2293 gcc_assert (GET_MODE (base_reg
) == mode
);
2294 move2add_record_mode (base_reg
);
2297 /* Copy base information from our base register. */
2298 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2299 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2300 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2302 /* Compute the sum of the offsets or constants. */
2304 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2306 move2add_record_mode (dst
);
2311 /* Invalidate the contents of the register. */
2312 move2add_record_mode (dst
);
2313 reg_mode
[regno
] = VOIDmode
;
2319 const pass_data pass_data_postreload_cse
=
2321 RTL_PASS
, /* type */
2322 "postreload", /* name */
2323 OPTGROUP_NONE
, /* optinfo_flags */
2324 TV_RELOAD_CSE_REGS
, /* tv_id */
2325 0, /* properties_required */
2326 0, /* properties_provided */
2327 0, /* properties_destroyed */
2328 0, /* todo_flags_start */
2329 TODO_df_finish
, /* todo_flags_finish */
2332 class pass_postreload_cse
: public rtl_opt_pass
2335 pass_postreload_cse (gcc::context
*ctxt
)
2336 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2339 /* opt_pass methods: */
2340 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2342 virtual unsigned int execute (function
*);
2344 }; // class pass_postreload_cse
2347 pass_postreload_cse::execute (function
*fun
)
2349 if (!dbg_cnt (postreload_cse
))
2352 /* Do a very simple CSE pass over just the hard registers. */
2353 reload_cse_regs (get_insns ());
2354 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2355 Remove any EH edges associated with them. */
2356 if (fun
->can_throw_non_call_exceptions
2357 && purge_all_dead_edges ())
2366 make_pass_postreload_cse (gcc::context
*ctxt
)
2368 return new pass_postreload_cse (ctxt
);