| blob | e813d66b40a6a9abce0a913f3d643153917bfd05 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
68 /* This file should be included last. */
71 /* Defined for convenience. */
72 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
74 /* Classifies an address.
76 ADDRESS_REG_IMM
77 A simple base register plus immediate offset.
79 ADDRESS_REG_WB
80 A base register indexed by immediate offset with writeback.
82 ADDRESS_REG_REG
83 A base register indexed by (optionally scaled) register.
85 ADDRESS_REG_UXTW
86 A base register indexed by (optionally scaled) zero-extended register.
88 ADDRESS_REG_SXTW
89 A base register indexed by (optionally scaled) sign-extended register.
91 ADDRESS_LO_SUM
92 A LO_SUM rtx with a base register and "LO12" symbol relocation.
94 ADDRESS_SYMBOLIC:
95 A constant symbolic address, in pc-relative literal pool. */
98 ADDRESS_REG_IMM,
99 ADDRESS_REG_WB,
100 ADDRESS_REG_REG,
101 ADDRESS_REG_UXTW,
102 ADDRESS_REG_SXTW,
103 ADDRESS_LO_SUM,
104 ADDRESS_SYMBOLIC
105 };
109 rtx base;
110 rtx offset;
113 };
115 struct simd_immediate_info
116 {
117 rtx value;
122 };
124 /* The current code model. */
127 #ifdef HAVE_AS_TLS
128 #undef TARGET_HAVE_TLS
129 #define TARGET_HAVE_TLS 1
130 #endif
134 const_tree,
145 /* Major revision number of the ARM Architecture implemented by the target. */
148 /* The processor for which instructions should be scheduled. */
151 /* Mask to specify which instruction scheduling options should be used. */
154 /* Global flag for PC relative loads. */
157 /* Support for command line parsing of boolean flags in the tuning
158 structures. */
159 struct aarch64_flag_desc
160 {
163 };
165 #define AARCH64_FUSION_PAIR(name, internal_name) \
166 { name, AARCH64_FUSE_##internal_name },
168 {
173 };
174 #undef AARCH64_FUION_PAIR
176 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
177 { name, AARCH64_EXTRA_TUNE_##internal_name },
179 {
184 };
185 #undef AARCH64_EXTRA_TUNING_OPTION
187 /* Tuning parameters. */
190 {
191 {
196 },
203 };
206 {
207 {
212 },
219 };
222 {
223 {
228 },
235 };
238 {
239 {
244 },
251 };
254 {
255 {
260 },
267 };
270 {
271 {
276 },
283 };
286 {
288 /* Avoid the use of slow int<->fp moves for spilling by setting
289 their cost higher than memmov_cost. */
293 };
296 {
298 /* Avoid the use of slow int<->fp moves for spilling by setting
299 their cost higher than memmov_cost. */
303 };
306 {
308 /* Avoid the use of slow int<->fp moves for spilling by setting
309 their cost higher than memmov_cost. */
313 };
316 {
318 /* Avoid the use of slow int<->fp moves for spilling by setting
319 their cost higher than memmov_cost (actual, 4 and 9). */
323 };
326 {
331 };
334 {
336 /* Avoid the use of slow int<->fp moves for spilling by setting
337 their cost higher than memmov_cost. */
341 };
344 {
346 /* Avoid the use of int<->fp moves for spilling. */
350 };
353 {
355 /* Avoid the use of int<->fp moves for spilling. */
359 };
361 /* Generic costs for vector insn classes. */
363 {
377 };
379 /* ThunderX costs for vector insn classes. */
381 {
395 };
397 /* Generic costs for vector insn classes. */
399 {
413 };
416 {
430 };
432 /* Generic costs for vector insn classes. */
434 {
448 };
450 /* Costs for vector insn classes for Vulcan. */
452 {
466 };
468 /* Generic costs for branch instructions. */
470 {
473 };
475 /* Branch costs for Cortex-A57. */
477 {
480 };
482 /* Branch costs for Vulcan. */
484 {
487 };
489 /* Generic approximation modes. */
491 {
494 AARCH64_APPROX_NONE /* recip_sqrt */
495 };
497 /* Approximation modes for Exynos M1. */
499 {
502 AARCH64_APPROX_ALL /* recip_sqrt */
503 };
505 /* Approximation modes for X-Gene 1. */
507 {
510 AARCH64_APPROX_ALL /* recip_sqrt */
511 };
514 {
536 };
539 {
562 };
565 {
588 };
591 {
614 };
617 {
640 };
643 {
666 };
669 {
691 };
694 {
716 };
719 {
741 };
744 {
767 };
770 {
792 };
794 /* Support for fine-grained override of the tuning structures. */
795 struct aarch64_tuning_override_function
796 {
799 };
804 static const struct aarch64_tuning_override_function
805 aarch64_tuning_override_functions[] =
806 {
810 };
812 /* A processor implementing AArch64. */
813 struct processor
814 {
822 };
824 /* Architectures implementing AArch64. */
826 {
827 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
828 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
830 #undef AARCH64_ARCH
832 };
834 /* Processor cores implementing AArch64. */
836 {
837 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
838 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
839 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
840 FLAGS, &COSTS##_tunings},
842 #undef AARCH64_CORE
846 };
849 /* Target specification. These are populated by the -march, -mtune, -mcpu
850 handling code or by target attributes. */
855 /* The current tuning set. */
858 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
860 /* An ISA extension in the co-processor and main instruction set space. */
861 struct aarch64_option_extension
862 {
866 };
869 {
873 }
874 aarch64_cc;
876 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
878 /* The condition codes of the processor, and the inverse function. */
880 {
883 };
885 /* Generate code to enable conditional branches in functions over 1 MiB. */
889 {
906 }
908 void
910 {
914 else
916 }
918 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
919 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
920 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
921 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
922 cost (in this case the best class is the lowest cost one). Using ALL_REGS
923 irrespectively of its cost results in bad allocations with many redundant
924 int<->FP moves which are expensive on various cores.
925 To avoid this we don't allow ALL_REGS as the allocno class, but force a
926 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
927 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
928 Otherwise set the allocno class depending on the mode.
929 The result of this is that it is no longer inefficient to have a higher
930 memory move cost than the register move cost.
931 */
933 static reg_class_t
935 reg_class_t best_class)
936 {
947 }
949 static unsigned int
951 {
955 }
957 static int
960 {
968 }
970 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
971 unsigned
973 {
981 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
982 equivalent DWARF register. */
984 }
986 /* Return TRUE if MODE is any of the large INT modes. */
987 static bool
989 {
991 }
993 /* Return TRUE if MODE is any of the vector modes. */
994 static bool
996 {
999 }
1001 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1002 static bool
1005 {
1013 }
1015 /* Implement HARD_REGNO_NREGS. */
1017 int
1019 {
1021 {
1027 }
1029 }
1031 /* Implement HARD_REGNO_MODE_OK. */
1033 int
1035 {
1040 /* The purpose of comparing with ptr_mode is to support the
1041 global register variable associated with the stack pointer
1042 register via the syntax of asm ("wsp") in ILP32. */
1052 {
1054 return
1056 else
1058 }
1061 }
1063 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1064 machine_mode
1066 machine_mode mode)
1067 {
1068 /* Handle modes that fit within single registers. */
1070 {
1073 else
1075 }
1076 /* Fall back to generic for multi-reg and very large modes. */
1077 else
1079 }
1081 /* Return true if calls to DECL should be treated as
1082 long-calls (ie called via a register). */
1083 static bool
1085 {
1087 }
1089 /* Return true if calls to symbol-ref SYM should be treated as
1090 long-calls (ie called via a register). */
1091 bool
1093 {
1095 }
1097 /* Return true if calls to symbol-ref SYM should not go through
1098 plt stubs. */
1100 bool
1102 {
1106 && decl
1107 && (!flag_plt
1113 }
1115 /* Return true if the offsets to a zero/sign-extract operation
1116 represent an expression that matches an extend operation. The
1117 operands represent the paramters from
1119 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1120 bool
1122 rtx extract_imm)
1123 {
1140 }
1142 /* Emit an insn that's a simple single-set. Both the operands must be
1143 known to be valid. */
1146 {
1148 }
1150 /* X and Y are two things to compare using CODE. Emit the compare insn and
1151 return the rtx for register 0 in the proper mode. */
1152 rtx
1154 {
1160 }
1162 /* Build the SYMBOL_REF for __tls_get_addr. */
1166 rtx
1168 {
1172 }
1174 /* Return the TLS model to use for ADDR. */
1176 static enum tls_model
1178 {
1183 {
1187 }
1192 }
1194 /* We'll allow lo_sum's in addresses in our legitimate addresses
1195 so that combine would take care of combining addresses where
1196 necessary, but for generation purposes, we'll generate the address
1197 as :
1198 RTL Absolute
1199 tmp = hi (symbol_ref); adrp x1, foo
1200 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1201 nop
1203 PIC TLS
1204 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1205 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1206 bl __tls_get_addr
1207 nop
1209 Load TLS symbol, depending on TLS mechanism and TLS access model.
1211 Global Dynamic - Traditional TLS:
1212 adrp tmp, :tlsgd:imm
1213 add dest, tmp, #:tlsgd_lo12:imm
1214 bl __tls_get_addr
1216 Global Dynamic - TLS Descriptors:
1217 adrp dest, :tlsdesc:imm
1218 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1219 add dest, dest, #:tlsdesc_lo12:imm
1220 blr tmp
1221 mrs tp, tpidr_el0
1222 add dest, dest, tp
1224 Initial Exec:
1225 mrs tp, tpidr_el0
1226 adrp tmp, :gottprel:imm
1227 ldr dest, [tmp, #:gottprel_lo12:imm]
1228 add dest, dest, tp
1230 Local Exec:
1231 mrs tp, tpidr_el0
1232 add t0, tp, #:tprel_hi12:imm, lsl #12
1233 add t0, t0, #:tprel_lo12_nc:imm
1234 */
1236 static void
1239 {
1241 {
1243 {
1244 /* In ILP32, the mode of dest can be either SImode or DImode. */
1256 }
1263 {
1266 rtx insn;
1267 rtx mem;
1269 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1270 here before rtl expand. Tree IVOPT will generate rtl pattern to
1271 decide rtx costs, in which case pic_offset_table_rtx is not
1272 initialized. For that case no need to generate the first adrp
1273 instruction as the final cost for global variable access is
1274 one instruction. */
1276 {
1277 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1278 using the page base as GOT base, the first page may be wasted,
1279 in the worst scenario, there is only 28K space for GOT).
1281 The generate instruction sequence for accessing global variable
1282 is:
1284 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1286 Only one instruction needed. But we must initialize
1287 pic_offset_table_rtx properly. We generate initialize insn for
1288 every global access, and allow CSE to remove all redundant.
1290 The final instruction sequences will look like the following
1291 for multiply global variables access.
1293 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1295 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1296 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1297 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1298 ... */
1306 }
1309 {
1312 else
1316 }
1317 else
1318 {
1323 }
1325 /* The operand is expected to be MEM. Whenever the related insn
1326 pattern changed, above code which calculate mem should be
1327 updated. */
1333 }
1336 {
1337 /* In ILP32, the mode of dest can be either SImode or DImode,
1338 while the got entry is always of SImode size. The mode of
1339 dest depends on how dest is used: if dest is assigned to a
1340 pointer (e.g. in the memory), it has SImode; it may have
1341 DImode if dest is dereferenced to access the memeory.
1342 This is why we have to handle three different ldr_got_small
1343 patterns here (two patterns for ILP32). */
1345 rtx insn;
1346 rtx mem;
1355 {
1358 else
1362 }
1363 else
1364 {
1369 }
1376 }
1379 {
1391 }
1394 {
1397 rtx tp;
1401 /* In ILP32, the got entry is always of SImode size. Unlike
1402 small GOT, the dest is fixed at reg 0. */
1405 else
1415 }
1418 {
1419 /* In ILP32, the mode of dest can be either SImode or DImode,
1420 while the got entry is always of SImode size. The mode of
1421 dest depends on how dest is used: if dest is assigned to a
1422 pointer (e.g. in the memory), it has SImode; it may have
1423 DImode if dest is dereferenced to access the memeory.
1424 This is why we have to handle three different tlsie_small
1425 patterns here (two patterns for ILP32). */
1431 {
1434 else
1435 {
1438 }
1439 }
1440 else
1441 {
1444 }
1449 }
1455 {
1463 {
1486 }
1490 }
1497 {
1502 {
1505 else
1506 {
1509 }
1510 }
1511 else
1512 {
1515 }
1519 }
1523 }
1524 }
1526 /* Emit a move from SRC to DEST. Assume that the move expanders can
1527 handle all moves if !can_create_pseudo_p (). The distinction is
1528 important because, unlike emit_move_insn, the move expanders know
1529 how to force Pmode objects into the constant pool even when the
1530 constant pool address is not itself legitimate. */
1531 static rtx
1533 {
1537 }
1539 /* Split a 128-bit move operation into two 64-bit move operations,
1540 taking care to handle partial overlap of register to register
1541 copies. Special cases are needed when moving between GP regs and
1542 FP regs. SRC can be a register, constant or memory; DST a register
1543 or memory. If either operand is memory it must not have any side
1544 effects. */
1545 void
1547 {
1558 {
1562 /* Handle FP <-> GP regs. */
1564 {
1569 {
1572 }
1573 else
1574 {
1577 }
1579 }
1581 {
1586 {
1589 }
1590 else
1591 {
1594 }
1596 }
1597 }
1604 /* At most one pairing may overlap. */
1606 {
1609 }
1610 else
1611 {
1614 }
1615 }
1617 bool
1619 {
1622 }
1624 /* Split a complex SIMD combine. */
1626 void
1628 {
1635 {
1639 {
1663 }
1667 }
1668 }
1670 /* Split a complex SIMD move. */
1672 void
1674 {
1681 {
1687 {
1711 }
1715 }
1716 }
1718 bool
1721 {
1725 }
1728 static rtx
1730 {
1733 else
1734 {
1737 }
1738 }
1741 static rtx
1743 {
1745 {
1746 rtx high;
1747 /* Load the full offset into a register. This
1748 might be improvable in the future. */
1754 }
1756 }
1758 static int
1760 machine_mode mode)
1761 {
1770 {
1774 }
1777 {
1779 {
1784 else
1787 }
1789 }
1791 /* Remaining cases are all for DImode. */
1800 {
1801 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1802 For a 64-bit bitmask try whether changing 16 bits to all ones or
1803 zeroes creates a valid bitmask. To check any repeated bitmask,
1804 try using 16 bits from the other 32-bit half of val. */
1807 {
1818 }
1820 {
1822 {
1826 }
1828 }
1829 }
1831 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1832 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1833 otherwise skip zero bits. */
1845 {
1851 num_insns ++;
1852 }
1855 }
1858 void
1860 {
1865 /* Check on what type of symbol it is. */
1869 {
1873 /* If we have (const (plus symbol offset)), separate out the offset
1874 before we start classifying the symbol. */
1879 {
1883 {
1889 }
1894 /* If we aren't generating PC relative literals, then
1895 we need to expand the literal pool access carefully.
1896 This is something that needs to be done in a number
1897 of places, so could well live as a separate function. */
1899 {
1904 }
1921 {
1927 }
1928 /* FALLTHRU */
1941 }
1942 }
1945 {
1948 else
1949 {
1953 }
1956 }
1959 }
1961 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to held
1962 intermediate value if necessary.
1964 This function is sometimes used to adjust the stack pointer, so we must
1965 ensure that it can never cause transient stack deallocation by writing an
1966 invalid value into REGNUM. */
1968 static void
1971 {
1976 /* Do nothing if mdelta is zero. */
1980 /* We only need single instruction if the offset fit into add/sub. */
1982 {
1986 }
1988 /* We need two add/sub instructions, each one performing part of the
1989 calculation. Don't do this if the addend can be loaded into register with
1990 a single instruction, in that case we prefer a move to a scratch register
1991 following by an addition. */
1993 {
2002 }
2004 /* Otherwise use generic function to handle all other situations. */
2009 {
2013 }
2014 }
2016 static bool
2018 tree exp ATTRIBUTE_UNUSED)
2019 {
2020 /* Currently, always true. */
2022 }
2024 /* Implement TARGET_PASS_BY_REFERENCE. */
2026 static bool
2028 machine_mode mode,
2029 const_tree type,
2031 {
2032 HOST_WIDE_INT size;
2033 machine_mode dummymode;
2036 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2040 /* Aggregates are passed by reference based on their size. */
2042 {
2044 }
2046 /* Variable sized arguments are always returned by reference. */
2050 /* Can this be a candidate to be passed in fp/simd register(s)? */
2053 NULL))
2056 /* Arguments which are variable sized or larger than 2 registers are
2057 passed by reference unless they are a homogenous floating point
2058 aggregate. */
2060 }
2062 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2063 static bool
2065 {
2066 machine_mode dummy_mode;
2069 /* Never happens in little-endian mode. */
2073 /* Only composite types smaller than or equal to 16 bytes can
2074 be potentially returned in registers. */
2080 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2081 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2082 is always passed/returned in the least significant bits of fp/simd
2083 register(s). */
2089 }
2091 /* Implement TARGET_FUNCTION_VALUE.
2092 Define how to find the value returned by a function. */
2094 static rtx
2097 {
2098 machine_mode mode;
2101 machine_mode ag_mode;
2108 {
2112 {
2115 }
2116 }
2120 {
2122 {
2125 }
2126 else
2127 {
2129 rtx par;
2133 {
2138 }
2140 }
2141 }
2142 else
2144 }
2146 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2147 Return true if REGNO is the number of a hard register in which the values
2148 of called function may come back. */
2150 static bool
2152 {
2153 /* Maximum of 16 bytes can be returned in the general registers. Examples
2154 of 16-byte return values are: 128-bit integers and 16-byte small
2155 structures (excluding homogeneous floating-point aggregates). */
2159 /* Up to four fp/simd registers can return a function value, e.g. a
2160 homogeneous floating-point aggregate having four members. */
2165 }
2167 /* Implement TARGET_RETURN_IN_MEMORY.
2169 If the type T of the result of a function is such that
2170 void func (T arg)
2171 would require that arg be passed as a value in a register (or set of
2172 registers) according to the parameter passing rules, then the result
2173 is returned in the same registers as would be used for such an
2174 argument. */
2176 static bool
2178 {
2179 HOST_WIDE_INT size;
2180 machine_mode ag_mode;
2186 /* Simple scalar types always returned in registers. */
2190 type,
2193 NULL))
2196 /* Types larger than 2 registers returned in memory. */
2199 }
2201 static bool
2204 {
2207 type,
2209 nregs,
2210 NULL);
2211 }
2213 /* Given MODE and TYPE of a function argument, return the alignment in
2214 bits. The idea is to suppress any stronger alignment requested by
2215 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2216 This is a helper function for local use only. */
2218 static unsigned int
2220 {
2240 }
2242 /* Layout a function argument according to the AAPCS64 rules. The rule
2243 numbers refer to the rule numbers in the AAPCS64. */
2245 static void
2247 const_tree type,
2249 {
2253 HOST_WIDE_INT size;
2255 /* We need to do this once per argument. */
2261 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2262 size
2264 UNITS_PER_WORD);
2268 mode,
2269 type,
2272 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2273 The following code thus handles passing by SIMD/FP registers first. */
2277 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2278 and homogenous short-vector aggregates (HVA). */
2280 {
2285 {
2288 {
2291 }
2292 else
2293 {
2294 rtx par;
2298 {
2301 tmp = gen_rtx_EXPR_LIST
2305 }
2307 }
2309 }
2310 else
2311 {
2312 /* C.3 NSRN is set to 8. */
2315 }
2316 }
2321 /* C6 - C9. though the sign and zero extension semantics are
2322 handled elsewhere. This is the case where the argument fits
2323 entirely general registers. */
2325 {
2330 /* C.8 if the argument has an alignment of 16 then the NGRN is
2331 rounded up to the next even number. */
2333 {
2336 }
2337 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2338 A reg is still generated for it, but the caller should be smart
2339 enough not to use it. */
2341 {
2343 }
2344 else
2345 {
2346 rtx par;
2351 {
2356 }
2358 }
2362 }
2364 /* C.11 */
2367 /* The argument is passed on stack; record the needed number of words for
2368 this argument and align the total size if necessary. */
2369 on_stack:
2375 }
2377 /* Implement TARGET_FUNCTION_ARG. */
2379 static rtx
2382 {
2391 }
2393 void
2395 const_tree fntype ATTRIBUTE_UNUSED,
2396 rtx libname ATTRIBUTE_UNUSED,
2397 const_tree fndecl ATTRIBUTE_UNUSED,
2399 {
2413 {
2420 }
2422 }
2424 static void
2426 machine_mode mode,
2427 const_tree type,
2429 {
2432 {
2442 }
2443 }
2445 bool
2447 {
2450 }
2452 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2453 PARM_BOUNDARY bits of alignment, but will be given anything up
2454 to STACK_BOUNDARY bits if the type requires it. This makes sure
2455 that both before and after the layout of each argument, the Next
2456 Stacked Argument Address (NSAA) will have a minimum alignment of
2457 8 bytes. */
2459 static unsigned int
2461 {
2469 }
2471 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2473 Return true if an argument passed on the stack should be padded upwards,
2474 i.e. if the least-significant byte of the stack slot has useful data.
2476 Small aggregate types are placed in the lowest memory address.
2478 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2480 bool
2482 {
2483 /* On little-endian targets, the least significant byte of every stack
2484 argument is passed at the lowest byte address of the stack slot. */
2488 /* Otherwise, integral, floating-point and pointer types are padded downward:
2489 the least significant byte of a stack argument is passed at the highest
2490 byte address of the stack slot. */
2497 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2499 }
2501 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2503 It specifies padding for the last (may also be the only)
2504 element of a block move between registers and memory. If
2505 assuming the block is in the memory, padding upward means that
2506 the last element is padded after its highest significant byte,
2507 while in downward padding, the last element is padded at the
2508 its least significant byte side.
2510 Small aggregates and small complex types are always padded
2511 upwards.
2513 We don't need to worry about homogeneous floating-point or
2514 short-vector aggregates; their move is not affected by the
2515 padding direction determined here. Regardless of endianness,
2516 each element of such an aggregate is put in the least
2517 significant bits of a fp/simd register.
2519 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2520 register has useful data, and return the opposite if the most
2521 significant byte does. */
2523 bool
2526 {
2528 /* Small composite types are always padded upward. */
2530 {
2535 }
2537 /* Otherwise, use the default padding. */
2539 }
2541 static machine_mode
2543 {
2545 }
2547 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2549 /* We use the 12-bit shifted immediate arithmetic instructions so values
2550 must be multiple of (1 << 12), i.e. 4096. */
2551 #define ARITH_FACTOR 4096
2553 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2554 #error Cannot use simple address calculation for stack probing
2555 #endif
2557 /* The pair of scratch registers used for stack probing. */
2558 #define PROBE_STACK_FIRST_REG 9
2559 #define PROBE_STACK_SECOND_REG 10
2561 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2562 inclusive. These are offsets from the current stack pointer. */
2564 static void
2566 {
2569 /* See the same assertion on PROBE_INTERVAL above. */
2572 /* See if we have a constant small number of probes to generate. If so,
2573 that's the easy case. */
2575 {
2582 }
2584 /* The run-time loop is made up of 8 insns in the generic case while the
2585 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2587 {
2592 stack_pointer_rtx,
2596 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2597 it exceeds SIZE. If only two probes are needed, this will not
2598 generate any code. Then probe at FIRST + SIZE. */
2600 {
2604 }
2608 {
2613 }
2614 else
2616 }
2618 /* Otherwise, do the same as above, but in a loop. Note that we must be
2619 extra careful with variables wrapping around because we might be at
2620 the very top (or the very bottom) of the address space and we have
2621 to be able to handle this case properly; in particular, we use an
2622 equality test for the loop condition. */
2623 else
2624 {
2627 /* Step 1: round SIZE to the previous multiple of the interval. */
2632 /* Step 2: compute initial and final value of the loop counter. */
2634 /* TEST_ADDR = SP + FIRST. */
2638 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2644 /* Step 3: the loop
2646 do
2647 {
2648 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2649 probe at TEST_ADDR
2650 }
2651 while (TEST_ADDR != LAST_ADDR)
2653 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2654 until it is equal to ROUNDED_SIZE. */
2658 else
2662 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2663 that SIZE is equal to ROUNDED_SIZE. */
2666 {
2670 {
2675 }
2676 else
2678 }
2679 }
2681 /* Make sure nothing is scheduled before we are done. */
2683 }
2685 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2686 absolute addresses. */
2690 {
2697 /* Loop. */
2700 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2705 /* Probe at TEST_ADDR. */
2708 /* Test if TEST_ADDR == LAST_ADDR. */
2712 /* Branch. */
2718 }
2720 static bool
2722 {
2723 /* In aarch64_override_options_after_change
2724 flag_omit_leaf_frame_pointer turns off the frame pointer by
2725 default. Turn it back on now if we've not got a leaf
2726 function. */
2732 }
2734 /* Mark the registers that need to be saved by the callee and calculate
2735 the size of the callee-saved registers area and frame record (both FP
2736 and LR may be omitted). */
2737 static void
2739 {
2746 #define SLOT_NOT_REQUIRED (-2)
2747 #define SLOT_REQUIRED (-1)
2752 /* First mark all the registers that really need to be saved... */
2759 /* ... that includes the eh data registers (if needed)... */
2765 /* ... and any callee saved register that dataflow says is live. */
2778 {
2779 /* FP and LR are placed in the linkage record. */
2785 }
2787 /* Now assign stack slots for them. */
2790 {
2797 }
2801 {
2809 }
2815 HOST_WIDE_INT varargs_and_saved_regs_size
2842 {
2843 /* Simple, small frame with no outgoing arguments:
2844 stp reg1, reg2, [sp, -frame_size]!
2845 stp reg3, reg4, [sp, 16] */
2847 }
2852 {
2853 /* Frame with small outgoing arguments:
2854 sub sp, sp, frame_size
2855 stp reg1, reg2, [sp, outgoing_args_size]
2856 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2860 }
2862 {
2863 /* Frame with large outgoing arguments but a small local area:
2864 stp reg1, reg2, [sp, -hard_fp_offset]!
2865 stp reg3, reg4, [sp, 16]
2866 sub sp, sp, outgoing_args_size */
2870 }
2873 {
2874 /* Frame with large local area and outgoing arguments (this pushes the
2875 callee-saves first, followed by the locals and outgoing area):
2876 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2877 stp reg3, reg4, [sp, 16]
2878 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2884 }
2885 else
2886 {
2887 /* Frame with large local area and outgoing arguments using frame pointer:
2888 sub sp, sp, hard_fp_offset
2889 stp x29, x30, [sp, 0]
2890 add x29, sp, 0
2891 stp reg3, reg4, [sp, 16]
2892 sub sp, sp, outgoing_args_size */
2896 }
2899 }
2901 static bool
2903 {
2905 }
2907 static unsigned
2909 {
2911 regno ++;
2913 }
2915 static void
2917 HOST_WIDE_INT adjustment)
2918 {
2929 }
2931 static rtx
2933 HOST_WIDE_INT adjustment)
2934 {
2936 {
2947 }
2948 }
2950 static void
2952 {
2967 }
2969 static rtx
2971 HOST_WIDE_INT adjustment)
2972 {
2974 {
2983 }
2984 }
2986 static void
2989 {
2996 {
3000 }
3001 else
3002 {
3007 }
3008 }
3010 static rtx
3012 rtx reg2)
3013 {
3015 {
3024 }
3025 }
3027 static rtx
3029 rtx mem2)
3030 {
3032 {
3041 }
3042 }
3045 static void
3048 {
3058 {
3060 HOST_WIDE_INT offset;
3070 offset));
3078 {
3080 rtx mem2;
3084 offset));
3086 reg2));
3088 /* The first part of a frame-related parallel insn is
3089 always assumed to be relevant to the frame
3090 calculations; subsequent parts, are only
3091 frame-related if explicitly marked. */
3094 }
3095 else
3099 }
3100 }
3102 static void
3106 {
3112 HOST_WIDE_INT offset;
3117 {
3134 {
3136 rtx mem2;
3144 }
3145 else
3148 }
3149 }
3151 /* AArch64 stack frames generated by this compiler look like:
3153 +-------------------------------+
3154 | |
3155 | incoming stack arguments |
3156 | |
3157 +-------------------------------+
3158 | | <-- incoming stack pointer (aligned)
3159 | callee-allocated save area |
3160 | for register varargs |
3161 | |
3162 +-------------------------------+
3163 | local variables | <-- frame_pointer_rtx
3164 | |
3165 +-------------------------------+
3166 | padding0 | \
3167 +-------------------------------+ |
3168 | callee-saved registers | | frame.saved_regs_size
3169 +-------------------------------+ |
3170 | LR' | |
3171 +-------------------------------+ |
3172 | FP' | / <- hard_frame_pointer_rtx (aligned)
3173 +-------------------------------+
3174 | dynamic allocation |
3175 +-------------------------------+
3176 | padding |
3177 +-------------------------------+
3178 | outgoing stack arguments | <-- arg_pointer
3179 | |
3180 +-------------------------------+
3181 | | <-- stack_pointer_rtx (aligned)
3183 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3184 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3185 unchanged. */
3187 /* Generate the prologue instructions for entry into a function.
3188 Establish the stack frame by decreasing the stack pointer with a
3189 properly calculated size and, if necessary, create a frame record
3190 filled with the values of LR and previous frame pointer. The
3191 current FP is also set up if it is in use. */
3193 void
3195 {
3211 {
3213 {
3217 }
3220 }
3228 {
3233 stack_pointer_rtx,
3237 }
3245 }
3247 /* Return TRUE if we can use a simple_return insn.
3249 This function checks whether the callee saved stack is empty, which
3250 means no restore actions are need. The pro_and_epilogue will use
3251 this to check whether shrink-wrapping opt is feasible. */
3253 bool
3255 {
3265 }
3267 /* Generate the epilogue instructions for returning from a function.
3268 This is almost exactly the reverse of the prolog sequence, except
3269 that we need to insert barriers to avoid scheduling loads that read
3270 from a deallocated stack, and we optimize the unwind records by
3271 emitting them all together if possible. */
3272 void
3274 {
3286 /* We need to add memory barrier to prevent read from deallocated stack. */
3290 /* Emit a barrier to prevent loads from a deallocated stack. */
3292 {
3295 }
3297 /* Restore the stack pointer from the frame pointer if it may not
3298 be the same as the stack pointer. */
3300 {
3302 hard_frame_pointer_rtx,
3304 /* If writeback is used when restoring callee-saves, the CFA
3305 is restored on the instruction doing the writeback. */
3307 }
3308 else
3323 {
3324 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3330 }
3335 {
3336 /* Emit delayed restores and reset the CFA to be SP. */
3341 }
3343 /* Stack adjustment for exception handler. */
3345 {
3346 /* We need to unwind the stack by the offset computed by
3347 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3348 to be SP; letting the CFA move during this adjustment
3349 is just as correct as retaining the CFA from the body
3350 of the function. Therefore, do nothing special. */
3352 }
3357 }
3359 /* Return the place to copy the exception unwinding return address to.
3360 This will probably be a stack slot, but could (in theory be the
3361 return register). */
3362 rtx
3364 {
3365 HOST_WIDE_INT fp_offset;
3375 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
3376 result in a store to save LR introduced by builtin_eh_return () being
3377 incorrectly deleted because the alias is not detected.
3378 So in the calculation of the address to copy the exception unwinding
3379 return address to, we note 2 cases.
3380 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
3381 we return a SP-relative location since all the addresses are SP-relative
3382 in this case. This prevents the store from being optimized away.
3383 If the fp_offset is not 0, then the addresses will be FP-relative and
3384 therefore we return a FP-relative location. */
3387 {
3391 else
3394 }
3396 /* If FP is not needed, we calculate the location of LR, which would be
3397 at the top of the saved registers block. */
3401 stack_pointer_rtx,
3402 fp_offset
3405 }
3407 /* Output code to add DELTA to the first argument, and then jump
3408 to FUNCTION. Used for C++ multiple inheritance. */
3409 static void
3411 HOST_WIDE_INT delta,
3412 HOST_WIDE_INT vcall_offset,
3413 tree function)
3414 {
3415 /* The this pointer is always in x0. Note that this differs from
3416 Arm where the this pointer maybe bumped to r1 if r0 is required
3417 to return a pointer to an aggregate. On AArch64 a result value
3418 pointer will be in x8. */
3428 else
3429 {
3438 {
3442 else
3444 }
3448 else
3455 else
3456 {
3458 Pmode);
3460 }
3464 else
3470 }
3472 /* Generate a tail call to the target function. */
3474 {
3477 }
3489 /* Stop pretending to be a post-reload pass. */
3491 }
3493 static bool
3495 {
3500 {
3504 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3505 TLS offsets, not real symbol references. */
3508 }
3510 }
3513 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3514 a left shift of 0 or 12 bits. */
3515 bool
3517 {
3520 );
3521 }
3524 /* Return true if val is an immediate that can be loaded into a
3525 register by a MOVZ instruction. */
3526 static bool
3528 {
3530 {
3534 }
3535 else
3536 {
3537 /* Ignore sign extension. */
3539 }
3542 }
3544 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3547 {
3553 };
3556 /* Return true if val is a valid bitmask immediate. */
3558 bool
3560 {
3564 /* Check for a single sequence of one bits and return quickly if so.
3565 The special cases of all ones and all zeroes returns false. */
3572 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3576 /* Invert if the immediate doesn't start with a zero bit - this means we
3577 only need to search for sequences of one bits. */
3581 /* Find the first set bit and set tmp to val with the first sequence of one
3582 bits removed. Return success if there is a single sequence of ones. */
3589 /* Find the next set bit and compute the difference in bit position. */
3594 /* Check the bit position difference is a power of 2, and that the first
3595 sequence of one bits fits within 'bits' bits. */
3599 /* Check the sequence of one bits is repeated 64/bits times. */
3601 }
3604 /* Return true if val is an immediate that can be loaded into a
3605 register in a single instruction. */
3606 bool
3608 {
3612 }
3614 static bool
3616 {
3624 {
3628 else
3629 /* Avoid generating a 64-bit relocation in ILP32; leave
3630 to aarch64_expand_mov_immediate to handle it properly. */
3632 }
3635 }
3637 /* Implement TARGET_CASE_VALUES_THRESHOLD.
3638 The expansion for a table switch is quite expensive due to the number
3639 of instructions, the table lookup and hard to predict indirect jump.
3640 When optimizing for speed, and -O3 enabled, use the per-core tuning if
3641 set, otherwise use tables for > 16 cases as a tradeoff between size and
3642 performance. When optimizing for size, use the default setting. */
3644 static unsigned int
3646 {
3647 /* Use the specified limit for the number of cases before using jump
3648 tables at higher optimization levels. */
3652 else
3654 }
3656 /* Return true if register REGNO is a valid index register.
3657 STRICT_P is true if REG_OK_STRICT is in effect. */
3659 bool
3661 {
3663 {
3671 }
3673 }
3675 /* Return true if register REGNO is a valid base register for mode MODE.
3676 STRICT_P is true if REG_OK_STRICT is in effect. */
3678 bool
3680 {
3682 {
3690 }
3692 /* The fake registers will be eliminated to either the stack or
3693 hard frame pointer, both of which are usually valid base registers.
3694 Reload deals with the cases where the eliminated form isn't valid. */
3699 }
3701 /* Return true if X is a valid base register for mode MODE.
3702 STRICT_P is true if REG_OK_STRICT is in effect. */
3704 static bool
3706 {
3711 }
3713 /* Return true if address offset is a valid index. If it is, fill in INFO
3714 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3716 static bool
3719 {
3721 rtx index;
3724 /* (reg:P) */
3727 {
3731 }
3732 /* (sign_extend:DI (reg:SI)) */
3737 {
3742 }
3743 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3750 {
3755 }
3756 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3763 {
3768 }
3769 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3776 {
3784 }
3785 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3786 (const_int 0xffffffff<<shift)) */
3793 {
3799 }
3800 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3807 {
3815 }
3816 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3817 (const_int 0xffffffff<<shift)) */
3824 {
3830 }
3831 /* (mult:P (reg:P) (const_int scale)) */
3836 {
3840 }
3841 /* (ashift:P (reg:P) (const_int shift)) */
3846 {
3850 }
3851 else
3862 {
3867 }
3870 }
3872 bool
3874 {
3878 }
3882 HOST_WIDE_INT offset)
3883 {
3885 }
3889 {
3893 }
3895 /* Return true if MODE is one of the modes for which we
3896 support LDP/STP operations. */
3898 static bool
3900 {
3905 }
3907 /* Return true if REGNO is a virtual pointer register, or an eliminable
3908 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
3909 include stack_pointer or hard_frame_pointer. */
3910 static bool
3912 {
3917 }
3919 /* Return true if X is a valid address for machine mode MODE. If it is,
3920 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3921 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3923 static bool
3927 {
3931 /* On BE, we use load/store pair for all large int mode load/stores. */
3933 || (BYTES_BIG_ENDIAN
3937 !load_store_pair_p
3941 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3942 REG addressing. */
3948 {
3964 {
3970 }
3975 {
3982 /* TImode and TFmode values are allowed in both pairs of X
3983 registers and individual Q registers. The available
3984 address modes are:
3985 X,X: 7-bit signed scaled offset
3986 Q: 9-bit signed offset
3987 We conservatively require an offset representable in either mode.
3988 When performing the check for pairs of X registers i.e. LDP/STP
3989 pass down DImode since that is the natural size of the LDP/STP
3990 instruction memory accesses. */
3995 /* A 7bit offset check because OImode will emit a ldp/stp
3996 instruction (only big endian will get here).
3997 For ldp/stp instructions, the offset is scaled for the size of a
3998 single element of the pair. */
4002 /* Three 9/12 bit offsets checks because CImode will emit three
4003 ldr/str instructions (only big endian will get here). */
4010 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4011 instructions (only big endian will get here). */
4020 else
4023 }
4026 {
4027 /* Look for base + (scaled/extended) index register. */
4030 {
4033 }
4036 {
4039 }
4040 }
4061 {
4062 HOST_WIDE_INT offset;
4066 /* TImode and TFmode values are allowed in both pairs of X
4067 registers and individual Q registers. The available
4068 address modes are:
4069 X,X: 7-bit signed scaled offset
4070 Q: 9-bit signed offset
4071 We conservatively require an offset representable in either mode.
4072 */
4080 else
4082 }
4088 /* load literal: pc-relative constant pool entry. Only supported
4089 for SI mode or larger. */
4093 {
4101 }
4110 {
4115 {
4116 /* The symbol and offset must be aligned to the access size. */
4123 {
4127 }
4133 else
4142 }
4143 }
4148 }
4149 }
4151 bool
4153 {
4154 rtx offset;
4158 }
4160 /* Classify the base of symbolic expression X. */
4162 enum aarch64_symbol_type
4164 {
4165 rtx offset;
4169 }
4172 /* Return TRUE if X is a legitimate address for accessing memory in
4173 mode MODE. */
4174 static bool
4176 {
4180 }
4182 /* Return TRUE if X is a legitimate address for accessing memory in
4183 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4184 pair operation. */
4185 bool
4188 {
4192 }
4194 /* Return TRUE if rtx X is immediate constant 0.0 */
4195 bool
4197 {
4204 }
4206 /* Return the fixed registers used for condition codes. */
4208 static bool
4210 {
4214 }
4216 /* Emit call insn with PAT and do aarch64-specific handling. */
4218 void
4220 {
4226 }
4228 machine_mode
4230 {
4231 /* All floating point compares return CCFP if it is an equality
4232 comparison, and CCFPE otherwise. */
4234 {
4236 {
4257 }
4258 }
4260 /* Equality comparisons of short modes against zero can be performed
4261 using the TST instruction with the appropriate bitmask. */
4267 /* Similarly, comparisons of zero_extends from shorter modes can
4268 be performed using an ANDS with an immediate mask. */
4284 /* A compare with a shifted operand. Because of canonicalization,
4285 the comparison will have to be swapped when we emit the assembly
4286 code. */
4294 /* Similarly for a negated operand, but we can only do this for
4295 equalities. */
4302 /* A test for unsigned overflow. */
4309 /* For everything else, return CCmode. */
4311 }
4313 static int
4316 int
4318 {
4325 }
4327 static int
4329 {
4331 {
4335 {
4349 }
4354 {
4366 }
4371 {
4383 }
4388 {
4394 }
4399 {
4403 }
4408 {
4412 }
4418 }
4421 }
4423 bool
4425 HOST_WIDE_INT minval,
4426 HOST_WIDE_INT maxval)
4427 {
4428 HOST_WIDE_INT firstval;
4445 }
4447 bool
4449 {
4451 }
4454 /* N Z C V. */
4455 #define AARCH64_CC_V 1
4456 #define AARCH64_CC_C (1 << 1)
4457 #define AARCH64_CC_Z (1 << 2)
4458 #define AARCH64_CC_N (1 << 3)
4460 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4462 {
4479 };
4481 static void
4483 {
4485 {
4486 /* An integer or symbol address without a preceding # sign. */
4489 {
4501 {
4504 }
4505 /* Fall through. */
4509 }
4513 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4514 {
4519 {
4522 }
4525 {
4538 }
4539 }
4543 {
4546 /* Print N such that 2^N == X. */
4548 {
4551 }
4554 }
4558 /* Print the number of non-zero bits in X (a const_int). */
4560 {
4563 }
4569 /* Print the higher numbered register of a pair (TImode) of regs. */
4571 {
4574 }
4581 {
4583 /* Print a condition (eq, ne, etc) or its inverse. */
4585 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4587 {
4591 }
4594 {
4597 }
4604 }
4612 /* Print a scalar FP/SIMD register name. */
4614 {
4615 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4617 }
4625 /* Print the first FP/SIMD register name in a list. */
4627 {
4628 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4630 }
4635 /* Print a scalar FP/SIMD register name + 1. */
4637 {
4638 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4640 }
4645 /* Print bottom 16 bits of integer constant in hex. */
4647 {
4650 }
4656 /* Print a general register name or the zero register (32-bit or
4657 64-bit). */
4660 {
4663 }
4666 {
4669 }
4672 {
4675 }
4677 /* Fall through */
4680 /* Print a normal operand, if it's a general register, then we
4681 assume DImode. */
4683 {
4686 }
4689 {
4710 {
4713 HOST_WIDE_INT_MIN,
4714 HOST_WIDE_INT_MAX));
4716 }
4718 {
4720 }
4721 else
4726 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4727 be getting CONST_DOUBLEs holding integers. */
4730 {
4733 }
4735 {
4736 #define buf_size 20
4744 #undef buf_size
4745 }
4751 }
4759 {
4786 }
4792 {
4827 }
4834 {
4840 }
4845 {
4846 HOST_WIDE_INT cond_code;
4847 /* Print nzcv. */
4850 {
4853 }
4858 }
4864 }
4865 }
4867 static void
4869 {
4874 {
4878 else
4887 else
4896 else
4905 else
4912 {
4939 }
4950 }
4953 }
4955 bool
4957 {
4964 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4965 referencing instruction, but they are constant offsets, not
4966 symbols. */
4972 {
4974 {
4980 }
4983 }
4986 }
4988 /* Implement REGNO_REG_CLASS. */
4990 enum reg_class
4992 {
5007 }
5009 static rtx
5011 {
5012 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5013 where mask is selected by alignment and size of the offset.
5014 We try to pick as large a range for the offset as possible to
5015 maximize the chance of a CSE. However, for aligned addresses
5016 we limit the range to 4k so that structures with different sized
5017 elements are likely to use the same base. We need to be careful
5018 not to split a CONST for some forms of address expression, otherwise
5019 it will generate sub-optimal code. */
5022 {
5028 {
5032 /* Force any scaling into a temp for CSE. */
5036 /* Let the pointer register be in op0. */
5040 /* If the pointer is virtual or frame related, then we know that
5041 virtual register instantiation or register elimination is going
5042 to apply a second constant. We want the two constants folded
5043 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5045 {
5049 }
5051 /* Otherwise, in order to encourage CSE (and thence loop strength
5052 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5056 }
5058 /* Does it look like we'll need a load/store-pair operation? */
5059 HOST_WIDE_INT base_offset;
5064 /* For offsets aren't a multiple of the access size, the limit is
5065 -256...255. */
5068 else
5072 {
5076 }
5077 }
5080 }
5082 /* Return the reload icode required for a constant pool in mode. */
5083 static enum insn_code
5085 {
5087 {
5123 }
5126 }
5127 static reg_class_t
5129 reg_class_t rclass,
5130 machine_mode mode,
5132 {
5134 /* If we have to disable direct literal pool loads and stores because the
5135 function is too big, then we need a scratch register. */
5140 {
5143 }
5145 /* Without the TARGET_SIMD instructions we cannot move a Q register
5146 to a Q register directly. We need a scratch. */
5150 {
5156 }
5158 /* A TFmode or TImode memory access should be handled via an FP_REGS
5159 because AArch64 has richer addressing modes for LDR/STR instructions
5160 than LDP/STP instructions. */
5169 }
5171 static bool
5173 {
5174 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5175 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5178 {
5190 }
5191 else
5192 {
5193 /* If we decided that we didn't need a leaf frame pointer but then used
5194 LR in the function, then we'll want a frame pointer after all, so
5195 prevent this elimination to ensure a frame pointer is used. */
5197 && flag_omit_leaf_frame_pointer
5200 }
5203 }
5205 HOST_WIDE_INT
5207 {
5211 {
5218 }
5221 {
5225 }
5228 }
5230 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5231 previous frame. */
5233 rtx
5235 {
5239 }
5242 static void
5244 {
5246 {
5249 }
5250 else
5251 {
5254 }
5259 }
5261 static void
5263 {
5267 /* Don't need to copy the trailing D-words, we fill those in below. */
5279 /* XXX We should really define a "clear_cache" pattern and use
5280 gen_clear_cache(). */
5285 ptr_mode);
5286 }
5288 static unsigned char
5290 {
5292 {
5299 return
5311 }
5313 }
5315 static reg_class_t
5317 {
5322 {
5328 }
5330 /* If it's an integer immediate that MOVI can't handle, then
5331 FP_REGS is not an option, so we return NO_REGS instead. */
5336 /* Register eliminiation can result in a request for
5337 SP+constant->FP_REGS. We cannot support such operations which
5338 use SP as source and an FP_REG as destination, so reject out
5339 right now. */
5341 {
5344 /* Look through a possible SUBREG introduced by ILP32. */
5350 POINTER_REGS));
5352 }
5355 }
5357 void
5359 {
5361 }
5363 static void
5365 {
5368 else
5369 {
5377 }
5378 }
5380 static void
5382 {
5385 else
5386 {
5394 }
5395 }
5399 {
5405 {
5406 {
5409 },
5410 {
5413 },
5414 {
5417 },
5418 /* We assume that DImode is only generated when not optimizing and
5419 that we don't really need 64-bit address offsets. That would
5420 imply an object file with 8GB of code in a single function! */
5421 {
5424 }
5425 };
5433 /* Need to implement table size reduction, by chaning the code below. */
5443 }
5446 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5447 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5448 operator. */
5450 int
5452 {
5454 {
5457 {
5461 }
5462 }
5464 }
5466 /* Constant pools are per function only when PC relative
5467 literal loads are true or we are in the large memory
5468 model. */
5472 {
5475 }
5477 static bool
5479 {
5480 /* Fixme:: In an ideal world this would work similar
5481 to the logic in aarch64_select_rtx_section but this
5482 breaks bootstrap in gcc go. For now we workaround
5483 this by returning false here. */
5485 }
5487 /* Select appropriate section for constants depending
5488 on where we place literal pools. */
5492 rtx x,
5494 {
5499 }
5501 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5502 void
5504 HOST_WIDE_INT offset)
5505 {
5506 /* When using per-function literal pools, we must ensure that any code
5507 section is aligned to the minimal instruction length, lest we get
5508 errors from the assembler re "unaligned instructions". */
5511 }
5513 /* Costs. */
5515 /* Helper function for rtx cost calculation. Strip a shift expression
5516 from X. Returns the inner operand if successful, or the original
5517 expression on failure. */
5518 static rtx
5520 {
5523 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5524 we can convert both to ROR during final output. */
5539 }
5541 /* Helper function for rtx cost calculation. Strip an extend
5542 expression from X. Returns the inner operand if successful, or the
5543 original expression on failure. We deal with a number of possible
5544 canonicalization variations here. */
5545 static rtx
5547 {
5550 /* Zero and sign extraction of a widened value. */
5558 /* It can also be represented (for zero-extend) as an AND with an
5559 immediate. */
5568 /* Now handle extended register, as this may also have an optional
5569 left shift by 1..4. */
5583 }
5585 /* Return true iff CODE is a shift supported in combination
5586 with arithmetic instructions. */
5588 static bool
5590 {
5592 }
5594 /* Helper function for rtx cost calculation. Calculate the cost of
5595 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5596 Return the calculated cost of the expression, recursing manually in to
5597 operands where needed. */
5599 static int
5601 {
5617 /* Integer multiply/fma. */
5619 {
5620 /* The multiply will be canonicalized as a shift, cost it as such. */
5624 {
5628 {
5630 {
5632 /* ARITH + shift-by-register. */
5635 /* ARITH + extended register. We don't have a cost field
5636 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5638 else
5639 /* ARITH + shift-by-immediate. */
5641 }
5642 else
5643 /* LSL (immediate). */
5646 }
5647 /* Strip extends as we will have costed them in the case above. */
5654 }
5656 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5657 compound and let the below cases handle it. After all, MNEG is a
5658 special-case alias of MSUB. */
5660 {
5663 }
5665 /* Integer multiplies or FMAs have zero/sign extending variants. */
5670 {
5675 {
5677 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5679 else
5680 /* MUL/SMULL/UMULL. */
5682 }
5685 }
5687 /* This is either an integer multiply or a MADD. In both cases
5688 we want to recurse and cost the operands. */
5693 {
5695 /* MADD/MSUB. */
5697 else
5698 /* MUL. */
5700 }
5703 }
5704 else
5705 {
5707 {
5708 /* Floating-point FMA/FMUL can also support negations of the
5709 operands, unless the rounding mode is upward or downward in
5710 which case FNMUL is different than FMUL with operand negation. */
5714 {
5719 }
5722 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5724 else
5725 /* FMUL/FNMUL. */
5727 }
5732 }
5733 }
5735 static int
5737 machine_mode mode,
5738 addr_space_t as ATTRIBUTE_UNUSED,
5740 {
5748 {
5750 {
5751 /* This is a CONST or SYMBOL ref which will be split
5752 in a different way depending on the code model in use.
5753 Cost it through the generic infrastructure. */
5755 /* Divide through by the cost of one instruction to
5756 bring it to the same units as the address costs. */
5758 /* The cost is then the cost of preparing the address,
5759 followed by an immediate (possibly 0) offset. */
5761 }
5762 else
5763 {
5764 /* This is most likely a jump table from a case
5765 statement. */
5767 }
5768 }
5771 {
5783 else
5802 }
5806 {
5807 /* For the sake of calculating the cost of the shifted register
5808 component, we can treat same sized modes in the same way. */
5810 {
5823 /* We can't tell, or this is a 128-bit vector. */
5827 }
5828 }
5831 }
5833 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5834 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5835 to be taken. */
5837 int
5839 {
5840 /* When optimizing for speed, use the cost of unpredictable branches. */
5846 else
5848 }
5850 /* Return true if the RTX X in mode MODE is a zero or sign extract
5851 usable in an ADD or SUB (extended register) instruction. */
5852 static bool
5854 {
5855 /* Catch add with a sign extract.
5856 This is add_<optab><mode>_multp2. */
5859 {
5870 op1))
5871 {
5873 }
5874 }
5875 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5876 No shift. */
5882 }
5884 static bool
5886 {
5888 {
5900 }
5901 }
5903 /* Return true iff X is an rtx that will match an extr instruction
5904 i.e. as described in the *extr<mode>5_insn family of patterns.
5905 OP0 and OP1 will be set to the operands of the shifts involved
5906 on success and will be NULL_RTX otherwise. */
5908 static bool
5910 {
5925 {
5926 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5938 {
5942 }
5943 }
5946 }
5948 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5949 storing it in *COST. Result is true if the total cost of the operation
5950 has now been calculated. */
5951 static bool
5953 {
5954 rtx inner;
5955 rtx comparator;
5959 {
5963 }
5964 else
5965 {
5969 }
5972 {
5973 /* Conditional branch. */
5976 else
5977 {
5979 {
5981 {
5982 /* TBZ/TBNZ/CBZ/CBNZ. */
5984 /* TBZ/TBNZ. */
5987 else
5988 /* CBZ/CBNZ. */
5992 }
5993 }
5995 {
5996 /* TBZ/TBNZ. */
5999 }
6000 }
6001 }
6003 {
6004 /* CCMP. */
6006 {
6007 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6011 {
6018 else
6020 }
6022 }
6024 /* It's a conditional operation based on the status flags,
6025 so it must be some flavor of CSEL. */
6027 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6033 {
6034 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6037 }
6042 }
6044 /* We don't know what this is, cost all operands. */
6046 }
6048 /* Check whether X is a bitfield operation of the form shift + extend that
6049 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6050 operand to which the bitfield operation is applied. Otherwise return
6051 NULL_RTX. */
6053 static rtx
6055 {
6069 {
6087 }
6090 }
6092 /* Return true if the mask and a shift amount from an RTX of the form
6093 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6094 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6096 bool
6098 {
6103 }
6105 /* Calculate the cost of calculating X, storing it in *COST. Result
6106 is true if the total cost of the operation has now been calculated. */
6107 static bool
6110 {
6116 /* By default, assume that everything has equivalent cost to the
6117 cheapest instruction. Any additional costs are applied as a delta
6118 above this default. */
6122 {
6124 /* The cost depends entirely on the operands to SET. */
6130 {
6133 {
6147 }
6156 /* Fall through. */
6158 /* The cost is one per vector-register copied. */
6160 {
6164 }
6165 /* const0_rtx is in general free, but we will use an
6166 instruction to set a register to 0. */
6168 {
6169 /* The cost is 1 per register copied. */
6173 }
6174 else
6175 /* Cost is just the cost of the RHS of the set. */
6181 /* Bit-field insertion. Strip any redundant widening of
6182 the RHS to meet the width of the target. */
6193 {
6194 /* MOV immediate is assumed to always be cheap. */
6196 }
6197 else
6198 {
6199 /* BFM. */
6203 }
6208 /* We can't make sense of this, assume default cost. */
6211 }
6215 /* If an instruction can incorporate a constant within the
6216 instruction, the instruction's expression avoids calling
6217 rtx_cost() on the constant. If rtx_cost() is called on a
6218 constant, then it is usually because the constant must be
6219 moved into a register by one or more instructions.
6221 The exception is constant 0, which can be expressed
6222 as XZR/WZR and is therefore free. The exception to this is
6223 if we have (set (reg) (const0_rtx)) in which case we must cost
6224 the move. However, we can catch that when we cost the SET, so
6225 we don't need to consider that here. */
6228 else
6229 {
6230 /* To an approximation, building any other constant is
6231 proportionally expensive to the number of instructions
6232 required to build that constant. This is true whether we
6233 are compiling for SPEED or otherwise. */
6236 }
6241 {
6242 /* mov[df,sf]_aarch64. */
6244 /* FMOV (scalar immediate). */
6247 {
6248 /* This will be a load from memory. */
6251 else
6253 }
6254 else
6255 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6256 or MOV v0.s[0], wzr - neither of which are modeled by the
6257 cost tables. Just use the default cost. */
6258 {
6259 }
6260 }
6266 {
6267 /* For loads we want the base cost of a load, plus an
6268 approximation for the additional cost of the addressing
6269 mode. */
6283 }
6291 {
6293 {
6294 /* FNEG. */
6296 }
6298 }
6301 {
6304 {
6305 /* CSETM. */
6308 }
6310 /* Cost this as SUB wzr, X. */
6314 }
6317 {
6318 /* Support (neg(fma...)) as a single instruction only if
6319 sign of zeros is unimportant. This matches the decision
6320 making in aarch64.md. */
6322 {
6323 /* FNMADD. */
6326 }
6328 {
6329 /* FNMUL. */
6332 }
6334 /* FNEG. */
6337 }
6344 {
6347 else
6349 }
6359 {
6363 }
6366 {
6367 /* TODO: A write to the CC flags possibly costs extra, this
6368 needs encoding in the cost tables. */
6371 /* ANDS. */
6373 {
6376 }
6379 {
6380 /* ADDS (and CMN alias). */
6383 }
6386 {
6387 /* SUBS. */
6390 }
6395 {
6396 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6397 Handle it here directly rather than going to cost_logic
6398 since we know the immediate generated for the TST is valid
6399 so we can avoid creating an intermediate rtx for it only
6400 for costing purposes. */
6407 }
6410 {
6411 /* CMN. */
6418 }
6420 /* CMP.
6422 Compare can freely swap the order of operands, and
6423 canonicalization puts the more complex operation first.
6424 But the integer MINUS logic expects the shift/extend
6425 operation in op1. */
6428 {
6431 }
6433 }
6436 {
6437 /* FCMP. */
6442 {
6444 /* FCMP supports constant 0.0 for no extra cost. */
6446 }
6448 }
6451 {
6452 /* Vector compare. */
6457 {
6458 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6459 cost. */
6461 }
6463 }
6467 {
6471 cost_minus:
6474 /* Detect valid immediates. */
6480 {
6482 /* SUB(S) (immediate). */
6485 }
6487 /* Look for SUB (extended register). */
6489 {
6497 }
6501 /* Cost this as an FMA-alike operation. */
6505 {
6508 speed);
6510 }
6515 {
6517 {
6518 /* Vector SUB. */
6520 }
6522 {
6523 /* SUB(S). */
6525 }
6527 {
6528 /* FSUB. */
6530 }
6531 }
6533 }
6536 {
6537 rtx new_op0;
6542 cost_plus:
6545 {
6546 /* CSINC. */
6550 }
6555 {
6559 /* ADD (immediate). */
6562 }
6566 /* Look for ADD (extended register). */
6568 {
6576 }
6578 /* Strip any extend, leave shifts behind as we will
6579 cost them through mult_cost. */
6584 {
6586 speed);
6588 }
6593 {
6595 {
6596 /* Vector ADD. */
6598 }
6600 {
6601 /* ADD. */
6603 }
6605 {
6606 /* FADD. */
6608 }
6609 }
6611 }
6617 {
6620 else
6622 }
6627 {
6631 {
6634 else
6636 }
6638 }
6641 {
6648 }
6649 /* Fall through. */
6652 cost_logic:
6657 {
6661 }
6669 {
6670 /* This is a UBFM/SBFM. */
6675 }
6678 {
6680 {
6681 /* We have a mask + shift version of a UBFIZ
6682 i.e. the *andim_ashift<mode>_bfiz pattern. */
6686 {
6693 }
6695 {
6696 /* We possibly get the immediate for free, this is not
6697 modelled. */
6703 }
6704 }
6705 else
6706 {
6709 /* Handle ORN, EON, or BIC. */
6715 /* If we had a shift on op0 then this is a logical-shift-
6716 by-register/immediate operation. Otherwise, this is just
6717 a logical operation. */
6719 {
6721 {
6722 /* Shift by immediate. */
6725 else
6727 }
6728 else
6730 }
6732 /* In both cases we want to cost both operands. */
6737 }
6738 }
6746 {
6747 /* Vector NOT. */
6750 }
6752 /* MVN-shifted-reg. */
6754 {
6761 }
6762 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6763 Handle the second form here taking care that 'a' in the above can
6764 be a shift. */
6766 {
6775 {
6778 else
6780 }
6783 }
6784 /* MVN. */
6793 /* If a value is written in SI mode, then zero extended to DI
6794 mode, the operation will in general be free as a write to
6795 a 'w' register implicitly zeroes the upper bits of an 'x'
6796 register. However, if this is
6798 (set (reg) (zero_extend (reg)))
6800 we must cost the explicit register move. */
6804 {
6807 /* If OP_COST is non-zero, then the cost of the zero extend
6808 is effectively the cost of the inner operation. Otherwise
6809 we have a MOV instruction and we take the cost from the MOV
6810 itself. This is true independently of whether we are
6811 optimizing for space or time. */
6816 }
6818 {
6819 /* All loads can zero extend to any size for free. */
6822 }
6826 {
6831 }
6834 {
6836 {
6837 /* UMOV. */
6839 }
6840 else
6841 {
6842 /* We generate an AND instead of UXTB/UXTH. */
6844 }
6845 }
6850 {
6851 /* LDRSH. */
6853 {
6860 }
6862 }
6866 {
6871 }
6874 {
6877 else
6879 }
6887 {
6889 {
6891 {
6892 /* Vector shift (immediate). */
6894 }
6895 else
6896 {
6897 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6898 aliases. */
6900 }
6901 }
6903 /* We can incorporate zero/sign extend for free. */
6910 }
6911 else
6912 {
6914 {
6916 {
6917 /* Vector shift (register). */
6919 }
6920 else
6921 {
6922 /* LSLV. */
6924 }
6925 }
6927 }
6937 {
6938 /* ASR (immediate) and friends. */
6940 {
6943 else
6945 }
6949 }
6950 else
6951 {
6953 /* ASR (register) and friends. */
6955 {
6958 else
6960 }
6962 }
6968 {
6969 /* LDR. */
6972 }
6975 {
6976 /* ADRP, followed by ADD. */
6980 }
6983 {
6984 /* ADR. */
6987 }
6990 {
6991 /* One extra load instruction, after accessing the GOT. */
6995 }
7000 /* ADRP/ADD (immediate). */
7007 /* UBFX/SBFX. */
7009 {
7012 else
7014 }
7016 /* We can trust that the immediates used will be correct (there
7017 are no by-register forms), so we need only cost op0. */
7023 /* aarch64_rtx_mult_cost always handles recursion to its
7024 operands. */
7028 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7029 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7030 an unconditional negate. This case should only ever be reached through
7031 the set_smod_pow2_cheap check in expmed.c. */
7035 {
7036 /* We expand to 4 instructions. Reset the baseline. */
7044 }
7046 /* Fall-through. */
7049 {
7061 }
7068 {
7072 /* There is no integer SQRT, so only DIV and UDIV can get
7073 here. */
7075 else
7077 }
7103 {
7106 else
7108 }
7110 /* FMSUB, FNMADD, and FNMSUB are free. */
7117 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7118 and the by-element operand as operand 0. */
7122 /* Catch vector-by-element operations. The by-element operand can
7123 either be (vec_duplicate (vec_select (x))) or just
7124 (vec_select (x)), depending on whether we are multiplying by
7125 a vector or a scalar.
7127 Canonicalization is not very good in these cases, FMA4 will put the
7128 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7139 /* If the remaining parameters are not registers,
7140 get the cost to put them into registers. */
7154 {
7156 {
7157 /*Vector truncate. */
7159 }
7160 else
7162 }
7167 {
7169 {
7170 /*Vector conversion. */
7172 }
7173 else
7175 }
7181 /* Strip the rounding part. They will all be implemented
7182 by the fcvt* family of instructions anyway. */
7184 {
7193 }
7196 {
7199 else
7201 }
7203 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7204 fixed-point fcvt. */
7209 {
7213 }
7220 {
7221 /* ABS (vector). */
7224 }
7226 {
7229 /* FABD, which is analogous to FADD. */
7231 {
7238 }
7239 /* Simple FABS is analogous to FNEG. */
7242 }
7243 else
7244 {
7245 /* Integer ABS will either be split to
7246 two arithmetic instructions, or will be an ABS
7247 (scalar), which we don't model. */
7251 }
7257 {
7260 else
7261 {
7262 /* FMAXNM/FMINNM/FMAX/FMIN.
7263 TODO: This may not be accurate for all implementations, but
7264 we do not model this in the cost tables. */
7266 }
7267 }
7271 /* The floating point round to integer frint* instructions. */
7273 {
7278 }
7281 {
7286 }
7291 /* Decompose <su>muldi3_highpart. */
7293 mode == DImode
7294 /* (lshiftrt:TI */
7297 /* (mult:TI */
7299 /* (ANY_EXTEND:TI (reg:DI))
7300 (ANY_EXTEND:TI (reg:DI))) */
7307 /* (const_int 64) */
7310 {
7311 /* UMULH/SMULH. */
7319 }
7321 /* Fall through. */
7324 }
7331 }
7333 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7334 calculated for X. This cost is stored in *COST. Returns true
7335 if the total cost of X was calculated. */
7336 static bool
7339 {
7343 {
7348 }
7351 }
7353 static int
7356 {
7362 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7369 /* Moving between GPR and stack cost is the same as GP2GP. */
7374 /* To/From the stack register, we move via the gprs. */
7380 {
7381 /* 128-bit operations on general registers require 2 instructions. */
7389 /* When AdvSIMD instructions are disabled it is not possible to move
7390 a 128-bit value directly between Q registers. This is handled in
7391 secondary reload. A general register is used as a scratch to move
7392 the upper DI value and the lower DI value is moved directly,
7393 hence the cost is the sum of three moves. */
7398 }
7408 }
7410 static int
7412 reg_class_t rclass ATTRIBUTE_UNUSED,
7414 {
7416 }
7418 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7419 to optimize 1.0/sqrt. */
7421 static bool
7423 {
7425 && flag_unsafe_math_optimizations
7429 }
7431 /* Function to decide when to use the approximate reciprocal square root
7432 builtin. */
7434 static tree
7436 {
7442 }
7446 /* Select reciprocal square root initial estimate insn depending on machine
7447 mode. */
7449 static rsqrte_type
7451 {
7453 {
7460 }
7461 }
7465 /* Select reciprocal square root series step insn depending on machine mode. */
7467 static rsqrts_type
7469 {
7471 {
7478 }
7479 }
7481 /* Emit instruction sequence to compute either the approximate square root
7482 or its approximate reciprocal, depending on the flag RECP, and return
7483 whether the sequence was emitted or not. */
7485 bool
7487 {
7493 machine_mode mmsk = mode_for_vector
7497 && (flag_mlow_precision_sqrt
7501 && (flag_mrecip_low_precision_sqrt
7506 || flag_trapping_math
7507 || !flag_unsafe_math_optimizations
7514 /* When calculating the approximate square root, compare the argument with
7515 0.0 and create a mask. */
7519 /* Estimate the approximate reciprocal square root. */
7523 /* Iterate over the series twice for SF and thrice for DF. */
7526 /* Optionally iterate over the series once less for faster performance
7527 while sacrificing the accuracy. */
7530 iterations--;
7532 /* Iterate over the series to calculate the approximate reciprocal square
7533 root. */
7536 {
7544 }
7547 {
7548 /* Qualify the approximate reciprocal square root when the argument is
7549 0.0 by squashing the intermediary result to 0.0. */
7555 /* Calculate the approximate square root. */
7557 }
7559 /* Finalize the approximation. */
7563 }
7567 /* Select reciprocal initial estimate insn depending on machine mode. */
7569 static recpe_type
7571 {
7573 {
7580 }
7581 }
7585 /* Select reciprocal series step insn depending on machine mode. */
7587 static recps_type
7589 {
7591 {
7598 }
7599 }
7601 /* Emit the instruction sequence to compute the approximation for the division
7602 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
7604 bool
7606 {
7617 || flag_trapping_math
7618 || !flag_unsafe_math_optimizations
7623 /* Estimate the approximate reciprocal. */
7627 /* Iterate over the series twice for SF and thrice for DF. */
7630 /* Optionally iterate over the series once less for faster performance,
7631 while sacrificing the accuracy. */
7633 iterations--;
7635 /* Iterate over the series to calculate the approximate reciprocal. */
7638 {
7643 }
7646 {
7647 /* As the approximate reciprocal of DEN is already calculated, only
7648 calculate the approximate division when NUM is not 1.0. */
7651 }
7653 /* Finalize the approximation. */
7656 }
7658 /* Return the number of instructions that can be issued per cycle. */
7659 static int
7661 {
7663 }
7665 static int
7667 {
7671 }
7674 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7675 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7676 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7678 static int
7681 {
7683 }
7686 /* Vectorizer cost model target hooks. */
7688 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7689 static int
7691 tree vectype,
7693 {
7697 {
7746 }
7747 }
7749 /* Implement targetm.vectorize.add_stmt_cost. */
7750 static unsigned
7754 {
7759 {
7764 /* Statements in an inner loop relative to the loop being
7765 vectorized are weighted more heavily. The value here is
7766 arbitrary and could potentially be improved with analysis. */
7772 }
7775 }
7779 /* Parse the TO_PARSE string and put the architecture struct that it
7780 selects into RES and the architectural features into ISA_FLAGS.
7781 Return an aarch64_parse_opt_result describing the parse result.
7782 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7784 static enum aarch64_parse_opt_result
7787 {
7799 else
7806 /* Loop through the list of supported ARCHes to find a match. */
7808 {
7810 {
7814 {
7815 /* TO_PARSE string contains at least one extension. */
7816 enum aarch64_parse_opt_result ext_res
7821 }
7822 /* Extension parsing was successful. Confirm the result
7823 arch and ISA flags. */
7827 }
7828 }
7830 /* ARCH name not found in list. */
7832 }
7834 /* Parse the TO_PARSE string and put the result tuning in RES and the
7835 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7836 describing the parse result. If there is an error parsing, RES and
7837 ISA_FLAGS are left unchanged. */
7839 static enum aarch64_parse_opt_result
7842 {
7854 else
7861 /* Loop through the list of supported CPUs to find a match. */
7863 {
7865 {
7870 {
7871 /* TO_PARSE string contains at least one extension. */
7872 enum aarch64_parse_opt_result ext_res
7877 }
7878 /* Extension parsing was successfull. Confirm the result
7879 cpu and ISA flags. */
7883 }
7884 }
7886 /* CPU name not found in list. */
7888 }
7890 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7891 Return an aarch64_parse_opt_result describing the parse result.
7892 If the parsing fails the RES does not change. */
7894 static enum aarch64_parse_opt_result
7896 {
7902 /* Loop through the list of supported CPUs to find a match. */
7904 {
7906 {
7909 }
7910 }
7912 /* CPU name not found in list. */
7914 }
7916 /* Parse TOKEN, which has length LENGTH to see if it is an option
7917 described in FLAG. If it is, return the index bit for that fusion type.
7918 If not, error (printing OPTION_NAME) and return zero. */
7920 static unsigned int
7925 {
7927 {
7931 }
7935 }
7937 /* Parse OPTION which is a comma-separated list of flags to enable.
7938 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7939 default state we inherit from the CPU tuning structures. OPTION_NAME
7940 gives the top-level option we are parsing in the -moverride string,
7941 for use in error messages. */
7943 static unsigned int
7948 {
7955 {
7958 token_length,
7959 flags,
7960 option_name);
7961 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7962 in the token stream, reset the supported operations. So:
7964 adrp+add.cmp+branch.none.adrp+add
7966 would have the result of turning on only adrp+add fusion. */
7972 }
7974 /* We ended with a comma, print something. */
7976 {
7979 }
7981 /* We still have one more token to parse. */
7984 token_length,
7985 flags,
7986 option_name);
7992 }
7994 /* Support for overriding instruction fusion. */
7996 static void
7999 {
8001 aarch64_fusible_pairs,
8004 }
8006 /* Support for overriding other tuning flags. */
8008 static void
8011 {
8012 tune->extra_tuning_flags
8014 aarch64_tuning_flags,
8017 }
8019 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8020 we understand. If it is, extract the option string and handoff to
8021 the appropriate function. */
8023 void
8027 {
8033 {
8036 }
8038 /* Get the length of the option name. */
8040 /* Skip the '=' to get to the option string. */
8041 option_part++;
8044 {
8046 {
8049 }
8050 }
8054 }
8056 /* A checking mechanism for the implementation of the tls size. */
8058 static void
8060 {
8065 {
8067 /* Both the default and maximum TLS size allowed under tiny is 1M which
8068 needs two instructions to address, so we clamp the size to 24. */
8073 /* The maximum TLS size allowed under small is 4G. */
8078 /* The maximum TLS size allowed under large is 16E.
8079 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8085 }
8088 }
8090 /* Parse STRING looking for options in the format:
8091 string :: option:string
8092 option :: name=substring
8093 name :: {a-z}
8094 substring :: defined by option. */
8096 static void
8099 {
8110 {
8112 /* Make this substring look like a string. */
8116 }
8118 /* One last option to parse. */
8121 }
8124 static void
8126 {
8127 /* The logic here is that if we are disabling all frame pointer generation
8128 then we do not need to disable leaf frame pointer generation as a
8129 separate operation. But if we are *only* disabling leaf frame pointer
8130 generation then we set flag_omit_frame_pointer to true, but in
8131 aarch64_frame_pointer_required we return false only for leaf functions.
8133 PR 70044: We have to be careful about being called multiple times for the
8134 same function. Once we have decided to set flag_omit_frame_pointer just
8135 so that we can omit leaf frame pointers, we must then not interpret a
8136 second call as meaning that all frame pointer generation should be
8137 omitted. We do this by setting flag_omit_frame_pointer to a special,
8138 non-zero value. */
8147 /* If not optimizing for size, set the default
8148 alignment to what the target wants. */
8150 {
8157 }
8159 /* We default to no pc-relative literal loads. */
8163 /* If -mpc-relative-literal-loads is set on the command line, this
8164 implies that the user asked for PC relative literal loads. */
8168 /* This is PR70113. When building the Linux kernel with
8169 CONFIG_ARM64_ERRATUM_843419, support for relocations
8170 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8171 removed from the kernel to avoid loading objects with possibly
8172 offending sequences. Without -mpc-relative-literal-loads we would
8173 generate such relocations, preventing the kernel build from
8174 succeeding. */
8179 /* In the tiny memory model it makes no sense to disallow PC relative
8180 literal pool loads. */
8185 /* When enabling the lower precision Newton series for the square root, also
8186 enable it for the reciprocal square root, since the latter is an
8187 intermediary step for the former. */
8190 }
8192 /* 'Unpack' up the internal tuning structs and update the options
8193 in OPTS. The caller must have set up selected_tune and selected_arch
8194 as all the other target-specific codegen decisions are
8195 derived from them. */
8197 void
8199 {
8202 /* Make a copy of the tuning parameters attached to the core, which
8203 we may later overwrite. */
8211 /* This target defaults to strict volatile bitfields. */
8220 {
8232 }
8234 /* We don't mind passing in global_options_set here as we don't use
8235 the *options_set structs anyway. */
8237 queue_depth,
8241 /* Set the L1 cache line size. */
8249 }
8251 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8252 specified in STR and throw errors if appropriate. Put the results if
8253 they are valid in RES and ISA_FLAGS. Return whether the option is
8254 valid. */
8256 static bool
8259 {
8260 enum aarch64_parse_opt_result parse_res
8267 {
8279 }
8282 }
8284 /* Validate a command-line -march option. Parse the arch and extensions
8285 (if any) specified in STR and throw errors if appropriate. Put the
8286 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8287 option is valid. */
8289 static bool
8292 {
8293 enum aarch64_parse_opt_result parse_res
8300 {
8312 }
8315 }
8317 /* Validate a command-line -mtune option. Parse the cpu
8318 specified in STR and throw errors if appropriate. Put the
8319 result, if it is valid, in RES. Return whether the option is
8320 valid. */
8322 static bool
8324 {
8325 enum aarch64_parse_opt_result parse_res
8332 {
8341 }
8343 }
8345 /* Return the CPU corresponding to the enum CPU.
8346 If it doesn't specify a cpu, return the default. */
8350 {
8354 /* The & 0x3f is to extract the bottom 6 bits that encode the
8355 default cpu as selected by the --with-cpu GCC configure option
8356 in config.gcc.
8357 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8358 flags mechanism should be reworked to make it more sane. */
8360 }
8362 /* Return the architecture corresponding to the enum ARCH.
8363 If it doesn't specify a valid architecture, return the default. */
8367 {
8374 }
8376 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8377 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8378 tuning structs. In particular it must set selected_tune and
8379 aarch64_isa_flags that define the available ISA features and tuning
8380 decisions. It must also set selected_arch as this will be used to
8381 output the .arch asm tags for each function. */
8383 static void
8385 {
8398 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8399 If either of -march or -mtune is given, they override their
8400 respective component of -mcpu. */
8412 /* If the user did not specify a processor, choose the default
8413 one for them. This will be the CPU set during configuration using
8414 --with-cpu, otherwise it is "generic". */
8416 {
8418 {
8422 }
8423 else
8424 {
8425 /* Get default configure-time CPU. */
8428 }
8432 }
8433 /* If both -mcpu and -march are specified check that they are architecturally
8434 compatible, warn if they're not and prefer the -march ISA flags. */
8436 {
8438 {
8442 }
8447 }
8448 else
8449 {
8450 /* -mcpu but no -march. */
8457 }
8459 /* Set the arch as well as we will need it when outputing
8460 the .arch directive in assembly. */
8462 {
8465 }
8470 #ifndef HAVE_AS_MABI_OPTION
8471 /* The compiler may have been configured with 2.23.* binutils, which does
8472 not have support for ILP32. */
8475 #endif
8477 /* Make sure we properly set up the explicit options. */
8488 /* Save these options as the default ones in case we push and pop them later
8489 while processing functions with potential target attributes. */
8490 target_option_default_node = target_option_current_node
8495 }
8497 /* Implement targetm.override_options_after_change. */
8499 static void
8501 {
8503 }
8507 {
8511 }
8513 void
8515 {
8517 }
8519 /* A checking mechanism for the implementation of the various code models. */
8520 static void
8522 {
8524 {
8526 {
8531 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8533 ? AARCH64_CMODEL_SMALL_PIC
8535 #else
8537 #endif
8545 }
8546 }
8547 else
8549 }
8551 /* Implement TARGET_OPTION_SAVE. */
8553 static void
8555 {
8557 }
8559 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8560 using the information saved in PTR. */
8562 static void
8564 {
8572 }
8574 /* Implement TARGET_OPTION_PRINT. */
8576 static void
8578 {
8589 }
8593 void
8595 {
8597 }
8599 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
8600 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
8601 make sure optab availability predicates are recomputed when necessary. */
8603 void
8605 {
8610 else
8612 }
8614 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8615 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8616 of the function, if such exists. This function may be called multiple
8617 times on a single function so use aarch64_previous_fndecl to avoid
8618 setting up identical state. */
8620 static void
8622 {
8626 tree old_tree = (aarch64_previous_fndecl
8632 /* If current function has no attributes but the previous one did,
8633 use the default node. */
8637 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
8638 the default have been handled by aarch64_save_restore_target_globals from
8639 aarch64_pragma_target_parse. */
8645 /* First set the target options. */
8649 }
8651 /* Enum describing the various ways we can handle attributes.
8652 In many cases we can reuse the generic option handling machinery. */
8654 enum aarch64_attr_opt_type
8655 {
8659 aarch64_attr_custom /* Attribute requires a custom handling function. */
8660 };
8662 /* All the information needed to handle a target attribute.
8663 NAME is the name of the attribute.
8664 ATTR_TYPE specifies the type of behavior of the attribute as described
8665 in the definition of enum aarch64_attr_opt_type.
8666 ALLOW_NEG is true if the attribute supports a "no-" form.
8667 HANDLER is the function that takes the attribute string and whether
8668 it is a pragma or attribute and handles the option. It is needed only
8669 when the ATTR_TYPE is aarch64_attr_custom.
8670 OPT_NUM is the enum specifying the option that the attribute modifies.
8671 This is needed for attributes that mirror the behavior of a command-line
8672 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8673 aarch64_attr_enum. */
8675 struct aarch64_attribute_info
8676 {
8682 };
8684 /* Handle the ARCH_STR argument to the arch= target attribute.
8685 PRAGMA_OR_ATTR is used in potential error messages. */
8687 static bool
8689 {
8691 enum aarch64_parse_opt_result parse_res
8695 {
8700 }
8703 {
8716 }
8719 }
8721 /* Handle the argument CPU_STR to the cpu= target attribute.
8722 PRAGMA_OR_ATTR is used in potential error messages. */
8724 static bool
8726 {
8728 enum aarch64_parse_opt_result parse_res
8732 {
8740 }
8743 {
8756 }
8759 }
8761 /* Handle the argument STR to the tune= target attribute.
8762 PRAGMA_OR_ATTR is used in potential error messages. */
8764 static bool
8766 {
8768 enum aarch64_parse_opt_result parse_res
8772 {
8777 }
8780 {
8786 }
8789 }
8791 /* Parse an architecture extensions target attribute string specified in STR.
8792 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8793 if successful. Update aarch64_isa_flags to reflect the ISA features
8794 modified.
8795 PRAGMA_OR_ATTR is used in potential error messages. */
8797 static bool
8799 {
8803 /* We allow "+nothing" in the beginning to clear out all architectural
8804 features if the user wants to handpick specific features. */
8806 {
8809 }
8814 {
8817 }
8820 {
8833 }
8836 }
8838 /* The target attributes that we support. On top of these we also support just
8839 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8840 handled explicitly in aarch64_process_one_target_attr. */
8843 {
8845 OPT_mgeneral_regs_only },
8847 OPT_mfix_cortex_a53_835769 },
8849 OPT_mfix_cortex_a53_843419 },
8853 OPT_momit_leaf_frame_pointer },
8856 OPT_march_ },
8859 OPT_mtune_ },
8861 };
8863 /* Parse ARG_STR which contains the definition of one target attribute.
8864 Show appropriate errors if any or return true if the attribute is valid.
8865 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8866 we're processing a target attribute or pragma. */
8868 static bool
8870 {
8876 {
8879 }
8884 /* Skip leading whitespace. */
8886 str_to_check++;
8888 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8889 It is easier to detect and handle it explicitly here rather than going
8890 through the machinery for the rest of the target attributes in this
8891 function. */
8896 {
8899 }
8902 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8903 and point ARG to "foo". */
8905 {
8907 arg++;
8908 }
8912 {
8913 /* If the names don't match up, or the user has given an argument
8914 to an attribute that doesn't accept one, or didn't give an argument
8915 to an attribute that expects one, fail to match. */
8924 {
8928 }
8930 /* If the name matches but the attribute does not allow "no-" versions
8931 then we can't match. */
8933 {
8937 }
8940 {
8941 /* Has a custom handler registered.
8942 For example, cpu=, arch=, tune=. */
8949 /* Either set or unset a boolean option. */
8951 {
8959 }
8960 /* Set or unset a bit in the target_flags. aarch64_handle_option
8961 should know what mask to apply given the option number. */
8963 {
8965 /* We only need to specify the option number.
8966 aarch64_handle_option will know which mask to apply. */
8972 }
8973 /* Use the option setting machinery to set an option to an enum. */
8975 {
8982 {
8985 global_dc);
8986 }
8987 else
8988 {
8991 }
8993 }
8996 }
8997 }
8999 /* If we reached here we either have found an attribute and validated
9000 it or didn't match any. If we matched an attribute but its arguments
9001 were malformed we will have returned false already. */
9003 }
9005 /* Count how many times the character C appears in
9006 NULL-terminated string STR. */
9008 static unsigned int
9010 {
9013 {
9015 res++;
9017 str++;
9018 }
9021 }
9023 /* Parse the tree in ARGS that contains the target attribute information
9024 and update the global target options space. PRAGMA_OR_ATTR is a string
9025 to be used in error messages, specifying whether this is processing
9026 a target attribute or a target pragma. */
9028 bool
9030 {
9032 {
9033 do
9034 {
9037 {
9040 }
9045 }
9046 /* We expect to find a string to parse. */
9054 {
9057 }
9059 /* Used to catch empty spaces between commas i.e.
9060 attribute ((target ("attr1,,attr2"))). */
9063 /* Handle multiple target attributes separated by ','. */
9068 {
9069 num_attrs++;
9071 {
9074 }
9077 }
9080 {
9084 }
9087 }
9089 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9090 process attribute ((target ("..."))). */
9092 static bool
9094 {
9097 tree old_optimize;
9101 /* If what we're processing is the current pragma string then the
9102 target option node is already stored in target_option_current_node
9103 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9104 having to re-parse the string. This is especially useful to keep
9105 arm_neon.h compile times down since that header contains a lot
9106 of intrinsics enclosed in pragmas. */
9108 {
9111 }
9117 /* If the function changed the optimization levels as well as setting
9118 target options, start with the optimizations specified. */
9123 /* Save the current target options to restore at the end. */
9126 /* If fndecl already has some target attributes applied to it, unpack
9127 them so that we add this attribute on top of them, rather than
9128 overwriting them. */
9130 {
9136 }
9137 else
9144 /* Set up any additional state. */
9146 {
9148 /* Initialize SIMD builtins if we haven't already.
9149 Set current_target_pragma to NULL for the duration so that
9150 the builtin initialization code doesn't try to tag the functions
9151 being built with the attributes specified by any current pragma, thus
9152 going into an infinite recursion. */
9154 {
9159 }
9161 }
9162 else
9168 {
9173 }
9181 }
9183 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9184 tri-bool options (yes, no, don't care) and the default value is
9185 DEF, determine whether to reject inlining. */
9187 static bool
9190 {
9191 /* If the callee doesn't care, always allow inlining. */
9195 /* If the caller doesn't care, always allow inlining. */
9199 /* Otherwise, allow inlining if either the callee and caller values
9200 agree, or if the callee is using the default value. */
9202 }
9204 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9205 to inline CALLEE into CALLER based on target-specific info.
9206 Make sure that the caller and callee have compatible architectural
9207 features. Then go through the other possible target attributes
9208 and see if they can block inlining. Try not to reject always_inline
9209 callees unless they are incompatible architecturally. */
9211 static bool
9213 {
9217 /* If callee has no option attributes, then it is ok to inline. */
9228 /* Callee's ISA flags should be a subset of the caller's. */
9233 /* Allow non-strict aligned functions inlining into strict
9234 aligned ones. */
9244 /* If the architectural features match up and the callee is always_inline
9245 then the other attributes don't matter. */
9257 /* Honour explicit requests to workaround errata. */
9270 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9271 caller and calle and they don't match up, reject inlining. */
9278 /* If the callee has specific tuning overrides, respect them. */
9283 /* If the user specified tuning override strings for the
9284 caller and callee and they don't match up, reject inlining.
9285 We just do a string compare here, we don't analyze the meaning
9286 of the string, as it would be too costly for little gain. */
9294 }
9296 /* Return true if SYMBOL_REF X binds locally. */
9298 static bool
9300 {
9304 }
9306 /* Return true if SYMBOL_REF X is thread local */
9307 static bool
9309 {
9317 }
9319 /* Classify a TLS symbol into one of the TLS kinds. */
9320 enum aarch64_symbol_type
9322 {
9326 {
9333 {
9339 }
9350 else
9359 }
9360 }
9362 /* Return the method that should be used to access SYMBOL_REF or
9363 LABEL_REF X. */
9365 enum aarch64_symbol_type
9367 {
9369 {
9371 {
9386 }
9387 }
9390 {
9395 {
9397 /* When we retrieve symbol + offset address, we have to make sure
9398 the offset does not cause overflow of the final address. But
9399 we have no way of knowing the address of symbol at compile time
9400 so we can't accurately say if the distance between the PC and
9401 symbol + offset is outside the addressible range of +/-1M in the
9402 TINY code model. So we rely on images not being greater than
9403 1M and cap the offset at 1M and anything beyond 1M will have to
9404 be loaded using an alternative mechanism. Furthermore if the
9405 symbol is a weak reference to something that isn't known to
9406 resolve to a symbol in this module, then force to memory. */
9414 /* Same reasoning as the tiny code model, but the offset cap here is
9415 4G. */
9436 /* This is alright even in PIC code as the constant
9437 pool reference is always PC relative and within
9438 the same translation unit. */
9441 else
9446 }
9447 }
9449 /* By default push everything into the constant pool. */
9451 }
9453 bool
9455 {
9457 }
9459 bool
9461 {
9469 }
9471 /* Return true if X holds either a quarter-precision or
9472 floating-point +0.0 constant. */
9473 static bool
9475 {
9482 /* We only handle moving 0.0 to a TFmode register. */
9487 }
9489 static bool
9491 {
9492 /* Do not allow vector struct mode constants. We could support
9493 0 and -1 easily, but they need support in aarch64-simd.md. */
9497 /* This could probably go away because
9498 we now decompose CONST_INTs according to expand_mov_immediate. */
9509 }
9511 rtx
9513 {
9519 /* Can return in any reg. */
9522 }
9524 /* On AAPCS systems, this is the "struct __va_list". */
9527 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9528 Return the type to use as __builtin_va_list.
9530 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9532 struct __va_list
9533 {
9534 void *__stack;
9535 void *__gr_top;
9536 void *__vr_top;
9537 int __gr_offs;
9538 int __vr_offs;
9539 }; */
9541 static tree
9543 {
9544 tree va_list_name;
9547 /* Create the type. */
9549 /* Give it the required name. */
9551 TYPE_DECL,
9553 va_list_type);
9558 /* Create the fields. */
9561 ptr_type_node);
9564 ptr_type_node);
9567 ptr_type_node);
9570 integer_type_node);
9573 integer_type_node);
9575 /* Tell tree-stdarg pass about our internal offset fields.
9576 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9577 purpose to identify whether the code is updating va_list internal
9578 offset fields through irregular way. */
9600 /* Compute its layout. */
9604 }
9606 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9607 static void
9609 {
9613 tree t;
9627 {
9630 }
9639 NULL_TREE);
9641 NULL_TREE);
9643 NULL_TREE);
9645 NULL_TREE);
9647 NULL_TREE);
9649 /* Emit code to initialize STACK, which points to the next varargs stack
9650 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9651 by named arguments. STACK is 8-byte aligned. */
9658 /* Emit code to initialize GRTOP, the top of the GR save area.
9659 virtual_incoming_args_rtx should have been 16 byte aligned. */
9664 /* Emit code to initialize VRTOP, the top of the VR save area.
9665 This address is gr_save_area_bytes below GRTOP, rounded
9666 down to the next 16-byte boundary. */
9676 /* Emit code to initialize GROFF, the offset from GRTOP of the
9677 next GPR argument. */
9682 /* Likewise emit code to initialize VROFF, the offset from FTOP
9683 of the next VR argument. */
9687 }
9689 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9691 static tree
9694 {
9695 tree addr;
9701 machine_mode mode;
9728 type,
9732 {
9733 /* TYPE passed in fp/simd registers. */
9745 {
9748 }
9751 {
9753 }
9754 }
9755 else
9756 {
9757 /* TYPE passed in general registers. */
9770 {
9772 }
9773 }
9775 /* Get a local temporary for the field value. */
9778 /* Emit code to branch if off >= 0. */
9784 {
9785 /* Emit: offs = (offs + 15) & -16. */
9791 }
9792 else
9795 /* Update ap.__[g|v]r_offs */
9800 /* String up. */
9804 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9809 /* String up: make sure the assignment happens before the use. */
9813 /* Prepare the trees handling the argument that is passed on the stack;
9814 the top level node will store in ON_STACK. */
9817 {
9818 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9826 }
9827 else
9829 /* Advance ap.__stack */
9837 /* String up roundup and advance. */
9840 /* String up with arg */
9842 /* Big-endianness related address adjustment. */
9845 {
9849 }
9854 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9864 {
9865 /* type ha; // treat as "struct {ftype field[n];}"
9866 ... [computing offs]
9867 for (i = 0; i <nregs; ++i, offs += 16)
9868 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9869 return ha; */
9873 /* Declare a local variable. */
9877 /* Establish the base type. */
9879 {
9898 {
9902 }
9906 }
9908 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9916 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9918 {
9928 }
9932 }
9942 }
9944 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9946 static void
9950 {
9952 CUMULATIVE_ARGS local_cum;
9956 /* The caller has advanced CUM up to, but not beyond, the last named
9957 argument. Advance a local copy of CUM past the last "real" named
9958 argument, to find out how many registers are left over. */
9962 /* Found out how many registers we need to save.
9963 Honor tree-stdvar analysis results. */
9972 {
9975 }
9978 {
9980 {
9983 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9991 }
9993 {
9994 /* We can't use move_block_from_reg, because it will use
9995 the wrong mode, storing D regs only. */
9999 /* Set OFF to the offset from virtual_incoming_args_rtx of
10000 the first vector register. The VR save area lies below
10001 the GR one, and is aligned to 16 bytes. */
10008 {
10016 }
10017 }
10018 }
10020 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10021 any complication of having crtl->args.pretend_args_size changed. */
10026 }
10028 static void
10030 {
10033 {
10035 {
10038 }
10039 }
10040 }
10042 /* Walk down the type tree of TYPE counting consecutive base elements.
10043 If *MODEP is VOIDmode, then set it to the first valid floating point
10044 type. If a non-floating point type is found, or if a floating point
10045 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10046 otherwise return the count in the sub-tree. */
10047 static int
10049 {
10050 machine_mode mode;
10051 HOST_WIDE_INT size;
10054 {
10084 /* Use V2SImode and V4SImode as representatives of all 64-bit
10085 and 128-bit vector types. */
10088 {
10097 }
10102 /* Vector modes are considered to be opaque: two vectors are
10103 equivalent for the purposes of being homogeneous aggregates
10104 if they are the same size. */
10111 {
10115 /* Can't handle incomplete types nor sizes that are not
10116 fixed. */
10123 || !index
10134 /* There must be no padding. */
10139 }
10142 {
10145 tree field;
10147 /* Can't handle incomplete types nor sizes that are not
10148 fixed. */
10154 {
10162 }
10164 /* There must be no padding. */
10169 }
10173 {
10174 /* These aren't very interesting except in a degenerate case. */
10177 tree field;
10179 /* Can't handle incomplete types nor sizes that are not
10180 fixed. */
10186 {
10194 }
10196 /* There must be no padding. */
10201 }
10205 }
10208 }
10210 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10211 type as described in AAPCS64 \S 4.1.2.
10213 See the comment above aarch64_composite_type_p for the notes on MODE. */
10215 static bool
10217 machine_mode mode)
10218 {
10228 }
10230 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10231 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10232 array types. The C99 floating-point complex types are also considered
10233 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10234 types, which are GCC extensions and out of the scope of AAPCS64, are
10235 treated as composite types here as well.
10237 Note that MODE itself is not sufficient in determining whether a type
10238 is such a composite type or not. This is because
10239 stor-layout.c:compute_record_mode may have already changed the MODE
10240 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10241 structure with only one field may have its MODE set to the mode of the
10242 field. Also an integer mode whose size matches the size of the
10243 RECORD_TYPE type may be used to substitute the original mode
10244 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10245 solely relied on. */
10247 static bool
10249 machine_mode mode)
10250 {
10263 }
10265 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10266 shall be passed or returned in simd/fp register(s) (providing these
10267 parameter passing registers are available).
10269 Upon successful return, *COUNT returns the number of needed registers,
10270 *BASE_MODE returns the mode of the individual register and when IS_HAF
10271 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10272 floating-point aggregate or a homogeneous short-vector aggregate. */
10274 static bool
10276 const_tree type,
10280 {
10288 {
10291 }
10293 {
10297 }
10299 {
10303 {
10306 }
10307 else
10309 }
10310 else
10315 }
10317 /* Implement TARGET_STRUCT_VALUE_RTX. */
10319 static rtx
10322 {
10324 }
10326 /* Implements target hook vector_mode_supported_p. */
10327 static bool
10329 {
10341 }
10343 /* Return appropriate SIMD container
10344 for MODE within a vector of WIDTH bits. */
10345 static machine_mode
10347 {
10350 {
10353 {
10368 }
10369 else
10371 {
10382 }
10383 }
10385 }
10387 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10388 static machine_mode
10390 {
10392 }
10394 /* Return the bitmask of possible vector sizes for the vectorizer
10395 to iterate over. */
10396 static unsigned int
10398 {
10400 }
10402 /* Implement TARGET_MANGLE_TYPE. */
10406 {
10407 /* The AArch64 ABI documents say that "__va_list" has to be
10408 managled as if it is in the "std" namespace. */
10412 /* Half-precision float. */
10416 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10417 builtin types. */
10421 /* Use the default mangling. */
10423 }
10426 /* Return true if the rtx_insn contains a MEM RTX somewhere
10427 in it. */
10429 static bool
10431 {
10438 }
10440 /* Find the first rtx_insn before insn that will generate an assembly
10441 instruction. */
10445 {
10449 do
10450 {
10452 }
10456 }
10458 static bool
10460 {
10462 /* A number of these may be AArch32 only. */
10467 };
10470 {
10473 }
10476 }
10478 /* Check if there is a register dependency between a load and the insn
10479 for which we hold recog_data. */
10481 static bool
10483 {
10484 rtx load_reg;
10494 {
10500 }
10502 }
10505 /* When working around the Cortex-A53 erratum 835769,
10506 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10507 instruction and has a preceding memory instruction such that a NOP
10508 should be inserted between them. */
10510 bool
10512 {
10515 rtx body;
10528 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10529 Restore recog state to INSN to avoid state corruption. */
10537 /* If the previous insn is a memory op and there is no dependency between
10538 it and the DImode madd, emit a NOP between them. If body is NULL then we
10539 have a complex memory operation, probably a load/store pair.
10540 Be conservative for now and emit a NOP. */
10547 }
10550 /* Implement FINAL_PRESCAN_INSN. */
10552 void
10554 {
10557 }
10560 /* Return the equivalent letter for size. */
10561 static char
10563 {
10565 {
10571 }
10572 }
10574 /* Return true iff x is a uniform vector of floating-point
10575 constants, and the constant can be represented in
10576 quarter-precision form. Note, as aarch64_float_const_representable
10577 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10578 static bool
10580 {
10581 rtx elt;
10585 }
10587 /* Return true for valid and false for invalid. */
10588 bool
10591 {
10592 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10593 matches = 1; \
10594 for (i = 0; i < idx; i += (STRIDE)) \
10595 if (!(TEST)) \
10596 matches = 0; \
10597 if (matches) \
10598 { \
10599 immtype = (CLASS); \
10600 elsize = (ELSIZE); \
10601 eshift = (SHIFT); \
10602 emvn = (NEG); \
10603 break; \
10604 }
10614 {
10620 {
10625 }
10628 }
10630 /* Splat vector constant out into a byte vector. */
10632 {
10633 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10634 it must be laid out in the vector register in reverse order. */
10642 {
10645 }
10647 }
10649 /* Sanity check. */
10652 do
10653 {
10702 }
10709 {
10719 /* Un-invert bytes of recognized vector, if necessary. */
10725 {
10726 /* FIXME: Broken on 32-bit H_W_I hosts. */
10735 }
10736 else
10737 {
10741 /* Construct 'abcdefgh' because the assembler cannot handle
10742 generic constants. */
10747 }
10748 }
10751 #undef CHECK
10752 }
10754 /* Check of immediate shift constants are within range. */
10755 bool
10757 {
10761 else
10763 }
10765 /* Return true if X is a uniform vector where all elements
10766 are either the floating-point constant 0.0 or the
10767 integer constant 0. */
10768 bool
10770 {
10772 }
10775 /* Return the bitmask CONST_INT to select the bits required by a zero extract
10776 operation of width WIDTH at bit position POS. */
10778 rtx
10780 {
10784 unsigned HOST_WIDE_INT mask
10787 }
10789 bool
10791 {
10796 {
10801 }
10804 }
10806 bool
10808 {
10821 }
10823 /* Return a const_int vector of VAL. */
10824 rtx
10826 {
10835 }
10837 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10839 bool
10841 {
10842 machine_mode vmode;
10848 }
10850 /* Construct and return a PARALLEL RTX vector with elements numbering the
10851 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10852 the vector - from the perspective of the architecture. This does not
10853 line up with GCC's perspective on lane numbers, so we end up with
10854 different masks depending on our target endian-ness. The diagram
10855 below may help. We must draw the distinction when building masks
10856 which select one half of the vector. An instruction selecting
10857 architectural low-lanes for a big-endian target, must be described using
10858 a mask selecting GCC high-lanes.
10860 Big-Endian Little-Endian
10862 GCC 0 1 2 3 3 2 1 0
10863 | x | x | x | x | | x | x | x | x |
10864 Architecture 3 2 1 0 3 2 1 0
10866 Low Mask: { 2, 3 } { 0, 1 }
10867 High Mask: { 0, 1 } { 2, 3 }
10868 */
10870 rtx
10872 {
10878 rtx t1;
10883 else
10891 }
10893 /* Check OP for validity as a PARALLEL RTX vector with elements
10894 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10895 from the perspective of the architecture. See the diagram above
10896 aarch64_simd_vect_par_cnst_half for more details. */
10898 bool
10901 {
10914 {
10921 }
10923 }
10925 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10926 HIGH (exclusive). */
10927 void
10929 const_tree exp)
10930 {
10931 HOST_WIDE_INT lane;
10936 {
10939 else
10941 }
10942 }
10944 /* Return TRUE if OP is a valid vector addressing mode. */
10945 bool
10947 {
10950 }
10952 /* Emit a register copy from operand to operand, taking care not to
10953 early-clobber source registers in the process.
10955 COUNT is the number of components into which the copy needs to be
10956 decomposed. */
10957 void
10960 {
10970 else
10974 }
10976 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10977 one of VSTRUCT modes: OI, CI, or XI. */
10978 int
10980 {
10982 }
10984 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
10985 alignment of a vector to 128 bits. */
10986 static HOST_WIDE_INT
10988 {
10991 }
10993 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
10994 static bool
10996 {
11000 /* We guarantee alignment for vectors up to 128-bits. */
11005 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11007 }
11009 /* If VALS is a vector constant that can be loaded into a register
11010 using DUP, generate instructions to do so and return an RTX to
11011 assign to the register. Otherwise return NULL_RTX. */
11012 static rtx
11014 {
11017 rtx x;
11022 /* We can load this constant by using DUP and a constant in a
11023 single ARM register. This will be cheaper than a vector
11024 load. */
11027 }
11030 /* Generate code to load VALS, which is a PARALLEL containing only
11031 constants (for vec_init) or CONST_VECTOR, efficiently into a
11032 register. Returns an RTX to copy into the register, or NULL_RTX
11033 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11034 static rtx
11036 {
11038 rtx const_dup;
11047 {
11048 /* A CONST_VECTOR must contain only CONST_INTs and
11049 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11050 Only store valid constants in a CONST_VECTOR. */
11052 {
11055 n_const++;
11056 }
11059 }
11060 else
11065 /* Load using MOVI/MVNI. */
11068 /* Loaded using DUP. */
11071 /* Load from constant pool. We can not take advantage of single-cycle
11072 LD1 because we need a PC-relative addressing mode. */
11074 else
11075 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11076 We can not construct an initializer. */
11078 }
11080 /* Expand a vector initialisation sequence, such that TARGET is
11081 initialised to contain VALS. */
11083 void
11085 {
11088 /* The number of vector elements. */
11090 /* The number of vector elements which are not constant. */
11093 /* The first element of vals. */
11097 /* Count the number of variable elements to initialise. */
11099 {
11103 else
11107 }
11109 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11110 how best to handle this. */
11112 {
11115 {
11118 }
11119 }
11121 /* Splat a single non-constant element if we can. */
11123 {
11127 }
11129 /* Initialise a vector which is part-variable. We want to first try
11130 to build those lanes which are constant in the most efficient way we
11131 can. */
11133 {
11136 /* Load constant part of vector. We really don't care what goes into the
11137 parts we will overwrite, but we're more likely to be able to load the
11138 constant efficiently if it has fewer, larger, repeating parts
11139 (see aarch64_simd_valid_immediate). */
11141 {
11147 {
11148 /* Look in the copied vector, as more elements are const. */
11151 {
11154 }
11155 }
11157 }
11159 }
11161 /* Insert the variable lanes directly. */
11167 {
11173 }
11174 }
11176 static unsigned HOST_WIDE_INT
11178 {
11179 return
11180 (!SHIFT_COUNT_TRUNCATED
11183 }
11185 /* Select a format to encode pointers in exception handling data. */
11186 int
11188 {
11191 {
11197 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11198 for everything. */
11202 /* No assumptions here. 8-byte relocs required. */
11205 }
11207 }
11209 /* The last .arch and .tune assembly strings that we printed. */
11213 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11214 by the function fndecl. */
11216 void
11218 tree fndecl)
11219 {
11225 else
11236 /* Only update the assembler .arch string if it is distinct from the last
11237 such string we printed. */
11240 {
11243 }
11245 /* Print the cpu name we're tuning for in the comments, might be
11246 useful to readers of the generated asm. Do it only when it changes
11247 from function to function and verbose assembly is requested. */
11252 {
11256 }
11258 /* Don't forget the type directive for ELF. */
11261 }
11263 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11265 static void
11267 {
11284 }
11286 /* Emit load exclusive. */
11288 static void
11291 {
11295 {
11302 }
11305 }
11307 /* Emit store exclusive. */
11309 static void
11312 {
11316 {
11323 }
11326 }
11328 /* Mark the previous jump instruction as unlikely. */
11330 static void
11332 {
11337 }
11339 /* Expand a compare and swap pattern. */
11341 void
11343 {
11348 gen_cas_fn gen;
11350 {
11351 gen_aarch64_compare_and_swapqi,
11352 gen_aarch64_compare_and_swaphi,
11353 gen_aarch64_compare_and_swapsi,
11354 gen_aarch64_compare_and_swapdi
11355 };
11357 {
11358 gen_aarch64_compare_and_swapqi_lse,
11359 gen_aarch64_compare_and_swaphi_lse,
11360 gen_aarch64_compare_and_swapsi_lse,
11361 gen_aarch64_compare_and_swapdi_lse
11362 };
11375 /* Normally the succ memory model must be stronger than fail, but in the
11376 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11377 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11384 {
11387 /* For short modes, we're going to perform the comparison in SImode,
11388 so do the zero-extension now. */
11392 /* Fall through. */
11396 /* Force the value into a register if needed. */
11403 }
11406 {
11413 }
11416 else
11427 }
11429 /* Test whether the target supports using a atomic load-operate instruction.
11430 CODE is the operation and AFTER is TRUE if the data in memory after the
11431 operation should be returned and FALSE if the data before the operation
11432 should be returned. Returns FALSE if the operation isn't supported by the
11433 architecture. */
11435 bool
11437 {
11442 {
11452 }
11453 }
11455 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11456 sequence implementing an atomic operation. */
11458 static void
11460 {
11467 {
11469 }
11470 }
11472 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11473 for the data in memory. EXPECTED is the value expected to be in memory.
11474 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11475 is the memory ordering to use. */
11477 void
11480 rtx model)
11481 {
11483 machine_mode mode;
11488 {
11495 }
11497 /* Move the expected value into the CAS destination register. */
11500 /* Emit the CAS. */
11503 /* Compare the expected value with the value loaded by the CAS, to establish
11504 whether the swap was made. */
11506 }
11508 /* Split a compare and swap pattern. */
11510 void
11512 {
11514 machine_mode mode;
11519 rtx model_rtx;
11533 {
11536 }
11539 /* The initial load can be relaxed for a __sync operation since a final
11540 barrier will be emitted to stop code hoisting. */
11544 else
11556 {
11561 }
11562 else
11563 {
11567 }
11571 /* Emit any final barrier needed for a __sync operation. */
11574 }
11576 /* Emit a BIC instruction. */
11578 static void
11580 {
11585 {
11590 }
11593 }
11595 /* Emit an atomic swap. */
11597 static void
11600 {
11604 {
11611 }
11614 }
11616 /* Operations supported by aarch64_emit_atomic_load_op. */
11618 enum aarch64_atomic_load_op_code
11619 {
11623 AARCH64_LDOP_BIC /* A & ~B */
11624 };
11626 /* Emit an atomic load-operate. */
11628 static void
11632 {
11635 {
11636 gen_aarch64_atomic_loadaddqi,
11637 gen_aarch64_atomic_loadaddhi,
11638 gen_aarch64_atomic_loadaddsi,
11639 gen_aarch64_atomic_loadadddi
11640 };
11642 {
11643 gen_aarch64_atomic_loadeorqi,
11644 gen_aarch64_atomic_loadeorhi,
11645 gen_aarch64_atomic_loadeorsi,
11646 gen_aarch64_atomic_loadeordi
11647 };
11649 {
11650 gen_aarch64_atomic_loadsetqi,
11651 gen_aarch64_atomic_loadsethi,
11652 gen_aarch64_atomic_loadsetsi,
11653 gen_aarch64_atomic_loadsetdi
11654 };
11656 {
11657 gen_aarch64_atomic_loadclrqi,
11658 gen_aarch64_atomic_loadclrhi,
11659 gen_aarch64_atomic_loadclrsi,
11660 gen_aarch64_atomic_loadclrdi
11661 };
11662 aarch64_atomic_load_op_fn gen;
11666 {
11673 }
11676 {
11683 }
11686 }
11688 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11689 location to store the data read from memory. OUT_RESULT is the location to
11690 store the result of the operation. MEM is the memory location to read and
11691 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11692 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11693 be NULL. */
11695 void
11698 {
11702 aarch64_atomic_load_op_code ldop_code;
11703 rtx src;
11704 rtx x;
11712 /* Make sure the value is in a register, putting it into a destination
11713 register if it needs to be manipulated. */
11716 {
11719 }
11720 else
11724 /* Preprocess the data for the operation as necessary. If the operation is
11725 a SET then emit a swap instruction and finish. */
11727 {
11733 /* Negate the value and treat it as a PLUS. */
11734 {
11735 rtx neg_src;
11737 /* Resize the value if necessary. */
11746 }
11747 /* Fall-through. */
11761 {
11762 rtx not_src;
11764 /* Resize the value if necessary. */
11773 }
11778 /* The operation can't be done with atomic instructions. */
11780 }
11784 /* If necessary, calculate the data in memory after the update by redoing the
11785 operation from values in registers. */
11790 {
11794 }
11799 {
11815 }
11820 }
11822 /* Split an atomic operation. */
11824 void
11827 {
11833 rtx x;
11835 /* Split the atomic operation into a sequence. */
11843 else
11847 /* The initial load can be relaxed for a __sync operation since a final
11848 barrier will be emitted to stop code hoisting. */
11852 else
11856 {
11870 {
11873 }
11874 /* Fall through. */
11880 }
11890 /* Emit any final barrier needed for a __sync operation. */
11893 }
11895 static void
11897 {
11898 /* Half-precision float operations. The compiler handles all operations
11899 with NULL libfuncs by converting to SFmode. */
11901 /* Conversions. */
11905 /* Arithmetic. */
11912 /* Comparisons. */
11920 }
11922 /* Target hook for c_mode_for_suffix. */
11923 static machine_mode
11925 {
11930 }
11932 /* We can only represent floating point constants which will fit in
11933 "quarter-precision" values. These values are characterised by
11934 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
11935 by:
11937 (-1)^s * (n/16) * 2^r
11939 Where:
11940 's' is the sign bit.
11941 'n' is an integer in the range 16 <= n <= 31.
11942 'r' is an integer in the range -3 <= r <= 4. */
11944 /* Return true iff X can be represented by a quarter-precision
11945 floating point immediate operand X. Note, we cannot represent 0.0. */
11946 bool
11948 {
11949 /* This represents our current view of how many bits
11950 make up the mantissa. */
11960 /* We don't support HFmode constants yet. */
11966 /* We cannot represent infinities, NaNs or +/-zero. We won't
11967 know if we have +zero until we analyse the mantissa, but we
11968 can reject the other invalid values. */
11973 /* Extract exponent. */
11977 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11978 highest (sign) bit, with a fixed binary point at bit point_pos.
11979 m1 holds the low part of the mantissa, m2 the high part.
11980 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11981 bits for the mantissa, this can fail (low bits will be lost). */
11985 /* If the low part of the mantissa has bits set we cannot represent
11986 the value. */
11989 /* We have rejected the lower HOST_WIDE_INT, so update our
11990 understanding of how many bits lie in the mantissa and
11991 look only at the high HOST_WIDE_INT. */
11995 /* We can only represent values with a mantissa of the form 1.xxxx. */
12000 /* Having filtered unrepresentable values, we may now remove all
12001 but the highest 5 bits. */
12004 /* We cannot represent the value 0.0, so reject it. This is handled
12005 elsewhere. */
12009 /* Then, as bit 4 is always set, we can mask it off, leaving
12010 the mantissa in the range [0, 15]. */
12014 /* GCC internally does not use IEEE754-like encoding (where normalized
12015 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12016 Our mantissa values are shifted 4 places to the left relative to
12017 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12018 by 5 places to correct for GCC's representation. */
12022 }
12026 machine_mode mode,
12028 {
12038 /* This will return true to show const_vector is legal for use as either
12039 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12040 also update INFO to show how the immediate should be generated. */
12049 {
12051 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12052 move immediate path. */
12055 else
12056 {
12065 else
12069 }
12070 }
12083 else
12087 }
12091 machine_mode mode)
12092 {
12093 machine_mode vmode;
12099 }
12101 /* Split operands into moves from op[1] + op[2] into op[0]. */
12103 void
12105 {
12116 {
12117 /* No-op move. Can't split to nothing; emit something. */
12120 }
12122 /* Preserve register attributes for variable tracking. */
12127 /* Special case of reversed high/low parts. */
12130 {
12134 }
12136 {
12137 /* Try to avoid unnecessary moves if part of the result
12138 is in the right place already. */
12143 }
12144 else
12145 {
12150 }
12151 }
12153 /* vec_perm support. */
12155 #define MAX_VECT_LEN 16
12157 struct expand_vec_perm_d
12158 {
12161 machine_mode vmode;
12165 };
12167 /* Generate a variable permutation. */
12169 static void
12171 {
12182 {
12184 {
12185 /* Expand the argument to a V16QI mode by duplicating it. */
12189 }
12190 else
12191 {
12193 }
12194 }
12195 else
12196 {
12197 rtx pair;
12200 {
12204 }
12205 else
12206 {
12210 }
12211 }
12212 }
12214 void
12216 {
12220 rtx mask;
12222 /* The TBL instruction does not use a modulo index, so we must take care
12223 of that ourselves. */
12228 /* For big-endian, we also need to reverse the index within the vector
12229 (but not which vector). */
12231 {
12232 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12237 }
12239 }
12241 /* Recognize patterns suitable for the TRN instructions. */
12242 static bool
12244 {
12253 /* Note that these are little-endian tests.
12254 We correct for big-endian later. */
12259 else
12264 {
12269 }
12271 /* Success! */
12278 {
12281 }
12285 {
12287 {
12302 }
12303 }
12304 else
12305 {
12307 {
12322 }
12323 }
12327 }
12329 /* Recognize patterns suitable for the UZP instructions. */
12330 static bool
12332 {
12341 /* Note that these are little-endian tests.
12342 We correct for big-endian later. */
12347 else
12352 {
12356 }
12358 /* Success! */
12365 {
12368 }
12372 {
12374 {
12389 }
12390 }
12391 else
12392 {
12394 {
12409 }
12410 }
12414 }
12416 /* Recognize patterns suitable for the ZIP instructions. */
12417 static bool
12419 {
12428 /* Note that these are little-endian tests.
12429 We correct for big-endian later. */
12432 /* Do Nothing. */
12433 ;
12436 else
12441 {
12448 }
12450 /* Success! */
12457 {
12460 }
12464 {
12466 {
12481 }
12482 }
12483 else
12484 {
12486 {
12501 }
12502 }
12506 }
12508 /* Recognize patterns for the EXT insn. */
12510 static bool
12512 {
12515 rtx offset;
12519 /* Check if the extracted indices are increasing by one. */
12521 {
12524 {
12525 /* We'll pass the same vector in twice, so allow indices to wrap. */
12527 }
12530 }
12533 {
12548 }
12550 /* Success! */
12554 /* The case where (location == 0) is a no-op for both big- and little-endian,
12555 and is removed by the mid-end at optimization levels -O1 and higher. */
12558 {
12559 /* After setup, we want the high elements of the first vector (stored
12560 at the LSB end of the register), and the low elements of the second
12561 vector (stored at the MSB end of the register). So swap. */
12563 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12565 }
12570 }
12572 /* Recognize patterns for the REV insns. */
12574 static bool
12576 {
12585 {
12588 {
12593 }
12597 {
12604 }
12608 {
12621 }
12625 }
12629 {
12630 /* This is guaranteed to be true as the value of diff
12631 is 7, 3, 1 and we should have enough elements in the
12632 queue to generate this. Getting a vector mask with a
12633 value of diff other than these values implies that
12634 something is wrong by the time we get here. */
12638 }
12640 /* Success! */
12646 }
12648 static bool
12650 {
12653 rtx in0;
12656 rtx lane;
12660 {
12663 }
12665 /* The generic preparation in aarch64_expand_vec_perm_const_1
12666 swaps the operand order and the permute indices if it finds
12667 d->perm[0] to be in the second operand. Thus, we can always
12668 use d->op0 and need not do any extra arithmetic to get the
12669 correct lane number. */
12674 {
12689 }
12693 }
12695 static bool
12697 {
12705 /* Generic code will try constant permutation twice. Once with the
12706 original mode and again with the elements lowered to QImode.
12707 So wait and don't do the selector expansion ourselves. */
12712 {
12715 /* If big-endian and two vectors we end up with a weird mixed-endian
12716 mode on NEON. Reverse the index within each word but not the word
12717 itself. */
12720 }
12726 }
12728 static bool
12730 {
12731 /* The pattern matching functions above are written to look for a small
12732 number to begin the sequence (0, 1, N/2). If we begin with an index
12733 from the second operand, we can swap the operands. */
12735 {
12743 }
12746 {
12760 }
12762 }
12764 /* Expand a vec_perm_const pattern. */
12766 bool
12768 {
12782 {
12787 }
12790 {
12799 /* The elements of PERM do not suggest that only the first operand
12800 is used, but both operands are identical. Allow easier matching
12801 of the permutation by folding the permutation into the single
12802 input vector. */
12803 /* Fall Through. */
12815 }
12818 }
12820 static bool
12823 {
12833 /* Calculate whether all elements are in one vector. */
12835 {
12839 }
12841 /* If all elements are from the second vector, reindex as if from the
12842 first vector. */
12847 /* Check whether the mask can be applied to a single vector. */
12860 }
12862 rtx
12864 {
12865 /* We have to reverse each vector because we dont have
12866 a permuted load that can reverse-load according to ABI rules. */
12867 rtx mask;
12881 }
12883 /* Implement MODES_TIEABLE_P. In principle we should always return true.
12884 However due to issues with register allocation it is preferable to avoid
12885 tieing integer scalar and FP scalar modes. Executing integer operations
12886 in general registers is better than treating them as scalar vector
12887 operations. This reduces latency and avoids redundant int<->FP moves.
12888 So tie modes if they are either the same class, or vector modes with
12889 other vector modes, vector structs or any scalar mode.
12890 */
12892 bool
12894 {
12898 /* We specifically want to allow elements of "structure" modes to
12899 be tieable to the structure. This more general condition allows
12900 other rarer situations too. */
12904 /* Also allow any scalar modes with vectors. */
12910 }
12912 /* Return a new RTX holding the result of moving POINTER forward by
12913 AMOUNT bytes. */
12915 static rtx
12917 {
12922 }
12924 /* Return a new RTX holding the result of moving POINTER forward by the
12925 size of the mode it points to. */
12927 static rtx
12929 {
12933 }
12935 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
12936 MODE bytes. */
12938 static void
12940 machine_mode mode)
12941 {
12944 /* "Cast" the pointers to the correct mode. */
12947 /* Emit the memcpy. */
12950 /* Move the pointers forward. */
12953 }
12955 /* Expand movmem, as if from a __builtin_memcpy. Return true if
12956 we succeed, otherwise return false. */
12958 bool
12960 {
12964 rtx base;
12967 /* When optimizing for size, give a better estimate of the length of a
12968 memcpy call, but use the default otherwise. */
12971 /* We can't do anything smart if the amount to copy is not constant. */
12977 /* Try to keep the number of instructions low. For cases below 16 bytes we
12978 need to make at most two moves. For cases above 16 bytes it will be one
12979 move for each 16 byte chunk, then at most two additional moves. */
12989 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
12990 1-byte chunk. */
12992 {
12994 {
12997 }
13003 }
13005 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13006 4-byte chunk, partially overlapping with the previously copied chunk. */
13008 {
13012 {
13018 }
13020 }
13022 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13023 them, then (if applicable) an 8-byte chunk. */
13025 {
13027 {
13030 }
13031 else
13032 {
13035 }
13036 }
13038 /* Finish the final bytes of the copy. We can always do this in one
13039 instruction. We either copy the exact amount we need, or partially
13040 overlap with the previous chunk we copied and copy 8-bytes. */
13049 else
13050 {
13052 {
13056 }
13057 else
13058 {
13064 }
13065 }
13068 }
13070 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13072 static unsigned HOST_WIDE_INT
13074 {
13076 }
13078 static bool
13083 {
13084 /* STORE_BY_PIECES can be used when copying a constant string, but
13085 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13086 For now we always fail this and let the move_by_pieces code copy
13087 the string from read-only memory. */
13092 }
13094 static rtx
13097 {
13101 insn_code icode;
13112 {
13140 }
13145 {
13148 }
13157 {
13160 }
13166 }
13168 static rtx
13171 {
13175 insn_code icode;
13187 {
13215 }
13220 {
13223 }
13231 {
13236 }
13247 {
13250 }
13256 }
13258 #undef TARGET_GEN_CCMP_FIRST
13259 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13261 #undef TARGET_GEN_CCMP_NEXT
13262 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13264 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13265 instruction fusion of some sort. */
13267 static bool
13269 {
13271 }
13274 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13275 should be kept together during scheduling. */
13277 static bool
13279 {
13280 rtx set_dest;
13283 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13290 {
13291 /* We are trying to match:
13292 prev (mov) == (set (reg r0) (const_int imm16))
13293 curr (movk) == (set (zero_extract (reg r0)
13294 (const_int 16)
13295 (const_int 16))
13296 (const_int imm16_1)) */
13308 {
13310 }
13311 }
13314 {
13316 /* We're trying to match:
13317 prev (adrp) == (set (reg r1)
13318 (high (symbol_ref ("SYM"))))
13319 curr (add) == (set (reg r0)
13320 (lo_sum (reg r1)
13321 (symbol_ref ("SYM"))))
13322 Note that r0 need not necessarily be the same as r1, especially
13323 during pre-regalloc scheduling. */
13327 {
13335 }
13336 }
13339 {
13341 /* We're trying to match:
13342 prev (movk) == (set (zero_extract (reg r0)
13343 (const_int 16)
13344 (const_int 32))
13345 (const_int imm16_1))
13346 curr (movk) == (set (zero_extract (reg r0)
13347 (const_int 16)
13348 (const_int 48))
13349 (const_int imm16_2)) */
13365 }
13367 {
13368 /* We're trying to match:
13369 prev (adrp) == (set (reg r0)
13370 (high (symbol_ref ("SYM"))))
13371 curr (ldr) == (set (reg r1)
13372 (mem (lo_sum (reg r0)
13373 (symbol_ref ("SYM")))))
13374 or
13375 curr (ldr) == (set (reg r1)
13376 (zero_extend (mem
13377 (lo_sum (reg r0)
13378 (symbol_ref ("SYM")))))) */
13381 {
13394 }
13395 }
13403 {
13406 /* FIXME: this misses some which is considered simple arthematic
13407 instructions for ThunderX. Simple shifts are missed here. */
13413 }
13416 }
13418 /* Return true iff the instruction fusion described by OP is enabled. */
13420 bool
13422 {
13424 }
13426 /* If MEM is in the form of [base+offset], extract the two parts
13427 of address and set to BASE and OFFSET, otherwise return false
13428 after clearing BASE and OFFSET. */
13430 bool
13432 {
13433 rtx addr;
13440 {
13444 }
13448 {
13452 }
13458 }
13460 /* Types for scheduling fusion. */
13461 enum sched_fusion_type
13462 {
13464 SCHED_FUSION_LD_SIGN_EXTEND,
13465 SCHED_FUSION_LD_ZERO_EXTEND,
13466 SCHED_FUSION_LD,
13467 SCHED_FUSION_ST,
13468 SCHED_FUSION_NUM
13469 };
13471 /* If INSN is a load or store of address in the form of [base+offset],
13472 extract the two parts and set to BASE and OFFSET. Return scheduling
13473 fusion type this INSN is. */
13475 static enum sched_fusion_type
13477 {
13495 {
13500 }
13502 {
13507 }
13512 {
13515 }
13516 else
13523 }
13525 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13527 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13528 and PRI are only calculated for these instructions. For other instruction,
13529 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13530 type instruction fusion can be added by returning different priorities.
13532 It's important that irrelevant instructions get the largest FUSION_PRI. */
13534 static void
13537 {
13547 {
13551 }
13553 /* Set FUSION_PRI according to fusion type and base register. */
13556 /* Calculate PRI. */
13559 /* INSN with smaller offset goes first. */
13563 else
13568 }
13570 /* Given OPERANDS of consecutive load/store, check if we can merge
13571 them into ldp/stp. LOAD is true if they are load instructions.
13572 MODE is the mode of memory operands. */
13574 bool
13577 {
13583 {
13591 }
13592 else
13593 {
13598 }
13600 /* The mems cannot be volatile. */
13604 /* Check if the addresses are in the form of [base+offset]. */
13612 /* Check if the bases are same. */
13619 /* Check if the offsets are consecutive. */
13623 /* Check if the addresses are clobbered by load. */
13625 {
13629 /* In increasing order, the last load can clobber the address. */
13632 }
13636 else
13641 else
13644 /* Check if the registers are of same class. */
13649 }
13651 /* Given OPERANDS of consecutive load/store, check if we can merge
13652 them into ldp/stp by adjusting the offset. LOAD is true if they
13653 are load instructions. MODE is the mode of memory operands.
13655 Given below consecutive stores:
13657 str w1, [xb, 0x100]
13658 str w1, [xb, 0x104]
13659 str w1, [xb, 0x108]
13660 str w1, [xb, 0x10c]
13662 Though the offsets are out of the range supported by stp, we can
13663 still pair them after adjusting the offset, like:
13665 add scratch, xb, 0x100
13666 stp w1, w1, [scratch]
13667 stp w1, w1, [scratch, 0x8]
13669 The peephole patterns detecting this opportunity should guarantee
13670 the scratch register is avaliable. */
13672 bool
13675 {
13682 {
13695 }
13696 else
13697 {
13706 }
13707 /* Skip if memory operand is by itslef valid for ldp/stp. */
13711 /* The mems cannot be volatile. */
13716 /* Check if the addresses are in the form of [base+offset]. */
13730 /* Check if the bases are same. */
13741 /* Check if the offsets are consecutive. */
13750 /* Check if the addresses are clobbered by load. */
13752 {
13758 /* In increasing order, the last load can clobber the address. */
13761 }
13765 else
13770 else
13775 else
13780 else
13783 /* Check if the registers are of same class. */
13788 }
13790 /* Given OPERANDS of consecutive load/store, this function pairs them
13791 into ldp/stp after adjusting the offset. It depends on the fact
13792 that addresses of load/store instructions are in increasing order.
13793 MODE is the mode of memory operands. CODE is the rtl operator
13794 which should be applied to all memory operands, it's SIGN_EXTEND,
13795 ZERO_EXTEND or UNKNOWN. */
13797 bool
13800 {
13806 {
13811 }
13812 else
13813 {
13819 }
13824 /* Adjust offset thus it can fit in ldp/stp instruction. */
13832 /* Further adjust to make sure all offsets are OK. */
13834 {
13837 }
13839 /* Make sure the adjustment can be done with ADD/SUB instructions. */
13844 {
13847 }
13849 /* Create new memory references. */
13853 /* Check if the adjusted address is OK for ldp/stp. */
13872 {
13877 }
13879 {
13884 }
13887 {
13892 }
13893 else
13894 {
13899 }
13901 /* Emit adjusting instruction. */
13903 /* Emit ldp/stp instructions. */
13911 }
13913 /* Return 1 if pseudo register should be created and used to hold
13914 GOT address for PIC code. */
13916 bool
13918 {
13920 }
13922 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
13924 static int
13926 {
13928 {
13935 }
13938 }
13941 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
13942 return the log2 of that value. Otherwise return -1. */
13944 int
13946 {
13961 }
13963 /* If X is a vector of equal CONST_DOUBLE values and that value is
13964 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
13966 int
13968 {
13984 }
13986 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
13987 static tree
13989 {
13993 }
13995 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
13997 static bool
13999 optimization_type opt_type)
14000 {
14002 {
14008 }
14009 }
14011 #undef TARGET_ADDRESS_COST
14012 #define TARGET_ADDRESS_COST aarch64_address_cost
14014 /* This hook will determines whether unnamed bitfields affect the alignment
14015 of the containing structure. The hook returns true if the structure
14016 should inherit the alignment requirements of an unnamed bitfield's
14017 type. */
14018 #undef TARGET_ALIGN_ANON_BITFIELD
14019 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14021 #undef TARGET_ASM_ALIGNED_DI_OP
14024 #undef TARGET_ASM_ALIGNED_HI_OP
14027 #undef TARGET_ASM_ALIGNED_SI_OP
14030 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14031 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14032 hook_bool_const_tree_hwi_hwi_const_tree_true
14034 #undef TARGET_ASM_FILE_START
14035 #define TARGET_ASM_FILE_START aarch64_start_file
14037 #undef TARGET_ASM_OUTPUT_MI_THUNK
14038 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14040 #undef TARGET_ASM_SELECT_RTX_SECTION
14041 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14043 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14044 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14046 #undef TARGET_BUILD_BUILTIN_VA_LIST
14047 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14049 #undef TARGET_CALLEE_COPIES
14050 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14052 #undef TARGET_CAN_ELIMINATE
14053 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14055 #undef TARGET_CAN_INLINE_P
14056 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14058 #undef TARGET_CANNOT_FORCE_CONST_MEM
14059 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14061 #undef TARGET_CASE_VALUES_THRESHOLD
14062 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14064 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14065 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14067 /* Only the least significant bit is used for initialization guard
14068 variables. */
14069 #undef TARGET_CXX_GUARD_MASK_BIT
14070 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14072 #undef TARGET_C_MODE_FOR_SUFFIX
14073 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14075 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14076 #undef TARGET_DEFAULT_TARGET_FLAGS
14077 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14078 #endif
14080 #undef TARGET_CLASS_MAX_NREGS
14081 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14083 #undef TARGET_BUILTIN_DECL
14084 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14086 #undef TARGET_BUILTIN_RECIPROCAL
14087 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14089 #undef TARGET_EXPAND_BUILTIN
14090 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14092 #undef TARGET_EXPAND_BUILTIN_VA_START
14093 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14095 #undef TARGET_FOLD_BUILTIN
14096 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14098 #undef TARGET_FUNCTION_ARG
14099 #define TARGET_FUNCTION_ARG aarch64_function_arg
14101 #undef TARGET_FUNCTION_ARG_ADVANCE
14102 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14104 #undef TARGET_FUNCTION_ARG_BOUNDARY
14105 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14107 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14108 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14110 #undef TARGET_FUNCTION_VALUE
14111 #define TARGET_FUNCTION_VALUE aarch64_function_value
14113 #undef TARGET_FUNCTION_VALUE_REGNO_P
14114 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14116 #undef TARGET_FRAME_POINTER_REQUIRED
14117 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14119 #undef TARGET_GIMPLE_FOLD_BUILTIN
14120 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14122 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14123 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14125 #undef TARGET_INIT_BUILTINS
14126 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14128 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14129 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14130 aarch64_ira_change_pseudo_allocno_class
14132 #undef TARGET_LEGITIMATE_ADDRESS_P
14133 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14135 #undef TARGET_LEGITIMATE_CONSTANT_P
14136 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14138 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14139 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14141 #undef TARGET_LRA_P
14142 #define TARGET_LRA_P hook_bool_void_true
14144 #undef TARGET_MANGLE_TYPE
14145 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14147 #undef TARGET_MEMORY_MOVE_COST
14148 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14150 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14151 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14153 #undef TARGET_MUST_PASS_IN_STACK
14154 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14156 /* This target hook should return true if accesses to volatile bitfields
14157 should use the narrowest mode possible. It should return false if these
14158 accesses should use the bitfield container type. */
14159 #undef TARGET_NARROW_VOLATILE_BITFIELD
14160 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14162 #undef TARGET_OPTION_OVERRIDE
14163 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14165 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14166 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14167 aarch64_override_options_after_change
14169 #undef TARGET_OPTION_SAVE
14170 #define TARGET_OPTION_SAVE aarch64_option_save
14172 #undef TARGET_OPTION_RESTORE
14173 #define TARGET_OPTION_RESTORE aarch64_option_restore
14175 #undef TARGET_OPTION_PRINT
14176 #define TARGET_OPTION_PRINT aarch64_option_print
14178 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14179 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14181 #undef TARGET_SET_CURRENT_FUNCTION
14182 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14184 #undef TARGET_PASS_BY_REFERENCE
14185 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14187 #undef TARGET_PREFERRED_RELOAD_CLASS
14188 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14190 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14191 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14193 #undef TARGET_PROMOTED_TYPE
14194 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14196 #undef TARGET_SECONDARY_RELOAD
14197 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14199 #undef TARGET_SHIFT_TRUNCATION_MASK
14200 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14202 #undef TARGET_SETUP_INCOMING_VARARGS
14203 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14205 #undef TARGET_STRUCT_VALUE_RTX
14206 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14208 #undef TARGET_REGISTER_MOVE_COST
14209 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14211 #undef TARGET_RETURN_IN_MEMORY
14212 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14214 #undef TARGET_RETURN_IN_MSB
14215 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14217 #undef TARGET_RTX_COSTS
14218 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14220 #undef TARGET_SCHED_ISSUE_RATE
14221 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14223 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14224 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14225 aarch64_sched_first_cycle_multipass_dfa_lookahead
14227 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14228 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14229 aarch64_first_cycle_multipass_dfa_lookahead_guard
14231 #undef TARGET_TRAMPOLINE_INIT
14232 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14234 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14235 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14237 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14238 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14240 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14241 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14243 #undef TARGET_VECTORIZE_ADD_STMT_COST
14244 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14246 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14247 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14248 aarch64_builtin_vectorization_cost
14250 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14251 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14253 #undef TARGET_VECTORIZE_BUILTINS
14254 #define TARGET_VECTORIZE_BUILTINS
14256 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14257 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14258 aarch64_builtin_vectorized_function
14260 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14261 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14262 aarch64_autovectorize_vector_sizes
14264 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14265 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14266 aarch64_atomic_assign_expand_fenv
14268 /* Section anchor support. */
14270 #undef TARGET_MIN_ANCHOR_OFFSET
14271 #define TARGET_MIN_ANCHOR_OFFSET -256
14273 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14274 byte offset; we can do much more for larger data types, but have no way
14275 to determine the size of the access. We assume accesses are aligned. */
14276 #undef TARGET_MAX_ANCHOR_OFFSET
14277 #define TARGET_MAX_ANCHOR_OFFSET 4095
14279 #undef TARGET_VECTOR_ALIGNMENT
14280 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14282 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14283 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14284 aarch64_simd_vector_alignment_reachable
14286 /* vec_perm support. */
14288 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14289 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14290 aarch64_vectorize_vec_perm_const_ok
14292 #undef TARGET_INIT_LIBFUNCS
14293 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14295 #undef TARGET_FIXED_CONDITION_CODE_REGS
14296 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14298 #undef TARGET_FLAGS_REGNUM
14299 #define TARGET_FLAGS_REGNUM CC_REGNUM
14301 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
14302 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
14304 #undef TARGET_ASAN_SHADOW_OFFSET
14305 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
14307 #undef TARGET_LEGITIMIZE_ADDRESS
14308 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
14310 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14311 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14312 aarch64_use_by_pieces_infrastructure_p
14314 #undef TARGET_CAN_USE_DOLOOP_P
14315 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
14317 #undef TARGET_SCHED_MACRO_FUSION_P
14318 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
14320 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
14321 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
14323 #undef TARGET_SCHED_FUSION_PRIORITY
14324 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
14326 #undef TARGET_UNSPEC_MAY_TRAP_P
14327 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
14329 #undef TARGET_USE_PSEUDO_PIC_REG
14330 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
14332 #undef TARGET_PRINT_OPERAND
14333 #define TARGET_PRINT_OPERAND aarch64_print_operand
14335 #undef TARGET_PRINT_OPERAND_ADDRESS
14336 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
14338 #undef TARGET_OPTAB_SUPPORTED_P
14339 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
14341 #undef TARGET_OMIT_STRUCT_RETURN_REG
14342 #define TARGET_OMIT_STRUCT_RETURN_REG true