1 /* Subroutines for insn-output.c for VAX.
2 Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
35 #include "insn-attr.h"
44 #include "target-def.h"
46 static void vax_output_function_prologue (FILE *, HOST_WIDE_INT
);
47 static void vax_file_start (void);
48 static void vax_init_libfuncs (void);
49 static void vax_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
51 static int vax_address_cost_1 (rtx
);
52 static int vax_address_cost (rtx
);
53 static int vax_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
54 static bool vax_rtx_costs (rtx
, int, int, int *);
55 static rtx
vax_struct_value_rtx (tree
, int);
57 /* Initialize the GCC target structure. */
58 #undef TARGET_ASM_ALIGNED_HI_OP
59 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
61 #undef TARGET_ASM_FUNCTION_PROLOGUE
62 #define TARGET_ASM_FUNCTION_PROLOGUE vax_output_function_prologue
64 #undef TARGET_ASM_FILE_START
65 #define TARGET_ASM_FILE_START vax_file_start
66 #undef TARGET_ASM_FILE_START_APP_OFF
67 #define TARGET_ASM_FILE_START_APP_OFF true
69 #undef TARGET_INIT_LIBFUNCS
70 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
72 #undef TARGET_ASM_OUTPUT_MI_THUNK
73 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
74 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
75 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
77 #undef TARGET_RTX_COSTS
78 #define TARGET_RTX_COSTS vax_rtx_costs
79 #undef TARGET_ADDRESS_COST
80 #define TARGET_ADDRESS_COST vax_address_cost
82 #undef TARGET_PROMOTE_PROTOTYPES
83 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
85 #undef TARGET_STRUCT_VALUE_RTX
86 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
88 struct gcc_target targetm
= TARGET_INITIALIZER
;
90 /* Set global variables as needed for the options enabled. */
93 override_options (void)
95 /* We're VAX floating point, not IEEE floating point. */
97 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
100 /* Generate the assembly code for function entry. FILE is a stdio
101 stream to output the code to. SIZE is an int: how many units of
102 temporary storage to allocate.
104 Refer to the array `regs_ever_live' to determine which registers to
105 save; `regs_ever_live[I]' is nonzero if register number I is ever
106 used in the function. This function is responsible for knowing
107 which registers should not be saved even if used. */
110 vax_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
113 register int mask
= 0;
115 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
116 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
119 fprintf (file
, "\t.word 0x%x\n", mask
);
121 if (dwarf2out_do_frame ())
123 const char *label
= dwarf2out_cfi_label ();
126 for (regno
= FIRST_PSEUDO_REGISTER
-1; regno
>= 0; --regno
)
127 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
128 dwarf2out_reg_save (label
, regno
, offset
-= 4);
130 dwarf2out_reg_save (label
, PC_REGNUM
, offset
-= 4);
131 dwarf2out_reg_save (label
, FRAME_POINTER_REGNUM
, offset
-= 4);
132 dwarf2out_reg_save (label
, ARG_POINTER_REGNUM
, offset
-= 4);
133 dwarf2out_def_cfa (label
, FRAME_POINTER_REGNUM
, -(offset
- 4));
136 size
-= STARTING_FRAME_OFFSET
;
138 asm_fprintf (file
, "\tmovab %wd(%Rsp),%Rsp\n", -size
);
140 asm_fprintf (file
, "\tsubl2 $%wd,%Rsp\n", size
);
143 /* When debugging with stabs, we want to output an extra dummy label
144 so that gas can distinguish between D_float and G_float prior to
145 processing the .stabs directive identifying type double. */
147 vax_file_start (void)
149 default_file_start ();
151 if (write_symbols
== DBX_DEBUG
)
152 fprintf (asm_out_file
, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR
);
155 /* We can use the BSD C library routines for the libgcc calls that are
156 still generated, since that's what they boil down to anyways. When
157 ELF, avoid the user's namespace. */
160 vax_init_libfuncs (void)
162 set_optab_libfunc (udiv_optab
, SImode
, TARGET_ELF
? "*__udiv" : "*udiv");
163 set_optab_libfunc (umod_optab
, SImode
, TARGET_ELF
? "*__urem" : "*urem");
166 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
169 split_quadword_operands (rtx
* operands
, rtx
* low
, int n ATTRIBUTE_UNUSED
)
172 /* Split operands. */
174 low
[0] = low
[1] = low
[2] = 0;
175 for (i
= 0; i
< 3; i
++)
178 /* it's already been figured out */;
179 else if (GET_CODE (operands
[i
]) == MEM
180 && (GET_CODE (XEXP (operands
[i
], 0)) == POST_INC
))
182 rtx addr
= XEXP (operands
[i
], 0);
183 operands
[i
] = low
[i
] = gen_rtx_MEM (SImode
, addr
);
184 if (which_alternative
== 0 && i
== 0)
186 addr
= XEXP (operands
[i
], 0);
187 operands
[i
+1] = low
[i
+1] = gen_rtx_MEM (SImode
, addr
);
192 low
[i
] = operand_subword (operands
[i
], 0, 0, DImode
);
193 operands
[i
] = operand_subword (operands
[i
], 1, 0, DImode
);
199 print_operand_address (FILE * file
, register rtx addr
)
201 register rtx reg1
, breg
, ireg
;
205 switch (GET_CODE (addr
))
209 addr
= XEXP (addr
, 0);
213 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
217 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
221 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
225 /* There can be either two or three things added here. One must be a
226 REG. One can be either a REG or a MULT of a REG and an appropriate
227 constant, and the third can only be a constant or a MEM.
229 We get these two or three things and put the constant or MEM in
230 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
231 a register and can't tell yet if it is a base or index register,
234 reg1
= 0; ireg
= 0; breg
= 0; offset
= 0;
236 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
237 || GET_CODE (XEXP (addr
, 0)) == MEM
)
239 offset
= XEXP (addr
, 0);
240 addr
= XEXP (addr
, 1);
242 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
243 || GET_CODE (XEXP (addr
, 1)) == MEM
)
245 offset
= XEXP (addr
, 1);
246 addr
= XEXP (addr
, 0);
248 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
250 ireg
= XEXP (addr
, 1);
251 addr
= XEXP (addr
, 0);
253 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
255 ireg
= XEXP (addr
, 0);
256 addr
= XEXP (addr
, 1);
258 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
260 reg1
= XEXP (addr
, 1);
261 addr
= XEXP (addr
, 0);
263 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
265 reg1
= XEXP (addr
, 0);
266 addr
= XEXP (addr
, 1);
271 if (GET_CODE (addr
) == REG
)
278 else if (GET_CODE (addr
) == MULT
)
280 else if (GET_CODE (addr
) == PLUS
)
282 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
283 || GET_CODE (XEXP (addr
, 0)) == MEM
)
287 if (GET_CODE (offset
) == CONST_INT
)
288 offset
= plus_constant (XEXP (addr
, 0), INTVAL (offset
));
289 else if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
290 offset
= plus_constant (offset
, INTVAL (XEXP (addr
, 0)));
294 offset
= XEXP (addr
, 0);
296 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
299 ireg
= reg1
, breg
= XEXP (addr
, 0), reg1
= 0;
301 reg1
= XEXP (addr
, 0);
303 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
307 ireg
= XEXP (addr
, 0);
312 if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
313 || GET_CODE (XEXP (addr
, 1)) == MEM
)
317 if (GET_CODE (offset
) == CONST_INT
)
318 offset
= plus_constant (XEXP (addr
, 1), INTVAL (offset
));
319 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
320 offset
= plus_constant (offset
, INTVAL (XEXP (addr
, 1)));
324 offset
= XEXP (addr
, 1);
326 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
329 ireg
= reg1
, breg
= XEXP (addr
, 1), reg1
= 0;
331 reg1
= XEXP (addr
, 1);
333 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
337 ireg
= XEXP (addr
, 1);
345 /* If REG1 is nonzero, figure out if it is a base or index register. */
348 if (breg
!= 0 || (offset
&& GET_CODE (offset
) == MEM
))
359 output_address (offset
);
362 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
366 if (GET_CODE (ireg
) == MULT
)
367 ireg
= XEXP (ireg
, 0);
368 if (GET_CODE (ireg
) != REG
)
370 fprintf (file
, "[%s]", reg_names
[REGNO (ireg
)]);
375 output_addr_const (file
, addr
);
380 rev_cond_name (rtx op
)
382 switch (GET_CODE (op
))
411 vax_float_literal(register rtx c
)
413 register enum machine_mode mode
;
414 REAL_VALUE_TYPE r
, s
;
417 if (GET_CODE (c
) != CONST_DOUBLE
)
422 if (c
== const_tiny_rtx
[(int) mode
][0]
423 || c
== const_tiny_rtx
[(int) mode
][1]
424 || c
== const_tiny_rtx
[(int) mode
][2])
427 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
429 for (i
= 0; i
< 7; i
++)
432 REAL_VALUE_FROM_INT (s
, x
, 0, mode
);
434 if (REAL_VALUES_EQUAL (r
, s
))
436 if (!exact_real_inverse (mode
, &s
))
438 if (REAL_VALUES_EQUAL (r
, s
))
445 /* Return the cost in cycles of a memory address, relative to register
448 Each of the following adds the indicated number of cycles:
452 1 - indexing and/or offset(register)
457 vax_address_cost_1 (register rtx addr
)
459 int reg
= 0, indexed
= 0, indir
= 0, offset
= 0, predec
= 0;
460 rtx plus_op0
= 0, plus_op1
= 0;
462 switch (GET_CODE (addr
))
472 indexed
= 1; /* 2 on VAX 2 */
475 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
477 offset
= (unsigned)(INTVAL(addr
)+128) > 256;
481 offset
= 1; /* 2 on VAX 2 */
483 case LABEL_REF
: /* this is probably a byte offset from the pc */
489 plus_op1
= XEXP (addr
, 0);
491 plus_op0
= XEXP (addr
, 0);
492 addr
= XEXP (addr
, 1);
495 indir
= 2; /* 3 on VAX 2 */
496 addr
= XEXP (addr
, 0);
502 /* Up to 3 things can be added in an address. They are stored in
503 plus_op0, plus_op1, and addr. */
517 /* Indexing and register+offset can both be used (except on a VAX 2)
518 without increasing execution time over either one alone. */
519 if (reg
&& indexed
&& offset
)
520 return reg
+ indir
+ offset
+ predec
;
521 return reg
+ indexed
+ indir
+ offset
+ predec
;
525 vax_address_cost (rtx x
)
527 return (1 + (GET_CODE (x
) == REG
? 0 : vax_address_cost_1 (x
)));
530 /* Cost of an expression on a VAX. This version has costs tuned for the
531 CVAX chip (found in the VAX 3 series) with comments for variations on
535 vax_rtx_costs_1 (register rtx x
, enum rtx_code code
, enum rtx_code outer_code
)
537 enum machine_mode mode
= GET_MODE (x
);
539 int i
= 0; /* may be modified in switch */
540 const char *fmt
= GET_RTX_FORMAT (code
); /* may be modified in switch */
544 /* On a VAX, constants from 0..63 are cheap because they can use the
545 1 byte literal constant format. compare to -1 should be made cheap
546 so that decrement-and-branch insns can be formed more easily (if
547 the value -1 is copied to a register some decrement-and-branch
548 patterns will not match). */
552 if (outer_code
== AND
)
553 return ((unsigned HOST_WIDE_INT
) ~INTVAL (x
) <= 077) ? 1 : 2;
554 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) <= 077)
556 if (outer_code
== COMPARE
&& INTVAL (x
) == -1)
558 if (outer_code
== PLUS
&& (unsigned HOST_WIDE_INT
) -INTVAL (x
) <= 077)
568 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
569 return vax_float_literal (x
) ? 5 : 8;
571 return (((CONST_DOUBLE_HIGH (x
) == 0
572 && (unsigned HOST_WIDE_INT
) CONST_DOUBLE_LOW (x
) < 64)
573 || (outer_code
== PLUS
574 && CONST_DOUBLE_HIGH (x
) == -1 \
575 && (unsigned HOST_WIDE_INT
)-CONST_DOUBLE_LOW (x
) < 64))
586 c
= 16; /* 4 on VAX 9000 */
589 c
= 9; /* 4 on VAX 9000, 12 on VAX 2 */
592 c
= 16; /* 6 on VAX 9000, 28 on VAX 2 */
597 c
= 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
600 return MAX_COST
; /* Mode is not supported. */
605 return MAX_COST
; /* Mode is not supported. */
610 c
= 30; /* highly variable */
611 else if (mode
== DFmode
)
612 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
615 c
= 11; /* 25 on VAX 2 */
622 return MAX_COST
; /* Mode is not supported. */
626 c
= 6 + (mode
== DFmode
) + (GET_MODE (XEXP (x
, 0)) != SImode
);
630 c
= 7; /* 17 on VAX 2 */
638 c
= 10; /* 6 on VAX 9000 */
642 c
= 6; /* 5 on VAX 2, 4 on VAX 9000 */
643 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
644 fmt
= "e"; /* all constant rotate counts are short */
647 /* Check for small negative integer operand: subl2 can be used with
648 a short positive constant instead. */
649 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
650 if ((unsigned)(INTVAL (XEXP (x
, 1)) + 63) < 127)
653 c
= (mode
== DFmode
) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
659 /* AND is special because the first operand is complemented. */
661 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
663 if ((unsigned)~INTVAL (XEXP (x
, 0)) > 63)
672 else if (mode
== SFmode
)
674 else if (mode
== DImode
)
683 if (mode
== DImode
|| mode
== DFmode
)
684 c
= 5; /* 7 on VAX 2 */
686 c
= 3; /* 4 on VAX 2 */
688 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == POST_INC
)
690 return c
+ vax_address_cost_1 (x
);
696 /* Now look inside the expression. Operands which are not registers or
697 short constants add to the cost.
699 FMT and I may have been adjusted in the switch above for instructions
700 which require special handling */
702 while (*fmt
++ == 'e')
704 register rtx op
= XEXP (x
, i
++);
705 code
= GET_CODE (op
);
707 /* A NOT is likely to be found as the first operand of an AND
708 (in which case the relevant cost is of the operand inside
709 the not) and not likely to be found anywhere else. */
711 op
= XEXP (op
, 0), code
= GET_CODE (op
);
716 if ((unsigned)INTVAL (op
) > 63 && GET_MODE (x
) != QImode
)
717 c
+= 1; /* 2 on VAX 2 */
722 c
+= 1; /* 2 on VAX 2 */
725 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
727 /* Registers are faster than floating point constants -- even
728 those constants which can be encoded in a single byte. */
729 if (vax_float_literal (op
))
732 c
+= (GET_MODE (x
) == DFmode
) ? 3 : 2;
736 if (CONST_DOUBLE_HIGH (op
) != 0
737 || (unsigned)CONST_DOUBLE_LOW (op
) > 63)
742 c
+= 1; /* 2 on VAX 2 */
743 if (GET_CODE (XEXP (op
, 0)) != REG
)
744 c
+= vax_address_cost_1 (XEXP (op
, 0));
758 vax_rtx_costs (rtx x
, int code
, int outer_code
, int * total
)
760 *total
= vax_rtx_costs_1 (x
, code
, outer_code
);
764 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
765 Used for C++ multiple inheritance.
766 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask
767 addl2 $DELTA, 4(ap) #adjust first argument
768 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask
772 vax_output_mi_thunk (FILE * file
,
773 tree thunk ATTRIBUTE_UNUSED
,
775 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
778 fprintf (file
, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC
, delta
);
779 asm_fprintf (file
, ",4(%Rap)\n");
780 fprintf (file
, "\tjmp ");
781 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
782 fprintf (file
, "+2\n");
786 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
787 int incoming ATTRIBUTE_UNUSED
)
789 return gen_rtx_REG (Pmode
, VAX_STRUCT_VALUE_REGNUM
);
792 /* Worker function for NOTICE_UPDATE_CC. */
795 vax_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
797 if (GET_CODE (exp
) == SET
)
799 if (GET_CODE (SET_SRC (exp
)) == CALL
)
801 else if (GET_CODE (SET_DEST (exp
)) != ZERO_EXTRACT
802 && GET_CODE (SET_DEST (exp
)) != PC
)
805 /* The integer operations below don't set carry or
806 set it in an incompatible way. That's ok though
807 as the Z bit is all we need when doing unsigned
808 comparisons on the result of these insns (since
809 they're always with 0). Set CC_NO_OVERFLOW to
810 generate the correct unsigned branches. */
811 switch (GET_CODE (SET_SRC (exp
)))
814 if (GET_MODE_CLASS (GET_MODE (exp
)) == MODE_FLOAT
)
822 cc_status
.flags
= CC_NO_OVERFLOW
;
827 cc_status
.value1
= SET_DEST (exp
);
828 cc_status
.value2
= SET_SRC (exp
);
831 else if (GET_CODE (exp
) == PARALLEL
832 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
834 if (GET_CODE (SET_SRC (XVECEXP (exp
, 0, 0))) == CALL
)
836 else if (GET_CODE (SET_DEST (XVECEXP (exp
, 0, 0))) != PC
)
839 cc_status
.value1
= SET_DEST (XVECEXP (exp
, 0, 0));
840 cc_status
.value2
= SET_SRC (XVECEXP (exp
, 0, 0));
843 /* PARALLELs whose first element sets the PC are aob,
844 sob insns. They do change the cc's. */
849 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
851 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
852 cc_status
.value2
= 0;
853 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
855 && GET_CODE (cc_status
.value2
) == MEM
)
856 cc_status
.value2
= 0;
857 /* Actual condition, one line up, should be that value2's address
858 depends on value1, but that is too much of a pain. */