1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Return nonzero if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return nonzero if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return nonzero if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return nonzero if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is a Q_REGS class register.
47 (define_predicate "q_regs_operand"
48 (match_operand 0 "register_operand")
50 if (GET_CODE (op) == SUBREG)
52 return ANY_QI_REG_P (op);
55 ;; Return true if op is a NON_Q_REGS class register.
56 (define_predicate "non_q_regs_operand"
57 (match_operand 0 "register_operand")
59 if (GET_CODE (op) == SUBREG)
61 return NON_QI_REG_P (op);
64 ;; Match an SI or HImode register for a zero_extract.
65 (define_special_predicate "ext_register_operand"
66 (match_operand 0 "register_operand")
68 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
69 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
71 if (GET_CODE (op) == SUBREG)
74 /* Be careful to accept only registers having upper parts. */
75 return REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) < 4;
78 ;; Return true if op is the AX register.
79 (define_predicate "ax_reg_operand"
80 (and (match_code "reg")
81 (match_test "REGNO (op) == 0")))
83 ;; Return true if op is the flags register.
84 (define_predicate "flags_reg_operand"
85 (and (match_code "reg")
86 (match_test "REGNO (op) == FLAGS_REG")))
88 ;; Return 1 if VALUE can be stored in a sign extended immediate field.
89 (define_predicate "x86_64_immediate_operand"
90 (match_code "const_int,symbol_ref,label_ref,const")
93 return immediate_operand (op, mode);
95 switch (GET_CODE (op))
98 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
99 to be at least 32 and this all acceptable constants are
100 represented as CONST_INT. */
101 if (HOST_BITS_PER_WIDE_INT == 32)
105 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
106 return trunc_int_for_mode (val, SImode) == val;
111 /* For certain code models, the symbolic references are known to fit.
112 in CM_SMALL_PIC model we know it fits if it is local to the shared
113 library. Don't count TLS SYMBOL_REFs here, since they should fit
114 only if inside of UNSPEC handled below. */
115 /* TLS symbols are not constant. */
116 if (SYMBOL_REF_TLS_MODEL (op))
118 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
119 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
122 /* For certain code models, the code is near as well. */
123 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
124 || ix86_cmodel == CM_KERNEL);
127 /* We also may accept the offsetted memory references in certain
129 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
130 switch (XINT (XEXP (op, 0), 1))
132 case UNSPEC_GOTPCREL:
134 case UNSPEC_GOTNTPOFF:
141 if (GET_CODE (XEXP (op, 0)) == PLUS)
143 rtx op1 = XEXP (XEXP (op, 0), 0);
144 rtx op2 = XEXP (XEXP (op, 0), 1);
145 HOST_WIDE_INT offset;
147 if (ix86_cmodel == CM_LARGE)
149 if (GET_CODE (op2) != CONST_INT)
151 offset = trunc_int_for_mode (INTVAL (op2), DImode);
152 switch (GET_CODE (op1))
155 /* TLS symbols are not constant. */
156 if (SYMBOL_REF_TLS_MODEL (op1))
158 /* For CM_SMALL assume that latest object is 16MB before
159 end of 31bits boundary. We may also accept pretty
160 large negative constants knowing that all objects are
161 in the positive half of address space. */
162 if ((ix86_cmodel == CM_SMALL
163 || (ix86_cmodel == CM_MEDIUM
164 && !SYMBOL_REF_FAR_ADDR_P (op1)))
165 && offset < 16*1024*1024
166 && trunc_int_for_mode (offset, SImode) == offset)
168 /* For CM_KERNEL we know that all object resist in the
169 negative half of 32bits address space. We may not
170 accept negative offsets, since they may be just off
171 and we may accept pretty large positive ones. */
172 if (ix86_cmodel == CM_KERNEL
174 && trunc_int_for_mode (offset, SImode) == offset)
179 /* These conditions are similar to SYMBOL_REF ones, just the
180 constraints for code models differ. */
181 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
182 && offset < 16*1024*1024
183 && trunc_int_for_mode (offset, SImode) == offset)
185 if (ix86_cmodel == CM_KERNEL
187 && trunc_int_for_mode (offset, SImode) == offset)
192 switch (XINT (op1, 1))
197 && trunc_int_for_mode (offset, SImode) == offset)
215 ;; Return 1 if VALUE can be stored in the zero extended immediate field.
216 (define_predicate "x86_64_zext_immediate_operand"
217 (match_code "const_double,const_int,symbol_ref,label_ref,const")
219 switch (GET_CODE (op))
222 if (HOST_BITS_PER_WIDE_INT == 32)
223 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
228 if (HOST_BITS_PER_WIDE_INT == 32)
229 return INTVAL (op) >= 0;
231 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
234 /* For certain code models, the symbolic references are known to fit. */
235 /* TLS symbols are not constant. */
236 if (SYMBOL_REF_TLS_MODEL (op))
238 return (ix86_cmodel == CM_SMALL
239 || (ix86_cmodel == CM_MEDIUM
240 && !SYMBOL_REF_FAR_ADDR_P (op)));
243 /* For certain code models, the code is near as well. */
244 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
247 /* We also may accept the offsetted memory references in certain
249 if (GET_CODE (XEXP (op, 0)) == PLUS)
251 rtx op1 = XEXP (XEXP (op, 0), 0);
252 rtx op2 = XEXP (XEXP (op, 0), 1);
254 if (ix86_cmodel == CM_LARGE)
256 switch (GET_CODE (op1))
259 /* TLS symbols are not constant. */
260 if (SYMBOL_REF_TLS_MODEL (op1))
262 /* For small code model we may accept pretty large positive
263 offsets, since one bit is available for free. Negative
264 offsets are limited by the size of NULL pointer area
265 specified by the ABI. */
266 if ((ix86_cmodel == CM_SMALL
267 || (ix86_cmodel == CM_MEDIUM
268 && !SYMBOL_REF_FAR_ADDR_P (op1)))
269 && GET_CODE (op2) == CONST_INT
270 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
271 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
273 /* ??? For the kernel, we may accept adjustment of
274 -0x10000000, since we know that it will just convert
275 negative address space to positive, but perhaps this
276 is not worthwhile. */
280 /* These conditions are similar to SYMBOL_REF ones, just the
281 constraints for code models differ. */
282 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
283 && GET_CODE (op2) == CONST_INT
284 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
285 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
301 ;; Return nonzero if OP is general operand representable on x86_64.
302 (define_predicate "x86_64_general_operand"
303 (if_then_else (match_test "TARGET_64BIT")
304 (ior (match_operand 0 "nonimmediate_operand")
305 (match_operand 0 "x86_64_immediate_operand"))
306 (match_operand 0 "general_operand")))
308 ;; Return nonzero if OP is general operand representable on x86_64
309 ;; as either sign extended or zero extended constant.
310 (define_predicate "x86_64_szext_general_operand"
311 (if_then_else (match_test "TARGET_64BIT")
312 (ior (match_operand 0 "nonimmediate_operand")
313 (ior (match_operand 0 "x86_64_immediate_operand")
314 (match_operand 0 "x86_64_zext_immediate_operand")))
315 (match_operand 0 "general_operand")))
317 ;; Return nonzero if OP is nonmemory operand representable on x86_64.
318 (define_predicate "x86_64_nonmemory_operand"
319 (if_then_else (match_test "TARGET_64BIT")
320 (ior (match_operand 0 "register_operand")
321 (match_operand 0 "x86_64_immediate_operand"))
322 (match_operand 0 "nonmemory_operand")))
324 ;; Return nonzero if OP is nonmemory operand representable on x86_64.
325 (define_predicate "x86_64_szext_nonmemory_operand"
326 (if_then_else (match_test "TARGET_64BIT")
327 (ior (match_operand 0 "register_operand")
328 (ior (match_operand 0 "x86_64_immediate_operand")
329 (match_operand 0 "x86_64_zext_immediate_operand")))
330 (match_operand 0 "nonmemory_operand")))
332 ;; Return true when operand is PIC expression that can be computed by lea
334 (define_predicate "pic_32bit_operand"
335 (match_code "const,symbol_ref,label_ref")
339 /* Rule out relocations that translate into 64bit constants. */
340 if (TARGET_64BIT && GET_CODE (op) == CONST)
343 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
345 if (GET_CODE (op) == UNSPEC
346 && (XINT (op, 1) == UNSPEC_GOTOFF
347 || XINT (op, 1) == UNSPEC_GOT))
350 return symbolic_operand (op, mode);
354 ;; Return nonzero if OP is nonmemory operand acceptable by movabs patterns.
355 (define_predicate "x86_64_movabs_operand"
356 (if_then_else (match_test "!TARGET_64BIT || !flag_pic")
357 (match_operand 0 "nonmemory_operand")
358 (ior (match_operand 0 "register_operand")
359 (and (match_operand 0 "const_double_operand")
360 (match_test "GET_MODE_SIZE (mode) <= 8")))))
362 ;; Returns nonzero if OP is either a symbol reference or a sum of a symbol
363 ;; reference and a constant.
364 (define_predicate "symbolic_operand"
365 (match_code "symbol_ref,label_ref,const")
367 switch (GET_CODE (op))
375 if (GET_CODE (op) == SYMBOL_REF
376 || GET_CODE (op) == LABEL_REF
377 || (GET_CODE (op) == UNSPEC
378 && (XINT (op, 1) == UNSPEC_GOT
379 || XINT (op, 1) == UNSPEC_GOTOFF
380 || XINT (op, 1) == UNSPEC_GOTPCREL)))
382 if (GET_CODE (op) != PLUS
383 || GET_CODE (XEXP (op, 1)) != CONST_INT)
387 if (GET_CODE (op) == SYMBOL_REF
388 || GET_CODE (op) == LABEL_REF)
390 /* Only @GOTOFF gets offsets. */
391 if (GET_CODE (op) != UNSPEC
392 || XINT (op, 1) != UNSPEC_GOTOFF)
395 op = XVECEXP (op, 0, 0);
396 if (GET_CODE (op) == SYMBOL_REF
397 || GET_CODE (op) == LABEL_REF)
406 ;; Return true if the operand contains a @GOT or @GOTOFF reference.
407 (define_predicate "pic_symbolic_operand"
413 if (GET_CODE (op) == UNSPEC
414 && XINT (op, 1) == UNSPEC_GOTPCREL)
416 if (GET_CODE (op) == PLUS
417 && GET_CODE (XEXP (op, 0)) == UNSPEC
418 && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)
423 if (GET_CODE (op) == UNSPEC)
425 if (GET_CODE (op) != PLUS
426 || GET_CODE (XEXP (op, 1)) != CONST_INT)
429 if (GET_CODE (op) == UNSPEC)
435 ;; Return true if OP is a symbolic operand that resolves locally.
436 (define_predicate "local_symbolic_operand"
437 (match_code "const,label_ref,symbol_ref")
439 if (GET_CODE (op) == CONST
440 && GET_CODE (XEXP (op, 0)) == PLUS
441 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
442 op = XEXP (XEXP (op, 0), 0);
444 if (GET_CODE (op) == LABEL_REF)
447 if (GET_CODE (op) != SYMBOL_REF)
450 if (SYMBOL_REF_LOCAL_P (op))
453 /* There is, however, a not insubstantial body of code in the rest of
454 the compiler that assumes it can just stick the results of
455 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
456 /* ??? This is a hack. Should update the body of the compiler to
457 always create a DECL an invoke targetm.encode_section_info. */
458 if (strncmp (XSTR (op, 0), internal_label_prefix,
459 internal_label_prefix_len) == 0)
465 ;; Test for various thread-local symbols.
466 (define_predicate "tls_symbolic_operand"
467 (and (match_code "symbol_ref")
468 (match_test "SYMBOL_REF_TLS_MODEL (op) != 0")))
470 (define_predicate "tls_modbase_operand"
471 (and (match_code "symbol_ref")
472 (match_test "op == ix86_tls_module_base ()")))
474 (define_predicate "tp_or_register_operand"
475 (ior (match_operand 0 "register_operand")
476 (and (match_code "unspec")
477 (match_test "XINT (op, 1) == UNSPEC_TP"))))
479 ;; Test for a pc-relative call operand
480 (define_predicate "constant_call_address_operand"
481 (ior (match_code "symbol_ref")
482 (match_operand 0 "local_symbolic_operand")))
484 ;; True for any non-virtual or eliminable register. Used in places where
485 ;; instantiation of such a register may cause the pattern to not be recognized.
486 (define_predicate "register_no_elim_operand"
487 (match_operand 0 "register_operand")
489 if (GET_CODE (op) == SUBREG)
490 op = SUBREG_REG (op);
491 return !(op == arg_pointer_rtx
492 || op == frame_pointer_rtx
493 || (REGNO (op) >= FIRST_PSEUDO_REGISTER
494 && REGNO (op) <= LAST_VIRTUAL_REGISTER));
497 ;; Similarly, but include the stack pointer. This is used to prevent esp
498 ;; from being used as an index reg.
499 (define_predicate "index_register_operand"
500 (match_operand 0 "register_operand")
502 if (GET_CODE (op) == SUBREG)
503 op = SUBREG_REG (op);
504 if (reload_in_progress || reload_completed)
505 return REG_OK_FOR_INDEX_STRICT_P (op);
507 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
510 ;; Return false if this is any eliminable register. Otherwise general_operand.
511 (define_predicate "general_no_elim_operand"
512 (if_then_else (match_code "reg,subreg")
513 (match_operand 0 "register_no_elim_operand")
514 (match_operand 0 "general_operand")))
516 ;; Return false if this is any eliminable register. Otherwise
517 ;; register_operand or a constant.
518 (define_predicate "nonmemory_no_elim_operand"
519 (ior (match_operand 0 "register_no_elim_operand")
520 (match_operand 0 "immediate_operand")))
522 ;; Test for a valid operand for a call instruction.
523 (define_predicate "call_insn_operand"
524 (ior (match_operand 0 "constant_call_address_operand")
525 (ior (match_operand 0 "register_no_elim_operand")
526 (match_operand 0 "memory_operand"))))
528 ;; Similarly, but for tail calls, in which we cannot allow memory references.
529 (define_predicate "sibcall_insn_operand"
530 (ior (match_operand 0 "constant_call_address_operand")
531 (match_operand 0 "register_no_elim_operand")))
533 ;; Match exactly zero.
534 (define_predicate "const0_operand"
535 (match_code "const_int,const_double,const_vector")
537 if (mode == VOIDmode)
538 mode = GET_MODE (op);
539 return op == CONST0_RTX (mode);
542 ;; Match exactly one.
543 (define_predicate "const1_operand"
544 (and (match_code "const_int")
545 (match_test "op == const1_rtx")))
547 ;; Match 2, 4, or 8. Used for leal multiplicands.
548 (define_predicate "const248_operand"
549 (match_code "const_int")
551 HOST_WIDE_INT i = INTVAL (op);
552 return i == 2 || i == 4 || i == 8;
556 (define_predicate "const_0_to_1_operand"
557 (and (match_code "const_int")
558 (match_test "op == const0_rtx || op == const1_rtx")))
561 (define_predicate "const_0_to_3_operand"
562 (and (match_code "const_int")
563 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 3")))
566 (define_predicate "const_0_to_7_operand"
567 (and (match_code "const_int")
568 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
571 (define_predicate "const_0_to_15_operand"
572 (and (match_code "const_int")
573 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
576 (define_predicate "const_0_to_63_operand"
577 (and (match_code "const_int")
578 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
581 (define_predicate "const_0_to_255_operand"
582 (and (match_code "const_int")
583 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 255")))
585 ;; Match (0 to 255) * 8
586 (define_predicate "const_0_to_255_mul_8_operand"
587 (match_code "const_int")
589 unsigned HOST_WIDE_INT val = INTVAL (op);
590 return val <= 255*8 && val % 8 == 0;
593 ;; Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
594 ;; for shift & compare patterns, as shifting by 0 does not change flags).
595 (define_predicate "const_1_to_31_operand"
596 (and (match_code "const_int")
597 (match_test "INTVAL (op) >= 1 && INTVAL (op) <= 31")))
600 (define_predicate "const_2_to_3_operand"
601 (and (match_code "const_int")
602 (match_test "INTVAL (op) == 2 || INTVAL (op) == 3")))
605 (define_predicate "const_4_to_7_operand"
606 (and (match_code "const_int")
607 (match_test "INTVAL (op) >= 4 && INTVAL (op) <= 7")))
609 ;; Match exactly one bit in 4-bit mask.
610 (define_predicate "const_pow2_1_to_8_operand"
611 (match_code "const_int")
613 unsigned int log = exact_log2 (INTVAL (op));
617 ;; Match exactly one bit in 8-bit mask.
618 (define_predicate "const_pow2_1_to_128_operand"
619 (match_code "const_int")
621 unsigned int log = exact_log2 (INTVAL (op));
625 ;; True if this is a constant appropriate for an increment or decrement.
626 (define_predicate "incdec_operand"
627 (match_code "const_int")
629 /* On Pentium4, the inc and dec operations causes extra dependency on flag
630 registers, since carry flag is not set. */
631 if (!TARGET_USE_INCDEC && !optimize_size)
633 return op == const1_rtx || op == constm1_rtx;
636 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
637 (define_predicate "reg_or_pm1_operand"
638 (ior (match_operand 0 "register_operand")
639 (and (match_code "const_int")
640 (match_test "op == const1_rtx || op == constm1_rtx"))))
642 ;; True if OP is acceptable as operand of DImode shift expander.
643 (define_predicate "shiftdi_operand"
644 (if_then_else (match_test "TARGET_64BIT")
645 (match_operand 0 "nonimmediate_operand")
646 (match_operand 0 "register_operand")))
648 (define_predicate "ashldi_input_operand"
649 (if_then_else (match_test "TARGET_64BIT")
650 (match_operand 0 "nonimmediate_operand")
651 (match_operand 0 "reg_or_pm1_operand")))
653 ;; Return true if OP is a vector load from the constant pool with just
654 ;; the first element nonzero.
655 (define_predicate "zero_extended_scalar_load_operand"
659 op = maybe_get_pool_constant (op);
662 if (GET_CODE (op) != CONST_VECTOR)
665 (GET_MODE_SIZE (GET_MODE (op)) /
666 GET_MODE_SIZE (GET_MODE_INNER (GET_MODE (op))));
667 for (n_elts--; n_elts > 0; n_elts--)
669 rtx elt = CONST_VECTOR_ELT (op, n_elts);
670 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
676 ;; Return 1 when OP is operand acceptable for standard SSE move.
677 (define_predicate "vector_move_operand"
678 (ior (match_operand 0 "nonimmediate_operand")
679 (match_operand 0 "const0_operand")))
681 ;; Return true if OP is a register or a zero.
682 (define_predicate "reg_or_0_operand"
683 (ior (match_operand 0 "register_operand")
684 (match_operand 0 "const0_operand")))
686 ;; Return true if op if a valid address, and does not contain
687 ;; a segment override.
688 (define_special_predicate "no_seg_address_operand"
689 (match_operand 0 "address_operand")
691 struct ix86_address parts;
694 ok = ix86_decompose_address (op, &parts);
696 return parts.seg == SEG_DEFAULT;
699 ;; Return nonzero if the rtx is known to be at least 32 bits aligned.
700 (define_predicate "aligned_operand"
701 (match_operand 0 "general_operand")
703 struct ix86_address parts;
706 /* Registers and immediate operands are always "aligned". */
707 if (GET_CODE (op) != MEM)
710 /* All patterns using aligned_operand on memory operands ends up
711 in promoting memory operand to 64bit and thus causing memory mismatch. */
712 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_size)
715 /* Don't even try to do any aligned optimizations with volatiles. */
716 if (MEM_VOLATILE_P (op))
719 if (MEM_ALIGN (op) >= 32)
724 /* Pushes and pops are only valid on the stack pointer. */
725 if (GET_CODE (op) == PRE_DEC
726 || GET_CODE (op) == POST_INC)
729 /* Decode the address. */
730 ok = ix86_decompose_address (op, &parts);
733 /* Look for some component that isn't known to be aligned. */
736 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
741 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
746 if (GET_CODE (parts.disp) != CONST_INT
747 || (INTVAL (parts.disp) & 3) != 0)
751 /* Didn't find one -- this must be an aligned address. */
755 ;; Returns 1 if OP is memory operand with a displacement.
756 (define_predicate "memory_displacement_operand"
757 (match_operand 0 "memory_operand")
759 struct ix86_address parts;
762 ok = ix86_decompose_address (XEXP (op, 0), &parts);
764 return parts.disp != NULL_RTX;
767 ;; Returns 1 if OP is memory operand with a displacement only.
768 (define_predicate "memory_displacement_only_operand"
769 (match_operand 0 "memory_operand")
771 struct ix86_address parts;
774 ok = ix86_decompose_address (XEXP (op, 0), &parts);
777 if (parts.base || parts.index)
780 return parts.disp != NULL_RTX;
783 ;; Returns 1 if OP is memory operand that cannot be represented
784 ;; by the modRM array.
785 (define_predicate "long_memory_operand"
786 (and (match_operand 0 "memory_operand")
787 (match_test "memory_address_length (op) != 0")))
789 ;; Return 1 if OP is a comparison operator that can be issued by fcmov.
790 (define_predicate "fcmov_comparison_operator"
791 (match_operand 0 "comparison_operator")
793 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
794 enum rtx_code code = GET_CODE (op);
796 if (inmode == CCFPmode || inmode == CCFPUmode)
798 enum rtx_code second_code, bypass_code;
799 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
800 if (bypass_code != UNKNOWN || second_code != UNKNOWN)
802 code = ix86_fp_compare_code_to_integer (code);
804 /* i387 supports just limited amount of conditional codes. */
807 case LTU: case GTU: case LEU: case GEU:
808 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode)
811 case ORDERED: case UNORDERED:
819 ;; Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS insns.
820 ;; The first set are supported directly; the second set can't be done with
821 ;; full IEEE support, i.e. NaNs.
823 ;; ??? It would seem that we have a lot of uses of this predicate that pass
824 ;; it the wrong mode. We got away with this because the old function didn't
825 ;; check the mode at all. Mirror that for now by calling this a special
828 (define_special_predicate "sse_comparison_operator"
829 (match_code "eq,lt,le,unordered,ne,unge,ungt,ordered"))
831 ;; Return 1 if OP is a valid comparison operator in valid mode.
832 (define_predicate "ix86_comparison_operator"
833 (match_operand 0 "comparison_operator")
835 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
836 enum rtx_code code = GET_CODE (op);
838 if (inmode == CCFPmode || inmode == CCFPUmode)
840 enum rtx_code second_code, bypass_code;
841 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
842 return (bypass_code == UNKNOWN && second_code == UNKNOWN);
849 if (inmode == CCmode || inmode == CCGCmode
850 || inmode == CCGOCmode || inmode == CCNOmode)
853 case LTU: case GTU: case LEU: case ORDERED: case UNORDERED: case GEU:
854 if (inmode == CCmode)
858 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
866 ;; Return 1 if OP is a valid comparison operator testing carry flag to be set.
867 (define_predicate "ix86_carry_flag_operator"
868 (match_code "ltu,lt,unlt,gt,ungt,le,unle,ge,unge,ltgt,uneq")
870 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
871 enum rtx_code code = GET_CODE (op);
873 if (GET_CODE (XEXP (op, 0)) != REG
874 || REGNO (XEXP (op, 0)) != FLAGS_REG
875 || XEXP (op, 1) != const0_rtx)
878 if (inmode == CCFPmode || inmode == CCFPUmode)
880 enum rtx_code second_code, bypass_code;
881 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
882 if (bypass_code != UNKNOWN || second_code != UNKNOWN)
884 code = ix86_fp_compare_code_to_integer (code);
886 else if (inmode != CCmode)
892 ;; Nearly general operand, but accept any const_double, since we wish
893 ;; to be able to drop them into memory rather than have them get pulled
895 (define_predicate "cmp_fp_expander_operand"
896 (ior (match_code "const_double")
897 (match_operand 0 "general_operand")))
899 ;; Return true if this is a valid binary floating-point operation.
900 (define_predicate "binary_fp_operator"
901 (match_code "plus,minus,mult,div"))
903 ;; Return true if this is a multiply operation.
904 (define_predicate "mult_operator"
907 ;; Return true if this is a division operation.
908 (define_predicate "div_operator"
911 ;; Return true if this is a float extend operation.
912 (define_predicate "float_operator"
913 (match_code "float"))
915 ;; Return true for ARITHMETIC_P.
916 (define_predicate "arith_or_logical_operator"
917 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
918 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
920 ;; Return 1 if OP is a binary operator that can be promoted to wider mode.
921 ;; Modern CPUs have same latency for HImode and SImode multiply,
922 ;; but 386 and 486 do HImode multiply faster. */
923 (define_predicate "promotable_binary_operator"
924 (ior (match_code "plus,and,ior,xor,ashift")
925 (and (match_code "mult")
926 (match_test "ix86_tune > PROCESSOR_I486"))))
928 ;; To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
929 ;; re-recognize the operand to avoid a copy_to_mode_reg that will fail.
931 ;; ??? It seems likely that this will only work because cmpsi is an
932 ;; expander, and no actual insns use this.
934 (define_predicate "cmpsi_operand"
935 (ior (match_operand 0 "nonimmediate_operand")
936 (and (match_code "and")
937 (match_code "zero_extract" "0")
938 (match_code "const_int" "1")
939 (match_code "const_int" "01")
940 (match_code "const_int" "02")
941 (match_test "INTVAL (XEXP (XEXP (op, 0), 1)) == 8")
942 (match_test "INTVAL (XEXP (XEXP (op, 0), 2)) == 8")
945 (define_predicate "compare_operator"
946 (match_code "compare"))
948 (define_predicate "absneg_operator"
949 (match_code "abs,neg"))